opcodes/mep-desc.h

   1 /* CPU data header for mep.
   2
   3 THIS FILE IS MACHINE GENERATED WITH CGEN.
   4
   5 Copyright 1996-2007 Free Software Foundation, Inc.
   6
   7 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
   8
   9    This file is free software; you can redistribute it and/or modify
  10    it under the terms of the GNU General Public License as published by
  11    the Free Software Foundation; either version 3, or (at your option)
  12    any later version.
  13
  14    It is distributed in the hope that it will be useful, but WITHOUT
  15    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  16    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  17    License for more details.
  18
  19    You should have received a copy of the GNU General Public License along
  20    with this program; if not, write to the Free Software Foundation, Inc.,
  21    51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
  22
  23 */
  24
  25 #ifndef MEP_CPU_H
  26 #define MEP_CPU_H
  27
  28 #include "opcode/cgen-bitset.h"
  29
  30 #define CGEN_ARCH mep
  31
  32 /* Given symbol S, return mep_cgen_<S>.  */
  33 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
  34 #define CGEN_SYM(s) mep##_cgen_##s
  35 #else
  36 #define CGEN_SYM(s) mep/**/_cgen_/**/s
  37 #endif
  38
  39
  40 /* Selected cpu families.  */
  41 #define HAVE_CPU_MEPF
  42
  43 #define CGEN_INSN_LSB0_P 0
  44
  45 /* Minimum size of any insn (in bytes).  */
  46 #define CGEN_MIN_INSN_SIZE 2
  47
  48 /* Maximum size of any insn (in bytes).  */
  49 #define CGEN_MAX_INSN_SIZE 4
  50
  51 #define CGEN_INT_INSN_P 1
  52
  53 /* Maximum number of syntax elements in an instruction.  */
  54 #define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 17
  55
  56 /* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
  57    e.g. In "b,a foo" the ",a" is an operand.  If mnemonics have operands
  58    we can't hash on everything up to the space.  */
  59 #define CGEN_MNEMONIC_OPERANDS
  60
  61 /* Maximum number of fields in an instruction.  */
  62 #define CGEN_ACTUAL_MAX_IFMT_OPERANDS 9
  63
  64 /* Enums.  */
  65
  66 /* Enum declaration for major opcodes.  */
  67 typedef enum major {
  68   MAJ_0, MAJ_1, MAJ_2, MAJ_3
  69  , MAJ_4, MAJ_5, MAJ_6, MAJ_7
  70  , MAJ_8, MAJ_9, MAJ_10, MAJ_11
  71  , MAJ_12, MAJ_13, MAJ_14, MAJ_15
  72 } MAJOR;
  73
  74 /* Attributes.  */
  75
  76 /* Enum declaration for machine type selection.  */
  77 typedef enum mach_attr {
  78   MACH_BASE, MACH_MEP, MACH_H1, MACH_MAX
  79 } MACH_ATTR;
  80
  81 /* Enum declaration for instruction set selection.  */
  82 typedef enum isa_attr {
  83   ISA_MEP, ISA_EXT_CORE1, ISA_MAX
  84 } ISA_ATTR;
  85
  86 /* Enum declaration for datatype to use for C intrinsics mapping.  */
  87 typedef enum cdata_attr {
  88   CDATA_LABEL, CDATA_REGNUM, CDATA_FMAX_FLOAT, CDATA_FMAX_INT
  89  , CDATA_POINTER, CDATA_LONG, CDATA_ULONG, CDATA_SHORT
  90  , CDATA_USHORT, CDATA_CHAR, CDATA_UCHAR, CDATA_CP_DATA_BUS_INT
  91 } CDATA_ATTR;
  92
  93 /* Enum declaration for .  */
  94 typedef enum config_attr {
  95   CONFIG_NONE, CONFIG_DEFAULT
  96 } CONFIG_ATTR;
  97
  98 /* Number of architecture variants.  */
  99 #define MAX_ISAS  ((int) ISA_MAX)
 100 #define MAX_MACHS ((int) MACH_MAX)
 101
 102 /* Ifield support.  */
 103
 104 /* Ifield attribute indices.  */
 105
 106 /* Enum declaration for cgen_ifld attrs.  */
 107 typedef enum cgen_ifld_attr {
 108   CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED
 109  , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31
 110  , CGEN_IFLD_MACH, CGEN_IFLD_ISA, CGEN_IFLD_END_NBOOLS
 111 } CGEN_IFLD_ATTR;
 112
 113 /* Number of non-boolean elements in cgen_ifld_attr.  */
 114 #define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1)
 115
 116 /* cgen_ifld attribute accessor macros.  */
 117 #define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset)
 118 #define CGEN_ATTR_CGEN_IFLD_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_ISA-CGEN_IFLD_START_NBOOLS-1].bitset)
 119 #define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_VIRTUAL)) != 0)
 120 #define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_PCREL_ADDR)) != 0)
 121 #define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_ABS_ADDR)) != 0)
 122 #define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_RESERVED)) != 0)
 123 #define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGN_OPT)) != 0)
 124 #define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGNED)) != 0)
 125
 126 /* Enum declaration for mep ifield types.  */
 127 typedef enum ifield_type {
 128   MEP_F_NIL, MEP_F_ANYOF, MEP_F_MAJOR, MEP_F_RN
 129  , MEP_F_RN3, MEP_F_RM, MEP_F_RL, MEP_F_SUB2
 130  , MEP_F_SUB3, MEP_F_SUB4, MEP_F_EXT, MEP_F_CRN
 131  , MEP_F_CSRN_HI, MEP_F_CSRN_LO, MEP_F_CSRN, MEP_F_CRNX_HI
 132  , MEP_F_CRNX_LO, MEP_F_CRNX, MEP_F_0, MEP_F_1
 133  , MEP_F_2, MEP_F_3, MEP_F_4, MEP_F_5
 134  , MEP_F_6, MEP_F_7, MEP_F_8, MEP_F_9
 135  , MEP_F_10, MEP_F_11, MEP_F_12, MEP_F_13
 136  , MEP_F_14, MEP_F_15, MEP_F_16, MEP_F_17
 137  , MEP_F_18, MEP_F_19, MEP_F_20, MEP_F_21
 138  , MEP_F_22, MEP_F_23, MEP_F_24, MEP_F_25
 139  , MEP_F_26, MEP_F_27, MEP_F_28, MEP_F_29
 140  , MEP_F_30, MEP_F_31, MEP_F_8S8A2, MEP_F_12S4A2
 141  , MEP_F_17S16A2, MEP_F_24S5A2N_HI, MEP_F_24S5A2N_LO, MEP_F_24S5A2N
 142  , MEP_F_24U5A2N_HI, MEP_F_24U5A2N_LO, MEP_F_24U5A2N, MEP_F_2U6
 143  , MEP_F_7U9, MEP_F_7U9A2, MEP_F_7U9A4, MEP_F_16S16
 144  , MEP_F_2U10, MEP_F_3U5, MEP_F_4U8, MEP_F_5U8
 145  , MEP_F_5U24, MEP_F_6S8, MEP_F_8S8, MEP_F_16U16
 146  , MEP_F_12U16, MEP_F_3U29, MEP_F_8S24, MEP_F_8S24A2
 147  , MEP_F_8S24A4, MEP_F_8S24A8, MEP_F_24U8A4N_HI, MEP_F_24U8A4N_LO
 148  , MEP_F_24U8A4N, MEP_F_24U8N_HI, MEP_F_24U8N_LO, MEP_F_24U8N
 149  , MEP_F_24U4N_HI, MEP_F_24U4N_LO, MEP_F_24U4N, MEP_F_CALLNUM
 150  , MEP_F_CCRN_HI, MEP_F_CCRN_LO, MEP_F_CCRN, MEP_F_MAX
 151 } IFIELD_TYPE;
 152
 153 #define MAX_IFLD ((int) MEP_F_MAX)
 154
 155 /* Hardware attribute indices.  */
 156
 157 /* Enum declaration for cgen_hw attrs.  */
 158 typedef enum cgen_hw_attr {
 159   CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE
 160  , CGEN_HW_IS_FLOAT, CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH
 161  , CGEN_HW_ISA, CGEN_HW_END_NBOOLS
 162 } CGEN_HW_ATTR;
 163
 164 /* Number of non-boolean elements in cgen_hw_attr.  */
 165 #define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1)
 166
 167 /* cgen_hw attribute accessor macros.  */
 168 #define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset)
 169 #define CGEN_ATTR_CGEN_HW_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_ISA-CGEN_HW_START_NBOOLS-1].bitset)
 170 #define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_VIRTUAL)) != 0)
 171 #define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_CACHE_ADDR)) != 0)
 172 #define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PC)) != 0)
 173 #define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PROFILE)) != 0)
 174 #define CGEN_ATTR_CGEN_HW_IS_FLOAT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_IS_FLOAT)) != 0)
 175
 176 /* Enum declaration for mep hardware types.  */
 177 typedef enum cgen_hw_type {
 178   HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR
 179  , HW_H_IADDR, HW_H_PC, HW_H_GPR, HW_H_CSR
 180  , HW_H_CR64, HW_H_CR, HW_H_CCR, HW_MAX
 181 } CGEN_HW_TYPE;
 182
 183 #define MAX_HW ((int) HW_MAX)
 184
 185 /* Operand attribute indices.  */
 186
 187 /* Enum declaration for cgen_operand attrs.  */
 188 typedef enum cgen_operand_attr {
 189   CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT
 190  , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY
 191  , CGEN_OPERAND_RELOC_IMPLIES_OVERFLOW, CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH
 192  , CGEN_OPERAND_ISA, CGEN_OPERAND_CDATA, CGEN_OPERAND_ALIGN, CGEN_OPERAND_END_NBOOLS
 193 } CGEN_OPERAND_ATTR;
 194
 195 /* Number of non-boolean elements in cgen_operand_attr.  */
 196 #define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1)
 197
 198 /* cgen_operand attribute accessor macros.  */
 199 #define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset)
 200 #define CGEN_ATTR_CGEN_OPERAND_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_ISA-CGEN_OPERAND_START_NBOOLS-1].bitset)
 201 #define CGEN_ATTR_CGEN_OPERAND_CDATA_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_CDATA-CGEN_OPERAND_START_NBOOLS-1].nonbitset)
 202 #define CGEN_ATTR_CGEN_OPERAND_ALIGN_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_ALIGN-CGEN_OPERAND_START_NBOOLS-1].nonbitset)
 203 #define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_VIRTUAL)) != 0)
 204 #define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0)
 205 #define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_ABS_ADDR)) != 0)
 206 #define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGN_OPT)) != 0)
 207 #define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGNED)) != 0)
 208 #define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_NEGATIVE)) != 0)
 209 #define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_RELAX)) != 0)
 210 #define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SEM_ONLY)) != 0)
 211 #define CGEN_ATTR_CGEN_OPERAND_RELOC_IMPLIES_OVERFLOW_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_RELOC_IMPLIES_OVERFLOW)) != 0)
 212
 213 /* Enum declaration for mep operand types.  */
 214 typedef enum cgen_operand_type {
 215   MEP_OPERAND_PC, MEP_OPERAND_R0, MEP_OPERAND_RN, MEP_OPERAND_RM
 216  , MEP_OPERAND_RL, MEP_OPERAND_RN3, MEP_OPERAND_RMA, MEP_OPERAND_RNC
 217  , MEP_OPERAND_RNUC, MEP_OPERAND_RNS, MEP_OPERAND_RNUS, MEP_OPERAND_RNL
 218  , MEP_OPERAND_RNUL, MEP_OPERAND_RN3C, MEP_OPERAND_RN3UC, MEP_OPERAND_RN3S
 219  , MEP_OPERAND_RN3US, MEP_OPERAND_RN3L, MEP_OPERAND_RN3UL, MEP_OPERAND_LP
 220  , MEP_OPERAND_SAR, MEP_OPERAND_HI, MEP_OPERAND_LO, MEP_OPERAND_MB0
 221  , MEP_OPERAND_ME0, MEP_OPERAND_MB1, MEP_OPERAND_ME1, MEP_OPERAND_PSW
 222  , MEP_OPERAND_EPC, MEP_OPERAND_EXC, MEP_OPERAND_NPC, MEP_OPERAND_DBG
 223  , MEP_OPERAND_DEPC, MEP_OPERAND_OPT, MEP_OPERAND_R1, MEP_OPERAND_TP
 224  , MEP_OPERAND_SP, MEP_OPERAND_TPR, MEP_OPERAND_SPR, MEP_OPERAND_CSRN
 225  , MEP_OPERAND_CSRN_IDX, MEP_OPERAND_CRN64, MEP_OPERAND_CRN, MEP_OPERAND_CRNX64
 226  , MEP_OPERAND_CRNX, MEP_OPERAND_CCRN, MEP_OPERAND_CCCC, MEP_OPERAND_PCREL8A2
 227  , MEP_OPERAND_PCREL12A2, MEP_OPERAND_PCREL17A2, MEP_OPERAND_PCREL24A2, MEP_OPERAND_PCABS24A2
 228  , MEP_OPERAND_SDISP16, MEP_OPERAND_SIMM16, MEP_OPERAND_UIMM16, MEP_OPERAND_CODE16
 229  , MEP_OPERAND_UDISP2, MEP_OPERAND_UIMM2, MEP_OPERAND_SIMM6, MEP_OPERAND_SIMM8
 230  , MEP_OPERAND_ADDR24A4, MEP_OPERAND_CODE24, MEP_OPERAND_CALLNUM, MEP_OPERAND_UIMM3
 231  , MEP_OPERAND_UIMM4, MEP_OPERAND_UIMM5, MEP_OPERAND_UDISP7, MEP_OPERAND_UDISP7A2
 232  , MEP_OPERAND_UDISP7A4, MEP_OPERAND_UIMM7A4, MEP_OPERAND_UIMM24, MEP_OPERAND_CIMM4
 233  , MEP_OPERAND_CIMM5, MEP_OPERAND_CDISP8, MEP_OPERAND_CDISP8A2, MEP_OPERAND_CDISP8A4
 234  , MEP_OPERAND_CDISP8A8, MEP_OPERAND_ZERO, MEP_OPERAND_CP_FLAG, MEP_OPERAND_MAX
 235 } CGEN_OPERAND_TYPE;
 236
 237 /* Number of operands types.  */
 238 #define MAX_OPERANDS 79
 239
 240 /* Maximum number of operands referenced by any insn.  */
 241 #define MAX_OPERAND_INSTANCES 8
 242
 243 /* Insn attribute indices.  */
 244
 245 /* Enum declaration for cgen_insn attrs.  */
 246 typedef enum cgen_insn_attr {
 247   CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
 248  , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED
 249  , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_OPTIONAL_BIT_INSN, CGEN_INSN_OPTIONAL_MUL_INSN
 250  , CGEN_INSN_OPTIONAL_DIV_INSN, CGEN_INSN_OPTIONAL_DEBUG_INSN, CGEN_INSN_OPTIONAL_LDZ_INSN, CGEN_INSN_OPTIONAL_ABS_INSN
 251  , CGEN_INSN_OPTIONAL_AVE_INSN, CGEN_INSN_OPTIONAL_MINMAX_INSN, CGEN_INSN_OPTIONAL_CLIP_INSN, CGEN_INSN_OPTIONAL_SAT_INSN
 252  , CGEN_INSN_OPTIONAL_UCI_INSN, CGEN_INSN_OPTIONAL_DSP_INSN, CGEN_INSN_OPTIONAL_CP_INSN, CGEN_INSN_OPTIONAL_CP64_INSN
 253  , CGEN_INSN_OPTIONAL_VLIW64, CGEN_INSN_MAY_TRAP, CGEN_INSN_VLIW_ALONE, CGEN_INSN_VLIW_NO_CORE_NOP
 254  , CGEN_INSN_VLIW_NO_COP_NOP, CGEN_INSN_VLIW64_NO_MATCHING_NOP, CGEN_INSN_VLIW32_NO_MATCHING_NOP, CGEN_INSN_VOLATILE
 255  , CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_ISA
 256  , CGEN_INSN_LATENCY, CGEN_INSN_CONFIG, CGEN_INSN_END_NBOOLS
 257 } CGEN_INSN_ATTR;
 258
 259 /* Number of non-boolean elements in cgen_insn_attr.  */
 260 #define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1)
 261
 262 /* cgen_insn attribute accessor macros.  */
 263 #define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset)
 264 #define CGEN_ATTR_CGEN_INSN_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_ISA-CGEN_INSN_START_NBOOLS-1].bitset)
 265 #define CGEN_ATTR_CGEN_INSN_LATENCY_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_LATENCY-CGEN_INSN_START_NBOOLS-1].nonbitset)
 266 #define CGEN_ATTR_CGEN_INSN_CONFIG_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_CONFIG-CGEN_INSN_START_NBOOLS-1].nonbitset)
 267 #define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_ALIAS)) != 0)
 268 #define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VIRTUAL)) != 0)
 269 #define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_UNCOND_CTI)) != 0)
 270 #define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_COND_CTI)) != 0)
 271 #define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_SKIP_CTI)) != 0)
 272 #define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_DELAY_SLOT)) != 0)
 273 #define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXABLE)) != 0)
 274 #define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXED)) != 0)
 275 #define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_NO_DIS)) != 0)
 276 #define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_PBB)) != 0)
 277 #define CGEN_ATTR_CGEN_INSN_OPTIONAL_BIT_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_BIT_INSN)) != 0)
 278 #define CGEN_ATTR_CGEN_INSN_OPTIONAL_MUL_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_MUL_INSN)) != 0)
 279 #define CGEN_ATTR_CGEN_INSN_OPTIONAL_DIV_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_DIV_INSN)) != 0)
 280 #define CGEN_ATTR_CGEN_INSN_OPTIONAL_DEBUG_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_DEBUG_INSN)) != 0)
 281 #define CGEN_ATTR_CGEN_INSN_OPTIONAL_LDZ_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_LDZ_INSN)) != 0)
 282 #define CGEN_ATTR_CGEN_INSN_OPTIONAL_ABS_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_ABS_INSN)) != 0)
 283 #define CGEN_ATTR_CGEN_INSN_OPTIONAL_AVE_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_AVE_INSN)) != 0)
 284 #define CGEN_ATTR_CGEN_INSN_OPTIONAL_MINMAX_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_MINMAX_INSN)) != 0)
 285 #define CGEN_ATTR_CGEN_INSN_OPTIONAL_CLIP_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_CLIP_INSN)) != 0)
 286 #define CGEN_ATTR_CGEN_INSN_OPTIONAL_SAT_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_SAT_INSN)) != 0)
 287 #define CGEN_ATTR_CGEN_INSN_OPTIONAL_UCI_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_UCI_INSN)) != 0)
 288 #define CGEN_ATTR_CGEN_INSN_OPTIONAL_DSP_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_DSP_INSN)) != 0)
 289 #define CGEN_ATTR_CGEN_INSN_OPTIONAL_CP_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_CP_INSN)) != 0)
 290 #define CGEN_ATTR_CGEN_INSN_OPTIONAL_CP64_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_CP64_INSN)) != 0)
 291 #define CGEN_ATTR_CGEN_INSN_OPTIONAL_VLIW64_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_VLIW64)) != 0)
 292 #define CGEN_ATTR_CGEN_INSN_MAY_TRAP_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_MAY_TRAP)) != 0)
 293 #define CGEN_ATTR_CGEN_INSN_VLIW_ALONE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VLIW_ALONE)) != 0)
 294 #define CGEN_ATTR_CGEN_INSN_VLIW_NO_CORE_NOP_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VLIW_NO_CORE_NOP)) != 0)
 295 #define CGEN_ATTR_CGEN_INSN_VLIW_NO_COP_NOP_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VLIW_NO_COP_NOP)) != 0)
 296 #define CGEN_ATTR_CGEN_INSN_VLIW64_NO_MATCHING_NOP_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VLIW64_NO_MATCHING_NOP)) != 0)
 297 #define CGEN_ATTR_CGEN_INSN_VLIW32_NO_MATCHING_NOP_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VLIW32_NO_MATCHING_NOP)) != 0)
 298 #define CGEN_ATTR_CGEN_INSN_VOLATILE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VOLATILE)) != 0)
 299
 300 /* cgen.h uses things we just defined.  */
 301 #include "opcode/cgen.h"
 302
 303 extern const struct cgen_ifld mep_cgen_ifld_table[];
 304
 305 /* Attributes.  */
 306 extern const CGEN_ATTR_TABLE mep_cgen_hardware_attr_table[];
 307 extern const CGEN_ATTR_TABLE mep_cgen_ifield_attr_table[];
 308 extern const CGEN_ATTR_TABLE mep_cgen_operand_attr_table[];
 309 extern const CGEN_ATTR_TABLE mep_cgen_insn_attr_table[];
 310
 311 /* Hardware decls.  */
 312
 313 extern CGEN_KEYWORD mep_cgen_opval_h_gpr;
 314 extern CGEN_KEYWORD mep_cgen_opval_h_csr;
 315 extern CGEN_KEYWORD mep_cgen_opval_h_cr64;
 316 extern CGEN_KEYWORD mep_cgen_opval_h_cr;
 317 extern CGEN_KEYWORD mep_cgen_opval_h_ccr;
 318
 319 extern const CGEN_HW_ENTRY mep_cgen_hw_table[];
 320
 321
 322
 323 #endif /* MEP_CPU_H */