opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
   3    2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
   4    Free Software Foundation, Inc.
   5
   6    This file is part of the GNU opcodes library.
   7
   8    This library is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3, or (at your option)
  11    any later version.
  12
  13    It is distributed in the hope that it will be useful, but WITHOUT
  14    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  16    License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; if not, write to the Free Software
  20    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  21    MA 02110-1301, USA.  */
  22
  23
  24 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  25    July 1988
  26     modified by John Hassey (hassey@dg-rtp.dg.com)
  27     x86-64 support added by Jan Hubicka (jh@suse.cz)
  28     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  29
  30 /* The main tables describing the instructions is essentially a copy
  31    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  32    Programmers Manual.  Usually, there is a capital letter, followed
  33    by a small letter.  The capital letter tell the addressing mode,
  34    and the small letter tells about the operand size.  Refer to
  35    the Intel manual for details.  */
  36
  37 #include "sysdep.h"
  38 #include "dis-asm.h"
  39 #include "opintl.h"
  40 #include "opcode/i386.h"
  41 #include "libiberty.h"
  42
  43 #include <setjmp.h>
  44
  45 static int print_insn (bfd_vma, disassemble_info *);
  46 static void dofloat (int);
  47 static void OP_ST (int, int);
  48 static void OP_STi (int, int);
  49 static int putop (const char *, int);
  50 static void oappend (const char *);
  51 static void append_seg (void);
  52 static void OP_indirE (int, int);
  53 static void print_operand_value (char *, int, bfd_vma);
  54 static void OP_E_register (int, int);
  55 static void OP_E_memory (int, int);
  56 static void print_displacement (char *, bfd_vma);
  57 static void OP_E (int, int);
  58 static void OP_G (int, int);
  59 static bfd_vma get64 (void);
  60 static bfd_signed_vma get32 (void);
  61 static bfd_signed_vma get32s (void);
  62 static int get16 (void);
  63 static void set_op (bfd_vma, int);
  64 static void OP_Skip_MODRM (int, int);
  65 static void OP_REG (int, int);
  66 static void OP_IMREG (int, int);
  67 static void OP_I (int, int);
  68 static void OP_I64 (int, int);
  69 static void OP_sI (int, int);
  70 static void OP_J (int, int);
  71 static void OP_SEG (int, int);
  72 static void OP_DIR (int, int);
  73 static void OP_OFF (int, int);
  74 static void OP_OFF64 (int, int);
  75 static void ptr_reg (int, int);
  76 static void OP_ESreg (int, int);
  77 static void OP_DSreg (int, int);
  78 static void OP_C (int, int);
  79 static void OP_D (int, int);
  80 static void OP_T (int, int);
  81 static void OP_R (int, int);
  82 static void OP_MMX (int, int);
  83 static void OP_XMM (int, int);
  84 static void OP_EM (int, int);
  85 static void OP_EX (int, int);
  86 static void OP_EMC (int,int);
  87 static void OP_MXC (int,int);
  88 static void OP_MS (int, int);
  89 static void OP_XS (int, int);
  90 static void OP_M (int, int);
  91 static void OP_VEX (int, int);
  92 static void OP_EX_Vex (int, int);
  93 static void OP_EX_VexW (int, int);
  94 static void OP_XMM_Vex (int, int);
  95 static void OP_XMM_VexW (int, int);
  96 static void OP_REG_VexI4 (int, int);
  97 static void PCLMUL_Fixup (int, int);
  98 static void VEXI4_Fixup (int, int);
  99 static void VZERO_Fixup (int, int);
 100 static void VCMP_Fixup (int, int);
 101 static void OP_0f07 (int, int);
 102 static void OP_Monitor (int, int);
 103 static void OP_Mwait (int, int);
 104 static void NOP_Fixup1 (int, int);
 105 static void NOP_Fixup2 (int, int);
 106 static void OP_3DNowSuffix (int, int);
 107 static void CMP_Fixup (int, int);
 108 static void BadOp (void);
 109 static void REP_Fixup (int, int);
 110 static void CMPXCHG8B_Fixup (int, int);
 111 static void XMM_Fixup (int, int);
 112 static void CRC32_Fixup (int, int);
 113 static void FXSAVE_Fixup (int, int);
 114 static void OP_LWPCB_E (int, int);
 115 static void OP_LWP_E (int, int);
 116 static void OP_LWP_I (int, int);
 117 static void OP_Vex_2src_1 (int, int);
 118 static void OP_Vex_2src_2 (int, int);
 119
 120 static void MOVBE_Fixup (int, int);
 121
 122 struct dis_private {
 123   /* Points to first byte not fetched.  */
 124   bfd_byte *max_fetched;
 125   bfd_byte the_buffer[MAX_MNEM_SIZE];
 126   bfd_vma insn_start;
 127   int orig_sizeflag;
 128   jmp_buf bailout;
 129 };
 130
 131 enum address_mode
 132 {
 133   mode_16bit,
 134   mode_32bit,
 135   mode_64bit
 136 };
 137
 138 enum address_mode address_mode;
 139
 140 /* Flags for the prefixes for the current instruction.  See below.  */
 141 static int prefixes;
 142
 143 /* REX prefix the current instruction.  See below.  */
 144 static int rex;
 145 /* Bits of REX we've already used.  */
 146 static int rex_used;
 147 /* Original REX prefix.  */
 148 static int rex_original;
 149 /* REX bits in original REX prefix ignored.  It may not be the same
 150    as rex_original since some bits may not be ignored.  */
 151 static int rex_ignored;
 152 /* Mark parts used in the REX prefix.  When we are testing for
 153    empty prefix (for 8bit register REX extension), just mask it
 154    out.  Otherwise test for REX bit is excuse for existence of REX
 155    only in case value is nonzero.  */
 156 #define USED_REX(value)                                 \
 157   {                                                     \
 158     if (value)                                          \
 159       {                                                 \
 160         if ((rex & value))                              \
 161           rex_used |= (value) | REX_OPCODE;             \
 162       }                                                 \
 163     else                                                \
 164       rex_used |= REX_OPCODE;                           \
 165   }
 166
 167 /* Flags for prefixes which we somehow handled when printing the
 168    current instruction.  */
 169 static int used_prefixes;
 170
 171 /* Flags stored in PREFIXES.  */
 172 #define PREFIX_REPZ 1
 173 #define PREFIX_REPNZ 2
 174 #define PREFIX_LOCK 4
 175 #define PREFIX_CS 8
 176 #define PREFIX_SS 0x10
 177 #define PREFIX_DS 0x20
 178 #define PREFIX_ES 0x40
 179 #define PREFIX_FS 0x80
 180 #define PREFIX_GS 0x100
 181 #define PREFIX_DATA 0x200
 182 #define PREFIX_ADDR 0x400
 183 #define PREFIX_FWAIT 0x800
 184
 185 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 186    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 187    on error.  */
 188 #define FETCH_DATA(info, addr) \
 189   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 190    ? 1 : fetch_data ((info), (addr)))
 191
 192 static int
 193 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 194 {
 195   int status;
 196   struct dis_private *priv = (struct dis_private *) info->private_data;
 197   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 198
 199   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 200     status = (*info->read_memory_func) (start,
 201                                         priv->max_fetched,
 202                                         addr - priv->max_fetched,
 203                                         info);
 204   else
 205     status = -1;
 206   if (status != 0)
 207     {
 208       /* If we did manage to read at least one byte, then
 209          print_insn_i386 will do something sensible.  Otherwise, print
 210          an error.  We do that here because this is where we know
 211          STATUS.  */
 212       if (priv->max_fetched == priv->the_buffer)
 213         (*info->memory_error_func) (status, start, info);
 214       longjmp (priv->bailout, 1);
 215     }
 216   else
 217     priv->max_fetched = addr;
 218   return 1;
 219 }
 220
 221 #define XX { NULL, 0 }
 222
 223 #define Eb { OP_E, b_mode }
 224 #define EbS { OP_E, b_swap_mode }
 225 #define Ev { OP_E, v_mode }
 226 #define EvS { OP_E, v_swap_mode }
 227 #define Ed { OP_E, d_mode }
 228 #define Edq { OP_E, dq_mode }
 229 #define Edqw { OP_E, dqw_mode }
 230 #define Edqb { OP_E, dqb_mode }
 231 #define Edqd { OP_E, dqd_mode }
 232 #define Eq { OP_E, q_mode }
 233 #define indirEv { OP_indirE, stack_v_mode }
 234 #define indirEp { OP_indirE, f_mode }
 235 #define stackEv { OP_E, stack_v_mode }
 236 #define Em { OP_E, m_mode }
 237 #define Ew { OP_E, w_mode }
 238 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 239 #define Ma { OP_M, a_mode }
 240 #define Mb { OP_M, b_mode }
 241 #define Md { OP_M, d_mode }
 242 #define Mo { OP_M, o_mode }
 243 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 244 #define Mq { OP_M, q_mode }
 245 #define Mx { OP_M, x_mode }
 246 #define Mxmm { OP_M, xmm_mode }
 247 #define Gb { OP_G, b_mode }
 248 #define Gv { OP_G, v_mode }
 249 #define Gd { OP_G, d_mode }
 250 #define Gdq { OP_G, dq_mode }
 251 #define Gm { OP_G, m_mode }
 252 #define Gw { OP_G, w_mode }
 253 #define Rd { OP_R, d_mode }
 254 #define Rm { OP_R, m_mode }
 255 #define Ib { OP_I, b_mode }
 256 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 257 #define Iv { OP_I, v_mode }
 258 #define Iq { OP_I, q_mode }
 259 #define Iv64 { OP_I64, v_mode }
 260 #define Iw { OP_I, w_mode }
 261 #define I1 { OP_I, const_1_mode }
 262 #define Jb { OP_J, b_mode }
 263 #define Jv { OP_J, v_mode }
 264 #define Cm { OP_C, m_mode }
 265 #define Dm { OP_D, m_mode }
 266 #define Td { OP_T, d_mode }
 267 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 268
 269 #define RMeAX { OP_REG, eAX_reg }
 270 #define RMeBX { OP_REG, eBX_reg }
 271 #define RMeCX { OP_REG, eCX_reg }
 272 #define RMeDX { OP_REG, eDX_reg }
 273 #define RMeSP { OP_REG, eSP_reg }
 274 #define RMeBP { OP_REG, eBP_reg }
 275 #define RMeSI { OP_REG, eSI_reg }
 276 #define RMeDI { OP_REG, eDI_reg }
 277 #define RMrAX { OP_REG, rAX_reg }
 278 #define RMrBX { OP_REG, rBX_reg }
 279 #define RMrCX { OP_REG, rCX_reg }
 280 #define RMrDX { OP_REG, rDX_reg }
 281 #define RMrSP { OP_REG, rSP_reg }
 282 #define RMrBP { OP_REG, rBP_reg }
 283 #define RMrSI { OP_REG, rSI_reg }
 284 #define RMrDI { OP_REG, rDI_reg }
 285 #define RMAL { OP_REG, al_reg }
 286 #define RMAL { OP_REG, al_reg }
 287 #define RMCL { OP_REG, cl_reg }
 288 #define RMDL { OP_REG, dl_reg }
 289 #define RMBL { OP_REG, bl_reg }
 290 #define RMAH { OP_REG, ah_reg }
 291 #define RMCH { OP_REG, ch_reg }
 292 #define RMDH { OP_REG, dh_reg }
 293 #define RMBH { OP_REG, bh_reg }
 294 #define RMAX { OP_REG, ax_reg }
 295 #define RMDX { OP_REG, dx_reg }
 296
 297 #define eAX { OP_IMREG, eAX_reg }
 298 #define eBX { OP_IMREG, eBX_reg }
 299 #define eCX { OP_IMREG, eCX_reg }
 300 #define eDX { OP_IMREG, eDX_reg }
 301 #define eSP { OP_IMREG, eSP_reg }
 302 #define eBP { OP_IMREG, eBP_reg }
 303 #define eSI { OP_IMREG, eSI_reg }
 304 #define eDI { OP_IMREG, eDI_reg }
 305 #define AL { OP_IMREG, al_reg }
 306 #define CL { OP_IMREG, cl_reg }
 307 #define DL { OP_IMREG, dl_reg }
 308 #define BL { OP_IMREG, bl_reg }
 309 #define AH { OP_IMREG, ah_reg }
 310 #define CH { OP_IMREG, ch_reg }
 311 #define DH { OP_IMREG, dh_reg }
 312 #define BH { OP_IMREG, bh_reg }
 313 #define AX { OP_IMREG, ax_reg }
 314 #define DX { OP_IMREG, dx_reg }
 315 #define zAX { OP_IMREG, z_mode_ax_reg }
 316 #define indirDX { OP_IMREG, indir_dx_reg }
 317
 318 #define Sw { OP_SEG, w_mode }
 319 #define Sv { OP_SEG, v_mode }
 320 #define Ap { OP_DIR, 0 }
 321 #define Ob { OP_OFF64, b_mode }
 322 #define Ov { OP_OFF64, v_mode }
 323 #define Xb { OP_DSreg, eSI_reg }
 324 #define Xv { OP_DSreg, eSI_reg }
 325 #define Xz { OP_DSreg, eSI_reg }
 326 #define Yb { OP_ESreg, eDI_reg }
 327 #define Yv { OP_ESreg, eDI_reg }
 328 #define DSBX { OP_DSreg, eBX_reg }
 329
 330 #define es { OP_REG, es_reg }
 331 #define ss { OP_REG, ss_reg }
 332 #define cs { OP_REG, cs_reg }
 333 #define ds { OP_REG, ds_reg }
 334 #define fs { OP_REG, fs_reg }
 335 #define gs { OP_REG, gs_reg }
 336
 337 #define MX { OP_MMX, 0 }
 338 #define XM { OP_XMM, 0 }
 339 #define XMM { OP_XMM, xmm_mode }
 340 #define EM { OP_EM, v_mode }
 341 #define EMS { OP_EM, v_swap_mode }
 342 #define EMd { OP_EM, d_mode }
 343 #define EMx { OP_EM, x_mode }
 344 #define EXw { OP_EX, w_mode }
 345 #define EXd { OP_EX, d_mode }
 346 #define EXdS { OP_EX, d_swap_mode }
 347 #define EXq { OP_EX, q_mode }
 348 #define EXqS { OP_EX, q_swap_mode }
 349 #define EXx { OP_EX, x_mode }
 350 #define EXxS { OP_EX, x_swap_mode }
 351 #define EXxmm { OP_EX, xmm_mode }
 352 #define EXxmmq { OP_EX, xmmq_mode }
 353 #define EXymmq { OP_EX, ymmq_mode }
 354 #define EXVexWdq { OP_EX, vex_w_dq_mode }
 355 #define MS { OP_MS, v_mode }
 356 #define XS { OP_XS, v_mode }
 357 #define EMCq { OP_EMC, q_mode }
 358 #define MXC { OP_MXC, 0 }
 359 #define OPSUF { OP_3DNowSuffix, 0 }
 360 #define CMP { CMP_Fixup, 0 }
 361 #define XMM0 { XMM_Fixup, 0 }
 362 #define FXSAVE { FXSAVE_Fixup, 0 }
 363 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
 364 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
 365
 366 #define Vex { OP_VEX, vex_mode }
 367 #define Vex128 { OP_VEX, vex128_mode }
 368 #define Vex256 { OP_VEX, vex256_mode }
 369 #define VexI4 { VEXI4_Fixup, 0}
 370 #define EXdVex { OP_EX_Vex, d_mode }
 371 #define EXdVexS { OP_EX_Vex, d_swap_mode }
 372 #define EXqVex { OP_EX_Vex, q_mode }
 373 #define EXqVexS { OP_EX_Vex, q_swap_mode }
 374 #define EXVexW { OP_EX_VexW, x_mode }
 375 #define EXdVexW { OP_EX_VexW, d_mode }
 376 #define EXqVexW { OP_EX_VexW, q_mode }
 377 #define XMVex { OP_XMM_Vex, 0 }
 378 #define XMVexW { OP_XMM_VexW, 0 }
 379 #define XMVexI4 { OP_REG_VexI4, x_mode }
 380 #define PCLMUL { PCLMUL_Fixup, 0 }
 381 #define VZERO { VZERO_Fixup, 0 }
 382 #define VCMP { VCMP_Fixup, 0 }
 383
 384 /* Used handle "rep" prefix for string instructions.  */
 385 #define Xbr { REP_Fixup, eSI_reg }
 386 #define Xvr { REP_Fixup, eSI_reg }
 387 #define Ybr { REP_Fixup, eDI_reg }
 388 #define Yvr { REP_Fixup, eDI_reg }
 389 #define Yzr { REP_Fixup, eDI_reg }
 390 #define indirDXr { REP_Fixup, indir_dx_reg }
 391 #define ALr { REP_Fixup, al_reg }
 392 #define eAXr { REP_Fixup, eAX_reg }
 393
 394 #define cond_jump_flag { NULL, cond_jump_mode }
 395 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 396
 397 /* bits in sizeflag */
 398 #define SUFFIX_ALWAYS 4
 399 #define AFLAG 2
 400 #define DFLAG 1
 401
 402 enum
 403 {
 404   /* byte operand */
 405   b_mode = 1,
 406   /* byte operand with operand swapped */
 407   b_swap_mode,
 408   /* operand size depends on prefixes */
 409   v_mode,
 410   /* operand size depends on prefixes with operand swapped */
 411   v_swap_mode,
 412   /* word operand */
 413   w_mode,
 414   /* double word operand  */
 415   d_mode,
 416   /* double word operand with operand swapped */
 417   d_swap_mode,
 418   /* quad word operand */
 419   q_mode,
 420   /* quad word operand with operand swapped */
 421   q_swap_mode,
 422   /* ten-byte operand */
 423   t_mode,
 424   /* 16-byte XMM or 32-byte YMM operand */
 425   x_mode,
 426   /* 16-byte XMM or 32-byte YMM operand with operand swapped */
 427   x_swap_mode,
 428   /* 16-byte XMM operand */
 429   xmm_mode,
 430   /* 16-byte XMM or quad word operand */
 431   xmmq_mode,
 432   /* 32-byte YMM or quad word operand */
 433   ymmq_mode,
 434   /* d_mode in 32bit, q_mode in 64bit mode.  */
 435   m_mode,
 436   /* pair of v_mode operands */
 437   a_mode,
 438   cond_jump_mode,
 439   loop_jcxz_mode,
 440   /* operand size depends on REX prefixes.  */
 441   dq_mode,
 442   /* registers like dq_mode, memory like w_mode.  */
 443   dqw_mode,
 444   /* 4- or 6-byte pointer operand */
 445   f_mode,
 446   const_1_mode,
 447   /* v_mode for stack-related opcodes.  */
 448   stack_v_mode,
 449   /* non-quad operand size depends on prefixes */
 450   z_mode,
 451   /* 16-byte operand */
 452   o_mode,
 453   /* registers like dq_mode, memory like b_mode.  */
 454   dqb_mode,
 455   /* registers like dq_mode, memory like d_mode.  */
 456   dqd_mode,
 457   /* normal vex mode */
 458   vex_mode,
 459   /* 128bit vex mode */
 460   vex128_mode,
 461   /* 256bit vex mode */
 462   vex256_mode,
 463   /* operand size depends on the VEX.W bit.  */
 464   vex_w_dq_mode,
 465
 466   es_reg,
 467   cs_reg,
 468   ss_reg,
 469   ds_reg,
 470   fs_reg,
 471   gs_reg,
 472
 473   eAX_reg,
 474   eCX_reg,
 475   eDX_reg,
 476   eBX_reg,
 477   eSP_reg,
 478   eBP_reg,
 479   eSI_reg,
 480   eDI_reg,
 481
 482   al_reg,
 483   cl_reg,
 484   dl_reg,
 485   bl_reg,
 486   ah_reg,
 487   ch_reg,
 488   dh_reg,
 489   bh_reg,
 490
 491   ax_reg,
 492   cx_reg,
 493   dx_reg,
 494   bx_reg,
 495   sp_reg,
 496   bp_reg,
 497   si_reg,
 498   di_reg,
 499
 500   rAX_reg,
 501   rCX_reg,
 502   rDX_reg,
 503   rBX_reg,
 504   rSP_reg,
 505   rBP_reg,
 506   rSI_reg,
 507   rDI_reg,
 508
 509   z_mode_ax_reg,
 510   indir_dx_reg
 511 };
 512
 513 enum
 514 {
 515   FLOATCODE = 1,
 516   USE_REG_TABLE,
 517   USE_MOD_TABLE,
 518   USE_RM_TABLE,
 519   USE_PREFIX_TABLE,
 520   USE_X86_64_TABLE,
 521   USE_3BYTE_TABLE,
 522   USE_XOP_8F_TABLE,
 523   USE_VEX_C4_TABLE,
 524   USE_VEX_C5_TABLE,
 525   USE_VEX_LEN_TABLE
 526 };
 527
 528 #define FLOAT                   NULL, { { NULL, FLOATCODE } }
 529
 530 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }
 531 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 532 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 533 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 534 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 535 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 536 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 537 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 538 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 539 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 540 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 541
 542 enum
 543 {
 544   REG_80 = 0,
 545   REG_81,
 546   REG_82,
 547   REG_8F,
 548   REG_C0,
 549   REG_C1,
 550   REG_C6,
 551   REG_C7,
 552   REG_D0,
 553   REG_D1,
 554   REG_D2,
 555   REG_D3,
 556   REG_F6,
 557   REG_F7,
 558   REG_FE,
 559   REG_FF,
 560   REG_0F00,
 561   REG_0F01,
 562   REG_0F0D,
 563   REG_0F18,
 564   REG_0F71,
 565   REG_0F72,
 566   REG_0F73,
 567   REG_0FA6,
 568   REG_0FA7,
 569   REG_0FAE,
 570   REG_0FBA,
 571   REG_0FC7,
 572   REG_VEX_71,
 573   REG_VEX_72,
 574   REG_VEX_73,
 575   REG_VEX_AE,
 576   REG_XOP_LWPCB,
 577   REG_XOP_LWP
 578 };
 579
 580 enum
 581 {
 582   MOD_8D = 0,
 583   MOD_0F01_REG_0,
 584   MOD_0F01_REG_1,
 585   MOD_0F01_REG_2,
 586   MOD_0F01_REG_3,
 587   MOD_0F01_REG_7,
 588   MOD_0F12_PREFIX_0,
 589   MOD_0F13,
 590   MOD_0F16_PREFIX_0,
 591   MOD_0F17,
 592   MOD_0F18_REG_0,
 593   MOD_0F18_REG_1,
 594   MOD_0F18_REG_2,
 595   MOD_0F18_REG_3,
 596   MOD_0F20,
 597   MOD_0F21,
 598   MOD_0F22,
 599   MOD_0F23,
 600   MOD_0F24,
 601   MOD_0F26,
 602   MOD_0F2B_PREFIX_0,
 603   MOD_0F2B_PREFIX_1,
 604   MOD_0F2B_PREFIX_2,
 605   MOD_0F2B_PREFIX_3,
 606   MOD_0F51,
 607   MOD_0F71_REG_2,
 608   MOD_0F71_REG_4,
 609   MOD_0F71_REG_6,
 610   MOD_0F72_REG_2,
 611   MOD_0F72_REG_4,
 612   MOD_0F72_REG_6,
 613   MOD_0F73_REG_2,
 614   MOD_0F73_REG_3,
 615   MOD_0F73_REG_6,
 616   MOD_0F73_REG_7,
 617   MOD_0FAE_REG_0,
 618   MOD_0FAE_REG_1,
 619   MOD_0FAE_REG_2,
 620   MOD_0FAE_REG_3,
 621   MOD_0FAE_REG_4,
 622   MOD_0FAE_REG_5,
 623   MOD_0FAE_REG_6,
 624   MOD_0FAE_REG_7,
 625   MOD_0FB2,
 626   MOD_0FB4,
 627   MOD_0FB5,
 628   MOD_0FC7_REG_6,
 629   MOD_0FC7_REG_7,
 630   MOD_0FD7,
 631   MOD_0FE7_PREFIX_2,
 632   MOD_0FF0_PREFIX_3,
 633   MOD_0F382A_PREFIX_2,
 634   MOD_62_32BIT,
 635   MOD_C4_32BIT,
 636   MOD_C5_32BIT,
 637   MOD_VEX_12_PREFIX_0,
 638   MOD_VEX_13,
 639   MOD_VEX_16_PREFIX_0,
 640   MOD_VEX_17,
 641   MOD_VEX_2B,
 642   MOD_VEX_50,
 643   MOD_VEX_71_REG_2,
 644   MOD_VEX_71_REG_4,
 645   MOD_VEX_71_REG_6,
 646   MOD_VEX_72_REG_2,
 647   MOD_VEX_72_REG_4,
 648   MOD_VEX_72_REG_6,
 649   MOD_VEX_73_REG_2,
 650   MOD_VEX_73_REG_3,
 651   MOD_VEX_73_REG_6,
 652   MOD_VEX_73_REG_7,
 653   MOD_VEX_AE_REG_2,
 654   MOD_VEX_AE_REG_3,
 655   MOD_VEX_D7_PREFIX_2,
 656   MOD_VEX_E7_PREFIX_2,
 657   MOD_VEX_F0_PREFIX_3,
 658   MOD_VEX_3818_PREFIX_2,
 659   MOD_VEX_3819_PREFIX_2,
 660   MOD_VEX_381A_PREFIX_2,
 661   MOD_VEX_382A_PREFIX_2,
 662   MOD_VEX_382C_PREFIX_2,
 663   MOD_VEX_382D_PREFIX_2,
 664   MOD_VEX_382E_PREFIX_2,
 665   MOD_VEX_382F_PREFIX_2
 666 };
 667
 668 enum
 669 {
 670   RM_0F01_REG_0 = 0,
 671   RM_0F01_REG_1,
 672   RM_0F01_REG_2,
 673   RM_0F01_REG_3,
 674   RM_0F01_REG_7,
 675   RM_0FAE_REG_5,
 676   RM_0FAE_REG_6,
 677   RM_0FAE_REG_7
 678 };
 679
 680 enum
 681 {
 682   PREFIX_90 = 0,
 683   PREFIX_0F10,
 684   PREFIX_0F11,
 685   PREFIX_0F12,
 686   PREFIX_0F16,
 687   PREFIX_0F2A,
 688   PREFIX_0F2B,
 689   PREFIX_0F2C,
 690   PREFIX_0F2D,
 691   PREFIX_0F2E,
 692   PREFIX_0F2F,
 693   PREFIX_0F51,
 694   PREFIX_0F52,
 695   PREFIX_0F53,
 696   PREFIX_0F58,
 697   PREFIX_0F59,
 698   PREFIX_0F5A,
 699   PREFIX_0F5B,
 700   PREFIX_0F5C,
 701   PREFIX_0F5D,
 702   PREFIX_0F5E,
 703   PREFIX_0F5F,
 704   PREFIX_0F60,
 705   PREFIX_0F61,
 706   PREFIX_0F62,
 707   PREFIX_0F6C,
 708   PREFIX_0F6D,
 709   PREFIX_0F6F,
 710   PREFIX_0F70,
 711   PREFIX_0F73_REG_3,
 712   PREFIX_0F73_REG_7,
 713   PREFIX_0F78,
 714   PREFIX_0F79,
 715   PREFIX_0F7C,
 716   PREFIX_0F7D,
 717   PREFIX_0F7E,
 718   PREFIX_0F7F,
 719   PREFIX_0FB8,
 720   PREFIX_0FBD,
 721   PREFIX_0FC2,
 722   PREFIX_0FC3,
 723   PREFIX_0FC7_REG_6,
 724   PREFIX_0FD0,
 725   PREFIX_0FD6,
 726   PREFIX_0FE6,
 727   PREFIX_0FE7,
 728   PREFIX_0FF0,
 729   PREFIX_0FF7,
 730   PREFIX_0F3810,
 731   PREFIX_0F3814,
 732   PREFIX_0F3815,
 733   PREFIX_0F3817,
 734   PREFIX_0F3820,
 735   PREFIX_0F3821,
 736   PREFIX_0F3822,
 737   PREFIX_0F3823,
 738   PREFIX_0F3824,
 739   PREFIX_0F3825,
 740   PREFIX_0F3828,
 741   PREFIX_0F3829,
 742   PREFIX_0F382A,
 743   PREFIX_0F382B,
 744   PREFIX_0F3830,
 745   PREFIX_0F3831,
 746   PREFIX_0F3832,
 747   PREFIX_0F3833,
 748   PREFIX_0F3834,
 749   PREFIX_0F3835,
 750   PREFIX_0F3837,
 751   PREFIX_0F3838,
 752   PREFIX_0F3839,
 753   PREFIX_0F383A,
 754   PREFIX_0F383B,
 755   PREFIX_0F383C,
 756   PREFIX_0F383D,
 757   PREFIX_0F383E,
 758   PREFIX_0F383F,
 759   PREFIX_0F3840,
 760   PREFIX_0F3841,
 761   PREFIX_0F3880,
 762   PREFIX_0F3881,
 763   PREFIX_0F38DB,
 764   PREFIX_0F38DC,
 765   PREFIX_0F38DD,
 766   PREFIX_0F38DE,
 767   PREFIX_0F38DF,
 768   PREFIX_0F38F0,
 769   PREFIX_0F38F1,
 770   PREFIX_0F3A08,
 771   PREFIX_0F3A09,
 772   PREFIX_0F3A0A,
 773   PREFIX_0F3A0B,
 774   PREFIX_0F3A0C,
 775   PREFIX_0F3A0D,
 776   PREFIX_0F3A0E,
 777   PREFIX_0F3A14,
 778   PREFIX_0F3A15,
 779   PREFIX_0F3A16,
 780   PREFIX_0F3A17,
 781   PREFIX_0F3A20,
 782   PREFIX_0F3A21,
 783   PREFIX_0F3A22,
 784   PREFIX_0F3A40,
 785   PREFIX_0F3A41,
 786   PREFIX_0F3A42,
 787   PREFIX_0F3A44,
 788   PREFIX_0F3A60,
 789   PREFIX_0F3A61,
 790   PREFIX_0F3A62,
 791   PREFIX_0F3A63,
 792   PREFIX_0F3ADF,
 793   PREFIX_VEX_10,
 794   PREFIX_VEX_11,
 795   PREFIX_VEX_12,
 796   PREFIX_VEX_16,
 797   PREFIX_VEX_2A,
 798   PREFIX_VEX_2C,
 799   PREFIX_VEX_2D,
 800   PREFIX_VEX_2E,
 801   PREFIX_VEX_2F,
 802   PREFIX_VEX_51,
 803   PREFIX_VEX_52,
 804   PREFIX_VEX_53,
 805   PREFIX_VEX_58,
 806   PREFIX_VEX_59,
 807   PREFIX_VEX_5A,
 808   PREFIX_VEX_5B,
 809   PREFIX_VEX_5C,
 810   PREFIX_VEX_5D,
 811   PREFIX_VEX_5E,
 812   PREFIX_VEX_5F,
 813   PREFIX_VEX_60,
 814   PREFIX_VEX_61,
 815   PREFIX_VEX_62,
 816   PREFIX_VEX_63,
 817   PREFIX_VEX_64,
 818   PREFIX_VEX_65,
 819   PREFIX_VEX_66,
 820   PREFIX_VEX_67,
 821   PREFIX_VEX_68,
 822   PREFIX_VEX_69,
 823   PREFIX_VEX_6A,
 824   PREFIX_VEX_6B,
 825   PREFIX_VEX_6C,
 826   PREFIX_VEX_6D,
 827   PREFIX_VEX_6E,
 828   PREFIX_VEX_6F,
 829   PREFIX_VEX_70,
 830   PREFIX_VEX_71_REG_2,
 831   PREFIX_VEX_71_REG_4,
 832   PREFIX_VEX_71_REG_6,
 833   PREFIX_VEX_72_REG_2,
 834   PREFIX_VEX_72_REG_4,
 835   PREFIX_VEX_72_REG_6,
 836   PREFIX_VEX_73_REG_2,
 837   PREFIX_VEX_73_REG_3,
 838   PREFIX_VEX_73_REG_6,
 839   PREFIX_VEX_73_REG_7,
 840   PREFIX_VEX_74,
 841   PREFIX_VEX_75,
 842   PREFIX_VEX_76,
 843   PREFIX_VEX_77,
 844   PREFIX_VEX_7C,
 845   PREFIX_VEX_7D,
 846   PREFIX_VEX_7E,
 847   PREFIX_VEX_7F,
 848   PREFIX_VEX_C2,
 849   PREFIX_VEX_C4,
 850   PREFIX_VEX_C5,
 851   PREFIX_VEX_D0,
 852   PREFIX_VEX_D1,
 853   PREFIX_VEX_D2,
 854   PREFIX_VEX_D3,
 855   PREFIX_VEX_D4,
 856   PREFIX_VEX_D5,
 857   PREFIX_VEX_D6,
 858   PREFIX_VEX_D7,
 859   PREFIX_VEX_D8,
 860   PREFIX_VEX_D9,
 861   PREFIX_VEX_DA,
 862   PREFIX_VEX_DB,
 863   PREFIX_VEX_DC,
 864   PREFIX_VEX_DD,
 865   PREFIX_VEX_DE,
 866   PREFIX_VEX_DF,
 867   PREFIX_VEX_E0,
 868   PREFIX_VEX_E1,
 869   PREFIX_VEX_E2,
 870   PREFIX_VEX_E3,
 871   PREFIX_VEX_E4,
 872   PREFIX_VEX_E5,
 873   PREFIX_VEX_E6,
 874   PREFIX_VEX_E7,
 875   PREFIX_VEX_E8,
 876   PREFIX_VEX_E9,
 877   PREFIX_VEX_EA,
 878   PREFIX_VEX_EB,
 879   PREFIX_VEX_EC,
 880   PREFIX_VEX_ED,
 881   PREFIX_VEX_EE,
 882   PREFIX_VEX_EF,
 883   PREFIX_VEX_F0,
 884   PREFIX_VEX_F1,
 885   PREFIX_VEX_F2,
 886   PREFIX_VEX_F3,
 887   PREFIX_VEX_F4,
 888   PREFIX_VEX_F5,
 889   PREFIX_VEX_F6,
 890   PREFIX_VEX_F7,
 891   PREFIX_VEX_F8,
 892   PREFIX_VEX_F9,
 893   PREFIX_VEX_FA,
 894   PREFIX_VEX_FB,
 895   PREFIX_VEX_FC,
 896   PREFIX_VEX_FD,
 897   PREFIX_VEX_FE,
 898   PREFIX_VEX_3800,
 899   PREFIX_VEX_3801,
 900   PREFIX_VEX_3802,
 901   PREFIX_VEX_3803,
 902   PREFIX_VEX_3804,
 903   PREFIX_VEX_3805,
 904   PREFIX_VEX_3806,
 905   PREFIX_VEX_3807,
 906   PREFIX_VEX_3808,
 907   PREFIX_VEX_3809,
 908   PREFIX_VEX_380A,
 909   PREFIX_VEX_380B,
 910   PREFIX_VEX_380C,
 911   PREFIX_VEX_380D,
 912   PREFIX_VEX_380E,
 913   PREFIX_VEX_380F,
 914   PREFIX_VEX_3817,
 915   PREFIX_VEX_3818,
 916   PREFIX_VEX_3819,
 917   PREFIX_VEX_381A,
 918   PREFIX_VEX_381C,
 919   PREFIX_VEX_381D,
 920   PREFIX_VEX_381E,
 921   PREFIX_VEX_3820,
 922   PREFIX_VEX_3821,
 923   PREFIX_VEX_3822,
 924   PREFIX_VEX_3823,
 925   PREFIX_VEX_3824,
 926   PREFIX_VEX_3825,
 927   PREFIX_VEX_3828,
 928   PREFIX_VEX_3829,
 929   PREFIX_VEX_382A,
 930   PREFIX_VEX_382B,
 931   PREFIX_VEX_382C,
 932   PREFIX_VEX_382D,
 933   PREFIX_VEX_382E,
 934   PREFIX_VEX_382F,
 935   PREFIX_VEX_3830,
 936   PREFIX_VEX_3831,
 937   PREFIX_VEX_3832,
 938   PREFIX_VEX_3833,
 939   PREFIX_VEX_3834,
 940   PREFIX_VEX_3835,
 941   PREFIX_VEX_3837,
 942   PREFIX_VEX_3838,
 943   PREFIX_VEX_3839,
 944   PREFIX_VEX_383A,
 945   PREFIX_VEX_383B,
 946   PREFIX_VEX_383C,
 947   PREFIX_VEX_383D,
 948   PREFIX_VEX_383E,
 949   PREFIX_VEX_383F,
 950   PREFIX_VEX_3840,
 951   PREFIX_VEX_3841,
 952   PREFIX_VEX_3896,
 953   PREFIX_VEX_3897,
 954   PREFIX_VEX_3898,
 955   PREFIX_VEX_3899,
 956   PREFIX_VEX_389A,
 957   PREFIX_VEX_389B,
 958   PREFIX_VEX_389C,
 959   PREFIX_VEX_389D,
 960   PREFIX_VEX_389E,
 961   PREFIX_VEX_389F,
 962   PREFIX_VEX_38A6,
 963   PREFIX_VEX_38A7,
 964   PREFIX_VEX_38A8,
 965   PREFIX_VEX_38A9,
 966   PREFIX_VEX_38AA,
 967   PREFIX_VEX_38AB,
 968   PREFIX_VEX_38AC,
 969   PREFIX_VEX_38AD,
 970   PREFIX_VEX_38AE,
 971   PREFIX_VEX_38AF,
 972   PREFIX_VEX_38B6,
 973   PREFIX_VEX_38B7,
 974   PREFIX_VEX_38B8,
 975   PREFIX_VEX_38B9,
 976   PREFIX_VEX_38BA,
 977   PREFIX_VEX_38BB,
 978   PREFIX_VEX_38BC,
 979   PREFIX_VEX_38BD,
 980   PREFIX_VEX_38BE,
 981   PREFIX_VEX_38BF,
 982   PREFIX_VEX_38DB,
 983   PREFIX_VEX_38DC,
 984   PREFIX_VEX_38DD,
 985   PREFIX_VEX_38DE,
 986   PREFIX_VEX_38DF,
 987   PREFIX_VEX_3A04,
 988   PREFIX_VEX_3A05,
 989   PREFIX_VEX_3A06,
 990   PREFIX_VEX_3A08,
 991   PREFIX_VEX_3A09,
 992   PREFIX_VEX_3A0A,
 993   PREFIX_VEX_3A0B,
 994   PREFIX_VEX_3A0C,
 995   PREFIX_VEX_3A0D,
 996   PREFIX_VEX_3A0E,
 997   PREFIX_VEX_3A0F,
 998   PREFIX_VEX_3A14,
 999   PREFIX_VEX_3A15,
1000   PREFIX_VEX_3A16,
1001   PREFIX_VEX_3A17,
1002   PREFIX_VEX_3A18,
1003   PREFIX_VEX_3A19,
1004   PREFIX_VEX_3A20,
1005   PREFIX_VEX_3A21,
1006   PREFIX_VEX_3A22,
1007   PREFIX_VEX_3A40,
1008   PREFIX_VEX_3A41,
1009   PREFIX_VEX_3A42,
1010   PREFIX_VEX_3A44,
1011   PREFIX_VEX_3A4A,
1012   PREFIX_VEX_3A4B,
1013   PREFIX_VEX_3A4C,
1014   PREFIX_VEX_3A5C,
1015   PREFIX_VEX_3A5D,
1016   PREFIX_VEX_3A5E,
1017   PREFIX_VEX_3A5F,
1018   PREFIX_VEX_3A60,
1019   PREFIX_VEX_3A61,
1020   PREFIX_VEX_3A62,
1021   PREFIX_VEX_3A63,
1022   PREFIX_VEX_3A68,
1023   PREFIX_VEX_3A69,
1024   PREFIX_VEX_3A6A,
1025   PREFIX_VEX_3A6B,
1026   PREFIX_VEX_3A6C,
1027   PREFIX_VEX_3A6D,
1028   PREFIX_VEX_3A6E,
1029   PREFIX_VEX_3A6F,
1030   PREFIX_VEX_3A78,
1031   PREFIX_VEX_3A79,
1032   PREFIX_VEX_3A7A,
1033   PREFIX_VEX_3A7B,
1034   PREFIX_VEX_3A7C,
1035   PREFIX_VEX_3A7D,
1036   PREFIX_VEX_3A7E,
1037   PREFIX_VEX_3A7F,
1038   PREFIX_VEX_3ADF
1039 };
1040
1041 enum
1042 {
1043   X86_64_06 = 0,
1044   X86_64_07,
1045   X86_64_0D,
1046   X86_64_16,
1047   X86_64_17,
1048   X86_64_1E,
1049   X86_64_1F,
1050   X86_64_27,
1051   X86_64_2F,
1052   X86_64_37,
1053   X86_64_3F,
1054   X86_64_60,
1055   X86_64_61,
1056   X86_64_62,
1057   X86_64_63,
1058   X86_64_6D,
1059   X86_64_6F,
1060   X86_64_9A,
1061   X86_64_C4,
1062   X86_64_C5,
1063   X86_64_CE,
1064   X86_64_D4,
1065   X86_64_D5,
1066   X86_64_EA,
1067   X86_64_0F01_REG_0,
1068   X86_64_0F01_REG_1,
1069   X86_64_0F01_REG_2,
1070   X86_64_0F01_REG_3
1071 };
1072
1073 enum
1074 {
1075   THREE_BYTE_0F38 = 0,
1076   THREE_BYTE_0F3A,
1077   THREE_BYTE_0F7A
1078 };
1079
1080 enum
1081 {
1082   XOP_08 = 0,
1083   XOP_09,
1084   XOP_0A
1085 };
1086
1087 enum
1088 {
1089   VEX_0F = 0,
1090   VEX_0F38,
1091   VEX_0F3A
1092 };
1093
1094 enum
1095 {
1096   VEX_LEN_10_P_1 = 0,
1097   VEX_LEN_10_P_3,
1098   VEX_LEN_11_P_1,
1099   VEX_LEN_11_P_3,
1100   VEX_LEN_12_P_0_M_0,
1101   VEX_LEN_12_P_0_M_1,
1102   VEX_LEN_12_P_2,
1103   VEX_LEN_13_M_0,
1104   VEX_LEN_16_P_0_M_0,
1105   VEX_LEN_16_P_0_M_1,
1106   VEX_LEN_16_P_2,
1107   VEX_LEN_17_M_0,
1108   VEX_LEN_2A_P_1,
1109   VEX_LEN_2A_P_3,
1110   VEX_LEN_2C_P_1,
1111   VEX_LEN_2C_P_3,
1112   VEX_LEN_2D_P_1,
1113   VEX_LEN_2D_P_3,
1114   VEX_LEN_2E_P_0,
1115   VEX_LEN_2E_P_2,
1116   VEX_LEN_2F_P_0,
1117   VEX_LEN_2F_P_2,
1118   VEX_LEN_51_P_1,
1119   VEX_LEN_51_P_3,
1120   VEX_LEN_52_P_1,
1121   VEX_LEN_53_P_1,
1122   VEX_LEN_58_P_1,
1123   VEX_LEN_58_P_3,
1124   VEX_LEN_59_P_1,
1125   VEX_LEN_59_P_3,
1126   VEX_LEN_5A_P_1,
1127   VEX_LEN_5A_P_3,
1128   VEX_LEN_5C_P_1,
1129   VEX_LEN_5C_P_3,
1130   VEX_LEN_5D_P_1,
1131   VEX_LEN_5D_P_3,
1132   VEX_LEN_5E_P_1,
1133   VEX_LEN_5E_P_3,
1134   VEX_LEN_5F_P_1,
1135   VEX_LEN_5F_P_3,
1136   VEX_LEN_60_P_2,
1137   VEX_LEN_61_P_2,
1138   VEX_LEN_62_P_2,
1139   VEX_LEN_63_P_2,
1140   VEX_LEN_64_P_2,
1141   VEX_LEN_65_P_2,
1142   VEX_LEN_66_P_2,
1143   VEX_LEN_67_P_2,
1144   VEX_LEN_68_P_2,
1145   VEX_LEN_69_P_2,
1146   VEX_LEN_6A_P_2,
1147   VEX_LEN_6B_P_2,
1148   VEX_LEN_6C_P_2,
1149   VEX_LEN_6D_P_2,
1150   VEX_LEN_6E_P_2,
1151   VEX_LEN_70_P_1,
1152   VEX_LEN_70_P_2,
1153   VEX_LEN_70_P_3,
1154   VEX_LEN_71_R_2_P_2,
1155   VEX_LEN_71_R_4_P_2,
1156   VEX_LEN_71_R_6_P_2,
1157   VEX_LEN_72_R_2_P_2,
1158   VEX_LEN_72_R_4_P_2,
1159   VEX_LEN_72_R_6_P_2,
1160   VEX_LEN_73_R_2_P_2,
1161   VEX_LEN_73_R_3_P_2,
1162   VEX_LEN_73_R_6_P_2,
1163   VEX_LEN_73_R_7_P_2,
1164   VEX_LEN_74_P_2,
1165   VEX_LEN_75_P_2,
1166   VEX_LEN_76_P_2,
1167   VEX_LEN_7E_P_1,
1168   VEX_LEN_7E_P_2,
1169   VEX_LEN_AE_R_2_M_0,
1170   VEX_LEN_AE_R_3_M_0,
1171   VEX_LEN_C2_P_1,
1172   VEX_LEN_C2_P_3,
1173   VEX_LEN_C4_P_2,
1174   VEX_LEN_C5_P_2,
1175   VEX_LEN_D1_P_2,
1176   VEX_LEN_D2_P_2,
1177   VEX_LEN_D3_P_2,
1178   VEX_LEN_D4_P_2,
1179   VEX_LEN_D5_P_2,
1180   VEX_LEN_D6_P_2,
1181   VEX_LEN_D7_P_2_M_1,
1182   VEX_LEN_D8_P_2,
1183   VEX_LEN_D9_P_2,
1184   VEX_LEN_DA_P_2,
1185   VEX_LEN_DB_P_2,
1186   VEX_LEN_DC_P_2,
1187   VEX_LEN_DD_P_2,
1188   VEX_LEN_DE_P_2,
1189   VEX_LEN_DF_P_2,
1190   VEX_LEN_E0_P_2,
1191   VEX_LEN_E1_P_2,
1192   VEX_LEN_E2_P_2,
1193   VEX_LEN_E3_P_2,
1194   VEX_LEN_E4_P_2,
1195   VEX_LEN_E5_P_2,
1196   VEX_LEN_E8_P_2,
1197   VEX_LEN_E9_P_2,
1198   VEX_LEN_EA_P_2,
1199   VEX_LEN_EB_P_2,
1200   VEX_LEN_EC_P_2,
1201   VEX_LEN_ED_P_2,
1202   VEX_LEN_EE_P_2,
1203   VEX_LEN_EF_P_2,
1204   VEX_LEN_F1_P_2,
1205   VEX_LEN_F2_P_2,
1206   VEX_LEN_F3_P_2,
1207   VEX_LEN_F4_P_2,
1208   VEX_LEN_F5_P_2,
1209   VEX_LEN_F6_P_2,
1210   VEX_LEN_F7_P_2,
1211   VEX_LEN_F8_P_2,
1212   VEX_LEN_F9_P_2,
1213   VEX_LEN_FA_P_2,
1214   VEX_LEN_FB_P_2,
1215   VEX_LEN_FC_P_2,
1216   VEX_LEN_FD_P_2,
1217   VEX_LEN_FE_P_2,
1218   VEX_LEN_3800_P_2,
1219   VEX_LEN_3801_P_2,
1220   VEX_LEN_3802_P_2,
1221   VEX_LEN_3803_P_2,
1222   VEX_LEN_3804_P_2,
1223   VEX_LEN_3805_P_2,
1224   VEX_LEN_3806_P_2,
1225   VEX_LEN_3807_P_2,
1226   VEX_LEN_3808_P_2,
1227   VEX_LEN_3809_P_2,
1228   VEX_LEN_380A_P_2,
1229   VEX_LEN_380B_P_2,
1230   VEX_LEN_3819_P_2_M_0,
1231   VEX_LEN_381A_P_2_M_0,
1232   VEX_LEN_381C_P_2,
1233   VEX_LEN_381D_P_2,
1234   VEX_LEN_381E_P_2,
1235   VEX_LEN_3820_P_2,
1236   VEX_LEN_3821_P_2,
1237   VEX_LEN_3822_P_2,
1238   VEX_LEN_3823_P_2,
1239   VEX_LEN_3824_P_2,
1240   VEX_LEN_3825_P_2,
1241   VEX_LEN_3828_P_2,
1242   VEX_LEN_3829_P_2,
1243   VEX_LEN_382A_P_2_M_0,
1244   VEX_LEN_382B_P_2,
1245   VEX_LEN_3830_P_2,
1246   VEX_LEN_3831_P_2,
1247   VEX_LEN_3832_P_2,
1248   VEX_LEN_3833_P_2,
1249   VEX_LEN_3834_P_2,
1250   VEX_LEN_3835_P_2,
1251   VEX_LEN_3837_P_2,
1252   VEX_LEN_3838_P_2,
1253   VEX_LEN_3839_P_2,
1254   VEX_LEN_383A_P_2,
1255   VEX_LEN_383B_P_2,
1256   VEX_LEN_383C_P_2,
1257   VEX_LEN_383D_P_2,
1258   VEX_LEN_383E_P_2,
1259   VEX_LEN_383F_P_2,
1260   VEX_LEN_3840_P_2,
1261   VEX_LEN_3841_P_2,
1262   VEX_LEN_38DB_P_2,
1263   VEX_LEN_38DC_P_2,
1264   VEX_LEN_38DD_P_2,
1265   VEX_LEN_38DE_P_2,
1266   VEX_LEN_38DF_P_2,
1267   VEX_LEN_3A06_P_2,
1268   VEX_LEN_3A0A_P_2,
1269   VEX_LEN_3A0B_P_2,
1270   VEX_LEN_3A0E_P_2,
1271   VEX_LEN_3A0F_P_2,
1272   VEX_LEN_3A14_P_2,
1273   VEX_LEN_3A15_P_2,
1274   VEX_LEN_3A16_P_2,
1275   VEX_LEN_3A17_P_2,
1276   VEX_LEN_3A18_P_2,
1277   VEX_LEN_3A19_P_2,
1278   VEX_LEN_3A20_P_2,
1279   VEX_LEN_3A21_P_2,
1280   VEX_LEN_3A22_P_2,
1281   VEX_LEN_3A41_P_2,
1282   VEX_LEN_3A42_P_2,
1283   VEX_LEN_3A44_P_2,
1284   VEX_LEN_3A4C_P_2,
1285   VEX_LEN_3A60_P_2,
1286   VEX_LEN_3A61_P_2,
1287   VEX_LEN_3A62_P_2,
1288   VEX_LEN_3A63_P_2,
1289   VEX_LEN_3A6A_P_2,
1290   VEX_LEN_3A6B_P_2,
1291   VEX_LEN_3A6E_P_2,
1292   VEX_LEN_3A6F_P_2,
1293   VEX_LEN_3A7A_P_2,
1294   VEX_LEN_3A7B_P_2,
1295   VEX_LEN_3A7E_P_2,
1296   VEX_LEN_3A7F_P_2,
1297   VEX_LEN_3ADF_P_2,
1298   VEX_LEN_XOP_09_80,
1299   VEX_LEN_XOP_09_81
1300 };
1301
1302 typedef void (*op_rtn) (int bytemode, int sizeflag);
1303
1304 struct dis386 {
1305   const char *name;
1306   struct
1307     {
1308       op_rtn rtn;
1309       int bytemode;
1310     } op[MAX_OPERANDS];
1311 };
1312
1313 /* Upper case letters in the instruction names here are macros.
1314    'A' => print 'b' if no register operands or suffix_always is true
1315    'B' => print 'b' if suffix_always is true
1316    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
1317           size prefix
1318    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
1319           suffix_always is true
1320    'E' => print 'e' if 32-bit form of jcxz
1321    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
1322    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
1323    'H' => print ",pt" or ",pn" branch hint
1324    'I' => honor following macro letter even in Intel mode (implemented only
1325           for some of the macro letters)
1326    'J' => print 'l'
1327    'K' => print 'd' or 'q' if rex prefix is present.
1328    'L' => print 'l' if suffix_always is true
1329    'M' => print 'r' if intel_mnemonic is false.
1330    'N' => print 'n' if instruction has no wait "prefix"
1331    'O' => print 'd' or 'o' (or 'q' in Intel mode)
1332    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
1333           or suffix_always is true.  print 'q' if rex prefix is present.
1334    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
1335           is true
1336    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
1337    'S' => print 'w', 'l' or 'q' if suffix_always is true
1338    'T' => print 'q' in 64bit mode and behave as 'P' otherwise
1339    'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
1340    'V' => print 'q' in 64bit mode and behave as 'S' otherwise
1341    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
1342    'X' => print 's', 'd' depending on data16 prefix (for XMM)
1343    'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
1344           suffix_always is true.
1345    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
1346    '!' => change condition from true to false or from false to true.
1347    '%' => add 1 upper case letter to the macro.
1348
1349    2 upper case letter macros:
1350    "XY" => print 'x' or 'y' if no register operands or suffix_always
1351            is true.
1352    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
1353    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
1354            or suffix_always is true
1355    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
1356    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
1357    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
1358
1359    Many of the above letters print nothing in Intel mode.  See "putop"
1360    for the details.
1361
1362    Braces '{' and '}', and vertical bars '|', indicate alternative
1363    mnemonic strings for AT&T and Intel.  */
1364
1365 static const struct dis386 dis386[] = {
1366   /* 00 */
1367   { "addB",             { Eb, Gb } },
1368   { "addS",             { Ev, Gv } },
1369   { "addB",             { Gb, EbS } },
1370   { "addS",             { Gv, EvS } },
1371   { "addB",             { AL, Ib } },
1372   { "addS",             { eAX, Iv } },
1373   { X86_64_TABLE (X86_64_06) },
1374   { X86_64_TABLE (X86_64_07) },
1375   /* 08 */
1376   { "orB",              { Eb, Gb } },
1377   { "orS",              { Ev, Gv } },
1378   { "orB",              { Gb, EbS } },
1379   { "orS",              { Gv, EvS } },
1380   { "orB",              { AL, Ib } },
1381   { "orS",              { eAX, Iv } },
1382   { X86_64_TABLE (X86_64_0D) },
1383   { "(bad)",            { XX } },       /* 0x0f extended opcode escape */
1384   /* 10 */
1385   { "adcB",             { Eb, Gb } },
1386   { "adcS",             { Ev, Gv } },
1387   { "adcB",             { Gb, EbS } },
1388   { "adcS",             { Gv, EvS } },
1389   { "adcB",             { AL, Ib } },
1390   { "adcS",             { eAX, Iv } },
1391   { X86_64_TABLE (X86_64_16) },
1392   { X86_64_TABLE (X86_64_17) },
1393   /* 18 */
1394   { "sbbB",             { Eb, Gb } },
1395   { "sbbS",             { Ev, Gv } },
1396   { "sbbB",             { Gb, EbS } },
1397   { "sbbS",             { Gv, EvS } },
1398   { "sbbB",             { AL, Ib } },
1399   { "sbbS",             { eAX, Iv } },
1400   { X86_64_TABLE (X86_64_1E) },
1401   { X86_64_TABLE (X86_64_1F) },
1402   /* 20 */
1403   { "andB",             { Eb, Gb } },
1404   { "andS",             { Ev, Gv } },
1405   { "andB",             { Gb, EbS } },
1406   { "andS",             { Gv, EvS } },
1407   { "andB",             { AL, Ib } },
1408   { "andS",             { eAX, Iv } },
1409   { "(bad)",            { XX } },       /* SEG ES prefix */
1410   { X86_64_TABLE (X86_64_27) },
1411   /* 28 */
1412   { "subB",             { Eb, Gb } },
1413   { "subS",             { Ev, Gv } },
1414   { "subB",             { Gb, EbS } },
1415   { "subS",             { Gv, EvS } },
1416   { "subB",             { AL, Ib } },
1417   { "subS",             { eAX, Iv } },
1418   { "(bad)",            { XX } },       /* SEG CS prefix */
1419   { X86_64_TABLE (X86_64_2F) },
1420   /* 30 */
1421   { "xorB",             { Eb, Gb } },
1422   { "xorS",             { Ev, Gv } },
1423   { "xorB",             { Gb, EbS } },
1424   { "xorS",             { Gv, EvS } },
1425   { "xorB",             { AL, Ib } },
1426   { "xorS",             { eAX, Iv } },
1427   { "(bad)",            { XX } },       /* SEG SS prefix */
1428   { X86_64_TABLE (X86_64_37) },
1429   /* 38 */
1430   { "cmpB",             { Eb, Gb } },
1431   { "cmpS",             { Ev, Gv } },
1432   { "cmpB",             { Gb, EbS } },
1433   { "cmpS",             { Gv, EvS } },
1434   { "cmpB",             { AL, Ib } },
1435   { "cmpS",             { eAX, Iv } },
1436   { "(bad)",            { XX } },       /* SEG DS prefix */
1437   { X86_64_TABLE (X86_64_3F) },
1438   /* 40 */
1439   { "inc{S|}",          { RMeAX } },
1440   { "inc{S|}",          { RMeCX } },
1441   { "inc{S|}",          { RMeDX } },
1442   { "inc{S|}",          { RMeBX } },
1443   { "inc{S|}",          { RMeSP } },
1444   { "inc{S|}",          { RMeBP } },
1445   { "inc{S|}",          { RMeSI } },
1446   { "inc{S|}",          { RMeDI } },
1447   /* 48 */
1448   { "dec{S|}",          { RMeAX } },
1449   { "dec{S|}",          { RMeCX } },
1450   { "dec{S|}",          { RMeDX } },
1451   { "dec{S|}",          { RMeBX } },
1452   { "dec{S|}",          { RMeSP } },
1453   { "dec{S|}",          { RMeBP } },
1454   { "dec{S|}",          { RMeSI } },
1455   { "dec{S|}",          { RMeDI } },
1456   /* 50 */
1457   { "pushV",            { RMrAX } },
1458   { "pushV",            { RMrCX } },
1459   { "pushV",            { RMrDX } },
1460   { "pushV",            { RMrBX } },
1461   { "pushV",            { RMrSP } },
1462   { "pushV",            { RMrBP } },
1463   { "pushV",            { RMrSI } },
1464   { "pushV",            { RMrDI } },
1465   /* 58 */
1466   { "popV",             { RMrAX } },
1467   { "popV",             { RMrCX } },
1468   { "popV",             { RMrDX } },
1469   { "popV",             { RMrBX } },
1470   { "popV",             { RMrSP } },
1471   { "popV",             { RMrBP } },
1472   { "popV",             { RMrSI } },
1473   { "popV",             { RMrDI } },
1474   /* 60 */
1475   { X86_64_TABLE (X86_64_60) },
1476   { X86_64_TABLE (X86_64_61) },
1477   { X86_64_TABLE (X86_64_62) },
1478   { X86_64_TABLE (X86_64_63) },
1479   { "(bad)",            { XX } },       /* seg fs */
1480   { "(bad)",            { XX } },       /* seg gs */
1481   { "(bad)",            { XX } },       /* op size prefix */
1482   { "(bad)",            { XX } },       /* adr size prefix */
1483   /* 68 */
1484   { "pushT",            { Iq } },
1485   { "imulS",            { Gv, Ev, Iv } },
1486   { "pushT",            { sIb } },
1487   { "imulS",            { Gv, Ev, sIb } },
1488   { "ins{b|}",          { Ybr, indirDX } },
1489   { X86_64_TABLE (X86_64_6D) },
1490   { "outs{b|}",         { indirDXr, Xb } },
1491   { X86_64_TABLE (X86_64_6F) },
1492   /* 70 */
1493   { "joH",              { Jb, XX, cond_jump_flag } },
1494   { "jnoH",             { Jb, XX, cond_jump_flag } },
1495   { "jbH",              { Jb, XX, cond_jump_flag } },
1496   { "jaeH",             { Jb, XX, cond_jump_flag } },
1497   { "jeH",              { Jb, XX, cond_jump_flag } },
1498   { "jneH",             { Jb, XX, cond_jump_flag } },
1499   { "jbeH",             { Jb, XX, cond_jump_flag } },
1500   { "jaH",              { Jb, XX, cond_jump_flag } },
1501   /* 78 */
1502   { "jsH",              { Jb, XX, cond_jump_flag } },
1503   { "jnsH",             { Jb, XX, cond_jump_flag } },
1504   { "jpH",              { Jb, XX, cond_jump_flag } },
1505   { "jnpH",             { Jb, XX, cond_jump_flag } },
1506   { "jlH",              { Jb, XX, cond_jump_flag } },
1507   { "jgeH",             { Jb, XX, cond_jump_flag } },
1508   { "jleH",             { Jb, XX, cond_jump_flag } },
1509   { "jgH",              { Jb, XX, cond_jump_flag } },
1510   /* 80 */
1511   { REG_TABLE (REG_80) },
1512   { REG_TABLE (REG_81) },
1513   { "(bad)",            { XX } },
1514   { REG_TABLE (REG_82) },
1515   { "testB",            { Eb, Gb } },
1516   { "testS",            { Ev, Gv } },
1517   { "xchgB",            { Eb, Gb } },
1518   { "xchgS",            { Ev, Gv } },
1519   /* 88 */
1520   { "movB",             { Eb, Gb } },
1521   { "movS",             { Ev, Gv } },
1522   { "movB",             { Gb, EbS } },
1523   { "movS",             { Gv, EvS } },
1524   { "movD",             { Sv, Sw } },
1525   { MOD_TABLE (MOD_8D) },
1526   { "movD",             { Sw, Sv } },
1527   { REG_TABLE (REG_8F) },
1528   /* 90 */
1529   { PREFIX_TABLE (PREFIX_90) },
1530   { "xchgS",            { RMeCX, eAX } },
1531   { "xchgS",            { RMeDX, eAX } },
1532   { "xchgS",            { RMeBX, eAX } },
1533   { "xchgS",            { RMeSP, eAX } },
1534   { "xchgS",            { RMeBP, eAX } },
1535   { "xchgS",            { RMeSI, eAX } },
1536   { "xchgS",            { RMeDI, eAX } },
1537   /* 98 */
1538   { "cW{t|}R",          { XX } },
1539   { "cR{t|}O",          { XX } },
1540   { X86_64_TABLE (X86_64_9A) },
1541   { "(bad)",            { XX } },       /* fwait */
1542   { "pushfT",           { XX } },
1543   { "popfT",            { XX } },
1544   { "sahf",             { XX } },
1545   { "lahf",             { XX } },
1546   /* a0 */
1547   { "mov%LB",           { AL, Ob } },
1548   { "mov%LS",           { eAX, Ov } },
1549   { "mov%LB",           { Ob, AL } },
1550   { "mov%LS",           { Ov, eAX } },
1551   { "movs{b|}",         { Ybr, Xb } },
1552   { "movs{R|}",         { Yvr, Xv } },
1553   { "cmps{b|}",         { Xb, Yb } },
1554   { "cmps{R|}",         { Xv, Yv } },
1555   /* a8 */
1556   { "testB",            { AL, Ib } },
1557   { "testS",            { eAX, Iv } },
1558   { "stosB",            { Ybr, AL } },
1559   { "stosS",            { Yvr, eAX } },
1560   { "lodsB",            { ALr, Xb } },
1561   { "lodsS",            { eAXr, Xv } },
1562   { "scasB",            { AL, Yb } },
1563   { "scasS",            { eAX, Yv } },
1564   /* b0 */
1565   { "movB",             { RMAL, Ib } },
1566   { "movB",             { RMCL, Ib } },
1567   { "movB",             { RMDL, Ib } },
1568   { "movB",             { RMBL, Ib } },
1569   { "movB",             { RMAH, Ib } },
1570   { "movB",             { RMCH, Ib } },
1571   { "movB",             { RMDH, Ib } },
1572   { "movB",             { RMBH, Ib } },
1573   /* b8 */
1574   { "mov%LV",           { RMeAX, Iv64 } },
1575   { "mov%LV",           { RMeCX, Iv64 } },
1576   { "mov%LV",           { RMeDX, Iv64 } },
1577   { "mov%LV",           { RMeBX, Iv64 } },
1578   { "mov%LV",           { RMeSP, Iv64 } },
1579   { "mov%LV",           { RMeBP, Iv64 } },
1580   { "mov%LV",           { RMeSI, Iv64 } },
1581   { "mov%LV",           { RMeDI, Iv64 } },
1582   /* c0 */
1583   { REG_TABLE (REG_C0) },
1584   { REG_TABLE (REG_C1) },
1585   { "retT",             { Iw } },
1586   { "retT",             { XX } },
1587   { X86_64_TABLE (X86_64_C4) },
1588   { X86_64_TABLE (X86_64_C5) },
1589   { REG_TABLE (REG_C6) },
1590   { REG_TABLE (REG_C7) },
1591   /* c8 */
1592   { "enterT",           { Iw, Ib } },
1593   { "leaveT",           { XX } },
1594   { "Jret{|f}P",        { Iw } },
1595   { "Jret{|f}P",        { XX } },
1596   { "int3",             { XX } },
1597   { "int",              { Ib } },
1598   { X86_64_TABLE (X86_64_CE) },
1599   { "iretP",            { XX } },
1600   /* d0 */
1601   { REG_TABLE (REG_D0) },
1602   { REG_TABLE (REG_D1) },
1603   { REG_TABLE (REG_D2) },
1604   { REG_TABLE (REG_D3) },
1605   { X86_64_TABLE (X86_64_D4) },
1606   { X86_64_TABLE (X86_64_D5) },
1607   { "(bad)",            { XX } },
1608   { "xlat",             { DSBX } },
1609   /* d8 */
1610   { FLOAT },
1611   { FLOAT },
1612   { FLOAT },
1613   { FLOAT },
1614   { FLOAT },
1615   { FLOAT },
1616   { FLOAT },
1617   { FLOAT },
1618   /* e0 */
1619   { "loopneFH",         { Jb, XX, loop_jcxz_flag } },
1620   { "loopeFH",          { Jb, XX, loop_jcxz_flag } },
1621   { "loopFH",           { Jb, XX, loop_jcxz_flag } },
1622   { "jEcxzH",           { Jb, XX, loop_jcxz_flag } },
1623   { "inB",              { AL, Ib } },
1624   { "inG",              { zAX, Ib } },
1625   { "outB",             { Ib, AL } },
1626   { "outG",             { Ib, zAX } },
1627   /* e8 */
1628   { "callT",            { Jv } },
1629   { "jmpT",             { Jv } },
1630   { X86_64_TABLE (X86_64_EA) },
1631   { "jmp",              { Jb } },
1632   { "inB",              { AL, indirDX } },
1633   { "inG",              { zAX, indirDX } },
1634   { "outB",             { indirDX, AL } },
1635   { "outG",             { indirDX, zAX } },
1636   /* f0 */
1637   { "(bad)",            { XX } },       /* lock prefix */
1638   { "icebp",            { XX } },
1639   { "(bad)",            { XX } },       /* repne */
1640   { "(bad)",            { XX } },       /* repz */
1641   { "hlt",              { XX } },
1642   { "cmc",              { XX } },
1643   { REG_TABLE (REG_F6) },
1644   { REG_TABLE (REG_F7) },
1645   /* f8 */
1646   { "clc",              { XX } },
1647   { "stc",              { XX } },
1648   { "cli",              { XX } },
1649   { "sti",              { XX } },
1650   { "cld",              { XX } },
1651   { "std",              { XX } },
1652   { REG_TABLE (REG_FE) },
1653   { REG_TABLE (REG_FF) },
1654 };
1655
1656 static const struct dis386 dis386_twobyte[] = {
1657   /* 00 */
1658   { REG_TABLE (REG_0F00 ) },
1659   { REG_TABLE (REG_0F01 ) },
1660   { "larS",             { Gv, Ew } },
1661   { "lslS",             { Gv, Ew } },
1662   { "(bad)",            { XX } },
1663   { "syscall",          { XX } },
1664   { "clts",             { XX } },
1665   { "sysretP",          { XX } },
1666   /* 08 */
1667   { "invd",             { XX } },
1668   { "wbinvd",           { XX } },
1669   { "(bad)",            { XX } },
1670   { "ud2a",             { XX } },
1671   { "(bad)",            { XX } },
1672   { REG_TABLE (REG_0F0D) },
1673   { "femms",            { XX } },
1674   { "",                 { MX, EM, OPSUF } }, /* See OP_3DNowSuffix.  */
1675   /* 10 */
1676   { PREFIX_TABLE (PREFIX_0F10) },
1677   { PREFIX_TABLE (PREFIX_0F11) },
1678   { PREFIX_TABLE (PREFIX_0F12) },
1679   { MOD_TABLE (MOD_0F13) },
1680   { "unpcklpX",         { XM, EXx } },
1681   { "unpckhpX",         { XM, EXx } },
1682   { PREFIX_TABLE (PREFIX_0F16) },
1683   { MOD_TABLE (MOD_0F17) },
1684   /* 18 */
1685   { REG_TABLE (REG_0F18) },
1686   { "nopQ",             { Ev } },
1687   { "nopQ",             { Ev } },
1688   { "nopQ",             { Ev } },
1689   { "nopQ",             { Ev } },
1690   { "nopQ",             { Ev } },
1691   { "nopQ",             { Ev } },
1692   { "nopQ",             { Ev } },
1693   /* 20 */
1694   { MOD_TABLE (MOD_0F20) },
1695   { MOD_TABLE (MOD_0F21) },
1696   { MOD_TABLE (MOD_0F22) },
1697   { MOD_TABLE (MOD_0F23) },
1698   { MOD_TABLE (MOD_0F24) },
1699   { "(bad)",            { XX } },
1700   { MOD_TABLE (MOD_0F26) },
1701   { "(bad)",            { XX } },
1702   /* 28 */
1703   { "movapX",           { XM, EXx } },
1704   { "movapX",           { EXxS, XM } },
1705   { PREFIX_TABLE (PREFIX_0F2A) },
1706   { PREFIX_TABLE (PREFIX_0F2B) },
1707   { PREFIX_TABLE (PREFIX_0F2C) },
1708   { PREFIX_TABLE (PREFIX_0F2D) },
1709   { PREFIX_TABLE (PREFIX_0F2E) },
1710   { PREFIX_TABLE (PREFIX_0F2F) },
1711   /* 30 */
1712   { "wrmsr",            { XX } },
1713   { "rdtsc",            { XX } },
1714   { "rdmsr",            { XX } },
1715   { "rdpmc",            { XX } },
1716   { "sysenter",         { XX } },
1717   { "sysexit",          { XX } },
1718   { "(bad)",            { XX } },
1719   { "getsec",           { XX } },
1720   /* 38 */
1721   { THREE_BYTE_TABLE (THREE_BYTE_0F38) },
1722   { "(bad)",            { XX } },
1723   { THREE_BYTE_TABLE (THREE_BYTE_0F3A) },
1724   { "(bad)",            { XX } },
1725   { "(bad)",            { XX } },
1726   { "(bad)",            { XX } },
1727   { "(bad)",            { XX } },
1728   { "(bad)",            { XX } },
1729   /* 40 */
1730   { "cmovoS",           { Gv, Ev } },
1731   { "cmovnoS",          { Gv, Ev } },
1732   { "cmovbS",           { Gv, Ev } },
1733   { "cmovaeS",          { Gv, Ev } },
1734   { "cmoveS",           { Gv, Ev } },
1735   { "cmovneS",          { Gv, Ev } },
1736   { "cmovbeS",          { Gv, Ev } },
1737   { "cmovaS",           { Gv, Ev } },
1738   /* 48 */
1739   { "cmovsS",           { Gv, Ev } },
1740   { "cmovnsS",          { Gv, Ev } },
1741   { "cmovpS",           { Gv, Ev } },
1742   { "cmovnpS",          { Gv, Ev } },
1743   { "cmovlS",           { Gv, Ev } },
1744   { "cmovgeS",          { Gv, Ev } },
1745   { "cmovleS",          { Gv, Ev } },
1746   { "cmovgS",           { Gv, Ev } },
1747   /* 50 */
1748   { MOD_TABLE (MOD_0F51) },
1749   { PREFIX_TABLE (PREFIX_0F51) },
1750   { PREFIX_TABLE (PREFIX_0F52) },
1751   { PREFIX_TABLE (PREFIX_0F53) },
1752   { "andpX",            { XM, EXx } },
1753   { "andnpX",           { XM, EXx } },
1754   { "orpX",             { XM, EXx } },
1755   { "xorpX",            { XM, EXx } },
1756   /* 58 */
1757   { PREFIX_TABLE (PREFIX_0F58) },
1758   { PREFIX_TABLE (PREFIX_0F59) },
1759   { PREFIX_TABLE (PREFIX_0F5A) },
1760   { PREFIX_TABLE (PREFIX_0F5B) },
1761   { PREFIX_TABLE (PREFIX_0F5C) },
1762   { PREFIX_TABLE (PREFIX_0F5D) },
1763   { PREFIX_TABLE (PREFIX_0F5E) },
1764   { PREFIX_TABLE (PREFIX_0F5F) },
1765   /* 60 */
1766   { PREFIX_TABLE (PREFIX_0F60) },
1767   { PREFIX_TABLE (PREFIX_0F61) },
1768   { PREFIX_TABLE (PREFIX_0F62) },
1769   { "packsswb",         { MX, EM } },
1770   { "pcmpgtb",          { MX, EM } },
1771   { "pcmpgtw",          { MX, EM } },
1772   { "pcmpgtd",          { MX, EM } },
1773   { "packuswb",         { MX, EM } },
1774   /* 68 */
1775   { "punpckhbw",        { MX, EM } },
1776   { "punpckhwd",        { MX, EM } },
1777   { "punpckhdq",        { MX, EM } },
1778   { "packssdw",         { MX, EM } },
1779   { PREFIX_TABLE (PREFIX_0F6C) },
1780   { PREFIX_TABLE (PREFIX_0F6D) },
1781   { "movK",             { MX, Edq } },
1782   { PREFIX_TABLE (PREFIX_0F6F) },
1783   /* 70 */
1784   { PREFIX_TABLE (PREFIX_0F70) },
1785   { REG_TABLE (REG_0F71) },
1786   { REG_TABLE (REG_0F72) },
1787   { REG_TABLE (REG_0F73) },
1788   { "pcmpeqb",          { MX, EM } },
1789   { "pcmpeqw",          { MX, EM } },
1790   { "pcmpeqd",          { MX, EM } },
1791   { "emms",             { XX } },
1792   /* 78 */
1793   { PREFIX_TABLE (PREFIX_0F78) },
1794   { PREFIX_TABLE (PREFIX_0F79) },
1795   { THREE_BYTE_TABLE (THREE_BYTE_0F7A) },
1796   { "(bad)",            { XX } },
1797   { PREFIX_TABLE (PREFIX_0F7C) },
1798   { PREFIX_TABLE (PREFIX_0F7D) },
1799   { PREFIX_TABLE (PREFIX_0F7E) },
1800   { PREFIX_TABLE (PREFIX_0F7F) },
1801   /* 80 */
1802   { "joH",              { Jv, XX, cond_jump_flag } },
1803   { "jnoH",             { Jv, XX, cond_jump_flag } },
1804   { "jbH",              { Jv, XX, cond_jump_flag } },
1805   { "jaeH",             { Jv, XX, cond_jump_flag } },
1806   { "jeH",              { Jv, XX, cond_jump_flag } },
1807   { "jneH",             { Jv, XX, cond_jump_flag } },
1808   { "jbeH",             { Jv, XX, cond_jump_flag } },
1809   { "jaH",              { Jv, XX, cond_jump_flag } },
1810   /* 88 */
1811   { "jsH",              { Jv, XX, cond_jump_flag } },
1812   { "jnsH",             { Jv, XX, cond_jump_flag } },
1813   { "jpH",              { Jv, XX, cond_jump_flag } },
1814   { "jnpH",             { Jv, XX, cond_jump_flag } },
1815   { "jlH",              { Jv, XX, cond_jump_flag } },
1816   { "jgeH",             { Jv, XX, cond_jump_flag } },
1817   { "jleH",             { Jv, XX, cond_jump_flag } },
1818   { "jgH",              { Jv, XX, cond_jump_flag } },
1819   /* 90 */
1820   { "seto",             { Eb } },
1821   { "setno",            { Eb } },
1822   { "setb",             { Eb } },
1823   { "setae",            { Eb } },
1824   { "sete",             { Eb } },
1825   { "setne",            { Eb } },
1826   { "setbe",            { Eb } },
1827   { "seta",             { Eb } },
1828   /* 98 */
1829   { "sets",             { Eb } },
1830   { "setns",            { Eb } },
1831   { "setp",             { Eb } },
1832   { "setnp",            { Eb } },
1833   { "setl",             { Eb } },
1834   { "setge",            { Eb } },
1835   { "setle",            { Eb } },
1836   { "setg",             { Eb } },
1837   /* a0 */
1838   { "pushT",            { fs } },
1839   { "popT",             { fs } },
1840   { "cpuid",            { XX } },
1841   { "btS",              { Ev, Gv } },
1842   { "shldS",            { Ev, Gv, Ib } },
1843   { "shldS",            { Ev, Gv, CL } },
1844   { REG_TABLE (REG_0FA6) },
1845   { REG_TABLE (REG_0FA7) },
1846   /* a8 */
1847   { "pushT",            { gs } },
1848   { "popT",             { gs } },
1849   { "rsm",              { XX } },
1850   { "btsS",             { Ev, Gv } },
1851   { "shrdS",            { Ev, Gv, Ib } },
1852   { "shrdS",            { Ev, Gv, CL } },
1853   { REG_TABLE (REG_0FAE) },
1854   { "imulS",            { Gv, Ev } },
1855   /* b0 */
1856   { "cmpxchgB",         { Eb, Gb } },
1857   { "cmpxchgS",         { Ev, Gv } },
1858   { MOD_TABLE (MOD_0FB2) },
1859   { "btrS",             { Ev, Gv } },
1860   { MOD_TABLE (MOD_0FB4) },
1861   { MOD_TABLE (MOD_0FB5) },
1862   { "movz{bR|x}",       { Gv, Eb } },
1863   { "movz{wR|x}",       { Gv, Ew } }, /* yes, there really is movzww ! */
1864   /* b8 */
1865   { PREFIX_TABLE (PREFIX_0FB8) },
1866   { "ud2b",             { XX } },
1867   { REG_TABLE (REG_0FBA) },
1868   { "btcS",             { Ev, Gv } },
1869   { "bsfS",             { Gv, Ev } },
1870   { PREFIX_TABLE (PREFIX_0FBD) },
1871   { "movs{bR|x}",       { Gv, Eb } },
1872   { "movs{wR|x}",       { Gv, Ew } }, /* yes, there really is movsww ! */
1873   /* c0 */
1874   { "xaddB",            { Eb, Gb } },
1875   { "xaddS",            { Ev, Gv } },
1876   { PREFIX_TABLE (PREFIX_0FC2) },
1877   { PREFIX_TABLE (PREFIX_0FC3) },
1878   { "pinsrw",           { MX, Edqw, Ib } },
1879   { "pextrw",           { Gdq, MS, Ib } },
1880   { "shufpX",           { XM, EXx, Ib } },
1881   { REG_TABLE (REG_0FC7) },
1882   /* c8 */
1883   { "bswap",            { RMeAX } },
1884   { "bswap",            { RMeCX } },
1885   { "bswap",            { RMeDX } },
1886   { "bswap",            { RMeBX } },
1887   { "bswap",            { RMeSP } },
1888   { "bswap",            { RMeBP } },
1889   { "bswap",            { RMeSI } },
1890   { "bswap",            { RMeDI } },
1891   /* d0 */
1892   { PREFIX_TABLE (PREFIX_0FD0) },
1893   { "psrlw",            { MX, EM } },
1894   { "psrld",            { MX, EM } },
1895   { "psrlq",            { MX, EM } },
1896   { "paddq",            { MX, EM } },
1897   { "pmullw",           { MX, EM } },
1898   { PREFIX_TABLE (PREFIX_0FD6) },
1899   { MOD_TABLE (MOD_0FD7) },
1900   /* d8 */
1901   { "psubusb",          { MX, EM } },
1902   { "psubusw",          { MX, EM } },
1903   { "pminub",           { MX, EM } },
1904   { "pand",             { MX, EM } },
1905   { "paddusb",          { MX, EM } },
1906   { "paddusw",          { MX, EM } },
1907   { "pmaxub",           { MX, EM } },
1908   { "pandn",            { MX, EM } },
1909   /* e0 */
1910   { "pavgb",            { MX, EM } },
1911   { "psraw",            { MX, EM } },
1912   { "psrad",            { MX, EM } },
1913   { "pavgw",            { MX, EM } },
1914   { "pmulhuw",          { MX, EM } },
1915   { "pmulhw",           { MX, EM } },
1916   { PREFIX_TABLE (PREFIX_0FE6) },
1917   { PREFIX_TABLE (PREFIX_0FE7) },
1918   /* e8 */
1919   { "psubsb",           { MX, EM } },
1920   { "psubsw",           { MX, EM } },
1921   { "pminsw",           { MX, EM } },
1922   { "por",              { MX, EM } },
1923   { "paddsb",           { MX, EM } },
1924   { "paddsw",           { MX, EM } },
1925   { "pmaxsw",           { MX, EM } },
1926   { "pxor",             { MX, EM } },
1927   /* f0 */
1928   { PREFIX_TABLE (PREFIX_0FF0) },
1929   { "psllw",            { MX, EM } },
1930   { "pslld",            { MX, EM } },
1931   { "psllq",            { MX, EM } },
1932   { "pmuludq",          { MX, EM } },
1933   { "pmaddwd",          { MX, EM } },
1934   { "psadbw",           { MX, EM } },
1935   { PREFIX_TABLE (PREFIX_0FF7) },
1936   /* f8 */
1937   { "psubb",            { MX, EM } },
1938   { "psubw",            { MX, EM } },
1939   { "psubd",            { MX, EM } },
1940   { "psubq",            { MX, EM } },
1941   { "paddb",            { MX, EM } },
1942   { "paddw",            { MX, EM } },
1943   { "paddd",            { MX, EM } },
1944   { "(bad)",            { XX } },
1945 };
1946
1947 static const unsigned char onebyte_has_modrm[256] = {
1948   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
1949   /*       -------------------------------        */
1950   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
1951   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
1952   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
1953   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
1954   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
1955   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
1956   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
1957   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
1958   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
1959   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
1960   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
1961   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
1962   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
1963   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
1964   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
1965   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
1966   /*       -------------------------------        */
1967   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
1968 };
1969
1970 static const unsigned char twobyte_has_modrm[256] = {
1971   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
1972   /*       -------------------------------        */
1973   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
1974   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
1975   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
1976   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
1977   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
1978   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
1979   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
1980   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
1981   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
1982   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
1983   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
1984   /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
1985   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
1986   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
1987   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
1988   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0  /* ff */
1989   /*       -------------------------------        */
1990   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
1991 };
1992
1993 static char obuf[100];
1994 static char *obufp;
1995 static char *mnemonicendp;
1996 static char scratchbuf[100];
1997 static unsigned char *start_codep;
1998 static unsigned char *insn_codep;
1999 static unsigned char *codep;
2000 static int last_lock_prefix;
2001 static int last_repz_prefix;
2002 static int last_repnz_prefix;
2003 static int last_data_prefix;
2004 static int last_addr_prefix;
2005 static int last_rex_prefix;
2006 static int last_seg_prefix;
2007 #define MAX_CODE_LENGTH 15
2008 /* We can up to 14 prefixes since the maximum instruction length is
2009    15bytes.  */
2010 static int all_prefixes[MAX_CODE_LENGTH - 1];
2011 static disassemble_info *the_info;
2012 static struct
2013   {
2014     int mod;
2015     int reg;
2016     int rm;
2017   }
2018 modrm;
2019 static unsigned char need_modrm;
2020 static struct
2021   {
2022     int register_specifier;
2023     int length;
2024     int prefix;
2025     int w;
2026   }
2027 vex;
2028 static unsigned char need_vex;
2029 static unsigned char need_vex_reg;
2030 static unsigned char vex_w_done;
2031
2032 struct op
2033   {
2034     const char *name;
2035     unsigned int len;
2036   };
2037
2038 /* If we are accessing mod/rm/reg without need_modrm set, then the
2039    values are stale.  Hitting this abort likely indicates that you
2040    need to update onebyte_has_modrm or twobyte_has_modrm.  */
2041 #define MODRM_CHECK  if (!need_modrm) abort ()
2042
2043 static const char **names64;
2044 static const char **names32;
2045 static const char **names16;
2046 static const char **names8;
2047 static const char **names8rex;
2048 static const char **names_seg;
2049 static const char *index64;
2050 static const char *index32;
2051 static const char **index16;
2052
2053 static const char *intel_names64[] = {
2054   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2055   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2056 };
2057 static const char *intel_names32[] = {
2058   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2059   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2060 };
2061 static const char *intel_names16[] = {
2062   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2063   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2064 };
2065 static const char *intel_names8[] = {
2066   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2067 };
2068 static const char *intel_names8rex[] = {
2069   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2070   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2071 };
2072 static const char *intel_names_seg[] = {
2073   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2074 };
2075 static const char *intel_index64 = "riz";
2076 static const char *intel_index32 = "eiz";
2077 static const char *intel_index16[] = {
2078   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2079 };
2080
2081 static const char *att_names64[] = {
2082   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2083   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2084 };
2085 static const char *att_names32[] = {
2086   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2087   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2088 };
2089 static const char *att_names16[] = {
2090   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2091   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2092 };
2093 static const char *att_names8[] = {
2094   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2095 };
2096 static const char *att_names8rex[] = {
2097   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2098   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2099 };
2100 static const char *att_names_seg[] = {
2101   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2102 };
2103 static const char *att_index64 = "%riz";
2104 static const char *att_index32 = "%eiz";
2105 static const char *att_index16[] = {
2106   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2107 };
2108
2109 static const struct dis386 reg_table[][8] = {
2110   /* REG_80 */
2111   {
2112     { "addA",   { Eb, Ib } },
2113     { "orA",    { Eb, Ib } },
2114     { "adcA",   { Eb, Ib } },
2115     { "sbbA",   { Eb, Ib } },
2116     { "andA",   { Eb, Ib } },
2117     { "subA",   { Eb, Ib } },
2118     { "xorA",   { Eb, Ib } },
2119     { "cmpA",   { Eb, Ib } },
2120   },
2121   /* REG_81 */
2122   {
2123     { "addQ",   { Ev, Iv } },
2124     { "orQ",    { Ev, Iv } },
2125     { "adcQ",   { Ev, Iv } },
2126     { "sbbQ",   { Ev, Iv } },
2127     { "andQ",   { Ev, Iv } },
2128     { "subQ",   { Ev, Iv } },
2129     { "xorQ",   { Ev, Iv } },
2130     { "cmpQ",   { Ev, Iv } },
2131   },
2132   /* REG_82 */
2133   {
2134     { "addQ",   { Ev, sIb } },
2135     { "orQ",    { Ev, sIb } },
2136     { "adcQ",   { Ev, sIb } },
2137     { "sbbQ",   { Ev, sIb } },
2138     { "andQ",   { Ev, sIb } },
2139     { "subQ",   { Ev, sIb } },
2140     { "xorQ",   { Ev, sIb } },
2141     { "cmpQ",   { Ev, sIb } },
2142   },
2143   /* REG_8F */
2144   {
2145     { "popU",   { stackEv } },
2146     { XOP_8F_TABLE (XOP_09) },
2147     { "(bad)",  { XX } },
2148     { "(bad)",  { XX } },
2149     { "(bad)",  { XX } },
2150     { XOP_8F_TABLE (XOP_09) },
2151     { "(bad)",  { XX } },
2152     { "(bad)",  { XX } },
2153   },
2154   /* REG_C0 */
2155   {
2156     { "rolA",   { Eb, Ib } },
2157     { "rorA",   { Eb, Ib } },
2158     { "rclA",   { Eb, Ib } },
2159     { "rcrA",   { Eb, Ib } },
2160     { "shlA",   { Eb, Ib } },
2161     { "shrA",   { Eb, Ib } },
2162     { "(bad)",  { XX } },
2163     { "sarA",   { Eb, Ib } },
2164   },
2165   /* REG_C1 */
2166   {
2167     { "rolQ",   { Ev, Ib } },
2168     { "rorQ",   { Ev, Ib } },
2169     { "rclQ",   { Ev, Ib } },
2170     { "rcrQ",   { Ev, Ib } },
2171     { "shlQ",   { Ev, Ib } },
2172     { "shrQ",   { Ev, Ib } },
2173     { "(bad)",  { XX } },
2174     { "sarQ",   { Ev, Ib } },
2175   },
2176   /* REG_C6 */
2177   {
2178     { "movA",   { Eb, Ib } },
2179     { "(bad)",  { XX } },
2180     { "(bad)",  { XX } },
2181     { "(bad)",  { XX } },
2182     { "(bad)",  { XX } },
2183     { "(bad)",  { XX } },
2184     { "(bad)",  { XX } },
2185     { "(bad)",  { XX } },
2186   },
2187   /* REG_C7 */
2188   {
2189     { "movQ",   { Ev, Iv } },
2190     { "(bad)",  { XX } },
2191     { "(bad)",  { XX } },
2192     { "(bad)",  { XX } },
2193     { "(bad)",  { XX } },
2194     { "(bad)",  { XX } },
2195     { "(bad)",  { XX } },
2196     { "(bad)",  { XX } },
2197   },
2198   /* REG_D0 */
2199   {
2200     { "rolA",   { Eb, I1 } },
2201     { "rorA",   { Eb, I1 } },
2202     { "rclA",   { Eb, I1 } },
2203     { "rcrA",   { Eb, I1 } },
2204     { "shlA",   { Eb, I1 } },
2205     { "shrA",   { Eb, I1 } },
2206     { "(bad)",  { XX } },
2207     { "sarA",   { Eb, I1 } },
2208   },
2209   /* REG_D1 */
2210   {
2211     { "rolQ",   { Ev, I1 } },
2212     { "rorQ",   { Ev, I1 } },
2213     { "rclQ",   { Ev, I1 } },
2214     { "rcrQ",   { Ev, I1 } },
2215     { "shlQ",   { Ev, I1 } },
2216     { "shrQ",   { Ev, I1 } },
2217     { "(bad)",  { XX } },
2218     { "sarQ",   { Ev, I1 } },
2219   },
2220   /* REG_D2 */
2221   {
2222     { "rolA",   { Eb, CL } },
2223     { "rorA",   { Eb, CL } },
2224     { "rclA",   { Eb, CL } },
2225     { "rcrA",   { Eb, CL } },
2226     { "shlA",   { Eb, CL } },
2227     { "shrA",   { Eb, CL } },
2228     { "(bad)",  { XX } },
2229     { "sarA",   { Eb, CL } },
2230   },
2231   /* REG_D3 */
2232   {
2233     { "rolQ",   { Ev, CL } },
2234     { "rorQ",   { Ev, CL } },
2235     { "rclQ",   { Ev, CL } },
2236     { "rcrQ",   { Ev, CL } },
2237     { "shlQ",   { Ev, CL } },
2238     { "shrQ",   { Ev, CL } },
2239     { "(bad)",  { XX } },
2240     { "sarQ",   { Ev, CL } },
2241   },
2242   /* REG_F6 */
2243   {
2244     { "testA",  { Eb, Ib } },
2245     { "(bad)",  { XX } },
2246     { "notA",   { Eb } },
2247     { "negA",   { Eb } },
2248     { "mulA",   { Eb } },       /* Don't print the implicit %al register,  */
2249     { "imulA",  { Eb } },       /* to distinguish these opcodes from other */
2250     { "divA",   { Eb } },       /* mul/imul opcodes.  Do the same for div  */
2251     { "idivA",  { Eb } },       /* and idiv for consistency.               */
2252   },
2253   /* REG_F7 */
2254   {
2255     { "testQ",  { Ev, Iv } },
2256     { "(bad)",  { XX } },
2257     { "notQ",   { Ev } },
2258     { "negQ",   { Ev } },
2259     { "mulQ",   { Ev } },       /* Don't print the implicit register.  */
2260     { "imulQ",  { Ev } },
2261     { "divQ",   { Ev } },
2262     { "idivQ",  { Ev } },
2263   },
2264   /* REG_FE */
2265   {
2266     { "incA",   { Eb } },
2267     { "decA",   { Eb } },
2268     { "(bad)",  { XX } },
2269     { "(bad)",  { XX } },
2270     { "(bad)",  { XX } },
2271     { "(bad)",  { XX } },
2272     { "(bad)",  { XX } },
2273     { "(bad)",  { XX } },
2274   },
2275   /* REG_FF */
2276   {
2277     { "incQ",   { Ev } },
2278     { "decQ",   { Ev } },
2279     { "callT",  { indirEv } },
2280     { "JcallT", { indirEp } },
2281     { "jmpT",   { indirEv } },
2282     { "JjmpT",  { indirEp } },
2283     { "pushU",  { stackEv } },
2284     { "(bad)",  { XX } },
2285   },
2286   /* REG_0F00 */
2287   {
2288     { "sldtD",  { Sv } },
2289     { "strD",   { Sv } },
2290     { "lldt",   { Ew } },
2291     { "ltr",    { Ew } },
2292     { "verr",   { Ew } },
2293     { "verw",   { Ew } },
2294     { "(bad)",  { XX } },
2295     { "(bad)",  { XX } },
2296   },
2297   /* REG_0F01 */
2298   {
2299     { MOD_TABLE (MOD_0F01_REG_0) },
2300     { MOD_TABLE (MOD_0F01_REG_1) },
2301     { MOD_TABLE (MOD_0F01_REG_2) },
2302     { MOD_TABLE (MOD_0F01_REG_3) },
2303     { "smswD",  { Sv } },
2304     { "(bad)",  { XX } },
2305     { "lmsw",   { Ew } },
2306     { MOD_TABLE (MOD_0F01_REG_7) },
2307   },
2308   /* REG_0F0D */
2309   {
2310     { "prefetch",       { Eb } },
2311     { "prefetchw",      { Eb } },
2312     { "(bad)",          { XX } },
2313     { "(bad)",          { XX } },
2314     { "(bad)",          { XX } },
2315     { "(bad)",          { XX } },
2316     { "(bad)",          { XX } },
2317     { "(bad)",          { XX } },
2318   },
2319   /* REG_0F18 */
2320   {
2321     { MOD_TABLE (MOD_0F18_REG_0) },
2322     { MOD_TABLE (MOD_0F18_REG_1) },
2323     { MOD_TABLE (MOD_0F18_REG_2) },
2324     { MOD_TABLE (MOD_0F18_REG_3) },
2325     { "(bad)",  { XX } },
2326     { "(bad)",  { XX } },
2327     { "(bad)",  { XX } },
2328     { "(bad)",  { XX } },
2329   },
2330   /* REG_0F71 */
2331   {
2332     { "(bad)",  { XX } },
2333     { "(bad)",  { XX } },
2334     { MOD_TABLE (MOD_0F71_REG_2) },
2335     { "(bad)",  { XX } },
2336     { MOD_TABLE (MOD_0F71_REG_4) },
2337     { "(bad)",  { XX } },
2338     { MOD_TABLE (MOD_0F71_REG_6) },
2339     { "(bad)",  { XX } },
2340   },
2341   /* REG_0F72 */
2342   {
2343     { "(bad)",  { XX } },
2344     { "(bad)",  { XX } },
2345     { MOD_TABLE (MOD_0F72_REG_2) },
2346     { "(bad)",  { XX } },
2347     { MOD_TABLE (MOD_0F72_REG_4) },
2348     { "(bad)",  { XX } },
2349     { MOD_TABLE (MOD_0F72_REG_6) },
2350     { "(bad)",  { XX } },
2351   },
2352   /* REG_0F73 */
2353   {
2354     { "(bad)",  { XX } },
2355     { "(bad)",  { XX } },
2356     { MOD_TABLE (MOD_0F73_REG_2) },
2357     { MOD_TABLE (MOD_0F73_REG_3) },
2358     { "(bad)",  { XX } },
2359     { "(bad)",  { XX } },
2360     { MOD_TABLE (MOD_0F73_REG_6) },
2361     { MOD_TABLE (MOD_0F73_REG_7) },
2362   },
2363   /* REG_0FA6 */
2364   {
2365     { "montmul",        { { OP_0f07, 0 } } },
2366     { "xsha1",          { { OP_0f07, 0 } } },
2367     { "xsha256",        { { OP_0f07, 0 } } },
2368     { "(bad)",          { { OP_0f07, 0 } } },
2369     { "(bad)",          { { OP_0f07, 0 } } },
2370     { "(bad)",          { { OP_0f07, 0 } } },
2371     { "(bad)",          { { OP_0f07, 0 } } },
2372     { "(bad)",          { { OP_0f07, 0 } } },
2373   },
2374   /* REG_0FA7 */
2375   {
2376     { "xstore-rng",     { { OP_0f07, 0 } } },
2377     { "xcrypt-ecb",     { { OP_0f07, 0 } } },
2378     { "xcrypt-cbc",     { { OP_0f07, 0 } } },
2379     { "xcrypt-ctr",     { { OP_0f07, 0 } } },
2380     { "xcrypt-cfb",     { { OP_0f07, 0 } } },
2381     { "xcrypt-ofb",     { { OP_0f07, 0 } } },
2382     { "(bad)",          { { OP_0f07, 0 } } },
2383     { "(bad)",          { { OP_0f07, 0 } } },
2384   },
2385   /* REG_0FAE */
2386   {
2387     { MOD_TABLE (MOD_0FAE_REG_0) },
2388     { MOD_TABLE (MOD_0FAE_REG_1) },
2389     { MOD_TABLE (MOD_0FAE_REG_2) },
2390     { MOD_TABLE (MOD_0FAE_REG_3) },
2391     { MOD_TABLE (MOD_0FAE_REG_4) },
2392     { MOD_TABLE (MOD_0FAE_REG_5) },
2393     { MOD_TABLE (MOD_0FAE_REG_6) },
2394     { MOD_TABLE (MOD_0FAE_REG_7) },
2395   },
2396   /* REG_0FBA */
2397   {
2398     { "(bad)",  { XX } },
2399     { "(bad)",  { XX } },
2400     { "(bad)",  { XX } },
2401     { "(bad)",  { XX } },
2402     { "btQ",    { Ev, Ib } },
2403     { "btsQ",   { Ev, Ib } },
2404     { "btrQ",   { Ev, Ib } },
2405     { "btcQ",   { Ev, Ib } },
2406   },
2407   /* REG_0FC7 */
2408   {
2409     { "(bad)",  { XX } },
2410     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } },
2411     { "(bad)",  { XX } },
2412     { "(bad)",  { XX } },
2413     { "(bad)",  { XX } },
2414     { "(bad)",  { XX } },
2415     { MOD_TABLE (MOD_0FC7_REG_6) },
2416     { MOD_TABLE (MOD_0FC7_REG_7) },
2417   },
2418   /* REG_VEX_71 */
2419   {
2420     { "(bad)",  { XX } },
2421     { "(bad)",  { XX } },
2422     { MOD_TABLE (MOD_VEX_71_REG_2) },
2423     { "(bad)",  { XX } },
2424     { MOD_TABLE (MOD_VEX_71_REG_4) },
2425     { "(bad)",  { XX } },
2426     { MOD_TABLE (MOD_VEX_71_REG_6) },
2427     { "(bad)",  { XX } },
2428   },
2429   /* REG_VEX_72 */
2430   {
2431     { "(bad)",  { XX } },
2432     { "(bad)",  { XX } },
2433     { MOD_TABLE (MOD_VEX_72_REG_2) },
2434     { "(bad)",  { XX } },
2435     { MOD_TABLE (MOD_VEX_72_REG_4) },
2436     { "(bad)",  { XX } },
2437     { MOD_TABLE (MOD_VEX_72_REG_6) },
2438     { "(bad)",  { XX } },
2439   },
2440   /* REG_VEX_73 */
2441   {
2442     { "(bad)",  { XX } },
2443     { "(bad)",  { XX } },
2444     { MOD_TABLE (MOD_VEX_73_REG_2) },
2445     { MOD_TABLE (MOD_VEX_73_REG_3) },
2446     { "(bad)",  { XX } },
2447     { "(bad)",  { XX } },
2448     { MOD_TABLE (MOD_VEX_73_REG_6) },
2449     { MOD_TABLE (MOD_VEX_73_REG_7) },
2450   },
2451   /* REG_VEX_AE */
2452   {
2453     { "(bad)",  { XX } },
2454     { "(bad)",  { XX } },
2455     { MOD_TABLE (MOD_VEX_AE_REG_2) },
2456     { MOD_TABLE (MOD_VEX_AE_REG_3) },
2457     { "(bad)",  { XX } },
2458     { "(bad)",  { XX } },
2459     { "(bad)",  { XX } },
2460     { "(bad)",  { XX } },
2461   },
2462   /* REG_XOP_LWPCB */
2463   {
2464     { "llwpcb", { { OP_LWPCB_E, 0 } } },
2465     { "slwpcb", { { OP_LWPCB_E, 0 } } },
2466     { "(bad)",  { XX } },
2467     { "(bad)",  { XX } },
2468     { "(bad)",  { XX } },
2469     { "(bad)",  { XX } },
2470     { "(bad)",  { XX } },
2471     { "(bad)",  { XX } },
2472   },
2473   /* REG_XOP_LWP */
2474   {
2475     { "lwpins", { { OP_LWP_E, 0 }, Ed, { OP_LWP_I, 0 } } },
2476     { "lwpval", { { OP_LWP_E, 0 }, Ed, { OP_LWP_I, 0 } } },
2477     { "(bad)",  { XX } },
2478     { "(bad)",  { XX } },
2479     { "(bad)",  { XX } },
2480     { "(bad)",  { XX } },
2481     { "(bad)",  { XX } },
2482     { "(bad)",  { XX } },
2483   },
2484 };
2485
2486 static const struct dis386 prefix_table[][4] = {
2487   /* PREFIX_90 */
2488   {
2489     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
2490     { "pause", { XX } },
2491     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
2492     { "(bad)", { XX } },
2493   },
2494
2495   /* PREFIX_0F10 */
2496   {
2497     { "movups", { XM, EXx } },
2498     { "movss",  { XM, EXd } },
2499     { "movupd", { XM, EXx } },
2500     { "movsd",  { XM, EXq } },
2501   },
2502
2503   /* PREFIX_0F11 */
2504   {
2505     { "movups", { EXxS, XM } },
2506     { "movss",  { EXdS, XM } },
2507     { "movupd", { EXxS, XM } },
2508     { "movsd",  { EXqS, XM } },
2509   },
2510
2511   /* PREFIX_0F12 */
2512   {
2513     { MOD_TABLE (MOD_0F12_PREFIX_0) },
2514     { "movsldup", { XM, EXx } },
2515     { "movlpd", { XM, EXq } },
2516     { "movddup", { XM, EXq } },
2517   },
2518
2519   /* PREFIX_0F16 */
2520   {
2521     { MOD_TABLE (MOD_0F16_PREFIX_0) },
2522     { "movshdup", { XM, EXx } },
2523     { "movhpd", { XM, EXq } },
2524     { "(bad)",  { XX } },
2525   },
2526
2527   /* PREFIX_0F2A */
2528   {
2529     { "cvtpi2ps", { XM, EMCq } },
2530     { "cvtsi2ss%LQ", { XM, Ev } },
2531     { "cvtpi2pd", { XM, EMCq } },
2532     { "cvtsi2sd%LQ", { XM, Ev } },
2533   },
2534
2535   /* PREFIX_0F2B */
2536   {
2537     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
2538     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
2539     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
2540     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
2541   },
2542
2543   /* PREFIX_0F2C */
2544   {
2545     { "cvttps2pi", { MXC, EXq } },
2546     { "cvttss2siY", { Gv, EXd } },
2547     { "cvttpd2pi", { MXC, EXx } },
2548     { "cvttsd2siY", { Gv, EXq } },
2549   },
2550
2551   /* PREFIX_0F2D */
2552   {
2553     { "cvtps2pi", { MXC, EXq } },
2554     { "cvtss2siY", { Gv, EXd } },
2555     { "cvtpd2pi", { MXC, EXx } },
2556     { "cvtsd2siY", { Gv, EXq } },
2557   },
2558
2559   /* PREFIX_0F2E */
2560   {
2561     { "ucomiss",{ XM, EXd } },
2562     { "(bad)",  { XX } },
2563     { "ucomisd",{ XM, EXq } },
2564     { "(bad)",  { XX } },
2565   },
2566
2567   /* PREFIX_0F2F */
2568   {
2569     { "comiss", { XM, EXd } },
2570     { "(bad)",  { XX } },
2571     { "comisd", { XM, EXq } },
2572     { "(bad)",  { XX } },
2573   },
2574
2575   /* PREFIX_0F51 */
2576   {
2577     { "sqrtps", { XM, EXx } },
2578     { "sqrtss", { XM, EXd } },
2579     { "sqrtpd", { XM, EXx } },
2580     { "sqrtsd", { XM, EXq } },
2581   },
2582
2583   /* PREFIX_0F52 */
2584   {
2585     { "rsqrtps",{ XM, EXx } },
2586     { "rsqrtss",{ XM, EXd } },
2587     { "(bad)",  { XX } },
2588     { "(bad)",  { XX } },
2589   },
2590
2591   /* PREFIX_0F53 */
2592   {
2593     { "rcpps",  { XM, EXx } },
2594     { "rcpss",  { XM, EXd } },
2595     { "(bad)",  { XX } },
2596     { "(bad)",  { XX } },
2597   },
2598
2599   /* PREFIX_0F58 */
2600   {
2601     { "addps", { XM, EXx } },
2602     { "addss", { XM, EXd } },
2603     { "addpd", { XM, EXx } },
2604     { "addsd", { XM, EXq } },
2605   },
2606
2607   /* PREFIX_0F59 */
2608   {
2609     { "mulps",  { XM, EXx } },
2610     { "mulss",  { XM, EXd } },
2611     { "mulpd",  { XM, EXx } },
2612     { "mulsd",  { XM, EXq } },
2613   },
2614
2615   /* PREFIX_0F5A */
2616   {
2617     { "cvtps2pd", { XM, EXq } },
2618     { "cvtss2sd", { XM, EXd } },
2619     { "cvtpd2ps", { XM, EXx } },
2620     { "cvtsd2ss", { XM, EXq } },
2621   },
2622
2623   /* PREFIX_0F5B */
2624   {
2625     { "cvtdq2ps", { XM, EXx } },
2626     { "cvttps2dq", { XM, EXx } },
2627     { "cvtps2dq", { XM, EXx } },
2628     { "(bad)",  { XX } },
2629   },
2630
2631   /* PREFIX_0F5C */
2632   {
2633     { "subps",  { XM, EXx } },
2634     { "subss",  { XM, EXd } },
2635     { "subpd",  { XM, EXx } },
2636     { "subsd",  { XM, EXq } },
2637   },
2638
2639   /* PREFIX_0F5D */
2640   {
2641     { "minps",  { XM, EXx } },
2642     { "minss",  { XM, EXd } },
2643     { "minpd",  { XM, EXx } },
2644     { "minsd",  { XM, EXq } },
2645   },
2646
2647   /* PREFIX_0F5E */
2648   {
2649     { "divps",  { XM, EXx } },
2650     { "divss",  { XM, EXd } },
2651     { "divpd",  { XM, EXx } },
2652     { "divsd",  { XM, EXq } },
2653   },
2654
2655   /* PREFIX_0F5F */
2656   {
2657     { "maxps",  { XM, EXx } },
2658     { "maxss",  { XM, EXd } },
2659     { "maxpd",  { XM, EXx } },
2660     { "maxsd",  { XM, EXq } },
2661   },
2662
2663   /* PREFIX_0F60 */
2664   {
2665     { "punpcklbw",{ MX, EMd } },
2666     { "(bad)",  { XX } },
2667     { "punpcklbw",{ MX, EMx } },
2668     { "(bad)",  { XX } },
2669   },
2670
2671   /* PREFIX_0F61 */
2672   {
2673     { "punpcklwd",{ MX, EMd } },
2674     { "(bad)",  { XX } },
2675     { "punpcklwd",{ MX, EMx } },
2676     { "(bad)",  { XX } },
2677   },
2678
2679   /* PREFIX_0F62 */
2680   {
2681     { "punpckldq",{ MX, EMd } },
2682     { "(bad)",  { XX } },
2683     { "punpckldq",{ MX, EMx } },
2684     { "(bad)",  { XX } },
2685   },
2686
2687   /* PREFIX_0F6C */
2688   {
2689     { "(bad)",  { XX } },
2690     { "(bad)",  { XX } },
2691     { "punpcklqdq", { XM, EXx } },
2692     { "(bad)",  { XX } },
2693   },
2694
2695   /* PREFIX_0F6D */
2696   {
2697     { "(bad)",  { XX } },
2698     { "(bad)",  { XX } },
2699     { "punpckhqdq", { XM, EXx } },
2700     { "(bad)",  { XX } },
2701   },
2702
2703   /* PREFIX_0F6F */
2704   {
2705     { "movq",   { MX, EM } },
2706     { "movdqu", { XM, EXx } },
2707     { "movdqa", { XM, EXx } },
2708     { "(bad)",  { XX } },
2709   },
2710
2711   /* PREFIX_0F70 */
2712   {
2713     { "pshufw", { MX, EM, Ib } },
2714     { "pshufhw",{ XM, EXx, Ib } },
2715     { "pshufd", { XM, EXx, Ib } },
2716     { "pshuflw",{ XM, EXx, Ib } },
2717   },
2718
2719   /* PREFIX_0F73_REG_3 */
2720   {
2721     { "(bad)",  { XX } },
2722     { "(bad)",  { XX } },
2723     { "psrldq", { XS, Ib } },
2724     { "(bad)",  { XX } },
2725   },
2726
2727   /* PREFIX_0F73_REG_7 */
2728   {
2729     { "(bad)",  { XX } },
2730     { "(bad)",  { XX } },
2731     { "pslldq", { XS, Ib } },
2732     { "(bad)",  { XX } },
2733   },
2734
2735   /* PREFIX_0F78 */
2736   {
2737     {"vmread",  { Em, Gm } },
2738     {"(bad)",   { XX } },
2739     {"extrq",   { XS, Ib, Ib } },
2740     {"insertq", { XM, XS, Ib, Ib } },
2741   },
2742
2743   /* PREFIX_0F79 */
2744   {
2745     {"vmwrite", { Gm, Em } },
2746     {"(bad)",   { XX } },
2747     {"extrq",   { XM, XS } },
2748     {"insertq", { XM, XS } },
2749   },
2750
2751   /* PREFIX_0F7C */
2752   {
2753     { "(bad)",  { XX } },
2754     { "(bad)",  { XX } },
2755     { "haddpd", { XM, EXx } },
2756     { "haddps", { XM, EXx } },
2757   },
2758
2759   /* PREFIX_0F7D */
2760   {
2761     { "(bad)",  { XX } },
2762     { "(bad)",  { XX } },
2763     { "hsubpd", { XM, EXx } },
2764     { "hsubps", { XM, EXx } },
2765   },
2766
2767   /* PREFIX_0F7E */
2768   {
2769     { "movK",   { Edq, MX } },
2770     { "movq",   { XM, EXq } },
2771     { "movK",   { Edq, XM } },
2772     { "(bad)",  { XX } },
2773   },
2774
2775   /* PREFIX_0F7F */
2776   {
2777     { "movq",   { EMS, MX } },
2778     { "movdqu", { EXxS, XM } },
2779     { "movdqa", { EXxS, XM } },
2780     { "(bad)",  { XX } },
2781   },
2782
2783   /* PREFIX_0FB8 */
2784   {
2785     { "(bad)", { XX } },
2786     { "popcntS", { Gv, Ev } },
2787     { "(bad)", { XX } },
2788     { "(bad)", { XX } },
2789   },
2790
2791   /* PREFIX_0FBD */
2792   {
2793     { "bsrS",   { Gv, Ev } },
2794     { "lzcntS", { Gv, Ev } },
2795     { "bsrS",   { Gv, Ev } },
2796     { "(bad)",  { XX } },
2797   },
2798
2799   /* PREFIX_0FC2 */
2800   {
2801     { "cmpps",  { XM, EXx, CMP } },
2802     { "cmpss",  { XM, EXd, CMP } },
2803     { "cmppd",  { XM, EXx, CMP } },
2804     { "cmpsd",  { XM, EXq, CMP } },
2805   },
2806
2807   /* PREFIX_0FC3 */
2808   {
2809     { "movntiS", { Ma, Gv } },
2810     { "(bad)",  { XX } },
2811     { "(bad)",  { XX } },
2812     { "(bad)",  { XX } },
2813   },
2814
2815   /* PREFIX_0FC7_REG_6 */
2816   {
2817     { "vmptrld",{ Mq } },
2818     { "vmxon",  { Mq } },
2819     { "vmclear",{ Mq } },
2820     { "(bad)",  { XX } },
2821   },
2822
2823   /* PREFIX_0FD0 */
2824   {
2825     { "(bad)",  { XX } },
2826     { "(bad)",  { XX } },
2827     { "addsubpd", { XM, EXx } },
2828     { "addsubps", { XM, EXx } },
2829   },
2830
2831   /* PREFIX_0FD6 */
2832   {
2833     { "(bad)",  { XX } },
2834     { "movq2dq",{ XM, MS } },
2835     { "movq",   { EXqS, XM } },
2836     { "movdq2q",{ MX, XS } },
2837   },
2838
2839   /* PREFIX_0FE6 */
2840   {
2841     { "(bad)",  { XX } },
2842     { "cvtdq2pd", { XM, EXq } },
2843     { "cvttpd2dq", { XM, EXx } },
2844     { "cvtpd2dq", { XM, EXx } },
2845   },
2846
2847   /* PREFIX_0FE7 */
2848   {
2849     { "movntq", { Mq, MX } },
2850     { "(bad)",  { XX } },
2851     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
2852     { "(bad)",  { XX } },
2853   },
2854
2855   /* PREFIX_0FF0 */
2856   {
2857     { "(bad)",  { XX } },
2858     { "(bad)",  { XX } },
2859     { "(bad)",  { XX } },
2860     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
2861   },
2862
2863   /* PREFIX_0FF7 */
2864   {
2865     { "maskmovq", { MX, MS } },
2866     { "(bad)",  { XX } },
2867     { "maskmovdqu", { XM, XS } },
2868     { "(bad)",  { XX } },
2869   },
2870
2871   /* PREFIX_0F3810 */
2872   {
2873     { "(bad)",  { XX } },
2874     { "(bad)",  { XX } },
2875     { "pblendvb", { XM, EXx, XMM0 } },
2876     { "(bad)",  { XX } },
2877   },
2878
2879   /* PREFIX_0F3814 */
2880   {
2881     { "(bad)",  { XX } },
2882     { "(bad)",  { XX } },
2883     { "blendvps", { XM, EXx, XMM0 } },
2884     { "(bad)",  { XX } },
2885   },
2886
2887   /* PREFIX_0F3815 */
2888   {
2889     { "(bad)",  { XX } },
2890     { "(bad)",  { XX } },
2891     { "blendvpd", { XM, EXx, XMM0 } },
2892     { "(bad)",  { XX } },
2893   },
2894
2895   /* PREFIX_0F3817 */
2896   {
2897     { "(bad)",  { XX } },
2898     { "(bad)",  { XX } },
2899     { "ptest",  { XM, EXx } },
2900     { "(bad)",  { XX } },
2901   },
2902
2903   /* PREFIX_0F3820 */
2904   {
2905     { "(bad)",  { XX } },
2906     { "(bad)",  { XX } },
2907     { "pmovsxbw", { XM, EXq } },
2908     { "(bad)",  { XX } },
2909   },
2910
2911   /* PREFIX_0F3821 */
2912   {
2913     { "(bad)",  { XX } },
2914     { "(bad)",  { XX } },
2915     { "pmovsxbd", { XM, EXd } },
2916     { "(bad)",  { XX } },
2917   },
2918
2919   /* PREFIX_0F3822 */
2920   {
2921     { "(bad)",  { XX } },
2922     { "(bad)",  { XX } },
2923     { "pmovsxbq", { XM, EXw } },
2924     { "(bad)",  { XX } },
2925   },
2926
2927   /* PREFIX_0F3823 */
2928   {
2929     { "(bad)",  { XX } },
2930     { "(bad)",  { XX } },
2931     { "pmovsxwd", { XM, EXq } },
2932     { "(bad)",  { XX } },
2933   },
2934
2935   /* PREFIX_0F3824 */
2936   {
2937     { "(bad)",  { XX } },
2938     { "(bad)",  { XX } },
2939     { "pmovsxwq", { XM, EXd } },
2940     { "(bad)",  { XX } },
2941   },
2942
2943   /* PREFIX_0F3825 */
2944   {
2945     { "(bad)",  { XX } },
2946     { "(bad)",  { XX } },
2947     { "pmovsxdq", { XM, EXq } },
2948     { "(bad)",  { XX } },
2949   },
2950
2951   /* PREFIX_0F3828 */
2952   {
2953     { "(bad)",  { XX } },
2954     { "(bad)",  { XX } },
2955     { "pmuldq", { XM, EXx } },
2956     { "(bad)",  { XX } },
2957   },
2958
2959   /* PREFIX_0F3829 */
2960   {
2961     { "(bad)",  { XX } },
2962     { "(bad)",  { XX } },
2963     { "pcmpeqq", { XM, EXx } },
2964     { "(bad)",  { XX } },
2965   },
2966
2967   /* PREFIX_0F382A */
2968   {
2969     { "(bad)",  { XX } },
2970     { "(bad)",  { XX } },
2971     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
2972     { "(bad)",  { XX } },
2973   },
2974
2975   /* PREFIX_0F382B */
2976   {
2977     { "(bad)",  { XX } },
2978     { "(bad)",  { XX } },
2979     { "packusdw", { XM, EXx } },
2980     { "(bad)",  { XX } },
2981   },
2982
2983   /* PREFIX_0F3830 */
2984   {
2985     { "(bad)",  { XX } },
2986     { "(bad)",  { XX } },
2987     { "pmovzxbw", { XM, EXq } },
2988     { "(bad)",  { XX } },
2989   },
2990
2991   /* PREFIX_0F3831 */
2992   {
2993     { "(bad)",  { XX } },
2994     { "(bad)",  { XX } },
2995     { "pmovzxbd", { XM, EXd } },
2996     { "(bad)",  { XX } },
2997   },
2998
2999   /* PREFIX_0F3832 */
3000   {
3001     { "(bad)",  { XX } },
3002     { "(bad)",  { XX } },
3003     { "pmovzxbq", { XM, EXw } },
3004     { "(bad)",  { XX } },
3005   },
3006
3007   /* PREFIX_0F3833 */
3008   {
3009     { "(bad)",  { XX } },
3010     { "(bad)",  { XX } },
3011     { "pmovzxwd", { XM, EXq } },
3012     { "(bad)",  { XX } },
3013   },
3014
3015   /* PREFIX_0F3834 */
3016   {
3017     { "(bad)",  { XX } },
3018     { "(bad)",  { XX } },
3019     { "pmovzxwq", { XM, EXd } },
3020     { "(bad)",  { XX } },
3021   },
3022
3023   /* PREFIX_0F3835 */
3024   {
3025     { "(bad)",  { XX } },
3026     { "(bad)",  { XX } },
3027     { "pmovzxdq", { XM, EXq } },
3028     { "(bad)",  { XX } },
3029   },
3030
3031   /* PREFIX_0F3837 */
3032   {
3033     { "(bad)",  { XX } },
3034     { "(bad)",  { XX } },
3035     { "pcmpgtq", { XM, EXx } },
3036     { "(bad)",  { XX } },
3037   },
3038
3039   /* PREFIX_0F3838 */
3040   {
3041     { "(bad)",  { XX } },
3042     { "(bad)",  { XX } },
3043     { "pminsb", { XM, EXx } },
3044     { "(bad)",  { XX } },
3045   },
3046
3047   /* PREFIX_0F3839 */
3048   {
3049     { "(bad)",  { XX } },
3050     { "(bad)",  { XX } },
3051     { "pminsd", { XM, EXx } },
3052     { "(bad)",  { XX } },
3053   },
3054
3055   /* PREFIX_0F383A */
3056   {
3057     { "(bad)",  { XX } },
3058     { "(bad)",  { XX } },
3059     { "pminuw", { XM, EXx } },
3060     { "(bad)",  { XX } },
3061   },
3062
3063   /* PREFIX_0F383B */
3064   {
3065     { "(bad)",  { XX } },
3066     { "(bad)",  { XX } },
3067     { "pminud", { XM, EXx } },
3068     { "(bad)",  { XX } },
3069   },
3070
3071   /* PREFIX_0F383C */
3072   {
3073     { "(bad)",  { XX } },
3074     { "(bad)",  { XX } },
3075     { "pmaxsb", { XM, EXx } },
3076     { "(bad)",  { XX } },
3077   },
3078
3079   /* PREFIX_0F383D */
3080   {
3081     { "(bad)",  { XX } },
3082     { "(bad)",  { XX } },
3083     { "pmaxsd", { XM, EXx } },
3084     { "(bad)",  { XX } },
3085   },
3086
3087   /* PREFIX_0F383E */
3088   {
3089     { "(bad)",  { XX } },
3090     { "(bad)",  { XX } },
3091     { "pmaxuw", { XM, EXx } },
3092     { "(bad)",  { XX } },
3093   },
3094
3095   /* PREFIX_0F383F */
3096   {
3097     { "(bad)",  { XX } },
3098     { "(bad)",  { XX } },
3099     { "pmaxud", { XM, EXx } },
3100     { "(bad)",  { XX } },
3101   },
3102
3103   /* PREFIX_0F3840 */
3104   {
3105     { "(bad)",  { XX } },
3106     { "(bad)",  { XX } },
3107     { "pmulld", { XM, EXx } },
3108     { "(bad)",  { XX } },
3109   },
3110
3111   /* PREFIX_0F3841 */
3112   {
3113     { "(bad)",  { XX } },
3114     { "(bad)",  { XX } },
3115     { "phminposuw", { XM, EXx } },
3116     { "(bad)",  { XX } },
3117   },
3118
3119   /* PREFIX_0F3880 */
3120   {
3121     { "(bad)",  { XX } },
3122     { "(bad)",  { XX } },
3123     { "invept", { Gm, Mo } },
3124     { "(bad)",  { XX } },
3125   },
3126
3127   /* PREFIX_0F3881 */
3128   {
3129     { "(bad)",  { XX } },
3130     { "(bad)",  { XX } },
3131     { "invvpid", { Gm, Mo } },
3132     { "(bad)",  { XX } },
3133   },
3134
3135   /* PREFIX_0F38DB */
3136   {
3137     { "(bad)",  { XX } },
3138     { "(bad)",  { XX } },
3139     { "aesimc", { XM, EXx } },
3140     { "(bad)",  { XX } },
3141   },
3142
3143   /* PREFIX_0F38DC */
3144   {
3145     { "(bad)",  { XX } },
3146     { "(bad)",  { XX } },
3147     { "aesenc", { XM, EXx } },
3148     { "(bad)",  { XX } },
3149   },
3150
3151   /* PREFIX_0F38DD */
3152   {
3153     { "(bad)",  { XX } },
3154     { "(bad)",  { XX } },
3155     { "aesenclast", { XM, EXx } },
3156     { "(bad)",  { XX } },
3157   },
3158
3159   /* PREFIX_0F38DE */
3160   {
3161     { "(bad)",  { XX } },
3162     { "(bad)",  { XX } },
3163     { "aesdec", { XM, EXx } },
3164     { "(bad)",  { XX } },
3165   },
3166
3167   /* PREFIX_0F38DF */
3168   {
3169     { "(bad)",  { XX } },
3170     { "(bad)",  { XX } },
3171     { "aesdeclast", { XM, EXx } },
3172     { "(bad)",  { XX } },
3173   },
3174
3175   /* PREFIX_0F38F0 */
3176   {
3177     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
3178     { "(bad)",  { XX } },
3179     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
3180     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } } },
3181   },
3182
3183   /* PREFIX_0F38F1 */
3184   {
3185     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
3186     { "(bad)",  { XX } },
3187     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
3188     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } } },
3189   },
3190
3191   /* PREFIX_0F3A08 */
3192   {
3193     { "(bad)",  { XX } },
3194     { "(bad)",  { XX } },
3195     { "roundps", { XM, EXx, Ib } },
3196     { "(bad)",  { XX } },
3197   },
3198
3199   /* PREFIX_0F3A09 */
3200   {
3201     { "(bad)",  { XX } },
3202     { "(bad)",  { XX } },
3203     { "roundpd", { XM, EXx, Ib } },
3204     { "(bad)",  { XX } },
3205   },
3206
3207   /* PREFIX_0F3A0A */
3208   {
3209     { "(bad)",  { XX } },
3210     { "(bad)",  { XX } },
3211     { "roundss", { XM, EXd, Ib } },
3212     { "(bad)",  { XX } },
3213   },
3214
3215   /* PREFIX_0F3A0B */
3216   {
3217     { "(bad)",  { XX } },
3218     { "(bad)",  { XX } },
3219     { "roundsd", { XM, EXq, Ib } },
3220     { "(bad)",  { XX } },
3221   },
3222
3223   /* PREFIX_0F3A0C */
3224   {
3225     { "(bad)",  { XX } },
3226     { "(bad)",  { XX } },
3227     { "blendps", { XM, EXx, Ib } },
3228     { "(bad)",  { XX } },
3229   },
3230
3231   /* PREFIX_0F3A0D */
3232   {
3233     { "(bad)",  { XX } },
3234     { "(bad)",  { XX } },
3235     { "blendpd", { XM, EXx, Ib } },
3236     { "(bad)",  { XX } },
3237   },
3238
3239   /* PREFIX_0F3A0E */
3240   {
3241     { "(bad)",  { XX } },
3242     { "(bad)",  { XX } },
3243     { "pblendw", { XM, EXx, Ib } },
3244     { "(bad)",  { XX } },
3245   },
3246
3247   /* PREFIX_0F3A14 */
3248   {
3249     { "(bad)",  { XX } },
3250     { "(bad)",  { XX } },
3251     { "pextrb", { Edqb, XM, Ib } },
3252     { "(bad)",  { XX } },
3253   },
3254
3255   /* PREFIX_0F3A15 */
3256   {
3257     { "(bad)",  { XX } },
3258     { "(bad)",  { XX } },
3259     { "pextrw", { Edqw, XM, Ib } },
3260     { "(bad)",  { XX } },
3261   },
3262
3263   /* PREFIX_0F3A16 */
3264   {
3265     { "(bad)",  { XX } },
3266     { "(bad)",  { XX } },
3267     { "pextrK", { Edq, XM, Ib } },
3268     { "(bad)",  { XX } },
3269   },
3270
3271   /* PREFIX_0F3A17 */
3272   {
3273     { "(bad)",  { XX } },
3274     { "(bad)",  { XX } },
3275     { "extractps", { Edqd, XM, Ib } },
3276     { "(bad)",  { XX } },
3277   },
3278
3279   /* PREFIX_0F3A20 */
3280   {
3281     { "(bad)",  { XX } },
3282     { "(bad)",  { XX } },
3283     { "pinsrb", { XM, Edqb, Ib } },
3284     { "(bad)",  { XX } },
3285   },
3286
3287   /* PREFIX_0F3A21 */
3288   {
3289     { "(bad)",  { XX } },
3290     { "(bad)",  { XX } },
3291     { "insertps", { XM, EXd, Ib } },
3292     { "(bad)",  { XX } },
3293   },
3294
3295   /* PREFIX_0F3A22 */
3296   {
3297     { "(bad)",  { XX } },
3298     { "(bad)",  { XX } },
3299     { "pinsrK", { XM, Edq, Ib } },
3300     { "(bad)",  { XX } },
3301   },
3302
3303   /* PREFIX_0F3A40 */
3304   {
3305     { "(bad)",  { XX } },
3306     { "(bad)",  { XX } },
3307     { "dpps",   { XM, EXx, Ib } },
3308     { "(bad)",  { XX } },
3309   },
3310
3311   /* PREFIX_0F3A41 */
3312   {
3313     { "(bad)",  { XX } },
3314     { "(bad)",  { XX } },
3315     { "dppd",   { XM, EXx, Ib } },
3316     { "(bad)",  { XX } },
3317   },
3318
3319   /* PREFIX_0F3A42 */
3320   {
3321     { "(bad)",  { XX } },
3322     { "(bad)",  { XX } },
3323     { "mpsadbw", { XM, EXx, Ib } },
3324     { "(bad)",  { XX } },
3325   },
3326
3327   /* PREFIX_0F3A44 */
3328   {
3329     { "(bad)",  { XX } },
3330     { "(bad)",  { XX } },
3331     { "pclmulqdq", { XM, EXx, PCLMUL } },
3332     { "(bad)",  { XX } },
3333   },
3334
3335   /* PREFIX_0F3A60 */
3336   {
3337     { "(bad)",  { XX } },
3338     { "(bad)",  { XX } },
3339     { "pcmpestrm", { XM, EXx, Ib } },
3340     { "(bad)",  { XX } },
3341   },
3342
3343   /* PREFIX_0F3A61 */
3344   {
3345     { "(bad)",  { XX } },
3346     { "(bad)",  { XX } },
3347     { "pcmpestri", { XM, EXx, Ib } },
3348     { "(bad)",  { XX } },
3349   },
3350
3351   /* PREFIX_0F3A62 */
3352   {
3353     { "(bad)",  { XX } },
3354     { "(bad)",  { XX } },
3355     { "pcmpistrm", { XM, EXx, Ib } },
3356     { "(bad)",  { XX } },
3357   },
3358
3359   /* PREFIX_0F3A63 */
3360   {
3361     { "(bad)",  { XX } },
3362     { "(bad)",  { XX } },
3363     { "pcmpistri", { XM, EXx, Ib } },
3364     { "(bad)",  { XX } },
3365   },
3366
3367   /* PREFIX_0F3ADF */
3368   {
3369     { "(bad)",  { XX } },
3370     { "(bad)",  { XX } },
3371     { "aeskeygenassist", { XM, EXx, Ib } },
3372     { "(bad)",  { XX } },
3373   },
3374
3375   /* PREFIX_VEX_10 */
3376   {
3377     { "vmovups", { XM, EXx } },
3378     { VEX_LEN_TABLE (VEX_LEN_10_P_1) },
3379     { "vmovupd", { XM, EXx } },
3380     { VEX_LEN_TABLE (VEX_LEN_10_P_3) },
3381   },
3382
3383   /* PREFIX_VEX_11 */
3384   {
3385     { "vmovups", { EXxS, XM } },
3386     { VEX_LEN_TABLE (VEX_LEN_11_P_1) },
3387     { "vmovupd", { EXxS, XM } },
3388     { VEX_LEN_TABLE (VEX_LEN_11_P_3) },
3389   },
3390
3391   /* PREFIX_VEX_12 */
3392   {
3393     { MOD_TABLE (MOD_VEX_12_PREFIX_0) },
3394     { "vmovsldup", { XM, EXx } },
3395     { VEX_LEN_TABLE (VEX_LEN_12_P_2) },
3396     { "vmovddup", { XM, EXymmq } },
3397   },
3398
3399   /* PREFIX_VEX_16 */
3400   {
3401     { MOD_TABLE (MOD_VEX_16_PREFIX_0) },
3402     { "vmovshdup", { XM, EXx } },
3403     { VEX_LEN_TABLE (VEX_LEN_16_P_2) },
3404     { "(bad)",  { XX } },
3405   },
3406
3407   /* PREFIX_VEX_2A */
3408   {
3409     { "(bad)",  { XX } },
3410     { VEX_LEN_TABLE (VEX_LEN_2A_P_1) },
3411     { "(bad)",  { XX } },
3412     { VEX_LEN_TABLE (VEX_LEN_2A_P_3) },
3413   },
3414
3415   /* PREFIX_VEX_2C */
3416   {
3417     { "(bad)",  { XX } },
3418     { VEX_LEN_TABLE (VEX_LEN_2C_P_1) },
3419     { "(bad)",  { XX } },
3420     { VEX_LEN_TABLE (VEX_LEN_2C_P_3) },
3421   },
3422
3423   /* PREFIX_VEX_2D */
3424   {
3425     { "(bad)",  { XX } },
3426     { VEX_LEN_TABLE (VEX_LEN_2D_P_1) },
3427     { "(bad)",  { XX } },
3428     { VEX_LEN_TABLE (VEX_LEN_2D_P_3) },
3429   },
3430
3431   /* PREFIX_VEX_2E */
3432   {
3433     { VEX_LEN_TABLE (VEX_LEN_2E_P_0) },
3434     { "(bad)",  { XX } },
3435     { VEX_LEN_TABLE (VEX_LEN_2E_P_2) },
3436     { "(bad)",  { XX } },
3437   },
3438
3439   /* PREFIX_VEX_2F */
3440   {
3441     { VEX_LEN_TABLE (VEX_LEN_2F_P_0) },
3442     { "(bad)",  { XX } },
3443     { VEX_LEN_TABLE (VEX_LEN_2F_P_2) },
3444     { "(bad)",  { XX } },
3445   },
3446
3447   /* PREFIX_VEX_51 */
3448   {
3449     { "vsqrtps", { XM, EXx } },
3450     { VEX_LEN_TABLE (VEX_LEN_51_P_1) },
3451     { "vsqrtpd", { XM, EXx } },
3452     { VEX_LEN_TABLE (VEX_LEN_51_P_3) },
3453   },
3454
3455   /* PREFIX_VEX_52 */
3456   {
3457     { "vrsqrtps", { XM, EXx } },
3458     { VEX_LEN_TABLE (VEX_LEN_52_P_1) },
3459     { "(bad)",  { XX } },
3460     { "(bad)",  { XX } },
3461   },
3462
3463   /* PREFIX_VEX_53 */
3464   {
3465     { "vrcpps", { XM, EXx } },
3466     { VEX_LEN_TABLE (VEX_LEN_53_P_1) },
3467     { "(bad)",  { XX } },
3468     { "(bad)",  { XX } },
3469   },
3470
3471   /* PREFIX_VEX_58 */
3472   {
3473     { "vaddps", { XM, Vex, EXx } },
3474     { VEX_LEN_TABLE (VEX_LEN_58_P_1) },
3475     { "vaddpd", { XM, Vex, EXx } },
3476     { VEX_LEN_TABLE (VEX_LEN_58_P_3) },
3477   },
3478
3479   /* PREFIX_VEX_59 */
3480   {
3481     { "vmulps", { XM, Vex, EXx } },
3482     { VEX_LEN_TABLE (VEX_LEN_59_P_1) },
3483     { "vmulpd", { XM, Vex, EXx } },
3484     { VEX_LEN_TABLE (VEX_LEN_59_P_3) },
3485   },
3486
3487   /* PREFIX_VEX_5A */
3488   {
3489     { "vcvtps2pd", { XM, EXxmmq } },
3490     { VEX_LEN_TABLE (VEX_LEN_5A_P_1) },
3491     { "vcvtpd2ps%XY", { XMM, EXx } },
3492     { VEX_LEN_TABLE (VEX_LEN_5A_P_3) },
3493   },
3494
3495   /* PREFIX_VEX_5B */
3496   {
3497     { "vcvtdq2ps", { XM, EXx } },
3498     { "vcvttps2dq", { XM, EXx } },
3499     { "vcvtps2dq", { XM, EXx } },
3500     { "(bad)",  { XX } },
3501   },
3502
3503   /* PREFIX_VEX_5C */
3504   {
3505     { "vsubps", { XM, Vex, EXx } },
3506     { VEX_LEN_TABLE (VEX_LEN_5C_P_1) },
3507     { "vsubpd", { XM, Vex, EXx } },
3508     { VEX_LEN_TABLE (VEX_LEN_5C_P_3) },
3509   },
3510
3511   /* PREFIX_VEX_5D */
3512   {
3513     { "vminps", { XM, Vex, EXx } },
3514     { VEX_LEN_TABLE (VEX_LEN_5D_P_1) },
3515     { "vminpd", { XM, Vex, EXx } },
3516     { VEX_LEN_TABLE (VEX_LEN_5D_P_3) },
3517   },
3518
3519   /* PREFIX_VEX_5E */
3520   {
3521     { "vdivps", { XM, Vex, EXx } },
3522     { VEX_LEN_TABLE (VEX_LEN_5E_P_1) },
3523     { "vdivpd", { XM, Vex, EXx } },
3524     { VEX_LEN_TABLE (VEX_LEN_5E_P_3) },
3525   },
3526
3527   /* PREFIX_VEX_5F */
3528   {
3529     { "vmaxps", { XM, Vex, EXx } },
3530     { VEX_LEN_TABLE (VEX_LEN_5F_P_1) },
3531     { "vmaxpd", { XM, Vex, EXx } },
3532     { VEX_LEN_TABLE (VEX_LEN_5F_P_3) },
3533   },
3534
3535   /* PREFIX_VEX_60 */
3536   {
3537     { "(bad)",  { XX } },
3538     { "(bad)",  { XX } },
3539     { VEX_LEN_TABLE (VEX_LEN_60_P_2) },
3540     { "(bad)",  { XX } },
3541   },
3542
3543   /* PREFIX_VEX_61 */
3544   {
3545     { "(bad)",  { XX } },
3546     { "(bad)",  { XX } },
3547     { VEX_LEN_TABLE (VEX_LEN_61_P_2) },
3548     { "(bad)",  { XX } },
3549   },
3550
3551   /* PREFIX_VEX_62 */
3552   {
3553     { "(bad)",  { XX } },
3554     { "(bad)",  { XX } },
3555     { VEX_LEN_TABLE (VEX_LEN_62_P_2) },
3556     { "(bad)",  { XX } },
3557   },
3558
3559   /* PREFIX_VEX_63 */
3560   {
3561     { "(bad)",  { XX } },
3562     { "(bad)",  { XX } },
3563     { VEX_LEN_TABLE (VEX_LEN_63_P_2) },
3564     { "(bad)",  { XX } },
3565   },
3566
3567   /* PREFIX_VEX_64 */
3568   {
3569     { "(bad)",  { XX } },
3570     { "(bad)",  { XX } },
3571     { VEX_LEN_TABLE (VEX_LEN_64_P_2) },
3572     { "(bad)",  { XX } },
3573   },
3574
3575   /* PREFIX_VEX_65 */
3576   {
3577     { "(bad)",  { XX } },
3578     { "(bad)",  { XX } },
3579     { VEX_LEN_TABLE (VEX_LEN_65_P_2) },
3580     { "(bad)",  { XX } },
3581   },
3582
3583   /* PREFIX_VEX_66 */
3584   {
3585     { "(bad)",  { XX } },
3586     { "(bad)",  { XX } },
3587     { VEX_LEN_TABLE (VEX_LEN_66_P_2) },
3588     { "(bad)",  { XX } },
3589   },
3590
3591   /* PREFIX_VEX_67 */
3592   {
3593     { "(bad)",  { XX } },
3594     { "(bad)",  { XX } },
3595     { VEX_LEN_TABLE (VEX_LEN_67_P_2) },
3596     { "(bad)",  { XX } },
3597   },
3598
3599   /* PREFIX_VEX_68 */
3600   {
3601     { "(bad)",  { XX } },
3602     { "(bad)",  { XX } },
3603     { VEX_LEN_TABLE (VEX_LEN_68_P_2) },
3604     { "(bad)",  { XX } },
3605   },
3606
3607   /* PREFIX_VEX_69 */
3608   {
3609     { "(bad)",  { XX } },
3610     { "(bad)",  { XX } },
3611     { VEX_LEN_TABLE (VEX_LEN_69_P_2) },
3612     { "(bad)",  { XX } },
3613   },
3614
3615   /* PREFIX_VEX_6A */
3616   {
3617     { "(bad)",  { XX } },
3618     { "(bad)",  { XX } },
3619     { VEX_LEN_TABLE (VEX_LEN_6A_P_2) },
3620     { "(bad)",  { XX } },
3621   },
3622
3623   /* PREFIX_VEX_6B */
3624   {
3625     { "(bad)",  { XX } },
3626     { "(bad)",  { XX } },
3627     { VEX_LEN_TABLE (VEX_LEN_6B_P_2) },
3628     { "(bad)",  { XX } },
3629   },
3630
3631   /* PREFIX_VEX_6C */
3632   {
3633     { "(bad)",  { XX } },
3634     { "(bad)",  { XX } },
3635     { VEX_LEN_TABLE (VEX_LEN_6C_P_2) },
3636     { "(bad)",  { XX } },
3637   },
3638
3639   /* PREFIX_VEX_6D */
3640   {
3641     { "(bad)",  { XX } },
3642     { "(bad)",  { XX } },
3643     { VEX_LEN_TABLE (VEX_LEN_6D_P_2) },
3644     { "(bad)",  { XX } },
3645   },
3646
3647   /* PREFIX_VEX_6E */
3648   {
3649     { "(bad)",  { XX } },
3650     { "(bad)",  { XX } },
3651     { VEX_LEN_TABLE (VEX_LEN_6E_P_2) },
3652     { "(bad)",  { XX } },
3653   },
3654
3655   /* PREFIX_VEX_6F */
3656   {
3657     { "(bad)",  { XX } },
3658     { "vmovdqu", { XM, EXx } },
3659     { "vmovdqa", { XM, EXx } },
3660     { "(bad)",  { XX } },
3661   },
3662
3663   /* PREFIX_VEX_70 */
3664   {
3665     { "(bad)",  { XX } },
3666     { VEX_LEN_TABLE (VEX_LEN_70_P_1) },
3667     { VEX_LEN_TABLE (VEX_LEN_70_P_2) },
3668     { VEX_LEN_TABLE (VEX_LEN_70_P_3) },
3669   },
3670
3671   /* PREFIX_VEX_71_REG_2 */
3672   {
3673     { "(bad)",  { XX } },
3674     { "(bad)",  { XX } },
3675     { VEX_LEN_TABLE (VEX_LEN_71_R_2_P_2) },
3676     { "(bad)",  { XX } },
3677   },
3678
3679   /* PREFIX_VEX_71_REG_4 */
3680   {
3681     { "(bad)",  { XX } },
3682     { "(bad)",  { XX } },
3683     { VEX_LEN_TABLE (VEX_LEN_71_R_4_P_2) },
3684     { "(bad)",  { XX } },
3685   },
3686
3687   /* PREFIX_VEX_71_REG_6 */
3688   {
3689     { "(bad)",  { XX } },
3690     { "(bad)",  { XX } },
3691     { VEX_LEN_TABLE (VEX_LEN_71_R_6_P_2) },
3692     { "(bad)",  { XX } },
3693   },
3694
3695   /* PREFIX_VEX_72_REG_2 */
3696   {
3697     { "(bad)",  { XX } },
3698     { "(bad)",  { XX } },
3699     { VEX_LEN_TABLE (VEX_LEN_72_R_2_P_2) },
3700     { "(bad)",  { XX } },
3701   },
3702
3703   /* PREFIX_VEX_72_REG_4 */
3704   {
3705     { "(bad)",  { XX } },
3706     { "(bad)",  { XX } },
3707     { VEX_LEN_TABLE (VEX_LEN_72_R_4_P_2) },
3708     { "(bad)",  { XX } },
3709   },
3710
3711   /* PREFIX_VEX_72_REG_6 */
3712   {
3713     { "(bad)",  { XX } },
3714     { "(bad)",  { XX } },
3715     { VEX_LEN_TABLE (VEX_LEN_72_R_6_P_2) },
3716     { "(bad)",  { XX } },
3717   },
3718
3719   /* PREFIX_VEX_73_REG_2 */
3720   {
3721     { "(bad)",  { XX } },
3722     { "(bad)",  { XX } },
3723     { VEX_LEN_TABLE (VEX_LEN_73_R_2_P_2) },
3724     { "(bad)",  { XX } },
3725   },
3726
3727   /* PREFIX_VEX_73_REG_3 */
3728   {
3729     { "(bad)",  { XX } },
3730     { "(bad)",  { XX } },
3731     { VEX_LEN_TABLE (VEX_LEN_73_R_3_P_2) },
3732     { "(bad)",  { XX } },
3733   },
3734
3735   /* PREFIX_VEX_73_REG_6 */
3736   {
3737     { "(bad)",  { XX } },
3738     { "(bad)",  { XX } },
3739     { VEX_LEN_TABLE (VEX_LEN_73_R_6_P_2) },
3740     { "(bad)",  { XX } },
3741   },
3742
3743   /* PREFIX_VEX_73_REG_7 */
3744   {
3745     { "(bad)",  { XX } },
3746     { "(bad)",  { XX } },
3747     { VEX_LEN_TABLE (VEX_LEN_73_R_7_P_2) },
3748     { "(bad)",  { XX } },
3749   },
3750
3751   /* PREFIX_VEX_74 */
3752   {
3753     { "(bad)",  { XX } },
3754     { "(bad)",  { XX } },
3755     { VEX_LEN_TABLE (VEX_LEN_74_P_2) },
3756     { "(bad)",  { XX } },
3757   },
3758
3759   /* PREFIX_VEX_75 */
3760   {
3761     { "(bad)",  { XX } },
3762     { "(bad)",  { XX } },
3763     { VEX_LEN_TABLE (VEX_LEN_75_P_2) },
3764     { "(bad)",  { XX } },
3765   },
3766
3767   /* PREFIX_VEX_76 */
3768   {
3769     { "(bad)",  { XX } },
3770     { "(bad)",  { XX } },
3771     { VEX_LEN_TABLE (VEX_LEN_76_P_2) },
3772     { "(bad)",  { XX } },
3773   },
3774
3775   /* PREFIX_VEX_77 */
3776   {
3777     { "",       { VZERO } },
3778     { "(bad)",  { XX } },
3779     { "(bad)",  { XX } },
3780     { "(bad)",  { XX } },
3781   },
3782
3783   /* PREFIX_VEX_7C */
3784   {
3785     { "(bad)",  { XX } },
3786     { "(bad)",  { XX } },
3787     { "vhaddpd", { XM, Vex, EXx } },
3788     { "vhaddps", { XM, Vex, EXx } },
3789   },
3790
3791   /* PREFIX_VEX_7D */
3792   {
3793     { "(bad)",  { XX } },
3794     { "(bad)",  { XX } },
3795     { "vhsubpd", { XM, Vex, EXx } },
3796     { "vhsubps", { XM, Vex, EXx } },
3797   },
3798
3799   /* PREFIX_VEX_7E */
3800   {
3801     { "(bad)",  { XX } },
3802     { VEX_LEN_TABLE (VEX_LEN_7E_P_1) },
3803     { VEX_LEN_TABLE (VEX_LEN_7E_P_2) },
3804     { "(bad)",  { XX } },
3805   },
3806
3807   /* PREFIX_VEX_7F */
3808   {
3809     { "(bad)",  { XX } },
3810     { "vmovdqu", { EXxS, XM } },
3811     { "vmovdqa", { EXxS, XM } },
3812     { "(bad)",  { XX } },
3813   },
3814
3815   /* PREFIX_VEX_C2 */
3816   {
3817     { "vcmpps", { XM, Vex, EXx, VCMP } },
3818     { VEX_LEN_TABLE (VEX_LEN_C2_P_1) },
3819     { "vcmppd", { XM, Vex, EXx, VCMP } },
3820     { VEX_LEN_TABLE (VEX_LEN_C2_P_3) },
3821   },
3822
3823   /* PREFIX_VEX_C4 */
3824   {
3825     { "(bad)",  { XX } },
3826     { "(bad)",  { XX } },
3827     { VEX_LEN_TABLE (VEX_LEN_C4_P_2) },
3828     { "(bad)",  { XX } },
3829   },
3830
3831   /* PREFIX_VEX_C5 */
3832   {
3833     { "(bad)",  { XX } },
3834     { "(bad)",  { XX } },
3835     { VEX_LEN_TABLE (VEX_LEN_C5_P_2) },
3836     { "(bad)",  { XX } },
3837   },
3838
3839   /* PREFIX_VEX_D0 */
3840   {
3841     { "(bad)",  { XX } },
3842     { "(bad)",  { XX } },
3843     { "vaddsubpd", { XM, Vex, EXx } },
3844     { "vaddsubps", { XM, Vex, EXx } },
3845   },
3846
3847   /* PREFIX_VEX_D1 */
3848   {
3849     { "(bad)",  { XX } },
3850     { "(bad)",  { XX } },
3851     { VEX_LEN_TABLE (VEX_LEN_D1_P_2) },
3852     { "(bad)",  { XX } },
3853   },
3854
3855   /* PREFIX_VEX_D2 */
3856   {
3857     { "(bad)",  { XX } },
3858     { "(bad)",  { XX } },
3859     { VEX_LEN_TABLE (VEX_LEN_D2_P_2) },
3860     { "(bad)",  { XX } },
3861   },
3862
3863   /* PREFIX_VEX_D3 */
3864   {
3865     { "(bad)",  { XX } },
3866     { "(bad)",  { XX } },
3867     { VEX_LEN_TABLE (VEX_LEN_D3_P_2) },
3868     { "(bad)",  { XX } },
3869   },
3870
3871   /* PREFIX_VEX_D4 */
3872   {
3873     { "(bad)",  { XX } },
3874     { "(bad)",  { XX } },
3875     { VEX_LEN_TABLE (VEX_LEN_D4_P_2) },
3876     { "(bad)",  { XX } },
3877   },
3878
3879   /* PREFIX_VEX_D5 */
3880   {
3881     { "(bad)",  { XX } },
3882     { "(bad)",  { XX } },
3883     { VEX_LEN_TABLE (VEX_LEN_D5_P_2) },
3884     { "(bad)",  { XX } },
3885   },
3886
3887   /* PREFIX_VEX_D6 */
3888   {
3889     { "(bad)",  { XX } },
3890     { "(bad)",  { XX } },
3891     { VEX_LEN_TABLE (VEX_LEN_D6_P_2) },
3892     { "(bad)",  { XX } },
3893   },
3894
3895   /* PREFIX_VEX_D7 */
3896   {
3897     { "(bad)",  { XX } },
3898     { "(bad)",  { XX } },
3899     { MOD_TABLE (MOD_VEX_D7_PREFIX_2) },
3900     { "(bad)",  { XX } },
3901   },
3902
3903   /* PREFIX_VEX_D8 */
3904   {
3905     { "(bad)",  { XX } },
3906     { "(bad)",  { XX } },
3907     { VEX_LEN_TABLE (VEX_LEN_D8_P_2) },
3908     { "(bad)",  { XX } },
3909   },
3910
3911   /* PREFIX_VEX_D9 */
3912   {
3913     { "(bad)",  { XX } },
3914     { "(bad)",  { XX } },
3915     { VEX_LEN_TABLE (VEX_LEN_D9_P_2) },
3916     { "(bad)",  { XX } },
3917   },
3918
3919   /* PREFIX_VEX_DA */
3920   {
3921     { "(bad)",  { XX } },
3922     { "(bad)",  { XX } },
3923     { VEX_LEN_TABLE (VEX_LEN_DA_P_2) },
3924     { "(bad)",  { XX } },
3925   },
3926
3927   /* PREFIX_VEX_DB */
3928   {
3929     { "(bad)",  { XX } },
3930     { "(bad)",  { XX } },
3931     { VEX_LEN_TABLE (VEX_LEN_DB_P_2) },
3932     { "(bad)",  { XX } },
3933   },
3934
3935   /* PREFIX_VEX_DC */
3936   {
3937     { "(bad)",  { XX } },
3938     { "(bad)",  { XX } },
3939     { VEX_LEN_TABLE (VEX_LEN_DC_P_2) },
3940     { "(bad)",  { XX } },
3941   },
3942
3943   /* PREFIX_VEX_DD */
3944   {
3945     { "(bad)",  { XX } },
3946     { "(bad)",  { XX } },
3947     { VEX_LEN_TABLE (VEX_LEN_DD_P_2) },
3948     { "(bad)",  { XX } },
3949   },
3950
3951   /* PREFIX_VEX_DE */
3952   {
3953     { "(bad)",  { XX } },
3954     { "(bad)",  { XX } },
3955     { VEX_LEN_TABLE (VEX_LEN_DE_P_2) },
3956     { "(bad)",  { XX } },
3957   },
3958
3959   /* PREFIX_VEX_DF */
3960   {
3961     { "(bad)",  { XX } },
3962     { "(bad)",  { XX } },
3963     { VEX_LEN_TABLE (VEX_LEN_DF_P_2) },
3964     { "(bad)",  { XX } },
3965   },
3966
3967   /* PREFIX_VEX_E0 */
3968   {
3969     { "(bad)",  { XX } },
3970     { "(bad)",  { XX } },
3971     { VEX_LEN_TABLE (VEX_LEN_E0_P_2) },
3972     { "(bad)",  { XX } },
3973   },
3974
3975   /* PREFIX_VEX_E1 */
3976   {
3977     { "(bad)",  { XX } },
3978     { "(bad)",  { XX } },
3979     { VEX_LEN_TABLE (VEX_LEN_E1_P_2) },
3980     { "(bad)",  { XX } },
3981   },
3982
3983   /* PREFIX_VEX_E2 */
3984   {
3985     { "(bad)",  { XX } },
3986     { "(bad)",  { XX } },
3987     { VEX_LEN_TABLE (VEX_LEN_E2_P_2) },
3988     { "(bad)",  { XX } },
3989   },
3990
3991   /* PREFIX_VEX_E3 */
3992   {
3993     { "(bad)",  { XX } },
3994     { "(bad)",  { XX } },
3995     { VEX_LEN_TABLE (VEX_LEN_E3_P_2) },
3996     { "(bad)",  { XX } },
3997   },
3998
3999   /* PREFIX_VEX_E4 */
4000   {
4001     { "(bad)",  { XX } },
4002     { "(bad)",  { XX } },
4003     { VEX_LEN_TABLE (VEX_LEN_E4_P_2) },
4004     { "(bad)",  { XX } },
4005   },
4006
4007   /* PREFIX_VEX_E5 */
4008   {
4009     { "(bad)",  { XX } },
4010     { "(bad)",  { XX } },
4011     { VEX_LEN_TABLE (VEX_LEN_E5_P_2) },
4012     { "(bad)",  { XX } },
4013   },
4014
4015   /* PREFIX_VEX_E6 */
4016   {
4017     { "(bad)",  { XX } },
4018     { "vcvtdq2pd", { XM, EXxmmq } },
4019     { "vcvttpd2dq%XY", { XMM, EXx } },
4020     { "vcvtpd2dq%XY", { XMM, EXx } },
4021   },
4022
4023   /* PREFIX_VEX_E7 */
4024   {
4025     { "(bad)",  { XX } },
4026     { "(bad)",  { XX } },
4027     { MOD_TABLE (MOD_VEX_E7_PREFIX_2) },
4028     { "(bad)",  { XX } },
4029   },
4030
4031   /* PREFIX_VEX_E8 */
4032   {
4033     { "(bad)",  { XX } },
4034     { "(bad)",  { XX } },
4035     { VEX_LEN_TABLE (VEX_LEN_E8_P_2) },
4036     { "(bad)",  { XX } },
4037   },
4038
4039   /* PREFIX_VEX_E9 */
4040   {
4041     { "(bad)",  { XX } },
4042     { "(bad)",  { XX } },
4043     { VEX_LEN_TABLE (VEX_LEN_E9_P_2) },
4044     { "(bad)",  { XX } },
4045   },
4046
4047   /* PREFIX_VEX_EA */
4048   {
4049     { "(bad)",  { XX } },
4050     { "(bad)",  { XX } },
4051     { VEX_LEN_TABLE (VEX_LEN_EA_P_2) },
4052     { "(bad)",  { XX } },
4053   },
4054
4055   /* PREFIX_VEX_EB */
4056   {
4057     { "(bad)",  { XX } },
4058     { "(bad)",  { XX } },
4059     { VEX_LEN_TABLE (VEX_LEN_EB_P_2) },
4060     { "(bad)",  { XX } },
4061   },
4062
4063   /* PREFIX_VEX_EC */
4064   {
4065     { "(bad)",  { XX } },
4066     { "(bad)",  { XX } },
4067     { VEX_LEN_TABLE (VEX_LEN_EC_P_2) },
4068     { "(bad)",  { XX } },
4069   },
4070
4071   /* PREFIX_VEX_ED */
4072   {
4073     { "(bad)",  { XX } },
4074     { "(bad)",  { XX } },
4075     { VEX_LEN_TABLE (VEX_LEN_ED_P_2) },
4076     { "(bad)",  { XX } },
4077   },
4078
4079   /* PREFIX_VEX_EE */
4080   {
4081     { "(bad)",  { XX } },
4082     { "(bad)",  { XX } },
4083     { VEX_LEN_TABLE (VEX_LEN_EE_P_2) },
4084     { "(bad)",  { XX } },
4085   },
4086
4087   /* PREFIX_VEX_EF */
4088   {
4089     { "(bad)",  { XX } },
4090     { "(bad)",  { XX } },
4091     { VEX_LEN_TABLE (VEX_LEN_EF_P_2) },
4092     { "(bad)",  { XX } },
4093   },
4094
4095   /* PREFIX_VEX_F0 */
4096   {
4097     { "(bad)",  { XX } },
4098     { "(bad)",  { XX } },
4099     { "(bad)",  { XX } },
4100     { MOD_TABLE (MOD_VEX_F0_PREFIX_3) },
4101   },
4102
4103   /* PREFIX_VEX_F1 */
4104   {
4105     { "(bad)",  { XX } },
4106     { "(bad)",  { XX } },
4107     { VEX_LEN_TABLE (VEX_LEN_F1_P_2) },
4108     { "(bad)",  { XX } },
4109   },
4110
4111   /* PREFIX_VEX_F2 */
4112   {
4113     { "(bad)",  { XX } },
4114     { "(bad)",  { XX } },
4115     { VEX_LEN_TABLE (VEX_LEN_F2_P_2) },
4116     { "(bad)",  { XX } },
4117   },
4118
4119   /* PREFIX_VEX_F3 */
4120   {
4121     { "(bad)",  { XX } },
4122     { "(bad)",  { XX } },
4123     { VEX_LEN_TABLE (VEX_LEN_F3_P_2) },
4124     { "(bad)",  { XX } },
4125   },
4126
4127   /* PREFIX_VEX_F4 */
4128   {
4129     { "(bad)",  { XX } },
4130     { "(bad)",  { XX } },
4131     { VEX_LEN_TABLE (VEX_LEN_F4_P_2) },
4132     { "(bad)",  { XX } },
4133   },
4134
4135   /* PREFIX_VEX_F5 */
4136   {
4137     { "(bad)",  { XX } },
4138     { "(bad)",  { XX } },
4139     { VEX_LEN_TABLE (VEX_LEN_F5_P_2) },
4140     { "(bad)",  { XX } },
4141   },
4142
4143   /* PREFIX_VEX_F6 */
4144   {
4145     { "(bad)",  { XX } },
4146     { "(bad)",  { XX } },
4147     { VEX_LEN_TABLE (VEX_LEN_F6_P_2) },
4148     { "(bad)",  { XX } },
4149   },
4150
4151   /* PREFIX_VEX_F7 */
4152   {
4153     { "(bad)",  { XX } },
4154     { "(bad)",  { XX } },
4155     { VEX_LEN_TABLE (VEX_LEN_F7_P_2) },
4156     { "(bad)",  { XX } },
4157   },
4158
4159   /* PREFIX_VEX_F8 */
4160   {
4161     { "(bad)",  { XX } },
4162     { "(bad)",  { XX } },
4163     { VEX_LEN_TABLE (VEX_LEN_F8_P_2) },
4164     { "(bad)",  { XX } },
4165   },
4166
4167   /* PREFIX_VEX_F9 */
4168   {
4169     { "(bad)",  { XX } },
4170     { "(bad)",  { XX } },
4171     { VEX_LEN_TABLE (VEX_LEN_F9_P_2) },
4172     { "(bad)",  { XX } },
4173   },
4174
4175   /* PREFIX_VEX_FA */
4176   {
4177     { "(bad)",  { XX } },
4178     { "(bad)",  { XX } },
4179     { VEX_LEN_TABLE (VEX_LEN_FA_P_2) },
4180     { "(bad)",  { XX } },
4181   },
4182
4183   /* PREFIX_VEX_FB */
4184   {
4185     { "(bad)",  { XX } },
4186     { "(bad)",  { XX } },
4187     { VEX_LEN_TABLE (VEX_LEN_FB_P_2) },
4188     { "(bad)",  { XX } },
4189   },
4190
4191   /* PREFIX_VEX_FC */
4192   {
4193     { "(bad)",  { XX } },
4194     { "(bad)",  { XX } },
4195     { VEX_LEN_TABLE (VEX_LEN_FC_P_2) },
4196     { "(bad)",  { XX } },
4197   },
4198
4199   /* PREFIX_VEX_FD */
4200   {
4201     { "(bad)",  { XX } },
4202     { "(bad)",  { XX } },
4203     { VEX_LEN_TABLE (VEX_LEN_FD_P_2) },
4204     { "(bad)",  { XX } },
4205   },
4206
4207   /* PREFIX_VEX_FE */
4208   {
4209     { "(bad)",  { XX } },
4210     { "(bad)",  { XX } },
4211     { VEX_LEN_TABLE (VEX_LEN_FE_P_2) },
4212     { "(bad)",  { XX } },
4213   },
4214
4215   /* PREFIX_VEX_3800 */
4216   {
4217     { "(bad)",  { XX } },
4218     { "(bad)",  { XX } },
4219     { VEX_LEN_TABLE (VEX_LEN_3800_P_2) },
4220     { "(bad)",  { XX } },
4221   },
4222
4223   /* PREFIX_VEX_3801 */
4224   {
4225     { "(bad)",  { XX } },
4226     { "(bad)",  { XX } },
4227     { VEX_LEN_TABLE (VEX_LEN_3801_P_2) },
4228     { "(bad)",  { XX } },
4229   },
4230
4231   /* PREFIX_VEX_3802 */
4232   {
4233     { "(bad)",  { XX } },
4234     { "(bad)",  { XX } },
4235     { VEX_LEN_TABLE (VEX_LEN_3802_P_2) },
4236     { "(bad)",  { XX } },
4237   },
4238
4239   /* PREFIX_VEX_3803 */
4240   {
4241     { "(bad)",  { XX } },
4242     { "(bad)",  { XX } },
4243     { VEX_LEN_TABLE (VEX_LEN_3803_P_2) },
4244     { "(bad)",  { XX } },
4245   },
4246
4247   /* PREFIX_VEX_3804 */
4248   {
4249     { "(bad)",  { XX } },
4250     { "(bad)",  { XX } },
4251     { VEX_LEN_TABLE (VEX_LEN_3804_P_2) },
4252     { "(bad)",  { XX } },
4253   },
4254
4255   /* PREFIX_VEX_3805 */
4256   {
4257     { "(bad)",  { XX } },
4258     { "(bad)",  { XX } },
4259     { VEX_LEN_TABLE (VEX_LEN_3805_P_2) },
4260     { "(bad)",  { XX } },
4261   },
4262
4263   /* PREFIX_VEX_3806 */
4264   {
4265     { "(bad)",  { XX } },
4266     { "(bad)",  { XX } },
4267     { VEX_LEN_TABLE (VEX_LEN_3806_P_2) },
4268     { "(bad)",  { XX } },
4269   },
4270
4271   /* PREFIX_VEX_3807 */
4272   {
4273     { "(bad)",  { XX } },
4274     { "(bad)",  { XX } },
4275     { VEX_LEN_TABLE (VEX_LEN_3807_P_2) },
4276     { "(bad)",  { XX } },
4277   },
4278
4279   /* PREFIX_VEX_3808 */
4280   {
4281     { "(bad)",  { XX } },
4282     { "(bad)",  { XX } },
4283     { VEX_LEN_TABLE (VEX_LEN_3808_P_2) },
4284     { "(bad)",  { XX } },
4285   },
4286
4287   /* PREFIX_VEX_3809 */
4288   {
4289     { "(bad)",  { XX } },
4290     { "(bad)",  { XX } },
4291     { VEX_LEN_TABLE (VEX_LEN_3809_P_2) },
4292     { "(bad)",  { XX } },
4293   },
4294
4295   /* PREFIX_VEX_380A */
4296   {
4297     { "(bad)",  { XX } },
4298     { "(bad)",  { XX } },
4299     { VEX_LEN_TABLE (VEX_LEN_380A_P_2) },
4300     { "(bad)",  { XX } },
4301   },
4302
4303   /* PREFIX_VEX_380B */
4304   {
4305     { "(bad)",  { XX } },
4306     { "(bad)",  { XX } },
4307     { VEX_LEN_TABLE (VEX_LEN_380B_P_2) },
4308     { "(bad)",  { XX } },
4309   },
4310
4311   /* PREFIX_VEX_380C */
4312   {
4313     { "(bad)",  { XX } },
4314     { "(bad)",  { XX } },
4315     { "vpermilps", { XM, Vex, EXx } },
4316     { "(bad)",  { XX } },
4317   },
4318
4319   /* PREFIX_VEX_380D */
4320   {
4321     { "(bad)",  { XX } },
4322     { "(bad)",  { XX } },
4323     { "vpermilpd", { XM, Vex, EXx } },
4324     { "(bad)",  { XX } },
4325   },
4326
4327   /* PREFIX_VEX_380E */
4328   {
4329     { "(bad)",  { XX } },
4330     { "(bad)",  { XX } },
4331     { "vtestps", { XM, EXx } },
4332     { "(bad)",  { XX } },
4333   },
4334
4335   /* PREFIX_VEX_380F */
4336   {
4337     { "(bad)",  { XX } },
4338     { "(bad)",  { XX } },
4339     { "vtestpd", { XM, EXx } },
4340     { "(bad)",  { XX } },
4341   },
4342
4343   /* PREFIX_VEX_3817 */
4344   {
4345     { "(bad)",  { XX } },
4346     { "(bad)",  { XX } },
4347     { "vptest", { XM, EXx } },
4348     { "(bad)",  { XX } },
4349   },
4350
4351   /* PREFIX_VEX_3818 */
4352   {
4353     { "(bad)",  { XX } },
4354     { "(bad)",  { XX } },
4355     { MOD_TABLE (MOD_VEX_3818_PREFIX_2) },
4356     { "(bad)",  { XX } },
4357   },
4358
4359   /* PREFIX_VEX_3819 */
4360   {
4361     { "(bad)",  { XX } },
4362     { "(bad)",  { XX } },
4363     { MOD_TABLE (MOD_VEX_3819_PREFIX_2) },
4364     { "(bad)",  { XX } },
4365   },
4366
4367   /* PREFIX_VEX_381A */
4368   {
4369     { "(bad)",  { XX } },
4370     { "(bad)",  { XX } },
4371     { MOD_TABLE (MOD_VEX_381A_PREFIX_2) },
4372     { "(bad)",  { XX } },
4373   },
4374
4375   /* PREFIX_VEX_381C */
4376   {
4377     { "(bad)",  { XX } },
4378     { "(bad)",  { XX } },
4379     { VEX_LEN_TABLE (VEX_LEN_381C_P_2) },
4380     { "(bad)",  { XX } },
4381   },
4382
4383   /* PREFIX_VEX_381D */
4384   {
4385     { "(bad)",  { XX } },
4386     { "(bad)",  { XX } },
4387     { VEX_LEN_TABLE (VEX_LEN_381D_P_2) },
4388     { "(bad)",  { XX } },
4389   },
4390
4391   /* PREFIX_VEX_381E */
4392   {
4393     { "(bad)",  { XX } },
4394     { "(bad)",  { XX } },
4395     { VEX_LEN_TABLE (VEX_LEN_381E_P_2) },
4396     { "(bad)",  { XX } },
4397   },
4398
4399   /* PREFIX_VEX_3820 */
4400   {
4401     { "(bad)",  { XX } },
4402     { "(bad)",  { XX } },
4403     { VEX_LEN_TABLE (VEX_LEN_3820_P_2) },
4404     { "(bad)",  { XX } },
4405   },
4406
4407   /* PREFIX_VEX_3821 */
4408   {
4409     { "(bad)",  { XX } },
4410     { "(bad)",  { XX } },
4411     { VEX_LEN_TABLE (VEX_LEN_3821_P_2) },
4412     { "(bad)",  { XX } },
4413   },
4414
4415   /* PREFIX_VEX_3822 */
4416   {
4417     { "(bad)",  { XX } },
4418     { "(bad)",  { XX } },
4419     { VEX_LEN_TABLE (VEX_LEN_3822_P_2) },
4420     { "(bad)",  { XX } },
4421   },
4422
4423   /* PREFIX_VEX_3823 */
4424   {
4425     { "(bad)",  { XX } },
4426     { "(bad)",  { XX } },
4427     { VEX_LEN_TABLE (VEX_LEN_3823_P_2) },
4428     { "(bad)",  { XX } },
4429   },
4430
4431   /* PREFIX_VEX_3824 */
4432   {
4433     { "(bad)",  { XX } },
4434     { "(bad)",  { XX } },
4435     { VEX_LEN_TABLE (VEX_LEN_3824_P_2) },
4436     { "(bad)",  { XX } },
4437   },
4438
4439   /* PREFIX_VEX_3825 */
4440   {
4441     { "(bad)",  { XX } },
4442     { "(bad)",  { XX } },
4443     { VEX_LEN_TABLE (VEX_LEN_3825_P_2) },
4444     { "(bad)",  { XX } },
4445   },
4446
4447   /* PREFIX_VEX_3828 */
4448   {
4449     { "(bad)",  { XX } },
4450     { "(bad)",  { XX } },
4451     { VEX_LEN_TABLE (VEX_LEN_3828_P_2) },
4452     { "(bad)",  { XX } },
4453   },
4454
4455   /* PREFIX_VEX_3829 */
4456   {
4457     { "(bad)",  { XX } },
4458     { "(bad)",  { XX } },
4459     { VEX_LEN_TABLE (VEX_LEN_3829_P_2) },
4460     { "(bad)",  { XX } },
4461   },
4462
4463   /* PREFIX_VEX_382A */
4464   {
4465     { "(bad)",  { XX } },
4466     { "(bad)",  { XX } },
4467     { MOD_TABLE (MOD_VEX_382A_PREFIX_2) },
4468     { "(bad)",  { XX } },
4469   },
4470
4471   /* PREFIX_VEX_382B */
4472   {
4473     { "(bad)",  { XX } },
4474     { "(bad)",  { XX } },
4475     { VEX_LEN_TABLE (VEX_LEN_382B_P_2) },
4476     { "(bad)",  { XX } },
4477   },
4478
4479   /* PREFIX_VEX_382C */
4480   {
4481     { "(bad)",  { XX } },
4482     { "(bad)",  { XX } },
4483      { MOD_TABLE (MOD_VEX_382C_PREFIX_2) },
4484     { "(bad)",  { XX } },
4485   },
4486
4487   /* PREFIX_VEX_382D */
4488   {
4489     { "(bad)",  { XX } },
4490     { "(bad)",  { XX } },
4491      { MOD_TABLE (MOD_VEX_382D_PREFIX_2) },
4492     { "(bad)",  { XX } },
4493   },
4494
4495   /* PREFIX_VEX_382E */
4496   {
4497     { "(bad)",  { XX } },
4498     { "(bad)",  { XX } },
4499      { MOD_TABLE (MOD_VEX_382E_PREFIX_2) },
4500     { "(bad)",  { XX } },
4501   },
4502
4503   /* PREFIX_VEX_382F */
4504   {
4505     { "(bad)",  { XX } },
4506     { "(bad)",  { XX } },
4507      { MOD_TABLE (MOD_VEX_382F_PREFIX_2) },
4508     { "(bad)",  { XX } },
4509   },
4510
4511   /* PREFIX_VEX_3830 */
4512   {
4513     { "(bad)",  { XX } },
4514     { "(bad)",  { XX } },
4515     { VEX_LEN_TABLE (VEX_LEN_3830_P_2) },
4516     { "(bad)",  { XX } },
4517   },
4518
4519   /* PREFIX_VEX_3831 */
4520   {
4521     { "(bad)",  { XX } },
4522     { "(bad)",  { XX } },
4523     { VEX_LEN_TABLE (VEX_LEN_3831_P_2) },
4524     { "(bad)",  { XX } },
4525   },
4526
4527   /* PREFIX_VEX_3832 */
4528   {
4529     { "(bad)",  { XX } },
4530     { "(bad)",  { XX } },
4531     { VEX_LEN_TABLE (VEX_LEN_3832_P_2) },
4532     { "(bad)",  { XX } },
4533   },
4534
4535   /* PREFIX_VEX_3833 */
4536   {
4537     { "(bad)",  { XX } },
4538     { "(bad)",  { XX } },
4539     { VEX_LEN_TABLE (VEX_LEN_3833_P_2) },
4540     { "(bad)",  { XX } },
4541   },
4542
4543   /* PREFIX_VEX_3834 */
4544   {
4545     { "(bad)",  { XX } },
4546     { "(bad)",  { XX } },
4547     { VEX_LEN_TABLE (VEX_LEN_3834_P_2) },
4548     { "(bad)",  { XX } },
4549   },
4550
4551   /* PREFIX_VEX_3835 */
4552   {
4553     { "(bad)",  { XX } },
4554     { "(bad)",  { XX } },
4555     { VEX_LEN_TABLE (VEX_LEN_3835_P_2) },
4556     { "(bad)",  { XX } },
4557   },
4558
4559   /* PREFIX_VEX_3837 */
4560   {
4561     { "(bad)",  { XX } },
4562     { "(bad)",  { XX } },
4563     { VEX_LEN_TABLE (VEX_LEN_3837_P_2) },
4564     { "(bad)",  { XX } },
4565   },
4566
4567   /* PREFIX_VEX_3838 */
4568   {
4569     { "(bad)",  { XX } },
4570     { "(bad)",  { XX } },
4571     { VEX_LEN_TABLE (VEX_LEN_3838_P_2) },
4572     { "(bad)",  { XX } },
4573   },
4574
4575   /* PREFIX_VEX_3839 */
4576   {
4577     { "(bad)",  { XX } },
4578     { "(bad)",  { XX } },
4579     { VEX_LEN_TABLE (VEX_LEN_3839_P_2) },
4580     { "(bad)",  { XX } },
4581   },
4582
4583   /* PREFIX_VEX_383A */
4584   {
4585     { "(bad)",  { XX } },
4586     { "(bad)",  { XX } },
4587     { VEX_LEN_TABLE (VEX_LEN_383A_P_2) },
4588     { "(bad)",  { XX } },
4589   },
4590
4591   /* PREFIX_VEX_383B */
4592   {
4593     { "(bad)",  { XX } },
4594     { "(bad)",  { XX } },
4595     { VEX_LEN_TABLE (VEX_LEN_383B_P_2) },
4596     { "(bad)",  { XX } },
4597   },
4598
4599   /* PREFIX_VEX_383C */
4600   {
4601     { "(bad)",  { XX } },
4602     { "(bad)",  { XX } },
4603     { VEX_LEN_TABLE (VEX_LEN_383C_P_2) },
4604     { "(bad)",  { XX } },
4605   },
4606
4607   /* PREFIX_VEX_383D */
4608   {
4609     { "(bad)",  { XX } },
4610     { "(bad)",  { XX } },
4611     { VEX_LEN_TABLE (VEX_LEN_383D_P_2) },
4612     { "(bad)",  { XX } },
4613   },
4614
4615   /* PREFIX_VEX_383E */
4616   {
4617     { "(bad)",  { XX } },
4618     { "(bad)",  { XX } },
4619     { VEX_LEN_TABLE (VEX_LEN_383E_P_2) },
4620     { "(bad)",  { XX } },
4621   },
4622
4623   /* PREFIX_VEX_383F */
4624   {
4625     { "(bad)",  { XX } },
4626     { "(bad)",  { XX } },
4627     { VEX_LEN_TABLE (VEX_LEN_383F_P_2) },
4628     { "(bad)",  { XX } },
4629   },
4630
4631   /* PREFIX_VEX_3840 */
4632   {
4633     { "(bad)",  { XX } },
4634     { "(bad)",  { XX } },
4635     { VEX_LEN_TABLE (VEX_LEN_3840_P_2) },
4636     { "(bad)",  { XX } },
4637   },
4638
4639   /* PREFIX_VEX_3841 */
4640   {
4641     { "(bad)",  { XX } },
4642     { "(bad)",  { XX } },
4643     { VEX_LEN_TABLE (VEX_LEN_3841_P_2) },
4644     { "(bad)",  { XX } },
4645   },
4646
4647   /* PREFIX_VEX_3896 */
4648   {
4649     { "(bad)",  { XX } },
4650     { "(bad)",  { XX } },
4651     { "vfmaddsub132p%XW", { XM, Vex, EXx } },
4652     { "(bad)",  { XX } },
4653   },
4654
4655   /* PREFIX_VEX_3897 */
4656   {
4657     { "(bad)",  { XX } },
4658     { "(bad)",  { XX } },
4659     { "vfmsubadd132p%XW", { XM, Vex, EXx } },
4660     { "(bad)",  { XX } },
4661   },
4662
4663   /* PREFIX_VEX_3898 */
4664   {
4665     { "(bad)",  { XX } },
4666     { "(bad)",  { XX } },
4667     { "vfmadd132p%XW", { XM, Vex, EXx } },
4668     { "(bad)",  { XX } },
4669   },
4670
4671   /* PREFIX_VEX_3899 */
4672   {
4673     { "(bad)",  { XX } },
4674     { "(bad)",  { XX } },
4675     { "vfmadd132s%XW", { XM, Vex, EXVexWdq } },
4676     { "(bad)",  { XX } },
4677   },
4678
4679   /* PREFIX_VEX_389A */
4680   {
4681     { "(bad)",  { XX } },
4682     { "(bad)",  { XX } },
4683     { "vfmsub132p%XW", { XM, Vex, EXx } },
4684     { "(bad)",  { XX } },
4685   },
4686
4687   /* PREFIX_VEX_389B */
4688   {
4689     { "(bad)",  { XX } },
4690     { "(bad)",  { XX } },
4691     { "vfmsub132s%XW", { XM, Vex, EXVexWdq } },
4692     { "(bad)",  { XX } },
4693   },
4694
4695   /* PREFIX_VEX_389C */
4696   {
4697     { "(bad)",  { XX } },
4698     { "(bad)",  { XX } },
4699     { "vfnmadd132p%XW", { XM, Vex, EXx } },
4700     { "(bad)",  { XX } },
4701   },
4702
4703   /* PREFIX_VEX_389D */
4704   {
4705     { "(bad)",  { XX } },
4706     { "(bad)",  { XX } },
4707     { "vfnmadd132s%XW", { XM, Vex, EXVexWdq } },
4708     { "(bad)",  { XX } },
4709   },
4710
4711   /* PREFIX_VEX_389E */
4712   {
4713     { "(bad)",  { XX } },
4714     { "(bad)",  { XX } },
4715     { "vfnmsub132p%XW", { XM, Vex, EXx } },
4716     { "(bad)",  { XX } },
4717   },
4718
4719   /* PREFIX_VEX_389F */
4720   {
4721     { "(bad)",  { XX } },
4722     { "(bad)",  { XX } },
4723     { "vfnmsub132s%XW", { XM, Vex, EXVexWdq } },
4724     { "(bad)",  { XX } },
4725   },
4726
4727   /* PREFIX_VEX_38A6 */
4728   {
4729     { "(bad)",  { XX } },
4730     { "(bad)",  { XX } },
4731     { "vfmaddsub213p%XW", { XM, Vex, EXx } },
4732     { "(bad)",  { XX } },
4733   },
4734
4735   /* PREFIX_VEX_38A7 */
4736   {
4737     { "(bad)",  { XX } },
4738     { "(bad)",  { XX } },
4739     { "vfmsubadd213p%XW", { XM, Vex, EXx } },
4740     { "(bad)",  { XX } },
4741   },
4742
4743   /* PREFIX_VEX_38A8 */
4744   {
4745     { "(bad)",  { XX } },
4746     { "(bad)",  { XX } },
4747     { "vfmadd213p%XW", { XM, Vex, EXx } },
4748     { "(bad)",  { XX } },
4749   },
4750
4751   /* PREFIX_VEX_38A9 */
4752   {
4753     { "(bad)",  { XX } },
4754     { "(bad)",  { XX } },
4755     { "vfmadd213s%XW", { XM, Vex, EXVexWdq } },
4756     { "(bad)",  { XX } },
4757   },
4758
4759   /* PREFIX_VEX_38AA */
4760   {
4761     { "(bad)",  { XX } },
4762     { "(bad)",  { XX } },
4763     { "vfmsub213p%XW", { XM, Vex, EXx } },
4764     { "(bad)",  { XX } },
4765   },
4766
4767   /* PREFIX_VEX_38AB */
4768   {
4769     { "(bad)",  { XX } },
4770     { "(bad)",  { XX } },
4771     { "vfmsub213s%XW", { XM, Vex, EXVexWdq } },
4772     { "(bad)",  { XX } },
4773   },
4774
4775   /* PREFIX_VEX_38AC */
4776   {
4777     { "(bad)",  { XX } },
4778     { "(bad)",  { XX } },
4779     { "vfnmadd213p%XW", { XM, Vex, EXx } },
4780     { "(bad)",  { XX } },
4781   },
4782
4783   /* PREFIX_VEX_38AD */
4784   {
4785     { "(bad)",  { XX } },
4786     { "(bad)",  { XX } },
4787     { "vfnmadd213s%XW", { XM, Vex, EXVexWdq } },
4788     { "(bad)",  { XX } },
4789   },
4790
4791   /* PREFIX_VEX_38AE */
4792   {
4793     { "(bad)",  { XX } },
4794     { "(bad)",  { XX } },
4795     { "vfnmsub213p%XW", { XM, Vex, EXx } },
4796     { "(bad)",  { XX } },
4797   },
4798
4799   /* PREFIX_VEX_38AF */
4800   {
4801     { "(bad)",  { XX } },
4802     { "(bad)",  { XX } },
4803     { "vfnmsub213s%XW", { XM, Vex, EXVexWdq } },
4804     { "(bad)",  { XX } },
4805   },
4806
4807   /* PREFIX_VEX_38B6 */
4808   {
4809     { "(bad)",  { XX } },
4810     { "(bad)",  { XX } },
4811     { "vfmaddsub231p%XW", { XM, Vex, EXx } },
4812     { "(bad)",  { XX } },
4813   },
4814
4815   /* PREFIX_VEX_38B7 */
4816   {
4817     { "(bad)",  { XX } },
4818     { "(bad)",  { XX } },
4819     { "vfmsubadd231p%XW", { XM, Vex, EXx } },
4820     { "(bad)",  { XX } },
4821   },
4822
4823   /* PREFIX_VEX_38B8 */
4824   {
4825     { "(bad)",  { XX } },
4826     { "(bad)",  { XX } },
4827     { "vfmadd231p%XW", { XM, Vex, EXx } },
4828     { "(bad)",  { XX } },
4829   },
4830
4831   /* PREFIX_VEX_38B9 */
4832   {
4833     { "(bad)",  { XX } },
4834     { "(bad)",  { XX } },
4835     { "vfmadd231s%XW", { XM, Vex, EXVexWdq } },
4836     { "(bad)",  { XX } },
4837   },
4838
4839   /* PREFIX_VEX_38BA */
4840   {
4841     { "(bad)",  { XX } },
4842     { "(bad)",  { XX } },
4843     { "vfmsub231p%XW", { XM, Vex, EXx } },
4844     { "(bad)",  { XX } },
4845   },
4846
4847   /* PREFIX_VEX_38BB */
4848   {
4849     { "(bad)",  { XX } },
4850     { "(bad)",  { XX } },
4851     { "vfmsub231s%XW", { XM, Vex, EXVexWdq } },
4852     { "(bad)",  { XX } },
4853   },
4854
4855   /* PREFIX_VEX_38BC */
4856   {
4857     { "(bad)",  { XX } },
4858     { "(bad)",  { XX } },
4859     { "vfnmadd231p%XW", { XM, Vex, EXx } },
4860     { "(bad)",  { XX } },
4861   },
4862
4863   /* PREFIX_VEX_38BD */
4864   {
4865     { "(bad)",  { XX } },
4866     { "(bad)",  { XX } },
4867     { "vfnmadd231s%XW", { XM, Vex, EXVexWdq } },
4868     { "(bad)",  { XX } },
4869   },
4870
4871   /* PREFIX_VEX_38BE */
4872   {
4873     { "(bad)",  { XX } },
4874     { "(bad)",  { XX } },
4875     { "vfnmsub231p%XW", { XM, Vex, EXx } },
4876     { "(bad)",  { XX } },
4877   },
4878
4879   /* PREFIX_VEX_38BF */
4880   {
4881     { "(bad)",  { XX } },
4882     { "(bad)",  { XX } },
4883     { "vfnmsub231s%XW", { XM, Vex, EXVexWdq } },
4884     { "(bad)",  { XX } },
4885   },
4886
4887   /* PREFIX_VEX_38DB */
4888   {
4889     { "(bad)",  { XX } },
4890     { "(bad)",  { XX } },
4891     { VEX_LEN_TABLE (VEX_LEN_38DB_P_2) },
4892     { "(bad)",  { XX } },
4893   },
4894
4895   /* PREFIX_VEX_38DC */
4896   {
4897     { "(bad)",  { XX } },
4898     { "(bad)",  { XX } },
4899     { VEX_LEN_TABLE (VEX_LEN_38DC_P_2) },
4900     { "(bad)",  { XX } },
4901   },
4902
4903   /* PREFIX_VEX_38DD */
4904   {
4905     { "(bad)",  { XX } },
4906     { "(bad)",  { XX } },
4907     { VEX_LEN_TABLE (VEX_LEN_38DD_P_2) },
4908     { "(bad)",  { XX } },
4909   },
4910
4911   /* PREFIX_VEX_38DE */
4912   {
4913     { "(bad)",  { XX } },
4914     { "(bad)",  { XX } },
4915     { VEX_LEN_TABLE (VEX_LEN_38DE_P_2) },
4916     { "(bad)",  { XX } },
4917   },
4918
4919   /* PREFIX_VEX_38DF */
4920   {
4921     { "(bad)",  { XX } },
4922     { "(bad)",  { XX } },
4923     { VEX_LEN_TABLE (VEX_LEN_38DF_P_2) },
4924     { "(bad)",  { XX } },
4925   },
4926
4927   /* PREFIX_VEX_3A04 */
4928   {
4929     { "(bad)",  { XX } },
4930     { "(bad)",  { XX } },
4931     { "vpermilps", { XM, EXx, Ib } },
4932     { "(bad)",  { XX } },
4933   },
4934
4935   /* PREFIX_VEX_3A05 */
4936   {
4937     { "(bad)",  { XX } },
4938     { "(bad)",  { XX } },
4939     { "vpermilpd", { XM, EXx, Ib } },
4940     { "(bad)",  { XX } },
4941   },
4942
4943   /* PREFIX_VEX_3A06 */
4944   {
4945     { "(bad)",  { XX } },
4946     { "(bad)",  { XX } },
4947     { VEX_LEN_TABLE (VEX_LEN_3A06_P_2) },
4948     { "(bad)",  { XX } },
4949   },
4950
4951   /* PREFIX_VEX_3A08 */
4952   {
4953     { "(bad)",  { XX } },
4954     { "(bad)",  { XX } },
4955     { "vroundps", { XM, EXx, Ib } },
4956     { "(bad)",  { XX } },
4957   },
4958
4959   /* PREFIX_VEX_3A09 */
4960   {
4961     { "(bad)",  { XX } },
4962     { "(bad)",  { XX } },
4963     { "vroundpd", { XM, EXx, Ib } },
4964     { "(bad)",  { XX } },
4965   },
4966
4967   /* PREFIX_VEX_3A0A */
4968   {
4969     { "(bad)",  { XX } },
4970     { "(bad)",  { XX } },
4971     { VEX_LEN_TABLE (VEX_LEN_3A0A_P_2) },
4972     { "(bad)",  { XX } },
4973   },
4974
4975   /* PREFIX_VEX_3A0B */
4976   {
4977     { "(bad)",  { XX } },
4978     { "(bad)",  { XX } },
4979     { VEX_LEN_TABLE (VEX_LEN_3A0B_P_2) },
4980     { "(bad)",  { XX } },
4981   },
4982
4983   /* PREFIX_VEX_3A0C */
4984   {
4985     { "(bad)",  { XX } },
4986     { "(bad)",  { XX } },
4987     { "vblendps", { XM, Vex, EXx, Ib } },
4988     { "(bad)",  { XX } },
4989   },
4990
4991   /* PREFIX_VEX_3A0D */
4992   {
4993     { "(bad)",  { XX } },
4994     { "(bad)",  { XX } },
4995     { "vblendpd", { XM, Vex, EXx, Ib } },
4996     { "(bad)",  { XX } },
4997   },
4998
4999   /* PREFIX_VEX_3A0E */
5000   {
5001     { "(bad)",  { XX } },
5002     { "(bad)",  { XX } },
5003     { VEX_LEN_TABLE (VEX_LEN_3A0E_P_2) },
5004     { "(bad)",  { XX } },
5005   },
5006
5007   /* PREFIX_VEX_3A0F */
5008   {
5009     { "(bad)",  { XX } },
5010     { "(bad)",  { XX } },
5011     { VEX_LEN_TABLE (VEX_LEN_3A0F_P_2) },
5012     { "(bad)",  { XX } },
5013   },
5014
5015   /* PREFIX_VEX_3A14 */
5016   {
5017     { "(bad)",  { XX } },
5018     { "(bad)",  { XX } },
5019     { VEX_LEN_TABLE (VEX_LEN_3A14_P_2) },
5020     { "(bad)",  { XX } },
5021   },
5022
5023   /* PREFIX_VEX_3A15 */
5024   {
5025     { "(bad)",  { XX } },
5026     { "(bad)",  { XX } },
5027     { VEX_LEN_TABLE (VEX_LEN_3A15_P_2) },
5028     { "(bad)",  { XX } },
5029   },
5030
5031   /* PREFIX_VEX_3A16 */
5032   {
5033     { "(bad)",  { XX } },
5034     { "(bad)",  { XX } },
5035     { VEX_LEN_TABLE (VEX_LEN_3A16_P_2) },
5036     { "(bad)",  { XX } },
5037   },
5038
5039   /* PREFIX_VEX_3A17 */
5040   {
5041     { "(bad)",  { XX } },
5042     { "(bad)",  { XX } },
5043     { VEX_LEN_TABLE (VEX_LEN_3A17_P_2) },
5044     { "(bad)",  { XX } },
5045   },
5046
5047   /* PREFIX_VEX_3A18 */
5048   {
5049     { "(bad)",  { XX } },
5050     { "(bad)",  { XX } },
5051     { VEX_LEN_TABLE (VEX_LEN_3A18_P_2) },
5052     { "(bad)",  { XX } },
5053   },
5054
5055   /* PREFIX_VEX_3A19 */
5056   {
5057     { "(bad)",  { XX } },
5058     { "(bad)",  { XX } },
5059     { VEX_LEN_TABLE (VEX_LEN_3A19_P_2) },
5060     { "(bad)",  { XX } },
5061   },
5062
5063   /* PREFIX_VEX_3A20 */
5064   {
5065     { "(bad)",  { XX } },
5066     { "(bad)",  { XX } },
5067     { VEX_LEN_TABLE (VEX_LEN_3A20_P_2) },
5068     { "(bad)",  { XX } },
5069   },
5070
5071   /* PREFIX_VEX_3A21 */
5072   {
5073     { "(bad)",  { XX } },
5074     { "(bad)",  { XX } },
5075     { VEX_LEN_TABLE (VEX_LEN_3A21_P_2) },
5076     { "(bad)",  { XX } },
5077   },
5078
5079   /* PREFIX_VEX_3A22 */
5080   {
5081     { "(bad)",  { XX } },
5082     { "(bad)",  { XX } },
5083     { VEX_LEN_TABLE (VEX_LEN_3A22_P_2) },
5084     { "(bad)",  { XX } },
5085   },
5086
5087   /* PREFIX_VEX_3A40 */
5088   {
5089     { "(bad)",  { XX } },
5090     { "(bad)",  { XX } },
5091     { "vdpps",  { XM, Vex, EXx, Ib } },
5092     { "(bad)",  { XX } },
5093   },
5094
5095   /* PREFIX_VEX_3A41 */
5096   {
5097     { "(bad)",  { XX } },
5098     { "(bad)",  { XX } },
5099     { VEX_LEN_TABLE (VEX_LEN_3A41_P_2) },
5100     { "(bad)",  { XX } },
5101   },
5102
5103   /* PREFIX_VEX_3A42 */
5104   {
5105     { "(bad)",  { XX } },
5106     { "(bad)",  { XX } },
5107     { VEX_LEN_TABLE (VEX_LEN_3A42_P_2) },
5108     { "(bad)",  { XX } },
5109   },
5110
5111   /* PREFIX_VEX_3A44 */
5112   {
5113     { "(bad)",  { XX } },
5114     { "(bad)",  { XX } },
5115     { VEX_LEN_TABLE (VEX_LEN_3A44_P_2) },
5116     { "(bad)",  { XX } },
5117   },
5118
5119   /* PREFIX_VEX_3A4A */
5120   {
5121     { "(bad)",  { XX } },
5122     { "(bad)",  { XX } },
5123     { "vblendvps", { XM, Vex, EXx, XMVexI4 } },
5124     { "(bad)",  { XX } },
5125   },
5126
5127   /* PREFIX_VEX_3A4B */
5128   {
5129     { "(bad)",  { XX } },
5130     { "(bad)",  { XX } },
5131     { "vblendvpd", { XM, Vex, EXx, XMVexI4 } },
5132     { "(bad)",  { XX } },
5133   },
5134
5135   /* PREFIX_VEX_3A4C */
5136   {
5137     { "(bad)",  { XX } },
5138     { "(bad)",  { XX } },
5139     { VEX_LEN_TABLE (VEX_LEN_3A4C_P_2) },
5140     { "(bad)",  { XX } },
5141   },
5142
5143   /* PREFIX_VEX_3A5C */
5144   {
5145     { "(bad)",  { XX } },
5146     { "(bad)",  { XX } },
5147     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5148     { "(bad)",  { XX } },
5149   },
5150
5151   /* PREFIX_VEX_3A5D */
5152   {
5153     { "(bad)",  { XX } },
5154     { "(bad)",  { XX } },
5155     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5156     { "(bad)",  { XX } },
5157   },
5158
5159   /* PREFIX_VEX_3A5E */
5160   {
5161     { "(bad)",  { XX } },
5162     { "(bad)",  { XX } },
5163     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5164     { "(bad)",  { XX } },
5165   },
5166
5167   /* PREFIX_VEX_3A5F */
5168   {
5169     { "(bad)",  { XX } },
5170     { "(bad)",  { XX } },
5171     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5172     { "(bad)",  { XX } },
5173   },
5174
5175   /* PREFIX_VEX_3A60 */
5176   {
5177     { "(bad)",  { XX } },
5178     { "(bad)",  { XX } },
5179     { VEX_LEN_TABLE (VEX_LEN_3A60_P_2) },
5180     { "(bad)",  { XX } },
5181   },
5182
5183   /* PREFIX_VEX_3A61 */
5184   {
5185     { "(bad)",  { XX } },
5186     { "(bad)",  { XX } },
5187     { VEX_LEN_TABLE (VEX_LEN_3A61_P_2) },
5188     { "(bad)",  { XX } },
5189   },
5190
5191   /* PREFIX_VEX_3A62 */
5192   {
5193     { "(bad)",  { XX } },
5194     { "(bad)",  { XX } },
5195     { VEX_LEN_TABLE (VEX_LEN_3A62_P_2) },
5196     { "(bad)",  { XX } },
5197   },
5198
5199   /* PREFIX_VEX_3A63 */
5200   {
5201     { "(bad)",  { XX } },
5202     { "(bad)",  { XX } },
5203     { VEX_LEN_TABLE (VEX_LEN_3A63_P_2) },
5204     { "(bad)",  { XX } },
5205   },
5206
5207   /* PREFIX_VEX_3A68 */
5208   {
5209     { "(bad)",  { XX } },
5210     { "(bad)",  { XX } },
5211     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5212     { "(bad)",  { XX } },
5213   },
5214
5215   /* PREFIX_VEX_3A69 */
5216   {
5217     { "(bad)",  { XX } },
5218     { "(bad)",  { XX } },
5219     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5220     { "(bad)",  { XX } },
5221   },
5222
5223   /* PREFIX_VEX_3A6A */
5224   {
5225     { "(bad)",  { XX } },
5226     { "(bad)",  { XX } },
5227     { VEX_LEN_TABLE (VEX_LEN_3A6A_P_2) },
5228     { "(bad)",  { XX } },
5229   },
5230
5231   /* PREFIX_VEX_3A6B */
5232   {
5233     { "(bad)",  { XX } },
5234     { "(bad)",  { XX } },
5235     { VEX_LEN_TABLE (VEX_LEN_3A6B_P_2) },
5236     { "(bad)",  { XX } },
5237   },
5238
5239   /* PREFIX_VEX_3A6C */
5240   {
5241     { "(bad)",  { XX } },
5242     { "(bad)",  { XX } },
5243     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5244     { "(bad)",  { XX } },
5245   },
5246
5247   /* PREFIX_VEX_3A6D */
5248   {
5249     { "(bad)",  { XX } },
5250     { "(bad)",  { XX } },
5251     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5252     { "(bad)",  { XX } },
5253   },
5254
5255   /* PREFIX_VEX_3A6E */
5256   {
5257     { "(bad)",  { XX } },
5258     { "(bad)",  { XX } },
5259     { VEX_LEN_TABLE (VEX_LEN_3A6E_P_2) },
5260     { "(bad)",  { XX } },
5261   },
5262
5263   /* PREFIX_VEX_3A6F */
5264   {
5265     { "(bad)",  { XX } },
5266     { "(bad)",  { XX } },
5267     { VEX_LEN_TABLE (VEX_LEN_3A6F_P_2) },
5268     { "(bad)",  { XX } },
5269   },
5270
5271   /* PREFIX_VEX_3A78 */
5272   {
5273     { "(bad)",  { XX } },
5274     { "(bad)",  { XX } },
5275     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5276     { "(bad)",  { XX } },
5277   },
5278
5279   /* PREFIX_VEX_3A79 */
5280   {
5281     { "(bad)",  { XX } },
5282     { "(bad)",  { XX } },
5283     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5284     { "(bad)",  { XX } },
5285   },
5286
5287   /* PREFIX_VEX_3A7A */
5288   {
5289     { "(bad)",  { XX } },
5290     { "(bad)",  { XX } },
5291     { VEX_LEN_TABLE (VEX_LEN_3A7A_P_2) },
5292     { "(bad)",  { XX } },
5293   },
5294
5295   /* PREFIX_VEX_3A7B */
5296   {
5297     { "(bad)",  { XX } },
5298     { "(bad)",  { XX } },
5299     { VEX_LEN_TABLE (VEX_LEN_3A7B_P_2) },
5300     { "(bad)",  { XX } },
5301   },
5302
5303   /* PREFIX_VEX_3A7C */
5304   {
5305     { "(bad)",  { XX } },
5306     { "(bad)",  { XX } },
5307     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5308     { "(bad)",  { XX } },
5309   },
5310
5311   /* PREFIX_VEX_3A7D */
5312   {
5313     { "(bad)",  { XX } },
5314     { "(bad)",  { XX } },
5315     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5316     { "(bad)",  { XX } },
5317   },
5318
5319   /* PREFIX_VEX_3A7E */
5320   {
5321     { "(bad)",  { XX } },
5322     { "(bad)",  { XX } },
5323     { VEX_LEN_TABLE (VEX_LEN_3A7E_P_2) },
5324     { "(bad)",  { XX } },
5325   },
5326
5327   /* PREFIX_VEX_3A7F */
5328   {
5329     { "(bad)",  { XX } },
5330     { "(bad)",  { XX } },
5331     { VEX_LEN_TABLE (VEX_LEN_3A7F_P_2) },
5332     { "(bad)",  { XX } },
5333   },
5334
5335   /* PREFIX_VEX_3ADF */
5336   {
5337     { "(bad)",  { XX } },
5338     { "(bad)",  { XX } },
5339     { VEX_LEN_TABLE (VEX_LEN_3ADF_P_2) },
5340     { "(bad)",  { XX } },
5341   },
5342 };
5343
5344 static const struct dis386 x86_64_table[][2] = {
5345   /* X86_64_06 */
5346   {
5347     { "push{T|}", { es } },
5348     { "(bad)", { XX } },
5349   },
5350
5351   /* X86_64_07 */
5352   {
5353     { "pop{T|}", { es } },
5354     { "(bad)", { XX } },
5355   },
5356
5357   /* X86_64_0D */
5358   {
5359     { "push{T|}", { cs } },
5360     { "(bad)", { XX } },
5361   },
5362
5363   /* X86_64_16 */
5364   {
5365     { "push{T|}", { ss } },
5366     { "(bad)", { XX } },
5367   },
5368
5369   /* X86_64_17 */
5370   {
5371     { "pop{T|}", { ss } },
5372     { "(bad)", { XX } },
5373   },
5374
5375   /* X86_64_1E */
5376   {
5377     { "push{T|}", { ds } },
5378     { "(bad)", { XX } },
5379   },
5380
5381   /* X86_64_1F */
5382   {
5383     { "pop{T|}", { ds } },
5384     { "(bad)", { XX } },
5385   },
5386
5387   /* X86_64_27 */
5388   {
5389     { "daa", { XX } },
5390     { "(bad)", { XX } },
5391   },
5392
5393   /* X86_64_2F */
5394   {
5395     { "das", { XX } },
5396     { "(bad)", { XX } },
5397   },
5398
5399   /* X86_64_37 */
5400   {
5401     { "aaa", { XX } },
5402     { "(bad)", { XX } },
5403   },
5404
5405   /* X86_64_3F */
5406   {
5407     { "aas", { XX } },
5408     { "(bad)", { XX } },
5409   },
5410
5411   /* X86_64_60 */
5412   {
5413     { "pusha{P|}", { XX } },
5414     { "(bad)", { XX } },
5415   },
5416
5417   /* X86_64_61 */
5418   {
5419     { "popa{P|}", { XX } },
5420     { "(bad)", { XX } },
5421   },
5422
5423   /* X86_64_62 */
5424   {
5425     { MOD_TABLE (MOD_62_32BIT) },
5426     { "(bad)", { XX } },
5427   },
5428
5429   /* X86_64_63 */
5430   {
5431     { "arpl", { Ew, Gw } },
5432     { "movs{lq|xd}", { Gv, Ed } },
5433   },
5434
5435   /* X86_64_6D */
5436   {
5437     { "ins{R|}", { Yzr, indirDX } },
5438     { "ins{G|}", { Yzr, indirDX } },
5439   },
5440
5441   /* X86_64_6F */
5442   {
5443     { "outs{R|}", { indirDXr, Xz } },
5444     { "outs{G|}", { indirDXr, Xz } },
5445   },
5446
5447   /* X86_64_9A */
5448   {
5449     { "Jcall{T|}", { Ap } },
5450     { "(bad)", { XX } },
5451   },
5452
5453   /* X86_64_C4 */
5454   {
5455     { MOD_TABLE (MOD_C4_32BIT) },
5456     { VEX_C4_TABLE (VEX_0F) },
5457   },
5458
5459   /* X86_64_C5 */
5460   {
5461     { MOD_TABLE (MOD_C5_32BIT) },
5462     { VEX_C5_TABLE (VEX_0F) },
5463   },
5464
5465   /* X86_64_CE */
5466   {
5467     { "into", { XX } },
5468     { "(bad)", { XX } },
5469   },
5470
5471   /* X86_64_D4 */
5472   {
5473     { "aam", { sIb } },
5474     { "(bad)", { XX } },
5475   },
5476
5477   /* X86_64_D5 */
5478   {
5479     { "aad", { sIb } },
5480     { "(bad)", { XX } },
5481   },
5482
5483   /* X86_64_EA */
5484   {
5485     { "Jjmp{T|}", { Ap } },
5486     { "(bad)", { XX } },
5487   },
5488
5489   /* X86_64_0F01_REG_0 */
5490   {
5491     { "sgdt{Q|IQ}", { M } },
5492     { "sgdt", { M } },
5493   },
5494
5495   /* X86_64_0F01_REG_1 */
5496   {
5497     { "sidt{Q|IQ}", { M } },
5498     { "sidt", { M } },
5499   },
5500
5501   /* X86_64_0F01_REG_2 */
5502   {
5503     { "lgdt{Q|Q}", { M } },
5504     { "lgdt", { M } },
5505   },
5506
5507   /* X86_64_0F01_REG_3 */
5508   {
5509     { "lidt{Q|Q}", { M } },
5510     { "lidt", { M } },
5511   },
5512 };
5513
5514 static const struct dis386 three_byte_table[][256] = {
5515
5516   /* THREE_BYTE_0F38 */
5517   {
5518     /* 00 */
5519     { "pshufb",         { MX, EM } },
5520     { "phaddw",         { MX, EM } },
5521     { "phaddd",         { MX, EM } },
5522     { "phaddsw",        { MX, EM } },
5523     { "pmaddubsw",      { MX, EM } },
5524     { "phsubw",         { MX, EM } },
5525     { "phsubd",         { MX, EM } },
5526     { "phsubsw",        { MX, EM } },
5527     /* 08 */
5528     { "psignb",         { MX, EM } },
5529     { "psignw",         { MX, EM } },
5530     { "psignd",         { MX, EM } },
5531     { "pmulhrsw",       { MX, EM } },
5532     { "(bad)",          { XX } },
5533     { "(bad)",          { XX } },
5534     { "(bad)",          { XX } },
5535     { "(bad)",          { XX } },
5536     /* 10 */
5537     { PREFIX_TABLE (PREFIX_0F3810) },
5538     { "(bad)",          { XX } },
5539     { "(bad)",          { XX } },
5540     { "(bad)",          { XX } },
5541     { PREFIX_TABLE (PREFIX_0F3814) },
5542     { PREFIX_TABLE (PREFIX_0F3815) },
5543     { "(bad)",          { XX } },
5544     { PREFIX_TABLE (PREFIX_0F3817) },
5545     /* 18 */
5546     { "(bad)",          { XX } },
5547     { "(bad)",          { XX } },
5548     { "(bad)",          { XX } },
5549     { "(bad)",          { XX } },
5550     { "pabsb",          { MX, EM } },
5551     { "pabsw",          { MX, EM } },
5552     { "pabsd",          { MX, EM } },
5553     { "(bad)",          { XX } },
5554     /* 20 */
5555     { PREFIX_TABLE (PREFIX_0F3820) },
5556     { PREFIX_TABLE (PREFIX_0F3821) },
5557     { PREFIX_TABLE (PREFIX_0F3822) },
5558     { PREFIX_TABLE (PREFIX_0F3823) },
5559     { PREFIX_TABLE (PREFIX_0F3824) },
5560     { PREFIX_TABLE (PREFIX_0F3825) },
5561     { "(bad)",          { XX } },
5562     { "(bad)",          { XX } },
5563     /* 28 */
5564     { PREFIX_TABLE (PREFIX_0F3828) },
5565     { PREFIX_TABLE (PREFIX_0F3829) },
5566     { PREFIX_TABLE (PREFIX_0F382A) },
5567     { PREFIX_TABLE (PREFIX_0F382B) },
5568     { "(bad)",          { XX } },
5569     { "(bad)",          { XX } },
5570     { "(bad)",          { XX } },
5571     { "(bad)",          { XX } },
5572     /* 30 */
5573     { PREFIX_TABLE (PREFIX_0F3830) },
5574     { PREFIX_TABLE (PREFIX_0F3831) },
5575     { PREFIX_TABLE (PREFIX_0F3832) },
5576     { PREFIX_TABLE (PREFIX_0F3833) },
5577     { PREFIX_TABLE (PREFIX_0F3834) },
5578     { PREFIX_TABLE (PREFIX_0F3835) },
5579     { "(bad)",          { XX } },
5580     { PREFIX_TABLE (PREFIX_0F3837) },
5581     /* 38 */
5582     { PREFIX_TABLE (PREFIX_0F3838) },
5583     { PREFIX_TABLE (PREFIX_0F3839) },
5584     { PREFIX_TABLE (PREFIX_0F383A) },
5585     { PREFIX_TABLE (PREFIX_0F383B) },
5586     { PREFIX_TABLE (PREFIX_0F383C) },
5587     { PREFIX_TABLE (PREFIX_0F383D) },
5588     { PREFIX_TABLE (PREFIX_0F383E) },
5589     { PREFIX_TABLE (PREFIX_0F383F) },
5590     /* 40 */
5591     { PREFIX_TABLE (PREFIX_0F3840) },
5592     { PREFIX_TABLE (PREFIX_0F3841) },
5593     { "(bad)",          { XX } },
5594     { "(bad)",          { XX } },
5595     { "(bad)",          { XX } },
5596     { "(bad)",          { XX } },
5597     { "(bad)",          { XX } },
5598     { "(bad)",          { XX } },
5599     /* 48 */
5600     { "(bad)",          { XX } },
5601     { "(bad)",          { XX } },
5602     { "(bad)",          { XX } },
5603     { "(bad)",          { XX } },
5604     { "(bad)",          { XX } },
5605     { "(bad)",          { XX } },
5606     { "(bad)",          { XX } },
5607     { "(bad)",          { XX } },
5608     /* 50 */
5609     { "(bad)",          { XX } },
5610     { "(bad)",          { XX } },
5611     { "(bad)",          { XX } },
5612     { "(bad)",          { XX } },
5613     { "(bad)",          { XX } },
5614     { "(bad)",          { XX } },
5615     { "(bad)",          { XX } },
5616     { "(bad)",          { XX } },
5617     /* 58 */
5618     { "(bad)",          { XX } },
5619     { "(bad)",          { XX } },
5620     { "(bad)",          { XX } },
5621     { "(bad)",          { XX } },
5622     { "(bad)",          { XX } },
5623     { "(bad)",          { XX } },
5624     { "(bad)",          { XX } },
5625     { "(bad)",          { XX } },
5626     /* 60 */
5627     { "(bad)",          { XX } },
5628     { "(bad)",          { XX } },
5629     { "(bad)",          { XX } },
5630     { "(bad)",          { XX } },
5631     { "(bad)",          { XX } },
5632     { "(bad)",          { XX } },
5633     { "(bad)",          { XX } },
5634     { "(bad)",          { XX } },
5635     /* 68 */
5636     { "(bad)",          { XX } },
5637     { "(bad)",          { XX } },
5638     { "(bad)",          { XX } },
5639     { "(bad)",          { XX } },
5640     { "(bad)",          { XX } },
5641     { "(bad)",          { XX } },
5642     { "(bad)",          { XX } },
5643     { "(bad)",          { XX } },
5644     /* 70 */
5645     { "(bad)",          { XX } },
5646     { "(bad)",          { XX } },
5647     { "(bad)",          { XX } },
5648     { "(bad)",          { XX } },
5649     { "(bad)",          { XX } },
5650     { "(bad)",          { XX } },
5651     { "(bad)",          { XX } },
5652     { "(bad)",          { XX } },
5653     /* 78 */
5654     { "(bad)",          { XX } },
5655     { "(bad)",          { XX } },
5656     { "(bad)",          { XX } },
5657     { "(bad)",          { XX } },
5658     { "(bad)",          { XX } },
5659     { "(bad)",          { XX } },
5660     { "(bad)",          { XX } },
5661     { "(bad)",          { XX } },
5662     /* 80 */
5663     { PREFIX_TABLE (PREFIX_0F3880) },
5664     { PREFIX_TABLE (PREFIX_0F3881) },
5665     { "(bad)",          { XX } },
5666     { "(bad)",          { XX } },
5667     { "(bad)",          { XX } },
5668     { "(bad)",          { XX } },
5669     { "(bad)",          { XX } },
5670     { "(bad)",          { XX } },
5671     /* 88 */
5672     { "(bad)",          { XX } },
5673     { "(bad)",          { XX } },
5674     { "(bad)",          { XX } },
5675     { "(bad)",          { XX } },
5676     { "(bad)",          { XX } },
5677     { "(bad)",          { XX } },
5678     { "(bad)",          { XX } },
5679     { "(bad)",          { XX } },
5680     /* 90 */
5681     { "(bad)",          { XX } },
5682     { "(bad)",          { XX } },
5683     { "(bad)",          { XX } },
5684     { "(bad)",          { XX } },
5685     { "(bad)",          { XX } },
5686     { "(bad)",          { XX } },
5687     { "(bad)",          { XX } },
5688     { "(bad)",          { XX } },
5689     /* 98 */
5690     { "(bad)",          { XX } },
5691     { "(bad)",          { XX } },
5692     { "(bad)",          { XX } },
5693     { "(bad)",          { XX } },
5694     { "(bad)",          { XX } },
5695     { "(bad)",          { XX } },
5696     { "(bad)",          { XX } },
5697     { "(bad)",          { XX } },
5698     /* a0 */
5699     { "(bad)",          { XX } },
5700     { "(bad)",          { XX } },
5701     { "(bad)",          { XX } },
5702     { "(bad)",          { XX } },
5703     { "(bad)",          { XX } },
5704     { "(bad)",          { XX } },
5705     { "(bad)",          { XX } },
5706     { "(bad)",          { XX } },
5707     /* a8 */
5708     { "(bad)",          { XX } },
5709     { "(bad)",          { XX } },
5710     { "(bad)",          { XX } },
5711     { "(bad)",          { XX } },
5712     { "(bad)",          { XX } },
5713     { "(bad)",          { XX } },
5714     { "(bad)",          { XX } },
5715     { "(bad)",          { XX } },
5716     /* b0 */
5717     { "(bad)",          { XX } },
5718     { "(bad)",          { XX } },
5719     { "(bad)",          { XX } },
5720     { "(bad)",          { XX } },
5721     { "(bad)",          { XX } },
5722     { "(bad)",          { XX } },
5723     { "(bad)",          { XX } },
5724     { "(bad)",          { XX } },
5725     /* b8 */
5726     { "(bad)",          { XX } },
5727     { "(bad)",          { XX } },
5728     { "(bad)",          { XX } },
5729     { "(bad)",          { XX } },
5730     { "(bad)",          { XX } },
5731     { "(bad)",          { XX } },
5732     { "(bad)",          { XX } },
5733     { "(bad)",          { XX } },
5734     /* c0 */
5735     { "(bad)",          { XX } },
5736     { "(bad)",          { XX } },
5737     { "(bad)",          { XX } },
5738     { "(bad)",          { XX } },
5739     { "(bad)",          { XX } },
5740     { "(bad)",          { XX } },
5741     { "(bad)",          { XX } },
5742     { "(bad)",          { XX } },
5743     /* c8 */
5744     { "(bad)",          { XX } },
5745     { "(bad)",          { XX } },
5746     { "(bad)",          { XX } },
5747     { "(bad)",          { XX } },
5748     { "(bad)",          { XX } },
5749     { "(bad)",          { XX } },
5750     { "(bad)",          { XX } },
5751     { "(bad)",          { XX } },
5752     /* d0 */
5753     { "(bad)",          { XX } },
5754     { "(bad)",          { XX } },
5755     { "(bad)",          { XX } },
5756     { "(bad)",          { XX } },
5757     { "(bad)",          { XX } },
5758     { "(bad)",          { XX } },
5759     { "(bad)",          { XX } },
5760     { "(bad)",          { XX } },
5761     /* d8 */
5762     { "(bad)",          { XX } },
5763     { "(bad)",          { XX } },
5764     { "(bad)",          { XX } },
5765     { PREFIX_TABLE (PREFIX_0F38DB) },
5766     { PREFIX_TABLE (PREFIX_0F38DC) },
5767     { PREFIX_TABLE (PREFIX_0F38DD) },
5768     { PREFIX_TABLE (PREFIX_0F38DE) },
5769     { PREFIX_TABLE (PREFIX_0F38DF) },
5770     /* e0 */
5771     { "(bad)",          { XX } },
5772     { "(bad)",          { XX } },
5773     { "(bad)",          { XX } },
5774     { "(bad)",          { XX } },
5775     { "(bad)",          { XX } },
5776     { "(bad)",          { XX } },
5777     { "(bad)",          { XX } },
5778     { "(bad)",          { XX } },
5779     /* e8 */
5780     { "(bad)",          { XX } },
5781     { "(bad)",          { XX } },
5782     { "(bad)",          { XX } },
5783     { "(bad)",          { XX } },
5784     { "(bad)",          { XX } },
5785     { "(bad)",          { XX } },
5786     { "(bad)",          { XX } },
5787     { "(bad)",          { XX } },
5788     /* f0 */
5789     { PREFIX_TABLE (PREFIX_0F38F0) },
5790     { PREFIX_TABLE (PREFIX_0F38F1) },
5791     { "(bad)",          { XX } },
5792     { "(bad)",          { XX } },
5793     { "(bad)",          { XX } },
5794     { "(bad)",          { XX } },
5795     { "(bad)",          { XX } },
5796     { "(bad)",          { XX } },
5797     /* f8 */
5798     { "(bad)",          { XX } },
5799     { "(bad)",          { XX } },
5800     { "(bad)",          { XX } },
5801     { "(bad)",          { XX } },
5802     { "(bad)",          { XX } },
5803     { "(bad)",          { XX } },
5804     { "(bad)",          { XX } },
5805     { "(bad)",          { XX } },
5806   },
5807   /* THREE_BYTE_0F3A */
5808   {
5809     /* 00 */
5810     { "(bad)",          { XX } },
5811     { "(bad)",          { XX } },
5812     { "(bad)",          { XX } },
5813     { "(bad)",          { XX } },
5814     { "(bad)",          { XX } },
5815     { "(bad)",          { XX } },
5816     { "(bad)",          { XX } },
5817     { "(bad)",          { XX } },
5818     /* 08 */
5819     { PREFIX_TABLE (PREFIX_0F3A08) },
5820     { PREFIX_TABLE (PREFIX_0F3A09) },
5821     { PREFIX_TABLE (PREFIX_0F3A0A) },
5822     { PREFIX_TABLE (PREFIX_0F3A0B) },
5823     { PREFIX_TABLE (PREFIX_0F3A0C) },
5824     { PREFIX_TABLE (PREFIX_0F3A0D) },
5825     { PREFIX_TABLE (PREFIX_0F3A0E) },
5826     { "palignr",        { MX, EM, Ib } },
5827     /* 10 */
5828     { "(bad)",          { XX } },
5829     { "(bad)",          { XX } },
5830     { "(bad)",          { XX } },
5831     { "(bad)",          { XX } },
5832     { PREFIX_TABLE (PREFIX_0F3A14) },
5833     { PREFIX_TABLE (PREFIX_0F3A15) },
5834     { PREFIX_TABLE (PREFIX_0F3A16) },
5835     { PREFIX_TABLE (PREFIX_0F3A17) },
5836     /* 18 */
5837     { "(bad)",          { XX } },
5838     { "(bad)",          { XX } },
5839     { "(bad)",          { XX } },
5840     { "(bad)",          { XX } },
5841     { "(bad)",          { XX } },
5842     { "(bad)",          { XX } },
5843     { "(bad)",          { XX } },
5844     { "(bad)",          { XX } },
5845     /* 20 */
5846     { PREFIX_TABLE (PREFIX_0F3A20) },
5847     { PREFIX_TABLE (PREFIX_0F3A21) },
5848     { PREFIX_TABLE (PREFIX_0F3A22) },
5849     { "(bad)",          { XX } },
5850     { "(bad)",          { XX } },
5851     { "(bad)",          { XX } },
5852     { "(bad)",          { XX } },
5853     { "(bad)",          { XX } },
5854     /* 28 */
5855     { "(bad)",          { XX } },
5856     { "(bad)",          { XX } },
5857     { "(bad)",          { XX } },
5858     { "(bad)",          { XX } },
5859     { "(bad)",          { XX } },
5860     { "(bad)",          { XX } },
5861     { "(bad)",          { XX } },
5862     { "(bad)",          { XX } },
5863     /* 30 */
5864     { "(bad)",          { XX } },
5865     { "(bad)",          { XX } },
5866     { "(bad)",          { XX } },
5867     { "(bad)",          { XX } },
5868     { "(bad)",          { XX } },
5869     { "(bad)",          { XX } },
5870     { "(bad)",          { XX } },
5871     { "(bad)",          { XX } },
5872     /* 38 */
5873     { "(bad)",          { XX } },
5874     { "(bad)",          { XX } },
5875     { "(bad)",          { XX } },
5876     { "(bad)",          { XX } },
5877     { "(bad)",          { XX } },
5878     { "(bad)",          { XX } },
5879     { "(bad)",          { XX } },
5880     { "(bad)",          { XX } },
5881     /* 40 */
5882     { PREFIX_TABLE (PREFIX_0F3A40) },
5883     { PREFIX_TABLE (PREFIX_0F3A41) },
5884     { PREFIX_TABLE (PREFIX_0F3A42) },
5885     { "(bad)",          { XX } },
5886     { PREFIX_TABLE (PREFIX_0F3A44) },
5887     { "(bad)",          { XX } },
5888     { "(bad)",          { XX } },
5889     { "(bad)",          { XX } },
5890     /* 48 */
5891     { "(bad)",          { XX } },
5892     { "(bad)",          { XX } },
5893     { "(bad)",          { XX } },
5894     { "(bad)",          { XX } },
5895     { "(bad)",          { XX } },
5896     { "(bad)",          { XX } },
5897     { "(bad)",          { XX } },
5898     { "(bad)",          { XX } },
5899     /* 50 */
5900     { "(bad)",          { XX } },
5901     { "(bad)",          { XX } },
5902     { "(bad)",          { XX } },
5903     { "(bad)",          { XX } },
5904     { "(bad)",          { XX } },
5905     { "(bad)",          { XX } },
5906     { "(bad)",          { XX } },
5907     { "(bad)",          { XX } },
5908     /* 58 */
5909     { "(bad)",          { XX } },
5910     { "(bad)",          { XX } },
5911     { "(bad)",          { XX } },
5912     { "(bad)",          { XX } },
5913     { "(bad)",          { XX } },
5914     { "(bad)",          { XX } },
5915     { "(bad)",          { XX } },
5916     { "(bad)",          { XX } },
5917     /* 60 */
5918     { PREFIX_TABLE (PREFIX_0F3A60) },
5919     { PREFIX_TABLE (PREFIX_0F3A61) },
5920     { PREFIX_TABLE (PREFIX_0F3A62) },
5921     { PREFIX_TABLE (PREFIX_0F3A63) },
5922     { "(bad)",          { XX } },
5923     { "(bad)",          { XX } },
5924     { "(bad)",          { XX } },
5925     { "(bad)",          { XX } },
5926     /* 68 */
5927     { "(bad)",          { XX } },
5928     { "(bad)",          { XX } },
5929     { "(bad)",          { XX } },
5930     { "(bad)",          { XX } },
5931     { "(bad)",          { XX } },
5932     { "(bad)",          { XX } },
5933     { "(bad)",          { XX } },
5934     { "(bad)",          { XX } },
5935     /* 70 */
5936     { "(bad)",          { XX } },
5937     { "(bad)",          { XX } },
5938     { "(bad)",          { XX } },
5939     { "(bad)",          { XX } },
5940     { "(bad)",          { XX } },
5941     { "(bad)",          { XX } },
5942     { "(bad)",          { XX } },
5943     { "(bad)",          { XX } },
5944     /* 78 */
5945     { "(bad)",          { XX } },
5946     { "(bad)",          { XX } },
5947     { "(bad)",          { XX } },
5948     { "(bad)",          { XX } },
5949     { "(bad)",          { XX } },
5950     { "(bad)",          { XX } },
5951     { "(bad)",          { XX } },
5952     { "(bad)",          { XX } },
5953     /* 80 */
5954     { "(bad)",          { XX } },
5955     { "(bad)",          { XX } },
5956     { "(bad)",          { XX } },
5957     { "(bad)",          { XX } },
5958     { "(bad)",          { XX } },
5959     { "(bad)",          { XX } },
5960     { "(bad)",          { XX } },
5961     { "(bad)",          { XX } },
5962     /* 88 */
5963     { "(bad)",          { XX } },
5964     { "(bad)",          { XX } },
5965     { "(bad)",          { XX } },
5966     { "(bad)",          { XX } },
5967     { "(bad)",          { XX } },
5968     { "(bad)",          { XX } },
5969     { "(bad)",          { XX } },
5970     { "(bad)",          { XX } },
5971     /* 90 */
5972     { "(bad)",          { XX } },
5973     { "(bad)",          { XX } },
5974     { "(bad)",          { XX } },
5975     { "(bad)",          { XX } },
5976     { "(bad)",          { XX } },
5977     { "(bad)",          { XX } },
5978     { "(bad)",          { XX } },
5979     { "(bad)",          { XX } },
5980     /* 98 */
5981     { "(bad)",          { XX } },
5982     { "(bad)",          { XX } },
5983     { "(bad)",          { XX } },
5984     { "(bad)",          { XX } },
5985     { "(bad)",          { XX } },
5986     { "(bad)",          { XX } },
5987     { "(bad)",          { XX } },
5988     { "(bad)",          { XX } },
5989     /* a0 */
5990     { "(bad)",          { XX } },
5991     { "(bad)",          { XX } },
5992     { "(bad)",          { XX } },
5993     { "(bad)",          { XX } },
5994     { "(bad)",          { XX } },
5995     { "(bad)",          { XX } },
5996     { "(bad)",          { XX } },
5997     { "(bad)",          { XX } },
5998     /* a8 */
5999     { "(bad)",          { XX } },
6000     { "(bad)",          { XX } },
6001     { "(bad)",          { XX } },
6002     { "(bad)",          { XX } },
6003     { "(bad)",          { XX } },
6004     { "(bad)",          { XX } },
6005     { "(bad)",          { XX } },
6006     { "(bad)",          { XX } },
6007     /* b0 */
6008     { "(bad)",          { XX } },
6009     { "(bad)",          { XX } },
6010     { "(bad)",          { XX } },
6011     { "(bad)",          { XX } },
6012     { "(bad)",          { XX } },
6013     { "(bad)",          { XX } },
6014     { "(bad)",          { XX } },
6015     { "(bad)",          { XX } },
6016     /* b8 */
6017     { "(bad)",          { XX } },
6018     { "(bad)",          { XX } },
6019     { "(bad)",          { XX } },
6020     { "(bad)",          { XX } },
6021     { "(bad)",          { XX } },
6022     { "(bad)",          { XX } },
6023     { "(bad)",          { XX } },
6024     { "(bad)",          { XX } },
6025     /* c0 */
6026     { "(bad)",          { XX } },
6027     { "(bad)",          { XX } },
6028     { "(bad)",          { XX } },
6029     { "(bad)",          { XX } },
6030     { "(bad)",          { XX } },
6031     { "(bad)",          { XX } },
6032     { "(bad)",          { XX } },
6033     { "(bad)",          { XX } },
6034     /* c8 */
6035     { "(bad)",          { XX } },
6036     { "(bad)",          { XX } },
6037     { "(bad)",          { XX } },
6038     { "(bad)",          { XX } },
6039     { "(bad)",          { XX } },
6040     { "(bad)",          { XX } },
6041     { "(bad)",          { XX } },
6042     { "(bad)",          { XX } },
6043     /* d0 */
6044     { "(bad)",          { XX } },
6045     { "(bad)",          { XX } },
6046     { "(bad)",          { XX } },
6047     { "(bad)",          { XX } },
6048     { "(bad)",          { XX } },
6049     { "(bad)",          { XX } },
6050     { "(bad)",          { XX } },
6051     { "(bad)",          { XX } },
6052     /* d8 */
6053     { "(bad)",          { XX } },
6054     { "(bad)",          { XX } },
6055     { "(bad)",          { XX } },
6056     { "(bad)",          { XX } },
6057     { "(bad)",          { XX } },
6058     { "(bad)",          { XX } },
6059     { "(bad)",          { XX } },
6060     { PREFIX_TABLE (PREFIX_0F3ADF) },
6061     /* e0 */
6062     { "(bad)",          { XX } },
6063     { "(bad)",          { XX } },
6064     { "(bad)",          { XX } },
6065     { "(bad)",          { XX } },
6066     { "(bad)",          { XX } },
6067     { "(bad)",          { XX } },
6068     { "(bad)",          { XX } },
6069     { "(bad)",          { XX } },
6070     /* e8 */
6071     { "(bad)",          { XX } },
6072     { "(bad)",          { XX } },
6073     { "(bad)",          { XX } },
6074     { "(bad)",          { XX } },
6075     { "(bad)",          { XX } },
6076     { "(bad)",          { XX } },
6077     { "(bad)",          { XX } },
6078     { "(bad)",          { XX } },
6079     /* f0 */
6080     { "(bad)",          { XX } },
6081     { "(bad)",          { XX } },
6082     { "(bad)",          { XX } },
6083     { "(bad)",          { XX } },
6084     { "(bad)",          { XX } },
6085     { "(bad)",          { XX } },
6086     { "(bad)",          { XX } },
6087     { "(bad)",          { XX } },
6088     /* f8 */
6089     { "(bad)",          { XX } },
6090     { "(bad)",          { XX } },
6091     { "(bad)",          { XX } },
6092     { "(bad)",          { XX } },
6093     { "(bad)",          { XX } },
6094     { "(bad)",          { XX } },
6095     { "(bad)",          { XX } },
6096     { "(bad)",          { XX } },
6097   },
6098
6099   /* THREE_BYTE_0F7A */
6100   {
6101     /* 00 */
6102     { "(bad)",          { XX } },
6103     { "(bad)",          { XX } },
6104     { "(bad)",          { XX } },
6105     { "(bad)",          { XX } },
6106     { "(bad)",          { XX } },
6107     { "(bad)",          { XX } },
6108     { "(bad)",          { XX } },
6109     { "(bad)",          { XX } },
6110     /* 08 */
6111     { "(bad)",          { XX } },
6112     { "(bad)",          { XX } },
6113     { "(bad)",          { XX } },
6114     { "(bad)",          { XX } },
6115     { "(bad)",          { XX } },
6116     { "(bad)",          { XX } },
6117     { "(bad)",          { XX } },
6118     { "(bad)",          { XX } },
6119     /* 10 */
6120     { "(bad)",          { XX } },
6121     { "(bad)",          { XX } },
6122     { "(bad)",          { XX } },
6123     { "(bad)",          { XX } },
6124     { "(bad)",          { XX } },
6125     { "(bad)",          { XX } },
6126     { "(bad)",          { XX } },
6127     { "(bad)",          { XX } },
6128     /* 18 */
6129     { "(bad)",          { XX } },
6130     { "(bad)",          { XX } },
6131     { "(bad)",          { XX } },
6132     { "(bad)",          { XX } },
6133     { "(bad)",          { XX } },
6134     { "(bad)",          { XX } },
6135     { "(bad)",          { XX } },
6136     { "(bad)",          { XX } },
6137     /* 20 */
6138     { "ptest",          { XX } },
6139     { "(bad)",          { XX } },
6140     { "(bad)",          { XX } },
6141     { "(bad)",          { XX } },
6142     { "(bad)",          { XX } },
6143     { "(bad)",          { XX } },
6144     { "(bad)",          { XX } },
6145     { "(bad)",          { XX } },
6146     /* 28 */
6147     { "(bad)",          { XX } },
6148     { "(bad)",          { XX } },
6149     { "(bad)",          { XX } },
6150     { "(bad)",          { XX } },
6151     { "(bad)",          { XX } },
6152     { "(bad)",          { XX } },
6153     { "(bad)",          { XX } },
6154     { "(bad)",          { XX } },
6155     /* 30 */
6156     { "(bad)",          { XX } },
6157     { "(bad)",          { XX } },
6158     { "(bad)",          { XX } },
6159     { "(bad)",          { XX } },
6160     { "(bad)",          { XX } },
6161     { "(bad)",          { XX } },
6162     { "(bad)",          { XX } },
6163     { "(bad)",          { XX } },
6164     /* 38 */
6165     { "(bad)",          { XX } },
6166     { "(bad)",          { XX } },
6167     { "(bad)",          { XX } },
6168     { "(bad)",          { XX } },
6169     { "(bad)",          { XX } },
6170     { "(bad)",          { XX } },
6171     { "(bad)",          { XX } },
6172     { "(bad)",          { XX } },
6173     /* 40 */
6174     { "(bad)",          { XX } },
6175     { "phaddbw",        { XM, EXq } },
6176     { "phaddbd",        { XM, EXq } },
6177     { "phaddbq",        { XM, EXq } },
6178     { "(bad)",          { XX } },
6179     { "(bad)",          { XX } },
6180     { "phaddwd",        { XM, EXq } },
6181     { "phaddwq",        { XM, EXq } },
6182     /* 48 */
6183     { "(bad)",          { XX } },
6184     { "(bad)",          { XX } },
6185     { "(bad)",          { XX } },
6186     { "phadddq",        { XM, EXq } },
6187     { "(bad)",          { XX } },
6188     { "(bad)",          { XX } },
6189     { "(bad)",          { XX } },
6190     { "(bad)",          { XX } },
6191     /* 50 */
6192     { "(bad)",          { XX } },
6193     { "phaddubw",       { XM, EXq } },
6194     { "phaddubd",       { XM, EXq } },
6195     { "phaddubq",       { XM, EXq } },
6196     { "(bad)",          { XX } },
6197     { "(bad)",          { XX } },
6198     { "phadduwd",       { XM, EXq } },
6199     { "phadduwq",       { XM, EXq } },
6200     /* 58 */
6201     { "(bad)",          { XX } },
6202     { "(bad)",          { XX } },
6203     { "(bad)",          { XX } },
6204     { "phaddudq",       { XM, EXq } },
6205     { "(bad)",          { XX } },
6206     { "(bad)",          { XX } },
6207     { "(bad)",          { XX } },
6208     { "(bad)",          { XX } },
6209     /* 60 */
6210     { "(bad)",          { XX } },
6211     { "phsubbw",        { XM, EXq } },
6212     { "phsubbd",        { XM, EXq } },
6213     { "phsubbq",        { XM, EXq } },
6214     { "(bad)",          { XX } },
6215     { "(bad)",          { XX } },
6216     { "(bad)",          { XX } },
6217     { "(bad)",          { XX } },
6218     /* 68 */
6219     { "(bad)",          { XX } },
6220     { "(bad)",          { XX } },
6221     { "(bad)",          { XX } },
6222     { "(bad)",          { XX } },
6223     { "(bad)",          { XX } },
6224     { "(bad)",          { XX } },
6225     { "(bad)",          { XX } },
6226     { "(bad)",          { XX } },
6227     /* 70 */
6228     { "(bad)",          { XX } },
6229     { "(bad)",          { XX } },
6230     { "(bad)",          { XX } },
6231     { "(bad)",          { XX } },
6232     { "(bad)",          { XX } },
6233     { "(bad)",          { XX } },
6234     { "(bad)",          { XX } },
6235     { "(bad)",          { XX } },
6236     /* 78 */
6237     { "(bad)",          { XX } },
6238     { "(bad)",          { XX } },
6239     { "(bad)",          { XX } },
6240     { "(bad)",          { XX } },
6241     { "(bad)",          { XX } },
6242     { "(bad)",          { XX } },
6243     { "(bad)",          { XX } },
6244     { "(bad)",          { XX } },
6245     /* 80 */
6246     { "(bad)",          { XX } },
6247     { "(bad)",          { XX } },
6248     { "(bad)",          { XX } },
6249     { "(bad)",          { XX } },
6250     { "(bad)",          { XX } },
6251     { "(bad)",          { XX } },
6252     { "(bad)",          { XX } },
6253     { "(bad)",          { XX } },
6254     /* 88 */
6255     { "(bad)",          { XX } },
6256     { "(bad)",          { XX } },
6257     { "(bad)",          { XX } },
6258     { "(bad)",          { XX } },
6259     { "(bad)",          { XX } },
6260     { "(bad)",          { XX } },
6261     { "(bad)",          { XX } },
6262     { "(bad)",          { XX } },
6263     /* 90 */
6264     { "(bad)",          { XX } },
6265     { "(bad)",          { XX } },
6266     { "(bad)",          { XX } },
6267     { "(bad)",          { XX } },
6268     { "(bad)",          { XX } },
6269     { "(bad)",          { XX } },
6270     { "(bad)",          { XX } },
6271     { "(bad)",          { XX } },
6272     /* 98 */
6273     { "(bad)",          { XX } },
6274     { "(bad)",          { XX } },
6275     { "(bad)",          { XX } },
6276     { "(bad)",          { XX } },
6277     { "(bad)",          { XX } },
6278     { "(bad)",          { XX } },
6279     { "(bad)",          { XX } },
6280     { "(bad)",          { XX } },
6281     /* a0 */
6282     { "(bad)",          { XX } },
6283     { "(bad)",          { XX } },
6284     { "(bad)",          { XX } },
6285     { "(bad)",          { XX } },
6286     { "(bad)",          { XX } },
6287     { "(bad)",          { XX } },
6288     { "(bad)",          { XX } },
6289     { "(bad)",          { XX } },
6290     /* a8 */
6291     { "(bad)",          { XX } },
6292     { "(bad)",          { XX } },
6293     { "(bad)",          { XX } },
6294     { "(bad)",          { XX } },
6295     { "(bad)",          { XX } },
6296     { "(bad)",          { XX } },
6297     { "(bad)",          { XX } },
6298     { "(bad)",          { XX } },
6299     /* b0 */
6300     { "(bad)",          { XX } },
6301     { "(bad)",          { XX } },
6302     { "(bad)",          { XX } },
6303     { "(bad)",          { XX } },
6304     { "(bad)",          { XX } },
6305     { "(bad)",          { XX } },
6306     { "(bad)",          { XX } },
6307     { "(bad)",          { XX } },
6308     /* b8 */
6309     { "(bad)",          { XX } },
6310     { "(bad)",          { XX } },
6311     { "(bad)",          { XX } },
6312     { "(bad)",          { XX } },
6313     { "(bad)",          { XX } },
6314     { "(bad)",          { XX } },
6315     { "(bad)",          { XX } },
6316     { "(bad)",          { XX } },
6317     /* c0 */
6318     { "(bad)",          { XX } },
6319     { "(bad)",          { XX } },
6320     { "(bad)",          { XX } },
6321     { "(bad)",          { XX } },
6322     { "(bad)",          { XX } },
6323     { "(bad)",          { XX } },
6324     { "(bad)",          { XX } },
6325     { "(bad)",          { XX } },
6326     /* c8 */
6327     { "(bad)",          { XX } },
6328     { "(bad)",          { XX } },
6329     { "(bad)",          { XX } },
6330     { "(bad)",          { XX } },
6331     { "(bad)",          { XX } },
6332     { "(bad)",          { XX } },
6333     { "(bad)",          { XX } },
6334     { "(bad)",          { XX } },
6335     /* d0 */
6336     { "(bad)",          { XX } },
6337     { "(bad)",          { XX } },
6338     { "(bad)",          { XX } },
6339     { "(bad)",          { XX } },
6340     { "(bad)",          { XX } },
6341     { "(bad)",          { XX } },
6342     { "(bad)",          { XX } },
6343     { "(bad)",          { XX } },
6344     /* d8 */
6345     { "(bad)",          { XX } },
6346     { "(bad)",          { XX } },
6347     { "(bad)",          { XX } },
6348     { "(bad)",          { XX } },
6349     { "(bad)",          { XX } },
6350     { "(bad)",          { XX } },
6351     { "(bad)",          { XX } },
6352     { "(bad)",          { XX } },
6353     /* e0 */
6354     { "(bad)",          { XX } },
6355     { "(bad)",          { XX } },
6356     { "(bad)",          { XX } },
6357     { "(bad)",          { XX } },
6358     { "(bad)",          { XX } },
6359     { "(bad)",          { XX } },
6360     { "(bad)",          { XX } },
6361     { "(bad)",          { XX } },
6362     /* e8 */
6363     { "(bad)",          { XX } },
6364     { "(bad)",          { XX } },
6365     { "(bad)",          { XX } },
6366     { "(bad)",          { XX } },
6367     { "(bad)",          { XX } },
6368     { "(bad)",          { XX } },
6369     { "(bad)",          { XX } },
6370     { "(bad)",          { XX } },
6371     /* f0 */
6372     { "(bad)",          { XX } },
6373     { "(bad)",          { XX } },
6374     { "(bad)",          { XX } },
6375     { "(bad)",          { XX } },
6376     { "(bad)",          { XX } },
6377     { "(bad)",          { XX } },
6378     { "(bad)",          { XX } },
6379     { "(bad)",          { XX } },
6380     /* f8 */
6381     { "(bad)",          { XX } },
6382     { "(bad)",          { XX } },
6383     { "(bad)",          { XX } },
6384     { "(bad)",          { XX } },
6385     { "(bad)",          { XX } },
6386     { "(bad)",          { XX } },
6387     { "(bad)",          { XX } },
6388     { "(bad)",          { XX } },
6389   },
6390 };
6391
6392 static const struct dis386 xop_table[][256] = {
6393   /* XOP_08 */
6394   {
6395     /* 00 */
6396     { "(bad)",          { XX } },
6397     { "(bad)",          { XX } },
6398     { "(bad)",          { XX } },
6399     { "(bad)",          { XX } },
6400     { "(bad)",          { XX } },
6401     { "(bad)",          { XX } },
6402     { "(bad)",          { XX } },
6403     { "(bad)",          { XX } },
6404     /* 08 */
6405     { "(bad)",          { XX } },
6406     { "(bad)",          { XX } },
6407     { "(bad)",          { XX } },
6408     { "(bad)",          { XX } },
6409     { "(bad)",          { XX } },
6410     { "(bad)",          { XX } },
6411     { "(bad)",          { XX } },
6412     { "(bad)",          { XX } },
6413     /* 10 */
6414     { "(bad)",          { XX } },
6415     { "(bad)",          { XX } },
6416     { "(bad)",          { XX } },
6417     { "(bad)",          { XX } },
6418     { "(bad)",          { XX } },
6419     { "(bad)",          { XX } },
6420     { "(bad)",          { XX } },
6421     { "(bad)",          { XX } },
6422     /* 18 */
6423     { "(bad)",          { XX } },
6424     { "(bad)",          { XX } },
6425     { "(bad)",          { XX } },
6426     { "(bad)",          { XX } },
6427     { "(bad)",          { XX } },
6428     { "(bad)",          { XX } },
6429     { "(bad)",          { XX } },
6430     { "(bad)",          { XX } },
6431     /* 20 */
6432     { "(bad)",          { XX } },
6433     { "(bad)",          { XX } },
6434     { "(bad)",          { XX } },
6435     { "(bad)",          { XX } },
6436     { "(bad)",          { XX } },
6437     { "(bad)",          { XX } },
6438     { "(bad)",          { XX } },
6439     { "(bad)",          { XX } },
6440     /* 28 */
6441     { "(bad)",          { XX } },
6442     { "(bad)",          { XX } },
6443     { "(bad)",          { XX } },
6444     { "(bad)",          { XX } },
6445     { "(bad)",          { XX } },
6446     { "(bad)",          { XX } },
6447     { "(bad)",          { XX } },
6448     { "(bad)",          { XX } },
6449     /* 30 */
6450     { "(bad)",          { XX } },
6451     { "(bad)",          { XX } },
6452     { "(bad)",          { XX } },
6453     { "(bad)",          { XX } },
6454     { "(bad)",          { XX } },
6455     { "(bad)",          { XX } },
6456     { "(bad)",          { XX } },
6457     { "(bad)",          { XX } },
6458     /* 38 */
6459     { "(bad)",          { XX } },
6460     { "(bad)",          { XX } },
6461     { "(bad)",          { XX } },
6462     { "(bad)",          { XX } },
6463     { "(bad)",          { XX } },
6464     { "(bad)",          { XX } },
6465     { "(bad)",          { XX } },
6466     { "(bad)",          { XX } },
6467     /* 40 */
6468     { "(bad)",          { XX } },
6469     { "(bad)",          { XX } },
6470     { "(bad)",          { XX } },
6471     { "(bad)",          { XX } },
6472     { "(bad)",          { XX } },
6473     { "(bad)",          { XX } },
6474     { "(bad)",          { XX } },
6475     { "(bad)",          { XX } },
6476     /* 48 */
6477     { "(bad)",          { XX } },
6478     { "(bad)",          { XX } },
6479     { "(bad)",          { XX } },
6480     { "(bad)",          { XX } },
6481     { "(bad)",          { XX } },
6482     { "(bad)",          { XX } },
6483     { "(bad)",          { XX } },
6484     { "(bad)",          { XX } },
6485     /* 50 */
6486     { "(bad)",          { XX } },
6487     { "(bad)",          { XX } },
6488     { "(bad)",          { XX } },
6489     { "(bad)",          { XX } },
6490     { "(bad)",          { XX } },
6491     { "(bad)",          { XX } },
6492     { "(bad)",          { XX } },
6493     { "(bad)",          { XX } },
6494     /* 58 */
6495     { "(bad)",          { XX } },
6496     { "(bad)",          { XX } },
6497     { "(bad)",          { XX } },
6498     { "(bad)",          { XX } },
6499     { "(bad)",          { XX } },
6500     { "(bad)",          { XX } },
6501     { "(bad)",          { XX } },
6502     { "(bad)",          { XX } },
6503     /* 60 */
6504     { "(bad)",          { XX } },
6505     { "(bad)",          { XX } },
6506     { "(bad)",          { XX } },
6507     { "(bad)",          { XX } },
6508     { "(bad)",          { XX } },
6509     { "(bad)",          { XX } },
6510     { "(bad)",          { XX } },
6511     { "(bad)",          { XX } },
6512     /* 68 */
6513     { "(bad)",          { XX } },
6514     { "(bad)",          { XX } },
6515     { "(bad)",          { XX } },
6516     { "(bad)",          { XX } },
6517     { "(bad)",          { XX } },
6518     { "(bad)",          { XX } },
6519     { "(bad)",          { XX } },
6520     { "(bad)",          { XX } },
6521     /* 70 */
6522     { "(bad)",          { XX } },
6523     { "(bad)",          { XX } },
6524     { "(bad)",          { XX } },
6525     { "(bad)",          { XX } },
6526     { "(bad)",          { XX } },
6527     { "(bad)",          { XX } },
6528     { "(bad)",          { XX } },
6529     { "(bad)",          { XX } },
6530     /* 78 */
6531     { "(bad)",          { XX } },
6532     { "(bad)",          { XX } },
6533     { "(bad)",          { XX } },
6534     { "(bad)",          { XX } },
6535     { "(bad)",          { XX } },
6536     { "(bad)",          { XX } },
6537     { "(bad)",          { XX } },
6538     { "(bad)",          { XX } },
6539     /* 80 */
6540     { "(bad)",          { XX } },
6541     { "(bad)",          { XX } },
6542     { "(bad)",          { XX } },
6543     { "(bad)",          { XX } },
6544     { "(bad)",          { XX } },
6545     { "vpmacssww",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6546     { "vpmacsswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6547     { "vpmacssdql",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6548     /* 88 */
6549     { "(bad)",          { XX } },
6550     { "(bad)",          { XX } },
6551     { "(bad)",          { XX } },
6552     { "(bad)",          { XX } },
6553     { "(bad)",          { XX } },
6554     { "(bad)",          { XX } },
6555     { "vpmacssdd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6556     { "vpmacssdqh",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6557     /* 90 */
6558     { "(bad)",          { XX } },
6559     { "(bad)",          { XX } },
6560     { "(bad)",          { XX } },
6561     { "(bad)",          { XX } },
6562     { "(bad)",          { XX } },
6563     { "vpmacsww",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6564     { "vpmacswd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6565     { "vpmacsdql",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6566     /* 98 */
6567     { "(bad)",          { XX } },
6568     { "(bad)",          { XX } },
6569     { "(bad)",          { XX } },
6570     { "(bad)",          { XX } },
6571     { "(bad)",          { XX } },
6572     { "(bad)",          { XX } },
6573     { "vpmacsdd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6574     { "vpmacsdqh",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6575     /* a0 */
6576     { "(bad)",          { XX } },
6577     { "(bad)",          { XX } },
6578     { "vpcmov",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6579     { "vpperm",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6580     { "(bad)",          { XX } },
6581     { "(bad)",          { XX } },
6582     { "vpmadcsswd",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6583     { "(bad)",          { XX } },
6584     /* a8 */
6585     { "(bad)",          { XX } },
6586     { "(bad)",          { XX } },
6587     { "(bad)",          { XX } },
6588     { "(bad)",          { XX } },
6589     { "(bad)",          { XX } },
6590     { "(bad)",          { XX } },
6591     { "(bad)",          { XX } },
6592     { "(bad)",          { XX } },
6593     /* b0 */
6594     { "(bad)",          { XX } },
6595     { "(bad)",          { XX } },
6596     { "(bad)",          { XX } },
6597     { "(bad)",          { XX } },
6598     { "(bad)",          { XX } },
6599     { "(bad)",          { XX } },
6600     { "vpmadcswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6601     { "(bad)",          { XX } },
6602     /* b8 */
6603     { "(bad)",          { XX } },
6604     { "(bad)",          { XX } },
6605     { "(bad)",          { XX } },
6606     { "(bad)",          { XX } },
6607     { "(bad)",          { XX } },
6608     { "(bad)",          { XX } },
6609     { "(bad)",          { XX } },
6610     { "(bad)",          { XX } },
6611     /* c0 */
6612     { "vprotb",         { XM, Vex_2src_1, Ib } },
6613     { "vprotw",         { XM, Vex_2src_1, Ib } },
6614     { "vprotd",         { XM, Vex_2src_1, Ib } },
6615     { "vprotq",         { XM, Vex_2src_1, Ib } },
6616     { "(bad)",          { XX } },
6617     { "(bad)",          { XX } },
6618     { "(bad)",          { XX } },
6619     { "(bad)",          { XX } },
6620     /* c8 */
6621     { "(bad)",          { XX } },
6622     { "(bad)",          { XX } },
6623     { "(bad)",          { XX } },
6624     { "(bad)",          { XX } },
6625     { "vpcomb",         { XM, Vex128, EXx, Ib } },
6626     { "vpcomw",         { XM, Vex128, EXx, Ib } },
6627     { "vpcomd",         { XM, Vex128, EXx, Ib } },
6628     { "vpcomq",         { XM, Vex128, EXx, Ib } },
6629     /* d0 */
6630     { "(bad)",          { XX } },
6631     { "(bad)",          { XX } },
6632     { "(bad)",          { XX } },
6633     { "(bad)",          { XX } },
6634     { "(bad)",          { XX } },
6635     { "(bad)",          { XX } },
6636     { "(bad)",          { XX } },
6637     { "(bad)",          { XX } },
6638     /* d8 */
6639     { "(bad)",          { XX } },
6640     { "(bad)",          { XX } },
6641     { "(bad)",          { XX } },
6642     { "(bad)",          { XX } },
6643     { "(bad)",          { XX } },
6644     { "(bad)",          { XX } },
6645     { "(bad)",          { XX } },
6646     { "(bad)",          { XX } },
6647     /* e0 */
6648     { "(bad)",          { XX } },
6649     { "(bad)",          { XX } },
6650     { "(bad)",          { XX } },
6651     { "(bad)",          { XX } },
6652     { "(bad)",          { XX } },
6653     { "(bad)",          { XX } },
6654     { "(bad)",          { XX } },
6655     { "(bad)",          { XX } },
6656     /* e8 */
6657     { "(bad)",          { XX } },
6658     { "(bad)",          { XX } },
6659     { "(bad)",          { XX } },
6660     { "(bad)",          { XX } },
6661     { "vpcomub",        { XM, Vex128, EXx, Ib } },
6662     { "vpcomuw",        { XM, Vex128, EXx, Ib } },
6663     { "vpcomud",        { XM, Vex128, EXx, Ib } },
6664     { "vpcomuq",        { XM, Vex128, EXx, Ib } },
6665     /* f0 */
6666     { "(bad)",          { XX } },
6667     { "(bad)",          { XX } },
6668     { "(bad)",          { XX } },
6669     { "(bad)",          { XX } },
6670     { "(bad)",          { XX } },
6671     { "(bad)",          { XX } },
6672     { "(bad)",          { XX } },
6673     { "(bad)",          { XX } },
6674     /* f8 */
6675     { "(bad)",          { XX } },
6676     { "(bad)",          { XX } },
6677     { "(bad)",          { XX } },
6678     { "(bad)",          { XX } },
6679     { "(bad)",          { XX } },
6680     { "(bad)",          { XX } },
6681     { "(bad)",          { XX } },
6682     { "(bad)",          { XX } },
6683   },
6684   /* XOP_09 */
6685   {
6686     /* 00 */
6687     { "(bad)",          { XX } },
6688     { "(bad)",          { XX } },
6689     { "(bad)",          { XX } },
6690     { "(bad)",          { XX } },
6691     { "(bad)",          { XX } },
6692     { "(bad)",          { XX } },
6693     { "(bad)",          { XX } },
6694     { "(bad)",          { XX } },
6695     /* 08 */
6696     { "(bad)",          { XX } },
6697     { "(bad)",          { XX } },
6698     { "(bad)",          { XX } },
6699     { "(bad)",          { XX } },
6700     { "(bad)",          { XX } },
6701     { "(bad)",          { XX } },
6702     { "(bad)",          { XX } },
6703     { "(bad)",          { XX } },
6704     /* 10 */
6705     { "(bad)",          { XX } },
6706     { "(bad)",          { XX } },
6707     { REG_TABLE (REG_XOP_LWPCB) },
6708     { "(bad)",          { XX } },
6709     { "(bad)",          { XX } },
6710     { "(bad)",          { XX } },
6711     { "(bad)",          { XX } },
6712     { "(bad)",          { XX } },
6713     /* 18 */
6714     { "(bad)",          { XX } },
6715     { "(bad)",          { XX } },
6716     { "(bad)",          { XX } },
6717     { "(bad)",          { XX } },
6718     { "(bad)",          { XX } },
6719     { "(bad)",          { XX } },
6720     { "(bad)",          { XX } },
6721     { "(bad)",          { XX } },
6722     /* 20 */
6723     { "(bad)",          { XX } },
6724     { "(bad)",          { XX } },
6725     { "(bad)",          { XX } },
6726     { "(bad)",          { XX } },
6727     { "(bad)",          { XX } },
6728     { "(bad)",          { XX } },
6729     { "(bad)",          { XX } },
6730     { "(bad)",          { XX } },
6731     /* 28 */
6732     { "(bad)",          { XX } },
6733     { "(bad)",          { XX } },
6734     { "(bad)",          { XX } },
6735     { "(bad)",          { XX } },
6736     { "(bad)",          { XX } },
6737     { "(bad)",          { XX } },
6738     { "(bad)",          { XX } },
6739     { "(bad)",          { XX } },
6740     /* 30 */
6741     { "(bad)",          { XX } },
6742     { "(bad)",          { XX } },
6743     { "(bad)",          { XX } },
6744     { "(bad)",          { XX } },
6745     { "(bad)",          { XX } },
6746     { "(bad)",          { XX } },
6747     { "(bad)",          { XX } },
6748     { "(bad)",          { XX } },
6749     /* 38 */
6750     { "(bad)",          { XX } },
6751     { "(bad)",          { XX } },
6752     { "(bad)",          { XX } },
6753     { "(bad)",          { XX } },
6754     { "(bad)",          { XX } },
6755     { "(bad)",          { XX } },
6756     { "(bad)",          { XX } },
6757     { "(bad)",          { XX } },
6758     /* 40 */
6759     { "(bad)",          { XX } },
6760     { "(bad)",          { XX } },
6761     { "(bad)",          { XX } },
6762     { "(bad)",          { XX } },
6763     { "(bad)",          { XX } },
6764     { "(bad)",          { XX } },
6765     { "(bad)",          { XX } },
6766     { "(bad)",          { XX } },
6767     /* 48 */
6768     { "(bad)",          { XX } },
6769     { "(bad)",          { XX } },
6770     { "(bad)",          { XX } },
6771     { "(bad)",          { XX } },
6772     { "(bad)",          { XX } },
6773     { "(bad)",          { XX } },
6774     { "(bad)",          { XX } },
6775     { "(bad)",          { XX } },
6776     /* 50 */
6777     { "(bad)",          { XX } },
6778     { "(bad)",          { XX } },
6779     { "(bad)",          { XX } },
6780     { "(bad)",          { XX } },
6781     { "(bad)",          { XX } },
6782     { "(bad)",          { XX } },
6783     { "(bad)",          { XX } },
6784     { "(bad)",          { XX } },
6785     /* 58 */
6786     { "(bad)",          { XX } },
6787     { "(bad)",          { XX } },
6788     { "(bad)",          { XX } },
6789     { "(bad)",          { XX } },
6790     { "(bad)",          { XX } },
6791     { "(bad)",          { XX } },
6792     { "(bad)",          { XX } },
6793     { "(bad)",          { XX } },
6794     /* 60 */
6795     { "(bad)",          { XX } },
6796     { "(bad)",          { XX } },
6797     { "(bad)",          { XX } },
6798     { "(bad)",          { XX } },
6799     { "(bad)",          { XX } },
6800     { "(bad)",          { XX } },
6801     { "(bad)",          { XX } },
6802     { "(bad)",          { XX } },
6803     /* 68 */
6804     { "(bad)",          { XX } },
6805     { "(bad)",          { XX } },
6806     { "(bad)",          { XX } },
6807     { "(bad)",          { XX } },
6808     { "(bad)",          { XX } },
6809     { "(bad)",          { XX } },
6810     { "(bad)",          { XX } },
6811     { "(bad)",          { XX } },
6812     /* 70 */
6813     { "(bad)",          { XX } },
6814     { "(bad)",          { XX } },
6815     { "(bad)",          { XX } },
6816     { "(bad)",          { XX } },
6817     { "(bad)",          { XX } },
6818     { "(bad)",          { XX } },
6819     { "(bad)",          { XX } },
6820     { "(bad)",          { XX } },
6821     /* 78 */
6822     { "(bad)",          { XX } },
6823     { "(bad)",          { XX } },
6824     { "(bad)",          { XX } },
6825     { "(bad)",          { XX } },
6826     { "(bad)",          { XX } },
6827     { "(bad)",          { XX } },
6828     { "(bad)",          { XX } },
6829     { "(bad)",          { XX } },
6830     /* 80 */
6831     { VEX_LEN_TABLE (VEX_LEN_XOP_09_80) },
6832     { VEX_LEN_TABLE (VEX_LEN_XOP_09_81) },
6833     { "vfrczss",        { XM, EXd } },
6834     { "vfrczsd",        { XM, EXq } },
6835     { "(bad)",          { XX } },
6836     { "(bad)",          { XX } },
6837     { "(bad)",          { XX } },
6838     { "(bad)",          { XX } },
6839     /* 88 */
6840     { "(bad)",          { XX } },
6841     { "(bad)",          { XX } },
6842     { "(bad)",          { XX } },
6843     { "(bad)",          { XX } },
6844     { "(bad)",          { XX } },
6845     { "(bad)",          { XX } },
6846     { "(bad)",          { XX } },
6847     { "(bad)",          { XX } },
6848     /* 90 */
6849     { "vprotb",         { XM, Vex_2src_1, Vex_2src_2 } },
6850     { "vprotw",         { XM, Vex_2src_1, Vex_2src_2 } },
6851     { "vprotd",         { XM, Vex_2src_1, Vex_2src_2 } },
6852     { "vprotq",         { XM, Vex_2src_1, Vex_2src_2 } },
6853     { "vpshlb",         { XM, Vex_2src_1, Vex_2src_2 } },
6854     { "vpshlw",         { XM, Vex_2src_1, Vex_2src_2 } },
6855     { "vpshld",         { XM, Vex_2src_1, Vex_2src_2 } },
6856     { "vpshlq",         { XM, Vex_2src_1, Vex_2src_2 } },
6857     /* 98 */
6858     { "vpshab",         { XM, Vex_2src_1, Vex_2src_2 } },
6859     { "vpshaw",         { XM, Vex_2src_1, Vex_2src_2 } },
6860     { "vpshad",         { XM, Vex_2src_1, Vex_2src_2 } },
6861     { "vpshaq",         { XM, Vex_2src_1, Vex_2src_2 } },
6862     { "(bad)",          { XX } },
6863     { "(bad)",          { XX } },
6864     { "(bad)",          { XX } },
6865     { "(bad)",          { XX } },
6866     /* a0 */
6867     { "(bad)",          { XX } },
6868     { "(bad)",          { XX } },
6869     { "(bad)",          { XX } },
6870     { "(bad)",          { XX } },
6871     { "(bad)",          { XX } },
6872     { "(bad)",          { XX } },
6873     { "(bad)",          { XX } },
6874     { "(bad)",          { XX } },
6875     /* a8 */
6876     { "(bad)",          { XX } },
6877     { "(bad)",          { XX } },
6878     { "(bad)",          { XX } },
6879     { "(bad)",          { XX } },
6880     { "(bad)",          { XX } },
6881     { "(bad)",          { XX } },
6882     { "(bad)",          { XX } },
6883     { "(bad)",          { XX } },
6884     /* b0 */
6885     { "(bad)",          { XX } },
6886     { "(bad)",          { XX } },
6887     { "(bad)",          { XX } },
6888     { "(bad)",          { XX } },
6889     { "(bad)",          { XX } },
6890     { "(bad)",          { XX } },
6891     { "(bad)",          { XX } },
6892     { "(bad)",          { XX } },
6893     /* b8 */
6894     { "(bad)",          { XX } },
6895     { "(bad)",          { XX } },
6896     { "(bad)",          { XX } },
6897     { "(bad)",          { XX } },
6898     { "(bad)",          { XX } },
6899     { "(bad)",          { XX } },
6900     { "(bad)",          { XX } },
6901     { "(bad)",          { XX } },
6902     /* c0 */
6903     { "(bad)",          { XX } },
6904     { "vphaddbw",       { XM, EXxmm } },
6905     { "vphaddbd",       { XM, EXxmm } },
6906     { "vphaddbq",       { XM, EXxmm } },
6907     { "(bad)",          { XX } },
6908     { "(bad)",          { XX } },
6909     { "vphaddwd",       { XM, EXxmm } },
6910     { "vphaddwq",       { XM, EXxmm } },
6911     /* c8 */
6912     { "(bad)",          { XX } },
6913     { "(bad)",          { XX } },
6914     { "(bad)",          { XX } },
6915     { "vphadddq",       { XM, EXxmm } },
6916     { "(bad)",          { XX } },
6917     { "(bad)",          { XX } },
6918     { "(bad)",          { XX } },
6919     { "(bad)",          { XX } },
6920     /* d0 */
6921     { "(bad)",          { XX } },
6922     { "vphaddubw",      { XM, EXxmm } },
6923     { "vphaddubd",      { XM, EXxmm } },
6924     { "vphaddubq",      { XM, EXxmm } },
6925     { "(bad)",          { XX } },
6926     { "(bad)",          { XX } },
6927     { "vphadduwd",      { XM, EXxmm } },
6928     { "vphadduwq",      { XM, EXxmm } },
6929     /* d8 */
6930     { "(bad)",          { XX } },
6931     { "(bad)",          { XX } },
6932     { "(bad)",          { XX } },
6933     { "vphaddudq",      { XM, EXxmm } },
6934     { "(bad)",          { XX } },
6935     { "(bad)",          { XX } },
6936     { "(bad)",          { XX } },
6937     { "(bad)",          { XX } },
6938     /* e0 */
6939     { "(bad)",          { XX } },
6940     { "vphsubbw",       { XM, EXxmm } },
6941     { "vphsubwd",       { XM, EXxmm } },
6942     { "vphsubdq",       { XM, EXxmm } },
6943     { "(bad)",          { XX } },
6944     { "(bad)",          { XX } },
6945     { "(bad)",          { XX } },
6946     { "(bad)",          { XX } },
6947     /* e8 */
6948     { "(bad)",          { XX } },
6949     { "(bad)",          { XX } },
6950     { "(bad)",          { XX } },
6951     { "(bad)",          { XX } },
6952     { "(bad)",          { XX } },
6953     { "(bad)",          { XX } },
6954     { "(bad)",          { XX } },
6955     { "(bad)",          { XX } },
6956     /* f0 */
6957     { "(bad)",          { XX } },
6958     { "(bad)",          { XX } },
6959     { "(bad)",          { XX } },
6960     { "(bad)",          { XX } },
6961     { "(bad)",          { XX } },
6962     { "(bad)",          { XX } },
6963     { "(bad)",          { XX } },
6964     { "(bad)",          { XX } },
6965     /* f8 */
6966     { "(bad)",          { XX } },
6967     { "(bad)",          { XX } },
6968     { "(bad)",          { XX } },
6969     { "(bad)",          { XX } },
6970     { "(bad)",          { XX } },
6971     { "(bad)",          { XX } },
6972     { "(bad)",          { XX } },
6973     { "(bad)",          { XX } },
6974   },
6975   /* XOP_0A */
6976   {
6977     /* 00 */
6978     { "(bad)",          { XX } },
6979     { "(bad)",          { XX } },
6980     { "(bad)",          { XX } },
6981     { "(bad)",          { XX } },
6982     { "(bad)",          { XX } },
6983     { "(bad)",          { XX } },
6984     { "(bad)",          { XX } },
6985     { "(bad)",          { XX } },
6986     /* 08 */
6987     { "(bad)",          { XX } },
6988     { "(bad)",          { XX } },
6989     { "(bad)",          { XX } },
6990     { "(bad)",          { XX } },
6991     { "(bad)",          { XX } },
6992     { "(bad)",          { XX } },
6993     { "(bad)",          { XX } },
6994     { "(bad)",          { XX } },
6995     /* 10 */
6996     { "(bad)",          { XX } },
6997     { "(bad)",          { XX } },
6998     { REG_TABLE (REG_XOP_LWP) },
6999     { "(bad)",          { XX } },
7000     { "(bad)",          { XX } },
7001     { "(bad)",          { XX } },
7002     { "(bad)",          { XX } },
7003     { "(bad)",          { XX } },
7004     /* 18 */
7005     { "(bad)",          { XX } },
7006     { "(bad)",          { XX } },
7007     { "(bad)",          { XX } },
7008     { "(bad)",          { XX } },
7009     { "(bad)",          { XX } },
7010     { "(bad)",          { XX } },
7011     { "(bad)",          { XX } },
7012     { "(bad)",          { XX } },
7013     /* 20 */
7014     { "(bad)",          { XX } },
7015     { "(bad)",          { XX } },
7016     { "(bad)",          { XX } },
7017     { "(bad)",          { XX } },
7018     { "(bad)",          { XX } },
7019     { "(bad)",          { XX } },
7020     { "(bad)",          { XX } },
7021     { "(bad)",          { XX } },
7022     /* 28 */
7023     { "(bad)",          { XX } },
7024     { "(bad)",          { XX } },
7025     { "(bad)",          { XX } },
7026     { "(bad)",          { XX } },
7027     { "(bad)",          { XX } },
7028     { "(bad)",          { XX } },
7029     { "(bad)",          { XX } },
7030     { "(bad)",          { XX } },
7031     /* 30 */
7032     { "(bad)",          { XX } },
7033     { "(bad)",          { XX } },
7034     { "(bad)",          { XX } },
7035     { "(bad)",          { XX } },
7036     { "(bad)",          { XX } },
7037     { "(bad)",          { XX } },
7038     { "(bad)",          { XX } },
7039     { "(bad)",          { XX } },
7040     /* 38 */
7041     { "(bad)",          { XX } },
7042     { "(bad)",          { XX } },
7043     { "(bad)",          { XX } },
7044     { "(bad)",          { XX } },
7045     { "(bad)",          { XX } },
7046     { "(bad)",          { XX } },
7047     { "(bad)",          { XX } },
7048     { "(bad)",          { XX } },
7049     /* 40 */
7050     { "(bad)",          { XX } },
7051     { "(bad)",          { XX } },
7052     { "(bad)",          { XX } },
7053     { "(bad)",          { XX } },
7054     { "(bad)",          { XX } },
7055     { "(bad)",          { XX } },
7056     { "(bad)",          { XX } },
7057     { "(bad)",          { XX } },
7058     /* 48 */
7059     { "(bad)",          { XX } },
7060     { "(bad)",          { XX } },
7061     { "(bad)",          { XX } },
7062     { "(bad)",          { XX } },
7063     { "(bad)",          { XX } },
7064     { "(bad)",          { XX } },
7065     { "(bad)",          { XX } },
7066     { "(bad)",          { XX } },
7067     /* 50 */
7068     { "(bad)",          { XX } },
7069     { "(bad)",          { XX } },
7070     { "(bad)",          { XX } },
7071     { "(bad)",          { XX } },
7072     { "(bad)",          { XX } },
7073     { "(bad)",          { XX } },
7074     { "(bad)",          { XX } },
7075     { "(bad)",          { XX } },
7076     /* 58 */
7077     { "(bad)",          { XX } },
7078     { "(bad)",          { XX } },
7079     { "(bad)",          { XX } },
7080     { "(bad)",          { XX } },
7081     { "(bad)",          { XX } },
7082     { "(bad)",          { XX } },
7083     { "(bad)",          { XX } },
7084     { "(bad)",          { XX } },
7085     /* 60 */
7086     { "(bad)",          { XX } },
7087     { "(bad)",          { XX } },
7088     { "(bad)",          { XX } },
7089     { "(bad)",          { XX } },
7090     { "(bad)",          { XX } },
7091     { "(bad)",          { XX } },
7092     { "(bad)",          { XX } },
7093     { "(bad)",          { XX } },
7094     /* 68 */
7095     { "(bad)",          { XX } },
7096     { "(bad)",          { XX } },
7097     { "(bad)",          { XX } },
7098     { "(bad)",          { XX } },
7099     { "(bad)",          { XX } },
7100     { "(bad)",          { XX } },
7101     { "(bad)",          { XX } },
7102     { "(bad)",          { XX } },
7103     /* 70 */
7104     { "(bad)",          { XX } },
7105     { "(bad)",          { XX } },
7106     { "(bad)",          { XX } },
7107     { "(bad)",          { XX } },
7108     { "(bad)",          { XX } },
7109     { "(bad)",          { XX } },
7110     { "(bad)",          { XX } },
7111     { "(bad)",          { XX } },
7112     /* 78 */
7113     { "(bad)",          { XX } },
7114     { "(bad)",          { XX } },
7115     { "(bad)",          { XX } },
7116     { "(bad)",          { XX } },
7117     { "(bad)",          { XX } },
7118     { "(bad)",          { XX } },
7119     { "(bad)",          { XX } },
7120     { "(bad)",          { XX } },
7121     /* 80 */
7122     { "(bad)",          { XX } },
7123     { "(bad)",          { XX } },
7124     { "(bad)",          { XX } },
7125     { "(bad)",          { XX } },
7126     { "(bad)",          { XX } },
7127     { "(bad)",          { XX } },
7128     { "(bad)",          { XX } },
7129     { "(bad)",          { XX } },
7130     /* 88 */
7131     { "(bad)",          { XX } },
7132     { "(bad)",          { XX } },
7133     { "(bad)",          { XX } },
7134     { "(bad)",          { XX } },
7135     { "(bad)",          { XX } },
7136     { "(bad)",          { XX } },
7137     { "(bad)",          { XX } },
7138     { "(bad)",          { XX } },
7139     /* 90 */
7140     { "(bad)",          { XX } },
7141     { "(bad)",          { XX } },
7142     { "(bad)",          { XX } },
7143     { "(bad)",          { XX } },
7144     { "(bad)",          { XX } },
7145     { "(bad)",          { XX } },
7146     { "(bad)",          { XX } },
7147     { "(bad)",          { XX } },
7148     /* 98 */
7149     { "(bad)",          { XX } },
7150     { "(bad)",          { XX } },
7151     { "(bad)",          { XX } },
7152     { "(bad)",          { XX } },
7153     { "(bad)",          { XX } },
7154     { "(bad)",          { XX } },
7155     { "(bad)",          { XX } },
7156     { "(bad)",          { XX } },
7157     /* a0 */
7158     { "(bad)",          { XX } },
7159     { "(bad)",          { XX } },
7160     { "(bad)",          { XX } },
7161     { "(bad)",          { XX } },
7162     { "(bad)",          { XX } },
7163     { "(bad)",          { XX } },
7164     { "(bad)",          { XX } },
7165     { "(bad)",          { XX } },
7166     /* a8 */
7167     { "(bad)",          { XX } },
7168     { "(bad)",          { XX } },
7169     { "(bad)",          { XX } },
7170     { "(bad)",          { XX } },
7171     { "(bad)",          { XX } },
7172     { "(bad)",          { XX } },
7173     { "(bad)",          { XX } },
7174     { "(bad)",          { XX } },
7175     /* b0 */
7176     { "(bad)",          { XX } },
7177     { "(bad)",          { XX } },
7178     { "(bad)",          { XX } },
7179     { "(bad)",          { XX } },
7180     { "(bad)",          { XX } },
7181     { "(bad)",          { XX } },
7182     { "(bad)",          { XX } },
7183     { "(bad)",          { XX } },
7184     /* b8 */
7185     { "(bad)",          { XX } },
7186     { "(bad)",          { XX } },
7187     { "(bad)",          { XX } },
7188     { "(bad)",          { XX } },
7189     { "(bad)",          { XX } },
7190     { "(bad)",          { XX } },
7191     { "(bad)",          { XX } },
7192     { "(bad)",          { XX } },
7193     /* c0 */
7194     { "(bad)",          { XX } },
7195     { "(bad)",          { XX } },
7196     { "(bad)",          { XX } },
7197     { "(bad)",          { XX } },
7198     { "(bad)",          { XX } },
7199     { "(bad)",          { XX } },
7200     { "(bad)",          { XX } },
7201     { "(bad)",          { XX } },
7202     /* c8 */
7203     { "(bad)",          { XX } },
7204     { "(bad)",          { XX } },
7205     { "(bad)",          { XX } },
7206     { "(bad)",          { XX } },
7207     { "(bad)",          { XX } },
7208     { "(bad)",          { XX } },
7209     { "(bad)",          { XX } },
7210     { "(bad)",          { XX } },
7211     /* d0 */
7212     { "(bad)",          { XX } },
7213     { "(bad)",          { XX } },
7214     { "(bad)",          { XX } },
7215     { "(bad)",          { XX } },
7216     { "(bad)",          { XX } },
7217     { "(bad)",          { XX } },
7218     { "(bad)",          { XX } },
7219     { "(bad)",          { XX } },
7220     /* d8 */
7221     { "(bad)",          { XX } },
7222     { "(bad)",          { XX } },
7223     { "(bad)",          { XX } },
7224     { "(bad)",          { XX } },
7225     { "(bad)",          { XX } },
7226     { "(bad)",          { XX } },
7227     { "(bad)",          { XX } },
7228     { "(bad)",          { XX } },
7229     /* e0 */
7230     { "(bad)",          { XX } },
7231     { "(bad)",          { XX } },
7232     { "(bad)",          { XX } },
7233     { "(bad)",          { XX } },
7234     { "(bad)",          { XX } },
7235     { "(bad)",          { XX } },
7236     { "(bad)",          { XX } },
7237     { "(bad)",          { XX } },
7238     /* e8 */
7239     { "(bad)",          { XX } },
7240     { "(bad)",          { XX } },
7241     { "(bad)",          { XX } },
7242     { "(bad)",          { XX } },
7243     { "(bad)",          { XX } },
7244     { "(bad)",          { XX } },
7245     { "(bad)",          { XX } },
7246     { "(bad)",          { XX } },
7247     /* f0 */
7248     { "(bad)",          { XX } },
7249     { "(bad)",          { XX } },
7250     { "(bad)",          { XX } },
7251     { "(bad)",          { XX } },
7252     { "(bad)",          { XX } },
7253     { "(bad)",          { XX } },
7254     { "(bad)",          { XX } },
7255     { "(bad)",          { XX } },
7256     /* f8 */
7257     { "(bad)",          { XX } },
7258     { "(bad)",          { XX } },
7259     { "(bad)",          { XX } },
7260     { "(bad)",          { XX } },
7261     { "(bad)",          { XX } },
7262     { "(bad)",          { XX } },
7263     { "(bad)",          { XX } },
7264     { "(bad)",          { XX } },
7265   },
7266 };
7267
7268 static const struct dis386 vex_table[][256] = {
7269   /* VEX_0F */
7270   {
7271     /* 00 */
7272     { "(bad)",          { XX } },
7273     { "(bad)",          { XX } },
7274     { "(bad)",          { XX } },
7275     { "(bad)",          { XX } },
7276     { "(bad)",          { XX } },
7277     { "(bad)",          { XX } },
7278     { "(bad)",          { XX } },
7279     { "(bad)",          { XX } },
7280     /* 08 */
7281     { "(bad)",          { XX } },
7282     { "(bad)",          { XX } },
7283     { "(bad)",          { XX } },
7284     { "(bad)",          { XX } },
7285     { "(bad)",          { XX } },
7286     { "(bad)",          { XX } },
7287     { "(bad)",          { XX } },
7288     { "(bad)",          { XX } },
7289     /* 10 */
7290     { PREFIX_TABLE (PREFIX_VEX_10) },
7291     { PREFIX_TABLE (PREFIX_VEX_11) },
7292     { PREFIX_TABLE (PREFIX_VEX_12) },
7293     { MOD_TABLE (MOD_VEX_13) },
7294     { "vunpcklpX",      { XM, Vex, EXx } },
7295     { "vunpckhpX",      { XM, Vex, EXx } },
7296     { PREFIX_TABLE (PREFIX_VEX_16) },
7297     { MOD_TABLE (MOD_VEX_17) },
7298     /* 18 */
7299     { "(bad)",          { XX } },
7300     { "(bad)",          { XX } },
7301     { "(bad)",          { XX } },
7302     { "(bad)",          { XX } },
7303     { "(bad)",          { XX } },
7304     { "(bad)",          { XX } },
7305     { "(bad)",          { XX } },
7306     { "(bad)",          { XX } },
7307     /* 20 */
7308     { "(bad)",          { XX } },
7309     { "(bad)",          { XX } },
7310     { "(bad)",          { XX } },
7311     { "(bad)",          { XX } },
7312     { "(bad)",          { XX } },
7313     { "(bad)",          { XX } },
7314     { "(bad)",          { XX } },
7315     { "(bad)",          { XX } },
7316     /* 28 */
7317     { "vmovapX",        { XM, EXx } },
7318     { "vmovapX",        { EXxS, XM } },
7319     { PREFIX_TABLE (PREFIX_VEX_2A) },
7320     { MOD_TABLE (MOD_VEX_2B) },
7321     { PREFIX_TABLE (PREFIX_VEX_2C) },
7322     { PREFIX_TABLE (PREFIX_VEX_2D) },
7323     { PREFIX_TABLE (PREFIX_VEX_2E) },
7324     { PREFIX_TABLE (PREFIX_VEX_2F) },
7325     /* 30 */
7326     { "(bad)",          { XX } },
7327     { "(bad)",          { XX } },
7328     { "(bad)",          { XX } },
7329     { "(bad)",          { XX } },
7330     { "(bad)",          { XX } },
7331     { "(bad)",          { XX } },
7332     { "(bad)",          { XX } },
7333     { "(bad)",          { XX } },
7334     /* 38 */
7335     { "(bad)",          { XX } },
7336     { "(bad)",          { XX } },
7337     { "(bad)",          { XX } },
7338     { "(bad)",          { XX } },
7339     { "(bad)",          { XX } },
7340     { "(bad)",          { XX } },
7341     { "(bad)",          { XX } },
7342     { "(bad)",          { XX } },
7343     /* 40 */
7344     { "(bad)",          { XX } },
7345     { "(bad)",          { XX } },
7346     { "(bad)",          { XX } },
7347     { "(bad)",          { XX } },
7348     { "(bad)",          { XX } },
7349     { "(bad)",          { XX } },
7350     { "(bad)",          { XX } },
7351     { "(bad)",          { XX } },
7352     /* 48 */
7353     { "(bad)",          { XX } },
7354     { "(bad)",          { XX } },
7355     { "(bad)",          { XX } },
7356     { "(bad)",          { XX } },
7357     { "(bad)",          { XX } },
7358     { "(bad)",          { XX } },
7359     { "(bad)",          { XX } },
7360     { "(bad)",          { XX } },
7361     /* 50 */
7362     { MOD_TABLE (MOD_VEX_50) },
7363     { PREFIX_TABLE (PREFIX_VEX_51) },
7364     { PREFIX_TABLE (PREFIX_VEX_52) },
7365     { PREFIX_TABLE (PREFIX_VEX_53) },
7366     { "vandpX",         { XM, Vex, EXx } },
7367     { "vandnpX",        { XM, Vex, EXx } },
7368     { "vorpX",          { XM, Vex, EXx } },
7369     { "vxorpX",         { XM, Vex, EXx } },
7370     /* 58 */
7371     { PREFIX_TABLE (PREFIX_VEX_58) },
7372     { PREFIX_TABLE (PREFIX_VEX_59) },
7373     { PREFIX_TABLE (PREFIX_VEX_5A) },
7374     { PREFIX_TABLE (PREFIX_VEX_5B) },
7375     { PREFIX_TABLE (PREFIX_VEX_5C) },
7376     { PREFIX_TABLE (PREFIX_VEX_5D) },
7377     { PREFIX_TABLE (PREFIX_VEX_5E) },
7378     { PREFIX_TABLE (PREFIX_VEX_5F) },
7379     /* 60 */
7380     { PREFIX_TABLE (PREFIX_VEX_60) },
7381     { PREFIX_TABLE (PREFIX_VEX_61) },
7382     { PREFIX_TABLE (PREFIX_VEX_62) },
7383     { PREFIX_TABLE (PREFIX_VEX_63) },
7384     { PREFIX_TABLE (PREFIX_VEX_64) },
7385     { PREFIX_TABLE (PREFIX_VEX_65) },
7386     { PREFIX_TABLE (PREFIX_VEX_66) },
7387     { PREFIX_TABLE (PREFIX_VEX_67) },
7388     /* 68 */
7389     { PREFIX_TABLE (PREFIX_VEX_68) },
7390     { PREFIX_TABLE (PREFIX_VEX_69) },
7391     { PREFIX_TABLE (PREFIX_VEX_6A) },
7392     { PREFIX_TABLE (PREFIX_VEX_6B) },
7393     { PREFIX_TABLE (PREFIX_VEX_6C) },
7394     { PREFIX_TABLE (PREFIX_VEX_6D) },
7395     { PREFIX_TABLE (PREFIX_VEX_6E) },
7396     { PREFIX_TABLE (PREFIX_VEX_6F) },
7397     /* 70 */
7398     { PREFIX_TABLE (PREFIX_VEX_70) },
7399     { REG_TABLE (REG_VEX_71) },
7400     { REG_TABLE (REG_VEX_72) },
7401     { REG_TABLE (REG_VEX_73) },
7402     { PREFIX_TABLE (PREFIX_VEX_74) },
7403     { PREFIX_TABLE (PREFIX_VEX_75) },
7404     { PREFIX_TABLE (PREFIX_VEX_76) },
7405     { PREFIX_TABLE (PREFIX_VEX_77) },
7406     /* 78 */
7407     { "(bad)",          { XX } },
7408     { "(bad)",          { XX } },
7409     { "(bad)",          { XX } },
7410     { "(bad)",          { XX } },
7411     { PREFIX_TABLE (PREFIX_VEX_7C) },
7412     { PREFIX_TABLE (PREFIX_VEX_7D) },
7413     { PREFIX_TABLE (PREFIX_VEX_7E) },
7414     { PREFIX_TABLE (PREFIX_VEX_7F) },
7415     /* 80 */
7416     { "(bad)",          { XX } },
7417     { "(bad)",          { XX } },
7418     { "(bad)",          { XX } },
7419     { "(bad)",          { XX } },
7420     { "(bad)",          { XX } },
7421     { "(bad)",          { XX } },
7422     { "(bad)",          { XX } },
7423     { "(bad)",          { XX } },
7424     /* 88 */
7425     { "(bad)",          { XX } },
7426     { "(bad)",          { XX } },
7427     { "(bad)",          { XX } },
7428     { "(bad)",          { XX } },
7429     { "(bad)",          { XX } },
7430     { "(bad)",          { XX } },
7431     { "(bad)",          { XX } },
7432     { "(bad)",          { XX } },
7433     /* 90 */
7434     { "(bad)",          { XX } },
7435     { "(bad)",          { XX } },
7436     { "(bad)",          { XX } },
7437     { "(bad)",          { XX } },
7438     { "(bad)",          { XX } },
7439     { "(bad)",          { XX } },
7440     { "(bad)",          { XX } },
7441     { "(bad)",          { XX } },
7442     /* 98 */
7443     { "(bad)",          { XX } },
7444     { "(bad)",          { XX } },
7445     { "(bad)",          { XX } },
7446     { "(bad)",          { XX } },
7447     { "(bad)",          { XX } },
7448     { "(bad)",          { XX } },
7449     { "(bad)",          { XX } },
7450     { "(bad)",          { XX } },
7451     /* a0 */
7452     { "(bad)",          { XX } },
7453     { "(bad)",          { XX } },
7454     { "(bad)",          { XX } },
7455     { "(bad)",          { XX } },
7456     { "(bad)",          { XX } },
7457     { "(bad)",          { XX } },
7458     { "(bad)",          { XX } },
7459     { "(bad)",          { XX } },
7460     /* a8 */
7461     { "(bad)",          { XX } },
7462     { "(bad)",          { XX } },
7463     { "(bad)",          { XX } },
7464     { "(bad)",          { XX } },
7465     { "(bad)",          { XX } },
7466     { "(bad)",          { XX } },
7467     { REG_TABLE (REG_VEX_AE) },
7468     { "(bad)",          { XX } },
7469     /* b0 */
7470     { "(bad)",          { XX } },
7471     { "(bad)",          { XX } },
7472     { "(bad)",          { XX } },
7473     { "(bad)",          { XX } },
7474     { "(bad)",          { XX } },
7475     { "(bad)",          { XX } },
7476     { "(bad)",          { XX } },
7477     { "(bad)",          { XX } },
7478     /* b8 */
7479     { "(bad)",          { XX } },
7480     { "(bad)",          { XX } },
7481     { "(bad)",          { XX } },
7482     { "(bad)",          { XX } },
7483     { "(bad)",          { XX } },
7484     { "(bad)",          { XX } },
7485     { "(bad)",          { XX } },
7486     { "(bad)",          { XX } },
7487     /* c0 */
7488     { "(bad)",          { XX } },
7489     { "(bad)",          { XX } },
7490     { PREFIX_TABLE (PREFIX_VEX_C2) },
7491     { "(bad)",          { XX } },
7492     { PREFIX_TABLE (PREFIX_VEX_C4) },
7493     { PREFIX_TABLE (PREFIX_VEX_C5) },
7494     { "vshufpX",        { XM, Vex, EXx, Ib } },
7495     { "(bad)",          { XX } },
7496     /* c8 */
7497     { "(bad)",          { XX } },
7498     { "(bad)",          { XX } },
7499     { "(bad)",          { XX } },
7500     { "(bad)",          { XX } },
7501     { "(bad)",          { XX } },
7502     { "(bad)",          { XX } },
7503     { "(bad)",          { XX } },
7504     { "(bad)",          { XX } },
7505     /* d0 */
7506     { PREFIX_TABLE (PREFIX_VEX_D0) },
7507     { PREFIX_TABLE (PREFIX_VEX_D1) },
7508     { PREFIX_TABLE (PREFIX_VEX_D2) },
7509     { PREFIX_TABLE (PREFIX_VEX_D3) },
7510     { PREFIX_TABLE (PREFIX_VEX_D4) },
7511     { PREFIX_TABLE (PREFIX_VEX_D5) },
7512     { PREFIX_TABLE (PREFIX_VEX_D6) },
7513     { PREFIX_TABLE (PREFIX_VEX_D7) },
7514     /* d8 */
7515     { PREFIX_TABLE (PREFIX_VEX_D8) },
7516     { PREFIX_TABLE (PREFIX_VEX_D9) },
7517     { PREFIX_TABLE (PREFIX_VEX_DA) },
7518     { PREFIX_TABLE (PREFIX_VEX_DB) },
7519     { PREFIX_TABLE (PREFIX_VEX_DC) },
7520     { PREFIX_TABLE (PREFIX_VEX_DD) },
7521     { PREFIX_TABLE (PREFIX_VEX_DE) },
7522     { PREFIX_TABLE (PREFIX_VEX_DF) },
7523     /* e0 */
7524     { PREFIX_TABLE (PREFIX_VEX_E0) },
7525     { PREFIX_TABLE (PREFIX_VEX_E1) },
7526     { PREFIX_TABLE (PREFIX_VEX_E2) },
7527     { PREFIX_TABLE (PREFIX_VEX_E3) },
7528     { PREFIX_TABLE (PREFIX_VEX_E4) },
7529     { PREFIX_TABLE (PREFIX_VEX_E5) },
7530     { PREFIX_TABLE (PREFIX_VEX_E6) },
7531     { PREFIX_TABLE (PREFIX_VEX_E7) },
7532     /* e8 */
7533     { PREFIX_TABLE (PREFIX_VEX_E8) },
7534     { PREFIX_TABLE (PREFIX_VEX_E9) },
7535     { PREFIX_TABLE (PREFIX_VEX_EA) },
7536     { PREFIX_TABLE (PREFIX_VEX_EB) },
7537     { PREFIX_TABLE (PREFIX_VEX_EC) },
7538     { PREFIX_TABLE (PREFIX_VEX_ED) },
7539     { PREFIX_TABLE (PREFIX_VEX_EE) },
7540     { PREFIX_TABLE (PREFIX_VEX_EF) },
7541     /* f0 */
7542     { PREFIX_TABLE (PREFIX_VEX_F0) },
7543     { PREFIX_TABLE (PREFIX_VEX_F1) },
7544     { PREFIX_TABLE (PREFIX_VEX_F2) },
7545     { PREFIX_TABLE (PREFIX_VEX_F3) },
7546     { PREFIX_TABLE (PREFIX_VEX_F4) },
7547     { PREFIX_TABLE (PREFIX_VEX_F5) },
7548     { PREFIX_TABLE (PREFIX_VEX_F6) },
7549     { PREFIX_TABLE (PREFIX_VEX_F7) },
7550     /* f8 */
7551     { PREFIX_TABLE (PREFIX_VEX_F8) },
7552     { PREFIX_TABLE (PREFIX_VEX_F9) },
7553     { PREFIX_TABLE (PREFIX_VEX_FA) },
7554     { PREFIX_TABLE (PREFIX_VEX_FB) },
7555     { PREFIX_TABLE (PREFIX_VEX_FC) },
7556     { PREFIX_TABLE (PREFIX_VEX_FD) },
7557     { PREFIX_TABLE (PREFIX_VEX_FE) },
7558     { "(bad)",          { XX } },
7559   },
7560   /* VEX_0F38 */
7561   {
7562     /* 00 */
7563     { PREFIX_TABLE (PREFIX_VEX_3800) },
7564     { PREFIX_TABLE (PREFIX_VEX_3801) },
7565     { PREFIX_TABLE (PREFIX_VEX_3802) },
7566     { PREFIX_TABLE (PREFIX_VEX_3803) },
7567     { PREFIX_TABLE (PREFIX_VEX_3804) },
7568     { PREFIX_TABLE (PREFIX_VEX_3805) },
7569     { PREFIX_TABLE (PREFIX_VEX_3806) },
7570     { PREFIX_TABLE (PREFIX_VEX_3807) },
7571     /* 08 */
7572     { PREFIX_TABLE (PREFIX_VEX_3808) },
7573     { PREFIX_TABLE (PREFIX_VEX_3809) },
7574     { PREFIX_TABLE (PREFIX_VEX_380A) },
7575     { PREFIX_TABLE (PREFIX_VEX_380B) },
7576     { PREFIX_TABLE (PREFIX_VEX_380C) },
7577     { PREFIX_TABLE (PREFIX_VEX_380D) },
7578     { PREFIX_TABLE (PREFIX_VEX_380E) },
7579     { PREFIX_TABLE (PREFIX_VEX_380F) },
7580     /* 10 */
7581     { "(bad)",          { XX } },
7582     { "(bad)",          { XX } },
7583     { "(bad)",          { XX } },
7584     { "(bad)",          { XX } },
7585     { "(bad)",          { XX } },
7586     { "(bad)",          { XX } },
7587     { "(bad)",          { XX } },
7588     { PREFIX_TABLE (PREFIX_VEX_3817) },
7589     /* 18 */
7590     { PREFIX_TABLE (PREFIX_VEX_3818) },
7591     { PREFIX_TABLE (PREFIX_VEX_3819) },
7592     { PREFIX_TABLE (PREFIX_VEX_381A) },
7593     { "(bad)",          { XX } },
7594     { PREFIX_TABLE (PREFIX_VEX_381C) },
7595     { PREFIX_TABLE (PREFIX_VEX_381D) },
7596     { PREFIX_TABLE (PREFIX_VEX_381E) },
7597     { "(bad)",          { XX } },
7598     /* 20 */
7599     { PREFIX_TABLE (PREFIX_VEX_3820) },
7600     { PREFIX_TABLE (PREFIX_VEX_3821) },
7601     { PREFIX_TABLE (PREFIX_VEX_3822) },
7602     { PREFIX_TABLE (PREFIX_VEX_3823) },
7603     { PREFIX_TABLE (PREFIX_VEX_3824) },
7604     { PREFIX_TABLE (PREFIX_VEX_3825) },
7605     { "(bad)",          { XX } },
7606     { "(bad)",          { XX } },
7607     /* 28 */
7608     { PREFIX_TABLE (PREFIX_VEX_3828) },
7609     { PREFIX_TABLE (PREFIX_VEX_3829) },
7610     { PREFIX_TABLE (PREFIX_VEX_382A) },
7611     { PREFIX_TABLE (PREFIX_VEX_382B) },
7612     { PREFIX_TABLE (PREFIX_VEX_382C) },
7613     { PREFIX_TABLE (PREFIX_VEX_382D) },
7614     { PREFIX_TABLE (PREFIX_VEX_382E) },
7615     { PREFIX_TABLE (PREFIX_VEX_382F) },
7616     /* 30 */
7617     { PREFIX_TABLE (PREFIX_VEX_3830) },
7618     { PREFIX_TABLE (PREFIX_VEX_3831) },
7619     { PREFIX_TABLE (PREFIX_VEX_3832) },
7620     { PREFIX_TABLE (PREFIX_VEX_3833) },
7621     { PREFIX_TABLE (PREFIX_VEX_3834) },
7622     { PREFIX_TABLE (PREFIX_VEX_3835) },
7623     { "(bad)",          { XX } },
7624     { PREFIX_TABLE (PREFIX_VEX_3837) },
7625     /* 38 */
7626     { PREFIX_TABLE (PREFIX_VEX_3838) },
7627     { PREFIX_TABLE (PREFIX_VEX_3839) },
7628     { PREFIX_TABLE (PREFIX_VEX_383A) },
7629     { PREFIX_TABLE (PREFIX_VEX_383B) },
7630     { PREFIX_TABLE (PREFIX_VEX_383C) },
7631     { PREFIX_TABLE (PREFIX_VEX_383D) },
7632     { PREFIX_TABLE (PREFIX_VEX_383E) },
7633     { PREFIX_TABLE (PREFIX_VEX_383F) },
7634     /* 40 */
7635     { PREFIX_TABLE (PREFIX_VEX_3840) },
7636     { PREFIX_TABLE (PREFIX_VEX_3841) },
7637     { "(bad)",          { XX } },
7638     { "(bad)",          { XX } },
7639     { "(bad)",          { XX } },
7640     { "(bad)",          { XX } },
7641     { "(bad)",          { XX } },
7642     { "(bad)",          { XX } },
7643     /* 48 */
7644     { "(bad)",          { XX } },
7645     { "(bad)",          { XX } },
7646     { "(bad)",          { XX } },
7647     { "(bad)",          { XX } },
7648     { "(bad)",          { XX } },
7649     { "(bad)",          { XX } },
7650     { "(bad)",          { XX } },
7651     { "(bad)",          { XX } },
7652     /* 50 */
7653     { "(bad)",          { XX } },
7654     { "(bad)",          { XX } },
7655     { "(bad)",          { XX } },
7656     { "(bad)",          { XX } },
7657     { "(bad)",          { XX } },
7658     { "(bad)",          { XX } },
7659     { "(bad)",          { XX } },
7660     { "(bad)",          { XX } },
7661     /* 58 */
7662     { "(bad)",          { XX } },
7663     { "(bad)",          { XX } },
7664     { "(bad)",          { XX } },
7665     { "(bad)",          { XX } },
7666     { "(bad)",          { XX } },
7667     { "(bad)",          { XX } },
7668     { "(bad)",          { XX } },
7669     { "(bad)",          { XX } },
7670     /* 60 */
7671     { "(bad)",          { XX } },
7672     { "(bad)",          { XX } },
7673     { "(bad)",          { XX } },
7674     { "(bad)",          { XX } },
7675     { "(bad)",          { XX } },
7676     { "(bad)",          { XX } },
7677     { "(bad)",          { XX } },
7678     { "(bad)",          { XX } },
7679     /* 68 */
7680     { "(bad)",          { XX } },
7681     { "(bad)",          { XX } },
7682     { "(bad)",          { XX } },
7683     { "(bad)",          { XX } },
7684     { "(bad)",          { XX } },
7685     { "(bad)",          { XX } },
7686     { "(bad)",          { XX } },
7687     { "(bad)",          { XX } },
7688     /* 70 */
7689     { "(bad)",          { XX } },
7690     { "(bad)",          { XX } },
7691     { "(bad)",          { XX } },
7692     { "(bad)",          { XX } },
7693     { "(bad)",          { XX } },
7694     { "(bad)",          { XX } },
7695     { "(bad)",          { XX } },
7696     { "(bad)",          { XX } },
7697     /* 78 */
7698     { "(bad)",          { XX } },
7699     { "(bad)",          { XX } },
7700     { "(bad)",          { XX } },
7701     { "(bad)",          { XX } },
7702     { "(bad)",          { XX } },
7703     { "(bad)",          { XX } },
7704     { "(bad)",          { XX } },
7705     { "(bad)",          { XX } },
7706     /* 80 */
7707     { "(bad)",          { XX } },
7708     { "(bad)",          { XX } },
7709     { "(bad)",          { XX } },
7710     { "(bad)",          { XX } },
7711     { "(bad)",          { XX } },
7712     { "(bad)",          { XX } },
7713     { "(bad)",          { XX } },
7714     { "(bad)",          { XX } },
7715     /* 88 */
7716     { "(bad)",          { XX } },
7717     { "(bad)",          { XX } },
7718     { "(bad)",          { XX } },
7719     { "(bad)",          { XX } },
7720     { "(bad)",          { XX } },
7721     { "(bad)",          { XX } },
7722     { "(bad)",          { XX } },
7723     { "(bad)",          { XX } },
7724     /* 90 */
7725     { "(bad)",          { XX } },
7726     { "(bad)",          { XX } },
7727     { "(bad)",          { XX } },
7728     { "(bad)",          { XX } },
7729     { "(bad)",          { XX } },
7730     { "(bad)",          { XX } },
7731     { PREFIX_TABLE (PREFIX_VEX_3896) },
7732     { PREFIX_TABLE (PREFIX_VEX_3897) },
7733     /* 98 */
7734     { PREFIX_TABLE (PREFIX_VEX_3898) },
7735     { PREFIX_TABLE (PREFIX_VEX_3899) },
7736     { PREFIX_TABLE (PREFIX_VEX_389A) },
7737     { PREFIX_TABLE (PREFIX_VEX_389B) },
7738     { PREFIX_TABLE (PREFIX_VEX_389C) },
7739     { PREFIX_TABLE (PREFIX_VEX_389D) },
7740     { PREFIX_TABLE (PREFIX_VEX_389E) },
7741     { PREFIX_TABLE (PREFIX_VEX_389F) },
7742     /* a0 */
7743     { "(bad)",          { XX } },
7744     { "(bad)",          { XX } },
7745     { "(bad)",          { XX } },
7746     { "(bad)",          { XX } },
7747     { "(bad)",          { XX } },
7748     { "(bad)",          { XX } },
7749     { PREFIX_TABLE (PREFIX_VEX_38A6) },
7750     { PREFIX_TABLE (PREFIX_VEX_38A7) },
7751     /* a8 */
7752     { PREFIX_TABLE (PREFIX_VEX_38A8) },
7753     { PREFIX_TABLE (PREFIX_VEX_38A9) },
7754     { PREFIX_TABLE (PREFIX_VEX_38AA) },
7755     { PREFIX_TABLE (PREFIX_VEX_38AB) },
7756     { PREFIX_TABLE (PREFIX_VEX_38AC) },
7757     { PREFIX_TABLE (PREFIX_VEX_38AD) },
7758     { PREFIX_TABLE (PREFIX_VEX_38AE) },
7759     { PREFIX_TABLE (PREFIX_VEX_38AF) },
7760     /* b0 */
7761     { "(bad)",          { XX } },
7762     { "(bad)",          { XX } },
7763     { "(bad)",          { XX } },
7764     { "(bad)",          { XX } },
7765     { "(bad)",          { XX } },
7766     { "(bad)",          { XX } },
7767     { PREFIX_TABLE (PREFIX_VEX_38B6) },
7768     { PREFIX_TABLE (PREFIX_VEX_38B7) },
7769     /* b8 */
7770     { PREFIX_TABLE (PREFIX_VEX_38B8) },
7771     { PREFIX_TABLE (PREFIX_VEX_38B9) },
7772     { PREFIX_TABLE (PREFIX_VEX_38BA) },
7773     { PREFIX_TABLE (PREFIX_VEX_38BB) },
7774     { PREFIX_TABLE (PREFIX_VEX_38BC) },
7775     { PREFIX_TABLE (PREFIX_VEX_38BD) },
7776     { PREFIX_TABLE (PREFIX_VEX_38BE) },
7777     { PREFIX_TABLE (PREFIX_VEX_38BF) },
7778     /* c0 */
7779     { "(bad)",          { XX } },
7780     { "(bad)",          { XX } },
7781     { "(bad)",          { XX } },
7782     { "(bad)",          { XX } },
7783     { "(bad)",          { XX } },
7784     { "(bad)",          { XX } },
7785     { "(bad)",          { XX } },
7786     { "(bad)",          { XX } },
7787     /* c8 */
7788     { "(bad)",          { XX } },
7789     { "(bad)",          { XX } },
7790     { "(bad)",          { XX } },
7791     { "(bad)",          { XX } },
7792     { "(bad)",          { XX } },
7793     { "(bad)",          { XX } },
7794     { "(bad)",          { XX } },
7795     { "(bad)",          { XX } },
7796     /* d0 */
7797     { "(bad)",          { XX } },
7798     { "(bad)",          { XX } },
7799     { "(bad)",          { XX } },
7800     { "(bad)",          { XX } },
7801     { "(bad)",          { XX } },
7802     { "(bad)",          { XX } },
7803     { "(bad)",          { XX } },
7804     { "(bad)",          { XX } },
7805     /* d8 */
7806     { "(bad)",          { XX } },
7807     { "(bad)",          { XX } },
7808     { "(bad)",          { XX } },
7809     { PREFIX_TABLE (PREFIX_VEX_38DB) },
7810     { PREFIX_TABLE (PREFIX_VEX_38DC) },
7811     { PREFIX_TABLE (PREFIX_VEX_38DD) },
7812     { PREFIX_TABLE (PREFIX_VEX_38DE) },
7813     { PREFIX_TABLE (PREFIX_VEX_38DF) },
7814     /* e0 */
7815     { "(bad)",          { XX } },
7816     { "(bad)",          { XX } },
7817     { "(bad)",          { XX } },
7818     { "(bad)",          { XX } },
7819     { "(bad)",          { XX } },
7820     { "(bad)",          { XX } },
7821     { "(bad)",          { XX } },
7822     { "(bad)",          { XX } },
7823     /* e8 */
7824     { "(bad)",          { XX } },
7825     { "(bad)",          { XX } },
7826     { "(bad)",          { XX } },
7827     { "(bad)",          { XX } },
7828     { "(bad)",          { XX } },
7829     { "(bad)",          { XX } },
7830     { "(bad)",          { XX } },
7831     { "(bad)",          { XX } },
7832     /* f0 */
7833     { "(bad)",          { XX } },
7834     { "(bad)",          { XX } },
7835     { "(bad)",          { XX } },
7836     { "(bad)",          { XX } },
7837     { "(bad)",          { XX } },
7838     { "(bad)",          { XX } },
7839     { "(bad)",          { XX } },
7840     { "(bad)",          { XX } },
7841     /* f8 */
7842     { "(bad)",          { XX } },
7843     { "(bad)",          { XX } },
7844     { "(bad)",          { XX } },
7845     { "(bad)",          { XX } },
7846     { "(bad)",          { XX } },
7847     { "(bad)",          { XX } },
7848     { "(bad)",          { XX } },
7849     { "(bad)",          { XX } },
7850   },
7851   /* VEX_0F3A */
7852   {
7853     /* 00 */
7854     { "(bad)",          { XX } },
7855     { "(bad)",          { XX } },
7856     { "(bad)",          { XX } },
7857     { "(bad)",          { XX } },
7858     { PREFIX_TABLE (PREFIX_VEX_3A04) },
7859     { PREFIX_TABLE (PREFIX_VEX_3A05) },
7860     { PREFIX_TABLE (PREFIX_VEX_3A06) },
7861     { "(bad)",          { XX } },
7862     /* 08 */
7863     { PREFIX_TABLE (PREFIX_VEX_3A08) },
7864     { PREFIX_TABLE (PREFIX_VEX_3A09) },
7865     { PREFIX_TABLE (PREFIX_VEX_3A0A) },
7866     { PREFIX_TABLE (PREFIX_VEX_3A0B) },
7867     { PREFIX_TABLE (PREFIX_VEX_3A0C) },
7868     { PREFIX_TABLE (PREFIX_VEX_3A0D) },
7869     { PREFIX_TABLE (PREFIX_VEX_3A0E) },
7870     { PREFIX_TABLE (PREFIX_VEX_3A0F) },
7871     /* 10 */
7872     { "(bad)",          { XX } },
7873     { "(bad)",          { XX } },
7874     { "(bad)",          { XX } },
7875     { "(bad)",          { XX } },
7876     { PREFIX_TABLE (PREFIX_VEX_3A14) },
7877     { PREFIX_TABLE (PREFIX_VEX_3A15) },
7878     { PREFIX_TABLE (PREFIX_VEX_3A16) },
7879     { PREFIX_TABLE (PREFIX_VEX_3A17) },
7880     /* 18 */
7881     { PREFIX_TABLE (PREFIX_VEX_3A18) },
7882     { PREFIX_TABLE (PREFIX_VEX_3A19) },
7883     { "(bad)",          { XX } },
7884     { "(bad)",          { XX } },
7885     { "(bad)",          { XX } },
7886     { "(bad)",          { XX } },
7887     { "(bad)",          { XX } },
7888     { "(bad)",          { XX } },
7889     /* 20 */
7890     { PREFIX_TABLE (PREFIX_VEX_3A20) },
7891     { PREFIX_TABLE (PREFIX_VEX_3A21) },
7892     { PREFIX_TABLE (PREFIX_VEX_3A22) },
7893     { "(bad)",          { XX } },
7894     { "(bad)",          { XX } },
7895     { "(bad)",          { XX } },
7896     { "(bad)",          { XX } },
7897     { "(bad)",          { XX } },
7898     /* 28 */
7899     { "(bad)",          { XX } },
7900     { "(bad)",          { XX } },
7901     { "(bad)",          { XX } },
7902     { "(bad)",          { XX } },
7903     { "(bad)",          { XX } },
7904     { "(bad)",          { XX } },
7905     { "(bad)",          { XX } },
7906     { "(bad)",          { XX } },
7907     /* 30 */
7908     { "(bad)",          { XX } },
7909     { "(bad)",          { XX } },
7910     { "(bad)",          { XX } },
7911     { "(bad)",          { XX } },
7912     { "(bad)",          { XX } },
7913     { "(bad)",          { XX } },
7914     { "(bad)",          { XX } },
7915     { "(bad)",          { XX } },
7916     /* 38 */
7917     { "(bad)",          { XX } },
7918     { "(bad)",          { XX } },
7919     { "(bad)",          { XX } },
7920     { "(bad)",          { XX } },
7921     { "(bad)",          { XX } },
7922     { "(bad)",          { XX } },
7923     { "(bad)",          { XX } },
7924     { "(bad)",          { XX } },
7925     /* 40 */
7926     { PREFIX_TABLE (PREFIX_VEX_3A40) },
7927     { PREFIX_TABLE (PREFIX_VEX_3A41) },
7928     { PREFIX_TABLE (PREFIX_VEX_3A42) },
7929     { "(bad)",          { XX } },
7930     { PREFIX_TABLE (PREFIX_VEX_3A44) },
7931     { "(bad)",          { XX } },
7932     { "(bad)",          { XX } },
7933     { "(bad)",          { XX } },
7934     /* 48 */
7935     { "(bad)",          { XX } },
7936     { "(bad)",          { XX } },
7937     { PREFIX_TABLE (PREFIX_VEX_3A4A) },
7938     { PREFIX_TABLE (PREFIX_VEX_3A4B) },
7939     { PREFIX_TABLE (PREFIX_VEX_3A4C) },
7940     { "(bad)",          { XX } },
7941     { "(bad)",          { XX } },
7942     { "(bad)",          { XX } },
7943     /* 50 */
7944     { "(bad)",          { XX } },
7945     { "(bad)",          { XX } },
7946     { "(bad)",          { XX } },
7947     { "(bad)",          { XX } },
7948     { "(bad)",          { XX } },
7949     { "(bad)",          { XX } },
7950     { "(bad)",          { XX } },
7951     { "(bad)",          { XX } },
7952     /* 58 */
7953     { "(bad)",          { XX } },
7954     { "(bad)",          { XX } },
7955     { "(bad)",          { XX } },
7956     { "(bad)",          { XX } },
7957     { PREFIX_TABLE (PREFIX_VEX_3A5C) },
7958     { PREFIX_TABLE (PREFIX_VEX_3A5D) },
7959     { PREFIX_TABLE (PREFIX_VEX_3A5E) },
7960     { PREFIX_TABLE (PREFIX_VEX_3A5F) },
7961     /* 60 */
7962     { PREFIX_TABLE (PREFIX_VEX_3A60) },
7963     { PREFIX_TABLE (PREFIX_VEX_3A61) },
7964     { PREFIX_TABLE (PREFIX_VEX_3A62) },
7965     { PREFIX_TABLE (PREFIX_VEX_3A63) },
7966     { "(bad)",          { XX } },
7967     { "(bad)",          { XX } },
7968     { "(bad)",          { XX } },
7969     { "(bad)",          { XX } },
7970     /* 68 */
7971     { PREFIX_TABLE (PREFIX_VEX_3A68) },
7972     { PREFIX_TABLE (PREFIX_VEX_3A69) },
7973     { PREFIX_TABLE (PREFIX_VEX_3A6A) },
7974     { PREFIX_TABLE (PREFIX_VEX_3A6B) },
7975     { PREFIX_TABLE (PREFIX_VEX_3A6C) },
7976     { PREFIX_TABLE (PREFIX_VEX_3A6D) },
7977     { PREFIX_TABLE (PREFIX_VEX_3A6E) },
7978     { PREFIX_TABLE (PREFIX_VEX_3A6F) },
7979     /* 70 */
7980     { "(bad)",          { XX } },
7981     { "(bad)",          { XX } },
7982     { "(bad)",          { XX } },
7983     { "(bad)",          { XX } },
7984     { "(bad)",          { XX } },
7985     { "(bad)",          { XX } },
7986     { "(bad)",          { XX } },
7987     { "(bad)",          { XX } },
7988     /* 78 */
7989     { PREFIX_TABLE (PREFIX_VEX_3A78) },
7990     { PREFIX_TABLE (PREFIX_VEX_3A79) },
7991     { PREFIX_TABLE (PREFIX_VEX_3A7A) },
7992     { PREFIX_TABLE (PREFIX_VEX_3A7B) },
7993     { PREFIX_TABLE (PREFIX_VEX_3A7C) },
7994     { PREFIX_TABLE (PREFIX_VEX_3A7D) },
7995     { PREFIX_TABLE (PREFIX_VEX_3A7E) },
7996     { PREFIX_TABLE (PREFIX_VEX_3A7F) },
7997     /* 80 */
7998     { "(bad)",          { XX } },
7999     { "(bad)",          { XX } },
8000     { "(bad)",          { XX } },
8001     { "(bad)",          { XX } },
8002     { "(bad)",          { XX } },
8003     { "(bad)",          { XX } },
8004     { "(bad)",          { XX } },
8005     { "(bad)",          { XX } },
8006     /* 88 */
8007     { "(bad)",          { XX } },
8008     { "(bad)",          { XX } },
8009     { "(bad)",          { XX } },
8010     { "(bad)",          { XX } },
8011     { "(bad)",          { XX } },
8012     { "(bad)",          { XX } },
8013     { "(bad)",          { XX } },
8014     { "(bad)",          { XX } },
8015     /* 90 */
8016     { "(bad)",          { XX } },
8017     { "(bad)",          { XX } },
8018     { "(bad)",          { XX } },
8019     { "(bad)",          { XX } },
8020     { "(bad)",          { XX } },
8021     { "(bad)",          { XX } },
8022     { "(bad)",          { XX } },
8023     { "(bad)",          { XX } },
8024     /* 98 */
8025     { "(bad)",          { XX } },
8026     { "(bad)",          { XX } },
8027     { "(bad)",          { XX } },
8028     { "(bad)",          { XX } },
8029     { "(bad)",          { XX } },
8030     { "(bad)",          { XX } },
8031     { "(bad)",          { XX } },
8032     { "(bad)",          { XX } },
8033     /* a0 */
8034     { "(bad)",          { XX } },
8035     { "(bad)",          { XX } },
8036     { "(bad)",          { XX } },
8037     { "(bad)",          { XX } },
8038     { "(bad)",          { XX } },
8039     { "(bad)",          { XX } },
8040     { "(bad)",          { XX } },
8041     { "(bad)",          { XX } },
8042     /* a8 */
8043     { "(bad)",          { XX } },
8044     { "(bad)",          { XX } },
8045     { "(bad)",          { XX } },
8046     { "(bad)",          { XX } },
8047     { "(bad)",          { XX } },
8048     { "(bad)",          { XX } },
8049     { "(bad)",          { XX } },
8050     { "(bad)",          { XX } },
8051     /* b0 */
8052     { "(bad)",          { XX } },
8053     { "(bad)",          { XX } },
8054     { "(bad)",          { XX } },
8055     { "(bad)",          { XX } },
8056     { "(bad)",          { XX } },
8057     { "(bad)",          { XX } },
8058     { "(bad)",          { XX } },
8059     { "(bad)",          { XX } },
8060     /* b8 */
8061     { "(bad)",          { XX } },
8062     { "(bad)",          { XX } },
8063     { "(bad)",          { XX } },
8064     { "(bad)",          { XX } },
8065     { "(bad)",          { XX } },
8066     { "(bad)",          { XX } },
8067     { "(bad)",          { XX } },
8068     { "(bad)",          { XX } },
8069     /* c0 */
8070     { "(bad)",          { XX } },
8071     { "(bad)",          { XX } },
8072     { "(bad)",          { XX } },
8073     { "(bad)",          { XX } },
8074     { "(bad)",          { XX } },
8075     { "(bad)",          { XX } },
8076     { "(bad)",          { XX } },
8077     { "(bad)",          { XX } },
8078     /* c8 */
8079     { "(bad)",          { XX } },
8080     { "(bad)",          { XX } },
8081     { "(bad)",          { XX } },
8082     { "(bad)",          { XX } },
8083     { "(bad)",          { XX } },
8084     { "(bad)",          { XX } },
8085     { "(bad)",          { XX } },
8086     { "(bad)",          { XX } },
8087     /* d0 */
8088     { "(bad)",          { XX } },
8089     { "(bad)",          { XX } },
8090     { "(bad)",          { XX } },
8091     { "(bad)",          { XX } },
8092     { "(bad)",          { XX } },
8093     { "(bad)",          { XX } },
8094     { "(bad)",          { XX } },
8095     { "(bad)",          { XX } },
8096     /* d8 */
8097     { "(bad)",          { XX } },
8098     { "(bad)",          { XX } },
8099     { "(bad)",          { XX } },
8100     { "(bad)",          { XX } },
8101     { "(bad)",          { XX } },
8102     { "(bad)",          { XX } },
8103     { "(bad)",          { XX } },
8104     { PREFIX_TABLE (PREFIX_VEX_3ADF) },
8105     /* e0 */
8106     { "(bad)",          { XX } },
8107     { "(bad)",          { XX } },
8108     { "(bad)",          { XX } },
8109     { "(bad)",          { XX } },
8110     { "(bad)",          { XX } },
8111     { "(bad)",          { XX } },
8112     { "(bad)",          { XX } },
8113     { "(bad)",          { XX } },
8114     /* e8 */
8115     { "(bad)",          { XX } },
8116     { "(bad)",          { XX } },
8117     { "(bad)",          { XX } },
8118     { "(bad)",          { XX } },
8119     { "(bad)",          { XX } },
8120     { "(bad)",          { XX } },
8121     { "(bad)",          { XX } },
8122     { "(bad)",          { XX } },
8123     /* f0 */
8124     { "(bad)",          { XX } },
8125     { "(bad)",          { XX } },
8126     { "(bad)",          { XX } },
8127     { "(bad)",          { XX } },
8128     { "(bad)",          { XX } },
8129     { "(bad)",          { XX } },
8130     { "(bad)",          { XX } },
8131     { "(bad)",          { XX } },
8132     /* f8 */
8133     { "(bad)",          { XX } },
8134     { "(bad)",          { XX } },
8135     { "(bad)",          { XX } },
8136     { "(bad)",          { XX } },
8137     { "(bad)",          { XX } },
8138     { "(bad)",          { XX } },
8139     { "(bad)",          { XX } },
8140     { "(bad)",          { XX } },
8141   },
8142 };
8143
8144 static const struct dis386 vex_len_table[][2] = {
8145   /* VEX_LEN_10_P_1 */
8146   {
8147     { "vmovss",         { XMVex, Vex128, EXd } },
8148     { "(bad)",          { XX } },
8149   },
8150
8151   /* VEX_LEN_10_P_3 */
8152   {
8153     { "vmovsd",         { XMVex, Vex128, EXq } },
8154     { "(bad)",          { XX } },
8155   },
8156
8157   /* VEX_LEN_11_P_1 */
8158   {
8159     { "vmovss",         { EXdVexS, Vex128, XM } },
8160     { "(bad)",          { XX } },
8161   },
8162
8163   /* VEX_LEN_11_P_3 */
8164   {
8165     { "vmovsd",         { EXqVexS, Vex128, XM } },
8166     { "(bad)",          { XX } },
8167   },
8168
8169   /* VEX_LEN_12_P_0_M_0 */
8170   {
8171     { "vmovlps",        { XM, Vex128, EXq } },
8172     { "(bad)",          { XX } },
8173   },
8174
8175   /* VEX_LEN_12_P_0_M_1 */
8176   {
8177     { "vmovhlps",       { XM, Vex128, EXq } },
8178     { "(bad)",          { XX } },
8179   },
8180
8181   /* VEX_LEN_12_P_2 */
8182   {
8183     { "vmovlpd",        { XM, Vex128, EXq } },
8184     { "(bad)",          { XX } },
8185   },
8186
8187   /* VEX_LEN_13_M_0 */
8188   {
8189     { "vmovlpX",        { EXq, XM } },
8190     { "(bad)",          { XX } },
8191   },
8192
8193   /* VEX_LEN_16_P_0_M_0 */
8194   {
8195     { "vmovhps",        { XM, Vex128, EXq } },
8196     { "(bad)",          { XX } },
8197   },
8198
8199   /* VEX_LEN_16_P_0_M_1 */
8200   {
8201     { "vmovlhps",       { XM, Vex128, EXq } },
8202     { "(bad)",          { XX } },
8203   },
8204
8205   /* VEX_LEN_16_P_2 */
8206   {
8207     { "vmovhpd",        { XM, Vex128, EXq } },
8208     { "(bad)",          { XX } },
8209   },
8210
8211   /* VEX_LEN_17_M_0 */
8212   {
8213     { "vmovhpX",        { EXq, XM } },
8214     { "(bad)",          { XX } },
8215   },
8216
8217   /* VEX_LEN_2A_P_1 */
8218   {
8219     { "vcvtsi2ss%LQ",   { XM, Vex128, Ev } },
8220     { "(bad)",          { XX } },
8221   },
8222
8223   /* VEX_LEN_2A_P_3 */
8224   {
8225     { "vcvtsi2sd%LQ",   { XM, Vex128, Ev } },
8226     { "(bad)",          { XX } },
8227   },
8228
8229   /* VEX_LEN_2C_P_1 */
8230   {
8231     { "vcvttss2siY",    { Gv, EXd } },
8232     { "(bad)",          { XX } },
8233   },
8234
8235   /* VEX_LEN_2C_P_3 */
8236   {
8237     { "vcvttsd2siY",    { Gv, EXq } },
8238     { "(bad)",          { XX } },
8239   },
8240
8241   /* VEX_LEN_2D_P_1 */
8242   {
8243     { "vcvtss2siY",     { Gv, EXd } },
8244     { "(bad)",          { XX } },
8245   },
8246
8247   /* VEX_LEN_2D_P_3 */
8248   {
8249     { "vcvtsd2siY",     { Gv, EXq } },
8250     { "(bad)",          { XX } },
8251   },
8252
8253   /* VEX_LEN_2E_P_0 */
8254   {
8255     { "vucomiss",       { XM, EXd } },
8256     { "(bad)",          { XX } },
8257   },
8258
8259   /* VEX_LEN_2E_P_2 */
8260   {
8261     { "vucomisd",       { XM, EXq } },
8262     { "(bad)",          { XX } },
8263   },
8264
8265   /* VEX_LEN_2F_P_0 */
8266   {
8267     { "vcomiss",        { XM, EXd } },
8268     { "(bad)",          { XX } },
8269   },
8270
8271   /* VEX_LEN_2F_P_2 */
8272   {
8273     { "vcomisd",        { XM, EXq } },
8274     { "(bad)",          { XX } },
8275   },
8276
8277   /* VEX_LEN_51_P_1 */
8278   {
8279     { "vsqrtss",        { XM, Vex128, EXd } },
8280     { "(bad)",          { XX } },
8281   },
8282
8283   /* VEX_LEN_51_P_3 */
8284   {
8285     { "vsqrtsd",        { XM, Vex128, EXq } },
8286     { "(bad)",          { XX } },
8287   },
8288
8289   /* VEX_LEN_52_P_1 */
8290   {
8291     { "vrsqrtss",       { XM, Vex128, EXd } },
8292     { "(bad)",          { XX } },
8293   },
8294
8295   /* VEX_LEN_53_P_1 */
8296   {
8297     { "vrcpss",         { XM, Vex128, EXd } },
8298     { "(bad)",          { XX } },
8299   },
8300
8301   /* VEX_LEN_58_P_1 */
8302   {
8303     { "vaddss",         { XM, Vex128, EXd } },
8304     { "(bad)",          { XX } },
8305   },
8306
8307   /* VEX_LEN_58_P_3 */
8308   {
8309     { "vaddsd",         { XM, Vex128, EXq } },
8310     { "(bad)",          { XX } },
8311   },
8312
8313   /* VEX_LEN_59_P_1 */
8314   {
8315     { "vmulss",         { XM, Vex128, EXd } },
8316     { "(bad)",          { XX } },
8317   },
8318
8319   /* VEX_LEN_59_P_3 */
8320   {
8321     { "vmulsd",         { XM, Vex128, EXq } },
8322     { "(bad)",          { XX } },
8323   },
8324
8325   /* VEX_LEN_5A_P_1 */
8326   {
8327     { "vcvtss2sd",      { XM, Vex128, EXd } },
8328     { "(bad)",          { XX } },
8329   },
8330
8331   /* VEX_LEN_5A_P_3 */
8332   {
8333     { "vcvtsd2ss",      { XM, Vex128, EXq } },
8334     { "(bad)",          { XX } },
8335   },
8336
8337   /* VEX_LEN_5C_P_1 */
8338   {
8339     { "vsubss",         { XM, Vex128, EXd } },
8340     { "(bad)",          { XX } },
8341   },
8342
8343   /* VEX_LEN_5C_P_3 */
8344   {
8345     { "vsubsd",         { XM, Vex128, EXq } },
8346     { "(bad)",          { XX } },
8347   },
8348
8349   /* VEX_LEN_5D_P_1 */
8350   {
8351     { "vminss",         { XM, Vex128, EXd } },
8352     { "(bad)",          { XX } },
8353   },
8354
8355   /* VEX_LEN_5D_P_3 */
8356   {
8357     { "vminsd",         { XM, Vex128, EXq } },
8358     { "(bad)",          { XX } },
8359   },
8360
8361   /* VEX_LEN_5E_P_1 */
8362   {
8363     { "vdivss",         { XM, Vex128, EXd } },
8364     { "(bad)",          { XX } },
8365   },
8366
8367   /* VEX_LEN_5E_P_3 */
8368   {
8369     { "vdivsd",         { XM, Vex128, EXq } },
8370     { "(bad)",          { XX } },
8371   },
8372
8373   /* VEX_LEN_5F_P_1 */
8374   {
8375     { "vmaxss",         { XM, Vex128, EXd } },
8376     { "(bad)",          { XX } },
8377   },
8378
8379   /* VEX_LEN_5F_P_3 */
8380   {
8381     { "vmaxsd",         { XM, Vex128, EXq } },
8382     { "(bad)",          { XX } },
8383   },
8384
8385   /* VEX_LEN_60_P_2 */
8386   {
8387     { "vpunpcklbw",     { XM, Vex128, EXx } },
8388     { "(bad)",          { XX } },
8389   },
8390
8391   /* VEX_LEN_61_P_2 */
8392   {
8393     { "vpunpcklwd",     { XM, Vex128, EXx } },
8394     { "(bad)",          { XX } },
8395   },
8396
8397   /* VEX_LEN_62_P_2 */
8398   {
8399     { "vpunpckldq",     { XM, Vex128, EXx } },
8400     { "(bad)",          { XX } },
8401   },
8402
8403   /* VEX_LEN_63_P_2 */
8404   {
8405     { "vpacksswb",      { XM, Vex128, EXx } },
8406     { "(bad)",          { XX } },
8407   },
8408
8409   /* VEX_LEN_64_P_2 */
8410   {
8411     { "vpcmpgtb",       { XM, Vex128, EXx } },
8412     { "(bad)",          { XX } },
8413   },
8414
8415   /* VEX_LEN_65_P_2 */
8416   {
8417     { "vpcmpgtw",       { XM, Vex128, EXx } },
8418     { "(bad)",          { XX } },
8419   },
8420
8421   /* VEX_LEN_66_P_2 */
8422   {
8423     { "vpcmpgtd",       { XM, Vex128, EXx } },
8424     { "(bad)",          { XX } },
8425   },
8426
8427   /* VEX_LEN_67_P_2 */
8428   {
8429     { "vpackuswb",      { XM, Vex128, EXx } },
8430     { "(bad)",          { XX } },
8431   },
8432
8433   /* VEX_LEN_68_P_2 */
8434   {
8435     { "vpunpckhbw",     { XM, Vex128, EXx } },
8436     { "(bad)",          { XX } },
8437   },
8438
8439   /* VEX_LEN_69_P_2 */
8440   {
8441     { "vpunpckhwd",     { XM, Vex128, EXx } },
8442     { "(bad)",          { XX } },
8443   },
8444
8445   /* VEX_LEN_6A_P_2 */
8446   {
8447     { "vpunpckhdq",     { XM, Vex128, EXx } },
8448     { "(bad)",          { XX } },
8449   },
8450
8451   /* VEX_LEN_6B_P_2 */
8452   {
8453     { "vpackssdw",      { XM, Vex128, EXx } },
8454     { "(bad)",          { XX } },
8455   },
8456
8457   /* VEX_LEN_6C_P_2 */
8458   {
8459     { "vpunpcklqdq",    { XM, Vex128, EXx } },
8460     { "(bad)",          { XX } },
8461   },
8462
8463   /* VEX_LEN_6D_P_2 */
8464   {
8465     { "vpunpckhqdq",    { XM, Vex128, EXx } },
8466     { "(bad)",          { XX } },
8467   },
8468
8469   /* VEX_LEN_6E_P_2 */
8470   {
8471     { "vmovK",          { XM, Edq } },
8472     { "(bad)",          { XX } },
8473   },
8474
8475   /* VEX_LEN_70_P_1 */
8476   {
8477     { "vpshufhw",       { XM, EXx, Ib } },
8478     { "(bad)",          { XX } },
8479   },
8480
8481   /* VEX_LEN_70_P_2 */
8482   {
8483     { "vpshufd",        { XM, EXx, Ib } },
8484     { "(bad)",          { XX } },
8485   },
8486
8487   /* VEX_LEN_70_P_3 */
8488   {
8489     { "vpshuflw",       { XM, EXx, Ib } },
8490     { "(bad)",          { XX } },
8491   },
8492
8493   /* VEX_LEN_71_R_2_P_2 */
8494   {
8495     { "vpsrlw",         { Vex128, XS, Ib } },
8496     { "(bad)",          { XX } },
8497   },
8498
8499   /* VEX_LEN_71_R_4_P_2 */
8500   {
8501     { "vpsraw",         { Vex128, XS, Ib } },
8502     { "(bad)",          { XX } },
8503   },
8504
8505   /* VEX_LEN_71_R_6_P_2 */
8506   {
8507     { "vpsllw",         { Vex128, XS, Ib } },
8508     { "(bad)",          { XX } },
8509   },
8510
8511   /* VEX_LEN_72_R_2_P_2 */
8512   {
8513     { "vpsrld",         { Vex128, XS, Ib } },
8514     { "(bad)",          { XX } },
8515   },
8516
8517   /* VEX_LEN_72_R_4_P_2 */
8518   {
8519     { "vpsrad",         { Vex128, XS, Ib } },
8520     { "(bad)",          { XX } },
8521   },
8522
8523   /* VEX_LEN_72_R_6_P_2 */
8524   {
8525     { "vpslld",         { Vex128, XS, Ib } },
8526     { "(bad)",          { XX } },
8527   },
8528
8529   /* VEX_LEN_73_R_2_P_2 */
8530   {
8531     { "vpsrlq",         { Vex128, XS, Ib } },
8532     { "(bad)",          { XX } },
8533   },
8534
8535   /* VEX_LEN_73_R_3_P_2 */
8536   {
8537     { "vpsrldq",        { Vex128, XS, Ib } },
8538     { "(bad)",          { XX } },
8539   },
8540
8541   /* VEX_LEN_73_R_6_P_2 */
8542   {
8543     { "vpsllq",         { Vex128, XS, Ib } },
8544     { "(bad)",          { XX } },
8545   },
8546
8547   /* VEX_LEN_73_R_7_P_2 */
8548   {
8549     { "vpslldq",        { Vex128, XS, Ib } },
8550     { "(bad)",          { XX } },
8551   },
8552
8553   /* VEX_LEN_74_P_2 */
8554   {
8555     { "vpcmpeqb",       { XM, Vex128, EXx } },
8556     { "(bad)",          { XX } },
8557   },
8558
8559   /* VEX_LEN_75_P_2 */
8560   {
8561     { "vpcmpeqw",       { XM, Vex128, EXx } },
8562     { "(bad)",          { XX } },
8563   },
8564
8565   /* VEX_LEN_76_P_2 */
8566   {
8567     { "vpcmpeqd",       { XM, Vex128, EXx } },
8568     { "(bad)",          { XX } },
8569   },
8570
8571   /* VEX_LEN_7E_P_1 */
8572   {
8573     { "vmovq",          { XM, EXq } },
8574     { "(bad)",          { XX } },
8575   },
8576
8577   /* VEX_LEN_7E_P_2 */
8578   {
8579     { "vmovK",          { Edq, XM } },
8580     { "(bad)",          { XX } },
8581   },
8582
8583   /* VEX_LEN_AE_R_2_M_0 */
8584   {
8585     { "vldmxcsr",       { Md } },
8586     { "(bad)",          { XX } },
8587   },
8588
8589   /* VEX_LEN_AE_R_3_M_0 */
8590   {
8591     { "vstmxcsr",       { Md } },
8592     { "(bad)",          { XX } },
8593   },
8594
8595   /* VEX_LEN_C2_P_1 */
8596   {
8597     { "vcmpss",         { XM, Vex128, EXd, VCMP } },
8598     { "(bad)",          { XX } },
8599   },
8600
8601   /* VEX_LEN_C2_P_3 */
8602   {
8603     { "vcmpsd",         { XM, Vex128, EXq, VCMP } },
8604     { "(bad)",          { XX } },
8605   },
8606
8607   /* VEX_LEN_C4_P_2 */
8608   {
8609     { "vpinsrw",        { XM, Vex128, Edqw, Ib } },
8610     { "(bad)",          { XX } },
8611   },
8612
8613   /* VEX_LEN_C5_P_2 */
8614   {
8615     { "vpextrw",        { Gdq, XS, Ib } },
8616     { "(bad)",          { XX } },
8617   },
8618
8619   /* VEX_LEN_D1_P_2 */
8620   {
8621     { "vpsrlw",         { XM, Vex128, EXx } },
8622     { "(bad)",          { XX } },
8623   },
8624
8625   /* VEX_LEN_D2_P_2 */
8626   {
8627     { "vpsrld",         { XM, Vex128, EXx } },
8628     { "(bad)",          { XX } },
8629   },
8630
8631   /* VEX_LEN_D3_P_2 */
8632   {
8633     { "vpsrlq",         { XM, Vex128, EXx } },
8634     { "(bad)",          { XX } },
8635   },
8636
8637   /* VEX_LEN_D4_P_2 */
8638   {
8639     { "vpaddq",         { XM, Vex128, EXx } },
8640     { "(bad)",          { XX } },
8641   },
8642
8643   /* VEX_LEN_D5_P_2 */
8644   {
8645     { "vpmullw",        { XM, Vex128, EXx } },
8646     { "(bad)",          { XX } },
8647   },
8648
8649   /* VEX_LEN_D6_P_2 */
8650   {
8651     { "vmovq",          { EXqS, XM } },
8652     { "(bad)",          { XX } },
8653   },
8654
8655   /* VEX_LEN_D7_P_2_M_1 */
8656   {
8657     { "vpmovmskb",      { Gdq, XS } },
8658     { "(bad)",          { XX } },
8659   },
8660
8661   /* VEX_LEN_D8_P_2 */
8662   {
8663     { "vpsubusb",       { XM, Vex128, EXx } },
8664     { "(bad)",          { XX } },
8665   },
8666
8667   /* VEX_LEN_D9_P_2 */
8668   {
8669     { "vpsubusw",       { XM, Vex128, EXx } },
8670     { "(bad)",          { XX } },
8671   },
8672
8673   /* VEX_LEN_DA_P_2 */
8674   {
8675     { "vpminub",        { XM, Vex128, EXx } },
8676     { "(bad)",          { XX } },
8677   },
8678
8679   /* VEX_LEN_DB_P_2 */
8680   {
8681     { "vpand",          { XM, Vex128, EXx } },
8682     { "(bad)",          { XX } },
8683   },
8684
8685   /* VEX_LEN_DC_P_2 */
8686   {
8687     { "vpaddusb",       { XM, Vex128, EXx } },
8688     { "(bad)",          { XX } },
8689   },
8690
8691   /* VEX_LEN_DD_P_2 */
8692   {
8693     { "vpaddusw",       { XM, Vex128, EXx } },
8694     { "(bad)",          { XX } },
8695   },
8696
8697   /* VEX_LEN_DE_P_2 */
8698   {
8699     { "vpmaxub",        { XM, Vex128, EXx } },
8700     { "(bad)",          { XX } },
8701   },
8702
8703   /* VEX_LEN_DF_P_2 */
8704   {
8705     { "vpandn",         { XM, Vex128, EXx } },
8706     { "(bad)",          { XX } },
8707   },
8708
8709   /* VEX_LEN_E0_P_2 */
8710   {
8711     { "vpavgb",         { XM, Vex128, EXx } },
8712     { "(bad)",          { XX } },
8713   },
8714
8715   /* VEX_LEN_E1_P_2 */
8716   {
8717     { "vpsraw",         { XM, Vex128, EXx } },
8718     { "(bad)",          { XX } },
8719   },
8720
8721   /* VEX_LEN_E2_P_2 */
8722   {
8723     { "vpsrad",         { XM, Vex128, EXx } },
8724     { "(bad)",          { XX } },
8725   },
8726
8727   /* VEX_LEN_E3_P_2 */
8728   {
8729     { "vpavgw",         { XM, Vex128, EXx } },
8730     { "(bad)",          { XX } },
8731   },
8732
8733   /* VEX_LEN_E4_P_2 */
8734   {
8735     { "vpmulhuw",       { XM, Vex128, EXx } },
8736     { "(bad)",          { XX } },
8737   },
8738
8739   /* VEX_LEN_E5_P_2 */
8740   {
8741     { "vpmulhw",        { XM, Vex128, EXx } },
8742     { "(bad)",          { XX } },
8743   },
8744
8745   /* VEX_LEN_E8_P_2 */
8746   {
8747     { "vpsubsb",        { XM, Vex128, EXx } },
8748     { "(bad)",          { XX } },
8749   },
8750
8751   /* VEX_LEN_E9_P_2 */
8752   {
8753     { "vpsubsw",        { XM, Vex128, EXx } },
8754     { "(bad)",          { XX } },
8755   },
8756
8757   /* VEX_LEN_EA_P_2 */
8758   {
8759     { "vpminsw",        { XM, Vex128, EXx } },
8760     { "(bad)",          { XX } },
8761   },
8762
8763   /* VEX_LEN_EB_P_2 */
8764   {
8765     { "vpor",           { XM, Vex128, EXx } },
8766     { "(bad)",          { XX } },
8767   },
8768
8769   /* VEX_LEN_EC_P_2 */
8770   {
8771     { "vpaddsb",        { XM, Vex128, EXx } },
8772     { "(bad)",          { XX } },
8773   },
8774
8775   /* VEX_LEN_ED_P_2 */
8776   {
8777     { "vpaddsw",        { XM, Vex128, EXx } },
8778     { "(bad)",          { XX } },
8779   },
8780
8781   /* VEX_LEN_EE_P_2 */
8782   {
8783     { "vpmaxsw",        { XM, Vex128, EXx } },
8784     { "(bad)",          { XX } },
8785   },
8786
8787   /* VEX_LEN_EF_P_2 */
8788   {
8789     { "vpxor",          { XM, Vex128, EXx } },
8790     { "(bad)",          { XX } },
8791   },
8792
8793   /* VEX_LEN_F1_P_2 */
8794   {
8795     { "vpsllw",         { XM, Vex128, EXx } },
8796     { "(bad)",          { XX } },
8797   },
8798
8799   /* VEX_LEN_F2_P_2 */
8800   {
8801     { "vpslld",         { XM, Vex128, EXx } },
8802     { "(bad)",          { XX } },
8803   },
8804
8805   /* VEX_LEN_F3_P_2 */
8806   {
8807     { "vpsllq",         { XM, Vex128, EXx } },
8808     { "(bad)",          { XX } },
8809   },
8810
8811   /* VEX_LEN_F4_P_2 */
8812   {
8813     { "vpmuludq",       { XM, Vex128, EXx } },
8814     { "(bad)",          { XX } },
8815   },
8816
8817   /* VEX_LEN_F5_P_2 */
8818   {
8819     { "vpmaddwd",       { XM, Vex128, EXx } },
8820     { "(bad)",          { XX } },
8821   },
8822
8823   /* VEX_LEN_F6_P_2 */
8824   {
8825     { "vpsadbw",        { XM, Vex128, EXx } },
8826     { "(bad)",          { XX } },
8827   },
8828
8829   /* VEX_LEN_F7_P_2 */
8830   {
8831     { "vmaskmovdqu",    { XM, XS } },
8832     { "(bad)",          { XX } },
8833   },
8834
8835   /* VEX_LEN_F8_P_2 */
8836   {
8837     { "vpsubb",         { XM, Vex128, EXx } },
8838     { "(bad)",          { XX } },
8839   },
8840
8841   /* VEX_LEN_F9_P_2 */
8842   {
8843     { "vpsubw",         { XM, Vex128, EXx } },
8844     { "(bad)",          { XX } },
8845   },
8846
8847   /* VEX_LEN_FA_P_2 */
8848   {
8849     { "vpsubd",         { XM, Vex128, EXx } },
8850     { "(bad)",          { XX } },
8851   },
8852
8853   /* VEX_LEN_FB_P_2 */
8854   {
8855     { "vpsubq",         { XM, Vex128, EXx } },
8856     { "(bad)",          { XX } },
8857   },
8858
8859   /* VEX_LEN_FC_P_2 */
8860   {
8861     { "vpaddb",         { XM, Vex128, EXx } },
8862     { "(bad)",          { XX } },
8863   },
8864
8865   /* VEX_LEN_FD_P_2 */
8866   {
8867     { "vpaddw",         { XM, Vex128, EXx } },
8868     { "(bad)",          { XX } },
8869   },
8870
8871   /* VEX_LEN_FE_P_2 */
8872   {
8873     { "vpaddd",         { XM, Vex128, EXx } },
8874     { "(bad)",          { XX } },
8875   },
8876
8877   /* VEX_LEN_3800_P_2 */
8878   {
8879     { "vpshufb",        { XM, Vex128, EXx } },
8880     { "(bad)",          { XX } },
8881   },
8882
8883   /* VEX_LEN_3801_P_2 */
8884   {
8885     { "vphaddw",        { XM, Vex128, EXx } },
8886     { "(bad)",          { XX } },
8887   },
8888
8889   /* VEX_LEN_3802_P_2 */
8890   {
8891     { "vphaddd",        { XM, Vex128, EXx } },
8892     { "(bad)",          { XX } },
8893   },
8894
8895   /* VEX_LEN_3803_P_2 */
8896   {
8897     { "vphaddsw",       { XM, Vex128, EXx } },
8898     { "(bad)",          { XX } },
8899   },
8900
8901   /* VEX_LEN_3804_P_2 */
8902   {
8903     { "vpmaddubsw",     { XM, Vex128, EXx } },
8904     { "(bad)",          { XX } },
8905   },
8906
8907   /* VEX_LEN_3805_P_2 */
8908   {
8909     { "vphsubw",        { XM, Vex128, EXx } },
8910     { "(bad)",          { XX } },
8911   },
8912
8913   /* VEX_LEN_3806_P_2 */
8914   {
8915     { "vphsubd",        { XM, Vex128, EXx } },
8916     { "(bad)",          { XX } },
8917   },
8918
8919   /* VEX_LEN_3807_P_2 */
8920   {
8921     { "vphsubsw",       { XM, Vex128, EXx } },
8922     { "(bad)",          { XX } },
8923   },
8924
8925   /* VEX_LEN_3808_P_2 */
8926   {
8927     { "vpsignb",        { XM, Vex128, EXx } },
8928     { "(bad)",          { XX } },
8929   },
8930
8931   /* VEX_LEN_3809_P_2 */
8932   {
8933     { "vpsignw",        { XM, Vex128, EXx } },
8934     { "(bad)",          { XX } },
8935   },
8936
8937   /* VEX_LEN_380A_P_2 */
8938   {
8939     { "vpsignd",        { XM, Vex128, EXx } },
8940     { "(bad)",          { XX } },
8941   },
8942
8943   /* VEX_LEN_380B_P_2 */
8944   {
8945     { "vpmulhrsw",      { XM, Vex128, EXx } },
8946     { "(bad)",          { XX } },
8947   },
8948
8949   /* VEX_LEN_3819_P_2_M_0 */
8950   {
8951     { "(bad)",          { XX } },
8952     { "vbroadcastsd",   { XM, Mq } },
8953   },
8954
8955   /* VEX_LEN_381A_P_2_M_0 */
8956   {
8957     { "(bad)",          { XX } },
8958     { "vbroadcastf128", { XM, Mxmm } },
8959   },
8960
8961   /* VEX_LEN_381C_P_2 */
8962   {
8963     { "vpabsb",         { XM, EXx } },
8964     { "(bad)",          { XX } },
8965   },
8966
8967   /* VEX_LEN_381D_P_2 */
8968   {
8969     { "vpabsw",         { XM, EXx } },
8970     { "(bad)",          { XX } },
8971   },
8972
8973   /* VEX_LEN_381E_P_2 */
8974   {
8975     { "vpabsd",         { XM, EXx } },
8976     { "(bad)",          { XX } },
8977   },
8978
8979   /* VEX_LEN_3820_P_2 */
8980   {
8981     { "vpmovsxbw",      { XM, EXq } },
8982     { "(bad)",          { XX } },
8983   },
8984
8985   /* VEX_LEN_3821_P_2 */
8986   {
8987     { "vpmovsxbd",      { XM, EXd } },
8988     { "(bad)",          { XX } },
8989   },
8990
8991   /* VEX_LEN_3822_P_2 */
8992   {
8993     { "vpmovsxbq",      { XM, EXw } },
8994     { "(bad)",          { XX } },
8995   },
8996
8997   /* VEX_LEN_3823_P_2 */
8998   {
8999     { "vpmovsxwd",      { XM, EXq } },
9000     { "(bad)",          { XX } },
9001   },
9002
9003   /* VEX_LEN_3824_P_2 */
9004   {
9005     { "vpmovsxwq",      { XM, EXd } },
9006     { "(bad)",          { XX } },
9007   },
9008
9009   /* VEX_LEN_3825_P_2 */
9010   {
9011     { "vpmovsxdq",      { XM, EXq } },
9012     { "(bad)",          { XX } },
9013   },
9014
9015   /* VEX_LEN_3828_P_2 */
9016   {
9017     { "vpmuldq",        { XM, Vex128, EXx } },
9018     { "(bad)",          { XX } },
9019   },
9020
9021   /* VEX_LEN_3829_P_2 */
9022   {
9023     { "vpcmpeqq",       { XM, Vex128, EXx } },
9024     { "(bad)",          { XX } },
9025   },
9026
9027   /* VEX_LEN_382A_P_2_M_0 */
9028   {
9029     { "vmovntdqa",      { XM, Mx } },
9030     { "(bad)",          { XX } },
9031   },
9032
9033   /* VEX_LEN_382B_P_2 */
9034   {
9035     { "vpackusdw",      { XM, Vex128, EXx } },
9036     { "(bad)",          { XX } },
9037   },
9038
9039   /* VEX_LEN_3830_P_2 */
9040   {
9041     { "vpmovzxbw",      { XM, EXq } },
9042     { "(bad)",          { XX } },
9043   },
9044
9045   /* VEX_LEN_3831_P_2 */
9046   {
9047     { "vpmovzxbd",      { XM, EXd } },
9048     { "(bad)",          { XX } },
9049   },
9050
9051   /* VEX_LEN_3832_P_2 */
9052   {
9053     { "vpmovzxbq",      { XM, EXw } },
9054     { "(bad)",          { XX } },
9055   },
9056
9057   /* VEX_LEN_3833_P_2 */
9058   {
9059     { "vpmovzxwd",      { XM, EXq } },
9060     { "(bad)",          { XX } },
9061   },
9062
9063   /* VEX_LEN_3834_P_2 */
9064   {
9065     { "vpmovzxwq",      { XM, EXd } },
9066     { "(bad)",          { XX } },
9067   },
9068
9069   /* VEX_LEN_3835_P_2 */
9070   {
9071     { "vpmovzxdq",      { XM, EXq } },
9072     { "(bad)",          { XX } },
9073   },
9074
9075   /* VEX_LEN_3837_P_2 */
9076   {
9077     { "vpcmpgtq",       { XM, Vex128, EXx } },
9078     { "(bad)",          { XX } },
9079   },
9080
9081   /* VEX_LEN_3838_P_2 */
9082   {
9083     { "vpminsb",        { XM, Vex128, EXx } },
9084     { "(bad)",          { XX } },
9085   },
9086
9087   /* VEX_LEN_3839_P_2 */
9088   {
9089     { "vpminsd",        { XM, Vex128, EXx } },
9090     { "(bad)",          { XX } },
9091   },
9092
9093   /* VEX_LEN_383A_P_2 */
9094   {
9095     { "vpminuw",        { XM, Vex128, EXx } },
9096     { "(bad)",          { XX } },
9097   },
9098
9099   /* VEX_LEN_383B_P_2 */
9100   {
9101     { "vpminud",        { XM, Vex128, EXx } },
9102     { "(bad)",          { XX } },
9103   },
9104
9105   /* VEX_LEN_383C_P_2 */
9106   {
9107     { "vpmaxsb",        { XM, Vex128, EXx } },
9108     { "(bad)",          { XX } },
9109   },
9110
9111   /* VEX_LEN_383D_P_2 */
9112   {
9113     { "vpmaxsd",        { XM, Vex128, EXx } },
9114     { "(bad)",          { XX } },
9115   },
9116
9117   /* VEX_LEN_383E_P_2 */
9118   {
9119     { "vpmaxuw",        { XM, Vex128, EXx } },
9120     { "(bad)",          { XX } },
9121   },
9122
9123   /* VEX_LEN_383F_P_2 */
9124   {
9125     { "vpmaxud",        { XM, Vex128, EXx } },
9126     { "(bad)",          { XX } },
9127   },
9128
9129   /* VEX_LEN_3840_P_2 */
9130   {
9131     { "vpmulld",        { XM, Vex128, EXx } },
9132     { "(bad)",          { XX } },
9133   },
9134
9135   /* VEX_LEN_3841_P_2 */
9136   {
9137     { "vphminposuw",    { XM, EXx } },
9138     { "(bad)",          { XX } },
9139   },
9140
9141   /* VEX_LEN_38DB_P_2 */
9142   {
9143     { "vaesimc",        { XM, EXx } },
9144     { "(bad)",          { XX } },
9145   },
9146
9147   /* VEX_LEN_38DC_P_2 */
9148   {
9149     { "vaesenc",        { XM, Vex128, EXx } },
9150     { "(bad)",          { XX } },
9151   },
9152
9153   /* VEX_LEN_38DD_P_2 */
9154   {
9155     { "vaesenclast",    { XM, Vex128, EXx } },
9156     { "(bad)",          { XX } },
9157   },
9158
9159   /* VEX_LEN_38DE_P_2 */
9160   {
9161     { "vaesdec",        { XM, Vex128, EXx } },
9162     { "(bad)",          { XX } },
9163   },
9164
9165   /* VEX_LEN_38DF_P_2 */
9166   {
9167     { "vaesdeclast",    { XM, Vex128, EXx } },
9168     { "(bad)",          { XX } },
9169   },
9170
9171   /* VEX_LEN_3A06_P_2 */
9172   {
9173     { "(bad)",          { XX } },
9174     { "vperm2f128",     { XM, Vex256, EXx, Ib } },
9175   },
9176
9177   /* VEX_LEN_3A0A_P_2 */
9178   {
9179     { "vroundss",       { XM, Vex128, EXd, Ib } },
9180     { "(bad)",          { XX } },
9181   },
9182
9183   /* VEX_LEN_3A0B_P_2 */
9184   {
9185     { "vroundsd",       { XM, Vex128, EXq, Ib } },
9186     { "(bad)",          { XX } },
9187   },
9188
9189   /* VEX_LEN_3A0E_P_2 */
9190   {
9191     { "vpblendw",       { XM, Vex128, EXx, Ib } },
9192     { "(bad)",          { XX } },
9193   },
9194
9195   /* VEX_LEN_3A0F_P_2 */
9196   {
9197     { "vpalignr",       { XM, Vex128, EXx, Ib } },
9198     { "(bad)",          { XX } },
9199   },
9200
9201   /* VEX_LEN_3A14_P_2 */
9202   {
9203     { "vpextrb",        { Edqb, XM, Ib } },
9204     { "(bad)",          { XX } },
9205   },
9206
9207   /* VEX_LEN_3A15_P_2 */
9208   {
9209     { "vpextrw",        { Edqw, XM, Ib } },
9210     { "(bad)",          { XX } },
9211   },
9212
9213   /* VEX_LEN_3A16_P_2  */
9214   {
9215     { "vpextrK",        { Edq, XM, Ib } },
9216     { "(bad)",          { XX } },
9217   },
9218
9219   /* VEX_LEN_3A17_P_2 */
9220   {
9221     { "vextractps",     { Edqd, XM, Ib } },
9222     { "(bad)",          { XX } },
9223   },
9224
9225   /* VEX_LEN_3A18_P_2 */
9226   {
9227     { "(bad)",          { XX } },
9228     { "vinsertf128",    { XM, Vex256, EXxmm, Ib } },
9229   },
9230
9231   /* VEX_LEN_3A19_P_2 */
9232   {
9233     { "(bad)",          { XX } },
9234     { "vextractf128",   { EXxmm, XM, Ib } },
9235   },
9236
9237   /* VEX_LEN_3A20_P_2 */
9238   {
9239     { "vpinsrb",        { XM, Vex128, Edqb, Ib } },
9240     { "(bad)",          { XX } },
9241   },
9242
9243   /* VEX_LEN_3A21_P_2 */
9244   {
9245     { "vinsertps",      { XM, Vex128, EXd, Ib } },
9246     { "(bad)",          { XX } },
9247   },
9248
9249   /* VEX_LEN_3A22_P_2 */
9250   {
9251     { "vpinsrK",        { XM, Vex128, Edq, Ib } },
9252     { "(bad)",          { XX } },
9253   },
9254
9255   /* VEX_LEN_3A41_P_2 */
9256   {
9257     { "vdppd",          { XM, Vex128, EXx, Ib } },
9258     { "(bad)",          { XX } },
9259   },
9260
9261   /* VEX_LEN_3A42_P_2 */
9262   {
9263     { "vmpsadbw",       { XM, Vex128, EXx, Ib } },
9264     { "(bad)",          { XX } },
9265   },
9266
9267   /* VEX_LEN_3A44_P_2 */
9268   {
9269     { "vpclmulqdq",     { XM, Vex128, EXx, PCLMUL } },
9270     { "(bad)",          { XX } },
9271   },
9272
9273   /* VEX_LEN_3A4C_P_2 */
9274   {
9275     { "vpblendvb",      { XM, Vex128, EXx, XMVexI4 } },
9276     { "(bad)",          { XX } },
9277   },
9278
9279   /* VEX_LEN_3A60_P_2 */
9280   {
9281     { "vpcmpestrm",     { XM, EXx, Ib } },
9282     { "(bad)",          { XX } },
9283   },
9284
9285   /* VEX_LEN_3A61_P_2 */
9286   {
9287     { "vpcmpestri",     { XM, EXx, Ib } },
9288     { "(bad)",          { XX } },
9289   },
9290
9291   /* VEX_LEN_3A62_P_2 */
9292   {
9293     { "vpcmpistrm",     { XM, EXx, Ib } },
9294     { "(bad)",          { XX } },
9295   },
9296
9297   /* VEX_LEN_3A63_P_2 */
9298   {
9299     { "vpcmpistri",     { XM, EXx, Ib } },
9300     { "(bad)",          { XX } },
9301   },
9302
9303   /* VEX_LEN_3A6A_P_2 */
9304   {
9305     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9306     { "(bad)",          { XX } },
9307   },
9308
9309   /* VEX_LEN_3A6B_P_2 */
9310   {
9311     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9312     { "(bad)",          { XX } },
9313   },
9314
9315   /* VEX_LEN_3A6E_P_2 */
9316   {
9317     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9318     { "(bad)",          { XX } },
9319   },
9320
9321   /* VEX_LEN_3A6F_P_2 */
9322   {
9323     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9324     { "(bad)",          { XX } },
9325   },
9326
9327   /* VEX_LEN_3A7A_P_2 */
9328   {
9329     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9330     { "(bad)",          { XX } },
9331   },
9332
9333   /* VEX_LEN_3A7B_P_2 */
9334   {
9335     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9336     { "(bad)",          { XX } },
9337   },
9338
9339   /* VEX_LEN_3A7E_P_2 */
9340   {
9341     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9342     { "(bad)",          { XX } },
9343   },
9344
9345   /* VEX_LEN_3A7F_P_2 */
9346   {
9347     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9348     { "(bad)",          { XX } },
9349   },
9350
9351   /* VEX_LEN_3ADF_P_2 */
9352   {
9353     { "vaeskeygenassist", { XM, EXx, Ib } },
9354     { "(bad)",          { XX } },
9355   },
9356   /* VEX_LEN_XOP_09_80 */
9357   {
9358     { "vfrczps", { XM, EXxmm } },
9359     { "vfrczps", { XM, EXymmq } },
9360   },
9361   /* VEX_LEN_XOP_09_81 */
9362   {
9363     { "vfrczpd", { XM, EXxmm } },
9364     { "vfrczpd", { XM, EXymmq } },
9365   },
9366 };
9367
9368 static const struct dis386 mod_table[][2] = {
9369   {
9370     /* MOD_8D */
9371     { "leaS",           { Gv, M } },
9372     { "(bad)",          { XX } },
9373   },
9374   {
9375     /* MOD_0F01_REG_0 */
9376     { X86_64_TABLE (X86_64_0F01_REG_0) },
9377     { RM_TABLE (RM_0F01_REG_0) },
9378   },
9379   {
9380     /* MOD_0F01_REG_1 */
9381     { X86_64_TABLE (X86_64_0F01_REG_1) },
9382     { RM_TABLE (RM_0F01_REG_1) },
9383   },
9384   {
9385     /* MOD_0F01_REG_2 */
9386     { X86_64_TABLE (X86_64_0F01_REG_2) },
9387     { RM_TABLE (RM_0F01_REG_2) },
9388   },
9389   {
9390     /* MOD_0F01_REG_3 */
9391     { X86_64_TABLE (X86_64_0F01_REG_3) },
9392     { RM_TABLE (RM_0F01_REG_3) },
9393   },
9394   {
9395     /* MOD_0F01_REG_7 */
9396     { "invlpg",         { Mb } },
9397     { RM_TABLE (RM_0F01_REG_7) },
9398   },
9399   {
9400     /* MOD_0F12_PREFIX_0 */
9401     { "movlps",         { XM, EXq } },
9402     { "movhlps",        { XM, EXq } },
9403   },
9404   {
9405     /* MOD_0F13 */
9406     { "movlpX",         { EXq, XM } },
9407     { "(bad)",          { XX } },
9408   },
9409   {
9410     /* MOD_0F16_PREFIX_0 */
9411     { "movhps",         { XM, EXq } },
9412     { "movlhps",        { XM, EXq } },
9413   },
9414   {
9415     /* MOD_0F17 */
9416     { "movhpX",         { EXq, XM } },
9417     { "(bad)",          { XX } },
9418   },
9419   {
9420     /* MOD_0F18_REG_0 */
9421     { "prefetchnta",    { Mb } },
9422     { "(bad)",          { XX } },
9423   },
9424   {
9425     /* MOD_0F18_REG_1 */
9426     { "prefetcht0",     { Mb } },
9427     { "(bad)",          { XX } },
9428   },
9429   {
9430     /* MOD_0F18_REG_2 */
9431     { "prefetcht1",     { Mb } },
9432     { "(bad)",          { XX } },
9433   },
9434   {
9435     /* MOD_0F18_REG_3 */
9436     { "prefetcht2",     { Mb } },
9437     { "(bad)",          { XX } },
9438   },
9439   {
9440     /* MOD_0F20 */
9441     { "(bad)",          { XX } },
9442     { "movZ",           { Rm, Cm } },
9443   },
9444   {
9445     /* MOD_0F21 */
9446     { "(bad)",          { XX } },
9447     { "movZ",           { Rm, Dm } },
9448   },
9449   {
9450     /* MOD_0F22 */
9451     { "(bad)",          { XX } },
9452     { "movZ",           { Cm, Rm } },
9453   },
9454   {
9455     /* MOD_0F23 */
9456     { "(bad)",          { XX } },
9457     { "movZ",           { Dm, Rm } },
9458   },
9459   {
9460     /* MOD_0F24 */
9461     { "(bad)",          { XX } },
9462     { "movL",           { Rd, Td } },
9463   },
9464   {
9465     /* MOD_0F26 */
9466     { "(bad)",          { XX } },
9467     { "movL",           { Td, Rd } },
9468   },
9469   {
9470     /* MOD_0F2B_PREFIX_0 */
9471     {"movntps",         { Mx, XM } },
9472     { "(bad)",          { XX } },
9473   },
9474   {
9475     /* MOD_0F2B_PREFIX_1 */
9476     {"movntss",         { Md, XM } },
9477     { "(bad)",          { XX } },
9478   },
9479   {
9480     /* MOD_0F2B_PREFIX_2 */
9481     {"movntpd",         { Mx, XM } },
9482     { "(bad)",          { XX } },
9483   },
9484   {
9485     /* MOD_0F2B_PREFIX_3 */
9486     {"movntsd",         { Mq, XM } },
9487     { "(bad)",          { XX } },
9488   },
9489   {
9490     /* MOD_0F51 */
9491     { "(bad)",          { XX } },
9492     { "movmskpX",       { Gdq, XS } },
9493   },
9494   {
9495     /* MOD_0F71_REG_2 */
9496     { "(bad)",          { XX } },
9497     { "psrlw",          { MS, Ib } },
9498   },
9499   {
9500     /* MOD_0F71_REG_4 */
9501     { "(bad)",          { XX } },
9502     { "psraw",          { MS, Ib } },
9503   },
9504   {
9505     /* MOD_0F71_REG_6 */
9506     { "(bad)",          { XX } },
9507     { "psllw",          { MS, Ib } },
9508   },
9509   {
9510     /* MOD_0F72_REG_2 */
9511     { "(bad)",          { XX } },
9512     { "psrld",          { MS, Ib } },
9513   },
9514   {
9515     /* MOD_0F72_REG_4 */
9516     { "(bad)",          { XX } },
9517     { "psrad",          { MS, Ib } },
9518   },
9519   {
9520     /* MOD_0F72_REG_6 */
9521     { "(bad)",          { XX } },
9522     { "pslld",          { MS, Ib } },
9523   },
9524   {
9525     /* MOD_0F73_REG_2 */
9526     { "(bad)",          { XX } },
9527     { "psrlq",          { MS, Ib } },
9528   },
9529   {
9530     /* MOD_0F73_REG_3 */
9531     { "(bad)",          { XX } },
9532     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
9533   },
9534   {
9535     /* MOD_0F73_REG_6 */
9536     { "(bad)",          { XX } },
9537     { "psllq",          { MS, Ib } },
9538   },
9539   {
9540     /* MOD_0F73_REG_7 */
9541     { "(bad)",          { XX } },
9542     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
9543   },
9544   {
9545     /* MOD_0FAE_REG_0 */
9546     { "fxsave",         { FXSAVE } },
9547     { "(bad)",          { XX } },
9548   },
9549   {
9550     /* MOD_0FAE_REG_1 */
9551     { "fxrstor",        { FXSAVE } },
9552     { "(bad)",          { XX } },
9553   },
9554   {
9555     /* MOD_0FAE_REG_2 */
9556     { "ldmxcsr",        { Md } },
9557     { "(bad)",          { XX } },
9558   },
9559   {
9560     /* MOD_0FAE_REG_3 */
9561     { "stmxcsr",        { Md } },
9562     { "(bad)",          { XX } },
9563   },
9564   {
9565     /* MOD_0FAE_REG_4 */
9566     { "xsave",          { M } },
9567     { "(bad)",          { XX } },
9568   },
9569   {
9570     /* MOD_0FAE_REG_5 */
9571     { "xrstor",         { M } },
9572     { RM_TABLE (RM_0FAE_REG_5) },
9573   },
9574   {
9575     /* MOD_0FAE_REG_6 */
9576     { "xsaveopt",       { M } },
9577     { RM_TABLE (RM_0FAE_REG_6) },
9578   },
9579   {
9580     /* MOD_0FAE_REG_7 */
9581     { "clflush",        { Mb } },
9582     { RM_TABLE (RM_0FAE_REG_7) },
9583   },
9584   {
9585     /* MOD_0FB2 */
9586     { "lssS",           { Gv, Mp } },
9587     { "(bad)",          { XX } },
9588   },
9589   {
9590     /* MOD_0FB4 */
9591     { "lfsS",           { Gv, Mp } },
9592     { "(bad)",          { XX } },
9593   },
9594   {
9595     /* MOD_0FB5 */
9596     { "lgsS",           { Gv, Mp } },
9597     { "(bad)",          { XX } },
9598   },
9599   {
9600     /* MOD_0FC7_REG_6 */
9601     { PREFIX_TABLE (PREFIX_0FC7_REG_6) },
9602     { "(bad)",          { XX } },
9603   },
9604   {
9605     /* MOD_0FC7_REG_7 */
9606     { "vmptrst",        { Mq } },
9607     { "(bad)",          { XX } },
9608   },
9609   {
9610     /* MOD_0FD7 */
9611     { "(bad)",          { XX } },
9612     { "pmovmskb",       { Gdq, MS } },
9613   },
9614   {
9615     /* MOD_0FE7_PREFIX_2 */
9616     { "movntdq",        { Mx, XM } },
9617     { "(bad)",          { XX } },
9618   },
9619   {
9620     /* MOD_0FF0_PREFIX_3 */
9621     { "lddqu",          { XM, M } },
9622     { "(bad)",          { XX } },
9623   },
9624   {
9625     /* MOD_0F382A_PREFIX_2 */
9626     { "movntdqa",       { XM, Mx } },
9627     { "(bad)",          { XX } },
9628   },
9629   {
9630     /* MOD_62_32BIT */
9631     { "bound{S|}",      { Gv, Ma } },
9632     { "(bad)",          { XX } },
9633   },
9634   {
9635     /* MOD_C4_32BIT */
9636     { "lesS",           { Gv, Mp } },
9637     { VEX_C4_TABLE (VEX_0F) },
9638   },
9639   {
9640     /* MOD_C5_32BIT */
9641     { "ldsS",           { Gv, Mp } },
9642     { VEX_C5_TABLE (VEX_0F) },
9643   },
9644   {
9645     /* MOD_VEX_12_PREFIX_0 */
9646     { VEX_LEN_TABLE (VEX_LEN_12_P_0_M_0) },
9647     { VEX_LEN_TABLE (VEX_LEN_12_P_0_M_1) },
9648   },
9649   {
9650     /* MOD_VEX_13 */
9651     { VEX_LEN_TABLE (VEX_LEN_13_M_0) },
9652     { "(bad)",          { XX } },
9653   },
9654   {
9655     /* MOD_VEX_16_PREFIX_0 */
9656     { VEX_LEN_TABLE (VEX_LEN_16_P_0_M_0) },
9657     { VEX_LEN_TABLE (VEX_LEN_16_P_0_M_1) },
9658   },
9659   {
9660     /* MOD_VEX_17 */
9661     { VEX_LEN_TABLE (VEX_LEN_17_M_0) },
9662     { "(bad)",          { XX } },
9663   },
9664   {
9665     /* MOD_VEX_2B */
9666     { "vmovntpX",       { Mx, XM } },
9667     { "(bad)",          { XX } },
9668   },
9669   {
9670     /* MOD_VEX_50 */
9671     { "(bad)",          { XX } },
9672     { "vmovmskpX",      { Gdq, XS } },
9673   },
9674   {
9675     /* MOD_VEX_71_REG_2 */
9676     { "(bad)",          { XX } },
9677     { PREFIX_TABLE (PREFIX_VEX_71_REG_2) },
9678   },
9679   {
9680     /* MOD_VEX_71_REG_4 */
9681     { "(bad)",          { XX } },
9682     { PREFIX_TABLE (PREFIX_VEX_71_REG_4) },
9683   },
9684   {
9685     /* MOD_VEX_71_REG_6 */
9686     { "(bad)",          { XX } },
9687     { PREFIX_TABLE (PREFIX_VEX_71_REG_6) },
9688   },
9689   {
9690     /* MOD_VEX_72_REG_2 */
9691     { "(bad)",          { XX } },
9692     { PREFIX_TABLE (PREFIX_VEX_72_REG_2) },
9693   },
9694   {
9695     /* MOD_VEX_72_REG_4 */
9696     { "(bad)",          { XX } },
9697     { PREFIX_TABLE (PREFIX_VEX_72_REG_4) },
9698   },
9699   {
9700     /* MOD_VEX_72_REG_6 */
9701     { "(bad)",          { XX } },
9702     { PREFIX_TABLE (PREFIX_VEX_72_REG_6) },
9703   },
9704   {
9705     /* MOD_VEX_73_REG_2 */
9706     { "(bad)",          { XX } },
9707     { PREFIX_TABLE (PREFIX_VEX_73_REG_2) },
9708   },
9709   {
9710     /* MOD_VEX_73_REG_3 */
9711     { "(bad)",          { XX } },
9712     { PREFIX_TABLE (PREFIX_VEX_73_REG_3) },
9713   },
9714   {
9715     /* MOD_VEX_73_REG_6 */
9716     { "(bad)",          { XX } },
9717     { PREFIX_TABLE (PREFIX_VEX_73_REG_6) },
9718   },
9719   {
9720     /* MOD_VEX_73_REG_7 */
9721     { "(bad)",          { XX } },
9722     { PREFIX_TABLE (PREFIX_VEX_73_REG_7) },
9723   },
9724   {
9725     /* MOD_VEX_AE_REG_2 */
9726     { VEX_LEN_TABLE (VEX_LEN_AE_R_2_M_0) },
9727     { "(bad)",          { XX } },
9728   },
9729   {
9730     /* MOD_VEX_AE_REG_3 */
9731     { VEX_LEN_TABLE (VEX_LEN_AE_R_3_M_0) },
9732     { "(bad)",          { XX } },
9733   },
9734   {
9735     /* MOD_VEX_D7_PREFIX_2 */
9736     { "(bad)",          { XX } },
9737     { VEX_LEN_TABLE (VEX_LEN_D7_P_2_M_1) },
9738   },
9739   {
9740     /* MOD_VEX_E7_PREFIX_2 */
9741     { "vmovntdq",       { Mx, XM } },
9742     { "(bad)",          { XX } },
9743   },
9744   {
9745     /* MOD_VEX_F0_PREFIX_3 */
9746     { "vlddqu",         { XM, M } },
9747     { "(bad)",          { XX } },
9748   },
9749   {
9750     /* MOD_VEX_3818_PREFIX_2 */
9751     { "vbroadcastss",   { XM, Md } },
9752     { "(bad)",          { XX } },
9753   },
9754   {
9755     /* MOD_VEX_3819_PREFIX_2 */
9756     { VEX_LEN_TABLE (VEX_LEN_3819_P_2_M_0) },
9757     { "(bad)",          { XX } },
9758   },
9759   {
9760     /* MOD_VEX_381A_PREFIX_2 */
9761     { VEX_LEN_TABLE (VEX_LEN_381A_P_2_M_0) },
9762     { "(bad)",          { XX } },
9763   },
9764   {
9765     /* MOD_VEX_382A_PREFIX_2 */
9766     { VEX_LEN_TABLE (VEX_LEN_382A_P_2_M_0) },
9767     { "(bad)",          { XX } },
9768   },
9769   {
9770     /* MOD_VEX_382C_PREFIX_2 */
9771     { "vmaskmovps",     { XM, Vex, Mx } },
9772     { "(bad)",          { XX } },
9773   },
9774   {
9775     /* MOD_VEX_382D_PREFIX_2 */
9776     { "vmaskmovpd",     { XM, Vex, Mx } },
9777     { "(bad)",          { XX } },
9778   },
9779   {
9780     /* MOD_VEX_382E_PREFIX_2 */
9781     { "vmaskmovps",     { Mx, Vex, XM } },
9782     { "(bad)",          { XX } },
9783   },
9784   {
9785     /* MOD_VEX_382F_PREFIX_2 */
9786     { "vmaskmovpd",     { Mx, Vex, XM } },
9787     { "(bad)",          { XX } },
9788   },
9789 };
9790
9791 static const struct dis386 rm_table[][8] = {
9792   {
9793     /* RM_0F01_REG_0 */
9794     { "(bad)",          { XX } },
9795     { "vmcall",         { Skip_MODRM } },
9796     { "vmlaunch",       { Skip_MODRM } },
9797     { "vmresume",       { Skip_MODRM } },
9798     { "vmxoff",         { Skip_MODRM } },
9799     { "(bad)",          { XX } },
9800     { "(bad)",          { XX } },
9801     { "(bad)",          { XX } },
9802   },
9803   {
9804     /* RM_0F01_REG_1 */
9805     { "monitor",        { { OP_Monitor, 0 } } },
9806     { "mwait",          { { OP_Mwait, 0 } } },
9807     { "(bad)",          { XX } },
9808     { "(bad)",          { XX } },
9809     { "(bad)",          { XX } },
9810     { "(bad)",          { XX } },
9811     { "(bad)",          { XX } },
9812     { "(bad)",          { XX } },
9813   },
9814   {
9815     /* RM_0F01_REG_2 */
9816     { "xgetbv",         { Skip_MODRM } },
9817     { "xsetbv",         { Skip_MODRM } },
9818     { "(bad)",          { XX } },
9819     { "(bad)",          { XX } },
9820     { "(bad)",          { XX } },
9821     { "(bad)",          { XX } },
9822     { "(bad)",          { XX } },
9823     { "(bad)",          { XX } },
9824   },
9825   {
9826     /* RM_0F01_REG_3 */
9827     { "vmrun",          { Skip_MODRM } },
9828     { "vmmcall",        { Skip_MODRM } },
9829     { "vmload",         { Skip_MODRM } },
9830     { "vmsave",         { Skip_MODRM } },
9831     { "stgi",           { Skip_MODRM } },
9832     { "clgi",           { Skip_MODRM } },
9833     { "skinit",         { Skip_MODRM } },
9834     { "invlpga",        { Skip_MODRM } },
9835   },
9836   {
9837     /* RM_0F01_REG_7 */
9838     { "swapgs",         { Skip_MODRM } },
9839     { "rdtscp",         { Skip_MODRM } },
9840     { "(bad)",          { XX } },
9841     { "(bad)",          { XX } },
9842     { "(bad)",          { XX } },
9843     { "(bad)",          { XX } },
9844     { "(bad)",          { XX } },
9845     { "(bad)",          { XX } },
9846   },
9847   {
9848     /* RM_0FAE_REG_5 */
9849     { "lfence",         { Skip_MODRM } },
9850     { "(bad)",          { XX } },
9851     { "(bad)",          { XX } },
9852     { "(bad)",          { XX } },
9853     { "(bad)",          { XX } },
9854     { "(bad)",          { XX } },
9855     { "(bad)",          { XX } },
9856     { "(bad)",          { XX } },
9857   },
9858   {
9859     /* RM_0FAE_REG_6 */
9860     { "mfence",         { Skip_MODRM } },
9861     { "(bad)",          { XX } },
9862     { "(bad)",          { XX } },
9863     { "(bad)",          { XX } },
9864     { "(bad)",          { XX } },
9865     { "(bad)",          { XX } },
9866     { "(bad)",          { XX } },
9867     { "(bad)",          { XX } },
9868   },
9869   {
9870     /* RM_0FAE_REG_7 */
9871     { "sfence",         { Skip_MODRM } },
9872     { "(bad)",          { XX } },
9873     { "(bad)",          { XX } },
9874     { "(bad)",          { XX } },
9875     { "(bad)",          { XX } },
9876     { "(bad)",          { XX } },
9877     { "(bad)",          { XX } },
9878     { "(bad)",          { XX } },
9879   },
9880 };
9881
9882 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
9883
9884 /* We use the high bit to indicate different name for the same
9885    prefix.  */
9886 #define ADDR16_PREFIX   (0x67 | 0x100)
9887 #define ADDR32_PREFIX   (0x67 | 0x200)
9888 #define DATA16_PREFIX   (0x66 | 0x100)
9889 #define DATA32_PREFIX   (0x66 | 0x200)
9890 #define REP_PREFIX      (0xf3 | 0x100)
9891
9892 static int
9893 ckprefix (void)
9894 {
9895   int newrex, i, length;
9896   rex = 0;
9897   rex_original = 0;
9898   rex_ignored = 0;
9899   prefixes = 0;
9900   used_prefixes = 0;
9901   rex_used = 0;
9902   last_lock_prefix = -1;
9903   last_repz_prefix = -1;
9904   last_repnz_prefix = -1;
9905   last_data_prefix = -1;
9906   last_addr_prefix = -1;
9907   last_rex_prefix = -1;
9908   last_seg_prefix = -1;
9909   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
9910     all_prefixes[i] = 0;
9911   i = 0;
9912   length = 0;
9913   /* The maximum instruction length is 15bytes.  */
9914   while (length < MAX_CODE_LENGTH - 1)
9915     {
9916       FETCH_DATA (the_info, codep + 1);
9917       newrex = 0;
9918       switch (*codep)
9919         {
9920         /* REX prefixes family.  */
9921         case 0x40:
9922         case 0x41:
9923         case 0x42:
9924         case 0x43:
9925         case 0x44:
9926         case 0x45:
9927         case 0x46:
9928         case 0x47:
9929         case 0x48:
9930         case 0x49:
9931         case 0x4a:
9932         case 0x4b:
9933         case 0x4c:
9934         case 0x4d:
9935         case 0x4e:
9936         case 0x4f:
9937           if (address_mode == mode_64bit)
9938             newrex = *codep;
9939           else
9940             return 1;
9941           last_rex_prefix = i;
9942           break;
9943         case 0xf3:
9944           prefixes |= PREFIX_REPZ;
9945           last_repz_prefix = i;
9946           break;
9947         case 0xf2:
9948           prefixes |= PREFIX_REPNZ;
9949           last_repnz_prefix = i;
9950           break;
9951         case 0xf0:
9952           prefixes |= PREFIX_LOCK;
9953           last_lock_prefix = i;
9954           break;
9955         case 0x2e:
9956           prefixes |= PREFIX_CS;
9957           last_seg_prefix = i;
9958           break;
9959         case 0x36:
9960           prefixes |= PREFIX_SS;
9961           last_seg_prefix = i;
9962           break;
9963         case 0x3e:
9964           prefixes |= PREFIX_DS;
9965           last_seg_prefix = i;
9966           break;
9967         case 0x26:
9968           prefixes |= PREFIX_ES;
9969           last_seg_prefix = i;
9970           break;
9971         case 0x64:
9972           prefixes |= PREFIX_FS;
9973           last_seg_prefix = i;
9974           break;
9975         case 0x65:
9976           prefixes |= PREFIX_GS;
9977           last_seg_prefix = i;
9978           break;
9979         case 0x66:
9980           prefixes |= PREFIX_DATA;
9981           last_data_prefix = i;
9982           break;
9983         case 0x67:
9984           prefixes |= PREFIX_ADDR;
9985           last_addr_prefix = i;
9986           break;
9987         case FWAIT_OPCODE:
9988           /* fwait is really an instruction.  If there are prefixes
9989              before the fwait, they belong to the fwait, *not* to the
9990              following instruction.  */
9991           if (prefixes || rex)
9992             {
9993               prefixes |= PREFIX_FWAIT;
9994               codep++;
9995               return 1;
9996             }
9997           prefixes = PREFIX_FWAIT;
9998           break;
9999         default:
10000           return 1;
10001         }
10002       /* Rex is ignored when followed by another prefix.  */
10003       if (rex)
10004         {
10005           rex_used = rex;
10006           return 1;
10007         }
10008       if (*codep != FWAIT_OPCODE)
10009         all_prefixes[i++] = *codep;
10010       rex = newrex;
10011       rex_original = rex;
10012       codep++;
10013       length++;
10014     }
10015   return 0;
10016 }
10017
10018 static int
10019 seg_prefix (int pref)
10020 {
10021   switch (pref)
10022     {
10023     case 0x2e:
10024       return PREFIX_CS;
10025     case 0x36:
10026       return PREFIX_SS;
10027     case 0x3e:
10028       return PREFIX_DS;
10029     case 0x26:
10030       return PREFIX_ES;
10031     case 0x64:
10032       return PREFIX_FS;
10033     case 0x65:
10034       return PREFIX_GS;
10035     default:
10036       return 0;
10037     }
10038 }
10039
10040 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
10041    prefix byte.  */
10042
10043 static const char *
10044 prefix_name (int pref, int sizeflag)
10045 {
10046   static const char *rexes [16] =
10047     {
10048       "rex",            /* 0x40 */
10049       "rex.B",          /* 0x41 */
10050       "rex.X",          /* 0x42 */
10051       "rex.XB",         /* 0x43 */
10052       "rex.R",          /* 0x44 */
10053       "rex.RB",         /* 0x45 */
10054       "rex.RX",         /* 0x46 */
10055       "rex.RXB",        /* 0x47 */
10056       "rex.W",          /* 0x48 */
10057       "rex.WB",         /* 0x49 */
10058       "rex.WX",         /* 0x4a */
10059       "rex.WXB",        /* 0x4b */
10060       "rex.WR",         /* 0x4c */
10061       "rex.WRB",        /* 0x4d */
10062       "rex.WRX",        /* 0x4e */
10063       "rex.WRXB",       /* 0x4f */
10064     };
10065
10066   switch (pref)
10067     {
10068     /* REX prefixes family.  */
10069     case 0x40:
10070     case 0x41:
10071     case 0x42:
10072     case 0x43:
10073     case 0x44:
10074     case 0x45:
10075     case 0x46:
10076     case 0x47:
10077     case 0x48:
10078     case 0x49:
10079     case 0x4a:
10080     case 0x4b:
10081     case 0x4c:
10082     case 0x4d:
10083     case 0x4e:
10084     case 0x4f:
10085       return rexes [pref - 0x40];
10086     case 0xf3:
10087       return "repz";
10088     case 0xf2:
10089       return "repnz";
10090     case 0xf0:
10091       return "lock";
10092     case 0x2e:
10093       return "cs";
10094     case 0x36:
10095       return "ss";
10096     case 0x3e:
10097       return "ds";
10098     case 0x26:
10099       return "es";
10100     case 0x64:
10101       return "fs";
10102     case 0x65:
10103       return "gs";
10104     case 0x66:
10105       return (sizeflag & DFLAG) ? "data16" : "data32";
10106     case 0x67:
10107       if (address_mode == mode_64bit)
10108         return (sizeflag & AFLAG) ? "addr32" : "addr64";
10109       else
10110         return (sizeflag & AFLAG) ? "addr16" : "addr32";
10111     case FWAIT_OPCODE:
10112       return "fwait";
10113     case ADDR16_PREFIX:
10114       return "addr16";
10115     case ADDR32_PREFIX:
10116       return "addr32";
10117     case DATA16_PREFIX:
10118       return "data16";
10119     case DATA32_PREFIX:
10120       return "data32";
10121     case REP_PREFIX:
10122       return "rep";
10123     default:
10124       return NULL;
10125     }
10126 }
10127
10128 static char op_out[MAX_OPERANDS][100];
10129 static int op_ad, op_index[MAX_OPERANDS];
10130 static int two_source_ops;
10131 static bfd_vma op_address[MAX_OPERANDS];
10132 static bfd_vma op_riprel[MAX_OPERANDS];
10133 static bfd_vma start_pc;
10134
10135 /*
10136  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
10137  *   (see topic "Redundant prefixes" in the "Differences from 8086"
10138  *   section of the "Virtual 8086 Mode" chapter.)
10139  * 'pc' should be the address of this instruction, it will
10140  *   be used to print the target address if this is a relative jump or call
10141  * The function returns the length of this instruction in bytes.
10142  */
10143
10144 static char intel_syntax;
10145 static char intel_mnemonic = !SYSV386_COMPAT;
10146 static char open_char;
10147 static char close_char;
10148 static char separator_char;
10149 static char scale_char;
10150
10151 /* Here for backwards compatibility.  When gdb stops using
10152    print_insn_i386_att and print_insn_i386_intel these functions can
10153    disappear, and print_insn_i386 be merged into print_insn.  */
10154 int
10155 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
10156 {
10157   intel_syntax = 0;
10158
10159   return print_insn (pc, info);
10160 }
10161
10162 int
10163 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
10164 {
10165   intel_syntax = 1;
10166
10167   return print_insn (pc, info);
10168 }
10169
10170 int
10171 print_insn_i386 (bfd_vma pc, disassemble_info *info)
10172 {
10173   intel_syntax = -1;
10174
10175   return print_insn (pc, info);
10176 }
10177
10178 void
10179 print_i386_disassembler_options (FILE *stream)
10180 {
10181   fprintf (stream, _("\n\
10182 The following i386/x86-64 specific disassembler options are supported for use\n\
10183 with the -M switch (multiple options should be separated by commas):\n"));
10184
10185   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
10186   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
10187   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
10188   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
10189   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
10190   fprintf (stream, _("  att-mnemonic\n"
10191                      "              Display instruction in AT&T mnemonic\n"));
10192   fprintf (stream, _("  intel-mnemonic\n"
10193                      "              Display instruction in Intel mnemonic\n"));
10194   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
10195   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
10196   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
10197   fprintf (stream, _("  data32      Assume 32bit data size\n"));
10198   fprintf (stream, _("  data16      Assume 16bit data size\n"));
10199   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
10200 }
10201
10202 /* Get a pointer to struct dis386 with a valid name.  */
10203
10204 static const struct dis386 *
10205 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
10206 {
10207   int vindex, vex_table_index;
10208
10209   if (dp->name != NULL)
10210     return dp;
10211
10212   switch (dp->op[0].bytemode)
10213     {
10214     case USE_REG_TABLE:
10215       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
10216       break;
10217
10218     case USE_MOD_TABLE:
10219       vindex = modrm.mod == 0x3 ? 1 : 0;
10220       dp = &mod_table[dp->op[1].bytemode][vindex];
10221       break;
10222
10223     case USE_RM_TABLE:
10224       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
10225       break;
10226
10227     case USE_PREFIX_TABLE:
10228       if (need_vex)
10229         {
10230           /* The prefix in VEX is implicit.  */
10231           switch (vex.prefix)
10232             {
10233             case 0:
10234               vindex = 0;
10235               break;
10236             case REPE_PREFIX_OPCODE:
10237               vindex = 1;
10238               break;
10239             case DATA_PREFIX_OPCODE:
10240               vindex = 2;
10241               break;
10242             case REPNE_PREFIX_OPCODE:
10243               vindex = 3;
10244               break;
10245             default:
10246               abort ();
10247               break;
10248             }
10249         }
10250       else
10251         {
10252           vindex = 0;
10253           used_prefixes |= (prefixes & PREFIX_REPZ);
10254           if (prefixes & PREFIX_REPZ)
10255             {
10256               vindex = 1;
10257               all_prefixes[last_repz_prefix] = 0;
10258             }
10259           else
10260             {
10261               /* We should check PREFIX_REPNZ and PREFIX_REPZ before
10262                  PREFIX_DATA.  */
10263               used_prefixes |= (prefixes & PREFIX_REPNZ);
10264               if (prefixes & PREFIX_REPNZ)
10265                 {
10266                   vindex = 3;
10267                   all_prefixes[last_repnz_prefix] = 0;
10268                 }
10269               else
10270                 {
10271                   used_prefixes |= (prefixes & PREFIX_DATA);
10272                   if (prefixes & PREFIX_DATA)
10273                     {
10274                       vindex = 2;
10275                       all_prefixes[last_data_prefix] = 0;
10276                     }
10277                 }
10278             }
10279         }
10280       dp = &prefix_table[dp->op[1].bytemode][vindex];
10281       break;
10282
10283     case USE_X86_64_TABLE:
10284       vindex = address_mode == mode_64bit ? 1 : 0;
10285       dp = &x86_64_table[dp->op[1].bytemode][vindex];
10286       break;
10287
10288     case USE_3BYTE_TABLE:
10289       FETCH_DATA (info, codep + 2);
10290       vindex = *codep++;
10291       dp = &three_byte_table[dp->op[1].bytemode][vindex];
10292       modrm.mod = (*codep >> 6) & 3;
10293       modrm.reg = (*codep >> 3) & 7;
10294       modrm.rm = *codep & 7;
10295       break;
10296
10297     case USE_VEX_LEN_TABLE:
10298       if (!need_vex)
10299         abort ();
10300
10301       switch (vex.length)
10302         {
10303         case 128:
10304           vindex = 0;
10305           break;
10306         case 256:
10307           vindex = 1;
10308           break;
10309         default:
10310           abort ();
10311           break;
10312         }
10313
10314       dp = &vex_len_table[dp->op[1].bytemode][vindex];
10315       break;
10316
10317     case USE_XOP_8F_TABLE:
10318       FETCH_DATA (info, codep + 3);
10319       /* All bits in the REX prefix are ignored.  */
10320       rex_ignored = rex;
10321       rex = ~(*codep >> 5) & 0x7;
10322
10323       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
10324       switch ((*codep & 0x1f))
10325         {
10326         default:
10327           BadOp ();
10328         case 0x8:
10329           vex_table_index = XOP_08;
10330           break;
10331         case 0x9:
10332           vex_table_index = XOP_09;
10333           break;
10334         case 0xa:
10335           vex_table_index = XOP_0A;
10336           break;
10337         }
10338       codep++;
10339       vex.w = *codep & 0x80;
10340       if (vex.w && address_mode == mode_64bit)
10341         rex |= REX_W;
10342
10343       vex.register_specifier = (~(*codep >> 3)) & 0xf;
10344       if (address_mode != mode_64bit
10345           && vex.register_specifier > 0x7)
10346         BadOp ();
10347
10348       vex.length = (*codep & 0x4) ? 256 : 128;
10349       switch ((*codep & 0x3))
10350         {
10351         case 0:
10352           vex.prefix = 0;
10353           break;
10354         case 1:
10355           vex.prefix = DATA_PREFIX_OPCODE;
10356           break;
10357         case 2:
10358           vex.prefix = REPE_PREFIX_OPCODE;
10359           break;
10360         case 3:
10361           vex.prefix = REPNE_PREFIX_OPCODE;
10362           break;
10363         }
10364       need_vex = 1;
10365       need_vex_reg = 1;
10366       codep++;
10367       vindex = *codep++;
10368       dp = &xop_table[vex_table_index][vindex];
10369
10370       FETCH_DATA (info, codep + 1);
10371       modrm.mod = (*codep >> 6) & 3;
10372       modrm.reg = (*codep >> 3) & 7;
10373       modrm.rm = *codep & 7;
10374       break;
10375
10376     case USE_VEX_C4_TABLE:
10377       FETCH_DATA (info, codep + 3);
10378       /* All bits in the REX prefix are ignored.  */
10379       rex_ignored = rex;
10380       rex = ~(*codep >> 5) & 0x7;
10381       switch ((*codep & 0x1f))
10382         {
10383         default:
10384           BadOp ();
10385         case 0x1:
10386           vex_table_index = VEX_0F;
10387           break;
10388         case 0x2:
10389           vex_table_index = VEX_0F38;
10390           break;
10391         case 0x3:
10392           vex_table_index = VEX_0F3A;
10393           break;
10394         }
10395       codep++;
10396       vex.w = *codep & 0x80;
10397       if (vex.w && address_mode == mode_64bit)
10398         rex |= REX_W;
10399
10400       vex.register_specifier = (~(*codep >> 3)) & 0xf;
10401       if (address_mode != mode_64bit
10402           && vex.register_specifier > 0x7)
10403         BadOp ();
10404
10405       vex.length = (*codep & 0x4) ? 256 : 128;
10406       switch ((*codep & 0x3))
10407         {
10408         case 0:
10409           vex.prefix = 0;
10410           break;
10411         case 1:
10412           vex.prefix = DATA_PREFIX_OPCODE;
10413           break;
10414         case 2:
10415           vex.prefix = REPE_PREFIX_OPCODE;
10416           break;
10417         case 3:
10418           vex.prefix = REPNE_PREFIX_OPCODE;
10419           break;
10420         }
10421       need_vex = 1;
10422       need_vex_reg = 1;
10423       codep++;
10424       vindex = *codep++;
10425       dp = &vex_table[vex_table_index][vindex];
10426       /* There is no MODRM byte for VEX [82|77].  */
10427       if (vindex != 0x77 && vindex != 0x82)
10428         {
10429           FETCH_DATA (info, codep + 1);
10430           modrm.mod = (*codep >> 6) & 3;
10431           modrm.reg = (*codep >> 3) & 7;
10432           modrm.rm = *codep & 7;
10433         }
10434       break;
10435
10436     case USE_VEX_C5_TABLE:
10437       FETCH_DATA (info, codep + 2);
10438       /* All bits in the REX prefix are ignored.  */
10439       rex_ignored = rex;
10440       rex = (*codep & 0x80) ? 0 : REX_R;
10441
10442       vex.register_specifier = (~(*codep >> 3)) & 0xf;
10443       if (address_mode != mode_64bit
10444           && vex.register_specifier > 0x7)
10445         BadOp ();
10446
10447       vex.w = 0;
10448
10449       vex.length = (*codep & 0x4) ? 256 : 128;
10450       switch ((*codep & 0x3))
10451         {
10452         case 0:
10453           vex.prefix = 0;
10454           break;
10455         case 1:
10456           vex.prefix = DATA_PREFIX_OPCODE;
10457           break;
10458         case 2:
10459           vex.prefix = REPE_PREFIX_OPCODE;
10460           break;
10461         case 3:
10462           vex.prefix = REPNE_PREFIX_OPCODE;
10463           break;
10464         }
10465       need_vex = 1;
10466       need_vex_reg = 1;
10467       codep++;
10468       vindex = *codep++;
10469       dp = &vex_table[dp->op[1].bytemode][vindex];
10470       /* There is no MODRM byte for VEX [82|77].  */
10471       if (vindex != 0x77 && vindex != 0x82)
10472         {
10473           FETCH_DATA (info, codep + 1);
10474           modrm.mod = (*codep >> 6) & 3;
10475           modrm.reg = (*codep >> 3) & 7;
10476           modrm.rm = *codep & 7;
10477         }
10478       break;
10479
10480     default:
10481       abort ();
10482     }
10483
10484   if (dp->name != NULL)
10485     return dp;
10486   else
10487     return get_valid_dis386 (dp, info);
10488 }
10489
10490 static int
10491 print_insn (bfd_vma pc, disassemble_info *info)
10492 {
10493   const struct dis386 *dp;
10494   int i;
10495   char *op_txt[MAX_OPERANDS];
10496   int needcomma;
10497   int sizeflag;
10498   const char *p;
10499   struct dis_private priv;
10500   unsigned char op;
10501   int prefix_length;
10502   int default_prefixes;
10503
10504   if (info->mach == bfd_mach_x86_64_intel_syntax
10505       || info->mach == bfd_mach_x86_64
10506       || info->mach == bfd_mach_l1om
10507       || info->mach == bfd_mach_l1om_intel_syntax)
10508     address_mode = mode_64bit;
10509   else
10510     address_mode = mode_32bit;
10511
10512   if (intel_syntax == (char) -1)
10513     intel_syntax = (info->mach == bfd_mach_i386_i386_intel_syntax
10514                     || info->mach == bfd_mach_x86_64_intel_syntax
10515                     || info->mach == bfd_mach_l1om_intel_syntax);
10516
10517   if (info->mach == bfd_mach_i386_i386
10518       || info->mach == bfd_mach_x86_64
10519       || info->mach == bfd_mach_l1om
10520       || info->mach == bfd_mach_i386_i386_intel_syntax
10521       || info->mach == bfd_mach_x86_64_intel_syntax
10522       || info->mach == bfd_mach_l1om_intel_syntax)
10523     priv.orig_sizeflag = AFLAG | DFLAG;
10524   else if (info->mach == bfd_mach_i386_i8086)
10525     priv.orig_sizeflag = 0;
10526   else
10527     abort ();
10528
10529   for (p = info->disassembler_options; p != NULL; )
10530     {
10531       if (CONST_STRNEQ (p, "x86-64"))
10532         {
10533           address_mode = mode_64bit;
10534           priv.orig_sizeflag = AFLAG | DFLAG;
10535         }
10536       else if (CONST_STRNEQ (p, "i386"))
10537         {
10538           address_mode = mode_32bit;
10539           priv.orig_sizeflag = AFLAG | DFLAG;
10540         }
10541       else if (CONST_STRNEQ (p, "i8086"))
10542         {
10543           address_mode = mode_16bit;
10544           priv.orig_sizeflag = 0;
10545         }
10546       else if (CONST_STRNEQ (p, "intel"))
10547         {
10548           intel_syntax = 1;
10549           if (CONST_STRNEQ (p + 5, "-mnemonic"))
10550             intel_mnemonic = 1;
10551         }
10552       else if (CONST_STRNEQ (p, "att"))
10553         {
10554           intel_syntax = 0;
10555           if (CONST_STRNEQ (p + 3, "-mnemonic"))
10556             intel_mnemonic = 0;
10557         }
10558       else if (CONST_STRNEQ (p, "addr"))
10559         {
10560           if (address_mode == mode_64bit)
10561             {
10562               if (p[4] == '3' && p[5] == '2')
10563                 priv.orig_sizeflag &= ~AFLAG;
10564               else if (p[4] == '6' && p[5] == '4')
10565                 priv.orig_sizeflag |= AFLAG;
10566             }
10567           else
10568             {
10569               if (p[4] == '1' && p[5] == '6')
10570                 priv.orig_sizeflag &= ~AFLAG;
10571               else if (p[4] == '3' && p[5] == '2')
10572                 priv.orig_sizeflag |= AFLAG;
10573             }
10574         }
10575       else if (CONST_STRNEQ (p, "data"))
10576         {
10577           if (p[4] == '1' && p[5] == '6')
10578             priv.orig_sizeflag &= ~DFLAG;
10579           else if (p[4] == '3' && p[5] == '2')
10580             priv.orig_sizeflag |= DFLAG;
10581         }
10582       else if (CONST_STRNEQ (p, "suffix"))
10583         priv.orig_sizeflag |= SUFFIX_ALWAYS;
10584
10585       p = strchr (p, ',');
10586       if (p != NULL)
10587         p++;
10588     }
10589
10590   if (intel_syntax)
10591     {
10592       names64 = intel_names64;
10593       names32 = intel_names32;
10594       names16 = intel_names16;
10595       names8 = intel_names8;
10596       names8rex = intel_names8rex;
10597       names_seg = intel_names_seg;
10598       index64 = intel_index64;
10599       index32 = intel_index32;
10600       index16 = intel_index16;
10601       open_char = '[';
10602       close_char = ']';
10603       separator_char = '+';
10604       scale_char = '*';
10605     }
10606   else
10607     {
10608       names64 = att_names64;
10609       names32 = att_names32;
10610       names16 = att_names16;
10611       names8 = att_names8;
10612       names8rex = att_names8rex;
10613       names_seg = att_names_seg;
10614       index64 = att_index64;
10615       index32 = att_index32;
10616       index16 = att_index16;
10617       open_char = '(';
10618       close_char =  ')';
10619       separator_char = ',';
10620       scale_char = ',';
10621     }
10622
10623   /* The output looks better if we put 7 bytes on a line, since that
10624      puts most long word instructions on a single line.  Use 8 bytes
10625      for Intel L1OM.  */
10626   if (info->mach == bfd_mach_l1om
10627       || info->mach == bfd_mach_l1om_intel_syntax)
10628     info->bytes_per_line = 8;
10629   else
10630     info->bytes_per_line = 7;
10631
10632   info->private_data = &priv;
10633   priv.max_fetched = priv.the_buffer;
10634   priv.insn_start = pc;
10635
10636   obuf[0] = 0;
10637   for (i = 0; i < MAX_OPERANDS; ++i)
10638     {
10639       op_out[i][0] = 0;
10640       op_index[i] = -1;
10641     }
10642
10643   the_info = info;
10644   start_pc = pc;
10645   start_codep = priv.the_buffer;
10646   codep = priv.the_buffer;
10647
10648   if (setjmp (priv.bailout) != 0)
10649     {
10650       const char *name;
10651
10652       /* Getting here means we tried for data but didn't get it.  That
10653          means we have an incomplete instruction of some sort.  Just
10654          print the first byte as a prefix or a .byte pseudo-op.  */
10655       if (codep > priv.the_buffer)
10656         {
10657           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
10658           if (name != NULL)
10659             (*info->fprintf_func) (info->stream, "%s", name);
10660           else
10661             {
10662               /* Just print the first byte as a .byte instruction.  */
10663               (*info->fprintf_func) (info->stream, ".byte 0x%x",
10664                                      (unsigned int) priv.the_buffer[0]);
10665             }
10666
10667           return 1;
10668         }
10669
10670       return -1;
10671     }
10672
10673   obufp = obuf;
10674   sizeflag = priv.orig_sizeflag;
10675
10676   if (!ckprefix () || rex_used)
10677     {
10678       /* Too many prefixes or unused REX prefixes.  */
10679       for (i = 0;
10680            all_prefixes[i] && i < (int) ARRAY_SIZE (all_prefixes);
10681            i++)
10682         (*info->fprintf_func) (info->stream, "%s",
10683                                prefix_name (all_prefixes[i], sizeflag));
10684       return 1;
10685     }
10686
10687   insn_codep = codep;
10688
10689   FETCH_DATA (info, codep + 1);
10690   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
10691
10692   if (((prefixes & PREFIX_FWAIT)
10693        && ((*codep < 0xd8) || (*codep > 0xdf))))
10694     {
10695       (*info->fprintf_func) (info->stream, "fwait");
10696       return 1;
10697     }
10698
10699   op = 0;
10700
10701   if (*codep == 0x0f)
10702     {
10703       unsigned char threebyte;
10704       FETCH_DATA (info, codep + 2);
10705       threebyte = *++codep;
10706       dp = &dis386_twobyte[threebyte];
10707       need_modrm = twobyte_has_modrm[*codep];
10708       codep++;
10709     }
10710   else
10711     {
10712       dp = &dis386[*codep];
10713       need_modrm = onebyte_has_modrm[*codep];
10714       codep++;
10715     }
10716
10717   if ((prefixes & PREFIX_REPZ))
10718     used_prefixes |= PREFIX_REPZ;
10719   if ((prefixes & PREFIX_REPNZ))
10720     used_prefixes |= PREFIX_REPNZ;
10721   if ((prefixes & PREFIX_LOCK))
10722     used_prefixes |= PREFIX_LOCK;
10723
10724   default_prefixes = 0;
10725   if (prefixes & PREFIX_ADDR)
10726     {
10727       sizeflag ^= AFLAG;
10728       if (dp->op[2].bytemode != loop_jcxz_mode || intel_syntax)
10729         {
10730           if ((sizeflag & AFLAG) || address_mode == mode_64bit)
10731             all_prefixes[last_addr_prefix] = ADDR32_PREFIX;
10732           else
10733             all_prefixes[last_addr_prefix] = ADDR16_PREFIX;
10734           default_prefixes |= PREFIX_ADDR;
10735         }
10736     }
10737
10738   if ((prefixes & PREFIX_DATA))
10739     {
10740       sizeflag ^= DFLAG;
10741       if (dp->op[2].bytemode == cond_jump_mode
10742           && dp->op[0].bytemode == v_mode
10743           && !intel_syntax)
10744         {
10745           if (sizeflag & DFLAG)
10746             all_prefixes[last_data_prefix] = DATA32_PREFIX;
10747           else
10748             all_prefixes[last_data_prefix] = DATA16_PREFIX;
10749           default_prefixes |= PREFIX_DATA;
10750         }
10751       else if (rex & REX_W)
10752         {
10753           /* REX_W will override PREFIX_DATA.  */
10754           default_prefixes |= PREFIX_DATA;
10755         }
10756     }
10757
10758   if (need_modrm)
10759     {
10760       FETCH_DATA (info, codep + 1);
10761       modrm.mod = (*codep >> 6) & 3;
10762       modrm.reg = (*codep >> 3) & 7;
10763       modrm.rm = *codep & 7;
10764     }
10765
10766    need_vex = 0;
10767    need_vex_reg = 0;
10768    vex_w_done = 0;
10769
10770   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
10771     {
10772       dofloat (sizeflag);
10773     }
10774   else
10775     {
10776       dp = get_valid_dis386 (dp, info);
10777       if (dp != NULL && putop (dp->name, sizeflag) == 0)
10778         {
10779           for (i = 0; i < MAX_OPERANDS; ++i)
10780             {
10781               obufp = op_out[i];
10782               op_ad = MAX_OPERANDS - 1 - i;
10783               if (dp->op[i].rtn)
10784                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
10785             }
10786         }
10787     }
10788
10789   /* See if any prefixes were not used.  If so, print the first one
10790      separately.  If we don't do this, we'll wind up printing an
10791      instruction stream which does not precisely correspond to the
10792      bytes we are disassembling.  */
10793   if ((prefixes & ~(used_prefixes | default_prefixes)) != 0)
10794     {
10795       for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
10796         if (all_prefixes[i])
10797           {
10798             const char *name;
10799             name = prefix_name (all_prefixes[i], priv.orig_sizeflag);
10800             if (name == NULL)
10801               name = INTERNAL_DISASSEMBLER_ERROR;
10802             (*info->fprintf_func) (info->stream, "%s", name);
10803             return 1;
10804           }
10805     }
10806
10807   /* Check if the REX prefix used.  */
10808   if (rex_ignored == 0 && (rex ^ rex_used) == 0)
10809     all_prefixes[last_rex_prefix] = 0;
10810
10811   /* Check if the SEG prefix used.  */
10812   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
10813                    | PREFIX_FS | PREFIX_GS)) != 0
10814       && (used_prefixes
10815           & seg_prefix (all_prefixes[last_seg_prefix])) != 0)
10816     all_prefixes[last_seg_prefix] = 0;
10817
10818   /* Check if the ADDR prefix used.  */
10819   if ((prefixes & PREFIX_ADDR) != 0
10820       && (used_prefixes & PREFIX_ADDR) != 0)
10821     all_prefixes[last_addr_prefix] = 0;
10822
10823   /* Check if the DATA prefix used.  */
10824   if ((prefixes & PREFIX_DATA) != 0
10825       && (used_prefixes & PREFIX_DATA) != 0)
10826     all_prefixes[last_data_prefix] = 0;
10827
10828   prefix_length = 0;
10829   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
10830     if (all_prefixes[i])
10831       {
10832         const char *name;
10833         name = prefix_name (all_prefixes[i], sizeflag);
10834         if (name == NULL)
10835           abort ();
10836         prefix_length += strlen (name) + 1;
10837         (*info->fprintf_func) (info->stream, "%s ", name);
10838       }
10839
10840   /* Check maximum code length.  */
10841   if ((codep - start_codep) > MAX_CODE_LENGTH)
10842     {
10843       (*info->fprintf_func) (info->stream, "(bad)");
10844       return MAX_CODE_LENGTH;
10845     }
10846
10847   obufp = mnemonicendp;
10848   for (i = strlen (obuf) + prefix_length; i < 6; i++)
10849     oappend (" ");
10850   oappend (" ");
10851   (*info->fprintf_func) (info->stream, "%s", obuf);
10852
10853   /* The enter and bound instructions are printed with operands in the same
10854      order as the intel book; everything else is printed in reverse order.  */
10855   if (intel_syntax || two_source_ops)
10856     {
10857       bfd_vma riprel;
10858
10859       for (i = 0; i < MAX_OPERANDS; ++i)
10860         op_txt[i] = op_out[i];
10861
10862       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
10863         {
10864           op_ad = op_index[i];
10865           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
10866           op_index[MAX_OPERANDS - 1 - i] = op_ad;
10867           riprel = op_riprel[i];
10868           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
10869           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
10870         }
10871     }
10872   else
10873     {
10874       for (i = 0; i < MAX_OPERANDS; ++i)
10875         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
10876     }
10877
10878   needcomma = 0;
10879   for (i = 0; i < MAX_OPERANDS; ++i)
10880     if (*op_txt[i])
10881       {
10882         if (needcomma)
10883           (*info->fprintf_func) (info->stream, ",");
10884         if (op_index[i] != -1 && !op_riprel[i])
10885           (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
10886         else
10887           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
10888         needcomma = 1;
10889       }
10890
10891   for (i = 0; i < MAX_OPERANDS; i++)
10892     if (op_index[i] != -1 && op_riprel[i])
10893       {
10894         (*info->fprintf_func) (info->stream, "        # ");
10895         (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep
10896                                                 + op_address[op_index[i]]), info);
10897         break;
10898       }
10899   return codep - priv.the_buffer;
10900 }
10901
10902 static const char *float_mem[] = {
10903   /* d8 */
10904   "fadd{s|}",
10905   "fmul{s|}",
10906   "fcom{s|}",
10907   "fcomp{s|}",
10908   "fsub{s|}",
10909   "fsubr{s|}",
10910   "fdiv{s|}",
10911   "fdivr{s|}",
10912   /* d9 */
10913   "fld{s|}",
10914   "(bad)",
10915   "fst{s|}",
10916   "fstp{s|}",
10917   "fldenvIC",
10918   "fldcw",
10919   "fNstenvIC",
10920   "fNstcw",
10921   /* da */
10922   "fiadd{l|}",
10923   "fimul{l|}",
10924   "ficom{l|}",
10925   "ficomp{l|}",
10926   "fisub{l|}",
10927   "fisubr{l|}",
10928   "fidiv{l|}",
10929   "fidivr{l|}",
10930   /* db */
10931   "fild{l|}",
10932   "fisttp{l|}",
10933   "fist{l|}",
10934   "fistp{l|}",
10935   "(bad)",
10936   "fld{t||t|}",
10937   "(bad)",
10938   "fstp{t||t|}",
10939   /* dc */
10940   "fadd{l|}",
10941   "fmul{l|}",
10942   "fcom{l|}",
10943   "fcomp{l|}",
10944   "fsub{l|}",
10945   "fsubr{l|}",
10946   "fdiv{l|}",
10947   "fdivr{l|}",
10948   /* dd */
10949   "fld{l|}",
10950   "fisttp{ll|}",
10951   "fst{l||}",
10952   "fstp{l|}",
10953   "frstorIC",
10954   "(bad)",
10955   "fNsaveIC",
10956   "fNstsw",
10957   /* de */
10958   "fiadd",
10959   "fimul",
10960   "ficom",
10961   "ficomp",
10962   "fisub",
10963   "fisubr",
10964   "fidiv",
10965   "fidivr",
10966   /* df */
10967   "fild",
10968   "fisttp",
10969   "fist",
10970   "fistp",
10971   "fbld",
10972   "fild{ll|}",
10973   "fbstp",
10974   "fistp{ll|}",
10975 };
10976
10977 static const unsigned char float_mem_mode[] = {
10978   /* d8 */
10979   d_mode,
10980   d_mode,
10981   d_mode,
10982   d_mode,
10983   d_mode,
10984   d_mode,
10985   d_mode,
10986   d_mode,
10987   /* d9 */
10988   d_mode,
10989   0,
10990   d_mode,
10991   d_mode,
10992   0,
10993   w_mode,
10994   0,
10995   w_mode,
10996   /* da */
10997   d_mode,
10998   d_mode,
10999   d_mode,
11000   d_mode,
11001   d_mode,
11002   d_mode,
11003   d_mode,
11004   d_mode,
11005   /* db */
11006   d_mode,
11007   d_mode,
11008   d_mode,
11009   d_mode,
11010   0,
11011   t_mode,
11012   0,
11013   t_mode,
11014   /* dc */
11015   q_mode,
11016   q_mode,
11017   q_mode,
11018   q_mode,
11019   q_mode,
11020   q_mode,
11021   q_mode,
11022   q_mode,
11023   /* dd */
11024   q_mode,
11025   q_mode,
11026   q_mode,
11027   q_mode,
11028   0,
11029   0,
11030   0,
11031   w_mode,
11032   /* de */
11033   w_mode,
11034   w_mode,
11035   w_mode,
11036   w_mode,
11037   w_mode,
11038   w_mode,
11039   w_mode,
11040   w_mode,
11041   /* df */
11042   w_mode,
11043   w_mode,
11044   w_mode,
11045   w_mode,
11046   t_mode,
11047   q_mode,
11048   t_mode,
11049   q_mode
11050 };
11051
11052 #define ST { OP_ST, 0 }
11053 #define STi { OP_STi, 0 }
11054
11055 #define FGRPd9_2 NULL, { { NULL, 0 } }
11056 #define FGRPd9_4 NULL, { { NULL, 1 } }
11057 #define FGRPd9_5 NULL, { { NULL, 2 } }
11058 #define FGRPd9_6 NULL, { { NULL, 3 } }
11059 #define FGRPd9_7 NULL, { { NULL, 4 } }
11060 #define FGRPda_5 NULL, { { NULL, 5 } }
11061 #define FGRPdb_4 NULL, { { NULL, 6 } }
11062 #define FGRPde_3 NULL, { { NULL, 7 } }
11063 #define FGRPdf_4 NULL, { { NULL, 8 } }
11064
11065 static const struct dis386 float_reg[][8] = {
11066   /* d8 */
11067   {
11068     { "fadd",   { ST, STi } },
11069     { "fmul",   { ST, STi } },
11070     { "fcom",   { STi } },
11071     { "fcomp",  { STi } },
11072     { "fsub",   { ST, STi } },
11073     { "fsubr",  { ST, STi } },
11074     { "fdiv",   { ST, STi } },
11075     { "fdivr",  { ST, STi } },
11076   },
11077   /* d9 */
11078   {
11079     { "fld",    { STi } },
11080     { "fxch",   { STi } },
11081     { FGRPd9_2 },
11082     { "(bad)",  { XX } },
11083     { FGRPd9_4 },
11084     { FGRPd9_5 },
11085     { FGRPd9_6 },
11086     { FGRPd9_7 },
11087   },
11088   /* da */
11089   {
11090     { "fcmovb", { ST, STi } },
11091     { "fcmove", { ST, STi } },
11092     { "fcmovbe",{ ST, STi } },
11093     { "fcmovu", { ST, STi } },
11094     { "(bad)",  { XX } },
11095     { FGRPda_5 },
11096     { "(bad)",  { XX } },
11097     { "(bad)",  { XX } },
11098   },
11099   /* db */
11100   {
11101     { "fcmovnb",{ ST, STi } },
11102     { "fcmovne",{ ST, STi } },
11103     { "fcmovnbe",{ ST, STi } },
11104     { "fcmovnu",{ ST, STi } },
11105     { FGRPdb_4 },
11106     { "fucomi", { ST, STi } },
11107     { "fcomi",  { ST, STi } },
11108     { "(bad)",  { XX } },
11109   },
11110   /* dc */
11111   {
11112     { "fadd",   { STi, ST } },
11113     { "fmul",   { STi, ST } },
11114     { "(bad)",  { XX } },
11115     { "(bad)",  { XX } },
11116     { "fsub!M", { STi, ST } },
11117     { "fsubM",  { STi, ST } },
11118     { "fdiv!M", { STi, ST } },
11119     { "fdivM",  { STi, ST } },
11120   },
11121   /* dd */
11122   {
11123     { "ffree",  { STi } },
11124     { "(bad)",  { XX } },
11125     { "fst",    { STi } },
11126     { "fstp",   { STi } },
11127     { "fucom",  { STi } },
11128     { "fucomp", { STi } },
11129     { "(bad)",  { XX } },
11130     { "(bad)",  { XX } },
11131   },
11132   /* de */
11133   {
11134     { "faddp",  { STi, ST } },
11135     { "fmulp",  { STi, ST } },
11136     { "(bad)",  { XX } },
11137     { FGRPde_3 },
11138     { "fsub!Mp", { STi, ST } },
11139     { "fsubMp", { STi, ST } },
11140     { "fdiv!Mp", { STi, ST } },
11141     { "fdivMp", { STi, ST } },
11142   },
11143   /* df */
11144   {
11145     { "ffreep", { STi } },
11146     { "(bad)",  { XX } },
11147     { "(bad)",  { XX } },
11148     { "(bad)",  { XX } },
11149     { FGRPdf_4 },
11150     { "fucomip", { ST, STi } },
11151     { "fcomip", { ST, STi } },
11152     { "(bad)",  { XX } },
11153   },
11154 };
11155
11156 static char *fgrps[][8] = {
11157   /* d9_2  0 */
11158   {
11159     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
11160   },
11161
11162   /* d9_4  1 */
11163   {
11164     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
11165   },
11166
11167   /* d9_5  2 */
11168   {
11169     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
11170   },
11171
11172   /* d9_6  3 */
11173   {
11174     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
11175   },
11176
11177   /* d9_7  4 */
11178   {
11179     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
11180   },
11181
11182   /* da_5  5 */
11183   {
11184     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
11185   },
11186
11187   /* db_4  6 */
11188   {
11189     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
11190     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
11191   },
11192
11193   /* de_3  7 */
11194   {
11195     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
11196   },
11197
11198   /* df_4  8 */
11199   {
11200     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
11201   },
11202 };
11203
11204 static void
11205 swap_operand (void)
11206 {
11207   mnemonicendp[0] = '.';
11208   mnemonicendp[1] = 's';
11209   mnemonicendp += 2;
11210 }
11211
11212 static void
11213 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
11214                int sizeflag ATTRIBUTE_UNUSED)
11215 {
11216   /* Skip mod/rm byte.  */
11217   MODRM_CHECK;
11218   codep++;
11219 }
11220
11221 static void
11222 dofloat (int sizeflag)
11223 {
11224   const struct dis386 *dp;
11225   unsigned char floatop;
11226
11227   floatop = codep[-1];
11228
11229   if (modrm.mod != 3)
11230     {
11231       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
11232
11233       putop (float_mem[fp_indx], sizeflag);
11234       obufp = op_out[0];
11235       op_ad = 2;
11236       OP_E (float_mem_mode[fp_indx], sizeflag);
11237       return;
11238     }
11239   /* Skip mod/rm byte.  */
11240   MODRM_CHECK;
11241   codep++;
11242
11243   dp = &float_reg[floatop - 0xd8][modrm.reg];
11244   if (dp->name == NULL)
11245     {
11246       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
11247
11248       /* Instruction fnstsw is only one with strange arg.  */
11249       if (floatop == 0xdf && codep[-1] == 0xe0)
11250         strcpy (op_out[0], names16[0]);
11251     }
11252   else
11253     {
11254       putop (dp->name, sizeflag);
11255
11256       obufp = op_out[0];
11257       op_ad = 2;
11258       if (dp->op[0].rtn)
11259         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
11260
11261       obufp = op_out[1];
11262       op_ad = 1;
11263       if (dp->op[1].rtn)
11264         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
11265     }
11266 }
11267
11268 static void
11269 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
11270 {
11271   oappend ("%st" + intel_syntax);
11272 }
11273
11274 static void
11275 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
11276 {
11277   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
11278   oappend (scratchbuf + intel_syntax);
11279 }
11280
11281 /* Capital letters in template are macros.  */
11282 static int
11283 putop (const char *in_template, int sizeflag)
11284 {
11285   const char *p;
11286   int alt = 0;
11287   int cond = 1;
11288   unsigned int l = 0, len = 1;
11289   char last[4];
11290
11291 #define SAVE_LAST(c)                    \
11292   if (l < len && l < sizeof (last))     \
11293     last[l++] = c;                      \
11294   else                                  \
11295     abort ();
11296
11297   for (p = in_template; *p; p++)
11298     {
11299       switch (*p)
11300         {
11301         default:
11302           *obufp++ = *p;
11303           break;
11304         case '%':
11305           len++;
11306           break;
11307         case '!':
11308           cond = 0;
11309           break;
11310         case '{':
11311           alt = 0;
11312           if (intel_syntax)
11313             {
11314               while (*++p != '|')
11315                 if (*p == '}' || *p == '\0')
11316                   abort ();
11317             }
11318           /* Fall through.  */
11319         case 'I':
11320           alt = 1;
11321           continue;
11322         case '|':
11323           while (*++p != '}')
11324             {
11325               if (*p == '\0')
11326                 abort ();
11327             }
11328           break;
11329         case '}':
11330           break;
11331         case 'A':
11332           if (intel_syntax)
11333             break;
11334           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
11335             *obufp++ = 'b';
11336           break;
11337         case 'B':
11338           if (l == 0 && len == 1)
11339             {
11340 case_B:
11341               if (intel_syntax)
11342                 break;
11343               if (sizeflag & SUFFIX_ALWAYS)
11344                 *obufp++ = 'b';
11345             }
11346           else
11347             {
11348               if (l != 1
11349                   || len != 2
11350                   || last[0] != 'L')
11351                 {
11352                   SAVE_LAST (*p);
11353                   break;
11354                 }
11355
11356               if (address_mode == mode_64bit
11357                   && !(prefixes & PREFIX_ADDR))
11358                 {
11359                   *obufp++ = 'a';
11360                   *obufp++ = 'b';
11361                   *obufp++ = 's';
11362                 }
11363
11364               goto case_B;
11365             }
11366           break;
11367         case 'C':
11368           if (intel_syntax && !alt)
11369             break;
11370           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
11371             {
11372               if (sizeflag & DFLAG)
11373                 *obufp++ = intel_syntax ? 'd' : 'l';
11374               else
11375                 *obufp++ = intel_syntax ? 'w' : 's';
11376               used_prefixes |= (prefixes & PREFIX_DATA);
11377             }
11378           break;
11379         case 'D':
11380           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
11381             break;
11382           USED_REX (REX_W);
11383           if (modrm.mod == 3)
11384             {
11385               if (rex & REX_W)
11386                 *obufp++ = 'q';
11387               else
11388                 {
11389                   if (sizeflag & DFLAG)
11390                     *obufp++ = intel_syntax ? 'd' : 'l';
11391                   else
11392                     *obufp++ = 'w';
11393                   used_prefixes |= (prefixes & PREFIX_DATA);
11394                 }
11395             }
11396           else
11397             *obufp++ = 'w';
11398           break;
11399         case 'E':               /* For jcxz/jecxz */
11400           if (address_mode == mode_64bit)
11401             {
11402               if (sizeflag & AFLAG)
11403                 *obufp++ = 'r';
11404               else
11405                 *obufp++ = 'e';
11406             }
11407           else
11408             if (sizeflag & AFLAG)
11409               *obufp++ = 'e';
11410           used_prefixes |= (prefixes & PREFIX_ADDR);
11411           break;
11412         case 'F':
11413           if (intel_syntax)
11414             break;
11415           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
11416             {
11417               if (sizeflag & AFLAG)
11418                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
11419               else
11420                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
11421               used_prefixes |= (prefixes & PREFIX_ADDR);
11422             }
11423           break;
11424         case 'G':
11425           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
11426             break;
11427           if ((rex & REX_W) || (sizeflag & DFLAG))
11428             *obufp++ = 'l';
11429           else
11430             *obufp++ = 'w';
11431           if (!(rex & REX_W))
11432             used_prefixes |= (prefixes & PREFIX_DATA);
11433           break;
11434         case 'H':
11435           if (intel_syntax)
11436             break;
11437           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
11438               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
11439             {
11440               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
11441               *obufp++ = ',';
11442               *obufp++ = 'p';
11443               if (prefixes & PREFIX_DS)
11444                 *obufp++ = 't';
11445               else
11446                 *obufp++ = 'n';
11447             }
11448           break;
11449         case 'J':
11450           if (intel_syntax)
11451             break;
11452           *obufp++ = 'l';
11453           break;
11454         case 'K':
11455           USED_REX (REX_W);
11456           if (rex & REX_W)
11457             *obufp++ = 'q';
11458           else
11459             *obufp++ = 'd';
11460           break;
11461         case 'Z':
11462           if (intel_syntax)
11463             break;
11464           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
11465             {
11466               *obufp++ = 'q';
11467               break;
11468             }
11469           /* Fall through.  */
11470           goto case_L;
11471         case 'L':
11472           if (l != 0 || len != 1)
11473             {
11474               SAVE_LAST (*p);
11475               break;
11476             }
11477 case_L:
11478           if (intel_syntax)
11479             break;
11480           if (sizeflag & SUFFIX_ALWAYS)
11481             *obufp++ = 'l';
11482           break;
11483         case 'M':
11484           if (intel_mnemonic != cond)
11485             *obufp++ = 'r';
11486           break;
11487         case 'N':
11488           if ((prefixes & PREFIX_FWAIT) == 0)
11489             *obufp++ = 'n';
11490           else
11491             used_prefixes |= PREFIX_FWAIT;
11492           break;
11493         case 'O':
11494           USED_REX (REX_W);
11495           if (rex & REX_W)
11496             *obufp++ = 'o';
11497           else if (intel_syntax && (sizeflag & DFLAG))
11498             *obufp++ = 'q';
11499           else
11500             *obufp++ = 'd';
11501           if (!(rex & REX_W))
11502             used_prefixes |= (prefixes & PREFIX_DATA);
11503           break;
11504         case 'T':
11505           if (intel_syntax)
11506             break;
11507           if (address_mode == mode_64bit && (sizeflag & DFLAG))
11508             {
11509               *obufp++ = 'q';
11510               break;
11511             }
11512           /* Fall through.  */
11513         case 'P':
11514           if (intel_syntax)
11515             break;
11516           if ((prefixes & PREFIX_DATA)
11517               || (rex & REX_W)
11518               || (sizeflag & SUFFIX_ALWAYS))
11519             {
11520               USED_REX (REX_W);
11521               if (rex & REX_W)
11522                 *obufp++ = 'q';
11523               else
11524                 {
11525                    if (sizeflag & DFLAG)
11526                       *obufp++ = 'l';
11527                    else
11528                      *obufp++ = 'w';
11529                    used_prefixes |= (prefixes & PREFIX_DATA);
11530                 }
11531             }
11532           break;
11533         case 'U':
11534           if (intel_syntax)
11535             break;
11536           if (address_mode == mode_64bit && (sizeflag & DFLAG))
11537             {
11538               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
11539                 *obufp++ = 'q';
11540               break;
11541             }
11542           /* Fall through.  */
11543           goto case_Q;
11544         case 'Q':
11545           if (l == 0 && len == 1)
11546             {
11547 case_Q:
11548               if (intel_syntax && !alt)
11549                 break;
11550               USED_REX (REX_W);
11551               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
11552                 {
11553                   if (rex & REX_W)
11554                     *obufp++ = 'q';
11555                   else
11556                     {
11557                       if (sizeflag & DFLAG)
11558                         *obufp++ = intel_syntax ? 'd' : 'l';
11559                       else
11560                         *obufp++ = 'w';
11561                       used_prefixes |= (prefixes & PREFIX_DATA);
11562                     }
11563                 }
11564             }
11565           else
11566             {
11567               if (l != 1 || len != 2 || last[0] != 'L')
11568                 {
11569                   SAVE_LAST (*p);
11570                   break;
11571                 }
11572               if (intel_syntax
11573                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
11574                 break;
11575               if ((rex & REX_W))
11576                 {
11577                   USED_REX (REX_W);
11578                   *obufp++ = 'q';
11579                 }
11580               else
11581                 *obufp++ = 'l';
11582             }
11583           break;
11584         case 'R':
11585           USED_REX (REX_W);
11586           if (rex & REX_W)
11587             *obufp++ = 'q';
11588           else if (sizeflag & DFLAG)
11589             {
11590               if (intel_syntax)
11591                   *obufp++ = 'd';
11592               else
11593                   *obufp++ = 'l';
11594             }
11595           else
11596             *obufp++ = 'w';
11597           if (intel_syntax && !p[1]
11598               && ((rex & REX_W) || (sizeflag & DFLAG)))
11599             *obufp++ = 'e';
11600           if (!(rex & REX_W))
11601             used_prefixes |= (prefixes & PREFIX_DATA);
11602           break;
11603         case 'V':
11604           if (l == 0 && len == 1)
11605             {
11606               if (intel_syntax)
11607                 break;
11608               if (address_mode == mode_64bit && (sizeflag & DFLAG))
11609                 {
11610                   if (sizeflag & SUFFIX_ALWAYS)
11611                     *obufp++ = 'q';
11612                   break;
11613                 }
11614             }
11615           else
11616             {
11617               if (l != 1
11618                   || len != 2
11619                   || last[0] != 'L')
11620                 {
11621                   SAVE_LAST (*p);
11622                   break;
11623                 }
11624
11625               if (rex & REX_W)
11626                 {
11627                   *obufp++ = 'a';
11628                   *obufp++ = 'b';
11629                   *obufp++ = 's';
11630                 }
11631             }
11632           /* Fall through.  */
11633           goto case_S;
11634         case 'S':
11635           if (l == 0 && len == 1)
11636             {
11637 case_S:
11638               if (intel_syntax)
11639                 break;
11640               if (sizeflag & SUFFIX_ALWAYS)
11641                 {
11642                   if (rex & REX_W)
11643                     *obufp++ = 'q';
11644                   else
11645                     {
11646                       if (sizeflag & DFLAG)
11647                         *obufp++ = 'l';
11648                       else
11649                         *obufp++ = 'w';
11650                       used_prefixes |= (prefixes & PREFIX_DATA);
11651                     }
11652                 }
11653             }
11654           else
11655             {
11656               if (l != 1
11657                   || len != 2
11658                   || last[0] != 'L')
11659                 {
11660                   SAVE_LAST (*p);
11661                   break;
11662                 }
11663
11664               if (address_mode == mode_64bit
11665                   && !(prefixes & PREFIX_ADDR))
11666                 {
11667                   *obufp++ = 'a';
11668                   *obufp++ = 'b';
11669                   *obufp++ = 's';
11670                 }
11671
11672               goto case_S;
11673             }
11674           break;
11675         case 'X':
11676           if (l != 0 || len != 1)
11677             {
11678               SAVE_LAST (*p);
11679               break;
11680             }
11681           if (need_vex && vex.prefix)
11682             {
11683               if (vex.prefix == DATA_PREFIX_OPCODE)
11684                 *obufp++ = 'd';
11685               else
11686                 *obufp++ = 's';
11687             }
11688           else
11689             {
11690               if (prefixes & PREFIX_DATA)
11691                 *obufp++ = 'd';
11692               else
11693                 *obufp++ = 's';
11694               used_prefixes |= (prefixes & PREFIX_DATA);
11695             }
11696           break;
11697         case 'Y':
11698           if (l == 0 && len == 1)
11699             {
11700               if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
11701                 break;
11702               if (rex & REX_W)
11703                 {
11704                   USED_REX (REX_W);
11705                   *obufp++ = 'q';
11706                 }
11707               break;
11708             }
11709           else
11710             {
11711               if (l != 1 || len != 2 || last[0] != 'X')
11712                 {
11713                   SAVE_LAST (*p);
11714                   break;
11715                 }
11716               if (!need_vex)
11717                 abort ();
11718               if (intel_syntax
11719                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
11720                 break;
11721               switch (vex.length)
11722                 {
11723                 case 128:
11724                   *obufp++ = 'x';
11725                   break;
11726                 case 256:
11727                   *obufp++ = 'y';
11728                   break;
11729                 default:
11730                   abort ();
11731                 }
11732             }
11733           break;
11734         case 'W':
11735           if (l == 0 && len == 1)
11736             {
11737               /* operand size flag for cwtl, cbtw */
11738               USED_REX (REX_W);
11739               if (rex & REX_W)
11740                 {
11741                   if (intel_syntax)
11742                     *obufp++ = 'd';
11743                   else
11744                     *obufp++ = 'l';
11745                 }
11746               else if (sizeflag & DFLAG)
11747                 *obufp++ = 'w';
11748               else
11749                 *obufp++ = 'b';
11750               if (!(rex & REX_W))
11751                 used_prefixes |= (prefixes & PREFIX_DATA);
11752             }
11753           else
11754             {
11755               if (l != 1 || len != 2 || last[0] != 'X')
11756                 {
11757                   SAVE_LAST (*p);
11758                   break;
11759                 }
11760               if (!need_vex)
11761                 abort ();
11762               *obufp++ = vex.w ? 'd': 's';
11763             }
11764           break;
11765         }
11766       alt = 0;
11767     }
11768   *obufp = 0;
11769   mnemonicendp = obufp;
11770   return 0;
11771 }
11772
11773 static void
11774 oappend (const char *s)
11775 {
11776   obufp = stpcpy (obufp, s);
11777 }
11778
11779 static void
11780 append_seg (void)
11781 {
11782   if (prefixes & PREFIX_CS)
11783     {
11784       used_prefixes |= PREFIX_CS;
11785       oappend ("%cs:" + intel_syntax);
11786     }
11787   if (prefixes & PREFIX_DS)
11788     {
11789       used_prefixes |= PREFIX_DS;
11790       oappend ("%ds:" + intel_syntax);
11791     }
11792   if (prefixes & PREFIX_SS)
11793     {
11794       used_prefixes |= PREFIX_SS;
11795       oappend ("%ss:" + intel_syntax);
11796     }
11797   if (prefixes & PREFIX_ES)
11798     {
11799       used_prefixes |= PREFIX_ES;
11800       oappend ("%es:" + intel_syntax);
11801     }
11802   if (prefixes & PREFIX_FS)
11803     {
11804       used_prefixes |= PREFIX_FS;
11805       oappend ("%fs:" + intel_syntax);
11806     }
11807   if (prefixes & PREFIX_GS)
11808     {
11809       used_prefixes |= PREFIX_GS;
11810       oappend ("%gs:" + intel_syntax);
11811     }
11812 }
11813
11814 static void
11815 OP_indirE (int bytemode, int sizeflag)
11816 {
11817   if (!intel_syntax)
11818     oappend ("*");
11819   OP_E (bytemode, sizeflag);
11820 }
11821
11822 static void
11823 print_operand_value (char *buf, int hex, bfd_vma disp)
11824 {
11825   if (address_mode == mode_64bit)
11826     {
11827       if (hex)
11828         {
11829           char tmp[30];
11830           int i;
11831           buf[0] = '0';
11832           buf[1] = 'x';
11833           sprintf_vma (tmp, disp);
11834           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
11835           strcpy (buf + 2, tmp + i);
11836         }
11837       else
11838         {
11839           bfd_signed_vma v = disp;
11840           char tmp[30];
11841           int i;
11842           if (v < 0)
11843             {
11844               *(buf++) = '-';
11845               v = -disp;
11846               /* Check for possible overflow on 0x8000000000000000.  */
11847               if (v < 0)
11848                 {
11849                   strcpy (buf, "9223372036854775808");
11850                   return;
11851                 }
11852             }
11853           if (!v)
11854             {
11855               strcpy (buf, "0");
11856               return;
11857             }
11858
11859           i = 0;
11860           tmp[29] = 0;
11861           while (v)
11862             {
11863               tmp[28 - i] = (v % 10) + '0';
11864               v /= 10;
11865               i++;
11866             }
11867           strcpy (buf, tmp + 29 - i);
11868         }
11869     }
11870   else
11871     {
11872       if (hex)
11873         sprintf (buf, "0x%x", (unsigned int) disp);
11874       else
11875         sprintf (buf, "%d", (int) disp);
11876     }
11877 }
11878
11879 /* Put DISP in BUF as signed hex number.  */
11880
11881 static void
11882 print_displacement (char *buf, bfd_vma disp)
11883 {
11884   bfd_signed_vma val = disp;
11885   char tmp[30];
11886   int i, j = 0;
11887
11888   if (val < 0)
11889     {
11890       buf[j++] = '-';
11891       val = -disp;
11892
11893       /* Check for possible overflow.  */
11894       if (val < 0)
11895         {
11896           switch (address_mode)
11897             {
11898             case mode_64bit:
11899               strcpy (buf + j, "0x8000000000000000");
11900               break;
11901             case mode_32bit:
11902               strcpy (buf + j, "0x80000000");
11903               break;
11904             case mode_16bit:
11905               strcpy (buf + j, "0x8000");
11906               break;
11907             }
11908           return;
11909         }
11910     }
11911
11912   buf[j++] = '0';
11913   buf[j++] = 'x';
11914
11915   sprintf_vma (tmp, (bfd_vma) val);
11916   for (i = 0; tmp[i] == '0'; i++)
11917     continue;
11918   if (tmp[i] == '\0')
11919     i--;
11920   strcpy (buf + j, tmp + i);
11921 }
11922
11923 static void
11924 intel_operand_size (int bytemode, int sizeflag)
11925 {
11926   switch (bytemode)
11927     {
11928     case b_mode:
11929     case b_swap_mode:
11930     case dqb_mode:
11931       oappend ("BYTE PTR ");
11932       break;
11933     case w_mode:
11934     case dqw_mode:
11935       oappend ("WORD PTR ");
11936       break;
11937     case stack_v_mode:
11938       if (address_mode == mode_64bit && (sizeflag & DFLAG))
11939         {
11940           oappend ("QWORD PTR ");
11941           break;
11942         }
11943       /* FALLTHRU */
11944     case v_mode:
11945     case v_swap_mode:
11946     case dq_mode:
11947       USED_REX (REX_W);
11948       if (rex & REX_W)
11949         oappend ("QWORD PTR ");
11950       else
11951         {
11952           if ((sizeflag & DFLAG) || bytemode == dq_mode)
11953             oappend ("DWORD PTR ");
11954           else
11955             oappend ("WORD PTR ");
11956           used_prefixes |= (prefixes & PREFIX_DATA);
11957         }
11958       break;
11959     case z_mode:
11960       if ((rex & REX_W) || (sizeflag & DFLAG))
11961         *obufp++ = 'D';
11962       oappend ("WORD PTR ");
11963       if (!(rex & REX_W))
11964         used_prefixes |= (prefixes & PREFIX_DATA);
11965       break;
11966     case a_mode:
11967       if (sizeflag & DFLAG)
11968         oappend ("QWORD PTR ");
11969       else
11970         oappend ("DWORD PTR ");
11971       used_prefixes |= (prefixes & PREFIX_DATA);
11972       break;
11973     case d_mode:
11974     case d_swap_mode:
11975     case dqd_mode:
11976       oappend ("DWORD PTR ");
11977       break;
11978     case q_mode:
11979     case q_swap_mode:
11980       oappend ("QWORD PTR ");
11981       break;
11982     case m_mode:
11983       if (address_mode == mode_64bit)
11984         oappend ("QWORD PTR ");
11985       else
11986         oappend ("DWORD PTR ");
11987       break;
11988     case f_mode:
11989       if (sizeflag & DFLAG)
11990         oappend ("FWORD PTR ");
11991       else
11992         oappend ("DWORD PTR ");
11993       used_prefixes |= (prefixes & PREFIX_DATA);
11994       break;
11995     case t_mode:
11996       oappend ("TBYTE PTR ");
11997       break;
11998     case x_mode:
11999     case x_swap_mode:
12000       if (need_vex)
12001         {
12002           switch (vex.length)
12003             {
12004             case 128:
12005               oappend ("XMMWORD PTR ");
12006               break;
12007             case 256:
12008               oappend ("YMMWORD PTR ");
12009               break;
12010             default:
12011               abort ();
12012             }
12013         }
12014       else
12015         oappend ("XMMWORD PTR ");
12016       break;
12017     case xmm_mode:
12018       oappend ("XMMWORD PTR ");
12019       break;
12020     case xmmq_mode:
12021       if (!need_vex)
12022         abort ();
12023
12024       switch (vex.length)
12025         {
12026         case 128:
12027           oappend ("QWORD PTR ");
12028           break;
12029         case 256:
12030           oappend ("XMMWORD PTR ");
12031           break;
12032         default:
12033           abort ();
12034         }
12035       break;
12036     case ymmq_mode:
12037       if (!need_vex)
12038         abort ();
12039
12040       switch (vex.length)
12041         {
12042         case 128:
12043           oappend ("QWORD PTR ");
12044           break;
12045         case 256:
12046           oappend ("YMMWORD PTR ");
12047           break;
12048         default:
12049           abort ();
12050         }
12051       break;
12052     case o_mode:
12053       oappend ("OWORD PTR ");
12054       break;
12055     case vex_w_dq_mode:
12056       if (!need_vex)
12057         abort ();
12058
12059       if (vex.w)
12060         oappend ("QWORD PTR ");
12061       else
12062         oappend ("DWORD PTR ");
12063       break;
12064     default:
12065       break;
12066     }
12067 }
12068
12069 static void
12070 OP_E_register (int bytemode, int sizeflag)
12071 {
12072   int reg = modrm.rm;
12073   const char **names;
12074
12075   USED_REX (REX_B);
12076   if ((rex & REX_B))
12077     reg += 8;
12078
12079   if ((sizeflag & SUFFIX_ALWAYS)
12080       && (bytemode == b_swap_mode || bytemode == v_swap_mode))
12081     swap_operand ();
12082
12083   switch (bytemode)
12084     {
12085     case b_mode:
12086     case b_swap_mode:
12087       USED_REX (0);
12088       if (rex)
12089         names = names8rex;
12090       else
12091         names = names8;
12092       break;
12093     case w_mode:
12094       names = names16;
12095       break;
12096     case d_mode:
12097       names = names32;
12098       break;
12099     case q_mode:
12100       names = names64;
12101       break;
12102     case m_mode:
12103       names = address_mode == mode_64bit ? names64 : names32;
12104       break;
12105     case stack_v_mode:
12106       if (address_mode == mode_64bit && (sizeflag & DFLAG))
12107         {
12108           names = names64;
12109           break;
12110         }
12111       bytemode = v_mode;
12112       /* FALLTHRU */
12113     case v_mode:
12114     case v_swap_mode:
12115     case dq_mode:
12116     case dqb_mode:
12117     case dqd_mode:
12118     case dqw_mode:
12119       USED_REX (REX_W);
12120       if (rex & REX_W)
12121         names = names64;
12122       else
12123         {
12124           if ((sizeflag & DFLAG)
12125               || (bytemode != v_mode
12126                   && bytemode != v_swap_mode))
12127             names = names32;
12128           else
12129             names = names16;
12130           used_prefixes |= (prefixes & PREFIX_DATA);
12131         }
12132       break;
12133     case 0:
12134       return;
12135     default:
12136       oappend (INTERNAL_DISASSEMBLER_ERROR);
12137       return;
12138     }
12139   oappend (names[reg]);
12140 }
12141
12142 static void
12143 OP_E_memory (int bytemode, int sizeflag)
12144 {
12145   bfd_vma disp = 0;
12146   int add = (rex & REX_B) ? 8 : 0;
12147   int riprel = 0;
12148
12149   USED_REX (REX_B);
12150   if (intel_syntax)
12151     intel_operand_size (bytemode, sizeflag);
12152   append_seg ();
12153
12154   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
12155     {
12156       /* 32/64 bit address mode */
12157       int havedisp;
12158       int havesib;
12159       int havebase;
12160       int haveindex;
12161       int needindex;
12162       int base, rbase;
12163       int vindex = 0;
12164       int scale = 0;
12165
12166       havesib = 0;
12167       havebase = 1;
12168       haveindex = 0;
12169       base = modrm.rm;
12170
12171       if (base == 4)
12172         {
12173           havesib = 1;
12174           FETCH_DATA (the_info, codep + 1);
12175           vindex = (*codep >> 3) & 7;
12176           scale = (*codep >> 6) & 3;
12177           base = *codep & 7;
12178           USED_REX (REX_X);
12179           if (rex & REX_X)
12180             vindex += 8;
12181           haveindex = vindex != 4;
12182           codep++;
12183         }
12184       rbase = base + add;
12185
12186       switch (modrm.mod)
12187         {
12188         case 0:
12189           if (base == 5)
12190             {
12191               havebase = 0;
12192               if (address_mode == mode_64bit && !havesib)
12193                 riprel = 1;
12194               disp = get32s ();
12195             }
12196           break;
12197         case 1:
12198           FETCH_DATA (the_info, codep + 1);
12199           disp = *codep++;
12200           if ((disp & 0x80) != 0)
12201             disp -= 0x100;
12202           break;
12203         case 2:
12204           disp = get32s ();
12205           break;
12206         }
12207
12208       /* In 32bit mode, we need index register to tell [offset] from
12209          [eiz*1 + offset].  */
12210       needindex = (havesib
12211                    && !havebase
12212                    && !haveindex
12213                    && address_mode == mode_32bit);
12214       havedisp = (havebase
12215                   || needindex
12216                   || (havesib && (haveindex || scale != 0)));
12217
12218       if (!intel_syntax)
12219         if (modrm.mod != 0 || base == 5)
12220           {
12221             if (havedisp || riprel)
12222               print_displacement (scratchbuf, disp);
12223             else
12224               print_operand_value (scratchbuf, 1, disp);
12225             oappend (scratchbuf);
12226             if (riprel)
12227               {
12228                 set_op (disp, 1);
12229                 oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)");
12230               }
12231           }
12232
12233       if (havebase || haveindex || riprel)
12234         used_prefixes |= PREFIX_ADDR;
12235
12236       if (havedisp || (intel_syntax && riprel))
12237         {
12238           *obufp++ = open_char;
12239           if (intel_syntax && riprel)
12240             {
12241               set_op (disp, 1);
12242               oappend (sizeflag & AFLAG ? "rip" : "eip");
12243             }
12244           *obufp = '\0';
12245           if (havebase)
12246             oappend (address_mode == mode_64bit && (sizeflag & AFLAG)
12247                      ? names64[rbase] : names32[rbase]);
12248           if (havesib)
12249             {
12250               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
12251                  print index to tell base + index from base.  */
12252               if (scale != 0
12253                   || needindex
12254                   || haveindex
12255                   || (havebase && base != ESP_REG_NUM))
12256                 {
12257                   if (!intel_syntax || havebase)
12258                     {
12259                       *obufp++ = separator_char;
12260                       *obufp = '\0';
12261                     }
12262                   if (haveindex)
12263                     oappend (address_mode == mode_64bit
12264                              && (sizeflag & AFLAG)
12265                              ? names64[vindex] : names32[vindex]);
12266                   else
12267                     oappend (address_mode == mode_64bit
12268                              && (sizeflag & AFLAG)
12269                              ? index64 : index32);
12270
12271                   *obufp++ = scale_char;
12272                   *obufp = '\0';
12273                   sprintf (scratchbuf, "%d", 1 << scale);
12274                   oappend (scratchbuf);
12275                 }
12276             }
12277           if (intel_syntax
12278               && (disp || modrm.mod != 0 || base == 5))
12279             {
12280               if (!havedisp || (bfd_signed_vma) disp >= 0)
12281                 {
12282                   *obufp++ = '+';
12283                   *obufp = '\0';
12284                 }
12285               else if (modrm.mod != 1 && disp != -disp)
12286                 {
12287                   *obufp++ = '-';
12288                   *obufp = '\0';
12289                   disp = - (bfd_signed_vma) disp;
12290                 }
12291
12292               if (havedisp)
12293                 print_displacement (scratchbuf, disp);
12294               else
12295                 print_operand_value (scratchbuf, 1, disp);
12296               oappend (scratchbuf);
12297             }
12298
12299           *obufp++ = close_char;
12300           *obufp = '\0';
12301         }
12302       else if (intel_syntax)
12303         {
12304           if (modrm.mod != 0 || base == 5)
12305             {
12306               if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
12307                               | PREFIX_ES | PREFIX_FS | PREFIX_GS))
12308                 ;
12309               else
12310                 {
12311                   oappend (names_seg[ds_reg - es_reg]);
12312                   oappend (":");
12313                 }
12314               print_operand_value (scratchbuf, 1, disp);
12315               oappend (scratchbuf);
12316             }
12317         }
12318     }
12319   else
12320     {
12321       /* 16 bit address mode */
12322       used_prefixes |= prefixes & PREFIX_ADDR;
12323       switch (modrm.mod)
12324         {
12325         case 0:
12326           if (modrm.rm == 6)
12327             {
12328               disp = get16 ();
12329               if ((disp & 0x8000) != 0)
12330                 disp -= 0x10000;
12331             }
12332           break;
12333         case 1:
12334           FETCH_DATA (the_info, codep + 1);
12335           disp = *codep++;
12336           if ((disp & 0x80) != 0)
12337             disp -= 0x100;
12338           break;
12339         case 2:
12340           disp = get16 ();
12341           if ((disp & 0x8000) != 0)
12342             disp -= 0x10000;
12343           break;
12344         }
12345
12346       if (!intel_syntax)
12347         if (modrm.mod != 0 || modrm.rm == 6)
12348           {
12349             print_displacement (scratchbuf, disp);
12350             oappend (scratchbuf);
12351           }
12352
12353       if (modrm.mod != 0 || modrm.rm != 6)
12354         {
12355           *obufp++ = open_char;
12356           *obufp = '\0';
12357           oappend (index16[modrm.rm]);
12358           if (intel_syntax
12359               && (disp || modrm.mod != 0 || modrm.rm == 6))
12360             {
12361               if ((bfd_signed_vma) disp >= 0)
12362                 {
12363                   *obufp++ = '+';
12364                   *obufp = '\0';
12365                 }
12366               else if (modrm.mod != 1)
12367                 {
12368                   *obufp++ = '-';
12369                   *obufp = '\0';
12370                   disp = - (bfd_signed_vma) disp;
12371                 }
12372
12373               print_displacement (scratchbuf, disp);
12374               oappend (scratchbuf);
12375             }
12376
12377           *obufp++ = close_char;
12378           *obufp = '\0';
12379         }
12380       else if (intel_syntax)
12381         {
12382           if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
12383                           | PREFIX_ES | PREFIX_FS | PREFIX_GS))
12384             ;
12385           else
12386             {
12387               oappend (names_seg[ds_reg - es_reg]);
12388               oappend (":");
12389             }
12390           print_operand_value (scratchbuf, 1, disp & 0xffff);
12391           oappend (scratchbuf);
12392         }
12393     }
12394 }
12395
12396 static void
12397 OP_E (int bytemode, int sizeflag)
12398 {
12399   /* Skip mod/rm byte.  */
12400   MODRM_CHECK;
12401   codep++;
12402
12403   if (modrm.mod == 3)
12404     OP_E_register (bytemode, sizeflag);
12405   else
12406     OP_E_memory (bytemode, sizeflag);
12407 }
12408
12409 static void
12410 OP_G (int bytemode, int sizeflag)
12411 {
12412   int add = 0;
12413   USED_REX (REX_R);
12414   if (rex & REX_R)
12415     add += 8;
12416   switch (bytemode)
12417     {
12418     case b_mode:
12419       USED_REX (0);
12420       if (rex)
12421         oappend (names8rex[modrm.reg + add]);
12422       else
12423         oappend (names8[modrm.reg + add]);
12424       break;
12425     case w_mode:
12426       oappend (names16[modrm.reg + add]);
12427       break;
12428     case d_mode:
12429       oappend (names32[modrm.reg + add]);
12430       break;
12431     case q_mode:
12432       oappend (names64[modrm.reg + add]);
12433       break;
12434     case v_mode:
12435     case dq_mode:
12436     case dqb_mode:
12437     case dqd_mode:
12438     case dqw_mode:
12439       USED_REX (REX_W);
12440       if (rex & REX_W)
12441         oappend (names64[modrm.reg + add]);
12442       else
12443         {
12444           if ((sizeflag & DFLAG) || bytemode != v_mode)
12445             oappend (names32[modrm.reg + add]);
12446           else
12447             oappend (names16[modrm.reg + add]);
12448           used_prefixes |= (prefixes & PREFIX_DATA);
12449         }
12450       break;
12451     case m_mode:
12452       if (address_mode == mode_64bit)
12453         oappend (names64[modrm.reg + add]);
12454       else
12455         oappend (names32[modrm.reg + add]);
12456       break;
12457     default:
12458       oappend (INTERNAL_DISASSEMBLER_ERROR);
12459       break;
12460     }
12461 }
12462
12463 static bfd_vma
12464 get64 (void)
12465 {
12466   bfd_vma x;
12467 #ifdef BFD64
12468   unsigned int a;
12469   unsigned int b;
12470
12471   FETCH_DATA (the_info, codep + 8);
12472   a = *codep++ & 0xff;
12473   a |= (*codep++ & 0xff) << 8;
12474   a |= (*codep++ & 0xff) << 16;
12475   a |= (*codep++ & 0xff) << 24;
12476   b = *codep++ & 0xff;
12477   b |= (*codep++ & 0xff) << 8;
12478   b |= (*codep++ & 0xff) << 16;
12479   b |= (*codep++ & 0xff) << 24;
12480   x = a + ((bfd_vma) b << 32);
12481 #else
12482   abort ();
12483   x = 0;
12484 #endif
12485   return x;
12486 }
12487
12488 static bfd_signed_vma
12489 get32 (void)
12490 {
12491   bfd_signed_vma x = 0;
12492
12493   FETCH_DATA (the_info, codep + 4);
12494   x = *codep++ & (bfd_signed_vma) 0xff;
12495   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
12496   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
12497   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
12498   return x;
12499 }
12500
12501 static bfd_signed_vma
12502 get32s (void)
12503 {
12504   bfd_signed_vma x = 0;
12505
12506   FETCH_DATA (the_info, codep + 4);
12507   x = *codep++ & (bfd_signed_vma) 0xff;
12508   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
12509   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
12510   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
12511
12512   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
12513
12514   return x;
12515 }
12516
12517 static int
12518 get16 (void)
12519 {
12520   int x = 0;
12521
12522   FETCH_DATA (the_info, codep + 2);
12523   x = *codep++ & 0xff;
12524   x |= (*codep++ & 0xff) << 8;
12525   return x;
12526 }
12527
12528 static void
12529 set_op (bfd_vma op, int riprel)
12530 {
12531   op_index[op_ad] = op_ad;
12532   if (address_mode == mode_64bit)
12533     {
12534       op_address[op_ad] = op;
12535       op_riprel[op_ad] = riprel;
12536     }
12537   else
12538     {
12539       /* Mask to get a 32-bit address.  */
12540       op_address[op_ad] = op & 0xffffffff;
12541       op_riprel[op_ad] = riprel & 0xffffffff;
12542     }
12543 }
12544
12545 static void
12546 OP_REG (int code, int sizeflag)
12547 {
12548   const char *s;
12549   int add;
12550   USED_REX (REX_B);
12551   if (rex & REX_B)
12552     add = 8;
12553   else
12554     add = 0;
12555
12556   switch (code)
12557     {
12558     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
12559     case sp_reg: case bp_reg: case si_reg: case di_reg:
12560       s = names16[code - ax_reg + add];
12561       break;
12562     case es_reg: case ss_reg: case cs_reg:
12563     case ds_reg: case fs_reg: case gs_reg:
12564       s = names_seg[code - es_reg + add];
12565       break;
12566     case al_reg: case ah_reg: case cl_reg: case ch_reg:
12567     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
12568       USED_REX (0);
12569       if (rex)
12570         s = names8rex[code - al_reg + add];
12571       else
12572         s = names8[code - al_reg];
12573       break;
12574     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
12575     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
12576       if (address_mode == mode_64bit && (sizeflag & DFLAG))
12577         {
12578           s = names64[code - rAX_reg + add];
12579           break;
12580         }
12581       code += eAX_reg - rAX_reg;
12582       /* Fall through.  */
12583     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
12584     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
12585       USED_REX (REX_W);
12586       if (rex & REX_W)
12587         s = names64[code - eAX_reg + add];
12588       else
12589         {
12590           if (sizeflag & DFLAG)
12591             s = names32[code - eAX_reg + add];
12592           else
12593             s = names16[code - eAX_reg + add];
12594           used_prefixes |= (prefixes & PREFIX_DATA);
12595         }
12596       break;
12597     default:
12598       s = INTERNAL_DISASSEMBLER_ERROR;
12599       break;
12600     }
12601   oappend (s);
12602 }
12603
12604 static void
12605 OP_IMREG (int code, int sizeflag)
12606 {
12607   const char *s;
12608
12609   switch (code)
12610     {
12611     case indir_dx_reg:
12612       if (intel_syntax)
12613         s = "dx";
12614       else
12615         s = "(%dx)";
12616       break;
12617     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
12618     case sp_reg: case bp_reg: case si_reg: case di_reg:
12619       s = names16[code - ax_reg];
12620       break;
12621     case es_reg: case ss_reg: case cs_reg:
12622     case ds_reg: case fs_reg: case gs_reg:
12623       s = names_seg[code - es_reg];
12624       break;
12625     case al_reg: case ah_reg: case cl_reg: case ch_reg:
12626     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
12627       USED_REX (0);
12628       if (rex)
12629         s = names8rex[code - al_reg];
12630       else
12631         s = names8[code - al_reg];
12632       break;
12633     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
12634     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
12635       USED_REX (REX_W);
12636       if (rex & REX_W)
12637         s = names64[code - eAX_reg];
12638       else
12639         {
12640           if (sizeflag & DFLAG)
12641             s = names32[code - eAX_reg];
12642           else
12643             s = names16[code - eAX_reg];
12644           used_prefixes |= (prefixes & PREFIX_DATA);
12645         }
12646       break;
12647     case z_mode_ax_reg:
12648       if ((rex & REX_W) || (sizeflag & DFLAG))
12649         s = *names32;
12650       else
12651         s = *names16;
12652       if (!(rex & REX_W))
12653         used_prefixes |= (prefixes & PREFIX_DATA);
12654       break;
12655     default:
12656       s = INTERNAL_DISASSEMBLER_ERROR;
12657       break;
12658     }
12659   oappend (s);
12660 }
12661
12662 static void
12663 OP_I (int bytemode, int sizeflag)
12664 {
12665   bfd_signed_vma op;
12666   bfd_signed_vma mask = -1;
12667
12668   switch (bytemode)
12669     {
12670     case b_mode:
12671       FETCH_DATA (the_info, codep + 1);
12672       op = *codep++;
12673       mask = 0xff;
12674       break;
12675     case q_mode:
12676       if (address_mode == mode_64bit)
12677         {
12678           op = get32s ();
12679           break;
12680         }
12681       /* Fall through.  */
12682     case v_mode:
12683       USED_REX (REX_W);
12684       if (rex & REX_W)
12685         op = get32s ();
12686       else
12687         {
12688           if (sizeflag & DFLAG)
12689             {
12690               op = get32 ();
12691               mask = 0xffffffff;
12692             }
12693           else
12694             {
12695               op = get16 ();
12696               mask = 0xfffff;
12697             }
12698           used_prefixes |= (prefixes & PREFIX_DATA);
12699         }
12700       break;
12701     case w_mode:
12702       mask = 0xfffff;
12703       op = get16 ();
12704       break;
12705     case const_1_mode:
12706       if (intel_syntax)
12707         oappend ("1");
12708       return;
12709     default:
12710       oappend (INTERNAL_DISASSEMBLER_ERROR);
12711       return;
12712     }
12713
12714   op &= mask;
12715   scratchbuf[0] = '$';
12716   print_operand_value (scratchbuf + 1, 1, op);
12717   oappend (scratchbuf + intel_syntax);
12718   scratchbuf[0] = '\0';
12719 }
12720
12721 static void
12722 OP_I64 (int bytemode, int sizeflag)
12723 {
12724   bfd_signed_vma op;
12725   bfd_signed_vma mask = -1;
12726
12727   if (address_mode != mode_64bit)
12728     {
12729       OP_I (bytemode, sizeflag);
12730       return;
12731     }
12732
12733   switch (bytemode)
12734     {
12735     case b_mode:
12736       FETCH_DATA (the_info, codep + 1);
12737       op = *codep++;
12738       mask = 0xff;
12739       break;
12740     case v_mode:
12741       USED_REX (REX_W);
12742       if (rex & REX_W)
12743         op = get64 ();
12744       else
12745         {
12746           if (sizeflag & DFLAG)
12747             {
12748               op = get32 ();
12749               mask = 0xffffffff;
12750             }
12751           else
12752             {
12753               op = get16 ();
12754               mask = 0xfffff;
12755             }
12756           used_prefixes |= (prefixes & PREFIX_DATA);
12757         }
12758       break;
12759     case w_mode:
12760       mask = 0xfffff;
12761       op = get16 ();
12762       break;
12763     default:
12764       oappend (INTERNAL_DISASSEMBLER_ERROR);
12765       return;
12766     }
12767
12768   op &= mask;
12769   scratchbuf[0] = '$';
12770   print_operand_value (scratchbuf + 1, 1, op);
12771   oappend (scratchbuf + intel_syntax);
12772   scratchbuf[0] = '\0';
12773 }
12774
12775 static void
12776 OP_sI (int bytemode, int sizeflag)
12777 {
12778   bfd_signed_vma op;
12779   bfd_signed_vma mask = -1;
12780
12781   switch (bytemode)
12782     {
12783     case b_mode:
12784       FETCH_DATA (the_info, codep + 1);
12785       op = *codep++;
12786       if ((op & 0x80) != 0)
12787         op -= 0x100;
12788       mask = 0xffffffff;
12789       break;
12790     case v_mode:
12791       USED_REX (REX_W);
12792       if (rex & REX_W)
12793         op = get32s ();
12794       else
12795         {
12796           if (sizeflag & DFLAG)
12797             {
12798               op = get32s ();
12799               mask = 0xffffffff;
12800             }
12801           else
12802             {
12803               mask = 0xffffffff;
12804               op = get16 ();
12805               if ((op & 0x8000) != 0)
12806                 op -= 0x10000;
12807             }
12808           used_prefixes |= (prefixes & PREFIX_DATA);
12809         }
12810       break;
12811     case w_mode:
12812       op = get16 ();
12813       mask = 0xffffffff;
12814       if ((op & 0x8000) != 0)
12815         op -= 0x10000;
12816       break;
12817     default:
12818       oappend (INTERNAL_DISASSEMBLER_ERROR);
12819       return;
12820     }
12821
12822   scratchbuf[0] = '$';
12823   print_operand_value (scratchbuf + 1, 1, op);
12824   oappend (scratchbuf + intel_syntax);
12825 }
12826
12827 static void
12828 OP_J (int bytemode, int sizeflag)
12829 {
12830   bfd_vma disp;
12831   bfd_vma mask = -1;
12832   bfd_vma segment = 0;
12833
12834   switch (bytemode)
12835     {
12836     case b_mode:
12837       FETCH_DATA (the_info, codep + 1);
12838       disp = *codep++;
12839       if ((disp & 0x80) != 0)
12840         disp -= 0x100;
12841       break;
12842     case v_mode:
12843       USED_REX (REX_W);
12844       if ((sizeflag & DFLAG) || (rex & REX_W))
12845         disp = get32s ();
12846       else
12847         {
12848           disp = get16 ();
12849           if ((disp & 0x8000) != 0)
12850             disp -= 0x10000;
12851           /* In 16bit mode, address is wrapped around at 64k within
12852              the same segment.  Otherwise, a data16 prefix on a jump
12853              instruction means that the pc is masked to 16 bits after
12854              the displacement is added!  */
12855           mask = 0xffff;
12856           if ((prefixes & PREFIX_DATA) == 0)
12857             segment = ((start_pc + codep - start_codep)
12858                        & ~((bfd_vma) 0xffff));
12859         }
12860       if (!(rex & REX_W))
12861         used_prefixes |= (prefixes & PREFIX_DATA);
12862       break;
12863     default:
12864       oappend (INTERNAL_DISASSEMBLER_ERROR);
12865       return;
12866     }
12867   disp = ((start_pc + codep - start_codep + disp) & mask) | segment;
12868   set_op (disp, 0);
12869   print_operand_value (scratchbuf, 1, disp);
12870   oappend (scratchbuf);
12871 }
12872
12873 static void
12874 OP_SEG (int bytemode, int sizeflag)
12875 {
12876   if (bytemode == w_mode)
12877     oappend (names_seg[modrm.reg]);
12878   else
12879     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
12880 }
12881
12882 static void
12883 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
12884 {
12885   int seg, offset;
12886
12887   if (sizeflag & DFLAG)
12888     {
12889       offset = get32 ();
12890       seg = get16 ();
12891     }
12892   else
12893     {
12894       offset = get16 ();
12895       seg = get16 ();
12896     }
12897   used_prefixes |= (prefixes & PREFIX_DATA);
12898   if (intel_syntax)
12899     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
12900   else
12901     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
12902   oappend (scratchbuf);
12903 }
12904
12905 static void
12906 OP_OFF (int bytemode, int sizeflag)
12907 {
12908   bfd_vma off;
12909
12910   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12911     intel_operand_size (bytemode, sizeflag);
12912   append_seg ();
12913
12914   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
12915     off = get32 ();
12916   else
12917     off = get16 ();
12918
12919   if (intel_syntax)
12920     {
12921       if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
12922                         | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
12923         {
12924           oappend (names_seg[ds_reg - es_reg]);
12925           oappend (":");
12926         }
12927     }
12928   print_operand_value (scratchbuf, 1, off);
12929   oappend (scratchbuf);
12930 }
12931
12932 static void
12933 OP_OFF64 (int bytemode, int sizeflag)
12934 {
12935   bfd_vma off;
12936
12937   if (address_mode != mode_64bit
12938       || (prefixes & PREFIX_ADDR))
12939     {
12940       OP_OFF (bytemode, sizeflag);
12941       return;
12942     }
12943
12944   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12945     intel_operand_size (bytemode, sizeflag);
12946   append_seg ();
12947
12948   off = get64 ();
12949
12950   if (intel_syntax)
12951     {
12952       if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
12953                         | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
12954         {
12955           oappend (names_seg[ds_reg - es_reg]);
12956           oappend (":");
12957         }
12958     }
12959   print_operand_value (scratchbuf, 1, off);
12960   oappend (scratchbuf);
12961 }
12962
12963 static void
12964 ptr_reg (int code, int sizeflag)
12965 {
12966   const char *s;
12967
12968   *obufp++ = open_char;
12969   used_prefixes |= (prefixes & PREFIX_ADDR);
12970   if (address_mode == mode_64bit)
12971     {
12972       if (!(sizeflag & AFLAG))
12973         s = names32[code - eAX_reg];
12974       else
12975         s = names64[code - eAX_reg];
12976     }
12977   else if (sizeflag & AFLAG)
12978     s = names32[code - eAX_reg];
12979   else
12980     s = names16[code - eAX_reg];
12981   oappend (s);
12982   *obufp++ = close_char;
12983   *obufp = 0;
12984 }
12985
12986 static void
12987 OP_ESreg (int code, int sizeflag)
12988 {
12989   if (intel_syntax)
12990     {
12991       switch (codep[-1])
12992         {
12993         case 0x6d:      /* insw/insl */
12994           intel_operand_size (z_mode, sizeflag);
12995           break;
12996         case 0xa5:      /* movsw/movsl/movsq */
12997         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
12998         case 0xab:      /* stosw/stosl */
12999         case 0xaf:      /* scasw/scasl */
13000           intel_operand_size (v_mode, sizeflag);
13001           break;
13002         default:
13003           intel_operand_size (b_mode, sizeflag);
13004         }
13005     }
13006   oappend ("%es:" + intel_syntax);
13007   ptr_reg (code, sizeflag);
13008 }
13009
13010 static void
13011 OP_DSreg (int code, int sizeflag)
13012 {
13013   if (intel_syntax)
13014     {
13015       switch (codep[-1])
13016         {
13017         case 0x6f:      /* outsw/outsl */
13018           intel_operand_size (z_mode, sizeflag);
13019           break;
13020         case 0xa5:      /* movsw/movsl/movsq */
13021         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
13022         case 0xad:      /* lodsw/lodsl/lodsq */
13023           intel_operand_size (v_mode, sizeflag);
13024           break;
13025         default:
13026           intel_operand_size (b_mode, sizeflag);
13027         }
13028     }
13029   if ((prefixes
13030        & (PREFIX_CS
13031           | PREFIX_DS
13032           | PREFIX_SS
13033           | PREFIX_ES
13034           | PREFIX_FS
13035           | PREFIX_GS)) == 0)
13036     prefixes |= PREFIX_DS;
13037   append_seg ();
13038   ptr_reg (code, sizeflag);
13039 }
13040
13041 static void
13042 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13043 {
13044   int add;
13045   if (rex & REX_R)
13046     {
13047       USED_REX (REX_R);
13048       add = 8;
13049     }
13050   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
13051     {
13052       all_prefixes[last_lock_prefix] = 0;
13053       used_prefixes |= PREFIX_LOCK;
13054       add = 8;
13055     }
13056   else
13057     add = 0;
13058   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
13059   oappend (scratchbuf + intel_syntax);
13060 }
13061
13062 static void
13063 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13064 {
13065   int add;
13066   USED_REX (REX_R);
13067   if (rex & REX_R)
13068     add = 8;
13069   else
13070     add = 0;
13071   if (intel_syntax)
13072     sprintf (scratchbuf, "db%d", modrm.reg + add);
13073   else
13074     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
13075   oappend (scratchbuf);
13076 }
13077
13078 static void
13079 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13080 {
13081   sprintf (scratchbuf, "%%tr%d", modrm.reg);
13082   oappend (scratchbuf + intel_syntax);
13083 }
13084
13085 static void
13086 OP_R (int bytemode, int sizeflag)
13087 {
13088   if (modrm.mod == 3)
13089     OP_E (bytemode, sizeflag);
13090   else
13091     BadOp ();
13092 }
13093
13094 static void
13095 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13096 {
13097   used_prefixes |= (prefixes & PREFIX_DATA);
13098   if (prefixes & PREFIX_DATA)
13099     {
13100       int add;
13101       USED_REX (REX_R);
13102       if (rex & REX_R)
13103         add = 8;
13104       else
13105         add = 0;
13106       sprintf (scratchbuf, "%%xmm%d", modrm.reg + add);
13107     }
13108   else
13109     sprintf (scratchbuf, "%%mm%d", modrm.reg);
13110   oappend (scratchbuf + intel_syntax);
13111 }
13112
13113 static void
13114 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13115 {
13116   int add;
13117   USED_REX (REX_R);
13118   if (rex & REX_R)
13119     add = 8;
13120   else
13121     add = 0;
13122   if (need_vex && bytemode != xmm_mode)
13123     {
13124       switch (vex.length)
13125         {
13126         case 128:
13127           sprintf (scratchbuf, "%%xmm%d", modrm.reg + add);
13128           break;
13129         case 256:
13130           sprintf (scratchbuf, "%%ymm%d", modrm.reg + add);
13131           break;
13132         default:
13133           abort ();
13134         }
13135     }
13136   else
13137     sprintf (scratchbuf, "%%xmm%d", modrm.reg + add);
13138   oappend (scratchbuf + intel_syntax);
13139 }
13140
13141 static void
13142 OP_EM (int bytemode, int sizeflag)
13143 {
13144   if (modrm.mod != 3)
13145     {
13146       if (intel_syntax
13147           && (bytemode == v_mode || bytemode == v_swap_mode))
13148         {
13149           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
13150           used_prefixes |= (prefixes & PREFIX_DATA);
13151         }
13152       OP_E (bytemode, sizeflag);
13153       return;
13154     }
13155
13156   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
13157     swap_operand ();
13158
13159   /* Skip mod/rm byte.  */
13160   MODRM_CHECK;
13161   codep++;
13162   used_prefixes |= (prefixes & PREFIX_DATA);
13163   if (prefixes & PREFIX_DATA)
13164     {
13165       int add;
13166
13167       USED_REX (REX_B);
13168       if (rex & REX_B)
13169         add = 8;
13170       else
13171         add = 0;
13172       sprintf (scratchbuf, "%%xmm%d", modrm.rm + add);
13173     }
13174   else
13175     sprintf (scratchbuf, "%%mm%d", modrm.rm);
13176   oappend (scratchbuf + intel_syntax);
13177 }
13178
13179 /* cvt* are the only instructions in sse2 which have
13180    both SSE and MMX operands and also have 0x66 prefix
13181    in their opcode. 0x66 was originally used to differentiate
13182    between SSE and MMX instruction(operands). So we have to handle the
13183    cvt* separately using OP_EMC and OP_MXC */
13184 static void
13185 OP_EMC (int bytemode, int sizeflag)
13186 {
13187   if (modrm.mod != 3)
13188     {
13189       if (intel_syntax && bytemode == v_mode)
13190         {
13191           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
13192           used_prefixes |= (prefixes & PREFIX_DATA);
13193         }
13194       OP_E (bytemode, sizeflag);
13195       return;
13196     }
13197
13198   /* Skip mod/rm byte.  */
13199   MODRM_CHECK;
13200   codep++;
13201   used_prefixes |= (prefixes & PREFIX_DATA);
13202   sprintf (scratchbuf, "%%mm%d", modrm.rm);
13203   oappend (scratchbuf + intel_syntax);
13204 }
13205
13206 static void
13207 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13208 {
13209   used_prefixes |= (prefixes & PREFIX_DATA);
13210   sprintf (scratchbuf, "%%mm%d", modrm.reg);
13211   oappend (scratchbuf + intel_syntax);
13212 }
13213
13214 static void
13215 OP_EX (int bytemode, int sizeflag)
13216 {
13217   int add;
13218
13219   /* Skip mod/rm byte.  */
13220   MODRM_CHECK;
13221   codep++;
13222
13223   if (modrm.mod != 3)
13224     {
13225       OP_E_memory (bytemode, sizeflag);
13226       return;
13227     }
13228
13229   USED_REX (REX_B);
13230   if (rex & REX_B)
13231     add = 8;
13232   else
13233     add = 0;
13234
13235   if ((sizeflag & SUFFIX_ALWAYS)
13236       && (bytemode == x_swap_mode
13237           || bytemode == d_swap_mode
13238           || bytemode == q_swap_mode))
13239     swap_operand ();
13240
13241   if (need_vex
13242       && bytemode != xmm_mode
13243       && bytemode != xmmq_mode)
13244     {
13245       switch (vex.length)
13246         {
13247         case 128:
13248           sprintf (scratchbuf, "%%xmm%d", modrm.rm + add);
13249           break;
13250         case 256:
13251           sprintf (scratchbuf, "%%ymm%d", modrm.rm + add);
13252           break;
13253         default:
13254           abort ();
13255         }
13256     }
13257   else
13258     sprintf (scratchbuf, "%%xmm%d", modrm.rm + add);
13259   oappend (scratchbuf + intel_syntax);
13260 }
13261
13262 static void
13263 OP_MS (int bytemode, int sizeflag)
13264 {
13265   if (modrm.mod == 3)
13266     OP_EM (bytemode, sizeflag);
13267   else
13268     BadOp ();
13269 }
13270
13271 static void
13272 OP_XS (int bytemode, int sizeflag)
13273 {
13274   if (modrm.mod == 3)
13275     OP_EX (bytemode, sizeflag);
13276   else
13277     BadOp ();
13278 }
13279
13280 static void
13281 OP_M (int bytemode, int sizeflag)
13282 {
13283   if (modrm.mod == 3)
13284     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
13285     BadOp ();
13286   else
13287     OP_E (bytemode, sizeflag);
13288 }
13289
13290 static void
13291 OP_0f07 (int bytemode, int sizeflag)
13292 {
13293   if (modrm.mod != 3 || modrm.rm != 0)
13294     BadOp ();
13295   else
13296     OP_E (bytemode, sizeflag);
13297 }
13298
13299 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
13300    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
13301
13302 static void
13303 NOP_Fixup1 (int bytemode, int sizeflag)
13304 {
13305   if ((prefixes & PREFIX_DATA) != 0
13306       || (rex != 0
13307           && rex != 0x48
13308           && address_mode == mode_64bit))
13309     OP_REG (bytemode, sizeflag);
13310   else
13311     strcpy (obuf, "nop");
13312 }
13313
13314 static void
13315 NOP_Fixup2 (int bytemode, int sizeflag)
13316 {
13317   if ((prefixes & PREFIX_DATA) != 0
13318       || (rex != 0
13319           && rex != 0x48
13320           && address_mode == mode_64bit))
13321     OP_IMREG (bytemode, sizeflag);
13322 }
13323
13324 static const char *const Suffix3DNow[] = {
13325 /* 00 */        NULL,           NULL,           NULL,           NULL,
13326 /* 04 */        NULL,           NULL,           NULL,           NULL,
13327 /* 08 */        NULL,           NULL,           NULL,           NULL,
13328 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
13329 /* 10 */        NULL,           NULL,           NULL,           NULL,
13330 /* 14 */        NULL,           NULL,           NULL,           NULL,
13331 /* 18 */        NULL,           NULL,           NULL,           NULL,
13332 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
13333 /* 20 */        NULL,           NULL,           NULL,           NULL,
13334 /* 24 */        NULL,           NULL,           NULL,           NULL,
13335 /* 28 */        NULL,           NULL,           NULL,           NULL,
13336 /* 2C */        NULL,           NULL,           NULL,           NULL,
13337 /* 30 */        NULL,           NULL,           NULL,           NULL,
13338 /* 34 */        NULL,           NULL,           NULL,           NULL,
13339 /* 38 */        NULL,           NULL,           NULL,           NULL,
13340 /* 3C */        NULL,           NULL,           NULL,           NULL,
13341 /* 40 */        NULL,           NULL,           NULL,           NULL,
13342 /* 44 */        NULL,           NULL,           NULL,           NULL,
13343 /* 48 */        NULL,           NULL,           NULL,           NULL,
13344 /* 4C */        NULL,           NULL,           NULL,           NULL,
13345 /* 50 */        NULL,           NULL,           NULL,           NULL,
13346 /* 54 */        NULL,           NULL,           NULL,           NULL,
13347 /* 58 */        NULL,           NULL,           NULL,           NULL,
13348 /* 5C */        NULL,           NULL,           NULL,           NULL,
13349 /* 60 */        NULL,           NULL,           NULL,           NULL,
13350 /* 64 */        NULL,           NULL,           NULL,           NULL,
13351 /* 68 */        NULL,           NULL,           NULL,           NULL,
13352 /* 6C */        NULL,           NULL,           NULL,           NULL,
13353 /* 70 */        NULL,           NULL,           NULL,           NULL,
13354 /* 74 */        NULL,           NULL,           NULL,           NULL,
13355 /* 78 */        NULL,           NULL,           NULL,           NULL,
13356 /* 7C */        NULL,           NULL,           NULL,           NULL,
13357 /* 80 */        NULL,           NULL,           NULL,           NULL,
13358 /* 84 */        NULL,           NULL,           NULL,           NULL,
13359 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
13360 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
13361 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
13362 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
13363 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
13364 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
13365 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
13366 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
13367 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
13368 /* AC */        NULL,           NULL,           "pfacc",        NULL,
13369 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
13370 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
13371 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
13372 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
13373 /* C0 */        NULL,           NULL,           NULL,           NULL,
13374 /* C4 */        NULL,           NULL,           NULL,           NULL,
13375 /* C8 */        NULL,           NULL,           NULL,           NULL,
13376 /* CC */        NULL,           NULL,           NULL,           NULL,
13377 /* D0 */        NULL,           NULL,           NULL,           NULL,
13378 /* D4 */        NULL,           NULL,           NULL,           NULL,
13379 /* D8 */        NULL,           NULL,           NULL,           NULL,
13380 /* DC */        NULL,           NULL,           NULL,           NULL,
13381 /* E0 */        NULL,           NULL,           NULL,           NULL,
13382 /* E4 */        NULL,           NULL,           NULL,           NULL,
13383 /* E8 */        NULL,           NULL,           NULL,           NULL,
13384 /* EC */        NULL,           NULL,           NULL,           NULL,
13385 /* F0 */        NULL,           NULL,           NULL,           NULL,
13386 /* F4 */        NULL,           NULL,           NULL,           NULL,
13387 /* F8 */        NULL,           NULL,           NULL,           NULL,
13388 /* FC */        NULL,           NULL,           NULL,           NULL,
13389 };
13390
13391 static void
13392 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13393 {
13394   const char *mnemonic;
13395
13396   FETCH_DATA (the_info, codep + 1);
13397   /* AMD 3DNow! instructions are specified by an opcode suffix in the
13398      place where an 8-bit immediate would normally go.  ie. the last
13399      byte of the instruction.  */
13400   obufp = mnemonicendp;
13401   mnemonic = Suffix3DNow[*codep++ & 0xff];
13402   if (mnemonic)
13403     oappend (mnemonic);
13404   else
13405     {
13406       /* Since a variable sized modrm/sib chunk is between the start
13407          of the opcode (0x0f0f) and the opcode suffix, we need to do
13408          all the modrm processing first, and don't know until now that
13409          we have a bad opcode.  This necessitates some cleaning up.  */
13410       op_out[0][0] = '\0';
13411       op_out[1][0] = '\0';
13412       BadOp ();
13413     }
13414   mnemonicendp = obufp;
13415 }
13416
13417 static struct op simd_cmp_op[] =
13418 {
13419   { STRING_COMMA_LEN ("eq") },
13420   { STRING_COMMA_LEN ("lt") },
13421   { STRING_COMMA_LEN ("le") },
13422   { STRING_COMMA_LEN ("unord") },
13423   { STRING_COMMA_LEN ("neq") },
13424   { STRING_COMMA_LEN ("nlt") },
13425   { STRING_COMMA_LEN ("nle") },
13426   { STRING_COMMA_LEN ("ord") }
13427 };
13428
13429 static void
13430 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13431 {
13432   unsigned int cmp_type;
13433
13434   FETCH_DATA (the_info, codep + 1);
13435   cmp_type = *codep++ & 0xff;
13436   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
13437     {
13438       char suffix [3];
13439       char *p = mnemonicendp - 2;
13440       suffix[0] = p[0];
13441       suffix[1] = p[1];
13442       suffix[2] = '\0';
13443       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
13444       mnemonicendp += simd_cmp_op[cmp_type].len;
13445     }
13446   else
13447     {
13448       /* We have a reserved extension byte.  Output it directly.  */
13449       scratchbuf[0] = '$';
13450       print_operand_value (scratchbuf + 1, 1, cmp_type);
13451       oappend (scratchbuf + intel_syntax);
13452       scratchbuf[0] = '\0';
13453     }
13454 }
13455
13456 static void
13457 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
13458           int sizeflag ATTRIBUTE_UNUSED)
13459 {
13460   /* mwait %eax,%ecx  */
13461   if (!intel_syntax)
13462     {
13463       const char **names = (address_mode == mode_64bit
13464                             ? names64 : names32);
13465       strcpy (op_out[0], names[0]);
13466       strcpy (op_out[1], names[1]);
13467       two_source_ops = 1;
13468     }
13469   /* Skip mod/rm byte.  */
13470   MODRM_CHECK;
13471   codep++;
13472 }
13473
13474 static void
13475 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
13476             int sizeflag ATTRIBUTE_UNUSED)
13477 {
13478   /* monitor %eax,%ecx,%edx"  */
13479   if (!intel_syntax)
13480     {
13481       const char **op1_names;
13482       const char **names = (address_mode == mode_64bit
13483                             ? names64 : names32);
13484
13485       if (!(prefixes & PREFIX_ADDR))
13486         op1_names = (address_mode == mode_16bit
13487                      ? names16 : names);
13488       else
13489         {
13490           /* Remove "addr16/addr32".  */
13491           all_prefixes[last_addr_prefix] = 0;
13492           op1_names = (address_mode != mode_32bit
13493                        ? names32 : names16);
13494           used_prefixes |= PREFIX_ADDR;
13495         }
13496       strcpy (op_out[0], op1_names[0]);
13497       strcpy (op_out[1], names[1]);
13498       strcpy (op_out[2], names[2]);
13499       two_source_ops = 1;
13500     }
13501   /* Skip mod/rm byte.  */
13502   MODRM_CHECK;
13503   codep++;
13504 }
13505
13506 static void
13507 BadOp (void)
13508 {
13509   /* Throw away prefixes and 1st. opcode byte.  */
13510   codep = insn_codep + 1;
13511   oappend ("(bad)");
13512 }
13513
13514 static void
13515 REP_Fixup (int bytemode, int sizeflag)
13516 {
13517   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
13518      lods and stos.  */
13519   if (prefixes & PREFIX_REPZ)
13520     all_prefixes[last_repz_prefix] = REP_PREFIX;
13521
13522   switch (bytemode)
13523     {
13524     case al_reg:
13525     case eAX_reg:
13526     case indir_dx_reg:
13527       OP_IMREG (bytemode, sizeflag);
13528       break;
13529     case eDI_reg:
13530       OP_ESreg (bytemode, sizeflag);
13531       break;
13532     case eSI_reg:
13533       OP_DSreg (bytemode, sizeflag);
13534       break;
13535     default:
13536       abort ();
13537       break;
13538     }
13539 }
13540
13541 static void
13542 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
13543 {
13544   USED_REX (REX_W);
13545   if (rex & REX_W)
13546     {
13547       /* Change cmpxchg8b to cmpxchg16b.  */
13548       char *p = mnemonicendp - 2;
13549       mnemonicendp = stpcpy (p, "16b");
13550       bytemode = o_mode;
13551     }
13552   OP_M (bytemode, sizeflag);
13553 }
13554
13555 static void
13556 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
13557 {
13558   if (need_vex)
13559     {
13560       switch (vex.length)
13561         {
13562         case 128:
13563           sprintf (scratchbuf, "%%xmm%d", reg);
13564           break;
13565         case 256:
13566           sprintf (scratchbuf, "%%ymm%d", reg);
13567           break;
13568         default:
13569           abort ();
13570         }
13571     }
13572   else
13573     sprintf (scratchbuf, "%%xmm%d", reg);
13574   oappend (scratchbuf + intel_syntax);
13575 }
13576
13577 static void
13578 CRC32_Fixup (int bytemode, int sizeflag)
13579 {
13580   /* Add proper suffix to "crc32".  */
13581   char *p = mnemonicendp;
13582
13583   switch (bytemode)
13584     {
13585     case b_mode:
13586       if (intel_syntax)
13587         goto skip;
13588
13589       *p++ = 'b';
13590       break;
13591     case v_mode:
13592       if (intel_syntax)
13593         goto skip;
13594
13595       USED_REX (REX_W);
13596       if (rex & REX_W)
13597         *p++ = 'q';
13598       else
13599         {
13600           if (sizeflag & DFLAG)
13601             *p++ = 'l';
13602           else
13603             *p++ = 'w';
13604           used_prefixes |= (prefixes & PREFIX_DATA);
13605         }
13606       break;
13607     default:
13608       oappend (INTERNAL_DISASSEMBLER_ERROR);
13609       break;
13610     }
13611   mnemonicendp = p;
13612   *p = '\0';
13613
13614 skip:
13615   if (modrm.mod == 3)
13616     {
13617       int add;
13618
13619       /* Skip mod/rm byte.  */
13620       MODRM_CHECK;
13621       codep++;
13622
13623       USED_REX (REX_B);
13624       add = (rex & REX_B) ? 8 : 0;
13625       if (bytemode == b_mode)
13626         {
13627           USED_REX (0);
13628           if (rex)
13629             oappend (names8rex[modrm.rm + add]);
13630           else
13631             oappend (names8[modrm.rm + add]);
13632         }
13633       else
13634         {
13635           USED_REX (REX_W);
13636           if (rex & REX_W)
13637             oappend (names64[modrm.rm + add]);
13638           else if ((prefixes & PREFIX_DATA))
13639             oappend (names16[modrm.rm + add]);
13640           else
13641             oappend (names32[modrm.rm + add]);
13642         }
13643     }
13644   else
13645     OP_E (bytemode, sizeflag);
13646 }
13647
13648 static void
13649 FXSAVE_Fixup (int bytemode, int sizeflag)
13650 {
13651   /* Add proper suffix to "fxsave" and "fxrstor".  */
13652   USED_REX (REX_W);
13653   if (rex & REX_W)
13654     {
13655       char *p = mnemonicendp;
13656       *p++ = '6';
13657       *p++ = '4';
13658       *p = '\0';
13659       mnemonicendp = p;
13660     }
13661   OP_M (bytemode, sizeflag);
13662 }
13663
13664 /* Display the destination register operand for instructions with
13665    VEX. */
13666
13667 static void
13668 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13669 {
13670   if (!need_vex)
13671     abort ();
13672
13673   if (!need_vex_reg)
13674     return;
13675
13676   switch (vex.length)
13677     {
13678     case 128:
13679       switch (bytemode)
13680         {
13681         case vex_mode:
13682         case vex128_mode:
13683           break;
13684         default:
13685           abort ();
13686           return;
13687         }
13688
13689       sprintf (scratchbuf, "%%xmm%d", vex.register_specifier);
13690       break;
13691     case 256:
13692       switch (bytemode)
13693         {
13694         case vex_mode:
13695         case vex256_mode:
13696           break;
13697         default:
13698           abort ();
13699           return;
13700         }
13701
13702       sprintf (scratchbuf, "%%ymm%d", vex.register_specifier);
13703       break;
13704     default:
13705       abort ();
13706       break;
13707     }
13708   oappend (scratchbuf + intel_syntax);
13709 }
13710
13711 /* Get the VEX immediate byte without moving codep.  */
13712
13713 static unsigned char
13714 get_vex_imm8 (int sizeflag, int opnum)
13715 {
13716   int bytes_before_imm = 0;
13717
13718   if (modrm.mod != 3)
13719     {
13720       /* There are SIB/displacement bytes.  */
13721       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
13722         {
13723           /* 32/64 bit address mode */
13724           int base = modrm.rm;
13725
13726           /* Check SIB byte.  */
13727           if (base == 4)
13728             {
13729               FETCH_DATA (the_info, codep + 1);
13730               base = *codep & 7;
13731               /* When decoding the third source, don't increase
13732                  bytes_before_imm as this has already been incremented
13733                  by one in OP_E_memory while decoding the second
13734                  source operand.  */
13735               if (opnum == 0)
13736                 bytes_before_imm++;
13737             }
13738
13739           /* Don't increase bytes_before_imm when decoding the third source,
13740              it has already been incremented by OP_E_memory while decoding
13741              the second source operand.  */
13742           if (opnum == 0)
13743             {
13744               switch (modrm.mod)
13745                 {
13746                   case 0:
13747                     /* When modrm.rm == 5 or modrm.rm == 4 and base in
13748                        SIB == 5, there is a 4 byte displacement.  */
13749                     if (base != 5)
13750                       /* No displacement. */
13751                       break;
13752                   case 2:
13753                     /* 4 byte displacement.  */
13754                     bytes_before_imm += 4;
13755                     break;
13756                   case 1:
13757                     /* 1 byte displacement.  */
13758                     bytes_before_imm++;
13759                     break;
13760                 }
13761             }
13762         }
13763       else
13764         {
13765           /* 16 bit address mode */
13766           /* Don't increase bytes_before_imm when decoding the third source,
13767              it has already been incremented by OP_E_memory while decoding
13768              the second source operand.  */
13769           if (opnum == 0)
13770             {
13771               switch (modrm.mod)
13772                 {
13773                 case 0:
13774                   /* When modrm.rm == 6, there is a 2 byte displacement.  */
13775                   if (modrm.rm != 6)
13776                     /* No displacement. */
13777                     break;
13778                 case 2:
13779                   /* 2 byte displacement.  */
13780                   bytes_before_imm += 2;
13781                   break;
13782                 case 1:
13783                   /* 1 byte displacement: when decoding the third source,
13784                      don't increase bytes_before_imm as this has already
13785                      been incremented by one in OP_E_memory while decoding
13786                      the second source operand.  */
13787                   if (opnum == 0)
13788                     bytes_before_imm++;
13789
13790                   break;
13791                 }
13792             }
13793         }
13794     }
13795
13796   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
13797   return codep [bytes_before_imm];
13798 }
13799
13800 static void
13801 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
13802 {
13803   if (reg == -1 && modrm.mod != 3)
13804     {
13805       OP_E_memory (bytemode, sizeflag);
13806       return;
13807     }
13808   else
13809     {
13810       if (reg == -1)
13811         {
13812           reg = modrm.rm;
13813           USED_REX (REX_B);
13814           if (rex & REX_B)
13815             reg += 8;
13816         }
13817       else if (reg > 7 && address_mode != mode_64bit)
13818         BadOp ();
13819     }
13820
13821   switch (vex.length)
13822     {
13823     case 128:
13824       sprintf (scratchbuf, "%%xmm%d", reg);
13825       break;
13826     case 256:
13827       sprintf (scratchbuf, "%%ymm%d", reg);
13828       break;
13829     default:
13830       abort ();
13831     }
13832   oappend (scratchbuf + intel_syntax);
13833 }
13834
13835 static void
13836 OP_Vex_2src (int bytemode, int sizeflag)
13837 {
13838   if (modrm.mod == 3)
13839     {
13840       USED_REX (REX_B);
13841       sprintf (scratchbuf, "%%xmm%d", rex & REX_B ? modrm.rm + 8 : modrm.rm);
13842       oappend (scratchbuf + intel_syntax);
13843     }
13844   else
13845     {
13846       if (intel_syntax
13847           && (bytemode == v_mode || bytemode == v_swap_mode))
13848         {
13849           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
13850           used_prefixes |= (prefixes & PREFIX_DATA);
13851         }
13852       OP_E (bytemode, sizeflag);
13853     }
13854 }
13855
13856 static void
13857 OP_Vex_2src_1 (int bytemode, int sizeflag)
13858 {
13859   if (modrm.mod == 3)
13860     {
13861       /* Skip mod/rm byte.   */
13862       MODRM_CHECK;
13863       codep++;
13864     }
13865
13866   if (vex.w)
13867     {
13868       sprintf (scratchbuf, "%%xmm%d", vex.register_specifier);
13869       oappend (scratchbuf + intel_syntax);
13870     }
13871   else
13872     OP_Vex_2src (bytemode, sizeflag);
13873 }
13874
13875 static void
13876 OP_Vex_2src_2 (int bytemode, int sizeflag)
13877 {
13878   if (vex.w)
13879     OP_Vex_2src (bytemode, sizeflag);
13880   else
13881     {
13882       sprintf (scratchbuf, "%%xmm%d", vex.register_specifier);
13883       oappend (scratchbuf + intel_syntax);
13884     }
13885 }
13886
13887 static void
13888 OP_EX_VexW (int bytemode, int sizeflag)
13889 {
13890   int reg = -1;
13891
13892   if (!vex_w_done)
13893     {
13894       vex_w_done = 1;
13895
13896       /* Skip mod/rm byte.  */
13897       MODRM_CHECK;
13898       codep++;
13899
13900       if (vex.w)
13901         reg = get_vex_imm8 (sizeflag, 0) >> 4;
13902     }
13903   else
13904     {
13905       if (!vex.w)
13906         reg = get_vex_imm8 (sizeflag, 1) >> 4;
13907     }
13908
13909   OP_EX_VexReg (bytemode, sizeflag, reg);
13910 }
13911
13912 static void
13913 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
13914              int sizeflag ATTRIBUTE_UNUSED)
13915 {
13916   /* Skip the immediate byte and check for invalid bits.  */
13917   FETCH_DATA (the_info, codep + 1);
13918   if (*codep++ & 0xf)
13919     BadOp ();
13920 }
13921
13922 static void
13923 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13924 {
13925   int reg;
13926   FETCH_DATA (the_info, codep + 1);
13927   reg = *codep++;
13928
13929   if (bytemode != x_mode)
13930     abort ();
13931
13932   if (reg & 0xf)
13933       BadOp ();
13934
13935   reg >>= 4;
13936   if (reg > 7 && address_mode != mode_64bit)
13937     BadOp ();
13938
13939   switch (vex.length)
13940     {
13941     case 128:
13942       sprintf (scratchbuf, "%%xmm%d", reg);
13943       break;
13944     case 256:
13945       sprintf (scratchbuf, "%%ymm%d", reg);
13946       break;
13947     default:
13948       abort ();
13949     }
13950   oappend (scratchbuf + intel_syntax);
13951 }
13952
13953 static void
13954 OP_XMM_VexW (int bytemode, int sizeflag)
13955 {
13956   /* Turn off the REX.W bit since it is used for swapping operands
13957      now.  */
13958   rex &= ~REX_W;
13959   OP_XMM (bytemode, sizeflag);
13960 }
13961
13962 static void
13963 OP_EX_Vex (int bytemode, int sizeflag)
13964 {
13965   if (modrm.mod != 3)
13966     {
13967       if (vex.register_specifier != 0)
13968         BadOp ();
13969       need_vex_reg = 0;
13970     }
13971   OP_EX (bytemode, sizeflag);
13972 }
13973
13974 static void
13975 OP_XMM_Vex (int bytemode, int sizeflag)
13976 {
13977   if (modrm.mod != 3)
13978     {
13979       if (vex.register_specifier != 0)
13980         BadOp ();
13981       need_vex_reg = 0;
13982     }
13983   OP_XMM (bytemode, sizeflag);
13984 }
13985
13986 static void
13987 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13988 {
13989   switch (vex.length)
13990     {
13991     case 128:
13992       mnemonicendp = stpcpy (obuf, "vzeroupper");
13993       break;
13994     case 256:
13995       mnemonicendp = stpcpy (obuf, "vzeroall");
13996       break;
13997     default:
13998       abort ();
13999     }
14000 }
14001
14002 static struct op vex_cmp_op[] =
14003 {
14004   { STRING_COMMA_LEN ("eq") },
14005   { STRING_COMMA_LEN ("lt") },
14006   { STRING_COMMA_LEN ("le") },
14007   { STRING_COMMA_LEN ("unord") },
14008   { STRING_COMMA_LEN ("neq") },
14009   { STRING_COMMA_LEN ("nlt") },
14010   { STRING_COMMA_LEN ("nle") },
14011   { STRING_COMMA_LEN ("ord") },
14012   { STRING_COMMA_LEN ("eq_uq") },
14013   { STRING_COMMA_LEN ("nge") },
14014   { STRING_COMMA_LEN ("ngt") },
14015   { STRING_COMMA_LEN ("false") },
14016   { STRING_COMMA_LEN ("neq_oq") },
14017   { STRING_COMMA_LEN ("ge") },
14018   { STRING_COMMA_LEN ("gt") },
14019   { STRING_COMMA_LEN ("true") },
14020   { STRING_COMMA_LEN ("eq_os") },
14021   { STRING_COMMA_LEN ("lt_oq") },
14022   { STRING_COMMA_LEN ("le_oq") },
14023   { STRING_COMMA_LEN ("unord_s") },
14024   { STRING_COMMA_LEN ("neq_us") },
14025   { STRING_COMMA_LEN ("nlt_uq") },
14026   { STRING_COMMA_LEN ("nle_uq") },
14027   { STRING_COMMA_LEN ("ord_s") },
14028   { STRING_COMMA_LEN ("eq_us") },
14029   { STRING_COMMA_LEN ("nge_uq") },
14030   { STRING_COMMA_LEN ("ngt_uq") },
14031   { STRING_COMMA_LEN ("false_os") },
14032   { STRING_COMMA_LEN ("neq_os") },
14033   { STRING_COMMA_LEN ("ge_oq") },
14034   { STRING_COMMA_LEN ("gt_oq") },
14035   { STRING_COMMA_LEN ("true_us") },
14036 };
14037
14038 static void
14039 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14040 {
14041   unsigned int cmp_type;
14042
14043   FETCH_DATA (the_info, codep + 1);
14044   cmp_type = *codep++ & 0xff;
14045   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
14046     {
14047       char suffix [3];
14048       char *p = mnemonicendp - 2;
14049       suffix[0] = p[0];
14050       suffix[1] = p[1];
14051       suffix[2] = '\0';
14052       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
14053       mnemonicendp += vex_cmp_op[cmp_type].len;
14054     }
14055   else
14056     {
14057       /* We have a reserved extension byte.  Output it directly.  */
14058       scratchbuf[0] = '$';
14059       print_operand_value (scratchbuf + 1, 1, cmp_type);
14060       oappend (scratchbuf + intel_syntax);
14061       scratchbuf[0] = '\0';
14062     }
14063 }
14064
14065 static const struct op pclmul_op[] =
14066 {
14067   { STRING_COMMA_LEN ("lql") },
14068   { STRING_COMMA_LEN ("hql") },
14069   { STRING_COMMA_LEN ("lqh") },
14070   { STRING_COMMA_LEN ("hqh") }
14071 };
14072
14073 static void
14074 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
14075               int sizeflag ATTRIBUTE_UNUSED)
14076 {
14077   unsigned int pclmul_type;
14078
14079   FETCH_DATA (the_info, codep + 1);
14080   pclmul_type = *codep++ & 0xff;
14081   switch (pclmul_type)
14082     {
14083     case 0x10:
14084       pclmul_type = 2;
14085       break;
14086     case 0x11:
14087       pclmul_type = 3;
14088       break;
14089     default:
14090       break;
14091     }
14092   if (pclmul_type < ARRAY_SIZE (pclmul_op))
14093     {
14094       char suffix [4];
14095       char *p = mnemonicendp - 3;
14096       suffix[0] = p[0];
14097       suffix[1] = p[1];
14098       suffix[2] = p[2];
14099       suffix[3] = '\0';
14100       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
14101       mnemonicendp += pclmul_op[pclmul_type].len;
14102     }
14103   else
14104     {
14105       /* We have a reserved extension byte.  Output it directly.  */
14106       scratchbuf[0] = '$';
14107       print_operand_value (scratchbuf + 1, 1, pclmul_type);
14108       oappend (scratchbuf + intel_syntax);
14109       scratchbuf[0] = '\0';
14110     }
14111 }
14112
14113 static void
14114 MOVBE_Fixup (int bytemode, int sizeflag)
14115 {
14116   /* Add proper suffix to "movbe".  */
14117   char *p = mnemonicendp;
14118
14119   switch (bytemode)
14120     {
14121     case v_mode:
14122       if (intel_syntax)
14123         goto skip;
14124
14125       USED_REX (REX_W);
14126       if (sizeflag & SUFFIX_ALWAYS)
14127         {
14128           if (rex & REX_W)
14129             *p++ = 'q';
14130           else
14131             {
14132               if (sizeflag & DFLAG)
14133                 *p++ = 'l';
14134               else
14135                 *p++ = 'w';
14136               used_prefixes |= (prefixes & PREFIX_DATA);
14137             }
14138         }
14139       break;
14140     default:
14141       oappend (INTERNAL_DISASSEMBLER_ERROR);
14142       break;
14143     }
14144   mnemonicendp = p;
14145   *p = '\0';
14146
14147 skip:
14148   OP_M (bytemode, sizeflag);
14149 }
14150
14151 static void
14152 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14153 {
14154   int reg;
14155   const char **names;
14156
14157   /* Skip mod/rm byte.  */
14158   MODRM_CHECK;
14159   codep++;
14160
14161   if (vex.w)
14162     names = names64;
14163   else if (vex.length == 256)
14164     names = names32;
14165   else
14166     names = names16;
14167
14168   reg = modrm.rm;
14169   USED_REX (REX_B);
14170   if (rex & REX_B)
14171     reg += 8;
14172
14173   oappend (names[reg]);
14174 }
14175
14176 static void
14177 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14178 {
14179   const char **names;
14180
14181   if (vex.w)
14182     names = names64;
14183   else if (vex.length == 256)
14184     names = names32;
14185   else
14186     names = names16;
14187
14188   oappend (names[vex.register_specifier]);
14189 }
14190
14191 static void
14192 OP_LWP_I (int bytemode ATTRIBUTE_UNUSED, int sizeflag)
14193 {
14194   if (vex.w || vex.length == 256)
14195     OP_I (q_mode, sizeflag);
14196   else
14197     OP_I (w_mode, sizeflag);
14198 }
14199