1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002
3 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
29 #include "safe-ctype.h"
38 #include "opcode/mips.h"
42 #define DBG(x) printf x
48 /* Clean up namespace so we can include obj-elf.h too. */
49 static int mips_output_flavor
PARAMS ((void));
50 static int mips_output_flavor () { return OUTPUT_FLAVOR
; }
51 #undef OBJ_PROCESS_STAB
58 #undef obj_frob_file_after_relocs
59 #undef obj_frob_symbol
61 #undef obj_sec_sym_ok_for_reloc
62 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
65 /* Fix any of them that we actually care about. */
67 #define OUTPUT_FLAVOR mips_output_flavor()
74 #ifndef ECOFF_DEBUGGING
75 #define NO_ECOFF_DEBUGGING
76 #define ECOFF_DEBUGGING 0
81 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
82 static char *mips_regmask_frag
;
87 #define PIC_CALL_REG 25
95 #define ILLEGAL_REG (32)
97 /* Allow override of standard little-endian ECOFF format. */
99 #ifndef ECOFF_LITTLE_FORMAT
100 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
103 extern int target_big_endian
;
105 /* The name of the readonly data section. */
106 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
108 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
110 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
112 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
116 /* The ABI to use. */
127 /* MIPS ABI we are using for this output file. */
128 static enum mips_abi_level file_mips_abi
= NO_ABI
;
130 /* This is the set of options which may be modified by the .set
131 pseudo-op. We use a struct so that .set push and .set pop are more
134 struct mips_set_options
136 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
137 if it has not been initialized. Changed by `.set mipsN', and the
138 -mipsN command line option, and the default CPU. */
140 /* Enabled Application Specific Extensions (ASEs). These are set to -1
141 if they have not been initialized. Changed by `.set <asename>', by
142 command line options, and based on the default architecture. */
144 /* Whether we are assembling for the mips16 processor. 0 if we are
145 not, 1 if we are, and -1 if the value has not been initialized.
146 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
147 -nomips16 command line options, and the default CPU. */
149 /* Non-zero if we should not reorder instructions. Changed by `.set
150 reorder' and `.set noreorder'. */
152 /* Non-zero if we should not permit the $at ($1) register to be used
153 in instructions. Changed by `.set at' and `.set noat'. */
155 /* Non-zero if we should warn when a macro instruction expands into
156 more than one machine instruction. Changed by `.set nomacro' and
158 int warn_about_macros
;
159 /* Non-zero if we should not move instructions. Changed by `.set
160 move', `.set volatile', `.set nomove', and `.set novolatile'. */
162 /* Non-zero if we should not optimize branches by moving the target
163 of the branch into the delay slot. Actually, we don't perform
164 this optimization anyhow. Changed by `.set bopt' and `.set
167 /* Non-zero if we should not autoextend mips16 instructions.
168 Changed by `.set autoextend' and `.set noautoextend'. */
170 /* Restrict general purpose registers and floating point registers
171 to 32 bit. This is initially determined when -mgp32 or -mfp32
172 is passed but can changed if the assembler code uses .set mipsN. */
175 /* The ABI currently in use. This is changed by .set mipsN to loosen
176 restrictions and doesn't affect the whole file. */
177 enum mips_abi_level abi
;
180 /* True if -mgp32 was passed. */
181 static int file_mips_gp32
= -1;
183 /* True if -mfp32 was passed. */
184 static int file_mips_fp32
= -1;
186 /* This is the struct we use to hold the current set of options. Note
187 that we must set the isa field to ISA_UNKNOWN and the mips16 field to
188 -1 to indicate that they have not been initialized. */
190 static struct mips_set_options mips_opts
=
192 ISA_UNKNOWN
, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, NO_ABI
195 /* These variables are filled in with the masks of registers used.
196 The object format code reads them and puts them in the appropriate
198 unsigned long mips_gprmask
;
199 unsigned long mips_cprmask
[4];
201 /* MIPS ISA we are using for this output file. */
202 static int file_mips_isa
= ISA_UNKNOWN
;
204 /* True if -mips3d was passed or implied by arguments passed on the
205 command line (e.g., by -march). */
206 static int file_ase_mips3d
;
208 /* The argument of the -mcpu= flag. Historical for code generation. */
209 static int mips_cpu
= CPU_UNKNOWN
;
211 /* The argument of the -march= flag. The architecture we are assembling. */
212 static int mips_arch
= CPU_UNKNOWN
;
214 /* The argument of the -mtune= flag. The architecture for which we
216 static int mips_tune
= CPU_UNKNOWN
;
218 /* Whether we should mark the file EABI64 or EABI32. */
219 static int mips_eabi64
= 0;
221 /* If they asked for mips1 or mips2 and a cpu that is
222 mips3 or greater, then mark the object file 32BITMODE. */
223 static int mips_32bitmode
= 0;
225 /* Some ISA's have delay slots for instructions which read or write
226 from a coprocessor (eg. mips1-mips3); some don't (eg mips4).
227 Return true if instructions marked INSN_LOAD_COPROC_DELAY,
228 INSN_COPROC_MOVE_DELAY, or INSN_WRITE_COND_CODE actually have a
229 delay slot in this ISA. The uses of this macro assume that any
230 ISA that has delay slots for one of these, has them for all. They
231 also assume that ISAs which don't have delays for these insns, don't
232 have delays for the INSN_LOAD_MEMORY_DELAY instructions either. */
233 #define ISA_HAS_COPROC_DELAYS(ISA) ( \
235 || (ISA) == ISA_MIPS2 \
236 || (ISA) == ISA_MIPS3 \
239 /* Return true if ISA supports 64 bit gp register instructions. */
240 #define ISA_HAS_64BIT_REGS(ISA) ( \
242 || (ISA) == ISA_MIPS4 \
243 || (ISA) == ISA_MIPS5 \
244 || (ISA) == ISA_MIPS64 \
247 #define HAVE_32BIT_GPRS \
249 || mips_opts.abi == O32_ABI \
250 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
252 #define HAVE_32BIT_FPRS \
254 || mips_opts.abi == O32_ABI \
255 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
257 #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS)
258 #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS)
260 #define HAVE_NEWABI (mips_opts.abi == N32_ABI || mips_opts.abi == N64_ABI)
262 #define HAVE_64BIT_OBJECTS (mips_opts.abi == N64_ABI)
264 /* We can only have 64bit addresses if the object file format
266 #define HAVE_32BIT_ADDRESSES \
268 || ((bfd_arch_bits_per_address (stdoutput) == 32 \
269 || ! HAVE_64BIT_OBJECTS) \
270 && mips_pic != EMBEDDED_PIC))
272 #define HAVE_64BIT_ADDRESSES (! HAVE_32BIT_ADDRESSES)
274 /* Return true if the given CPU supports the MIPS3D ASE. */
275 #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \
278 /* Whether the processor uses hardware interlocks to protect
279 reads from the HI and LO registers, and thus does not
280 require nops to be inserted. */
282 #define hilo_interlocks (mips_arch == CPU_R4010 \
283 || mips_arch == CPU_SB1 \
286 /* Whether the processor uses hardware interlocks to protect reads
287 from the GPRs, and thus does not require nops to be inserted. */
288 #define gpr_interlocks \
289 (mips_opts.isa != ISA_MIPS1 \
290 || mips_arch == CPU_R3900)
292 /* As with other "interlocks" this is used by hardware that has FP
293 (co-processor) interlocks. */
294 /* Itbl support may require additional care here. */
295 #define cop_interlocks (mips_arch == CPU_R4300 \
296 || mips_arch == CPU_SB1 \
299 /* Is this a mfhi or mflo instruction? */
300 #define MF_HILO_INSN(PINFO) \
301 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
303 /* MIPS PIC level. */
307 /* Do not generate PIC code. */
310 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
311 not sure what it is supposed to do. */
314 /* Generate PIC code as in the SVR4 MIPS ABI. */
317 /* Generate PIC code without using a global offset table: the data
318 segment has a maximum size of 64K, all data references are off
319 the $gp register, and all text references are PC relative. This
320 is used on some embedded systems. */
324 static enum mips_pic_level mips_pic
;
326 /* Warn about all NOPS that the assembler generates. */
327 static int warn_nops
= 0;
329 /* 1 if we should generate 32 bit offsets from the GP register in
330 SVR4_PIC mode. Currently has no meaning in other modes. */
331 static int mips_big_got
;
333 /* 1 if trap instructions should used for overflow rather than break
335 static int mips_trap
;
337 /* 1 if double width floating point constants should not be constructed
338 by assembling two single width halves into two single width floating
339 point registers which just happen to alias the double width destination
340 register. On some architectures this aliasing can be disabled by a bit
341 in the status register, and the setting of this bit cannot be determined
342 automatically at assemble time. */
343 static int mips_disable_float_construction
;
345 /* Non-zero if any .set noreorder directives were used. */
347 static int mips_any_noreorder
;
349 /* Non-zero if nops should be inserted when the register referenced in
350 an mfhi/mflo instruction is read in the next two instructions. */
351 static int mips_7000_hilo_fix
;
353 /* The size of the small data section. */
354 static unsigned int g_switch_value
= 8;
355 /* Whether the -G option was used. */
356 static int g_switch_seen
= 0;
361 /* If we can determine in advance that GP optimization won't be
362 possible, we can skip the relaxation stuff that tries to produce
363 GP-relative references. This makes delay slot optimization work
366 This function can only provide a guess, but it seems to work for
367 gcc output. It needs to guess right for gcc, otherwise gcc
368 will put what it thinks is a GP-relative instruction in a branch
371 I don't know if a fix is needed for the SVR4_PIC mode. I've only
372 fixed it for the non-PIC mode. KR 95/04/07 */
373 static int nopic_need_relax
PARAMS ((symbolS
*, int));
375 /* handle of the OPCODE hash table */
376 static struct hash_control
*op_hash
= NULL
;
378 /* The opcode hash table we use for the mips16. */
379 static struct hash_control
*mips16_op_hash
= NULL
;
381 /* This array holds the chars that always start a comment. If the
382 pre-processor is disabled, these aren't very useful */
383 const char comment_chars
[] = "#";
385 /* This array holds the chars that only start a comment at the beginning of
386 a line. If the line seems to have the form '# 123 filename'
387 .line and .file directives will appear in the pre-processed output */
388 /* Note that input_file.c hand checks for '#' at the beginning of the
389 first line of the input file. This is because the compiler outputs
390 #NO_APP at the beginning of its output. */
391 /* Also note that C style comments are always supported. */
392 const char line_comment_chars
[] = "#";
394 /* This array holds machine specific line separator characters. */
395 const char line_separator_chars
[] = ";";
397 /* Chars that can be used to separate mant from exp in floating point nums */
398 const char EXP_CHARS
[] = "eE";
400 /* Chars that mean this number is a floating point constant */
403 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
405 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
406 changed in read.c . Ideally it shouldn't have to know about it at all,
407 but nothing is ideal around here.
410 static char *insn_error
;
412 static int auto_align
= 1;
414 /* When outputting SVR4 PIC code, the assembler needs to know the
415 offset in the stack frame from which to restore the $gp register.
416 This is set by the .cprestore pseudo-op, and saved in this
418 static offsetT mips_cprestore_offset
= -1;
420 /* Similiar for NewABI PIC code, where $gp is callee-saved. NewABI has some
421 more optimizations, it can use a register value instead of a memory-saved
422 offset and even an other register than $gp as global pointer. */
423 static offsetT mips_cpreturn_offset
= -1;
424 static int mips_cpreturn_register
= -1;
425 static int mips_gp_register
= GP
;
427 /* Whether mips_cprestore_offset has been set in the current function
428 (or whether it has already been warned about, if not). */
429 static int mips_cprestore_valid
= 0;
431 /* This is the register which holds the stack frame, as set by the
432 .frame pseudo-op. This is needed to implement .cprestore. */
433 static int mips_frame_reg
= SP
;
435 /* Whether mips_frame_reg has been set in the current function
436 (or whether it has already been warned about, if not). */
437 static int mips_frame_reg_valid
= 0;
439 /* To output NOP instructions correctly, we need to keep information
440 about the previous two instructions. */
442 /* Whether we are optimizing. The default value of 2 means to remove
443 unneeded NOPs and swap branch instructions when possible. A value
444 of 1 means to not swap branches. A value of 0 means to always
446 static int mips_optimize
= 2;
448 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
449 equivalent to seeing no -g option at all. */
450 static int mips_debug
= 0;
452 /* The previous instruction. */
453 static struct mips_cl_insn prev_insn
;
455 /* The instruction before prev_insn. */
456 static struct mips_cl_insn prev_prev_insn
;
458 /* If we don't want information for prev_insn or prev_prev_insn, we
459 point the insn_mo field at this dummy integer. */
460 static const struct mips_opcode dummy_opcode
= { NULL
, NULL
, 0, 0, 0, 0 };
462 /* Non-zero if prev_insn is valid. */
463 static int prev_insn_valid
;
465 /* The frag for the previous instruction. */
466 static struct frag
*prev_insn_frag
;
468 /* The offset into prev_insn_frag for the previous instruction. */
469 static long prev_insn_where
;
471 /* The reloc type for the previous instruction, if any. */
472 static bfd_reloc_code_real_type prev_insn_reloc_type
[3];
474 /* The reloc for the previous instruction, if any. */
475 static fixS
*prev_insn_fixp
[3];
477 /* Non-zero if the previous instruction was in a delay slot. */
478 static int prev_insn_is_delay_slot
;
480 /* Non-zero if the previous instruction was in a .set noreorder. */
481 static int prev_insn_unreordered
;
483 /* Non-zero if the previous instruction uses an extend opcode (if
485 static int prev_insn_extended
;
487 /* Non-zero if the previous previous instruction was in a .set
489 static int prev_prev_insn_unreordered
;
491 /* If this is set, it points to a frag holding nop instructions which
492 were inserted before the start of a noreorder section. If those
493 nops turn out to be unnecessary, the size of the frag can be
495 static fragS
*prev_nop_frag
;
497 /* The number of nop instructions we created in prev_nop_frag. */
498 static int prev_nop_frag_holds
;
500 /* The number of nop instructions that we know we need in
502 static int prev_nop_frag_required
;
504 /* The number of instructions we've seen since prev_nop_frag. */
505 static int prev_nop_frag_since
;
507 /* For ECOFF and ELF, relocations against symbols are done in two
508 parts, with a HI relocation and a LO relocation. Each relocation
509 has only 16 bits of space to store an addend. This means that in
510 order for the linker to handle carries correctly, it must be able
511 to locate both the HI and the LO relocation. This means that the
512 relocations must appear in order in the relocation table.
514 In order to implement this, we keep track of each unmatched HI
515 relocation. We then sort them so that they immediately precede the
516 corresponding LO relocation. */
521 struct mips_hi_fixup
*next
;
524 /* The section this fixup is in. */
528 /* The list of unmatched HI relocs. */
530 static struct mips_hi_fixup
*mips_hi_fixup_list
;
532 /* Map normal MIPS register numbers to mips16 register numbers. */
534 #define X ILLEGAL_REG
535 static const int mips32_to_16_reg_map
[] =
537 X
, X
, 2, 3, 4, 5, 6, 7,
538 X
, X
, X
, X
, X
, X
, X
, X
,
539 0, 1, X
, X
, X
, X
, X
, X
,
540 X
, X
, X
, X
, X
, X
, X
, X
544 /* Map mips16 register numbers to normal MIPS register numbers. */
546 static const unsigned int mips16_to_32_reg_map
[] =
548 16, 17, 2, 3, 4, 5, 6, 7
551 /* Since the MIPS does not have multiple forms of PC relative
552 instructions, we do not have to do relaxing as is done on other
553 platforms. However, we do have to handle GP relative addressing
554 correctly, which turns out to be a similar problem.
556 Every macro that refers to a symbol can occur in (at least) two
557 forms, one with GP relative addressing and one without. For
558 example, loading a global variable into a register generally uses
559 a macro instruction like this:
561 If i can be addressed off the GP register (this is true if it is in
562 the .sbss or .sdata section, or if it is known to be smaller than
563 the -G argument) this will generate the following instruction:
565 This instruction will use a GPREL reloc. If i can not be addressed
566 off the GP register, the following instruction sequence will be used:
569 In this case the first instruction will have a HI16 reloc, and the
570 second reloc will have a LO16 reloc. Both relocs will be against
573 The issue here is that we may not know whether i is GP addressable
574 until after we see the instruction that uses it. Therefore, we
575 want to be able to choose the final instruction sequence only at
576 the end of the assembly. This is similar to the way other
577 platforms choose the size of a PC relative instruction only at the
580 When generating position independent code we do not use GP
581 addressing in quite the same way, but the issue still arises as
582 external symbols and local symbols must be handled differently.
584 We handle these issues by actually generating both possible
585 instruction sequences. The longer one is put in a frag_var with
586 type rs_machine_dependent. We encode what to do with the frag in
587 the subtype field. We encode (1) the number of existing bytes to
588 replace, (2) the number of new bytes to use, (3) the offset from
589 the start of the existing bytes to the first reloc we must generate
590 (that is, the offset is applied from the start of the existing
591 bytes after they are replaced by the new bytes, if any), (4) the
592 offset from the start of the existing bytes to the second reloc,
593 (5) whether a third reloc is needed (the third reloc is always four
594 bytes after the second reloc), and (6) whether to warn if this
595 variant is used (this is sometimes needed if .set nomacro or .set
596 noat is in effect). All these numbers are reasonably small.
598 Generating two instruction sequences must be handled carefully to
599 ensure that delay slots are handled correctly. Fortunately, there
600 are a limited number of cases. When the second instruction
601 sequence is generated, append_insn is directed to maintain the
602 existing delay slot information, so it continues to apply to any
603 code after the second instruction sequence. This means that the
604 second instruction sequence must not impose any requirements not
605 required by the first instruction sequence.
607 These variant frags are then handled in functions called by the
608 machine independent code. md_estimate_size_before_relax returns
609 the final size of the frag. md_convert_frag sets up the final form
610 of the frag. tc_gen_reloc adjust the first reloc and adds a second
612 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
616 | (((reloc1) + 64) << 9) \
617 | (((reloc2) + 64) << 2) \
618 | ((reloc3) ? (1 << 1) : 0) \
620 #define RELAX_OLD(i) (((i) >> 23) & 0x7f)
621 #define RELAX_NEW(i) (((i) >> 16) & 0x7f)
622 #define RELAX_RELOC1(i) ((valueT) (((i) >> 9) & 0x7f) - 64)
623 #define RELAX_RELOC2(i) ((valueT) (((i) >> 2) & 0x7f) - 64)
624 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
625 #define RELAX_WARN(i) ((i) & 1)
627 /* For mips16 code, we use an entirely different form of relaxation.
628 mips16 supports two versions of most instructions which take
629 immediate values: a small one which takes some small value, and a
630 larger one which takes a 16 bit value. Since branches also follow
631 this pattern, relaxing these values is required.
633 We can assemble both mips16 and normal MIPS code in a single
634 object. Therefore, we need to support this type of relaxation at
635 the same time that we support the relaxation described above. We
636 use the high bit of the subtype field to distinguish these cases.
638 The information we store for this type of relaxation is the
639 argument code found in the opcode file for this relocation, whether
640 the user explicitly requested a small or extended form, and whether
641 the relocation is in a jump or jal delay slot. That tells us the
642 size of the value, and how it should be stored. We also store
643 whether the fragment is considered to be extended or not. We also
644 store whether this is known to be a branch to a different section,
645 whether we have tried to relax this frag yet, and whether we have
646 ever extended a PC relative fragment because of a shift count. */
647 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
650 | ((small) ? 0x100 : 0) \
651 | ((ext) ? 0x200 : 0) \
652 | ((dslot) ? 0x400 : 0) \
653 | ((jal_dslot) ? 0x800 : 0))
654 #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0)
655 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
656 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
657 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
658 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
659 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
660 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
661 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
662 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
663 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
664 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
665 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
667 /* Prototypes for static functions. */
670 #define internalError() \
671 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
673 #define internalError() as_fatal (_("MIPS internal Error"));
676 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
678 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
679 unsigned int reg
, enum mips_regclass
class));
680 static int reg_needs_delay
PARAMS ((unsigned int));
681 static void mips16_mark_labels
PARAMS ((void));
682 static void append_insn
PARAMS ((char *place
,
683 struct mips_cl_insn
* ip
,
685 bfd_reloc_code_real_type
*r
,
687 static void mips_no_prev_insn
PARAMS ((int));
688 static void mips_emit_delays
PARAMS ((boolean
));
690 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
691 const char *name
, const char *fmt
,
694 static void macro_build ();
696 static void mips16_macro_build
PARAMS ((char *, int *, expressionS
*,
697 const char *, const char *,
699 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
700 expressionS
* ep
, int regnum
));
701 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
702 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
704 static void load_register
PARAMS ((int *, int, expressionS
*, int));
705 static void load_address
PARAMS ((int *, int, expressionS
*, int, int *));
706 static void move_register
PARAMS ((int *, int, int));
707 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
708 static void mips16_macro
PARAMS ((struct mips_cl_insn
* ip
));
709 #ifdef LOSING_COMPILER
710 static void macro2
PARAMS ((struct mips_cl_insn
* ip
));
712 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
713 static void mips16_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
714 static void mips16_immed
PARAMS ((char *, unsigned int, int, offsetT
, boolean
,
715 boolean
, boolean
, unsigned long *,
716 boolean
*, unsigned short *));
717 static int my_getPercentOp
PARAMS ((char **, unsigned int *, int *));
718 static int my_getSmallParser
PARAMS ((char **, unsigned int *, int *));
719 static int my_getSmallExpression
PARAMS ((expressionS
*, char *));
720 static void my_getExpression
PARAMS ((expressionS
*, char *));
722 static int support_64bit_objects
PARAMS((void));
724 static symbolS
*get_symbol
PARAMS ((void));
725 static void mips_align
PARAMS ((int to
, int fill
, symbolS
*label
));
726 static void s_align
PARAMS ((int));
727 static void s_change_sec
PARAMS ((int));
728 static void s_cons
PARAMS ((int));
729 static void s_float_cons
PARAMS ((int));
730 static void s_mips_globl
PARAMS ((int));
731 static void s_option
PARAMS ((int));
732 static void s_mipsset
PARAMS ((int));
733 static void s_abicalls
PARAMS ((int));
734 static void s_cpload
PARAMS ((int));
735 static void s_cpsetup
PARAMS ((int));
736 static void s_cplocal
PARAMS ((int));
737 static void s_cprestore
PARAMS ((int));
738 static void s_cpreturn
PARAMS ((int));
739 static void s_gpvalue
PARAMS ((int));
740 static void s_gpword
PARAMS ((int));
741 static void s_cpadd
PARAMS ((int));
742 static void s_insn
PARAMS ((int));
743 static void md_obj_begin
PARAMS ((void));
744 static void md_obj_end
PARAMS ((void));
745 static long get_number
PARAMS ((void));
746 static void s_mips_ent
PARAMS ((int));
747 static void s_mips_end
PARAMS ((int));
748 static void s_mips_frame
PARAMS ((int));
749 static void s_mips_mask
PARAMS ((int));
750 static void s_mips_stab
PARAMS ((int));
751 static void s_mips_weakext
PARAMS ((int));
752 static void s_file
PARAMS ((int));
753 static int mips16_extended_frag
PARAMS ((fragS
*, asection
*, long));
754 static const char *mips_isa_to_str
PARAMS ((int));
755 static const char *mips_cpu_to_str
PARAMS ((int));
756 static int validate_mips_insn
PARAMS ((const struct mips_opcode
*));
757 static void show
PARAMS ((FILE *, char *, int *, int *));
759 static int mips_need_elf_addend_fixup
PARAMS ((fixS
*));
762 /* Return values of my_getSmallExpression(). */
769 /* Direct relocation creation by %percent_op(). */
788 /* Table and functions used to map between CPU/ISA names, and
789 ISA levels, and CPU numbers. */
793 const char *name
; /* CPU or ISA name. */
794 int is_isa
; /* Is this an ISA? (If 0, a CPU.) */
795 int isa
; /* ISA level. */
796 int cpu
; /* CPU number (default CPU if ISA). */
799 static const struct mips_cpu_info
*mips_cpu_info_from_name
PARAMS ((const char *));
800 static const struct mips_cpu_info
*mips_cpu_info_from_isa
PARAMS ((int));
801 static const struct mips_cpu_info
*mips_cpu_info_from_cpu
PARAMS ((int));
805 The following pseudo-ops from the Kane and Heinrich MIPS book
806 should be defined here, but are currently unsupported: .alias,
807 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
809 The following pseudo-ops from the Kane and Heinrich MIPS book are
810 specific to the type of debugging information being generated, and
811 should be defined by the object format: .aent, .begin, .bend,
812 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
815 The following pseudo-ops from the Kane and Heinrich MIPS book are
816 not MIPS CPU specific, but are also not specific to the object file
817 format. This file is probably the best place to define them, but
818 they are not currently supported: .asm0, .endr, .lab, .repeat,
821 static const pseudo_typeS mips_pseudo_table
[] =
823 /* MIPS specific pseudo-ops. */
824 {"option", s_option
, 0},
825 {"set", s_mipsset
, 0},
826 {"rdata", s_change_sec
, 'r'},
827 {"sdata", s_change_sec
, 's'},
828 {"livereg", s_ignore
, 0},
829 {"abicalls", s_abicalls
, 0},
830 {"cpload", s_cpload
, 0},
831 {"cpsetup", s_cpsetup
, 0},
832 {"cplocal", s_cplocal
, 0},
833 {"cprestore", s_cprestore
, 0},
834 {"cpreturn", s_cpreturn
, 0},
835 {"gpvalue", s_gpvalue
, 0},
836 {"gpword", s_gpword
, 0},
837 {"cpadd", s_cpadd
, 0},
840 /* Relatively generic pseudo-ops that happen to be used on MIPS
842 {"asciiz", stringer
, 1},
843 {"bss", s_change_sec
, 'b'},
846 {"dword", s_cons
, 3},
847 {"weakext", s_mips_weakext
, 0},
849 /* These pseudo-ops are defined in read.c, but must be overridden
850 here for one reason or another. */
851 {"align", s_align
, 0},
853 {"data", s_change_sec
, 'd'},
854 {"double", s_float_cons
, 'd'},
855 {"float", s_float_cons
, 'f'},
856 {"globl", s_mips_globl
, 0},
857 {"global", s_mips_globl
, 0},
858 {"hword", s_cons
, 1},
863 {"short", s_cons
, 1},
864 {"single", s_float_cons
, 'f'},
865 {"stabn", s_mips_stab
, 'n'},
866 {"text", s_change_sec
, 't'},
869 #ifdef MIPS_STABS_ELF
870 { "extern", ecoff_directive_extern
, 0},
876 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
878 /* These pseudo-ops should be defined by the object file format.
879 However, a.out doesn't support them, so we have versions here. */
880 {"aent", s_mips_ent
, 1},
881 {"bgnb", s_ignore
, 0},
882 {"end", s_mips_end
, 0},
883 {"endb", s_ignore
, 0},
884 {"ent", s_mips_ent
, 0},
886 {"fmask", s_mips_mask
, 'F'},
887 {"frame", s_mips_frame
, 0},
888 {"loc", s_ignore
, 0},
889 {"mask", s_mips_mask
, 'R'},
890 {"verstamp", s_ignore
, 0},
894 extern void pop_insert
PARAMS ((const pseudo_typeS
*));
899 pop_insert (mips_pseudo_table
);
900 if (! ECOFF_DEBUGGING
)
901 pop_insert (mips_nonecoff_pseudo_table
);
904 /* Symbols labelling the current insn. */
906 struct insn_label_list
908 struct insn_label_list
*next
;
912 static struct insn_label_list
*insn_labels
;
913 static struct insn_label_list
*free_insn_labels
;
915 static void mips_clear_insn_labels
PARAMS ((void));
918 mips_clear_insn_labels ()
920 register struct insn_label_list
**pl
;
922 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
928 static char *expr_end
;
930 /* Expressions which appear in instructions. These are set by
933 static expressionS imm_expr
;
934 static expressionS offset_expr
;
936 /* Relocs associated with imm_expr and offset_expr. */
938 static bfd_reloc_code_real_type imm_reloc
[3]
939 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
940 static bfd_reloc_code_real_type offset_reloc
[3]
941 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
943 /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */
945 static boolean imm_unmatched_hi
;
947 /* These are set by mips16_ip if an explicit extension is used. */
949 static boolean mips16_small
, mips16_ext
;
951 #ifdef MIPS_STABS_ELF
952 /* The pdr segment for per procedure frame/regmask info */
958 mips_isa_to_str (isa
)
961 const struct mips_cpu_info
*ci
;
964 ci
= mips_cpu_info_from_isa (isa
);
968 sprintf (s
, "ISA#%d", isa
);
973 mips_cpu_to_str (cpu
)
976 const struct mips_cpu_info
*ci
;
979 ci
= mips_cpu_info_from_cpu (cpu
);
983 sprintf (s
, "CPU#%d", cpu
);
987 /* The default target format to use. */
990 mips_target_format ()
992 switch (OUTPUT_FLAVOR
)
994 case bfd_target_aout_flavour
:
995 return target_big_endian
? "a.out-mips-big" : "a.out-mips-little";
996 case bfd_target_ecoff_flavour
:
997 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
998 case bfd_target_coff_flavour
:
1000 case bfd_target_elf_flavour
:
1002 /* This is traditional mips */
1003 return (target_big_endian
1004 ? (HAVE_64BIT_OBJECTS
? "elf64-tradbigmips"
1005 : "elf32-tradbigmips")
1006 : (HAVE_64BIT_OBJECTS
? "elf64-tradlittlemips"
1007 : "elf32-tradlittlemips"));
1009 return (target_big_endian
1010 ? (HAVE_64BIT_OBJECTS
? "elf64-bigmips" : "elf32-bigmips")
1011 : (HAVE_64BIT_OBJECTS
? "elf64-littlemips"
1012 : "elf32-littlemips"));
1020 /* This function is called once, at assembler startup time. It should
1021 set up all the tables, etc. that the MD part of the assembler will need. */
1026 register const char *retval
= NULL
;
1031 int mips_isa_from_cpu
;
1032 int target_cpu_had_mips16
= 0;
1033 const struct mips_cpu_info
*ci
;
1035 /* GP relative stuff not working for PE */
1036 if (strncmp (TARGET_OS
, "pe", 2) == 0
1037 && g_switch_value
!= 0)
1040 as_bad (_("-G not supported in this configuration."));
1045 if (strcmp (cpu
+ (sizeof TARGET_CPU
) - 3, "el") == 0)
1047 a
= xmalloc (sizeof TARGET_CPU
);
1048 strcpy (a
, TARGET_CPU
);
1049 a
[(sizeof TARGET_CPU
) - 3] = '\0';
1053 if (strncmp (cpu
, "mips16", sizeof "mips16" - 1) == 0)
1055 target_cpu_had_mips16
= 1;
1056 cpu
+= sizeof "mips16" - 1;
1059 if (mips_opts
.mips16
< 0)
1060 mips_opts
.mips16
= target_cpu_had_mips16
;
1062 /* Backward compatibility for historic -mcpu= option. Check for
1063 incompatible options, warn if -mcpu is used. */
1064 if (mips_cpu
!= CPU_UNKNOWN
1065 && mips_arch
!= CPU_UNKNOWN
1066 && mips_cpu
!= mips_arch
)
1068 as_fatal (_("The -mcpu option can't be used together with -march. "
1069 "Use -mtune instead of -mcpu."));
1072 if (mips_cpu
!= CPU_UNKNOWN
1073 && mips_tune
!= CPU_UNKNOWN
1074 && mips_cpu
!= mips_tune
)
1076 as_fatal (_("The -mcpu option can't be used together with -mtune. "
1077 "Use -march instead of -mcpu."));
1081 /* For backward compatibility, let -mipsN set various defaults. */
1082 /* This code should go away, to be replaced with something rather more
1083 draconian. Until GCC 3.1 has been released for some reasonable
1084 amount of time, however, we need to support this. */
1085 if (mips_opts
.isa
!= ISA_UNKNOWN
)
1087 /* Translate -mipsN to the appropriate settings of file_mips_gp32
1088 and file_mips_fp32. Tag binaries as using the mipsN ISA. */
1089 if (file_mips_gp32
< 0)
1091 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
1096 if (file_mips_fp32
< 0)
1098 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
1104 ci
= mips_cpu_info_from_isa (mips_opts
.isa
);
1105 assert (ci
!= NULL
);
1106 /* -mipsN has higher priority than -mcpu but lower than -march. */
1107 if (mips_arch
== CPU_UNKNOWN
)
1108 mips_arch
= ci
->cpu
;
1110 /* Default mips_abi. */
1111 if (mips_opts
.abi
== NO_ABI
)
1113 if (mips_opts
.isa
== ISA_MIPS1
|| mips_opts
.isa
== ISA_MIPS2
)
1114 mips_opts
.abi
= O32_ABI
;
1115 else if (mips_opts
.isa
== ISA_MIPS3
|| mips_opts
.isa
== ISA_MIPS4
)
1116 mips_opts
.abi
= O64_ABI
;
1120 if (mips_arch
== CPU_UNKNOWN
&& mips_cpu
!= CPU_UNKNOWN
)
1122 ci
= mips_cpu_info_from_cpu (mips_cpu
);
1123 assert (ci
!= NULL
);
1124 mips_arch
= ci
->cpu
;
1125 as_warn (_("The -mcpu option is deprecated. Please use -march and "
1126 "-mtune instead."));
1129 /* Set tune from -mcpu, not from -mipsN. */
1130 if (mips_tune
== CPU_UNKNOWN
&& mips_cpu
!= CPU_UNKNOWN
)
1132 ci
= mips_cpu_info_from_cpu (mips_cpu
);
1133 assert (ci
!= NULL
);
1134 mips_tune
= ci
->cpu
;
1137 /* At this point, mips_arch will either be CPU_UNKNOWN if no ARCH was
1138 specified on the command line, or some other value if one was.
1139 Similarly, mips_opts.isa will be ISA_UNKNOWN if not specified on
1140 the command line, or will be set otherwise if one was. */
1142 if (mips_arch
!= CPU_UNKNOWN
&& mips_opts
.isa
!= ISA_UNKNOWN
)
1143 /* Handled above. */;
1145 if (mips_arch
== CPU_UNKNOWN
&& mips_cpu
!= CPU_UNKNOWN
)
1147 ci
= mips_cpu_info_from_cpu (mips_cpu
);
1148 assert (ci
!= NULL
);
1149 mips_arch
= ci
->cpu
;
1150 as_warn (_("The -mcpu option is deprecated. Please use -march and "
1151 "-mtune instead."));
1154 /* At this point, mips_arch will either be CPU_UNKNOWN if no ARCH was
1155 specified on the command line, or some other value if one was.
1156 Similarly, mips_opts.isa will be ISA_UNKNOWN if not specified on
1157 the command line, or will be set otherwise if one was. */
1159 if (mips_arch
!= CPU_UNKNOWN
&& mips_opts
.isa
!= ISA_UNKNOWN
)
1161 /* We have to check if the isa is the default isa of arch. Otherwise
1162 we'll get invalid object file headers. */
1163 ci
= mips_cpu_info_from_cpu (mips_arch
);
1164 assert (ci
!= NULL
);
1165 if (mips_opts
.isa
!= ci
->isa
)
1167 /* This really should be an error instead of a warning, but old
1168 compilers only have -mcpu which sets both arch and tune. For
1169 now, we discard arch and preserve tune. */
1170 as_warn (_("The -march option is incompatible to -mipsN and "
1171 "therefore ignored."));
1172 if (mips_tune
== CPU_UNKNOWN
)
1173 mips_tune
= mips_arch
;
1174 ci
= mips_cpu_info_from_isa (mips_opts
.isa
);
1175 assert (ci
!= NULL
);
1176 mips_arch
= ci
->cpu
;
1180 else if (mips_arch
!= CPU_UNKNOWN
&& mips_opts
.isa
== ISA_UNKNOWN
)
1182 /* We have ARCH, we need ISA. */
1183 ci
= mips_cpu_info_from_cpu (mips_arch
);
1184 assert (ci
!= NULL
);
1185 mips_opts
.isa
= ci
->isa
;
1187 else if (mips_arch
== CPU_UNKNOWN
&& mips_opts
.isa
!= ISA_UNKNOWN
)
1189 /* We have ISA, we need default ARCH. */
1190 ci
= mips_cpu_info_from_isa (mips_opts
.isa
);
1191 assert (ci
!= NULL
);
1192 mips_arch
= ci
->cpu
;
1196 /* We need to set both ISA and ARCH from target cpu. */
1197 ci
= mips_cpu_info_from_name (cpu
);
1199 ci
= mips_cpu_info_from_cpu (CPU_R3000
);
1200 assert (ci
!= NULL
);
1201 mips_opts
.isa
= ci
->isa
;
1202 mips_arch
= ci
->cpu
;
1205 if (mips_tune
== CPU_UNKNOWN
)
1206 mips_tune
= mips_arch
;
1208 ci
= mips_cpu_info_from_cpu (mips_arch
);
1209 assert (ci
!= NULL
);
1210 mips_isa_from_cpu
= ci
->isa
;
1212 /* End of TARGET_CPU processing, get rid of malloced memory
1221 if (mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
1222 as_bad (_("trap exception not supported at ISA 1"));
1224 /* Set the EABI kind based on the ISA before the user gets
1225 to change the ISA with directives. This isn't really
1226 the best, but then neither is basing the abi on the isa. */
1227 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
)
1228 && mips_opts
.abi
== EABI_ABI
)
1231 /* If they asked for mips1 or mips2 and a cpu that is
1232 mips3 or greater, then mark the object file 32BITMODE. */
1233 if (mips_isa_from_cpu
!= ISA_UNKNOWN
1234 && ! ISA_HAS_64BIT_REGS (mips_opts
.isa
)
1235 && ISA_HAS_64BIT_REGS (mips_isa_from_cpu
))
1238 /* If the selected architecture includes support for ASEs, enable
1239 generation of code for them. */
1240 if (mips_opts
.ase_mips3d
== -1 && CPU_HAS_MIPS3D (mips_arch
))
1241 mips_opts
.ase_mips3d
= 1;
1243 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, mips_arch
))
1244 as_warn (_("Could not set architecture and machine"));
1246 if (file_mips_gp32
< 0)
1248 if (file_mips_fp32
< 0)
1251 file_mips_isa
= mips_opts
.isa
;
1252 file_mips_abi
= mips_opts
.abi
;
1253 file_ase_mips3d
= mips_opts
.ase_mips3d
;
1254 mips_opts
.gp32
= file_mips_gp32
;
1255 mips_opts
.fp32
= file_mips_fp32
;
1257 op_hash
= hash_new ();
1259 for (i
= 0; i
< NUMOPCODES
;)
1261 const char *name
= mips_opcodes
[i
].name
;
1263 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
1266 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
1267 mips_opcodes
[i
].name
, retval
);
1268 /* Probably a memory allocation problem? Give up now. */
1269 as_fatal (_("Broken assembler. No assembly attempted."));
1273 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
1275 if (!validate_mips_insn (&mips_opcodes
[i
]))
1280 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
1283 mips16_op_hash
= hash_new ();
1286 while (i
< bfd_mips16_num_opcodes
)
1288 const char *name
= mips16_opcodes
[i
].name
;
1290 retval
= hash_insert (mips16_op_hash
, name
, (PTR
) &mips16_opcodes
[i
]);
1292 as_fatal (_("internal: can't hash `%s': %s"),
1293 mips16_opcodes
[i
].name
, retval
);
1296 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
1297 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
1298 != mips16_opcodes
[i
].match
))
1300 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
1301 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
1306 while (i
< bfd_mips16_num_opcodes
1307 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
1311 as_fatal (_("Broken assembler. No assembly attempted."));
1313 /* We add all the general register names to the symbol table. This
1314 helps us detect invalid uses of them. */
1315 for (i
= 0; i
< 32; i
++)
1319 sprintf (buf
, "$%d", i
);
1320 symbol_table_insert (symbol_new (buf
, reg_section
, i
,
1321 &zero_address_frag
));
1323 symbol_table_insert (symbol_new ("$fp", reg_section
, FP
,
1324 &zero_address_frag
));
1325 symbol_table_insert (symbol_new ("$sp", reg_section
, SP
,
1326 &zero_address_frag
));
1327 symbol_table_insert (symbol_new ("$gp", reg_section
, GP
,
1328 &zero_address_frag
));
1329 symbol_table_insert (symbol_new ("$at", reg_section
, AT
,
1330 &zero_address_frag
));
1331 symbol_table_insert (symbol_new ("$kt0", reg_section
, KT0
,
1332 &zero_address_frag
));
1333 symbol_table_insert (symbol_new ("$kt1", reg_section
, KT1
,
1334 &zero_address_frag
));
1335 symbol_table_insert (symbol_new ("$pc", reg_section
, -1,
1336 &zero_address_frag
));
1338 mips_no_prev_insn (false);
1341 mips_cprmask
[0] = 0;
1342 mips_cprmask
[1] = 0;
1343 mips_cprmask
[2] = 0;
1344 mips_cprmask
[3] = 0;
1346 /* set the default alignment for the text section (2**2) */
1347 record_alignment (text_section
, 2);
1349 if (USE_GLOBAL_POINTER_OPT
)
1350 bfd_set_gp_size (stdoutput
, g_switch_value
);
1352 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1354 /* On a native system, sections must be aligned to 16 byte
1355 boundaries. When configured for an embedded ELF target, we
1357 if (strcmp (TARGET_OS
, "elf") != 0)
1359 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
1360 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
1361 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
1364 /* Create a .reginfo section for register masks and a .mdebug
1365 section for debugging information. */
1373 subseg
= now_subseg
;
1375 /* The ABI says this section should be loaded so that the
1376 running program can access it. However, we don't load it
1377 if we are configured for an embedded target */
1378 flags
= SEC_READONLY
| SEC_DATA
;
1379 if (strcmp (TARGET_OS
, "elf") != 0)
1380 flags
|= SEC_ALLOC
| SEC_LOAD
;
1382 if (file_mips_abi
!= N64_ABI
)
1384 sec
= subseg_new (".reginfo", (subsegT
) 0);
1386 bfd_set_section_flags (stdoutput
, sec
, flags
);
1387 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
1390 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
1395 /* The 64-bit ABI uses a .MIPS.options section rather than
1396 .reginfo section. */
1397 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
1398 bfd_set_section_flags (stdoutput
, sec
, flags
);
1399 bfd_set_section_alignment (stdoutput
, sec
, 3);
1402 /* Set up the option header. */
1404 Elf_Internal_Options opthdr
;
1407 opthdr
.kind
= ODK_REGINFO
;
1408 opthdr
.size
= (sizeof (Elf_External_Options
)
1409 + sizeof (Elf64_External_RegInfo
));
1412 f
= frag_more (sizeof (Elf_External_Options
));
1413 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
1414 (Elf_External_Options
*) f
);
1416 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
1421 if (ECOFF_DEBUGGING
)
1423 sec
= subseg_new (".mdebug", (subsegT
) 0);
1424 (void) bfd_set_section_flags (stdoutput
, sec
,
1425 SEC_HAS_CONTENTS
| SEC_READONLY
);
1426 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1429 #ifdef MIPS_STABS_ELF
1430 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
1431 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
1432 SEC_READONLY
| SEC_RELOC
| SEC_DEBUGGING
);
1433 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
1436 subseg_set (seg
, subseg
);
1440 if (! ECOFF_DEBUGGING
)
1447 if (! ECOFF_DEBUGGING
)
1455 struct mips_cl_insn insn
;
1456 bfd_reloc_code_real_type unused_reloc
[3]
1457 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1459 imm_expr
.X_op
= O_absent
;
1460 imm_unmatched_hi
= false;
1461 offset_expr
.X_op
= O_absent
;
1462 imm_reloc
[0] = BFD_RELOC_UNUSED
;
1463 imm_reloc
[1] = BFD_RELOC_UNUSED
;
1464 imm_reloc
[2] = BFD_RELOC_UNUSED
;
1465 offset_reloc
[0] = BFD_RELOC_UNUSED
;
1466 offset_reloc
[1] = BFD_RELOC_UNUSED
;
1467 offset_reloc
[2] = BFD_RELOC_UNUSED
;
1469 if (mips_opts
.mips16
)
1470 mips16_ip (str
, &insn
);
1473 mips_ip (str
, &insn
);
1474 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1475 str
, insn
.insn_opcode
));
1480 as_bad ("%s `%s'", insn_error
, str
);
1484 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1486 if (mips_opts
.mips16
)
1487 mips16_macro (&insn
);
1493 if (imm_expr
.X_op
!= O_absent
)
1494 append_insn (NULL
, &insn
, &imm_expr
, imm_reloc
, imm_unmatched_hi
);
1495 else if (offset_expr
.X_op
!= O_absent
)
1496 append_insn (NULL
, &insn
, &offset_expr
, offset_reloc
, false);
1498 append_insn (NULL
, &insn
, NULL
, unused_reloc
, false);
1502 /* See whether instruction IP reads register REG. CLASS is the type
1506 insn_uses_reg (ip
, reg
, class)
1507 struct mips_cl_insn
*ip
;
1509 enum mips_regclass
class;
1511 if (class == MIPS16_REG
)
1513 assert (mips_opts
.mips16
);
1514 reg
= mips16_to_32_reg_map
[reg
];
1515 class = MIPS_GR_REG
;
1518 /* Don't report on general register 0, since it never changes. */
1519 if (class == MIPS_GR_REG
&& reg
== 0)
1522 if (class == MIPS_FP_REG
)
1524 assert (! mips_opts
.mips16
);
1525 /* If we are called with either $f0 or $f1, we must check $f0.
1526 This is not optimal, because it will introduce an unnecessary
1527 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1528 need to distinguish reading both $f0 and $f1 or just one of
1529 them. Note that we don't have to check the other way,
1530 because there is no instruction that sets both $f0 and $f1
1531 and requires a delay. */
1532 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
1533 && ((((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
) &~(unsigned)1)
1534 == (reg
&~ (unsigned) 1)))
1536 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
1537 && ((((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
) &~(unsigned)1)
1538 == (reg
&~ (unsigned) 1)))
1541 else if (! mips_opts
.mips16
)
1543 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
1544 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
1546 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
1547 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
1552 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
1553 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1554 & MIPS16OP_MASK_RX
)]
1557 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
1558 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1559 & MIPS16OP_MASK_RY
)]
1562 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
1563 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1564 & MIPS16OP_MASK_MOVE32Z
)]
1567 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
1569 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
1571 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
1573 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
1574 && ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1575 & MIPS16OP_MASK_REGR32
) == reg
)
1582 /* This function returns true if modifying a register requires a
1586 reg_needs_delay (reg
)
1589 unsigned long prev_pinfo
;
1591 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1592 if (! mips_opts
.noreorder
1593 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1594 && ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1595 || (! gpr_interlocks
1596 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1598 /* A load from a coprocessor or from memory. All load
1599 delays delay the use of general register rt for one
1600 instruction on the r3000. The r6000 and r4000 use
1602 /* Itbl support may require additional care here. */
1603 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1604 if (reg
== ((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
))
1611 /* Mark instruction labels in mips16 mode. This permits the linker to
1612 handle them specially, such as generating jalx instructions when
1613 needed. We also make them odd for the duration of the assembly, in
1614 order to generate the right sort of code. We will make them even
1615 in the adjust_symtab routine, while leaving them marked. This is
1616 convenient for the debugger and the disassembler. The linker knows
1617 to make them odd again. */
1620 mips16_mark_labels ()
1622 if (mips_opts
.mips16
)
1624 struct insn_label_list
*l
;
1627 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1630 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1631 S_SET_OTHER (l
->label
, STO_MIPS16
);
1633 val
= S_GET_VALUE (l
->label
);
1635 S_SET_VALUE (l
->label
, val
+ 1);
1640 /* Output an instruction. PLACE is where to put the instruction; if
1641 it is NULL, this uses frag_more to get room. IP is the instruction
1642 information. ADDRESS_EXPR is an operand of the instruction to be
1643 used with RELOC_TYPE. */
1646 append_insn (place
, ip
, address_expr
, reloc_type
, unmatched_hi
)
1648 struct mips_cl_insn
*ip
;
1649 expressionS
*address_expr
;
1650 bfd_reloc_code_real_type
*reloc_type
;
1651 boolean unmatched_hi
;
1653 register unsigned long prev_pinfo
, pinfo
;
1658 /* Mark instruction labels in mips16 mode. */
1659 if (mips_opts
.mips16
)
1660 mips16_mark_labels ();
1662 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1663 pinfo
= ip
->insn_mo
->pinfo
;
1665 if (place
== NULL
&& (! mips_opts
.noreorder
|| prev_nop_frag
!= NULL
))
1669 /* If the previous insn required any delay slots, see if we need
1670 to insert a NOP or two. There are eight kinds of possible
1671 hazards, of which an instruction can have at most one type.
1672 (1) a load from memory delay
1673 (2) a load from a coprocessor delay
1674 (3) an unconditional branch delay
1675 (4) a conditional branch delay
1676 (5) a move to coprocessor register delay
1677 (6) a load coprocessor register from memory delay
1678 (7) a coprocessor condition code delay
1679 (8) a HI/LO special register delay
1681 There are a lot of optimizations we could do that we don't.
1682 In particular, we do not, in general, reorder instructions.
1683 If you use gcc with optimization, it will reorder
1684 instructions and generally do much more optimization then we
1685 do here; repeating all that work in the assembler would only
1686 benefit hand written assembly code, and does not seem worth
1689 /* This is how a NOP is emitted. */
1690 #define emit_nop() \
1692 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1693 : md_number_to_chars (frag_more (4), 0, 4))
1695 /* The previous insn might require a delay slot, depending upon
1696 the contents of the current insn. */
1697 if (! mips_opts
.mips16
1698 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1699 && (((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1700 && ! cop_interlocks
)
1701 || (! gpr_interlocks
1702 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1704 /* A load from a coprocessor or from memory. All load
1705 delays delay the use of general register rt for one
1706 instruction on the r3000. The r6000 and r4000 use
1708 /* Itbl support may require additional care here. */
1709 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1710 if (mips_optimize
== 0
1711 || insn_uses_reg (ip
,
1712 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1717 else if (! mips_opts
.mips16
1718 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1719 && (((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
1720 && ! cop_interlocks
)
1721 || (mips_opts
.isa
== ISA_MIPS1
1722 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))))
1724 /* A generic coprocessor delay. The previous instruction
1725 modified a coprocessor general or control register. If
1726 it modified a control register, we need to avoid any
1727 coprocessor instruction (this is probably not always
1728 required, but it sometimes is). If it modified a general
1729 register, we avoid using that register.
1731 On the r6000 and r4000 loading a coprocessor register
1732 from memory is interlocked, and does not require a delay.
1734 This case is not handled very well. There is no special
1735 knowledge of CP0 handling, and the coprocessors other
1736 than the floating point unit are not distinguished at
1738 /* Itbl support may require additional care here. FIXME!
1739 Need to modify this to include knowledge about
1740 user specified delays! */
1741 if (prev_pinfo
& INSN_WRITE_FPR_T
)
1743 if (mips_optimize
== 0
1744 || insn_uses_reg (ip
,
1745 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
1750 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
1752 if (mips_optimize
== 0
1753 || insn_uses_reg (ip
,
1754 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
1761 /* We don't know exactly what the previous instruction
1762 does. If the current instruction uses a coprocessor
1763 register, we must insert a NOP. If previous
1764 instruction may set the condition codes, and the
1765 current instruction uses them, we must insert two
1767 /* Itbl support may require additional care here. */
1768 if (mips_optimize
== 0
1769 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
1770 && (pinfo
& INSN_READ_COND_CODE
)))
1772 else if (pinfo
& INSN_COP
)
1776 else if (! mips_opts
.mips16
1777 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1778 && (prev_pinfo
& INSN_WRITE_COND_CODE
)
1779 && ! cop_interlocks
)
1781 /* The previous instruction sets the coprocessor condition
1782 codes, but does not require a general coprocessor delay
1783 (this means it is a floating point comparison
1784 instruction). If this instruction uses the condition
1785 codes, we need to insert a single NOP. */
1786 /* Itbl support may require additional care here. */
1787 if (mips_optimize
== 0
1788 || (pinfo
& INSN_READ_COND_CODE
))
1792 /* If we're fixing up mfhi/mflo for the r7000 and the
1793 previous insn was an mfhi/mflo and the current insn
1794 reads the register that the mfhi/mflo wrote to, then
1797 else if (mips_7000_hilo_fix
1798 && MF_HILO_INSN (prev_pinfo
)
1799 && insn_uses_reg (ip
, ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1806 /* If we're fixing up mfhi/mflo for the r7000 and the
1807 2nd previous insn was an mfhi/mflo and the current insn
1808 reads the register that the mfhi/mflo wrote to, then
1811 else if (mips_7000_hilo_fix
1812 && MF_HILO_INSN (prev_prev_insn
.insn_opcode
)
1813 && insn_uses_reg (ip
, ((prev_prev_insn
.insn_opcode
>> OP_SH_RD
)
1821 else if (prev_pinfo
& INSN_READ_LO
)
1823 /* The previous instruction reads the LO register; if the
1824 current instruction writes to the LO register, we must
1825 insert two NOPS. Some newer processors have interlocks.
1826 Also the tx39's multiply instructions can be exectuted
1827 immediatly after a read from HI/LO (without the delay),
1828 though the tx39's divide insns still do require the
1830 if (! (hilo_interlocks
1831 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
1832 && (mips_optimize
== 0
1833 || (pinfo
& INSN_WRITE_LO
)))
1835 /* Most mips16 branch insns don't have a delay slot.
1836 If a read from LO is immediately followed by a branch
1837 to a write to LO we have a read followed by a write
1838 less than 2 insns away. We assume the target of
1839 a branch might be a write to LO, and insert a nop
1840 between a read and an immediately following branch. */
1841 else if (mips_opts
.mips16
1842 && (mips_optimize
== 0
1843 || (pinfo
& MIPS16_INSN_BRANCH
)))
1846 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1848 /* The previous instruction reads the HI register; if the
1849 current instruction writes to the HI register, we must
1850 insert a NOP. Some newer processors have interlocks.
1851 Also the note tx39's multiply above. */
1852 if (! (hilo_interlocks
1853 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
1854 && (mips_optimize
== 0
1855 || (pinfo
& INSN_WRITE_HI
)))
1857 /* Most mips16 branch insns don't have a delay slot.
1858 If a read from HI is immediately followed by a branch
1859 to a write to HI we have a read followed by a write
1860 less than 2 insns away. We assume the target of
1861 a branch might be a write to HI, and insert a nop
1862 between a read and an immediately following branch. */
1863 else if (mips_opts
.mips16
1864 && (mips_optimize
== 0
1865 || (pinfo
& MIPS16_INSN_BRANCH
)))
1869 /* If the previous instruction was in a noreorder section, then
1870 we don't want to insert the nop after all. */
1871 /* Itbl support may require additional care here. */
1872 if (prev_insn_unreordered
)
1875 /* There are two cases which require two intervening
1876 instructions: 1) setting the condition codes using a move to
1877 coprocessor instruction which requires a general coprocessor
1878 delay and then reading the condition codes 2) reading the HI
1879 or LO register and then writing to it (except on processors
1880 which have interlocks). If we are not already emitting a NOP
1881 instruction, we must check for these cases compared to the
1882 instruction previous to the previous instruction. */
1883 if ((! mips_opts
.mips16
1884 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1885 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1886 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1887 && (pinfo
& INSN_READ_COND_CODE
)
1888 && ! cop_interlocks
)
1889 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
1890 && (pinfo
& INSN_WRITE_LO
)
1891 && ! (hilo_interlocks
1892 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
))))
1893 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1894 && (pinfo
& INSN_WRITE_HI
)
1895 && ! (hilo_interlocks
1896 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
)))))
1901 if (prev_prev_insn_unreordered
)
1904 if (prev_prev_nop
&& nops
== 0)
1907 /* If we are being given a nop instruction, don't bother with
1908 one of the nops we would otherwise output. This will only
1909 happen when a nop instruction is used with mips_optimize set
1912 && ! mips_opts
.noreorder
1913 && ip
->insn_opcode
== (unsigned) (mips_opts
.mips16
? 0x6500 : 0))
1916 /* Now emit the right number of NOP instructions. */
1917 if (nops
> 0 && ! mips_opts
.noreorder
)
1920 unsigned long old_frag_offset
;
1922 struct insn_label_list
*l
;
1924 old_frag
= frag_now
;
1925 old_frag_offset
= frag_now_fix ();
1927 for (i
= 0; i
< nops
; i
++)
1932 listing_prev_line ();
1933 /* We may be at the start of a variant frag. In case we
1934 are, make sure there is enough space for the frag
1935 after the frags created by listing_prev_line. The
1936 argument to frag_grow here must be at least as large
1937 as the argument to all other calls to frag_grow in
1938 this file. We don't have to worry about being in the
1939 middle of a variant frag, because the variants insert
1940 all needed nop instructions themselves. */
1944 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1948 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
1949 symbol_set_frag (l
->label
, frag_now
);
1950 val
= (valueT
) frag_now_fix ();
1951 /* mips16 text labels are stored as odd. */
1952 if (mips_opts
.mips16
)
1954 S_SET_VALUE (l
->label
, val
);
1957 #ifndef NO_ECOFF_DEBUGGING
1958 if (ECOFF_DEBUGGING
)
1959 ecoff_fix_loc (old_frag
, old_frag_offset
);
1962 else if (prev_nop_frag
!= NULL
)
1964 /* We have a frag holding nops we may be able to remove. If
1965 we don't need any nops, we can decrease the size of
1966 prev_nop_frag by the size of one instruction. If we do
1967 need some nops, we count them in prev_nops_required. */
1968 if (prev_nop_frag_since
== 0)
1972 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1973 --prev_nop_frag_holds
;
1976 prev_nop_frag_required
+= nops
;
1980 if (prev_prev_nop
== 0)
1982 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1983 --prev_nop_frag_holds
;
1986 ++prev_nop_frag_required
;
1989 if (prev_nop_frag_holds
<= prev_nop_frag_required
)
1990 prev_nop_frag
= NULL
;
1992 ++prev_nop_frag_since
;
1994 /* Sanity check: by the time we reach the second instruction
1995 after prev_nop_frag, we should have used up all the nops
1996 one way or another. */
1997 assert (prev_nop_frag_since
<= 1 || prev_nop_frag
== NULL
);
2001 if (*reloc_type
> BFD_RELOC_UNUSED
)
2003 /* We need to set up a variant frag. */
2004 assert (mips_opts
.mips16
&& address_expr
!= NULL
);
2005 f
= frag_var (rs_machine_dependent
, 4, 0,
2006 RELAX_MIPS16_ENCODE (*reloc_type
- BFD_RELOC_UNUSED
,
2007 mips16_small
, mips16_ext
,
2009 & INSN_UNCOND_BRANCH_DELAY
),
2010 (*prev_insn_reloc_type
2011 == BFD_RELOC_MIPS16_JMP
)),
2012 make_expr_symbol (address_expr
), 0, NULL
);
2014 else if (place
!= NULL
)
2016 else if (mips_opts
.mips16
2018 && *reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2020 /* Make sure there is enough room to swap this instruction with
2021 a following jump instruction. */
2027 if (mips_opts
.mips16
2028 && mips_opts
.noreorder
2029 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
2030 as_warn (_("extended instruction in delay slot"));
2035 fixp
[0] = fixp
[1] = fixp
[2] = NULL
;
2036 if (address_expr
!= NULL
&& *reloc_type
< BFD_RELOC_UNUSED
)
2038 if (address_expr
->X_op
== O_constant
)
2042 switch (*reloc_type
)
2045 ip
->insn_opcode
|= address_expr
->X_add_number
;
2048 case BFD_RELOC_MIPS_HIGHEST
:
2049 tmp
= (address_expr
->X_add_number
+ 0x800080008000) >> 16;
2051 ip
->insn_opcode
|= (tmp
>> 16) & 0xffff;
2054 case BFD_RELOC_MIPS_HIGHER
:
2055 tmp
= (address_expr
->X_add_number
+ 0x80008000) >> 16;
2056 ip
->insn_opcode
|= (tmp
>> 16) & 0xffff;
2059 case BFD_RELOC_HI16_S
:
2060 ip
->insn_opcode
|= ((address_expr
->X_add_number
+ 0x8000)
2064 case BFD_RELOC_HI16
:
2065 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 16) & 0xffff;
2068 case BFD_RELOC_LO16
:
2069 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
2072 case BFD_RELOC_MIPS_JMP
:
2073 if ((address_expr
->X_add_number
& 3) != 0)
2074 as_bad (_("jump to misaligned address (0x%lx)"),
2075 (unsigned long) address_expr
->X_add_number
);
2076 if (address_expr
->X_add_number
& ~0xfffffff
2077 || address_expr
->X_add_number
> 0x7fffffc)
2078 as_bad (_("jump address range overflow (0x%lx)"),
2079 (unsigned long) address_expr
->X_add_number
);
2080 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
2083 case BFD_RELOC_MIPS16_JMP
:
2084 if ((address_expr
->X_add_number
& 3) != 0)
2085 as_bad (_("jump to misaligned address (0x%lx)"),
2086 (unsigned long) address_expr
->X_add_number
);
2087 if (address_expr
->X_add_number
& ~0xfffffff
2088 || address_expr
->X_add_number
> 0x7fffffc)
2089 as_bad (_("jump address range overflow (0x%lx)"),
2090 (unsigned long) address_expr
->X_add_number
);
2092 (((address_expr
->X_add_number
& 0x7c0000) << 3)
2093 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
2094 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
2097 case BFD_RELOC_16_PCREL
:
2098 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
2101 case BFD_RELOC_16_PCREL_S2
:
2111 /* Don't generate a reloc if we are writing into a variant frag. */
2114 fixp
[0] = fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
2116 (*reloc_type
== BFD_RELOC_16_PCREL
2117 || *reloc_type
== BFD_RELOC_16_PCREL_S2
),
2120 /* These relocations can have an addend that won't fit in
2121 4 octets for 64bit assembly. */
2122 if (HAVE_64BIT_GPRS
&&
2123 (*reloc_type
== BFD_RELOC_16
2124 || *reloc_type
== BFD_RELOC_32
2125 || *reloc_type
== BFD_RELOC_MIPS_JMP
2126 || *reloc_type
== BFD_RELOC_HI16_S
2127 || *reloc_type
== BFD_RELOC_LO16
2128 || *reloc_type
== BFD_RELOC_GPREL16
2129 || *reloc_type
== BFD_RELOC_MIPS_LITERAL
2130 || *reloc_type
== BFD_RELOC_GPREL32
2131 || *reloc_type
== BFD_RELOC_64
2132 || *reloc_type
== BFD_RELOC_CTOR
2133 || *reloc_type
== BFD_RELOC_MIPS_SUB
2134 || *reloc_type
== BFD_RELOC_MIPS_HIGHEST
2135 || *reloc_type
== BFD_RELOC_MIPS_HIGHER
2136 || *reloc_type
== BFD_RELOC_MIPS_SCN_DISP
2137 || *reloc_type
== BFD_RELOC_MIPS_REL16
2138 || *reloc_type
== BFD_RELOC_MIPS_RELGOT
))
2139 fixp
[0]->fx_no_overflow
= 1;
2143 struct mips_hi_fixup
*hi_fixup
;
2145 assert (*reloc_type
== BFD_RELOC_HI16_S
);
2146 hi_fixup
= ((struct mips_hi_fixup
*)
2147 xmalloc (sizeof (struct mips_hi_fixup
)));
2148 hi_fixup
->fixp
= fixp
[0];
2149 hi_fixup
->seg
= now_seg
;
2150 hi_fixup
->next
= mips_hi_fixup_list
;
2151 mips_hi_fixup_list
= hi_fixup
;
2154 if (reloc_type
[1] != BFD_RELOC_UNUSED
)
2156 /* FIXME: This symbol can be one of
2157 RSS_UNDEF, RSS_GP, RSS_GP0, RSS_LOC. */
2158 address_expr
->X_op
= O_absent
;
2159 address_expr
->X_add_symbol
= 0;
2160 address_expr
->X_add_number
= 0;
2162 fixp
[1] = fix_new_exp (frag_now
, f
- frag_now
->fr_literal
,
2163 4, address_expr
, false,
2166 /* These relocations can have an addend that won't fit in
2167 4 octets for 64bit assembly. */
2168 if (HAVE_64BIT_GPRS
&&
2169 (*reloc_type
== BFD_RELOC_16
2170 || *reloc_type
== BFD_RELOC_32
2171 || *reloc_type
== BFD_RELOC_MIPS_JMP
2172 || *reloc_type
== BFD_RELOC_HI16_S
2173 || *reloc_type
== BFD_RELOC_LO16
2174 || *reloc_type
== BFD_RELOC_GPREL16
2175 || *reloc_type
== BFD_RELOC_MIPS_LITERAL
2176 || *reloc_type
== BFD_RELOC_GPREL32
2177 || *reloc_type
== BFD_RELOC_64
2178 || *reloc_type
== BFD_RELOC_CTOR
2179 || *reloc_type
== BFD_RELOC_MIPS_SUB
2180 || *reloc_type
== BFD_RELOC_MIPS_HIGHEST
2181 || *reloc_type
== BFD_RELOC_MIPS_HIGHER
2182 || *reloc_type
== BFD_RELOC_MIPS_SCN_DISP
2183 || *reloc_type
== BFD_RELOC_MIPS_REL16
2184 || *reloc_type
== BFD_RELOC_MIPS_RELGOT
))
2185 fixp
[1]->fx_no_overflow
= 1;
2187 if (reloc_type
[2] != BFD_RELOC_UNUSED
)
2189 address_expr
->X_op
= O_absent
;
2190 address_expr
->X_add_symbol
= 0;
2191 address_expr
->X_add_number
= 0;
2193 fixp
[2] = fix_new_exp (frag_now
,
2194 f
- frag_now
->fr_literal
, 4,
2195 address_expr
, false,
2198 /* These relocations can have an addend that won't fit in
2199 4 octets for 64bit assembly. */
2200 if (HAVE_64BIT_GPRS
&&
2201 (*reloc_type
== BFD_RELOC_16
2202 || *reloc_type
== BFD_RELOC_32
2203 || *reloc_type
== BFD_RELOC_MIPS_JMP
2204 || *reloc_type
== BFD_RELOC_HI16_S
2205 || *reloc_type
== BFD_RELOC_LO16
2206 || *reloc_type
== BFD_RELOC_GPREL16
2207 || *reloc_type
== BFD_RELOC_MIPS_LITERAL
2208 || *reloc_type
== BFD_RELOC_GPREL32
2209 || *reloc_type
== BFD_RELOC_64
2210 || *reloc_type
== BFD_RELOC_CTOR
2211 || *reloc_type
== BFD_RELOC_MIPS_SUB
2212 || *reloc_type
== BFD_RELOC_MIPS_HIGHEST
2213 || *reloc_type
== BFD_RELOC_MIPS_HIGHER
2214 || *reloc_type
== BFD_RELOC_MIPS_SCN_DISP
2215 || *reloc_type
== BFD_RELOC_MIPS_REL16
2216 || *reloc_type
== BFD_RELOC_MIPS_RELGOT
))
2217 fixp
[2]->fx_no_overflow
= 1;
2224 if (! mips_opts
.mips16
)
2225 md_number_to_chars (f
, ip
->insn_opcode
, 4);
2226 else if (*reloc_type
== BFD_RELOC_MIPS16_JMP
)
2228 md_number_to_chars (f
, ip
->insn_opcode
>> 16, 2);
2229 md_number_to_chars (f
+ 2, ip
->insn_opcode
& 0xffff, 2);
2235 md_number_to_chars (f
, 0xf000 | ip
->extend
, 2);
2238 md_number_to_chars (f
, ip
->insn_opcode
, 2);
2241 /* Update the register mask information. */
2242 if (! mips_opts
.mips16
)
2244 if (pinfo
& INSN_WRITE_GPR_D
)
2245 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
2246 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
2247 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
2248 if (pinfo
& INSN_READ_GPR_S
)
2249 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
2250 if (pinfo
& INSN_WRITE_GPR_31
)
2251 mips_gprmask
|= 1 << 31;
2252 if (pinfo
& INSN_WRITE_FPR_D
)
2253 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
2254 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
2255 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
2256 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
2257 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
2258 if ((pinfo
& INSN_READ_FPR_R
) != 0)
2259 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
2260 if (pinfo
& INSN_COP
)
2262 /* We don't keep enough information to sort these cases out.
2263 The itbl support does keep this information however, although
2264 we currently don't support itbl fprmats as part of the cop
2265 instruction. May want to add this support in the future. */
2267 /* Never set the bit for $0, which is always zero. */
2268 mips_gprmask
&= ~1 << 0;
2272 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
2273 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
2274 & MIPS16OP_MASK_RX
);
2275 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
2276 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
2277 & MIPS16OP_MASK_RY
);
2278 if (pinfo
& MIPS16_INSN_WRITE_Z
)
2279 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RZ
)
2280 & MIPS16OP_MASK_RZ
);
2281 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
2282 mips_gprmask
|= 1 << TREG
;
2283 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
2284 mips_gprmask
|= 1 << SP
;
2285 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
2286 mips_gprmask
|= 1 << RA
;
2287 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2288 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
2289 if (pinfo
& MIPS16_INSN_READ_Z
)
2290 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
2291 & MIPS16OP_MASK_MOVE32Z
);
2292 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
2293 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
2294 & MIPS16OP_MASK_REGR32
);
2297 if (place
== NULL
&& ! mips_opts
.noreorder
)
2299 /* Filling the branch delay slot is more complex. We try to
2300 switch the branch with the previous instruction, which we can
2301 do if the previous instruction does not set up a condition
2302 that the branch tests and if the branch is not itself the
2303 target of any branch. */
2304 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2305 || (pinfo
& INSN_COND_BRANCH_DELAY
))
2307 if (mips_optimize
< 2
2308 /* If we have seen .set volatile or .set nomove, don't
2310 || mips_opts
.nomove
!= 0
2311 /* If we had to emit any NOP instructions, then we
2312 already know we can not swap. */
2314 /* If we don't even know the previous insn, we can not
2316 || ! prev_insn_valid
2317 /* If the previous insn is already in a branch delay
2318 slot, then we can not swap. */
2319 || prev_insn_is_delay_slot
2320 /* If the previous previous insn was in a .set
2321 noreorder, we can't swap. Actually, the MIPS
2322 assembler will swap in this situation. However, gcc
2323 configured -with-gnu-as will generate code like
2329 in which we can not swap the bne and INSN. If gcc is
2330 not configured -with-gnu-as, it does not output the
2331 .set pseudo-ops. We don't have to check
2332 prev_insn_unreordered, because prev_insn_valid will
2333 be 0 in that case. We don't want to use
2334 prev_prev_insn_valid, because we do want to be able
2335 to swap at the start of a function. */
2336 || prev_prev_insn_unreordered
2337 /* If the branch is itself the target of a branch, we
2338 can not swap. We cheat on this; all we check for is
2339 whether there is a label on this instruction. If
2340 there are any branches to anything other than a
2341 label, users must use .set noreorder. */
2342 || insn_labels
!= NULL
2343 /* If the previous instruction is in a variant frag, we
2344 can not do the swap. This does not apply to the
2345 mips16, which uses variant frags for different
2347 || (! mips_opts
.mips16
2348 && prev_insn_frag
->fr_type
== rs_machine_dependent
)
2349 /* If the branch reads the condition codes, we don't
2350 even try to swap, because in the sequence
2355 we can not swap, and I don't feel like handling that
2357 || (! mips_opts
.mips16
2358 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2359 && (pinfo
& INSN_READ_COND_CODE
))
2360 /* We can not swap with an instruction that requires a
2361 delay slot, becase the target of the branch might
2362 interfere with that instruction. */
2363 || (! mips_opts
.mips16
2364 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2366 /* Itbl support may require additional care here. */
2367 & (INSN_LOAD_COPROC_DELAY
2368 | INSN_COPROC_MOVE_DELAY
2369 | INSN_WRITE_COND_CODE
)))
2370 || (! (hilo_interlocks
2371 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
2375 || (! mips_opts
.mips16
2377 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))
2378 || (! mips_opts
.mips16
2379 && mips_opts
.isa
== ISA_MIPS1
2380 /* Itbl support may require additional care here. */
2381 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))
2382 /* We can not swap with a branch instruction. */
2384 & (INSN_UNCOND_BRANCH_DELAY
2385 | INSN_COND_BRANCH_DELAY
2386 | INSN_COND_BRANCH_LIKELY
))
2387 /* We do not swap with a trap instruction, since it
2388 complicates trap handlers to have the trap
2389 instruction be in a delay slot. */
2390 || (prev_pinfo
& INSN_TRAP
)
2391 /* If the branch reads a register that the previous
2392 instruction sets, we can not swap. */
2393 || (! mips_opts
.mips16
2394 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2395 && insn_uses_reg (ip
,
2396 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
2399 || (! mips_opts
.mips16
2400 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2401 && insn_uses_reg (ip
,
2402 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
2405 || (mips_opts
.mips16
2406 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
2407 && insn_uses_reg (ip
,
2408 ((prev_insn
.insn_opcode
2410 & MIPS16OP_MASK_RX
),
2412 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
2413 && insn_uses_reg (ip
,
2414 ((prev_insn
.insn_opcode
2416 & MIPS16OP_MASK_RY
),
2418 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
2419 && insn_uses_reg (ip
,
2420 ((prev_insn
.insn_opcode
2422 & MIPS16OP_MASK_RZ
),
2424 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
2425 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
2426 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2427 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
2428 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2429 && insn_uses_reg (ip
,
2430 MIPS16OP_EXTRACT_REG32R (prev_insn
.
2433 /* If the branch writes a register that the previous
2434 instruction sets, we can not swap (we know that
2435 branches write only to RD or to $31). */
2436 || (! mips_opts
.mips16
2437 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2438 && (((pinfo
& INSN_WRITE_GPR_D
)
2439 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
2440 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2441 || ((pinfo
& INSN_WRITE_GPR_31
)
2442 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
2445 || (! mips_opts
.mips16
2446 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2447 && (((pinfo
& INSN_WRITE_GPR_D
)
2448 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
2449 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2450 || ((pinfo
& INSN_WRITE_GPR_31
)
2451 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
2454 || (mips_opts
.mips16
2455 && (pinfo
& MIPS16_INSN_WRITE_31
)
2456 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2457 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2458 && (MIPS16OP_EXTRACT_REG32R (prev_insn
.insn_opcode
)
2460 /* If the branch writes a register that the previous
2461 instruction reads, we can not swap (we know that
2462 branches only write to RD or to $31). */
2463 || (! mips_opts
.mips16
2464 && (pinfo
& INSN_WRITE_GPR_D
)
2465 && insn_uses_reg (&prev_insn
,
2466 ((ip
->insn_opcode
>> OP_SH_RD
)
2469 || (! mips_opts
.mips16
2470 && (pinfo
& INSN_WRITE_GPR_31
)
2471 && insn_uses_reg (&prev_insn
, 31, MIPS_GR_REG
))
2472 || (mips_opts
.mips16
2473 && (pinfo
& MIPS16_INSN_WRITE_31
)
2474 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
2475 /* If we are generating embedded PIC code, the branch
2476 might be expanded into a sequence which uses $at, so
2477 we can't swap with an instruction which reads it. */
2478 || (mips_pic
== EMBEDDED_PIC
2479 && insn_uses_reg (&prev_insn
, AT
, MIPS_GR_REG
))
2480 /* If the previous previous instruction has a load
2481 delay, and sets a register that the branch reads, we
2483 || (! mips_opts
.mips16
2484 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2485 /* Itbl support may require additional care here. */
2486 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
2487 || (! gpr_interlocks
2488 && (prev_prev_insn
.insn_mo
->pinfo
2489 & INSN_LOAD_MEMORY_DELAY
)))
2490 && insn_uses_reg (ip
,
2491 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
2494 /* If one instruction sets a condition code and the
2495 other one uses a condition code, we can not swap. */
2496 || ((pinfo
& INSN_READ_COND_CODE
)
2497 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
2498 || ((pinfo
& INSN_WRITE_COND_CODE
)
2499 && (prev_pinfo
& INSN_READ_COND_CODE
))
2500 /* If the previous instruction uses the PC, we can not
2502 || (mips_opts
.mips16
2503 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
2504 /* If the previous instruction was extended, we can not
2506 || (mips_opts
.mips16
&& prev_insn_extended
)
2507 /* If the previous instruction had a fixup in mips16
2508 mode, we can not swap. This normally means that the
2509 previous instruction was a 4 byte branch anyhow. */
2510 || (mips_opts
.mips16
&& prev_insn_fixp
[0])
2511 /* If the previous instruction is a sync, sync.l, or
2512 sync.p, we can not swap. */
2513 || (prev_pinfo
& INSN_SYNC
))
2515 /* We could do even better for unconditional branches to
2516 portions of this object file; we could pick up the
2517 instruction at the destination, put it in the delay
2518 slot, and bump the destination address. */
2520 /* Update the previous insn information. */
2521 prev_prev_insn
= *ip
;
2522 prev_insn
.insn_mo
= &dummy_opcode
;
2526 /* It looks like we can actually do the swap. */
2527 if (! mips_opts
.mips16
)
2532 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2533 memcpy (temp
, prev_f
, 4);
2534 memcpy (prev_f
, f
, 4);
2535 memcpy (f
, temp
, 4);
2536 if (prev_insn_fixp
[0])
2538 prev_insn_fixp
[0]->fx_frag
= frag_now
;
2539 prev_insn_fixp
[0]->fx_where
= f
- frag_now
->fr_literal
;
2541 if (prev_insn_fixp
[1])
2543 prev_insn_fixp
[1]->fx_frag
= frag_now
;
2544 prev_insn_fixp
[1]->fx_where
= f
- frag_now
->fr_literal
;
2546 if (prev_insn_fixp
[2])
2548 prev_insn_fixp
[2]->fx_frag
= frag_now
;
2549 prev_insn_fixp
[2]->fx_where
= f
- frag_now
->fr_literal
;
2553 fixp
[0]->fx_frag
= prev_insn_frag
;
2554 fixp
[0]->fx_where
= prev_insn_where
;
2558 fixp
[1]->fx_frag
= prev_insn_frag
;
2559 fixp
[1]->fx_where
= prev_insn_where
;
2563 fixp
[2]->fx_frag
= prev_insn_frag
;
2564 fixp
[2]->fx_where
= prev_insn_where
;
2572 assert (prev_insn_fixp
[0] == NULL
);
2573 assert (prev_insn_fixp
[1] == NULL
);
2574 assert (prev_insn_fixp
[2] == NULL
);
2575 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2576 memcpy (temp
, prev_f
, 2);
2577 memcpy (prev_f
, f
, 2);
2578 if (*reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2580 assert (*reloc_type
== BFD_RELOC_UNUSED
);
2581 memcpy (f
, temp
, 2);
2585 memcpy (f
, f
+ 2, 2);
2586 memcpy (f
+ 2, temp
, 2);
2590 fixp
[0]->fx_frag
= prev_insn_frag
;
2591 fixp
[0]->fx_where
= prev_insn_where
;
2595 fixp
[1]->fx_frag
= prev_insn_frag
;
2596 fixp
[1]->fx_where
= prev_insn_where
;
2600 fixp
[2]->fx_frag
= prev_insn_frag
;
2601 fixp
[2]->fx_where
= prev_insn_where
;
2605 /* Update the previous insn information; leave prev_insn
2607 prev_prev_insn
= *ip
;
2609 prev_insn_is_delay_slot
= 1;
2611 /* If that was an unconditional branch, forget the previous
2612 insn information. */
2613 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2615 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2616 prev_insn
.insn_mo
= &dummy_opcode
;
2619 prev_insn_fixp
[0] = NULL
;
2620 prev_insn_fixp
[1] = NULL
;
2621 prev_insn_fixp
[2] = NULL
;
2622 prev_insn_reloc_type
[0] = BFD_RELOC_UNUSED
;
2623 prev_insn_reloc_type
[1] = BFD_RELOC_UNUSED
;
2624 prev_insn_reloc_type
[2] = BFD_RELOC_UNUSED
;
2625 prev_insn_extended
= 0;
2627 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
2629 /* We don't yet optimize a branch likely. What we should do
2630 is look at the target, copy the instruction found there
2631 into the delay slot, and increment the branch to jump to
2632 the next instruction. */
2634 /* Update the previous insn information. */
2635 prev_prev_insn
= *ip
;
2636 prev_insn
.insn_mo
= &dummy_opcode
;
2637 prev_insn_fixp
[0] = NULL
;
2638 prev_insn_fixp
[1] = NULL
;
2639 prev_insn_fixp
[2] = NULL
;
2640 prev_insn_reloc_type
[0] = BFD_RELOC_UNUSED
;
2641 prev_insn_reloc_type
[1] = BFD_RELOC_UNUSED
;
2642 prev_insn_reloc_type
[2] = BFD_RELOC_UNUSED
;
2643 prev_insn_extended
= 0;
2647 /* Update the previous insn information. */
2649 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2651 prev_prev_insn
= prev_insn
;
2654 /* Any time we see a branch, we always fill the delay slot
2655 immediately; since this insn is not a branch, we know it
2656 is not in a delay slot. */
2657 prev_insn_is_delay_slot
= 0;
2659 prev_insn_fixp
[0] = fixp
[0];
2660 prev_insn_fixp
[1] = fixp
[1];
2661 prev_insn_fixp
[2] = fixp
[2];
2662 prev_insn_reloc_type
[0] = reloc_type
[0];
2663 prev_insn_reloc_type
[1] = reloc_type
[1];
2664 prev_insn_reloc_type
[2] = reloc_type
[2];
2665 if (mips_opts
.mips16
)
2666 prev_insn_extended
= (ip
->use_extend
2667 || *reloc_type
> BFD_RELOC_UNUSED
);
2670 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2671 prev_insn_unreordered
= 0;
2672 prev_insn_frag
= frag_now
;
2673 prev_insn_where
= f
- frag_now
->fr_literal
;
2674 prev_insn_valid
= 1;
2676 else if (place
== NULL
)
2678 /* We need to record a bit of information even when we are not
2679 reordering, in order to determine the base address for mips16
2680 PC relative relocs. */
2681 prev_prev_insn
= prev_insn
;
2683 prev_insn_reloc_type
[0] = reloc_type
[0];
2684 prev_insn_reloc_type
[1] = reloc_type
[1];
2685 prev_insn_reloc_type
[2] = reloc_type
[2];
2686 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2687 prev_insn_unreordered
= 1;
2690 /* We just output an insn, so the next one doesn't have a label. */
2691 mips_clear_insn_labels ();
2693 /* We must ensure that a fixup associated with an unmatched %hi
2694 reloc does not become a variant frag. Otherwise, the
2695 rearrangement of %hi relocs in frob_file may confuse
2699 frag_wane (frag_now
);
2704 /* This function forgets that there was any previous instruction or
2705 label. If PRESERVE is non-zero, it remembers enough information to
2706 know whether nops are needed before a noreorder section. */
2709 mips_no_prev_insn (preserve
)
2714 prev_insn
.insn_mo
= &dummy_opcode
;
2715 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2716 prev_nop_frag
= NULL
;
2717 prev_nop_frag_holds
= 0;
2718 prev_nop_frag_required
= 0;
2719 prev_nop_frag_since
= 0;
2721 prev_insn_valid
= 0;
2722 prev_insn_is_delay_slot
= 0;
2723 prev_insn_unreordered
= 0;
2724 prev_insn_extended
= 0;
2725 prev_insn_reloc_type
[0] = BFD_RELOC_UNUSED
;
2726 prev_insn_reloc_type
[1] = BFD_RELOC_UNUSED
;
2727 prev_insn_reloc_type
[2] = BFD_RELOC_UNUSED
;
2728 prev_prev_insn_unreordered
= 0;
2729 mips_clear_insn_labels ();
2732 /* This function must be called whenever we turn on noreorder or emit
2733 something other than instructions. It inserts any NOPS which might
2734 be needed by the previous instruction, and clears the information
2735 kept for the previous instructions. The INSNS parameter is true if
2736 instructions are to follow. */
2739 mips_emit_delays (insns
)
2742 if (! mips_opts
.noreorder
)
2747 if ((! mips_opts
.mips16
2748 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2749 && (! cop_interlocks
2750 && (prev_insn
.insn_mo
->pinfo
2751 & (INSN_LOAD_COPROC_DELAY
2752 | INSN_COPROC_MOVE_DELAY
2753 | INSN_WRITE_COND_CODE
))))
2754 || (! hilo_interlocks
2755 && (prev_insn
.insn_mo
->pinfo
2758 || (! mips_opts
.mips16
2760 && (prev_insn
.insn_mo
->pinfo
2761 & INSN_LOAD_MEMORY_DELAY
))
2762 || (! mips_opts
.mips16
2763 && mips_opts
.isa
== ISA_MIPS1
2764 && (prev_insn
.insn_mo
->pinfo
2765 & INSN_COPROC_MEMORY_DELAY
)))
2767 /* Itbl support may require additional care here. */
2769 if ((! mips_opts
.mips16
2770 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2771 && (! cop_interlocks
2772 && prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2773 || (! hilo_interlocks
2774 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2775 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2778 if (prev_insn_unreordered
)
2781 else if ((! mips_opts
.mips16
2782 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2783 && (! cop_interlocks
2784 && prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2785 || (! hilo_interlocks
2786 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2787 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2789 /* Itbl support may require additional care here. */
2790 if (! prev_prev_insn_unreordered
)
2796 struct insn_label_list
*l
;
2800 /* Record the frag which holds the nop instructions, so
2801 that we can remove them if we don't need them. */
2802 frag_grow (mips_opts
.mips16
? nops
* 2 : nops
* 4);
2803 prev_nop_frag
= frag_now
;
2804 prev_nop_frag_holds
= nops
;
2805 prev_nop_frag_required
= 0;
2806 prev_nop_frag_since
= 0;
2809 for (; nops
> 0; --nops
)
2814 /* Move on to a new frag, so that it is safe to simply
2815 decrease the size of prev_nop_frag. */
2816 frag_wane (frag_now
);
2820 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2824 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2825 symbol_set_frag (l
->label
, frag_now
);
2826 val
= (valueT
) frag_now_fix ();
2827 /* mips16 text labels are stored as odd. */
2828 if (mips_opts
.mips16
)
2830 S_SET_VALUE (l
->label
, val
);
2835 /* Mark instruction labels in mips16 mode. */
2836 if (mips_opts
.mips16
&& insns
)
2837 mips16_mark_labels ();
2839 mips_no_prev_insn (insns
);
2842 /* Build an instruction created by a macro expansion. This is passed
2843 a pointer to the count of instructions created so far, an
2844 expression, the name of the instruction to build, an operand format
2845 string, and corresponding arguments. */
2849 macro_build (char *place
,
2857 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
2866 struct mips_cl_insn insn
;
2867 bfd_reloc_code_real_type r
[3];
2871 va_start (args
, fmt
);
2877 * If the macro is about to expand into a second instruction,
2878 * print a warning if needed. We need to pass ip as a parameter
2879 * to generate a better warning message here...
2881 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
2882 as_warn (_("Macro instruction expanded into multiple instructions"));
2885 * If the macro is about to expand into a second instruction,
2886 * and it is in a delay slot, print a warning.
2890 && mips_opts
.noreorder
2891 && (prev_prev_insn
.insn_mo
->pinfo
2892 & (INSN_UNCOND_BRANCH_DELAY
| INSN_COND_BRANCH_DELAY
2893 | INSN_COND_BRANCH_LIKELY
)) != 0)
2894 as_warn (_("Macro instruction expanded into multiple instructions in a branch delay slot"));
2897 *counter
+= 1; /* bump instruction counter */
2899 if (mips_opts
.mips16
)
2901 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
);
2906 r
[0] = BFD_RELOC_UNUSED
;
2907 r
[1] = BFD_RELOC_UNUSED
;
2908 r
[2] = BFD_RELOC_UNUSED
;
2909 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2910 assert (insn
.insn_mo
);
2911 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2913 /* Search until we get a match for NAME. */
2916 /* It is assumed here that macros will never generate
2917 MIPS-3D instructions. */
2918 if (strcmp (fmt
, insn
.insn_mo
->args
) == 0
2919 && insn
.insn_mo
->pinfo
!= INSN_MACRO
2920 && OPCODE_IS_MEMBER (insn
.insn_mo
, mips_opts
.isa
, mips_arch
)
2921 && (mips_arch
!= CPU_R4650
|| (insn
.insn_mo
->pinfo
& FP_D
) == 0))
2925 assert (insn
.insn_mo
->name
);
2926 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2929 insn
.insn_opcode
= insn
.insn_mo
->match
;
2945 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RT
;
2949 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE
;
2954 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FT
;
2959 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RD
;
2964 int tmp
= va_arg (args
, int);
2966 insn
.insn_opcode
|= tmp
<< OP_SH_RT
;
2967 insn
.insn_opcode
|= tmp
<< OP_SH_RD
;
2973 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FS
;
2980 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_SHAMT
;
2984 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FD
;
2988 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE20
;
2992 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE19
;
2996 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE2
;
3003 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RS
;
3009 *r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
3010 assert (*r
== BFD_RELOC_GPREL16
3011 || *r
== BFD_RELOC_MIPS_LITERAL
3012 || *r
== BFD_RELOC_MIPS_HIGHER
3013 || *r
== BFD_RELOC_HI16_S
3014 || *r
== BFD_RELOC_LO16
3015 || *r
== BFD_RELOC_MIPS_GOT16
3016 || *r
== BFD_RELOC_MIPS_CALL16
3017 || *r
== BFD_RELOC_MIPS_GOT_LO16
3018 || *r
== BFD_RELOC_MIPS_CALL_LO16
3019 || (ep
->X_op
== O_subtract
3020 && *r
== BFD_RELOC_PCREL_LO16
));
3024 *r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
3026 && (ep
->X_op
== O_constant
3027 || (ep
->X_op
== O_symbol
3028 && (*r
== BFD_RELOC_MIPS_HIGHEST
3029 || *r
== BFD_RELOC_HI16_S
3030 || *r
== BFD_RELOC_HI16
3031 || *r
== BFD_RELOC_GPREL16
3032 || *r
== BFD_RELOC_MIPS_GOT_HI16
3033 || *r
== BFD_RELOC_MIPS_CALL_HI16
))
3034 || (ep
->X_op
== O_subtract
3035 && *r
== BFD_RELOC_PCREL_HI16_S
)));
3039 assert (ep
!= NULL
);
3041 * This allows macro() to pass an immediate expression for
3042 * creating short branches without creating a symbol.
3043 * Note that the expression still might come from the assembly
3044 * input, in which case the value is not checked for range nor
3045 * is a relocation entry generated (yuck).
3047 if (ep
->X_op
== O_constant
)
3049 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
3053 if (mips_pic
== EMBEDDED_PIC
)
3054 *r
= BFD_RELOC_16_PCREL_S2
;
3056 *r
= BFD_RELOC_16_PCREL
;
3060 assert (ep
!= NULL
);
3061 *r
= BFD_RELOC_MIPS_JMP
;
3065 insn
.insn_opcode
|= va_arg (args
, unsigned long);
3074 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3076 append_insn (place
, &insn
, ep
, r
, false);
3080 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
)
3082 int *counter ATTRIBUTE_UNUSED
;
3088 struct mips_cl_insn insn
;
3089 bfd_reloc_code_real_type r
[3]
3090 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3092 insn
.insn_mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
3093 assert (insn
.insn_mo
);
3094 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3096 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
3097 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
3100 assert (insn
.insn_mo
->name
);
3101 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3104 insn
.insn_opcode
= insn
.insn_mo
->match
;
3105 insn
.use_extend
= false;
3124 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RY
;
3129 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RX
;
3133 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RZ
;
3137 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_MOVE32Z
;
3147 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_REGR32
;
3154 regno
= va_arg (args
, int);
3155 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
3156 insn
.insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
3177 assert (ep
!= NULL
);
3179 if (ep
->X_op
!= O_constant
)
3180 *r
= (int) BFD_RELOC_UNUSED
+ c
;
3183 mips16_immed (NULL
, 0, c
, ep
->X_add_number
, false, false,
3184 false, &insn
.insn_opcode
, &insn
.use_extend
,
3187 *r
= BFD_RELOC_UNUSED
;
3193 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_IMM6
;
3200 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3202 append_insn (place
, &insn
, ep
, r
, false);
3206 * Generate a "lui" instruction.
3209 macro_build_lui (place
, counter
, ep
, regnum
)
3215 expressionS high_expr
;
3216 struct mips_cl_insn insn
;
3217 bfd_reloc_code_real_type r
[3]
3218 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3219 CONST
char *name
= "lui";
3220 CONST
char *fmt
= "t,u";
3222 assert (! mips_opts
.mips16
);
3228 high_expr
.X_op
= O_constant
;
3229 high_expr
.X_add_number
= ep
->X_add_number
;
3232 if (high_expr
.X_op
== O_constant
)
3234 /* we can compute the instruction now without a relocation entry */
3235 high_expr
.X_add_number
= ((high_expr
.X_add_number
+ 0x8000)
3237 *r
= BFD_RELOC_UNUSED
;
3239 else if (! HAVE_NEWABI
)
3241 assert (ep
->X_op
== O_symbol
);
3242 /* _gp_disp is a special case, used from s_cpload. */
3243 assert (mips_pic
== NO_PIC
3244 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
3245 *r
= BFD_RELOC_HI16_S
;
3249 * If the macro is about to expand into a second instruction,
3250 * print a warning if needed. We need to pass ip as a parameter
3251 * to generate a better warning message here...
3253 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
3254 as_warn (_("Macro instruction expanded into multiple instructions"));
3257 *counter
+= 1; /* bump instruction counter */
3259 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
3260 assert (insn
.insn_mo
);
3261 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3262 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
3264 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
3265 if (*r
== BFD_RELOC_UNUSED
)
3267 insn
.insn_opcode
|= high_expr
.X_add_number
;
3268 append_insn (place
, &insn
, NULL
, r
, false);
3271 append_insn (place
, &insn
, &high_expr
, r
, false);
3275 * Generates code to set the $at register to true (one)
3276 * if reg is less than the immediate expression.
3279 set_at (counter
, reg
, unsignedp
)
3284 if (imm_expr
.X_op
== O_constant
3285 && imm_expr
.X_add_number
>= -0x8000
3286 && imm_expr
.X_add_number
< 0x8000)
3287 macro_build ((char *) NULL
, counter
, &imm_expr
,
3288 unsignedp
? "sltiu" : "slti",
3289 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
3292 load_register (counter
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
3293 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3294 unsignedp
? "sltu" : "slt",
3295 "d,v,t", AT
, reg
, AT
);
3299 /* Warn if an expression is not a constant. */
3302 check_absolute_expr (ip
, ex
)
3303 struct mips_cl_insn
*ip
;
3306 if (ex
->X_op
== O_big
)
3307 as_bad (_("unsupported large constant"));
3308 else if (ex
->X_op
!= O_constant
)
3309 as_bad (_("Instruction %s requires absolute expression"), ip
->insn_mo
->name
);
3312 /* Count the leading zeroes by performing a binary chop. This is a
3313 bulky bit of source, but performance is a LOT better for the
3314 majority of values than a simple loop to count the bits:
3315 for (lcnt = 0; (lcnt < 32); lcnt++)
3316 if ((v) & (1 << (31 - lcnt)))
3318 However it is not code size friendly, and the gain will drop a bit
3319 on certain cached systems.
3321 #define COUNT_TOP_ZEROES(v) \
3322 (((v) & ~0xffff) == 0 \
3323 ? ((v) & ~0xff) == 0 \
3324 ? ((v) & ~0xf) == 0 \
3325 ? ((v) & ~0x3) == 0 \
3326 ? ((v) & ~0x1) == 0 \
3331 : ((v) & ~0x7) == 0 \
3334 : ((v) & ~0x3f) == 0 \
3335 ? ((v) & ~0x1f) == 0 \
3338 : ((v) & ~0x7f) == 0 \
3341 : ((v) & ~0xfff) == 0 \
3342 ? ((v) & ~0x3ff) == 0 \
3343 ? ((v) & ~0x1ff) == 0 \
3346 : ((v) & ~0x7ff) == 0 \
3349 : ((v) & ~0x3fff) == 0 \
3350 ? ((v) & ~0x1fff) == 0 \
3353 : ((v) & ~0x7fff) == 0 \
3356 : ((v) & ~0xffffff) == 0 \
3357 ? ((v) & ~0xfffff) == 0 \
3358 ? ((v) & ~0x3ffff) == 0 \
3359 ? ((v) & ~0x1ffff) == 0 \
3362 : ((v) & ~0x7ffff) == 0 \
3365 : ((v) & ~0x3fffff) == 0 \
3366 ? ((v) & ~0x1fffff) == 0 \
3369 : ((v) & ~0x7fffff) == 0 \
3372 : ((v) & ~0xfffffff) == 0 \
3373 ? ((v) & ~0x3ffffff) == 0 \
3374 ? ((v) & ~0x1ffffff) == 0 \
3377 : ((v) & ~0x7ffffff) == 0 \
3380 : ((v) & ~0x3fffffff) == 0 \
3381 ? ((v) & ~0x1fffffff) == 0 \
3384 : ((v) & ~0x7fffffff) == 0 \
3388 /* Is the given value a sign-extended 32-bit value? */
3389 #define IS_SEXT_32BIT_NUM(x) \
3390 (((x) &~ (offsetT) 0x7fffffff) == 0 \
3391 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
3394 * This routine generates the least number of instructions neccessary to load
3395 * an absolute expression value into a register.
3398 load_register (counter
, reg
, ep
, dbl
)
3405 expressionS hi32
, lo32
;
3407 if (ep
->X_op
!= O_big
)
3409 assert (ep
->X_op
== O_constant
);
3410 if (ep
->X_add_number
< 0x8000
3411 && (ep
->X_add_number
>= 0
3412 || (ep
->X_add_number
>= -0x8000
3415 || sizeof (ep
->X_add_number
) > 4))))
3417 /* We can handle 16 bit signed values with an addiu to
3418 $zero. No need to ever use daddiu here, since $zero and
3419 the result are always correct in 32 bit mode. */
3420 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
3421 (int) BFD_RELOC_LO16
);
3424 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
3426 /* We can handle 16 bit unsigned values with an ori to
3428 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
3429 (int) BFD_RELOC_LO16
);
3432 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)
3435 || sizeof (ep
->X_add_number
) > 4
3436 || (ep
->X_add_number
& 0x80000000) == 0))
3437 || ((HAVE_32BIT_GPRS
|| ! dbl
)
3438 && (ep
->X_add_number
&~ (offsetT
) 0xffffffff) == 0)
3441 && ((ep
->X_add_number
&~ (offsetT
) 0xffffffff)
3442 == ~ (offsetT
) 0xffffffff)))
3444 /* 32 bit values require an lui. */
3445 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
3446 (int) BFD_RELOC_HI16
);
3447 if ((ep
->X_add_number
& 0xffff) != 0)
3448 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
3449 (int) BFD_RELOC_LO16
);
3454 /* The value is larger than 32 bits. */
3456 if (HAVE_32BIT_GPRS
)
3458 as_bad (_("Number (0x%lx) larger than 32 bits"),
3459 (unsigned long) ep
->X_add_number
);
3460 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
3461 (int) BFD_RELOC_LO16
);
3465 if (ep
->X_op
!= O_big
)
3468 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3469 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3470 hi32
.X_add_number
&= 0xffffffff;
3472 lo32
.X_add_number
&= 0xffffffff;
3476 assert (ep
->X_add_number
> 2);
3477 if (ep
->X_add_number
== 3)
3478 generic_bignum
[3] = 0;
3479 else if (ep
->X_add_number
> 4)
3480 as_bad (_("Number larger than 64 bits"));
3481 lo32
.X_op
= O_constant
;
3482 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
3483 hi32
.X_op
= O_constant
;
3484 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
3487 if (hi32
.X_add_number
== 0)
3492 unsigned long hi
, lo
;
3494 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
3496 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
3498 macro_build ((char *) NULL
, counter
, &lo32
, "addiu", "t,r,j",
3499 reg
, 0, (int) BFD_RELOC_LO16
);
3502 if (lo32
.X_add_number
& 0x80000000)
3504 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3505 (int) BFD_RELOC_HI16
);
3506 if (lo32
.X_add_number
& 0xffff)
3507 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i",
3508 reg
, reg
, (int) BFD_RELOC_LO16
);
3513 /* Check for 16bit shifted constant. We know that hi32 is
3514 non-zero, so start the mask on the first bit of the hi32
3519 unsigned long himask
, lomask
;
3523 himask
= 0xffff >> (32 - shift
);
3524 lomask
= (0xffff << shift
) & 0xffffffff;
3528 himask
= 0xffff << (shift
- 32);
3531 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
3532 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
3536 tmp
.X_op
= O_constant
;
3538 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
3539 | (lo32
.X_add_number
>> shift
));
3541 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
3542 macro_build ((char *) NULL
, counter
, &tmp
,
3543 "ori", "t,r,i", reg
, 0,
3544 (int) BFD_RELOC_LO16
);
3545 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3546 (shift
>= 32) ? "dsll32" : "dsll",
3548 (shift
>= 32) ? shift
- 32 : shift
);
3553 while (shift
<= (64 - 16));
3555 /* Find the bit number of the lowest one bit, and store the
3556 shifted value in hi/lo. */
3557 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
3558 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
3562 while ((lo
& 1) == 0)
3567 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
3573 while ((hi
& 1) == 0)
3582 /* Optimize if the shifted value is a (power of 2) - 1. */
3583 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
3584 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
3586 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
3591 /* This instruction will set the register to be all
3593 tmp
.X_op
= O_constant
;
3594 tmp
.X_add_number
= (offsetT
) -1;
3595 macro_build ((char *) NULL
, counter
, &tmp
, "addiu", "t,r,j",
3596 reg
, 0, (int) BFD_RELOC_LO16
);
3600 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3601 (bit
>= 32) ? "dsll32" : "dsll",
3603 (bit
>= 32) ? bit
- 32 : bit
);
3605 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3606 (shift
>= 32) ? "dsrl32" : "dsrl",
3608 (shift
>= 32) ? shift
- 32 : shift
);
3613 /* Sign extend hi32 before calling load_register, because we can
3614 generally get better code when we load a sign extended value. */
3615 if ((hi32
.X_add_number
& 0x80000000) != 0)
3616 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
3617 load_register (counter
, reg
, &hi32
, 0);
3620 if ((lo32
.X_add_number
& 0xffff0000) == 0)
3624 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3625 "dsll32", "d,w,<", reg
, freg
, 0);
3633 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
3635 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3636 (int) BFD_RELOC_HI16
);
3637 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3638 "dsrl32", "d,w,<", reg
, reg
, 0);
3644 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "dsll",
3645 "d,w,<", reg
, freg
, 16);
3649 mid16
.X_add_number
>>= 16;
3650 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
3651 freg
, (int) BFD_RELOC_LO16
);
3652 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "dsll",
3653 "d,w,<", reg
, reg
, 16);
3656 if ((lo32
.X_add_number
& 0xffff) != 0)
3657 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, freg
,
3658 (int) BFD_RELOC_LO16
);
3661 /* Load an address into a register. */
3664 load_address (counter
, reg
, ep
, dbl
, used_at
)
3673 if (ep
->X_op
!= O_constant
3674 && ep
->X_op
!= O_symbol
)
3676 as_bad (_("expression too complex"));
3677 ep
->X_op
= O_constant
;
3680 if (ep
->X_op
== O_constant
)
3682 load_register (counter
, reg
, ep
, dbl
);
3686 if (mips_pic
== NO_PIC
)
3688 /* If this is a reference to a GP relative symbol, we want
3689 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3691 lui $reg,<sym> (BFD_RELOC_HI16_S)
3692 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3693 If we have an addend, we always use the latter form.
3695 With 64bit address space and a usable $at we want
3696 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3697 lui $at,<sym> (BFD_RELOC_HI16_S)
3698 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3699 daddiu $at,<sym> (BFD_RELOC_LO16)
3703 If $at is already in use, we use an path which is suboptimal
3704 on superscalar processors.
3705 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3706 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3708 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
3710 daddiu $reg,<sym> (BFD_RELOC_LO16)
3716 /* We don't do GP optimization for now because RELAX_ENCODE can't
3717 hold the data for such large chunks. */
3721 macro_build (p
, counter
, ep
, "lui", "t,u",
3722 reg
, (int) BFD_RELOC_MIPS_HIGHEST
);
3723 macro_build (p
, counter
, ep
, "lui", "t,u",
3724 AT
, (int) BFD_RELOC_HI16_S
);
3725 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3726 reg
, reg
, (int) BFD_RELOC_MIPS_HIGHER
);
3727 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3728 AT
, AT
, (int) BFD_RELOC_LO16
);
3729 macro_build (p
, counter
, (expressionS
*) NULL
, "dsll32",
3730 "d,w,<", reg
, reg
, 0);
3731 macro_build (p
, counter
, (expressionS
*) NULL
, "dadd",
3732 "d,v,t", reg
, reg
, AT
);
3737 macro_build (p
, counter
, ep
, "lui", "t,u",
3738 reg
, (int) BFD_RELOC_MIPS_HIGHEST
);
3739 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3740 reg
, reg
, (int) BFD_RELOC_MIPS_HIGHER
);
3741 macro_build (p
, counter
, (expressionS
*) NULL
, "dsll",
3742 "d,w,<", reg
, reg
, 16);
3743 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3744 reg
, reg
, (int) BFD_RELOC_HI16_S
);
3745 macro_build (p
, counter
, (expressionS
*) NULL
, "dsll",
3746 "d,w,<", reg
, reg
, 16);
3747 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3748 reg
, reg
, (int) BFD_RELOC_LO16
);
3754 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
3755 && ! nopic_need_relax (ep
->X_add_symbol
, 1))
3758 macro_build ((char *) NULL
, counter
, ep
,
3759 dbl
? "daddiu" : "addiu", "t,r,j", reg
, GP
,
3760 (int) BFD_RELOC_GPREL16
);
3761 p
= frag_var (rs_machine_dependent
, 8, 0,
3762 RELAX_ENCODE (4, 8, 0, 4, 0,
3763 mips_opts
.warn_about_macros
),
3764 ep
->X_add_symbol
, 0, NULL
);
3766 macro_build_lui (p
, counter
, ep
, reg
);
3769 macro_build (p
, counter
, ep
, dbl
? "daddiu" : "addiu",
3770 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3773 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3777 /* If this is a reference to an external symbol, we want
3778 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3780 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3782 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3783 If there is a constant, it must be added in after. */
3784 ex
.X_add_number
= ep
->X_add_number
;
3785 ep
->X_add_number
= 0;
3787 macro_build ((char *) NULL
, counter
, ep
,
3788 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
3789 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3790 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
3791 p
= frag_var (rs_machine_dependent
, 4, 0,
3792 RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts
.warn_about_macros
),
3793 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3794 macro_build (p
, counter
, ep
,
3795 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3796 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3797 if (ex
.X_add_number
!= 0)
3799 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3800 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3801 ex
.X_op
= O_constant
;
3802 macro_build ((char *) NULL
, counter
, &ex
,
3803 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3804 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3807 else if (mips_pic
== SVR4_PIC
)
3812 /* This is the large GOT case. If this is a reference to an
3813 external symbol, we want
3814 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3816 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3817 Otherwise, for a reference to a local symbol, we want
3818 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3820 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3821 If there is a constant, it must be added in after. */
3822 ex
.X_add_number
= ep
->X_add_number
;
3823 ep
->X_add_number
= 0;
3824 if (reg_needs_delay (GP
))
3829 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
3830 (int) BFD_RELOC_MIPS_GOT_HI16
);
3831 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3832 dbl
? "daddu" : "addu", "d,v,t", reg
, reg
, GP
);
3833 macro_build ((char *) NULL
, counter
, ep
, dbl
? "ld" : "lw",
3834 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT_LO16
, reg
);
3835 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
3836 RELAX_ENCODE (12, 12 + off
, off
, 8 + off
, 0,
3837 mips_opts
.warn_about_macros
),
3838 ep
->X_add_symbol
, 0, NULL
);
3841 /* We need a nop before loading from $gp. This special
3842 check is required because the lui which starts the main
3843 instruction stream does not refer to $gp, and so will not
3844 insert the nop which may be required. */
3845 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3848 macro_build (p
, counter
, ep
, dbl
? "ld" : "lw",
3849 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3851 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3853 macro_build (p
, counter
, ep
, dbl
? "daddiu" : "addiu",
3854 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3855 if (ex
.X_add_number
!= 0)
3857 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3858 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3859 ex
.X_op
= O_constant
;
3860 macro_build ((char *) NULL
, counter
, &ex
, dbl
? "daddiu" : "addiu",
3861 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3864 else if (mips_pic
== EMBEDDED_PIC
)
3867 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3869 macro_build ((char *) NULL
, counter
, ep
, dbl
? "daddiu" : "addiu",
3870 "t,r,j", reg
, GP
, (int) BFD_RELOC_GPREL16
);
3876 /* Move the contents of register SOURCE into register DEST. */
3879 move_register (counter
, dest
, source
)
3884 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3885 HAVE_32BIT_GPRS
? "addu" : "daddu",
3886 "d,v,t", dest
, source
, 0);
3891 * This routine implements the seemingly endless macro or synthesized
3892 * instructions and addressing modes in the mips assembly language. Many
3893 * of these macros are simple and are similar to each other. These could
3894 * probably be handled by some kind of table or grammer aproach instead of
3895 * this verbose method. Others are not simple macros but are more like
3896 * optimizing code generation.
3897 * One interesting optimization is when several store macros appear
3898 * consecutivly that would load AT with the upper half of the same address.
3899 * The ensuing load upper instructions are ommited. This implies some kind
3900 * of global optimization. We currently only optimize within a single macro.
3901 * For many of the load and store macros if the address is specified as a
3902 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
3903 * first load register 'at' with zero and use it as the base register. The
3904 * mips assembler simply uses register $zero. Just one tiny optimization
3909 struct mips_cl_insn
*ip
;
3911 register int treg
, sreg
, dreg
, breg
;
3927 bfd_reloc_code_real_type r
;
3929 int hold_mips_optimize
;
3931 assert (! mips_opts
.mips16
);
3933 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
3934 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
3935 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
3936 mask
= ip
->insn_mo
->mask
;
3938 expr1
.X_op
= O_constant
;
3939 expr1
.X_op_symbol
= NULL
;
3940 expr1
.X_add_symbol
= NULL
;
3941 expr1
.X_add_number
= 1;
3953 mips_emit_delays (true);
3954 ++mips_opts
.noreorder
;
3955 mips_any_noreorder
= 1;
3957 expr1
.X_add_number
= 8;
3958 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
3960 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "",
3963 move_register (&icnt
, dreg
, sreg
);
3964 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3965 dbl
? "dsub" : "sub", "d,v,t", dreg
, 0, sreg
);
3967 --mips_opts
.noreorder
;
3988 if (imm_expr
.X_op
== O_constant
3989 && imm_expr
.X_add_number
>= -0x8000
3990 && imm_expr
.X_add_number
< 0x8000)
3992 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
3993 (int) BFD_RELOC_LO16
);
3996 load_register (&icnt
, AT
, &imm_expr
, dbl
);
3997 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s2
, "d,v,t",
4017 if (imm_expr
.X_op
== O_constant
4018 && imm_expr
.X_add_number
>= 0
4019 && imm_expr
.X_add_number
< 0x10000)
4021 if (mask
!= M_NOR_I
)
4022 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
4023 sreg
, (int) BFD_RELOC_LO16
);
4026 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
4027 treg
, sreg
, (int) BFD_RELOC_LO16
);
4028 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nor",
4029 "d,v,t", treg
, treg
, 0);
4034 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4035 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s2
, "d,v,t",
4053 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4055 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
4059 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4060 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
4068 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4069 likely
? "bgezl" : "bgez", "s,p", sreg
);
4074 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4075 likely
? "blezl" : "blez", "s,p", treg
);
4078 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "slt", "d,v,t",
4080 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4081 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4087 /* check for > max integer */
4088 maxnum
= 0x7fffffff;
4089 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4096 if (imm_expr
.X_op
== O_constant
4097 && imm_expr
.X_add_number
>= maxnum
4098 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4101 /* result is always false */
4105 as_warn (_("Branch %s is always false (nop)"),
4107 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop",
4113 as_warn (_("Branch likely %s is always false"),
4115 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
4120 if (imm_expr
.X_op
!= O_constant
)
4121 as_bad (_("Unsupported large constant"));
4122 imm_expr
.X_add_number
++;
4126 if (mask
== M_BGEL_I
)
4128 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4130 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4131 likely
? "bgezl" : "bgez", "s,p", sreg
);
4134 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4136 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4137 likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4140 maxnum
= 0x7fffffff;
4141 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4148 maxnum
= - maxnum
- 1;
4149 if (imm_expr
.X_op
== O_constant
4150 && imm_expr
.X_add_number
<= maxnum
4151 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4154 /* result is always true */
4155 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
4156 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
4159 set_at (&icnt
, sreg
, 0);
4160 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4161 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4171 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4172 likely
? "beql" : "beq", "s,t,p", 0, treg
);
4175 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
4176 "d,v,t", AT
, sreg
, treg
);
4177 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4178 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4186 && imm_expr
.X_op
== O_constant
4187 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4189 if (imm_expr
.X_op
!= O_constant
)
4190 as_bad (_("Unsupported large constant"));
4191 imm_expr
.X_add_number
++;
4195 if (mask
== M_BGEUL_I
)
4197 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4199 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4201 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4202 likely
? "bnel" : "bne", "s,t,p", sreg
, 0);
4205 set_at (&icnt
, sreg
, 1);
4206 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4207 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4215 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4216 likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4221 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4222 likely
? "bltzl" : "bltz", "s,p", treg
);
4225 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "slt", "d,v,t",
4227 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4228 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4236 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4237 likely
? "bnel" : "bne", "s,t,p", sreg
, 0);
4242 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
4243 "d,v,t", AT
, treg
, sreg
);
4244 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4245 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4253 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4254 likely
? "blezl" : "blez", "s,p", sreg
);
4259 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4260 likely
? "bgezl" : "bgez", "s,p", treg
);
4263 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "slt", "d,v,t",
4265 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4266 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4272 maxnum
= 0x7fffffff;
4273 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4280 if (imm_expr
.X_op
== O_constant
4281 && imm_expr
.X_add_number
>= maxnum
4282 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4284 if (imm_expr
.X_op
!= O_constant
)
4285 as_bad (_("Unsupported large constant"));
4286 imm_expr
.X_add_number
++;
4290 if (mask
== M_BLTL_I
)
4292 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4294 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4295 likely
? "bltzl" : "bltz", "s,p", sreg
);
4298 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4300 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4301 likely
? "blezl" : "blez", "s,p", sreg
);
4304 set_at (&icnt
, sreg
, 0);
4305 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4306 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4314 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4315 likely
? "beql" : "beq", "s,t,p", sreg
, 0);
4320 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
4321 "d,v,t", AT
, treg
, sreg
);
4322 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4323 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4331 && imm_expr
.X_op
== O_constant
4332 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4334 if (imm_expr
.X_op
!= O_constant
)
4335 as_bad (_("Unsupported large constant"));
4336 imm_expr
.X_add_number
++;
4340 if (mask
== M_BLTUL_I
)
4342 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4344 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4346 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4347 likely
? "beql" : "beq",
4351 set_at (&icnt
, sreg
, 1);
4352 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4353 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4361 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4362 likely
? "bltzl" : "bltz", "s,p", sreg
);
4367 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4368 likely
? "bgtzl" : "bgtz", "s,p", treg
);
4371 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "slt", "d,v,t",
4373 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4374 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4384 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4385 likely
? "bnel" : "bne", "s,t,p", 0, treg
);
4388 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
4391 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4392 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4407 as_warn (_("Divide by zero."));
4409 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "teq",
4412 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
4417 mips_emit_delays (true);
4418 ++mips_opts
.noreorder
;
4419 mips_any_noreorder
= 1;
4422 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "teq",
4424 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4425 dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
4429 expr1
.X_add_number
= 8;
4430 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
4431 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4432 dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
4433 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
4436 expr1
.X_add_number
= -1;
4437 macro_build ((char *) NULL
, &icnt
, &expr1
,
4438 dbl
? "daddiu" : "addiu",
4439 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
4440 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
4441 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
4444 expr1
.X_add_number
= 1;
4445 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
4446 (int) BFD_RELOC_LO16
);
4447 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsll32",
4448 "d,w,<", AT
, AT
, 31);
4452 expr1
.X_add_number
= 0x80000000;
4453 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
4454 (int) BFD_RELOC_HI16
);
4458 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "teq",
4460 /* We want to close the noreorder block as soon as possible, so
4461 that later insns are available for delay slot filling. */
4462 --mips_opts
.noreorder
;
4466 expr1
.X_add_number
= 8;
4467 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
4468 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "",
4471 /* We want to close the noreorder block as soon as possible, so
4472 that later insns are available for delay slot filling. */
4473 --mips_opts
.noreorder
;
4475 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
4478 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d", dreg
);
4517 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4519 as_warn (_("Divide by zero."));
4521 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "teq",
4524 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
4528 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4530 if (strcmp (s2
, "mflo") == 0)
4531 move_register (&icnt
, dreg
, sreg
);
4533 move_register (&icnt
, dreg
, 0);
4536 if (imm_expr
.X_op
== O_constant
4537 && imm_expr
.X_add_number
== -1
4538 && s
[strlen (s
) - 1] != 'u')
4540 if (strcmp (s2
, "mflo") == 0)
4542 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4543 dbl
? "dneg" : "neg", "d,w", dreg
, sreg
);
4546 move_register (&icnt
, dreg
, 0);
4550 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4551 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "z,s,t",
4553 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s2
, "d", dreg
);
4572 mips_emit_delays (true);
4573 ++mips_opts
.noreorder
;
4574 mips_any_noreorder
= 1;
4577 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "teq",
4579 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "z,s,t",
4581 /* We want to close the noreorder block as soon as possible, so
4582 that later insns are available for delay slot filling. */
4583 --mips_opts
.noreorder
;
4587 expr1
.X_add_number
= 8;
4588 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
4589 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "z,s,t",
4592 /* We want to close the noreorder block as soon as possible, so
4593 that later insns are available for delay slot filling. */
4594 --mips_opts
.noreorder
;
4595 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
4598 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s2
, "d", dreg
);
4604 /* Load the address of a symbol into a register. If breg is not
4605 zero, we then add a base register to it. */
4607 if (dbl
&& HAVE_32BIT_GPRS
)
4608 as_warn (_("dla used to load 32-bit register"));
4610 if (! dbl
&& HAVE_64BIT_ADDRESSES
)
4611 as_warn (_("la used to load 64-bit address"));
4624 /* When generating embedded PIC code, we permit expressions of
4627 la $treg,foo-bar($breg)
4628 where bar is an address in the current section. These are used
4629 when getting the addresses of functions. We don't permit
4630 X_add_number to be non-zero, because if the symbol is
4631 external the relaxing code needs to know that any addend is
4632 purely the offset to X_op_symbol. */
4633 if (mips_pic
== EMBEDDED_PIC
4634 && offset_expr
.X_op
== O_subtract
4635 && (symbol_constant_p (offset_expr
.X_op_symbol
)
4636 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == now_seg
4637 : (symbol_equated_p (offset_expr
.X_op_symbol
)
4639 (symbol_get_value_expression (offset_expr
.X_op_symbol
)
4642 && (offset_expr
.X_add_number
== 0
4643 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
))
4649 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4650 tempreg
, (int) BFD_RELOC_PCREL_HI16_S
);
4654 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4655 tempreg
, (int) BFD_RELOC_PCREL_HI16_S
);
4656 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4657 (dbl
|| HAVE_64BIT_ADDRESSES
) ? "daddu" : "addu",
4658 "d,v,t", tempreg
, tempreg
, breg
);
4660 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4661 (dbl
|| HAVE_64BIT_ADDRESSES
) ? "daddiu" : "addiu",
4662 "t,r,j", treg
, tempreg
, (int) BFD_RELOC_PCREL_LO16
);
4668 if (offset_expr
.X_op
!= O_symbol
4669 && offset_expr
.X_op
!= O_constant
)
4671 as_bad (_("expression too complex"));
4672 offset_expr
.X_op
= O_constant
;
4675 if (offset_expr
.X_op
== O_constant
)
4676 load_register (&icnt
, tempreg
, &offset_expr
,
4677 ((mips_pic
== EMBEDDED_PIC
|| mips_pic
== NO_PIC
)
4678 ? (dbl
|| HAVE_64BIT_ADDRESSES
)
4679 : HAVE_64BIT_ADDRESSES
));
4680 else if (mips_pic
== NO_PIC
)
4682 /* If this is a reference to a GP relative symbol, we want
4683 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
4685 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4686 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4687 If we have a constant, we need two instructions anyhow,
4688 so we may as well always use the latter form.
4690 With 64bit address space and a usable $at we want
4691 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4692 lui $at,<sym> (BFD_RELOC_HI16_S)
4693 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4694 daddiu $at,<sym> (BFD_RELOC_LO16)
4696 dadd $tempreg,$tempreg,$at
4698 If $at is already in use, we use an path which is suboptimal
4699 on superscalar processors.
4700 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4701 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4703 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
4705 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
4708 if (HAVE_64BIT_ADDRESSES
)
4710 /* We don't do GP optimization for now because RELAX_ENCODE can't
4711 hold the data for such large chunks. */
4715 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
4716 tempreg
, (int) BFD_RELOC_MIPS_HIGHEST
);
4717 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
4718 AT
, (int) BFD_RELOC_HI16_S
);
4719 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
4720 tempreg
, tempreg
, (int) BFD_RELOC_MIPS_HIGHER
);
4721 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
4722 AT
, AT
, (int) BFD_RELOC_LO16
);
4723 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll32",
4724 "d,w,<", tempreg
, tempreg
, 0);
4725 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dadd", "d,v,t",
4726 tempreg
, tempreg
, AT
);
4731 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
4732 tempreg
, (int) BFD_RELOC_MIPS_HIGHEST
);
4733 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
4734 tempreg
, tempreg
, (int) BFD_RELOC_MIPS_HIGHER
);
4735 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll", "d,w,<",
4736 tempreg
, tempreg
, 16);
4737 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
4738 tempreg
, tempreg
, (int) BFD_RELOC_HI16_S
);
4739 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll", "d,w,<",
4740 tempreg
, tempreg
, 16);
4741 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
4742 tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4747 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
4748 && ! nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4751 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "addiu",
4752 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_GPREL16
);
4753 p
= frag_var (rs_machine_dependent
, 8, 0,
4754 RELAX_ENCODE (4, 8, 0, 4, 0,
4755 mips_opts
.warn_about_macros
),
4756 offset_expr
.X_add_symbol
, 0, NULL
);
4758 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4761 macro_build (p
, &icnt
, &offset_expr
, "addiu",
4762 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4765 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
4767 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
4769 /* If this is a reference to an external symbol, and there
4770 is no constant, we want
4771 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4772 or if tempreg is PIC_CALL_REG
4773 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4774 For a local symbol, we want
4775 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4777 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4779 If we have a small constant, and this is a reference to
4780 an external symbol, we want
4781 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4783 addiu $tempreg,$tempreg,<constant>
4784 For a local symbol, we want the same instruction
4785 sequence, but we output a BFD_RELOC_LO16 reloc on the
4788 If we have a large constant, and this is a reference to
4789 an external symbol, we want
4790 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4791 lui $at,<hiconstant>
4792 addiu $at,$at,<loconstant>
4793 addu $tempreg,$tempreg,$at
4794 For a local symbol, we want the same instruction
4795 sequence, but we output a BFD_RELOC_LO16 reloc on the
4796 addiu instruction. */
4797 expr1
.X_add_number
= offset_expr
.X_add_number
;
4798 offset_expr
.X_add_number
= 0;
4800 if (expr1
.X_add_number
== 0 && tempreg
== PIC_CALL_REG
)
4801 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
4802 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4803 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
4804 "t,o(b)", tempreg
, lw_reloc_type
, GP
);
4805 if (expr1
.X_add_number
== 0)
4813 /* We're going to put in an addu instruction using
4814 tempreg, so we may as well insert the nop right
4816 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4820 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
4821 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
4823 ? mips_opts
.warn_about_macros
4825 offset_expr
.X_add_symbol
, 0, NULL
);
4828 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4831 macro_build (p
, &icnt
, &expr1
,
4832 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4833 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4834 /* FIXME: If breg == 0, and the next instruction uses
4835 $tempreg, then if this variant case is used an extra
4836 nop will be generated. */
4838 else if (expr1
.X_add_number
>= -0x8000
4839 && expr1
.X_add_number
< 0x8000)
4841 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4843 macro_build ((char *) NULL
, &icnt
, &expr1
,
4844 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4845 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4846 frag_var (rs_machine_dependent
, 0, 0,
4847 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
4848 offset_expr
.X_add_symbol
, 0, NULL
);
4854 /* If we are going to add in a base register, and the
4855 target register and the base register are the same,
4856 then we are using AT as a temporary register. Since
4857 we want to load the constant into AT, we add our
4858 current AT (from the global offset table) and the
4859 register into the register now, and pretend we were
4860 not using a base register. */
4865 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4867 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4868 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4869 "d,v,t", treg
, AT
, breg
);
4875 /* Set mips_optimize around the lui instruction to avoid
4876 inserting an unnecessary nop after the lw. */
4877 hold_mips_optimize
= mips_optimize
;
4879 macro_build_lui (NULL
, &icnt
, &expr1
, AT
);
4880 mips_optimize
= hold_mips_optimize
;
4882 macro_build ((char *) NULL
, &icnt
, &expr1
,
4883 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4884 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4885 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4886 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4887 "d,v,t", tempreg
, tempreg
, AT
);
4888 frag_var (rs_machine_dependent
, 0, 0,
4889 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
4890 offset_expr
.X_add_symbol
, 0, NULL
);
4894 else if (mips_pic
== SVR4_PIC
)
4897 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
4898 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
4900 /* This is the large GOT case. If this is a reference to an
4901 external symbol, and there is no constant, we want
4902 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4903 addu $tempreg,$tempreg,$gp
4904 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4905 or if tempreg is PIC_CALL_REG
4906 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
4907 addu $tempreg,$tempreg,$gp
4908 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
4909 For a local symbol, we want
4910 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4912 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4914 If we have a small constant, and this is a reference to
4915 an external symbol, we want
4916 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4917 addu $tempreg,$tempreg,$gp
4918 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4920 addiu $tempreg,$tempreg,<constant>
4921 For a local symbol, we want
4922 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4924 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
4926 If we have a large constant, and this is a reference to
4927 an external symbol, we want
4928 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4929 addu $tempreg,$tempreg,$gp
4930 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4931 lui $at,<hiconstant>
4932 addiu $at,$at,<loconstant>
4933 addu $tempreg,$tempreg,$at
4934 For a local symbol, we want
4935 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4936 lui $at,<hiconstant>
4937 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
4938 addu $tempreg,$tempreg,$at
4940 expr1
.X_add_number
= offset_expr
.X_add_number
;
4941 offset_expr
.X_add_number
= 0;
4943 if (reg_needs_delay (GP
))
4947 if (expr1
.X_add_number
== 0 && tempreg
== PIC_CALL_REG
)
4949 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
4950 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
4952 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4953 tempreg
, lui_reloc_type
);
4954 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4955 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4956 "d,v,t", tempreg
, tempreg
, GP
);
4957 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4958 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
4959 "t,o(b)", tempreg
, lw_reloc_type
, tempreg
);
4960 if (expr1
.X_add_number
== 0)
4968 /* We're going to put in an addu instruction using
4969 tempreg, so we may as well insert the nop right
4971 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4976 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4977 RELAX_ENCODE (12 + off
, 12 + gpdel
, gpdel
,
4980 ? mips_opts
.warn_about_macros
4982 offset_expr
.X_add_symbol
, 0, NULL
);
4984 else if (expr1
.X_add_number
>= -0x8000
4985 && expr1
.X_add_number
< 0x8000)
4987 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4989 macro_build ((char *) NULL
, &icnt
, &expr1
,
4990 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4991 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4993 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4994 RELAX_ENCODE (20, 12 + gpdel
, gpdel
, 8 + gpdel
, 0,
4996 ? mips_opts
.warn_about_macros
4998 offset_expr
.X_add_symbol
, 0, NULL
);
5004 /* If we are going to add in a base register, and the
5005 target register and the base register are the same,
5006 then we are using AT as a temporary register. Since
5007 we want to load the constant into AT, we add our
5008 current AT (from the global offset table) and the
5009 register into the register now, and pretend we were
5010 not using a base register. */
5018 assert (tempreg
== AT
);
5019 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5021 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5022 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5023 "d,v,t", treg
, AT
, breg
);
5028 /* Set mips_optimize around the lui instruction to avoid
5029 inserting an unnecessary nop after the lw. */
5030 hold_mips_optimize
= mips_optimize
;
5032 macro_build_lui (NULL
, &icnt
, &expr1
, AT
);
5033 mips_optimize
= hold_mips_optimize
;
5035 macro_build ((char *) NULL
, &icnt
, &expr1
,
5036 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5037 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
5038 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5039 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5040 "d,v,t", dreg
, dreg
, AT
);
5042 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ adj
, 0,
5043 RELAX_ENCODE (24 + adj
, 16 + gpdel
+ adj
, gpdel
,
5046 ? mips_opts
.warn_about_macros
5048 offset_expr
.X_add_symbol
, 0, NULL
);
5055 /* This is needed because this instruction uses $gp, but
5056 the first instruction on the main stream does not. */
5057 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5060 macro_build (p
, &icnt
, &offset_expr
,
5061 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5062 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5064 if (expr1
.X_add_number
>= -0x8000
5065 && expr1
.X_add_number
< 0x8000)
5067 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5069 macro_build (p
, &icnt
, &expr1
,
5070 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5071 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5072 /* FIXME: If add_number is 0, and there was no base
5073 register, the external symbol case ended with a load,
5074 so if the symbol turns out to not be external, and
5075 the next instruction uses tempreg, an unnecessary nop
5076 will be inserted. */
5082 /* We must add in the base register now, as in the
5083 external symbol case. */
5084 assert (tempreg
== AT
);
5085 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5087 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5088 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5089 "d,v,t", treg
, AT
, breg
);
5092 /* We set breg to 0 because we have arranged to add
5093 it in in both cases. */
5097 macro_build_lui (p
, &icnt
, &expr1
, AT
);
5099 macro_build (p
, &icnt
, &expr1
,
5100 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5101 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
5103 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5104 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5105 "d,v,t", tempreg
, tempreg
, AT
);
5109 else if (mips_pic
== EMBEDDED_PIC
)
5112 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
5114 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5115 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5116 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_GPREL16
);
5125 if (mips_pic
== EMBEDDED_PIC
|| mips_pic
== NO_PIC
)
5126 s
= (dbl
|| HAVE_64BIT_ADDRESSES
) ? "daddu" : "addu";
5128 s
= HAVE_64BIT_ADDRESSES
? "daddu" : "addu";
5130 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
,
5131 "d,v,t", treg
, tempreg
, breg
);
5140 /* The j instruction may not be used in PIC code, since it
5141 requires an absolute address. We convert it to a b
5143 if (mips_pic
== NO_PIC
)
5144 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
5146 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
5149 /* The jal instructions must be handled as macros because when
5150 generating PIC code they expand to multi-instruction
5151 sequences. Normally they are simple instructions. */
5156 if (mips_pic
== NO_PIC
5157 || mips_pic
== EMBEDDED_PIC
)
5158 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
5160 else if (mips_pic
== SVR4_PIC
)
5162 if (sreg
!= PIC_CALL_REG
)
5163 as_warn (_("MIPS PIC call to register other than $25"));
5165 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
5169 if (mips_cprestore_offset
< 0)
5170 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5173 if (! mips_frame_reg_valid
)
5175 as_warn (_("No .frame pseudo-op used in PIC code"));
5176 /* Quiet this warning. */
5177 mips_frame_reg_valid
= 1;
5179 if (! mips_cprestore_valid
)
5181 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5182 /* Quiet this warning. */
5183 mips_cprestore_valid
= 1;
5185 expr1
.X_add_number
= mips_cprestore_offset
;
5186 macro_build ((char *) NULL
, &icnt
, &expr1
,
5187 HAVE_32BIT_ADDRESSES
? "lw" : "ld", "t,o(b)",
5188 GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
5198 if (mips_pic
== NO_PIC
)
5199 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
5200 else if (mips_pic
== SVR4_PIC
)
5202 /* If this is a reference to an external symbol, and we are
5203 using a small GOT, we want
5204 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5208 lw $gp,cprestore($sp)
5209 The cprestore value is set using the .cprestore
5210 pseudo-op. If we are using a big GOT, we want
5211 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5213 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
5217 lw $gp,cprestore($sp)
5218 If the symbol is not external, we want
5219 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5221 addiu $25,$25,<sym> (BFD_RELOC_LO16)
5224 lw $gp,cprestore($sp) */
5228 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5229 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5230 "t,o(b)", PIC_CALL_REG
,
5231 (int) BFD_RELOC_MIPS_CALL16
, GP
);
5232 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5234 p
= frag_var (rs_machine_dependent
, 4, 0,
5235 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
5236 offset_expr
.X_add_symbol
, 0, NULL
);
5242 if (reg_needs_delay (GP
))
5246 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5247 PIC_CALL_REG
, (int) BFD_RELOC_MIPS_CALL_HI16
);
5248 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5249 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5250 "d,v,t", PIC_CALL_REG
, PIC_CALL_REG
, GP
);
5251 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5252 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5253 "t,o(b)", PIC_CALL_REG
,
5254 (int) BFD_RELOC_MIPS_CALL_LO16
, PIC_CALL_REG
);
5255 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5257 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
5258 RELAX_ENCODE (16, 12 + gpdel
, gpdel
, 8 + gpdel
,
5260 offset_expr
.X_add_symbol
, 0, NULL
);
5263 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5266 macro_build (p
, &icnt
, &offset_expr
,
5267 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5268 "t,o(b)", PIC_CALL_REG
,
5269 (int) BFD_RELOC_MIPS_GOT16
, GP
);
5271 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5274 macro_build (p
, &icnt
, &offset_expr
,
5275 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5276 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
5277 (int) BFD_RELOC_LO16
);
5278 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5279 "jalr", "s", PIC_CALL_REG
);
5282 if (mips_cprestore_offset
< 0)
5283 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5286 if (! mips_frame_reg_valid
)
5288 as_warn (_("No .frame pseudo-op used in PIC code"));
5289 /* Quiet this warning. */
5290 mips_frame_reg_valid
= 1;
5292 if (! mips_cprestore_valid
)
5294 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5295 /* Quiet this warning. */
5296 mips_cprestore_valid
= 1;
5298 if (mips_opts
.noreorder
)
5299 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5301 expr1
.X_add_number
= mips_cprestore_offset
;
5302 macro_build ((char *) NULL
, &icnt
, &expr1
,
5303 HAVE_32BIT_ADDRESSES
? "lw" : "ld", "t,o(b)",
5304 GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
5308 else if (mips_pic
== EMBEDDED_PIC
)
5310 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
5311 /* The linker may expand the call to a longer sequence which
5312 uses $at, so we must break rather than return. */
5337 /* Itbl support may require additional care here. */
5342 /* Itbl support may require additional care here. */
5347 /* Itbl support may require additional care here. */
5352 /* Itbl support may require additional care here. */
5364 if (mips_arch
== CPU_R4650
)
5366 as_bad (_("opcode not supported on this processor"));
5370 /* Itbl support may require additional care here. */
5375 /* Itbl support may require additional care here. */
5380 /* Itbl support may require additional care here. */
5400 if (breg
== treg
|| coproc
|| lr
)
5422 /* Itbl support may require additional care here. */
5427 /* Itbl support may require additional care here. */
5432 /* Itbl support may require additional care here. */
5437 /* Itbl support may require additional care here. */
5453 if (mips_arch
== CPU_R4650
)
5455 as_bad (_("opcode not supported on this processor"));
5460 /* Itbl support may require additional care here. */
5464 /* Itbl support may require additional care here. */
5469 /* Itbl support may require additional care here. */
5481 /* Itbl support may require additional care here. */
5482 if (mask
== M_LWC1_AB
5483 || mask
== M_SWC1_AB
5484 || mask
== M_LDC1_AB
5485 || mask
== M_SDC1_AB
5494 /* For embedded PIC, we allow loads where the offset is calculated
5495 by subtracting a symbol in the current segment from an unknown
5496 symbol, relative to a base register, e.g.:
5497 <op> $treg, <sym>-<localsym>($breg)
5498 This is used by the compiler for switch statements. */
5499 if (mips_pic
== EMBEDDED_PIC
5500 && offset_expr
.X_op
== O_subtract
5501 && (symbol_constant_p (offset_expr
.X_op_symbol
)
5502 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == now_seg
5503 : (symbol_equated_p (offset_expr
.X_op_symbol
)
5505 (symbol_get_value_expression (offset_expr
.X_op_symbol
)
5509 && (offset_expr
.X_add_number
== 0
5510 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
))
5512 /* For this case, we output the instructions:
5513 lui $tempreg,<sym> (BFD_RELOC_PCREL_HI16_S)
5514 addiu $tempreg,$tempreg,$breg
5515 <op> $treg,<sym>($tempreg) (BFD_RELOC_PCREL_LO16)
5516 If the relocation would fit entirely in 16 bits, it would be
5518 <op> $treg,<sym>($breg) (BFD_RELOC_PCREL_LO16)
5519 instead, but that seems quite difficult. */
5520 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5521 tempreg
, (int) BFD_RELOC_PCREL_HI16_S
);
5522 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5523 ((bfd_arch_bits_per_address (stdoutput
) == 32
5524 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5525 ? "addu" : "daddu"),
5526 "d,v,t", tempreg
, tempreg
, breg
);
5527 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
, treg
,
5528 (int) BFD_RELOC_PCREL_LO16
, tempreg
);
5534 if (offset_expr
.X_op
!= O_constant
5535 && offset_expr
.X_op
!= O_symbol
)
5537 as_bad (_("expression too complex"));
5538 offset_expr
.X_op
= O_constant
;
5541 /* A constant expression in PIC code can be handled just as it
5542 is in non PIC code. */
5543 if (mips_pic
== NO_PIC
5544 || offset_expr
.X_op
== O_constant
)
5546 /* If this is a reference to a GP relative symbol, and there
5547 is no base register, we want
5548 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
5549 Otherwise, if there is no base register, we want
5550 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5551 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5552 If we have a constant, we need two instructions anyhow,
5553 so we always use the latter form.
5555 If we have a base register, and this is a reference to a
5556 GP relative symbol, we want
5557 addu $tempreg,$breg,$gp
5558 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
5560 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5561 addu $tempreg,$tempreg,$breg
5562 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5563 With a constant we always use the latter case.
5565 With 64bit address space and no base register and $at usable,
5567 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5568 lui $at,<sym> (BFD_RELOC_HI16_S)
5569 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5572 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5573 If we have a base register, we want
5574 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5575 lui $at,<sym> (BFD_RELOC_HI16_S)
5576 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5580 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5582 Without $at we can't generate the optimal path for superscalar
5583 processors here since this would require two temporary registers.
5584 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5585 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5587 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5589 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5590 If we have a base register, we want
5591 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5592 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5594 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5596 daddu $tempreg,$tempreg,$breg
5597 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5599 If we have 64-bit addresses, as an optimization, for
5600 addresses which are 32-bit constants (e.g. kseg0/kseg1
5601 addresses) we fall back to the 32-bit address generation
5602 mechanism since it is more efficient. This code should
5603 probably attempt to generate 64-bit constants more
5604 efficiently in general.
5606 if (HAVE_64BIT_ADDRESSES
5607 && !(offset_expr
.X_op
== O_constant
5608 && IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
)))
5612 /* We don't do GP optimization for now because RELAX_ENCODE can't
5613 hold the data for such large chunks. */
5617 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
5618 tempreg
, (int) BFD_RELOC_MIPS_HIGHEST
);
5619 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
5620 AT
, (int) BFD_RELOC_HI16_S
);
5621 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
5622 tempreg
, tempreg
, (int) BFD_RELOC_MIPS_HIGHER
);
5624 macro_build (p
, &icnt
, (expressionS
*) NULL
, "daddu",
5625 "d,v,t", AT
, AT
, breg
);
5626 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll32",
5627 "d,w,<", tempreg
, tempreg
, 0);
5628 macro_build (p
, &icnt
, (expressionS
*) NULL
, "daddu",
5629 "d,v,t", tempreg
, tempreg
, AT
);
5630 macro_build (p
, &icnt
, &offset_expr
, s
,
5631 fmt
, treg
, (int) BFD_RELOC_LO16
, tempreg
);
5636 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
5637 tempreg
, (int) BFD_RELOC_MIPS_HIGHEST
);
5638 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
5639 tempreg
, tempreg
, (int) BFD_RELOC_MIPS_HIGHER
);
5640 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll",
5641 "d,w,<", tempreg
, tempreg
, 16);
5642 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
5643 tempreg
, tempreg
, (int) BFD_RELOC_HI16_S
);
5644 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll",
5645 "d,w,<", tempreg
, tempreg
, 16);
5647 macro_build (p
, &icnt
, (expressionS
*) NULL
, "daddu",
5648 "d,v,t", tempreg
, tempreg
, breg
);
5649 macro_build (p
, &icnt
, &offset_expr
, s
,
5650 fmt
, treg
, (int) BFD_RELOC_LO16
, tempreg
);
5658 if ((valueT
) offset_expr
.X_add_number
> MAX_GPREL_OFFSET
5659 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5664 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5665 treg
, (int) BFD_RELOC_GPREL16
, GP
);
5666 p
= frag_var (rs_machine_dependent
, 8, 0,
5667 RELAX_ENCODE (4, 8, 0, 4, 0,
5668 (mips_opts
.warn_about_macros
5670 && mips_opts
.noat
))),
5671 offset_expr
.X_add_symbol
, 0, NULL
);
5674 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
5677 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
5678 (int) BFD_RELOC_LO16
, tempreg
);
5682 if ((valueT
) offset_expr
.X_add_number
> MAX_GPREL_OFFSET
5683 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5688 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5689 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5690 "d,v,t", tempreg
, breg
, GP
);
5691 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5692 treg
, (int) BFD_RELOC_GPREL16
, tempreg
);
5693 p
= frag_var (rs_machine_dependent
, 12, 0,
5694 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
5695 offset_expr
.X_add_symbol
, 0, NULL
);
5697 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
5700 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5701 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5702 "d,v,t", tempreg
, tempreg
, breg
);
5705 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
5706 (int) BFD_RELOC_LO16
, tempreg
);
5709 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
5711 /* If this is a reference to an external symbol, we want
5712 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5714 <op> $treg,0($tempreg)
5716 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5718 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5719 <op> $treg,0($tempreg)
5720 If there is a base register, we add it to $tempreg before
5721 the <op>. If there is a constant, we stick it in the
5722 <op> instruction. We don't handle constants larger than
5723 16 bits, because we have no way to load the upper 16 bits
5724 (actually, we could handle them for the subset of cases
5725 in which we are not using $at). */
5726 assert (offset_expr
.X_op
== O_symbol
);
5727 expr1
.X_add_number
= offset_expr
.X_add_number
;
5728 offset_expr
.X_add_number
= 0;
5729 if (expr1
.X_add_number
< -0x8000
5730 || expr1
.X_add_number
>= 0x8000)
5731 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5733 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5734 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5735 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5736 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5737 p
= frag_var (rs_machine_dependent
, 4, 0,
5738 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
5739 offset_expr
.X_add_symbol
, 0, NULL
);
5740 macro_build (p
, &icnt
, &offset_expr
,
5741 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5742 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5744 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5745 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5746 "d,v,t", tempreg
, tempreg
, breg
);
5747 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
5748 (int) BFD_RELOC_LO16
, tempreg
);
5750 else if (mips_pic
== SVR4_PIC
)
5754 /* If this is a reference to an external symbol, we want
5755 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5756 addu $tempreg,$tempreg,$gp
5757 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5758 <op> $treg,0($tempreg)
5760 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5762 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5763 <op> $treg,0($tempreg)
5764 If there is a base register, we add it to $tempreg before
5765 the <op>. If there is a constant, we stick it in the
5766 <op> instruction. We don't handle constants larger than
5767 16 bits, because we have no way to load the upper 16 bits
5768 (actually, we could handle them for the subset of cases
5769 in which we are not using $at). */
5770 assert (offset_expr
.X_op
== O_symbol
);
5771 expr1
.X_add_number
= offset_expr
.X_add_number
;
5772 offset_expr
.X_add_number
= 0;
5773 if (expr1
.X_add_number
< -0x8000
5774 || expr1
.X_add_number
>= 0x8000)
5775 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5776 if (reg_needs_delay (GP
))
5781 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5782 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
5783 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5784 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5785 "d,v,t", tempreg
, tempreg
, GP
);
5786 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5787 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5788 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
5790 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
5791 RELAX_ENCODE (12, 12 + gpdel
, gpdel
, 8 + gpdel
, 0, 0),
5792 offset_expr
.X_add_symbol
, 0, NULL
);
5795 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5798 macro_build (p
, &icnt
, &offset_expr
,
5799 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5800 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5802 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5804 macro_build (p
, &icnt
, &offset_expr
,
5805 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5806 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5808 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5809 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5810 "d,v,t", tempreg
, tempreg
, breg
);
5811 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
5812 (int) BFD_RELOC_LO16
, tempreg
);
5814 else if (mips_pic
== EMBEDDED_PIC
)
5816 /* If there is no base register, we want
5817 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
5818 If there is a base register, we want
5819 addu $tempreg,$breg,$gp
5820 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
5822 assert (offset_expr
.X_op
== O_symbol
);
5825 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5826 treg
, (int) BFD_RELOC_GPREL16
, GP
);
5831 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5832 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5833 "d,v,t", tempreg
, breg
, GP
);
5834 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5835 treg
, (int) BFD_RELOC_GPREL16
, tempreg
);
5848 load_register (&icnt
, treg
, &imm_expr
, 0);
5852 load_register (&icnt
, treg
, &imm_expr
, 1);
5856 if (imm_expr
.X_op
== O_constant
)
5858 load_register (&icnt
, AT
, &imm_expr
, 0);
5859 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5860 "mtc1", "t,G", AT
, treg
);
5865 assert (offset_expr
.X_op
== O_symbol
5866 && strcmp (segment_name (S_GET_SEGMENT
5867 (offset_expr
.X_add_symbol
)),
5869 && offset_expr
.X_add_number
== 0);
5870 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5871 treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
5876 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
5877 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
5878 order 32 bits of the value and the low order 32 bits are either
5879 zero or in OFFSET_EXPR. */
5880 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
5882 if (HAVE_64BIT_GPRS
)
5883 load_register (&icnt
, treg
, &imm_expr
, 1);
5888 if (target_big_endian
)
5900 load_register (&icnt
, hreg
, &imm_expr
, 0);
5903 if (offset_expr
.X_op
== O_absent
)
5904 move_register (&icnt
, lreg
, 0);
5907 assert (offset_expr
.X_op
== O_constant
);
5908 load_register (&icnt
, lreg
, &offset_expr
, 0);
5915 /* We know that sym is in the .rdata section. First we get the
5916 upper 16 bits of the address. */
5917 if (mips_pic
== NO_PIC
)
5919 macro_build_lui (NULL
, &icnt
, &offset_expr
, AT
);
5921 else if (mips_pic
== SVR4_PIC
)
5923 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5924 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5925 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5927 else if (mips_pic
== EMBEDDED_PIC
)
5929 /* For embedded PIC we pick up the entire address off $gp in
5930 a single instruction. */
5931 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5932 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5933 "t,r,j", AT
, GP
, (int) BFD_RELOC_GPREL16
);
5934 offset_expr
.X_op
= O_constant
;
5935 offset_expr
.X_add_number
= 0;
5940 /* Now we load the register(s). */
5941 if (HAVE_64BIT_GPRS
)
5942 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
5943 treg
, (int) BFD_RELOC_LO16
, AT
);
5946 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
5947 treg
, (int) BFD_RELOC_LO16
, AT
);
5950 /* FIXME: How in the world do we deal with the possible
5952 offset_expr
.X_add_number
+= 4;
5953 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
5954 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
5958 /* To avoid confusion in tc_gen_reloc, we must ensure that this
5959 does not become a variant frag. */
5960 frag_wane (frag_now
);
5966 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
5967 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
5968 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
5969 the value and the low order 32 bits are either zero or in
5971 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
5973 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_FPRS
);
5974 if (HAVE_64BIT_FPRS
)
5976 assert (HAVE_64BIT_GPRS
);
5977 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5978 "dmtc1", "t,S", AT
, treg
);
5982 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5983 "mtc1", "t,G", AT
, treg
+ 1);
5984 if (offset_expr
.X_op
== O_absent
)
5985 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5986 "mtc1", "t,G", 0, treg
);
5989 assert (offset_expr
.X_op
== O_constant
);
5990 load_register (&icnt
, AT
, &offset_expr
, 0);
5991 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5992 "mtc1", "t,G", AT
, treg
);
5998 assert (offset_expr
.X_op
== O_symbol
5999 && offset_expr
.X_add_number
== 0);
6000 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
6001 if (strcmp (s
, ".lit8") == 0)
6003 if (mips_opts
.isa
!= ISA_MIPS1
)
6005 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
6006 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
6010 r
= BFD_RELOC_MIPS_LITERAL
;
6015 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
6016 if (mips_pic
== SVR4_PIC
)
6017 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
6018 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
6019 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
6022 /* FIXME: This won't work for a 64 bit address. */
6023 macro_build_lui (NULL
, &icnt
, &offset_expr
, AT
);
6026 if (mips_opts
.isa
!= ISA_MIPS1
)
6028 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
6029 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, AT
);
6031 /* To avoid confusion in tc_gen_reloc, we must ensure
6032 that this does not become a variant frag. */
6033 frag_wane (frag_now
);
6044 if (mips_arch
== CPU_R4650
)
6046 as_bad (_("opcode not supported on this processor"));
6049 /* Even on a big endian machine $fn comes before $fn+1. We have
6050 to adjust when loading from memory. */
6053 assert (mips_opts
.isa
== ISA_MIPS1
);
6054 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
6055 target_big_endian
? treg
+ 1 : treg
,
6057 /* FIXME: A possible overflow which I don't know how to deal
6059 offset_expr
.X_add_number
+= 4;
6060 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
6061 target_big_endian
? treg
: treg
+ 1,
6064 /* To avoid confusion in tc_gen_reloc, we must ensure that this
6065 does not become a variant frag. */
6066 frag_wane (frag_now
);
6075 * The MIPS assembler seems to check for X_add_number not
6076 * being double aligned and generating:
6079 * addiu at,at,%lo(foo+1)
6082 * But, the resulting address is the same after relocation so why
6083 * generate the extra instruction?
6085 if (mips_arch
== CPU_R4650
)
6087 as_bad (_("opcode not supported on this processor"));
6090 /* Itbl support may require additional care here. */
6092 if (mips_opts
.isa
!= ISA_MIPS1
)
6103 if (mips_arch
== CPU_R4650
)
6105 as_bad (_("opcode not supported on this processor"));
6109 if (mips_opts
.isa
!= ISA_MIPS1
)
6117 /* Itbl support may require additional care here. */
6122 if (HAVE_64BIT_GPRS
)
6133 if (HAVE_64BIT_GPRS
)
6143 /* We do _not_ bother to allow embedded PIC (symbol-local_symbol)
6144 loads for the case of doing a pair of loads to simulate an 'ld'.
6145 This is not currently done by the compiler, and assembly coders
6146 writing embedded-pic code can cope. */
6148 if (offset_expr
.X_op
!= O_symbol
6149 && offset_expr
.X_op
!= O_constant
)
6151 as_bad (_("expression too complex"));
6152 offset_expr
.X_op
= O_constant
;
6155 /* Even on a big endian machine $fn comes before $fn+1. We have
6156 to adjust when loading from memory. We set coproc if we must
6157 load $fn+1 first. */
6158 /* Itbl support may require additional care here. */
6159 if (! target_big_endian
)
6162 if (mips_pic
== NO_PIC
6163 || offset_expr
.X_op
== O_constant
)
6165 /* If this is a reference to a GP relative symbol, we want
6166 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6167 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6168 If we have a base register, we use this
6170 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6171 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6172 If this is not a GP relative symbol, we want
6173 lui $at,<sym> (BFD_RELOC_HI16_S)
6174 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6175 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6176 If there is a base register, we add it to $at after the
6177 lui instruction. If there is a constant, we always use
6179 if ((valueT
) offset_expr
.X_add_number
> MAX_GPREL_OFFSET
6180 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6199 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6200 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6201 "d,v,t", AT
, breg
, GP
);
6207 /* Itbl support may require additional care here. */
6208 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
6209 coproc
? treg
+ 1 : treg
,
6210 (int) BFD_RELOC_GPREL16
, tempreg
);
6211 offset_expr
.X_add_number
+= 4;
6213 /* Set mips_optimize to 2 to avoid inserting an
6215 hold_mips_optimize
= mips_optimize
;
6217 /* Itbl support may require additional care here. */
6218 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
6219 coproc
? treg
: treg
+ 1,
6220 (int) BFD_RELOC_GPREL16
, tempreg
);
6221 mips_optimize
= hold_mips_optimize
;
6223 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
6224 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
6225 used_at
&& mips_opts
.noat
),
6226 offset_expr
.X_add_symbol
, 0, NULL
);
6228 /* We just generated two relocs. When tc_gen_reloc
6229 handles this case, it will skip the first reloc and
6230 handle the second. The second reloc already has an
6231 extra addend of 4, which we added above. We must
6232 subtract it out, and then subtract another 4 to make
6233 the first reloc come out right. The second reloc
6234 will come out right because we are going to add 4 to
6235 offset_expr when we build its instruction below.
6237 If we have a symbol, then we don't want to include
6238 the offset, because it will wind up being included
6239 when we generate the reloc. */
6241 if (offset_expr
.X_op
== O_constant
)
6242 offset_expr
.X_add_number
-= 8;
6245 offset_expr
.X_add_number
= -4;
6246 offset_expr
.X_op
= O_constant
;
6249 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
6254 macro_build (p
, &icnt
, (expressionS
*) NULL
,
6255 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6256 "d,v,t", AT
, breg
, AT
);
6260 /* Itbl support may require additional care here. */
6261 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
6262 coproc
? treg
+ 1 : treg
,
6263 (int) BFD_RELOC_LO16
, AT
);
6266 /* FIXME: How do we handle overflow here? */
6267 offset_expr
.X_add_number
+= 4;
6268 /* Itbl support may require additional care here. */
6269 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
6270 coproc
? treg
: treg
+ 1,
6271 (int) BFD_RELOC_LO16
, AT
);
6273 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
6277 /* If this is a reference to an external symbol, we want
6278 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6283 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6285 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6286 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6287 If there is a base register we add it to $at before the
6288 lwc1 instructions. If there is a constant we include it
6289 in the lwc1 instructions. */
6291 expr1
.X_add_number
= offset_expr
.X_add_number
;
6292 offset_expr
.X_add_number
= 0;
6293 if (expr1
.X_add_number
< -0x8000
6294 || expr1
.X_add_number
>= 0x8000 - 4)
6295 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6300 frag_grow (24 + off
);
6301 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
6302 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
6303 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
6304 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
6306 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6307 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6308 "d,v,t", AT
, breg
, AT
);
6309 /* Itbl support may require additional care here. */
6310 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
6311 coproc
? treg
+ 1 : treg
,
6312 (int) BFD_RELOC_LO16
, AT
);
6313 expr1
.X_add_number
+= 4;
6315 /* Set mips_optimize to 2 to avoid inserting an undesired
6317 hold_mips_optimize
= mips_optimize
;
6319 /* Itbl support may require additional care here. */
6320 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
6321 coproc
? treg
: treg
+ 1,
6322 (int) BFD_RELOC_LO16
, AT
);
6323 mips_optimize
= hold_mips_optimize
;
6325 (void) frag_var (rs_machine_dependent
, 0, 0,
6326 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
6327 offset_expr
.X_add_symbol
, 0, NULL
);
6329 else if (mips_pic
== SVR4_PIC
)
6333 /* If this is a reference to an external symbol, we want
6334 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6336 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
6341 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6343 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6344 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6345 If there is a base register we add it to $at before the
6346 lwc1 instructions. If there is a constant we include it
6347 in the lwc1 instructions. */
6349 expr1
.X_add_number
= offset_expr
.X_add_number
;
6350 offset_expr
.X_add_number
= 0;
6351 if (expr1
.X_add_number
< -0x8000
6352 || expr1
.X_add_number
>= 0x8000 - 4)
6353 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6354 if (reg_needs_delay (GP
))
6363 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
6364 AT
, (int) BFD_RELOC_MIPS_GOT_HI16
);
6365 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6366 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6367 "d,v,t", AT
, AT
, GP
);
6368 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
6369 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
6370 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT_LO16
, AT
);
6371 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
6373 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6374 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6375 "d,v,t", AT
, breg
, AT
);
6376 /* Itbl support may require additional care here. */
6377 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
6378 coproc
? treg
+ 1 : treg
,
6379 (int) BFD_RELOC_LO16
, AT
);
6380 expr1
.X_add_number
+= 4;
6382 /* Set mips_optimize to 2 to avoid inserting an undesired
6384 hold_mips_optimize
= mips_optimize
;
6386 /* Itbl support may require additional care here. */
6387 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
6388 coproc
? treg
: treg
+ 1,
6389 (int) BFD_RELOC_LO16
, AT
);
6390 mips_optimize
= hold_mips_optimize
;
6391 expr1
.X_add_number
-= 4;
6393 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ off
, 0,
6394 RELAX_ENCODE (24 + off
, 16 + gpdel
+ off
, gpdel
,
6395 8 + gpdel
+ off
, 1, 0),
6396 offset_expr
.X_add_symbol
, 0, NULL
);
6399 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
6402 macro_build (p
, &icnt
, &offset_expr
,
6403 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
6404 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
6406 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
6410 macro_build (p
, &icnt
, (expressionS
*) NULL
,
6411 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6412 "d,v,t", AT
, breg
, AT
);
6415 /* Itbl support may require additional care here. */
6416 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
6417 coproc
? treg
+ 1 : treg
,
6418 (int) BFD_RELOC_LO16
, AT
);
6420 expr1
.X_add_number
+= 4;
6422 /* Set mips_optimize to 2 to avoid inserting an undesired
6424 hold_mips_optimize
= mips_optimize
;
6426 /* Itbl support may require additional care here. */
6427 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
6428 coproc
? treg
: treg
+ 1,
6429 (int) BFD_RELOC_LO16
, AT
);
6430 mips_optimize
= hold_mips_optimize
;
6432 else if (mips_pic
== EMBEDDED_PIC
)
6434 /* If there is no base register, we use
6435 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6436 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6437 If we have a base register, we use
6439 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6440 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6449 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6450 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6451 "d,v,t", AT
, breg
, GP
);
6456 /* Itbl support may require additional care here. */
6457 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
6458 coproc
? treg
+ 1 : treg
,
6459 (int) BFD_RELOC_GPREL16
, tempreg
);
6460 offset_expr
.X_add_number
+= 4;
6461 /* Itbl support may require additional care here. */
6462 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
6463 coproc
? treg
: treg
+ 1,
6464 (int) BFD_RELOC_GPREL16
, tempreg
);
6480 assert (HAVE_32BIT_ADDRESSES
);
6481 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6482 (int) BFD_RELOC_LO16
, breg
);
6483 offset_expr
.X_add_number
+= 4;
6484 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
6485 (int) BFD_RELOC_LO16
, breg
);
6488 /* New code added to support COPZ instructions.
6489 This code builds table entries out of the macros in mip_opcodes.
6490 R4000 uses interlocks to handle coproc delays.
6491 Other chips (like the R3000) require nops to be inserted for delays.
6493 FIXME: Currently, we require that the user handle delays.
6494 In order to fill delay slots for non-interlocked chips,
6495 we must have a way to specify delays based on the coprocessor.
6496 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
6497 What are the side-effects of the cop instruction?
6498 What cache support might we have and what are its effects?
6499 Both coprocessor & memory require delays. how long???
6500 What registers are read/set/modified?
6502 If an itbl is provided to interpret cop instructions,
6503 this knowledge can be encoded in the itbl spec. */
6517 /* For now we just do C (same as Cz). The parameter will be
6518 stored in insn_opcode by mips_ip. */
6519 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "C",
6524 move_register (&icnt
, dreg
, sreg
);
6527 #ifdef LOSING_COMPILER
6529 /* Try and see if this is a new itbl instruction.
6530 This code builds table entries out of the macros in mip_opcodes.
6531 FIXME: For now we just assemble the expression and pass it's
6532 value along as a 32-bit immediate.
6533 We may want to have the assembler assemble this value,
6534 so that we gain the assembler's knowledge of delay slots,
6536 Would it be more efficient to use mask (id) here? */
6537 if (itbl_have_entries
6538 && (immed_expr
= itbl_assemble (ip
->insn_mo
->name
, "")))
6540 s
= ip
->insn_mo
->name
;
6542 coproc
= ITBL_DECODE_PNUM (immed_expr
);;
6543 macro_build ((char *) NULL
, &icnt
, &immed_expr
, s
, "C");
6550 as_warn (_("Macro used $at after \".set noat\""));
6555 struct mips_cl_insn
*ip
;
6557 register int treg
, sreg
, dreg
, breg
;
6573 bfd_reloc_code_real_type r
;
6576 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
6577 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
6578 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
6579 mask
= ip
->insn_mo
->mask
;
6581 expr1
.X_op
= O_constant
;
6582 expr1
.X_op_symbol
= NULL
;
6583 expr1
.X_add_symbol
= NULL
;
6584 expr1
.X_add_number
= 1;
6588 #endif /* LOSING_COMPILER */
6593 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6594 dbl
? "dmultu" : "multu", "s,t", sreg
, treg
);
6595 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "d",
6602 /* The MIPS assembler some times generates shifts and adds. I'm
6603 not trying to be that fancy. GCC should do this for us
6605 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6606 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6607 dbl
? "dmult" : "mult", "s,t", sreg
, AT
);
6608 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "d",
6622 mips_emit_delays (true);
6623 ++mips_opts
.noreorder
;
6624 mips_any_noreorder
= 1;
6626 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6627 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6628 dbl
? "dmult" : "mult", "s,t", sreg
, imm
? AT
: treg
);
6629 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "d",
6631 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6632 dbl
? "dsra32" : "sra", "d,w,<", dreg
, dreg
, 31);
6633 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mfhi", "d",
6636 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "tne", "s,t",
6640 expr1
.X_add_number
= 8;
6641 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
,
6643 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "",
6645 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
6648 --mips_opts
.noreorder
;
6649 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "d", dreg
);
6662 mips_emit_delays (true);
6663 ++mips_opts
.noreorder
;
6664 mips_any_noreorder
= 1;
6666 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6667 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6668 dbl
? "dmultu" : "multu",
6669 "s,t", sreg
, imm
? AT
: treg
);
6670 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mfhi", "d",
6672 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "d",
6675 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "tne", "s,t",
6679 expr1
.X_add_number
= 8;
6680 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
6681 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "",
6683 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
6686 --mips_opts
.noreorder
;
6690 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "subu",
6691 "d,v,t", AT
, 0, treg
);
6692 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srlv",
6693 "d,t,s", AT
, sreg
, AT
);
6694 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sllv",
6695 "d,t,s", dreg
, sreg
, treg
);
6696 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
6697 "d,v,t", dreg
, dreg
, AT
);
6701 if (imm_expr
.X_op
!= O_constant
)
6702 as_bad (_("rotate count too large"));
6703 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sll", "d,w,<",
6704 AT
, sreg
, (int) (imm_expr
.X_add_number
& 0x1f));
6705 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srl", "d,w,<",
6706 dreg
, sreg
, (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
6707 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or", "d,v,t",
6712 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "subu",
6713 "d,v,t", AT
, 0, treg
);
6714 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sllv",
6715 "d,t,s", AT
, sreg
, AT
);
6716 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srlv",
6717 "d,t,s", dreg
, sreg
, treg
);
6718 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
6719 "d,v,t", dreg
, dreg
, AT
);
6723 if (imm_expr
.X_op
!= O_constant
)
6724 as_bad (_("rotate count too large"));
6725 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srl", "d,w,<",
6726 AT
, sreg
, (int) (imm_expr
.X_add_number
& 0x1f));
6727 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sll", "d,w,<",
6728 dreg
, sreg
, (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
6729 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or", "d,v,t",
6734 if (mips_arch
== CPU_R4650
)
6736 as_bad (_("opcode not supported on this processor"));
6739 assert (mips_opts
.isa
== ISA_MIPS1
);
6740 /* Even on a big endian machine $fn comes before $fn+1. We have
6741 to adjust when storing to memory. */
6742 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
6743 target_big_endian
? treg
+ 1 : treg
,
6744 (int) BFD_RELOC_LO16
, breg
);
6745 offset_expr
.X_add_number
+= 4;
6746 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
6747 target_big_endian
? treg
: treg
+ 1,
6748 (int) BFD_RELOC_LO16
, breg
);
6753 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6754 treg
, (int) BFD_RELOC_LO16
);
6756 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6757 sreg
, (int) BFD_RELOC_LO16
);
6760 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "xor",
6761 "d,v,t", dreg
, sreg
, treg
);
6762 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6763 dreg
, (int) BFD_RELOC_LO16
);
6768 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6770 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6771 sreg
, (int) BFD_RELOC_LO16
);
6776 as_warn (_("Instruction %s: result is always false"),
6778 move_register (&icnt
, dreg
, 0);
6781 if (imm_expr
.X_op
== O_constant
6782 && imm_expr
.X_add_number
>= 0
6783 && imm_expr
.X_add_number
< 0x10000)
6785 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
6786 sreg
, (int) BFD_RELOC_LO16
);
6789 else if (imm_expr
.X_op
== O_constant
6790 && imm_expr
.X_add_number
> -0x8000
6791 && imm_expr
.X_add_number
< 0)
6793 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6794 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6795 HAVE_32BIT_GPRS
? "addiu" : "daddiu",
6796 "t,r,j", dreg
, sreg
,
6797 (int) BFD_RELOC_LO16
);
6802 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
6803 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "xor",
6804 "d,v,t", dreg
, sreg
, AT
);
6807 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
6808 (int) BFD_RELOC_LO16
);
6813 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
6819 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d,v,t",
6821 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6822 (int) BFD_RELOC_LO16
);
6825 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
6827 if (imm_expr
.X_op
== O_constant
6828 && imm_expr
.X_add_number
>= -0x8000
6829 && imm_expr
.X_add_number
< 0x8000)
6831 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6832 mask
== M_SGE_I
? "slti" : "sltiu",
6833 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6838 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
6839 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6840 mask
== M_SGE_I
? "slt" : "sltu", "d,v,t", dreg
, sreg
,
6844 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6845 (int) BFD_RELOC_LO16
);
6850 case M_SGT
: /* sreg > treg <==> treg < sreg */
6856 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d,v,t",
6860 case M_SGT_I
: /* sreg > I <==> I < sreg */
6866 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
6867 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d,v,t",
6871 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
6877 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d,v,t",
6879 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6880 (int) BFD_RELOC_LO16
);
6883 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
6889 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
6890 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d,v,t",
6892 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6893 (int) BFD_RELOC_LO16
);
6897 if (imm_expr
.X_op
== O_constant
6898 && imm_expr
.X_add_number
>= -0x8000
6899 && imm_expr
.X_add_number
< 0x8000)
6901 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
6902 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6905 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
6906 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "slt", "d,v,t",
6911 if (imm_expr
.X_op
== O_constant
6912 && imm_expr
.X_add_number
>= -0x8000
6913 && imm_expr
.X_add_number
< 0x8000)
6915 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
6916 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6919 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
6920 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
6921 "d,v,t", dreg
, sreg
, AT
);
6926 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
6927 "d,v,t", dreg
, 0, treg
);
6929 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
6930 "d,v,t", dreg
, 0, sreg
);
6933 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "xor",
6934 "d,v,t", dreg
, sreg
, treg
);
6935 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
6936 "d,v,t", dreg
, 0, dreg
);
6941 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6943 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
6944 "d,v,t", dreg
, 0, sreg
);
6949 as_warn (_("Instruction %s: result is always true"),
6951 macro_build ((char *) NULL
, &icnt
, &expr1
,
6952 HAVE_32BIT_GPRS
? "addiu" : "daddiu",
6953 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
6956 if (imm_expr
.X_op
== O_constant
6957 && imm_expr
.X_add_number
>= 0
6958 && imm_expr
.X_add_number
< 0x10000)
6960 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
6961 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6964 else if (imm_expr
.X_op
== O_constant
6965 && imm_expr
.X_add_number
> -0x8000
6966 && imm_expr
.X_add_number
< 0)
6968 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6969 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6970 HAVE_32BIT_GPRS
? "addiu" : "daddiu",
6971 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6976 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
6977 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "xor",
6978 "d,v,t", dreg
, sreg
, AT
);
6981 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
6982 "d,v,t", dreg
, 0, dreg
);
6990 if (imm_expr
.X_op
== O_constant
6991 && imm_expr
.X_add_number
> -0x8000
6992 && imm_expr
.X_add_number
<= 0x8000)
6994 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6995 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6996 dbl
? "daddi" : "addi",
6997 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
7000 load_register (&icnt
, AT
, &imm_expr
, dbl
);
7001 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7002 dbl
? "dsub" : "sub", "d,v,t", dreg
, sreg
, AT
);
7008 if (imm_expr
.X_op
== O_constant
7009 && imm_expr
.X_add_number
> -0x8000
7010 && imm_expr
.X_add_number
<= 0x8000)
7012 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7013 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
7014 dbl
? "daddiu" : "addiu",
7015 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
7018 load_register (&icnt
, AT
, &imm_expr
, dbl
);
7019 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7020 dbl
? "dsubu" : "subu", "d,v,t", dreg
, sreg
, AT
);
7041 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7042 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "s,t", sreg
,
7048 assert (mips_opts
.isa
== ISA_MIPS1
);
7049 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
7050 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
7053 * Is the double cfc1 instruction a bug in the mips assembler;
7054 * or is there a reason for it?
7056 mips_emit_delays (true);
7057 ++mips_opts
.noreorder
;
7058 mips_any_noreorder
= 1;
7059 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "cfc1", "t,G",
7061 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "cfc1", "t,G",
7063 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
7064 expr1
.X_add_number
= 3;
7065 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
7066 (int) BFD_RELOC_LO16
);
7067 expr1
.X_add_number
= 2;
7068 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
7069 (int) BFD_RELOC_LO16
);
7070 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "ctc1", "t,G",
7072 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
7073 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7074 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
7075 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "ctc1", "t,G",
7077 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
7078 --mips_opts
.noreorder
;
7087 if (offset_expr
.X_add_number
>= 0x7fff)
7088 as_bad (_("operand overflow"));
7089 /* avoid load delay */
7090 if (! target_big_endian
)
7091 offset_expr
.X_add_number
+= 1;
7092 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
7093 (int) BFD_RELOC_LO16
, breg
);
7094 if (! target_big_endian
)
7095 offset_expr
.X_add_number
-= 1;
7097 offset_expr
.X_add_number
+= 1;
7098 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
7099 (int) BFD_RELOC_LO16
, breg
);
7100 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sll", "d,w,<",
7102 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or", "d,v,t",
7116 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7117 as_bad (_("operand overflow"));
7118 if (! target_big_endian
)
7119 offset_expr
.X_add_number
+= off
;
7120 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
7121 (int) BFD_RELOC_LO16
, breg
);
7122 if (! target_big_endian
)
7123 offset_expr
.X_add_number
-= off
;
7125 offset_expr
.X_add_number
+= off
;
7126 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
7127 (int) BFD_RELOC_LO16
, breg
);
7141 load_address (&icnt
, AT
, &offset_expr
, HAVE_64BIT_ADDRESSES
, &used_at
);
7143 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7144 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
7145 "d,v,t", AT
, AT
, breg
);
7146 if (! target_big_endian
)
7147 expr1
.X_add_number
= off
;
7149 expr1
.X_add_number
= 0;
7150 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
7151 (int) BFD_RELOC_LO16
, AT
);
7152 if (! target_big_endian
)
7153 expr1
.X_add_number
= 0;
7155 expr1
.X_add_number
= off
;
7156 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
7157 (int) BFD_RELOC_LO16
, AT
);
7163 load_address (&icnt
, AT
, &offset_expr
, HAVE_64BIT_ADDRESSES
, &used_at
);
7165 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7166 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
7167 "d,v,t", AT
, AT
, breg
);
7168 if (target_big_endian
)
7169 expr1
.X_add_number
= 0;
7170 macro_build ((char *) NULL
, &icnt
, &expr1
,
7171 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
7172 (int) BFD_RELOC_LO16
, AT
);
7173 if (target_big_endian
)
7174 expr1
.X_add_number
= 1;
7176 expr1
.X_add_number
= 0;
7177 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
7178 (int) BFD_RELOC_LO16
, AT
);
7179 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sll", "d,w,<",
7181 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or", "d,v,t",
7186 if (offset_expr
.X_add_number
>= 0x7fff)
7187 as_bad (_("operand overflow"));
7188 if (target_big_endian
)
7189 offset_expr
.X_add_number
+= 1;
7190 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
7191 (int) BFD_RELOC_LO16
, breg
);
7192 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srl", "d,w,<",
7194 if (target_big_endian
)
7195 offset_expr
.X_add_number
-= 1;
7197 offset_expr
.X_add_number
+= 1;
7198 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
7199 (int) BFD_RELOC_LO16
, breg
);
7212 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7213 as_bad (_("operand overflow"));
7214 if (! target_big_endian
)
7215 offset_expr
.X_add_number
+= off
;
7216 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
7217 (int) BFD_RELOC_LO16
, breg
);
7218 if (! target_big_endian
)
7219 offset_expr
.X_add_number
-= off
;
7221 offset_expr
.X_add_number
+= off
;
7222 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
7223 (int) BFD_RELOC_LO16
, breg
);
7237 load_address (&icnt
, AT
, &offset_expr
, HAVE_64BIT_ADDRESSES
, &used_at
);
7239 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7240 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
7241 "d,v,t", AT
, AT
, breg
);
7242 if (! target_big_endian
)
7243 expr1
.X_add_number
= off
;
7245 expr1
.X_add_number
= 0;
7246 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
7247 (int) BFD_RELOC_LO16
, AT
);
7248 if (! target_big_endian
)
7249 expr1
.X_add_number
= 0;
7251 expr1
.X_add_number
= off
;
7252 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
7253 (int) BFD_RELOC_LO16
, AT
);
7258 load_address (&icnt
, AT
, &offset_expr
, HAVE_64BIT_ADDRESSES
, &used_at
);
7260 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7261 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
7262 "d,v,t", AT
, AT
, breg
);
7263 if (! target_big_endian
)
7264 expr1
.X_add_number
= 0;
7265 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
7266 (int) BFD_RELOC_LO16
, AT
);
7267 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srl", "d,w,<",
7269 if (! target_big_endian
)
7270 expr1
.X_add_number
= 1;
7272 expr1
.X_add_number
= 0;
7273 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
7274 (int) BFD_RELOC_LO16
, AT
);
7275 if (! target_big_endian
)
7276 expr1
.X_add_number
= 0;
7278 expr1
.X_add_number
= 1;
7279 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
7280 (int) BFD_RELOC_LO16
, AT
);
7281 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sll", "d,w,<",
7283 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or", "d,v,t",
7288 /* FIXME: Check if this is one of the itbl macros, since they
7289 are added dynamically. */
7290 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
7294 as_warn (_("Macro used $at after \".set noat\""));
7297 /* Implement macros in mips16 mode. */
7301 struct mips_cl_insn
*ip
;
7304 int xreg
, yreg
, zreg
, tmp
;
7308 const char *s
, *s2
, *s3
;
7310 mask
= ip
->insn_mo
->mask
;
7312 xreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
7313 yreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
;
7314 zreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
7318 expr1
.X_op
= O_constant
;
7319 expr1
.X_op_symbol
= NULL
;
7320 expr1
.X_add_symbol
= NULL
;
7321 expr1
.X_add_number
= 1;
7340 mips_emit_delays (true);
7341 ++mips_opts
.noreorder
;
7342 mips_any_noreorder
= 1;
7343 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7344 dbl
? "ddiv" : "div",
7345 "0,x,y", xreg
, yreg
);
7346 expr1
.X_add_number
= 2;
7347 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
7348 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break", "6",
7351 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
7352 since that causes an overflow. We should do that as well,
7353 but I don't see how to do the comparisons without a temporary
7355 --mips_opts
.noreorder
;
7356 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "x", zreg
);
7375 mips_emit_delays (true);
7376 ++mips_opts
.noreorder
;
7377 mips_any_noreorder
= 1;
7378 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "0,x,y",
7380 expr1
.X_add_number
= 2;
7381 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
7382 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
7384 --mips_opts
.noreorder
;
7385 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s2
, "x", zreg
);
7391 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7392 dbl
? "dmultu" : "multu", "x,y", xreg
, yreg
);
7393 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "x",
7402 if (imm_expr
.X_op
!= O_constant
)
7403 as_bad (_("Unsupported large constant"));
7404 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7405 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
7406 dbl
? "daddiu" : "addiu", "y,x,4", yreg
, xreg
);
7410 if (imm_expr
.X_op
!= O_constant
)
7411 as_bad (_("Unsupported large constant"));
7412 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7413 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "addiu",
7418 if (imm_expr
.X_op
!= O_constant
)
7419 as_bad (_("Unsupported large constant"));
7420 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7421 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "daddiu",
7444 goto do_reverse_branch
;
7448 goto do_reverse_branch
;
7460 goto do_reverse_branch
;
7471 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "x,y",
7473 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
7500 goto do_addone_branch_i
;
7505 goto do_addone_branch_i
;
7520 goto do_addone_branch_i
;
7527 if (imm_expr
.X_op
!= O_constant
)
7528 as_bad (_("Unsupported large constant"));
7529 ++imm_expr
.X_add_number
;
7532 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, s3
, xreg
);
7533 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
7537 expr1
.X_add_number
= 0;
7538 macro_build ((char *) NULL
, &icnt
, &expr1
, "slti", "x,8", yreg
);
7540 move_register (&icnt
, xreg
, yreg
);
7541 expr1
.X_add_number
= 2;
7542 macro_build ((char *) NULL
, &icnt
, &expr1
, "bteqz", "p");
7543 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7544 "neg", "x,w", xreg
, xreg
);
7548 /* For consistency checking, verify that all bits are specified either
7549 by the match/mask part of the instruction definition, or by the
7552 validate_mips_insn (opc
)
7553 const struct mips_opcode
*opc
;
7555 const char *p
= opc
->args
;
7557 unsigned long used_bits
= opc
->mask
;
7559 if ((used_bits
& opc
->match
) != opc
->match
)
7561 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
7562 opc
->name
, opc
->args
);
7565 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
7572 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7573 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7575 case 'B': USE_BITS (OP_MASK_CODE20
, OP_SH_CODE20
); break;
7576 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
7577 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
7578 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7580 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7581 case 'H': USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
7583 case 'J': USE_BITS (OP_MASK_CODE19
, OP_SH_CODE19
); break;
7585 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
7586 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
7587 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
7588 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7589 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7590 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7591 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7592 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
7593 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7594 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
7595 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7597 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
7598 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
7599 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7600 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
7602 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7603 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7604 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
7605 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7606 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7607 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7608 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
7609 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7610 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7613 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
7614 case 'U': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
7615 USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7617 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
7618 c
, opc
->name
, opc
->args
);
7622 if (used_bits
!= 0xffffffff)
7624 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
7625 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
7631 /* This routine assembles an instruction into its binary format. As a
7632 side effect, it sets one of the global variables imm_reloc or
7633 offset_reloc to the type of relocation to do if one of the operands
7634 is an address expression. */
7639 struct mips_cl_insn
*ip
;
7644 struct mips_opcode
*insn
;
7647 unsigned int lastregno
= 0;
7653 /* If the instruction contains a '.', we first try to match an instruction
7654 including the '.'. Then we try again without the '.'. */
7656 for (s
= str
; *s
!= '\0' && !ISSPACE (*s
); ++s
)
7659 /* If we stopped on whitespace, then replace the whitespace with null for
7660 the call to hash_find. Save the character we replaced just in case we
7661 have to re-parse the instruction. */
7668 insn
= (struct mips_opcode
*) hash_find (op_hash
, str
);
7670 /* If we didn't find the instruction in the opcode table, try again, but
7671 this time with just the instruction up to, but not including the
7675 /* Restore the character we overwrite above (if any). */
7679 /* Scan up to the first '.' or whitespace. */
7681 *s
!= '\0' && *s
!= '.' && !ISSPACE (*s
);
7685 /* If we did not find a '.', then we can quit now. */
7688 insn_error
= "unrecognized opcode";
7692 /* Lookup the instruction in the hash table. */
7694 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
7696 insn_error
= "unrecognized opcode";
7706 assert (strcmp (insn
->name
, str
) == 0);
7708 if (OPCODE_IS_MEMBER (insn
,
7710 | (mips_opts
.ase_mips3d
? INSN_MIPS3D
: 0)),
7716 if (insn
->pinfo
!= INSN_MACRO
)
7718 if (mips_arch
== CPU_R4650
&& (insn
->pinfo
& FP_D
) != 0)
7724 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
7725 && strcmp (insn
->name
, insn
[1].name
) == 0)
7734 static char buf
[100];
7736 _("opcode not supported on this processor: %s (%s)"),
7737 mips_cpu_to_str (mips_arch
),
7738 mips_isa_to_str (mips_opts
.isa
));
7749 ip
->insn_opcode
= insn
->match
;
7751 for (args
= insn
->args
;; ++args
)
7753 s
+= strspn (s
, " \t");
7756 case '\0': /* end of args */
7769 ip
->insn_opcode
|= lastregno
<< OP_SH_RS
;
7773 ip
->insn_opcode
|= lastregno
<< OP_SH_RT
;
7777 ip
->insn_opcode
|= lastregno
<< OP_SH_FT
;
7781 ip
->insn_opcode
|= lastregno
<< OP_SH_FS
;
7787 /* Handle optional base register.
7788 Either the base register is omitted or
7789 we must have a left paren. */
7790 /* This is dependent on the next operand specifier
7791 is a base register specification. */
7792 assert (args
[1] == 'b' || args
[1] == '5'
7793 || args
[1] == '-' || args
[1] == '4');
7797 case ')': /* these must match exactly */
7802 case '<': /* must be at least one digit */
7804 * According to the manual, if the shift amount is greater
7805 * than 31 or less than 0, then the shift amount should be
7806 * mod 32. In reality the mips assembler issues an error.
7807 * We issue a warning and mask out all but the low 5 bits.
7809 my_getExpression (&imm_expr
, s
);
7810 check_absolute_expr (ip
, &imm_expr
);
7811 if ((unsigned long) imm_expr
.X_add_number
> 31)
7813 as_warn (_("Improper shift amount (%ld)"),
7814 (long) imm_expr
.X_add_number
);
7815 imm_expr
.X_add_number
&= OP_MASK_SHAMT
;
7817 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_SHAMT
;
7818 imm_expr
.X_op
= O_absent
;
7822 case '>': /* shift amount minus 32 */
7823 my_getExpression (&imm_expr
, s
);
7824 check_absolute_expr (ip
, &imm_expr
);
7825 if ((unsigned long) imm_expr
.X_add_number
< 32
7826 || (unsigned long) imm_expr
.X_add_number
> 63)
7828 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << OP_SH_SHAMT
;
7829 imm_expr
.X_op
= O_absent
;
7833 case 'k': /* cache code */
7834 case 'h': /* prefx code */
7835 my_getExpression (&imm_expr
, s
);
7836 check_absolute_expr (ip
, &imm_expr
);
7837 if ((unsigned long) imm_expr
.X_add_number
> 31)
7839 as_warn (_("Invalid value for `%s' (%lu)"),
7841 (unsigned long) imm_expr
.X_add_number
);
7842 imm_expr
.X_add_number
&= 0x1f;
7845 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
7847 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
7848 imm_expr
.X_op
= O_absent
;
7852 case 'c': /* break code */
7853 my_getExpression (&imm_expr
, s
);
7854 check_absolute_expr (ip
, &imm_expr
);
7855 if ((unsigned) imm_expr
.X_add_number
> 1023)
7857 as_warn (_("Illegal break code (%ld)"),
7858 (long) imm_expr
.X_add_number
);
7859 imm_expr
.X_add_number
&= OP_MASK_CODE
;
7861 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE
;
7862 imm_expr
.X_op
= O_absent
;
7866 case 'q': /* lower break code */
7867 my_getExpression (&imm_expr
, s
);
7868 check_absolute_expr (ip
, &imm_expr
);
7869 if ((unsigned) imm_expr
.X_add_number
> 1023)
7871 as_warn (_("Illegal lower break code (%ld)"),
7872 (long) imm_expr
.X_add_number
);
7873 imm_expr
.X_add_number
&= OP_MASK_CODE2
;
7875 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE2
;
7876 imm_expr
.X_op
= O_absent
;
7880 case 'B': /* 20-bit syscall/break code. */
7881 my_getExpression (&imm_expr
, s
);
7882 check_absolute_expr (ip
, &imm_expr
);
7883 if ((unsigned) imm_expr
.X_add_number
> OP_MASK_CODE20
)
7884 as_warn (_("Illegal 20-bit code (%ld)"),
7885 (long) imm_expr
.X_add_number
);
7886 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE20
;
7887 imm_expr
.X_op
= O_absent
;
7891 case 'C': /* Coprocessor code */
7892 my_getExpression (&imm_expr
, s
);
7893 check_absolute_expr (ip
, &imm_expr
);
7894 if ((unsigned long) imm_expr
.X_add_number
>= (1 << 25))
7896 as_warn (_("Coproccesor code > 25 bits (%ld)"),
7897 (long) imm_expr
.X_add_number
);
7898 imm_expr
.X_add_number
&= ((1 << 25) - 1);
7900 ip
->insn_opcode
|= imm_expr
.X_add_number
;
7901 imm_expr
.X_op
= O_absent
;
7905 case 'J': /* 19-bit wait code. */
7906 my_getExpression (&imm_expr
, s
);
7907 check_absolute_expr (ip
, &imm_expr
);
7908 if ((unsigned) imm_expr
.X_add_number
> OP_MASK_CODE19
)
7909 as_warn (_("Illegal 19-bit code (%ld)"),
7910 (long) imm_expr
.X_add_number
);
7911 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE19
;
7912 imm_expr
.X_op
= O_absent
;
7916 case 'P': /* Performance register */
7917 my_getExpression (&imm_expr
, s
);
7918 check_absolute_expr (ip
, &imm_expr
);
7919 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
7921 as_warn (_("Invalid performance register (%ld)"),
7922 (long) imm_expr
.X_add_number
);
7923 imm_expr
.X_add_number
&= OP_MASK_PERFREG
;
7925 ip
->insn_opcode
|= (imm_expr
.X_add_number
<< OP_SH_PERFREG
);
7926 imm_expr
.X_op
= O_absent
;
7930 case 'b': /* base register */
7931 case 'd': /* destination register */
7932 case 's': /* source register */
7933 case 't': /* target register */
7934 case 'r': /* both target and source */
7935 case 'v': /* both dest and source */
7936 case 'w': /* both dest and target */
7937 case 'E': /* coprocessor target register */
7938 case 'G': /* coprocessor destination register */
7939 case 'x': /* ignore register name */
7940 case 'z': /* must be zero register */
7941 case 'U': /* destination register (clo/clz). */
7956 while (ISDIGIT (*s
));
7958 as_bad (_("Invalid register number (%d)"), regno
);
7960 else if (*args
== 'E' || *args
== 'G')
7964 if (s
[1] == 'f' && s
[2] == 'p')
7969 else if (s
[1] == 's' && s
[2] == 'p')
7974 else if (s
[1] == 'g' && s
[2] == 'p')
7979 else if (s
[1] == 'a' && s
[2] == 't')
7984 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
7989 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
7994 else if (itbl_have_entries
)
7999 p
= s
+ 1; /* advance past '$' */
8000 n
= itbl_get_field (&p
); /* n is name */
8002 /* See if this is a register defined in an
8004 if (itbl_get_reg_val (n
, &r
))
8006 /* Get_field advances to the start of
8007 the next field, so we need to back
8008 rack to the end of the last field. */
8012 s
= strchr (s
, '\0');
8025 as_warn (_("Used $at without \".set noat\""));
8031 if (c
== 'r' || c
== 'v' || c
== 'w')
8038 /* 'z' only matches $0. */
8039 if (c
== 'z' && regno
!= 0)
8042 /* Now that we have assembled one operand, we use the args string
8043 * to figure out where it goes in the instruction. */
8050 ip
->insn_opcode
|= regno
<< OP_SH_RS
;
8054 ip
->insn_opcode
|= regno
<< OP_SH_RD
;
8057 ip
->insn_opcode
|= regno
<< OP_SH_RD
;
8058 ip
->insn_opcode
|= regno
<< OP_SH_RT
;
8063 ip
->insn_opcode
|= regno
<< OP_SH_RT
;
8066 /* This case exists because on the r3000 trunc
8067 expands into a macro which requires a gp
8068 register. On the r6000 or r4000 it is
8069 assembled into a single instruction which
8070 ignores the register. Thus the insn version
8071 is MIPS_ISA2 and uses 'x', and the macro
8072 version is MIPS_ISA1 and uses 't'. */
8075 /* This case is for the div instruction, which
8076 acts differently if the destination argument
8077 is $0. This only matches $0, and is checked
8078 outside the switch. */
8081 /* Itbl operand; not yet implemented. FIXME ?? */
8083 /* What about all other operands like 'i', which
8084 can be specified in the opcode table? */
8094 ip
->insn_opcode
|= lastregno
<< OP_SH_RS
;
8097 ip
->insn_opcode
|= lastregno
<< OP_SH_RT
;
8102 case 'D': /* floating point destination register */
8103 case 'S': /* floating point source register */
8104 case 'T': /* floating point target register */
8105 case 'R': /* floating point source register */
8109 if (s
[0] == '$' && s
[1] == 'f'
8120 while (ISDIGIT (*s
));
8123 as_bad (_("Invalid float register number (%d)"), regno
);
8125 if ((regno
& 1) != 0
8127 && ! (strcmp (str
, "mtc1") == 0
8128 || strcmp (str
, "mfc1") == 0
8129 || strcmp (str
, "lwc1") == 0
8130 || strcmp (str
, "swc1") == 0
8131 || strcmp (str
, "l.s") == 0
8132 || strcmp (str
, "s.s") == 0))
8133 as_warn (_("Float register should be even, was %d"),
8141 if (c
== 'V' || c
== 'W')
8151 ip
->insn_opcode
|= regno
<< OP_SH_FD
;
8155 ip
->insn_opcode
|= regno
<< OP_SH_FS
;
8159 ip
->insn_opcode
|= regno
<< OP_SH_FT
;
8162 ip
->insn_opcode
|= regno
<< OP_SH_FR
;
8172 ip
->insn_opcode
|= lastregno
<< OP_SH_FS
;
8175 ip
->insn_opcode
|= lastregno
<< OP_SH_FT
;
8181 my_getExpression (&imm_expr
, s
);
8182 if (imm_expr
.X_op
!= O_big
8183 && imm_expr
.X_op
!= O_constant
)
8184 insn_error
= _("absolute expression required");
8189 my_getExpression (&offset_expr
, s
);
8190 *imm_reloc
= BFD_RELOC_32
;
8203 unsigned char temp
[8];
8205 unsigned int length
;
8210 /* These only appear as the last operand in an
8211 instruction, and every instruction that accepts
8212 them in any variant accepts them in all variants.
8213 This means we don't have to worry about backing out
8214 any changes if the instruction does not match.
8216 The difference between them is the size of the
8217 floating point constant and where it goes. For 'F'
8218 and 'L' the constant is 64 bits; for 'f' and 'l' it
8219 is 32 bits. Where the constant is placed is based
8220 on how the MIPS assembler does things:
8223 f -- immediate value
8226 The .lit4 and .lit8 sections are only used if
8227 permitted by the -G argument.
8229 When generating embedded PIC code, we use the
8230 .lit8 section but not the .lit4 section (we can do
8231 .lit4 inline easily; we need to put .lit8
8232 somewhere in the data segment, and using .lit8
8233 permits the linker to eventually combine identical
8236 The code below needs to know whether the target register
8237 is 32 or 64 bits wide. It relies on the fact 'f' and
8238 'F' are used with GPR-based instructions and 'l' and
8239 'L' are used with FPR-based instructions. */
8241 f64
= *args
== 'F' || *args
== 'L';
8242 using_gprs
= *args
== 'F' || *args
== 'f';
8244 save_in
= input_line_pointer
;
8245 input_line_pointer
= s
;
8246 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
8248 s
= input_line_pointer
;
8249 input_line_pointer
= save_in
;
8250 if (err
!= NULL
&& *err
!= '\0')
8252 as_bad (_("Bad floating point constant: %s"), err
);
8253 memset (temp
, '\0', sizeof temp
);
8254 length
= f64
? 8 : 4;
8257 assert (length
== (unsigned) (f64
? 8 : 4));
8261 && (! USE_GLOBAL_POINTER_OPT
8262 || mips_pic
== EMBEDDED_PIC
8263 || g_switch_value
< 4
8264 || (temp
[0] == 0 && temp
[1] == 0)
8265 || (temp
[2] == 0 && temp
[3] == 0))))
8267 imm_expr
.X_op
= O_constant
;
8268 if (! target_big_endian
)
8269 imm_expr
.X_add_number
= bfd_getl32 (temp
);
8271 imm_expr
.X_add_number
= bfd_getb32 (temp
);
8274 && ! mips_disable_float_construction
8275 /* Constants can only be constructed in GPRs and
8276 copied to FPRs if the GPRs are at least as wide
8277 as the FPRs. Force the constant into memory if
8278 we are using 64-bit FPRs but the GPRs are only
8281 || ! (HAVE_64BIT_FPRS
&& HAVE_32BIT_GPRS
))
8282 && ((temp
[0] == 0 && temp
[1] == 0)
8283 || (temp
[2] == 0 && temp
[3] == 0))
8284 && ((temp
[4] == 0 && temp
[5] == 0)
8285 || (temp
[6] == 0 && temp
[7] == 0)))
8287 /* The value is simple enough to load with a couple of
8288 instructions. If using 32-bit registers, set
8289 imm_expr to the high order 32 bits and offset_expr to
8290 the low order 32 bits. Otherwise, set imm_expr to
8291 the entire 64 bit constant. */
8292 if (using_gprs
? HAVE_32BIT_GPRS
: HAVE_32BIT_FPRS
)
8294 imm_expr
.X_op
= O_constant
;
8295 offset_expr
.X_op
= O_constant
;
8296 if (! target_big_endian
)
8298 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
8299 offset_expr
.X_add_number
= bfd_getl32 (temp
);
8303 imm_expr
.X_add_number
= bfd_getb32 (temp
);
8304 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
8306 if (offset_expr
.X_add_number
== 0)
8307 offset_expr
.X_op
= O_absent
;
8309 else if (sizeof (imm_expr
.X_add_number
) > 4)
8311 imm_expr
.X_op
= O_constant
;
8312 if (! target_big_endian
)
8313 imm_expr
.X_add_number
= bfd_getl64 (temp
);
8315 imm_expr
.X_add_number
= bfd_getb64 (temp
);
8319 imm_expr
.X_op
= O_big
;
8320 imm_expr
.X_add_number
= 4;
8321 if (! target_big_endian
)
8323 generic_bignum
[0] = bfd_getl16 (temp
);
8324 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
8325 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
8326 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
8330 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
8331 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
8332 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
8333 generic_bignum
[3] = bfd_getb16 (temp
);
8339 const char *newname
;
8342 /* Switch to the right section. */
8344 subseg
= now_subseg
;
8347 default: /* unused default case avoids warnings. */
8349 newname
= RDATA_SECTION_NAME
;
8350 if ((USE_GLOBAL_POINTER_OPT
&& g_switch_value
>= 8)
8351 || mips_pic
== EMBEDDED_PIC
)
8355 if (mips_pic
== EMBEDDED_PIC
)
8358 newname
= RDATA_SECTION_NAME
;
8361 assert (!USE_GLOBAL_POINTER_OPT
8362 || g_switch_value
>= 4);
8366 new_seg
= subseg_new (newname
, (subsegT
) 0);
8367 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
8368 bfd_set_section_flags (stdoutput
, new_seg
,
8373 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
8374 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
8375 && strcmp (TARGET_OS
, "elf") != 0)
8376 record_alignment (new_seg
, 4);
8378 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
8380 as_bad (_("Can't use floating point insn in this section"));
8382 /* Set the argument to the current address in the
8384 offset_expr
.X_op
= O_symbol
;
8385 offset_expr
.X_add_symbol
=
8386 symbol_new ("L0\001", now_seg
,
8387 (valueT
) frag_now_fix (), frag_now
);
8388 offset_expr
.X_add_number
= 0;
8390 /* Put the floating point number into the section. */
8391 p
= frag_more ((int) length
);
8392 memcpy (p
, temp
, length
);
8394 /* Switch back to the original section. */
8395 subseg_set (seg
, subseg
);
8400 case 'i': /* 16 bit unsigned immediate */
8401 case 'j': /* 16 bit signed immediate */
8402 *imm_reloc
= BFD_RELOC_LO16
;
8403 c
= my_getSmallExpression (&imm_expr
, s
);
8408 if (imm_expr
.X_op
== O_constant
)
8409 imm_expr
.X_add_number
=
8410 (imm_expr
.X_add_number
>> 16) & 0xffff;
8412 else if (c
== S_EX_HIGHEST
)
8413 *imm_reloc
= BFD_RELOC_MIPS_HIGHEST
;
8414 else if (c
== S_EX_HIGHER
)
8415 *imm_reloc
= BFD_RELOC_MIPS_HIGHER
;
8416 else if (c
== S_EX_GP_REL
)
8418 /* This occurs in NewABI only. */
8419 c
= my_getSmallExpression (&imm_expr
, s
);
8421 as_bad (_("bad composition of relocations"));
8424 c
= my_getSmallExpression (&imm_expr
, s
);
8426 as_bad (_("bad composition of relocations"));
8429 imm_reloc
[0] = BFD_RELOC_GPREL16
;
8430 imm_reloc
[1] = BFD_RELOC_MIPS_SUB
;
8431 imm_reloc
[2] = BFD_RELOC_LO16
;
8436 else if (c
== S_EX_HI
)
8438 *imm_reloc
= BFD_RELOC_HI16_S
;
8439 imm_unmatched_hi
= true;
8442 *imm_reloc
= BFD_RELOC_HI16
;
8444 else if (imm_expr
.X_op
== O_constant
)
8445 imm_expr
.X_add_number
&= 0xffff;
8449 if ((c
== S_EX_NONE
&& imm_expr
.X_op
!= O_constant
)
8450 || ((imm_expr
.X_add_number
< 0
8451 || imm_expr
.X_add_number
>= 0x10000)
8452 && imm_expr
.X_op
== O_constant
))
8454 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
8455 !strcmp (insn
->name
, insn
[1].name
))
8457 if (imm_expr
.X_op
== O_constant
8458 || imm_expr
.X_op
== O_big
)
8459 as_bad (_("16 bit expression not in range 0..65535"));
8467 /* The upper bound should be 0x8000, but
8468 unfortunately the MIPS assembler accepts numbers
8469 from 0x8000 to 0xffff and sign extends them, and
8470 we want to be compatible. We only permit this
8471 extended range for an instruction which does not
8472 provide any further alternates, since those
8473 alternates may handle other cases. People should
8474 use the numbers they mean, rather than relying on
8475 a mysterious sign extension. */
8476 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
8477 strcmp (insn
->name
, insn
[1].name
) == 0);
8482 if ((c
== S_EX_NONE
&& imm_expr
.X_op
!= O_constant
)
8483 || ((imm_expr
.X_add_number
< -0x8000
8484 || imm_expr
.X_add_number
>= max
)
8485 && imm_expr
.X_op
== O_constant
)
8487 && imm_expr
.X_add_number
< 0
8489 && imm_expr
.X_unsigned
8490 && sizeof (imm_expr
.X_add_number
) <= 4))
8494 if (imm_expr
.X_op
== O_constant
8495 || imm_expr
.X_op
== O_big
)
8496 as_bad (_("16 bit expression not in range -32768..32767"));
8502 case 'o': /* 16 bit offset */
8503 c
= my_getSmallExpression (&offset_expr
, s
);
8505 /* If this value won't fit into a 16 bit offset, then go
8506 find a macro that will generate the 32 bit offset
8509 && (offset_expr
.X_op
!= O_constant
8510 || offset_expr
.X_add_number
>= 0x8000
8511 || offset_expr
.X_add_number
< -0x8000))
8516 if (offset_expr
.X_op
!= O_constant
)
8518 offset_expr
.X_add_number
=
8519 (offset_expr
.X_add_number
>> 16) & 0xffff;
8521 *offset_reloc
= BFD_RELOC_LO16
;
8525 case 'p': /* pc relative offset */
8526 if (mips_pic
== EMBEDDED_PIC
)
8527 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
8529 *offset_reloc
= BFD_RELOC_16_PCREL
;
8530 my_getExpression (&offset_expr
, s
);
8534 case 'u': /* upper 16 bits */
8535 c
= my_getSmallExpression (&imm_expr
, s
);
8536 *imm_reloc
= BFD_RELOC_LO16
;
8541 if (imm_expr
.X_op
== O_constant
)
8542 imm_expr
.X_add_number
=
8543 (imm_expr
.X_add_number
>> 16) & 0xffff;
8544 else if (c
== S_EX_HI
)
8546 *imm_reloc
= BFD_RELOC_HI16_S
;
8547 imm_unmatched_hi
= true;
8550 else if (c
== S_EX_HIGHEST
)
8551 *imm_reloc
= BFD_RELOC_MIPS_HIGHEST
;
8552 else if (c
== S_EX_GP_REL
)
8554 /* This occurs in NewABI only. */
8555 c
= my_getSmallExpression (&imm_expr
, s
);
8557 as_bad (_("bad composition of relocations"));
8560 c
= my_getSmallExpression (&imm_expr
, s
);
8562 as_bad (_("bad composition of relocations"));
8565 imm_reloc
[0] = BFD_RELOC_GPREL16
;
8566 imm_reloc
[1] = BFD_RELOC_MIPS_SUB
;
8567 imm_reloc
[2] = BFD_RELOC_HI16_S
;
8573 *imm_reloc
= BFD_RELOC_HI16
;
8575 else if (imm_expr
.X_op
== O_constant
)
8576 imm_expr
.X_add_number
&= 0xffff;
8578 if (imm_expr
.X_op
== O_constant
8579 && (imm_expr
.X_add_number
< 0
8580 || imm_expr
.X_add_number
>= 0x10000))
8581 as_bad (_("lui expression not in range 0..65535"));
8585 case 'a': /* 26 bit address */
8586 my_getExpression (&offset_expr
, s
);
8588 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
8591 case 'N': /* 3 bit branch condition code */
8592 case 'M': /* 3 bit compare condition code */
8593 if (strncmp (s
, "$fcc", 4) != 0)
8603 while (ISDIGIT (*s
));
8605 as_bad (_("invalid condition code register $fcc%d"), regno
);
8607 ip
->insn_opcode
|= regno
<< OP_SH_BCC
;
8609 ip
->insn_opcode
|= regno
<< OP_SH_CCC
;
8613 if (s
[0] == '0' && (s
[1] == 'x' || s
[1] == 'X'))
8624 while (ISDIGIT (*s
));
8627 c
= 8; /* Invalid sel value. */
8630 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
8631 ip
->insn_opcode
|= c
;
8635 as_bad (_("bad char = '%c'\n"), *args
);
8640 /* Args don't match. */
8641 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
8642 !strcmp (insn
->name
, insn
[1].name
))
8646 insn_error
= _("illegal operands");
8651 insn_error
= _("illegal operands");
8656 /* This routine assembles an instruction into its binary format when
8657 assembling for the mips16. As a side effect, it sets one of the
8658 global variables imm_reloc or offset_reloc to the type of
8659 relocation to do if one of the operands is an address expression.
8660 It also sets mips16_small and mips16_ext if the user explicitly
8661 requested a small or extended instruction. */
8666 struct mips_cl_insn
*ip
;
8670 struct mips_opcode
*insn
;
8673 unsigned int lastregno
= 0;
8678 mips16_small
= false;
8681 for (s
= str
; ISLOWER (*s
); ++s
)
8693 if (s
[1] == 't' && s
[2] == ' ')
8696 mips16_small
= true;
8700 else if (s
[1] == 'e' && s
[2] == ' ')
8709 insn_error
= _("unknown opcode");
8713 if (mips_opts
.noautoextend
&& ! mips16_ext
)
8714 mips16_small
= true;
8716 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
8718 insn_error
= _("unrecognized opcode");
8725 assert (strcmp (insn
->name
, str
) == 0);
8728 ip
->insn_opcode
= insn
->match
;
8729 ip
->use_extend
= false;
8730 imm_expr
.X_op
= O_absent
;
8731 imm_reloc
[0] = BFD_RELOC_UNUSED
;
8732 imm_reloc
[1] = BFD_RELOC_UNUSED
;
8733 imm_reloc
[2] = BFD_RELOC_UNUSED
;
8734 offset_expr
.X_op
= O_absent
;
8735 offset_reloc
[0] = BFD_RELOC_UNUSED
;
8736 offset_reloc
[1] = BFD_RELOC_UNUSED
;
8737 offset_reloc
[2] = BFD_RELOC_UNUSED
;
8738 for (args
= insn
->args
; 1; ++args
)
8745 /* In this switch statement we call break if we did not find
8746 a match, continue if we did find a match, or return if we
8755 /* Stuff the immediate value in now, if we can. */
8756 if (imm_expr
.X_op
== O_constant
8757 && *imm_reloc
> BFD_RELOC_UNUSED
8758 && insn
->pinfo
!= INSN_MACRO
)
8760 mips16_immed (NULL
, 0, *imm_reloc
- BFD_RELOC_UNUSED
,
8761 imm_expr
.X_add_number
, true, mips16_small
,
8762 mips16_ext
, &ip
->insn_opcode
,
8763 &ip
->use_extend
, &ip
->extend
);
8764 imm_expr
.X_op
= O_absent
;
8765 *imm_reloc
= BFD_RELOC_UNUSED
;
8779 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
8782 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
8798 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
8800 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
8827 while (ISDIGIT (*s
));
8830 as_bad (_("invalid register number (%d)"), regno
);
8836 if (s
[1] == 'f' && s
[2] == 'p')
8841 else if (s
[1] == 's' && s
[2] == 'p')
8846 else if (s
[1] == 'g' && s
[2] == 'p')
8851 else if (s
[1] == 'a' && s
[2] == 't')
8856 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
8861 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
8874 if (c
== 'v' || c
== 'w')
8876 regno
= mips16_to_32_reg_map
[lastregno
];
8890 regno
= mips32_to_16_reg_map
[regno
];
8895 regno
= ILLEGAL_REG
;
8900 regno
= ILLEGAL_REG
;
8905 regno
= ILLEGAL_REG
;
8910 if (regno
== AT
&& ! mips_opts
.noat
)
8911 as_warn (_("used $at without \".set noat\""));
8918 if (regno
== ILLEGAL_REG
)
8925 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RX
;
8929 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RY
;
8932 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RZ
;
8935 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_MOVE32Z
;
8941 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REGR32
;
8944 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
8945 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
8955 if (strncmp (s
, "$pc", 3) == 0)
8979 && strncmp (s
+ 1, "gprel(", sizeof "gprel(" - 1) == 0)
8981 /* This is %gprel(SYMBOL). We need to read SYMBOL,
8982 and generate the appropriate reloc. If the text
8983 inside %gprel is not a symbol name with an
8984 optional offset, then we generate a normal reloc
8985 and will probably fail later. */
8986 my_getExpression (&imm_expr
, s
+ sizeof "%gprel" - 1);
8987 if (imm_expr
.X_op
== O_symbol
)
8990 *imm_reloc
= BFD_RELOC_MIPS16_GPREL
;
8992 ip
->use_extend
= true;
8999 /* Just pick up a normal expression. */
9000 my_getExpression (&imm_expr
, s
);
9003 if (imm_expr
.X_op
== O_register
)
9005 /* What we thought was an expression turned out to
9008 if (s
[0] == '(' && args
[1] == '(')
9010 /* It looks like the expression was omitted
9011 before a register indirection, which means
9012 that the expression is implicitly zero. We
9013 still set up imm_expr, so that we handle
9014 explicit extensions correctly. */
9015 imm_expr
.X_op
= O_constant
;
9016 imm_expr
.X_add_number
= 0;
9017 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9024 /* We need to relax this instruction. */
9025 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9034 /* We use offset_reloc rather than imm_reloc for the PC
9035 relative operands. This lets macros with both
9036 immediate and address operands work correctly. */
9037 my_getExpression (&offset_expr
, s
);
9039 if (offset_expr
.X_op
== O_register
)
9042 /* We need to relax this instruction. */
9043 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9047 case '6': /* break code */
9048 my_getExpression (&imm_expr
, s
);
9049 check_absolute_expr (ip
, &imm_expr
);
9050 if ((unsigned long) imm_expr
.X_add_number
> 63)
9052 as_warn (_("Invalid value for `%s' (%lu)"),
9054 (unsigned long) imm_expr
.X_add_number
);
9055 imm_expr
.X_add_number
&= 0x3f;
9057 ip
->insn_opcode
|= imm_expr
.X_add_number
<< MIPS16OP_SH_IMM6
;
9058 imm_expr
.X_op
= O_absent
;
9062 case 'a': /* 26 bit address */
9063 my_getExpression (&offset_expr
, s
);
9065 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
9066 ip
->insn_opcode
<<= 16;
9069 case 'l': /* register list for entry macro */
9070 case 'L': /* register list for exit macro */
9080 int freg
, reg1
, reg2
;
9082 while (*s
== ' ' || *s
== ',')
9086 as_bad (_("can't parse register list"));
9098 while (ISDIGIT (*s
))
9120 as_bad (_("invalid register list"));
9125 while (ISDIGIT (*s
))
9132 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
9137 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
9142 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
9143 mask
|= (reg2
- 3) << 3;
9144 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
9145 mask
|= (reg2
- 15) << 1;
9146 else if (reg1
== 31 && reg2
== 31)
9150 as_bad (_("invalid register list"));
9154 /* The mask is filled in in the opcode table for the
9155 benefit of the disassembler. We remove it before
9156 applying the actual mask. */
9157 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
9158 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
9162 case 'e': /* extend code */
9163 my_getExpression (&imm_expr
, s
);
9164 check_absolute_expr (ip
, &imm_expr
);
9165 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
9167 as_warn (_("Invalid value for `%s' (%lu)"),
9169 (unsigned long) imm_expr
.X_add_number
);
9170 imm_expr
.X_add_number
&= 0x7ff;
9172 ip
->insn_opcode
|= imm_expr
.X_add_number
;
9173 imm_expr
.X_op
= O_absent
;
9183 /* Args don't match. */
9184 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
9185 strcmp (insn
->name
, insn
[1].name
) == 0)
9192 insn_error
= _("illegal operands");
9198 /* This structure holds information we know about a mips16 immediate
9201 struct mips16_immed_operand
9203 /* The type code used in the argument string in the opcode table. */
9205 /* The number of bits in the short form of the opcode. */
9207 /* The number of bits in the extended form of the opcode. */
9209 /* The amount by which the short form is shifted when it is used;
9210 for example, the sw instruction has a shift count of 2. */
9212 /* The amount by which the short form is shifted when it is stored
9213 into the instruction code. */
9215 /* Non-zero if the short form is unsigned. */
9217 /* Non-zero if the extended form is unsigned. */
9219 /* Non-zero if the value is PC relative. */
9223 /* The mips16 immediate operand types. */
9225 static const struct mips16_immed_operand mips16_immed_operands
[] =
9227 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
9228 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
9229 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
9230 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
9231 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
9232 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9233 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9234 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9235 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9236 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
9237 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9238 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9239 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9240 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
9241 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
9242 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
9243 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
9244 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
9245 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
9246 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
9247 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
9250 #define MIPS16_NUM_IMMED \
9251 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
9253 /* Handle a mips16 instruction with an immediate value. This or's the
9254 small immediate value into *INSN. It sets *USE_EXTEND to indicate
9255 whether an extended value is needed; if one is needed, it sets
9256 *EXTEND to the value. The argument type is TYPE. The value is VAL.
9257 If SMALL is true, an unextended opcode was explicitly requested.
9258 If EXT is true, an extended opcode was explicitly requested. If
9259 WARN is true, warn if EXT does not match reality. */
9262 mips16_immed (file
, line
, type
, val
, warn
, small
, ext
, insn
, use_extend
,
9271 unsigned long *insn
;
9272 boolean
*use_extend
;
9273 unsigned short *extend
;
9275 register const struct mips16_immed_operand
*op
;
9276 int mintiny
, maxtiny
;
9279 op
= mips16_immed_operands
;
9280 while (op
->type
!= type
)
9283 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
9288 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
9291 maxtiny
= 1 << op
->nbits
;
9296 maxtiny
= (1 << op
->nbits
) - 1;
9301 mintiny
= - (1 << (op
->nbits
- 1));
9302 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
9305 /* Branch offsets have an implicit 0 in the lowest bit. */
9306 if (type
== 'p' || type
== 'q')
9309 if ((val
& ((1 << op
->shift
) - 1)) != 0
9310 || val
< (mintiny
<< op
->shift
)
9311 || val
> (maxtiny
<< op
->shift
))
9316 if (warn
&& ext
&& ! needext
)
9317 as_warn_where (file
, line
,
9318 _("extended operand requested but not required"));
9319 if (small
&& needext
)
9320 as_bad_where (file
, line
, _("invalid unextended operand value"));
9322 if (small
|| (! ext
&& ! needext
))
9326 *use_extend
= false;
9327 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
9328 insnval
<<= op
->op_shift
;
9333 long minext
, maxext
;
9339 maxext
= (1 << op
->extbits
) - 1;
9343 minext
= - (1 << (op
->extbits
- 1));
9344 maxext
= (1 << (op
->extbits
- 1)) - 1;
9346 if (val
< minext
|| val
> maxext
)
9347 as_bad_where (file
, line
,
9348 _("operand value out of range for instruction"));
9351 if (op
->extbits
== 16)
9353 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
9356 else if (op
->extbits
== 15)
9358 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
9363 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
9367 *extend
= (unsigned short) extval
;
9372 static struct percent_op_match
9375 const enum small_ex_type type
;
9380 {"%call_hi", S_EX_CALL_HI
},
9381 {"%call_lo", S_EX_CALL_LO
},
9382 {"%call16", S_EX_CALL16
},
9383 {"%got_disp", S_EX_GOT_DISP
},
9384 {"%got_page", S_EX_GOT_PAGE
},
9385 {"%got_ofst", S_EX_GOT_OFST
},
9386 {"%got_hi", S_EX_GOT_HI
},
9387 {"%got_lo", S_EX_GOT_LO
},
9389 {"%gp_rel", S_EX_GP_REL
},
9390 {"%half", S_EX_HALF
},
9391 {"%highest", S_EX_HIGHEST
},
9392 {"%higher", S_EX_HIGHER
},
9398 /* Parse small expression input. STR gets adjusted to eat up whitespace.
9399 It detects valid "%percent_op(...)" and "($reg)" strings. Percent_op's
9400 can be nested, this is handled by blanking the innermost, parsing the
9401 rest by subsequent calls. */
9404 my_getSmallParser (str
, len
, nestlevel
)
9410 *str
+= strspn (*str
, " \t");
9411 /* Check for expression in parentheses. */
9414 char *b
= *str
+ 1 + strspn (*str
+ 1, " \t");
9417 /* Check for base register. */
9421 && (e
= b
+ strcspn (b
, ") \t"))
9422 && e
- b
> 1 && e
- b
< 4)
9425 && ((b
[1] == 'f' && b
[2] == 'p')
9426 || (b
[1] == 's' && b
[2] == 'p')
9427 || (b
[1] == 'g' && b
[2] == 'p')
9428 || (b
[1] == 'a' && b
[2] == 't')
9430 && ISDIGIT (b
[2]))))
9431 || (ISDIGIT (b
[1])))
9433 *len
= strcspn (*str
, ")") + 1;
9434 return S_EX_REGISTER
;
9438 /* Check for percent_op (in parentheses). */
9439 else if (b
[0] == '%')
9442 return my_getPercentOp (str
, len
, nestlevel
);
9445 /* Some other expression in the parentheses, which can contain
9446 parentheses itself. Attempt to find the matching one. */
9452 for (s
= *str
+ 1; *s
&& pcnt
; s
++, (*len
)++)
9461 /* Check for percent_op (outside of parentheses). */
9462 else if (*str
[0] == '%')
9463 return my_getPercentOp (str
, len
, nestlevel
);
9465 /* Any other expression. */
9470 my_getPercentOp (str
, len
, nestlevel
)
9475 char *tmp
= *str
+ 1;
9478 while (ISALPHA (*tmp
) || *tmp
== '_')
9480 *tmp
= TOLOWER (*tmp
);
9483 while (i
< (sizeof (percent_op
) / sizeof (struct percent_op_match
)))
9485 if (strncmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)))
9489 int type
= percent_op
[i
].type
;
9491 /* Only %hi and %lo are allowed for OldABI. */
9492 if (! HAVE_NEWABI
&& type
!= S_EX_HI
&& type
!= S_EX_LO
)
9495 *len
= strlen (percent_op
[i
].str
);
9504 my_getSmallExpression (ep
, str
)
9508 static char *oldstr
= NULL
;
9514 /* Don't update oldstr if the last call had nested percent_op's. We need
9515 it to parse the outer ones later. */
9522 c
= my_getSmallParser (&str
, &len
, &nestlevel
);
9523 if (c
!= S_EX_NONE
&& c
!= S_EX_REGISTER
)
9526 while (c
!= S_EX_NONE
&& c
!= S_EX_REGISTER
);
9530 /* A percent_op was encountered. Don't try to get an expression if
9531 it is already blanked out. */
9532 if (*(str
+ strspn (str
+ 1, " )")) != ')')
9536 /* Let my_getExpression() stop at the closing parenthesis. */
9537 save
= *(str
+ len
);
9538 *(str
+ len
) = '\0';
9539 my_getExpression (ep
, str
);
9540 *(str
+ len
) = save
;
9544 /* Blank out including the % sign and the proper matching
9547 char *s
= strrchr (oldstr
, '%');
9550 for (end
= strchr (s
, '(') + 1; *end
&& pcnt
; end
++)
9554 else if (*end
== ')')
9558 memset (s
, ' ', end
- s
);
9562 expr_end
= str
+ len
;
9566 else if (c
== S_EX_NONE
)
9568 my_getExpression (ep
, str
);
9570 else if (c
== S_EX_REGISTER
)
9572 ep
->X_op
= O_constant
;
9574 ep
->X_add_symbol
= NULL
;
9575 ep
->X_op_symbol
= NULL
;
9576 ep
->X_add_number
= 0;
9580 as_fatal (_("internal error"));
9584 /* All percent_op's have been handled. */
9591 my_getExpression (ep
, str
)
9598 save_in
= input_line_pointer
;
9599 input_line_pointer
= str
;
9601 expr_end
= input_line_pointer
;
9602 input_line_pointer
= save_in
;
9604 /* If we are in mips16 mode, and this is an expression based on `.',
9605 then we bump the value of the symbol by 1 since that is how other
9606 text symbols are handled. We don't bother to handle complex
9607 expressions, just `.' plus or minus a constant. */
9608 if (mips_opts
.mips16
9609 && ep
->X_op
== O_symbol
9610 && strcmp (S_GET_NAME (ep
->X_add_symbol
), FAKE_LABEL_NAME
) == 0
9611 && S_GET_SEGMENT (ep
->X_add_symbol
) == now_seg
9612 && symbol_get_frag (ep
->X_add_symbol
) == frag_now
9613 && symbol_constant_p (ep
->X_add_symbol
)
9614 && (val
= S_GET_VALUE (ep
->X_add_symbol
)) == frag_now_fix ())
9615 S_SET_VALUE (ep
->X_add_symbol
, val
+ 1);
9618 /* Turn a string in input_line_pointer into a floating point constant
9619 of type TYPE, and store the appropriate bytes in *LITP. The number
9620 of LITTLENUMS emitted is stored in *SIZEP. An error message is
9621 returned, or NULL on OK. */
9624 md_atof (type
, litP
, sizeP
)
9630 LITTLENUM_TYPE words
[4];
9646 return _("bad call to md_atof");
9649 t
= atof_ieee (input_line_pointer
, type
, words
);
9651 input_line_pointer
= t
;
9655 if (! target_big_endian
)
9657 for (i
= prec
- 1; i
>= 0; i
--)
9659 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
9665 for (i
= 0; i
< prec
; i
++)
9667 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
9676 md_number_to_chars (buf
, val
, n
)
9681 if (target_big_endian
)
9682 number_to_chars_bigendian (buf
, val
, n
);
9684 number_to_chars_littleendian (buf
, val
, n
);
9688 static int support_64bit_objects(void)
9690 const char **list
, **l
;
9692 list
= bfd_target_list ();
9693 for (l
= list
; *l
!= NULL
; l
++)
9695 /* This is traditional mips */
9696 if (strcmp (*l
, "elf64-tradbigmips") == 0
9697 || strcmp (*l
, "elf64-tradlittlemips") == 0)
9699 if (strcmp (*l
, "elf64-bigmips") == 0
9700 || strcmp (*l
, "elf64-littlemips") == 0)
9704 return (*l
!= NULL
);
9706 #endif /* OBJ_ELF */
9708 CONST
char *md_shortopts
= "nO::g::G:";
9710 struct option md_longopts
[] =
9712 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
9713 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
9714 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
9715 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
9716 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
9717 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
9718 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
9719 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
9720 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
9721 #define OPTION_MIPS5 (OPTION_MD_BASE + 5)
9722 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
9723 #define OPTION_MIPS32 (OPTION_MD_BASE + 6)
9724 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
9725 #define OPTION_MIPS64 (OPTION_MD_BASE + 7)
9726 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
9727 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 8)
9728 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
9729 #define OPTION_TRAP (OPTION_MD_BASE + 9)
9730 {"trap", no_argument
, NULL
, OPTION_TRAP
},
9731 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
9732 #define OPTION_BREAK (OPTION_MD_BASE + 10)
9733 {"break", no_argument
, NULL
, OPTION_BREAK
},
9734 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
9735 #define OPTION_EB (OPTION_MD_BASE + 11)
9736 {"EB", no_argument
, NULL
, OPTION_EB
},
9737 #define OPTION_EL (OPTION_MD_BASE + 12)
9738 {"EL", no_argument
, NULL
, OPTION_EL
},
9739 #define OPTION_MIPS16 (OPTION_MD_BASE + 13)
9740 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
9741 #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 14)
9742 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
9743 #define OPTION_M7000_HILO_FIX (OPTION_MD_BASE + 15)
9744 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
9745 #define OPTION_NO_M7000_HILO_FIX (OPTION_MD_BASE + 16)
9746 {"no-fix-7000", no_argument
, NULL
, OPTION_NO_M7000_HILO_FIX
},
9747 #define OPTION_FP32 (OPTION_MD_BASE + 17)
9748 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
9749 #define OPTION_GP32 (OPTION_MD_BASE + 18)
9750 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
9751 #define OPTION_CONSTRUCT_FLOATS (OPTION_MD_BASE + 19)
9752 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
9753 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MD_BASE + 20)
9754 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
9755 #define OPTION_MARCH (OPTION_MD_BASE + 21)
9756 {"march", required_argument
, NULL
, OPTION_MARCH
},
9757 #define OPTION_MTUNE (OPTION_MD_BASE + 22)
9758 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
9759 #define OPTION_MCPU (OPTION_MD_BASE + 23)
9760 {"mcpu", required_argument
, NULL
, OPTION_MCPU
},
9761 #define OPTION_M4650 (OPTION_MD_BASE + 24)
9762 {"m4650", no_argument
, NULL
, OPTION_M4650
},
9763 #define OPTION_NO_M4650 (OPTION_MD_BASE + 25)
9764 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
9765 #define OPTION_M4010 (OPTION_MD_BASE + 26)
9766 {"m4010", no_argument
, NULL
, OPTION_M4010
},
9767 #define OPTION_NO_M4010 (OPTION_MD_BASE + 27)
9768 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
9769 #define OPTION_M4100 (OPTION_MD_BASE + 28)
9770 {"m4100", no_argument
, NULL
, OPTION_M4100
},
9771 #define OPTION_NO_M4100 (OPTION_MD_BASE + 29)
9772 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
9773 #define OPTION_M3900 (OPTION_MD_BASE + 30)
9774 {"m3900", no_argument
, NULL
, OPTION_M3900
},
9775 #define OPTION_NO_M3900 (OPTION_MD_BASE + 31)
9776 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
9777 #define OPTION_GP64 (OPTION_MD_BASE + 32)
9778 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
9779 #define OPTION_MIPS3D (OPTION_MD_BASE + 33)
9780 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
9781 #define OPTION_NO_MIPS3D (OPTION_MD_BASE + 34)
9782 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
9784 #define OPTION_ELF_BASE (OPTION_MD_BASE + 35)
9785 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
9786 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
9787 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
9788 #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1)
9789 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
9790 #define OPTION_XGOT (OPTION_ELF_BASE + 2)
9791 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
9792 #define OPTION_MABI (OPTION_ELF_BASE + 3)
9793 {"mabi", required_argument
, NULL
, OPTION_MABI
},
9794 #define OPTION_32 (OPTION_ELF_BASE + 4)
9795 {"32", no_argument
, NULL
, OPTION_32
},
9796 #define OPTION_N32 (OPTION_ELF_BASE + 5)
9797 {"n32", no_argument
, NULL
, OPTION_N32
},
9798 #define OPTION_64 (OPTION_ELF_BASE + 6)
9799 {"64", no_argument
, NULL
, OPTION_64
},
9800 #endif /* OBJ_ELF */
9801 {NULL
, no_argument
, NULL
, 0}
9803 size_t md_longopts_size
= sizeof (md_longopts
);
9806 md_parse_option (c
, arg
)
9812 case OPTION_CONSTRUCT_FLOATS
:
9813 mips_disable_float_construction
= 0;
9816 case OPTION_NO_CONSTRUCT_FLOATS
:
9817 mips_disable_float_construction
= 1;
9829 target_big_endian
= 1;
9833 target_big_endian
= 0;
9841 if (arg
&& arg
[1] == '0')
9851 mips_debug
= atoi (arg
);
9852 /* When the MIPS assembler sees -g or -g2, it does not do
9853 optimizations which limit full symbolic debugging. We take
9854 that to be equivalent to -O0. */
9855 if (mips_debug
== 2)
9860 mips_opts
.isa
= ISA_MIPS1
;
9864 mips_opts
.isa
= ISA_MIPS2
;
9868 mips_opts
.isa
= ISA_MIPS3
;
9872 mips_opts
.isa
= ISA_MIPS4
;
9876 mips_opts
.isa
= ISA_MIPS5
;
9880 mips_opts
.isa
= ISA_MIPS32
;
9884 mips_opts
.isa
= ISA_MIPS64
;
9891 int cpu
= CPU_UNKNOWN
;
9893 /* Identify the processor type. */
9894 if (strcasecmp (arg
, "default") != 0)
9896 const struct mips_cpu_info
*ci
;
9898 ci
= mips_cpu_info_from_name (arg
);
9899 if (ci
== NULL
|| ci
->is_isa
)
9904 as_fatal (_("invalid architecture -mtune=%s"), arg
);
9907 as_fatal (_("invalid architecture -march=%s"), arg
);
9910 as_fatal (_("invalid architecture -mcpu=%s"), arg
);
9921 if (mips_tune
!= CPU_UNKNOWN
&& mips_tune
!= cpu
)
9922 as_warn (_("A different -mtune= was already specified, is now "
9927 if (mips_arch
!= CPU_UNKNOWN
&& mips_arch
!= cpu
)
9928 as_warn (_("A different -march= was already specified, is now "
9933 if (mips_cpu
!= CPU_UNKNOWN
&& mips_cpu
!= cpu
)
9934 as_warn (_("A different -mcpu= was already specified, is now "
9942 if ((mips_arch
!= CPU_UNKNOWN
&& mips_arch
!= CPU_R4650
)
9943 || (mips_tune
!= CPU_UNKNOWN
&& mips_tune
!= CPU_R4650
))
9944 as_warn (_("A different -march= or -mtune= was already specified, "
9946 mips_arch
= CPU_R4650
;
9947 mips_tune
= CPU_R4650
;
9950 case OPTION_NO_M4650
:
9954 if ((mips_arch
!= CPU_UNKNOWN
&& mips_arch
!= CPU_R4010
)
9955 || (mips_tune
!= CPU_UNKNOWN
&& mips_tune
!= CPU_R4010
))
9956 as_warn (_("A different -march= or -mtune= was already specified, "
9958 mips_arch
= CPU_R4010
;
9959 mips_tune
= CPU_R4010
;
9962 case OPTION_NO_M4010
:
9966 if ((mips_arch
!= CPU_UNKNOWN
&& mips_arch
!= CPU_VR4100
)
9967 || (mips_tune
!= CPU_UNKNOWN
&& mips_tune
!= CPU_VR4100
))
9968 as_warn (_("A different -march= or -mtune= was already specified, "
9970 mips_arch
= CPU_VR4100
;
9971 mips_tune
= CPU_VR4100
;
9974 case OPTION_NO_M4100
:
9978 if ((mips_arch
!= CPU_UNKNOWN
&& mips_arch
!= CPU_R3900
)
9979 || (mips_tune
!= CPU_UNKNOWN
&& mips_tune
!= CPU_R3900
))
9980 as_warn (_("A different -march= or -mtune= was already specified, "
9982 mips_arch
= CPU_R3900
;
9983 mips_tune
= CPU_R3900
;
9986 case OPTION_NO_M3900
:
9990 mips_opts
.mips16
= 1;
9991 mips_no_prev_insn (false);
9994 case OPTION_NO_MIPS16
:
9995 mips_opts
.mips16
= 0;
9996 mips_no_prev_insn (false);
10000 mips_opts
.ase_mips3d
= 1;
10003 case OPTION_NO_MIPS3D
:
10004 mips_opts
.ase_mips3d
= 0;
10007 case OPTION_MEMBEDDED_PIC
:
10008 mips_pic
= EMBEDDED_PIC
;
10009 if (USE_GLOBAL_POINTER_OPT
&& g_switch_seen
)
10011 as_bad (_("-G may not be used with embedded PIC code"));
10014 g_switch_value
= 0x7fffffff;
10018 /* When generating ELF code, we permit -KPIC and -call_shared to
10019 select SVR4_PIC, and -non_shared to select no PIC. This is
10020 intended to be compatible with Irix 5. */
10021 case OPTION_CALL_SHARED
:
10022 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10024 as_bad (_("-call_shared is supported only for ELF format"));
10027 mips_pic
= SVR4_PIC
;
10028 if (g_switch_seen
&& g_switch_value
!= 0)
10030 as_bad (_("-G may not be used with SVR4 PIC code"));
10033 g_switch_value
= 0;
10036 case OPTION_NON_SHARED
:
10037 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10039 as_bad (_("-non_shared is supported only for ELF format"));
10045 /* The -xgot option tells the assembler to use 32 offsets when
10046 accessing the got in SVR4_PIC mode. It is for Irix
10051 #endif /* OBJ_ELF */
10054 if (! USE_GLOBAL_POINTER_OPT
)
10056 as_bad (_("-G is not supported for this configuration"));
10059 else if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
10061 as_bad (_("-G may not be used with SVR4 or embedded PIC code"));
10065 g_switch_value
= atoi (arg
);
10070 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
10073 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10075 as_bad (_("-32 is supported for ELF format only"));
10078 mips_opts
.abi
= O32_ABI
;
10082 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10084 as_bad (_("-n32 is supported for ELF format only"));
10087 mips_opts
.abi
= N32_ABI
;
10091 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10093 as_bad (_("-64 is supported for ELF format only"));
10096 mips_opts
.abi
= N64_ABI
;
10097 if (! support_64bit_objects())
10098 as_fatal (_("No compiled in support for 64 bit object file format"));
10100 #endif /* OBJ_ELF */
10103 file_mips_gp32
= 1;
10104 if (mips_opts
.abi
!= O32_ABI
)
10105 mips_opts
.abi
= NO_ABI
;
10109 file_mips_gp32
= 0;
10110 if (mips_opts
.abi
== O32_ABI
)
10111 mips_opts
.abi
= NO_ABI
;
10115 file_mips_fp32
= 1;
10116 if (mips_opts
.abi
!= O32_ABI
)
10117 mips_opts
.abi
= NO_ABI
;
10122 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10124 as_bad (_("-mabi is supported for ELF format only"));
10127 if (strcmp (arg
, "32") == 0)
10128 mips_opts
.abi
= O32_ABI
;
10129 else if (strcmp (arg
, "o64") == 0)
10130 mips_opts
.abi
= O64_ABI
;
10131 else if (strcmp (arg
, "n32") == 0)
10132 mips_opts
.abi
= N32_ABI
;
10133 else if (strcmp (arg
, "64") == 0)
10135 mips_opts
.abi
= N64_ABI
;
10136 if (! support_64bit_objects())
10137 as_fatal (_("No compiled in support for 64 bit object file "
10140 else if (strcmp (arg
, "eabi") == 0)
10141 mips_opts
.abi
= EABI_ABI
;
10144 as_fatal (_("invalid abi -mabi=%s"), arg
);
10148 #endif /* OBJ_ELF */
10150 case OPTION_M7000_HILO_FIX
:
10151 mips_7000_hilo_fix
= true;
10154 case OPTION_NO_M7000_HILO_FIX
:
10155 mips_7000_hilo_fix
= false;
10166 show (stream
, string
, col_p
, first_p
)
10174 fprintf (stream
, "%24s", "");
10179 fprintf (stream
, ", ");
10183 if (*col_p
+ strlen (string
) > 72)
10185 fprintf (stream
, "\n%24s", "");
10189 fprintf (stream
, "%s", string
);
10190 *col_p
+= strlen (string
);
10196 md_show_usage (stream
)
10201 fprintf (stream
, _("\
10203 -membedded-pic generate embedded position independent code\n\
10204 -EB generate big endian output\n\
10205 -EL generate little endian output\n\
10206 -g, -g2 do not remove unneeded NOPs or swap branches\n\
10207 -G NUM allow referencing objects up to NUM bytes\n\
10208 implicitly with the gp register [default 8]\n"));
10209 fprintf (stream
, _("\
10210 -mips1 generate MIPS ISA I instructions\n\
10211 -mips2 generate MIPS ISA II instructions\n\
10212 -mips3 generate MIPS ISA III instructions\n\
10213 -mips4 generate MIPS ISA IV instructions\n\
10214 -mips5 generate MIPS ISA V instructions\n\
10215 -mips32 generate MIPS32 ISA instructions\n\
10216 -mips64 generate MIPS64 ISA instructions\n\
10217 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
10221 show (stream
, "2000", &column
, &first
);
10222 show (stream
, "3000", &column
, &first
);
10223 show (stream
, "3900", &column
, &first
);
10224 show (stream
, "4000", &column
, &first
);
10225 show (stream
, "4010", &column
, &first
);
10226 show (stream
, "4100", &column
, &first
);
10227 show (stream
, "4111", &column
, &first
);
10228 show (stream
, "4300", &column
, &first
);
10229 show (stream
, "4400", &column
, &first
);
10230 show (stream
, "4600", &column
, &first
);
10231 show (stream
, "4650", &column
, &first
);
10232 show (stream
, "5000", &column
, &first
);
10233 show (stream
, "5200", &column
, &first
);
10234 show (stream
, "5230", &column
, &first
);
10235 show (stream
, "5231", &column
, &first
);
10236 show (stream
, "5261", &column
, &first
);
10237 show (stream
, "5721", &column
, &first
);
10238 show (stream
, "6000", &column
, &first
);
10239 show (stream
, "8000", &column
, &first
);
10240 show (stream
, "10000", &column
, &first
);
10241 show (stream
, "12000", &column
, &first
);
10242 show (stream
, "sb1", &column
, &first
);
10243 fputc ('\n', stream
);
10245 fprintf (stream
, _("\
10246 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
10247 -no-mCPU don't generate code specific to CPU.\n\
10248 For -mCPU and -no-mCPU, CPU must be one of:\n"));
10252 show (stream
, "3900", &column
, &first
);
10253 show (stream
, "4010", &column
, &first
);
10254 show (stream
, "4100", &column
, &first
);
10255 show (stream
, "4650", &column
, &first
);
10256 fputc ('\n', stream
);
10258 fprintf (stream
, _("\
10259 -mips16 generate mips16 instructions\n\
10260 -no-mips16 do not generate mips16 instructions\n"));
10261 fprintf (stream
, _("\
10262 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
10263 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
10264 -O0 remove unneeded NOPs, do not swap branches\n\
10265 -O remove unneeded NOPs and swap branches\n\
10266 -n warn about NOPs generated from macros\n\
10267 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
10268 --trap, --no-break trap exception on div by 0 and mult overflow\n\
10269 --break, --no-trap break exception on div by 0 and mult overflow\n"));
10271 fprintf (stream
, _("\
10272 -KPIC, -call_shared generate SVR4 position independent code\n\
10273 -non_shared do not generate position independent code\n\
10274 -xgot assume a 32 bit GOT\n\
10275 -mabi=ABI create ABI conformant object file for:\n"));
10279 show (stream
, "32", &column
, &first
);
10280 show (stream
, "o64", &column
, &first
);
10281 show (stream
, "n32", &column
, &first
);
10282 show (stream
, "64", &column
, &first
);
10283 show (stream
, "eabi", &column
, &first
);
10285 fputc ('\n', stream
);
10287 fprintf (stream
, _("\
10288 -32 create o32 ABI object file (default)\n\
10289 -n32 create n32 ABI object file\n\
10290 -64 create 64 ABI object file\n"));
10295 mips_init_after_args ()
10297 /* initialize opcodes */
10298 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
10299 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
10303 md_pcrel_from (fixP
)
10306 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
10307 && fixP
->fx_addsy
!= (symbolS
*) NULL
10308 && ! S_IS_DEFINED (fixP
->fx_addsy
))
10310 /* This makes a branch to an undefined symbol be a branch to the
10311 current location. */
10312 if (mips_pic
== EMBEDDED_PIC
)
10318 /* return the address of the delay slot */
10319 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10322 /* This is called before the symbol table is processed. In order to
10323 work with gcc when using mips-tfile, we must keep all local labels.
10324 However, in other cases, we want to discard them. If we were
10325 called with -g, but we didn't see any debugging information, it may
10326 mean that gcc is smuggling debugging information through to
10327 mips-tfile, in which case we must generate all local labels. */
10330 mips_frob_file_before_adjust ()
10332 #ifndef NO_ECOFF_DEBUGGING
10333 if (ECOFF_DEBUGGING
10335 && ! ecoff_debugging_seen
)
10336 flag_keep_locals
= 1;
10340 /* Sort any unmatched HI16_S relocs so that they immediately precede
10341 the corresponding LO reloc. This is called before md_apply_fix3 and
10342 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
10343 explicit use of the %hi modifier. */
10348 struct mips_hi_fixup
*l
;
10350 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
10352 segment_info_type
*seginfo
;
10355 assert (l
->fixp
->fx_r_type
== BFD_RELOC_HI16_S
);
10357 /* Check quickly whether the next fixup happens to be a matching
10359 if (l
->fixp
->fx_next
!= NULL
10360 && l
->fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
10361 && l
->fixp
->fx_addsy
== l
->fixp
->fx_next
->fx_addsy
10362 && l
->fixp
->fx_offset
== l
->fixp
->fx_next
->fx_offset
)
10365 /* Look through the fixups for this segment for a matching %lo.
10366 When we find one, move the %hi just in front of it. We do
10367 this in two passes. In the first pass, we try to find a
10368 unique %lo. In the second pass, we permit multiple %hi
10369 relocs for a single %lo (this is a GNU extension). */
10370 seginfo
= seg_info (l
->seg
);
10371 for (pass
= 0; pass
< 2; pass
++)
10376 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
10378 /* Check whether this is a %lo fixup which matches l->fixp. */
10379 if (f
->fx_r_type
== BFD_RELOC_LO16
10380 && f
->fx_addsy
== l
->fixp
->fx_addsy
10381 && f
->fx_offset
== l
->fixp
->fx_offset
10384 || prev
->fx_r_type
!= BFD_RELOC_HI16_S
10385 || prev
->fx_addsy
!= f
->fx_addsy
10386 || prev
->fx_offset
!= f
->fx_offset
))
10390 /* Move l->fixp before f. */
10391 for (pf
= &seginfo
->fix_root
;
10393 pf
= &(*pf
)->fx_next
)
10394 assert (*pf
!= NULL
);
10396 *pf
= l
->fixp
->fx_next
;
10398 l
->fixp
->fx_next
= f
;
10400 seginfo
->fix_root
= l
->fixp
;
10402 prev
->fx_next
= l
->fixp
;
10413 #if 0 /* GCC code motion plus incomplete dead code elimination
10414 can leave a %hi without a %lo. */
10416 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
10417 _("Unmatched %%hi reloc"));
10423 /* When generating embedded PIC code we need to use a special
10424 relocation to represent the difference of two symbols in the .text
10425 section (switch tables use a difference of this sort). See
10426 include/coff/mips.h for details. This macro checks whether this
10427 fixup requires the special reloc. */
10428 #define SWITCH_TABLE(fixp) \
10429 ((fixp)->fx_r_type == BFD_RELOC_32 \
10430 && OUTPUT_FLAVOR != bfd_target_elf_flavour \
10431 && (fixp)->fx_addsy != NULL \
10432 && (fixp)->fx_subsy != NULL \
10433 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
10434 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
10436 /* When generating embedded PIC code we must keep all PC relative
10437 relocations, in case the linker has to relax a call. We also need
10438 to keep relocations for switch table entries.
10440 We may have combined relocations without symbols in the N32/N64 ABI.
10441 We have to prevent gas from dropping them. */
10444 mips_force_relocation (fixp
)
10447 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
10448 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
10452 && S_GET_SEGMENT (fixp
->fx_addsy
) == bfd_abs_section_ptr
10453 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_SUB
10454 || fixp
->fx_r_type
== BFD_RELOC_HI16_S
10455 || fixp
->fx_r_type
== BFD_RELOC_LO16
))
10458 return (mips_pic
== EMBEDDED_PIC
10460 || SWITCH_TABLE (fixp
)
10461 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
10462 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
10467 mips_need_elf_addend_fixup (fixP
)
10470 if (S_GET_OTHER (fixP
->fx_addsy
) == STO_MIPS16
)
10472 if (mips_pic
== EMBEDDED_PIC
10473 && S_IS_WEAK (fixP
->fx_addsy
))
10475 if (mips_pic
!= EMBEDDED_PIC
10476 && (S_IS_WEAK (fixP
->fx_addsy
)
10477 || S_IS_EXTERN (fixP
->fx_addsy
))
10478 && !S_IS_COMMON (fixP
->fx_addsy
))
10480 if (symbol_used_in_reloc_p (fixP
->fx_addsy
)
10481 && (((bfd_get_section_flags (stdoutput
,
10482 S_GET_SEGMENT (fixP
->fx_addsy
))
10483 & SEC_LINK_ONCE
) != 0)
10484 || !strncmp (segment_name (S_GET_SEGMENT (fixP
->fx_addsy
)),
10486 sizeof (".gnu.linkonce") - 1)))
10492 /* Apply a fixup to the object file. */
10495 md_apply_fix3 (fixP
, valP
, seg
)
10498 segT seg ATTRIBUTE_UNUSED
;
10504 assert (fixP
->fx_size
== 4
10505 || fixP
->fx_r_type
== BFD_RELOC_16
10506 || fixP
->fx_r_type
== BFD_RELOC_32
10507 || fixP
->fx_r_type
== BFD_RELOC_MIPS_JMP
10508 || fixP
->fx_r_type
== BFD_RELOC_HI16_S
10509 || fixP
->fx_r_type
== BFD_RELOC_LO16
10510 || fixP
->fx_r_type
== BFD_RELOC_GPREL16
10511 || fixP
->fx_r_type
== BFD_RELOC_MIPS_LITERAL
10512 || fixP
->fx_r_type
== BFD_RELOC_GPREL32
10513 || fixP
->fx_r_type
== BFD_RELOC_64
10514 || fixP
->fx_r_type
== BFD_RELOC_CTOR
10515 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
10516 || fixP
->fx_r_type
== BFD_RELOC_MIPS_HIGHEST
10517 || fixP
->fx_r_type
== BFD_RELOC_MIPS_HIGHER
10518 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SCN_DISP
10519 || fixP
->fx_r_type
== BFD_RELOC_MIPS_REL16
10520 || fixP
->fx_r_type
== BFD_RELOC_MIPS_RELGOT
10521 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
10522 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
);
10526 /* If we aren't adjusting this fixup to be against the section
10527 symbol, we need to adjust the value. */
10529 if (fixP
->fx_addsy
!= NULL
&& OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
10531 if (mips_need_elf_addend_fixup (fixP
))
10533 valueT symval
= S_GET_VALUE (fixP
->fx_addsy
);
10536 if (value
!= 0 && ! fixP
->fx_pcrel
)
10538 /* In this case, the bfd_install_relocation routine will
10539 incorrectly add the symbol value back in. We just want
10540 the addend to appear in the object file. */
10543 /* Make sure the addend is still non-zero. If it became zero
10544 after the last operation, set it to a spurious value and
10545 subtract the same value from the object file's contents. */
10550 /* The in-place addends for LO16 relocations are signed;
10551 leave the matching HI16 in-place addends as zero. */
10552 if (fixP
->fx_r_type
!= BFD_RELOC_HI16_S
)
10554 reloc_howto_type
*howto
;
10555 bfd_vma contents
, mask
, field
;
10557 howto
= bfd_reloc_type_lookup (stdoutput
,
10560 contents
= bfd_get_bits (fixP
->fx_frag
->fr_literal
10563 target_big_endian
);
10565 /* MASK has bits set where the relocation should go.
10566 FIELD is -value, shifted into the appropriate place
10567 for this relocation. */
10568 mask
= 1 << (howto
->bitsize
- 1);
10569 mask
= (((mask
- 1) << 1) | 1) << howto
->bitpos
;
10570 field
= (-value
>> howto
->rightshift
) << howto
->bitpos
;
10572 bfd_put_bits ((field
& mask
) | (contents
& ~mask
),
10573 fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
10575 target_big_endian
);
10581 /* This code was generated using trial and error and so is
10582 fragile and not trustworthy. If you change it, you should
10583 rerun the elf-rel, elf-rel2, and empic testcases and ensure
10584 they still pass. */
10585 if (fixP
->fx_pcrel
|| fixP
->fx_subsy
!= NULL
)
10587 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
10589 /* BFD's REL handling, for MIPS, is _very_ weird.
10590 This gives the right results, but it can't possibly
10591 be the way things are supposed to work. */
10592 if ((fixP
->fx_r_type
!= BFD_RELOC_16_PCREL
10593 && fixP
->fx_r_type
!= BFD_RELOC_16_PCREL_S2
)
10594 || S_GET_SEGMENT (fixP
->fx_addsy
) != undefined_section
)
10595 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
10600 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc. */
10602 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
)
10605 switch (fixP
->fx_r_type
)
10607 case BFD_RELOC_MIPS_JMP
:
10608 case BFD_RELOC_MIPS_SHIFT5
:
10609 case BFD_RELOC_MIPS_SHIFT6
:
10610 case BFD_RELOC_MIPS_GOT_DISP
:
10611 case BFD_RELOC_MIPS_GOT_PAGE
:
10612 case BFD_RELOC_MIPS_GOT_OFST
:
10613 case BFD_RELOC_MIPS_SUB
:
10614 case BFD_RELOC_MIPS_INSERT_A
:
10615 case BFD_RELOC_MIPS_INSERT_B
:
10616 case BFD_RELOC_MIPS_DELETE
:
10617 case BFD_RELOC_MIPS_HIGHEST
:
10618 case BFD_RELOC_MIPS_HIGHER
:
10619 case BFD_RELOC_MIPS_SCN_DISP
:
10620 case BFD_RELOC_MIPS_REL16
:
10621 case BFD_RELOC_MIPS_RELGOT
:
10622 case BFD_RELOC_MIPS_JALR
:
10623 case BFD_RELOC_HI16
:
10624 case BFD_RELOC_HI16_S
:
10625 case BFD_RELOC_GPREL16
:
10626 case BFD_RELOC_MIPS_LITERAL
:
10627 case BFD_RELOC_MIPS_CALL16
:
10628 case BFD_RELOC_MIPS_GOT16
:
10629 case BFD_RELOC_GPREL32
:
10630 case BFD_RELOC_MIPS_GOT_HI16
:
10631 case BFD_RELOC_MIPS_GOT_LO16
:
10632 case BFD_RELOC_MIPS_CALL_HI16
:
10633 case BFD_RELOC_MIPS_CALL_LO16
:
10634 case BFD_RELOC_MIPS16_GPREL
:
10635 if (fixP
->fx_pcrel
)
10636 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10637 _("Invalid PC relative reloc"));
10638 /* Nothing needed to do. The value comes from the reloc entry */
10641 case BFD_RELOC_MIPS16_JMP
:
10642 /* We currently always generate a reloc against a symbol, which
10643 means that we don't want an addend even if the symbol is
10645 fixP
->fx_addnumber
= 0;
10648 case BFD_RELOC_PCREL_HI16_S
:
10649 /* The addend for this is tricky if it is internal, so we just
10650 do everything here rather than in bfd_install_relocation. */
10651 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
10656 && (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_SECTION_SYM
) == 0)
10658 /* For an external symbol adjust by the address to make it
10659 pcrel_offset. We use the address of the RELLO reloc
10660 which follows this one. */
10661 value
+= (fixP
->fx_next
->fx_frag
->fr_address
10662 + fixP
->fx_next
->fx_where
);
10664 value
= ((value
+ 0x8000) >> 16) & 0xffff;
10665 buf
= (bfd_byte
*) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
10666 if (target_big_endian
)
10668 md_number_to_chars ((char *) buf
, value
, 2);
10671 case BFD_RELOC_PCREL_LO16
:
10672 /* The addend for this is tricky if it is internal, so we just
10673 do everything here rather than in bfd_install_relocation. */
10674 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
10679 && (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_SECTION_SYM
) == 0)
10680 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
10681 buf
= (bfd_byte
*) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
10682 if (target_big_endian
)
10684 md_number_to_chars ((char *) buf
, value
, 2);
10688 /* This is handled like BFD_RELOC_32, but we output a sign
10689 extended value if we are only 32 bits. */
10691 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
10693 if (8 <= sizeof (valueT
))
10694 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
10701 w1
= w2
= fixP
->fx_where
;
10702 if (target_big_endian
)
10706 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w1
, value
, 4);
10707 if ((value
& 0x80000000) != 0)
10711 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w2
, hiv
, 4);
10716 case BFD_RELOC_RVA
:
10718 /* If we are deleting this reloc entry, we must fill in the
10719 value now. This can happen if we have a .word which is not
10720 resolved when it appears but is later defined. We also need
10721 to fill in the value if this is an embedded PIC switch table
10724 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
10725 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
10730 /* If we are deleting this reloc entry, we must fill in the
10732 assert (fixP
->fx_size
== 2);
10734 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
10738 case BFD_RELOC_LO16
:
10739 /* When handling an embedded PIC switch statement, we can wind
10740 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
10743 if (value
+ 0x8000 > 0xffff)
10744 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10745 _("relocation overflow"));
10746 buf
= (bfd_byte
*) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
10747 if (target_big_endian
)
10749 md_number_to_chars ((char *) buf
, value
, 2);
10753 case BFD_RELOC_16_PCREL_S2
:
10754 if ((value
& 0x3) != 0)
10755 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10756 _("Branch to odd address (%lx)"), (long) value
);
10758 /* Fall through. */
10760 case BFD_RELOC_16_PCREL
:
10762 * We need to save the bits in the instruction since fixup_segment()
10763 * might be deleting the relocation entry (i.e., a branch within
10764 * the current segment).
10766 if (!fixP
->fx_done
&& value
!= 0)
10768 /* If 'value' is zero, the remaining reloc code won't actually
10769 do the store, so it must be done here. This is probably
10770 a bug somewhere. */
10772 && (fixP
->fx_r_type
!= BFD_RELOC_16_PCREL_S2
10773 || fixP
->fx_addsy
== NULL
/* ??? */
10774 || ! S_IS_DEFINED (fixP
->fx_addsy
)))
10775 value
-= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
10777 value
= (offsetT
) value
>> 2;
10779 /* update old instruction data */
10780 buf
= (bfd_byte
*) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
10781 if (target_big_endian
)
10782 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
10784 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
10786 if (value
+ 0x8000 <= 0xffff)
10787 insn
|= value
& 0xffff;
10790 /* The branch offset is too large. If this is an
10791 unconditional branch, and we are not generating PIC code,
10792 we can convert it to an absolute jump instruction. */
10793 if (mips_pic
== NO_PIC
10795 && fixP
->fx_frag
->fr_address
>= text_section
->vma
10796 && (fixP
->fx_frag
->fr_address
10797 < text_section
->vma
+ text_section
->_raw_size
)
10798 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
10799 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
10800 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
10802 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
10803 insn
= 0x0c000000; /* jal */
10805 insn
= 0x08000000; /* j */
10806 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
10808 fixP
->fx_addsy
= section_symbol (text_section
);
10809 fixP
->fx_addnumber
= (value
<< 2) + md_pcrel_from (fixP
);
10813 /* FIXME. It would be possible in principle to handle
10814 conditional branches which overflow. They could be
10815 transformed into a branch around a jump. This would
10816 require setting up variant frags for each different
10817 branch type. The native MIPS assembler attempts to
10818 handle these cases, but it appears to do it
10820 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10821 _("Branch out of range"));
10825 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
10828 case BFD_RELOC_VTABLE_INHERIT
:
10831 && !S_IS_DEFINED (fixP
->fx_addsy
)
10832 && !S_IS_WEAK (fixP
->fx_addsy
))
10833 S_SET_WEAK (fixP
->fx_addsy
);
10836 case BFD_RELOC_VTABLE_ENTRY
:
10850 const struct mips_opcode
*p
;
10851 int treg
, sreg
, dreg
, shamt
;
10856 for (i
= 0; i
< NUMOPCODES
; ++i
)
10858 p
= &mips_opcodes
[i
];
10859 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
10861 printf ("%08lx %s\t", oc
, p
->name
);
10862 treg
= (oc
>> 16) & 0x1f;
10863 sreg
= (oc
>> 21) & 0x1f;
10864 dreg
= (oc
>> 11) & 0x1f;
10865 shamt
= (oc
>> 6) & 0x1f;
10867 for (args
= p
->args
;; ++args
)
10878 printf ("%c", *args
);
10882 assert (treg
== sreg
);
10883 printf ("$%d,$%d", treg
, sreg
);
10888 printf ("$%d", dreg
);
10893 printf ("$%d", treg
);
10897 printf ("0x%x", treg
);
10902 printf ("$%d", sreg
);
10906 printf ("0x%08lx", oc
& 0x1ffffff);
10913 printf ("%d", imm
);
10918 printf ("$%d", shamt
);
10929 printf (_("%08lx UNDEFINED\n"), oc
);
10940 name
= input_line_pointer
;
10941 c
= get_symbol_end ();
10942 p
= (symbolS
*) symbol_find_or_make (name
);
10943 *input_line_pointer
= c
;
10947 /* Align the current frag to a given power of two. The MIPS assembler
10948 also automatically adjusts any preceding label. */
10951 mips_align (to
, fill
, label
)
10956 mips_emit_delays (false);
10957 frag_align (to
, fill
, 0);
10958 record_alignment (now_seg
, to
);
10961 assert (S_GET_SEGMENT (label
) == now_seg
);
10962 symbol_set_frag (label
, frag_now
);
10963 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
10967 /* Align to a given power of two. .align 0 turns off the automatic
10968 alignment used by the data creating pseudo-ops. */
10972 int x ATTRIBUTE_UNUSED
;
10975 register long temp_fill
;
10976 long max_alignment
= 15;
10980 o Note that the assembler pulls down any immediately preceeding label
10981 to the aligned address.
10982 o It's not documented but auto alignment is reinstated by
10983 a .align pseudo instruction.
10984 o Note also that after auto alignment is turned off the mips assembler
10985 issues an error on attempt to assemble an improperly aligned data item.
10990 temp
= get_absolute_expression ();
10991 if (temp
> max_alignment
)
10992 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
10995 as_warn (_("Alignment negative: 0 assumed."));
10998 if (*input_line_pointer
== ',')
11000 input_line_pointer
++;
11001 temp_fill
= get_absolute_expression ();
11008 mips_align (temp
, (int) temp_fill
,
11009 insn_labels
!= NULL
? insn_labels
->label
: NULL
);
11016 demand_empty_rest_of_line ();
11020 mips_flush_pending_output ()
11022 mips_emit_delays (false);
11023 mips_clear_insn_labels ();
11032 /* When generating embedded PIC code, we only use the .text, .lit8,
11033 .sdata and .sbss sections. We change the .data and .rdata
11034 pseudo-ops to use .sdata. */
11035 if (mips_pic
== EMBEDDED_PIC
11036 && (sec
== 'd' || sec
== 'r'))
11040 /* The ELF backend needs to know that we are changing sections, so
11041 that .previous works correctly. We could do something like check
11042 for an obj_section_change_hook macro, but that might be confusing
11043 as it would not be appropriate to use it in the section changing
11044 functions in read.c, since obj-elf.c intercepts those. FIXME:
11045 This should be cleaner, somehow. */
11046 obj_elf_section_change_hook ();
11049 mips_emit_delays (false);
11059 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
11060 demand_empty_rest_of_line ();
11064 if (USE_GLOBAL_POINTER_OPT
)
11066 seg
= subseg_new (RDATA_SECTION_NAME
,
11067 (subsegT
) get_absolute_expression ());
11068 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11070 bfd_set_section_flags (stdoutput
, seg
,
11076 if (strcmp (TARGET_OS
, "elf") != 0)
11077 record_alignment (seg
, 4);
11079 demand_empty_rest_of_line ();
11083 as_bad (_("No read only data section in this object file format"));
11084 demand_empty_rest_of_line ();
11090 if (USE_GLOBAL_POINTER_OPT
)
11092 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
11093 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11095 bfd_set_section_flags (stdoutput
, seg
,
11096 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
11098 if (strcmp (TARGET_OS
, "elf") != 0)
11099 record_alignment (seg
, 4);
11101 demand_empty_rest_of_line ();
11106 as_bad (_("Global pointers not supported; recompile -G 0"));
11107 demand_empty_rest_of_line ();
11116 mips_enable_auto_align ()
11127 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11128 mips_emit_delays (false);
11129 if (log_size
> 0 && auto_align
)
11130 mips_align (log_size
, 0, label
);
11131 mips_clear_insn_labels ();
11132 cons (1 << log_size
);
11136 s_float_cons (type
)
11141 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11143 mips_emit_delays (false);
11148 mips_align (3, 0, label
);
11150 mips_align (2, 0, label
);
11153 mips_clear_insn_labels ();
11158 /* Handle .globl. We need to override it because on Irix 5 you are
11161 where foo is an undefined symbol, to mean that foo should be
11162 considered to be the address of a function. */
11166 int x ATTRIBUTE_UNUSED
;
11173 name
= input_line_pointer
;
11174 c
= get_symbol_end ();
11175 symbolP
= symbol_find_or_make (name
);
11176 *input_line_pointer
= c
;
11177 SKIP_WHITESPACE ();
11179 /* On Irix 5, every global symbol that is not explicitly labelled as
11180 being a function is apparently labelled as being an object. */
11183 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
11188 secname
= input_line_pointer
;
11189 c
= get_symbol_end ();
11190 sec
= bfd_get_section_by_name (stdoutput
, secname
);
11192 as_bad (_("%s: no such section"), secname
);
11193 *input_line_pointer
= c
;
11195 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
11196 flag
= BSF_FUNCTION
;
11199 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
11201 S_SET_EXTERNAL (symbolP
);
11202 demand_empty_rest_of_line ();
11207 int x ATTRIBUTE_UNUSED
;
11212 opt
= input_line_pointer
;
11213 c
= get_symbol_end ();
11217 /* FIXME: What does this mean? */
11219 else if (strncmp (opt
, "pic", 3) == 0)
11223 i
= atoi (opt
+ 3);
11227 mips_pic
= SVR4_PIC
;
11229 as_bad (_(".option pic%d not supported"), i
);
11231 if (USE_GLOBAL_POINTER_OPT
&& mips_pic
== SVR4_PIC
)
11233 if (g_switch_seen
&& g_switch_value
!= 0)
11234 as_warn (_("-G may not be used with SVR4 PIC code"));
11235 g_switch_value
= 0;
11236 bfd_set_gp_size (stdoutput
, 0);
11240 as_warn (_("Unrecognized option \"%s\""), opt
);
11242 *input_line_pointer
= c
;
11243 demand_empty_rest_of_line ();
11246 /* This structure is used to hold a stack of .set values. */
11248 struct mips_option_stack
11250 struct mips_option_stack
*next
;
11251 struct mips_set_options options
;
11254 static struct mips_option_stack
*mips_opts_stack
;
11256 /* Handle the .set pseudo-op. */
11260 int x ATTRIBUTE_UNUSED
;
11262 char *name
= input_line_pointer
, ch
;
11264 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
11265 input_line_pointer
++;
11266 ch
= *input_line_pointer
;
11267 *input_line_pointer
= '\0';
11269 if (strcmp (name
, "reorder") == 0)
11271 if (mips_opts
.noreorder
&& prev_nop_frag
!= NULL
)
11273 /* If we still have pending nops, we can discard them. The
11274 usual nop handling will insert any that are still
11276 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
11277 * (mips_opts
.mips16
? 2 : 4));
11278 prev_nop_frag
= NULL
;
11280 mips_opts
.noreorder
= 0;
11282 else if (strcmp (name
, "noreorder") == 0)
11284 mips_emit_delays (true);
11285 mips_opts
.noreorder
= 1;
11286 mips_any_noreorder
= 1;
11288 else if (strcmp (name
, "at") == 0)
11290 mips_opts
.noat
= 0;
11292 else if (strcmp (name
, "noat") == 0)
11294 mips_opts
.noat
= 1;
11296 else if (strcmp (name
, "macro") == 0)
11298 mips_opts
.warn_about_macros
= 0;
11300 else if (strcmp (name
, "nomacro") == 0)
11302 if (mips_opts
.noreorder
== 0)
11303 as_bad (_("`noreorder' must be set before `nomacro'"));
11304 mips_opts
.warn_about_macros
= 1;
11306 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
11308 mips_opts
.nomove
= 0;
11310 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
11312 mips_opts
.nomove
= 1;
11314 else if (strcmp (name
, "bopt") == 0)
11316 mips_opts
.nobopt
= 0;
11318 else if (strcmp (name
, "nobopt") == 0)
11320 mips_opts
.nobopt
= 1;
11322 else if (strcmp (name
, "mips16") == 0
11323 || strcmp (name
, "MIPS-16") == 0)
11324 mips_opts
.mips16
= 1;
11325 else if (strcmp (name
, "nomips16") == 0
11326 || strcmp (name
, "noMIPS-16") == 0)
11327 mips_opts
.mips16
= 0;
11328 else if (strcmp (name
, "mips3d") == 0)
11329 mips_opts
.ase_mips3d
= 1;
11330 else if (strcmp (name
, "nomips3d") == 0)
11331 mips_opts
.ase_mips3d
= 0;
11332 else if (strncmp (name
, "mips", 4) == 0)
11336 /* Permit the user to change the ISA on the fly. Needless to
11337 say, misuse can cause serious problems. */
11338 isa
= atoi (name
+ 4);
11342 mips_opts
.gp32
= file_mips_gp32
;
11343 mips_opts
.fp32
= file_mips_fp32
;
11344 mips_opts
.abi
= file_mips_abi
;
11349 mips_opts
.gp32
= 1;
11350 mips_opts
.fp32
= 1;
11356 /* Loosen ABI register width restriction. */
11357 if (mips_opts
.abi
== O32_ABI
)
11358 mips_opts
.abi
= NO_ABI
;
11359 mips_opts
.gp32
= 0;
11360 mips_opts
.fp32
= 0;
11363 as_bad (_("unknown ISA level %s"), name
+ 4);
11369 case 0: mips_opts
.isa
= file_mips_isa
; break;
11370 case 1: mips_opts
.isa
= ISA_MIPS1
; break;
11371 case 2: mips_opts
.isa
= ISA_MIPS2
; break;
11372 case 3: mips_opts
.isa
= ISA_MIPS3
; break;
11373 case 4: mips_opts
.isa
= ISA_MIPS4
; break;
11374 case 5: mips_opts
.isa
= ISA_MIPS5
; break;
11375 case 32: mips_opts
.isa
= ISA_MIPS32
; break;
11376 case 64: mips_opts
.isa
= ISA_MIPS64
; break;
11377 default: as_bad (_("unknown ISA level %s"), name
+ 4); break;
11380 else if (strcmp (name
, "autoextend") == 0)
11381 mips_opts
.noautoextend
= 0;
11382 else if (strcmp (name
, "noautoextend") == 0)
11383 mips_opts
.noautoextend
= 1;
11384 else if (strcmp (name
, "push") == 0)
11386 struct mips_option_stack
*s
;
11388 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
11389 s
->next
= mips_opts_stack
;
11390 s
->options
= mips_opts
;
11391 mips_opts_stack
= s
;
11393 else if (strcmp (name
, "pop") == 0)
11395 struct mips_option_stack
*s
;
11397 s
= mips_opts_stack
;
11399 as_bad (_(".set pop with no .set push"));
11402 /* If we're changing the reorder mode we need to handle
11403 delay slots correctly. */
11404 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
11405 mips_emit_delays (true);
11406 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
11408 if (prev_nop_frag
!= NULL
)
11410 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
11411 * (mips_opts
.mips16
? 2 : 4));
11412 prev_nop_frag
= NULL
;
11416 mips_opts
= s
->options
;
11417 mips_opts_stack
= s
->next
;
11423 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
11425 *input_line_pointer
= ch
;
11426 demand_empty_rest_of_line ();
11429 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
11430 .option pic2. It means to generate SVR4 PIC calls. */
11433 s_abicalls (ignore
)
11434 int ignore ATTRIBUTE_UNUSED
;
11436 mips_pic
= SVR4_PIC
;
11437 if (USE_GLOBAL_POINTER_OPT
)
11439 if (g_switch_seen
&& g_switch_value
!= 0)
11440 as_warn (_("-G may not be used with SVR4 PIC code"));
11441 g_switch_value
= 0;
11443 bfd_set_gp_size (stdoutput
, 0);
11444 demand_empty_rest_of_line ();
11447 /* Handle the .cpload pseudo-op. This is used when generating SVR4
11448 PIC code. It sets the $gp register for the function based on the
11449 function address, which is in the register named in the argument.
11450 This uses a relocation against _gp_disp, which is handled specially
11451 by the linker. The result is:
11452 lui $gp,%hi(_gp_disp)
11453 addiu $gp,$gp,%lo(_gp_disp)
11454 addu $gp,$gp,.cpload argument
11455 The .cpload argument is normally $25 == $t9. */
11459 int ignore ATTRIBUTE_UNUSED
;
11464 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
11465 .cpload is ignored. */
11466 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
11472 /* .cpload should be in a .set noreorder section. */
11473 if (mips_opts
.noreorder
== 0)
11474 as_warn (_(".cpload not in noreorder section"));
11476 ex
.X_op
= O_symbol
;
11477 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
11478 ex
.X_op_symbol
= NULL
;
11479 ex
.X_add_number
= 0;
11481 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
11482 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
11484 macro_build_lui (NULL
, &icnt
, &ex
, GP
);
11485 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j", GP
, GP
,
11486 (int) BFD_RELOC_LO16
);
11488 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
11489 GP
, GP
, tc_get_register (0));
11491 demand_empty_rest_of_line ();
11494 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
11495 .cpsetup $reg1, offset|$reg2, label
11497 If offset is given, this results in:
11498 sd $gp, offset($sp)
11499 lui $gp, %hi(%neg(%gp_rel(label)))
11500 daddiu $gp, $gp, %lo(%neg(%gp_rel(label)))
11501 addu $gp, $gp, $reg1
11503 If $reg2 is given, this results in:
11504 daddu $reg2, $gp, $0
11505 lui $gp, %hi(%neg(%gp_rel(label)))
11506 daddiu $gp, $gp, %lo(%neg(%gp_rel(label)))
11507 addu $gp, $gp, $reg1
11511 int ignore ATTRIBUTE_UNUSED
;
11513 expressionS ex_off
;
11514 expressionS ex_sym
;
11519 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
11520 We also need NewABI support. */
11521 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
11527 reg1
= tc_get_register (0);
11528 SKIP_WHITESPACE ();
11529 if (*input_line_pointer
!= ',')
11531 as_bad (_("missing argument separator ',' for .cpsetup"));
11535 input_line_pointer
++;
11536 SKIP_WHITESPACE ();
11537 if (*input_line_pointer
== '$')
11538 mips_cpreturn_register
= tc_get_register (0);
11540 mips_cpreturn_offset
= get_absolute_expression ();
11541 SKIP_WHITESPACE ();
11542 if (*input_line_pointer
!= ',')
11544 as_bad (_("missing argument separator ',' for .cpsetup"));
11548 input_line_pointer
++;
11549 SKIP_WHITESPACE ();
11550 sym
= input_line_pointer
;
11551 while (ISALNUM (*input_line_pointer
))
11552 input_line_pointer
++;
11553 *input_line_pointer
= 0;
11555 ex_sym
.X_op
= O_symbol
;
11556 ex_sym
.X_add_symbol
= symbol_find_or_make (sym
);
11557 ex_sym
.X_op_symbol
= NULL
;
11558 ex_sym
.X_add_number
= 0;
11560 if (mips_cpreturn_register
== -1)
11562 ex_off
.X_op
= O_constant
;
11563 ex_off
.X_add_symbol
= NULL
;
11564 ex_off
.X_op_symbol
= NULL
;
11565 ex_off
.X_add_number
= mips_cpreturn_offset
;
11567 macro_build ((char *) NULL
, &icnt
, &ex_off
, "sd", "t,o(b)",
11568 mips_gp_register
, (int) BFD_RELOC_LO16
, SP
);
11571 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "daddu",
11572 "d,v,t", mips_cpreturn_register
, mips_gp_register
, 0);
11574 macro_build ((char *) NULL
, &icnt
, &ex_sym
, "lui", "t,u", mips_gp_register
,
11575 (int) BFD_RELOC_GPREL16
);
11576 fix_new (frag_now
, prev_insn_where
, 0, NULL
, 0, 0, BFD_RELOC_MIPS_SUB
);
11577 fix_new (frag_now
, prev_insn_where
, 0, NULL
, 0, 0, BFD_RELOC_HI16_S
);
11578 macro_build ((char *) NULL
, &icnt
, &ex_sym
, "addiu", "t,r,j",
11579 mips_gp_register
, mips_gp_register
, (int) BFD_RELOC_GPREL16
);
11580 fix_new (frag_now
, prev_insn_where
, 0, NULL
, 0, 0, BFD_RELOC_MIPS_SUB
);
11581 fix_new (frag_now
, prev_insn_where
, 0, NULL
, 0, 0, BFD_RELOC_LO16
);
11582 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
11583 HAVE_64BIT_ADDRESSES
? "daddu" : "addu", "d,v,t",
11584 mips_gp_register
, mips_gp_register
, reg1
);
11586 demand_empty_rest_of_line ();
11591 int ignore ATTRIBUTE_UNUSED
;
11593 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
11594 .cplocal is ignored. */
11595 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
11601 mips_gp_register
= tc_get_register (0);
11604 /* Handle the .cprestore pseudo-op. This stores $gp into a given
11605 offset from $sp. The offset is remembered, and after making a PIC
11606 call $gp is restored from that location. */
11609 s_cprestore (ignore
)
11610 int ignore ATTRIBUTE_UNUSED
;
11615 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
11616 .cprestore is ignored. */
11617 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
11623 mips_cprestore_offset
= get_absolute_expression ();
11624 mips_cprestore_valid
= 1;
11626 ex
.X_op
= O_constant
;
11627 ex
.X_add_symbol
= NULL
;
11628 ex
.X_op_symbol
= NULL
;
11629 ex
.X_add_number
= mips_cprestore_offset
;
11631 macro_build ((char *) NULL
, &icnt
, &ex
,
11632 HAVE_32BIT_ADDRESSES
? "sw" : "sd",
11633 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, SP
);
11635 demand_empty_rest_of_line ();
11638 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
11639 was given in the preceeding .gpsetup, it results in:
11640 ld $gp, offset($sp)
11642 If a register $reg2 was given there, it results in:
11643 daddiu $gp, $gp, $reg2
11646 s_cpreturn (ignore
)
11647 int ignore ATTRIBUTE_UNUSED
;
11652 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
11653 We also need NewABI support. */
11654 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
11660 if (mips_cpreturn_register
== -1)
11662 ex
.X_op
= O_constant
;
11663 ex
.X_add_symbol
= NULL
;
11664 ex
.X_op_symbol
= NULL
;
11665 ex
.X_add_number
= mips_cpreturn_offset
;
11667 macro_build ((char *) NULL
, &icnt
, &ex
, "ld", "t,o(b)",
11668 mips_gp_register
, (int) BFD_RELOC_LO16
, SP
);
11671 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "daddu",
11672 "d,v,t", mips_gp_register
, mips_cpreturn_register
, 0);
11674 demand_empty_rest_of_line ();
11677 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
11678 code. It sets the offset to use in gp_rel relocations. */
11682 int ignore ATTRIBUTE_UNUSED
;
11684 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
11685 We also need NewABI support. */
11686 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
11692 mips_cpreturn_offset
= get_absolute_expression ();
11694 demand_empty_rest_of_line ();
11697 /* Handle the .gpword pseudo-op. This is used when generating PIC
11698 code. It generates a 32 bit GP relative reloc. */
11702 int ignore ATTRIBUTE_UNUSED
;
11708 /* When not generating PIC code, this is treated as .word. */
11709 if (mips_pic
!= SVR4_PIC
)
11715 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11716 mips_emit_delays (true);
11718 mips_align (2, 0, label
);
11719 mips_clear_insn_labels ();
11723 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
11725 as_bad (_("Unsupported use of .gpword"));
11726 ignore_rest_of_line ();
11730 md_number_to_chars (p
, (valueT
) 0, 4);
11731 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, 0,
11732 BFD_RELOC_GPREL32
);
11734 demand_empty_rest_of_line ();
11737 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
11738 tables in SVR4 PIC code. */
11742 int ignore ATTRIBUTE_UNUSED
;
11747 /* This is ignored when not generating SVR4 PIC code or if this is NewABI
11749 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
11755 /* Add $gp to the register named as an argument. */
11756 reg
= tc_get_register (0);
11757 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
11758 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
11759 "d,v,t", reg
, reg
, GP
);
11761 demand_empty_rest_of_line ();
11764 /* Handle the .insn pseudo-op. This marks instruction labels in
11765 mips16 mode. This permits the linker to handle them specially,
11766 such as generating jalx instructions when needed. We also make
11767 them odd for the duration of the assembly, in order to generate the
11768 right sort of code. We will make them even in the adjust_symtab
11769 routine, while leaving them marked. This is convenient for the
11770 debugger and the disassembler. The linker knows to make them odd
11775 int ignore ATTRIBUTE_UNUSED
;
11777 if (mips_opts
.mips16
)
11778 mips16_mark_labels ();
11780 demand_empty_rest_of_line ();
11783 /* Handle a .stabn directive. We need these in order to mark a label
11784 as being a mips16 text label correctly. Sometimes the compiler
11785 will emit a label, followed by a .stabn, and then switch sections.
11786 If the label and .stabn are in mips16 mode, then the label is
11787 really a mips16 text label. */
11793 if (type
== 'n' && mips_opts
.mips16
)
11794 mips16_mark_labels ();
11799 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
11803 s_mips_weakext (ignore
)
11804 int ignore ATTRIBUTE_UNUSED
;
11811 name
= input_line_pointer
;
11812 c
= get_symbol_end ();
11813 symbolP
= symbol_find_or_make (name
);
11814 S_SET_WEAK (symbolP
);
11815 *input_line_pointer
= c
;
11817 SKIP_WHITESPACE ();
11819 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
11821 if (S_IS_DEFINED (symbolP
))
11823 as_bad ("ignoring attempt to redefine symbol %s",
11824 S_GET_NAME (symbolP
));
11825 ignore_rest_of_line ();
11829 if (*input_line_pointer
== ',')
11831 ++input_line_pointer
;
11832 SKIP_WHITESPACE ();
11836 if (exp
.X_op
!= O_symbol
)
11838 as_bad ("bad .weakext directive");
11839 ignore_rest_of_line ();
11842 symbol_set_value_expression (symbolP
, &exp
);
11845 demand_empty_rest_of_line ();
11848 /* Parse a register string into a number. Called from the ECOFF code
11849 to parse .frame. The argument is non-zero if this is the frame
11850 register, so that we can record it in mips_frame_reg. */
11853 tc_get_register (frame
)
11858 SKIP_WHITESPACE ();
11859 if (*input_line_pointer
++ != '$')
11861 as_warn (_("expected `$'"));
11864 else if (ISDIGIT (*input_line_pointer
))
11866 reg
= get_absolute_expression ();
11867 if (reg
< 0 || reg
>= 32)
11869 as_warn (_("Bad register number"));
11875 if (strncmp (input_line_pointer
, "fp", 2) == 0)
11877 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
11879 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
11881 else if (strncmp (input_line_pointer
, "at", 2) == 0)
11885 as_warn (_("Unrecognized register name"));
11888 input_line_pointer
+= 2;
11892 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
11893 mips_frame_reg_valid
= 1;
11894 mips_cprestore_valid
= 0;
11900 md_section_align (seg
, addr
)
11904 int align
= bfd_get_section_alignment (stdoutput
, seg
);
11907 /* We don't need to align ELF sections to the full alignment.
11908 However, Irix 5 may prefer that we align them at least to a 16
11909 byte boundary. We don't bother to align the sections if we are
11910 targeted for an embedded system. */
11911 if (strcmp (TARGET_OS
, "elf") == 0)
11917 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
11920 /* Utility routine, called from above as well. If called while the
11921 input file is still being read, it's only an approximation. (For
11922 example, a symbol may later become defined which appeared to be
11923 undefined earlier.) */
11926 nopic_need_relax (sym
, before_relaxing
)
11928 int before_relaxing
;
11933 if (USE_GLOBAL_POINTER_OPT
&& g_switch_value
> 0)
11935 const char *symname
;
11938 /* Find out whether this symbol can be referenced off the GP
11939 register. It can be if it is smaller than the -G size or if
11940 it is in the .sdata or .sbss section. Certain symbols can
11941 not be referenced off the GP, although it appears as though
11943 symname
= S_GET_NAME (sym
);
11944 if (symname
!= (const char *) NULL
11945 && (strcmp (symname
, "eprol") == 0
11946 || strcmp (symname
, "etext") == 0
11947 || strcmp (symname
, "_gp") == 0
11948 || strcmp (symname
, "edata") == 0
11949 || strcmp (symname
, "_fbss") == 0
11950 || strcmp (symname
, "_fdata") == 0
11951 || strcmp (symname
, "_ftext") == 0
11952 || strcmp (symname
, "end") == 0
11953 || strcmp (symname
, "_gp_disp") == 0))
11955 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
11957 #ifndef NO_ECOFF_DEBUGGING
11958 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
11959 && (symbol_get_obj (sym
)->ecoff_extern_size
11960 <= g_switch_value
))
11962 /* We must defer this decision until after the whole
11963 file has been read, since there might be a .extern
11964 after the first use of this symbol. */
11965 || (before_relaxing
11966 #ifndef NO_ECOFF_DEBUGGING
11967 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
11969 && S_GET_VALUE (sym
) == 0)
11970 || (S_GET_VALUE (sym
) != 0
11971 && S_GET_VALUE (sym
) <= g_switch_value
)))
11975 const char *segname
;
11977 segname
= segment_name (S_GET_SEGMENT (sym
));
11978 assert (strcmp (segname
, ".lit8") != 0
11979 && strcmp (segname
, ".lit4") != 0);
11980 change
= (strcmp (segname
, ".sdata") != 0
11981 && strcmp (segname
, ".sbss") != 0
11982 && strncmp (segname
, ".sdata.", 7) != 0
11983 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
11988 /* We are not optimizing for the GP register. */
11992 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
11993 extended opcode. SEC is the section the frag is in. */
11996 mips16_extended_frag (fragp
, sec
, stretch
)
12002 register const struct mips16_immed_operand
*op
;
12004 int mintiny
, maxtiny
;
12008 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
12010 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
12013 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
12014 op
= mips16_immed_operands
;
12015 while (op
->type
!= type
)
12018 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
12023 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
12026 maxtiny
= 1 << op
->nbits
;
12031 maxtiny
= (1 << op
->nbits
) - 1;
12036 mintiny
= - (1 << (op
->nbits
- 1));
12037 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
12040 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
12041 val
= S_GET_VALUE (fragp
->fr_symbol
);
12042 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
12048 /* We won't have the section when we are called from
12049 mips_relax_frag. However, we will always have been called
12050 from md_estimate_size_before_relax first. If this is a
12051 branch to a different section, we mark it as such. If SEC is
12052 NULL, and the frag is not marked, then it must be a branch to
12053 the same section. */
12056 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
12061 /* Must have been called from md_estimate_size_before_relax. */
12064 fragp
->fr_subtype
=
12065 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12067 /* FIXME: We should support this, and let the linker
12068 catch branches and loads that are out of range. */
12069 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
12070 _("unsupported PC relative reference to different section"));
12074 if (fragp
!= sym_frag
&& sym_frag
->fr_address
== 0)
12075 /* Assume non-extended on the first relaxation pass.
12076 The address we have calculated will be bogus if this is
12077 a forward branch to another frag, as the forward frag
12078 will have fr_address == 0. */
12082 /* In this case, we know for sure that the symbol fragment is in
12083 the same section. If the relax_marker of the symbol fragment
12084 differs from the relax_marker of this fragment, we have not
12085 yet adjusted the symbol fragment fr_address. We want to add
12086 in STRETCH in order to get a better estimate of the address.
12087 This particularly matters because of the shift bits. */
12089 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
12093 /* Adjust stretch for any alignment frag. Note that if have
12094 been expanding the earlier code, the symbol may be
12095 defined in what appears to be an earlier frag. FIXME:
12096 This doesn't handle the fr_subtype field, which specifies
12097 a maximum number of bytes to skip when doing an
12099 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
12101 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
12104 stretch
= - ((- stretch
)
12105 & ~ ((1 << (int) f
->fr_offset
) - 1));
12107 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
12116 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
12118 /* The base address rules are complicated. The base address of
12119 a branch is the following instruction. The base address of a
12120 PC relative load or add is the instruction itself, but if it
12121 is in a delay slot (in which case it can not be extended) use
12122 the address of the instruction whose delay slot it is in. */
12123 if (type
== 'p' || type
== 'q')
12127 /* If we are currently assuming that this frag should be
12128 extended, then, the current address is two bytes
12130 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12133 /* Ignore the low bit in the target, since it will be set
12134 for a text label. */
12135 if ((val
& 1) != 0)
12138 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
12140 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
12143 val
-= addr
& ~ ((1 << op
->shift
) - 1);
12145 /* Branch offsets have an implicit 0 in the lowest bit. */
12146 if (type
== 'p' || type
== 'q')
12149 /* If any of the shifted bits are set, we must use an extended
12150 opcode. If the address depends on the size of this
12151 instruction, this can lead to a loop, so we arrange to always
12152 use an extended opcode. We only check this when we are in
12153 the main relaxation loop, when SEC is NULL. */
12154 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
12156 fragp
->fr_subtype
=
12157 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12161 /* If we are about to mark a frag as extended because the value
12162 is precisely maxtiny + 1, then there is a chance of an
12163 infinite loop as in the following code:
12168 In this case when the la is extended, foo is 0x3fc bytes
12169 away, so the la can be shrunk, but then foo is 0x400 away, so
12170 the la must be extended. To avoid this loop, we mark the
12171 frag as extended if it was small, and is about to become
12172 extended with a value of maxtiny + 1. */
12173 if (val
== ((maxtiny
+ 1) << op
->shift
)
12174 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
12177 fragp
->fr_subtype
=
12178 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12182 else if (symsec
!= absolute_section
&& sec
!= NULL
)
12183 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
12185 if ((val
& ((1 << op
->shift
) - 1)) != 0
12186 || val
< (mintiny
<< op
->shift
)
12187 || val
> (maxtiny
<< op
->shift
))
12193 /* Estimate the size of a frag before relaxing. Unless this is the
12194 mips16, we are not really relaxing here, and the final size is
12195 encoded in the subtype information. For the mips16, we have to
12196 decide whether we are using an extended opcode or not. */
12199 md_estimate_size_before_relax (fragp
, segtype
)
12204 boolean linkonce
= false;
12206 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
12207 /* We don't want to modify the EXTENDED bit here; it might get us
12208 into infinite loops. We change it only in mips_relax_frag(). */
12209 return (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2);
12211 if (mips_pic
== NO_PIC
)
12213 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
12215 else if (mips_pic
== SVR4_PIC
)
12220 sym
= fragp
->fr_symbol
;
12222 /* Handle the case of a symbol equated to another symbol. */
12223 while (symbol_equated_reloc_p (sym
))
12227 /* It's possible to get a loop here in a badly written
12229 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
12235 symsec
= S_GET_SEGMENT (sym
);
12237 /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
12238 if (symsec
!= segtype
&& ! S_IS_LOCAL (sym
))
12240 if ((bfd_get_section_flags (stdoutput
, symsec
) & SEC_LINK_ONCE
)
12244 /* The GNU toolchain uses an extension for ELF: a section
12245 beginning with the magic string .gnu.linkonce is a linkonce
12247 if (strncmp (segment_name (symsec
), ".gnu.linkonce",
12248 sizeof ".gnu.linkonce" - 1) == 0)
12252 /* This must duplicate the test in adjust_reloc_syms. */
12253 change
= (symsec
!= &bfd_und_section
12254 && symsec
!= &bfd_abs_section
12255 && ! bfd_is_com_section (symsec
)
12258 /* A global or weak symbol is treated as external. */
12259 && (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
12260 || (! S_IS_WEAK (sym
)
12261 && (! S_IS_EXTERN (sym
) || mips_pic
== EMBEDDED_PIC
)))
12270 /* Record the offset to the first reloc in the fr_opcode field.
12271 This lets md_convert_frag and tc_gen_reloc know that the code
12272 must be expanded. */
12273 fragp
->fr_opcode
= (fragp
->fr_literal
12275 - RELAX_OLD (fragp
->fr_subtype
)
12276 + RELAX_RELOC1 (fragp
->fr_subtype
));
12277 /* FIXME: This really needs as_warn_where. */
12278 if (RELAX_WARN (fragp
->fr_subtype
))
12279 as_warn (_("AT used after \".set noat\" or macro used after "
12280 "\".set nomacro\""));
12282 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
12288 /* This is called to see whether a reloc against a defined symbol
12289 should be converted into a reloc against a section. Don't adjust
12290 MIPS16 jump relocations, so we don't have to worry about the format
12291 of the offset in the .o file. Don't adjust relocations against
12292 mips16 symbols, so that the linker can find them if it needs to set
12296 mips_fix_adjustable (fixp
)
12300 /* Prevent all adjustments to global symbols. */
12301 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
12302 && mips_pic
!= EMBEDDED_PIC
12303 && (S_IS_EXTERN (fixp
->fx_addsy
) || S_IS_WEAK (fixp
->fx_addsy
)))
12306 if (fixp
->fx_r_type
== BFD_RELOC_MIPS16_JMP
)
12308 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
12309 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
12311 if (fixp
->fx_addsy
== NULL
)
12314 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
12315 && S_GET_OTHER (fixp
->fx_addsy
) == STO_MIPS16
12316 && fixp
->fx_subsy
== NULL
)
12322 /* Translate internal representation of relocation info to BFD target
12326 tc_gen_reloc (section
, fixp
)
12327 asection
*section ATTRIBUTE_UNUSED
;
12330 static arelent
*retval
[4];
12332 bfd_reloc_code_real_type code
;
12334 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
12337 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
12338 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
12339 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
12341 if (mips_pic
== EMBEDDED_PIC
12342 && SWITCH_TABLE (fixp
))
12344 /* For a switch table entry we use a special reloc. The addend
12345 is actually the difference between the reloc address and the
12347 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
12348 if (OUTPUT_FLAVOR
!= bfd_target_ecoff_flavour
)
12349 as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc"));
12350 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
12352 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
12354 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
12355 reloc
->addend
= fixp
->fx_addnumber
;
12358 /* We use a special addend for an internal RELLO reloc. */
12359 if (symbol_section_p (fixp
->fx_addsy
))
12360 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
12362 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
12365 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
12367 assert (fixp
->fx_next
!= NULL
12368 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
12370 /* The reloc is relative to the RELLO; adjust the addend
12372 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
12373 reloc
->addend
= fixp
->fx_next
->fx_addnumber
;
12376 /* We use a special addend for an internal RELHI reloc. */
12377 if (symbol_section_p (fixp
->fx_addsy
))
12378 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
12379 + fixp
->fx_next
->fx_where
12380 - S_GET_VALUE (fixp
->fx_subsy
));
12382 reloc
->addend
= (fixp
->fx_addnumber
12383 + fixp
->fx_next
->fx_frag
->fr_address
12384 + fixp
->fx_next
->fx_where
);
12387 else if (fixp
->fx_pcrel
== 0 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
12388 reloc
->addend
= fixp
->fx_addnumber
;
12391 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
)
12392 /* A gruesome hack which is a result of the gruesome gas reloc
12394 reloc
->addend
= reloc
->address
;
12396 reloc
->addend
= -reloc
->address
;
12399 /* If this is a variant frag, we may need to adjust the existing
12400 reloc and generate a new one. */
12401 if (fixp
->fx_frag
->fr_opcode
!= NULL
12402 && (fixp
->fx_r_type
== BFD_RELOC_GPREL16
12403 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
12404 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
12405 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
12406 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_LO16
12407 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
12408 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_LO16
)
12413 assert (! RELAX_MIPS16_P (fixp
->fx_frag
->fr_subtype
));
12415 /* If this is not the last reloc in this frag, then we have two
12416 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
12417 CALL_HI16/CALL_LO16, both of which are being replaced. Let
12418 the second one handle all of them. */
12419 if (fixp
->fx_next
!= NULL
12420 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
12422 assert ((fixp
->fx_r_type
== BFD_RELOC_GPREL16
12423 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_GPREL16
)
12424 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
12425 && (fixp
->fx_next
->fx_r_type
12426 == BFD_RELOC_MIPS_GOT_LO16
))
12427 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
12428 && (fixp
->fx_next
->fx_r_type
12429 == BFD_RELOC_MIPS_CALL_LO16
)));
12434 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
12435 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
12436 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
12438 reloc2
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
12439 *reloc2
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
12440 reloc2
->address
= (reloc
->address
12441 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
12442 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
12443 reloc2
->addend
= fixp
->fx_addnumber
;
12444 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
12445 assert (reloc2
->howto
!= NULL
);
12447 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
12451 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
12454 reloc3
->address
+= 4;
12457 if (mips_pic
== NO_PIC
)
12459 assert (fixp
->fx_r_type
== BFD_RELOC_GPREL16
);
12460 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
12462 else if (mips_pic
== SVR4_PIC
)
12464 switch (fixp
->fx_r_type
)
12468 case BFD_RELOC_MIPS_GOT16
:
12470 case BFD_RELOC_MIPS_CALL16
:
12471 case BFD_RELOC_MIPS_GOT_LO16
:
12472 case BFD_RELOC_MIPS_CALL_LO16
:
12473 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
12481 /* Since MIPS ELF uses Rel instead of Rela, encode the vtable entry
12482 to be used in the relocation's section offset. */
12483 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
12485 reloc
->address
= reloc
->addend
;
12489 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
12490 fixup_segment converted a non-PC relative reloc into a PC
12491 relative reloc. In such a case, we need to convert the reloc
12493 code
= fixp
->fx_r_type
;
12494 if (fixp
->fx_pcrel
)
12499 code
= BFD_RELOC_8_PCREL
;
12502 code
= BFD_RELOC_16_PCREL
;
12505 code
= BFD_RELOC_32_PCREL
;
12508 code
= BFD_RELOC_64_PCREL
;
12510 case BFD_RELOC_8_PCREL
:
12511 case BFD_RELOC_16_PCREL
:
12512 case BFD_RELOC_32_PCREL
:
12513 case BFD_RELOC_64_PCREL
:
12514 case BFD_RELOC_16_PCREL_S2
:
12515 case BFD_RELOC_PCREL_HI16_S
:
12516 case BFD_RELOC_PCREL_LO16
:
12519 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12520 _("Cannot make %s relocation PC relative"),
12521 bfd_get_reloc_code_name (code
));
12526 /* md_apply_fix3 has a double-subtraction hack to get
12527 bfd_install_relocation to behave nicely. GPREL relocations are
12528 handled correctly without this hack, so undo it here. We can't
12529 stop md_apply_fix3 from subtracting twice in the first place since
12530 the fake addend is required for variant frags above. */
12531 if (fixp
->fx_addsy
!= NULL
&& OUTPUT_FLAVOR
== bfd_target_elf_flavour
12532 && code
== BFD_RELOC_GPREL16
12533 && reloc
->addend
!= 0
12534 && mips_need_elf_addend_fixup (fixp
))
12535 reloc
->addend
+= S_GET_VALUE (fixp
->fx_addsy
);
12538 /* To support a PC relative reloc when generating embedded PIC code
12539 for ECOFF, we use a Cygnus extension. We check for that here to
12540 make sure that we don't let such a reloc escape normally. */
12541 if ((OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
12542 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
12543 && code
== BFD_RELOC_16_PCREL_S2
12544 && mips_pic
!= EMBEDDED_PIC
)
12545 reloc
->howto
= NULL
;
12547 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
12549 if (reloc
->howto
== NULL
)
12551 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12552 _("Can not represent %s relocation in this object file format"),
12553 bfd_get_reloc_code_name (code
));
12560 /* Relax a machine dependent frag. This returns the amount by which
12561 the current size of the frag should change. */
12564 mips_relax_frag (fragp
, stretch
)
12568 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
12571 if (mips16_extended_frag (fragp
, NULL
, stretch
))
12573 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12575 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
12580 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12582 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
12589 /* Convert a machine dependent frag. */
12592 md_convert_frag (abfd
, asec
, fragp
)
12593 bfd
*abfd ATTRIBUTE_UNUSED
;
12600 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
12603 register const struct mips16_immed_operand
*op
;
12604 boolean small
, ext
;
12607 unsigned long insn
;
12608 boolean use_extend
;
12609 unsigned short extend
;
12611 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
12612 op
= mips16_immed_operands
;
12613 while (op
->type
!= type
)
12616 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12627 resolve_symbol_value (fragp
->fr_symbol
);
12628 val
= S_GET_VALUE (fragp
->fr_symbol
);
12633 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
12635 /* The rules for the base address of a PC relative reloc are
12636 complicated; see mips16_extended_frag. */
12637 if (type
== 'p' || type
== 'q')
12642 /* Ignore the low bit in the target, since it will be
12643 set for a text label. */
12644 if ((val
& 1) != 0)
12647 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
12649 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
12652 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
12655 /* Make sure the section winds up with the alignment we have
12658 record_alignment (asec
, op
->shift
);
12662 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
12663 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
12664 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
12665 _("extended instruction in delay slot"));
12667 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
12669 if (target_big_endian
)
12670 insn
= bfd_getb16 (buf
);
12672 insn
= bfd_getl16 (buf
);
12674 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
12675 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
12676 small
, ext
, &insn
, &use_extend
, &extend
);
12680 md_number_to_chars ((char *) buf
, 0xf000 | extend
, 2);
12681 fragp
->fr_fix
+= 2;
12685 md_number_to_chars ((char *) buf
, insn
, 2);
12686 fragp
->fr_fix
+= 2;
12691 if (fragp
->fr_opcode
== NULL
)
12694 old
= RELAX_OLD (fragp
->fr_subtype
);
12695 new = RELAX_NEW (fragp
->fr_subtype
);
12696 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
12699 memcpy (fixptr
- old
, fixptr
, new);
12701 fragp
->fr_fix
+= new - old
;
12707 /* This function is called after the relocs have been generated.
12708 We've been storing mips16 text labels as odd. Here we convert them
12709 back to even for the convenience of the debugger. */
12712 mips_frob_file_after_relocs ()
12715 unsigned int count
, i
;
12717 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
12720 syms
= bfd_get_outsymbols (stdoutput
);
12721 count
= bfd_get_symcount (stdoutput
);
12722 for (i
= 0; i
< count
; i
++, syms
++)
12724 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
12725 && ((*syms
)->value
& 1) != 0)
12727 (*syms
)->value
&= ~1;
12728 /* If the symbol has an odd size, it was probably computed
12729 incorrectly, so adjust that as well. */
12730 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
12731 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
12738 /* This function is called whenever a label is defined. It is used
12739 when handling branch delays; if a branch has a label, we assume we
12740 can not move it. */
12743 mips_define_label (sym
)
12746 struct insn_label_list
*l
;
12748 if (free_insn_labels
== NULL
)
12749 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
12752 l
= free_insn_labels
;
12753 free_insn_labels
= l
->next
;
12757 l
->next
= insn_labels
;
12761 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12763 /* Some special processing for a MIPS ELF file. */
12766 mips_elf_final_processing ()
12768 /* Write out the register information. */
12769 if (file_mips_abi
!= N64_ABI
)
12773 s
.ri_gprmask
= mips_gprmask
;
12774 s
.ri_cprmask
[0] = mips_cprmask
[0];
12775 s
.ri_cprmask
[1] = mips_cprmask
[1];
12776 s
.ri_cprmask
[2] = mips_cprmask
[2];
12777 s
.ri_cprmask
[3] = mips_cprmask
[3];
12778 /* The gp_value field is set by the MIPS ELF backend. */
12780 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
12781 ((Elf32_External_RegInfo
*)
12782 mips_regmask_frag
));
12786 Elf64_Internal_RegInfo s
;
12788 s
.ri_gprmask
= mips_gprmask
;
12790 s
.ri_cprmask
[0] = mips_cprmask
[0];
12791 s
.ri_cprmask
[1] = mips_cprmask
[1];
12792 s
.ri_cprmask
[2] = mips_cprmask
[2];
12793 s
.ri_cprmask
[3] = mips_cprmask
[3];
12794 /* The gp_value field is set by the MIPS ELF backend. */
12796 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
12797 ((Elf64_External_RegInfo
*)
12798 mips_regmask_frag
));
12801 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
12802 sort of BFD interface for this. */
12803 if (mips_any_noreorder
)
12804 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
12805 if (mips_pic
!= NO_PIC
)
12806 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
12808 /* Set MIPS ELF flags for ASEs. */
12809 #if 0 /* XXX FIXME */
12810 if (file_ase_mips3d
)
12811 elf_elfheader (stdoutput
)->e_flags
|= ???;
12814 /* Set the MIPS ELF ABI flags. */
12815 if (file_mips_abi
== NO_ABI
)
12817 else if (file_mips_abi
== O32_ABI
)
12818 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
12819 else if (file_mips_abi
== O64_ABI
)
12820 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
12821 else if (file_mips_abi
== EABI_ABI
)
12824 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
12826 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
12828 else if (file_mips_abi
== N32_ABI
)
12829 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
12831 /* Nothing to do for "64". */
12833 if (mips_32bitmode
)
12834 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
12837 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
12839 typedef struct proc
{
12841 unsigned long reg_mask
;
12842 unsigned long reg_offset
;
12843 unsigned long fpreg_mask
;
12844 unsigned long fpreg_offset
;
12845 unsigned long frame_offset
;
12846 unsigned long frame_reg
;
12847 unsigned long pc_reg
;
12850 static procS cur_proc
;
12851 static procS
*cur_proc_ptr
;
12852 static int numprocs
;
12854 /* Fill in an rs_align_code fragment. */
12857 mips_handle_align (fragp
)
12860 if (fragp
->fr_type
!= rs_align_code
)
12863 if (mips_opts
.mips16
)
12865 static const unsigned char be_nop
[] = { 0x65, 0x00 };
12866 static const unsigned char le_nop
[] = { 0x00, 0x65 };
12871 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
12872 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
12877 fragp
->fr_fix
+= 1;
12880 memcpy (p
, (target_big_endian
? be_nop
: le_nop
), 2);
12884 /* For mips32, a nop is a zero, which we trivially get by doing nothing. */
12895 /* check for premature end, nesting errors, etc */
12897 as_warn (_("missing .end at end of assembly"));
12906 if (*input_line_pointer
== '-')
12908 ++input_line_pointer
;
12911 if (!ISDIGIT (*input_line_pointer
))
12912 as_bad (_("expected simple number"));
12913 if (input_line_pointer
[0] == '0')
12915 if (input_line_pointer
[1] == 'x')
12917 input_line_pointer
+= 2;
12918 while (ISXDIGIT (*input_line_pointer
))
12921 val
|= hex_value (*input_line_pointer
++);
12923 return negative
? -val
: val
;
12927 ++input_line_pointer
;
12928 while (ISDIGIT (*input_line_pointer
))
12931 val
|= *input_line_pointer
++ - '0';
12933 return negative
? -val
: val
;
12936 if (!ISDIGIT (*input_line_pointer
))
12938 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
12939 *input_line_pointer
, *input_line_pointer
);
12940 as_warn (_("invalid number"));
12943 while (ISDIGIT (*input_line_pointer
))
12946 val
+= *input_line_pointer
++ - '0';
12948 return negative
? -val
: val
;
12951 /* The .file directive; just like the usual .file directive, but there
12952 is an initial number which is the ECOFF file index. */
12956 int x ATTRIBUTE_UNUSED
;
12962 /* The .end directive. */
12966 int x ATTRIBUTE_UNUSED
;
12971 /* Following functions need their own .frame and .cprestore directives. */
12972 mips_frame_reg_valid
= 0;
12973 mips_cprestore_valid
= 0;
12975 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
12978 demand_empty_rest_of_line ();
12983 #ifdef BFD_ASSEMBLER
12984 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
12989 if (now_seg
!= data_section
&& now_seg
!= bss_section
)
12996 as_warn (_(".end not in text section"));
13000 as_warn (_(".end directive without a preceding .ent directive."));
13001 demand_empty_rest_of_line ();
13007 assert (S_GET_NAME (p
));
13008 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->isym
)))
13009 as_warn (_(".end symbol does not match .ent symbol."));
13012 as_warn (_(".end directive missing or unknown symbol"));
13014 #ifdef MIPS_STABS_ELF
13016 segT saved_seg
= now_seg
;
13017 subsegT saved_subseg
= now_subseg
;
13022 dot
= frag_now_fix ();
13024 #ifdef md_flush_pending_output
13025 md_flush_pending_output ();
13029 subseg_set (pdr_seg
, 0);
13031 /* Write the symbol. */
13032 exp
.X_op
= O_symbol
;
13033 exp
.X_add_symbol
= p
;
13034 exp
.X_add_number
= 0;
13035 emit_expr (&exp
, 4);
13037 fragp
= frag_more (7 * 4);
13039 md_number_to_chars (fragp
, (valueT
) cur_proc_ptr
->reg_mask
, 4);
13040 md_number_to_chars (fragp
+ 4, (valueT
) cur_proc_ptr
->reg_offset
, 4);
13041 md_number_to_chars (fragp
+ 8, (valueT
) cur_proc_ptr
->fpreg_mask
, 4);
13042 md_number_to_chars (fragp
+ 12, (valueT
) cur_proc_ptr
->fpreg_offset
, 4);
13043 md_number_to_chars (fragp
+ 16, (valueT
) cur_proc_ptr
->frame_offset
, 4);
13044 md_number_to_chars (fragp
+ 20, (valueT
) cur_proc_ptr
->frame_reg
, 4);
13045 md_number_to_chars (fragp
+ 24, (valueT
) cur_proc_ptr
->pc_reg
, 4);
13047 subseg_set (saved_seg
, saved_subseg
);
13051 cur_proc_ptr
= NULL
;
13054 /* The .aent and .ent directives. */
13063 symbolP
= get_symbol ();
13064 if (*input_line_pointer
== ',')
13065 input_line_pointer
++;
13066 SKIP_WHITESPACE ();
13067 if (ISDIGIT (*input_line_pointer
)
13068 || *input_line_pointer
== '-')
13071 #ifdef BFD_ASSEMBLER
13072 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
13077 if (now_seg
!= data_section
&& now_seg
!= bss_section
)
13084 as_warn (_(".ent or .aent not in text section."));
13086 if (!aent
&& cur_proc_ptr
)
13087 as_warn (_("missing .end"));
13091 /* This function needs its own .frame and .cprestore directives. */
13092 mips_frame_reg_valid
= 0;
13093 mips_cprestore_valid
= 0;
13095 cur_proc_ptr
= &cur_proc
;
13096 memset (cur_proc_ptr
, '\0', sizeof (procS
));
13098 cur_proc_ptr
->isym
= symbolP
;
13100 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
13105 demand_empty_rest_of_line ();
13108 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
13109 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
13110 s_mips_frame is used so that we can set the PDR information correctly.
13111 We can't use the ecoff routines because they make reference to the ecoff
13112 symbol table (in the mdebug section). */
13115 s_mips_frame (ignore
)
13116 int ignore ATTRIBUTE_UNUSED
;
13118 #ifdef MIPS_STABS_ELF
13122 if (cur_proc_ptr
== (procS
*) NULL
)
13124 as_warn (_(".frame outside of .ent"));
13125 demand_empty_rest_of_line ();
13129 cur_proc_ptr
->frame_reg
= tc_get_register (1);
13131 SKIP_WHITESPACE ();
13132 if (*input_line_pointer
++ != ','
13133 || get_absolute_expression_and_terminator (&val
) != ',')
13135 as_warn (_("Bad .frame directive"));
13136 --input_line_pointer
;
13137 demand_empty_rest_of_line ();
13141 cur_proc_ptr
->frame_offset
= val
;
13142 cur_proc_ptr
->pc_reg
= tc_get_register (0);
13144 demand_empty_rest_of_line ();
13147 #endif /* MIPS_STABS_ELF */
13150 /* The .fmask and .mask directives. If the mdebug section is present
13151 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
13152 embedded targets, s_mips_mask is used so that we can set the PDR
13153 information correctly. We can't use the ecoff routines because they
13154 make reference to the ecoff symbol table (in the mdebug section). */
13157 s_mips_mask (reg_type
)
13160 #ifdef MIPS_STABS_ELF
13163 if (cur_proc_ptr
== (procS
*) NULL
)
13165 as_warn (_(".mask/.fmask outside of .ent"));
13166 demand_empty_rest_of_line ();
13170 if (get_absolute_expression_and_terminator (&mask
) != ',')
13172 as_warn (_("Bad .mask/.fmask directive"));
13173 --input_line_pointer
;
13174 demand_empty_rest_of_line ();
13178 off
= get_absolute_expression ();
13180 if (reg_type
== 'F')
13182 cur_proc_ptr
->fpreg_mask
= mask
;
13183 cur_proc_ptr
->fpreg_offset
= off
;
13187 cur_proc_ptr
->reg_mask
= mask
;
13188 cur_proc_ptr
->reg_offset
= off
;
13191 demand_empty_rest_of_line ();
13193 s_ignore (reg_type
);
13194 #endif /* MIPS_STABS_ELF */
13197 /* The .loc directive. */
13208 assert (now_seg
== text_section
);
13210 lineno
= get_number ();
13211 addroff
= frag_now_fix ();
13213 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
13214 S_SET_TYPE (symbolP
, N_SLINE
);
13215 S_SET_OTHER (symbolP
, 0);
13216 S_SET_DESC (symbolP
, lineno
);
13217 symbolP
->sy_segment
= now_seg
;
13221 /* CPU name/ISA/number mapping table.
13223 Entries are grouped by type. The first matching CPU or ISA entry
13224 gets chosen by CPU or ISA, so it should be the 'canonical' name
13225 for that type. Entries after that within the type are sorted
13228 Case is ignored in comparison, so put the canonical entry in the
13229 appropriate case but everything else in lower case to ease eye pain. */
13230 static const struct mips_cpu_info mips_cpu_info_table
[] =
13233 { "MIPS1", 1, ISA_MIPS1
, CPU_R3000
, },
13234 { "mips", 1, ISA_MIPS1
, CPU_R3000
, },
13237 { "MIPS2", 1, ISA_MIPS2
, CPU_R6000
, },
13240 { "MIPS3", 1, ISA_MIPS3
, CPU_R4000
, },
13243 { "MIPS4", 1, ISA_MIPS4
, CPU_R8000
, },
13246 { "MIPS5", 1, ISA_MIPS5
, CPU_MIPS5
, },
13247 { "Generic-MIPS5", 0, ISA_MIPS5
, CPU_MIPS5
, },
13250 { "MIPS32", 1, ISA_MIPS32
, CPU_MIPS32
, },
13251 { "mipsisa32", 0, ISA_MIPS32
, CPU_MIPS32
, },
13252 { "Generic-MIPS32", 0, ISA_MIPS32
, CPU_MIPS32
, },
13253 { "4kc", 0, ISA_MIPS32
, CPU_MIPS32
, },
13254 { "4km", 0, ISA_MIPS32
, CPU_MIPS32
, },
13255 { "4kp", 0, ISA_MIPS32
, CPU_MIPS32
, },
13257 /* For historical reasons. */
13258 { "MIPS64", 1, ISA_MIPS3
, CPU_R4000
, },
13261 { "mipsisa64", 1, ISA_MIPS64
, CPU_MIPS64
, },
13262 { "Generic-MIPS64", 0, ISA_MIPS64
, CPU_MIPS64
, },
13263 { "5kc", 0, ISA_MIPS64
, CPU_MIPS64
, },
13264 { "20kc", 0, ISA_MIPS64
, CPU_MIPS64
, },
13267 { "R2000", 0, ISA_MIPS1
, CPU_R2000
, },
13268 { "2000", 0, ISA_MIPS1
, CPU_R2000
, },
13269 { "2k", 0, ISA_MIPS1
, CPU_R2000
, },
13270 { "r2k", 0, ISA_MIPS1
, CPU_R2000
, },
13273 { "R3000", 0, ISA_MIPS1
, CPU_R3000
, },
13274 { "3000", 0, ISA_MIPS1
, CPU_R3000
, },
13275 { "3k", 0, ISA_MIPS1
, CPU_R3000
, },
13276 { "r3k", 0, ISA_MIPS1
, CPU_R3000
, },
13279 { "R3900", 0, ISA_MIPS1
, CPU_R3900
, },
13280 { "3900", 0, ISA_MIPS1
, CPU_R3900
, },
13281 { "mipstx39", 0, ISA_MIPS1
, CPU_R3900
, },
13284 { "R4000", 0, ISA_MIPS3
, CPU_R4000
, },
13285 { "4000", 0, ISA_MIPS3
, CPU_R4000
, },
13286 { "4k", 0, ISA_MIPS3
, CPU_R4000
, }, /* beware */
13287 { "r4k", 0, ISA_MIPS3
, CPU_R4000
, },
13290 { "R4010", 0, ISA_MIPS2
, CPU_R4010
, },
13291 { "4010", 0, ISA_MIPS2
, CPU_R4010
, },
13294 { "R4400", 0, ISA_MIPS3
, CPU_R4400
, },
13295 { "4400", 0, ISA_MIPS3
, CPU_R4400
, },
13298 { "R4600", 0, ISA_MIPS3
, CPU_R4600
, },
13299 { "4600", 0, ISA_MIPS3
, CPU_R4600
, },
13300 { "mips64orion", 0, ISA_MIPS3
, CPU_R4600
, },
13301 { "orion", 0, ISA_MIPS3
, CPU_R4600
, },
13304 { "R4650", 0, ISA_MIPS3
, CPU_R4650
, },
13305 { "4650", 0, ISA_MIPS3
, CPU_R4650
, },
13308 { "R6000", 0, ISA_MIPS2
, CPU_R6000
, },
13309 { "6000", 0, ISA_MIPS2
, CPU_R6000
, },
13310 { "6k", 0, ISA_MIPS2
, CPU_R6000
, },
13311 { "r6k", 0, ISA_MIPS2
, CPU_R6000
, },
13314 { "R8000", 0, ISA_MIPS4
, CPU_R8000
, },
13315 { "8000", 0, ISA_MIPS4
, CPU_R8000
, },
13316 { "8k", 0, ISA_MIPS4
, CPU_R8000
, },
13317 { "r8k", 0, ISA_MIPS4
, CPU_R8000
, },
13320 { "R10000", 0, ISA_MIPS4
, CPU_R10000
, },
13321 { "10000", 0, ISA_MIPS4
, CPU_R10000
, },
13322 { "10k", 0, ISA_MIPS4
, CPU_R10000
, },
13323 { "r10k", 0, ISA_MIPS4
, CPU_R10000
, },
13326 { "R12000", 0, ISA_MIPS4
, CPU_R12000
, },
13327 { "12000", 0, ISA_MIPS4
, CPU_R12000
, },
13328 { "12k", 0, ISA_MIPS4
, CPU_R12000
, },
13329 { "r12k", 0, ISA_MIPS4
, CPU_R12000
, },
13332 { "VR4100", 0, ISA_MIPS3
, CPU_VR4100
, },
13333 { "4100", 0, ISA_MIPS3
, CPU_VR4100
, },
13334 { "mips64vr4100", 0, ISA_MIPS3
, CPU_VR4100
, },
13335 { "r4100", 0, ISA_MIPS3
, CPU_VR4100
, },
13338 { "VR4111", 0, ISA_MIPS3
, CPU_R4111
, },
13339 { "4111", 0, ISA_MIPS3
, CPU_R4111
, },
13340 { "mips64vr4111", 0, ISA_MIPS3
, CPU_R4111
, },
13341 { "r4111", 0, ISA_MIPS3
, CPU_R4111
, },
13344 { "VR4300", 0, ISA_MIPS3
, CPU_R4300
, },
13345 { "4300", 0, ISA_MIPS3
, CPU_R4300
, },
13346 { "mips64vr4300", 0, ISA_MIPS3
, CPU_R4300
, },
13347 { "r4300", 0, ISA_MIPS3
, CPU_R4300
, },
13350 { "VR5000", 0, ISA_MIPS4
, CPU_R5000
, },
13351 { "5000", 0, ISA_MIPS4
, CPU_R5000
, },
13352 { "5k", 0, ISA_MIPS4
, CPU_R5000
, },
13353 { "mips64vr5000", 0, ISA_MIPS4
, CPU_R5000
, },
13354 { "r5000", 0, ISA_MIPS4
, CPU_R5000
, },
13355 { "r5200", 0, ISA_MIPS4
, CPU_R5000
, },
13356 { "rm5200", 0, ISA_MIPS4
, CPU_R5000
, },
13357 { "r5230", 0, ISA_MIPS4
, CPU_R5000
, },
13358 { "rm5230", 0, ISA_MIPS4
, CPU_R5000
, },
13359 { "r5231", 0, ISA_MIPS4
, CPU_R5000
, },
13360 { "rm5231", 0, ISA_MIPS4
, CPU_R5000
, },
13361 { "r5261", 0, ISA_MIPS4
, CPU_R5000
, },
13362 { "rm5261", 0, ISA_MIPS4
, CPU_R5000
, },
13363 { "r5721", 0, ISA_MIPS4
, CPU_R5000
, },
13364 { "rm5721", 0, ISA_MIPS4
, CPU_R5000
, },
13365 { "r5k", 0, ISA_MIPS4
, CPU_R5000
, },
13366 { "r7000", 0, ISA_MIPS4
, CPU_R5000
, },
13368 /* Broadcom SB-1 CPU */
13369 { "SB-1", 0, ISA_MIPS64
, CPU_SB1
, },
13370 { "sb-1250", 0, ISA_MIPS64
, CPU_SB1
, },
13371 { "sb1", 0, ISA_MIPS64
, CPU_SB1
, },
13372 { "sb1250", 0, ISA_MIPS64
, CPU_SB1
, },
13375 { NULL
, 0, 0, 0, },
13378 static const struct mips_cpu_info
*
13379 mips_cpu_info_from_name (name
)
13384 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
13385 if (strcasecmp (name
, mips_cpu_info_table
[i
].name
) == 0)
13386 return (&mips_cpu_info_table
[i
]);
13391 static const struct mips_cpu_info
*
13392 mips_cpu_info_from_isa (isa
)
13397 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
13398 if (mips_cpu_info_table
[i
].is_isa
13399 && isa
== mips_cpu_info_table
[i
].isa
)
13400 return (&mips_cpu_info_table
[i
]);
13405 static const struct mips_cpu_info
*
13406 mips_cpu_info_from_cpu (cpu
)
13411 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
13412 if (!mips_cpu_info_table
[i
].is_isa
13413 && cpu
== mips_cpu_info_table
[i
].cpu
)
13414 return (&mips_cpu_info_table
[i
]);