1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "elf/x86-64.h"
36 #include "opcodes/i386-init.h"
38 #ifndef REGISTER_WARNINGS
39 #define REGISTER_WARNINGS 1
42 #ifndef INFER_ADDR_PREFIX
43 #define INFER_ADDR_PREFIX 1
47 #define DEFAULT_ARCH "i386"
52 #define INLINE __inline__
58 /* Prefixes will be emitted in the order defined below.
59 WAIT_PREFIX must be the first prefix since FWAIT is really is an
60 instruction, and so must come before any prefixes.
61 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
67 #define LOCKREP_PREFIX 4
68 #define REX_PREFIX 5 /* must come last. */
69 #define MAX_PREFIXES 6 /* max prefixes per opcode */
71 /* we define the syntax here (modulo base,index,scale syntax) */
72 #define REGISTER_PREFIX '%'
73 #define IMMEDIATE_PREFIX '$'
74 #define ABSOLUTE_PREFIX '*'
76 /* these are the instruction mnemonic suffixes in AT&T syntax or
77 memory operand size in Intel syntax. */
78 #define WORD_MNEM_SUFFIX 'w'
79 #define BYTE_MNEM_SUFFIX 'b'
80 #define SHORT_MNEM_SUFFIX 's'
81 #define LONG_MNEM_SUFFIX 'l'
82 #define QWORD_MNEM_SUFFIX 'q'
83 #define XMMWORD_MNEM_SUFFIX 'x'
84 #define YMMWORD_MNEM_SUFFIX 'y'
85 /* Intel Syntax. Use a non-ascii letter since since it never appears
87 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
89 #define END_OF_INSN '\0'
92 'templates' is for grouping together 'template' structures for opcodes
93 of the same name. This is only used for storing the insns in the grand
94 ole hash table of insns.
95 The templates themselves start at START and range up to (but not including)
100 const template *start
;
105 /* 386 operand encoding bytes: see 386 book for details of this. */
108 unsigned int regmem
; /* codes register or memory operand */
109 unsigned int reg
; /* codes register operand (or extended opcode) */
110 unsigned int mode
; /* how to interpret regmem & reg */
114 /* x86-64 extension prefix. */
115 typedef int rex_byte
;
117 /* The SSE5 instructions have a two bit instruction modifier (OC) that
118 is stored in two separate bytes in the instruction. Pick apart OC
119 into the 2 separate bits for instruction. */
120 #define DREX_OC0(x) (((x) & 1) != 0)
121 #define DREX_OC1(x) (((x) & 2) != 0)
123 #define DREX_OC0_MASK (1 << 3) /* set OC0 in byte 4 */
124 #define DREX_OC1_MASK (1 << 2) /* set OC1 in byte 3 */
127 #define DREX_XMEM_X1_X2_X2 0 /* 4 op insn, dest = src3, src1 = reg/mem */
128 #define DREX_X1_XMEM_X2_X2 1 /* 4 op insn, dest = src3, src2 = reg/mem */
129 #define DREX_X1_XMEM_X2_X1 2 /* 4 op insn, dest = src1, src2 = reg/mem */
130 #define DREX_X1_X2_XMEM_X1 3 /* 4 op insn, dest = src1, src3 = reg/mem */
132 #define DREX_XMEM_X1_X2 0 /* 3 op insn, src1 = reg/mem */
133 #define DREX_X1_XMEM_X2 1 /* 3 op insn, src1 = reg/mem */
135 /* Information needed to create the DREX byte in SSE5 instructions. */
138 unsigned int reg
; /* register */
139 unsigned int rex
; /* REX flags */
140 unsigned int modrm_reg
; /* which arg goes in the modrm.reg field */
141 unsigned int modrm_regmem
; /* which arg goes in the modrm.regmem field */
144 /* 386 opcode byte to code indirect addressing. */
159 PROCESSOR_PENTIUMPRO
,
172 /* x86 arch names, types and features */
175 const char *name
; /* arch name */
176 enum processor_type type
; /* arch type */
177 i386_cpu_flags flags
; /* cpu feature flags */
181 static void set_code_flag (int);
182 static void set_16bit_gcc_code_flag (int);
183 static void set_intel_syntax (int);
184 static void set_intel_mnemonic (int);
185 static void set_allow_index_reg (int);
186 static void set_cpu_arch (int);
188 static void pe_directive_secrel (int);
190 static void signed_cons (int);
191 static char *output_invalid (int c
);
192 static int i386_att_operand (char *);
193 static int i386_intel_operand (char *, int);
194 static const reg_entry
*parse_register (char *, char **);
195 static char *parse_insn (char *, char *);
196 static char *parse_operands (char *, const char *);
197 static void swap_operands (void);
198 static void swap_2_operands (int, int);
199 static void optimize_imm (void);
200 static void optimize_disp (void);
201 static int match_template (void);
202 static int check_string (void);
203 static int process_suffix (void);
204 static int check_byte_reg (void);
205 static int check_long_reg (void);
206 static int check_qword_reg (void);
207 static int check_word_reg (void);
208 static int finalize_imm (void);
209 static void process_drex (void);
210 static int process_operands (void);
211 static const seg_entry
*build_modrm_byte (void);
212 static void output_insn (void);
213 static void output_imm (fragS
*, offsetT
);
214 static void output_disp (fragS
*, offsetT
);
216 static void s_bss (int);
218 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
219 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
222 static const char *default_arch
= DEFAULT_ARCH
;
227 /* VEX prefix is either 2 byte or 3 byte. */
228 unsigned char bytes
[3];
230 /* Destination or source register specifier. */
231 const reg_entry
*register_specifier
;
234 /* 'md_assemble ()' gathers together information and puts it into a
241 const reg_entry
*regs
;
246 /* TM holds the template for the insn were currently assembling. */
249 /* SUFFIX holds the instruction size suffix for byte, word, dword
250 or qword, if given. */
253 /* OPERANDS gives the number of given operands. */
254 unsigned int operands
;
256 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
257 of given register, displacement, memory operands and immediate
259 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
261 /* TYPES [i] is the type (see above #defines) which tells us how to
262 use OP[i] for the corresponding operand. */
263 i386_operand_type types
[MAX_OPERANDS
];
265 /* Displacement expression, immediate expression, or register for each
267 union i386_op op
[MAX_OPERANDS
];
269 /* Flags for operands. */
270 unsigned int flags
[MAX_OPERANDS
];
271 #define Operand_PCrel 1
273 /* Relocation type for operand */
274 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
276 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
277 the base index byte below. */
278 const reg_entry
*base_reg
;
279 const reg_entry
*index_reg
;
280 unsigned int log2_scale_factor
;
282 /* SEG gives the seg_entries of this insn. They are zero unless
283 explicit segment overrides are given. */
284 const seg_entry
*seg
[2];
286 /* PREFIX holds all the given prefix opcodes (usually null).
287 PREFIXES is the number of prefix opcodes. */
288 unsigned int prefixes
;
289 unsigned char prefix
[MAX_PREFIXES
];
291 /* RM and SIB are the modrm byte and the sib byte where the
292 addressing modes of this insn are encoded. DREX is the byte
293 added by the SSE5 instructions. */
302 typedef struct _i386_insn i386_insn
;
304 /* List of chars besides those in app.c:symbol_chars that can start an
305 operand. Used to prevent the scrubber eating vital white-space. */
306 const char extra_symbol_chars
[] = "*%-(["
315 #if (defined (TE_I386AIX) \
316 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
317 && !defined (TE_GNU) \
318 && !defined (TE_LINUX) \
319 && !defined (TE_NETWARE) \
320 && !defined (TE_FreeBSD) \
321 && !defined (TE_NetBSD)))
322 /* This array holds the chars that always start a comment. If the
323 pre-processor is disabled, these aren't very useful. The option
324 --divide will remove '/' from this list. */
325 const char *i386_comment_chars
= "#/";
326 #define SVR4_COMMENT_CHARS 1
327 #define PREFIX_SEPARATOR '\\'
330 const char *i386_comment_chars
= "#";
331 #define PREFIX_SEPARATOR '/'
334 /* This array holds the chars that only start a comment at the beginning of
335 a line. If the line seems to have the form '# 123 filename'
336 .line and .file directives will appear in the pre-processed output.
337 Note that input_file.c hand checks for '#' at the beginning of the
338 first line of the input file. This is because the compiler outputs
339 #NO_APP at the beginning of its output.
340 Also note that comments started like this one will always work if
341 '/' isn't otherwise defined. */
342 const char line_comment_chars
[] = "#/";
344 const char line_separator_chars
[] = ";";
346 /* Chars that can be used to separate mant from exp in floating point
348 const char EXP_CHARS
[] = "eE";
350 /* Chars that mean this number is a floating point constant
353 const char FLT_CHARS
[] = "fFdDxX";
355 /* Tables for lexical analysis. */
356 static char mnemonic_chars
[256];
357 static char register_chars
[256];
358 static char operand_chars
[256];
359 static char identifier_chars
[256];
360 static char digit_chars
[256];
362 /* Lexical macros. */
363 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
364 #define is_operand_char(x) (operand_chars[(unsigned char) x])
365 #define is_register_char(x) (register_chars[(unsigned char) x])
366 #define is_space_char(x) ((x) == ' ')
367 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
368 #define is_digit_char(x) (digit_chars[(unsigned char) x])
370 /* All non-digit non-letter characters that may occur in an operand. */
371 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
373 /* md_assemble() always leaves the strings it's passed unaltered. To
374 effect this we maintain a stack of saved characters that we've smashed
375 with '\0's (indicating end of strings for various sub-fields of the
376 assembler instruction). */
377 static char save_stack
[32];
378 static char *save_stack_p
;
379 #define END_STRING_AND_SAVE(s) \
380 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
381 #define RESTORE_END_STRING(s) \
382 do { *(s) = *--save_stack_p; } while (0)
384 /* The instruction we're assembling. */
387 /* Possible templates for current insn. */
388 static const templates
*current_templates
;
390 /* Per instruction expressionS buffers: max displacements & immediates. */
391 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
392 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
394 /* Current operand we are working on. */
395 static int this_operand
;
397 /* We support four different modes. FLAG_CODE variable is used to distinguish
405 static enum flag_code flag_code
;
406 static unsigned int object_64bit
;
407 static int use_rela_relocations
= 0;
409 /* The names used to print error messages. */
410 static const char *flag_code_names
[] =
417 /* 1 for intel syntax,
419 static int intel_syntax
= 0;
421 /* 1 for intel mnemonic,
422 0 if att mnemonic. */
423 static int intel_mnemonic
= !SYSV386_COMPAT
;
425 /* 1 if support old (<= 2.8.1) versions of gcc. */
426 static int old_gcc
= OLDGCC_COMPAT
;
428 /* 1 if pseudo registers are permitted. */
429 static int allow_pseudo_reg
= 0;
431 /* 1 if register prefix % not required. */
432 static int allow_naked_reg
= 0;
434 /* 1 if pseudo index register, eiz/riz, is allowed . */
435 static int allow_index_reg
= 0;
437 /* Register prefix used for error message. */
438 static const char *register_prefix
= "%";
440 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
441 leave, push, and pop instructions so that gcc has the same stack
442 frame as in 32 bit mode. */
443 static char stackop_size
= '\0';
445 /* Non-zero to optimize code alignment. */
446 int optimize_align_code
= 1;
448 /* Non-zero to quieten some warnings. */
449 static int quiet_warnings
= 0;
452 static const char *cpu_arch_name
= NULL
;
453 static char *cpu_sub_arch_name
= NULL
;
455 /* CPU feature flags. */
456 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
458 /* If we have selected a cpu we are generating instructions for. */
459 static int cpu_arch_tune_set
= 0;
461 /* Cpu we are generating instructions for. */
462 static enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
464 /* CPU feature flags of cpu we are generating instructions for. */
465 static i386_cpu_flags cpu_arch_tune_flags
;
467 /* CPU instruction set architecture used. */
468 static enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
470 /* CPU feature flags of instruction set architecture used. */
471 static i386_cpu_flags cpu_arch_isa_flags
;
473 /* If set, conditional jumps are not automatically promoted to handle
474 larger than a byte offset. */
475 static unsigned int no_cond_jump_promotion
= 0;
477 /* Encode SSE instructions with VEX prefix. */
478 static unsigned int sse2avx
;
480 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
481 static symbolS
*GOT_symbol
;
483 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
484 unsigned int x86_dwarf2_return_column
;
486 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
487 int x86_cie_data_alignment
;
489 /* Interface to relax_segment.
490 There are 3 major relax states for 386 jump insns because the
491 different types of jumps add different sizes to frags when we're
492 figuring out what sort of jump to choose to reach a given label. */
495 #define UNCOND_JUMP 0
497 #define COND_JUMP86 2
502 #define SMALL16 (SMALL | CODE16)
504 #define BIG16 (BIG | CODE16)
508 #define INLINE __inline__
514 #define ENCODE_RELAX_STATE(type, size) \
515 ((relax_substateT) (((type) << 2) | (size)))
516 #define TYPE_FROM_RELAX_STATE(s) \
518 #define DISP_SIZE_FROM_RELAX_STATE(s) \
519 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
521 /* This table is used by relax_frag to promote short jumps to long
522 ones where necessary. SMALL (short) jumps may be promoted to BIG
523 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
524 don't allow a short jump in a 32 bit code segment to be promoted to
525 a 16 bit offset jump because it's slower (requires data size
526 prefix), and doesn't work, unless the destination is in the bottom
527 64k of the code segment (The top 16 bits of eip are zeroed). */
529 const relax_typeS md_relax_table
[] =
532 1) most positive reach of this state,
533 2) most negative reach of this state,
534 3) how many bytes this mode will have in the variable part of the frag
535 4) which index into the table to try if we can't fit into this one. */
537 /* UNCOND_JUMP states. */
538 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
539 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
540 /* dword jmp adds 4 bytes to frag:
541 0 extra opcode bytes, 4 displacement bytes. */
543 /* word jmp adds 2 byte2 to frag:
544 0 extra opcode bytes, 2 displacement bytes. */
547 /* COND_JUMP states. */
548 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
549 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
550 /* dword conditionals adds 5 bytes to frag:
551 1 extra opcode byte, 4 displacement bytes. */
553 /* word conditionals add 3 bytes to frag:
554 1 extra opcode byte, 2 displacement bytes. */
557 /* COND_JUMP86 states. */
558 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
559 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
560 /* dword conditionals adds 5 bytes to frag:
561 1 extra opcode byte, 4 displacement bytes. */
563 /* word conditionals add 4 bytes to frag:
564 1 displacement byte and a 3 byte long branch insn. */
568 static const arch_entry cpu_arch
[] =
570 { "generic32", PROCESSOR_GENERIC32
,
571 CPU_GENERIC32_FLAGS
},
572 { "generic64", PROCESSOR_GENERIC64
,
573 CPU_GENERIC64_FLAGS
},
574 { "i8086", PROCESSOR_UNKNOWN
,
576 { "i186", PROCESSOR_UNKNOWN
,
578 { "i286", PROCESSOR_UNKNOWN
,
580 { "i386", PROCESSOR_I386
,
582 { "i486", PROCESSOR_I486
,
584 { "i586", PROCESSOR_PENTIUM
,
586 { "i686", PROCESSOR_PENTIUMPRO
,
588 { "pentium", PROCESSOR_PENTIUM
,
590 { "pentiumpro", PROCESSOR_PENTIUMPRO
,
592 { "pentiumii", PROCESSOR_PENTIUMPRO
,
594 { "pentiumiii",PROCESSOR_PENTIUMPRO
,
596 { "pentium4", PROCESSOR_PENTIUM4
,
598 { "prescott", PROCESSOR_NOCONA
,
600 { "nocona", PROCESSOR_NOCONA
,
602 { "yonah", PROCESSOR_CORE
,
604 { "core", PROCESSOR_CORE
,
606 { "merom", PROCESSOR_CORE2
,
608 { "core2", PROCESSOR_CORE2
,
610 { "k6", PROCESSOR_K6
,
612 { "k6_2", PROCESSOR_K6
,
614 { "athlon", PROCESSOR_ATHLON
,
616 { "sledgehammer", PROCESSOR_K8
,
618 { "opteron", PROCESSOR_K8
,
620 { "k8", PROCESSOR_K8
,
622 { "amdfam10", PROCESSOR_AMDFAM10
,
623 CPU_AMDFAM10_FLAGS
},
624 { ".mmx", PROCESSOR_UNKNOWN
,
626 { ".sse", PROCESSOR_UNKNOWN
,
628 { ".sse2", PROCESSOR_UNKNOWN
,
630 { ".sse3", PROCESSOR_UNKNOWN
,
632 { ".ssse3", PROCESSOR_UNKNOWN
,
634 { ".sse4.1", PROCESSOR_UNKNOWN
,
636 { ".sse4.2", PROCESSOR_UNKNOWN
,
638 { ".sse4", PROCESSOR_UNKNOWN
,
640 { ".avx", PROCESSOR_UNKNOWN
,
642 { ".vmx", PROCESSOR_UNKNOWN
,
644 { ".smx", PROCESSOR_UNKNOWN
,
646 { ".xsave", PROCESSOR_UNKNOWN
,
648 { ".aes", PROCESSOR_UNKNOWN
,
650 { ".pclmul", PROCESSOR_UNKNOWN
,
652 { ".clmul", PROCESSOR_UNKNOWN
,
654 { ".fma", PROCESSOR_UNKNOWN
,
656 { ".3dnow", PROCESSOR_UNKNOWN
,
658 { ".3dnowa", PROCESSOR_UNKNOWN
,
660 { ".padlock", PROCESSOR_UNKNOWN
,
662 { ".pacifica", PROCESSOR_UNKNOWN
,
664 { ".svme", PROCESSOR_UNKNOWN
,
666 { ".sse4a", PROCESSOR_UNKNOWN
,
668 { ".abm", PROCESSOR_UNKNOWN
,
670 { ".sse5", PROCESSOR_UNKNOWN
,
674 const pseudo_typeS md_pseudo_table
[] =
676 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
677 {"align", s_align_bytes
, 0},
679 {"align", s_align_ptwo
, 0},
681 {"arch", set_cpu_arch
, 0},
685 {"ffloat", float_cons
, 'f'},
686 {"dfloat", float_cons
, 'd'},
687 {"tfloat", float_cons
, 'x'},
689 {"slong", signed_cons
, 4},
690 {"noopt", s_ignore
, 0},
691 {"optim", s_ignore
, 0},
692 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
693 {"code16", set_code_flag
, CODE_16BIT
},
694 {"code32", set_code_flag
, CODE_32BIT
},
695 {"code64", set_code_flag
, CODE_64BIT
},
696 {"intel_syntax", set_intel_syntax
, 1},
697 {"att_syntax", set_intel_syntax
, 0},
698 {"intel_mnemonic", set_intel_mnemonic
, 1},
699 {"att_mnemonic", set_intel_mnemonic
, 0},
700 {"allow_index_reg", set_allow_index_reg
, 1},
701 {"disallow_index_reg", set_allow_index_reg
, 0},
702 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
703 {"largecomm", handle_large_common
, 0},
705 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
706 {"loc", dwarf2_directive_loc
, 0},
707 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
710 {"secrel32", pe_directive_secrel
, 0},
715 /* For interface with expression (). */
716 extern char *input_line_pointer
;
718 /* Hash table for instruction mnemonic lookup. */
719 static struct hash_control
*op_hash
;
721 /* Hash table for register lookup. */
722 static struct hash_control
*reg_hash
;
725 i386_align_code (fragS
*fragP
, int count
)
727 /* Various efficient no-op patterns for aligning code labels.
728 Note: Don't try to assemble the instructions in the comments.
729 0L and 0w are not legal. */
730 static const char f32_1
[] =
732 static const char f32_2
[] =
733 {0x66,0x90}; /* xchg %ax,%ax */
734 static const char f32_3
[] =
735 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
736 static const char f32_4
[] =
737 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
738 static const char f32_5
[] =
740 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
741 static const char f32_6
[] =
742 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
743 static const char f32_7
[] =
744 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
745 static const char f32_8
[] =
747 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
748 static const char f32_9
[] =
749 {0x89,0xf6, /* movl %esi,%esi */
750 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
751 static const char f32_10
[] =
752 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
753 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
754 static const char f32_11
[] =
755 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
756 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
757 static const char f32_12
[] =
758 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
759 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
760 static const char f32_13
[] =
761 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
762 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
763 static const char f32_14
[] =
764 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
765 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
766 static const char f16_3
[] =
767 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
768 static const char f16_4
[] =
769 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
770 static const char f16_5
[] =
772 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
773 static const char f16_6
[] =
774 {0x89,0xf6, /* mov %si,%si */
775 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
776 static const char f16_7
[] =
777 {0x8d,0x74,0x00, /* lea 0(%si),%si */
778 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
779 static const char f16_8
[] =
780 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
781 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
782 static const char jump_31
[] =
783 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
784 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
785 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
786 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
787 static const char *const f32_patt
[] = {
788 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
789 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
791 static const char *const f16_patt
[] = {
792 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
795 static const char alt_3
[] =
797 /* nopl 0(%[re]ax) */
798 static const char alt_4
[] =
799 {0x0f,0x1f,0x40,0x00};
800 /* nopl 0(%[re]ax,%[re]ax,1) */
801 static const char alt_5
[] =
802 {0x0f,0x1f,0x44,0x00,0x00};
803 /* nopw 0(%[re]ax,%[re]ax,1) */
804 static const char alt_6
[] =
805 {0x66,0x0f,0x1f,0x44,0x00,0x00};
806 /* nopl 0L(%[re]ax) */
807 static const char alt_7
[] =
808 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
809 /* nopl 0L(%[re]ax,%[re]ax,1) */
810 static const char alt_8
[] =
811 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
812 /* nopw 0L(%[re]ax,%[re]ax,1) */
813 static const char alt_9
[] =
814 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
815 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
816 static const char alt_10
[] =
817 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
819 nopw %cs:0L(%[re]ax,%[re]ax,1) */
820 static const char alt_long_11
[] =
822 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
825 nopw %cs:0L(%[re]ax,%[re]ax,1) */
826 static const char alt_long_12
[] =
829 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
833 nopw %cs:0L(%[re]ax,%[re]ax,1) */
834 static const char alt_long_13
[] =
838 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
843 nopw %cs:0L(%[re]ax,%[re]ax,1) */
844 static const char alt_long_14
[] =
849 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
855 nopw %cs:0L(%[re]ax,%[re]ax,1) */
856 static const char alt_long_15
[] =
862 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
863 /* nopl 0(%[re]ax,%[re]ax,1)
864 nopw 0(%[re]ax,%[re]ax,1) */
865 static const char alt_short_11
[] =
866 {0x0f,0x1f,0x44,0x00,0x00,
867 0x66,0x0f,0x1f,0x44,0x00,0x00};
868 /* nopw 0(%[re]ax,%[re]ax,1)
869 nopw 0(%[re]ax,%[re]ax,1) */
870 static const char alt_short_12
[] =
871 {0x66,0x0f,0x1f,0x44,0x00,0x00,
872 0x66,0x0f,0x1f,0x44,0x00,0x00};
873 /* nopw 0(%[re]ax,%[re]ax,1)
875 static const char alt_short_13
[] =
876 {0x66,0x0f,0x1f,0x44,0x00,0x00,
877 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
880 static const char alt_short_14
[] =
881 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
882 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
884 nopl 0L(%[re]ax,%[re]ax,1) */
885 static const char alt_short_15
[] =
886 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
887 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
888 static const char *const alt_short_patt
[] = {
889 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
890 alt_9
, alt_10
, alt_short_11
, alt_short_12
, alt_short_13
,
891 alt_short_14
, alt_short_15
893 static const char *const alt_long_patt
[] = {
894 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
895 alt_9
, alt_10
, alt_long_11
, alt_long_12
, alt_long_13
,
896 alt_long_14
, alt_long_15
899 /* Only align for at least a positive non-zero boundary. */
900 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
903 /* We need to decide which NOP sequence to use for 32bit and
904 64bit. When -mtune= is used:
906 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
907 PROCESSOR_GENERIC32, f32_patt will be used.
908 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
909 PROCESSOR_CORE, PROCESSOR_CORE2, and PROCESSOR_GENERIC64,
910 alt_long_patt will be used.
911 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
912 PROCESSOR_AMDFAM10, alt_short_patt will be used.
914 When -mtune= isn't used, alt_long_patt will be used if
915 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
918 When -march= or .arch is used, we can't use anything beyond
919 cpu_arch_isa_flags. */
921 if (flag_code
== CODE_16BIT
)
925 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
927 /* Adjust jump offset. */
928 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
931 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
932 f16_patt
[count
- 1], count
);
936 const char *const *patt
= NULL
;
938 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
940 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
941 switch (cpu_arch_tune
)
943 case PROCESSOR_UNKNOWN
:
944 /* We use cpu_arch_isa_flags to check if we SHOULD
945 optimize for Cpu686. */
946 if (cpu_arch_isa_flags
.bitfield
.cpui686
)
947 patt
= alt_long_patt
;
951 case PROCESSOR_PENTIUMPRO
:
952 case PROCESSOR_PENTIUM4
:
953 case PROCESSOR_NOCONA
:
955 case PROCESSOR_CORE2
:
956 case PROCESSOR_GENERIC64
:
957 patt
= alt_long_patt
;
960 case PROCESSOR_ATHLON
:
962 case PROCESSOR_AMDFAM10
:
963 patt
= alt_short_patt
;
967 case PROCESSOR_PENTIUM
:
968 case PROCESSOR_GENERIC32
:
975 switch (cpu_arch_tune
)
977 case PROCESSOR_UNKNOWN
:
978 /* When cpu_arch_isa is net, cpu_arch_tune shouldn't be
979 PROCESSOR_UNKNOWN. */
985 case PROCESSOR_PENTIUM
:
987 case PROCESSOR_ATHLON
:
989 case PROCESSOR_AMDFAM10
:
990 case PROCESSOR_GENERIC32
:
991 /* We use cpu_arch_isa_flags to check if we CAN optimize
993 if (cpu_arch_isa_flags
.bitfield
.cpui686
)
994 patt
= alt_short_patt
;
998 case PROCESSOR_PENTIUMPRO
:
999 case PROCESSOR_PENTIUM4
:
1000 case PROCESSOR_NOCONA
:
1001 case PROCESSOR_CORE
:
1002 case PROCESSOR_CORE2
:
1003 if (cpu_arch_isa_flags
.bitfield
.cpui686
)
1004 patt
= alt_long_patt
;
1008 case PROCESSOR_GENERIC64
:
1009 patt
= alt_long_patt
;
1014 if (patt
== f32_patt
)
1016 /* If the padding is less than 15 bytes, we use the normal
1017 ones. Otherwise, we use a jump instruction and adjust
1020 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1021 patt
[count
- 1], count
);
1024 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1026 /* Adjust jump offset. */
1027 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1032 /* Maximum length of an instruction is 15 byte. If the
1033 padding is greater than 15 bytes and we don't use jump,
1034 we have to break it into smaller pieces. */
1035 int padding
= count
;
1036 while (padding
> 15)
1039 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1044 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1045 patt
[padding
- 1], padding
);
1048 fragP
->fr_var
= count
;
1052 operand_type_all_zero (const union i386_operand_type
*x
)
1054 switch (ARRAY_SIZE(x
->array
))
1063 return !x
->array
[0];
1070 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1072 switch (ARRAY_SIZE(x
->array
))
1087 operand_type_equal (const union i386_operand_type
*x
,
1088 const union i386_operand_type
*y
)
1090 switch (ARRAY_SIZE(x
->array
))
1093 if (x
->array
[2] != y
->array
[2])
1096 if (x
->array
[1] != y
->array
[1])
1099 return x
->array
[0] == y
->array
[0];
1107 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1109 switch (ARRAY_SIZE(x
->array
))
1118 return !x
->array
[0];
1125 cpu_flags_set (union i386_cpu_flags
*x
, unsigned int v
)
1127 switch (ARRAY_SIZE(x
->array
))
1142 cpu_flags_equal (const union i386_cpu_flags
*x
,
1143 const union i386_cpu_flags
*y
)
1145 switch (ARRAY_SIZE(x
->array
))
1148 if (x
->array
[2] != y
->array
[2])
1151 if (x
->array
[1] != y
->array
[1])
1154 return x
->array
[0] == y
->array
[0];
1162 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1164 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1165 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1168 static INLINE i386_cpu_flags
1169 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1171 switch (ARRAY_SIZE (x
.array
))
1174 x
.array
[2] &= y
.array
[2];
1176 x
.array
[1] &= y
.array
[1];
1178 x
.array
[0] &= y
.array
[0];
1186 static INLINE i386_cpu_flags
1187 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1189 switch (ARRAY_SIZE (x
.array
))
1192 x
.array
[2] |= y
.array
[2];
1194 x
.array
[1] |= y
.array
[1];
1196 x
.array
[0] |= y
.array
[0];
1204 #define CPU_FLAGS_ARCH_MATCH 0x1
1205 #define CPU_FLAGS_64BIT_MATCH 0x2
1207 #define CPU_FLAGS_32BIT_MATCH CPU_FLAGS_ARCH_MATCH
1208 #define CPU_FLAGS_PERFECT_MATCH \
1209 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1211 /* Return CPU flags match bits. */
1214 cpu_flags_match (const template *t
)
1216 i386_cpu_flags x
= t
->cpu_flags
;
1217 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1219 x
.bitfield
.cpu64
= 0;
1220 x
.bitfield
.cpuno64
= 0;
1222 if (cpu_flags_all_zero (&x
))
1224 /* This instruction is available on all archs. */
1225 match
|= CPU_FLAGS_32BIT_MATCH
;
1229 /* This instruction is available only on some archs. */
1230 i386_cpu_flags cpu
= cpu_arch_flags
;
1232 cpu
.bitfield
.cpu64
= 0;
1233 cpu
.bitfield
.cpuno64
= 0;
1234 cpu
= cpu_flags_and (x
, cpu
);
1235 if (!cpu_flags_all_zero (&cpu
))
1238 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1239 match
|= CPU_FLAGS_32BIT_MATCH
;
1245 static INLINE i386_operand_type
1246 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1248 switch (ARRAY_SIZE (x
.array
))
1251 x
.array
[2] &= y
.array
[2];
1253 x
.array
[1] &= y
.array
[1];
1255 x
.array
[0] &= y
.array
[0];
1263 static INLINE i386_operand_type
1264 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1266 switch (ARRAY_SIZE (x
.array
))
1269 x
.array
[2] |= y
.array
[2];
1271 x
.array
[1] |= y
.array
[1];
1273 x
.array
[0] |= y
.array
[0];
1281 static INLINE i386_operand_type
1282 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1284 switch (ARRAY_SIZE (x
.array
))
1287 x
.array
[2] ^= y
.array
[2];
1289 x
.array
[1] ^= y
.array
[1];
1291 x
.array
[0] ^= y
.array
[0];
1299 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1300 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1301 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1302 static const i386_operand_type inoutportreg
1303 = OPERAND_TYPE_INOUTPORTREG
;
1304 static const i386_operand_type reg16_inoutportreg
1305 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1306 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1307 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1308 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1309 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1310 static const i386_operand_type anydisp
1311 = OPERAND_TYPE_ANYDISP
;
1312 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1313 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1314 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1315 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1316 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1317 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1318 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1319 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1320 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1321 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1322 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1323 static const i386_operand_type vex_imm4
= OPERAND_TYPE_VEX_IMM4
;
1334 operand_type_check (i386_operand_type t
, enum operand_type c
)
1339 return (t
.bitfield
.reg8
1342 || t
.bitfield
.reg64
);
1345 return (t
.bitfield
.imm8
1349 || t
.bitfield
.imm32s
1350 || t
.bitfield
.imm64
);
1353 return (t
.bitfield
.disp8
1354 || t
.bitfield
.disp16
1355 || t
.bitfield
.disp32
1356 || t
.bitfield
.disp32s
1357 || t
.bitfield
.disp64
);
1360 return (t
.bitfield
.disp8
1361 || t
.bitfield
.disp16
1362 || t
.bitfield
.disp32
1363 || t
.bitfield
.disp32s
1364 || t
.bitfield
.disp64
1365 || t
.bitfield
.baseindex
);
1372 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1373 operand J for instruction template T. */
1376 match_reg_size (const template *t
, unsigned int j
)
1378 return !((i
.types
[j
].bitfield
.byte
1379 && !t
->operand_types
[j
].bitfield
.byte
)
1380 || (i
.types
[j
].bitfield
.word
1381 && !t
->operand_types
[j
].bitfield
.word
)
1382 || (i
.types
[j
].bitfield
.dword
1383 && !t
->operand_types
[j
].bitfield
.dword
)
1384 || (i
.types
[j
].bitfield
.qword
1385 && !t
->operand_types
[j
].bitfield
.qword
));
1388 /* Return 1 if there is no conflict in any size on operand J for
1389 instruction template T. */
1392 match_mem_size (const template *t
, unsigned int j
)
1394 return (match_reg_size (t
, j
)
1395 && !((i
.types
[j
].bitfield
.unspecified
1396 && !t
->operand_types
[j
].bitfield
.unspecified
)
1397 || (i
.types
[j
].bitfield
.fword
1398 && !t
->operand_types
[j
].bitfield
.fword
)
1399 || (i
.types
[j
].bitfield
.tbyte
1400 && !t
->operand_types
[j
].bitfield
.tbyte
)
1401 || (i
.types
[j
].bitfield
.xmmword
1402 && !t
->operand_types
[j
].bitfield
.xmmword
)
1403 || (i
.types
[j
].bitfield
.ymmword
1404 && !t
->operand_types
[j
].bitfield
.ymmword
)));
1407 /* Return 1 if there is no size conflict on any operands for
1408 instruction template T. */
1411 operand_size_match (const template *t
)
1416 /* Don't check jump instructions. */
1417 if (t
->opcode_modifier
.jump
1418 || t
->opcode_modifier
.jumpbyte
1419 || t
->opcode_modifier
.jumpdword
1420 || t
->opcode_modifier
.jumpintersegment
)
1423 /* Check memory and accumulator operand size. */
1424 for (j
= 0; j
< i
.operands
; j
++)
1426 if (t
->operand_types
[j
].bitfield
.anysize
)
1429 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1435 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1443 || (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
))
1446 /* Check reverse. */
1447 assert (i
.operands
== 2);
1450 for (j
= 0; j
< 2; j
++)
1452 if (t
->operand_types
[j
].bitfield
.acc
1453 && !match_reg_size (t
, j
? 0 : 1))
1459 if (i
.types
[j
].bitfield
.mem
1460 && !match_mem_size (t
, j
? 0 : 1))
1471 operand_type_match (i386_operand_type overlap
,
1472 i386_operand_type given
)
1474 i386_operand_type temp
= overlap
;
1476 temp
.bitfield
.jumpabsolute
= 0;
1477 temp
.bitfield
.unspecified
= 0;
1478 temp
.bitfield
.byte
= 0;
1479 temp
.bitfield
.word
= 0;
1480 temp
.bitfield
.dword
= 0;
1481 temp
.bitfield
.fword
= 0;
1482 temp
.bitfield
.qword
= 0;
1483 temp
.bitfield
.tbyte
= 0;
1484 temp
.bitfield
.xmmword
= 0;
1485 temp
.bitfield
.ymmword
= 0;
1486 if (operand_type_all_zero (&temp
))
1489 return (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1490 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
);
1493 /* If given types g0 and g1 are registers they must be of the same type
1494 unless the expected operand type register overlap is null.
1495 Note that Acc in a template matches every size of reg. */
1498 operand_type_register_match (i386_operand_type m0
,
1499 i386_operand_type g0
,
1500 i386_operand_type t0
,
1501 i386_operand_type m1
,
1502 i386_operand_type g1
,
1503 i386_operand_type t1
)
1505 if (!operand_type_check (g0
, reg
))
1508 if (!operand_type_check (g1
, reg
))
1511 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1512 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1513 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1514 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1517 if (m0
.bitfield
.acc
)
1519 t0
.bitfield
.reg8
= 1;
1520 t0
.bitfield
.reg16
= 1;
1521 t0
.bitfield
.reg32
= 1;
1522 t0
.bitfield
.reg64
= 1;
1525 if (m1
.bitfield
.acc
)
1527 t1
.bitfield
.reg8
= 1;
1528 t1
.bitfield
.reg16
= 1;
1529 t1
.bitfield
.reg32
= 1;
1530 t1
.bitfield
.reg64
= 1;
1533 return (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1534 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1535 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1536 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
));
1539 static INLINE
unsigned int
1540 mode_from_disp_size (i386_operand_type t
)
1542 if (t
.bitfield
.disp8
)
1544 else if (t
.bitfield
.disp16
1545 || t
.bitfield
.disp32
1546 || t
.bitfield
.disp32s
)
1553 fits_in_signed_byte (offsetT num
)
1555 return (num
>= -128) && (num
<= 127);
1559 fits_in_unsigned_byte (offsetT num
)
1561 return (num
& 0xff) == num
;
1565 fits_in_unsigned_word (offsetT num
)
1567 return (num
& 0xffff) == num
;
1571 fits_in_signed_word (offsetT num
)
1573 return (-32768 <= num
) && (num
<= 32767);
1577 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED
)
1582 return (!(((offsetT
) -1 << 31) & num
)
1583 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
1585 } /* fits_in_signed_long() */
1588 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED
)
1593 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
1595 } /* fits_in_unsigned_long() */
1598 fits_in_imm4 (offsetT num
)
1600 return (num
& 0xf) == num
;
1603 static i386_operand_type
1604 smallest_imm_type (offsetT num
)
1606 i386_operand_type t
;
1608 operand_type_set (&t
, 0);
1609 t
.bitfield
.imm64
= 1;
1611 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
1613 /* This code is disabled on the 486 because all the Imm1 forms
1614 in the opcode table are slower on the i486. They're the
1615 versions with the implicitly specified single-position
1616 displacement, which has another syntax if you really want to
1618 t
.bitfield
.imm1
= 1;
1619 t
.bitfield
.imm8
= 1;
1620 t
.bitfield
.imm8s
= 1;
1621 t
.bitfield
.imm16
= 1;
1622 t
.bitfield
.imm32
= 1;
1623 t
.bitfield
.imm32s
= 1;
1625 else if (fits_in_signed_byte (num
))
1627 t
.bitfield
.imm8
= 1;
1628 t
.bitfield
.imm8s
= 1;
1629 t
.bitfield
.imm16
= 1;
1630 t
.bitfield
.imm32
= 1;
1631 t
.bitfield
.imm32s
= 1;
1633 else if (fits_in_unsigned_byte (num
))
1635 t
.bitfield
.imm8
= 1;
1636 t
.bitfield
.imm16
= 1;
1637 t
.bitfield
.imm32
= 1;
1638 t
.bitfield
.imm32s
= 1;
1640 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
1642 t
.bitfield
.imm16
= 1;
1643 t
.bitfield
.imm32
= 1;
1644 t
.bitfield
.imm32s
= 1;
1646 else if (fits_in_signed_long (num
))
1648 t
.bitfield
.imm32
= 1;
1649 t
.bitfield
.imm32s
= 1;
1651 else if (fits_in_unsigned_long (num
))
1652 t
.bitfield
.imm32
= 1;
1658 offset_in_range (offsetT val
, int size
)
1664 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
1665 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
1666 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
1668 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
1673 /* If BFD64, sign extend val. */
1674 if (!use_rela_relocations
)
1675 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
1676 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
1678 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
1680 char buf1
[40], buf2
[40];
1682 sprint_value (buf1
, val
);
1683 sprint_value (buf2
, val
& mask
);
1684 as_warn (_("%s shortened to %s"), buf1
, buf2
);
1689 /* Returns 0 if attempting to add a prefix where one from the same
1690 class already exists, 1 if non rep/repne added, 2 if rep/repne
1693 add_prefix (unsigned int prefix
)
1698 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
1699 && flag_code
== CODE_64BIT
)
1701 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
1702 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
1703 && (prefix
& (REX_R
| REX_X
| REX_B
))))
1714 case CS_PREFIX_OPCODE
:
1715 case DS_PREFIX_OPCODE
:
1716 case ES_PREFIX_OPCODE
:
1717 case FS_PREFIX_OPCODE
:
1718 case GS_PREFIX_OPCODE
:
1719 case SS_PREFIX_OPCODE
:
1723 case REPNE_PREFIX_OPCODE
:
1724 case REPE_PREFIX_OPCODE
:
1727 case LOCK_PREFIX_OPCODE
:
1735 case ADDR_PREFIX_OPCODE
:
1739 case DATA_PREFIX_OPCODE
:
1743 if (i
.prefix
[q
] != 0)
1751 i
.prefix
[q
] |= prefix
;
1754 as_bad (_("same type of prefix used twice"));
1760 set_code_flag (int value
)
1763 if (flag_code
== CODE_64BIT
)
1765 cpu_arch_flags
.bitfield
.cpu64
= 1;
1766 cpu_arch_flags
.bitfield
.cpuno64
= 0;
1770 cpu_arch_flags
.bitfield
.cpu64
= 0;
1771 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1773 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
1775 as_bad (_("64bit mode not supported on this CPU."));
1777 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
1779 as_bad (_("32bit mode not supported on this CPU."));
1781 stackop_size
= '\0';
1785 set_16bit_gcc_code_flag (int new_code_flag
)
1787 flag_code
= new_code_flag
;
1788 if (flag_code
!= CODE_16BIT
)
1790 cpu_arch_flags
.bitfield
.cpu64
= 0;
1791 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1792 stackop_size
= LONG_MNEM_SUFFIX
;
1796 set_intel_syntax (int syntax_flag
)
1798 /* Find out if register prefixing is specified. */
1799 int ask_naked_reg
= 0;
1802 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1804 char *string
= input_line_pointer
;
1805 int e
= get_symbol_end ();
1807 if (strcmp (string
, "prefix") == 0)
1809 else if (strcmp (string
, "noprefix") == 0)
1812 as_bad (_("bad argument to syntax directive."));
1813 *input_line_pointer
= e
;
1815 demand_empty_rest_of_line ();
1817 intel_syntax
= syntax_flag
;
1819 if (ask_naked_reg
== 0)
1820 allow_naked_reg
= (intel_syntax
1821 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
1823 allow_naked_reg
= (ask_naked_reg
< 0);
1825 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
1826 identifier_chars
['$'] = intel_syntax
? '$' : 0;
1827 register_prefix
= allow_naked_reg
? "" : "%";
1831 set_intel_mnemonic (int mnemonic_flag
)
1833 intel_mnemonic
= mnemonic_flag
;
1837 set_allow_index_reg (int flag
)
1839 allow_index_reg
= flag
;
1843 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
1847 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1849 char *string
= input_line_pointer
;
1850 int e
= get_symbol_end ();
1852 i386_cpu_flags flags
;
1854 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
1856 if (strcmp (string
, cpu_arch
[i
].name
) == 0)
1860 cpu_arch_name
= cpu_arch
[i
].name
;
1861 cpu_sub_arch_name
= NULL
;
1862 cpu_arch_flags
= cpu_arch
[i
].flags
;
1863 if (flag_code
== CODE_64BIT
)
1865 cpu_arch_flags
.bitfield
.cpu64
= 1;
1866 cpu_arch_flags
.bitfield
.cpuno64
= 0;
1870 cpu_arch_flags
.bitfield
.cpu64
= 0;
1871 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1873 cpu_arch_isa
= cpu_arch
[i
].type
;
1874 cpu_arch_isa_flags
= cpu_arch
[i
].flags
;
1875 if (!cpu_arch_tune_set
)
1877 cpu_arch_tune
= cpu_arch_isa
;
1878 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
1883 flags
= cpu_flags_or (cpu_arch_flags
,
1885 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
1887 if (cpu_sub_arch_name
)
1889 char *name
= cpu_sub_arch_name
;
1890 cpu_sub_arch_name
= concat (name
,
1892 (const char *) NULL
);
1896 cpu_sub_arch_name
= xstrdup (cpu_arch
[i
].name
);
1897 cpu_arch_flags
= flags
;
1899 *input_line_pointer
= e
;
1900 demand_empty_rest_of_line ();
1904 if (i
>= ARRAY_SIZE (cpu_arch
))
1905 as_bad (_("no such architecture: `%s'"), string
);
1907 *input_line_pointer
= e
;
1910 as_bad (_("missing cpu architecture"));
1912 no_cond_jump_promotion
= 0;
1913 if (*input_line_pointer
== ','
1914 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
1916 char *string
= ++input_line_pointer
;
1917 int e
= get_symbol_end ();
1919 if (strcmp (string
, "nojumps") == 0)
1920 no_cond_jump_promotion
= 1;
1921 else if (strcmp (string
, "jumps") == 0)
1924 as_bad (_("no such architecture modifier: `%s'"), string
);
1926 *input_line_pointer
= e
;
1929 demand_empty_rest_of_line ();
1935 if (!strcmp (default_arch
, "x86_64"))
1936 return bfd_mach_x86_64
;
1937 else if (!strcmp (default_arch
, "i386"))
1938 return bfd_mach_i386_i386
;
1940 as_fatal (_("Unknown architecture"));
1946 const char *hash_err
;
1948 /* Initialize op_hash hash table. */
1949 op_hash
= hash_new ();
1952 const template *optab
;
1953 templates
*core_optab
;
1955 /* Setup for loop. */
1957 core_optab
= (templates
*) xmalloc (sizeof (templates
));
1958 core_optab
->start
= optab
;
1963 if (optab
->name
== NULL
1964 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
1966 /* different name --> ship out current template list;
1967 add to hash table; & begin anew. */
1968 core_optab
->end
= optab
;
1969 hash_err
= hash_insert (op_hash
,
1974 as_fatal (_("Internal Error: Can't hash %s: %s"),
1978 if (optab
->name
== NULL
)
1980 core_optab
= (templates
*) xmalloc (sizeof (templates
));
1981 core_optab
->start
= optab
;
1986 /* Initialize reg_hash hash table. */
1987 reg_hash
= hash_new ();
1989 const reg_entry
*regtab
;
1990 unsigned int regtab_size
= i386_regtab_size
;
1992 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
1994 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (PTR
) regtab
);
1996 as_fatal (_("Internal Error: Can't hash %s: %s"),
2002 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2007 for (c
= 0; c
< 256; c
++)
2012 mnemonic_chars
[c
] = c
;
2013 register_chars
[c
] = c
;
2014 operand_chars
[c
] = c
;
2016 else if (ISLOWER (c
))
2018 mnemonic_chars
[c
] = c
;
2019 register_chars
[c
] = c
;
2020 operand_chars
[c
] = c
;
2022 else if (ISUPPER (c
))
2024 mnemonic_chars
[c
] = TOLOWER (c
);
2025 register_chars
[c
] = mnemonic_chars
[c
];
2026 operand_chars
[c
] = c
;
2029 if (ISALPHA (c
) || ISDIGIT (c
))
2030 identifier_chars
[c
] = c
;
2033 identifier_chars
[c
] = c
;
2034 operand_chars
[c
] = c
;
2039 identifier_chars
['@'] = '@';
2042 identifier_chars
['?'] = '?';
2043 operand_chars
['?'] = '?';
2045 digit_chars
['-'] = '-';
2046 mnemonic_chars
['_'] = '_';
2047 mnemonic_chars
['-'] = '-';
2048 mnemonic_chars
['.'] = '.';
2049 identifier_chars
['_'] = '_';
2050 identifier_chars
['.'] = '.';
2052 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2053 operand_chars
[(unsigned char) *p
] = *p
;
2056 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2059 record_alignment (text_section
, 2);
2060 record_alignment (data_section
, 2);
2061 record_alignment (bss_section
, 2);
2065 if (flag_code
== CODE_64BIT
)
2067 x86_dwarf2_return_column
= 16;
2068 x86_cie_data_alignment
= -8;
2072 x86_dwarf2_return_column
= 8;
2073 x86_cie_data_alignment
= -4;
2078 i386_print_statistics (FILE *file
)
2080 hash_print_statistics (file
, "i386 opcode", op_hash
);
2081 hash_print_statistics (file
, "i386 register", reg_hash
);
2086 /* Debugging routines for md_assemble. */
2087 static void pte (template *);
2088 static void pt (i386_operand_type
);
2089 static void pe (expressionS
*);
2090 static void ps (symbolS
*);
2093 pi (char *line
, i386_insn
*x
)
2097 fprintf (stdout
, "%s: template ", line
);
2099 fprintf (stdout
, " address: base %s index %s scale %x\n",
2100 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2101 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2102 x
->log2_scale_factor
);
2103 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2104 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2105 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2106 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2107 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2108 (x
->rex
& REX_W
) != 0,
2109 (x
->rex
& REX_R
) != 0,
2110 (x
->rex
& REX_X
) != 0,
2111 (x
->rex
& REX_B
) != 0);
2112 fprintf (stdout
, " drex: reg %d rex 0x%x\n",
2113 x
->drex
.reg
, x
->drex
.rex
);
2114 for (i
= 0; i
< x
->operands
; i
++)
2116 fprintf (stdout
, " #%d: ", i
+ 1);
2118 fprintf (stdout
, "\n");
2119 if (x
->types
[i
].bitfield
.reg8
2120 || x
->types
[i
].bitfield
.reg16
2121 || x
->types
[i
].bitfield
.reg32
2122 || x
->types
[i
].bitfield
.reg64
2123 || x
->types
[i
].bitfield
.regmmx
2124 || x
->types
[i
].bitfield
.regxmm
2125 || x
->types
[i
].bitfield
.regymm
2126 || x
->types
[i
].bitfield
.sreg2
2127 || x
->types
[i
].bitfield
.sreg3
2128 || x
->types
[i
].bitfield
.control
2129 || x
->types
[i
].bitfield
.debug
2130 || x
->types
[i
].bitfield
.test
)
2131 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
2132 if (operand_type_check (x
->types
[i
], imm
))
2134 if (operand_type_check (x
->types
[i
], disp
))
2135 pe (x
->op
[i
].disps
);
2143 fprintf (stdout
, " %d operands ", t
->operands
);
2144 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2145 if (t
->extension_opcode
!= None
)
2146 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2147 if (t
->opcode_modifier
.d
)
2148 fprintf (stdout
, "D");
2149 if (t
->opcode_modifier
.w
)
2150 fprintf (stdout
, "W");
2151 fprintf (stdout
, "\n");
2152 for (i
= 0; i
< t
->operands
; i
++)
2154 fprintf (stdout
, " #%d type ", i
+ 1);
2155 pt (t
->operand_types
[i
]);
2156 fprintf (stdout
, "\n");
2163 fprintf (stdout
, " operation %d\n", e
->X_op
);
2164 fprintf (stdout
, " add_number %ld (%lx)\n",
2165 (long) e
->X_add_number
, (long) e
->X_add_number
);
2166 if (e
->X_add_symbol
)
2168 fprintf (stdout
, " add_symbol ");
2169 ps (e
->X_add_symbol
);
2170 fprintf (stdout
, "\n");
2174 fprintf (stdout
, " op_symbol ");
2175 ps (e
->X_op_symbol
);
2176 fprintf (stdout
, "\n");
2183 fprintf (stdout
, "%s type %s%s",
2185 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2186 segment_name (S_GET_SEGMENT (s
)));
2189 static struct type_name
2191 i386_operand_type mask
;
2194 const type_names
[] =
2196 { OPERAND_TYPE_REG8
, "r8" },
2197 { OPERAND_TYPE_REG16
, "r16" },
2198 { OPERAND_TYPE_REG32
, "r32" },
2199 { OPERAND_TYPE_REG64
, "r64" },
2200 { OPERAND_TYPE_IMM8
, "i8" },
2201 { OPERAND_TYPE_IMM8
, "i8s" },
2202 { OPERAND_TYPE_IMM16
, "i16" },
2203 { OPERAND_TYPE_IMM32
, "i32" },
2204 { OPERAND_TYPE_IMM32S
, "i32s" },
2205 { OPERAND_TYPE_IMM64
, "i64" },
2206 { OPERAND_TYPE_IMM1
, "i1" },
2207 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2208 { OPERAND_TYPE_DISP8
, "d8" },
2209 { OPERAND_TYPE_DISP16
, "d16" },
2210 { OPERAND_TYPE_DISP32
, "d32" },
2211 { OPERAND_TYPE_DISP32S
, "d32s" },
2212 { OPERAND_TYPE_DISP64
, "d64" },
2213 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2214 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2215 { OPERAND_TYPE_CONTROL
, "control reg" },
2216 { OPERAND_TYPE_TEST
, "test reg" },
2217 { OPERAND_TYPE_DEBUG
, "debug reg" },
2218 { OPERAND_TYPE_FLOATREG
, "FReg" },
2219 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2220 { OPERAND_TYPE_SREG2
, "SReg2" },
2221 { OPERAND_TYPE_SREG3
, "SReg3" },
2222 { OPERAND_TYPE_ACC
, "Acc" },
2223 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2224 { OPERAND_TYPE_REGMMX
, "rMMX" },
2225 { OPERAND_TYPE_REGXMM
, "rXMM" },
2226 { OPERAND_TYPE_ESSEG
, "es" },
2227 { OPERAND_TYPE_VEX_IMM4
, "VEX i4" },
2231 pt (i386_operand_type t
)
2234 i386_operand_type a
;
2236 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2238 a
= operand_type_and (t
, type_names
[j
].mask
);
2239 if (!UINTS_ALL_ZERO (a
))
2240 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2245 #endif /* DEBUG386 */
2247 static bfd_reloc_code_real_type
2248 reloc (unsigned int size
,
2251 bfd_reloc_code_real_type other
)
2253 if (other
!= NO_RELOC
)
2255 reloc_howto_type
*reloc
;
2260 case BFD_RELOC_X86_64_GOT32
:
2261 return BFD_RELOC_X86_64_GOT64
;
2263 case BFD_RELOC_X86_64_PLTOFF64
:
2264 return BFD_RELOC_X86_64_PLTOFF64
;
2266 case BFD_RELOC_X86_64_GOTPC32
:
2267 other
= BFD_RELOC_X86_64_GOTPC64
;
2269 case BFD_RELOC_X86_64_GOTPCREL
:
2270 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2272 case BFD_RELOC_X86_64_TPOFF32
:
2273 other
= BFD_RELOC_X86_64_TPOFF64
;
2275 case BFD_RELOC_X86_64_DTPOFF32
:
2276 other
= BFD_RELOC_X86_64_DTPOFF64
;
2282 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2283 if (size
== 4 && flag_code
!= CODE_64BIT
)
2286 reloc
= bfd_reloc_type_lookup (stdoutput
, other
);
2288 as_bad (_("unknown relocation (%u)"), other
);
2289 else if (size
!= bfd_get_reloc_size (reloc
))
2290 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2291 bfd_get_reloc_size (reloc
),
2293 else if (pcrel
&& !reloc
->pc_relative
)
2294 as_bad (_("non-pc-relative relocation for pc-relative field"));
2295 else if ((reloc
->complain_on_overflow
== complain_overflow_signed
2297 || (reloc
->complain_on_overflow
== complain_overflow_unsigned
2299 as_bad (_("relocated field and relocation type differ in signedness"));
2308 as_bad (_("there are no unsigned pc-relative relocations"));
2311 case 1: return BFD_RELOC_8_PCREL
;
2312 case 2: return BFD_RELOC_16_PCREL
;
2313 case 4: return BFD_RELOC_32_PCREL
;
2314 case 8: return BFD_RELOC_64_PCREL
;
2316 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
2323 case 4: return BFD_RELOC_X86_64_32S
;
2328 case 1: return BFD_RELOC_8
;
2329 case 2: return BFD_RELOC_16
;
2330 case 4: return BFD_RELOC_32
;
2331 case 8: return BFD_RELOC_64
;
2333 as_bad (_("cannot do %s %u byte relocation"),
2334 sign
> 0 ? "signed" : "unsigned", size
);
2338 return BFD_RELOC_NONE
;
2341 /* Here we decide which fixups can be adjusted to make them relative to
2342 the beginning of the section instead of the symbol. Basically we need
2343 to make sure that the dynamic relocations are done correctly, so in
2344 some cases we force the original symbol to be used. */
2347 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
2349 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2353 /* Don't adjust pc-relative references to merge sections in 64-bit
2355 if (use_rela_relocations
2356 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
2360 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2361 and changed later by validate_fix. */
2362 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
2363 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
2366 /* adjust_reloc_syms doesn't know about the GOT. */
2367 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
2368 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
2369 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
2370 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
2371 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
2372 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
2373 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
2374 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
2375 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
2376 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
2377 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
2378 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
2379 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
2380 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
2381 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
2382 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
2383 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
2384 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
2385 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
2386 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
2387 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
2388 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
2389 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
2390 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
2391 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
2392 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
2393 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
2394 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
2401 intel_float_operand (const char *mnemonic
)
2403 /* Note that the value returned is meaningful only for opcodes with (memory)
2404 operands, hence the code here is free to improperly handle opcodes that
2405 have no operands (for better performance and smaller code). */
2407 if (mnemonic
[0] != 'f')
2408 return 0; /* non-math */
2410 switch (mnemonic
[1])
2412 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2413 the fs segment override prefix not currently handled because no
2414 call path can make opcodes without operands get here */
2416 return 2 /* integer op */;
2418 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
2419 return 3; /* fldcw/fldenv */
2422 if (mnemonic
[2] != 'o' /* fnop */)
2423 return 3; /* non-waiting control op */
2426 if (mnemonic
[2] == 's')
2427 return 3; /* frstor/frstpm */
2430 if (mnemonic
[2] == 'a')
2431 return 3; /* fsave */
2432 if (mnemonic
[2] == 't')
2434 switch (mnemonic
[3])
2436 case 'c': /* fstcw */
2437 case 'd': /* fstdw */
2438 case 'e': /* fstenv */
2439 case 's': /* fsts[gw] */
2445 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
2446 return 0; /* fxsave/fxrstor are not really math ops */
2453 /* Build the VEX prefix. */
2456 build_vex_prefix (void)
2458 unsigned int register_specifier
;
2459 unsigned int implied_prefix
;
2460 unsigned int vector_length
;
2462 /* Check register specifier. */
2463 if (i
.vex
.register_specifier
)
2465 register_specifier
= i
.vex
.register_specifier
->reg_num
;
2466 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
2467 register_specifier
+= 8;
2468 register_specifier
= ~register_specifier
& 0xf;
2471 register_specifier
= 0xf;
2473 vector_length
= i
.tm
.opcode_modifier
.vex256
? 1 : 0;
2475 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
2480 case DATA_PREFIX_OPCODE
:
2483 case REPE_PREFIX_OPCODE
:
2486 case REPNE_PREFIX_OPCODE
:
2493 /* Use 2-byte VEX prefix if possible. */
2494 if (i
.tm
.opcode_modifier
.vex0f
2495 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
2497 /* 2-byte VEX prefix. */
2501 i
.vex
.bytes
[0] = 0xc5;
2503 /* Check the REX.R bit. */
2504 r
= (i
.rex
& REX_R
) ? 0 : 1;
2505 i
.vex
.bytes
[1] = (r
<< 7
2506 | register_specifier
<< 3
2507 | vector_length
<< 2
2512 /* 3-byte VEX prefix. */
2515 if (i
.tm
.opcode_modifier
.vex0f
)
2517 else if (i
.tm
.opcode_modifier
.vex0f38
)
2519 else if (i
.tm
.opcode_modifier
.vex0f3a
)
2525 i
.vex
.bytes
[0] = 0xc4;
2527 /* The high 3 bits of the second VEX byte are 1's compliment
2528 of RXB bits from REX. */
2529 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
2531 /* Check the REX.W bit. */
2532 w
= (i
.rex
& REX_W
) ? 1 : 0;
2533 if (i
.tm
.opcode_modifier
.vexw0
|| i
.tm
.opcode_modifier
.vexw1
)
2538 if (i
.tm
.opcode_modifier
.vexw1
)
2542 i
.vex
.bytes
[2] = (w
<< 7
2543 | register_specifier
<< 3
2544 | vector_length
<< 2
2550 process_immext (void)
2554 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
&& i
.operands
> 0)
2556 /* SSE3 Instructions have the fixed operands with an opcode
2557 suffix which is coded in the same place as an 8-bit immediate
2558 field would be. Here we check those operands and remove them
2562 for (x
= 0; x
< i
.operands
; x
++)
2563 if (i
.op
[x
].regs
->reg_num
!= x
)
2564 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
2565 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
2571 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
2572 which is coded in the same place as an 8-bit immediate field
2573 would be. Here we fake an 8-bit immediate operand from the
2574 opcode suffix stored in tm.extension_opcode.
2576 SSE5 and AVX instructions also use this encoding, for some of
2577 3 argument instructions. */
2579 assert (i
.imm_operands
== 0
2581 || (i
.tm
.cpu_flags
.bitfield
.cpusse5
2583 || (i
.tm
.opcode_modifier
.vex
2584 && i
.operands
<= 4)));
2586 exp
= &im_expressions
[i
.imm_operands
++];
2587 i
.op
[i
.operands
].imms
= exp
;
2588 i
.types
[i
.operands
] = imm8
;
2590 exp
->X_op
= O_constant
;
2591 exp
->X_add_number
= i
.tm
.extension_opcode
;
2592 i
.tm
.extension_opcode
= None
;
2595 /* This is the guts of the machine-dependent assembler. LINE points to a
2596 machine dependent instruction. This function is supposed to emit
2597 the frags/bytes it assembles to. */
2600 md_assemble (char *line
)
2603 char mnemonic
[MAX_MNEM_SIZE
];
2605 /* Initialize globals. */
2606 memset (&i
, '\0', sizeof (i
));
2607 for (j
= 0; j
< MAX_OPERANDS
; j
++)
2608 i
.reloc
[j
] = NO_RELOC
;
2609 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
2610 memset (im_expressions
, '\0', sizeof (im_expressions
));
2611 save_stack_p
= save_stack
;
2613 /* First parse an instruction mnemonic & call i386_operand for the operands.
2614 We assume that the scrubber has arranged it so that line[0] is the valid
2615 start of a (possibly prefixed) mnemonic. */
2617 line
= parse_insn (line
, mnemonic
);
2621 line
= parse_operands (line
, mnemonic
);
2625 /* Now we've parsed the mnemonic into a set of templates, and have the
2626 operands at hand. */
2628 /* All intel opcodes have reversed operands except for "bound" and
2629 "enter". We also don't reverse intersegment "jmp" and "call"
2630 instructions with 2 immediate operands so that the immediate segment
2631 precedes the offset, as it does when in AT&T mode. */
2634 && (strcmp (mnemonic
, "bound") != 0)
2635 && (strcmp (mnemonic
, "invlpga") != 0)
2636 && !(operand_type_check (i
.types
[0], imm
)
2637 && operand_type_check (i
.types
[1], imm
)))
2640 /* The order of the immediates should be reversed
2641 for 2 immediates extrq and insertq instructions */
2642 if (i
.imm_operands
== 2
2643 && (strcmp (mnemonic
, "extrq") == 0
2644 || strcmp (mnemonic
, "insertq") == 0))
2645 swap_2_operands (0, 1);
2650 /* Don't optimize displacement for movabs since it only takes 64bit
2653 && (flag_code
!= CODE_64BIT
2654 || strcmp (mnemonic
, "movabs") != 0))
2657 /* Next, we find a template that matches the given insn,
2658 making sure the overlap of the given operands types is consistent
2659 with the template operand types. */
2661 if (!match_template ())
2664 /* Zap movzx and movsx suffix. The suffix has been set from
2665 "word ptr" or "byte ptr" on the source operand in Intel syntax
2666 or extracted from mnemonic in AT&T syntax. But we'll use
2667 the destination register to choose the suffix for encoding. */
2668 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
2670 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
2671 there is no suffix, the default will be byte extension. */
2672 if (i
.reg_operands
!= 2
2675 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
2680 if (i
.tm
.opcode_modifier
.fwait
)
2681 if (!add_prefix (FWAIT_OPCODE
))
2684 /* Check string instruction segment overrides. */
2685 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
2687 if (!check_string ())
2691 if (!process_suffix ())
2694 /* Make still unresolved immediate matches conform to size of immediate
2695 given in i.suffix. */
2696 if (!finalize_imm ())
2699 if (i
.types
[0].bitfield
.imm1
)
2700 i
.imm_operands
= 0; /* kludge for shift insns. */
2702 for (j
= 0; j
< 3; j
++)
2703 if (i
.types
[j
].bitfield
.inoutportreg
2704 || i
.types
[j
].bitfield
.shiftcount
2705 || i
.types
[j
].bitfield
.acc
2706 || i
.types
[j
].bitfield
.floatacc
)
2709 /* ImmExt should be processed after SSE2AVX. */
2710 if (!i
.tm
.opcode_modifier
.sse2avx
2711 && i
.tm
.opcode_modifier
.immext
)
2714 /* For insns with operands there are more diddles to do to the opcode. */
2717 if (!process_operands ())
2720 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
2722 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2723 as_warn (_("translating to `%sp'"), i
.tm
.name
);
2726 if (i
.tm
.opcode_modifier
.vex
)
2727 build_vex_prefix ();
2729 /* Handle conversion of 'int $3' --> special int3 insn. */
2730 if (i
.tm
.base_opcode
== INT_OPCODE
&& i
.op
[0].imms
->X_add_number
== 3)
2732 i
.tm
.base_opcode
= INT3_OPCODE
;
2736 if ((i
.tm
.opcode_modifier
.jump
2737 || i
.tm
.opcode_modifier
.jumpbyte
2738 || i
.tm
.opcode_modifier
.jumpdword
)
2739 && i
.op
[0].disps
->X_op
== O_constant
)
2741 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2742 the absolute address given by the constant. Since ix86 jumps and
2743 calls are pc relative, we need to generate a reloc. */
2744 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
2745 i
.op
[0].disps
->X_op
= O_symbol
;
2748 if (i
.tm
.opcode_modifier
.rex64
)
2751 /* For 8 bit registers we need an empty rex prefix. Also if the
2752 instruction already has a prefix, we need to convert old
2753 registers to new ones. */
2755 if ((i
.types
[0].bitfield
.reg8
2756 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
2757 || (i
.types
[1].bitfield
.reg8
2758 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
2759 || ((i
.types
[0].bitfield
.reg8
2760 || i
.types
[1].bitfield
.reg8
)
2765 i
.rex
|= REX_OPCODE
;
2766 for (x
= 0; x
< 2; x
++)
2768 /* Look for 8 bit operand that uses old registers. */
2769 if (i
.types
[x
].bitfield
.reg8
2770 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
2772 /* In case it is "hi" register, give up. */
2773 if (i
.op
[x
].regs
->reg_num
> 3)
2774 as_bad (_("can't encode register '%s%s' in an "
2775 "instruction requiring REX prefix."),
2776 register_prefix
, i
.op
[x
].regs
->reg_name
);
2778 /* Otherwise it is equivalent to the extended register.
2779 Since the encoding doesn't change this is merely
2780 cosmetic cleanup for debug output. */
2782 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
2787 /* If the instruction has the DREX attribute (aka SSE5), don't emit a
2789 if (i
.tm
.opcode_modifier
.drex
|| i
.tm
.opcode_modifier
.drexc
)
2794 else if (i
.rex
!= 0)
2795 add_prefix (REX_OPCODE
| i
.rex
);
2797 /* We are ready to output the insn. */
2802 parse_insn (char *line
, char *mnemonic
)
2805 char *token_start
= l
;
2810 /* Non-zero if we found a prefix only acceptable with string insns. */
2811 const char *expecting_string_instruction
= NULL
;
2816 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
2819 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
2821 as_bad (_("no such instruction: `%s'"), token_start
);
2826 if (!is_space_char (*l
)
2827 && *l
!= END_OF_INSN
2829 || (*l
!= PREFIX_SEPARATOR
2832 as_bad (_("invalid character %s in mnemonic"),
2833 output_invalid (*l
));
2836 if (token_start
== l
)
2838 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
2839 as_bad (_("expecting prefix; got nothing"));
2841 as_bad (_("expecting mnemonic; got nothing"));
2845 /* Look up instruction (or prefix) via hash table. */
2846 current_templates
= hash_find (op_hash
, mnemonic
);
2848 if (*l
!= END_OF_INSN
2849 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
2850 && current_templates
2851 && current_templates
->start
->opcode_modifier
.isprefix
)
2853 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
2855 as_bad ((flag_code
!= CODE_64BIT
2856 ? _("`%s' is only supported in 64-bit mode")
2857 : _("`%s' is not supported in 64-bit mode")),
2858 current_templates
->start
->name
);
2861 /* If we are in 16-bit mode, do not allow addr16 or data16.
2862 Similarly, in 32-bit mode, do not allow addr32 or data32. */
2863 if ((current_templates
->start
->opcode_modifier
.size16
2864 || current_templates
->start
->opcode_modifier
.size32
)
2865 && flag_code
!= CODE_64BIT
2866 && (current_templates
->start
->opcode_modifier
.size32
2867 ^ (flag_code
== CODE_16BIT
)))
2869 as_bad (_("redundant %s prefix"),
2870 current_templates
->start
->name
);
2873 /* Add prefix, checking for repeated prefixes. */
2874 switch (add_prefix (current_templates
->start
->base_opcode
))
2879 expecting_string_instruction
= current_templates
->start
->name
;
2882 /* Skip past PREFIX_SEPARATOR and reset token_start. */
2889 if (!current_templates
)
2891 /* See if we can get a match by trimming off a suffix. */
2894 case WORD_MNEM_SUFFIX
:
2895 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
2896 i
.suffix
= SHORT_MNEM_SUFFIX
;
2898 case BYTE_MNEM_SUFFIX
:
2899 case QWORD_MNEM_SUFFIX
:
2900 i
.suffix
= mnem_p
[-1];
2902 current_templates
= hash_find (op_hash
, mnemonic
);
2904 case SHORT_MNEM_SUFFIX
:
2905 case LONG_MNEM_SUFFIX
:
2908 i
.suffix
= mnem_p
[-1];
2910 current_templates
= hash_find (op_hash
, mnemonic
);
2918 if (intel_float_operand (mnemonic
) == 1)
2919 i
.suffix
= SHORT_MNEM_SUFFIX
;
2921 i
.suffix
= LONG_MNEM_SUFFIX
;
2923 current_templates
= hash_find (op_hash
, mnemonic
);
2927 if (!current_templates
)
2929 as_bad (_("no such instruction: `%s'"), token_start
);
2934 if (current_templates
->start
->opcode_modifier
.jump
2935 || current_templates
->start
->opcode_modifier
.jumpbyte
)
2937 /* Check for a branch hint. We allow ",pt" and ",pn" for
2938 predict taken and predict not taken respectively.
2939 I'm not sure that branch hints actually do anything on loop
2940 and jcxz insns (JumpByte) for current Pentium4 chips. They
2941 may work in the future and it doesn't hurt to accept them
2943 if (l
[0] == ',' && l
[1] == 'p')
2947 if (!add_prefix (DS_PREFIX_OPCODE
))
2951 else if (l
[2] == 'n')
2953 if (!add_prefix (CS_PREFIX_OPCODE
))
2959 /* Any other comma loses. */
2962 as_bad (_("invalid character %s in mnemonic"),
2963 output_invalid (*l
));
2967 /* Check if instruction is supported on specified architecture. */
2969 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
2971 supported
|= cpu_flags_match (t
);
2972 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
2976 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
2978 as_bad (flag_code
== CODE_64BIT
2979 ? _("`%s' is not supported in 64-bit mode")
2980 : _("`%s' is only supported in 64-bit mode"),
2981 current_templates
->start
->name
);
2984 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
2986 as_bad (_("`%s' is not supported on `%s%s'"),
2987 current_templates
->start
->name
, cpu_arch_name
,
2988 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
2993 if (!cpu_arch_flags
.bitfield
.cpui386
2994 && (flag_code
!= CODE_16BIT
))
2996 as_warn (_("use .code16 to ensure correct addressing mode"));
2999 /* Check for rep/repne without a string instruction. */
3000 if (expecting_string_instruction
)
3002 static templates override
;
3004 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3005 if (t
->opcode_modifier
.isstring
)
3007 if (t
>= current_templates
->end
)
3009 as_bad (_("expecting string instruction after `%s'"),
3010 expecting_string_instruction
);
3013 for (override
.start
= t
; t
< current_templates
->end
; ++t
)
3014 if (!t
->opcode_modifier
.isstring
)
3017 current_templates
= &override
;
3024 parse_operands (char *l
, const char *mnemonic
)
3028 /* 1 if operand is pending after ','. */
3029 unsigned int expecting_operand
= 0;
3031 /* Non-zero if operand parens not balanced. */
3032 unsigned int paren_not_balanced
;
3034 while (*l
!= END_OF_INSN
)
3036 /* Skip optional white space before operand. */
3037 if (is_space_char (*l
))
3039 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
3041 as_bad (_("invalid character %s before operand %d"),
3042 output_invalid (*l
),
3046 token_start
= l
; /* after white space */
3047 paren_not_balanced
= 0;
3048 while (paren_not_balanced
|| *l
!= ',')
3050 if (*l
== END_OF_INSN
)
3052 if (paren_not_balanced
)
3055 as_bad (_("unbalanced parenthesis in operand %d."),
3058 as_bad (_("unbalanced brackets in operand %d."),
3063 break; /* we are done */
3065 else if (!is_operand_char (*l
) && !is_space_char (*l
))
3067 as_bad (_("invalid character %s in operand %d"),
3068 output_invalid (*l
),
3075 ++paren_not_balanced
;
3077 --paren_not_balanced
;
3082 ++paren_not_balanced
;
3084 --paren_not_balanced
;
3088 if (l
!= token_start
)
3089 { /* Yes, we've read in another operand. */
3090 unsigned int operand_ok
;
3091 this_operand
= i
.operands
++;
3092 i
.types
[this_operand
].bitfield
.unspecified
= 1;
3093 if (i
.operands
> MAX_OPERANDS
)
3095 as_bad (_("spurious operands; (%d operands/instruction max)"),
3099 /* Now parse operand adding info to 'i' as we go along. */
3100 END_STRING_AND_SAVE (l
);
3104 i386_intel_operand (token_start
,
3105 intel_float_operand (mnemonic
));
3107 operand_ok
= i386_att_operand (token_start
);
3109 RESTORE_END_STRING (l
);
3115 if (expecting_operand
)
3117 expecting_operand_after_comma
:
3118 as_bad (_("expecting operand after ','; got nothing"));
3123 as_bad (_("expecting operand before ','; got nothing"));
3128 /* Now *l must be either ',' or END_OF_INSN. */
3131 if (*++l
== END_OF_INSN
)
3133 /* Just skip it, if it's \n complain. */
3134 goto expecting_operand_after_comma
;
3136 expecting_operand
= 1;
3143 swap_2_operands (int xchg1
, int xchg2
)
3145 union i386_op temp_op
;
3146 i386_operand_type temp_type
;
3147 enum bfd_reloc_code_real temp_reloc
;
3149 temp_type
= i
.types
[xchg2
];
3150 i
.types
[xchg2
] = i
.types
[xchg1
];
3151 i
.types
[xchg1
] = temp_type
;
3152 temp_op
= i
.op
[xchg2
];
3153 i
.op
[xchg2
] = i
.op
[xchg1
];
3154 i
.op
[xchg1
] = temp_op
;
3155 temp_reloc
= i
.reloc
[xchg2
];
3156 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
3157 i
.reloc
[xchg1
] = temp_reloc
;
3161 swap_operands (void)
3167 swap_2_operands (1, i
.operands
- 2);
3170 swap_2_operands (0, i
.operands
- 1);
3176 if (i
.mem_operands
== 2)
3178 const seg_entry
*temp_seg
;
3179 temp_seg
= i
.seg
[0];
3180 i
.seg
[0] = i
.seg
[1];
3181 i
.seg
[1] = temp_seg
;
3185 /* Try to ensure constant immediates are represented in the smallest
3190 char guess_suffix
= 0;
3194 guess_suffix
= i
.suffix
;
3195 else if (i
.reg_operands
)
3197 /* Figure out a suffix from the last register operand specified.
3198 We can't do this properly yet, ie. excluding InOutPortReg,
3199 but the following works for instructions with immediates.
3200 In any case, we can't set i.suffix yet. */
3201 for (op
= i
.operands
; --op
>= 0;)
3202 if (i
.types
[op
].bitfield
.reg8
)
3204 guess_suffix
= BYTE_MNEM_SUFFIX
;
3207 else if (i
.types
[op
].bitfield
.reg16
)
3209 guess_suffix
= WORD_MNEM_SUFFIX
;
3212 else if (i
.types
[op
].bitfield
.reg32
)
3214 guess_suffix
= LONG_MNEM_SUFFIX
;
3217 else if (i
.types
[op
].bitfield
.reg64
)
3219 guess_suffix
= QWORD_MNEM_SUFFIX
;
3223 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
3224 guess_suffix
= WORD_MNEM_SUFFIX
;
3226 for (op
= i
.operands
; --op
>= 0;)
3227 if (operand_type_check (i
.types
[op
], imm
))
3229 switch (i
.op
[op
].imms
->X_op
)
3232 /* If a suffix is given, this operand may be shortened. */
3233 switch (guess_suffix
)
3235 case LONG_MNEM_SUFFIX
:
3236 i
.types
[op
].bitfield
.imm32
= 1;
3237 i
.types
[op
].bitfield
.imm64
= 1;
3239 case WORD_MNEM_SUFFIX
:
3240 i
.types
[op
].bitfield
.imm16
= 1;
3241 i
.types
[op
].bitfield
.imm32
= 1;
3242 i
.types
[op
].bitfield
.imm32s
= 1;
3243 i
.types
[op
].bitfield
.imm64
= 1;
3245 case BYTE_MNEM_SUFFIX
:
3246 i
.types
[op
].bitfield
.imm8
= 1;
3247 i
.types
[op
].bitfield
.imm8s
= 1;
3248 i
.types
[op
].bitfield
.imm16
= 1;
3249 i
.types
[op
].bitfield
.imm32
= 1;
3250 i
.types
[op
].bitfield
.imm32s
= 1;
3251 i
.types
[op
].bitfield
.imm64
= 1;
3255 /* If this operand is at most 16 bits, convert it
3256 to a signed 16 bit number before trying to see
3257 whether it will fit in an even smaller size.
3258 This allows a 16-bit operand such as $0xffe0 to
3259 be recognised as within Imm8S range. */
3260 if ((i
.types
[op
].bitfield
.imm16
)
3261 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
3263 i
.op
[op
].imms
->X_add_number
=
3264 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
3266 if ((i
.types
[op
].bitfield
.imm32
)
3267 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
3270 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
3271 ^ ((offsetT
) 1 << 31))
3272 - ((offsetT
) 1 << 31));
3275 = operand_type_or (i
.types
[op
],
3276 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
3278 /* We must avoid matching of Imm32 templates when 64bit
3279 only immediate is available. */
3280 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
3281 i
.types
[op
].bitfield
.imm32
= 0;
3288 /* Symbols and expressions. */
3290 /* Convert symbolic operand to proper sizes for matching, but don't
3291 prevent matching a set of insns that only supports sizes other
3292 than those matching the insn suffix. */
3294 i386_operand_type mask
, allowed
;
3297 operand_type_set (&mask
, 0);
3298 operand_type_set (&allowed
, 0);
3300 for (t
= current_templates
->start
;
3301 t
< current_templates
->end
;
3303 allowed
= operand_type_or (allowed
,
3304 t
->operand_types
[op
]);
3305 switch (guess_suffix
)
3307 case QWORD_MNEM_SUFFIX
:
3308 mask
.bitfield
.imm64
= 1;
3309 mask
.bitfield
.imm32s
= 1;
3311 case LONG_MNEM_SUFFIX
:
3312 mask
.bitfield
.imm32
= 1;
3314 case WORD_MNEM_SUFFIX
:
3315 mask
.bitfield
.imm16
= 1;
3317 case BYTE_MNEM_SUFFIX
:
3318 mask
.bitfield
.imm8
= 1;
3323 allowed
= operand_type_and (mask
, allowed
);
3324 if (!operand_type_all_zero (&allowed
))
3325 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
3332 /* Try to use the smallest displacement type too. */
3334 optimize_disp (void)
3338 for (op
= i
.operands
; --op
>= 0;)
3339 if (operand_type_check (i
.types
[op
], disp
))
3341 if (i
.op
[op
].disps
->X_op
== O_constant
)
3343 offsetT disp
= i
.op
[op
].disps
->X_add_number
;
3345 if (i
.types
[op
].bitfield
.disp16
3346 && (disp
& ~(offsetT
) 0xffff) == 0)
3348 /* If this operand is at most 16 bits, convert
3349 to a signed 16 bit number and don't use 64bit
3351 disp
= (((disp
& 0xffff) ^ 0x8000) - 0x8000);
3352 i
.types
[op
].bitfield
.disp64
= 0;
3354 if (i
.types
[op
].bitfield
.disp32
3355 && (disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
3357 /* If this operand is at most 32 bits, convert
3358 to a signed 32 bit number and don't use 64bit
3360 disp
&= (((offsetT
) 2 << 31) - 1);
3361 disp
= (disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
3362 i
.types
[op
].bitfield
.disp64
= 0;
3364 if (!disp
&& i
.types
[op
].bitfield
.baseindex
)
3366 i
.types
[op
].bitfield
.disp8
= 0;
3367 i
.types
[op
].bitfield
.disp16
= 0;
3368 i
.types
[op
].bitfield
.disp32
= 0;
3369 i
.types
[op
].bitfield
.disp32s
= 0;
3370 i
.types
[op
].bitfield
.disp64
= 0;
3374 else if (flag_code
== CODE_64BIT
)
3376 if (fits_in_signed_long (disp
))
3378 i
.types
[op
].bitfield
.disp64
= 0;
3379 i
.types
[op
].bitfield
.disp32s
= 1;
3381 if (fits_in_unsigned_long (disp
))
3382 i
.types
[op
].bitfield
.disp32
= 1;
3384 if ((i
.types
[op
].bitfield
.disp32
3385 || i
.types
[op
].bitfield
.disp32s
3386 || i
.types
[op
].bitfield
.disp16
)
3387 && fits_in_signed_byte (disp
))
3388 i
.types
[op
].bitfield
.disp8
= 1;
3390 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
3391 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
3393 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
3394 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
3395 i
.types
[op
].bitfield
.disp8
= 0;
3396 i
.types
[op
].bitfield
.disp16
= 0;
3397 i
.types
[op
].bitfield
.disp32
= 0;
3398 i
.types
[op
].bitfield
.disp32s
= 0;
3399 i
.types
[op
].bitfield
.disp64
= 0;
3402 /* We only support 64bit displacement on constants. */
3403 i
.types
[op
].bitfield
.disp64
= 0;
3407 /* Check if operands are valid for the instrucrtion. Update VEX
3411 VEX_check_operands (const template *t
)
3413 if (!t
->opcode_modifier
.vex
)
3416 /* Only check VEX_Imm4, which must be the first operand. */
3417 if (t
->operand_types
[0].bitfield
.vex_imm4
)
3419 if (i
.op
[0].imms
->X_op
!= O_constant
3420 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
3423 /* Turn off Imm8 so that update_imm won't complain. */
3424 i
.types
[0] = vex_imm4
;
3431 match_template (void)
3433 /* Points to template once we've found it. */
3435 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
3436 i386_operand_type overlap4
;
3437 unsigned int found_reverse_match
;
3438 i386_opcode_modifier suffix_check
;
3439 i386_operand_type operand_types
[MAX_OPERANDS
];
3440 int addr_prefix_disp
;
3442 unsigned int found_cpu_match
;
3443 unsigned int check_register
;
3445 #if MAX_OPERANDS != 5
3446 # error "MAX_OPERANDS must be 5."
3449 found_reverse_match
= 0;
3450 addr_prefix_disp
= -1;
3452 memset (&suffix_check
, 0, sizeof (suffix_check
));
3453 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
3454 suffix_check
.no_bsuf
= 1;
3455 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
3456 suffix_check
.no_wsuf
= 1;
3457 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
3458 suffix_check
.no_ssuf
= 1;
3459 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
3460 suffix_check
.no_lsuf
= 1;
3461 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
3462 suffix_check
.no_qsuf
= 1;
3463 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
3464 suffix_check
.no_ldsuf
= 1;
3466 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
3468 addr_prefix_disp
= -1;
3470 /* Must have right number of operands. */
3471 if (i
.operands
!= t
->operands
)
3474 /* Check processor support. */
3475 found_cpu_match
= (cpu_flags_match (t
)
3476 == CPU_FLAGS_PERFECT_MATCH
);
3477 if (!found_cpu_match
)
3480 /* Check old gcc support. */
3481 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
3484 /* Check AT&T mnemonic. */
3485 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
3488 /* Check AT&T syntax Intel syntax. */
3489 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
3490 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
3493 /* Check the suffix, except for some instructions in intel mode. */
3494 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
3495 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
3496 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
3497 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
3498 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
3499 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
3500 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
3503 if (!operand_size_match (t
))
3506 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3507 operand_types
[j
] = t
->operand_types
[j
];
3509 /* In general, don't allow 64-bit operands in 32-bit mode. */
3510 if (i
.suffix
== QWORD_MNEM_SUFFIX
3511 && flag_code
!= CODE_64BIT
3513 ? (!t
->opcode_modifier
.ignoresize
3514 && !intel_float_operand (t
->name
))
3515 : intel_float_operand (t
->name
) != 2)
3516 && ((!operand_types
[0].bitfield
.regmmx
3517 && !operand_types
[0].bitfield
.regxmm
3518 && !operand_types
[0].bitfield
.regymm
)
3519 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
3520 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
3521 && !!operand_types
[t
->operands
> 1].bitfield
.regymm
))
3522 && (t
->base_opcode
!= 0x0fc7
3523 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
3526 /* In general, don't allow 32-bit operands on pre-386. */
3527 else if (i
.suffix
== LONG_MNEM_SUFFIX
3528 && !cpu_arch_flags
.bitfield
.cpui386
3530 ? (!t
->opcode_modifier
.ignoresize
3531 && !intel_float_operand (t
->name
))
3532 : intel_float_operand (t
->name
) != 2)
3533 && ((!operand_types
[0].bitfield
.regmmx
3534 && !operand_types
[0].bitfield
.regxmm
)
3535 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
3536 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
3539 /* Do not verify operands when there are none. */
3543 /* We've found a match; break out of loop. */
3547 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3548 into Disp32/Disp16/Disp32 operand. */
3549 if (i
.prefix
[ADDR_PREFIX
] != 0)
3551 /* There should be only one Disp operand. */
3555 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3557 if (operand_types
[j
].bitfield
.disp16
)
3559 addr_prefix_disp
= j
;
3560 operand_types
[j
].bitfield
.disp32
= 1;
3561 operand_types
[j
].bitfield
.disp16
= 0;
3567 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3569 if (operand_types
[j
].bitfield
.disp32
)
3571 addr_prefix_disp
= j
;
3572 operand_types
[j
].bitfield
.disp32
= 0;
3573 operand_types
[j
].bitfield
.disp16
= 1;
3579 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3581 if (operand_types
[j
].bitfield
.disp64
)
3583 addr_prefix_disp
= j
;
3584 operand_types
[j
].bitfield
.disp64
= 0;
3585 operand_types
[j
].bitfield
.disp32
= 1;
3593 /* We check register size only if size of operands can be
3594 encoded the canonical way. */
3595 check_register
= t
->opcode_modifier
.w
;
3596 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
3597 switch (t
->operands
)
3600 if (!operand_type_match (overlap0
, i
.types
[0]))
3604 /* xchg %eax, %eax is a special case. It is an aliase for nop
3605 only in 32bit mode and we can use opcode 0x90. In 64bit
3606 mode, we can't use 0x90 for xchg %eax, %eax since it should
3607 zero-extend %eax to %rax. */
3608 if (flag_code
== CODE_64BIT
3609 && t
->base_opcode
== 0x90
3610 && operand_type_equal (&i
.types
[0], &acc32
)
3611 && operand_type_equal (&i
.types
[1], &acc32
))
3616 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
3617 if (!operand_type_match (overlap0
, i
.types
[0])
3618 || !operand_type_match (overlap1
, i
.types
[1])
3620 && !operand_type_register_match (overlap0
, i
.types
[0],
3622 overlap1
, i
.types
[1],
3625 /* Check if other direction is valid ... */
3626 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
3629 /* Try reversing direction of operands. */
3630 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
3631 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
3632 if (!operand_type_match (overlap0
, i
.types
[0])
3633 || !operand_type_match (overlap1
, i
.types
[1])
3635 && !operand_type_register_match (overlap0
,
3642 /* Does not match either direction. */
3645 /* found_reverse_match holds which of D or FloatDR
3647 if (t
->opcode_modifier
.d
)
3648 found_reverse_match
= Opcode_D
;
3649 else if (t
->opcode_modifier
.floatd
)
3650 found_reverse_match
= Opcode_FloatD
;
3652 found_reverse_match
= 0;
3653 if (t
->opcode_modifier
.floatr
)
3654 found_reverse_match
|= Opcode_FloatR
;
3658 /* Found a forward 2 operand match here. */
3659 switch (t
->operands
)
3662 overlap4
= operand_type_and (i
.types
[4],
3665 overlap3
= operand_type_and (i
.types
[3],
3668 overlap2
= operand_type_and (i
.types
[2],
3673 switch (t
->operands
)
3676 if (!operand_type_match (overlap4
, i
.types
[4])
3677 || !operand_type_register_match (overlap3
,
3685 if (!operand_type_match (overlap3
, i
.types
[3])
3687 && !operand_type_register_match (overlap2
,
3695 /* Here we make use of the fact that there are no
3696 reverse match 3 operand instructions, and all 3
3697 operand instructions only need to be checked for
3698 register consistency between operands 2 and 3. */
3699 if (!operand_type_match (overlap2
, i
.types
[2])
3701 && !operand_type_register_match (overlap1
,
3711 /* Found either forward/reverse 2, 3 or 4 operand match here:
3712 slip through to break. */
3714 if (!found_cpu_match
)
3716 found_reverse_match
= 0;
3720 /* Check if VEX operands are valid. */
3721 if (VEX_check_operands (t
))
3724 /* We've found a match; break out of loop. */
3728 if (t
== current_templates
->end
)
3730 /* We found no match. */
3731 as_bad (_("suffix or operands invalid for `%s'"),
3732 current_templates
->start
->name
);
3736 if (!quiet_warnings
)
3739 && (i
.types
[0].bitfield
.jumpabsolute
3740 != operand_types
[0].bitfield
.jumpabsolute
))
3742 as_warn (_("indirect %s without `*'"), t
->name
);
3745 if (t
->opcode_modifier
.isprefix
3746 && t
->opcode_modifier
.ignoresize
)
3748 /* Warn them that a data or address size prefix doesn't
3749 affect assembly of the next line of code. */
3750 as_warn (_("stand-alone `%s' prefix"), t
->name
);
3754 /* Copy the template we found. */
3757 if (addr_prefix_disp
!= -1)
3758 i
.tm
.operand_types
[addr_prefix_disp
]
3759 = operand_types
[addr_prefix_disp
];
3761 if (found_reverse_match
)
3763 /* If we found a reverse match we must alter the opcode
3764 direction bit. found_reverse_match holds bits to change
3765 (different for int & float insns). */
3767 i
.tm
.base_opcode
^= found_reverse_match
;
3769 i
.tm
.operand_types
[0] = operand_types
[1];
3770 i
.tm
.operand_types
[1] = operand_types
[0];
3779 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
3780 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
3782 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
3784 as_bad (_("`%s' operand %d must use `%%es' segment"),
3789 /* There's only ever one segment override allowed per instruction.
3790 This instruction possibly has a legal segment override on the
3791 second operand, so copy the segment to where non-string
3792 instructions store it, allowing common code. */
3793 i
.seg
[0] = i
.seg
[1];
3795 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
3797 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
3799 as_bad (_("`%s' operand %d must use `%%es' segment"),
3809 process_suffix (void)
3811 /* If matched instruction specifies an explicit instruction mnemonic
3813 if (i
.tm
.opcode_modifier
.size16
)
3814 i
.suffix
= WORD_MNEM_SUFFIX
;
3815 else if (i
.tm
.opcode_modifier
.size32
)
3816 i
.suffix
= LONG_MNEM_SUFFIX
;
3817 else if (i
.tm
.opcode_modifier
.size64
)
3818 i
.suffix
= QWORD_MNEM_SUFFIX
;
3819 else if (i
.reg_operands
)
3821 /* If there's no instruction mnemonic suffix we try to invent one
3822 based on register operands. */
3825 /* We take i.suffix from the last register operand specified,
3826 Destination register type is more significant than source
3827 register type. crc32 in SSE4.2 prefers source register
3829 if (i
.tm
.base_opcode
== 0xf20f38f1)
3831 if (i
.types
[0].bitfield
.reg16
)
3832 i
.suffix
= WORD_MNEM_SUFFIX
;
3833 else if (i
.types
[0].bitfield
.reg32
)
3834 i
.suffix
= LONG_MNEM_SUFFIX
;
3835 else if (i
.types
[0].bitfield
.reg64
)
3836 i
.suffix
= QWORD_MNEM_SUFFIX
;
3838 else if (i
.tm
.base_opcode
== 0xf20f38f0)
3840 if (i
.types
[0].bitfield
.reg8
)
3841 i
.suffix
= BYTE_MNEM_SUFFIX
;
3848 if (i
.tm
.base_opcode
== 0xf20f38f1
3849 || i
.tm
.base_opcode
== 0xf20f38f0)
3851 /* We have to know the operand size for crc32. */
3852 as_bad (_("ambiguous memory operand size for `%s`"),
3857 for (op
= i
.operands
; --op
>= 0;)
3858 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
3860 if (i
.types
[op
].bitfield
.reg8
)
3862 i
.suffix
= BYTE_MNEM_SUFFIX
;
3865 else if (i
.types
[op
].bitfield
.reg16
)
3867 i
.suffix
= WORD_MNEM_SUFFIX
;
3870 else if (i
.types
[op
].bitfield
.reg32
)
3872 i
.suffix
= LONG_MNEM_SUFFIX
;
3875 else if (i
.types
[op
].bitfield
.reg64
)
3877 i
.suffix
= QWORD_MNEM_SUFFIX
;
3883 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
3885 if (!check_byte_reg ())
3888 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
3890 if (!check_long_reg ())
3893 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
3896 && i
.tm
.opcode_modifier
.ignoresize
3897 && i
.tm
.opcode_modifier
.no_qsuf
)
3899 else if (!check_qword_reg ())
3902 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
3904 if (!check_word_reg ())
3907 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
3908 || i
.suffix
== YMMWORD_MNEM_SUFFIX
)
3910 /* Skip if the instruction has x/y suffix. match_template
3911 should check if it is a valid suffix. */
3913 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
3914 /* Do nothing if the instruction is going to ignore the prefix. */
3919 else if (i
.tm
.opcode_modifier
.defaultsize
3921 /* exclude fldenv/frstor/fsave/fstenv */
3922 && i
.tm
.opcode_modifier
.no_ssuf
)
3924 i
.suffix
= stackop_size
;
3926 else if (intel_syntax
3928 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
3929 || i
.tm
.opcode_modifier
.jumpbyte
3930 || i
.tm
.opcode_modifier
.jumpintersegment
3931 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
3932 && i
.tm
.extension_opcode
<= 3)))
3937 if (!i
.tm
.opcode_modifier
.no_qsuf
)
3939 i
.suffix
= QWORD_MNEM_SUFFIX
;
3943 if (!i
.tm
.opcode_modifier
.no_lsuf
)
3944 i
.suffix
= LONG_MNEM_SUFFIX
;
3947 if (!i
.tm
.opcode_modifier
.no_wsuf
)
3948 i
.suffix
= WORD_MNEM_SUFFIX
;
3957 if (i
.tm
.opcode_modifier
.w
)
3959 as_bad (_("no instruction mnemonic suffix given and "
3960 "no register operands; can't size instruction"));
3966 unsigned int suffixes
;
3968 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
3969 if (!i
.tm
.opcode_modifier
.no_wsuf
)
3971 if (!i
.tm
.opcode_modifier
.no_lsuf
)
3973 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
3975 if (!i
.tm
.opcode_modifier
.no_ssuf
)
3977 if (!i
.tm
.opcode_modifier
.no_qsuf
)
3980 /* There are more than suffix matches. */
3981 if (i
.tm
.opcode_modifier
.w
3982 || ((suffixes
& (suffixes
- 1))
3983 && !i
.tm
.opcode_modifier
.defaultsize
3984 && !i
.tm
.opcode_modifier
.ignoresize
))
3986 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
3992 /* Change the opcode based on the operand size given by i.suffix;
3993 We don't need to change things for byte insns. */
3996 && i
.suffix
!= BYTE_MNEM_SUFFIX
3997 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
3998 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
)
4000 /* It's not a byte, select word/dword operation. */
4001 if (i
.tm
.opcode_modifier
.w
)
4003 if (i
.tm
.opcode_modifier
.shortform
)
4004 i
.tm
.base_opcode
|= 8;
4006 i
.tm
.base_opcode
|= 1;
4009 /* Now select between word & dword operations via the operand
4010 size prefix, except for instructions that will ignore this
4012 if (i
.tm
.opcode_modifier
.addrprefixop0
)
4014 /* The address size override prefix changes the size of the
4016 if ((flag_code
== CODE_32BIT
4017 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
4018 || (flag_code
!= CODE_32BIT
4019 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
4020 if (!add_prefix (ADDR_PREFIX_OPCODE
))
4023 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
4024 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
4025 && !i
.tm
.opcode_modifier
.ignoresize
4026 && !i
.tm
.opcode_modifier
.floatmf
4027 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
4028 || (flag_code
== CODE_64BIT
4029 && i
.tm
.opcode_modifier
.jumpbyte
)))
4031 unsigned int prefix
= DATA_PREFIX_OPCODE
;
4033 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
4034 prefix
= ADDR_PREFIX_OPCODE
;
4036 if (!add_prefix (prefix
))
4040 /* Set mode64 for an operand. */
4041 if (i
.suffix
== QWORD_MNEM_SUFFIX
4042 && flag_code
== CODE_64BIT
4043 && !i
.tm
.opcode_modifier
.norex64
)
4045 /* Special case for xchg %rax,%rax. It is NOP and doesn't
4046 need rex64. cmpxchg8b is also a special case. */
4047 if (! (i
.operands
== 2
4048 && i
.tm
.base_opcode
== 0x90
4049 && i
.tm
.extension_opcode
== None
4050 && operand_type_equal (&i
.types
[0], &acc64
)
4051 && operand_type_equal (&i
.types
[1], &acc64
))
4052 && ! (i
.operands
== 1
4053 && i
.tm
.base_opcode
== 0xfc7
4054 && i
.tm
.extension_opcode
== 1
4055 && !operand_type_check (i
.types
[0], reg
)
4056 && operand_type_check (i
.types
[0], anymem
)))
4060 /* Size floating point instruction. */
4061 if (i
.suffix
== LONG_MNEM_SUFFIX
)
4062 if (i
.tm
.opcode_modifier
.floatmf
)
4063 i
.tm
.base_opcode
^= 4;
4070 check_byte_reg (void)
4074 for (op
= i
.operands
; --op
>= 0;)
4076 /* If this is an eight bit register, it's OK. If it's the 16 or
4077 32 bit version of an eight bit register, we will just use the
4078 low portion, and that's OK too. */
4079 if (i
.types
[op
].bitfield
.reg8
)
4082 /* Don't generate this warning if not needed. */
4083 if (intel_syntax
&& i
.tm
.opcode_modifier
.byteokintel
)
4086 /* crc32 doesn't generate this warning. */
4087 if (i
.tm
.base_opcode
== 0xf20f38f0)
4090 if ((i
.types
[op
].bitfield
.reg16
4091 || i
.types
[op
].bitfield
.reg32
4092 || i
.types
[op
].bitfield
.reg64
)
4093 && i
.op
[op
].regs
->reg_num
< 4)
4095 /* Prohibit these changes in the 64bit mode, since the
4096 lowering is more complicated. */
4097 if (flag_code
== CODE_64BIT
4098 && !i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4100 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4101 register_prefix
, i
.op
[op
].regs
->reg_name
,
4105 #if REGISTER_WARNINGS
4107 && !i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4108 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4110 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
4111 ? REGNAM_AL
- REGNAM_AX
4112 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
4114 i
.op
[op
].regs
->reg_name
,
4119 /* Any other register is bad. */
4120 if (i
.types
[op
].bitfield
.reg16
4121 || i
.types
[op
].bitfield
.reg32
4122 || i
.types
[op
].bitfield
.reg64
4123 || i
.types
[op
].bitfield
.regmmx
4124 || i
.types
[op
].bitfield
.regxmm
4125 || i
.types
[op
].bitfield
.regymm
4126 || i
.types
[op
].bitfield
.sreg2
4127 || i
.types
[op
].bitfield
.sreg3
4128 || i
.types
[op
].bitfield
.control
4129 || i
.types
[op
].bitfield
.debug
4130 || i
.types
[op
].bitfield
.test
4131 || i
.types
[op
].bitfield
.floatreg
4132 || i
.types
[op
].bitfield
.floatacc
)
4134 as_bad (_("`%s%s' not allowed with `%s%c'"),
4136 i
.op
[op
].regs
->reg_name
,
4146 check_long_reg (void)
4150 for (op
= i
.operands
; --op
>= 0;)
4151 /* Reject eight bit registers, except where the template requires
4152 them. (eg. movzb) */
4153 if (i
.types
[op
].bitfield
.reg8
4154 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4155 || i
.tm
.operand_types
[op
].bitfield
.reg32
4156 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4158 as_bad (_("`%s%s' not allowed with `%s%c'"),
4160 i
.op
[op
].regs
->reg_name
,
4165 /* Warn if the e prefix on a general reg is missing. */
4166 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4167 && i
.types
[op
].bitfield
.reg16
4168 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4169 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4171 /* Prohibit these changes in the 64bit mode, since the
4172 lowering is more complicated. */
4173 if (flag_code
== CODE_64BIT
)
4175 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4176 register_prefix
, i
.op
[op
].regs
->reg_name
,
4180 #if REGISTER_WARNINGS
4182 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4184 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
4186 i
.op
[op
].regs
->reg_name
,
4190 /* Warn if the r prefix on a general reg is missing. */
4191 else if (i
.types
[op
].bitfield
.reg64
4192 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4193 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4196 && i
.tm
.opcode_modifier
.toqword
4197 && !i
.types
[0].bitfield
.regxmm
)
4199 /* Convert to QWORD. We want REX byte. */
4200 i
.suffix
= QWORD_MNEM_SUFFIX
;
4204 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4205 register_prefix
, i
.op
[op
].regs
->reg_name
,
4214 check_qword_reg (void)
4218 for (op
= i
.operands
; --op
>= 0; )
4219 /* Reject eight bit registers, except where the template requires
4220 them. (eg. movzb) */
4221 if (i
.types
[op
].bitfield
.reg8
4222 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4223 || i
.tm
.operand_types
[op
].bitfield
.reg32
4224 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4226 as_bad (_("`%s%s' not allowed with `%s%c'"),
4228 i
.op
[op
].regs
->reg_name
,
4233 /* Warn if the e prefix on a general reg is missing. */
4234 else if ((i
.types
[op
].bitfield
.reg16
4235 || i
.types
[op
].bitfield
.reg32
)
4236 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4237 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4239 /* Prohibit these changes in the 64bit mode, since the
4240 lowering is more complicated. */
4242 && i
.tm
.opcode_modifier
.todword
4243 && !i
.types
[0].bitfield
.regxmm
)
4245 /* Convert to DWORD. We don't want REX byte. */
4246 i
.suffix
= LONG_MNEM_SUFFIX
;
4250 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4251 register_prefix
, i
.op
[op
].regs
->reg_name
,
4260 check_word_reg (void)
4263 for (op
= i
.operands
; --op
>= 0;)
4264 /* Reject eight bit registers, except where the template requires
4265 them. (eg. movzb) */
4266 if (i
.types
[op
].bitfield
.reg8
4267 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4268 || i
.tm
.operand_types
[op
].bitfield
.reg32
4269 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4271 as_bad (_("`%s%s' not allowed with `%s%c'"),
4273 i
.op
[op
].regs
->reg_name
,
4278 /* Warn if the e prefix on a general reg is present. */
4279 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4280 && i
.types
[op
].bitfield
.reg32
4281 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4282 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4284 /* Prohibit these changes in the 64bit mode, since the
4285 lowering is more complicated. */
4286 if (flag_code
== CODE_64BIT
)
4288 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4289 register_prefix
, i
.op
[op
].regs
->reg_name
,
4294 #if REGISTER_WARNINGS
4295 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4297 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
4299 i
.op
[op
].regs
->reg_name
,
4307 update_imm (unsigned int j
)
4309 i386_operand_type overlap
;
4311 overlap
= operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
4312 if ((overlap
.bitfield
.imm8
4313 || overlap
.bitfield
.imm8s
4314 || overlap
.bitfield
.imm16
4315 || overlap
.bitfield
.imm32
4316 || overlap
.bitfield
.imm32s
4317 || overlap
.bitfield
.imm64
)
4318 && !operand_type_equal (&overlap
, &imm8
)
4319 && !operand_type_equal (&overlap
, &imm8s
)
4320 && !operand_type_equal (&overlap
, &imm16
)
4321 && !operand_type_equal (&overlap
, &imm32
)
4322 && !operand_type_equal (&overlap
, &imm32s
)
4323 && !operand_type_equal (&overlap
, &imm64
))
4327 i386_operand_type temp
;
4329 operand_type_set (&temp
, 0);
4330 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4332 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
4333 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
4335 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4336 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
4337 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4339 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
4340 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
4343 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
4346 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
4347 || operand_type_equal (&overlap
, &imm16_32
)
4348 || operand_type_equal (&overlap
, &imm16_32s
))
4350 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4355 if (!operand_type_equal (&overlap
, &imm8
)
4356 && !operand_type_equal (&overlap
, &imm8s
)
4357 && !operand_type_equal (&overlap
, &imm16
)
4358 && !operand_type_equal (&overlap
, &imm32
)
4359 && !operand_type_equal (&overlap
, &imm32s
)
4360 && !operand_type_equal (&overlap
, &imm64
))
4362 as_bad (_("no instruction mnemonic suffix given; "
4363 "can't determine immediate size"));
4367 i
.types
[j
] = overlap
;
4377 for (j
= 0; j
< 2; j
++)
4378 if (update_imm (j
) == 0)
4381 i
.types
[2] = operand_type_and (i
.types
[2], i
.tm
.operand_types
[2]);
4382 assert (operand_type_check (i
.types
[2], imm
) == 0);
4390 i
.drex
.modrm_reg
= 0;
4391 i
.drex
.modrm_regmem
= 0;
4393 /* SSE5 4 operand instructions must have the destination the same as
4394 one of the inputs. Figure out the destination register and cache
4395 it away in the drex field, and remember which fields to use for
4397 if (i
.tm
.opcode_modifier
.drex
4398 && i
.tm
.opcode_modifier
.drexv
4401 i
.tm
.extension_opcode
= None
;
4403 /* Case 1: 4 operand insn, dest = src1, src3 = register. */
4404 if (i
.types
[0].bitfield
.regxmm
!= 0
4405 && i
.types
[1].bitfield
.regxmm
!= 0
4406 && i
.types
[2].bitfield
.regxmm
!= 0
4407 && i
.types
[3].bitfield
.regxmm
!= 0
4408 && i
.op
[0].regs
->reg_num
== i
.op
[3].regs
->reg_num
4409 && i
.op
[0].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4411 /* Clear the arguments that are stored in drex. */
4412 operand_type_set (&i
.types
[0], 0);
4413 operand_type_set (&i
.types
[3], 0);
4414 i
.reg_operands
-= 2;
4416 /* There are two different ways to encode a 4 operand
4417 instruction with all registers that uses OC1 set to
4418 0 or 1. Favor setting OC1 to 0 since this mimics the
4419 actions of other SSE5 assemblers. Use modrm encoding 2
4420 for register/register. Include the high order bit that
4421 is normally stored in the REX byte in the register
4423 i
.tm
.extension_opcode
= DREX_X1_XMEM_X2_X1
;
4424 i
.drex
.modrm_reg
= 2;
4425 i
.drex
.modrm_regmem
= 1;
4426 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4427 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4430 /* Case 2: 4 operand insn, dest = src1, src3 = memory. */
4431 else if (i
.types
[0].bitfield
.regxmm
!= 0
4432 && i
.types
[1].bitfield
.regxmm
!= 0
4433 && (i
.types
[2].bitfield
.regxmm
4434 || operand_type_check (i
.types
[2], anymem
))
4435 && i
.types
[3].bitfield
.regxmm
!= 0
4436 && i
.op
[0].regs
->reg_num
== i
.op
[3].regs
->reg_num
4437 && i
.op
[0].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4439 /* clear the arguments that are stored in drex */
4440 operand_type_set (&i
.types
[0], 0);
4441 operand_type_set (&i
.types
[3], 0);
4442 i
.reg_operands
-= 2;
4444 /* Specify the modrm encoding for memory addressing. Include
4445 the high order bit that is normally stored in the REX byte
4446 in the register field. */
4447 i
.tm
.extension_opcode
= DREX_X1_X2_XMEM_X1
;
4448 i
.drex
.modrm_reg
= 1;
4449 i
.drex
.modrm_regmem
= 2;
4450 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4451 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4454 /* Case 3: 4 operand insn, dest = src1, src2 = memory. */
4455 else if (i
.types
[0].bitfield
.regxmm
!= 0
4456 && operand_type_check (i
.types
[1], anymem
) != 0
4457 && i
.types
[2].bitfield
.regxmm
!= 0
4458 && i
.types
[3].bitfield
.regxmm
!= 0
4459 && i
.op
[0].regs
->reg_num
== i
.op
[3].regs
->reg_num
4460 && i
.op
[0].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4462 /* Clear the arguments that are stored in drex. */
4463 operand_type_set (&i
.types
[0], 0);
4464 operand_type_set (&i
.types
[3], 0);
4465 i
.reg_operands
-= 2;
4467 /* Specify the modrm encoding for memory addressing. Include
4468 the high order bit that is normally stored in the REX byte
4469 in the register field. */
4470 i
.tm
.extension_opcode
= DREX_X1_XMEM_X2_X1
;
4471 i
.drex
.modrm_reg
= 2;
4472 i
.drex
.modrm_regmem
= 1;
4473 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4474 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4477 /* Case 4: 4 operand insn, dest = src3, src2 = register. */
4478 else if (i
.types
[0].bitfield
.regxmm
!= 0
4479 && i
.types
[1].bitfield
.regxmm
!= 0
4480 && i
.types
[2].bitfield
.regxmm
!= 0
4481 && i
.types
[3].bitfield
.regxmm
!= 0
4482 && i
.op
[2].regs
->reg_num
== i
.op
[3].regs
->reg_num
4483 && i
.op
[2].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4485 /* clear the arguments that are stored in drex */
4486 operand_type_set (&i
.types
[2], 0);
4487 operand_type_set (&i
.types
[3], 0);
4488 i
.reg_operands
-= 2;
4490 /* There are two different ways to encode a 4 operand
4491 instruction with all registers that uses OC1 set to
4492 0 or 1. Favor setting OC1 to 0 since this mimics the
4493 actions of other SSE5 assemblers. Use modrm encoding
4494 2 for register/register. Include the high order bit that
4495 is normally stored in the REX byte in the register
4497 i
.tm
.extension_opcode
= DREX_XMEM_X1_X2_X2
;
4498 i
.drex
.modrm_reg
= 1;
4499 i
.drex
.modrm_regmem
= 0;
4501 /* Remember the register, including the upper bits */
4502 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4503 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4506 /* Case 5: 4 operand insn, dest = src3, src2 = memory. */
4507 else if (i
.types
[0].bitfield
.regxmm
!= 0
4508 && (i
.types
[1].bitfield
.regxmm
4509 || operand_type_check (i
.types
[1], anymem
))
4510 && i
.types
[2].bitfield
.regxmm
!= 0
4511 && i
.types
[3].bitfield
.regxmm
!= 0
4512 && i
.op
[2].regs
->reg_num
== i
.op
[3].regs
->reg_num
4513 && i
.op
[2].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4515 /* Clear the arguments that are stored in drex. */
4516 operand_type_set (&i
.types
[2], 0);
4517 operand_type_set (&i
.types
[3], 0);
4518 i
.reg_operands
-= 2;
4520 /* Specify the modrm encoding and remember the register
4521 including the bits normally stored in the REX byte. */
4522 i
.tm
.extension_opcode
= DREX_X1_XMEM_X2_X2
;
4523 i
.drex
.modrm_reg
= 0;
4524 i
.drex
.modrm_regmem
= 1;
4525 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4526 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4529 /* Case 6: 4 operand insn, dest = src3, src1 = memory. */
4530 else if (operand_type_check (i
.types
[0], anymem
) != 0
4531 && i
.types
[1].bitfield
.regxmm
!= 0
4532 && i
.types
[2].bitfield
.regxmm
!= 0
4533 && i
.types
[3].bitfield
.regxmm
!= 0
4534 && i
.op
[2].regs
->reg_num
== i
.op
[3].regs
->reg_num
4535 && i
.op
[2].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4537 /* clear the arguments that are stored in drex */
4538 operand_type_set (&i
.types
[2], 0);
4539 operand_type_set (&i
.types
[3], 0);
4540 i
.reg_operands
-= 2;
4542 /* Specify the modrm encoding and remember the register
4543 including the bits normally stored in the REX byte. */
4544 i
.tm
.extension_opcode
= DREX_XMEM_X1_X2_X2
;
4545 i
.drex
.modrm_reg
= 1;
4546 i
.drex
.modrm_regmem
= 0;
4547 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4548 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4552 as_bad (_("Incorrect operands for the '%s' instruction"),
4556 /* SSE5 instructions with the DREX byte where the only memory operand
4557 is in the 2nd argument, and the first and last xmm register must
4558 match, and is encoded in the DREX byte. */
4559 else if (i
.tm
.opcode_modifier
.drex
4560 && !i
.tm
.opcode_modifier
.drexv
4563 /* Case 1: 4 operand insn, dest = src1, src3 = reg/mem. */
4564 if (i
.types
[0].bitfield
.regxmm
!= 0
4565 && (i
.types
[1].bitfield
.regxmm
4566 || operand_type_check(i
.types
[1], anymem
))
4567 && i
.types
[2].bitfield
.regxmm
!= 0
4568 && i
.types
[3].bitfield
.regxmm
!= 0
4569 && i
.op
[0].regs
->reg_num
== i
.op
[3].regs
->reg_num
4570 && i
.op
[0].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4572 /* clear the arguments that are stored in drex */
4573 operand_type_set (&i
.types
[0], 0);
4574 operand_type_set (&i
.types
[3], 0);
4575 i
.reg_operands
-= 2;
4577 /* Specify the modrm encoding and remember the register
4578 including the high bit normally stored in the REX
4580 i
.drex
.modrm_reg
= 2;
4581 i
.drex
.modrm_regmem
= 1;
4582 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4583 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4587 as_bad (_("Incorrect operands for the '%s' instruction"),
4591 /* SSE5 3 operand instructions that the result is a register, being
4592 either operand can be a memory operand, using OC0 to note which
4593 one is the memory. */
4594 else if (i
.tm
.opcode_modifier
.drex
4595 && i
.tm
.opcode_modifier
.drexv
4598 i
.tm
.extension_opcode
= None
;
4600 /* Case 1: 3 operand insn, src1 = register. */
4601 if (i
.types
[0].bitfield
.regxmm
!= 0
4602 && i
.types
[1].bitfield
.regxmm
!= 0
4603 && i
.types
[2].bitfield
.regxmm
!= 0)
4605 /* Clear the arguments that are stored in drex. */
4606 operand_type_set (&i
.types
[2], 0);
4609 /* Specify the modrm encoding and remember the register
4610 including the high bit normally stored in the REX byte. */
4611 i
.tm
.extension_opcode
= DREX_XMEM_X1_X2
;
4612 i
.drex
.modrm_reg
= 1;
4613 i
.drex
.modrm_regmem
= 0;
4614 i
.drex
.reg
= (i
.op
[2].regs
->reg_num
4615 + ((i
.op
[2].regs
->reg_flags
& RegRex
) ? 8 : 0));
4618 /* Case 2: 3 operand insn, src1 = memory. */
4619 else if (operand_type_check (i
.types
[0], anymem
) != 0
4620 && i
.types
[1].bitfield
.regxmm
!= 0
4621 && i
.types
[2].bitfield
.regxmm
!= 0)
4623 /* Clear the arguments that are stored in drex. */
4624 operand_type_set (&i
.types
[2], 0);
4627 /* Specify the modrm encoding and remember the register
4628 including the high bit normally stored in the REX
4630 i
.tm
.extension_opcode
= DREX_XMEM_X1_X2
;
4631 i
.drex
.modrm_reg
= 1;
4632 i
.drex
.modrm_regmem
= 0;
4633 i
.drex
.reg
= (i
.op
[2].regs
->reg_num
4634 + ((i
.op
[2].regs
->reg_flags
& RegRex
) ? 8 : 0));
4637 /* Case 3: 3 operand insn, src2 = memory. */
4638 else if (i
.types
[0].bitfield
.regxmm
!= 0
4639 && operand_type_check (i
.types
[1], anymem
) != 0
4640 && i
.types
[2].bitfield
.regxmm
!= 0)
4642 /* Clear the arguments that are stored in drex. */
4643 operand_type_set (&i
.types
[2], 0);
4646 /* Specify the modrm encoding and remember the register
4647 including the high bit normally stored in the REX byte. */
4648 i
.tm
.extension_opcode
= DREX_X1_XMEM_X2
;
4649 i
.drex
.modrm_reg
= 0;
4650 i
.drex
.modrm_regmem
= 1;
4651 i
.drex
.reg
= (i
.op
[2].regs
->reg_num
4652 + ((i
.op
[2].regs
->reg_flags
& RegRex
) ? 8 : 0));
4656 as_bad (_("Incorrect operands for the '%s' instruction"),
4660 /* SSE5 4 operand instructions that are the comparison instructions
4661 where the first operand is the immediate value of the comparison
4663 else if (i
.tm
.opcode_modifier
.drexc
!= 0 && i
.operands
== 4)
4665 /* Case 1: 4 operand insn, src1 = reg/memory. */
4666 if (operand_type_check (i
.types
[0], imm
) != 0
4667 && (i
.types
[1].bitfield
.regxmm
4668 || operand_type_check (i
.types
[1], anymem
))
4669 && i
.types
[2].bitfield
.regxmm
!= 0
4670 && i
.types
[3].bitfield
.regxmm
!= 0)
4672 /* clear the arguments that are stored in drex */
4673 operand_type_set (&i
.types
[3], 0);
4676 /* Specify the modrm encoding and remember the register
4677 including the high bit normally stored in the REX byte. */
4678 i
.drex
.modrm_reg
= 2;
4679 i
.drex
.modrm_regmem
= 1;
4680 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4681 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4684 /* Case 2: 3 operand insn with ImmExt that places the
4685 opcode_extension as an immediate argument. This is used for
4686 all of the varients of comparison that supplies the appropriate
4687 value as part of the instruction. */
4688 else if ((i
.types
[0].bitfield
.regxmm
4689 || operand_type_check (i
.types
[0], anymem
))
4690 && i
.types
[1].bitfield
.regxmm
!= 0
4691 && i
.types
[2].bitfield
.regxmm
!= 0
4692 && operand_type_check (i
.types
[3], imm
) != 0)
4694 /* clear the arguments that are stored in drex */
4695 operand_type_set (&i
.types
[2], 0);
4698 /* Specify the modrm encoding and remember the register
4699 including the high bit normally stored in the REX byte. */
4700 i
.drex
.modrm_reg
= 1;
4701 i
.drex
.modrm_regmem
= 0;
4702 i
.drex
.reg
= (i
.op
[2].regs
->reg_num
4703 + ((i
.op
[2].regs
->reg_flags
& RegRex
) ? 8 : 0));
4707 as_bad (_("Incorrect operands for the '%s' instruction"),
4711 else if (i
.tm
.opcode_modifier
.drex
4712 || i
.tm
.opcode_modifier
.drexv
4713 || i
.tm
.opcode_modifier
.drexc
)
4714 as_bad (_("Internal error for the '%s' instruction"), i
.tm
.name
);
4718 bad_implicit_operand (int xmm
)
4720 const char *reg
= xmm
? "xmm0" : "ymm0";
4722 as_bad (_("the last operand of `%s' must be `%s%s'"),
4723 i
.tm
.name
, register_prefix
, reg
);
4725 as_bad (_("the first operand of `%s' must be `%s%s'"),
4726 i
.tm
.name
, register_prefix
, reg
);
4731 process_operands (void)
4733 /* Default segment register this instruction will use for memory
4734 accesses. 0 means unknown. This is only for optimizing out
4735 unnecessary segment overrides. */
4736 const seg_entry
*default_seg
= 0;
4738 /* Handle all of the DREX munging that SSE5 needs. */
4739 if (i
.tm
.opcode_modifier
.drex
4740 || i
.tm
.opcode_modifier
.drexv
4741 || i
.tm
.opcode_modifier
.drexc
)
4744 if (i
.tm
.opcode_modifier
.sse2avx
4745 && (i
.tm
.opcode_modifier
.vexnds
4746 || i
.tm
.opcode_modifier
.vexndd
))
4748 unsigned int dup
= i
.operands
;
4749 unsigned int dest
= dup
- 1;
4752 /* The destination must be an xmm register. */
4753 assert (i
.reg_operands
4754 && MAX_OPERANDS
> dup
4755 && operand_type_equal (&i
.types
[dest
], ®xmm
));
4757 if (i
.tm
.opcode_modifier
.firstxmm0
)
4759 /* The first operand is implicit and must be xmm0. */
4760 assert (operand_type_equal (&i
.types
[0], ®xmm
));
4761 if (i
.op
[0].regs
->reg_num
!= 0)
4762 return bad_implicit_operand (1);
4764 if (i
.tm
.opcode_modifier
.vex3sources
)
4766 /* Keep xmm0 for instructions with VEX prefix and 3
4772 /* We remove the first xmm0 and keep the number of
4773 operands unchanged, which in fact duplicates the
4775 for (j
= 1; j
< i
.operands
; j
++)
4777 i
.op
[j
- 1] = i
.op
[j
];
4778 i
.types
[j
- 1] = i
.types
[j
];
4779 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
4783 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
4785 assert ((MAX_OPERANDS
- 1) > dup
4786 && i
.tm
.opcode_modifier
.vex3sources
);
4788 /* Add the implicit xmm0 for instructions with VEX prefix
4790 for (j
= i
.operands
; j
> 0; j
--)
4792 i
.op
[j
] = i
.op
[j
- 1];
4793 i
.types
[j
] = i
.types
[j
- 1];
4794 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
4797 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
4798 i
.types
[0] = regxmm
;
4799 i
.tm
.operand_types
[0] = regxmm
;
4802 i
.reg_operands
+= 2;
4807 i
.op
[dup
] = i
.op
[dest
];
4808 i
.types
[dup
] = i
.types
[dest
];
4809 i
.tm
.operand_types
[dup
] = i
.tm
.operand_types
[dest
];
4818 i
.op
[dup
] = i
.op
[dest
];
4819 i
.types
[dup
] = i
.types
[dest
];
4820 i
.tm
.operand_types
[dup
] = i
.tm
.operand_types
[dest
];
4823 if (i
.tm
.opcode_modifier
.immext
)
4826 else if (i
.tm
.opcode_modifier
.firstxmm0
)
4830 /* The first operand is implicit and must be xmm0/ymm0. */
4831 assert (i
.reg_operands
4832 && (operand_type_equal (&i
.types
[0], ®xmm
)
4833 || operand_type_equal (&i
.types
[0], ®ymm
)));
4834 if (i
.op
[0].regs
->reg_num
!= 0)
4835 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
4837 for (j
= 1; j
< i
.operands
; j
++)
4839 i
.op
[j
- 1] = i
.op
[j
];
4840 i
.types
[j
- 1] = i
.types
[j
];
4842 /* We need to adjust fields in i.tm since they are used by
4843 build_modrm_byte. */
4844 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
4851 else if (i
.tm
.opcode_modifier
.regkludge
)
4853 /* The imul $imm, %reg instruction is converted into
4854 imul $imm, %reg, %reg, and the clr %reg instruction
4855 is converted into xor %reg, %reg. */
4857 unsigned int first_reg_op
;
4859 if (operand_type_check (i
.types
[0], reg
))
4863 /* Pretend we saw the extra register operand. */
4864 assert (i
.reg_operands
== 1
4865 && i
.op
[first_reg_op
+ 1].regs
== 0);
4866 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
4867 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
4872 if (i
.tm
.opcode_modifier
.shortform
)
4874 if (i
.types
[0].bitfield
.sreg2
4875 || i
.types
[0].bitfield
.sreg3
)
4877 if (i
.tm
.base_opcode
== POP_SEG_SHORT
4878 && i
.op
[0].regs
->reg_num
== 1)
4880 as_bad (_("you can't `pop %%cs'"));
4883 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
4884 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
4889 /* The register or float register operand is in operand
4893 if (i
.types
[0].bitfield
.floatreg
4894 || operand_type_check (i
.types
[0], reg
))
4898 /* Register goes in low 3 bits of opcode. */
4899 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
4900 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
4902 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
4904 /* Warn about some common errors, but press on regardless.
4905 The first case can be generated by gcc (<= 2.8.1). */
4906 if (i
.operands
== 2)
4908 /* Reversed arguments on faddp, fsubp, etc. */
4909 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
4910 register_prefix
, i
.op
[1].regs
->reg_name
,
4911 register_prefix
, i
.op
[0].regs
->reg_name
);
4915 /* Extraneous `l' suffix on fp insn. */
4916 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
4917 register_prefix
, i
.op
[0].regs
->reg_name
);
4922 else if (i
.tm
.opcode_modifier
.modrm
)
4924 /* The opcode is completed (modulo i.tm.extension_opcode which
4925 must be put into the modrm byte). Now, we make the modrm and
4926 index base bytes based on all the info we've collected. */
4928 default_seg
= build_modrm_byte ();
4930 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
4934 else if (i
.tm
.opcode_modifier
.isstring
)
4936 /* For the string instructions that allow a segment override
4937 on one of their operands, the default segment is ds. */
4941 if (i
.tm
.base_opcode
== 0x8d /* lea */
4944 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
4946 /* If a segment was explicitly specified, and the specified segment
4947 is not the default, use an opcode prefix to select it. If we
4948 never figured out what the default segment is, then default_seg
4949 will be zero at this point, and the specified segment prefix will
4951 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
4953 if (!add_prefix (i
.seg
[0]->seg_prefix
))
4959 static const seg_entry
*
4960 build_modrm_byte (void)
4962 const seg_entry
*default_seg
= 0;
4963 unsigned int source
, dest
;
4966 /* The first operand of instructions with VEX prefix and 3 sources
4967 must be VEX_Imm4. */
4968 vex_3_sources
= i
.tm
.opcode_modifier
.vex3sources
;
4971 unsigned int nds
, reg
;
4973 if (i
.tm
.opcode_modifier
.veximmext
4974 && i
.tm
.opcode_modifier
.immext
)
4976 dest
= i
.operands
- 2;
4980 dest
= i
.operands
- 1;
4983 /* There are 2 kinds of instructions:
4984 1. 5 operands: one immediate operand and 4 register
4985 operands or 3 register operands plus 1 memory operand.
4986 It must have VexNDS and VexW0 or VexW1. The destination
4987 must be either XMM or YMM register.
4988 2. 4 operands: 4 register operands or 3 register operands
4989 plus 1 memory operand. It must have VexNDS and VexImmExt. */
4990 if (!((i
.reg_operands
== 4
4991 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
4992 && i
.tm
.opcode_modifier
.vexnds
4993 && (operand_type_equal (&i
.tm
.operand_types
[dest
], ®xmm
)
4994 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®ymm
))
4995 && (operand_type_equal (&i
.tm
.operand_types
[nds
], ®xmm
)
4996 || operand_type_equal (&i
.tm
.operand_types
[nds
], ®ymm
))
4998 && i
.imm_operands
== 1
4999 && i
.types
[0].bitfield
.vex_imm4
5000 && (i
.tm
.opcode_modifier
.vexw0
5001 || i
.tm
.opcode_modifier
.vexw1
))
5003 && (i
.imm_operands
== 0
5004 || (i
.imm_operands
== 1
5005 && i
.tm
.opcode_modifier
.immext
))
5006 && i
.tm
.opcode_modifier
.veximmext
))))
5009 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
5011 if (i
.imm_operands
== 0)
5013 /* When there is no immediate operand, generate an 8bit
5014 immediate operand to encode the first operand. */
5015 expressionS
*exp
= &im_expressions
[i
.imm_operands
++];
5016 i
.op
[i
.operands
].imms
= exp
;
5017 i
.types
[i
.operands
] = imm8
;
5019 /* If VexW1 is set, the first operand is the source and
5020 the second operand is encoded in the immediate operand. */
5021 if (i
.tm
.opcode_modifier
.vexw1
)
5031 assert (operand_type_equal (&i
.tm
.operand_types
[reg
], ®xmm
)
5032 || operand_type_equal (&i
.tm
.operand_types
[reg
],
5034 exp
->X_op
= O_constant
;
5036 = ((i
.op
[reg
].regs
->reg_num
5037 + ((i
.op
[reg
].regs
->reg_flags
& RegRex
) ? 8 : 0)) << 4);
5043 if (i
.tm
.opcode_modifier
.vexw0
)
5045 /* If VexW0 is set, the third operand is the source and
5046 the second operand is encoded in the immediate
5053 /* VexW1 is set, the second operand is the source and
5054 the third operand is encoded in the immediate
5060 if (i
.tm
.opcode_modifier
.immext
)
5062 /* When ImmExt is set, the immdiate byte is the last
5064 imm
= i
.operands
- 1;
5072 /* Turn on Imm8 so that output_imm will generate it. */
5073 i
.types
[imm
].bitfield
.imm8
= 1;
5076 assert (operand_type_equal (&i
.tm
.operand_types
[reg
], ®xmm
)
5077 || operand_type_equal (&i
.tm
.operand_types
[reg
],
5079 i
.op
[imm
].imms
->X_add_number
5080 |= ((i
.op
[reg
].regs
->reg_num
5081 + ((i
.op
[reg
].regs
->reg_flags
& RegRex
) ? 8 : 0)) << 4);
5087 /* SSE5 4 operand instructions are encoded in such a way that one of
5088 the inputs must match the destination register. Process_drex hides
5089 the 3rd argument in the drex field, so that by the time we get
5090 here, it looks to GAS as if this is a 2 operand instruction. */
5091 if ((i
.tm
.opcode_modifier
.drex
5092 || i
.tm
.opcode_modifier
.drexv
5093 || i
.tm
.opcode_modifier
.drexc
)
5094 && i
.reg_operands
== 2)
5096 const reg_entry
*reg
= i
.op
[i
.drex
.modrm_reg
].regs
;
5097 const reg_entry
*regmem
= i
.op
[i
.drex
.modrm_regmem
].regs
;
5099 i
.rm
.reg
= reg
->reg_num
;
5100 i
.rm
.regmem
= regmem
->reg_num
;
5102 if ((reg
->reg_flags
& RegRex
) != 0)
5104 if ((regmem
->reg_flags
& RegRex
) != 0)
5108 /* i.reg_operands MUST be the number of real register operands;
5109 implicit registers do not count. If there are 3 register
5110 operands, it must be a instruction with VexNDS. For a
5111 instruction with VexNDD, the destination register is encoded
5112 in VEX prefix. If there are 4 register operands, it must be
5113 a instruction with VEX prefix and 3 sources. */
5114 else if (i
.mem_operands
== 0
5115 && ((i
.reg_operands
== 2
5116 && !i
.tm
.opcode_modifier
.vexndd
)
5117 || (i
.reg_operands
== 3
5118 && i
.tm
.opcode_modifier
.vexnds
)
5119 || (i
.reg_operands
== 4 && vex_3_sources
)))
5127 /* When there are 3 operands, one of them may be immediate,
5128 which may be the first or the last operand. Otherwise,
5129 the first operand must be shift count register (cl) or it
5130 is an instruction with VexNDS. */
5131 assert (i
.imm_operands
== 1
5132 || (i
.imm_operands
== 0
5133 && (i
.tm
.opcode_modifier
.vexnds
5134 || i
.types
[0].bitfield
.shiftcount
)));
5135 if (operand_type_check (i
.types
[0], imm
)
5136 || i
.types
[0].bitfield
.shiftcount
)
5142 /* When there are 4 operands, the first two must be 8bit
5143 immediate operands. The source operand will be the 3rd
5146 For instructions with VexNDS, if the first operand
5147 an imm8, the source operand is the 2nd one. If the last
5148 operand is imm8, the source operand is the first one. */
5149 assert ((i
.imm_operands
== 2
5150 && i
.types
[0].bitfield
.imm8
5151 && i
.types
[1].bitfield
.imm8
)
5152 || (i
.tm
.opcode_modifier
.vexnds
5153 && i
.imm_operands
== 1
5154 && (i
.types
[0].bitfield
.imm8
5155 || i
.types
[i
.operands
- 1].bitfield
.imm8
)));
5156 if (i
.tm
.opcode_modifier
.vexnds
)
5158 if (i
.types
[0].bitfield
.imm8
)
5176 if (i
.tm
.opcode_modifier
.vexnds
)
5178 /* For instructions with VexNDS, the register-only
5179 source operand must be XMM or YMM register. It is
5180 encoded in VEX prefix. */
5181 if ((dest
+ 1) >= i
.operands
5182 || (!operand_type_equal (&i
.tm
.operand_types
[dest
],
5184 && !operand_type_equal (&i
.tm
.operand_types
[dest
],
5187 i
.vex
.register_specifier
= i
.op
[dest
].regs
;
5193 /* One of the register operands will be encoded in the i.tm.reg
5194 field, the other in the combined i.tm.mode and i.tm.regmem
5195 fields. If no form of this instruction supports a memory
5196 destination operand, then we assume the source operand may
5197 sometimes be a memory operand and so we need to store the
5198 destination in the i.rm.reg field. */
5199 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
5200 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
5202 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
5203 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
5204 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
5206 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
5211 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
5212 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
5213 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
5215 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
5218 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
5220 if (!i
.types
[0].bitfield
.control
5221 && !i
.types
[1].bitfield
.control
)
5223 i
.rex
&= ~(REX_R
| REX_B
);
5224 add_prefix (LOCK_PREFIX_OPCODE
);
5228 { /* If it's not 2 reg operands... */
5233 unsigned int fake_zero_displacement
= 0;
5236 /* This has been precalculated for SSE5 instructions
5237 that have a DREX field earlier in process_drex. */
5238 if (i
.tm
.opcode_modifier
.drex
5239 || i
.tm
.opcode_modifier
.drexv
5240 || i
.tm
.opcode_modifier
.drexc
)
5241 op
= i
.drex
.modrm_regmem
;
5244 for (op
= 0; op
< i
.operands
; op
++)
5245 if (operand_type_check (i
.types
[op
], anymem
))
5247 assert (op
< i
.operands
);
5252 if (i
.base_reg
== 0)
5255 if (!i
.disp_operands
)
5256 fake_zero_displacement
= 1;
5257 if (i
.index_reg
== 0)
5259 /* Operand is just <disp> */
5260 if (flag_code
== CODE_64BIT
)
5262 /* 64bit mode overwrites the 32bit absolute
5263 addressing by RIP relative addressing and
5264 absolute addressing is encoded by one of the
5265 redundant SIB forms. */
5266 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5267 i
.sib
.base
= NO_BASE_REGISTER
;
5268 i
.sib
.index
= NO_INDEX_REGISTER
;
5269 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
5270 ? disp32s
: disp32
);
5272 else if ((flag_code
== CODE_16BIT
)
5273 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
5275 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
5276 i
.types
[op
] = disp16
;
5280 i
.rm
.regmem
= NO_BASE_REGISTER
;
5281 i
.types
[op
] = disp32
;
5284 else /* !i.base_reg && i.index_reg */
5286 if (i
.index_reg
->reg_num
== RegEiz
5287 || i
.index_reg
->reg_num
== RegRiz
)
5288 i
.sib
.index
= NO_INDEX_REGISTER
;
5290 i
.sib
.index
= i
.index_reg
->reg_num
;
5291 i
.sib
.base
= NO_BASE_REGISTER
;
5292 i
.sib
.scale
= i
.log2_scale_factor
;
5293 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5294 i
.types
[op
].bitfield
.disp8
= 0;
5295 i
.types
[op
].bitfield
.disp16
= 0;
5296 i
.types
[op
].bitfield
.disp64
= 0;
5297 if (flag_code
!= CODE_64BIT
)
5299 /* Must be 32 bit */
5300 i
.types
[op
].bitfield
.disp32
= 1;
5301 i
.types
[op
].bitfield
.disp32s
= 0;
5305 i
.types
[op
].bitfield
.disp32
= 0;
5306 i
.types
[op
].bitfield
.disp32s
= 1;
5308 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5312 /* RIP addressing for 64bit mode. */
5313 else if (i
.base_reg
->reg_num
== RegRip
||
5314 i
.base_reg
->reg_num
== RegEip
)
5316 i
.rm
.regmem
= NO_BASE_REGISTER
;
5317 i
.types
[op
].bitfield
.disp8
= 0;
5318 i
.types
[op
].bitfield
.disp16
= 0;
5319 i
.types
[op
].bitfield
.disp32
= 0;
5320 i
.types
[op
].bitfield
.disp32s
= 1;
5321 i
.types
[op
].bitfield
.disp64
= 0;
5322 i
.flags
[op
] |= Operand_PCrel
;
5323 if (! i
.disp_operands
)
5324 fake_zero_displacement
= 1;
5326 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
5328 switch (i
.base_reg
->reg_num
)
5331 if (i
.index_reg
== 0)
5333 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
5334 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
5338 if (i
.index_reg
== 0)
5341 if (operand_type_check (i
.types
[op
], disp
) == 0)
5343 /* fake (%bp) into 0(%bp) */
5344 i
.types
[op
].bitfield
.disp8
= 1;
5345 fake_zero_displacement
= 1;
5348 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
5349 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
5351 default: /* (%si) -> 4 or (%di) -> 5 */
5352 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
5354 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5356 else /* i.base_reg and 32/64 bit mode */
5358 if (flag_code
== CODE_64BIT
5359 && operand_type_check (i
.types
[op
], disp
))
5361 i386_operand_type temp
;
5362 operand_type_set (&temp
, 0);
5363 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
5365 if (i
.prefix
[ADDR_PREFIX
] == 0)
5366 i
.types
[op
].bitfield
.disp32s
= 1;
5368 i
.types
[op
].bitfield
.disp32
= 1;
5371 i
.rm
.regmem
= i
.base_reg
->reg_num
;
5372 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
5374 i
.sib
.base
= i
.base_reg
->reg_num
;
5375 /* x86-64 ignores REX prefix bit here to avoid decoder
5377 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
5380 if (i
.disp_operands
== 0)
5382 fake_zero_displacement
= 1;
5383 i
.types
[op
].bitfield
.disp8
= 1;
5386 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
5390 i
.sib
.scale
= i
.log2_scale_factor
;
5391 if (i
.index_reg
== 0)
5393 /* <disp>(%esp) becomes two byte modrm with no index
5394 register. We've already stored the code for esp
5395 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5396 Any base register besides %esp will not use the
5397 extra modrm byte. */
5398 i
.sib
.index
= NO_INDEX_REGISTER
;
5402 if (i
.index_reg
->reg_num
== RegEiz
5403 || i
.index_reg
->reg_num
== RegRiz
)
5404 i
.sib
.index
= NO_INDEX_REGISTER
;
5406 i
.sib
.index
= i
.index_reg
->reg_num
;
5407 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5408 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5413 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5414 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
5417 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5420 if (fake_zero_displacement
)
5422 /* Fakes a zero displacement assuming that i.types[op]
5423 holds the correct displacement size. */
5426 assert (i
.op
[op
].disps
== 0);
5427 exp
= &disp_expressions
[i
.disp_operands
++];
5428 i
.op
[op
].disps
= exp
;
5429 exp
->X_op
= O_constant
;
5430 exp
->X_add_number
= 0;
5431 exp
->X_add_symbol
= (symbolS
*) 0;
5432 exp
->X_op_symbol
= (symbolS
*) 0;
5440 /* Fill in i.rm.reg or i.rm.regmem field with register operand
5441 (if any) based on i.tm.extension_opcode. Again, we must be
5442 careful to make sure that segment/control/debug/test/MMX
5443 registers are coded into the i.rm.reg field. */
5448 /* This has been precalculated for SSE5 instructions
5449 that have a DREX field earlier in process_drex. */
5450 if (i
.tm
.opcode_modifier
.drex
5451 || i
.tm
.opcode_modifier
.drexv
5452 || i
.tm
.opcode_modifier
.drexc
)
5454 op
= i
.drex
.modrm_reg
;
5455 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
5456 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5461 unsigned int vex_reg
= ~0;
5463 for (op
= 0; op
< i
.operands
; op
++)
5464 if (i
.types
[op
].bitfield
.reg8
5465 || i
.types
[op
].bitfield
.reg16
5466 || i
.types
[op
].bitfield
.reg32
5467 || i
.types
[op
].bitfield
.reg64
5468 || i
.types
[op
].bitfield
.regmmx
5469 || i
.types
[op
].bitfield
.regxmm
5470 || i
.types
[op
].bitfield
.regymm
5471 || i
.types
[op
].bitfield
.sreg2
5472 || i
.types
[op
].bitfield
.sreg3
5473 || i
.types
[op
].bitfield
.control
5474 || i
.types
[op
].bitfield
.debug
5475 || i
.types
[op
].bitfield
.test
)
5480 else if (i
.tm
.opcode_modifier
.vexnds
)
5482 /* For instructions with VexNDS, the register-only
5483 source operand is encoded in VEX prefix. */
5484 assert (mem
!= (unsigned int) ~0);
5489 assert (op
< i
.operands
);
5494 assert (vex_reg
< i
.operands
);
5497 else if (i
.tm
.opcode_modifier
.vexndd
)
5499 /* For instructions with VexNDD, there should be
5500 no memory operand and the register destination
5501 is encoded in VEX prefix. */
5502 assert (i
.mem_operands
== 0
5503 && (op
+ 2) == i
.operands
);
5507 assert (op
< i
.operands
);
5509 if (vex_reg
!= (unsigned int) ~0)
5511 assert (i
.reg_operands
== 2);
5513 if (!operand_type_equal (&i
.tm
.operand_types
[vex_reg
],
5515 && !operand_type_equal (&i
.tm
.operand_types
[vex_reg
],
5518 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
5521 /* If there is an extension opcode to put here, the
5522 register number must be put into the regmem field. */
5523 if (i
.tm
.extension_opcode
!= None
)
5525 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
5526 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5531 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
5532 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5537 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
5538 must set it to 3 to indicate this is a register operand
5539 in the regmem field. */
5540 if (!i
.mem_operands
)
5544 /* Fill in i.rm.reg field with extension opcode (if any). */
5545 if (i
.tm
.extension_opcode
!= None
5546 && !(i
.tm
.opcode_modifier
.drex
5547 || i
.tm
.opcode_modifier
.drexv
5548 || i
.tm
.opcode_modifier
.drexc
))
5549 i
.rm
.reg
= i
.tm
.extension_opcode
;
5555 output_branch (void)
5560 relax_substateT subtype
;
5565 if (flag_code
== CODE_16BIT
)
5569 if (i
.prefix
[DATA_PREFIX
] != 0)
5575 /* Pentium4 branch hints. */
5576 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
5577 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
5582 if (i
.prefix
[REX_PREFIX
] != 0)
5588 if (i
.prefixes
!= 0 && !intel_syntax
)
5589 as_warn (_("skipping prefixes on this instruction"));
5591 /* It's always a symbol; End frag & setup for relax.
5592 Make sure there is enough room in this frag for the largest
5593 instruction we may generate in md_convert_frag. This is 2
5594 bytes for the opcode and room for the prefix and largest
5596 frag_grow (prefix
+ 2 + 4);
5597 /* Prefix and 1 opcode byte go in fr_fix. */
5598 p
= frag_more (prefix
+ 1);
5599 if (i
.prefix
[DATA_PREFIX
] != 0)
5600 *p
++ = DATA_PREFIX_OPCODE
;
5601 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
5602 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
5603 *p
++ = i
.prefix
[SEG_PREFIX
];
5604 if (i
.prefix
[REX_PREFIX
] != 0)
5605 *p
++ = i
.prefix
[REX_PREFIX
];
5606 *p
= i
.tm
.base_opcode
;
5608 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
5609 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
);
5610 else if (cpu_arch_flags
.bitfield
.cpui386
)
5611 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, SMALL
);
5613 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, SMALL
);
5616 sym
= i
.op
[0].disps
->X_add_symbol
;
5617 off
= i
.op
[0].disps
->X_add_number
;
5619 if (i
.op
[0].disps
->X_op
!= O_constant
5620 && i
.op
[0].disps
->X_op
!= O_symbol
)
5622 /* Handle complex expressions. */
5623 sym
= make_expr_symbol (i
.op
[0].disps
);
5627 /* 1 possible extra opcode + 4 byte displacement go in var part.
5628 Pass reloc in fr_var. */
5629 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
5639 if (i
.tm
.opcode_modifier
.jumpbyte
)
5641 /* This is a loop or jecxz type instruction. */
5643 if (i
.prefix
[ADDR_PREFIX
] != 0)
5645 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
5648 /* Pentium4 branch hints. */
5649 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
5650 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
5652 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
5661 if (flag_code
== CODE_16BIT
)
5664 if (i
.prefix
[DATA_PREFIX
] != 0)
5666 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
5676 if (i
.prefix
[REX_PREFIX
] != 0)
5678 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
5682 if (i
.prefixes
!= 0 && !intel_syntax
)
5683 as_warn (_("skipping prefixes on this instruction"));
5685 p
= frag_more (1 + size
);
5686 *p
++ = i
.tm
.base_opcode
;
5688 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5689 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
5691 /* All jumps handled here are signed, but don't use a signed limit
5692 check for 32 and 16 bit jumps as we want to allow wrap around at
5693 4G and 64k respectively. */
5695 fixP
->fx_signed
= 1;
5699 output_interseg_jump (void)
5707 if (flag_code
== CODE_16BIT
)
5711 if (i
.prefix
[DATA_PREFIX
] != 0)
5717 if (i
.prefix
[REX_PREFIX
] != 0)
5727 if (i
.prefixes
!= 0 && !intel_syntax
)
5728 as_warn (_("skipping prefixes on this instruction"));
5730 /* 1 opcode; 2 segment; offset */
5731 p
= frag_more (prefix
+ 1 + 2 + size
);
5733 if (i
.prefix
[DATA_PREFIX
] != 0)
5734 *p
++ = DATA_PREFIX_OPCODE
;
5736 if (i
.prefix
[REX_PREFIX
] != 0)
5737 *p
++ = i
.prefix
[REX_PREFIX
];
5739 *p
++ = i
.tm
.base_opcode
;
5740 if (i
.op
[1].imms
->X_op
== O_constant
)
5742 offsetT n
= i
.op
[1].imms
->X_add_number
;
5745 && !fits_in_unsigned_word (n
)
5746 && !fits_in_signed_word (n
))
5748 as_bad (_("16-bit jump out of range"));
5751 md_number_to_chars (p
, n
, size
);
5754 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5755 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
5756 if (i
.op
[0].imms
->X_op
!= O_constant
)
5757 as_bad (_("can't handle non absolute segment in `%s'"),
5759 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
5765 fragS
*insn_start_frag
;
5766 offsetT insn_start_off
;
5768 /* Tie dwarf2 debug info to the address at the start of the insn.
5769 We can't do this after the insn has been output as the current
5770 frag may have been closed off. eg. by frag_var. */
5771 dwarf2_emit_insn (0);
5773 insn_start_frag
= frag_now
;
5774 insn_start_off
= frag_now_fix ();
5777 if (i
.tm
.opcode_modifier
.jump
)
5779 else if (i
.tm
.opcode_modifier
.jumpbyte
5780 || i
.tm
.opcode_modifier
.jumpdword
)
5782 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
5783 output_interseg_jump ();
5786 /* Output normal instructions here. */
5790 unsigned int prefix
;
5792 /* Since the VEX prefix contains the implicit prefix, we don't
5793 need the explicit prefix. */
5794 if (!i
.tm
.opcode_modifier
.vex
)
5796 switch (i
.tm
.opcode_length
)
5799 if (i
.tm
.base_opcode
& 0xff000000)
5801 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
5806 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
5808 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
5809 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
5812 if (prefix
!= REPE_PREFIX_OPCODE
5813 || (i
.prefix
[LOCKREP_PREFIX
]
5814 != REPE_PREFIX_OPCODE
))
5815 add_prefix (prefix
);
5818 add_prefix (prefix
);
5827 /* The prefix bytes. */
5828 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
5830 FRAG_APPEND_1_CHAR (*q
);
5833 if (i
.tm
.opcode_modifier
.vex
)
5835 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
5840 /* REX byte is encoded in VEX prefix. */
5844 FRAG_APPEND_1_CHAR (*q
);
5847 /* There should be no other prefixes for instructions
5852 /* Now the VEX prefix. */
5853 p
= frag_more (i
.vex
.length
);
5854 for (j
= 0; j
< i
.vex
.length
; j
++)
5855 p
[j
] = i
.vex
.bytes
[j
];
5858 /* Now the opcode; be careful about word order here! */
5859 if (i
.tm
.opcode_length
== 1)
5861 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
5865 switch (i
.tm
.opcode_length
)
5869 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
5879 /* Put out high byte first: can't use md_number_to_chars! */
5880 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
5881 *p
= i
.tm
.base_opcode
& 0xff;
5883 /* On SSE5, encode the OC1 bit in the DREX field if this
5884 encoding has multiple formats. */
5885 if (i
.tm
.opcode_modifier
.drex
5886 && i
.tm
.opcode_modifier
.drexv
5887 && DREX_OC1 (i
.tm
.extension_opcode
))
5888 *p
|= DREX_OC1_MASK
;
5891 /* Now the modrm byte and sib byte (if present). */
5892 if (i
.tm
.opcode_modifier
.modrm
)
5894 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
5897 /* If i.rm.regmem == ESP (4)
5898 && i.rm.mode != (Register mode)
5900 ==> need second modrm byte. */
5901 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
5903 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
5904 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
5906 | i
.sib
.scale
<< 6));
5909 /* Write the DREX byte if needed. */
5910 if (i
.tm
.opcode_modifier
.drex
|| i
.tm
.opcode_modifier
.drexc
)
5913 *p
= (((i
.drex
.reg
& 0xf) << 4) | (i
.drex
.rex
& 0x7));
5915 /* Encode the OC0 bit if this encoding has multiple
5917 if ((i
.tm
.opcode_modifier
.drex
5918 || i
.tm
.opcode_modifier
.drexv
)
5919 && DREX_OC0 (i
.tm
.extension_opcode
))
5920 *p
|= DREX_OC0_MASK
;
5923 if (i
.disp_operands
)
5924 output_disp (insn_start_frag
, insn_start_off
);
5927 output_imm (insn_start_frag
, insn_start_off
);
5933 pi ("" /*line*/, &i
);
5935 #endif /* DEBUG386 */
5938 /* Return the size of the displacement operand N. */
5941 disp_size (unsigned int n
)
5944 if (i
.types
[n
].bitfield
.disp64
)
5946 else if (i
.types
[n
].bitfield
.disp8
)
5948 else if (i
.types
[n
].bitfield
.disp16
)
5953 /* Return the size of the immediate operand N. */
5956 imm_size (unsigned int n
)
5959 if (i
.types
[n
].bitfield
.imm64
)
5961 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
5963 else if (i
.types
[n
].bitfield
.imm16
)
5969 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
5974 for (n
= 0; n
< i
.operands
; n
++)
5976 if (operand_type_check (i
.types
[n
], disp
))
5978 if (i
.op
[n
].disps
->X_op
== O_constant
)
5980 int size
= disp_size (n
);
5983 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
5985 p
= frag_more (size
);
5986 md_number_to_chars (p
, val
, size
);
5990 enum bfd_reloc_code_real reloc_type
;
5991 int size
= disp_size (n
);
5992 int sign
= i
.types
[n
].bitfield
.disp32s
;
5993 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
5995 /* We can't have 8 bit displacement here. */
5996 assert (!i
.types
[n
].bitfield
.disp8
);
5998 /* The PC relative address is computed relative
5999 to the instruction boundary, so in case immediate
6000 fields follows, we need to adjust the value. */
6001 if (pcrel
&& i
.imm_operands
)
6006 for (n1
= 0; n1
< i
.operands
; n1
++)
6007 if (operand_type_check (i
.types
[n1
], imm
))
6009 /* Only one immediate is allowed for PC
6010 relative address. */
6013 i
.op
[n
].disps
->X_add_number
-= sz
;
6015 /* We should find the immediate. */
6019 p
= frag_more (size
);
6020 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
6022 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
6023 && (((reloc_type
== BFD_RELOC_32
6024 || reloc_type
== BFD_RELOC_X86_64_32S
6025 || (reloc_type
== BFD_RELOC_64
6027 && (i
.op
[n
].disps
->X_op
== O_symbol
6028 || (i
.op
[n
].disps
->X_op
== O_add
6029 && ((symbol_get_value_expression
6030 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
6032 || reloc_type
== BFD_RELOC_32_PCREL
))
6036 if (insn_start_frag
== frag_now
)
6037 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
6042 add
= insn_start_frag
->fr_fix
- insn_start_off
;
6043 for (fr
= insn_start_frag
->fr_next
;
6044 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
6046 add
+= p
- frag_now
->fr_literal
;
6051 reloc_type
= BFD_RELOC_386_GOTPC
;
6052 i
.op
[n
].imms
->X_add_number
+= add
;
6054 else if (reloc_type
== BFD_RELOC_64
)
6055 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
6057 /* Don't do the adjustment for x86-64, as there
6058 the pcrel addressing is relative to the _next_
6059 insn, and that is taken care of in other code. */
6060 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
6062 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6063 i
.op
[n
].disps
, pcrel
, reloc_type
);
6070 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
6075 for (n
= 0; n
< i
.operands
; n
++)
6077 if (operand_type_check (i
.types
[n
], imm
))
6079 if (i
.op
[n
].imms
->X_op
== O_constant
)
6081 int size
= imm_size (n
);
6084 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
6086 p
= frag_more (size
);
6087 md_number_to_chars (p
, val
, size
);
6091 /* Not absolute_section.
6092 Need a 32-bit fixup (don't support 8bit
6093 non-absolute imms). Try to support other
6095 enum bfd_reloc_code_real reloc_type
;
6096 int size
= imm_size (n
);
6099 if (i
.types
[n
].bitfield
.imm32s
6100 && (i
.suffix
== QWORD_MNEM_SUFFIX
6101 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
6106 p
= frag_more (size
);
6107 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
6109 /* This is tough to explain. We end up with this one if we
6110 * have operands that look like
6111 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
6112 * obtain the absolute address of the GOT, and it is strongly
6113 * preferable from a performance point of view to avoid using
6114 * a runtime relocation for this. The actual sequence of
6115 * instructions often look something like:
6120 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
6122 * The call and pop essentially return the absolute address
6123 * of the label .L66 and store it in %ebx. The linker itself
6124 * will ultimately change the first operand of the addl so
6125 * that %ebx points to the GOT, but to keep things simple, the
6126 * .o file must have this operand set so that it generates not
6127 * the absolute address of .L66, but the absolute address of
6128 * itself. This allows the linker itself simply treat a GOTPC
6129 * relocation as asking for a pcrel offset to the GOT to be
6130 * added in, and the addend of the relocation is stored in the
6131 * operand field for the instruction itself.
6133 * Our job here is to fix the operand so that it would add
6134 * the correct offset so that %ebx would point to itself. The
6135 * thing that is tricky is that .-.L66 will point to the
6136 * beginning of the instruction, so we need to further modify
6137 * the operand so that it will point to itself. There are
6138 * other cases where you have something like:
6140 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
6142 * and here no correction would be required. Internally in
6143 * the assembler we treat operands of this form as not being
6144 * pcrel since the '.' is explicitly mentioned, and I wonder
6145 * whether it would simplify matters to do it this way. Who
6146 * knows. In earlier versions of the PIC patches, the
6147 * pcrel_adjust field was used to store the correction, but
6148 * since the expression is not pcrel, I felt it would be
6149 * confusing to do it this way. */
6151 if ((reloc_type
== BFD_RELOC_32
6152 || reloc_type
== BFD_RELOC_X86_64_32S
6153 || reloc_type
== BFD_RELOC_64
)
6155 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
6156 && (i
.op
[n
].imms
->X_op
== O_symbol
6157 || (i
.op
[n
].imms
->X_op
== O_add
6158 && ((symbol_get_value_expression
6159 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
6164 if (insn_start_frag
== frag_now
)
6165 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
6170 add
= insn_start_frag
->fr_fix
- insn_start_off
;
6171 for (fr
= insn_start_frag
->fr_next
;
6172 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
6174 add
+= p
- frag_now
->fr_literal
;
6178 reloc_type
= BFD_RELOC_386_GOTPC
;
6180 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
6182 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
6183 i
.op
[n
].imms
->X_add_number
+= add
;
6185 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6186 i
.op
[n
].imms
, 0, reloc_type
);
6192 /* x86_cons_fix_new is called via the expression parsing code when a
6193 reloc is needed. We use this hook to get the correct .got reloc. */
6194 static enum bfd_reloc_code_real got_reloc
= NO_RELOC
;
6195 static int cons_sign
= -1;
6198 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
6201 enum bfd_reloc_code_real r
= reloc (len
, 0, cons_sign
, got_reloc
);
6203 got_reloc
= NO_RELOC
;
6206 if (exp
->X_op
== O_secrel
)
6208 exp
->X_op
= O_symbol
;
6209 r
= BFD_RELOC_32_SECREL
;
6213 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
6216 #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
6217 # define lex_got(reloc, adjust, types) NULL
6219 /* Parse operands of the form
6220 <symbol>@GOTOFF+<nnn>
6221 and similar .plt or .got references.
6223 If we find one, set up the correct relocation in RELOC and copy the
6224 input string, minus the `@GOTOFF' into a malloc'd buffer for
6225 parsing by the calling routine. Return this buffer, and if ADJUST
6226 is non-null set it to the length of the string we removed from the
6227 input line. Otherwise return NULL. */
6229 lex_got (enum bfd_reloc_code_real
*reloc
,
6231 i386_operand_type
*types
)
6233 /* Some of the relocations depend on the size of what field is to
6234 be relocated. But in our callers i386_immediate and i386_displacement
6235 we don't yet know the operand size (this will be set by insn
6236 matching). Hence we record the word32 relocation here,
6237 and adjust the reloc according to the real size in reloc(). */
6238 static const struct {
6240 const enum bfd_reloc_code_real rel
[2];
6241 const i386_operand_type types64
;
6244 BFD_RELOC_X86_64_PLTOFF64
},
6245 OPERAND_TYPE_IMM64
},
6246 { "PLT", { BFD_RELOC_386_PLT32
,
6247 BFD_RELOC_X86_64_PLT32
},
6248 OPERAND_TYPE_IMM32_32S_DISP32
},
6250 BFD_RELOC_X86_64_GOTPLT64
},
6251 OPERAND_TYPE_IMM64_DISP64
},
6252 { "GOTOFF", { BFD_RELOC_386_GOTOFF
,
6253 BFD_RELOC_X86_64_GOTOFF64
},
6254 OPERAND_TYPE_IMM64_DISP64
},
6256 BFD_RELOC_X86_64_GOTPCREL
},
6257 OPERAND_TYPE_IMM32_32S_DISP32
},
6258 { "TLSGD", { BFD_RELOC_386_TLS_GD
,
6259 BFD_RELOC_X86_64_TLSGD
},
6260 OPERAND_TYPE_IMM32_32S_DISP32
},
6261 { "TLSLDM", { BFD_RELOC_386_TLS_LDM
,
6263 OPERAND_TYPE_NONE
},
6265 BFD_RELOC_X86_64_TLSLD
},
6266 OPERAND_TYPE_IMM32_32S_DISP32
},
6267 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32
,
6268 BFD_RELOC_X86_64_GOTTPOFF
},
6269 OPERAND_TYPE_IMM32_32S_DISP32
},
6270 { "TPOFF", { BFD_RELOC_386_TLS_LE_32
,
6271 BFD_RELOC_X86_64_TPOFF32
},
6272 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6273 { "NTPOFF", { BFD_RELOC_386_TLS_LE
,
6275 OPERAND_TYPE_NONE
},
6276 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32
,
6277 BFD_RELOC_X86_64_DTPOFF32
},
6279 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6280 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE
,
6282 OPERAND_TYPE_NONE
},
6283 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE
,
6285 OPERAND_TYPE_NONE
},
6286 { "GOT", { BFD_RELOC_386_GOT32
,
6287 BFD_RELOC_X86_64_GOT32
},
6288 OPERAND_TYPE_IMM32_32S_64_DISP32
},
6289 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC
,
6290 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
6291 OPERAND_TYPE_IMM32_32S_DISP32
},
6292 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL
,
6293 BFD_RELOC_X86_64_TLSDESC_CALL
},
6294 OPERAND_TYPE_IMM32_32S_DISP32
},
6302 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
6303 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
6306 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
6310 len
= strlen (gotrel
[j
].str
);
6311 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
6313 if (gotrel
[j
].rel
[object_64bit
] != 0)
6316 char *tmpbuf
, *past_reloc
;
6318 *reloc
= gotrel
[j
].rel
[object_64bit
];
6324 if (flag_code
!= CODE_64BIT
)
6326 types
->bitfield
.imm32
= 1;
6327 types
->bitfield
.disp32
= 1;
6330 *types
= gotrel
[j
].types64
;
6333 if (GOT_symbol
== NULL
)
6334 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
6336 /* The length of the first part of our input line. */
6337 first
= cp
- input_line_pointer
;
6339 /* The second part goes from after the reloc token until
6340 (and including) an end_of_line char or comma. */
6341 past_reloc
= cp
+ 1 + len
;
6343 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
6345 second
= cp
+ 1 - past_reloc
;
6347 /* Allocate and copy string. The trailing NUL shouldn't
6348 be necessary, but be safe. */
6349 tmpbuf
= xmalloc (first
+ second
+ 2);
6350 memcpy (tmpbuf
, input_line_pointer
, first
);
6351 if (second
!= 0 && *past_reloc
!= ' ')
6352 /* Replace the relocation token with ' ', so that
6353 errors like foo@GOTOFF1 will be detected. */
6354 tmpbuf
[first
++] = ' ';
6355 memcpy (tmpbuf
+ first
, past_reloc
, second
);
6356 tmpbuf
[first
+ second
] = '\0';
6360 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6361 gotrel
[j
].str
, 1 << (5 + object_64bit
));
6366 /* Might be a symbol version string. Don't as_bad here. */
6371 x86_cons (expressionS
*exp
, int size
)
6373 if (size
== 4 || (object_64bit
&& size
== 8))
6375 /* Handle @GOTOFF and the like in an expression. */
6377 char *gotfree_input_line
;
6380 save
= input_line_pointer
;
6381 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
6382 if (gotfree_input_line
)
6383 input_line_pointer
= gotfree_input_line
;
6387 if (gotfree_input_line
)
6389 /* expression () has merrily parsed up to the end of line,
6390 or a comma - in the wrong buffer. Transfer how far
6391 input_line_pointer has moved to the right buffer. */
6392 input_line_pointer
= (save
6393 + (input_line_pointer
- gotfree_input_line
)
6395 free (gotfree_input_line
);
6396 if (exp
->X_op
== O_constant
6397 || exp
->X_op
== O_absent
6398 || exp
->X_op
== O_illegal
6399 || exp
->X_op
== O_register
6400 || exp
->X_op
== O_big
)
6402 char c
= *input_line_pointer
;
6403 *input_line_pointer
= 0;
6404 as_bad (_("missing or invalid expression `%s'"), save
);
6405 *input_line_pointer
= c
;
6414 static void signed_cons (int size
)
6416 if (flag_code
== CODE_64BIT
)
6424 pe_directive_secrel (dummy
)
6425 int dummy ATTRIBUTE_UNUSED
;
6432 if (exp
.X_op
== O_symbol
)
6433 exp
.X_op
= O_secrel
;
6435 emit_expr (&exp
, 4);
6437 while (*input_line_pointer
++ == ',');
6439 input_line_pointer
--;
6440 demand_empty_rest_of_line ();
6445 i386_immediate (char *imm_start
)
6447 char *save_input_line_pointer
;
6448 char *gotfree_input_line
;
6451 i386_operand_type types
;
6453 operand_type_set (&types
, ~0);
6455 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
6457 as_bad (_("at most %d immediate operands are allowed"),
6458 MAX_IMMEDIATE_OPERANDS
);
6462 exp
= &im_expressions
[i
.imm_operands
++];
6463 i
.op
[this_operand
].imms
= exp
;
6465 if (is_space_char (*imm_start
))
6468 save_input_line_pointer
= input_line_pointer
;
6469 input_line_pointer
= imm_start
;
6471 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
6472 if (gotfree_input_line
)
6473 input_line_pointer
= gotfree_input_line
;
6475 exp_seg
= expression (exp
);
6478 if (*input_line_pointer
)
6479 as_bad (_("junk `%s' after expression"), input_line_pointer
);
6481 input_line_pointer
= save_input_line_pointer
;
6482 if (gotfree_input_line
)
6483 free (gotfree_input_line
);
6485 if (exp
->X_op
== O_absent
6486 || exp
->X_op
== O_illegal
6487 || exp
->X_op
== O_big
6488 || (gotfree_input_line
6489 && (exp
->X_op
== O_constant
6490 || exp
->X_op
== O_register
)))
6492 as_bad (_("missing or invalid immediate expression `%s'"),
6496 else if (exp
->X_op
== O_constant
)
6498 /* Size it properly later. */
6499 i
.types
[this_operand
].bitfield
.imm64
= 1;
6500 /* If BFD64, sign extend val. */
6501 if (!use_rela_relocations
6502 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
6504 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
6506 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6507 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
6508 && exp_seg
!= absolute_section
6509 && exp_seg
!= text_section
6510 && exp_seg
!= data_section
6511 && exp_seg
!= bss_section
6512 && exp_seg
!= undefined_section
6513 && !bfd_is_com_section (exp_seg
))
6515 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
6519 else if (!intel_syntax
&& exp
->X_op
== O_register
)
6521 as_bad (_("illegal immediate register operand %s"), imm_start
);
6526 /* This is an address. The size of the address will be
6527 determined later, depending on destination register,
6528 suffix, or the default for the section. */
6529 i
.types
[this_operand
].bitfield
.imm8
= 1;
6530 i
.types
[this_operand
].bitfield
.imm16
= 1;
6531 i
.types
[this_operand
].bitfield
.imm32
= 1;
6532 i
.types
[this_operand
].bitfield
.imm32s
= 1;
6533 i
.types
[this_operand
].bitfield
.imm64
= 1;
6534 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
6542 i386_scale (char *scale
)
6545 char *save
= input_line_pointer
;
6547 input_line_pointer
= scale
;
6548 val
= get_absolute_expression ();
6553 i
.log2_scale_factor
= 0;
6556 i
.log2_scale_factor
= 1;
6559 i
.log2_scale_factor
= 2;
6562 i
.log2_scale_factor
= 3;
6566 char sep
= *input_line_pointer
;
6568 *input_line_pointer
= '\0';
6569 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
6571 *input_line_pointer
= sep
;
6572 input_line_pointer
= save
;
6576 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
6578 as_warn (_("scale factor of %d without an index register"),
6579 1 << i
.log2_scale_factor
);
6580 i
.log2_scale_factor
= 0;
6582 scale
= input_line_pointer
;
6583 input_line_pointer
= save
;
6588 i386_displacement (char *disp_start
, char *disp_end
)
6592 char *save_input_line_pointer
;
6593 char *gotfree_input_line
;
6595 i386_operand_type bigdisp
, types
= anydisp
;
6598 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
6600 as_bad (_("at most %d displacement operands are allowed"),
6601 MAX_MEMORY_OPERANDS
);
6605 operand_type_set (&bigdisp
, 0);
6606 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
6607 || (!current_templates
->start
->opcode_modifier
.jump
6608 && !current_templates
->start
->opcode_modifier
.jumpdword
))
6610 bigdisp
.bitfield
.disp32
= 1;
6611 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
6612 if (flag_code
== CODE_64BIT
)
6616 bigdisp
.bitfield
.disp32s
= 1;
6617 bigdisp
.bitfield
.disp64
= 1;
6620 else if ((flag_code
== CODE_16BIT
) ^ override
)
6622 bigdisp
.bitfield
.disp32
= 0;
6623 bigdisp
.bitfield
.disp16
= 1;
6628 /* For PC-relative branches, the width of the displacement
6629 is dependent upon data size, not address size. */
6630 override
= (i
.prefix
[DATA_PREFIX
] != 0);
6631 if (flag_code
== CODE_64BIT
)
6633 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
6634 bigdisp
.bitfield
.disp16
= 1;
6637 bigdisp
.bitfield
.disp32
= 1;
6638 bigdisp
.bitfield
.disp32s
= 1;
6644 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
6646 : LONG_MNEM_SUFFIX
));
6647 bigdisp
.bitfield
.disp32
= 1;
6648 if ((flag_code
== CODE_16BIT
) ^ override
)
6650 bigdisp
.bitfield
.disp32
= 0;
6651 bigdisp
.bitfield
.disp16
= 1;
6655 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
6658 exp
= &disp_expressions
[i
.disp_operands
];
6659 i
.op
[this_operand
].disps
= exp
;
6661 save_input_line_pointer
= input_line_pointer
;
6662 input_line_pointer
= disp_start
;
6663 END_STRING_AND_SAVE (disp_end
);
6665 #ifndef GCC_ASM_O_HACK
6666 #define GCC_ASM_O_HACK 0
6669 END_STRING_AND_SAVE (disp_end
+ 1);
6670 if (i
.types
[this_operand
].bitfield
.baseIndex
6671 && displacement_string_end
[-1] == '+')
6673 /* This hack is to avoid a warning when using the "o"
6674 constraint within gcc asm statements.
6677 #define _set_tssldt_desc(n,addr,limit,type) \
6678 __asm__ __volatile__ ( \
6680 "movw %w1,2+%0\n\t" \
6682 "movb %b1,4+%0\n\t" \
6683 "movb %4,5+%0\n\t" \
6684 "movb $0,6+%0\n\t" \
6685 "movb %h1,7+%0\n\t" \
6687 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
6689 This works great except that the output assembler ends
6690 up looking a bit weird if it turns out that there is
6691 no offset. You end up producing code that looks like:
6704 So here we provide the missing zero. */
6706 *displacement_string_end
= '0';
6709 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
6710 if (gotfree_input_line
)
6711 input_line_pointer
= gotfree_input_line
;
6713 exp_seg
= expression (exp
);
6716 if (*input_line_pointer
)
6717 as_bad (_("junk `%s' after expression"), input_line_pointer
);
6719 RESTORE_END_STRING (disp_end
+ 1);
6721 input_line_pointer
= save_input_line_pointer
;
6722 if (gotfree_input_line
)
6723 free (gotfree_input_line
);
6726 /* We do this to make sure that the section symbol is in
6727 the symbol table. We will ultimately change the relocation
6728 to be relative to the beginning of the section. */
6729 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
6730 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
6731 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
6733 if (exp
->X_op
!= O_symbol
)
6736 if (S_IS_LOCAL (exp
->X_add_symbol
)
6737 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
6738 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
6739 exp
->X_op
= O_subtract
;
6740 exp
->X_op_symbol
= GOT_symbol
;
6741 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
6742 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
6743 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
6744 i
.reloc
[this_operand
] = BFD_RELOC_64
;
6746 i
.reloc
[this_operand
] = BFD_RELOC_32
;
6749 else if (exp
->X_op
== O_absent
6750 || exp
->X_op
== O_illegal
6751 || exp
->X_op
== O_big
6752 || (gotfree_input_line
6753 && (exp
->X_op
== O_constant
6754 || exp
->X_op
== O_register
)))
6757 as_bad (_("missing or invalid displacement expression `%s'"),
6762 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6763 else if (exp
->X_op
!= O_constant
6764 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
6765 && exp_seg
!= absolute_section
6766 && exp_seg
!= text_section
6767 && exp_seg
!= data_section
6768 && exp_seg
!= bss_section
6769 && exp_seg
!= undefined_section
6770 && !bfd_is_com_section (exp_seg
))
6772 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
6777 RESTORE_END_STRING (disp_end
);
6779 /* Check if this is a displacement only operand. */
6780 bigdisp
= i
.types
[this_operand
];
6781 bigdisp
.bitfield
.disp8
= 0;
6782 bigdisp
.bitfield
.disp16
= 0;
6783 bigdisp
.bitfield
.disp32
= 0;
6784 bigdisp
.bitfield
.disp32s
= 0;
6785 bigdisp
.bitfield
.disp64
= 0;
6786 if (operand_type_all_zero (&bigdisp
))
6787 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
6793 /* Make sure the memory operand we've been dealt is valid.
6794 Return 1 on success, 0 on a failure. */
6797 i386_index_check (const char *operand_string
)
6800 #if INFER_ADDR_PREFIX
6806 if (flag_code
== CODE_64BIT
)
6809 && ((i
.prefix
[ADDR_PREFIX
] == 0
6810 && !i
.base_reg
->reg_type
.bitfield
.reg64
)
6811 || (i
.prefix
[ADDR_PREFIX
]
6812 && !i
.base_reg
->reg_type
.bitfield
.reg32
))
6814 || i
.base_reg
->reg_num
!=
6815 (i
.prefix
[ADDR_PREFIX
] == 0 ? RegRip
: RegEip
)))
6817 && (!i
.index_reg
->reg_type
.bitfield
.baseindex
6818 || (i
.prefix
[ADDR_PREFIX
] == 0
6819 && i
.index_reg
->reg_num
!= RegRiz
6820 && !i
.index_reg
->reg_type
.bitfield
.reg64
6822 || (i
.prefix
[ADDR_PREFIX
]
6823 && i
.index_reg
->reg_num
!= RegEiz
6824 && !i
.index_reg
->reg_type
.bitfield
.reg32
))))
6829 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
6833 && (!i
.base_reg
->reg_type
.bitfield
.reg16
6834 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
6836 && (!i
.index_reg
->reg_type
.bitfield
.reg16
6837 || !i
.index_reg
->reg_type
.bitfield
.baseindex
6839 && i
.base_reg
->reg_num
< 6
6840 && i
.index_reg
->reg_num
>= 6
6841 && i
.log2_scale_factor
== 0))))
6848 && !i
.base_reg
->reg_type
.bitfield
.reg32
)
6850 && ((!i
.index_reg
->reg_type
.bitfield
.reg32
6851 && i
.index_reg
->reg_num
!= RegEiz
)
6852 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
6858 #if INFER_ADDR_PREFIX
6859 if (i
.prefix
[ADDR_PREFIX
] == 0)
6861 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
6863 /* Change the size of any displacement too. At most one of
6864 Disp16 or Disp32 is set.
6865 FIXME. There doesn't seem to be any real need for separate
6866 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
6867 Removing them would probably clean up the code quite a lot. */
6868 if (flag_code
!= CODE_64BIT
6869 && (i
.types
[this_operand
].bitfield
.disp16
6870 || i
.types
[this_operand
].bitfield
.disp32
))
6871 i
.types
[this_operand
]
6872 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
6877 as_bad (_("`%s' is not a valid base/index expression"),
6881 as_bad (_("`%s' is not a valid %s bit base/index expression"),
6883 flag_code_names
[flag_code
]);
6888 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
6892 i386_att_operand (char *operand_string
)
6896 char *op_string
= operand_string
;
6898 if (is_space_char (*op_string
))
6901 /* We check for an absolute prefix (differentiating,
6902 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
6903 if (*op_string
== ABSOLUTE_PREFIX
)
6906 if (is_space_char (*op_string
))
6908 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
6911 /* Check if operand is a register. */
6912 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
6914 i386_operand_type temp
;
6916 /* Check for a segment override by searching for ':' after a
6917 segment register. */
6919 if (is_space_char (*op_string
))
6921 if (*op_string
== ':'
6922 && (r
->reg_type
.bitfield
.sreg2
6923 || r
->reg_type
.bitfield
.sreg3
))
6928 i
.seg
[i
.mem_operands
] = &es
;
6931 i
.seg
[i
.mem_operands
] = &cs
;
6934 i
.seg
[i
.mem_operands
] = &ss
;
6937 i
.seg
[i
.mem_operands
] = &ds
;
6940 i
.seg
[i
.mem_operands
] = &fs
;
6943 i
.seg
[i
.mem_operands
] = &gs
;
6947 /* Skip the ':' and whitespace. */
6949 if (is_space_char (*op_string
))
6952 if (!is_digit_char (*op_string
)
6953 && !is_identifier_char (*op_string
)
6954 && *op_string
!= '('
6955 && *op_string
!= ABSOLUTE_PREFIX
)
6957 as_bad (_("bad memory operand `%s'"), op_string
);
6960 /* Handle case of %es:*foo. */
6961 if (*op_string
== ABSOLUTE_PREFIX
)
6964 if (is_space_char (*op_string
))
6966 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
6968 goto do_memory_reference
;
6972 as_bad (_("junk `%s' after register"), op_string
);
6976 temp
.bitfield
.baseindex
= 0;
6977 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
6979 i
.types
[this_operand
].bitfield
.unspecified
= 0;
6980 i
.op
[this_operand
].regs
= r
;
6983 else if (*op_string
== REGISTER_PREFIX
)
6985 as_bad (_("bad register name `%s'"), op_string
);
6988 else if (*op_string
== IMMEDIATE_PREFIX
)
6991 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
6993 as_bad (_("immediate operand illegal with absolute jump"));
6996 if (!i386_immediate (op_string
))
6999 else if (is_digit_char (*op_string
)
7000 || is_identifier_char (*op_string
)
7001 || *op_string
== '(')
7003 /* This is a memory reference of some sort. */
7006 /* Start and end of displacement string expression (if found). */
7007 char *displacement_string_start
;
7008 char *displacement_string_end
;
7010 do_memory_reference
:
7011 if ((i
.mem_operands
== 1
7012 && !current_templates
->start
->opcode_modifier
.isstring
)
7013 || i
.mem_operands
== 2)
7015 as_bad (_("too many memory references for `%s'"),
7016 current_templates
->start
->name
);
7020 /* Check for base index form. We detect the base index form by
7021 looking for an ')' at the end of the operand, searching
7022 for the '(' matching it, and finding a REGISTER_PREFIX or ','
7024 base_string
= op_string
+ strlen (op_string
);
7027 if (is_space_char (*base_string
))
7030 /* If we only have a displacement, set-up for it to be parsed later. */
7031 displacement_string_start
= op_string
;
7032 displacement_string_end
= base_string
+ 1;
7034 if (*base_string
== ')')
7037 unsigned int parens_balanced
= 1;
7038 /* We've already checked that the number of left & right ()'s are
7039 equal, so this loop will not be infinite. */
7043 if (*base_string
== ')')
7045 if (*base_string
== '(')
7048 while (parens_balanced
);
7050 temp_string
= base_string
;
7052 /* Skip past '(' and whitespace. */
7054 if (is_space_char (*base_string
))
7057 if (*base_string
== ','
7058 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
7061 displacement_string_end
= temp_string
;
7063 i
.types
[this_operand
].bitfield
.baseindex
= 1;
7067 base_string
= end_op
;
7068 if (is_space_char (*base_string
))
7072 /* There may be an index reg or scale factor here. */
7073 if (*base_string
== ',')
7076 if (is_space_char (*base_string
))
7079 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
7082 base_string
= end_op
;
7083 if (is_space_char (*base_string
))
7085 if (*base_string
== ',')
7088 if (is_space_char (*base_string
))
7091 else if (*base_string
!= ')')
7093 as_bad (_("expecting `,' or `)' "
7094 "after index register in `%s'"),
7099 else if (*base_string
== REGISTER_PREFIX
)
7101 as_bad (_("bad register name `%s'"), base_string
);
7105 /* Check for scale factor. */
7106 if (*base_string
!= ')')
7108 char *end_scale
= i386_scale (base_string
);
7113 base_string
= end_scale
;
7114 if (is_space_char (*base_string
))
7116 if (*base_string
!= ')')
7118 as_bad (_("expecting `)' "
7119 "after scale factor in `%s'"),
7124 else if (!i
.index_reg
)
7126 as_bad (_("expecting index register or scale factor "
7127 "after `,'; got '%c'"),
7132 else if (*base_string
!= ')')
7134 as_bad (_("expecting `,' or `)' "
7135 "after base register in `%s'"),
7140 else if (*base_string
== REGISTER_PREFIX
)
7142 as_bad (_("bad register name `%s'"), base_string
);
7147 /* If there's an expression beginning the operand, parse it,
7148 assuming displacement_string_start and
7149 displacement_string_end are meaningful. */
7150 if (displacement_string_start
!= displacement_string_end
)
7152 if (!i386_displacement (displacement_string_start
,
7153 displacement_string_end
))
7157 /* Special case for (%dx) while doing input/output op. */
7159 && operand_type_equal (&i
.base_reg
->reg_type
,
7160 ®16_inoutportreg
)
7162 && i
.log2_scale_factor
== 0
7163 && i
.seg
[i
.mem_operands
] == 0
7164 && !operand_type_check (i
.types
[this_operand
], disp
))
7166 i
.types
[this_operand
] = inoutportreg
;
7170 if (i386_index_check (operand_string
) == 0)
7172 i
.types
[this_operand
].bitfield
.mem
= 1;
7177 /* It's not a memory operand; argh! */
7178 as_bad (_("invalid char %s beginning operand %d `%s'"),
7179 output_invalid (*op_string
),
7184 return 1; /* Normal return. */
7187 /* md_estimate_size_before_relax()
7189 Called just before relax() for rs_machine_dependent frags. The x86
7190 assembler uses these frags to handle variable size jump
7193 Any symbol that is now undefined will not become defined.
7194 Return the correct fr_subtype in the frag.
7195 Return the initial "guess for variable size of frag" to caller.
7196 The guess is actually the growth beyond the fixed part. Whatever
7197 we do to grow the fixed or variable part contributes to our
7201 md_estimate_size_before_relax (fragP
, segment
)
7205 /* We've already got fragP->fr_subtype right; all we have to do is
7206 check for un-relaxable symbols. On an ELF system, we can't relax
7207 an externally visible symbol, because it may be overridden by a
7209 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
7210 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7212 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
7213 || S_IS_WEAK (fragP
->fr_symbol
)))
7217 /* Symbol is undefined in this segment, or we need to keep a
7218 reloc so that weak symbols can be overridden. */
7219 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
7220 enum bfd_reloc_code_real reloc_type
;
7221 unsigned char *opcode
;
7224 if (fragP
->fr_var
!= NO_RELOC
)
7225 reloc_type
= fragP
->fr_var
;
7227 reloc_type
= BFD_RELOC_16_PCREL
;
7229 reloc_type
= BFD_RELOC_32_PCREL
;
7231 old_fr_fix
= fragP
->fr_fix
;
7232 opcode
= (unsigned char *) fragP
->fr_opcode
;
7234 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
7237 /* Make jmp (0xeb) a (d)word displacement jump. */
7239 fragP
->fr_fix
+= size
;
7240 fix_new (fragP
, old_fr_fix
, size
,
7242 fragP
->fr_offset
, 1,
7248 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
7250 /* Negate the condition, and branch past an
7251 unconditional jump. */
7254 /* Insert an unconditional jump. */
7256 /* We added two extra opcode bytes, and have a two byte
7258 fragP
->fr_fix
+= 2 + 2;
7259 fix_new (fragP
, old_fr_fix
+ 2, 2,
7261 fragP
->fr_offset
, 1,
7268 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
7273 fixP
= fix_new (fragP
, old_fr_fix
, 1,
7275 fragP
->fr_offset
, 1,
7277 fixP
->fx_signed
= 1;
7281 /* This changes the byte-displacement jump 0x7N
7282 to the (d)word-displacement jump 0x0f,0x8N. */
7283 opcode
[1] = opcode
[0] + 0x10;
7284 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7285 /* We've added an opcode byte. */
7286 fragP
->fr_fix
+= 1 + size
;
7287 fix_new (fragP
, old_fr_fix
+ 1, size
,
7289 fragP
->fr_offset
, 1,
7294 BAD_CASE (fragP
->fr_subtype
);
7298 return fragP
->fr_fix
- old_fr_fix
;
7301 /* Guess size depending on current relax state. Initially the relax
7302 state will correspond to a short jump and we return 1, because
7303 the variable part of the frag (the branch offset) is one byte
7304 long. However, we can relax a section more than once and in that
7305 case we must either set fr_subtype back to the unrelaxed state,
7306 or return the value for the appropriate branch. */
7307 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
7310 /* Called after relax() is finished.
7312 In: Address of frag.
7313 fr_type == rs_machine_dependent.
7314 fr_subtype is what the address relaxed to.
7316 Out: Any fixSs and constants are set up.
7317 Caller will turn frag into a ".space 0". */
7320 md_convert_frag (abfd
, sec
, fragP
)
7321 bfd
*abfd ATTRIBUTE_UNUSED
;
7322 segT sec ATTRIBUTE_UNUSED
;
7325 unsigned char *opcode
;
7326 unsigned char *where_to_put_displacement
= NULL
;
7327 offsetT target_address
;
7328 offsetT opcode_address
;
7329 unsigned int extension
= 0;
7330 offsetT displacement_from_opcode_start
;
7332 opcode
= (unsigned char *) fragP
->fr_opcode
;
7334 /* Address we want to reach in file space. */
7335 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
7337 /* Address opcode resides at in file space. */
7338 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
7340 /* Displacement from opcode start to fill into instruction. */
7341 displacement_from_opcode_start
= target_address
- opcode_address
;
7343 if ((fragP
->fr_subtype
& BIG
) == 0)
7345 /* Don't have to change opcode. */
7346 extension
= 1; /* 1 opcode + 1 displacement */
7347 where_to_put_displacement
= &opcode
[1];
7351 if (no_cond_jump_promotion
7352 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
7353 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
7354 _("long jump required"));
7356 switch (fragP
->fr_subtype
)
7358 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
7359 extension
= 4; /* 1 opcode + 4 displacement */
7361 where_to_put_displacement
= &opcode
[1];
7364 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
7365 extension
= 2; /* 1 opcode + 2 displacement */
7367 where_to_put_displacement
= &opcode
[1];
7370 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
7371 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
7372 extension
= 5; /* 2 opcode + 4 displacement */
7373 opcode
[1] = opcode
[0] + 0x10;
7374 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7375 where_to_put_displacement
= &opcode
[2];
7378 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
7379 extension
= 3; /* 2 opcode + 2 displacement */
7380 opcode
[1] = opcode
[0] + 0x10;
7381 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7382 where_to_put_displacement
= &opcode
[2];
7385 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
7390 where_to_put_displacement
= &opcode
[3];
7394 BAD_CASE (fragP
->fr_subtype
);
7399 /* If size if less then four we are sure that the operand fits,
7400 but if it's 4, then it could be that the displacement is larger
7402 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
7404 && ((addressT
) (displacement_from_opcode_start
- extension
7405 + ((addressT
) 1 << 31))
7406 > (((addressT
) 2 << 31) - 1)))
7408 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
7409 _("jump target out of range"));
7410 /* Make us emit 0. */
7411 displacement_from_opcode_start
= extension
;
7413 /* Now put displacement after opcode. */
7414 md_number_to_chars ((char *) where_to_put_displacement
,
7415 (valueT
) (displacement_from_opcode_start
- extension
),
7416 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
7417 fragP
->fr_fix
+= extension
;
7420 /* Apply a fixup (fixS) to segment data, once it has been determined
7421 by our caller that we have all the info we need to fix it up.
7423 On the 386, immediates, displacements, and data pointers are all in
7424 the same (little-endian) format, so we don't need to care about which
7428 md_apply_fix (fixP
, valP
, seg
)
7429 /* The fix we're to put in. */
7431 /* Pointer to the value of the bits. */
7433 /* Segment fix is from. */
7434 segT seg ATTRIBUTE_UNUSED
;
7436 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
7437 valueT value
= *valP
;
7439 #if !defined (TE_Mach)
7442 switch (fixP
->fx_r_type
)
7448 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
7451 case BFD_RELOC_X86_64_32S
:
7452 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
7455 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
7458 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
7463 if (fixP
->fx_addsy
!= NULL
7464 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
7465 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
7466 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
7467 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
7468 && !use_rela_relocations
)
7470 /* This is a hack. There should be a better way to handle this.
7471 This covers for the fact that bfd_install_relocation will
7472 subtract the current location (for partial_inplace, PC relative
7473 relocations); see more below. */
7477 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
7480 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7482 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7485 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
7488 || (symbol_section_p (fixP
->fx_addsy
)
7489 && sym_seg
!= absolute_section
))
7490 && !generic_force_reloc (fixP
))
7492 /* Yes, we add the values in twice. This is because
7493 bfd_install_relocation subtracts them out again. I think
7494 bfd_install_relocation is broken, but I don't dare change
7496 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7500 #if defined (OBJ_COFF) && defined (TE_PE)
7501 /* For some reason, the PE format does not store a
7502 section address offset for a PC relative symbol. */
7503 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
7504 || S_IS_WEAK (fixP
->fx_addsy
))
7505 value
+= md_pcrel_from (fixP
);
7509 /* Fix a few things - the dynamic linker expects certain values here,
7510 and we must not disappoint it. */
7511 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7512 if (IS_ELF
&& fixP
->fx_addsy
)
7513 switch (fixP
->fx_r_type
)
7515 case BFD_RELOC_386_PLT32
:
7516 case BFD_RELOC_X86_64_PLT32
:
7517 /* Make the jump instruction point to the address of the operand. At
7518 runtime we merely add the offset to the actual PLT entry. */
7522 case BFD_RELOC_386_TLS_GD
:
7523 case BFD_RELOC_386_TLS_LDM
:
7524 case BFD_RELOC_386_TLS_IE_32
:
7525 case BFD_RELOC_386_TLS_IE
:
7526 case BFD_RELOC_386_TLS_GOTIE
:
7527 case BFD_RELOC_386_TLS_GOTDESC
:
7528 case BFD_RELOC_X86_64_TLSGD
:
7529 case BFD_RELOC_X86_64_TLSLD
:
7530 case BFD_RELOC_X86_64_GOTTPOFF
:
7531 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
7532 value
= 0; /* Fully resolved at runtime. No addend. */
7534 case BFD_RELOC_386_TLS_LE
:
7535 case BFD_RELOC_386_TLS_LDO_32
:
7536 case BFD_RELOC_386_TLS_LE_32
:
7537 case BFD_RELOC_X86_64_DTPOFF32
:
7538 case BFD_RELOC_X86_64_DTPOFF64
:
7539 case BFD_RELOC_X86_64_TPOFF32
:
7540 case BFD_RELOC_X86_64_TPOFF64
:
7541 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7544 case BFD_RELOC_386_TLS_DESC_CALL
:
7545 case BFD_RELOC_X86_64_TLSDESC_CALL
:
7546 value
= 0; /* Fully resolved at runtime. No addend. */
7547 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7551 case BFD_RELOC_386_GOT32
:
7552 case BFD_RELOC_X86_64_GOT32
:
7553 value
= 0; /* Fully resolved at runtime. No addend. */
7556 case BFD_RELOC_VTABLE_INHERIT
:
7557 case BFD_RELOC_VTABLE_ENTRY
:
7564 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
7566 #endif /* !defined (TE_Mach) */
7568 /* Are we finished with this relocation now? */
7569 if (fixP
->fx_addsy
== NULL
)
7571 else if (use_rela_relocations
)
7573 fixP
->fx_no_overflow
= 1;
7574 /* Remember value for tc_gen_reloc. */
7575 fixP
->fx_addnumber
= value
;
7579 md_number_to_chars (p
, value
, fixP
->fx_size
);
7583 md_atof (int type
, char *litP
, int *sizeP
)
7585 /* This outputs the LITTLENUMs in REVERSE order;
7586 in accord with the bigendian 386. */
7587 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
7590 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
7593 output_invalid (int c
)
7596 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
7599 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
7600 "(0x%x)", (unsigned char) c
);
7601 return output_invalid_buf
;
7604 /* REG_STRING starts *before* REGISTER_PREFIX. */
7606 static const reg_entry
*
7607 parse_real_register (char *reg_string
, char **end_op
)
7609 char *s
= reg_string
;
7611 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
7614 /* Skip possible REGISTER_PREFIX and possible whitespace. */
7615 if (*s
== REGISTER_PREFIX
)
7618 if (is_space_char (*s
))
7622 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
7624 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
7625 return (const reg_entry
*) NULL
;
7629 /* For naked regs, make sure that we are not dealing with an identifier.
7630 This prevents confusing an identifier like `eax_var' with register
7632 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
7633 return (const reg_entry
*) NULL
;
7637 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
7639 /* Handle floating point regs, allowing spaces in the (i) part. */
7640 if (r
== i386_regtab
/* %st is first entry of table */)
7642 if (is_space_char (*s
))
7647 if (is_space_char (*s
))
7649 if (*s
>= '0' && *s
<= '7')
7653 if (is_space_char (*s
))
7658 r
= hash_find (reg_hash
, "st(0)");
7663 /* We have "%st(" then garbage. */
7664 return (const reg_entry
*) NULL
;
7668 if (r
== NULL
|| allow_pseudo_reg
)
7671 if (operand_type_all_zero (&r
->reg_type
))
7672 return (const reg_entry
*) NULL
;
7674 if ((r
->reg_type
.bitfield
.reg32
7675 || r
->reg_type
.bitfield
.sreg3
7676 || r
->reg_type
.bitfield
.control
7677 || r
->reg_type
.bitfield
.debug
7678 || r
->reg_type
.bitfield
.test
)
7679 && !cpu_arch_flags
.bitfield
.cpui386
)
7680 return (const reg_entry
*) NULL
;
7682 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
7683 return (const reg_entry
*) NULL
;
7685 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpusse
)
7686 return (const reg_entry
*) NULL
;
7688 /* Don't allow fake index register unless allow_index_reg isn't 0. */
7689 if (!allow_index_reg
7690 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
7691 return (const reg_entry
*) NULL
;
7693 if (((r
->reg_flags
& (RegRex64
| RegRex
))
7694 || r
->reg_type
.bitfield
.reg64
)
7695 && (!cpu_arch_flags
.bitfield
.cpulm
7696 || !operand_type_equal (&r
->reg_type
, &control
))
7697 && flag_code
!= CODE_64BIT
)
7698 return (const reg_entry
*) NULL
;
7700 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
7701 return (const reg_entry
*) NULL
;
7706 /* REG_STRING starts *before* REGISTER_PREFIX. */
7708 static const reg_entry
*
7709 parse_register (char *reg_string
, char **end_op
)
7713 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
7714 r
= parse_real_register (reg_string
, end_op
);
7719 char *save
= input_line_pointer
;
7723 input_line_pointer
= reg_string
;
7724 c
= get_symbol_end ();
7725 symbolP
= symbol_find (reg_string
);
7726 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
7728 const expressionS
*e
= symbol_get_value_expression (symbolP
);
7730 know (e
->X_op
== O_register
);
7731 know (e
->X_add_number
>= 0
7732 && (valueT
) e
->X_add_number
< i386_regtab_size
);
7733 r
= i386_regtab
+ e
->X_add_number
;
7734 *end_op
= input_line_pointer
;
7736 *input_line_pointer
= c
;
7737 input_line_pointer
= save
;
7743 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
7746 char *end
= input_line_pointer
;
7749 r
= parse_register (name
, &input_line_pointer
);
7750 if (r
&& end
<= input_line_pointer
)
7752 *nextcharP
= *input_line_pointer
;
7753 *input_line_pointer
= 0;
7754 e
->X_op
= O_register
;
7755 e
->X_add_number
= r
- i386_regtab
;
7758 input_line_pointer
= end
;
7764 md_operand (expressionS
*e
)
7766 if (*input_line_pointer
== REGISTER_PREFIX
)
7769 const reg_entry
*r
= parse_real_register (input_line_pointer
, &end
);
7773 e
->X_op
= O_register
;
7774 e
->X_add_number
= r
- i386_regtab
;
7775 input_line_pointer
= end
;
7781 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7782 const char *md_shortopts
= "kVQ:sqn";
7784 const char *md_shortopts
= "qn";
7787 #define OPTION_32 (OPTION_MD_BASE + 0)
7788 #define OPTION_64 (OPTION_MD_BASE + 1)
7789 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
7790 #define OPTION_MARCH (OPTION_MD_BASE + 3)
7791 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
7792 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
7793 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
7794 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
7795 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
7796 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
7797 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
7799 struct option md_longopts
[] =
7801 {"32", no_argument
, NULL
, OPTION_32
},
7802 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
7803 {"64", no_argument
, NULL
, OPTION_64
},
7805 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
7806 {"march", required_argument
, NULL
, OPTION_MARCH
},
7807 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
7808 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
7809 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
7810 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
7811 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
7812 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
7813 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
7814 {NULL
, no_argument
, NULL
, 0}
7816 size_t md_longopts_size
= sizeof (md_longopts
);
7819 md_parse_option (int c
, char *arg
)
7827 optimize_align_code
= 0;
7834 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7835 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7836 should be emitted or not. FIXME: Not implemented. */
7840 /* -V: SVR4 argument to print version ID. */
7842 print_version_id ();
7845 /* -k: Ignore for FreeBSD compatibility. */
7850 /* -s: On i386 Solaris, this tells the native assembler to use
7851 .stab instead of .stab.excl. We always use .stab anyhow. */
7854 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
7857 const char **list
, **l
;
7859 list
= bfd_target_list ();
7860 for (l
= list
; *l
!= NULL
; l
++)
7861 if (CONST_STRNEQ (*l
, "elf64-x86-64")
7862 || strcmp (*l
, "coff-x86-64") == 0
7863 || strcmp (*l
, "pe-x86-64") == 0
7864 || strcmp (*l
, "pei-x86-64") == 0)
7866 default_arch
= "x86_64";
7870 as_fatal (_("No compiled in support for x86_64"));
7877 default_arch
= "i386";
7881 #ifdef SVR4_COMMENT_CHARS
7886 n
= (char *) xmalloc (strlen (i386_comment_chars
) + 1);
7888 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
7892 i386_comment_chars
= n
;
7898 arch
= xstrdup (arg
);
7902 as_fatal (_("Invalid -march= option: `%s'"), arg
);
7903 next
= strchr (arch
, '+');
7906 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
7908 if (strcmp (arch
, cpu_arch
[i
].name
) == 0)
7911 cpu_arch_name
= cpu_arch
[i
].name
;
7912 cpu_sub_arch_name
= NULL
;
7913 cpu_arch_flags
= cpu_arch
[i
].flags
;
7914 cpu_arch_isa
= cpu_arch
[i
].type
;
7915 cpu_arch_isa_flags
= cpu_arch
[i
].flags
;
7916 if (!cpu_arch_tune_set
)
7918 cpu_arch_tune
= cpu_arch_isa
;
7919 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
7923 else if (*cpu_arch
[i
].name
== '.'
7924 && strcmp (arch
, cpu_arch
[i
].name
+ 1) == 0)
7926 /* ISA entension. */
7927 i386_cpu_flags flags
;
7928 flags
= cpu_flags_or (cpu_arch_flags
,
7930 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
7932 if (cpu_sub_arch_name
)
7934 char *name
= cpu_sub_arch_name
;
7935 cpu_sub_arch_name
= concat (name
,
7937 (const char *) NULL
);
7941 cpu_sub_arch_name
= xstrdup (cpu_arch
[i
].name
);
7942 cpu_arch_flags
= flags
;
7948 if (i
>= ARRAY_SIZE (cpu_arch
))
7949 as_fatal (_("Invalid -march= option: `%s'"), arg
);
7953 while (next
!= NULL
);
7958 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
7959 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
7961 if (strcmp (arg
, cpu_arch
[i
].name
) == 0)
7963 cpu_arch_tune_set
= 1;
7964 cpu_arch_tune
= cpu_arch
[i
].type
;
7965 cpu_arch_tune_flags
= cpu_arch
[i
].flags
;
7969 if (i
>= ARRAY_SIZE (cpu_arch
))
7970 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
7973 case OPTION_MMNEMONIC
:
7974 if (strcasecmp (arg
, "att") == 0)
7976 else if (strcasecmp (arg
, "intel") == 0)
7979 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg
);
7982 case OPTION_MSYNTAX
:
7983 if (strcasecmp (arg
, "att") == 0)
7985 else if (strcasecmp (arg
, "intel") == 0)
7988 as_fatal (_("Invalid -msyntax= option: `%s'"), arg
);
7991 case OPTION_MINDEX_REG
:
7992 allow_index_reg
= 1;
7995 case OPTION_MNAKED_REG
:
7996 allow_naked_reg
= 1;
7999 case OPTION_MOLD_GCC
:
8003 case OPTION_MSSE2AVX
:
8014 md_show_usage (stream
)
8017 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8018 fprintf (stream
, _("\
8020 -V print assembler version number\n\
8023 fprintf (stream
, _("\
8024 -n Do not optimize code alignment\n\
8025 -q quieten some warnings\n"));
8026 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8027 fprintf (stream
, _("\
8030 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
8031 fprintf (stream
, _("\
8032 --32/--64 generate 32bit/64bit code\n"));
8034 #ifdef SVR4_COMMENT_CHARS
8035 fprintf (stream
, _("\
8036 --divide do not treat `/' as a comment character\n"));
8038 fprintf (stream
, _("\
8039 --divide ignored\n"));
8041 fprintf (stream
, _("\
8042 -march=CPU[,+EXTENSION...]\n\
8043 generate code for CPU and EXTENSION, CPU is one of:\n\
8044 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
8045 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
8046 core, core2, k6, k6_2, athlon, k8, amdfam10,\n\
8047 generic32, generic64\n\
8048 EXTENSION is combination of:\n\
8049 mmx, sse, sse2, sse3, ssse3, sse4.1, sse4.2, sse4,\n\
8050 avx, vmx, smx, xsave, aes, pclmul, fma, 3dnow,\n\
8051 3dnowa, sse4a, sse5, svme, abm, padlock\n"));
8052 fprintf (stream
, _("\
8053 -mtune=CPU optimize for CPU, CPU is one of:\n\
8054 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
8055 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
8056 core, core2, k6, k6_2, athlon, k8, amdfam10,\n\
8057 generic32, generic64\n"));
8058 fprintf (stream
, _("\
8059 -msse2avx encode SSE instructions with VEX prefix\n"));
8060 fprintf (stream
, _("\
8061 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
8062 fprintf (stream
, _("\
8063 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
8064 fprintf (stream
, _("\
8065 -mindex-reg support pseudo index registers\n"));
8066 fprintf (stream
, _("\
8067 -mnaked-reg don't require `%%' prefix for registers\n"));
8068 fprintf (stream
, _("\
8069 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
8072 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
8073 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (TE_PEP))
8075 /* Pick the target format to use. */
8078 i386_target_format (void)
8080 if (!strcmp (default_arch
, "x86_64"))
8082 set_code_flag (CODE_64BIT
);
8083 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
8085 cpu_arch_isa_flags
.bitfield
.cpui186
= 1;
8086 cpu_arch_isa_flags
.bitfield
.cpui286
= 1;
8087 cpu_arch_isa_flags
.bitfield
.cpui386
= 1;
8088 cpu_arch_isa_flags
.bitfield
.cpui486
= 1;
8089 cpu_arch_isa_flags
.bitfield
.cpui586
= 1;
8090 cpu_arch_isa_flags
.bitfield
.cpui686
= 1;
8091 cpu_arch_isa_flags
.bitfield
.cpup4
= 1;
8092 cpu_arch_isa_flags
.bitfield
.cpummx
= 1;
8093 cpu_arch_isa_flags
.bitfield
.cpusse
= 1;
8094 cpu_arch_isa_flags
.bitfield
.cpusse2
= 1;
8096 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
8098 cpu_arch_tune_flags
.bitfield
.cpui186
= 1;
8099 cpu_arch_tune_flags
.bitfield
.cpui286
= 1;
8100 cpu_arch_tune_flags
.bitfield
.cpui386
= 1;
8101 cpu_arch_tune_flags
.bitfield
.cpui486
= 1;
8102 cpu_arch_tune_flags
.bitfield
.cpui586
= 1;
8103 cpu_arch_tune_flags
.bitfield
.cpui686
= 1;
8104 cpu_arch_tune_flags
.bitfield
.cpup4
= 1;
8105 cpu_arch_tune_flags
.bitfield
.cpummx
= 1;
8106 cpu_arch_tune_flags
.bitfield
.cpusse
= 1;
8107 cpu_arch_tune_flags
.bitfield
.cpusse2
= 1;
8110 else if (!strcmp (default_arch
, "i386"))
8112 set_code_flag (CODE_32BIT
);
8113 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
8115 cpu_arch_isa_flags
.bitfield
.cpui186
= 1;
8116 cpu_arch_isa_flags
.bitfield
.cpui286
= 1;
8117 cpu_arch_isa_flags
.bitfield
.cpui386
= 1;
8119 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
8121 cpu_arch_tune_flags
.bitfield
.cpui186
= 1;
8122 cpu_arch_tune_flags
.bitfield
.cpui286
= 1;
8123 cpu_arch_tune_flags
.bitfield
.cpui386
= 1;
8127 as_fatal (_("Unknown architecture"));
8128 switch (OUTPUT_FLAVOR
)
8131 case bfd_target_coff_flavour
:
8132 return flag_code
== CODE_64BIT
? COFF_TARGET_FORMAT
: "coff-i386";
8135 #ifdef OBJ_MAYBE_AOUT
8136 case bfd_target_aout_flavour
:
8137 return AOUT_TARGET_FORMAT
;
8139 #ifdef OBJ_MAYBE_COFF
8140 case bfd_target_coff_flavour
:
8143 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8144 case bfd_target_elf_flavour
:
8146 if (flag_code
== CODE_64BIT
)
8149 use_rela_relocations
= 1;
8151 return flag_code
== CODE_64BIT
? ELF_TARGET_FORMAT64
: ELF_TARGET_FORMAT
;
8160 #endif /* OBJ_MAYBE_ more than one */
8162 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
8164 i386_elf_emit_arch_note (void)
8166 if (IS_ELF
&& cpu_arch_name
!= NULL
)
8169 asection
*seg
= now_seg
;
8170 subsegT subseg
= now_subseg
;
8171 Elf_Internal_Note i_note
;
8172 Elf_External_Note e_note
;
8173 asection
*note_secp
;
8176 /* Create the .note section. */
8177 note_secp
= subseg_new (".note", 0);
8178 bfd_set_section_flags (stdoutput
,
8180 SEC_HAS_CONTENTS
| SEC_READONLY
);
8182 /* Process the arch string. */
8183 len
= strlen (cpu_arch_name
);
8185 i_note
.namesz
= len
+ 1;
8187 i_note
.type
= NT_ARCH
;
8188 p
= frag_more (sizeof (e_note
.namesz
));
8189 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
8190 p
= frag_more (sizeof (e_note
.descsz
));
8191 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
8192 p
= frag_more (sizeof (e_note
.type
));
8193 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
8194 p
= frag_more (len
+ 1);
8195 strcpy (p
, cpu_arch_name
);
8197 frag_align (2, 0, 0);
8199 subseg_set (seg
, subseg
);
8205 md_undefined_symbol (name
)
8208 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
8209 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
8210 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
8211 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
8215 if (symbol_find (name
))
8216 as_bad (_("GOT already in symbol table"));
8217 GOT_symbol
= symbol_new (name
, undefined_section
,
8218 (valueT
) 0, &zero_address_frag
);
8225 /* Round up a section size to the appropriate boundary. */
8228 md_section_align (segment
, size
)
8229 segT segment ATTRIBUTE_UNUSED
;
8232 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8233 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
8235 /* For a.out, force the section size to be aligned. If we don't do
8236 this, BFD will align it for us, but it will not write out the
8237 final bytes of the section. This may be a bug in BFD, but it is
8238 easier to fix it here since that is how the other a.out targets
8242 align
= bfd_get_section_alignment (stdoutput
, segment
);
8243 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
8250 /* On the i386, PC-relative offsets are relative to the start of the
8251 next instruction. That is, the address of the offset, plus its
8252 size, since the offset is always the last part of the insn. */
8255 md_pcrel_from (fixS
*fixP
)
8257 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
8263 s_bss (int ignore ATTRIBUTE_UNUSED
)
8267 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8269 obj_elf_section_change_hook ();
8271 temp
= get_absolute_expression ();
8272 subseg_set (bss_section
, (subsegT
) temp
);
8273 demand_empty_rest_of_line ();
8279 i386_validate_fix (fixS
*fixp
)
8281 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
8283 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
8287 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
8292 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
8294 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
8301 tc_gen_reloc (section
, fixp
)
8302 asection
*section ATTRIBUTE_UNUSED
;
8306 bfd_reloc_code_real_type code
;
8308 switch (fixp
->fx_r_type
)
8310 case BFD_RELOC_X86_64_PLT32
:
8311 case BFD_RELOC_X86_64_GOT32
:
8312 case BFD_RELOC_X86_64_GOTPCREL
:
8313 case BFD_RELOC_386_PLT32
:
8314 case BFD_RELOC_386_GOT32
:
8315 case BFD_RELOC_386_GOTOFF
:
8316 case BFD_RELOC_386_GOTPC
:
8317 case BFD_RELOC_386_TLS_GD
:
8318 case BFD_RELOC_386_TLS_LDM
:
8319 case BFD_RELOC_386_TLS_LDO_32
:
8320 case BFD_RELOC_386_TLS_IE_32
:
8321 case BFD_RELOC_386_TLS_IE
:
8322 case BFD_RELOC_386_TLS_GOTIE
:
8323 case BFD_RELOC_386_TLS_LE_32
:
8324 case BFD_RELOC_386_TLS_LE
:
8325 case BFD_RELOC_386_TLS_GOTDESC
:
8326 case BFD_RELOC_386_TLS_DESC_CALL
:
8327 case BFD_RELOC_X86_64_TLSGD
:
8328 case BFD_RELOC_X86_64_TLSLD
:
8329 case BFD_RELOC_X86_64_DTPOFF32
:
8330 case BFD_RELOC_X86_64_DTPOFF64
:
8331 case BFD_RELOC_X86_64_GOTTPOFF
:
8332 case BFD_RELOC_X86_64_TPOFF32
:
8333 case BFD_RELOC_X86_64_TPOFF64
:
8334 case BFD_RELOC_X86_64_GOTOFF64
:
8335 case BFD_RELOC_X86_64_GOTPC32
:
8336 case BFD_RELOC_X86_64_GOT64
:
8337 case BFD_RELOC_X86_64_GOTPCREL64
:
8338 case BFD_RELOC_X86_64_GOTPC64
:
8339 case BFD_RELOC_X86_64_GOTPLT64
:
8340 case BFD_RELOC_X86_64_PLTOFF64
:
8341 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
8342 case BFD_RELOC_X86_64_TLSDESC_CALL
:
8344 case BFD_RELOC_VTABLE_ENTRY
:
8345 case BFD_RELOC_VTABLE_INHERIT
:
8347 case BFD_RELOC_32_SECREL
:
8349 code
= fixp
->fx_r_type
;
8351 case BFD_RELOC_X86_64_32S
:
8352 if (!fixp
->fx_pcrel
)
8354 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
8355 code
= fixp
->fx_r_type
;
8361 switch (fixp
->fx_size
)
8364 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8365 _("can not do %d byte pc-relative relocation"),
8367 code
= BFD_RELOC_32_PCREL
;
8369 case 1: code
= BFD_RELOC_8_PCREL
; break;
8370 case 2: code
= BFD_RELOC_16_PCREL
; break;
8371 case 4: code
= BFD_RELOC_32_PCREL
; break;
8373 case 8: code
= BFD_RELOC_64_PCREL
; break;
8379 switch (fixp
->fx_size
)
8382 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8383 _("can not do %d byte relocation"),
8385 code
= BFD_RELOC_32
;
8387 case 1: code
= BFD_RELOC_8
; break;
8388 case 2: code
= BFD_RELOC_16
; break;
8389 case 4: code
= BFD_RELOC_32
; break;
8391 case 8: code
= BFD_RELOC_64
; break;
8398 if ((code
== BFD_RELOC_32
8399 || code
== BFD_RELOC_32_PCREL
8400 || code
== BFD_RELOC_X86_64_32S
)
8402 && fixp
->fx_addsy
== GOT_symbol
)
8405 code
= BFD_RELOC_386_GOTPC
;
8407 code
= BFD_RELOC_X86_64_GOTPC32
;
8409 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
8411 && fixp
->fx_addsy
== GOT_symbol
)
8413 code
= BFD_RELOC_X86_64_GOTPC64
;
8416 rel
= (arelent
*) xmalloc (sizeof (arelent
));
8417 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
8418 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
8420 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
8422 if (!use_rela_relocations
)
8424 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
8425 vtable entry to be used in the relocation's section offset. */
8426 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
8427 rel
->address
= fixp
->fx_offset
;
8431 /* Use the rela in 64bit mode. */
8434 if (!fixp
->fx_pcrel
)
8435 rel
->addend
= fixp
->fx_offset
;
8439 case BFD_RELOC_X86_64_PLT32
:
8440 case BFD_RELOC_X86_64_GOT32
:
8441 case BFD_RELOC_X86_64_GOTPCREL
:
8442 case BFD_RELOC_X86_64_TLSGD
:
8443 case BFD_RELOC_X86_64_TLSLD
:
8444 case BFD_RELOC_X86_64_GOTTPOFF
:
8445 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
8446 case BFD_RELOC_X86_64_TLSDESC_CALL
:
8447 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
8450 rel
->addend
= (section
->vma
8452 + fixp
->fx_addnumber
8453 + md_pcrel_from (fixp
));
8458 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
8459 if (rel
->howto
== NULL
)
8461 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8462 _("cannot represent relocation type %s"),
8463 bfd_get_reloc_code_name (code
));
8464 /* Set howto to a garbage value so that we can keep going. */
8465 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
8466 assert (rel
->howto
!= NULL
);
8473 /* Parse operands using Intel syntax. This implements a recursive descent
8474 parser based on the BNF grammar published in Appendix B of the MASM 6.1
8477 FIXME: We do not recognize the full operand grammar defined in the MASM
8478 documentation. In particular, all the structure/union and
8479 high-level macro operands are missing.
8481 Uppercase words are terminals, lower case words are non-terminals.
8482 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
8483 bars '|' denote choices. Most grammar productions are implemented in
8484 functions called 'intel_<production>'.
8486 Initial production is 'expr'.
8492 binOp & | AND | \| | OR | ^ | XOR
8494 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
8496 constant digits [[ radixOverride ]]
8498 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD | YMMWORD
8536 => expr expr cmpOp e04
8539 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
8540 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
8542 hexdigit a | b | c | d | e | f
8543 | A | B | C | D | E | F
8549 mulOp * | / | % | MOD | << | SHL | >> | SHR
8553 register specialRegister
8557 segmentRegister CS | DS | ES | FS | GS | SS
8559 specialRegister CR0 | CR2 | CR3 | CR4
8560 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
8561 | TR3 | TR4 | TR5 | TR6 | TR7
8563 We simplify the grammar in obvious places (e.g., register parsing is
8564 done by calling parse_register) and eliminate immediate left recursion
8565 to implement a recursive-descent parser.
8569 expr' cmpOp e04 expr'
8621 /* Parsing structure for the intel syntax parser. Used to implement the
8622 semantic actions for the operand grammar. */
8623 struct intel_parser_s
8625 char *op_string
; /* The string being parsed. */
8626 int got_a_float
; /* Whether the operand is a float. */
8627 int op_modifier
; /* Operand modifier. */
8628 int is_mem
; /* 1 if operand is memory reference. */
8629 int in_offset
; /* >=1 if parsing operand of offset. */
8630 int in_bracket
; /* >=1 if parsing operand in brackets. */
8631 const reg_entry
*reg
; /* Last register reference found. */
8632 char *disp
; /* Displacement string being built. */
8633 char *next_operand
; /* Resume point when splitting operands. */
8636 static struct intel_parser_s intel_parser
;
8638 /* Token structure for parsing intel syntax. */
8641 int code
; /* Token code. */
8642 const reg_entry
*reg
; /* Register entry for register tokens. */
8643 char *str
; /* String representation. */
8646 static struct intel_token cur_token
, prev_token
;
8648 /* Token codes for the intel parser. Since T_SHORT is already used
8649 by COFF, undefine it first to prevent a warning. */
8667 #define T_YMMWORD 16
8669 /* Prototypes for intel parser functions. */
8670 static int intel_match_token (int);
8671 static void intel_putback_token (void);
8672 static void intel_get_token (void);
8673 static int intel_expr (void);
8674 static int intel_e04 (void);
8675 static int intel_e05 (void);
8676 static int intel_e06 (void);
8677 static int intel_e09 (void);
8678 static int intel_e10 (void);
8679 static int intel_e11 (void);
8682 i386_intel_operand (char *operand_string
, int got_a_float
)
8687 p
= intel_parser
.op_string
= xstrdup (operand_string
);
8688 intel_parser
.disp
= (char *) xmalloc (strlen (operand_string
) + 1);
8692 /* Initialize token holders. */
8693 cur_token
.code
= prev_token
.code
= T_NIL
;
8694 cur_token
.reg
= prev_token
.reg
= NULL
;
8695 cur_token
.str
= prev_token
.str
= NULL
;
8697 /* Initialize parser structure. */
8698 intel_parser
.got_a_float
= got_a_float
;
8699 intel_parser
.op_modifier
= 0;
8700 intel_parser
.is_mem
= 0;
8701 intel_parser
.in_offset
= 0;
8702 intel_parser
.in_bracket
= 0;
8703 intel_parser
.reg
= NULL
;
8704 intel_parser
.disp
[0] = '\0';
8705 intel_parser
.next_operand
= NULL
;
8707 /* Read the first token and start the parser. */
8709 ret
= intel_expr ();
8714 if (cur_token
.code
!= T_NIL
)
8716 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
8717 current_templates
->start
->name
, cur_token
.str
);
8720 /* If we found a memory reference, hand it over to i386_displacement
8721 to fill in the rest of the operand fields. */
8722 else if (intel_parser
.is_mem
)
8724 if ((i
.mem_operands
== 1
8725 && !current_templates
->start
->opcode_modifier
.isstring
)
8726 || i
.mem_operands
== 2)
8728 as_bad (_("too many memory references for '%s'"),
8729 current_templates
->start
->name
);
8734 char *s
= intel_parser
.disp
;
8735 i
.types
[this_operand
].bitfield
.mem
= 1;
8738 if (!quiet_warnings
&& intel_parser
.is_mem
< 0)
8739 /* See the comments in intel_bracket_expr. */
8740 as_warn (_("Treating `%s' as memory reference"), operand_string
);
8742 /* Add the displacement expression. */
8744 ret
= i386_displacement (s
, s
+ strlen (s
));
8747 /* Swap base and index in 16-bit memory operands like
8748 [si+bx]. Since i386_index_check is also used in AT&T
8749 mode we have to do that here. */
8752 && i
.base_reg
->reg_type
.bitfield
.reg16
8753 && i
.index_reg
->reg_type
.bitfield
.reg16
8754 && i
.base_reg
->reg_num
>= 6
8755 && i
.index_reg
->reg_num
< 6)
8757 const reg_entry
*base
= i
.index_reg
;
8759 i
.index_reg
= i
.base_reg
;
8762 ret
= i386_index_check (operand_string
);
8767 /* Constant and OFFSET expressions are handled by i386_immediate. */
8768 else if ((intel_parser
.op_modifier
& (1 << T_OFFSET
))
8769 || intel_parser
.reg
== NULL
)
8771 if (i
.mem_operands
< 2 && i
.seg
[i
.mem_operands
])
8773 if (!(intel_parser
.op_modifier
& (1 << T_OFFSET
)))
8774 as_warn (_("Segment override ignored"));
8775 i
.seg
[i
.mem_operands
] = NULL
;
8777 ret
= i386_immediate (intel_parser
.disp
);
8780 if (intel_parser
.next_operand
&& this_operand
>= MAX_OPERANDS
- 1)
8782 if (!ret
|| !intel_parser
.next_operand
)
8784 intel_parser
.op_string
= intel_parser
.next_operand
;
8785 this_operand
= i
.operands
++;
8786 i
.types
[this_operand
].bitfield
.unspecified
= 1;
8790 free (intel_parser
.disp
);
8795 #define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
8799 expr' cmpOp e04 expr'
8804 /* XXX Implement the comparison operators. */
8805 return intel_e04 ();
8822 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
8823 i
.base_reg
= i386_regtab
+ REGNAM_AL
; /* al is invalid as base */
8825 if (cur_token
.code
== '+')
8827 else if (cur_token
.code
== '-')
8828 nregs
= NUM_ADDRESS_REGS
;
8832 strcat (intel_parser
.disp
, cur_token
.str
);
8833 intel_match_token (cur_token
.code
);
8844 int nregs
= ~NUM_ADDRESS_REGS
;
8851 if (cur_token
.code
== '&'
8852 || cur_token
.code
== '|'
8853 || cur_token
.code
== '^')
8857 str
[0] = cur_token
.code
;
8859 strcat (intel_parser
.disp
, str
);
8864 intel_match_token (cur_token
.code
);
8869 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
8870 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 1; /* cl is invalid as base */
8881 int nregs
= ~NUM_ADDRESS_REGS
;
8888 if (cur_token
.code
== '*'
8889 || cur_token
.code
== '/'
8890 || cur_token
.code
== '%')
8894 str
[0] = cur_token
.code
;
8896 strcat (intel_parser
.disp
, str
);
8898 else if (cur_token
.code
== T_SHL
)
8899 strcat (intel_parser
.disp
, "<<");
8900 else if (cur_token
.code
== T_SHR
)
8901 strcat (intel_parser
.disp
, ">>");
8905 intel_match_token (cur_token
.code
);
8910 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
8911 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 2; /* dl is invalid as base */
8929 int nregs
= ~NUM_ADDRESS_REGS
;
8934 /* Don't consume constants here. */
8935 if (cur_token
.code
== '+' || cur_token
.code
== '-')
8937 /* Need to look one token ahead - if the next token
8938 is a constant, the current token is its sign. */
8941 intel_match_token (cur_token
.code
);
8942 next_code
= cur_token
.code
;
8943 intel_putback_token ();
8944 if (next_code
== T_CONST
)
8948 /* e09 OFFSET e09 */
8949 if (cur_token
.code
== T_OFFSET
)
8952 ++intel_parser
.in_offset
;
8956 else if (cur_token
.code
== T_SHORT
)
8957 intel_parser
.op_modifier
|= 1 << T_SHORT
;
8960 else if (cur_token
.code
== '+')
8961 strcat (intel_parser
.disp
, "+");
8966 else if (cur_token
.code
== '-' || cur_token
.code
== '~')
8972 str
[0] = cur_token
.code
;
8974 strcat (intel_parser
.disp
, str
);
8981 intel_match_token (cur_token
.code
);
8989 /* e09' PTR e10 e09' */
8990 if (cur_token
.code
== T_PTR
)
8994 if (prev_token
.code
== T_BYTE
)
8996 suffix
= BYTE_MNEM_SUFFIX
;
8997 i
.types
[this_operand
].bitfield
.byte
= 1;
9000 else if (prev_token
.code
== T_WORD
)
9002 if ((current_templates
->start
->name
[0] == 'l'
9003 && current_templates
->start
->name
[2] == 's'
9004 && current_templates
->start
->name
[3] == 0)
9005 || current_templates
->start
->base_opcode
== 0x62 /* bound */)
9006 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
9007 else if (intel_parser
.got_a_float
== 2) /* "fi..." */
9008 suffix
= SHORT_MNEM_SUFFIX
;
9010 suffix
= WORD_MNEM_SUFFIX
;
9011 i
.types
[this_operand
].bitfield
.word
= 1;
9014 else if (prev_token
.code
== T_DWORD
)
9016 if ((current_templates
->start
->name
[0] == 'l'
9017 && current_templates
->start
->name
[2] == 's'
9018 && current_templates
->start
->name
[3] == 0)
9019 || current_templates
->start
->base_opcode
== 0x62 /* bound */)
9020 suffix
= WORD_MNEM_SUFFIX
;
9021 else if (flag_code
== CODE_16BIT
9022 && (current_templates
->start
->opcode_modifier
.jump
9023 || current_templates
->start
->opcode_modifier
.jumpdword
))
9024 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
9025 else if (intel_parser
.got_a_float
== 1) /* "f..." */
9026 suffix
= SHORT_MNEM_SUFFIX
;
9028 suffix
= LONG_MNEM_SUFFIX
;
9029 i
.types
[this_operand
].bitfield
.dword
= 1;
9032 else if (prev_token
.code
== T_FWORD
)
9034 if (current_templates
->start
->name
[0] == 'l'
9035 && current_templates
->start
->name
[2] == 's'
9036 && current_templates
->start
->name
[3] == 0)
9037 suffix
= LONG_MNEM_SUFFIX
;
9038 else if (!intel_parser
.got_a_float
)
9040 if (flag_code
== CODE_16BIT
)
9041 add_prefix (DATA_PREFIX_OPCODE
);
9042 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
9045 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
9046 i
.types
[this_operand
].bitfield
.fword
= 1;
9049 else if (prev_token
.code
== T_QWORD
)
9051 if (current_templates
->start
->base_opcode
== 0x62 /* bound */
9052 || intel_parser
.got_a_float
== 1) /* "f..." */
9053 suffix
= LONG_MNEM_SUFFIX
;
9055 suffix
= QWORD_MNEM_SUFFIX
;
9056 i
.types
[this_operand
].bitfield
.qword
= 1;
9059 else if (prev_token
.code
== T_TBYTE
)
9061 if (intel_parser
.got_a_float
== 1)
9062 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
9064 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
9067 else if (prev_token
.code
== T_XMMWORD
)
9069 suffix
= XMMWORD_MNEM_SUFFIX
;
9070 i
.types
[this_operand
].bitfield
.xmmword
= 1;
9073 else if (prev_token
.code
== T_YMMWORD
)
9075 suffix
= YMMWORD_MNEM_SUFFIX
;
9076 i
.types
[this_operand
].bitfield
.ymmword
= 1;
9081 as_bad (_("Unknown operand modifier `%s'"), prev_token
.str
);
9085 i
.types
[this_operand
].bitfield
.unspecified
= 0;
9087 /* Operands for jump/call using 'ptr' notation denote absolute
9089 if (current_templates
->start
->opcode_modifier
.jump
9090 || current_templates
->start
->opcode_modifier
.jumpdword
)
9091 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
9093 if (current_templates
->start
->base_opcode
== 0x8d /* lea */)
9097 else if (i
.suffix
!= suffix
)
9099 as_bad (_("Conflicting operand modifiers"));
9105 /* e09' : e10 e09' */
9106 else if (cur_token
.code
== ':')
9108 if (prev_token
.code
!= T_REG
)
9110 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
9111 segment/group identifier (which we don't have), using comma
9112 as the operand separator there is even less consistent, since
9113 there all branches only have a single operand. */
9114 if (this_operand
!= 0
9115 || intel_parser
.in_offset
9116 || intel_parser
.in_bracket
9117 || (!current_templates
->start
->opcode_modifier
.jump
9118 && !current_templates
->start
->opcode_modifier
.jumpdword
9119 && !current_templates
->start
->opcode_modifier
.jumpintersegment
9120 && !current_templates
->start
->operand_types
[0].bitfield
.jumpabsolute
))
9121 return intel_match_token (T_NIL
);
9122 /* Remember the start of the 2nd operand and terminate 1st
9124 XXX This isn't right, yet (when SSSS:OOOO is right operand of
9125 another expression), but it gets at least the simplest case
9126 (a plain number or symbol on the left side) right. */
9127 intel_parser
.next_operand
= intel_parser
.op_string
;
9128 *--intel_parser
.op_string
= '\0';
9129 return intel_match_token (':');
9137 intel_match_token (cur_token
.code
);
9143 --intel_parser
.in_offset
;
9146 if (NUM_ADDRESS_REGS
> nregs
)
9148 as_bad (_("Invalid operand to `OFFSET'"));
9151 intel_parser
.op_modifier
|= 1 << T_OFFSET
;
9154 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
9155 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 3; /* bl is invalid as base */
9160 intel_bracket_expr (void)
9162 int was_offset
= intel_parser
.op_modifier
& (1 << T_OFFSET
);
9163 const char *start
= intel_parser
.op_string
;
9166 if (i
.op
[this_operand
].regs
)
9167 return intel_match_token (T_NIL
);
9169 intel_match_token ('[');
9171 /* Mark as a memory operand only if it's not already known to be an
9172 offset expression. If it's an offset expression, we need to keep
9174 if (!intel_parser
.in_offset
)
9176 ++intel_parser
.in_bracket
;
9178 /* Operands for jump/call inside brackets denote absolute addresses. */
9179 if (current_templates
->start
->opcode_modifier
.jump
9180 || current_templates
->start
->opcode_modifier
.jumpdword
)
9181 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
9183 /* Unfortunately gas always diverged from MASM in a respect that can't
9184 be easily fixed without risking to break code sequences likely to be
9185 encountered (the testsuite even check for this): MASM doesn't consider
9186 an expression inside brackets unconditionally as a memory reference.
9187 When that is e.g. a constant, an offset expression, or the sum of the
9188 two, this is still taken as a constant load. gas, however, always
9189 treated these as memory references. As a compromise, we'll try to make
9190 offset expressions inside brackets work the MASM way (since that's
9191 less likely to be found in real world code), but make constants alone
9192 continue to work the traditional gas way. In either case, issue a
9194 intel_parser
.op_modifier
&= ~was_offset
;
9197 strcat (intel_parser
.disp
, "[");
9199 /* Add a '+' to the displacement string if necessary. */
9200 if (*intel_parser
.disp
!= '\0'
9201 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
9202 strcat (intel_parser
.disp
, "+");
9205 && (len
= intel_parser
.op_string
- start
- 1,
9206 intel_match_token (']')))
9208 /* Preserve brackets when the operand is an offset expression. */
9209 if (intel_parser
.in_offset
)
9210 strcat (intel_parser
.disp
, "]");
9213 --intel_parser
.in_bracket
;
9214 if (i
.base_reg
|| i
.index_reg
)
9215 intel_parser
.is_mem
= 1;
9216 if (!intel_parser
.is_mem
)
9218 if (!(intel_parser
.op_modifier
& (1 << T_OFFSET
)))
9219 /* Defer the warning until all of the operand was parsed. */
9220 intel_parser
.is_mem
= -1;
9221 else if (!quiet_warnings
)
9222 as_warn (_("`[%.*s]' taken to mean just `%.*s'"),
9223 len
, start
, len
, start
);
9226 intel_parser
.op_modifier
|= was_offset
;
9243 while (cur_token
.code
== '[')
9245 if (!intel_bracket_expr ())
9271 switch (cur_token
.code
)
9275 intel_match_token ('(');
9276 strcat (intel_parser
.disp
, "(");
9278 if (intel_expr () && intel_match_token (')'))
9280 strcat (intel_parser
.disp
, ")");
9287 return intel_bracket_expr ();
9292 strcat (intel_parser
.disp
, cur_token
.str
);
9293 intel_match_token (cur_token
.code
);
9295 /* Mark as a memory operand only if it's not already known to be an
9296 offset expression. */
9297 if (!intel_parser
.in_offset
)
9298 intel_parser
.is_mem
= 1;
9305 const reg_entry
*reg
= intel_parser
.reg
= cur_token
.reg
;
9307 intel_match_token (T_REG
);
9309 /* Check for segment change. */
9310 if (cur_token
.code
== ':')
9312 if (!reg
->reg_type
.bitfield
.sreg2
9313 && !reg
->reg_type
.bitfield
.sreg3
)
9315 as_bad (_("`%s' is not a valid segment register"),
9319 else if (i
.mem_operands
>= 2)
9320 as_warn (_("Segment override ignored"));
9321 else if (i
.seg
[i
.mem_operands
])
9322 as_warn (_("Extra segment override ignored"));
9325 if (!intel_parser
.in_offset
)
9326 intel_parser
.is_mem
= 1;
9327 switch (reg
->reg_num
)
9330 i
.seg
[i
.mem_operands
] = &es
;
9333 i
.seg
[i
.mem_operands
] = &cs
;
9336 i
.seg
[i
.mem_operands
] = &ss
;
9339 i
.seg
[i
.mem_operands
] = &ds
;
9342 i
.seg
[i
.mem_operands
] = &fs
;
9345 i
.seg
[i
.mem_operands
] = &gs
;
9351 else if (reg
->reg_type
.bitfield
.sreg3
&& reg
->reg_num
== RegFlat
)
9353 as_bad (_("cannot use `FLAT' here"));
9357 /* Not a segment register. Check for register scaling. */
9358 else if (cur_token
.code
== '*')
9360 if (!intel_parser
.in_bracket
)
9362 as_bad (_("Register scaling only allowed in memory operands"));
9366 if (reg
->reg_type
.bitfield
.reg16
) /* Disallow things like [si*1]. */
9367 reg
= i386_regtab
+ REGNAM_AX
+ 4; /* sp is invalid as index */
9368 else if (i
.index_reg
)
9369 reg
= i386_regtab
+ REGNAM_EAX
+ 4; /* esp is invalid as index */
9371 /* What follows must be a valid scale. */
9372 intel_match_token ('*');
9374 i
.types
[this_operand
].bitfield
.baseindex
= 1;
9376 /* Set the scale after setting the register (otherwise,
9377 i386_scale will complain) */
9378 if (cur_token
.code
== '+' || cur_token
.code
== '-')
9380 char *str
, sign
= cur_token
.code
;
9381 intel_match_token (cur_token
.code
);
9382 if (cur_token
.code
!= T_CONST
)
9384 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
9388 str
= (char *) xmalloc (strlen (cur_token
.str
) + 2);
9389 strcpy (str
+ 1, cur_token
.str
);
9391 if (!i386_scale (str
))
9395 else if (!i386_scale (cur_token
.str
))
9397 intel_match_token (cur_token
.code
);
9400 /* No scaling. If this is a memory operand, the register is either a
9401 base register (first occurrence) or an index register (second
9403 else if (intel_parser
.in_bracket
)
9408 else if (!i
.index_reg
)
9412 as_bad (_("Too many register references in memory operand"));
9416 i
.types
[this_operand
].bitfield
.baseindex
= 1;
9419 /* It's neither base nor index. */
9420 else if (!intel_parser
.in_offset
&& !intel_parser
.is_mem
)
9422 i386_operand_type temp
= reg
->reg_type
;
9423 temp
.bitfield
.baseindex
= 0;
9424 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
9426 i
.types
[this_operand
].bitfield
.unspecified
= 0;
9427 i
.op
[this_operand
].regs
= reg
;
9432 as_bad (_("Invalid use of register"));
9436 /* Since registers are not part of the displacement string (except
9437 when we're parsing offset operands), we may need to remove any
9438 preceding '+' from the displacement string. */
9439 if (*intel_parser
.disp
!= '\0'
9440 && !intel_parser
.in_offset
)
9442 char *s
= intel_parser
.disp
;
9443 s
+= strlen (s
) - 1;
9468 intel_match_token (cur_token
.code
);
9470 if (cur_token
.code
== T_PTR
)
9473 /* It must have been an identifier. */
9474 intel_putback_token ();
9475 cur_token
.code
= T_ID
;
9481 if (!intel_parser
.in_offset
&& intel_parser
.is_mem
<= 0)
9485 /* The identifier represents a memory reference only if it's not
9486 preceded by an offset modifier and if it's not an equate. */
9487 symbolP
= symbol_find(cur_token
.str
);
9488 if (!symbolP
|| S_GET_SEGMENT(symbolP
) != absolute_section
)
9489 intel_parser
.is_mem
= 1;
9497 char *save_str
, sign
= 0;
9499 /* Allow constants that start with `+' or `-'. */
9500 if (cur_token
.code
== '-' || cur_token
.code
== '+')
9502 sign
= cur_token
.code
;
9503 intel_match_token (cur_token
.code
);
9504 if (cur_token
.code
!= T_CONST
)
9506 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
9512 save_str
= (char *) xmalloc (strlen (cur_token
.str
) + 2);
9513 strcpy (save_str
+ !!sign
, cur_token
.str
);
9517 /* Get the next token to check for register scaling. */
9518 intel_match_token (cur_token
.code
);
9520 /* Check if this constant is a scaling factor for an
9522 if (cur_token
.code
== '*')
9524 if (intel_match_token ('*') && cur_token
.code
== T_REG
)
9526 const reg_entry
*reg
= cur_token
.reg
;
9528 if (!intel_parser
.in_bracket
)
9530 as_bad (_("Register scaling only allowed "
9531 "in memory operands"));
9535 /* Disallow things like [1*si].
9536 sp and esp are invalid as index. */
9537 if (reg
->reg_type
.bitfield
.reg16
)
9538 reg
= i386_regtab
+ REGNAM_AX
+ 4;
9539 else if (i
.index_reg
)
9540 reg
= i386_regtab
+ REGNAM_EAX
+ 4;
9542 /* The constant is followed by `* reg', so it must be
9545 i
.types
[this_operand
].bitfield
.baseindex
= 1;
9547 /* Set the scale after setting the register (otherwise,
9548 i386_scale will complain) */
9549 if (!i386_scale (save_str
))
9551 intel_match_token (T_REG
);
9553 /* Since registers are not part of the displacement
9554 string, we may need to remove any preceding '+' from
9555 the displacement string. */
9556 if (*intel_parser
.disp
!= '\0')
9558 char *s
= intel_parser
.disp
;
9559 s
+= strlen (s
) - 1;
9569 /* The constant was not used for register scaling. Since we have
9570 already consumed the token following `*' we now need to put it
9571 back in the stream. */
9572 intel_putback_token ();
9575 /* Add the constant to the displacement string. */
9576 strcat (intel_parser
.disp
, save_str
);
9583 as_bad (_("Unrecognized token '%s'"), cur_token
.str
);
9587 /* Match the given token against cur_token. If they match, read the next
9588 token from the operand string. */
9590 intel_match_token (int code
)
9592 if (cur_token
.code
== code
)
9599 as_bad (_("Unexpected token `%s'"), cur_token
.str
);
9604 /* Read a new token from intel_parser.op_string and store it in cur_token. */
9606 intel_get_token (void)
9609 const reg_entry
*reg
;
9610 struct intel_token new_token
;
9612 new_token
.code
= T_NIL
;
9613 new_token
.reg
= NULL
;
9614 new_token
.str
= NULL
;
9616 /* Free the memory allocated to the previous token and move
9617 cur_token to prev_token. */
9619 free (prev_token
.str
);
9621 prev_token
= cur_token
;
9623 /* Skip whitespace. */
9624 while (is_space_char (*intel_parser
.op_string
))
9625 intel_parser
.op_string
++;
9627 /* Return an empty token if we find nothing else on the line. */
9628 if (*intel_parser
.op_string
== '\0')
9630 cur_token
= new_token
;
9634 /* The new token cannot be larger than the remainder of the operand
9636 new_token
.str
= (char *) xmalloc (strlen (intel_parser
.op_string
) + 1);
9637 new_token
.str
[0] = '\0';
9639 if (strchr ("0123456789", *intel_parser
.op_string
))
9641 char *p
= new_token
.str
;
9642 char *q
= intel_parser
.op_string
;
9643 new_token
.code
= T_CONST
;
9645 /* Allow any kind of identifier char to encompass floating point and
9646 hexadecimal numbers. */
9647 while (is_identifier_char (*q
))
9651 /* Recognize special symbol names [0-9][bf]. */
9652 if (strlen (intel_parser
.op_string
) == 2
9653 && (intel_parser
.op_string
[1] == 'b'
9654 || intel_parser
.op_string
[1] == 'f'))
9655 new_token
.code
= T_ID
;
9658 else if ((reg
= parse_register (intel_parser
.op_string
, &end_op
)) != NULL
)
9660 size_t len
= end_op
- intel_parser
.op_string
;
9662 new_token
.code
= T_REG
;
9663 new_token
.reg
= reg
;
9665 memcpy (new_token
.str
, intel_parser
.op_string
, len
);
9666 new_token
.str
[len
] = '\0';
9669 else if (is_identifier_char (*intel_parser
.op_string
))
9671 char *p
= new_token
.str
;
9672 char *q
= intel_parser
.op_string
;
9674 /* A '.' or '$' followed by an identifier char is an identifier.
9675 Otherwise, it's operator '.' followed by an expression. */
9676 if ((*q
== '.' || *q
== '$') && !is_identifier_char (*(q
+ 1)))
9678 new_token
.code
= '.';
9679 new_token
.str
[0] = '.';
9680 new_token
.str
[1] = '\0';
9684 while (is_identifier_char (*q
) || *q
== '@')
9688 if (strcasecmp (new_token
.str
, "NOT") == 0)
9689 new_token
.code
= '~';
9691 else if (strcasecmp (new_token
.str
, "MOD") == 0)
9692 new_token
.code
= '%';
9694 else if (strcasecmp (new_token
.str
, "AND") == 0)
9695 new_token
.code
= '&';
9697 else if (strcasecmp (new_token
.str
, "OR") == 0)
9698 new_token
.code
= '|';
9700 else if (strcasecmp (new_token
.str
, "XOR") == 0)
9701 new_token
.code
= '^';
9703 else if (strcasecmp (new_token
.str
, "SHL") == 0)
9704 new_token
.code
= T_SHL
;
9706 else if (strcasecmp (new_token
.str
, "SHR") == 0)
9707 new_token
.code
= T_SHR
;
9709 else if (strcasecmp (new_token
.str
, "BYTE") == 0)
9710 new_token
.code
= T_BYTE
;
9712 else if (strcasecmp (new_token
.str
, "WORD") == 0)
9713 new_token
.code
= T_WORD
;
9715 else if (strcasecmp (new_token
.str
, "DWORD") == 0)
9716 new_token
.code
= T_DWORD
;
9718 else if (strcasecmp (new_token
.str
, "FWORD") == 0)
9719 new_token
.code
= T_FWORD
;
9721 else if (strcasecmp (new_token
.str
, "QWORD") == 0)
9722 new_token
.code
= T_QWORD
;
9724 else if (strcasecmp (new_token
.str
, "TBYTE") == 0
9725 /* XXX remove (gcc still uses it) */
9726 || strcasecmp (new_token
.str
, "XWORD") == 0)
9727 new_token
.code
= T_TBYTE
;
9729 else if (strcasecmp (new_token
.str
, "XMMWORD") == 0
9730 || strcasecmp (new_token
.str
, "OWORD") == 0)
9731 new_token
.code
= T_XMMWORD
;
9733 else if (strcasecmp (new_token
.str
, "YMMWORD") == 0)
9734 new_token
.code
= T_YMMWORD
;
9736 else if (strcasecmp (new_token
.str
, "PTR") == 0)
9737 new_token
.code
= T_PTR
;
9739 else if (strcasecmp (new_token
.str
, "SHORT") == 0)
9740 new_token
.code
= T_SHORT
;
9742 else if (strcasecmp (new_token
.str
, "OFFSET") == 0)
9744 new_token
.code
= T_OFFSET
;
9746 /* ??? This is not mentioned in the MASM grammar but gcc
9747 makes use of it with -mintel-syntax. OFFSET may be
9748 followed by FLAT: */
9749 if (strncasecmp (q
, " FLAT:", 6) == 0)
9750 strcat (new_token
.str
, " FLAT:");
9754 new_token
.code
= T_ID
;
9758 else if (strchr ("+-/*%|&^:[]()~", *intel_parser
.op_string
))
9760 new_token
.code
= *intel_parser
.op_string
;
9761 new_token
.str
[0] = *intel_parser
.op_string
;
9762 new_token
.str
[1] = '\0';
9765 else if (strchr ("<>", *intel_parser
.op_string
)
9766 && *intel_parser
.op_string
== *(intel_parser
.op_string
+ 1))
9768 new_token
.code
= *intel_parser
.op_string
== '<' ? T_SHL
: T_SHR
;
9769 new_token
.str
[0] = *intel_parser
.op_string
;
9770 new_token
.str
[1] = *intel_parser
.op_string
;
9771 new_token
.str
[2] = '\0';
9775 as_bad (_("Unrecognized token `%s'"), intel_parser
.op_string
);
9777 intel_parser
.op_string
+= strlen (new_token
.str
);
9778 cur_token
= new_token
;
9781 /* Put cur_token back into the token stream and make cur_token point to
9784 intel_putback_token (void)
9786 if (cur_token
.code
!= T_NIL
)
9788 intel_parser
.op_string
-= strlen (cur_token
.str
);
9789 free (cur_token
.str
);
9791 cur_token
= prev_token
;
9793 /* Forget prev_token. */
9794 prev_token
.code
= T_NIL
;
9795 prev_token
.reg
= NULL
;
9796 prev_token
.str
= NULL
;
9800 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
9802 int saved_naked_reg
;
9803 char saved_register_dot
;
9805 saved_naked_reg
= allow_naked_reg
;
9806 allow_naked_reg
= 1;
9807 saved_register_dot
= register_chars
['.'];
9808 register_chars
['.'] = '.';
9809 allow_pseudo_reg
= 1;
9810 expression_and_evaluate (exp
);
9811 allow_pseudo_reg
= 0;
9812 register_chars
['.'] = saved_register_dot
;
9813 allow_naked_reg
= saved_naked_reg
;
9815 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
9817 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
9819 exp
->X_op
= O_constant
;
9820 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
9821 .dw2_regnum
[flag_code
>> 1];
9824 exp
->X_op
= O_illegal
;
9829 tc_x86_frame_initial_instructions (void)
9831 static unsigned int sp_regno
[2];
9833 if (!sp_regno
[flag_code
>> 1])
9835 char *saved_input
= input_line_pointer
;
9836 char sp
[][4] = {"esp", "rsp"};
9839 input_line_pointer
= sp
[flag_code
>> 1];
9840 tc_x86_parse_to_dw2regnum (&exp
);
9841 assert (exp
.X_op
== O_constant
);
9842 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
9843 input_line_pointer
= saved_input
;
9846 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
9847 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
9851 i386_elf_section_type (const char *str
, size_t len
)
9853 if (flag_code
== CODE_64BIT
9854 && len
== sizeof ("unwind") - 1
9855 && strncmp (str
, "unwind", 6) == 0)
9856 return SHT_X86_64_UNWIND
;
9863 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
9867 expr
.X_op
= O_secrel
;
9868 expr
.X_add_symbol
= symbol
;
9869 expr
.X_add_number
= 0;
9870 emit_expr (&expr
, size
);
9874 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9875 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
9878 x86_64_section_letter (int letter
, char **ptr_msg
)
9880 if (flag_code
== CODE_64BIT
)
9883 return SHF_X86_64_LARGE
;
9885 *ptr_msg
= _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
9888 *ptr_msg
= _("Bad .section directive: want a,w,x,M,S,G,T in string");
9893 x86_64_section_word (char *str
, size_t len
)
9895 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
9896 return SHF_X86_64_LARGE
;
9902 handle_large_common (int small ATTRIBUTE_UNUSED
)
9904 if (flag_code
!= CODE_64BIT
)
9906 s_comm_internal (0, elf_common_parse
);
9907 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
9911 static segT lbss_section
;
9912 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
9913 asection
*saved_bss_section
= bss_section
;
9915 if (lbss_section
== NULL
)
9917 flagword applicable
;
9919 subsegT subseg
= now_subseg
;
9921 /* The .lbss section is for local .largecomm symbols. */
9922 lbss_section
= subseg_new (".lbss", 0);
9923 applicable
= bfd_applicable_section_flags (stdoutput
);
9924 bfd_set_section_flags (stdoutput
, lbss_section
,
9925 applicable
& SEC_ALLOC
);
9926 seg_info (lbss_section
)->bss
= 1;
9928 subseg_set (seg
, subseg
);
9931 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
9932 bss_section
= lbss_section
;
9934 s_comm_internal (0, elf_common_parse
);
9936 elf_com_section_ptr
= saved_com_section_ptr
;
9937 bss_section
= saved_bss_section
;
9940 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */