1 /* Declarations for Intel 80386 opcode table
2 Copyright 2007, 2008, 2009
3 Free Software Foundation, Inc.
5 This file is part of the GNU opcodes library.
7 This library is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
22 #include "opcode/i386.h"
31 /* Position of cpu flags bitfiled. */
35 /* i186 or better required */
37 /* i286 or better required */
39 /* i386 or better required */
41 /* i486 or better required */
43 /* i585 or better required */
45 /* i686 or better required */
47 /* CLFLUSH Instuction support required */
49 /* SYSCALL Instuctions support required */
51 /* Floating point support required */
53 /* i287 support required */
55 /* i387 support required */
57 /* i686 and floating point support required */
59 /* SSE3 and floating point support required */
61 /* MMX support required */
63 /* SSE support required */
65 /* SSE2 support required */
67 /* 3dnow! support required */
69 /* 3dnow! Extensions support required */
71 /* SSE3 support required */
73 /* VIA PadLock required */
75 /* AMD Secure Virtual Machine Ext-s required */
77 /* VMX Instructions required */
79 /* SMX Instructions required */
81 /* SSSE3 support required */
83 /* SSE4a support required */
85 /* ABM New Instructions required */
87 /* SSE4.1 support required */
89 /* SSE4.2 support required */
91 /* AVX support required */
93 /* Intel L1OM support required */
95 /* Xsave/xrstor New Instuctions support required */
97 /* AES support required */
99 /* PCLMUL support required */
101 /* FMA support required */
103 /* FMA4 support required */
105 /* XOP support required */
107 /* LWP support required */
109 /* MOVBE Instuction support required */
111 /* EPT Instructions required */
113 /* RDTSCP Instuction support required */
115 /* 64bit support available, used by -march= in assembler. */
117 /* 64bit support required */
119 /* Not supported in the 64bit mode */
121 /* The last bitfield in i386_cpu_flags. */
125 #define CpuNumOfUints \
126 (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
127 #define CpuNumOfBits \
128 (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
130 /* If you get a compiler error for zero width of the unused field,
132 #define CpuUnused (CpuMax + 1)
134 /* We can check if an instruction is available with array instead
136 typedef union i386_cpu_flags
140 unsigned int cpui186
:1;
141 unsigned int cpui286
:1;
142 unsigned int cpui386
:1;
143 unsigned int cpui486
:1;
144 unsigned int cpui586
:1;
145 unsigned int cpui686
:1;
146 unsigned int cpuclflush
:1;
147 unsigned int cpusyscall
:1;
148 unsigned int cpu8087
:1;
149 unsigned int cpu287
:1;
150 unsigned int cpu387
:1;
151 unsigned int cpu687
:1;
152 unsigned int cpufisttp
:1;
153 unsigned int cpummx
:1;
154 unsigned int cpusse
:1;
155 unsigned int cpusse2
:1;
156 unsigned int cpua3dnow
:1;
157 unsigned int cpua3dnowa
:1;
158 unsigned int cpusse3
:1;
159 unsigned int cpupadlock
:1;
160 unsigned int cpusvme
:1;
161 unsigned int cpuvmx
:1;
162 unsigned int cpusmx
:1;
163 unsigned int cpussse3
:1;
164 unsigned int cpusse4a
:1;
165 unsigned int cpuabm
:1;
166 unsigned int cpusse4_1
:1;
167 unsigned int cpusse4_2
:1;
168 unsigned int cpuavx
:1;
169 unsigned int cpul1om
:1;
170 unsigned int cpuxsave
:1;
171 unsigned int cpuaes
:1;
172 unsigned int cpupclmul
:1;
173 unsigned int cpufma
:1;
174 unsigned int cpufma4
:1;
175 unsigned int cpuxop
:1;
176 unsigned int cpulwp
:1;
177 unsigned int cpumovbe
:1;
178 unsigned int cpuept
:1;
179 unsigned int cpurdtscp
:1;
180 unsigned int cpulm
:1;
181 unsigned int cpu64
:1;
182 unsigned int cpuno64
:1;
184 unsigned int unused
:(CpuNumOfBits
- CpuUnused
);
187 unsigned int array
[CpuNumOfUints
];
190 /* Position of opcode_modifier bits. */
194 /* has direction bit. */
196 /* set if operands can be words or dwords encoded the canonical way */
198 /* Skip the current insn and use the next insn in i386-opc.tbl to swap
199 operand in encoding. */
201 /* insn has a modrm byte. */
203 /* register is in low 3 bits of opcode */
205 /* special case for jump insns. */
211 /* special case for intersegment leaps/calls */
213 /* FP insn memory format bit, sized by 0x4 */
215 /* src/dest swap for floats. */
217 /* has float insn direction bit. */
219 /* needs size prefix if in 32-bit mode */
221 /* needs size prefix if in 16-bit mode */
223 /* needs size prefix if in 64-bit mode */
225 /* instruction ignores operand size prefix and in Intel mode ignores
226 mnemonic size suffix check. */
228 /* default insn size depends on mode */
230 /* b suffix on instruction illegal */
232 /* w suffix on instruction illegal */
234 /* l suffix on instruction illegal */
236 /* s suffix on instruction illegal */
238 /* q suffix on instruction illegal */
240 /* long double suffix on instruction illegal */
242 /* instruction needs FWAIT */
244 /* quick test for string instructions */
246 /* quick test for lockable instructions */
248 /* fake an extra reg operand for clr, imul and special register
249 processing for some instructions. */
251 /* The first operand must be xmm0 */
253 /* An implicit xmm0 as the first operand */
255 /* BYTE is OK in Intel syntax. */
257 /* Convert to DWORD */
259 /* Convert to QWORD */
261 /* Address prefix changes operand 0 */
263 /* opcode is a prefix */
265 /* instruction has extension in 8 bit imm */
267 /* instruction don't need Rex64 prefix. */
269 /* instruction require Rex64 prefix. */
271 /* deprecated fp insn, gets a warning */
273 /* insn has VEX prefix:
274 1: 128bit VEX prefix.
275 2: 256bit VEX prefix.
280 /* insn has VEX NDS. Register-only source is encoded in Vex prefix.
281 We use VexNDS on insns with VEX DDS since the register-only source
282 is the second source register. */
284 /* insn has VEX NDD. Register destination is encoded in Vex prefix. */
286 /* insn has VEX NDD. Register destination is encoded in Vex prefix
287 and one of the operands can access a memory location. */
289 /* insn has VEX W0. */
291 /* insn has VEX W1. */
293 /* insn has VEX 0x0F opcode prefix. */
295 /* insn has VEX 0x0F38 opcode prefix. */
297 /* insn has VEX 0x0F3A opcode prefix. */
299 /* insn has XOP 0x08 opcode prefix. */
301 /* insn has XOP 0x09 opcode prefix. */
303 /* insn has XOP 0x0A opcode prefix. */
305 /* insn has VEX prefix with 2 sources. */
307 /* insn has VEX prefix with 3 sources. */
309 /* instruction has VEX 8 bit imm */
311 /* SSE to AVX support required */
313 /* No AVX equivalent */
315 /* Compatible with old (<= 2.8.1) versions of gcc */
323 /* The last bitfield in i386_opcode_modifier. */
327 typedef struct i386_opcode_modifier
332 unsigned int modrm
:1;
333 unsigned int shortform
:1;
335 unsigned int jumpdword
:1;
336 unsigned int jumpbyte
:1;
337 unsigned int jumpintersegment
:1;
338 unsigned int floatmf
:1;
339 unsigned int floatr
:1;
340 unsigned int floatd
:1;
341 unsigned int size16
:1;
342 unsigned int size32
:1;
343 unsigned int size64
:1;
344 unsigned int ignoresize
:1;
345 unsigned int defaultsize
:1;
346 unsigned int no_bsuf
:1;
347 unsigned int no_wsuf
:1;
348 unsigned int no_lsuf
:1;
349 unsigned int no_ssuf
:1;
350 unsigned int no_qsuf
:1;
351 unsigned int no_ldsuf
:1;
352 unsigned int fwait
:1;
353 unsigned int isstring
:1;
354 unsigned int islockable
:1;
355 unsigned int regkludge
:1;
356 unsigned int firstxmm0
:1;
357 unsigned int implicit1stxmm0
:1;
358 unsigned int byteokintel
:1;
359 unsigned int todword
:1;
360 unsigned int toqword
:1;
361 unsigned int addrprefixop0
:1;
362 unsigned int isprefix
:1;
363 unsigned int immext
:1;
364 unsigned int norex64
:1;
365 unsigned int rex64
:1;
368 unsigned int vexnds
:1;
369 unsigned int vexndd
:1;
370 unsigned int vexlwp
:1;
371 unsigned int vexw0
:1;
372 unsigned int vexw1
:1;
373 unsigned int vex0f
:1;
374 unsigned int vex0f38
:1;
375 unsigned int vex0f3a
:1;
376 unsigned int xop08
:1;
377 unsigned int xop09
:1;
378 unsigned int xop0a
:1;
379 unsigned int vex2sources
:1;
380 unsigned int vex3sources
:1;
381 unsigned int veximmext
:1;
382 unsigned int sse2avx
:1;
383 unsigned int noavx
:1;
384 unsigned int oldgcc
:1;
385 unsigned int attmnemonic
:1;
386 unsigned int attsyntax
:1;
387 unsigned int intelsyntax
:1;
388 } i386_opcode_modifier
;
390 /* Position of operand_type bits. */
402 /* Floating pointer stack register */
410 /* Control register */
416 /* 2 bit segment register */
418 /* 3 bit segment register */
420 /* 1 bit immediate */
422 /* 8 bit immediate */
424 /* 8 bit immediate sign extended */
426 /* 16 bit immediate */
428 /* 32 bit immediate */
430 /* 32 bit immediate sign extended */
432 /* 64 bit immediate */
434 /* 8bit/16bit/32bit displacements are used in different ways,
435 depending on the instruction. For jumps, they specify the
436 size of the PC relative displacement, for instructions with
437 memory operand, they specify the size of the offset relative
438 to the base register, and for instructions with memory offset
439 such as `mov 1234,%al' they specify the size of the offset
440 relative to the segment base. */
441 /* 8 bit displacement */
443 /* 16 bit displacement */
445 /* 32 bit displacement */
447 /* 32 bit signed displacement */
449 /* 64 bit displacement */
451 /* Accumulator %al/%ax/%eax/%rax */
453 /* Floating pointer top stack register %st(0) */
455 /* Register which can be used for base or index in memory operand. */
457 /* Register to hold in/out port addr = dx */
459 /* Register to hold shift count = cl */
461 /* Absolute address for jump. */
463 /* String insn operand with fixed es segment */
465 /* RegMem is for instructions with a modrm byte where the register
466 destination operand should be encoded in the mod and regmem fields.
467 Normally, it will be encoded in the reg field. We add a RegMem
468 flag to the destination register operand to indicate that it should
469 be encoded in the regmem field. */
475 /* WORD memory. 2 byte */
477 /* DWORD memory. 4 byte */
479 /* FWORD memory. 6 byte */
481 /* QWORD memory. 8 byte */
483 /* TBYTE memory. 10 byte */
485 /* XMMWORD memory. */
487 /* YMMWORD memory. */
489 /* Unspecified memory size. */
491 /* Any memory size. */
494 /* The last bitfield in i386_operand_type. */
498 #define OTNumOfUints \
499 (OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
500 #define OTNumOfBits \
501 (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
503 /* If you get a compiler error for zero width of the unused field,
505 #define OTUnused (OTMax + 1)
507 typedef union i386_operand_type
512 unsigned int reg16
:1;
513 unsigned int reg32
:1;
514 unsigned int reg64
:1;
515 unsigned int floatreg
:1;
516 unsigned int regmmx
:1;
517 unsigned int regxmm
:1;
518 unsigned int regymm
:1;
519 unsigned int control
:1;
520 unsigned int debug
:1;
522 unsigned int sreg2
:1;
523 unsigned int sreg3
:1;
526 unsigned int imm8s
:1;
527 unsigned int imm16
:1;
528 unsigned int imm32
:1;
529 unsigned int imm32s
:1;
530 unsigned int imm64
:1;
531 unsigned int disp8
:1;
532 unsigned int disp16
:1;
533 unsigned int disp32
:1;
534 unsigned int disp32s
:1;
535 unsigned int disp64
:1;
537 unsigned int floatacc
:1;
538 unsigned int baseindex
:1;
539 unsigned int inoutportreg
:1;
540 unsigned int shiftcount
:1;
541 unsigned int jumpabsolute
:1;
542 unsigned int esseg
:1;
543 unsigned int regmem
:1;
547 unsigned int dword
:1;
548 unsigned int fword
:1;
549 unsigned int qword
:1;
550 unsigned int tbyte
:1;
551 unsigned int xmmword
:1;
552 unsigned int ymmword
:1;
553 unsigned int unspecified
:1;
554 unsigned int anysize
:1;
556 unsigned int unused
:(OTNumOfBits
- OTUnused
);
559 unsigned int array
[OTNumOfUints
];
562 typedef struct insn_template
564 /* instruction name sans width suffix ("mov" for movl insns) */
567 /* how many operands */
568 unsigned int operands
;
570 /* base_opcode is the fundamental opcode byte without optional
572 unsigned int base_opcode
;
573 #define Opcode_D 0x2 /* Direction bit:
574 set if Reg --> Regmem;
575 unset if Regmem --> Reg. */
576 #define Opcode_FloatR 0x8 /* Bit to swap src/dest for float insns. */
577 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
579 /* extension_opcode is the 3 bit extension for group <n> insns.
580 This field is also used to store the 8-bit opcode suffix for the
581 AMD 3DNow! instructions.
582 If this template has no extension opcode (the usual case) use None
584 unsigned int extension_opcode
;
585 #define None 0xffff /* If no extension_opcode is possible. */
588 unsigned char opcode_length
;
590 /* cpu feature flags */
591 i386_cpu_flags cpu_flags
;
593 /* the bits in opcode_modifier are used to generate the final opcode from
594 the base_opcode. These bits also are used to detect alternate forms of
595 the same instruction */
596 i386_opcode_modifier opcode_modifier
;
598 /* operand_types[i] describes the type of operand i. This is made
599 by OR'ing together all of the possible type masks. (e.g.
600 'operand_types[i] = Reg|Imm' specifies that operand i can be
601 either a register or an immediate operand. */
602 i386_operand_type operand_types
[MAX_OPERANDS
];
606 extern const insn_template i386_optab
[];
608 /* these are for register name --> number & type hash lookup */
612 i386_operand_type reg_type
;
613 unsigned char reg_flags
;
614 #define RegRex 0x1 /* Extended register. */
615 #define RegRex64 0x2 /* Extended 8 bit register. */
616 unsigned char reg_num
;
617 #define RegRip ((unsigned char ) ~0)
618 #define RegEip (RegRip - 1)
619 /* EIZ and RIZ are fake index registers. */
620 #define RegEiz (RegEip - 1)
621 #define RegRiz (RegEiz - 1)
622 /* FLAT is a fake segment register (Intel mode). */
623 #define RegFlat ((unsigned char) ~0)
624 signed char dw2_regnum
[2];
625 #define Dw2Inval (-1)
629 /* Entries in i386_regtab. */
632 #define REGNAM_EAX 41
634 extern const reg_entry i386_regtab
[];
635 extern const unsigned int i386_regtab_size
;
640 unsigned int seg_prefix
;
644 extern const seg_entry cs
;
645 extern const seg_entry ds
;
646 extern const seg_entry ss
;
647 extern const seg_entry es
;
648 extern const seg_entry fs
;
649 extern const seg_entry gs
;