include/opcode/i386.h

   1 /* opcode/i386.h -- Intel 80386 opcode macros
   2    Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
   3    2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
   4    Free Software Foundation, Inc.
   5
   6    This file is part of GAS, the GNU Assembler, and GDB, the GNU Debugger.
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 2 of the License, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; if not, write to the Free Software
  20    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
  21
  22 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T derived
  23    ix86 Unix assemblers, generate floating point instructions with
  24    reversed source and destination registers in certain cases.
  25    Unfortunately, gcc and possibly many other programs use this
  26    reversed syntax, so we're stuck with it.
  27
  28    eg. `fsub %st(3),%st' results in st = st - st(3) as expected, but
  29    `fsub %st,%st(3)' results in st(3) = st - st(3), rather than
  30    the expected st(3) = st(3) - st
  31
  32    This happens with all the non-commutative arithmetic floating point
  33    operations with two register operands, where the source register is
  34    %st, and destination register is %st(i).
  35
  36    The affected opcode map is dceX, dcfX, deeX, defX.  */
  37
  38 #ifndef OPCODE_I386_H
  39 #define OPCODE_I386_H
  40
  41 #ifndef SYSV386_COMPAT
  42 /* Set non-zero for broken, compatible instructions.  Set to zero for
  43    non-broken opcodes at your peril.  gcc generates SystemV/386
  44    compatible instructions.  */
  45 #define SYSV386_COMPAT 1
  46 #endif
  47 #ifndef OLDGCC_COMPAT
  48 /* Set non-zero to cater for old (<= 2.8.1) versions of gcc that could
  49    generate nonsense fsubp, fsubrp, fdivp and fdivrp with operands
  50    reversed.  */
  51 #define OLDGCC_COMPAT SYSV386_COMPAT
  52 #endif
  53
  54 #define MOV_AX_DISP32 0xa0
  55 #define POP_SEG_SHORT 0x07
  56 #define JUMP_PC_RELATIVE 0xeb
  57 #define INT_OPCODE  0xcd
  58 #define INT3_OPCODE 0xcc
  59 /* The opcode for the fwait instruction, which disassembler treats as a
  60    prefix when it can.  */
  61 #define FWAIT_OPCODE 0x9b
  62
  63 /* Instruction prefixes.
  64    NOTE: For certain SSE* instructions, 0x66,0xf2,0xf3 are treated as
  65    part of the opcode.  Other prefixes may still appear between them
  66    and the 0x0f part of the opcode.  */
  67 #define ADDR_PREFIX_OPCODE 0x67
  68 #define DATA_PREFIX_OPCODE 0x66
  69 #define LOCK_PREFIX_OPCODE 0xf0
  70 #define CS_PREFIX_OPCODE 0x2e
  71 #define DS_PREFIX_OPCODE 0x3e
  72 #define ES_PREFIX_OPCODE 0x26
  73 #define FS_PREFIX_OPCODE 0x64
  74 #define GS_PREFIX_OPCODE 0x65
  75 #define SS_PREFIX_OPCODE 0x36
  76 #define REPNE_PREFIX_OPCODE 0xf2
  77 #define REPE_PREFIX_OPCODE  0xf3
  78
  79 #define TWO_BYTE_OPCODE_ESCAPE 0x0f
  80 #define NOP_OPCODE (char) 0x90
  81
  82 /* register numbers */
  83 #define EAX_REG_NUM 0
  84 #define ECX_REG_NUM 1
  85 #define EDX_REG_NUM 2
  86 #define EBX_REG_NUM 3
  87 #define ESP_REG_NUM 4
  88 #define EBP_REG_NUM 5
  89 #define ESI_REG_NUM 6
  90 #define EDI_REG_NUM 7
  91
  92 /* modrm_byte.regmem for twobyte escape */
  93 #define ESCAPE_TO_TWO_BYTE_ADDRESSING ESP_REG_NUM
  94 /* index_base_byte.index for no index register addressing */
  95 #define NO_INDEX_REGISTER ESP_REG_NUM
  96 /* index_base_byte.base for no base register addressing */
  97 #define NO_BASE_REGISTER EBP_REG_NUM
  98 #define NO_BASE_REGISTER_16 6
  99
 100 /* modrm.mode = REGMEM_FIELD_HAS_REG when a register is in there */
 101 #define REGMEM_FIELD_HAS_REG 0x3/* always = 0x3 */
 102 #define REGMEM_FIELD_HAS_MEM (~REGMEM_FIELD_HAS_REG)
 103
 104 /* Extract fields from the mod/rm byte.  */
 105 #define MODRM_MOD_FIELD(modrm) (((modrm) >> 6) & 3)
 106 #define MODRM_REG_FIELD(modrm) (((modrm) >> 3) & 7)
 107 #define MODRM_RM_FIELD(modrm)  (((modrm) >> 0) & 7)
 108
 109 /* Extract fields from the sib byte.  */
 110 #define SIB_SCALE_FIELD(sib) (((sib) >> 6) & 3)
 111 #define SIB_INDEX_FIELD(sib) (((sib) >> 3) & 7)
 112 #define SIB_BASE_FIELD(sib)  (((sib) >> 0) & 7)
 113
 114 /* x86-64 extension prefix.  */
 115 #define REX_OPCODE      0x40
 116
 117 /* Non-zero if OPCODE is the rex prefix.  */
 118 #define REX_PREFIX_P(opcode) (((opcode) & 0xf0) == REX_OPCODE)
 119
 120 /* Indicates 64 bit operand size.  */
 121 #define REX_W   8
 122 /* High extension to reg field of modrm byte.  */
 123 #define REX_R   4
 124 /* High extension to SIB index field.  */
 125 #define REX_X   2
 126 /* High extension to base field of modrm or SIB, or reg field of opcode.  */
 127 #define REX_B   1
 128
 129 /* max operands per insn */
 130 #define MAX_OPERANDS 5
 131
 132 /* max immediates per insn (lcall, ljmp, insertq, extrq) */
 133 #define MAX_IMMEDIATE_OPERANDS 2
 134
 135 /* max memory refs per insn (string ops) */
 136 #define MAX_MEMORY_OPERANDS 2
 137
 138 /* max size of insn mnemonics.  */
 139 #define MAX_MNEM_SIZE 20
 140
 141 /* max size of register name in insn mnemonics.  */
 142 #define MAX_REG_NAME_SIZE 8
 143
 144 #endif /* OPCODE_I386_H */