1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
6 This file is part of the GNU opcodes library.
8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
24 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
26 modified by John Hassey (hassey@dg-rtp.dg.com)
27 x86-64 support added by Jan Hubicka (jh@suse.cz)
28 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
30 /* The main tables describing the instructions is essentially a copy
31 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
32 Programmers Manual. Usually, there is a capital letter, followed
33 by a small letter. The capital letter tell the addressing mode,
34 and the small letter tells about the operand size. Refer to
35 the Intel manual for details. */
40 #include "opcode/i386.h"
41 #include "libiberty.h"
45 static int print_insn (bfd_vma
, disassemble_info
*);
46 static void dofloat (int);
47 static void OP_ST (int, int);
48 static void OP_STi (int, int);
49 static int putop (const char *, int);
50 static void oappend (const char *);
51 static void append_seg (void);
52 static void OP_indirE (int, int);
53 static void print_operand_value (char *, int, bfd_vma
);
54 static void OP_E_register (int, int);
55 static void OP_E_memory (int, int);
56 static void print_displacement (char *, bfd_vma
);
57 static void OP_E (int, int);
58 static void OP_G (int, int);
59 static bfd_vma
get64 (void);
60 static bfd_signed_vma
get32 (void);
61 static bfd_signed_vma
get32s (void);
62 static int get16 (void);
63 static void set_op (bfd_vma
, int);
64 static void OP_Skip_MODRM (int, int);
65 static void OP_REG (int, int);
66 static void OP_IMREG (int, int);
67 static void OP_I (int, int);
68 static void OP_I64 (int, int);
69 static void OP_sI (int, int);
70 static void OP_J (int, int);
71 static void OP_SEG (int, int);
72 static void OP_DIR (int, int);
73 static void OP_OFF (int, int);
74 static void OP_OFF64 (int, int);
75 static void ptr_reg (int, int);
76 static void OP_ESreg (int, int);
77 static void OP_DSreg (int, int);
78 static void OP_C (int, int);
79 static void OP_D (int, int);
80 static void OP_T (int, int);
81 static void OP_R (int, int);
82 static void OP_MMX (int, int);
83 static void OP_XMM (int, int);
84 static void OP_EM (int, int);
85 static void OP_EX (int, int);
86 static void OP_EMC (int,int);
87 static void OP_MXC (int,int);
88 static void OP_MS (int, int);
89 static void OP_XS (int, int);
90 static void OP_M (int, int);
91 static void OP_VEX (int, int);
92 static void OP_EX_Vex (int, int);
93 static void OP_EX_VexW (int, int);
94 static void OP_XMM_Vex (int, int);
95 static void OP_XMM_VexW (int, int);
96 static void OP_REG_VexI4 (int, int);
97 static void PCLMUL_Fixup (int, int);
98 static void VEXI4_Fixup (int, int);
99 static void VZERO_Fixup (int, int);
100 static void VCMP_Fixup (int, int);
101 static void OP_0f07 (int, int);
102 static void OP_Monitor (int, int);
103 static void OP_Mwait (int, int);
104 static void NOP_Fixup1 (int, int);
105 static void NOP_Fixup2 (int, int);
106 static void OP_3DNowSuffix (int, int);
107 static void CMP_Fixup (int, int);
108 static void BadOp (void);
109 static void REP_Fixup (int, int);
110 static void CMPXCHG8B_Fixup (int, int);
111 static void XMM_Fixup (int, int);
112 static void CRC32_Fixup (int, int);
113 static void FXSAVE_Fixup (int, int);
114 static void OP_LWPCB_E (int, int);
115 static void OP_LWP_E (int, int);
116 static void OP_LWP_I (int, int);
117 static void OP_Vex_2src_1 (int, int);
118 static void OP_Vex_2src_2 (int, int);
120 static void MOVBE_Fixup (int, int);
123 /* Points to first byte not fetched. */
124 bfd_byte
*max_fetched
;
125 bfd_byte the_buffer
[MAX_MNEM_SIZE
];
138 enum address_mode address_mode
;
140 /* Flags for the prefixes for the current instruction. See below. */
143 /* REX prefix the current instruction. See below. */
145 /* Bits of REX we've already used. */
147 /* REX bits in original REX prefix ignored. */
148 static int rex_ignored
;
149 /* Mark parts used in the REX prefix. When we are testing for
150 empty prefix (for 8bit register REX extension), just mask it
151 out. Otherwise test for REX bit is excuse for existence of REX
152 only in case value is nonzero. */
153 #define USED_REX(value) \
158 rex_used |= (value) | REX_OPCODE; \
161 rex_used |= REX_OPCODE; \
164 /* Flags for prefixes which we somehow handled when printing the
165 current instruction. */
166 static int used_prefixes
;
168 /* Flags stored in PREFIXES. */
169 #define PREFIX_REPZ 1
170 #define PREFIX_REPNZ 2
171 #define PREFIX_LOCK 4
173 #define PREFIX_SS 0x10
174 #define PREFIX_DS 0x20
175 #define PREFIX_ES 0x40
176 #define PREFIX_FS 0x80
177 #define PREFIX_GS 0x100
178 #define PREFIX_DATA 0x200
179 #define PREFIX_ADDR 0x400
180 #define PREFIX_FWAIT 0x800
182 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
183 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
185 #define FETCH_DATA(info, addr) \
186 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
187 ? 1 : fetch_data ((info), (addr)))
190 fetch_data (struct disassemble_info
*info
, bfd_byte
*addr
)
193 struct dis_private
*priv
= (struct dis_private
*) info
->private_data
;
194 bfd_vma start
= priv
->insn_start
+ (priv
->max_fetched
- priv
->the_buffer
);
196 if (addr
<= priv
->the_buffer
+ MAX_MNEM_SIZE
)
197 status
= (*info
->read_memory_func
) (start
,
199 addr
- priv
->max_fetched
,
205 /* If we did manage to read at least one byte, then
206 print_insn_i386 will do something sensible. Otherwise, print
207 an error. We do that here because this is where we know
209 if (priv
->max_fetched
== priv
->the_buffer
)
210 (*info
->memory_error_func
) (status
, start
, info
);
211 longjmp (priv
->bailout
, 1);
214 priv
->max_fetched
= addr
;
218 #define XX { NULL, 0 }
219 #define Bad_Opcode NULL, { { NULL, 0 } }
221 #define Eb { OP_E, b_mode }
222 #define EbS { OP_E, b_swap_mode }
223 #define Ev { OP_E, v_mode }
224 #define EvS { OP_E, v_swap_mode }
225 #define Ed { OP_E, d_mode }
226 #define Edq { OP_E, dq_mode }
227 #define Edqw { OP_E, dqw_mode }
228 #define Edqb { OP_E, dqb_mode }
229 #define Edqd { OP_E, dqd_mode }
230 #define Eq { OP_E, q_mode }
231 #define indirEv { OP_indirE, stack_v_mode }
232 #define indirEp { OP_indirE, f_mode }
233 #define stackEv { OP_E, stack_v_mode }
234 #define Em { OP_E, m_mode }
235 #define Ew { OP_E, w_mode }
236 #define M { OP_M, 0 } /* lea, lgdt, etc. */
237 #define Ma { OP_M, a_mode }
238 #define Mb { OP_M, b_mode }
239 #define Md { OP_M, d_mode }
240 #define Mo { OP_M, o_mode }
241 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
242 #define Mq { OP_M, q_mode }
243 #define Mx { OP_M, x_mode }
244 #define Mxmm { OP_M, xmm_mode }
245 #define Gb { OP_G, b_mode }
246 #define Gv { OP_G, v_mode }
247 #define Gd { OP_G, d_mode }
248 #define Gdq { OP_G, dq_mode }
249 #define Gm { OP_G, m_mode }
250 #define Gw { OP_G, w_mode }
251 #define Rd { OP_R, d_mode }
252 #define Rm { OP_R, m_mode }
253 #define Ib { OP_I, b_mode }
254 #define sIb { OP_sI, b_mode } /* sign extened byte */
255 #define Iv { OP_I, v_mode }
256 #define Iq { OP_I, q_mode }
257 #define Iv64 { OP_I64, v_mode }
258 #define Iw { OP_I, w_mode }
259 #define I1 { OP_I, const_1_mode }
260 #define Jb { OP_J, b_mode }
261 #define Jv { OP_J, v_mode }
262 #define Cm { OP_C, m_mode }
263 #define Dm { OP_D, m_mode }
264 #define Td { OP_T, d_mode }
265 #define Skip_MODRM { OP_Skip_MODRM, 0 }
267 #define RMeAX { OP_REG, eAX_reg }
268 #define RMeBX { OP_REG, eBX_reg }
269 #define RMeCX { OP_REG, eCX_reg }
270 #define RMeDX { OP_REG, eDX_reg }
271 #define RMeSP { OP_REG, eSP_reg }
272 #define RMeBP { OP_REG, eBP_reg }
273 #define RMeSI { OP_REG, eSI_reg }
274 #define RMeDI { OP_REG, eDI_reg }
275 #define RMrAX { OP_REG, rAX_reg }
276 #define RMrBX { OP_REG, rBX_reg }
277 #define RMrCX { OP_REG, rCX_reg }
278 #define RMrDX { OP_REG, rDX_reg }
279 #define RMrSP { OP_REG, rSP_reg }
280 #define RMrBP { OP_REG, rBP_reg }
281 #define RMrSI { OP_REG, rSI_reg }
282 #define RMrDI { OP_REG, rDI_reg }
283 #define RMAL { OP_REG, al_reg }
284 #define RMAL { OP_REG, al_reg }
285 #define RMCL { OP_REG, cl_reg }
286 #define RMDL { OP_REG, dl_reg }
287 #define RMBL { OP_REG, bl_reg }
288 #define RMAH { OP_REG, ah_reg }
289 #define RMCH { OP_REG, ch_reg }
290 #define RMDH { OP_REG, dh_reg }
291 #define RMBH { OP_REG, bh_reg }
292 #define RMAX { OP_REG, ax_reg }
293 #define RMDX { OP_REG, dx_reg }
295 #define eAX { OP_IMREG, eAX_reg }
296 #define eBX { OP_IMREG, eBX_reg }
297 #define eCX { OP_IMREG, eCX_reg }
298 #define eDX { OP_IMREG, eDX_reg }
299 #define eSP { OP_IMREG, eSP_reg }
300 #define eBP { OP_IMREG, eBP_reg }
301 #define eSI { OP_IMREG, eSI_reg }
302 #define eDI { OP_IMREG, eDI_reg }
303 #define AL { OP_IMREG, al_reg }
304 #define CL { OP_IMREG, cl_reg }
305 #define DL { OP_IMREG, dl_reg }
306 #define BL { OP_IMREG, bl_reg }
307 #define AH { OP_IMREG, ah_reg }
308 #define CH { OP_IMREG, ch_reg }
309 #define DH { OP_IMREG, dh_reg }
310 #define BH { OP_IMREG, bh_reg }
311 #define AX { OP_IMREG, ax_reg }
312 #define DX { OP_IMREG, dx_reg }
313 #define zAX { OP_IMREG, z_mode_ax_reg }
314 #define indirDX { OP_IMREG, indir_dx_reg }
316 #define Sw { OP_SEG, w_mode }
317 #define Sv { OP_SEG, v_mode }
318 #define Ap { OP_DIR, 0 }
319 #define Ob { OP_OFF64, b_mode }
320 #define Ov { OP_OFF64, v_mode }
321 #define Xb { OP_DSreg, eSI_reg }
322 #define Xv { OP_DSreg, eSI_reg }
323 #define Xz { OP_DSreg, eSI_reg }
324 #define Yb { OP_ESreg, eDI_reg }
325 #define Yv { OP_ESreg, eDI_reg }
326 #define DSBX { OP_DSreg, eBX_reg }
328 #define es { OP_REG, es_reg }
329 #define ss { OP_REG, ss_reg }
330 #define cs { OP_REG, cs_reg }
331 #define ds { OP_REG, ds_reg }
332 #define fs { OP_REG, fs_reg }
333 #define gs { OP_REG, gs_reg }
335 #define MX { OP_MMX, 0 }
336 #define XM { OP_XMM, 0 }
337 #define XMM { OP_XMM, xmm_mode }
338 #define EM { OP_EM, v_mode }
339 #define EMS { OP_EM, v_swap_mode }
340 #define EMd { OP_EM, d_mode }
341 #define EMx { OP_EM, x_mode }
342 #define EXw { OP_EX, w_mode }
343 #define EXd { OP_EX, d_mode }
344 #define EXdS { OP_EX, d_swap_mode }
345 #define EXq { OP_EX, q_mode }
346 #define EXqS { OP_EX, q_swap_mode }
347 #define EXx { OP_EX, x_mode }
348 #define EXxS { OP_EX, x_swap_mode }
349 #define EXxmm { OP_EX, xmm_mode }
350 #define EXxmmq { OP_EX, xmmq_mode }
351 #define EXymmq { OP_EX, ymmq_mode }
352 #define EXVexWdq { OP_EX, vex_w_dq_mode }
353 #define MS { OP_MS, v_mode }
354 #define XS { OP_XS, v_mode }
355 #define EMCq { OP_EMC, q_mode }
356 #define MXC { OP_MXC, 0 }
357 #define OPSUF { OP_3DNowSuffix, 0 }
358 #define CMP { CMP_Fixup, 0 }
359 #define XMM0 { XMM_Fixup, 0 }
360 #define FXSAVE { FXSAVE_Fixup, 0 }
361 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
362 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
364 #define Vex { OP_VEX, vex_mode }
365 #define Vex128 { OP_VEX, vex128_mode }
366 #define Vex256 { OP_VEX, vex256_mode }
367 #define VexI4 { VEXI4_Fixup, 0}
368 #define EXdVex { OP_EX_Vex, d_mode }
369 #define EXdVexS { OP_EX_Vex, d_swap_mode }
370 #define EXqVex { OP_EX_Vex, q_mode }
371 #define EXqVexS { OP_EX_Vex, q_swap_mode }
372 #define EXVexW { OP_EX_VexW, x_mode }
373 #define EXdVexW { OP_EX_VexW, d_mode }
374 #define EXqVexW { OP_EX_VexW, q_mode }
375 #define XMVex { OP_XMM_Vex, 0 }
376 #define XMVexW { OP_XMM_VexW, 0 }
377 #define XMVexI4 { OP_REG_VexI4, x_mode }
378 #define PCLMUL { PCLMUL_Fixup, 0 }
379 #define VZERO { VZERO_Fixup, 0 }
380 #define VCMP { VCMP_Fixup, 0 }
382 /* Used handle "rep" prefix for string instructions. */
383 #define Xbr { REP_Fixup, eSI_reg }
384 #define Xvr { REP_Fixup, eSI_reg }
385 #define Ybr { REP_Fixup, eDI_reg }
386 #define Yvr { REP_Fixup, eDI_reg }
387 #define Yzr { REP_Fixup, eDI_reg }
388 #define indirDXr { REP_Fixup, indir_dx_reg }
389 #define ALr { REP_Fixup, al_reg }
390 #define eAXr { REP_Fixup, eAX_reg }
392 #define cond_jump_flag { NULL, cond_jump_mode }
393 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
395 /* bits in sizeflag */
396 #define SUFFIX_ALWAYS 4
404 /* byte operand with operand swapped */
406 /* operand size depends on prefixes */
408 /* operand size depends on prefixes with operand swapped */
412 /* double word operand */
414 /* double word operand with operand swapped */
416 /* quad word operand */
418 /* quad word operand with operand swapped */
420 /* ten-byte operand */
422 /* 16-byte XMM or 32-byte YMM operand */
424 /* 16-byte XMM or 32-byte YMM operand with operand swapped */
426 /* 16-byte XMM operand */
428 /* 16-byte XMM or quad word operand */
430 /* 32-byte YMM or quad word operand */
432 /* d_mode in 32bit, q_mode in 64bit mode. */
434 /* pair of v_mode operands */
438 /* operand size depends on REX prefixes. */
440 /* registers like dq_mode, memory like w_mode. */
442 /* 4- or 6-byte pointer operand */
445 /* v_mode for stack-related opcodes. */
447 /* non-quad operand size depends on prefixes */
449 /* 16-byte operand */
451 /* registers like dq_mode, memory like b_mode. */
453 /* registers like dq_mode, memory like d_mode. */
455 /* normal vex mode */
457 /* 128bit vex mode */
459 /* 256bit vex mode */
461 /* operand size depends on the VEX.W bit. */
527 #define FLOAT NULL, { { NULL, FLOATCODE } }
529 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }
530 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
531 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
532 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
533 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
534 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
535 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
536 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
537 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
538 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
539 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
540 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
658 MOD_VEX_3818_PREFIX_2
,
659 MOD_VEX_3819_PREFIX_2
,
660 MOD_VEX_381A_PREFIX_2
,
661 MOD_VEX_382A_PREFIX_2
,
662 MOD_VEX_382C_PREFIX_2
,
663 MOD_VEX_382D_PREFIX_2
,
664 MOD_VEX_382E_PREFIX_2
,
665 MOD_VEX_382F_PREFIX_2
1075 THREE_BYTE_0F38
= 0,
1230 VEX_LEN_3819_P_2_M_0
,
1231 VEX_LEN_381A_P_2_M_0
,
1243 VEX_LEN_382A_P_2_M_0
,
1559 typedef void (*op_rtn
) (int bytemode
, int sizeflag
);
1570 /* Upper case letters in the instruction names here are macros.
1571 'A' => print 'b' if no register operands or suffix_always is true
1572 'B' => print 'b' if suffix_always is true
1573 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
1575 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
1576 suffix_always is true
1577 'E' => print 'e' if 32-bit form of jcxz
1578 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
1579 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
1580 'H' => print ",pt" or ",pn" branch hint
1581 'I' => honor following macro letter even in Intel mode (implemented only
1582 for some of the macro letters)
1584 'K' => print 'd' or 'q' if rex prefix is present.
1585 'L' => print 'l' if suffix_always is true
1586 'M' => print 'r' if intel_mnemonic is false.
1587 'N' => print 'n' if instruction has no wait "prefix"
1588 'O' => print 'd' or 'o' (or 'q' in Intel mode)
1589 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
1590 or suffix_always is true. print 'q' if rex prefix is present.
1591 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
1593 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
1594 'S' => print 'w', 'l' or 'q' if suffix_always is true
1595 'T' => print 'q' in 64bit mode and behave as 'P' otherwise
1596 'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
1597 'V' => print 'q' in 64bit mode and behave as 'S' otherwise
1598 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
1599 'X' => print 's', 'd' depending on data16 prefix (for XMM)
1600 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
1601 suffix_always is true.
1602 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
1603 '!' => change condition from true to false or from false to true.
1604 '%' => add 1 upper case letter to the macro.
1606 2 upper case letter macros:
1607 "XY" => print 'x' or 'y' if no register operands or suffix_always
1609 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
1610 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
1611 or suffix_always is true
1612 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
1613 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
1614 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
1616 Many of the above letters print nothing in Intel mode. See "putop"
1619 Braces '{' and '}', and vertical bars '|', indicate alternative
1620 mnemonic strings for AT&T and Intel. */
1622 static const struct dis386 dis386
[] = {
1624 { "addB", { Eb
, Gb
} },
1625 { "addS", { Ev
, Gv
} },
1626 { "addB", { Gb
, EbS
} },
1627 { "addS", { Gv
, EvS
} },
1628 { "addB", { AL
, Ib
} },
1629 { "addS", { eAX
, Iv
} },
1630 { X86_64_TABLE (X86_64_06
) },
1631 { X86_64_TABLE (X86_64_07
) },
1633 { "orB", { Eb
, Gb
} },
1634 { "orS", { Ev
, Gv
} },
1635 { "orB", { Gb
, EbS
} },
1636 { "orS", { Gv
, EvS
} },
1637 { "orB", { AL
, Ib
} },
1638 { "orS", { eAX
, Iv
} },
1639 { X86_64_TABLE (X86_64_0D
) },
1640 { Bad_Opcode
}, /* 0x0f extended opcode escape */
1642 { "adcB", { Eb
, Gb
} },
1643 { "adcS", { Ev
, Gv
} },
1644 { "adcB", { Gb
, EbS
} },
1645 { "adcS", { Gv
, EvS
} },
1646 { "adcB", { AL
, Ib
} },
1647 { "adcS", { eAX
, Iv
} },
1648 { X86_64_TABLE (X86_64_16
) },
1649 { X86_64_TABLE (X86_64_17
) },
1651 { "sbbB", { Eb
, Gb
} },
1652 { "sbbS", { Ev
, Gv
} },
1653 { "sbbB", { Gb
, EbS
} },
1654 { "sbbS", { Gv
, EvS
} },
1655 { "sbbB", { AL
, Ib
} },
1656 { "sbbS", { eAX
, Iv
} },
1657 { X86_64_TABLE (X86_64_1E
) },
1658 { X86_64_TABLE (X86_64_1F
) },
1660 { "andB", { Eb
, Gb
} },
1661 { "andS", { Ev
, Gv
} },
1662 { "andB", { Gb
, EbS
} },
1663 { "andS", { Gv
, EvS
} },
1664 { "andB", { AL
, Ib
} },
1665 { "andS", { eAX
, Iv
} },
1666 { Bad_Opcode
}, /* SEG ES prefix */
1667 { X86_64_TABLE (X86_64_27
) },
1669 { "subB", { Eb
, Gb
} },
1670 { "subS", { Ev
, Gv
} },
1671 { "subB", { Gb
, EbS
} },
1672 { "subS", { Gv
, EvS
} },
1673 { "subB", { AL
, Ib
} },
1674 { "subS", { eAX
, Iv
} },
1675 { Bad_Opcode
}, /* SEG CS prefix */
1676 { X86_64_TABLE (X86_64_2F
) },
1678 { "xorB", { Eb
, Gb
} },
1679 { "xorS", { Ev
, Gv
} },
1680 { "xorB", { Gb
, EbS
} },
1681 { "xorS", { Gv
, EvS
} },
1682 { "xorB", { AL
, Ib
} },
1683 { "xorS", { eAX
, Iv
} },
1684 { Bad_Opcode
}, /* SEG SS prefix */
1685 { X86_64_TABLE (X86_64_37
) },
1687 { "cmpB", { Eb
, Gb
} },
1688 { "cmpS", { Ev
, Gv
} },
1689 { "cmpB", { Gb
, EbS
} },
1690 { "cmpS", { Gv
, EvS
} },
1691 { "cmpB", { AL
, Ib
} },
1692 { "cmpS", { eAX
, Iv
} },
1693 { Bad_Opcode
}, /* SEG DS prefix */
1694 { X86_64_TABLE (X86_64_3F
) },
1696 { "inc{S|}", { RMeAX
} },
1697 { "inc{S|}", { RMeCX
} },
1698 { "inc{S|}", { RMeDX
} },
1699 { "inc{S|}", { RMeBX
} },
1700 { "inc{S|}", { RMeSP
} },
1701 { "inc{S|}", { RMeBP
} },
1702 { "inc{S|}", { RMeSI
} },
1703 { "inc{S|}", { RMeDI
} },
1705 { "dec{S|}", { RMeAX
} },
1706 { "dec{S|}", { RMeCX
} },
1707 { "dec{S|}", { RMeDX
} },
1708 { "dec{S|}", { RMeBX
} },
1709 { "dec{S|}", { RMeSP
} },
1710 { "dec{S|}", { RMeBP
} },
1711 { "dec{S|}", { RMeSI
} },
1712 { "dec{S|}", { RMeDI
} },
1714 { "pushV", { RMrAX
} },
1715 { "pushV", { RMrCX
} },
1716 { "pushV", { RMrDX
} },
1717 { "pushV", { RMrBX
} },
1718 { "pushV", { RMrSP
} },
1719 { "pushV", { RMrBP
} },
1720 { "pushV", { RMrSI
} },
1721 { "pushV", { RMrDI
} },
1723 { "popV", { RMrAX
} },
1724 { "popV", { RMrCX
} },
1725 { "popV", { RMrDX
} },
1726 { "popV", { RMrBX
} },
1727 { "popV", { RMrSP
} },
1728 { "popV", { RMrBP
} },
1729 { "popV", { RMrSI
} },
1730 { "popV", { RMrDI
} },
1732 { X86_64_TABLE (X86_64_60
) },
1733 { X86_64_TABLE (X86_64_61
) },
1734 { X86_64_TABLE (X86_64_62
) },
1735 { X86_64_TABLE (X86_64_63
) },
1736 { Bad_Opcode
}, /* seg fs */
1737 { Bad_Opcode
}, /* seg gs */
1738 { Bad_Opcode
}, /* op size prefix */
1739 { Bad_Opcode
}, /* adr size prefix */
1741 { "pushT", { Iq
} },
1742 { "imulS", { Gv
, Ev
, Iv
} },
1743 { "pushT", { sIb
} },
1744 { "imulS", { Gv
, Ev
, sIb
} },
1745 { "ins{b|}", { Ybr
, indirDX
} },
1746 { X86_64_TABLE (X86_64_6D
) },
1747 { "outs{b|}", { indirDXr
, Xb
} },
1748 { X86_64_TABLE (X86_64_6F
) },
1750 { "joH", { Jb
, XX
, cond_jump_flag
} },
1751 { "jnoH", { Jb
, XX
, cond_jump_flag
} },
1752 { "jbH", { Jb
, XX
, cond_jump_flag
} },
1753 { "jaeH", { Jb
, XX
, cond_jump_flag
} },
1754 { "jeH", { Jb
, XX
, cond_jump_flag
} },
1755 { "jneH", { Jb
, XX
, cond_jump_flag
} },
1756 { "jbeH", { Jb
, XX
, cond_jump_flag
} },
1757 { "jaH", { Jb
, XX
, cond_jump_flag
} },
1759 { "jsH", { Jb
, XX
, cond_jump_flag
} },
1760 { "jnsH", { Jb
, XX
, cond_jump_flag
} },
1761 { "jpH", { Jb
, XX
, cond_jump_flag
} },
1762 { "jnpH", { Jb
, XX
, cond_jump_flag
} },
1763 { "jlH", { Jb
, XX
, cond_jump_flag
} },
1764 { "jgeH", { Jb
, XX
, cond_jump_flag
} },
1765 { "jleH", { Jb
, XX
, cond_jump_flag
} },
1766 { "jgH", { Jb
, XX
, cond_jump_flag
} },
1768 { REG_TABLE (REG_80
) },
1769 { REG_TABLE (REG_81
) },
1771 { REG_TABLE (REG_82
) },
1772 { "testB", { Eb
, Gb
} },
1773 { "testS", { Ev
, Gv
} },
1774 { "xchgB", { Eb
, Gb
} },
1775 { "xchgS", { Ev
, Gv
} },
1777 { "movB", { Eb
, Gb
} },
1778 { "movS", { Ev
, Gv
} },
1779 { "movB", { Gb
, EbS
} },
1780 { "movS", { Gv
, EvS
} },
1781 { "movD", { Sv
, Sw
} },
1782 { MOD_TABLE (MOD_8D
) },
1783 { "movD", { Sw
, Sv
} },
1784 { REG_TABLE (REG_8F
) },
1786 { PREFIX_TABLE (PREFIX_90
) },
1787 { "xchgS", { RMeCX
, eAX
} },
1788 { "xchgS", { RMeDX
, eAX
} },
1789 { "xchgS", { RMeBX
, eAX
} },
1790 { "xchgS", { RMeSP
, eAX
} },
1791 { "xchgS", { RMeBP
, eAX
} },
1792 { "xchgS", { RMeSI
, eAX
} },
1793 { "xchgS", { RMeDI
, eAX
} },
1795 { "cW{t|}R", { XX
} },
1796 { "cR{t|}O", { XX
} },
1797 { X86_64_TABLE (X86_64_9A
) },
1798 { Bad_Opcode
}, /* fwait */
1799 { "pushfT", { XX
} },
1800 { "popfT", { XX
} },
1804 { "mov%LB", { AL
, Ob
} },
1805 { "mov%LS", { eAX
, Ov
} },
1806 { "mov%LB", { Ob
, AL
} },
1807 { "mov%LS", { Ov
, eAX
} },
1808 { "movs{b|}", { Ybr
, Xb
} },
1809 { "movs{R|}", { Yvr
, Xv
} },
1810 { "cmps{b|}", { Xb
, Yb
} },
1811 { "cmps{R|}", { Xv
, Yv
} },
1813 { "testB", { AL
, Ib
} },
1814 { "testS", { eAX
, Iv
} },
1815 { "stosB", { Ybr
, AL
} },
1816 { "stosS", { Yvr
, eAX
} },
1817 { "lodsB", { ALr
, Xb
} },
1818 { "lodsS", { eAXr
, Xv
} },
1819 { "scasB", { AL
, Yb
} },
1820 { "scasS", { eAX
, Yv
} },
1822 { "movB", { RMAL
, Ib
} },
1823 { "movB", { RMCL
, Ib
} },
1824 { "movB", { RMDL
, Ib
} },
1825 { "movB", { RMBL
, Ib
} },
1826 { "movB", { RMAH
, Ib
} },
1827 { "movB", { RMCH
, Ib
} },
1828 { "movB", { RMDH
, Ib
} },
1829 { "movB", { RMBH
, Ib
} },
1831 { "mov%LV", { RMeAX
, Iv64
} },
1832 { "mov%LV", { RMeCX
, Iv64
} },
1833 { "mov%LV", { RMeDX
, Iv64
} },
1834 { "mov%LV", { RMeBX
, Iv64
} },
1835 { "mov%LV", { RMeSP
, Iv64
} },
1836 { "mov%LV", { RMeBP
, Iv64
} },
1837 { "mov%LV", { RMeSI
, Iv64
} },
1838 { "mov%LV", { RMeDI
, Iv64
} },
1840 { REG_TABLE (REG_C0
) },
1841 { REG_TABLE (REG_C1
) },
1844 { X86_64_TABLE (X86_64_C4
) },
1845 { X86_64_TABLE (X86_64_C5
) },
1846 { REG_TABLE (REG_C6
) },
1847 { REG_TABLE (REG_C7
) },
1849 { "enterT", { Iw
, Ib
} },
1850 { "leaveT", { XX
} },
1851 { "Jret{|f}P", { Iw
} },
1852 { "Jret{|f}P", { XX
} },
1855 { X86_64_TABLE (X86_64_CE
) },
1856 { "iretP", { XX
} },
1858 { REG_TABLE (REG_D0
) },
1859 { REG_TABLE (REG_D1
) },
1860 { REG_TABLE (REG_D2
) },
1861 { REG_TABLE (REG_D3
) },
1862 { X86_64_TABLE (X86_64_D4
) },
1863 { X86_64_TABLE (X86_64_D5
) },
1865 { "xlat", { DSBX
} },
1876 { "loopneFH", { Jb
, XX
, loop_jcxz_flag
} },
1877 { "loopeFH", { Jb
, XX
, loop_jcxz_flag
} },
1878 { "loopFH", { Jb
, XX
, loop_jcxz_flag
} },
1879 { "jEcxzH", { Jb
, XX
, loop_jcxz_flag
} },
1880 { "inB", { AL
, Ib
} },
1881 { "inG", { zAX
, Ib
} },
1882 { "outB", { Ib
, AL
} },
1883 { "outG", { Ib
, zAX
} },
1885 { "callT", { Jv
} },
1887 { X86_64_TABLE (X86_64_EA
) },
1889 { "inB", { AL
, indirDX
} },
1890 { "inG", { zAX
, indirDX
} },
1891 { "outB", { indirDX
, AL
} },
1892 { "outG", { indirDX
, zAX
} },
1894 { Bad_Opcode
}, /* lock prefix */
1895 { "icebp", { XX
} },
1896 { Bad_Opcode
}, /* repne */
1897 { Bad_Opcode
}, /* repz */
1900 { REG_TABLE (REG_F6
) },
1901 { REG_TABLE (REG_F7
) },
1909 { REG_TABLE (REG_FE
) },
1910 { REG_TABLE (REG_FF
) },
1913 static const struct dis386 dis386_twobyte
[] = {
1915 { REG_TABLE (REG_0F00
) },
1916 { REG_TABLE (REG_0F01
) },
1917 { "larS", { Gv
, Ew
} },
1918 { "lslS", { Gv
, Ew
} },
1920 { "syscall", { XX
} },
1922 { "sysretP", { XX
} },
1925 { "wbinvd", { XX
} },
1929 { REG_TABLE (REG_0F0D
) },
1930 { "femms", { XX
} },
1931 { "", { MX
, EM
, OPSUF
} }, /* See OP_3DNowSuffix. */
1933 { PREFIX_TABLE (PREFIX_0F10
) },
1934 { PREFIX_TABLE (PREFIX_0F11
) },
1935 { PREFIX_TABLE (PREFIX_0F12
) },
1936 { MOD_TABLE (MOD_0F13
) },
1937 { "unpcklpX", { XM
, EXx
} },
1938 { "unpckhpX", { XM
, EXx
} },
1939 { PREFIX_TABLE (PREFIX_0F16
) },
1940 { MOD_TABLE (MOD_0F17
) },
1942 { REG_TABLE (REG_0F18
) },
1951 { MOD_TABLE (MOD_0F20
) },
1952 { MOD_TABLE (MOD_0F21
) },
1953 { MOD_TABLE (MOD_0F22
) },
1954 { MOD_TABLE (MOD_0F23
) },
1955 { MOD_TABLE (MOD_0F24
) },
1957 { MOD_TABLE (MOD_0F26
) },
1960 { "movapX", { XM
, EXx
} },
1961 { "movapX", { EXxS
, XM
} },
1962 { PREFIX_TABLE (PREFIX_0F2A
) },
1963 { PREFIX_TABLE (PREFIX_0F2B
) },
1964 { PREFIX_TABLE (PREFIX_0F2C
) },
1965 { PREFIX_TABLE (PREFIX_0F2D
) },
1966 { PREFIX_TABLE (PREFIX_0F2E
) },
1967 { PREFIX_TABLE (PREFIX_0F2F
) },
1969 { "wrmsr", { XX
} },
1970 { "rdtsc", { XX
} },
1971 { "rdmsr", { XX
} },
1972 { "rdpmc", { XX
} },
1973 { "sysenter", { XX
} },
1974 { "sysexit", { XX
} },
1976 { "getsec", { XX
} },
1978 { THREE_BYTE_TABLE (THREE_BYTE_0F38
) },
1980 { THREE_BYTE_TABLE (THREE_BYTE_0F3A
) },
1987 { "cmovoS", { Gv
, Ev
} },
1988 { "cmovnoS", { Gv
, Ev
} },
1989 { "cmovbS", { Gv
, Ev
} },
1990 { "cmovaeS", { Gv
, Ev
} },
1991 { "cmoveS", { Gv
, Ev
} },
1992 { "cmovneS", { Gv
, Ev
} },
1993 { "cmovbeS", { Gv
, Ev
} },
1994 { "cmovaS", { Gv
, Ev
} },
1996 { "cmovsS", { Gv
, Ev
} },
1997 { "cmovnsS", { Gv
, Ev
} },
1998 { "cmovpS", { Gv
, Ev
} },
1999 { "cmovnpS", { Gv
, Ev
} },
2000 { "cmovlS", { Gv
, Ev
} },
2001 { "cmovgeS", { Gv
, Ev
} },
2002 { "cmovleS", { Gv
, Ev
} },
2003 { "cmovgS", { Gv
, Ev
} },
2005 { MOD_TABLE (MOD_0F51
) },
2006 { PREFIX_TABLE (PREFIX_0F51
) },
2007 { PREFIX_TABLE (PREFIX_0F52
) },
2008 { PREFIX_TABLE (PREFIX_0F53
) },
2009 { "andpX", { XM
, EXx
} },
2010 { "andnpX", { XM
, EXx
} },
2011 { "orpX", { XM
, EXx
} },
2012 { "xorpX", { XM
, EXx
} },
2014 { PREFIX_TABLE (PREFIX_0F58
) },
2015 { PREFIX_TABLE (PREFIX_0F59
) },
2016 { PREFIX_TABLE (PREFIX_0F5A
) },
2017 { PREFIX_TABLE (PREFIX_0F5B
) },
2018 { PREFIX_TABLE (PREFIX_0F5C
) },
2019 { PREFIX_TABLE (PREFIX_0F5D
) },
2020 { PREFIX_TABLE (PREFIX_0F5E
) },
2021 { PREFIX_TABLE (PREFIX_0F5F
) },
2023 { PREFIX_TABLE (PREFIX_0F60
) },
2024 { PREFIX_TABLE (PREFIX_0F61
) },
2025 { PREFIX_TABLE (PREFIX_0F62
) },
2026 { "packsswb", { MX
, EM
} },
2027 { "pcmpgtb", { MX
, EM
} },
2028 { "pcmpgtw", { MX
, EM
} },
2029 { "pcmpgtd", { MX
, EM
} },
2030 { "packuswb", { MX
, EM
} },
2032 { "punpckhbw", { MX
, EM
} },
2033 { "punpckhwd", { MX
, EM
} },
2034 { "punpckhdq", { MX
, EM
} },
2035 { "packssdw", { MX
, EM
} },
2036 { PREFIX_TABLE (PREFIX_0F6C
) },
2037 { PREFIX_TABLE (PREFIX_0F6D
) },
2038 { "movK", { MX
, Edq
} },
2039 { PREFIX_TABLE (PREFIX_0F6F
) },
2041 { PREFIX_TABLE (PREFIX_0F70
) },
2042 { REG_TABLE (REG_0F71
) },
2043 { REG_TABLE (REG_0F72
) },
2044 { REG_TABLE (REG_0F73
) },
2045 { "pcmpeqb", { MX
, EM
} },
2046 { "pcmpeqw", { MX
, EM
} },
2047 { "pcmpeqd", { MX
, EM
} },
2050 { PREFIX_TABLE (PREFIX_0F78
) },
2051 { PREFIX_TABLE (PREFIX_0F79
) },
2052 { THREE_BYTE_TABLE (THREE_BYTE_0F7A
) },
2054 { PREFIX_TABLE (PREFIX_0F7C
) },
2055 { PREFIX_TABLE (PREFIX_0F7D
) },
2056 { PREFIX_TABLE (PREFIX_0F7E
) },
2057 { PREFIX_TABLE (PREFIX_0F7F
) },
2059 { "joH", { Jv
, XX
, cond_jump_flag
} },
2060 { "jnoH", { Jv
, XX
, cond_jump_flag
} },
2061 { "jbH", { Jv
, XX
, cond_jump_flag
} },
2062 { "jaeH", { Jv
, XX
, cond_jump_flag
} },
2063 { "jeH", { Jv
, XX
, cond_jump_flag
} },
2064 { "jneH", { Jv
, XX
, cond_jump_flag
} },
2065 { "jbeH", { Jv
, XX
, cond_jump_flag
} },
2066 { "jaH", { Jv
, XX
, cond_jump_flag
} },
2068 { "jsH", { Jv
, XX
, cond_jump_flag
} },
2069 { "jnsH", { Jv
, XX
, cond_jump_flag
} },
2070 { "jpH", { Jv
, XX
, cond_jump_flag
} },
2071 { "jnpH", { Jv
, XX
, cond_jump_flag
} },
2072 { "jlH", { Jv
, XX
, cond_jump_flag
} },
2073 { "jgeH", { Jv
, XX
, cond_jump_flag
} },
2074 { "jleH", { Jv
, XX
, cond_jump_flag
} },
2075 { "jgH", { Jv
, XX
, cond_jump_flag
} },
2078 { "setno", { Eb
} },
2080 { "setae", { Eb
} },
2082 { "setne", { Eb
} },
2083 { "setbe", { Eb
} },
2087 { "setns", { Eb
} },
2089 { "setnp", { Eb
} },
2091 { "setge", { Eb
} },
2092 { "setle", { Eb
} },
2095 { "pushT", { fs
} },
2097 { "cpuid", { XX
} },
2098 { "btS", { Ev
, Gv
} },
2099 { "shldS", { Ev
, Gv
, Ib
} },
2100 { "shldS", { Ev
, Gv
, CL
} },
2101 { REG_TABLE (REG_0FA6
) },
2102 { REG_TABLE (REG_0FA7
) },
2104 { "pushT", { gs
} },
2107 { "btsS", { Ev
, Gv
} },
2108 { "shrdS", { Ev
, Gv
, Ib
} },
2109 { "shrdS", { Ev
, Gv
, CL
} },
2110 { REG_TABLE (REG_0FAE
) },
2111 { "imulS", { Gv
, Ev
} },
2113 { "cmpxchgB", { Eb
, Gb
} },
2114 { "cmpxchgS", { Ev
, Gv
} },
2115 { MOD_TABLE (MOD_0FB2
) },
2116 { "btrS", { Ev
, Gv
} },
2117 { MOD_TABLE (MOD_0FB4
) },
2118 { MOD_TABLE (MOD_0FB5
) },
2119 { "movz{bR|x}", { Gv
, Eb
} },
2120 { "movz{wR|x}", { Gv
, Ew
} }, /* yes, there really is movzww ! */
2122 { PREFIX_TABLE (PREFIX_0FB8
) },
2124 { REG_TABLE (REG_0FBA
) },
2125 { "btcS", { Ev
, Gv
} },
2126 { "bsfS", { Gv
, Ev
} },
2127 { PREFIX_TABLE (PREFIX_0FBD
) },
2128 { "movs{bR|x}", { Gv
, Eb
} },
2129 { "movs{wR|x}", { Gv
, Ew
} }, /* yes, there really is movsww ! */
2131 { "xaddB", { Eb
, Gb
} },
2132 { "xaddS", { Ev
, Gv
} },
2133 { PREFIX_TABLE (PREFIX_0FC2
) },
2134 { PREFIX_TABLE (PREFIX_0FC3
) },
2135 { "pinsrw", { MX
, Edqw
, Ib
} },
2136 { "pextrw", { Gdq
, MS
, Ib
} },
2137 { "shufpX", { XM
, EXx
, Ib
} },
2138 { REG_TABLE (REG_0FC7
) },
2140 { "bswap", { RMeAX
} },
2141 { "bswap", { RMeCX
} },
2142 { "bswap", { RMeDX
} },
2143 { "bswap", { RMeBX
} },
2144 { "bswap", { RMeSP
} },
2145 { "bswap", { RMeBP
} },
2146 { "bswap", { RMeSI
} },
2147 { "bswap", { RMeDI
} },
2149 { PREFIX_TABLE (PREFIX_0FD0
) },
2150 { "psrlw", { MX
, EM
} },
2151 { "psrld", { MX
, EM
} },
2152 { "psrlq", { MX
, EM
} },
2153 { "paddq", { MX
, EM
} },
2154 { "pmullw", { MX
, EM
} },
2155 { PREFIX_TABLE (PREFIX_0FD6
) },
2156 { MOD_TABLE (MOD_0FD7
) },
2158 { "psubusb", { MX
, EM
} },
2159 { "psubusw", { MX
, EM
} },
2160 { "pminub", { MX
, EM
} },
2161 { "pand", { MX
, EM
} },
2162 { "paddusb", { MX
, EM
} },
2163 { "paddusw", { MX
, EM
} },
2164 { "pmaxub", { MX
, EM
} },
2165 { "pandn", { MX
, EM
} },
2167 { "pavgb", { MX
, EM
} },
2168 { "psraw", { MX
, EM
} },
2169 { "psrad", { MX
, EM
} },
2170 { "pavgw", { MX
, EM
} },
2171 { "pmulhuw", { MX
, EM
} },
2172 { "pmulhw", { MX
, EM
} },
2173 { PREFIX_TABLE (PREFIX_0FE6
) },
2174 { PREFIX_TABLE (PREFIX_0FE7
) },
2176 { "psubsb", { MX
, EM
} },
2177 { "psubsw", { MX
, EM
} },
2178 { "pminsw", { MX
, EM
} },
2179 { "por", { MX
, EM
} },
2180 { "paddsb", { MX
, EM
} },
2181 { "paddsw", { MX
, EM
} },
2182 { "pmaxsw", { MX
, EM
} },
2183 { "pxor", { MX
, EM
} },
2185 { PREFIX_TABLE (PREFIX_0FF0
) },
2186 { "psllw", { MX
, EM
} },
2187 { "pslld", { MX
, EM
} },
2188 { "psllq", { MX
, EM
} },
2189 { "pmuludq", { MX
, EM
} },
2190 { "pmaddwd", { MX
, EM
} },
2191 { "psadbw", { MX
, EM
} },
2192 { PREFIX_TABLE (PREFIX_0FF7
) },
2194 { "psubb", { MX
, EM
} },
2195 { "psubw", { MX
, EM
} },
2196 { "psubd", { MX
, EM
} },
2197 { "psubq", { MX
, EM
} },
2198 { "paddb", { MX
, EM
} },
2199 { "paddw", { MX
, EM
} },
2200 { "paddd", { MX
, EM
} },
2204 static const unsigned char onebyte_has_modrm
[256] = {
2205 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2206 /* ------------------------------- */
2207 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2208 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2209 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2210 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2211 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2212 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2213 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2214 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2215 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2216 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2217 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2218 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2219 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2220 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2221 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2222 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
2223 /* ------------------------------- */
2224 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2227 static const unsigned char twobyte_has_modrm
[256] = {
2228 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2229 /* ------------------------------- */
2230 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2231 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2232 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2233 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2234 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2235 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2236 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2237 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2238 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2239 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2240 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2241 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
2242 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2243 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2244 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2245 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
2246 /* ------------------------------- */
2247 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2250 static char obuf
[100];
2252 static char *mnemonicendp
;
2253 static char scratchbuf
[100];
2254 static unsigned char *start_codep
;
2255 static unsigned char *insn_codep
;
2256 static unsigned char *codep
;
2257 static int last_lock_prefix
;
2258 static int last_repz_prefix
;
2259 static int last_repnz_prefix
;
2260 static int last_data_prefix
;
2261 static int last_addr_prefix
;
2262 static int last_rex_prefix
;
2263 static int last_seg_prefix
;
2264 #define MAX_CODE_LENGTH 15
2265 /* We can up to 14 prefixes since the maximum instruction length is
2267 static int all_prefixes
[MAX_CODE_LENGTH
- 1];
2268 static disassemble_info
*the_info
;
2276 static unsigned char need_modrm
;
2279 int register_specifier
;
2285 static unsigned char need_vex
;
2286 static unsigned char need_vex_reg
;
2287 static unsigned char vex_w_done
;
2295 /* If we are accessing mod/rm/reg without need_modrm set, then the
2296 values are stale. Hitting this abort likely indicates that you
2297 need to update onebyte_has_modrm or twobyte_has_modrm. */
2298 #define MODRM_CHECK if (!need_modrm) abort ()
2300 static const char **names64
;
2301 static const char **names32
;
2302 static const char **names16
;
2303 static const char **names8
;
2304 static const char **names8rex
;
2305 static const char **names_seg
;
2306 static const char *index64
;
2307 static const char *index32
;
2308 static const char **index16
;
2310 static const char *intel_names64
[] = {
2311 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2312 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2314 static const char *intel_names32
[] = {
2315 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2316 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2318 static const char *intel_names16
[] = {
2319 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2320 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2322 static const char *intel_names8
[] = {
2323 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2325 static const char *intel_names8rex
[] = {
2326 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2327 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2329 static const char *intel_names_seg
[] = {
2330 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2332 static const char *intel_index64
= "riz";
2333 static const char *intel_index32
= "eiz";
2334 static const char *intel_index16
[] = {
2335 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2338 static const char *att_names64
[] = {
2339 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2340 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2342 static const char *att_names32
[] = {
2343 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2344 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2346 static const char *att_names16
[] = {
2347 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2348 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2350 static const char *att_names8
[] = {
2351 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2353 static const char *att_names8rex
[] = {
2354 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2355 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2357 static const char *att_names_seg
[] = {
2358 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2360 static const char *att_index64
= "%riz";
2361 static const char *att_index32
= "%eiz";
2362 static const char *att_index16
[] = {
2363 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2366 static const char **names_mm
;
2367 static const char *intel_names_mm
[] = {
2368 "mm0", "mm1", "mm2", "mm3",
2369 "mm4", "mm5", "mm6", "mm7"
2371 static const char *att_names_mm
[] = {
2372 "%mm0", "%mm1", "%mm2", "%mm3",
2373 "%mm4", "%mm5", "%mm6", "%mm7"
2376 static const char **names_xmm
;
2377 static const char *intel_names_xmm
[] = {
2378 "xmm0", "xmm1", "xmm2", "xmm3",
2379 "xmm4", "xmm5", "xmm6", "xmm7",
2380 "xmm8", "xmm9", "xmm10", "xmm11",
2381 "xmm12", "xmm13", "xmm14", "xmm15"
2383 static const char *att_names_xmm
[] = {
2384 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
2385 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
2386 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
2387 "%xmm12", "%xmm13", "%xmm14", "%xmm15"
2390 static const char **names_ymm
;
2391 static const char *intel_names_ymm
[] = {
2392 "ymm0", "ymm1", "ymm2", "ymm3",
2393 "ymm4", "ymm5", "ymm6", "ymm7",
2394 "ymm8", "ymm9", "ymm10", "ymm11",
2395 "ymm12", "ymm13", "ymm14", "ymm15"
2397 static const char *att_names_ymm
[] = {
2398 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
2399 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
2400 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
2401 "%ymm12", "%ymm13", "%ymm14", "%ymm15"
2404 static const struct dis386 reg_table
[][8] = {
2407 { "addA", { Eb
, Ib
} },
2408 { "orA", { Eb
, Ib
} },
2409 { "adcA", { Eb
, Ib
} },
2410 { "sbbA", { Eb
, Ib
} },
2411 { "andA", { Eb
, Ib
} },
2412 { "subA", { Eb
, Ib
} },
2413 { "xorA", { Eb
, Ib
} },
2414 { "cmpA", { Eb
, Ib
} },
2418 { "addQ", { Ev
, Iv
} },
2419 { "orQ", { Ev
, Iv
} },
2420 { "adcQ", { Ev
, Iv
} },
2421 { "sbbQ", { Ev
, Iv
} },
2422 { "andQ", { Ev
, Iv
} },
2423 { "subQ", { Ev
, Iv
} },
2424 { "xorQ", { Ev
, Iv
} },
2425 { "cmpQ", { Ev
, Iv
} },
2429 { "addQ", { Ev
, sIb
} },
2430 { "orQ", { Ev
, sIb
} },
2431 { "adcQ", { Ev
, sIb
} },
2432 { "sbbQ", { Ev
, sIb
} },
2433 { "andQ", { Ev
, sIb
} },
2434 { "subQ", { Ev
, sIb
} },
2435 { "xorQ", { Ev
, sIb
} },
2436 { "cmpQ", { Ev
, sIb
} },
2440 { "popU", { stackEv
} },
2441 { XOP_8F_TABLE (XOP_09
) },
2445 { XOP_8F_TABLE (XOP_09
) },
2449 { "rolA", { Eb
, Ib
} },
2450 { "rorA", { Eb
, Ib
} },
2451 { "rclA", { Eb
, Ib
} },
2452 { "rcrA", { Eb
, Ib
} },
2453 { "shlA", { Eb
, Ib
} },
2454 { "shrA", { Eb
, Ib
} },
2456 { "sarA", { Eb
, Ib
} },
2460 { "rolQ", { Ev
, Ib
} },
2461 { "rorQ", { Ev
, Ib
} },
2462 { "rclQ", { Ev
, Ib
} },
2463 { "rcrQ", { Ev
, Ib
} },
2464 { "shlQ", { Ev
, Ib
} },
2465 { "shrQ", { Ev
, Ib
} },
2467 { "sarQ", { Ev
, Ib
} },
2471 { "movA", { Eb
, Ib
} },
2475 { "movQ", { Ev
, Iv
} },
2479 { "rolA", { Eb
, I1
} },
2480 { "rorA", { Eb
, I1
} },
2481 { "rclA", { Eb
, I1
} },
2482 { "rcrA", { Eb
, I1
} },
2483 { "shlA", { Eb
, I1
} },
2484 { "shrA", { Eb
, I1
} },
2486 { "sarA", { Eb
, I1
} },
2490 { "rolQ", { Ev
, I1
} },
2491 { "rorQ", { Ev
, I1
} },
2492 { "rclQ", { Ev
, I1
} },
2493 { "rcrQ", { Ev
, I1
} },
2494 { "shlQ", { Ev
, I1
} },
2495 { "shrQ", { Ev
, I1
} },
2497 { "sarQ", { Ev
, I1
} },
2501 { "rolA", { Eb
, CL
} },
2502 { "rorA", { Eb
, CL
} },
2503 { "rclA", { Eb
, CL
} },
2504 { "rcrA", { Eb
, CL
} },
2505 { "shlA", { Eb
, CL
} },
2506 { "shrA", { Eb
, CL
} },
2508 { "sarA", { Eb
, CL
} },
2512 { "rolQ", { Ev
, CL
} },
2513 { "rorQ", { Ev
, CL
} },
2514 { "rclQ", { Ev
, CL
} },
2515 { "rcrQ", { Ev
, CL
} },
2516 { "shlQ", { Ev
, CL
} },
2517 { "shrQ", { Ev
, CL
} },
2519 { "sarQ", { Ev
, CL
} },
2523 { "testA", { Eb
, Ib
} },
2527 { "mulA", { Eb
} }, /* Don't print the implicit %al register, */
2528 { "imulA", { Eb
} }, /* to distinguish these opcodes from other */
2529 { "divA", { Eb
} }, /* mul/imul opcodes. Do the same for div */
2530 { "idivA", { Eb
} }, /* and idiv for consistency. */
2534 { "testQ", { Ev
, Iv
} },
2538 { "mulQ", { Ev
} }, /* Don't print the implicit register. */
2539 { "imulQ", { Ev
} },
2541 { "idivQ", { Ev
} },
2552 { "callT", { indirEv
} },
2553 { "JcallT", { indirEp
} },
2554 { "jmpT", { indirEv
} },
2555 { "JjmpT", { indirEp
} },
2556 { "pushU", { stackEv
} },
2561 { "sldtD", { Sv
} },
2572 { MOD_TABLE (MOD_0F01_REG_0
) },
2573 { MOD_TABLE (MOD_0F01_REG_1
) },
2574 { MOD_TABLE (MOD_0F01_REG_2
) },
2575 { MOD_TABLE (MOD_0F01_REG_3
) },
2576 { "smswD", { Sv
} },
2579 { MOD_TABLE (MOD_0F01_REG_7
) },
2583 { "prefetch", { Eb
} },
2584 { "prefetchw", { Eb
} },
2588 { MOD_TABLE (MOD_0F18_REG_0
) },
2589 { MOD_TABLE (MOD_0F18_REG_1
) },
2590 { MOD_TABLE (MOD_0F18_REG_2
) },
2591 { MOD_TABLE (MOD_0F18_REG_3
) },
2597 { MOD_TABLE (MOD_0F71_REG_2
) },
2599 { MOD_TABLE (MOD_0F71_REG_4
) },
2601 { MOD_TABLE (MOD_0F71_REG_6
) },
2607 { MOD_TABLE (MOD_0F72_REG_2
) },
2609 { MOD_TABLE (MOD_0F72_REG_4
) },
2611 { MOD_TABLE (MOD_0F72_REG_6
) },
2617 { MOD_TABLE (MOD_0F73_REG_2
) },
2618 { MOD_TABLE (MOD_0F73_REG_3
) },
2621 { MOD_TABLE (MOD_0F73_REG_6
) },
2622 { MOD_TABLE (MOD_0F73_REG_7
) },
2626 { "montmul", { { OP_0f07
, 0 } } },
2627 { "xsha1", { { OP_0f07
, 0 } } },
2628 { "xsha256", { { OP_0f07
, 0 } } },
2632 { "xstore-rng", { { OP_0f07
, 0 } } },
2633 { "xcrypt-ecb", { { OP_0f07
, 0 } } },
2634 { "xcrypt-cbc", { { OP_0f07
, 0 } } },
2635 { "xcrypt-ctr", { { OP_0f07
, 0 } } },
2636 { "xcrypt-cfb", { { OP_0f07
, 0 } } },
2637 { "xcrypt-ofb", { { OP_0f07
, 0 } } },
2641 { MOD_TABLE (MOD_0FAE_REG_0
) },
2642 { MOD_TABLE (MOD_0FAE_REG_1
) },
2643 { MOD_TABLE (MOD_0FAE_REG_2
) },
2644 { MOD_TABLE (MOD_0FAE_REG_3
) },
2645 { MOD_TABLE (MOD_0FAE_REG_4
) },
2646 { MOD_TABLE (MOD_0FAE_REG_5
) },
2647 { MOD_TABLE (MOD_0FAE_REG_6
) },
2648 { MOD_TABLE (MOD_0FAE_REG_7
) },
2656 { "btQ", { Ev
, Ib
} },
2657 { "btsQ", { Ev
, Ib
} },
2658 { "btrQ", { Ev
, Ib
} },
2659 { "btcQ", { Ev
, Ib
} },
2664 { "cmpxchg8b", { { CMPXCHG8B_Fixup
, q_mode
} } },
2669 { MOD_TABLE (MOD_0FC7_REG_6
) },
2670 { MOD_TABLE (MOD_0FC7_REG_7
) },
2676 { MOD_TABLE (MOD_VEX_71_REG_2
) },
2678 { MOD_TABLE (MOD_VEX_71_REG_4
) },
2680 { MOD_TABLE (MOD_VEX_71_REG_6
) },
2686 { MOD_TABLE (MOD_VEX_72_REG_2
) },
2688 { MOD_TABLE (MOD_VEX_72_REG_4
) },
2690 { MOD_TABLE (MOD_VEX_72_REG_6
) },
2696 { MOD_TABLE (MOD_VEX_73_REG_2
) },
2697 { MOD_TABLE (MOD_VEX_73_REG_3
) },
2700 { MOD_TABLE (MOD_VEX_73_REG_6
) },
2701 { MOD_TABLE (MOD_VEX_73_REG_7
) },
2707 { MOD_TABLE (MOD_VEX_AE_REG_2
) },
2708 { MOD_TABLE (MOD_VEX_AE_REG_3
) },
2712 { "llwpcb", { { OP_LWPCB_E
, 0 } } },
2713 { "slwpcb", { { OP_LWPCB_E
, 0 } } },
2717 { "lwpins", { { OP_LWP_E
, 0 }, Ed
, { OP_LWP_I
, 0 } } },
2718 { "lwpval", { { OP_LWP_E
, 0 }, Ed
, { OP_LWP_I
, 0 } } },
2722 static const struct dis386 prefix_table
[][4] = {
2725 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} } },
2726 { "pause", { XX
} },
2727 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} } },
2732 { "movups", { XM
, EXx
} },
2733 { "movss", { XM
, EXd
} },
2734 { "movupd", { XM
, EXx
} },
2735 { "movsd", { XM
, EXq
} },
2740 { "movups", { EXxS
, XM
} },
2741 { "movss", { EXdS
, XM
} },
2742 { "movupd", { EXxS
, XM
} },
2743 { "movsd", { EXqS
, XM
} },
2748 { MOD_TABLE (MOD_0F12_PREFIX_0
) },
2749 { "movsldup", { XM
, EXx
} },
2750 { "movlpd", { XM
, EXq
} },
2751 { "movddup", { XM
, EXq
} },
2756 { MOD_TABLE (MOD_0F16_PREFIX_0
) },
2757 { "movshdup", { XM
, EXx
} },
2758 { "movhpd", { XM
, EXq
} },
2763 { "cvtpi2ps", { XM
, EMCq
} },
2764 { "cvtsi2ss%LQ", { XM
, Ev
} },
2765 { "cvtpi2pd", { XM
, EMCq
} },
2766 { "cvtsi2sd%LQ", { XM
, Ev
} },
2771 { MOD_TABLE (MOD_0F2B_PREFIX_0
) },
2772 { MOD_TABLE (MOD_0F2B_PREFIX_1
) },
2773 { MOD_TABLE (MOD_0F2B_PREFIX_2
) },
2774 { MOD_TABLE (MOD_0F2B_PREFIX_3
) },
2779 { "cvttps2pi", { MXC
, EXq
} },
2780 { "cvttss2siY", { Gv
, EXd
} },
2781 { "cvttpd2pi", { MXC
, EXx
} },
2782 { "cvttsd2siY", { Gv
, EXq
} },
2787 { "cvtps2pi", { MXC
, EXq
} },
2788 { "cvtss2siY", { Gv
, EXd
} },
2789 { "cvtpd2pi", { MXC
, EXx
} },
2790 { "cvtsd2siY", { Gv
, EXq
} },
2795 { "ucomiss",{ XM
, EXd
} },
2797 { "ucomisd",{ XM
, EXq
} },
2802 { "comiss", { XM
, EXd
} },
2804 { "comisd", { XM
, EXq
} },
2809 { "sqrtps", { XM
, EXx
} },
2810 { "sqrtss", { XM
, EXd
} },
2811 { "sqrtpd", { XM
, EXx
} },
2812 { "sqrtsd", { XM
, EXq
} },
2817 { "rsqrtps",{ XM
, EXx
} },
2818 { "rsqrtss",{ XM
, EXd
} },
2823 { "rcpps", { XM
, EXx
} },
2824 { "rcpss", { XM
, EXd
} },
2829 { "addps", { XM
, EXx
} },
2830 { "addss", { XM
, EXd
} },
2831 { "addpd", { XM
, EXx
} },
2832 { "addsd", { XM
, EXq
} },
2837 { "mulps", { XM
, EXx
} },
2838 { "mulss", { XM
, EXd
} },
2839 { "mulpd", { XM
, EXx
} },
2840 { "mulsd", { XM
, EXq
} },
2845 { "cvtps2pd", { XM
, EXq
} },
2846 { "cvtss2sd", { XM
, EXd
} },
2847 { "cvtpd2ps", { XM
, EXx
} },
2848 { "cvtsd2ss", { XM
, EXq
} },
2853 { "cvtdq2ps", { XM
, EXx
} },
2854 { "cvttps2dq", { XM
, EXx
} },
2855 { "cvtps2dq", { XM
, EXx
} },
2860 { "subps", { XM
, EXx
} },
2861 { "subss", { XM
, EXd
} },
2862 { "subpd", { XM
, EXx
} },
2863 { "subsd", { XM
, EXq
} },
2868 { "minps", { XM
, EXx
} },
2869 { "minss", { XM
, EXd
} },
2870 { "minpd", { XM
, EXx
} },
2871 { "minsd", { XM
, EXq
} },
2876 { "divps", { XM
, EXx
} },
2877 { "divss", { XM
, EXd
} },
2878 { "divpd", { XM
, EXx
} },
2879 { "divsd", { XM
, EXq
} },
2884 { "maxps", { XM
, EXx
} },
2885 { "maxss", { XM
, EXd
} },
2886 { "maxpd", { XM
, EXx
} },
2887 { "maxsd", { XM
, EXq
} },
2892 { "punpcklbw",{ MX
, EMd
} },
2894 { "punpcklbw",{ MX
, EMx
} },
2899 { "punpcklwd",{ MX
, EMd
} },
2901 { "punpcklwd",{ MX
, EMx
} },
2906 { "punpckldq",{ MX
, EMd
} },
2908 { "punpckldq",{ MX
, EMx
} },
2915 { "punpcklqdq", { XM
, EXx
} },
2922 { "punpckhqdq", { XM
, EXx
} },
2927 { "movq", { MX
, EM
} },
2928 { "movdqu", { XM
, EXx
} },
2929 { "movdqa", { XM
, EXx
} },
2934 { "pshufw", { MX
, EM
, Ib
} },
2935 { "pshufhw",{ XM
, EXx
, Ib
} },
2936 { "pshufd", { XM
, EXx
, Ib
} },
2937 { "pshuflw",{ XM
, EXx
, Ib
} },
2940 /* PREFIX_0F73_REG_3 */
2944 { "psrldq", { XS
, Ib
} },
2947 /* PREFIX_0F73_REG_7 */
2951 { "pslldq", { XS
, Ib
} },
2956 {"vmread", { Em
, Gm
} },
2958 {"extrq", { XS
, Ib
, Ib
} },
2959 {"insertq", { XM
, XS
, Ib
, Ib
} },
2964 {"vmwrite", { Gm
, Em
} },
2966 {"extrq", { XM
, XS
} },
2967 {"insertq", { XM
, XS
} },
2974 { "haddpd", { XM
, EXx
} },
2975 { "haddps", { XM
, EXx
} },
2982 { "hsubpd", { XM
, EXx
} },
2983 { "hsubps", { XM
, EXx
} },
2988 { "movK", { Edq
, MX
} },
2989 { "movq", { XM
, EXq
} },
2990 { "movK", { Edq
, XM
} },
2995 { "movq", { EMS
, MX
} },
2996 { "movdqu", { EXxS
, XM
} },
2997 { "movdqa", { EXxS
, XM
} },
3003 { "popcntS", { Gv
, Ev
} },
3008 { "bsrS", { Gv
, Ev
} },
3009 { "lzcntS", { Gv
, Ev
} },
3010 { "bsrS", { Gv
, Ev
} },
3015 { "cmpps", { XM
, EXx
, CMP
} },
3016 { "cmpss", { XM
, EXd
, CMP
} },
3017 { "cmppd", { XM
, EXx
, CMP
} },
3018 { "cmpsd", { XM
, EXq
, CMP
} },
3023 { "movntiS", { Ma
, Gv
} },
3026 /* PREFIX_0FC7_REG_6 */
3028 { "vmptrld",{ Mq
} },
3029 { "vmxon", { Mq
} },
3030 { "vmclear",{ Mq
} },
3037 { "addsubpd", { XM
, EXx
} },
3038 { "addsubps", { XM
, EXx
} },
3044 { "movq2dq",{ XM
, MS
} },
3045 { "movq", { EXqS
, XM
} },
3046 { "movdq2q",{ MX
, XS
} },
3052 { "cvtdq2pd", { XM
, EXq
} },
3053 { "cvttpd2dq", { XM
, EXx
} },
3054 { "cvtpd2dq", { XM
, EXx
} },
3059 { "movntq", { Mq
, MX
} },
3061 { MOD_TABLE (MOD_0FE7_PREFIX_2
) },
3069 { MOD_TABLE (MOD_0FF0_PREFIX_3
) },
3074 { "maskmovq", { MX
, MS
} },
3076 { "maskmovdqu", { XM
, XS
} },
3083 { "pblendvb", { XM
, EXx
, XMM0
} },
3090 { "blendvps", { XM
, EXx
, XMM0
} },
3097 { "blendvpd", { XM
, EXx
, XMM0
} },
3104 { "ptest", { XM
, EXx
} },
3111 { "pmovsxbw", { XM
, EXq
} },
3118 { "pmovsxbd", { XM
, EXd
} },
3125 { "pmovsxbq", { XM
, EXw
} },
3132 { "pmovsxwd", { XM
, EXq
} },
3139 { "pmovsxwq", { XM
, EXd
} },
3146 { "pmovsxdq", { XM
, EXq
} },
3153 { "pmuldq", { XM
, EXx
} },
3160 { "pcmpeqq", { XM
, EXx
} },
3167 { MOD_TABLE (MOD_0F382A_PREFIX_2
) },
3174 { "packusdw", { XM
, EXx
} },
3181 { "pmovzxbw", { XM
, EXq
} },
3188 { "pmovzxbd", { XM
, EXd
} },
3195 { "pmovzxbq", { XM
, EXw
} },
3202 { "pmovzxwd", { XM
, EXq
} },
3209 { "pmovzxwq", { XM
, EXd
} },
3216 { "pmovzxdq", { XM
, EXq
} },
3223 { "pcmpgtq", { XM
, EXx
} },
3230 { "pminsb", { XM
, EXx
} },
3237 { "pminsd", { XM
, EXx
} },
3244 { "pminuw", { XM
, EXx
} },
3251 { "pminud", { XM
, EXx
} },
3258 { "pmaxsb", { XM
, EXx
} },
3265 { "pmaxsd", { XM
, EXx
} },
3272 { "pmaxuw", { XM
, EXx
} },
3279 { "pmaxud", { XM
, EXx
} },
3286 { "pmulld", { XM
, EXx
} },
3293 { "phminposuw", { XM
, EXx
} },
3300 { "invept", { Gm
, Mo
} },
3307 { "invvpid", { Gm
, Mo
} },
3314 { "aesimc", { XM
, EXx
} },
3321 { "aesenc", { XM
, EXx
} },
3328 { "aesenclast", { XM
, EXx
} },
3335 { "aesdec", { XM
, EXx
} },
3342 { "aesdeclast", { XM
, EXx
} },
3347 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} } },
3349 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} } },
3350 { "crc32", { Gdq
, { CRC32_Fixup
, b_mode
} } },
3355 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
} },
3357 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
} },
3358 { "crc32", { Gdq
, { CRC32_Fixup
, v_mode
} } },
3365 { "roundps", { XM
, EXx
, Ib
} },
3372 { "roundpd", { XM
, EXx
, Ib
} },
3379 { "roundss", { XM
, EXd
, Ib
} },
3386 { "roundsd", { XM
, EXq
, Ib
} },
3393 { "blendps", { XM
, EXx
, Ib
} },
3400 { "blendpd", { XM
, EXx
, Ib
} },
3407 { "pblendw", { XM
, EXx
, Ib
} },
3414 { "pextrb", { Edqb
, XM
, Ib
} },
3421 { "pextrw", { Edqw
, XM
, Ib
} },
3428 { "pextrK", { Edq
, XM
, Ib
} },
3435 { "extractps", { Edqd
, XM
, Ib
} },
3442 { "pinsrb", { XM
, Edqb
, Ib
} },
3449 { "insertps", { XM
, EXd
, Ib
} },
3456 { "pinsrK", { XM
, Edq
, Ib
} },
3463 { "dpps", { XM
, EXx
, Ib
} },
3470 { "dppd", { XM
, EXx
, Ib
} },
3477 { "mpsadbw", { XM
, EXx
, Ib
} },
3484 { "pclmulqdq", { XM
, EXx
, PCLMUL
} },
3491 { "pcmpestrm", { XM
, EXx
, Ib
} },
3498 { "pcmpestri", { XM
, EXx
, Ib
} },
3505 { "pcmpistrm", { XM
, EXx
, Ib
} },
3512 { "pcmpistri", { XM
, EXx
, Ib
} },
3519 { "aeskeygenassist", { XM
, EXx
, Ib
} },
3524 { VEX_W_TABLE (VEX_W_10_P_0
) },
3525 { VEX_LEN_TABLE (VEX_LEN_10_P_1
) },
3526 { VEX_W_TABLE (VEX_W_10_P_2
) },
3527 { VEX_LEN_TABLE (VEX_LEN_10_P_3
) },
3532 { VEX_W_TABLE (VEX_W_11_P_0
) },
3533 { VEX_LEN_TABLE (VEX_LEN_11_P_1
) },
3534 { VEX_W_TABLE (VEX_W_11_P_2
) },
3535 { VEX_LEN_TABLE (VEX_LEN_11_P_3
) },
3540 { MOD_TABLE (MOD_VEX_12_PREFIX_0
) },
3541 { VEX_W_TABLE (VEX_W_12_P_1
) },
3542 { VEX_LEN_TABLE (VEX_LEN_12_P_2
) },
3543 { VEX_W_TABLE (VEX_W_12_P_3
) },
3548 { MOD_TABLE (MOD_VEX_16_PREFIX_0
) },
3549 { VEX_W_TABLE (VEX_W_16_P_1
) },
3550 { VEX_LEN_TABLE (VEX_LEN_16_P_2
) },
3556 { VEX_LEN_TABLE (VEX_LEN_2A_P_1
) },
3558 { VEX_LEN_TABLE (VEX_LEN_2A_P_3
) },
3564 { VEX_LEN_TABLE (VEX_LEN_2C_P_1
) },
3566 { VEX_LEN_TABLE (VEX_LEN_2C_P_3
) },
3572 { VEX_LEN_TABLE (VEX_LEN_2D_P_1
) },
3574 { VEX_LEN_TABLE (VEX_LEN_2D_P_3
) },
3579 { VEX_LEN_TABLE (VEX_LEN_2E_P_0
) },
3581 { VEX_LEN_TABLE (VEX_LEN_2E_P_2
) },
3586 { VEX_LEN_TABLE (VEX_LEN_2F_P_0
) },
3588 { VEX_LEN_TABLE (VEX_LEN_2F_P_2
) },
3593 { VEX_W_TABLE (VEX_W_51_P_0
) },
3594 { VEX_LEN_TABLE (VEX_LEN_51_P_1
) },
3595 { VEX_W_TABLE (VEX_W_51_P_2
) },
3596 { VEX_LEN_TABLE (VEX_LEN_51_P_3
) },
3601 { VEX_W_TABLE (VEX_W_52_P_0
) },
3602 { VEX_LEN_TABLE (VEX_LEN_52_P_1
) },
3607 { VEX_W_TABLE (VEX_W_53_P_0
) },
3608 { VEX_LEN_TABLE (VEX_LEN_53_P_1
) },
3613 { VEX_W_TABLE (VEX_W_58_P_0
) },
3614 { VEX_LEN_TABLE (VEX_LEN_58_P_1
) },
3615 { VEX_W_TABLE (VEX_W_58_P_2
) },
3616 { VEX_LEN_TABLE (VEX_LEN_58_P_3
) },
3621 { VEX_W_TABLE (VEX_W_59_P_0
) },
3622 { VEX_LEN_TABLE (VEX_LEN_59_P_1
) },
3623 { VEX_W_TABLE (VEX_W_59_P_2
) },
3624 { VEX_LEN_TABLE (VEX_LEN_59_P_3
) },
3629 { VEX_W_TABLE (VEX_W_5A_P_0
) },
3630 { VEX_LEN_TABLE (VEX_LEN_5A_P_1
) },
3631 { "vcvtpd2ps%XY", { XMM
, EXx
} },
3632 { VEX_LEN_TABLE (VEX_LEN_5A_P_3
) },
3637 { VEX_W_TABLE (VEX_W_5B_P_0
) },
3638 { VEX_W_TABLE (VEX_W_5B_P_1
) },
3639 { VEX_W_TABLE (VEX_W_5B_P_2
) },
3644 { VEX_W_TABLE (VEX_W_5C_P_0
) },
3645 { VEX_LEN_TABLE (VEX_LEN_5C_P_1
) },
3646 { VEX_W_TABLE (VEX_W_5C_P_2
) },
3647 { VEX_LEN_TABLE (VEX_LEN_5C_P_3
) },
3652 { VEX_W_TABLE (VEX_W_5D_P_0
) },
3653 { VEX_LEN_TABLE (VEX_LEN_5D_P_1
) },
3654 { VEX_W_TABLE (VEX_W_5D_P_2
) },
3655 { VEX_LEN_TABLE (VEX_LEN_5D_P_3
) },
3660 { VEX_W_TABLE (VEX_W_5E_P_0
) },
3661 { VEX_LEN_TABLE (VEX_LEN_5E_P_1
) },
3662 { VEX_W_TABLE (VEX_W_5E_P_2
) },
3663 { VEX_LEN_TABLE (VEX_LEN_5E_P_3
) },
3668 { VEX_W_TABLE (VEX_W_5F_P_0
) },
3669 { VEX_LEN_TABLE (VEX_LEN_5F_P_1
) },
3670 { VEX_W_TABLE (VEX_W_5F_P_2
) },
3671 { VEX_LEN_TABLE (VEX_LEN_5F_P_3
) },
3678 { VEX_LEN_TABLE (VEX_LEN_60_P_2
) },
3685 { VEX_LEN_TABLE (VEX_LEN_61_P_2
) },
3692 { VEX_LEN_TABLE (VEX_LEN_62_P_2
) },
3699 { VEX_LEN_TABLE (VEX_LEN_63_P_2
) },
3706 { VEX_LEN_TABLE (VEX_LEN_64_P_2
) },
3713 { VEX_LEN_TABLE (VEX_LEN_65_P_2
) },
3720 { VEX_LEN_TABLE (VEX_LEN_66_P_2
) },
3727 { VEX_LEN_TABLE (VEX_LEN_67_P_2
) },
3734 { VEX_LEN_TABLE (VEX_LEN_68_P_2
) },
3741 { VEX_LEN_TABLE (VEX_LEN_69_P_2
) },
3748 { VEX_LEN_TABLE (VEX_LEN_6A_P_2
) },
3755 { VEX_LEN_TABLE (VEX_LEN_6B_P_2
) },
3762 { VEX_LEN_TABLE (VEX_LEN_6C_P_2
) },
3769 { VEX_LEN_TABLE (VEX_LEN_6D_P_2
) },
3776 { VEX_LEN_TABLE (VEX_LEN_6E_P_2
) },
3782 { VEX_W_TABLE (VEX_W_6F_P_1
) },
3783 { VEX_W_TABLE (VEX_W_6F_P_2
) },
3789 { VEX_LEN_TABLE (VEX_LEN_70_P_1
) },
3790 { VEX_LEN_TABLE (VEX_LEN_70_P_2
) },
3791 { VEX_LEN_TABLE (VEX_LEN_70_P_3
) },
3794 /* PREFIX_VEX_71_REG_2 */
3798 { VEX_LEN_TABLE (VEX_LEN_71_R_2_P_2
) },
3801 /* PREFIX_VEX_71_REG_4 */
3805 { VEX_LEN_TABLE (VEX_LEN_71_R_4_P_2
) },
3808 /* PREFIX_VEX_71_REG_6 */
3812 { VEX_LEN_TABLE (VEX_LEN_71_R_6_P_2
) },
3815 /* PREFIX_VEX_72_REG_2 */
3819 { VEX_LEN_TABLE (VEX_LEN_72_R_2_P_2
) },
3822 /* PREFIX_VEX_72_REG_4 */
3826 { VEX_LEN_TABLE (VEX_LEN_72_R_4_P_2
) },
3829 /* PREFIX_VEX_72_REG_6 */
3833 { VEX_LEN_TABLE (VEX_LEN_72_R_6_P_2
) },
3836 /* PREFIX_VEX_73_REG_2 */
3840 { VEX_LEN_TABLE (VEX_LEN_73_R_2_P_2
) },
3843 /* PREFIX_VEX_73_REG_3 */
3847 { VEX_LEN_TABLE (VEX_LEN_73_R_3_P_2
) },
3850 /* PREFIX_VEX_73_REG_6 */
3854 { VEX_LEN_TABLE (VEX_LEN_73_R_6_P_2
) },
3857 /* PREFIX_VEX_73_REG_7 */
3861 { VEX_LEN_TABLE (VEX_LEN_73_R_7_P_2
) },
3868 { VEX_LEN_TABLE (VEX_LEN_74_P_2
) },
3875 { VEX_LEN_TABLE (VEX_LEN_75_P_2
) },
3882 { VEX_LEN_TABLE (VEX_LEN_76_P_2
) },
3887 { VEX_W_TABLE (VEX_W_77_P_0
) },
3894 { VEX_W_TABLE (VEX_W_7C_P_2
) },
3895 { VEX_W_TABLE (VEX_W_7C_P_3
) },
3902 { VEX_W_TABLE (VEX_W_7D_P_2
) },
3903 { VEX_W_TABLE (VEX_W_7D_P_3
) },
3909 { VEX_LEN_TABLE (VEX_LEN_7E_P_1
) },
3910 { VEX_LEN_TABLE (VEX_LEN_7E_P_2
) },
3916 { VEX_W_TABLE (VEX_W_7F_P_1
) },
3917 { VEX_W_TABLE (VEX_W_7F_P_2
) },
3922 { VEX_W_TABLE (VEX_W_C2_P_0
) },
3923 { VEX_LEN_TABLE (VEX_LEN_C2_P_1
) },
3924 { VEX_W_TABLE (VEX_W_C2_P_2
) },
3925 { VEX_LEN_TABLE (VEX_LEN_C2_P_3
) },
3932 { VEX_LEN_TABLE (VEX_LEN_C4_P_2
) },
3939 { VEX_LEN_TABLE (VEX_LEN_C5_P_2
) },
3946 { VEX_W_TABLE (VEX_W_D0_P_2
) },
3947 { VEX_W_TABLE (VEX_W_D0_P_3
) },
3954 { VEX_LEN_TABLE (VEX_LEN_D1_P_2
) },
3961 { VEX_LEN_TABLE (VEX_LEN_D2_P_2
) },
3968 { VEX_LEN_TABLE (VEX_LEN_D3_P_2
) },
3975 { VEX_LEN_TABLE (VEX_LEN_D4_P_2
) },
3982 { VEX_LEN_TABLE (VEX_LEN_D5_P_2
) },
3989 { VEX_LEN_TABLE (VEX_LEN_D6_P_2
) },
3996 { MOD_TABLE (MOD_VEX_D7_PREFIX_2
) },
4003 { VEX_LEN_TABLE (VEX_LEN_D8_P_2
) },
4010 { VEX_LEN_TABLE (VEX_LEN_D9_P_2
) },
4017 { VEX_LEN_TABLE (VEX_LEN_DA_P_2
) },
4024 { VEX_LEN_TABLE (VEX_LEN_DB_P_2
) },
4031 { VEX_LEN_TABLE (VEX_LEN_DC_P_2
) },
4038 { VEX_LEN_TABLE (VEX_LEN_DD_P_2
) },
4045 { VEX_LEN_TABLE (VEX_LEN_DE_P_2
) },
4052 { VEX_LEN_TABLE (VEX_LEN_DF_P_2
) },
4059 { VEX_LEN_TABLE (VEX_LEN_E0_P_2
) },
4066 { VEX_LEN_TABLE (VEX_LEN_E1_P_2
) },
4073 { VEX_LEN_TABLE (VEX_LEN_E2_P_2
) },
4080 { VEX_LEN_TABLE (VEX_LEN_E3_P_2
) },
4087 { VEX_LEN_TABLE (VEX_LEN_E4_P_2
) },
4094 { VEX_LEN_TABLE (VEX_LEN_E5_P_2
) },
4100 { VEX_W_TABLE (VEX_W_E6_P_1
) },
4101 { VEX_W_TABLE (VEX_W_E6_P_2
) },
4102 { VEX_W_TABLE (VEX_W_E6_P_3
) },
4109 { MOD_TABLE (MOD_VEX_E7_PREFIX_2
) },
4116 { VEX_LEN_TABLE (VEX_LEN_E8_P_2
) },
4123 { VEX_LEN_TABLE (VEX_LEN_E9_P_2
) },
4130 { VEX_LEN_TABLE (VEX_LEN_EA_P_2
) },
4137 { VEX_LEN_TABLE (VEX_LEN_EB_P_2
) },
4144 { VEX_LEN_TABLE (VEX_LEN_EC_P_2
) },
4151 { VEX_LEN_TABLE (VEX_LEN_ED_P_2
) },
4158 { VEX_LEN_TABLE (VEX_LEN_EE_P_2
) },
4165 { VEX_LEN_TABLE (VEX_LEN_EF_P_2
) },
4173 { MOD_TABLE (MOD_VEX_F0_PREFIX_3
) },
4180 { VEX_LEN_TABLE (VEX_LEN_F1_P_2
) },
4187 { VEX_LEN_TABLE (VEX_LEN_F2_P_2
) },
4194 { VEX_LEN_TABLE (VEX_LEN_F3_P_2
) },
4201 { VEX_LEN_TABLE (VEX_LEN_F4_P_2
) },
4208 { VEX_LEN_TABLE (VEX_LEN_F5_P_2
) },
4215 { VEX_LEN_TABLE (VEX_LEN_F6_P_2
) },
4222 { VEX_LEN_TABLE (VEX_LEN_F7_P_2
) },
4229 { VEX_LEN_TABLE (VEX_LEN_F8_P_2
) },
4236 { VEX_LEN_TABLE (VEX_LEN_F9_P_2
) },
4243 { VEX_LEN_TABLE (VEX_LEN_FA_P_2
) },
4250 { VEX_LEN_TABLE (VEX_LEN_FB_P_2
) },
4257 { VEX_LEN_TABLE (VEX_LEN_FC_P_2
) },
4264 { VEX_LEN_TABLE (VEX_LEN_FD_P_2
) },
4271 { VEX_LEN_TABLE (VEX_LEN_FE_P_2
) },
4274 /* PREFIX_VEX_3800 */
4278 { VEX_LEN_TABLE (VEX_LEN_3800_P_2
) },
4281 /* PREFIX_VEX_3801 */
4285 { VEX_LEN_TABLE (VEX_LEN_3801_P_2
) },
4288 /* PREFIX_VEX_3802 */
4292 { VEX_LEN_TABLE (VEX_LEN_3802_P_2
) },
4295 /* PREFIX_VEX_3803 */
4299 { VEX_LEN_TABLE (VEX_LEN_3803_P_2
) },
4302 /* PREFIX_VEX_3804 */
4306 { VEX_LEN_TABLE (VEX_LEN_3804_P_2
) },
4309 /* PREFIX_VEX_3805 */
4313 { VEX_LEN_TABLE (VEX_LEN_3805_P_2
) },
4316 /* PREFIX_VEX_3806 */
4320 { VEX_LEN_TABLE (VEX_LEN_3806_P_2
) },
4323 /* PREFIX_VEX_3807 */
4327 { VEX_LEN_TABLE (VEX_LEN_3807_P_2
) },
4330 /* PREFIX_VEX_3808 */
4334 { VEX_LEN_TABLE (VEX_LEN_3808_P_2
) },
4337 /* PREFIX_VEX_3809 */
4341 { VEX_LEN_TABLE (VEX_LEN_3809_P_2
) },
4344 /* PREFIX_VEX_380A */
4348 { VEX_LEN_TABLE (VEX_LEN_380A_P_2
) },
4351 /* PREFIX_VEX_380B */
4355 { VEX_LEN_TABLE (VEX_LEN_380B_P_2
) },
4358 /* PREFIX_VEX_380C */
4362 { VEX_W_TABLE (VEX_W_380C_P_2
) },
4365 /* PREFIX_VEX_380D */
4369 { VEX_W_TABLE (VEX_W_380D_P_2
) },
4372 /* PREFIX_VEX_380E */
4376 { VEX_W_TABLE (VEX_W_380E_P_2
) },
4379 /* PREFIX_VEX_380F */
4383 { VEX_W_TABLE (VEX_W_380F_P_2
) },
4386 /* PREFIX_VEX_3817 */
4390 { VEX_W_TABLE (VEX_W_3817_P_2
) },
4393 /* PREFIX_VEX_3818 */
4397 { MOD_TABLE (MOD_VEX_3818_PREFIX_2
) },
4400 /* PREFIX_VEX_3819 */
4404 { MOD_TABLE (MOD_VEX_3819_PREFIX_2
) },
4407 /* PREFIX_VEX_381A */
4411 { MOD_TABLE (MOD_VEX_381A_PREFIX_2
) },
4414 /* PREFIX_VEX_381C */
4418 { VEX_LEN_TABLE (VEX_LEN_381C_P_2
) },
4421 /* PREFIX_VEX_381D */
4425 { VEX_LEN_TABLE (VEX_LEN_381D_P_2
) },
4428 /* PREFIX_VEX_381E */
4432 { VEX_LEN_TABLE (VEX_LEN_381E_P_2
) },
4435 /* PREFIX_VEX_3820 */
4439 { VEX_LEN_TABLE (VEX_LEN_3820_P_2
) },
4443 /* PREFIX_VEX_3821 */
4447 { VEX_LEN_TABLE (VEX_LEN_3821_P_2
) },
4450 /* PREFIX_VEX_3822 */
4454 { VEX_LEN_TABLE (VEX_LEN_3822_P_2
) },
4457 /* PREFIX_VEX_3823 */
4461 { VEX_LEN_TABLE (VEX_LEN_3823_P_2
) },
4464 /* PREFIX_VEX_3824 */
4468 { VEX_LEN_TABLE (VEX_LEN_3824_P_2
) },
4471 /* PREFIX_VEX_3825 */
4475 { VEX_LEN_TABLE (VEX_LEN_3825_P_2
) },
4478 /* PREFIX_VEX_3828 */
4482 { VEX_LEN_TABLE (VEX_LEN_3828_P_2
) },
4485 /* PREFIX_VEX_3829 */
4489 { VEX_LEN_TABLE (VEX_LEN_3829_P_2
) },
4492 /* PREFIX_VEX_382A */
4496 { MOD_TABLE (MOD_VEX_382A_PREFIX_2
) },
4499 /* PREFIX_VEX_382B */
4503 { VEX_LEN_TABLE (VEX_LEN_382B_P_2
) },
4506 /* PREFIX_VEX_382C */
4510 { MOD_TABLE (MOD_VEX_382C_PREFIX_2
) },
4513 /* PREFIX_VEX_382D */
4517 { MOD_TABLE (MOD_VEX_382D_PREFIX_2
) },
4520 /* PREFIX_VEX_382E */
4524 { MOD_TABLE (MOD_VEX_382E_PREFIX_2
) },
4527 /* PREFIX_VEX_382F */
4531 { MOD_TABLE (MOD_VEX_382F_PREFIX_2
) },
4534 /* PREFIX_VEX_3830 */
4538 { VEX_LEN_TABLE (VEX_LEN_3830_P_2
) },
4541 /* PREFIX_VEX_3831 */
4545 { VEX_LEN_TABLE (VEX_LEN_3831_P_2
) },
4548 /* PREFIX_VEX_3832 */
4552 { VEX_LEN_TABLE (VEX_LEN_3832_P_2
) },
4555 /* PREFIX_VEX_3833 */
4559 { VEX_LEN_TABLE (VEX_LEN_3833_P_2
) },
4562 /* PREFIX_VEX_3834 */
4566 { VEX_LEN_TABLE (VEX_LEN_3834_P_2
) },
4569 /* PREFIX_VEX_3835 */
4573 { VEX_LEN_TABLE (VEX_LEN_3835_P_2
) },
4576 /* PREFIX_VEX_3837 */
4580 { VEX_LEN_TABLE (VEX_LEN_3837_P_2
) },
4583 /* PREFIX_VEX_3838 */
4587 { VEX_LEN_TABLE (VEX_LEN_3838_P_2
) },
4590 /* PREFIX_VEX_3839 */
4594 { VEX_LEN_TABLE (VEX_LEN_3839_P_2
) },
4597 /* PREFIX_VEX_383A */
4601 { VEX_LEN_TABLE (VEX_LEN_383A_P_2
) },
4604 /* PREFIX_VEX_383B */
4608 { VEX_LEN_TABLE (VEX_LEN_383B_P_2
) },
4611 /* PREFIX_VEX_383C */
4615 { VEX_LEN_TABLE (VEX_LEN_383C_P_2
) },
4618 /* PREFIX_VEX_383D */
4622 { VEX_LEN_TABLE (VEX_LEN_383D_P_2
) },
4625 /* PREFIX_VEX_383E */
4629 { VEX_LEN_TABLE (VEX_LEN_383E_P_2
) },
4632 /* PREFIX_VEX_383F */
4636 { VEX_LEN_TABLE (VEX_LEN_383F_P_2
) },
4639 /* PREFIX_VEX_3840 */
4643 { VEX_LEN_TABLE (VEX_LEN_3840_P_2
) },
4646 /* PREFIX_VEX_3841 */
4650 { VEX_LEN_TABLE (VEX_LEN_3841_P_2
) },
4653 /* PREFIX_VEX_3896 */
4657 { "vfmaddsub132p%XW", { XM
, Vex
, EXx
} },
4660 /* PREFIX_VEX_3897 */
4664 { "vfmsubadd132p%XW", { XM
, Vex
, EXx
} },
4667 /* PREFIX_VEX_3898 */
4671 { "vfmadd132p%XW", { XM
, Vex
, EXx
} },
4674 /* PREFIX_VEX_3899 */
4678 { "vfmadd132s%XW", { XM
, Vex
, EXVexWdq
} },
4681 /* PREFIX_VEX_389A */
4685 { "vfmsub132p%XW", { XM
, Vex
, EXx
} },
4688 /* PREFIX_VEX_389B */
4692 { "vfmsub132s%XW", { XM
, Vex
, EXVexWdq
} },
4695 /* PREFIX_VEX_389C */
4699 { "vfnmadd132p%XW", { XM
, Vex
, EXx
} },
4702 /* PREFIX_VEX_389D */
4706 { "vfnmadd132s%XW", { XM
, Vex
, EXVexWdq
} },
4709 /* PREFIX_VEX_389E */
4713 { "vfnmsub132p%XW", { XM
, Vex
, EXx
} },
4716 /* PREFIX_VEX_389F */
4720 { "vfnmsub132s%XW", { XM
, Vex
, EXVexWdq
} },
4723 /* PREFIX_VEX_38A6 */
4727 { "vfmaddsub213p%XW", { XM
, Vex
, EXx
} },
4731 /* PREFIX_VEX_38A7 */
4735 { "vfmsubadd213p%XW", { XM
, Vex
, EXx
} },
4738 /* PREFIX_VEX_38A8 */
4742 { "vfmadd213p%XW", { XM
, Vex
, EXx
} },
4745 /* PREFIX_VEX_38A9 */
4749 { "vfmadd213s%XW", { XM
, Vex
, EXVexWdq
} },
4752 /* PREFIX_VEX_38AA */
4756 { "vfmsub213p%XW", { XM
, Vex
, EXx
} },
4759 /* PREFIX_VEX_38AB */
4763 { "vfmsub213s%XW", { XM
, Vex
, EXVexWdq
} },
4766 /* PREFIX_VEX_38AC */
4770 { "vfnmadd213p%XW", { XM
, Vex
, EXx
} },
4773 /* PREFIX_VEX_38AD */
4777 { "vfnmadd213s%XW", { XM
, Vex
, EXVexWdq
} },
4780 /* PREFIX_VEX_38AE */
4784 { "vfnmsub213p%XW", { XM
, Vex
, EXx
} },
4787 /* PREFIX_VEX_38AF */
4791 { "vfnmsub213s%XW", { XM
, Vex
, EXVexWdq
} },
4794 /* PREFIX_VEX_38B6 */
4798 { "vfmaddsub231p%XW", { XM
, Vex
, EXx
} },
4801 /* PREFIX_VEX_38B7 */
4805 { "vfmsubadd231p%XW", { XM
, Vex
, EXx
} },
4808 /* PREFIX_VEX_38B8 */
4812 { "vfmadd231p%XW", { XM
, Vex
, EXx
} },
4815 /* PREFIX_VEX_38B9 */
4819 { "vfmadd231s%XW", { XM
, Vex
, EXVexWdq
} },
4822 /* PREFIX_VEX_38BA */
4826 { "vfmsub231p%XW", { XM
, Vex
, EXx
} },
4829 /* PREFIX_VEX_38BB */
4833 { "vfmsub231s%XW", { XM
, Vex
, EXVexWdq
} },
4836 /* PREFIX_VEX_38BC */
4840 { "vfnmadd231p%XW", { XM
, Vex
, EXx
} },
4843 /* PREFIX_VEX_38BD */
4847 { "vfnmadd231s%XW", { XM
, Vex
, EXVexWdq
} },
4850 /* PREFIX_VEX_38BE */
4854 { "vfnmsub231p%XW", { XM
, Vex
, EXx
} },
4857 /* PREFIX_VEX_38BF */
4861 { "vfnmsub231s%XW", { XM
, Vex
, EXVexWdq
} },
4864 /* PREFIX_VEX_38DB */
4868 { VEX_LEN_TABLE (VEX_LEN_38DB_P_2
) },
4871 /* PREFIX_VEX_38DC */
4875 { VEX_LEN_TABLE (VEX_LEN_38DC_P_2
) },
4878 /* PREFIX_VEX_38DD */
4882 { VEX_LEN_TABLE (VEX_LEN_38DD_P_2
) },
4885 /* PREFIX_VEX_38DE */
4889 { VEX_LEN_TABLE (VEX_LEN_38DE_P_2
) },
4892 /* PREFIX_VEX_38DF */
4896 { VEX_LEN_TABLE (VEX_LEN_38DF_P_2
) },
4899 /* PREFIX_VEX_3A04 */
4903 { VEX_W_TABLE (VEX_W_3A04_P_2
) },
4906 /* PREFIX_VEX_3A05 */
4910 { VEX_W_TABLE (VEX_W_3A05_P_2
) },
4913 /* PREFIX_VEX_3A06 */
4917 { VEX_LEN_TABLE (VEX_LEN_3A06_P_2
) },
4920 /* PREFIX_VEX_3A08 */
4924 { VEX_W_TABLE (VEX_W_3A08_P_2
) },
4927 /* PREFIX_VEX_3A09 */
4931 { VEX_W_TABLE (VEX_W_3A09_P_2
) },
4934 /* PREFIX_VEX_3A0A */
4938 { VEX_LEN_TABLE (VEX_LEN_3A0A_P_2
) },
4941 /* PREFIX_VEX_3A0B */
4945 { VEX_LEN_TABLE (VEX_LEN_3A0B_P_2
) },
4948 /* PREFIX_VEX_3A0C */
4952 { VEX_W_TABLE (VEX_W_3A0C_P_2
) },
4955 /* PREFIX_VEX_3A0D */
4959 { VEX_W_TABLE (VEX_W_3A0D_P_2
) },
4962 /* PREFIX_VEX_3A0E */
4966 { VEX_LEN_TABLE (VEX_LEN_3A0E_P_2
) },
4969 /* PREFIX_VEX_3A0F */
4973 { VEX_LEN_TABLE (VEX_LEN_3A0F_P_2
) },
4976 /* PREFIX_VEX_3A14 */
4980 { VEX_LEN_TABLE (VEX_LEN_3A14_P_2
) },
4983 /* PREFIX_VEX_3A15 */
4987 { VEX_LEN_TABLE (VEX_LEN_3A15_P_2
) },
4990 /* PREFIX_VEX_3A16 */
4994 { VEX_LEN_TABLE (VEX_LEN_3A16_P_2
) },
4997 /* PREFIX_VEX_3A17 */
5001 { VEX_LEN_TABLE (VEX_LEN_3A17_P_2
) },
5004 /* PREFIX_VEX_3A18 */
5008 { VEX_LEN_TABLE (VEX_LEN_3A18_P_2
) },
5011 /* PREFIX_VEX_3A19 */
5015 { VEX_LEN_TABLE (VEX_LEN_3A19_P_2
) },
5018 /* PREFIX_VEX_3A20 */
5022 { VEX_LEN_TABLE (VEX_LEN_3A20_P_2
) },
5025 /* PREFIX_VEX_3A21 */
5029 { VEX_LEN_TABLE (VEX_LEN_3A21_P_2
) },
5032 /* PREFIX_VEX_3A22 */
5036 { VEX_LEN_TABLE (VEX_LEN_3A22_P_2
) },
5039 /* PREFIX_VEX_3A40 */
5043 { VEX_W_TABLE (VEX_W_3A40_P_2
) },
5046 /* PREFIX_VEX_3A41 */
5050 { VEX_LEN_TABLE (VEX_LEN_3A41_P_2
) },
5053 /* PREFIX_VEX_3A42 */
5057 { VEX_LEN_TABLE (VEX_LEN_3A42_P_2
) },
5060 /* PREFIX_VEX_3A44 */
5064 { VEX_LEN_TABLE (VEX_LEN_3A44_P_2
) },
5067 /* PREFIX_VEX_3A4A */
5071 { VEX_W_TABLE (VEX_W_3A4A_P_2
) },
5074 /* PREFIX_VEX_3A4B */
5078 { VEX_W_TABLE (VEX_W_3A4B_P_2
) },
5081 /* PREFIX_VEX_3A4C */
5085 { VEX_LEN_TABLE (VEX_LEN_3A4C_P_2
) },
5088 /* PREFIX_VEX_3A5C */
5092 { "vfmaddsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
5095 /* PREFIX_VEX_3A5D */
5099 { "vfmaddsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
5102 /* PREFIX_VEX_3A5E */
5106 { "vfmsubaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
5109 /* PREFIX_VEX_3A5F */
5113 { "vfmsubaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
5116 /* PREFIX_VEX_3A60 */
5120 { VEX_LEN_TABLE (VEX_LEN_3A60_P_2
) },
5124 /* PREFIX_VEX_3A61 */
5128 { VEX_LEN_TABLE (VEX_LEN_3A61_P_2
) },
5131 /* PREFIX_VEX_3A62 */
5135 { VEX_LEN_TABLE (VEX_LEN_3A62_P_2
) },
5138 /* PREFIX_VEX_3A63 */
5142 { VEX_LEN_TABLE (VEX_LEN_3A63_P_2
) },
5145 /* PREFIX_VEX_3A68 */
5149 { "vfmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
5152 /* PREFIX_VEX_3A69 */
5156 { "vfmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
5159 /* PREFIX_VEX_3A6A */
5163 { VEX_LEN_TABLE (VEX_LEN_3A6A_P_2
) },
5166 /* PREFIX_VEX_3A6B */
5170 { VEX_LEN_TABLE (VEX_LEN_3A6B_P_2
) },
5173 /* PREFIX_VEX_3A6C */
5177 { "vfmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
5180 /* PREFIX_VEX_3A6D */
5184 { "vfmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
5187 /* PREFIX_VEX_3A6E */
5191 { VEX_LEN_TABLE (VEX_LEN_3A6E_P_2
) },
5194 /* PREFIX_VEX_3A6F */
5198 { VEX_LEN_TABLE (VEX_LEN_3A6F_P_2
) },
5201 /* PREFIX_VEX_3A78 */
5205 { "vfnmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
5208 /* PREFIX_VEX_3A79 */
5212 { "vfnmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
5215 /* PREFIX_VEX_3A7A */
5219 { VEX_LEN_TABLE (VEX_LEN_3A7A_P_2
) },
5222 /* PREFIX_VEX_3A7B */
5226 { VEX_LEN_TABLE (VEX_LEN_3A7B_P_2
) },
5229 /* PREFIX_VEX_3A7C */
5233 { "vfnmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
5237 /* PREFIX_VEX_3A7D */
5241 { "vfnmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
5244 /* PREFIX_VEX_3A7E */
5248 { VEX_LEN_TABLE (VEX_LEN_3A7E_P_2
) },
5251 /* PREFIX_VEX_3A7F */
5255 { VEX_LEN_TABLE (VEX_LEN_3A7F_P_2
) },
5258 /* PREFIX_VEX_3ADF */
5262 { VEX_LEN_TABLE (VEX_LEN_3ADF_P_2
) },
5266 static const struct dis386 x86_64_table
[][2] = {
5269 { "push{T|}", { es
} },
5274 { "pop{T|}", { es
} },
5279 { "push{T|}", { cs
} },
5284 { "push{T|}", { ss
} },
5289 { "pop{T|}", { ss
} },
5294 { "push{T|}", { ds
} },
5299 { "pop{T|}", { ds
} },
5324 { "pusha{P|}", { XX
} },
5329 { "popa{P|}", { XX
} },
5334 { MOD_TABLE (MOD_62_32BIT
) },
5339 { "arpl", { Ew
, Gw
} },
5340 { "movs{lq|xd}", { Gv
, Ed
} },
5345 { "ins{R|}", { Yzr
, indirDX
} },
5346 { "ins{G|}", { Yzr
, indirDX
} },
5351 { "outs{R|}", { indirDXr
, Xz
} },
5352 { "outs{G|}", { indirDXr
, Xz
} },
5357 { "Jcall{T|}", { Ap
} },
5362 { MOD_TABLE (MOD_C4_32BIT
) },
5363 { VEX_C4_TABLE (VEX_0F
) },
5368 { MOD_TABLE (MOD_C5_32BIT
) },
5369 { VEX_C5_TABLE (VEX_0F
) },
5389 { "Jjmp{T|}", { Ap
} },
5392 /* X86_64_0F01_REG_0 */
5394 { "sgdt{Q|IQ}", { M
} },
5398 /* X86_64_0F01_REG_1 */
5400 { "sidt{Q|IQ}", { M
} },
5404 /* X86_64_0F01_REG_2 */
5406 { "lgdt{Q|Q}", { M
} },
5410 /* X86_64_0F01_REG_3 */
5412 { "lidt{Q|Q}", { M
} },
5417 static const struct dis386 three_byte_table
[][256] = {
5419 /* THREE_BYTE_0F38 */
5422 { "pshufb", { MX
, EM
} },
5423 { "phaddw", { MX
, EM
} },
5424 { "phaddd", { MX
, EM
} },
5425 { "phaddsw", { MX
, EM
} },
5426 { "pmaddubsw", { MX
, EM
} },
5427 { "phsubw", { MX
, EM
} },
5428 { "phsubd", { MX
, EM
} },
5429 { "phsubsw", { MX
, EM
} },
5431 { "psignb", { MX
, EM
} },
5432 { "psignw", { MX
, EM
} },
5433 { "psignd", { MX
, EM
} },
5434 { "pmulhrsw", { MX
, EM
} },
5440 { PREFIX_TABLE (PREFIX_0F3810
) },
5444 { PREFIX_TABLE (PREFIX_0F3814
) },
5445 { PREFIX_TABLE (PREFIX_0F3815
) },
5447 { PREFIX_TABLE (PREFIX_0F3817
) },
5453 { "pabsb", { MX
, EM
} },
5454 { "pabsw", { MX
, EM
} },
5455 { "pabsd", { MX
, EM
} },
5458 { PREFIX_TABLE (PREFIX_0F3820
) },
5459 { PREFIX_TABLE (PREFIX_0F3821
) },
5460 { PREFIX_TABLE (PREFIX_0F3822
) },
5461 { PREFIX_TABLE (PREFIX_0F3823
) },
5462 { PREFIX_TABLE (PREFIX_0F3824
) },
5463 { PREFIX_TABLE (PREFIX_0F3825
) },
5467 { PREFIX_TABLE (PREFIX_0F3828
) },
5468 { PREFIX_TABLE (PREFIX_0F3829
) },
5469 { PREFIX_TABLE (PREFIX_0F382A
) },
5470 { PREFIX_TABLE (PREFIX_0F382B
) },
5476 { PREFIX_TABLE (PREFIX_0F3830
) },
5477 { PREFIX_TABLE (PREFIX_0F3831
) },
5478 { PREFIX_TABLE (PREFIX_0F3832
) },
5479 { PREFIX_TABLE (PREFIX_0F3833
) },
5480 { PREFIX_TABLE (PREFIX_0F3834
) },
5481 { PREFIX_TABLE (PREFIX_0F3835
) },
5483 { PREFIX_TABLE (PREFIX_0F3837
) },
5485 { PREFIX_TABLE (PREFIX_0F3838
) },
5486 { PREFIX_TABLE (PREFIX_0F3839
) },
5487 { PREFIX_TABLE (PREFIX_0F383A
) },
5488 { PREFIX_TABLE (PREFIX_0F383B
) },
5489 { PREFIX_TABLE (PREFIX_0F383C
) },
5490 { PREFIX_TABLE (PREFIX_0F383D
) },
5491 { PREFIX_TABLE (PREFIX_0F383E
) },
5492 { PREFIX_TABLE (PREFIX_0F383F
) },
5494 { PREFIX_TABLE (PREFIX_0F3840
) },
5495 { PREFIX_TABLE (PREFIX_0F3841
) },
5566 { PREFIX_TABLE (PREFIX_0F3880
) },
5567 { PREFIX_TABLE (PREFIX_0F3881
) },
5668 { PREFIX_TABLE (PREFIX_0F38DB
) },
5669 { PREFIX_TABLE (PREFIX_0F38DC
) },
5670 { PREFIX_TABLE (PREFIX_0F38DD
) },
5671 { PREFIX_TABLE (PREFIX_0F38DE
) },
5672 { PREFIX_TABLE (PREFIX_0F38DF
) },
5692 { PREFIX_TABLE (PREFIX_0F38F0
) },
5693 { PREFIX_TABLE (PREFIX_0F38F1
) },
5710 /* THREE_BYTE_0F3A */
5722 { PREFIX_TABLE (PREFIX_0F3A08
) },
5723 { PREFIX_TABLE (PREFIX_0F3A09
) },
5724 { PREFIX_TABLE (PREFIX_0F3A0A
) },
5725 { PREFIX_TABLE (PREFIX_0F3A0B
) },
5726 { PREFIX_TABLE (PREFIX_0F3A0C
) },
5727 { PREFIX_TABLE (PREFIX_0F3A0D
) },
5728 { PREFIX_TABLE (PREFIX_0F3A0E
) },
5729 { "palignr", { MX
, EM
, Ib
} },
5735 { PREFIX_TABLE (PREFIX_0F3A14
) },
5736 { PREFIX_TABLE (PREFIX_0F3A15
) },
5737 { PREFIX_TABLE (PREFIX_0F3A16
) },
5738 { PREFIX_TABLE (PREFIX_0F3A17
) },
5749 { PREFIX_TABLE (PREFIX_0F3A20
) },
5750 { PREFIX_TABLE (PREFIX_0F3A21
) },
5751 { PREFIX_TABLE (PREFIX_0F3A22
) },
5785 { PREFIX_TABLE (PREFIX_0F3A40
) },
5786 { PREFIX_TABLE (PREFIX_0F3A41
) },
5787 { PREFIX_TABLE (PREFIX_0F3A42
) },
5789 { PREFIX_TABLE (PREFIX_0F3A44
) },
5821 { PREFIX_TABLE (PREFIX_0F3A60
) },
5822 { PREFIX_TABLE (PREFIX_0F3A61
) },
5823 { PREFIX_TABLE (PREFIX_0F3A62
) },
5824 { PREFIX_TABLE (PREFIX_0F3A63
) },
5963 { PREFIX_TABLE (PREFIX_0F3ADF
) },
6002 /* THREE_BYTE_0F7A */
6041 { "ptest", { XX
} },
6078 { "phaddbw", { XM
, EXq
} },
6079 { "phaddbd", { XM
, EXq
} },
6080 { "phaddbq", { XM
, EXq
} },
6083 { "phaddwd", { XM
, EXq
} },
6084 { "phaddwq", { XM
, EXq
} },
6089 { "phadddq", { XM
, EXq
} },
6096 { "phaddubw", { XM
, EXq
} },
6097 { "phaddubd", { XM
, EXq
} },
6098 { "phaddubq", { XM
, EXq
} },
6101 { "phadduwd", { XM
, EXq
} },
6102 { "phadduwq", { XM
, EXq
} },
6107 { "phaddudq", { XM
, EXq
} },
6114 { "phsubbw", { XM
, EXq
} },
6115 { "phsubbd", { XM
, EXq
} },
6116 { "phsubbq", { XM
, EXq
} },
6295 static const struct dis386 xop_table
[][256] = {
6448 { "vpmacssww", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6449 { "vpmacsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6450 { "vpmacssdql", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6458 { "vpmacssdd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6459 { "vpmacssdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6466 { "vpmacsww", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6467 { "vpmacswd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6468 { "vpmacsdql", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6476 { "vpmacsdd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6477 { "vpmacsdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6481 { "vpcmov", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6482 { "vpperm", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6485 { "vpmadcsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6503 { "vpmadcswd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6515 { "vprotb", { XM
, Vex_2src_1
, Ib
} },
6516 { "vprotw", { XM
, Vex_2src_1
, Ib
} },
6517 { "vprotd", { XM
, Vex_2src_1
, Ib
} },
6518 { "vprotq", { XM
, Vex_2src_1
, Ib
} },
6528 { "vpcomb", { XM
, Vex128
, EXx
, Ib
} },
6529 { "vpcomw", { XM
, Vex128
, EXx
, Ib
} },
6530 { "vpcomd", { XM
, Vex128
, EXx
, Ib
} },
6531 { "vpcomq", { XM
, Vex128
, EXx
, Ib
} },
6564 { "vpcomub", { XM
, Vex128
, EXx
, Ib
} },
6565 { "vpcomuw", { XM
, Vex128
, EXx
, Ib
} },
6566 { "vpcomud", { XM
, Vex128
, EXx
, Ib
} },
6567 { "vpcomuq", { XM
, Vex128
, EXx
, Ib
} },
6610 { REG_TABLE (REG_XOP_LWPCB
) },
6734 { VEX_LEN_TABLE (VEX_LEN_XOP_09_80
) },
6735 { VEX_LEN_TABLE (VEX_LEN_XOP_09_81
) },
6736 { "vfrczss", { XM
, EXd
} },
6737 { "vfrczsd", { XM
, EXq
} },
6752 { "vprotb", { XM
, Vex_2src_1
, Vex_2src_2
} },
6753 { "vprotw", { XM
, Vex_2src_1
, Vex_2src_2
} },
6754 { "vprotd", { XM
, Vex_2src_1
, Vex_2src_2
} },
6755 { "vprotq", { XM
, Vex_2src_1
, Vex_2src_2
} },
6756 { "vpshlb", { XM
, Vex_2src_1
, Vex_2src_2
} },
6757 { "vpshlw", { XM
, Vex_2src_1
, Vex_2src_2
} },
6758 { "vpshld", { XM
, Vex_2src_1
, Vex_2src_2
} },
6759 { "vpshlq", { XM
, Vex_2src_1
, Vex_2src_2
} },
6761 { "vpshab", { XM
, Vex_2src_1
, Vex_2src_2
} },
6762 { "vpshaw", { XM
, Vex_2src_1
, Vex_2src_2
} },
6763 { "vpshad", { XM
, Vex_2src_1
, Vex_2src_2
} },
6764 { "vpshaq", { XM
, Vex_2src_1
, Vex_2src_2
} },
6807 { "vphaddbw", { XM
, EXxmm
} },
6808 { "vphaddbd", { XM
, EXxmm
} },
6809 { "vphaddbq", { XM
, EXxmm
} },
6812 { "vphaddwd", { XM
, EXxmm
} },
6813 { "vphaddwq", { XM
, EXxmm
} },
6818 { "vphadddq", { XM
, EXxmm
} },
6825 { "vphaddubw", { XM
, EXxmm
} },
6826 { "vphaddubd", { XM
, EXxmm
} },
6827 { "vphaddubq", { XM
, EXxmm
} },
6830 { "vphadduwd", { XM
, EXxmm
} },
6831 { "vphadduwq", { XM
, EXxmm
} },
6836 { "vphaddudq", { XM
, EXxmm
} },
6843 { "vphsubbw", { XM
, EXxmm
} },
6844 { "vphsubwd", { XM
, EXxmm
} },
6845 { "vphsubdq", { XM
, EXxmm
} },
6901 { REG_TABLE (REG_XOP_LWP
) },
7171 static const struct dis386 vex_table
[][256] = {
7193 { PREFIX_TABLE (PREFIX_VEX_10
) },
7194 { PREFIX_TABLE (PREFIX_VEX_11
) },
7195 { PREFIX_TABLE (PREFIX_VEX_12
) },
7196 { MOD_TABLE (MOD_VEX_13
) },
7197 { VEX_W_TABLE (VEX_W_14
) },
7198 { VEX_W_TABLE (VEX_W_15
) },
7199 { PREFIX_TABLE (PREFIX_VEX_16
) },
7200 { MOD_TABLE (MOD_VEX_17
) },
7220 { VEX_W_TABLE (VEX_W_28
) },
7221 { VEX_W_TABLE (VEX_W_29
) },
7222 { PREFIX_TABLE (PREFIX_VEX_2A
) },
7223 { MOD_TABLE (MOD_VEX_2B
) },
7224 { PREFIX_TABLE (PREFIX_VEX_2C
) },
7225 { PREFIX_TABLE (PREFIX_VEX_2D
) },
7226 { PREFIX_TABLE (PREFIX_VEX_2E
) },
7227 { PREFIX_TABLE (PREFIX_VEX_2F
) },
7265 { MOD_TABLE (MOD_VEX_50
) },
7266 { PREFIX_TABLE (PREFIX_VEX_51
) },
7267 { PREFIX_TABLE (PREFIX_VEX_52
) },
7268 { PREFIX_TABLE (PREFIX_VEX_53
) },
7269 { "vandpX", { XM
, Vex
, EXx
} },
7270 { "vandnpX", { XM
, Vex
, EXx
} },
7271 { "vorpX", { XM
, Vex
, EXx
} },
7272 { "vxorpX", { XM
, Vex
, EXx
} },
7274 { PREFIX_TABLE (PREFIX_VEX_58
) },
7275 { PREFIX_TABLE (PREFIX_VEX_59
) },
7276 { PREFIX_TABLE (PREFIX_VEX_5A
) },
7277 { PREFIX_TABLE (PREFIX_VEX_5B
) },
7278 { PREFIX_TABLE (PREFIX_VEX_5C
) },
7279 { PREFIX_TABLE (PREFIX_VEX_5D
) },
7280 { PREFIX_TABLE (PREFIX_VEX_5E
) },
7281 { PREFIX_TABLE (PREFIX_VEX_5F
) },
7283 { PREFIX_TABLE (PREFIX_VEX_60
) },
7284 { PREFIX_TABLE (PREFIX_VEX_61
) },
7285 { PREFIX_TABLE (PREFIX_VEX_62
) },
7286 { PREFIX_TABLE (PREFIX_VEX_63
) },
7287 { PREFIX_TABLE (PREFIX_VEX_64
) },
7288 { PREFIX_TABLE (PREFIX_VEX_65
) },
7289 { PREFIX_TABLE (PREFIX_VEX_66
) },
7290 { PREFIX_TABLE (PREFIX_VEX_67
) },
7292 { PREFIX_TABLE (PREFIX_VEX_68
) },
7293 { PREFIX_TABLE (PREFIX_VEX_69
) },
7294 { PREFIX_TABLE (PREFIX_VEX_6A
) },
7295 { PREFIX_TABLE (PREFIX_VEX_6B
) },
7296 { PREFIX_TABLE (PREFIX_VEX_6C
) },
7297 { PREFIX_TABLE (PREFIX_VEX_6D
) },
7298 { PREFIX_TABLE (PREFIX_VEX_6E
) },
7299 { PREFIX_TABLE (PREFIX_VEX_6F
) },
7301 { PREFIX_TABLE (PREFIX_VEX_70
) },
7302 { REG_TABLE (REG_VEX_71
) },
7303 { REG_TABLE (REG_VEX_72
) },
7304 { REG_TABLE (REG_VEX_73
) },
7305 { PREFIX_TABLE (PREFIX_VEX_74
) },
7306 { PREFIX_TABLE (PREFIX_VEX_75
) },
7307 { PREFIX_TABLE (PREFIX_VEX_76
) },
7308 { PREFIX_TABLE (PREFIX_VEX_77
) },
7314 { PREFIX_TABLE (PREFIX_VEX_7C
) },
7315 { PREFIX_TABLE (PREFIX_VEX_7D
) },
7316 { PREFIX_TABLE (PREFIX_VEX_7E
) },
7317 { PREFIX_TABLE (PREFIX_VEX_7F
) },
7370 { REG_TABLE (REG_VEX_AE
) },
7393 { PREFIX_TABLE (PREFIX_VEX_C2
) },
7395 { PREFIX_TABLE (PREFIX_VEX_C4
) },
7396 { PREFIX_TABLE (PREFIX_VEX_C5
) },
7397 { "vshufpX", { XM
, Vex
, EXx
, Ib
} },
7409 { PREFIX_TABLE (PREFIX_VEX_D0
) },
7410 { PREFIX_TABLE (PREFIX_VEX_D1
) },
7411 { PREFIX_TABLE (PREFIX_VEX_D2
) },
7412 { PREFIX_TABLE (PREFIX_VEX_D3
) },
7413 { PREFIX_TABLE (PREFIX_VEX_D4
) },
7414 { PREFIX_TABLE (PREFIX_VEX_D5
) },
7415 { PREFIX_TABLE (PREFIX_VEX_D6
) },
7416 { PREFIX_TABLE (PREFIX_VEX_D7
) },
7418 { PREFIX_TABLE (PREFIX_VEX_D8
) },
7419 { PREFIX_TABLE (PREFIX_VEX_D9
) },
7420 { PREFIX_TABLE (PREFIX_VEX_DA
) },
7421 { PREFIX_TABLE (PREFIX_VEX_DB
) },
7422 { PREFIX_TABLE (PREFIX_VEX_DC
) },
7423 { PREFIX_TABLE (PREFIX_VEX_DD
) },
7424 { PREFIX_TABLE (PREFIX_VEX_DE
) },
7425 { PREFIX_TABLE (PREFIX_VEX_DF
) },
7427 { PREFIX_TABLE (PREFIX_VEX_E0
) },
7428 { PREFIX_TABLE (PREFIX_VEX_E1
) },
7429 { PREFIX_TABLE (PREFIX_VEX_E2
) },
7430 { PREFIX_TABLE (PREFIX_VEX_E3
) },
7431 { PREFIX_TABLE (PREFIX_VEX_E4
) },
7432 { PREFIX_TABLE (PREFIX_VEX_E5
) },
7433 { PREFIX_TABLE (PREFIX_VEX_E6
) },
7434 { PREFIX_TABLE (PREFIX_VEX_E7
) },
7436 { PREFIX_TABLE (PREFIX_VEX_E8
) },
7437 { PREFIX_TABLE (PREFIX_VEX_E9
) },
7438 { PREFIX_TABLE (PREFIX_VEX_EA
) },
7439 { PREFIX_TABLE (PREFIX_VEX_EB
) },
7440 { PREFIX_TABLE (PREFIX_VEX_EC
) },
7441 { PREFIX_TABLE (PREFIX_VEX_ED
) },
7442 { PREFIX_TABLE (PREFIX_VEX_EE
) },
7443 { PREFIX_TABLE (PREFIX_VEX_EF
) },
7445 { PREFIX_TABLE (PREFIX_VEX_F0
) },
7446 { PREFIX_TABLE (PREFIX_VEX_F1
) },
7447 { PREFIX_TABLE (PREFIX_VEX_F2
) },
7448 { PREFIX_TABLE (PREFIX_VEX_F3
) },
7449 { PREFIX_TABLE (PREFIX_VEX_F4
) },
7450 { PREFIX_TABLE (PREFIX_VEX_F5
) },
7451 { PREFIX_TABLE (PREFIX_VEX_F6
) },
7452 { PREFIX_TABLE (PREFIX_VEX_F7
) },
7454 { PREFIX_TABLE (PREFIX_VEX_F8
) },
7455 { PREFIX_TABLE (PREFIX_VEX_F9
) },
7456 { PREFIX_TABLE (PREFIX_VEX_FA
) },
7457 { PREFIX_TABLE (PREFIX_VEX_FB
) },
7458 { PREFIX_TABLE (PREFIX_VEX_FC
) },
7459 { PREFIX_TABLE (PREFIX_VEX_FD
) },
7460 { PREFIX_TABLE (PREFIX_VEX_FE
) },
7466 { PREFIX_TABLE (PREFIX_VEX_3800
) },
7467 { PREFIX_TABLE (PREFIX_VEX_3801
) },
7468 { PREFIX_TABLE (PREFIX_VEX_3802
) },
7469 { PREFIX_TABLE (PREFIX_VEX_3803
) },
7470 { PREFIX_TABLE (PREFIX_VEX_3804
) },
7471 { PREFIX_TABLE (PREFIX_VEX_3805
) },
7472 { PREFIX_TABLE (PREFIX_VEX_3806
) },
7473 { PREFIX_TABLE (PREFIX_VEX_3807
) },
7475 { PREFIX_TABLE (PREFIX_VEX_3808
) },
7476 { PREFIX_TABLE (PREFIX_VEX_3809
) },
7477 { PREFIX_TABLE (PREFIX_VEX_380A
) },
7478 { PREFIX_TABLE (PREFIX_VEX_380B
) },
7479 { PREFIX_TABLE (PREFIX_VEX_380C
) },
7480 { PREFIX_TABLE (PREFIX_VEX_380D
) },
7481 { PREFIX_TABLE (PREFIX_VEX_380E
) },
7482 { PREFIX_TABLE (PREFIX_VEX_380F
) },
7491 { PREFIX_TABLE (PREFIX_VEX_3817
) },
7493 { PREFIX_TABLE (PREFIX_VEX_3818
) },
7494 { PREFIX_TABLE (PREFIX_VEX_3819
) },
7495 { PREFIX_TABLE (PREFIX_VEX_381A
) },
7497 { PREFIX_TABLE (PREFIX_VEX_381C
) },
7498 { PREFIX_TABLE (PREFIX_VEX_381D
) },
7499 { PREFIX_TABLE (PREFIX_VEX_381E
) },
7502 { PREFIX_TABLE (PREFIX_VEX_3820
) },
7503 { PREFIX_TABLE (PREFIX_VEX_3821
) },
7504 { PREFIX_TABLE (PREFIX_VEX_3822
) },
7505 { PREFIX_TABLE (PREFIX_VEX_3823
) },
7506 { PREFIX_TABLE (PREFIX_VEX_3824
) },
7507 { PREFIX_TABLE (PREFIX_VEX_3825
) },
7511 { PREFIX_TABLE (PREFIX_VEX_3828
) },
7512 { PREFIX_TABLE (PREFIX_VEX_3829
) },
7513 { PREFIX_TABLE (PREFIX_VEX_382A
) },
7514 { PREFIX_TABLE (PREFIX_VEX_382B
) },
7515 { PREFIX_TABLE (PREFIX_VEX_382C
) },
7516 { PREFIX_TABLE (PREFIX_VEX_382D
) },
7517 { PREFIX_TABLE (PREFIX_VEX_382E
) },
7518 { PREFIX_TABLE (PREFIX_VEX_382F
) },
7520 { PREFIX_TABLE (PREFIX_VEX_3830
) },
7521 { PREFIX_TABLE (PREFIX_VEX_3831
) },
7522 { PREFIX_TABLE (PREFIX_VEX_3832
) },
7523 { PREFIX_TABLE (PREFIX_VEX_3833
) },
7524 { PREFIX_TABLE (PREFIX_VEX_3834
) },
7525 { PREFIX_TABLE (PREFIX_VEX_3835
) },
7527 { PREFIX_TABLE (PREFIX_VEX_3837
) },
7529 { PREFIX_TABLE (PREFIX_VEX_3838
) },
7530 { PREFIX_TABLE (PREFIX_VEX_3839
) },
7531 { PREFIX_TABLE (PREFIX_VEX_383A
) },
7532 { PREFIX_TABLE (PREFIX_VEX_383B
) },
7533 { PREFIX_TABLE (PREFIX_VEX_383C
) },
7534 { PREFIX_TABLE (PREFIX_VEX_383D
) },
7535 { PREFIX_TABLE (PREFIX_VEX_383E
) },
7536 { PREFIX_TABLE (PREFIX_VEX_383F
) },
7538 { PREFIX_TABLE (PREFIX_VEX_3840
) },
7539 { PREFIX_TABLE (PREFIX_VEX_3841
) },
7634 { PREFIX_TABLE (PREFIX_VEX_3896
) },
7635 { PREFIX_TABLE (PREFIX_VEX_3897
) },
7637 { PREFIX_TABLE (PREFIX_VEX_3898
) },
7638 { PREFIX_TABLE (PREFIX_VEX_3899
) },
7639 { PREFIX_TABLE (PREFIX_VEX_389A
) },
7640 { PREFIX_TABLE (PREFIX_VEX_389B
) },
7641 { PREFIX_TABLE (PREFIX_VEX_389C
) },
7642 { PREFIX_TABLE (PREFIX_VEX_389D
) },
7643 { PREFIX_TABLE (PREFIX_VEX_389E
) },
7644 { PREFIX_TABLE (PREFIX_VEX_389F
) },
7652 { PREFIX_TABLE (PREFIX_VEX_38A6
) },
7653 { PREFIX_TABLE (PREFIX_VEX_38A7
) },
7655 { PREFIX_TABLE (PREFIX_VEX_38A8
) },
7656 { PREFIX_TABLE (PREFIX_VEX_38A9
) },
7657 { PREFIX_TABLE (PREFIX_VEX_38AA
) },
7658 { PREFIX_TABLE (PREFIX_VEX_38AB
) },
7659 { PREFIX_TABLE (PREFIX_VEX_38AC
) },
7660 { PREFIX_TABLE (PREFIX_VEX_38AD
) },
7661 { PREFIX_TABLE (PREFIX_VEX_38AE
) },
7662 { PREFIX_TABLE (PREFIX_VEX_38AF
) },
7670 { PREFIX_TABLE (PREFIX_VEX_38B6
) },
7671 { PREFIX_TABLE (PREFIX_VEX_38B7
) },
7673 { PREFIX_TABLE (PREFIX_VEX_38B8
) },
7674 { PREFIX_TABLE (PREFIX_VEX_38B9
) },
7675 { PREFIX_TABLE (PREFIX_VEX_38BA
) },
7676 { PREFIX_TABLE (PREFIX_VEX_38BB
) },
7677 { PREFIX_TABLE (PREFIX_VEX_38BC
) },
7678 { PREFIX_TABLE (PREFIX_VEX_38BD
) },
7679 { PREFIX_TABLE (PREFIX_VEX_38BE
) },
7680 { PREFIX_TABLE (PREFIX_VEX_38BF
) },
7712 { PREFIX_TABLE (PREFIX_VEX_38DB
) },
7713 { PREFIX_TABLE (PREFIX_VEX_38DC
) },
7714 { PREFIX_TABLE (PREFIX_VEX_38DD
) },
7715 { PREFIX_TABLE (PREFIX_VEX_38DE
) },
7716 { PREFIX_TABLE (PREFIX_VEX_38DF
) },
7761 { PREFIX_TABLE (PREFIX_VEX_3A04
) },
7762 { PREFIX_TABLE (PREFIX_VEX_3A05
) },
7763 { PREFIX_TABLE (PREFIX_VEX_3A06
) },
7766 { PREFIX_TABLE (PREFIX_VEX_3A08
) },
7767 { PREFIX_TABLE (PREFIX_VEX_3A09
) },
7768 { PREFIX_TABLE (PREFIX_VEX_3A0A
) },
7769 { PREFIX_TABLE (PREFIX_VEX_3A0B
) },
7770 { PREFIX_TABLE (PREFIX_VEX_3A0C
) },
7771 { PREFIX_TABLE (PREFIX_VEX_3A0D
) },
7772 { PREFIX_TABLE (PREFIX_VEX_3A0E
) },
7773 { PREFIX_TABLE (PREFIX_VEX_3A0F
) },
7779 { PREFIX_TABLE (PREFIX_VEX_3A14
) },
7780 { PREFIX_TABLE (PREFIX_VEX_3A15
) },
7781 { PREFIX_TABLE (PREFIX_VEX_3A16
) },
7782 { PREFIX_TABLE (PREFIX_VEX_3A17
) },
7784 { PREFIX_TABLE (PREFIX_VEX_3A18
) },
7785 { PREFIX_TABLE (PREFIX_VEX_3A19
) },
7793 { PREFIX_TABLE (PREFIX_VEX_3A20
) },
7794 { PREFIX_TABLE (PREFIX_VEX_3A21
) },
7795 { PREFIX_TABLE (PREFIX_VEX_3A22
) },
7829 { PREFIX_TABLE (PREFIX_VEX_3A40
) },
7830 { PREFIX_TABLE (PREFIX_VEX_3A41
) },
7831 { PREFIX_TABLE (PREFIX_VEX_3A42
) },
7833 { PREFIX_TABLE (PREFIX_VEX_3A44
) },
7840 { PREFIX_TABLE (PREFIX_VEX_3A4A
) },
7841 { PREFIX_TABLE (PREFIX_VEX_3A4B
) },
7842 { PREFIX_TABLE (PREFIX_VEX_3A4C
) },
7860 { PREFIX_TABLE (PREFIX_VEX_3A5C
) },
7861 { PREFIX_TABLE (PREFIX_VEX_3A5D
) },
7862 { PREFIX_TABLE (PREFIX_VEX_3A5E
) },
7863 { PREFIX_TABLE (PREFIX_VEX_3A5F
) },
7865 { PREFIX_TABLE (PREFIX_VEX_3A60
) },
7866 { PREFIX_TABLE (PREFIX_VEX_3A61
) },
7867 { PREFIX_TABLE (PREFIX_VEX_3A62
) },
7868 { PREFIX_TABLE (PREFIX_VEX_3A63
) },
7874 { PREFIX_TABLE (PREFIX_VEX_3A68
) },
7875 { PREFIX_TABLE (PREFIX_VEX_3A69
) },
7876 { PREFIX_TABLE (PREFIX_VEX_3A6A
) },
7877 { PREFIX_TABLE (PREFIX_VEX_3A6B
) },
7878 { PREFIX_TABLE (PREFIX_VEX_3A6C
) },
7879 { PREFIX_TABLE (PREFIX_VEX_3A6D
) },
7880 { PREFIX_TABLE (PREFIX_VEX_3A6E
) },
7881 { PREFIX_TABLE (PREFIX_VEX_3A6F
) },
7892 { PREFIX_TABLE (PREFIX_VEX_3A78
) },
7893 { PREFIX_TABLE (PREFIX_VEX_3A79
) },
7894 { PREFIX_TABLE (PREFIX_VEX_3A7A
) },
7895 { PREFIX_TABLE (PREFIX_VEX_3A7B
) },
7896 { PREFIX_TABLE (PREFIX_VEX_3A7C
) },
7897 { PREFIX_TABLE (PREFIX_VEX_3A7D
) },
7898 { PREFIX_TABLE (PREFIX_VEX_3A7E
) },
7899 { PREFIX_TABLE (PREFIX_VEX_3A7F
) },
8007 { PREFIX_TABLE (PREFIX_VEX_3ADF
) },
8047 static const struct dis386 vex_len_table
[][2] = {
8048 /* VEX_LEN_10_P_1 */
8050 { VEX_W_TABLE (VEX_W_10_P_1
) },
8053 /* VEX_LEN_10_P_3 */
8055 { VEX_W_TABLE (VEX_W_10_P_3
) },
8058 /* VEX_LEN_11_P_1 */
8060 { VEX_W_TABLE (VEX_W_11_P_1
) },
8063 /* VEX_LEN_11_P_3 */
8065 { VEX_W_TABLE (VEX_W_11_P_3
) },
8068 /* VEX_LEN_12_P_0_M_0 */
8070 { VEX_W_TABLE (VEX_W_12_P_0_M_0
) },
8073 /* VEX_LEN_12_P_0_M_1 */
8075 { VEX_W_TABLE (VEX_W_12_P_0_M_1
) },
8078 /* VEX_LEN_12_P_2 */
8080 { VEX_W_TABLE (VEX_W_12_P_2
) },
8083 /* VEX_LEN_13_M_0 */
8085 { VEX_W_TABLE (VEX_W_13_M_0
) },
8088 /* VEX_LEN_16_P_0_M_0 */
8090 { VEX_W_TABLE (VEX_W_16_P_0_M_0
) },
8093 /* VEX_LEN_16_P_0_M_1 */
8095 { VEX_W_TABLE (VEX_W_16_P_0_M_1
) },
8098 /* VEX_LEN_16_P_2 */
8100 { VEX_W_TABLE (VEX_W_16_P_2
) },
8103 /* VEX_LEN_17_M_0 */
8105 { VEX_W_TABLE (VEX_W_17_M_0
) },
8108 /* VEX_LEN_2A_P_1 */
8110 { "vcvtsi2ss%LQ", { XM
, Vex128
, Ev
} },
8113 /* VEX_LEN_2A_P_3 */
8115 { "vcvtsi2sd%LQ", { XM
, Vex128
, Ev
} },
8118 /* VEX_LEN_2C_P_1 */
8120 { "vcvttss2siY", { Gv
, EXd
} },
8123 /* VEX_LEN_2C_P_3 */
8125 { "vcvttsd2siY", { Gv
, EXq
} },
8128 /* VEX_LEN_2D_P_1 */
8130 { "vcvtss2siY", { Gv
, EXd
} },
8133 /* VEX_LEN_2D_P_3 */
8135 { "vcvtsd2siY", { Gv
, EXq
} },
8138 /* VEX_LEN_2E_P_0 */
8140 { VEX_W_TABLE (VEX_W_2E_P_0
) },
8143 /* VEX_LEN_2E_P_2 */
8145 { VEX_W_TABLE (VEX_W_2E_P_2
) },
8148 /* VEX_LEN_2F_P_0 */
8150 { VEX_W_TABLE (VEX_W_2F_P_0
) },
8153 /* VEX_LEN_2F_P_2 */
8155 { VEX_W_TABLE (VEX_W_2F_P_2
) },
8158 /* VEX_LEN_51_P_1 */
8160 { VEX_W_TABLE (VEX_W_51_P_1
) },
8163 /* VEX_LEN_51_P_3 */
8165 { VEX_W_TABLE (VEX_W_51_P_3
) },
8168 /* VEX_LEN_52_P_1 */
8170 { VEX_W_TABLE (VEX_W_52_P_1
) },
8173 /* VEX_LEN_53_P_1 */
8175 { VEX_W_TABLE (VEX_W_53_P_1
) },
8178 /* VEX_LEN_58_P_1 */
8180 { VEX_W_TABLE (VEX_W_58_P_1
) },
8183 /* VEX_LEN_58_P_3 */
8185 { VEX_W_TABLE (VEX_W_58_P_3
) },
8188 /* VEX_LEN_59_P_1 */
8190 { VEX_W_TABLE (VEX_W_59_P_1
) },
8193 /* VEX_LEN_59_P_3 */
8195 { VEX_W_TABLE (VEX_W_59_P_3
) },
8198 /* VEX_LEN_5A_P_1 */
8200 { VEX_W_TABLE (VEX_W_5A_P_1
) },
8203 /* VEX_LEN_5A_P_3 */
8205 { VEX_W_TABLE (VEX_W_5A_P_3
) },
8208 /* VEX_LEN_5C_P_1 */
8210 { VEX_W_TABLE (VEX_W_5C_P_1
) },
8213 /* VEX_LEN_5C_P_3 */
8215 { VEX_W_TABLE (VEX_W_5C_P_3
) },
8218 /* VEX_LEN_5D_P_1 */
8220 { VEX_W_TABLE (VEX_W_5D_P_1
) },
8223 /* VEX_LEN_5D_P_3 */
8225 { VEX_W_TABLE (VEX_W_5D_P_3
) },
8228 /* VEX_LEN_5E_P_1 */
8230 { VEX_W_TABLE (VEX_W_5E_P_1
) },
8233 /* VEX_LEN_5E_P_3 */
8235 { VEX_W_TABLE (VEX_W_5E_P_3
) },
8238 /* VEX_LEN_5F_P_1 */
8240 { VEX_W_TABLE (VEX_W_5F_P_1
) },
8243 /* VEX_LEN_5F_P_3 */
8245 { VEX_W_TABLE (VEX_W_5F_P_3
) },
8248 /* VEX_LEN_60_P_2 */
8250 { VEX_W_TABLE (VEX_W_60_P_2
) },
8253 /* VEX_LEN_61_P_2 */
8255 { VEX_W_TABLE (VEX_W_61_P_2
) },
8258 /* VEX_LEN_62_P_2 */
8260 { VEX_W_TABLE (VEX_W_62_P_2
) },
8263 /* VEX_LEN_63_P_2 */
8265 { VEX_W_TABLE (VEX_W_63_P_2
) },
8268 /* VEX_LEN_64_P_2 */
8270 { VEX_W_TABLE (VEX_W_64_P_2
) },
8273 /* VEX_LEN_65_P_2 */
8275 { VEX_W_TABLE (VEX_W_65_P_2
) },
8278 /* VEX_LEN_66_P_2 */
8280 { VEX_W_TABLE (VEX_W_66_P_2
) },
8283 /* VEX_LEN_67_P_2 */
8285 { VEX_W_TABLE (VEX_W_67_P_2
) },
8288 /* VEX_LEN_68_P_2 */
8290 { VEX_W_TABLE (VEX_W_68_P_2
) },
8293 /* VEX_LEN_69_P_2 */
8295 { VEX_W_TABLE (VEX_W_69_P_2
) },
8298 /* VEX_LEN_6A_P_2 */
8300 { VEX_W_TABLE (VEX_W_6A_P_2
) },
8303 /* VEX_LEN_6B_P_2 */
8305 { VEX_W_TABLE (VEX_W_6B_P_2
) },
8308 /* VEX_LEN_6C_P_2 */
8310 { VEX_W_TABLE (VEX_W_6C_P_2
) },
8313 /* VEX_LEN_6D_P_2 */
8315 { VEX_W_TABLE (VEX_W_6D_P_2
) },
8318 /* VEX_LEN_6E_P_2 */
8320 { "vmovK", { XM
, Edq
} },
8323 /* VEX_LEN_70_P_1 */
8325 { VEX_W_TABLE (VEX_W_70_P_1
) },
8328 /* VEX_LEN_70_P_2 */
8330 { VEX_W_TABLE (VEX_W_70_P_2
) },
8333 /* VEX_LEN_70_P_3 */
8335 { VEX_W_TABLE (VEX_W_70_P_3
) },
8338 /* VEX_LEN_71_R_2_P_2 */
8340 { VEX_W_TABLE (VEX_W_71_R_2_P_2
) },
8343 /* VEX_LEN_71_R_4_P_2 */
8345 { VEX_W_TABLE (VEX_W_71_R_4_P_2
) },
8348 /* VEX_LEN_71_R_6_P_2 */
8350 { VEX_W_TABLE (VEX_W_71_R_6_P_2
) },
8353 /* VEX_LEN_72_R_2_P_2 */
8355 { VEX_W_TABLE (VEX_W_72_R_2_P_2
) },
8358 /* VEX_LEN_72_R_4_P_2 */
8360 { VEX_W_TABLE (VEX_W_72_R_4_P_2
) },
8363 /* VEX_LEN_72_R_6_P_2 */
8365 { VEX_W_TABLE (VEX_W_72_R_6_P_2
) },
8368 /* VEX_LEN_73_R_2_P_2 */
8370 { VEX_W_TABLE (VEX_W_73_R_2_P_2
) },
8373 /* VEX_LEN_73_R_3_P_2 */
8375 { VEX_W_TABLE (VEX_W_73_R_3_P_2
) },
8378 /* VEX_LEN_73_R_6_P_2 */
8380 { VEX_W_TABLE (VEX_W_73_R_6_P_2
) },
8383 /* VEX_LEN_73_R_7_P_2 */
8385 { VEX_W_TABLE (VEX_W_73_R_7_P_2
) },
8388 /* VEX_LEN_74_P_2 */
8390 { VEX_W_TABLE (VEX_W_74_P_2
) },
8393 /* VEX_LEN_75_P_2 */
8395 { VEX_W_TABLE (VEX_W_75_P_2
) },
8398 /* VEX_LEN_76_P_2 */
8400 { VEX_W_TABLE (VEX_W_76_P_2
) },
8403 /* VEX_LEN_7E_P_1 */
8405 { VEX_W_TABLE (VEX_W_7E_P_1
) },
8408 /* VEX_LEN_7E_P_2 */
8410 { "vmovK", { Edq
, XM
} },
8413 /* VEX_LEN_AE_R_2_M_0 */
8415 { VEX_W_TABLE (VEX_W_AE_R_2_M_0
) },
8418 /* VEX_LEN_AE_R_3_M_0 */
8420 { VEX_W_TABLE (VEX_W_AE_R_3_M_0
) },
8423 /* VEX_LEN_C2_P_1 */
8425 { VEX_W_TABLE (VEX_W_C2_P_1
) },
8428 /* VEX_LEN_C2_P_3 */
8430 { VEX_W_TABLE (VEX_W_C2_P_3
) },
8433 /* VEX_LEN_C4_P_2 */
8435 { VEX_W_TABLE (VEX_W_C4_P_2
) },
8438 /* VEX_LEN_C5_P_2 */
8440 { VEX_W_TABLE (VEX_W_C5_P_2
) },
8443 /* VEX_LEN_D1_P_2 */
8445 { VEX_W_TABLE (VEX_W_D1_P_2
) },
8448 /* VEX_LEN_D2_P_2 */
8450 { VEX_W_TABLE (VEX_W_D2_P_2
) },
8453 /* VEX_LEN_D3_P_2 */
8455 { VEX_W_TABLE (VEX_W_D3_P_2
) },
8458 /* VEX_LEN_D4_P_2 */
8460 { VEX_W_TABLE (VEX_W_D4_P_2
) },
8463 /* VEX_LEN_D5_P_2 */
8465 { VEX_W_TABLE (VEX_W_D5_P_2
) },
8468 /* VEX_LEN_D6_P_2 */
8470 { VEX_W_TABLE (VEX_W_D6_P_2
) },
8473 /* VEX_LEN_D7_P_2_M_1 */
8475 { VEX_W_TABLE (VEX_W_D7_P_2_M_1
) },
8478 /* VEX_LEN_D8_P_2 */
8480 { VEX_W_TABLE (VEX_W_D8_P_2
) },
8483 /* VEX_LEN_D9_P_2 */
8485 { VEX_W_TABLE (VEX_W_D9_P_2
) },
8488 /* VEX_LEN_DA_P_2 */
8490 { VEX_W_TABLE (VEX_W_DA_P_2
) },
8493 /* VEX_LEN_DB_P_2 */
8495 { VEX_W_TABLE (VEX_W_DB_P_2
) },
8498 /* VEX_LEN_DC_P_2 */
8500 { VEX_W_TABLE (VEX_W_DC_P_2
) },
8503 /* VEX_LEN_DD_P_2 */
8505 { VEX_W_TABLE (VEX_W_DD_P_2
) },
8508 /* VEX_LEN_DE_P_2 */
8510 { VEX_W_TABLE (VEX_W_DE_P_2
) },
8513 /* VEX_LEN_DF_P_2 */
8515 { VEX_W_TABLE (VEX_W_DF_P_2
) },
8518 /* VEX_LEN_E0_P_2 */
8520 { VEX_W_TABLE (VEX_W_E0_P_2
) },
8523 /* VEX_LEN_E1_P_2 */
8525 { VEX_W_TABLE (VEX_W_E1_P_2
) },
8528 /* VEX_LEN_E2_P_2 */
8530 { VEX_W_TABLE (VEX_W_E2_P_2
) },
8533 /* VEX_LEN_E3_P_2 */
8535 { VEX_W_TABLE (VEX_W_E3_P_2
) },
8538 /* VEX_LEN_E4_P_2 */
8540 { VEX_W_TABLE (VEX_W_E4_P_2
) },
8543 /* VEX_LEN_E5_P_2 */
8545 { VEX_W_TABLE (VEX_W_E5_P_2
) },
8548 /* VEX_LEN_E8_P_2 */
8550 { VEX_W_TABLE (VEX_W_E8_P_2
) },
8553 /* VEX_LEN_E9_P_2 */
8555 { VEX_W_TABLE (VEX_W_E9_P_2
) },
8558 /* VEX_LEN_EA_P_2 */
8560 { VEX_W_TABLE (VEX_W_EA_P_2
) },
8563 /* VEX_LEN_EB_P_2 */
8565 { VEX_W_TABLE (VEX_W_EB_P_2
) },
8568 /* VEX_LEN_EC_P_2 */
8570 { VEX_W_TABLE (VEX_W_EC_P_2
) },
8573 /* VEX_LEN_ED_P_2 */
8575 { VEX_W_TABLE (VEX_W_ED_P_2
) },
8578 /* VEX_LEN_EE_P_2 */
8580 { VEX_W_TABLE (VEX_W_EE_P_2
) },
8583 /* VEX_LEN_EF_P_2 */
8585 { VEX_W_TABLE (VEX_W_EF_P_2
) },
8588 /* VEX_LEN_F1_P_2 */
8590 { VEX_W_TABLE (VEX_W_F1_P_2
) },
8593 /* VEX_LEN_F2_P_2 */
8595 { VEX_W_TABLE (VEX_W_F2_P_2
) },
8598 /* VEX_LEN_F3_P_2 */
8600 { VEX_W_TABLE (VEX_W_F3_P_2
) },
8603 /* VEX_LEN_F4_P_2 */
8605 { VEX_W_TABLE (VEX_W_F4_P_2
) },
8608 /* VEX_LEN_F5_P_2 */
8610 { VEX_W_TABLE (VEX_W_F5_P_2
) },
8613 /* VEX_LEN_F6_P_2 */
8615 { VEX_W_TABLE (VEX_W_F6_P_2
) },
8618 /* VEX_LEN_F7_P_2 */
8620 { VEX_W_TABLE (VEX_W_F7_P_2
) },
8623 /* VEX_LEN_F8_P_2 */
8625 { VEX_W_TABLE (VEX_W_F8_P_2
) },
8628 /* VEX_LEN_F9_P_2 */
8630 { VEX_W_TABLE (VEX_W_F9_P_2
) },
8633 /* VEX_LEN_FA_P_2 */
8635 { VEX_W_TABLE (VEX_W_FA_P_2
) },
8638 /* VEX_LEN_FB_P_2 */
8640 { VEX_W_TABLE (VEX_W_FB_P_2
) },
8643 /* VEX_LEN_FC_P_2 */
8645 { VEX_W_TABLE (VEX_W_FC_P_2
) },
8648 /* VEX_LEN_FD_P_2 */
8650 { VEX_W_TABLE (VEX_W_FD_P_2
) },
8653 /* VEX_LEN_FE_P_2 */
8655 { VEX_W_TABLE (VEX_W_FE_P_2
) },
8658 /* VEX_LEN_3800_P_2 */
8660 { VEX_W_TABLE (VEX_W_3800_P_2
) },
8663 /* VEX_LEN_3801_P_2 */
8665 { VEX_W_TABLE (VEX_W_3801_P_2
) },
8668 /* VEX_LEN_3802_P_2 */
8670 { VEX_W_TABLE (VEX_W_3802_P_2
) },
8673 /* VEX_LEN_3803_P_2 */
8675 { VEX_W_TABLE (VEX_W_3803_P_2
) },
8678 /* VEX_LEN_3804_P_2 */
8680 { VEX_W_TABLE (VEX_W_3804_P_2
) },
8683 /* VEX_LEN_3805_P_2 */
8685 { VEX_W_TABLE (VEX_W_3805_P_2
) },
8688 /* VEX_LEN_3806_P_2 */
8690 { VEX_W_TABLE (VEX_W_3806_P_2
) },
8693 /* VEX_LEN_3807_P_2 */
8695 { VEX_W_TABLE (VEX_W_3807_P_2
) },
8698 /* VEX_LEN_3808_P_2 */
8700 { VEX_W_TABLE (VEX_W_3808_P_2
) },
8703 /* VEX_LEN_3809_P_2 */
8705 { VEX_W_TABLE (VEX_W_3809_P_2
) },
8708 /* VEX_LEN_380A_P_2 */
8710 { VEX_W_TABLE (VEX_W_380A_P_2
) },
8713 /* VEX_LEN_380B_P_2 */
8715 { VEX_W_TABLE (VEX_W_380B_P_2
) },
8718 /* VEX_LEN_3819_P_2_M_0 */
8721 { VEX_W_TABLE (VEX_W_3819_P_2_M_0
) },
8724 /* VEX_LEN_381A_P_2_M_0 */
8727 { VEX_W_TABLE (VEX_W_381A_P_2_M_0
) },
8730 /* VEX_LEN_381C_P_2 */
8732 { VEX_W_TABLE (VEX_W_381C_P_2
) },
8735 /* VEX_LEN_381D_P_2 */
8737 { VEX_W_TABLE (VEX_W_381D_P_2
) },
8740 /* VEX_LEN_381E_P_2 */
8742 { VEX_W_TABLE (VEX_W_381E_P_2
) },
8745 /* VEX_LEN_3820_P_2 */
8747 { VEX_W_TABLE (VEX_W_3820_P_2
) },
8750 /* VEX_LEN_3821_P_2 */
8752 { VEX_W_TABLE (VEX_W_3821_P_2
) },
8755 /* VEX_LEN_3822_P_2 */
8757 { VEX_W_TABLE (VEX_W_3822_P_2
) },
8760 /* VEX_LEN_3823_P_2 */
8762 { VEX_W_TABLE (VEX_W_3823_P_2
) },
8765 /* VEX_LEN_3824_P_2 */
8767 { VEX_W_TABLE (VEX_W_3824_P_2
) },
8770 /* VEX_LEN_3825_P_2 */
8772 { VEX_W_TABLE (VEX_W_3825_P_2
) },
8775 /* VEX_LEN_3828_P_2 */
8777 { VEX_W_TABLE (VEX_W_3828_P_2
) },
8780 /* VEX_LEN_3829_P_2 */
8782 { VEX_W_TABLE (VEX_W_3829_P_2
) },
8785 /* VEX_LEN_382A_P_2_M_0 */
8787 { VEX_W_TABLE (VEX_W_382A_P_2_M_0
) },
8790 /* VEX_LEN_382B_P_2 */
8792 { VEX_W_TABLE (VEX_W_382B_P_2
) },
8795 /* VEX_LEN_3830_P_2 */
8797 { VEX_W_TABLE (VEX_W_3830_P_2
) },
8800 /* VEX_LEN_3831_P_2 */
8802 { VEX_W_TABLE (VEX_W_3831_P_2
) },
8805 /* VEX_LEN_3832_P_2 */
8807 { VEX_W_TABLE (VEX_W_3832_P_2
) },
8810 /* VEX_LEN_3833_P_2 */
8812 { VEX_W_TABLE (VEX_W_3833_P_2
) },
8815 /* VEX_LEN_3834_P_2 */
8817 { VEX_W_TABLE (VEX_W_3834_P_2
) },
8820 /* VEX_LEN_3835_P_2 */
8822 { VEX_W_TABLE (VEX_W_3835_P_2
) },
8825 /* VEX_LEN_3837_P_2 */
8827 { VEX_W_TABLE (VEX_W_3837_P_2
) },
8830 /* VEX_LEN_3838_P_2 */
8832 { VEX_W_TABLE (VEX_W_3838_P_2
) },
8835 /* VEX_LEN_3839_P_2 */
8837 { VEX_W_TABLE (VEX_W_3839_P_2
) },
8840 /* VEX_LEN_383A_P_2 */
8842 { VEX_W_TABLE (VEX_W_383A_P_2
) },
8845 /* VEX_LEN_383B_P_2 */
8847 { VEX_W_TABLE (VEX_W_383B_P_2
) },
8850 /* VEX_LEN_383C_P_2 */
8852 { VEX_W_TABLE (VEX_W_383C_P_2
) },
8855 /* VEX_LEN_383D_P_2 */
8857 { VEX_W_TABLE (VEX_W_383D_P_2
) },
8860 /* VEX_LEN_383E_P_2 */
8862 { VEX_W_TABLE (VEX_W_383E_P_2
) },
8865 /* VEX_LEN_383F_P_2 */
8867 { VEX_W_TABLE (VEX_W_383F_P_2
) },
8870 /* VEX_LEN_3840_P_2 */
8872 { VEX_W_TABLE (VEX_W_3840_P_2
) },
8875 /* VEX_LEN_3841_P_2 */
8877 { VEX_W_TABLE (VEX_W_3841_P_2
) },
8880 /* VEX_LEN_38DB_P_2 */
8882 { VEX_W_TABLE (VEX_W_38DB_P_2
) },
8885 /* VEX_LEN_38DC_P_2 */
8887 { VEX_W_TABLE (VEX_W_38DC_P_2
) },
8890 /* VEX_LEN_38DD_P_2 */
8892 { VEX_W_TABLE (VEX_W_38DD_P_2
) },
8895 /* VEX_LEN_38DE_P_2 */
8897 { VEX_W_TABLE (VEX_W_38DE_P_2
) },
8900 /* VEX_LEN_38DF_P_2 */
8902 { VEX_W_TABLE (VEX_W_38DF_P_2
) },
8905 /* VEX_LEN_3A06_P_2 */
8908 { VEX_W_TABLE (VEX_W_3A06_P_2
) },
8911 /* VEX_LEN_3A0A_P_2 */
8913 { VEX_W_TABLE (VEX_W_3A0A_P_2
) },
8916 /* VEX_LEN_3A0B_P_2 */
8918 { VEX_W_TABLE (VEX_W_3A0B_P_2
) },
8921 /* VEX_LEN_3A0E_P_2 */
8923 { VEX_W_TABLE (VEX_W_3A0E_P_2
) },
8926 /* VEX_LEN_3A0F_P_2 */
8928 { VEX_W_TABLE (VEX_W_3A0F_P_2
) },
8931 /* VEX_LEN_3A14_P_2 */
8933 { VEX_W_TABLE (VEX_W_3A14_P_2
) },
8936 /* VEX_LEN_3A15_P_2 */
8938 { VEX_W_TABLE (VEX_W_3A15_P_2
) },
8941 /* VEX_LEN_3A16_P_2 */
8943 { "vpextrK", { Edq
, XM
, Ib
} },
8946 /* VEX_LEN_3A17_P_2 */
8948 { "vextractps", { Edqd
, XM
, Ib
} },
8951 /* VEX_LEN_3A18_P_2 */
8954 { VEX_W_TABLE (VEX_W_3A18_P_2
) },
8957 /* VEX_LEN_3A19_P_2 */
8960 { VEX_W_TABLE (VEX_W_3A19_P_2
) },
8963 /* VEX_LEN_3A20_P_2 */
8965 { VEX_W_TABLE (VEX_W_3A20_P_2
) },
8968 /* VEX_LEN_3A21_P_2 */
8970 { VEX_W_TABLE (VEX_W_3A21_P_2
) },
8973 /* VEX_LEN_3A22_P_2 */
8975 { "vpinsrK", { XM
, Vex128
, Edq
, Ib
} },
8978 /* VEX_LEN_3A41_P_2 */
8980 { VEX_W_TABLE (VEX_W_3A41_P_2
) },
8983 /* VEX_LEN_3A42_P_2 */
8985 { VEX_W_TABLE (VEX_W_3A42_P_2
) },
8988 /* VEX_LEN_3A44_P_2 */
8990 { VEX_W_TABLE (VEX_W_3A44_P_2
) },
8993 /* VEX_LEN_3A4C_P_2 */
8995 { VEX_W_TABLE (VEX_W_3A4C_P_2
) },
8998 /* VEX_LEN_3A60_P_2 */
9000 { VEX_W_TABLE (VEX_W_3A60_P_2
) },
9003 /* VEX_LEN_3A61_P_2 */
9005 { VEX_W_TABLE (VEX_W_3A61_P_2
) },
9008 /* VEX_LEN_3A62_P_2 */
9010 { VEX_W_TABLE (VEX_W_3A62_P_2
) },
9013 /* VEX_LEN_3A63_P_2 */
9015 { VEX_W_TABLE (VEX_W_3A63_P_2
) },
9018 /* VEX_LEN_3A6A_P_2 */
9020 { "vfmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
, VexI4
} },
9023 /* VEX_LEN_3A6B_P_2 */
9025 { "vfmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
, VexI4
} },
9028 /* VEX_LEN_3A6E_P_2 */
9030 { "vfmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
, VexI4
} },
9033 /* VEX_LEN_3A6F_P_2 */
9035 { "vfmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
, VexI4
} },
9038 /* VEX_LEN_3A7A_P_2 */
9040 { "vfnmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
, VexI4
} },
9043 /* VEX_LEN_3A7B_P_2 */
9045 { "vfnmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
, VexI4
} },
9048 /* VEX_LEN_3A7E_P_2 */
9050 { "vfnmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
, VexI4
} },
9053 /* VEX_LEN_3A7F_P_2 */
9055 { "vfnmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
, VexI4
} },
9058 /* VEX_LEN_3ADF_P_2 */
9060 { VEX_W_TABLE (VEX_W_3ADF_P_2
) },
9063 /* VEX_LEN_XOP_09_80 */
9065 { "vfrczps", { XM
, EXxmm
} },
9066 { "vfrczps", { XM
, EXymmq
} },
9069 /* VEX_LEN_XOP_09_81 */
9071 { "vfrczpd", { XM
, EXxmm
} },
9072 { "vfrczpd", { XM
, EXymmq
} },
9076 static const struct dis386 vex_w_table
[][2] = {
9079 { "vmovups", { XM
, EXx
} },
9083 { "vmovss", { XMVex
, Vex128
, EXd
} },
9087 { "vmovupd", { XM
, EXx
} },
9091 { "vmovsd", { XMVex
, Vex128
, EXq
} },
9095 { "vmovups", { EXxS
, XM
} },
9099 { "vmovss", { EXdVexS
, Vex128
, XM
} },
9103 { "vmovupd", { EXxS
, XM
} },
9107 { "vmovsd", { EXqVexS
, Vex128
, XM
} },
9110 /* VEX_W_12_P_0_M_0 */
9111 { "vmovlps", { XM
, Vex128
, EXq
} },
9114 /* VEX_W_12_P_0_M_1 */
9115 { "vmovhlps", { XM
, Vex128
, EXq
} },
9119 { "vmovsldup", { XM
, EXx
} },
9123 { "vmovlpd", { XM
, Vex128
, EXq
} },
9127 { "vmovddup", { XM
, EXymmq
} },
9131 { "vmovlpX", { EXq
, XM
} },
9135 { "vunpcklpX", { XM
, Vex
, EXx
} },
9139 { "vunpckhpX", { XM
, Vex
, EXx
} },
9142 /* VEX_W_16_P_0_M_0 */
9143 { "vmovhps", { XM
, Vex128
, EXq
} },
9146 /* VEX_W_16_P_0_M_1 */
9147 { "vmovlhps", { XM
, Vex128
, EXq
} },
9151 { "vmovshdup", { XM
, EXx
} },
9155 { "vmovhpd", { XM
, Vex128
, EXq
} },
9159 { "vmovhpX", { EXq
, XM
} },
9163 { "vmovapX", { XM
, EXx
} },
9167 { "vmovapX", { EXxS
, XM
} },
9171 { "vmovntpX", { Mx
, XM
} },
9175 { "vucomiss", { XM
, EXd
} },
9179 { "vucomisd", { XM
, EXq
} },
9183 { "vcomiss", { XM
, EXd
} },
9187 { "vcomisd", { XM
, EXq
} },
9191 { "vmovmskpX", { Gdq
, XS
} },
9195 { "vsqrtps", { XM
, EXx
} },
9199 { "vsqrtss", { XM
, Vex128
, EXd
} },
9203 { "vsqrtpd", { XM
, EXx
} },
9207 { "vsqrtsd", { XM
, Vex128
, EXq
} },
9211 { "vrsqrtps", { XM
, EXx
} },
9215 { "vrsqrtss", { XM
, Vex128
, EXd
} },
9219 { "vrcpps", { XM
, EXx
} },
9223 { "vrcpss", { XM
, Vex128
, EXd
} },
9227 { "vaddps", { XM
, Vex
, EXx
} },
9231 { "vaddss", { XM
, Vex128
, EXd
} },
9235 { "vaddpd", { XM
, Vex
, EXx
} },
9239 { "vaddsd", { XM
, Vex128
, EXq
} },
9243 { "vmulps", { XM
, Vex
, EXx
} },
9247 { "vmulss", { XM
, Vex128
, EXd
} },
9251 { "vmulpd", { XM
, Vex
, EXx
} },
9255 { "vmulsd", { XM
, Vex128
, EXq
} },
9259 { "vcvtps2pd", { XM
, EXxmmq
} },
9263 { "vcvtss2sd", { XM
, Vex128
, EXd
} },
9267 { "vcvtsd2ss", { XM
, Vex128
, EXq
} },
9271 { "vcvtdq2ps", { XM
, EXx
} },
9275 { "vcvttps2dq", { XM
, EXx
} },
9279 { "vcvtps2dq", { XM
, EXx
} },
9283 { "vsubps", { XM
, Vex
, EXx
} },
9287 { "vsubss", { XM
, Vex128
, EXd
} },
9291 { "vsubpd", { XM
, Vex
, EXx
} },
9295 { "vsubsd", { XM
, Vex128
, EXq
} },
9299 { "vminps", { XM
, Vex
, EXx
} },
9303 { "vminss", { XM
, Vex128
, EXd
} },
9307 { "vminpd", { XM
, Vex
, EXx
} },
9311 { "vminsd", { XM
, Vex128
, EXq
} },
9315 { "vdivps", { XM
, Vex
, EXx
} },
9319 { "vdivss", { XM
, Vex128
, EXd
} },
9323 { "vdivpd", { XM
, Vex
, EXx
} },
9327 { "vdivsd", { XM
, Vex128
, EXq
} },
9331 { "vmaxps", { XM
, Vex
, EXx
} },
9335 { "vmaxss", { XM
, Vex128
, EXd
} },
9339 { "vmaxpd", { XM
, Vex
, EXx
} },
9343 { "vmaxsd", { XM
, Vex128
, EXq
} },
9347 { "vpunpcklbw", { XM
, Vex128
, EXx
} },
9351 { "vpunpcklwd", { XM
, Vex128
, EXx
} },
9355 { "vpunpckldq", { XM
, Vex128
, EXx
} },
9359 { "vpacksswb", { XM
, Vex128
, EXx
} },
9363 { "vpcmpgtb", { XM
, Vex128
, EXx
} },
9367 { "vpcmpgtw", { XM
, Vex128
, EXx
} },
9371 { "vpcmpgtd", { XM
, Vex128
, EXx
} },
9375 { "vpackuswb", { XM
, Vex128
, EXx
} },
9379 { "vpunpckhbw", { XM
, Vex128
, EXx
} },
9383 { "vpunpckhwd", { XM
, Vex128
, EXx
} },
9387 { "vpunpckhdq", { XM
, Vex128
, EXx
} },
9391 { "vpackssdw", { XM
, Vex128
, EXx
} },
9395 { "vpunpcklqdq", { XM
, Vex128
, EXx
} },
9399 { "vpunpckhqdq", { XM
, Vex128
, EXx
} },
9403 { "vmovdqu", { XM
, EXx
} },
9407 { "vmovdqa", { XM
, EXx
} },
9411 { "vpshufhw", { XM
, EXx
, Ib
} },
9415 { "vpshufd", { XM
, EXx
, Ib
} },
9419 { "vpshuflw", { XM
, EXx
, Ib
} },
9422 /* VEX_W_71_R_2_P_2 */
9423 { "vpsrlw", { Vex128
, XS
, Ib
} },
9426 /* VEX_W_71_R_4_P_2 */
9427 { "vpsraw", { Vex128
, XS
, Ib
} },
9430 /* VEX_W_71_R_6_P_2 */
9431 { "vpsllw", { Vex128
, XS
, Ib
} },
9434 /* VEX_W_72_R_2_P_2 */
9435 { "vpsrld", { Vex128
, XS
, Ib
} },
9438 /* VEX_W_72_R_4_P_2 */
9439 { "vpsrad", { Vex128
, XS
, Ib
} },
9442 /* VEX_W_72_R_6_P_2 */
9443 { "vpslld", { Vex128
, XS
, Ib
} },
9446 /* VEX_W_73_R_2_P_2 */
9447 { "vpsrlq", { Vex128
, XS
, Ib
} },
9450 /* VEX_W_73_R_3_P_2 */
9451 { "vpsrldq", { Vex128
, XS
, Ib
} },
9454 /* VEX_W_73_R_6_P_2 */
9455 { "vpsllq", { Vex128
, XS
, Ib
} },
9458 /* VEX_W_73_R_7_P_2 */
9459 { "vpslldq", { Vex128
, XS
, Ib
} },
9463 { "vpcmpeqb", { XM
, Vex128
, EXx
} },
9467 { "vpcmpeqw", { XM
, Vex128
, EXx
} },
9471 { "vpcmpeqd", { XM
, Vex128
, EXx
} },
9479 { "vhaddpd", { XM
, Vex
, EXx
} },
9483 { "vhaddps", { XM
, Vex
, EXx
} },
9487 { "vhsubpd", { XM
, Vex
, EXx
} },
9491 { "vhsubps", { XM
, Vex
, EXx
} },
9495 { "vmovq", { XM
, EXq
} },
9499 { "vmovdqu", { EXxS
, XM
} },
9503 { "vmovdqa", { EXxS
, XM
} },
9506 /* VEX_W_AE_R_2_M_0 */
9507 { "vldmxcsr", { Md
} },
9510 /* VEX_W_AE_R_3_M_0 */
9511 { "vstmxcsr", { Md
} },
9515 { "vcmpps", { XM
, Vex
, EXx
, VCMP
} },
9519 { "vcmpss", { XM
, Vex128
, EXd
, VCMP
} },
9523 { "vcmppd", { XM
, Vex
, EXx
, VCMP
} },
9527 { "vcmpsd", { XM
, Vex128
, EXq
, VCMP
} },
9531 { "vpinsrw", { XM
, Vex128
, Edqw
, Ib
} },
9535 { "vpextrw", { Gdq
, XS
, Ib
} },
9539 { "vaddsubpd", { XM
, Vex
, EXx
} },
9543 { "vaddsubps", { XM
, Vex
, EXx
} },
9547 { "vpsrlw", { XM
, Vex128
, EXx
} },
9551 { "vpsrld", { XM
, Vex128
, EXx
} },
9555 { "vpsrlq", { XM
, Vex128
, EXx
} },
9559 { "vpaddq", { XM
, Vex128
, EXx
} },
9563 { "vpmullw", { XM
, Vex128
, EXx
} },
9567 { "vmovq", { EXqS
, XM
} },
9570 /* VEX_W_D7_P_2_M_1 */
9571 { "vpmovmskb", { Gdq
, XS
} },
9575 { "vpsubusb", { XM
, Vex128
, EXx
} },
9579 { "vpsubusw", { XM
, Vex128
, EXx
} },
9583 { "vpminub", { XM
, Vex128
, EXx
} },
9587 { "vpand", { XM
, Vex128
, EXx
} },
9591 { "vpaddusb", { XM
, Vex128
, EXx
} },
9595 { "vpaddusw", { XM
, Vex128
, EXx
} },
9599 { "vpmaxub", { XM
, Vex128
, EXx
} },
9603 { "vpandn", { XM
, Vex128
, EXx
} },
9607 { "vpavgb", { XM
, Vex128
, EXx
} },
9611 { "vpsraw", { XM
, Vex128
, EXx
} },
9615 { "vpsrad", { XM
, Vex128
, EXx
} },
9619 { "vpavgw", { XM
, Vex128
, EXx
} },
9623 { "vpmulhuw", { XM
, Vex128
, EXx
} },
9627 { "vpmulhw", { XM
, Vex128
, EXx
} },
9631 { "vcvtdq2pd", { XM
, EXxmmq
} },
9635 { "vcvttpd2dq%XY", { XMM
, EXx
} },
9639 { "vcvtpd2dq%XY", { XMM
, EXx
} },
9642 /* VEX_W_E7_P_2_M_0 */
9643 { "vmovntdq", { Mx
, XM
} },
9647 { "vpsubsb", { XM
, Vex128
, EXx
} },
9651 { "vpsubsw", { XM
, Vex128
, EXx
} },
9655 { "vpminsw", { XM
, Vex128
, EXx
} },
9659 { "vpor", { XM
, Vex128
, EXx
} },
9663 { "vpaddsb", { XM
, Vex128
, EXx
} },
9667 { "vpaddsw", { XM
, Vex128
, EXx
} },
9671 { "vpmaxsw", { XM
, Vex128
, EXx
} },
9675 { "vpxor", { XM
, Vex128
, EXx
} },
9678 /* VEX_W_F0_P_3_M_0 */
9679 { "vlddqu", { XM
, M
} },
9683 { "vpsllw", { XM
, Vex128
, EXx
} },
9687 { "vpslld", { XM
, Vex128
, EXx
} },
9691 { "vpsllq", { XM
, Vex128
, EXx
} },
9695 { "vpmuludq", { XM
, Vex128
, EXx
} },
9699 { "vpmaddwd", { XM
, Vex128
, EXx
} },
9703 { "vpsadbw", { XM
, Vex128
, EXx
} },
9707 { "vmaskmovdqu", { XM
, XS
} },
9711 { "vpsubb", { XM
, Vex128
, EXx
} },
9715 { "vpsubw", { XM
, Vex128
, EXx
} },
9719 { "vpsubd", { XM
, Vex128
, EXx
} },
9723 { "vpsubq", { XM
, Vex128
, EXx
} },
9727 { "vpaddb", { XM
, Vex128
, EXx
} },
9731 { "vpaddw", { XM
, Vex128
, EXx
} },
9735 { "vpaddd", { XM
, Vex128
, EXx
} },
9738 /* VEX_W_3800_P_2 */
9739 { "vpshufb", { XM
, Vex128
, EXx
} },
9742 /* VEX_W_3801_P_2 */
9743 { "vphaddw", { XM
, Vex128
, EXx
} },
9746 /* VEX_W_3802_P_2 */
9747 { "vphaddd", { XM
, Vex128
, EXx
} },
9750 /* VEX_W_3803_P_2 */
9751 { "vphaddsw", { XM
, Vex128
, EXx
} },
9754 /* VEX_W_3804_P_2 */
9755 { "vpmaddubsw", { XM
, Vex128
, EXx
} },
9758 /* VEX_W_3805_P_2 */
9759 { "vphsubw", { XM
, Vex128
, EXx
} },
9762 /* VEX_W_3806_P_2 */
9763 { "vphsubd", { XM
, Vex128
, EXx
} },
9766 /* VEX_W_3807_P_2 */
9767 { "vphsubsw", { XM
, Vex128
, EXx
} },
9770 /* VEX_W_3808_P_2 */
9771 { "vpsignb", { XM
, Vex128
, EXx
} },
9774 /* VEX_W_3809_P_2 */
9775 { "vpsignw", { XM
, Vex128
, EXx
} },
9778 /* VEX_W_380A_P_2 */
9779 { "vpsignd", { XM
, Vex128
, EXx
} },
9782 /* VEX_W_380B_P_2 */
9783 { "vpmulhrsw", { XM
, Vex128
, EXx
} },
9786 /* VEX_W_380C_P_2 */
9787 { "vpermilps", { XM
, Vex
, EXx
} },
9790 /* VEX_W_380D_P_2 */
9791 { "vpermilpd", { XM
, Vex
, EXx
} },
9794 /* VEX_W_380E_P_2 */
9795 { "vtestps", { XM
, EXx
} },
9798 /* VEX_W_380F_P_2 */
9799 { "vtestpd", { XM
, EXx
} },
9802 /* VEX_W_3817_P_2 */
9803 { "vptest", { XM
, EXx
} },
9806 /* VEX_W_3818_P_2_M_0 */
9807 { "vbroadcastss", { XM
, Md
} },
9810 /* VEX_W_3819_P_2_M_0 */
9811 { "vbroadcastsd", { XM
, Mq
} },
9814 /* VEX_W_381A_P_2_M_0 */
9815 { "vbroadcastf128", { XM
, Mxmm
} },
9818 /* VEX_W_381C_P_2 */
9819 { "vpabsb", { XM
, EXx
} },
9822 /* VEX_W_381D_P_2 */
9823 { "vpabsw", { XM
, EXx
} },
9826 /* VEX_W_381E_P_2 */
9827 { "vpabsd", { XM
, EXx
} },
9830 /* VEX_W_3820_P_2 */
9831 { "vpmovsxbw", { XM
, EXq
} },
9834 /* VEX_W_3821_P_2 */
9835 { "vpmovsxbd", { XM
, EXd
} },
9838 /* VEX_W_3822_P_2 */
9839 { "vpmovsxbq", { XM
, EXw
} },
9842 /* VEX_W_3823_P_2 */
9843 { "vpmovsxwd", { XM
, EXq
} },
9846 /* VEX_W_3824_P_2 */
9847 { "vpmovsxwq", { XM
, EXd
} },
9850 /* VEX_W_3825_P_2 */
9851 { "vpmovsxdq", { XM
, EXq
} },
9854 /* VEX_W_3828_P_2 */
9855 { "vpmuldq", { XM
, Vex128
, EXx
} },
9858 /* VEX_W_3829_P_2 */
9859 { "vpcmpeqq", { XM
, Vex128
, EXx
} },
9862 /* VEX_W_382A_P_2_M_0 */
9863 { "vmovntdqa", { XM
, Mx
} },
9866 /* VEX_W_382B_P_2 */
9867 { "vpackusdw", { XM
, Vex128
, EXx
} },
9870 /* VEX_W_382C_P_2_M_0 */
9871 { "vmaskmovps", { XM
, Vex
, Mx
} },
9874 /* VEX_W_382D_P_2_M_0 */
9875 { "vmaskmovpd", { XM
, Vex
, Mx
} },
9878 /* VEX_W_382E_P_2_M_0 */
9879 { "vmaskmovps", { Mx
, Vex
, XM
} },
9882 /* VEX_W_382F_P_2_M_0 */
9883 { "vmaskmovpd", { Mx
, Vex
, XM
} },
9886 /* VEX_W_3830_P_2 */
9887 { "vpmovzxbw", { XM
, EXq
} },
9890 /* VEX_W_3831_P_2 */
9891 { "vpmovzxbd", { XM
, EXd
} },
9894 /* VEX_W_3832_P_2 */
9895 { "vpmovzxbq", { XM
, EXw
} },
9898 /* VEX_W_3833_P_2 */
9899 { "vpmovzxwd", { XM
, EXq
} },
9902 /* VEX_W_3834_P_2 */
9903 { "vpmovzxwq", { XM
, EXd
} },
9906 /* VEX_W_3835_P_2 */
9907 { "vpmovzxdq", { XM
, EXq
} },
9910 /* VEX_W_3837_P_2 */
9911 { "vpcmpgtq", { XM
, Vex128
, EXx
} },
9914 /* VEX_W_3838_P_2 */
9915 { "vpminsb", { XM
, Vex128
, EXx
} },
9918 /* VEX_W_3839_P_2 */
9919 { "vpminsd", { XM
, Vex128
, EXx
} },
9922 /* VEX_W_383A_P_2 */
9923 { "vpminuw", { XM
, Vex128
, EXx
} },
9926 /* VEX_W_383B_P_2 */
9927 { "vpminud", { XM
, Vex128
, EXx
} },
9930 /* VEX_W_383C_P_2 */
9931 { "vpmaxsb", { XM
, Vex128
, EXx
} },
9934 /* VEX_W_383D_P_2 */
9935 { "vpmaxsd", { XM
, Vex128
, EXx
} },
9938 /* VEX_W_383E_P_2 */
9939 { "vpmaxuw", { XM
, Vex128
, EXx
} },
9942 /* VEX_W_383F_P_2 */
9943 { "vpmaxud", { XM
, Vex128
, EXx
} },
9946 /* VEX_W_3840_P_2 */
9947 { "vpmulld", { XM
, Vex128
, EXx
} },
9950 /* VEX_W_3841_P_2 */
9951 { "vphminposuw", { XM
, EXx
} },
9954 /* VEX_W_38DB_P_2 */
9955 { "vaesimc", { XM
, EXx
} },
9958 /* VEX_W_38DC_P_2 */
9959 { "vaesenc", { XM
, Vex128
, EXx
} },
9962 /* VEX_W_38DD_P_2 */
9963 { "vaesenclast", { XM
, Vex128
, EXx
} },
9966 /* VEX_W_38DE_P_2 */
9967 { "vaesdec", { XM
, Vex128
, EXx
} },
9970 /* VEX_W_38DF_P_2 */
9971 { "vaesdeclast", { XM
, Vex128
, EXx
} },
9974 /* VEX_W_3A04_P_2 */
9975 { "vpermilps", { XM
, EXx
, Ib
} },
9978 /* VEX_W_3A05_P_2 */
9979 { "vpermilpd", { XM
, EXx
, Ib
} },
9982 /* VEX_W_3A06_P_2 */
9983 { "vperm2f128", { XM
, Vex256
, EXx
, Ib
} },
9986 /* VEX_W_3A08_P_2 */
9987 { "vroundps", { XM
, EXx
, Ib
} },
9990 /* VEX_W_3A09_P_2 */
9991 { "vroundpd", { XM
, EXx
, Ib
} },
9994 /* VEX_W_3A0A_P_2 */
9995 { "vroundss", { XM
, Vex128
, EXd
, Ib
} },
9998 /* VEX_W_3A0B_P_2 */
9999 { "vroundsd", { XM
, Vex128
, EXq
, Ib
} },
10002 /* VEX_W_3A0C_P_2 */
10003 { "vblendps", { XM
, Vex
, EXx
, Ib
} },
10006 /* VEX_W_3A0D_P_2 */
10007 { "vblendpd", { XM
, Vex
, EXx
, Ib
} },
10010 /* VEX_W_3A0E_P_2 */
10011 { "vpblendw", { XM
, Vex128
, EXx
, Ib
} },
10014 /* VEX_W_3A0F_P_2 */
10015 { "vpalignr", { XM
, Vex128
, EXx
, Ib
} },
10018 /* VEX_W_3A14_P_2 */
10019 { "vpextrb", { Edqb
, XM
, Ib
} },
10022 /* VEX_W_3A15_P_2 */
10023 { "vpextrw", { Edqw
, XM
, Ib
} },
10026 /* VEX_W_3A18_P_2 */
10027 { "vinsertf128", { XM
, Vex256
, EXxmm
, Ib
} },
10030 /* VEX_W_3A19_P_2 */
10031 { "vextractf128", { EXxmm
, XM
, Ib
} },
10034 /* VEX_W_3A20_P_2 */
10035 { "vpinsrb", { XM
, Vex128
, Edqb
, Ib
} },
10038 /* VEX_W_3A21_P_2 */
10039 { "vinsertps", { XM
, Vex128
, EXd
, Ib
} },
10042 /* VEX_W_3A40_P_2 */
10043 { "vdpps", { XM
, Vex
, EXx
, Ib
} },
10046 /* VEX_W_3A41_P_2 */
10047 { "vdppd", { XM
, Vex128
, EXx
, Ib
} },
10050 /* VEX_W_3A42_P_2 */
10051 { "vmpsadbw", { XM
, Vex128
, EXx
, Ib
} },
10054 /* VEX_W_3A44_P_2 */
10055 { "vpclmulqdq", { XM
, Vex128
, EXx
, PCLMUL
} },
10058 /* VEX_W_3A4A_P_2 */
10059 { "vblendvps", { XM
, Vex
, EXx
, XMVexI4
} },
10062 /* VEX_W_3A4B_P_2 */
10063 { "vblendvpd", { XM
, Vex
, EXx
, XMVexI4
} },
10066 /* VEX_W_3A4C_P_2 */
10067 { "vpblendvb", { XM
, Vex128
, EXx
, XMVexI4
} },
10070 /* VEX_W_3A60_P_2 */
10071 { "vpcmpestrm", { XM
, EXx
, Ib
} },
10074 /* VEX_W_3A61_P_2 */
10075 { "vpcmpestri", { XM
, EXx
, Ib
} },
10078 /* VEX_W_3A62_P_2 */
10079 { "vpcmpistrm", { XM
, EXx
, Ib
} },
10082 /* VEX_W_3A63_P_2 */
10083 { "vpcmpistri", { XM
, EXx
, Ib
} },
10086 /* VEX_W_3ADF_P_2 */
10087 { "vaeskeygenassist", { XM
, EXx
, Ib
} },
10091 static const struct dis386 mod_table
[][2] = {
10094 { "leaS", { Gv
, M
} },
10097 /* MOD_0F01_REG_0 */
10098 { X86_64_TABLE (X86_64_0F01_REG_0
) },
10099 { RM_TABLE (RM_0F01_REG_0
) },
10102 /* MOD_0F01_REG_1 */
10103 { X86_64_TABLE (X86_64_0F01_REG_1
) },
10104 { RM_TABLE (RM_0F01_REG_1
) },
10107 /* MOD_0F01_REG_2 */
10108 { X86_64_TABLE (X86_64_0F01_REG_2
) },
10109 { RM_TABLE (RM_0F01_REG_2
) },
10112 /* MOD_0F01_REG_3 */
10113 { X86_64_TABLE (X86_64_0F01_REG_3
) },
10114 { RM_TABLE (RM_0F01_REG_3
) },
10117 /* MOD_0F01_REG_7 */
10118 { "invlpg", { Mb
} },
10119 { RM_TABLE (RM_0F01_REG_7
) },
10122 /* MOD_0F12_PREFIX_0 */
10123 { "movlps", { XM
, EXq
} },
10124 { "movhlps", { XM
, EXq
} },
10128 { "movlpX", { EXq
, XM
} },
10131 /* MOD_0F16_PREFIX_0 */
10132 { "movhps", { XM
, EXq
} },
10133 { "movlhps", { XM
, EXq
} },
10137 { "movhpX", { EXq
, XM
} },
10140 /* MOD_0F18_REG_0 */
10141 { "prefetchnta", { Mb
} },
10144 /* MOD_0F18_REG_1 */
10145 { "prefetcht0", { Mb
} },
10148 /* MOD_0F18_REG_2 */
10149 { "prefetcht1", { Mb
} },
10152 /* MOD_0F18_REG_3 */
10153 { "prefetcht2", { Mb
} },
10158 { "movZ", { Rm
, Cm
} },
10163 { "movZ", { Rm
, Dm
} },
10168 { "movZ", { Cm
, Rm
} },
10173 { "movZ", { Dm
, Rm
} },
10178 { "movL", { Rd
, Td
} },
10183 { "movL", { Td
, Rd
} },
10186 /* MOD_0F2B_PREFIX_0 */
10187 {"movntps", { Mx
, XM
} },
10190 /* MOD_0F2B_PREFIX_1 */
10191 {"movntss", { Md
, XM
} },
10194 /* MOD_0F2B_PREFIX_2 */
10195 {"movntpd", { Mx
, XM
} },
10198 /* MOD_0F2B_PREFIX_3 */
10199 {"movntsd", { Mq
, XM
} },
10204 { "movmskpX", { Gdq
, XS
} },
10207 /* MOD_0F71_REG_2 */
10209 { "psrlw", { MS
, Ib
} },
10212 /* MOD_0F71_REG_4 */
10214 { "psraw", { MS
, Ib
} },
10217 /* MOD_0F71_REG_6 */
10219 { "psllw", { MS
, Ib
} },
10222 /* MOD_0F72_REG_2 */
10224 { "psrld", { MS
, Ib
} },
10227 /* MOD_0F72_REG_4 */
10229 { "psrad", { MS
, Ib
} },
10232 /* MOD_0F72_REG_6 */
10234 { "pslld", { MS
, Ib
} },
10237 /* MOD_0F73_REG_2 */
10239 { "psrlq", { MS
, Ib
} },
10242 /* MOD_0F73_REG_3 */
10244 { PREFIX_TABLE (PREFIX_0F73_REG_3
) },
10247 /* MOD_0F73_REG_6 */
10249 { "psllq", { MS
, Ib
} },
10252 /* MOD_0F73_REG_7 */
10254 { PREFIX_TABLE (PREFIX_0F73_REG_7
) },
10257 /* MOD_0FAE_REG_0 */
10258 { "fxsave", { FXSAVE
} },
10261 /* MOD_0FAE_REG_1 */
10262 { "fxrstor", { FXSAVE
} },
10265 /* MOD_0FAE_REG_2 */
10266 { "ldmxcsr", { Md
} },
10269 /* MOD_0FAE_REG_3 */
10270 { "stmxcsr", { Md
} },
10273 /* MOD_0FAE_REG_4 */
10274 { "xsave", { FXSAVE
} },
10277 /* MOD_0FAE_REG_5 */
10278 { "xrstor", { FXSAVE
} },
10279 { RM_TABLE (RM_0FAE_REG_5
) },
10282 /* MOD_0FAE_REG_6 */
10284 { RM_TABLE (RM_0FAE_REG_6
) },
10287 /* MOD_0FAE_REG_7 */
10288 { "clflush", { Mb
} },
10289 { RM_TABLE (RM_0FAE_REG_7
) },
10293 { "lssS", { Gv
, Mp
} },
10297 { "lfsS", { Gv
, Mp
} },
10301 { "lgsS", { Gv
, Mp
} },
10304 /* MOD_0FC7_REG_6 */
10305 { PREFIX_TABLE (PREFIX_0FC7_REG_6
) },
10308 /* MOD_0FC7_REG_7 */
10309 { "vmptrst", { Mq
} },
10314 { "pmovmskb", { Gdq
, MS
} },
10317 /* MOD_0FE7_PREFIX_2 */
10318 { "movntdq", { Mx
, XM
} },
10321 /* MOD_0FF0_PREFIX_3 */
10322 { "lddqu", { XM
, M
} },
10325 /* MOD_0F382A_PREFIX_2 */
10326 { "movntdqa", { XM
, Mx
} },
10330 { "bound{S|}", { Gv
, Ma
} },
10334 { "lesS", { Gv
, Mp
} },
10335 { VEX_C4_TABLE (VEX_0F
) },
10339 { "ldsS", { Gv
, Mp
} },
10340 { VEX_C5_TABLE (VEX_0F
) },
10343 /* MOD_VEX_12_PREFIX_0 */
10344 { VEX_LEN_TABLE (VEX_LEN_12_P_0_M_0
) },
10345 { VEX_LEN_TABLE (VEX_LEN_12_P_0_M_1
) },
10349 { VEX_LEN_TABLE (VEX_LEN_13_M_0
) },
10352 /* MOD_VEX_16_PREFIX_0 */
10353 { VEX_LEN_TABLE (VEX_LEN_16_P_0_M_0
) },
10354 { VEX_LEN_TABLE (VEX_LEN_16_P_0_M_1
) },
10358 { VEX_LEN_TABLE (VEX_LEN_17_M_0
) },
10362 { VEX_W_TABLE (VEX_W_2B_M_0
) },
10367 { VEX_W_TABLE (VEX_W_50_M_0
) },
10370 /* MOD_VEX_71_REG_2 */
10372 { PREFIX_TABLE (PREFIX_VEX_71_REG_2
) },
10375 /* MOD_VEX_71_REG_4 */
10377 { PREFIX_TABLE (PREFIX_VEX_71_REG_4
) },
10380 /* MOD_VEX_71_REG_6 */
10382 { PREFIX_TABLE (PREFIX_VEX_71_REG_6
) },
10385 /* MOD_VEX_72_REG_2 */
10387 { PREFIX_TABLE (PREFIX_VEX_72_REG_2
) },
10390 /* MOD_VEX_72_REG_4 */
10392 { PREFIX_TABLE (PREFIX_VEX_72_REG_4
) },
10395 /* MOD_VEX_72_REG_6 */
10397 { PREFIX_TABLE (PREFIX_VEX_72_REG_6
) },
10400 /* MOD_VEX_73_REG_2 */
10402 { PREFIX_TABLE (PREFIX_VEX_73_REG_2
) },
10405 /* MOD_VEX_73_REG_3 */
10407 { PREFIX_TABLE (PREFIX_VEX_73_REG_3
) },
10410 /* MOD_VEX_73_REG_6 */
10412 { PREFIX_TABLE (PREFIX_VEX_73_REG_6
) },
10415 /* MOD_VEX_73_REG_7 */
10417 { PREFIX_TABLE (PREFIX_VEX_73_REG_7
) },
10420 /* MOD_VEX_AE_REG_2 */
10421 { VEX_LEN_TABLE (VEX_LEN_AE_R_2_M_0
) },
10424 /* MOD_VEX_AE_REG_3 */
10425 { VEX_LEN_TABLE (VEX_LEN_AE_R_3_M_0
) },
10428 /* MOD_VEX_D7_PREFIX_2 */
10430 { VEX_LEN_TABLE (VEX_LEN_D7_P_2_M_1
) },
10433 /* MOD_VEX_E7_PREFIX_2 */
10434 { VEX_W_TABLE (VEX_W_E7_P_2_M_0
) },
10437 /* MOD_VEX_F0_PREFIX_3 */
10438 { VEX_W_TABLE (VEX_W_F0_P_3_M_0
) },
10441 /* MOD_VEX_3818_PREFIX_2 */
10442 { VEX_W_TABLE (VEX_W_3818_P_2_M_0
) },
10445 /* MOD_VEX_3819_PREFIX_2 */
10446 { VEX_LEN_TABLE (VEX_LEN_3819_P_2_M_0
) },
10449 /* MOD_VEX_381A_PREFIX_2 */
10450 { VEX_LEN_TABLE (VEX_LEN_381A_P_2_M_0
) },
10453 /* MOD_VEX_382A_PREFIX_2 */
10454 { VEX_LEN_TABLE (VEX_LEN_382A_P_2_M_0
) },
10457 /* MOD_VEX_382C_PREFIX_2 */
10458 { VEX_W_TABLE (VEX_W_382C_P_2_M_0
) },
10461 /* MOD_VEX_382D_PREFIX_2 */
10462 { VEX_W_TABLE (VEX_W_382D_P_2_M_0
) },
10465 /* MOD_VEX_382E_PREFIX_2 */
10466 { VEX_W_TABLE (VEX_W_382E_P_2_M_0
) },
10469 /* MOD_VEX_382F_PREFIX_2 */
10470 { VEX_W_TABLE (VEX_W_382F_P_2_M_0
) },
10474 static const struct dis386 rm_table
[][8] = {
10476 /* RM_0F01_REG_0 */
10478 { "vmcall", { Skip_MODRM
} },
10479 { "vmlaunch", { Skip_MODRM
} },
10480 { "vmresume", { Skip_MODRM
} },
10481 { "vmxoff", { Skip_MODRM
} },
10484 /* RM_0F01_REG_1 */
10485 { "monitor", { { OP_Monitor
, 0 } } },
10486 { "mwait", { { OP_Mwait
, 0 } } },
10489 /* RM_0F01_REG_2 */
10490 { "xgetbv", { Skip_MODRM
} },
10491 { "xsetbv", { Skip_MODRM
} },
10494 /* RM_0F01_REG_3 */
10495 { "vmrun", { Skip_MODRM
} },
10496 { "vmmcall", { Skip_MODRM
} },
10497 { "vmload", { Skip_MODRM
} },
10498 { "vmsave", { Skip_MODRM
} },
10499 { "stgi", { Skip_MODRM
} },
10500 { "clgi", { Skip_MODRM
} },
10501 { "skinit", { Skip_MODRM
} },
10502 { "invlpga", { Skip_MODRM
} },
10505 /* RM_0F01_REG_7 */
10506 { "swapgs", { Skip_MODRM
} },
10507 { "rdtscp", { Skip_MODRM
} },
10510 /* RM_0FAE_REG_5 */
10511 { "lfence", { Skip_MODRM
} },
10514 /* RM_0FAE_REG_6 */
10515 { "mfence", { Skip_MODRM
} },
10518 /* RM_0FAE_REG_7 */
10519 { "sfence", { Skip_MODRM
} },
10523 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
10525 /* We use the high bit to indicate different name for the same
10527 #define ADDR16_PREFIX (0x67 | 0x100)
10528 #define ADDR32_PREFIX (0x67 | 0x200)
10529 #define DATA16_PREFIX (0x66 | 0x100)
10530 #define DATA32_PREFIX (0x66 | 0x200)
10531 #define REP_PREFIX (0xf3 | 0x100)
10536 int newrex
, i
, length
;
10542 last_lock_prefix
= -1;
10543 last_repz_prefix
= -1;
10544 last_repnz_prefix
= -1;
10545 last_data_prefix
= -1;
10546 last_addr_prefix
= -1;
10547 last_rex_prefix
= -1;
10548 last_seg_prefix
= -1;
10549 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
10550 all_prefixes
[i
] = 0;
10553 /* The maximum instruction length is 15bytes. */
10554 while (length
< MAX_CODE_LENGTH
- 1)
10556 FETCH_DATA (the_info
, codep
+ 1);
10560 /* REX prefixes family. */
10577 if (address_mode
== mode_64bit
)
10581 last_rex_prefix
= i
;
10584 prefixes
|= PREFIX_REPZ
;
10585 last_repz_prefix
= i
;
10588 prefixes
|= PREFIX_REPNZ
;
10589 last_repnz_prefix
= i
;
10592 prefixes
|= PREFIX_LOCK
;
10593 last_lock_prefix
= i
;
10596 prefixes
|= PREFIX_CS
;
10597 last_seg_prefix
= i
;
10600 prefixes
|= PREFIX_SS
;
10601 last_seg_prefix
= i
;
10604 prefixes
|= PREFIX_DS
;
10605 last_seg_prefix
= i
;
10608 prefixes
|= PREFIX_ES
;
10609 last_seg_prefix
= i
;
10612 prefixes
|= PREFIX_FS
;
10613 last_seg_prefix
= i
;
10616 prefixes
|= PREFIX_GS
;
10617 last_seg_prefix
= i
;
10620 prefixes
|= PREFIX_DATA
;
10621 last_data_prefix
= i
;
10624 prefixes
|= PREFIX_ADDR
;
10625 last_addr_prefix
= i
;
10628 /* fwait is really an instruction. If there are prefixes
10629 before the fwait, they belong to the fwait, *not* to the
10630 following instruction. */
10631 if (prefixes
|| rex
)
10633 prefixes
|= PREFIX_FWAIT
;
10637 prefixes
= PREFIX_FWAIT
;
10642 /* Rex is ignored when followed by another prefix. */
10648 if (*codep
!= FWAIT_OPCODE
)
10649 all_prefixes
[i
++] = *codep
;
10658 seg_prefix (int pref
)
10679 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
10682 static const char *
10683 prefix_name (int pref
, int sizeflag
)
10685 static const char *rexes
[16] =
10688 "rex.B", /* 0x41 */
10689 "rex.X", /* 0x42 */
10690 "rex.XB", /* 0x43 */
10691 "rex.R", /* 0x44 */
10692 "rex.RB", /* 0x45 */
10693 "rex.RX", /* 0x46 */
10694 "rex.RXB", /* 0x47 */
10695 "rex.W", /* 0x48 */
10696 "rex.WB", /* 0x49 */
10697 "rex.WX", /* 0x4a */
10698 "rex.WXB", /* 0x4b */
10699 "rex.WR", /* 0x4c */
10700 "rex.WRB", /* 0x4d */
10701 "rex.WRX", /* 0x4e */
10702 "rex.WRXB", /* 0x4f */
10707 /* REX prefixes family. */
10724 return rexes
[pref
- 0x40];
10744 return (sizeflag
& DFLAG
) ? "data16" : "data32";
10746 if (address_mode
== mode_64bit
)
10747 return (sizeflag
& AFLAG
) ? "addr32" : "addr64";
10749 return (sizeflag
& AFLAG
) ? "addr16" : "addr32";
10752 case ADDR16_PREFIX
:
10754 case ADDR32_PREFIX
:
10756 case DATA16_PREFIX
:
10758 case DATA32_PREFIX
:
10767 static char op_out
[MAX_OPERANDS
][100];
10768 static int op_ad
, op_index
[MAX_OPERANDS
];
10769 static int two_source_ops
;
10770 static bfd_vma op_address
[MAX_OPERANDS
];
10771 static bfd_vma op_riprel
[MAX_OPERANDS
];
10772 static bfd_vma start_pc
;
10775 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
10776 * (see topic "Redundant prefixes" in the "Differences from 8086"
10777 * section of the "Virtual 8086 Mode" chapter.)
10778 * 'pc' should be the address of this instruction, it will
10779 * be used to print the target address if this is a relative jump or call
10780 * The function returns the length of this instruction in bytes.
10783 static char intel_syntax
;
10784 static char intel_mnemonic
= !SYSV386_COMPAT
;
10785 static char open_char
;
10786 static char close_char
;
10787 static char separator_char
;
10788 static char scale_char
;
10790 /* Here for backwards compatibility. When gdb stops using
10791 print_insn_i386_att and print_insn_i386_intel these functions can
10792 disappear, and print_insn_i386 be merged into print_insn. */
10794 print_insn_i386_att (bfd_vma pc
, disassemble_info
*info
)
10798 return print_insn (pc
, info
);
10802 print_insn_i386_intel (bfd_vma pc
, disassemble_info
*info
)
10806 return print_insn (pc
, info
);
10810 print_insn_i386 (bfd_vma pc
, disassemble_info
*info
)
10814 return print_insn (pc
, info
);
10818 print_i386_disassembler_options (FILE *stream
)
10820 fprintf (stream
, _("\n\
10821 The following i386/x86-64 specific disassembler options are supported for use\n\
10822 with the -M switch (multiple options should be separated by commas):\n"));
10824 fprintf (stream
, _(" x86-64 Disassemble in 64bit mode\n"));
10825 fprintf (stream
, _(" i386 Disassemble in 32bit mode\n"));
10826 fprintf (stream
, _(" i8086 Disassemble in 16bit mode\n"));
10827 fprintf (stream
, _(" att Display instruction in AT&T syntax\n"));
10828 fprintf (stream
, _(" intel Display instruction in Intel syntax\n"));
10829 fprintf (stream
, _(" att-mnemonic\n"
10830 " Display instruction in AT&T mnemonic\n"));
10831 fprintf (stream
, _(" intel-mnemonic\n"
10832 " Display instruction in Intel mnemonic\n"));
10833 fprintf (stream
, _(" addr64 Assume 64bit address size\n"));
10834 fprintf (stream
, _(" addr32 Assume 32bit address size\n"));
10835 fprintf (stream
, _(" addr16 Assume 16bit address size\n"));
10836 fprintf (stream
, _(" data32 Assume 32bit data size\n"));
10837 fprintf (stream
, _(" data16 Assume 16bit data size\n"));
10838 fprintf (stream
, _(" suffix Always display instruction suffix in AT&T syntax\n"));
10842 static const struct dis386 bad_opcode
= { "(bad)", { XX
} };
10844 /* Get a pointer to struct dis386 with a valid name. */
10846 static const struct dis386
*
10847 get_valid_dis386 (const struct dis386
*dp
, disassemble_info
*info
)
10849 int vindex
, vex_table_index
;
10851 if (dp
->name
!= NULL
)
10854 switch (dp
->op
[0].bytemode
)
10856 case USE_REG_TABLE
:
10857 dp
= ®_table
[dp
->op
[1].bytemode
][modrm
.reg
];
10860 case USE_MOD_TABLE
:
10861 vindex
= modrm
.mod
== 0x3 ? 1 : 0;
10862 dp
= &mod_table
[dp
->op
[1].bytemode
][vindex
];
10866 dp
= &rm_table
[dp
->op
[1].bytemode
][modrm
.rm
];
10869 case USE_PREFIX_TABLE
:
10872 /* The prefix in VEX is implicit. */
10873 switch (vex
.prefix
)
10878 case REPE_PREFIX_OPCODE
:
10881 case DATA_PREFIX_OPCODE
:
10884 case REPNE_PREFIX_OPCODE
:
10895 used_prefixes
|= (prefixes
& PREFIX_REPZ
);
10896 if (prefixes
& PREFIX_REPZ
)
10899 all_prefixes
[last_repz_prefix
] = 0;
10903 /* We should check PREFIX_REPNZ and PREFIX_REPZ before
10905 used_prefixes
|= (prefixes
& PREFIX_REPNZ
);
10906 if (prefixes
& PREFIX_REPNZ
)
10909 all_prefixes
[last_repnz_prefix
] = 0;
10913 used_prefixes
|= (prefixes
& PREFIX_DATA
);
10914 if (prefixes
& PREFIX_DATA
)
10917 all_prefixes
[last_data_prefix
] = 0;
10922 dp
= &prefix_table
[dp
->op
[1].bytemode
][vindex
];
10925 case USE_X86_64_TABLE
:
10926 vindex
= address_mode
== mode_64bit
? 1 : 0;
10927 dp
= &x86_64_table
[dp
->op
[1].bytemode
][vindex
];
10930 case USE_3BYTE_TABLE
:
10931 FETCH_DATA (info
, codep
+ 2);
10933 dp
= &three_byte_table
[dp
->op
[1].bytemode
][vindex
];
10934 modrm
.mod
= (*codep
>> 6) & 3;
10935 modrm
.reg
= (*codep
>> 3) & 7;
10936 modrm
.rm
= *codep
& 7;
10939 case USE_VEX_LEN_TABLE
:
10943 switch (vex
.length
)
10956 dp
= &vex_len_table
[dp
->op
[1].bytemode
][vindex
];
10959 case USE_XOP_8F_TABLE
:
10960 FETCH_DATA (info
, codep
+ 3);
10961 /* All bits in the REX prefix are ignored. */
10963 rex
= ~(*codep
>> 5) & 0x7;
10965 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
10966 switch ((*codep
& 0x1f))
10971 vex_table_index
= XOP_08
;
10974 vex_table_index
= XOP_09
;
10977 vex_table_index
= XOP_0A
;
10981 vex
.w
= *codep
& 0x80;
10982 if (vex
.w
&& address_mode
== mode_64bit
)
10985 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
10986 if (address_mode
!= mode_64bit
10987 && vex
.register_specifier
> 0x7)
10990 vex
.length
= (*codep
& 0x4) ? 256 : 128;
10991 switch ((*codep
& 0x3))
10997 vex
.prefix
= DATA_PREFIX_OPCODE
;
11000 vex
.prefix
= REPE_PREFIX_OPCODE
;
11003 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11010 dp
= &xop_table
[vex_table_index
][vindex
];
11012 FETCH_DATA (info
, codep
+ 1);
11013 modrm
.mod
= (*codep
>> 6) & 3;
11014 modrm
.reg
= (*codep
>> 3) & 7;
11015 modrm
.rm
= *codep
& 7;
11018 case USE_VEX_C4_TABLE
:
11019 FETCH_DATA (info
, codep
+ 3);
11020 /* All bits in the REX prefix are ignored. */
11022 rex
= ~(*codep
>> 5) & 0x7;
11023 switch ((*codep
& 0x1f))
11028 vex_table_index
= VEX_0F
;
11031 vex_table_index
= VEX_0F38
;
11034 vex_table_index
= VEX_0F3A
;
11038 vex
.w
= *codep
& 0x80;
11039 if (vex
.w
&& address_mode
== mode_64bit
)
11042 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11043 if (address_mode
!= mode_64bit
11044 && vex
.register_specifier
> 0x7)
11047 vex
.length
= (*codep
& 0x4) ? 256 : 128;
11048 switch ((*codep
& 0x3))
11054 vex
.prefix
= DATA_PREFIX_OPCODE
;
11057 vex
.prefix
= REPE_PREFIX_OPCODE
;
11060 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11067 dp
= &vex_table
[vex_table_index
][vindex
];
11068 /* There is no MODRM byte for VEX [82|77]. */
11069 if (vindex
!= 0x77 && vindex
!= 0x82)
11071 FETCH_DATA (info
, codep
+ 1);
11072 modrm
.mod
= (*codep
>> 6) & 3;
11073 modrm
.reg
= (*codep
>> 3) & 7;
11074 modrm
.rm
= *codep
& 7;
11078 case USE_VEX_C5_TABLE
:
11079 FETCH_DATA (info
, codep
+ 2);
11080 /* All bits in the REX prefix are ignored. */
11082 rex
= (*codep
& 0x80) ? 0 : REX_R
;
11084 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11085 if (address_mode
!= mode_64bit
11086 && vex
.register_specifier
> 0x7)
11091 vex
.length
= (*codep
& 0x4) ? 256 : 128;
11092 switch ((*codep
& 0x3))
11098 vex
.prefix
= DATA_PREFIX_OPCODE
;
11101 vex
.prefix
= REPE_PREFIX_OPCODE
;
11104 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11111 dp
= &vex_table
[dp
->op
[1].bytemode
][vindex
];
11112 /* There is no MODRM byte for VEX [82|77]. */
11113 if (vindex
!= 0x77 && vindex
!= 0x82)
11115 FETCH_DATA (info
, codep
+ 1);
11116 modrm
.mod
= (*codep
>> 6) & 3;
11117 modrm
.reg
= (*codep
>> 3) & 7;
11118 modrm
.rm
= *codep
& 7;
11122 case USE_VEX_W_TABLE
:
11126 dp
= &vex_w_table
[dp
->op
[1].bytemode
][vex
.w
? 1 : 0];
11137 if (dp
->name
!= NULL
)
11140 return get_valid_dis386 (dp
, info
);
11144 print_insn (bfd_vma pc
, disassemble_info
*info
)
11146 const struct dis386
*dp
;
11148 char *op_txt
[MAX_OPERANDS
];
11152 struct dis_private priv
;
11155 int default_prefixes
;
11157 if (info
->mach
== bfd_mach_x86_64_intel_syntax
11158 || info
->mach
== bfd_mach_x86_64
11159 || info
->mach
== bfd_mach_l1om
11160 || info
->mach
== bfd_mach_l1om_intel_syntax
)
11161 address_mode
= mode_64bit
;
11163 address_mode
= mode_32bit
;
11165 if (intel_syntax
== (char) -1)
11166 intel_syntax
= (info
->mach
== bfd_mach_i386_i386_intel_syntax
11167 || info
->mach
== bfd_mach_x86_64_intel_syntax
11168 || info
->mach
== bfd_mach_l1om_intel_syntax
);
11170 if (info
->mach
== bfd_mach_i386_i386
11171 || info
->mach
== bfd_mach_x86_64
11172 || info
->mach
== bfd_mach_l1om
11173 || info
->mach
== bfd_mach_i386_i386_intel_syntax
11174 || info
->mach
== bfd_mach_x86_64_intel_syntax
11175 || info
->mach
== bfd_mach_l1om_intel_syntax
)
11176 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
11177 else if (info
->mach
== bfd_mach_i386_i8086
)
11178 priv
.orig_sizeflag
= 0;
11182 for (p
= info
->disassembler_options
; p
!= NULL
; )
11184 if (CONST_STRNEQ (p
, "x86-64"))
11186 address_mode
= mode_64bit
;
11187 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
11189 else if (CONST_STRNEQ (p
, "i386"))
11191 address_mode
= mode_32bit
;
11192 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
11194 else if (CONST_STRNEQ (p
, "i8086"))
11196 address_mode
= mode_16bit
;
11197 priv
.orig_sizeflag
= 0;
11199 else if (CONST_STRNEQ (p
, "intel"))
11202 if (CONST_STRNEQ (p
+ 5, "-mnemonic"))
11203 intel_mnemonic
= 1;
11205 else if (CONST_STRNEQ (p
, "att"))
11208 if (CONST_STRNEQ (p
+ 3, "-mnemonic"))
11209 intel_mnemonic
= 0;
11211 else if (CONST_STRNEQ (p
, "addr"))
11213 if (address_mode
== mode_64bit
)
11215 if (p
[4] == '3' && p
[5] == '2')
11216 priv
.orig_sizeflag
&= ~AFLAG
;
11217 else if (p
[4] == '6' && p
[5] == '4')
11218 priv
.orig_sizeflag
|= AFLAG
;
11222 if (p
[4] == '1' && p
[5] == '6')
11223 priv
.orig_sizeflag
&= ~AFLAG
;
11224 else if (p
[4] == '3' && p
[5] == '2')
11225 priv
.orig_sizeflag
|= AFLAG
;
11228 else if (CONST_STRNEQ (p
, "data"))
11230 if (p
[4] == '1' && p
[5] == '6')
11231 priv
.orig_sizeflag
&= ~DFLAG
;
11232 else if (p
[4] == '3' && p
[5] == '2')
11233 priv
.orig_sizeflag
|= DFLAG
;
11235 else if (CONST_STRNEQ (p
, "suffix"))
11236 priv
.orig_sizeflag
|= SUFFIX_ALWAYS
;
11238 p
= strchr (p
, ',');
11245 names64
= intel_names64
;
11246 names32
= intel_names32
;
11247 names16
= intel_names16
;
11248 names8
= intel_names8
;
11249 names8rex
= intel_names8rex
;
11250 names_seg
= intel_names_seg
;
11251 names_mm
= intel_names_mm
;
11252 names_xmm
= intel_names_xmm
;
11253 names_ymm
= intel_names_ymm
;
11254 index64
= intel_index64
;
11255 index32
= intel_index32
;
11256 index16
= intel_index16
;
11259 separator_char
= '+';
11264 names64
= att_names64
;
11265 names32
= att_names32
;
11266 names16
= att_names16
;
11267 names8
= att_names8
;
11268 names8rex
= att_names8rex
;
11269 names_seg
= att_names_seg
;
11270 names_mm
= att_names_mm
;
11271 names_xmm
= att_names_xmm
;
11272 names_ymm
= att_names_ymm
;
11273 index64
= att_index64
;
11274 index32
= att_index32
;
11275 index16
= att_index16
;
11278 separator_char
= ',';
11282 /* The output looks better if we put 7 bytes on a line, since that
11283 puts most long word instructions on a single line. Use 8 bytes
11285 if (info
->mach
== bfd_mach_l1om
11286 || info
->mach
== bfd_mach_l1om_intel_syntax
)
11287 info
->bytes_per_line
= 8;
11289 info
->bytes_per_line
= 7;
11291 info
->private_data
= &priv
;
11292 priv
.max_fetched
= priv
.the_buffer
;
11293 priv
.insn_start
= pc
;
11296 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
11304 start_codep
= priv
.the_buffer
;
11305 codep
= priv
.the_buffer
;
11307 if (setjmp (priv
.bailout
) != 0)
11311 /* Getting here means we tried for data but didn't get it. That
11312 means we have an incomplete instruction of some sort. Just
11313 print the first byte as a prefix or a .byte pseudo-op. */
11314 if (codep
> priv
.the_buffer
)
11316 name
= prefix_name (priv
.the_buffer
[0], priv
.orig_sizeflag
);
11318 (*info
->fprintf_func
) (info
->stream
, "%s", name
);
11321 /* Just print the first byte as a .byte instruction. */
11322 (*info
->fprintf_func
) (info
->stream
, ".byte 0x%x",
11323 (unsigned int) priv
.the_buffer
[0]);
11333 sizeflag
= priv
.orig_sizeflag
;
11335 if (!ckprefix () || rex_used
)
11337 /* Too many prefixes or unused REX prefixes. */
11339 all_prefixes
[i
] && i
< (int) ARRAY_SIZE (all_prefixes
);
11341 (*info
->fprintf_func
) (info
->stream
, "%s",
11342 prefix_name (all_prefixes
[i
], sizeflag
));
11346 insn_codep
= codep
;
11348 FETCH_DATA (info
, codep
+ 1);
11349 two_source_ops
= (*codep
== 0x62) || (*codep
== 0xc8);
11351 if (((prefixes
& PREFIX_FWAIT
)
11352 && ((*codep
< 0xd8) || (*codep
> 0xdf))))
11354 (*info
->fprintf_func
) (info
->stream
, "fwait");
11360 if (*codep
== 0x0f)
11362 unsigned char threebyte
;
11363 FETCH_DATA (info
, codep
+ 2);
11364 threebyte
= *++codep
;
11365 dp
= &dis386_twobyte
[threebyte
];
11366 need_modrm
= twobyte_has_modrm
[*codep
];
11371 dp
= &dis386
[*codep
];
11372 need_modrm
= onebyte_has_modrm
[*codep
];
11376 if ((prefixes
& PREFIX_REPZ
))
11377 used_prefixes
|= PREFIX_REPZ
;
11378 if ((prefixes
& PREFIX_REPNZ
))
11379 used_prefixes
|= PREFIX_REPNZ
;
11380 if ((prefixes
& PREFIX_LOCK
))
11381 used_prefixes
|= PREFIX_LOCK
;
11383 default_prefixes
= 0;
11384 if (prefixes
& PREFIX_ADDR
)
11387 if (dp
->op
[2].bytemode
!= loop_jcxz_mode
|| intel_syntax
)
11389 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
11390 all_prefixes
[last_addr_prefix
] = ADDR32_PREFIX
;
11392 all_prefixes
[last_addr_prefix
] = ADDR16_PREFIX
;
11393 default_prefixes
|= PREFIX_ADDR
;
11397 if ((prefixes
& PREFIX_DATA
))
11400 if (dp
->op
[2].bytemode
== cond_jump_mode
11401 && dp
->op
[0].bytemode
== v_mode
11404 if (sizeflag
& DFLAG
)
11405 all_prefixes
[last_data_prefix
] = DATA32_PREFIX
;
11407 all_prefixes
[last_data_prefix
] = DATA16_PREFIX
;
11408 default_prefixes
|= PREFIX_DATA
;
11410 else if (rex
& REX_W
)
11412 /* REX_W will override PREFIX_DATA. */
11413 default_prefixes
|= PREFIX_DATA
;
11419 FETCH_DATA (info
, codep
+ 1);
11420 modrm
.mod
= (*codep
>> 6) & 3;
11421 modrm
.reg
= (*codep
>> 3) & 7;
11422 modrm
.rm
= *codep
& 7;
11429 if (dp
->name
== NULL
&& dp
->op
[0].bytemode
== FLOATCODE
)
11431 dofloat (sizeflag
);
11435 dp
= get_valid_dis386 (dp
, info
);
11436 if (dp
!= NULL
&& putop (dp
->name
, sizeflag
) == 0)
11438 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
11441 op_ad
= MAX_OPERANDS
- 1 - i
;
11443 (*dp
->op
[i
].rtn
) (dp
->op
[i
].bytemode
, sizeflag
);
11448 /* See if any prefixes were not used. If so, print the first one
11449 separately. If we don't do this, we'll wind up printing an
11450 instruction stream which does not precisely correspond to the
11451 bytes we are disassembling. */
11452 if ((prefixes
& ~(used_prefixes
| default_prefixes
)) != 0)
11454 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
11455 if (all_prefixes
[i
])
11458 name
= prefix_name (all_prefixes
[i
], priv
.orig_sizeflag
);
11460 name
= INTERNAL_DISASSEMBLER_ERROR
;
11461 (*info
->fprintf_func
) (info
->stream
, "%s", name
);
11466 /* Check if the REX prefix is used. */
11467 if (rex_ignored
== 0 && (rex
^ rex_used
) == 0)
11468 all_prefixes
[last_rex_prefix
] = 0;
11470 /* Check if the SEG prefix is used. */
11471 if ((prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
| PREFIX_ES
11472 | PREFIX_FS
| PREFIX_GS
)) != 0
11474 & seg_prefix (all_prefixes
[last_seg_prefix
])) != 0)
11475 all_prefixes
[last_seg_prefix
] = 0;
11477 /* Check if the ADDR prefix is used. */
11478 if ((prefixes
& PREFIX_ADDR
) != 0
11479 && (used_prefixes
& PREFIX_ADDR
) != 0)
11480 all_prefixes
[last_addr_prefix
] = 0;
11482 /* Check if the DATA prefix is used. */
11483 if ((prefixes
& PREFIX_DATA
) != 0
11484 && (used_prefixes
& PREFIX_DATA
) != 0)
11485 all_prefixes
[last_data_prefix
] = 0;
11488 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
11489 if (all_prefixes
[i
])
11492 name
= prefix_name (all_prefixes
[i
], sizeflag
);
11495 prefix_length
+= strlen (name
) + 1;
11496 (*info
->fprintf_func
) (info
->stream
, "%s ", name
);
11499 /* Check maximum code length. */
11500 if ((codep
- start_codep
) > MAX_CODE_LENGTH
)
11502 (*info
->fprintf_func
) (info
->stream
, "(bad)");
11503 return MAX_CODE_LENGTH
;
11506 obufp
= mnemonicendp
;
11507 for (i
= strlen (obuf
) + prefix_length
; i
< 6; i
++)
11510 (*info
->fprintf_func
) (info
->stream
, "%s", obuf
);
11512 /* The enter and bound instructions are printed with operands in the same
11513 order as the intel book; everything else is printed in reverse order. */
11514 if (intel_syntax
|| two_source_ops
)
11518 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
11519 op_txt
[i
] = op_out
[i
];
11521 for (i
= 0; i
< (MAX_OPERANDS
>> 1); ++i
)
11523 op_ad
= op_index
[i
];
11524 op_index
[i
] = op_index
[MAX_OPERANDS
- 1 - i
];
11525 op_index
[MAX_OPERANDS
- 1 - i
] = op_ad
;
11526 riprel
= op_riprel
[i
];
11527 op_riprel
[i
] = op_riprel
[MAX_OPERANDS
- 1 - i
];
11528 op_riprel
[MAX_OPERANDS
- 1 - i
] = riprel
;
11533 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
11534 op_txt
[MAX_OPERANDS
- 1 - i
] = op_out
[i
];
11538 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
11542 (*info
->fprintf_func
) (info
->stream
, ",");
11543 if (op_index
[i
] != -1 && !op_riprel
[i
])
11544 (*info
->print_address_func
) ((bfd_vma
) op_address
[op_index
[i
]], info
);
11546 (*info
->fprintf_func
) (info
->stream
, "%s", op_txt
[i
]);
11550 for (i
= 0; i
< MAX_OPERANDS
; i
++)
11551 if (op_index
[i
] != -1 && op_riprel
[i
])
11553 (*info
->fprintf_func
) (info
->stream
, " # ");
11554 (*info
->print_address_func
) ((bfd_vma
) (start_pc
+ codep
- start_codep
11555 + op_address
[op_index
[i
]]), info
);
11558 return codep
- priv
.the_buffer
;
11561 static const char *float_mem
[] = {
11636 static const unsigned char float_mem_mode
[] = {
11711 #define ST { OP_ST, 0 }
11712 #define STi { OP_STi, 0 }
11714 #define FGRPd9_2 NULL, { { NULL, 0 } }
11715 #define FGRPd9_4 NULL, { { NULL, 1 } }
11716 #define FGRPd9_5 NULL, { { NULL, 2 } }
11717 #define FGRPd9_6 NULL, { { NULL, 3 } }
11718 #define FGRPd9_7 NULL, { { NULL, 4 } }
11719 #define FGRPda_5 NULL, { { NULL, 5 } }
11720 #define FGRPdb_4 NULL, { { NULL, 6 } }
11721 #define FGRPde_3 NULL, { { NULL, 7 } }
11722 #define FGRPdf_4 NULL, { { NULL, 8 } }
11724 static const struct dis386 float_reg
[][8] = {
11727 { "fadd", { ST
, STi
} },
11728 { "fmul", { ST
, STi
} },
11729 { "fcom", { STi
} },
11730 { "fcomp", { STi
} },
11731 { "fsub", { ST
, STi
} },
11732 { "fsubr", { ST
, STi
} },
11733 { "fdiv", { ST
, STi
} },
11734 { "fdivr", { ST
, STi
} },
11738 { "fld", { STi
} },
11739 { "fxch", { STi
} },
11749 { "fcmovb", { ST
, STi
} },
11750 { "fcmove", { ST
, STi
} },
11751 { "fcmovbe",{ ST
, STi
} },
11752 { "fcmovu", { ST
, STi
} },
11760 { "fcmovnb",{ ST
, STi
} },
11761 { "fcmovne",{ ST
, STi
} },
11762 { "fcmovnbe",{ ST
, STi
} },
11763 { "fcmovnu",{ ST
, STi
} },
11765 { "fucomi", { ST
, STi
} },
11766 { "fcomi", { ST
, STi
} },
11771 { "fadd", { STi
, ST
} },
11772 { "fmul", { STi
, ST
} },
11775 { "fsub!M", { STi
, ST
} },
11776 { "fsubM", { STi
, ST
} },
11777 { "fdiv!M", { STi
, ST
} },
11778 { "fdivM", { STi
, ST
} },
11782 { "ffree", { STi
} },
11784 { "fst", { STi
} },
11785 { "fstp", { STi
} },
11786 { "fucom", { STi
} },
11787 { "fucomp", { STi
} },
11793 { "faddp", { STi
, ST
} },
11794 { "fmulp", { STi
, ST
} },
11797 { "fsub!Mp", { STi
, ST
} },
11798 { "fsubMp", { STi
, ST
} },
11799 { "fdiv!Mp", { STi
, ST
} },
11800 { "fdivMp", { STi
, ST
} },
11804 { "ffreep", { STi
} },
11809 { "fucomip", { ST
, STi
} },
11810 { "fcomip", { ST
, STi
} },
11815 static char *fgrps
[][8] = {
11818 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
11823 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
11828 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
11833 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
11838 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
11843 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
11848 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
11849 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
11854 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
11859 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
11864 swap_operand (void)
11866 mnemonicendp
[0] = '.';
11867 mnemonicendp
[1] = 's';
11872 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED
,
11873 int sizeflag ATTRIBUTE_UNUSED
)
11875 /* Skip mod/rm byte. */
11881 dofloat (int sizeflag
)
11883 const struct dis386
*dp
;
11884 unsigned char floatop
;
11886 floatop
= codep
[-1];
11888 if (modrm
.mod
!= 3)
11890 int fp_indx
= (floatop
- 0xd8) * 8 + modrm
.reg
;
11892 putop (float_mem
[fp_indx
], sizeflag
);
11895 OP_E (float_mem_mode
[fp_indx
], sizeflag
);
11898 /* Skip mod/rm byte. */
11902 dp
= &float_reg
[floatop
- 0xd8][modrm
.reg
];
11903 if (dp
->name
== NULL
)
11905 putop (fgrps
[dp
->op
[0].bytemode
][modrm
.rm
], sizeflag
);
11907 /* Instruction fnstsw is only one with strange arg. */
11908 if (floatop
== 0xdf && codep
[-1] == 0xe0)
11909 strcpy (op_out
[0], names16
[0]);
11913 putop (dp
->name
, sizeflag
);
11918 (*dp
->op
[0].rtn
) (dp
->op
[0].bytemode
, sizeflag
);
11923 (*dp
->op
[1].rtn
) (dp
->op
[1].bytemode
, sizeflag
);
11928 OP_ST (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
11930 oappend ("%st" + intel_syntax
);
11934 OP_STi (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
11936 sprintf (scratchbuf
, "%%st(%d)", modrm
.rm
);
11937 oappend (scratchbuf
+ intel_syntax
);
11940 /* Capital letters in template are macros. */
11942 putop (const char *in_template
, int sizeflag
)
11947 unsigned int l
= 0, len
= 1;
11950 #define SAVE_LAST(c) \
11951 if (l < len && l < sizeof (last)) \
11956 for (p
= in_template
; *p
; p
++)
11973 while (*++p
!= '|')
11974 if (*p
== '}' || *p
== '\0')
11977 /* Fall through. */
11982 while (*++p
!= '}')
11993 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
11997 if (l
== 0 && len
== 1)
12002 if (sizeflag
& SUFFIX_ALWAYS
)
12015 if (address_mode
== mode_64bit
12016 && !(prefixes
& PREFIX_ADDR
))
12027 if (intel_syntax
&& !alt
)
12029 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
12031 if (sizeflag
& DFLAG
)
12032 *obufp
++ = intel_syntax
? 'd' : 'l';
12034 *obufp
++ = intel_syntax
? 'w' : 's';
12035 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12039 if (intel_syntax
|| !(sizeflag
& SUFFIX_ALWAYS
))
12042 if (modrm
.mod
== 3)
12048 if (sizeflag
& DFLAG
)
12049 *obufp
++ = intel_syntax
? 'd' : 'l';
12052 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12058 case 'E': /* For jcxz/jecxz */
12059 if (address_mode
== mode_64bit
)
12061 if (sizeflag
& AFLAG
)
12067 if (sizeflag
& AFLAG
)
12069 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
12074 if ((prefixes
& PREFIX_ADDR
) || (sizeflag
& SUFFIX_ALWAYS
))
12076 if (sizeflag
& AFLAG
)
12077 *obufp
++ = address_mode
== mode_64bit
? 'q' : 'l';
12079 *obufp
++ = address_mode
== mode_64bit
? 'l' : 'w';
12080 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
12084 if (intel_syntax
|| (obufp
[-1] != 's' && !(sizeflag
& SUFFIX_ALWAYS
)))
12086 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
12090 if (!(rex
& REX_W
))
12091 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12096 if ((prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_CS
12097 || (prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_DS
)
12099 used_prefixes
|= prefixes
& (PREFIX_CS
| PREFIX_DS
);
12102 if (prefixes
& PREFIX_DS
)
12123 if (address_mode
== mode_64bit
&& (sizeflag
& SUFFIX_ALWAYS
))
12128 /* Fall through. */
12131 if (l
!= 0 || len
!= 1)
12139 if (sizeflag
& SUFFIX_ALWAYS
)
12143 if (intel_mnemonic
!= cond
)
12147 if ((prefixes
& PREFIX_FWAIT
) == 0)
12150 used_prefixes
|= PREFIX_FWAIT
;
12156 else if (intel_syntax
&& (sizeflag
& DFLAG
))
12160 if (!(rex
& REX_W
))
12161 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12166 if (address_mode
== mode_64bit
&& (sizeflag
& DFLAG
))
12171 /* Fall through. */
12175 if ((prefixes
& PREFIX_DATA
)
12177 || (sizeflag
& SUFFIX_ALWAYS
))
12184 if (sizeflag
& DFLAG
)
12188 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12195 if (address_mode
== mode_64bit
&& (sizeflag
& DFLAG
))
12197 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
12201 /* Fall through. */
12204 if (l
== 0 && len
== 1)
12207 if (intel_syntax
&& !alt
)
12210 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
12216 if (sizeflag
& DFLAG
)
12217 *obufp
++ = intel_syntax
? 'd' : 'l';
12220 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12226 if (l
!= 1 || len
!= 2 || last
[0] != 'L')
12232 || (modrm
.mod
== 3 && !(sizeflag
& SUFFIX_ALWAYS
)))
12247 else if (sizeflag
& DFLAG
)
12256 if (intel_syntax
&& !p
[1]
12257 && ((rex
& REX_W
) || (sizeflag
& DFLAG
)))
12259 if (!(rex
& REX_W
))
12260 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12263 if (l
== 0 && len
== 1)
12267 if (address_mode
== mode_64bit
&& (sizeflag
& DFLAG
))
12269 if (sizeflag
& SUFFIX_ALWAYS
)
12291 /* Fall through. */
12294 if (l
== 0 && len
== 1)
12299 if (sizeflag
& SUFFIX_ALWAYS
)
12305 if (sizeflag
& DFLAG
)
12309 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12323 if (address_mode
== mode_64bit
12324 && !(prefixes
& PREFIX_ADDR
))
12335 if (l
!= 0 || len
!= 1)
12340 if (need_vex
&& vex
.prefix
)
12342 if (vex
.prefix
== DATA_PREFIX_OPCODE
)
12349 if (prefixes
& PREFIX_DATA
)
12353 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12357 if (l
== 0 && len
== 1)
12359 if (intel_syntax
|| !(sizeflag
& SUFFIX_ALWAYS
))
12370 if (l
!= 1 || len
!= 2 || last
[0] != 'X')
12378 || (modrm
.mod
== 3 && !(sizeflag
& SUFFIX_ALWAYS
)))
12380 switch (vex
.length
)
12394 if (l
== 0 && len
== 1)
12396 /* operand size flag for cwtl, cbtw */
12405 else if (sizeflag
& DFLAG
)
12409 if (!(rex
& REX_W
))
12410 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12414 if (l
!= 1 || len
!= 2 || last
[0] != 'X')
12421 *obufp
++ = vex
.w
? 'd': 's';
12428 mnemonicendp
= obufp
;
12433 oappend (const char *s
)
12435 obufp
= stpcpy (obufp
, s
);
12441 if (prefixes
& PREFIX_CS
)
12443 used_prefixes
|= PREFIX_CS
;
12444 oappend ("%cs:" + intel_syntax
);
12446 if (prefixes
& PREFIX_DS
)
12448 used_prefixes
|= PREFIX_DS
;
12449 oappend ("%ds:" + intel_syntax
);
12451 if (prefixes
& PREFIX_SS
)
12453 used_prefixes
|= PREFIX_SS
;
12454 oappend ("%ss:" + intel_syntax
);
12456 if (prefixes
& PREFIX_ES
)
12458 used_prefixes
|= PREFIX_ES
;
12459 oappend ("%es:" + intel_syntax
);
12461 if (prefixes
& PREFIX_FS
)
12463 used_prefixes
|= PREFIX_FS
;
12464 oappend ("%fs:" + intel_syntax
);
12466 if (prefixes
& PREFIX_GS
)
12468 used_prefixes
|= PREFIX_GS
;
12469 oappend ("%gs:" + intel_syntax
);
12474 OP_indirE (int bytemode
, int sizeflag
)
12478 OP_E (bytemode
, sizeflag
);
12482 print_operand_value (char *buf
, int hex
, bfd_vma disp
)
12484 if (address_mode
== mode_64bit
)
12492 sprintf_vma (tmp
, disp
);
12493 for (i
= 0; tmp
[i
] == '0' && tmp
[i
+ 1]; i
++);
12494 strcpy (buf
+ 2, tmp
+ i
);
12498 bfd_signed_vma v
= disp
;
12505 /* Check for possible overflow on 0x8000000000000000. */
12508 strcpy (buf
, "9223372036854775808");
12522 tmp
[28 - i
] = (v
% 10) + '0';
12526 strcpy (buf
, tmp
+ 29 - i
);
12532 sprintf (buf
, "0x%x", (unsigned int) disp
);
12534 sprintf (buf
, "%d", (int) disp
);
12538 /* Put DISP in BUF as signed hex number. */
12541 print_displacement (char *buf
, bfd_vma disp
)
12543 bfd_signed_vma val
= disp
;
12552 /* Check for possible overflow. */
12555 switch (address_mode
)
12558 strcpy (buf
+ j
, "0x8000000000000000");
12561 strcpy (buf
+ j
, "0x80000000");
12564 strcpy (buf
+ j
, "0x8000");
12574 sprintf_vma (tmp
, (bfd_vma
) val
);
12575 for (i
= 0; tmp
[i
] == '0'; i
++)
12577 if (tmp
[i
] == '\0')
12579 strcpy (buf
+ j
, tmp
+ i
);
12583 intel_operand_size (int bytemode
, int sizeflag
)
12590 oappend ("BYTE PTR ");
12594 oappend ("WORD PTR ");
12597 if (address_mode
== mode_64bit
&& (sizeflag
& DFLAG
))
12599 oappend ("QWORD PTR ");
12608 oappend ("QWORD PTR ");
12611 if ((sizeflag
& DFLAG
) || bytemode
== dq_mode
)
12612 oappend ("DWORD PTR ");
12614 oappend ("WORD PTR ");
12615 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12619 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
12621 oappend ("WORD PTR ");
12622 if (!(rex
& REX_W
))
12623 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12626 if (sizeflag
& DFLAG
)
12627 oappend ("QWORD PTR ");
12629 oappend ("DWORD PTR ");
12630 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12635 oappend ("DWORD PTR ");
12639 oappend ("QWORD PTR ");
12642 if (address_mode
== mode_64bit
)
12643 oappend ("QWORD PTR ");
12645 oappend ("DWORD PTR ");
12648 if (sizeflag
& DFLAG
)
12649 oappend ("FWORD PTR ");
12651 oappend ("DWORD PTR ");
12652 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12655 oappend ("TBYTE PTR ");
12661 switch (vex
.length
)
12664 oappend ("XMMWORD PTR ");
12667 oappend ("YMMWORD PTR ");
12674 oappend ("XMMWORD PTR ");
12677 oappend ("XMMWORD PTR ");
12683 switch (vex
.length
)
12686 oappend ("QWORD PTR ");
12689 oappend ("XMMWORD PTR ");
12699 switch (vex
.length
)
12702 oappend ("QWORD PTR ");
12705 oappend ("YMMWORD PTR ");
12712 oappend ("OWORD PTR ");
12714 case vex_w_dq_mode
:
12719 oappend ("QWORD PTR ");
12721 oappend ("DWORD PTR ");
12729 OP_E_register (int bytemode
, int sizeflag
)
12731 int reg
= modrm
.rm
;
12732 const char **names
;
12738 if ((sizeflag
& SUFFIX_ALWAYS
)
12739 && (bytemode
== b_swap_mode
|| bytemode
== v_swap_mode
))
12762 names
= address_mode
== mode_64bit
? names64
: names32
;
12765 if (address_mode
== mode_64bit
&& (sizeflag
& DFLAG
))
12783 if ((sizeflag
& DFLAG
)
12784 || (bytemode
!= v_mode
12785 && bytemode
!= v_swap_mode
))
12789 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12795 oappend (INTERNAL_DISASSEMBLER_ERROR
);
12798 oappend (names
[reg
]);
12802 OP_E_memory (int bytemode
, int sizeflag
)
12805 int add
= (rex
& REX_B
) ? 8 : 0;
12810 intel_operand_size (bytemode
, sizeflag
);
12813 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
12815 /* 32/64 bit address mode */
12833 FETCH_DATA (the_info
, codep
+ 1);
12834 vindex
= (*codep
>> 3) & 7;
12835 scale
= (*codep
>> 6) & 3;
12840 haveindex
= vindex
!= 4;
12843 rbase
= base
+ add
;
12851 if (address_mode
== mode_64bit
&& !havesib
)
12857 FETCH_DATA (the_info
, codep
+ 1);
12859 if ((disp
& 0x80) != 0)
12867 /* In 32bit mode, we need index register to tell [offset] from
12868 [eiz*1 + offset]. */
12869 needindex
= (havesib
12872 && address_mode
== mode_32bit
);
12873 havedisp
= (havebase
12875 || (havesib
&& (haveindex
|| scale
!= 0)));
12878 if (modrm
.mod
!= 0 || base
== 5)
12880 if (havedisp
|| riprel
)
12881 print_displacement (scratchbuf
, disp
);
12883 print_operand_value (scratchbuf
, 1, disp
);
12884 oappend (scratchbuf
);
12888 oappend (sizeflag
& AFLAG
? "(%rip)" : "(%eip)");
12892 if (havebase
|| haveindex
|| riprel
)
12893 used_prefixes
|= PREFIX_ADDR
;
12895 if (havedisp
|| (intel_syntax
&& riprel
))
12897 *obufp
++ = open_char
;
12898 if (intel_syntax
&& riprel
)
12901 oappend (sizeflag
& AFLAG
? "rip" : "eip");
12905 oappend (address_mode
== mode_64bit
&& (sizeflag
& AFLAG
)
12906 ? names64
[rbase
] : names32
[rbase
]);
12909 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
12910 print index to tell base + index from base. */
12914 || (havebase
&& base
!= ESP_REG_NUM
))
12916 if (!intel_syntax
|| havebase
)
12918 *obufp
++ = separator_char
;
12922 oappend (address_mode
== mode_64bit
12923 && (sizeflag
& AFLAG
)
12924 ? names64
[vindex
] : names32
[vindex
]);
12926 oappend (address_mode
== mode_64bit
12927 && (sizeflag
& AFLAG
)
12928 ? index64
: index32
);
12930 *obufp
++ = scale_char
;
12932 sprintf (scratchbuf
, "%d", 1 << scale
);
12933 oappend (scratchbuf
);
12937 && (disp
|| modrm
.mod
!= 0 || base
== 5))
12939 if (!havedisp
|| (bfd_signed_vma
) disp
>= 0)
12944 else if (modrm
.mod
!= 1 && disp
!= -disp
)
12948 disp
= - (bfd_signed_vma
) disp
;
12952 print_displacement (scratchbuf
, disp
);
12954 print_operand_value (scratchbuf
, 1, disp
);
12955 oappend (scratchbuf
);
12958 *obufp
++ = close_char
;
12961 else if (intel_syntax
)
12963 if (modrm
.mod
!= 0 || base
== 5)
12965 if (prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
12966 | PREFIX_ES
| PREFIX_FS
| PREFIX_GS
))
12970 oappend (names_seg
[ds_reg
- es_reg
]);
12973 print_operand_value (scratchbuf
, 1, disp
);
12974 oappend (scratchbuf
);
12980 /* 16 bit address mode */
12981 used_prefixes
|= prefixes
& PREFIX_ADDR
;
12988 if ((disp
& 0x8000) != 0)
12993 FETCH_DATA (the_info
, codep
+ 1);
12995 if ((disp
& 0x80) != 0)
13000 if ((disp
& 0x8000) != 0)
13006 if (modrm
.mod
!= 0 || modrm
.rm
== 6)
13008 print_displacement (scratchbuf
, disp
);
13009 oappend (scratchbuf
);
13012 if (modrm
.mod
!= 0 || modrm
.rm
!= 6)
13014 *obufp
++ = open_char
;
13016 oappend (index16
[modrm
.rm
]);
13018 && (disp
|| modrm
.mod
!= 0 || modrm
.rm
== 6))
13020 if ((bfd_signed_vma
) disp
>= 0)
13025 else if (modrm
.mod
!= 1)
13029 disp
= - (bfd_signed_vma
) disp
;
13032 print_displacement (scratchbuf
, disp
);
13033 oappend (scratchbuf
);
13036 *obufp
++ = close_char
;
13039 else if (intel_syntax
)
13041 if (prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
13042 | PREFIX_ES
| PREFIX_FS
| PREFIX_GS
))
13046 oappend (names_seg
[ds_reg
- es_reg
]);
13049 print_operand_value (scratchbuf
, 1, disp
& 0xffff);
13050 oappend (scratchbuf
);
13056 OP_E (int bytemode
, int sizeflag
)
13058 /* Skip mod/rm byte. */
13062 if (modrm
.mod
== 3)
13063 OP_E_register (bytemode
, sizeflag
);
13065 OP_E_memory (bytemode
, sizeflag
);
13069 OP_G (int bytemode
, int sizeflag
)
13080 oappend (names8rex
[modrm
.reg
+ add
]);
13082 oappend (names8
[modrm
.reg
+ add
]);
13085 oappend (names16
[modrm
.reg
+ add
]);
13088 oappend (names32
[modrm
.reg
+ add
]);
13091 oappend (names64
[modrm
.reg
+ add
]);
13100 oappend (names64
[modrm
.reg
+ add
]);
13103 if ((sizeflag
& DFLAG
) || bytemode
!= v_mode
)
13104 oappend (names32
[modrm
.reg
+ add
]);
13106 oappend (names16
[modrm
.reg
+ add
]);
13107 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13111 if (address_mode
== mode_64bit
)
13112 oappend (names64
[modrm
.reg
+ add
]);
13114 oappend (names32
[modrm
.reg
+ add
]);
13117 oappend (INTERNAL_DISASSEMBLER_ERROR
);
13130 FETCH_DATA (the_info
, codep
+ 8);
13131 a
= *codep
++ & 0xff;
13132 a
|= (*codep
++ & 0xff) << 8;
13133 a
|= (*codep
++ & 0xff) << 16;
13134 a
|= (*codep
++ & 0xff) << 24;
13135 b
= *codep
++ & 0xff;
13136 b
|= (*codep
++ & 0xff) << 8;
13137 b
|= (*codep
++ & 0xff) << 16;
13138 b
|= (*codep
++ & 0xff) << 24;
13139 x
= a
+ ((bfd_vma
) b
<< 32);
13147 static bfd_signed_vma
13150 bfd_signed_vma x
= 0;
13152 FETCH_DATA (the_info
, codep
+ 4);
13153 x
= *codep
++ & (bfd_signed_vma
) 0xff;
13154 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
13155 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
13156 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
13160 static bfd_signed_vma
13163 bfd_signed_vma x
= 0;
13165 FETCH_DATA (the_info
, codep
+ 4);
13166 x
= *codep
++ & (bfd_signed_vma
) 0xff;
13167 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
13168 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
13169 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
13171 x
= (x
^ ((bfd_signed_vma
) 1 << 31)) - ((bfd_signed_vma
) 1 << 31);
13181 FETCH_DATA (the_info
, codep
+ 2);
13182 x
= *codep
++ & 0xff;
13183 x
|= (*codep
++ & 0xff) << 8;
13188 set_op (bfd_vma op
, int riprel
)
13190 op_index
[op_ad
] = op_ad
;
13191 if (address_mode
== mode_64bit
)
13193 op_address
[op_ad
] = op
;
13194 op_riprel
[op_ad
] = riprel
;
13198 /* Mask to get a 32-bit address. */
13199 op_address
[op_ad
] = op
& 0xffffffff;
13200 op_riprel
[op_ad
] = riprel
& 0xffffffff;
13205 OP_REG (int code
, int sizeflag
)
13217 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
13218 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
13219 s
= names16
[code
- ax_reg
+ add
];
13221 case es_reg
: case ss_reg
: case cs_reg
:
13222 case ds_reg
: case fs_reg
: case gs_reg
:
13223 s
= names_seg
[code
- es_reg
+ add
];
13225 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
13226 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
13229 s
= names8rex
[code
- al_reg
+ add
];
13231 s
= names8
[code
- al_reg
];
13233 case rAX_reg
: case rCX_reg
: case rDX_reg
: case rBX_reg
:
13234 case rSP_reg
: case rBP_reg
: case rSI_reg
: case rDI_reg
:
13235 if (address_mode
== mode_64bit
&& (sizeflag
& DFLAG
))
13237 s
= names64
[code
- rAX_reg
+ add
];
13240 code
+= eAX_reg
- rAX_reg
;
13241 /* Fall through. */
13242 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
13243 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
13246 s
= names64
[code
- eAX_reg
+ add
];
13249 if (sizeflag
& DFLAG
)
13250 s
= names32
[code
- eAX_reg
+ add
];
13252 s
= names16
[code
- eAX_reg
+ add
];
13253 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13257 s
= INTERNAL_DISASSEMBLER_ERROR
;
13264 OP_IMREG (int code
, int sizeflag
)
13276 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
13277 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
13278 s
= names16
[code
- ax_reg
];
13280 case es_reg
: case ss_reg
: case cs_reg
:
13281 case ds_reg
: case fs_reg
: case gs_reg
:
13282 s
= names_seg
[code
- es_reg
];
13284 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
13285 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
13288 s
= names8rex
[code
- al_reg
];
13290 s
= names8
[code
- al_reg
];
13292 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
13293 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
13296 s
= names64
[code
- eAX_reg
];
13299 if (sizeflag
& DFLAG
)
13300 s
= names32
[code
- eAX_reg
];
13302 s
= names16
[code
- eAX_reg
];
13303 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13306 case z_mode_ax_reg
:
13307 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
13311 if (!(rex
& REX_W
))
13312 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13315 s
= INTERNAL_DISASSEMBLER_ERROR
;
13322 OP_I (int bytemode
, int sizeflag
)
13325 bfd_signed_vma mask
= -1;
13330 FETCH_DATA (the_info
, codep
+ 1);
13335 if (address_mode
== mode_64bit
)
13340 /* Fall through. */
13347 if (sizeflag
& DFLAG
)
13357 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13369 oappend (INTERNAL_DISASSEMBLER_ERROR
);
13374 scratchbuf
[0] = '$';
13375 print_operand_value (scratchbuf
+ 1, 1, op
);
13376 oappend (scratchbuf
+ intel_syntax
);
13377 scratchbuf
[0] = '\0';
13381 OP_I64 (int bytemode
, int sizeflag
)
13384 bfd_signed_vma mask
= -1;
13386 if (address_mode
!= mode_64bit
)
13388 OP_I (bytemode
, sizeflag
);
13395 FETCH_DATA (the_info
, codep
+ 1);
13405 if (sizeflag
& DFLAG
)
13415 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13423 oappend (INTERNAL_DISASSEMBLER_ERROR
);
13428 scratchbuf
[0] = '$';
13429 print_operand_value (scratchbuf
+ 1, 1, op
);
13430 oappend (scratchbuf
+ intel_syntax
);
13431 scratchbuf
[0] = '\0';
13435 OP_sI (int bytemode
, int sizeflag
)
13438 bfd_signed_vma mask
= -1;
13443 FETCH_DATA (the_info
, codep
+ 1);
13445 if ((op
& 0x80) != 0)
13455 if (sizeflag
& DFLAG
)
13464 if ((op
& 0x8000) != 0)
13467 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13473 if ((op
& 0x8000) != 0)
13477 oappend (INTERNAL_DISASSEMBLER_ERROR
);
13481 scratchbuf
[0] = '$';
13482 print_operand_value (scratchbuf
+ 1, 1, op
);
13483 oappend (scratchbuf
+ intel_syntax
);
13487 OP_J (int bytemode
, int sizeflag
)
13491 bfd_vma segment
= 0;
13496 FETCH_DATA (the_info
, codep
+ 1);
13498 if ((disp
& 0x80) != 0)
13503 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
13508 if ((disp
& 0x8000) != 0)
13510 /* In 16bit mode, address is wrapped around at 64k within
13511 the same segment. Otherwise, a data16 prefix on a jump
13512 instruction means that the pc is masked to 16 bits after
13513 the displacement is added! */
13515 if ((prefixes
& PREFIX_DATA
) == 0)
13516 segment
= ((start_pc
+ codep
- start_codep
)
13517 & ~((bfd_vma
) 0xffff));
13519 if (!(rex
& REX_W
))
13520 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13523 oappend (INTERNAL_DISASSEMBLER_ERROR
);
13526 disp
= ((start_pc
+ codep
- start_codep
+ disp
) & mask
) | segment
;
13528 print_operand_value (scratchbuf
, 1, disp
);
13529 oappend (scratchbuf
);
13533 OP_SEG (int bytemode
, int sizeflag
)
13535 if (bytemode
== w_mode
)
13536 oappend (names_seg
[modrm
.reg
]);
13538 OP_E (modrm
.mod
== 3 ? bytemode
: w_mode
, sizeflag
);
13542 OP_DIR (int dummy ATTRIBUTE_UNUSED
, int sizeflag
)
13546 if (sizeflag
& DFLAG
)
13556 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13558 sprintf (scratchbuf
, "0x%x:0x%x", seg
, offset
);
13560 sprintf (scratchbuf
, "$0x%x,$0x%x", seg
, offset
);
13561 oappend (scratchbuf
);
13565 OP_OFF (int bytemode
, int sizeflag
)
13569 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
13570 intel_operand_size (bytemode
, sizeflag
);
13573 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
13580 if (!(prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
13581 | PREFIX_ES
| PREFIX_FS
| PREFIX_GS
)))
13583 oappend (names_seg
[ds_reg
- es_reg
]);
13587 print_operand_value (scratchbuf
, 1, off
);
13588 oappend (scratchbuf
);
13592 OP_OFF64 (int bytemode
, int sizeflag
)
13596 if (address_mode
!= mode_64bit
13597 || (prefixes
& PREFIX_ADDR
))
13599 OP_OFF (bytemode
, sizeflag
);
13603 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
13604 intel_operand_size (bytemode
, sizeflag
);
13611 if (!(prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
13612 | PREFIX_ES
| PREFIX_FS
| PREFIX_GS
)))
13614 oappend (names_seg
[ds_reg
- es_reg
]);
13618 print_operand_value (scratchbuf
, 1, off
);
13619 oappend (scratchbuf
);
13623 ptr_reg (int code
, int sizeflag
)
13627 *obufp
++ = open_char
;
13628 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
13629 if (address_mode
== mode_64bit
)
13631 if (!(sizeflag
& AFLAG
))
13632 s
= names32
[code
- eAX_reg
];
13634 s
= names64
[code
- eAX_reg
];
13636 else if (sizeflag
& AFLAG
)
13637 s
= names32
[code
- eAX_reg
];
13639 s
= names16
[code
- eAX_reg
];
13641 *obufp
++ = close_char
;
13646 OP_ESreg (int code
, int sizeflag
)
13652 case 0x6d: /* insw/insl */
13653 intel_operand_size (z_mode
, sizeflag
);
13655 case 0xa5: /* movsw/movsl/movsq */
13656 case 0xa7: /* cmpsw/cmpsl/cmpsq */
13657 case 0xab: /* stosw/stosl */
13658 case 0xaf: /* scasw/scasl */
13659 intel_operand_size (v_mode
, sizeflag
);
13662 intel_operand_size (b_mode
, sizeflag
);
13665 oappend ("%es:" + intel_syntax
);
13666 ptr_reg (code
, sizeflag
);
13670 OP_DSreg (int code
, int sizeflag
)
13676 case 0x6f: /* outsw/outsl */
13677 intel_operand_size (z_mode
, sizeflag
);
13679 case 0xa5: /* movsw/movsl/movsq */
13680 case 0xa7: /* cmpsw/cmpsl/cmpsq */
13681 case 0xad: /* lodsw/lodsl/lodsq */
13682 intel_operand_size (v_mode
, sizeflag
);
13685 intel_operand_size (b_mode
, sizeflag
);
13694 | PREFIX_GS
)) == 0)
13695 prefixes
|= PREFIX_DS
;
13697 ptr_reg (code
, sizeflag
);
13701 OP_C (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
13709 else if (address_mode
!= mode_64bit
&& (prefixes
& PREFIX_LOCK
))
13711 all_prefixes
[last_lock_prefix
] = 0;
13712 used_prefixes
|= PREFIX_LOCK
;
13717 sprintf (scratchbuf
, "%%cr%d", modrm
.reg
+ add
);
13718 oappend (scratchbuf
+ intel_syntax
);
13722 OP_D (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
13731 sprintf (scratchbuf
, "db%d", modrm
.reg
+ add
);
13733 sprintf (scratchbuf
, "%%db%d", modrm
.reg
+ add
);
13734 oappend (scratchbuf
);
13738 OP_T (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
13740 sprintf (scratchbuf
, "%%tr%d", modrm
.reg
);
13741 oappend (scratchbuf
+ intel_syntax
);
13745 OP_R (int bytemode
, int sizeflag
)
13747 if (modrm
.mod
== 3)
13748 OP_E (bytemode
, sizeflag
);
13754 OP_MMX (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
13756 int reg
= modrm
.reg
;
13757 const char **names
;
13759 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13760 if (prefixes
& PREFIX_DATA
)
13769 oappend (names
[reg
]);
13773 OP_XMM (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
13775 int reg
= modrm
.reg
;
13776 const char **names
;
13781 if (need_vex
&& bytemode
!= xmm_mode
)
13783 switch (vex
.length
)
13797 oappend (names
[reg
]);
13801 OP_EM (int bytemode
, int sizeflag
)
13804 const char **names
;
13806 if (modrm
.mod
!= 3)
13809 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
13811 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
13812 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13814 OP_E (bytemode
, sizeflag
);
13818 if ((sizeflag
& SUFFIX_ALWAYS
) && bytemode
== v_swap_mode
)
13821 /* Skip mod/rm byte. */
13824 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13826 if (prefixes
& PREFIX_DATA
)
13835 oappend (names
[reg
]);
13838 /* cvt* are the only instructions in sse2 which have
13839 both SSE and MMX operands and also have 0x66 prefix
13840 in their opcode. 0x66 was originally used to differentiate
13841 between SSE and MMX instruction(operands). So we have to handle the
13842 cvt* separately using OP_EMC and OP_MXC */
13844 OP_EMC (int bytemode
, int sizeflag
)
13846 if (modrm
.mod
!= 3)
13848 if (intel_syntax
&& bytemode
== v_mode
)
13850 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
13851 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13853 OP_E (bytemode
, sizeflag
);
13857 /* Skip mod/rm byte. */
13860 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13861 oappend (names_mm
[modrm
.rm
]);
13865 OP_MXC (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
13867 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13868 oappend (names_mm
[modrm
.reg
]);
13872 OP_EX (int bytemode
, int sizeflag
)
13875 const char **names
;
13877 /* Skip mod/rm byte. */
13881 if (modrm
.mod
!= 3)
13883 OP_E_memory (bytemode
, sizeflag
);
13892 if ((sizeflag
& SUFFIX_ALWAYS
)
13893 && (bytemode
== x_swap_mode
13894 || bytemode
== d_swap_mode
13895 || bytemode
== q_swap_mode
))
13899 && bytemode
!= xmm_mode
13900 && bytemode
!= xmmq_mode
)
13902 switch (vex
.length
)
13916 oappend (names
[reg
]);
13920 OP_MS (int bytemode
, int sizeflag
)
13922 if (modrm
.mod
== 3)
13923 OP_EM (bytemode
, sizeflag
);
13929 OP_XS (int bytemode
, int sizeflag
)
13931 if (modrm
.mod
== 3)
13932 OP_EX (bytemode
, sizeflag
);
13938 OP_M (int bytemode
, int sizeflag
)
13940 if (modrm
.mod
== 3)
13941 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
13944 OP_E (bytemode
, sizeflag
);
13948 OP_0f07 (int bytemode
, int sizeflag
)
13950 if (modrm
.mod
!= 3 || modrm
.rm
!= 0)
13953 OP_E (bytemode
, sizeflag
);
13956 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
13957 32bit mode and "xchg %rax,%rax" in 64bit mode. */
13960 NOP_Fixup1 (int bytemode
, int sizeflag
)
13962 if ((prefixes
& PREFIX_DATA
) != 0
13965 && address_mode
== mode_64bit
))
13966 OP_REG (bytemode
, sizeflag
);
13968 strcpy (obuf
, "nop");
13972 NOP_Fixup2 (int bytemode
, int sizeflag
)
13974 if ((prefixes
& PREFIX_DATA
) != 0
13977 && address_mode
== mode_64bit
))
13978 OP_IMREG (bytemode
, sizeflag
);
13981 static const char *const Suffix3DNow
[] = {
13982 /* 00 */ NULL
, NULL
, NULL
, NULL
,
13983 /* 04 */ NULL
, NULL
, NULL
, NULL
,
13984 /* 08 */ NULL
, NULL
, NULL
, NULL
,
13985 /* 0C */ "pi2fw", "pi2fd", NULL
, NULL
,
13986 /* 10 */ NULL
, NULL
, NULL
, NULL
,
13987 /* 14 */ NULL
, NULL
, NULL
, NULL
,
13988 /* 18 */ NULL
, NULL
, NULL
, NULL
,
13989 /* 1C */ "pf2iw", "pf2id", NULL
, NULL
,
13990 /* 20 */ NULL
, NULL
, NULL
, NULL
,
13991 /* 24 */ NULL
, NULL
, NULL
, NULL
,
13992 /* 28 */ NULL
, NULL
, NULL
, NULL
,
13993 /* 2C */ NULL
, NULL
, NULL
, NULL
,
13994 /* 30 */ NULL
, NULL
, NULL
, NULL
,
13995 /* 34 */ NULL
, NULL
, NULL
, NULL
,
13996 /* 38 */ NULL
, NULL
, NULL
, NULL
,
13997 /* 3C */ NULL
, NULL
, NULL
, NULL
,
13998 /* 40 */ NULL
, NULL
, NULL
, NULL
,
13999 /* 44 */ NULL
, NULL
, NULL
, NULL
,
14000 /* 48 */ NULL
, NULL
, NULL
, NULL
,
14001 /* 4C */ NULL
, NULL
, NULL
, NULL
,
14002 /* 50 */ NULL
, NULL
, NULL
, NULL
,
14003 /* 54 */ NULL
, NULL
, NULL
, NULL
,
14004 /* 58 */ NULL
, NULL
, NULL
, NULL
,
14005 /* 5C */ NULL
, NULL
, NULL
, NULL
,
14006 /* 60 */ NULL
, NULL
, NULL
, NULL
,
14007 /* 64 */ NULL
, NULL
, NULL
, NULL
,
14008 /* 68 */ NULL
, NULL
, NULL
, NULL
,
14009 /* 6C */ NULL
, NULL
, NULL
, NULL
,
14010 /* 70 */ NULL
, NULL
, NULL
, NULL
,
14011 /* 74 */ NULL
, NULL
, NULL
, NULL
,
14012 /* 78 */ NULL
, NULL
, NULL
, NULL
,
14013 /* 7C */ NULL
, NULL
, NULL
, NULL
,
14014 /* 80 */ NULL
, NULL
, NULL
, NULL
,
14015 /* 84 */ NULL
, NULL
, NULL
, NULL
,
14016 /* 88 */ NULL
, NULL
, "pfnacc", NULL
,
14017 /* 8C */ NULL
, NULL
, "pfpnacc", NULL
,
14018 /* 90 */ "pfcmpge", NULL
, NULL
, NULL
,
14019 /* 94 */ "pfmin", NULL
, "pfrcp", "pfrsqrt",
14020 /* 98 */ NULL
, NULL
, "pfsub", NULL
,
14021 /* 9C */ NULL
, NULL
, "pfadd", NULL
,
14022 /* A0 */ "pfcmpgt", NULL
, NULL
, NULL
,
14023 /* A4 */ "pfmax", NULL
, "pfrcpit1", "pfrsqit1",
14024 /* A8 */ NULL
, NULL
, "pfsubr", NULL
,
14025 /* AC */ NULL
, NULL
, "pfacc", NULL
,
14026 /* B0 */ "pfcmpeq", NULL
, NULL
, NULL
,
14027 /* B4 */ "pfmul", NULL
, "pfrcpit2", "pmulhrw",
14028 /* B8 */ NULL
, NULL
, NULL
, "pswapd",
14029 /* BC */ NULL
, NULL
, NULL
, "pavgusb",
14030 /* C0 */ NULL
, NULL
, NULL
, NULL
,
14031 /* C4 */ NULL
, NULL
, NULL
, NULL
,
14032 /* C8 */ NULL
, NULL
, NULL
, NULL
,
14033 /* CC */ NULL
, NULL
, NULL
, NULL
,
14034 /* D0 */ NULL
, NULL
, NULL
, NULL
,
14035 /* D4 */ NULL
, NULL
, NULL
, NULL
,
14036 /* D8 */ NULL
, NULL
, NULL
, NULL
,
14037 /* DC */ NULL
, NULL
, NULL
, NULL
,
14038 /* E0 */ NULL
, NULL
, NULL
, NULL
,
14039 /* E4 */ NULL
, NULL
, NULL
, NULL
,
14040 /* E8 */ NULL
, NULL
, NULL
, NULL
,
14041 /* EC */ NULL
, NULL
, NULL
, NULL
,
14042 /* F0 */ NULL
, NULL
, NULL
, NULL
,
14043 /* F4 */ NULL
, NULL
, NULL
, NULL
,
14044 /* F8 */ NULL
, NULL
, NULL
, NULL
,
14045 /* FC */ NULL
, NULL
, NULL
, NULL
,
14049 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
14051 const char *mnemonic
;
14053 FETCH_DATA (the_info
, codep
+ 1);
14054 /* AMD 3DNow! instructions are specified by an opcode suffix in the
14055 place where an 8-bit immediate would normally go. ie. the last
14056 byte of the instruction. */
14057 obufp
= mnemonicendp
;
14058 mnemonic
= Suffix3DNow
[*codep
++ & 0xff];
14060 oappend (mnemonic
);
14063 /* Since a variable sized modrm/sib chunk is between the start
14064 of the opcode (0x0f0f) and the opcode suffix, we need to do
14065 all the modrm processing first, and don't know until now that
14066 we have a bad opcode. This necessitates some cleaning up. */
14067 op_out
[0][0] = '\0';
14068 op_out
[1][0] = '\0';
14071 mnemonicendp
= obufp
;
14074 static struct op simd_cmp_op
[] =
14076 { STRING_COMMA_LEN ("eq") },
14077 { STRING_COMMA_LEN ("lt") },
14078 { STRING_COMMA_LEN ("le") },
14079 { STRING_COMMA_LEN ("unord") },
14080 { STRING_COMMA_LEN ("neq") },
14081 { STRING_COMMA_LEN ("nlt") },
14082 { STRING_COMMA_LEN ("nle") },
14083 { STRING_COMMA_LEN ("ord") }
14087 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
14089 unsigned int cmp_type
;
14091 FETCH_DATA (the_info
, codep
+ 1);
14092 cmp_type
= *codep
++ & 0xff;
14093 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
))
14096 char *p
= mnemonicendp
- 2;
14100 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
14101 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
14105 /* We have a reserved extension byte. Output it directly. */
14106 scratchbuf
[0] = '$';
14107 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
14108 oappend (scratchbuf
+ intel_syntax
);
14109 scratchbuf
[0] = '\0';
14114 OP_Mwait (int bytemode ATTRIBUTE_UNUSED
,
14115 int sizeflag ATTRIBUTE_UNUSED
)
14117 /* mwait %eax,%ecx */
14120 const char **names
= (address_mode
== mode_64bit
14121 ? names64
: names32
);
14122 strcpy (op_out
[0], names
[0]);
14123 strcpy (op_out
[1], names
[1]);
14124 two_source_ops
= 1;
14126 /* Skip mod/rm byte. */
14132 OP_Monitor (int bytemode ATTRIBUTE_UNUSED
,
14133 int sizeflag ATTRIBUTE_UNUSED
)
14135 /* monitor %eax,%ecx,%edx" */
14138 const char **op1_names
;
14139 const char **names
= (address_mode
== mode_64bit
14140 ? names64
: names32
);
14142 if (!(prefixes
& PREFIX_ADDR
))
14143 op1_names
= (address_mode
== mode_16bit
14144 ? names16
: names
);
14147 /* Remove "addr16/addr32". */
14148 all_prefixes
[last_addr_prefix
] = 0;
14149 op1_names
= (address_mode
!= mode_32bit
14150 ? names32
: names16
);
14151 used_prefixes
|= PREFIX_ADDR
;
14153 strcpy (op_out
[0], op1_names
[0]);
14154 strcpy (op_out
[1], names
[1]);
14155 strcpy (op_out
[2], names
[2]);
14156 two_source_ops
= 1;
14158 /* Skip mod/rm byte. */
14166 /* Throw away prefixes and 1st. opcode byte. */
14167 codep
= insn_codep
+ 1;
14172 REP_Fixup (int bytemode
, int sizeflag
)
14174 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
14176 if (prefixes
& PREFIX_REPZ
)
14177 all_prefixes
[last_repz_prefix
] = REP_PREFIX
;
14184 OP_IMREG (bytemode
, sizeflag
);
14187 OP_ESreg (bytemode
, sizeflag
);
14190 OP_DSreg (bytemode
, sizeflag
);
14199 CMPXCHG8B_Fixup (int bytemode
, int sizeflag
)
14204 /* Change cmpxchg8b to cmpxchg16b. */
14205 char *p
= mnemonicendp
- 2;
14206 mnemonicendp
= stpcpy (p
, "16b");
14209 OP_M (bytemode
, sizeflag
);
14213 XMM_Fixup (int reg
, int sizeflag ATTRIBUTE_UNUSED
)
14215 const char **names
;
14219 switch (vex
.length
)
14233 oappend (names
[reg
]);
14237 CRC32_Fixup (int bytemode
, int sizeflag
)
14239 /* Add proper suffix to "crc32". */
14240 char *p
= mnemonicendp
;
14259 if (sizeflag
& DFLAG
)
14263 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14267 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14274 if (modrm
.mod
== 3)
14278 /* Skip mod/rm byte. */
14283 add
= (rex
& REX_B
) ? 8 : 0;
14284 if (bytemode
== b_mode
)
14288 oappend (names8rex
[modrm
.rm
+ add
]);
14290 oappend (names8
[modrm
.rm
+ add
]);
14296 oappend (names64
[modrm
.rm
+ add
]);
14297 else if ((prefixes
& PREFIX_DATA
))
14298 oappend (names16
[modrm
.rm
+ add
]);
14300 oappend (names32
[modrm
.rm
+ add
]);
14304 OP_E (bytemode
, sizeflag
);
14308 FXSAVE_Fixup (int bytemode
, int sizeflag
)
14310 /* Add proper suffix to "fxsave" and "fxrstor". */
14314 char *p
= mnemonicendp
;
14320 OP_M (bytemode
, sizeflag
);
14323 /* Display the destination register operand for instructions with
14327 OP_VEX (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
14329 const char **names
;
14337 switch (vex
.length
)
14369 oappend (names
[vex
.register_specifier
]);
14372 /* Get the VEX immediate byte without moving codep. */
14374 static unsigned char
14375 get_vex_imm8 (int sizeflag
, int opnum
)
14377 int bytes_before_imm
= 0;
14379 if (modrm
.mod
!= 3)
14381 /* There are SIB/displacement bytes. */
14382 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
14384 /* 32/64 bit address mode */
14385 int base
= modrm
.rm
;
14387 /* Check SIB byte. */
14390 FETCH_DATA (the_info
, codep
+ 1);
14392 /* When decoding the third source, don't increase
14393 bytes_before_imm as this has already been incremented
14394 by one in OP_E_memory while decoding the second
14397 bytes_before_imm
++;
14400 /* Don't increase bytes_before_imm when decoding the third source,
14401 it has already been incremented by OP_E_memory while decoding
14402 the second source operand. */
14408 /* When modrm.rm == 5 or modrm.rm == 4 and base in
14409 SIB == 5, there is a 4 byte displacement. */
14411 /* No displacement. */
14414 /* 4 byte displacement. */
14415 bytes_before_imm
+= 4;
14418 /* 1 byte displacement. */
14419 bytes_before_imm
++;
14426 /* 16 bit address mode */
14427 /* Don't increase bytes_before_imm when decoding the third source,
14428 it has already been incremented by OP_E_memory while decoding
14429 the second source operand. */
14435 /* When modrm.rm == 6, there is a 2 byte displacement. */
14437 /* No displacement. */
14440 /* 2 byte displacement. */
14441 bytes_before_imm
+= 2;
14444 /* 1 byte displacement: when decoding the third source,
14445 don't increase bytes_before_imm as this has already
14446 been incremented by one in OP_E_memory while decoding
14447 the second source operand. */
14449 bytes_before_imm
++;
14457 FETCH_DATA (the_info
, codep
+ bytes_before_imm
+ 1);
14458 return codep
[bytes_before_imm
];
14462 OP_EX_VexReg (int bytemode
, int sizeflag
, int reg
)
14464 const char **names
;
14466 if (reg
== -1 && modrm
.mod
!= 3)
14468 OP_E_memory (bytemode
, sizeflag
);
14480 else if (reg
> 7 && address_mode
!= mode_64bit
)
14484 switch (vex
.length
)
14495 oappend (names
[reg
]);
14499 OP_Vex_2src (int bytemode
, int sizeflag
)
14501 if (modrm
.mod
== 3)
14503 int reg
= modrm
.rm
;
14507 oappend (names_xmm
[reg
]);
14512 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
14514 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
14515 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14517 OP_E (bytemode
, sizeflag
);
14522 OP_Vex_2src_1 (int bytemode
, int sizeflag
)
14524 if (modrm
.mod
== 3)
14526 /* Skip mod/rm byte. */
14532 oappend (names_xmm
[vex
.register_specifier
]);
14534 OP_Vex_2src (bytemode
, sizeflag
);
14538 OP_Vex_2src_2 (int bytemode
, int sizeflag
)
14541 OP_Vex_2src (bytemode
, sizeflag
);
14543 oappend (names_xmm
[vex
.register_specifier
]);
14547 OP_EX_VexW (int bytemode
, int sizeflag
)
14555 /* Skip mod/rm byte. */
14560 reg
= get_vex_imm8 (sizeflag
, 0) >> 4;
14565 reg
= get_vex_imm8 (sizeflag
, 1) >> 4;
14568 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
14572 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED
,
14573 int sizeflag ATTRIBUTE_UNUSED
)
14575 /* Skip the immediate byte and check for invalid bits. */
14576 FETCH_DATA (the_info
, codep
+ 1);
14577 if (*codep
++ & 0xf)
14582 OP_REG_VexI4 (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
14585 const char **names
;
14587 FETCH_DATA (the_info
, codep
+ 1);
14590 if (bytemode
!= x_mode
)
14597 if (reg
> 7 && address_mode
!= mode_64bit
)
14600 switch (vex
.length
)
14611 oappend (names
[reg
]);
14615 OP_XMM_VexW (int bytemode
, int sizeflag
)
14617 /* Turn off the REX.W bit since it is used for swapping operands
14620 OP_XMM (bytemode
, sizeflag
);
14624 OP_EX_Vex (int bytemode
, int sizeflag
)
14626 if (modrm
.mod
!= 3)
14628 if (vex
.register_specifier
!= 0)
14632 OP_EX (bytemode
, sizeflag
);
14636 OP_XMM_Vex (int bytemode
, int sizeflag
)
14638 if (modrm
.mod
!= 3)
14640 if (vex
.register_specifier
!= 0)
14644 OP_XMM (bytemode
, sizeflag
);
14648 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
14650 switch (vex
.length
)
14653 mnemonicendp
= stpcpy (obuf
, "vzeroupper");
14656 mnemonicendp
= stpcpy (obuf
, "vzeroall");
14663 static struct op vex_cmp_op
[] =
14665 { STRING_COMMA_LEN ("eq") },
14666 { STRING_COMMA_LEN ("lt") },
14667 { STRING_COMMA_LEN ("le") },
14668 { STRING_COMMA_LEN ("unord") },
14669 { STRING_COMMA_LEN ("neq") },
14670 { STRING_COMMA_LEN ("nlt") },
14671 { STRING_COMMA_LEN ("nle") },
14672 { STRING_COMMA_LEN ("ord") },
14673 { STRING_COMMA_LEN ("eq_uq") },
14674 { STRING_COMMA_LEN ("nge") },
14675 { STRING_COMMA_LEN ("ngt") },
14676 { STRING_COMMA_LEN ("false") },
14677 { STRING_COMMA_LEN ("neq_oq") },
14678 { STRING_COMMA_LEN ("ge") },
14679 { STRING_COMMA_LEN ("gt") },
14680 { STRING_COMMA_LEN ("true") },
14681 { STRING_COMMA_LEN ("eq_os") },
14682 { STRING_COMMA_LEN ("lt_oq") },
14683 { STRING_COMMA_LEN ("le_oq") },
14684 { STRING_COMMA_LEN ("unord_s") },
14685 { STRING_COMMA_LEN ("neq_us") },
14686 { STRING_COMMA_LEN ("nlt_uq") },
14687 { STRING_COMMA_LEN ("nle_uq") },
14688 { STRING_COMMA_LEN ("ord_s") },
14689 { STRING_COMMA_LEN ("eq_us") },
14690 { STRING_COMMA_LEN ("nge_uq") },
14691 { STRING_COMMA_LEN ("ngt_uq") },
14692 { STRING_COMMA_LEN ("false_os") },
14693 { STRING_COMMA_LEN ("neq_os") },
14694 { STRING_COMMA_LEN ("ge_oq") },
14695 { STRING_COMMA_LEN ("gt_oq") },
14696 { STRING_COMMA_LEN ("true_us") },
14700 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
14702 unsigned int cmp_type
;
14704 FETCH_DATA (the_info
, codep
+ 1);
14705 cmp_type
= *codep
++ & 0xff;
14706 if (cmp_type
< ARRAY_SIZE (vex_cmp_op
))
14709 char *p
= mnemonicendp
- 2;
14713 sprintf (p
, "%s%s", vex_cmp_op
[cmp_type
].name
, suffix
);
14714 mnemonicendp
+= vex_cmp_op
[cmp_type
].len
;
14718 /* We have a reserved extension byte. Output it directly. */
14719 scratchbuf
[0] = '$';
14720 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
14721 oappend (scratchbuf
+ intel_syntax
);
14722 scratchbuf
[0] = '\0';
14726 static const struct op pclmul_op
[] =
14728 { STRING_COMMA_LEN ("lql") },
14729 { STRING_COMMA_LEN ("hql") },
14730 { STRING_COMMA_LEN ("lqh") },
14731 { STRING_COMMA_LEN ("hqh") }
14735 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED
,
14736 int sizeflag ATTRIBUTE_UNUSED
)
14738 unsigned int pclmul_type
;
14740 FETCH_DATA (the_info
, codep
+ 1);
14741 pclmul_type
= *codep
++ & 0xff;
14742 switch (pclmul_type
)
14753 if (pclmul_type
< ARRAY_SIZE (pclmul_op
))
14756 char *p
= mnemonicendp
- 3;
14761 sprintf (p
, "%s%s", pclmul_op
[pclmul_type
].name
, suffix
);
14762 mnemonicendp
+= pclmul_op
[pclmul_type
].len
;
14766 /* We have a reserved extension byte. Output it directly. */
14767 scratchbuf
[0] = '$';
14768 print_operand_value (scratchbuf
+ 1, 1, pclmul_type
);
14769 oappend (scratchbuf
+ intel_syntax
);
14770 scratchbuf
[0] = '\0';
14775 MOVBE_Fixup (int bytemode
, int sizeflag
)
14777 /* Add proper suffix to "movbe". */
14778 char *p
= mnemonicendp
;
14787 if (sizeflag
& SUFFIX_ALWAYS
)
14793 if (sizeflag
& DFLAG
)
14797 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14802 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14809 OP_M (bytemode
, sizeflag
);
14813 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
14816 const char **names
;
14818 /* Skip mod/rm byte. */
14824 else if (vex
.length
== 256)
14834 oappend (names
[reg
]);
14838 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
14840 const char **names
;
14844 else if (vex
.length
== 256)
14849 oappend (names
[vex
.register_specifier
]);
14853 OP_LWP_I (int bytemode ATTRIBUTE_UNUSED
, int sizeflag
)
14855 if (vex
.w
|| vex
.length
== 256)
14856 OP_I (q_mode
, sizeflag
);
14858 OP_I (w_mode
, sizeflag
);