opcodes/ppc-opc.c

   1 /* ppc-opc.c -- PowerPC opcode list
   2    Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2004,
   3    2005 Free Software Foundation, Inc.
   4    Written by Ian Lance Taylor, Cygnus Support
   5
   6    This file is part of GDB, GAS, and the GNU binutils.
   7
   8    GDB, GAS, and the GNU binutils are free software; you can redistribute
   9    them and/or modify them under the terms of the GNU General Public
  10    License as published by the Free Software Foundation; either version
  11    2, or (at your option) any later version.
  12
  13    GDB, GAS, and the GNU binutils are distributed in the hope that they
  14    will be useful, but WITHOUT ANY WARRANTY; without even the implied
  15    warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
  16    the GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this file; see the file COPYING.  If not, write to the Free
  20    Software Foundation, 59 Temple Place - Suite 330, Boston, MA
  21    02111-1307, USA.  */
  22
  23 #include <stdio.h>
  24 #include "sysdep.h"
  25 #include "opcode/ppc.h"
  26 #include "opintl.h"
  27
  28 /* This file holds the PowerPC opcode table.  The opcode table
  29    includes almost all of the extended instruction mnemonics.  This
  30    permits the disassembler to use them, and simplifies the assembler
  31    logic, at the cost of increasing the table size.  The table is
  32    strictly constant data, so the compiler should be able to put it in
  33    the .text section.
  34
  35    This file also holds the operand table.  All knowledge about
  36    inserting operands into instructions and vice-versa is kept in this
  37    file.  */
  38 \f
  39 /* Local insertion and extraction functions.  */
  40
  41 static unsigned long insert_bat (unsigned long, long, int, const char **);
  42 static long extract_bat (unsigned long, int, int *);
  43 static unsigned long insert_bba (unsigned long, long, int, const char **);
  44 static long extract_bba (unsigned long, int, int *);
  45 static unsigned long insert_bd (unsigned long, long, int, const char **);
  46 static long extract_bd (unsigned long, int, int *);
  47 static unsigned long insert_bdm (unsigned long, long, int, const char **);
  48 static long extract_bdm (unsigned long, int, int *);
  49 static unsigned long insert_bdp (unsigned long, long, int, const char **);
  50 static long extract_bdp (unsigned long, int, int *);
  51 static unsigned long insert_bo (unsigned long, long, int, const char **);
  52 static long extract_bo (unsigned long, int, int *);
  53 static unsigned long insert_boe (unsigned long, long, int, const char **);
  54 static long extract_boe (unsigned long, int, int *);
  55 static unsigned long insert_dq (unsigned long, long, int, const char **);
  56 static long extract_dq (unsigned long, int, int *);
  57 static unsigned long insert_ds (unsigned long, long, int, const char **);
  58 static long extract_ds (unsigned long, int, int *);
  59 static unsigned long insert_de (unsigned long, long, int, const char **);
  60 static long extract_de (unsigned long, int, int *);
  61 static unsigned long insert_des (unsigned long, long, int, const char **);
  62 static long extract_des (unsigned long, int, int *);
  63 static unsigned long insert_fxm (unsigned long, long, int, const char **);
  64 static long extract_fxm (unsigned long, int, int *);
  65 static unsigned long insert_li (unsigned long, long, int, const char **);
  66 static long extract_li (unsigned long, int, int *);
  67 static unsigned long insert_mbe (unsigned long, long, int, const char **);
  68 static long extract_mbe (unsigned long, int, int *);
  69 static unsigned long insert_mb6 (unsigned long, long, int, const char **);
  70 static long extract_mb6 (unsigned long, int, int *);
  71 static unsigned long insert_nb (unsigned long, long, int, const char **);
  72 static long extract_nb (unsigned long, int, int *);
  73 static unsigned long insert_nsi (unsigned long, long, int, const char **);
  74 static long extract_nsi (unsigned long, int, int *);
  75 static unsigned long insert_ral (unsigned long, long, int, const char **);
  76 static unsigned long insert_ram (unsigned long, long, int, const char **);
  77 static unsigned long insert_raq (unsigned long, long, int, const char **);
  78 static unsigned long insert_ras (unsigned long, long, int, const char **);
  79 static unsigned long insert_rbs (unsigned long, long, int, const char **);
  80 static long extract_rbs (unsigned long, int, int *);
  81 static unsigned long insert_rsq (unsigned long, long, int, const char **);
  82 static unsigned long insert_rtq (unsigned long, long, int, const char **);
  83 static unsigned long insert_sh6 (unsigned long, long, int, const char **);
  84 static long extract_sh6 (unsigned long, int, int *);
  85 static unsigned long insert_spr (unsigned long, long, int, const char **);
  86 static long extract_spr (unsigned long, int, int *);
  87 static unsigned long insert_sprg (unsigned long, long, int, const char **);
  88 static long extract_sprg (unsigned long, int, int *);
  89 static unsigned long insert_tbr (unsigned long, long, int, const char **);
  90 static long extract_tbr (unsigned long, int, int *);
  91 static unsigned long insert_ev2 (unsigned long, long, int, const char **);
  92 static long extract_ev2 (unsigned long, int, int *);
  93 static unsigned long insert_ev4 (unsigned long, long, int, const char **);
  94 static long extract_ev4 (unsigned long, int, int *);
  95 static unsigned long insert_ev8 (unsigned long, long, int, const char **);
  96 static long extract_ev8 (unsigned long, int, int *);
  97 \f
  98 /* The operands table.
  99
 100    The fields are bits, shift, insert, extract, flags.
 101
 102    We used to put parens around the various additions, like the one
 103    for BA just below.  However, that caused trouble with feeble
 104    compilers with a limit on depth of a parenthesized expression, like
 105    (reportedly) the compiler in Microsoft Developer Studio 5.  So we
 106    omit the parens, since the macros are never used in a context where
 107    the addition will be ambiguous.  */
 108
 109 const struct powerpc_operand powerpc_operands[] =
 110 {
 111   /* The zero index is used to indicate the end of the list of
 112      operands.  */
 113 #define UNUSED 0
 114   { 0, 0, NULL, NULL, 0 },
 115
 116   /* The BA field in an XL form instruction.  */
 117 #define BA UNUSED + 1
 118 #define BA_MASK (0x1f << 16)
 119   { 5, 16, NULL, NULL, PPC_OPERAND_CR },
 120
 121   /* The BA field in an XL form instruction when it must be the same
 122      as the BT field in the same instruction.  */
 123 #define BAT BA + 1
 124   { 5, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
 125
 126   /* The BB field in an XL form instruction.  */
 127 #define BB BAT + 1
 128 #define BB_MASK (0x1f << 11)
 129   { 5, 11, NULL, NULL, PPC_OPERAND_CR },
 130
 131   /* The BB field in an XL form instruction when it must be the same
 132      as the BA field in the same instruction.  */
 133 #define BBA BB + 1
 134   { 5, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },
 135
 136   /* The BD field in a B form instruction.  The lower two bits are
 137      forced to zero.  */
 138 #define BD BBA + 1
 139   { 16, 0, insert_bd, extract_bd, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 140
 141   /* The BD field in a B form instruction when absolute addressing is
 142      used.  */
 143 #define BDA BD + 1
 144   { 16, 0, insert_bd, extract_bd, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
 145
 146   /* The BD field in a B form instruction when the - modifier is used.
 147      This sets the y bit of the BO field appropriately.  */
 148 #define BDM BDA + 1
 149   { 16, 0, insert_bdm, extract_bdm,
 150       PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 151
 152   /* The BD field in a B form instruction when the - modifier is used
 153      and absolute address is used.  */
 154 #define BDMA BDM + 1
 155   { 16, 0, insert_bdm, extract_bdm,
 156       PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
 157
 158   /* The BD field in a B form instruction when the + modifier is used.
 159      This sets the y bit of the BO field appropriately.  */
 160 #define BDP BDMA + 1
 161   { 16, 0, insert_bdp, extract_bdp,
 162       PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 163
 164   /* The BD field in a B form instruction when the + modifier is used
 165      and absolute addressing is used.  */
 166 #define BDPA BDP + 1
 167   { 16, 0, insert_bdp, extract_bdp,
 168       PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
 169
 170   /* The BF field in an X or XL form instruction.  */
 171 #define BF BDPA + 1
 172   { 3, 23, NULL, NULL, PPC_OPERAND_CR },
 173
 174   /* An optional BF field.  This is used for comparison instructions,
 175      in which an omitted BF field is taken as zero.  */
 176 #define OBF BF + 1
 177   { 3, 23, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
 178
 179   /* The BFA field in an X or XL form instruction.  */
 180 #define BFA OBF + 1
 181   { 3, 18, NULL, NULL, PPC_OPERAND_CR },
 182
 183   /* The BI field in a B form or XL form instruction.  */
 184 #define BI BFA + 1
 185 #define BI_MASK (0x1f << 16)
 186   { 5, 16, NULL, NULL, PPC_OPERAND_CR },
 187
 188   /* The BO field in a B form instruction.  Certain values are
 189      illegal.  */
 190 #define BO BI + 1
 191 #define BO_MASK (0x1f << 21)
 192   { 5, 21, insert_bo, extract_bo, 0 },
 193
 194   /* The BO field in a B form instruction when the + or - modifier is
 195      used.  This is like the BO field, but it must be even.  */
 196 #define BOE BO + 1
 197   { 5, 21, insert_boe, extract_boe, 0 },
 198
 199 #define BH BOE + 1
 200   { 2, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
 201
 202   /* The BT field in an X or XL form instruction.  */
 203 #define BT BH + 1
 204   { 5, 21, NULL, NULL, PPC_OPERAND_CR },
 205
 206   /* The condition register number portion of the BI field in a B form
 207      or XL form instruction.  This is used for the extended
 208      conditional branch mnemonics, which set the lower two bits of the
 209      BI field.  This field is optional.  */
 210 #define CR BT + 1
 211   { 3, 18, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
 212
 213   /* The CRB field in an X form instruction.  */
 214 #define CRB CR + 1
 215   { 5, 6, NULL, NULL, 0 },
 216
 217   /* The CRFD field in an X form instruction.  */
 218 #define CRFD CRB + 1
 219   { 3, 23, NULL, NULL, PPC_OPERAND_CR },
 220
 221   /* The CRFS field in an X form instruction.  */
 222 #define CRFS CRFD + 1
 223   { 3, 0, NULL, NULL, PPC_OPERAND_CR },
 224
 225   /* The CT field in an X form instruction.  */
 226 #define CT CRFS + 1
 227   { 5, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
 228
 229   /* The D field in a D form instruction.  This is a displacement off
 230      a register, and implies that the next operand is a register in
 231      parentheses.  */
 232 #define D CT + 1
 233   { 16, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
 234
 235   /* The DE field in a DE form instruction.  This is like D, but is 12
 236      bits only.  */
 237 #define DE D + 1
 238   { 14, 0, insert_de, extract_de, PPC_OPERAND_PARENS },
 239
 240   /* The DES field in a DES form instruction.  This is like DS, but is 14
 241      bits only (12 stored.)  */
 242 #define DES DE + 1
 243   { 14, 0, insert_des, extract_des, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
 244
 245   /* The DQ field in a DQ form instruction.  This is like D, but the
 246      lower four bits are forced to zero. */
 247 #define DQ DES + 1
 248   { 16, 0, insert_dq, extract_dq,
 249       PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ },
 250
 251   /* The DS field in a DS form instruction.  This is like D, but the
 252      lower two bits are forced to zero.  */
 253 #define DS DQ + 1
 254   { 16, 0, insert_ds, extract_ds,
 255       PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },
 256
 257   /* The E field in a wrteei instruction.  */
 258 #define E DS + 1
 259   { 1, 15, NULL, NULL, 0 },
 260
 261   /* The FL1 field in a POWER SC form instruction.  */
 262 #define FL1 E + 1
 263   { 4, 12, NULL, NULL, 0 },
 264
 265   /* The FL2 field in a POWER SC form instruction.  */
 266 #define FL2 FL1 + 1
 267   { 3, 2, NULL, NULL, 0 },
 268
 269   /* The FLM field in an XFL form instruction.  */
 270 #define FLM FL2 + 1
 271   { 8, 17, NULL, NULL, 0 },
 272
 273   /* The FRA field in an X or A form instruction.  */
 274 #define FRA FLM + 1
 275 #define FRA_MASK (0x1f << 16)
 276   { 5, 16, NULL, NULL, PPC_OPERAND_FPR },
 277
 278   /* The FRB field in an X or A form instruction.  */
 279 #define FRB FRA + 1
 280 #define FRB_MASK (0x1f << 11)
 281   { 5, 11, NULL, NULL, PPC_OPERAND_FPR },
 282
 283   /* The FRC field in an A form instruction.  */
 284 #define FRC FRB + 1
 285 #define FRC_MASK (0x1f << 6)
 286   { 5, 6, NULL, NULL, PPC_OPERAND_FPR },
 287
 288   /* The FRS field in an X form instruction or the FRT field in a D, X
 289      or A form instruction.  */
 290 #define FRS FRC + 1
 291 #define FRT FRS
 292   { 5, 21, NULL, NULL, PPC_OPERAND_FPR },
 293
 294   /* The FXM field in an XFX instruction.  */
 295 #define FXM FRS + 1
 296 #define FXM_MASK (0xff << 12)
 297   { 8, 12, insert_fxm, extract_fxm, 0 },
 298
 299   /* Power4 version for mfcr.  */
 300 #define FXM4 FXM + 1
 301   { 8, 12, insert_fxm, extract_fxm, PPC_OPERAND_OPTIONAL },
 302
 303   /* The L field in a D or X form instruction.  */
 304 #define L FXM4 + 1
 305   { 1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
 306
 307   /* The LEV field in a POWER SC form instruction.  */
 308 #define LEV L + 1
 309   { 7, 5, NULL, NULL, 0 },
 310
 311   /* The LI field in an I form instruction.  The lower two bits are
 312      forced to zero.  */
 313 #define LI LEV + 1
 314   { 26, 0, insert_li, extract_li, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 315
 316   /* The LI field in an I form instruction when used as an absolute
 317      address.  */
 318 #define LIA LI + 1
 319   { 26, 0, insert_li, extract_li, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
 320
 321   /* The LS field in an X (sync) form instruction.  */
 322 #define LS LIA + 1
 323   { 2, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
 324
 325   /* The MB field in an M form instruction.  */
 326 #define MB LS + 1
 327 #define MB_MASK (0x1f << 6)
 328   { 5, 6, NULL, NULL, 0 },
 329
 330   /* The ME field in an M form instruction.  */
 331 #define ME MB + 1
 332 #define ME_MASK (0x1f << 1)
 333   { 5, 1, NULL, NULL, 0 },
 334
 335   /* The MB and ME fields in an M form instruction expressed a single
 336      operand which is a bitmask indicating which bits to select.  This
 337      is a two operand form using PPC_OPERAND_NEXT.  See the
 338      description in opcode/ppc.h for what this means.  */
 339 #define MBE ME + 1
 340   { 5, 6, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
 341   { 32, 0, insert_mbe, extract_mbe, 0 },
 342
 343   /* The MB or ME field in an MD or MDS form instruction.  The high
 344      bit is wrapped to the low end.  */
 345 #define MB6 MBE + 2
 346 #define ME6 MB6
 347 #define MB6_MASK (0x3f << 5)
 348   { 6, 5, insert_mb6, extract_mb6, 0 },
 349
 350   /* The MO field in an mbar instruction.  */
 351 #define MO MB6 + 1
 352   { 5, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
 353
 354   /* The NB field in an X form instruction.  The value 32 is stored as
 355      0.  */
 356 #define NB MO + 1
 357   { 6, 11, insert_nb, extract_nb, 0 },
 358
 359   /* The NSI field in a D form instruction.  This is the same as the
 360      SI field, only negated.  */
 361 #define NSI NB + 1
 362   { 16, 0, insert_nsi, extract_nsi,
 363       PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
 364
 365   /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction.  */
 366 #define RA NSI + 1
 367 #define RA_MASK (0x1f << 16)
 368   { 5, 16, NULL, NULL, PPC_OPERAND_GPR },
 369
 370   /* As above, but 0 in the RA field means zero, not r0.  */
 371 #define RA0 RA + 1
 372   { 5, 16, NULL, NULL, PPC_OPERAND_GPR_0 },
 373
 374   /* The RA field in the DQ form lq instruction, which has special
 375      value restrictions.  */
 376 #define RAQ RA0 + 1
 377   { 5, 16, insert_raq, NULL, PPC_OPERAND_GPR_0 },
 378
 379   /* The RA field in a D or X form instruction which is an updating
 380      load, which means that the RA field may not be zero and may not
 381      equal the RT field.  */
 382 #define RAL RAQ + 1
 383   { 5, 16, insert_ral, NULL, PPC_OPERAND_GPR_0 },
 384
 385   /* The RA field in an lmw instruction, which has special value
 386      restrictions.  */
 387 #define RAM RAL + 1
 388   { 5, 16, insert_ram, NULL, PPC_OPERAND_GPR_0 },
 389
 390   /* The RA field in a D or X form instruction which is an updating
 391      store or an updating floating point load, which means that the RA
 392      field may not be zero.  */
 393 #define RAS RAM + 1
 394   { 5, 16, insert_ras, NULL, PPC_OPERAND_GPR_0 },
 395
 396   /* The RA field of the tlbwe instruction, which is optional.  */
 397 #define RAOPT RAS + 1
 398   { 5, 16, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
 399
 400   /* The RB field in an X, XO, M, or MDS form instruction.  */
 401 #define RB RAOPT + 1
 402 #define RB_MASK (0x1f << 11)
 403   { 5, 11, NULL, NULL, PPC_OPERAND_GPR },
 404
 405   /* The RB field in an X form instruction when it must be the same as
 406      the RS field in the instruction.  This is used for extended
 407      mnemonics like mr.  */
 408 #define RBS RB + 1
 409   { 5, 1, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },
 410
 411   /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
 412      instruction or the RT field in a D, DS, X, XFX or XO form
 413      instruction.  */
 414 #define RS RBS + 1
 415 #define RT RS
 416 #define RT_MASK (0x1f << 21)
 417   { 5, 21, NULL, NULL, PPC_OPERAND_GPR },
 418
 419   /* The RS field of the DS form stq instruction, which has special
 420      value restrictions.  */
 421 #define RSQ RS + 1
 422   { 5, 21, insert_rsq, NULL, PPC_OPERAND_GPR_0 },
 423
 424   /* The RT field of the DQ form lq instruction, which has special
 425      value restrictions.  */
 426 #define RTQ RSQ + 1
 427   { 5, 21, insert_rtq, NULL, PPC_OPERAND_GPR_0 },
 428
 429   /* The RS field of the tlbwe instruction, which is optional.  */
 430 #define RSO RTQ + 1
 431 #define RTO RSO
 432   { 5, 21, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
 433
 434   /* The SH field in an X or M form instruction.  */
 435 #define SH RSO + 1
 436 #define SH_MASK (0x1f << 11)
 437   { 5, 11, NULL, NULL, 0 },
 438
 439   /* The SH field in an MD form instruction.  This is split.  */
 440 #define SH6 SH + 1
 441 #define SH6_MASK ((0x1f << 11) | (1 << 1))
 442   { 6, 1, insert_sh6, extract_sh6, 0 },
 443
 444   /* The SH field of the tlbwe instruction, which is optional.  */
 445 #define SHO SH6 + 1
 446   { 5, 11,NULL, NULL, PPC_OPERAND_OPTIONAL },
 447
 448   /* The SI field in a D form instruction.  */
 449 #define SI SHO + 1
 450   { 16, 0, NULL, NULL, PPC_OPERAND_SIGNED },
 451
 452   /* The SI field in a D form instruction when we accept a wide range
 453      of positive values.  */
 454 #define SISIGNOPT SI + 1
 455   { 16, 0, NULL, NULL, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
 456
 457   /* The SPR field in an XFX form instruction.  This is flipped--the
 458      lower 5 bits are stored in the upper 5 and vice- versa.  */
 459 #define SPR SISIGNOPT + 1
 460 #define PMR SPR
 461 #define SPR_MASK (0x3ff << 11)
 462   { 10, 11, insert_spr, extract_spr, 0 },
 463
 464   /* The BAT index number in an XFX form m[ft]ibat[lu] instruction.  */
 465 #define SPRBAT SPR + 1
 466 #define SPRBAT_MASK (0x3 << 17)
 467   { 2, 17, NULL, NULL, 0 },
 468
 469   /* The SPRG register number in an XFX form m[ft]sprg instruction.  */
 470 #define SPRG SPRBAT + 1
 471   { 5, 16, insert_sprg, extract_sprg, 0 },
 472
 473   /* The SR field in an X form instruction.  */
 474 #define SR SPRG + 1
 475   { 4, 16, NULL, NULL, 0 },
 476
 477   /* The STRM field in an X AltiVec form instruction.  */
 478 #define STRM SR + 1
 479 #define STRM_MASK (0x3 << 21)
 480   { 2, 21, NULL, NULL, 0 },
 481
 482   /* The SV field in a POWER SC form instruction.  */
 483 #define SV STRM + 1
 484   { 14, 2, NULL, NULL, 0 },
 485
 486   /* The TBR field in an XFX form instruction.  This is like the SPR
 487      field, but it is optional.  */
 488 #define TBR SV + 1
 489   { 10, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL },
 490
 491   /* The TO field in a D or X form instruction.  */
 492 #define TO TBR + 1
 493 #define TO_MASK (0x1f << 21)
 494   { 5, 21, NULL, NULL, 0 },
 495
 496   /* The U field in an X form instruction.  */
 497 #define U TO + 1
 498   { 4, 12, NULL, NULL, 0 },
 499
 500   /* The UI field in a D form instruction.  */
 501 #define UI U + 1
 502   { 16, 0, NULL, NULL, 0 },
 503
 504   /* The VA field in a VA, VX or VXR form instruction.  */
 505 #define VA UI + 1
 506 #define VA_MASK (0x1f << 16)
 507   { 5, 16, NULL, NULL, PPC_OPERAND_VR },
 508
 509   /* The VB field in a VA, VX or VXR form instruction.  */
 510 #define VB VA + 1
 511 #define VB_MASK (0x1f << 11)
 512   { 5, 11, NULL, NULL, PPC_OPERAND_VR },
 513
 514   /* The VC field in a VA form instruction.  */
 515 #define VC VB + 1
 516 #define VC_MASK (0x1f << 6)
 517   { 5, 6, NULL, NULL, PPC_OPERAND_VR },
 518
 519   /* The VD or VS field in a VA, VX, VXR or X form instruction.  */
 520 #define VD VC + 1
 521 #define VS VD
 522 #define VD_MASK (0x1f << 21)
 523   { 5, 21, NULL, NULL, PPC_OPERAND_VR },
 524
 525   /* The SIMM field in a VX form instruction.  */
 526 #define SIMM VD + 1
 527   { 5, 16, NULL, NULL, PPC_OPERAND_SIGNED},
 528
 529   /* The UIMM field in a VX form instruction.  */
 530 #define UIMM SIMM + 1
 531   { 5, 16, NULL, NULL, 0 },
 532
 533   /* The SHB field in a VA form instruction.  */
 534 #define SHB UIMM + 1
 535   { 4, 6, NULL, NULL, 0 },
 536
 537   /* The other UIMM field in a EVX form instruction.  */
 538 #define EVUIMM SHB + 1
 539   { 5, 11, NULL, NULL, 0 },
 540
 541   /* The other UIMM field in a half word EVX form instruction.  */
 542 #define EVUIMM_2 EVUIMM + 1
 543   { 32, 11, insert_ev2, extract_ev2, PPC_OPERAND_PARENS },
 544
 545   /* The other UIMM field in a word EVX form instruction.  */
 546 #define EVUIMM_4 EVUIMM_2 + 1
 547   { 32, 11, insert_ev4, extract_ev4, PPC_OPERAND_PARENS },
 548
 549   /* The other UIMM field in a double EVX form instruction.  */
 550 #define EVUIMM_8 EVUIMM_4 + 1
 551   { 32, 11, insert_ev8, extract_ev8, PPC_OPERAND_PARENS },
 552
 553   /* The WS field.  */
 554 #define WS EVUIMM_8 + 1
 555 #define WS_MASK (0x7 << 11)
 556   { 3, 11, NULL, NULL, 0 },
 557
 558   /* The L field in an mtmsrd instruction */
 559 #define MTMSRD_L WS + 1
 560   { 1, 16, NULL, NULL, PPC_OPERAND_OPTIONAL },
 561
 562 };
 563
 564 /* The functions used to insert and extract complicated operands.  */
 565
 566 /* The BA field in an XL form instruction when it must be the same as
 567    the BT field in the same instruction.  This operand is marked FAKE.
 568    The insertion function just copies the BT field into the BA field,
 569    and the extraction function just checks that the fields are the
 570    same.  */
 571
 572 static unsigned long
 573 insert_bat (unsigned long insn,
 574             long value ATTRIBUTE_UNUSED,
 575             int dialect ATTRIBUTE_UNUSED,
 576             const char **errmsg ATTRIBUTE_UNUSED)
 577 {
 578   return insn | (((insn >> 21) & 0x1f) << 16);
 579 }
 580
 581 static long
 582 extract_bat (unsigned long insn,
 583              int dialect ATTRIBUTE_UNUSED,
 584              int *invalid)
 585 {
 586   if (((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
 587     *invalid = 1;
 588   return 0;
 589 }
 590
 591 /* The BB field in an XL form instruction when it must be the same as
 592    the BA field in the same instruction.  This operand is marked FAKE.
 593    The insertion function just copies the BA field into the BB field,
 594    and the extraction function just checks that the fields are the
 595    same.  */
 596
 597 static unsigned long
 598 insert_bba (unsigned long insn,
 599             long value ATTRIBUTE_UNUSED,
 600             int dialect ATTRIBUTE_UNUSED,
 601             const char **errmsg ATTRIBUTE_UNUSED)
 602 {
 603   return insn | (((insn >> 16) & 0x1f) << 11);
 604 }
 605
 606 static long
 607 extract_bba (unsigned long insn,
 608              int dialect ATTRIBUTE_UNUSED,
 609              int *invalid)
 610 {
 611   if (((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
 612     *invalid = 1;
 613   return 0;
 614 }
 615
 616 /* The BD field in a B form instruction.  The lower two bits are
 617    forced to zero.  */
 618
 619 static unsigned long
 620 insert_bd (unsigned long insn,
 621            long value,
 622            int dialect ATTRIBUTE_UNUSED,
 623            const char **errmsg ATTRIBUTE_UNUSED)
 624 {
 625   return insn | (value & 0xfffc);
 626 }
 627
 628 static long
 629 extract_bd (unsigned long insn,
 630             int dialect ATTRIBUTE_UNUSED,
 631             int *invalid ATTRIBUTE_UNUSED)
 632 {
 633   return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
 634 }
 635
 636 /* The BD field in a B form instruction when the - modifier is used.
 637    This modifier means that the branch is not expected to be taken.
 638    For chips built to versions of the architecture prior to version 2
 639    (ie. not Power4 compatible), we set the y bit of the BO field to 1
 640    if the offset is negative.  When extracting, we require that the y
 641    bit be 1 and that the offset be positive, since if the y bit is 0
 642    we just want to print the normal form of the instruction.
 643    Power4 compatible targets use two bits, "a", and "t", instead of
 644    the "y" bit.  "at" == 00 => no hint, "at" == 01 => unpredictable,
 645    "at" == 10 => not taken, "at" == 11 => taken.  The "t" bit is 00001
 646    in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000
 647    for branch on CTR.  We only handle the taken/not-taken hint here.  */
 648
 649 static unsigned long
 650 insert_bdm (unsigned long insn,
 651             long value,
 652             int dialect,
 653             const char **errmsg ATTRIBUTE_UNUSED)
 654 {
 655   if ((dialect & PPC_OPCODE_POWER4) == 0)
 656     {
 657       if ((value & 0x8000) != 0)
 658         insn |= 1 << 21;
 659     }
 660   else
 661     {
 662       if ((insn & (0x14 << 21)) == (0x04 << 21))
 663         insn |= 0x02 << 21;
 664       else if ((insn & (0x14 << 21)) == (0x10 << 21))
 665         insn |= 0x08 << 21;
 666     }
 667   return insn | (value & 0xfffc);
 668 }
 669
 670 static long
 671 extract_bdm (unsigned long insn,
 672              int dialect,
 673              int *invalid)
 674 {
 675   if ((dialect & PPC_OPCODE_POWER4) == 0)
 676     {
 677       if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0))
 678         *invalid = 1;
 679     }
 680   else
 681     {
 682       if ((insn & (0x17 << 21)) != (0x06 << 21)
 683           && (insn & (0x1d << 21)) != (0x18 << 21))
 684         *invalid = 1;
 685     }
 686
 687   return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
 688 }
 689
 690 /* The BD field in a B form instruction when the + modifier is used.
 691    This is like BDM, above, except that the branch is expected to be
 692    taken.  */
 693
 694 static unsigned long
 695 insert_bdp (unsigned long insn,
 696             long value,
 697             int dialect,
 698             const char **errmsg ATTRIBUTE_UNUSED)
 699 {
 700   if ((dialect & PPC_OPCODE_POWER4) == 0)
 701     {
 702       if ((value & 0x8000) == 0)
 703         insn |= 1 << 21;
 704     }
 705   else
 706     {
 707       if ((insn & (0x14 << 21)) == (0x04 << 21))
 708         insn |= 0x03 << 21;
 709       else if ((insn & (0x14 << 21)) == (0x10 << 21))
 710         insn |= 0x09 << 21;
 711     }
 712   return insn | (value & 0xfffc);
 713 }
 714
 715 static long
 716 extract_bdp (unsigned long insn,
 717              int dialect,
 718              int *invalid)
 719 {
 720   if ((dialect & PPC_OPCODE_POWER4) == 0)
 721     {
 722       if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0))
 723         *invalid = 1;
 724     }
 725   else
 726     {
 727       if ((insn & (0x17 << 21)) != (0x07 << 21)
 728           && (insn & (0x1d << 21)) != (0x19 << 21))
 729         *invalid = 1;
 730     }
 731
 732   return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
 733 }
 734
 735 /* Check for legal values of a BO field.  */
 736
 737 static int
 738 valid_bo (long value, int dialect)
 739 {
 740   if ((dialect & PPC_OPCODE_POWER4) == 0)
 741     {
 742       /* Certain encodings have bits that are required to be zero.
 743          These are (z must be zero, y may be anything):
 744              001zy
 745              011zy
 746              1z00y
 747              1z01y
 748              1z1zz
 749       */
 750       switch (value & 0x14)
 751         {
 752         default:
 753         case 0:
 754           return 1;
 755         case 0x4:
 756           return (value & 0x2) == 0;
 757         case 0x10:
 758           return (value & 0x8) == 0;
 759         case 0x14:
 760           return value == 0x14;
 761         }
 762     }
 763   else
 764     {
 765       /* Certain encodings have bits that are required to be zero.
 766          These are (z must be zero, a & t may be anything):
 767              0000z
 768              0001z
 769              0100z
 770              0101z
 771              001at
 772              011at
 773              1a00t
 774              1a01t
 775              1z1zz
 776       */
 777       if ((value & 0x14) == 0)
 778         return (value & 0x1) == 0;
 779       else if ((value & 0x14) == 0x14)
 780         return value == 0x14;
 781       else
 782         return 1;
 783     }
 784 }
 785
 786 /* The BO field in a B form instruction.  Warn about attempts to set
 787    the field to an illegal value.  */
 788
 789 static unsigned long
 790 insert_bo (unsigned long insn,
 791            long value,
 792            int dialect,
 793            const char **errmsg)
 794 {
 795   if (!valid_bo (value, dialect))
 796     *errmsg = _("invalid conditional option");
 797   return insn | ((value & 0x1f) << 21);
 798 }
 799
 800 static long
 801 extract_bo (unsigned long insn,
 802             int dialect,
 803             int *invalid)
 804 {
 805   long value;
 806
 807   value = (insn >> 21) & 0x1f;
 808   if (!valid_bo (value, dialect))
 809     *invalid = 1;
 810   return value;
 811 }
 812
 813 /* The BO field in a B form instruction when the + or - modifier is
 814    used.  This is like the BO field, but it must be even.  When
 815    extracting it, we force it to be even.  */
 816
 817 static unsigned long
 818 insert_boe (unsigned long insn,
 819             long value,
 820             int dialect,
 821             const char **errmsg)
 822 {
 823   if (!valid_bo (value, dialect))
 824     *errmsg = _("invalid conditional option");
 825   else if ((value & 1) != 0)
 826     *errmsg = _("attempt to set y bit when using + or - modifier");
 827
 828   return insn | ((value & 0x1f) << 21);
 829 }
 830
 831 static long
 832 extract_boe (unsigned long insn,
 833              int dialect,
 834              int *invalid)
 835 {
 836   long value;
 837
 838   value = (insn >> 21) & 0x1f;
 839   if (!valid_bo (value, dialect))
 840     *invalid = 1;
 841   return value & 0x1e;
 842 }
 843
 844 /* The DQ field in a DQ form instruction.  This is like D, but the
 845    lower four bits are forced to zero. */
 846
 847 static unsigned long
 848 insert_dq (unsigned long insn,
 849            long value,
 850            int dialect ATTRIBUTE_UNUSED,
 851            const char **errmsg)
 852 {
 853   if ((value & 0xf) != 0)
 854     *errmsg = _("offset not a multiple of 16");
 855   return insn | (value & 0xfff0);
 856 }
 857
 858 static long
 859 extract_dq (unsigned long insn,
 860             int dialect ATTRIBUTE_UNUSED,
 861             int *invalid ATTRIBUTE_UNUSED)
 862 {
 863   return ((insn & 0xfff0) ^ 0x8000) - 0x8000;
 864 }
 865
 866 static unsigned long
 867 insert_ev2 (unsigned long insn,
 868             long value,
 869             int dialect ATTRIBUTE_UNUSED,
 870             const char **errmsg)
 871 {
 872   if ((value & 1) != 0)
 873     *errmsg = _("offset not a multiple of 2");
 874   if ((value > 62) != 0)
 875     *errmsg = _("offset greater than 62");
 876   return insn | ((value & 0x3e) << 10);
 877 }
 878
 879 static long
 880 extract_ev2 (unsigned long insn,
 881              int dialect ATTRIBUTE_UNUSED,
 882              int *invalid ATTRIBUTE_UNUSED)
 883 {
 884   return (insn >> 10) & 0x3e;
 885 }
 886
 887 static unsigned long
 888 insert_ev4 (unsigned long insn,
 889             long value,
 890             int dialect ATTRIBUTE_UNUSED,
 891             const char **errmsg)
 892 {
 893   if ((value & 3) != 0)
 894     *errmsg = _("offset not a multiple of 4");
 895   if ((value > 124) != 0)
 896     *errmsg = _("offset greater than 124");
 897   return insn | ((value & 0x7c) << 9);
 898 }
 899
 900 static long
 901 extract_ev4 (unsigned long insn,
 902              int dialect ATTRIBUTE_UNUSED,
 903              int *invalid ATTRIBUTE_UNUSED)
 904 {
 905   return (insn >> 9) & 0x7c;
 906 }
 907
 908 static unsigned long
 909 insert_ev8 (unsigned long insn,
 910             long value,
 911             int dialect ATTRIBUTE_UNUSED,
 912             const char **errmsg)
 913 {
 914   if ((value & 7) != 0)
 915     *errmsg = _("offset not a multiple of 8");
 916   if ((value > 248) != 0)
 917     *errmsg = _("offset greater than 248");
 918   return insn | ((value & 0xf8) << 8);
 919 }
 920
 921 static long
 922 extract_ev8 (unsigned long insn,
 923              int dialect ATTRIBUTE_UNUSED,
 924              int *invalid ATTRIBUTE_UNUSED)
 925 {
 926   return (insn >> 8) & 0xf8;
 927 }
 928
 929 /* The DS field in a DS form instruction.  This is like D, but the
 930    lower two bits are forced to zero.  */
 931
 932 static unsigned long
 933 insert_ds (unsigned long insn,
 934            long value,
 935            int dialect ATTRIBUTE_UNUSED,
 936            const char **errmsg)
 937 {
 938   if ((value & 3) != 0)
 939     *errmsg = _("offset not a multiple of 4");
 940   return insn | (value & 0xfffc);
 941 }
 942
 943 static long
 944 extract_ds (unsigned long insn,
 945             int dialect ATTRIBUTE_UNUSED,
 946             int *invalid ATTRIBUTE_UNUSED)
 947 {
 948   return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
 949 }
 950
 951 /* The DE field in a DE form instruction.  */
 952
 953 static unsigned long
 954 insert_de (unsigned long insn,
 955            long value,
 956            int dialect ATTRIBUTE_UNUSED,
 957            const char **errmsg)
 958 {
 959   if (value > 2047 || value < -2048)
 960     *errmsg = _("offset not between -2048 and 2047");
 961   return insn | ((value << 4) & 0xfff0);
 962 }
 963
 964 static long
 965 extract_de (unsigned long insn,
 966             int dialect ATTRIBUTE_UNUSED,
 967             int *invalid ATTRIBUTE_UNUSED)
 968 {
 969   return (insn & 0xfff0) >> 4;
 970 }
 971
 972 /* The DES field in a DES form instruction.  */
 973
 974 static unsigned long
 975 insert_des (unsigned long insn,
 976             long value,
 977             int dialect ATTRIBUTE_UNUSED,
 978             const char **errmsg)
 979 {
 980   if (value > 8191 || value < -8192)
 981     *errmsg = _("offset not between -8192 and 8191");
 982   else if ((value & 3) != 0)
 983     *errmsg = _("offset not a multiple of 4");
 984   return insn | ((value << 2) & 0xfff0);
 985 }
 986
 987 static long
 988 extract_des (unsigned long insn,
 989              int dialect ATTRIBUTE_UNUSED,
 990              int *invalid ATTRIBUTE_UNUSED)
 991 {
 992   return (((insn >> 2) & 0x3ffc) ^ 0x2000) - 0x2000;
 993 }
 994
 995 /* FXM mask in mfcr and mtcrf instructions.  */
 996
 997 static unsigned long
 998 insert_fxm (unsigned long insn,
 999             long value,
1000             int dialect,
1001             const char **errmsg)
1002 {
1003   /* If we're handling the mfocrf and mtocrf insns ensure that exactly
1004      one bit of the mask field is set.  */
1005   if ((insn & (1 << 20)) != 0)
1006     {
1007       if (value == 0 || (value & -value) != value)
1008         {
1009           *errmsg = _("invalid mask field");
1010           value = 0;
1011         }
1012     }
1013
1014   /* If the optional field on mfcr is missing that means we want to use
1015      the old form of the instruction that moves the whole cr.  In that
1016      case we'll have VALUE zero.  There doesn't seem to be a way to
1017      distinguish this from the case where someone writes mfcr %r3,0.  */
1018   else if (value == 0)
1019     ;
1020
1021   /* If only one bit of the FXM field is set, we can use the new form
1022      of the instruction, which is faster.  Unlike the Power4 branch hint
1023      encoding, this is not backward compatible.  Do not generate the
1024      new form unless -mpower4 has been given, or -many and the two
1025      operand form of mfcr was used.  */
1026   else if ((value & -value) == value
1027            && ((dialect & PPC_OPCODE_POWER4) != 0
1028                || ((dialect & PPC_OPCODE_ANY) != 0
1029                    && (insn & (0x3ff << 1)) == 19 << 1)))
1030     insn |= 1 << 20;
1031
1032   /* Any other value on mfcr is an error.  */
1033   else if ((insn & (0x3ff << 1)) == 19 << 1)
1034     {
1035       *errmsg = _("ignoring invalid mfcr mask");
1036       value = 0;
1037     }
1038
1039   return insn | ((value & 0xff) << 12);
1040 }
1041
1042 static long
1043 extract_fxm (unsigned long insn,
1044              int dialect ATTRIBUTE_UNUSED,
1045              int *invalid)
1046 {
1047   long mask = (insn >> 12) & 0xff;
1048
1049   /* Is this a Power4 insn?  */
1050   if ((insn & (1 << 20)) != 0)
1051     {
1052       /* Exactly one bit of MASK should be set.  */
1053       if (mask == 0 || (mask & -mask) != mask)
1054         *invalid = 1;
1055     }
1056
1057   /* Check that non-power4 form of mfcr has a zero MASK.  */
1058   else if ((insn & (0x3ff << 1)) == 19 << 1)
1059     {
1060       if (mask != 0)
1061         *invalid = 1;
1062     }
1063
1064   return mask;
1065 }
1066
1067 /* The LI field in an I form instruction.  The lower two bits are
1068    forced to zero.  */
1069
1070 static unsigned long
1071 insert_li (unsigned long insn,
1072            long value,
1073            int dialect ATTRIBUTE_UNUSED,
1074            const char **errmsg)
1075 {
1076   if ((value & 3) != 0)
1077     *errmsg = _("ignoring least significant bits in branch offset");
1078   return insn | (value & 0x3fffffc);
1079 }
1080
1081 static long
1082 extract_li (unsigned long insn,
1083             int dialect ATTRIBUTE_UNUSED,
1084             int *invalid ATTRIBUTE_UNUSED)
1085 {
1086   return ((insn & 0x3fffffc) ^ 0x2000000) - 0x2000000;
1087 }
1088
1089 /* The MB and ME fields in an M form instruction expressed as a single
1090    operand which is itself a bitmask.  The extraction function always
1091    marks it as invalid, since we never want to recognize an
1092    instruction which uses a field of this type.  */
1093
1094 static unsigned long
1095 insert_mbe (unsigned long insn,
1096             long value,
1097             int dialect ATTRIBUTE_UNUSED,
1098             const char **errmsg)
1099 {
1100   unsigned long uval, mask;
1101   int mb, me, mx, count, last;
1102
1103   uval = value;
1104
1105   if (uval == 0)
1106     {
1107       *errmsg = _("illegal bitmask");
1108       return insn;
1109     }
1110
1111   mb = 0;
1112   me = 32;
1113   if ((uval & 1) != 0)
1114     last = 1;
1115   else
1116     last = 0;
1117   count = 0;
1118
1119   /* mb: location of last 0->1 transition */
1120   /* me: location of last 1->0 transition */
1121   /* count: # transitions */
1122
1123   for (mx = 0, mask = 1L << 31; mx < 32; ++mx, mask >>= 1)
1124     {
1125       if ((uval & mask) && !last)
1126         {
1127           ++count;
1128           mb = mx;
1129           last = 1;
1130         }
1131       else if (!(uval & mask) && last)
1132         {
1133           ++count;
1134           me = mx;
1135           last = 0;
1136         }
1137     }
1138   if (me == 0)
1139     me = 32;
1140
1141   if (count != 2 && (count != 0 || ! last))
1142     *errmsg = _("illegal bitmask");
1143
1144   return insn | (mb << 6) | ((me - 1) << 1);
1145 }
1146
1147 static long
1148 extract_mbe (unsigned long insn,
1149              int dialect ATTRIBUTE_UNUSED,
1150              int *invalid)
1151 {
1152   long ret;
1153   int mb, me;
1154   int i;
1155
1156   *invalid = 1;
1157
1158   mb = (insn >> 6) & 0x1f;
1159   me = (insn >> 1) & 0x1f;
1160   if (mb < me + 1)
1161     {
1162       ret = 0;
1163       for (i = mb; i <= me; i++)
1164         ret |= 1L << (31 - i);
1165     }
1166   else if (mb == me + 1)
1167     ret = ~0;
1168   else /* (mb > me + 1) */
1169     {
1170       ret = ~0;
1171       for (i = me + 1; i < mb; i++)
1172         ret &= ~(1L << (31 - i));
1173     }
1174   return ret;
1175 }
1176
1177 /* The MB or ME field in an MD or MDS form instruction.  The high bit
1178    is wrapped to the low end.  */
1179
1180 static unsigned long
1181 insert_mb6 (unsigned long insn,
1182             long value,
1183             int dialect ATTRIBUTE_UNUSED,
1184             const char **errmsg ATTRIBUTE_UNUSED)
1185 {
1186   return insn | ((value & 0x1f) << 6) | (value & 0x20);
1187 }
1188
1189 static long
1190 extract_mb6 (unsigned long insn,
1191              int dialect ATTRIBUTE_UNUSED,
1192              int *invalid ATTRIBUTE_UNUSED)
1193 {
1194   return ((insn >> 6) & 0x1f) | (insn & 0x20);
1195 }
1196
1197 /* The NB field in an X form instruction.  The value 32 is stored as
1198    0.  */
1199
1200 static unsigned long
1201 insert_nb (unsigned long insn,
1202            long value,
1203            int dialect ATTRIBUTE_UNUSED,
1204            const char **errmsg)
1205 {
1206   if (value < 0 || value > 32)
1207     *errmsg = _("value out of range");
1208   if (value == 32)
1209     value = 0;
1210   return insn | ((value & 0x1f) << 11);
1211 }
1212
1213 static long
1214 extract_nb (unsigned long insn,
1215             int dialect ATTRIBUTE_UNUSED,
1216             int *invalid ATTRIBUTE_UNUSED)
1217 {
1218   long ret;
1219
1220   ret = (insn >> 11) & 0x1f;
1221   if (ret == 0)
1222     ret = 32;
1223   return ret;
1224 }
1225
1226 /* The NSI field in a D form instruction.  This is the same as the SI
1227    field, only negated.  The extraction function always marks it as
1228    invalid, since we never want to recognize an instruction which uses
1229    a field of this type.  */
1230
1231 static unsigned long
1232 insert_nsi (unsigned long insn,
1233             long value,
1234             int dialect ATTRIBUTE_UNUSED,
1235             const char **errmsg ATTRIBUTE_UNUSED)
1236 {
1237   return insn | (-value & 0xffff);
1238 }
1239
1240 static long
1241 extract_nsi (unsigned long insn,
1242              int dialect ATTRIBUTE_UNUSED,
1243              int *invalid)
1244 {
1245   *invalid = 1;
1246   return -(((insn & 0xffff) ^ 0x8000) - 0x8000);
1247 }
1248
1249 /* The RA field in a D or X form instruction which is an updating
1250    load, which means that the RA field may not be zero and may not
1251    equal the RT field.  */
1252
1253 static unsigned long
1254 insert_ral (unsigned long insn,
1255             long value,
1256             int dialect ATTRIBUTE_UNUSED,
1257             const char **errmsg)
1258 {
1259   if (value == 0
1260       || (unsigned long) value == ((insn >> 21) & 0x1f))
1261     *errmsg = "invalid register operand when updating";
1262   return insn | ((value & 0x1f) << 16);
1263 }
1264
1265 /* The RA field in an lmw instruction, which has special value
1266    restrictions.  */
1267
1268 static unsigned long
1269 insert_ram (unsigned long insn,
1270             long value,
1271             int dialect ATTRIBUTE_UNUSED,
1272             const char **errmsg)
1273 {
1274   if ((unsigned long) value >= ((insn >> 21) & 0x1f))
1275     *errmsg = _("index register in load range");
1276   return insn | ((value & 0x1f) << 16);
1277 }
1278
1279 /* The RA field in the DQ form lq instruction, which has special
1280    value restrictions.  */
1281
1282 static unsigned long
1283 insert_raq (unsigned long insn,
1284             long value,
1285             int dialect ATTRIBUTE_UNUSED,
1286             const char **errmsg)
1287 {
1288   long rtvalue = (insn & RT_MASK) >> 21;
1289
1290   if (value == rtvalue)
1291     *errmsg = _("source and target register operands must be different");
1292   return insn | ((value & 0x1f) << 16);
1293 }
1294
1295 /* The RA field in a D or X form instruction which is an updating
1296    store or an updating floating point load, which means that the RA
1297    field may not be zero.  */
1298
1299 static unsigned long
1300 insert_ras (unsigned long insn,
1301             long value,
1302             int dialect ATTRIBUTE_UNUSED,
1303             const char **errmsg)
1304 {
1305   if (value == 0)
1306     *errmsg = _("invalid register operand when updating");
1307   return insn | ((value & 0x1f) << 16);
1308 }
1309
1310 /* The RB field in an X form instruction when it must be the same as
1311    the RS field in the instruction.  This is used for extended
1312    mnemonics like mr.  This operand is marked FAKE.  The insertion
1313    function just copies the BT field into the BA field, and the
1314    extraction function just checks that the fields are the same.  */
1315
1316 static unsigned long
1317 insert_rbs (unsigned long insn,
1318             long value ATTRIBUTE_UNUSED,
1319             int dialect ATTRIBUTE_UNUSED,
1320             const char **errmsg ATTRIBUTE_UNUSED)
1321 {
1322   return insn | (((insn >> 21) & 0x1f) << 11);
1323 }
1324
1325 static long
1326 extract_rbs (unsigned long insn,
1327              int dialect ATTRIBUTE_UNUSED,
1328              int *invalid)
1329 {
1330   if (((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f))
1331     *invalid = 1;
1332   return 0;
1333 }
1334
1335 /* The RT field of the DQ form lq instruction, which has special
1336    value restrictions.  */
1337
1338 static unsigned long
1339 insert_rtq (unsigned long insn,
1340             long value,
1341             int dialect ATTRIBUTE_UNUSED,
1342             const char **errmsg)
1343 {
1344   if ((value & 1) != 0)
1345     *errmsg = _("target register operand must be even");
1346   return insn | ((value & 0x1f) << 21);
1347 }
1348
1349 /* The RS field of the DS form stq instruction, which has special
1350    value restrictions.  */
1351
1352 static unsigned long
1353 insert_rsq (unsigned long insn,
1354             long value ATTRIBUTE_UNUSED,
1355             int dialect ATTRIBUTE_UNUSED,
1356             const char **errmsg)
1357 {
1358   if ((value & 1) != 0)
1359     *errmsg = _("source register operand must be even");
1360   return insn | ((value & 0x1f) << 21);
1361 }
1362
1363 /* The SH field in an MD form instruction.  This is split.  */
1364
1365 static unsigned long
1366 insert_sh6 (unsigned long insn,
1367             long value,
1368             int dialect ATTRIBUTE_UNUSED,
1369             const char **errmsg ATTRIBUTE_UNUSED)
1370 {
1371   return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
1372 }
1373
1374 static long
1375 extract_sh6 (unsigned long insn,
1376              int dialect ATTRIBUTE_UNUSED,
1377              int *invalid ATTRIBUTE_UNUSED)
1378 {
1379   return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
1380 }
1381
1382 /* The SPR field in an XFX form instruction.  This is flipped--the
1383    lower 5 bits are stored in the upper 5 and vice- versa.  */
1384
1385 static unsigned long
1386 insert_spr (unsigned long insn,
1387             long value,
1388             int dialect ATTRIBUTE_UNUSED,
1389             const char **errmsg ATTRIBUTE_UNUSED)
1390 {
1391   return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1392 }
1393
1394 static long
1395 extract_spr (unsigned long insn,
1396              int dialect ATTRIBUTE_UNUSED,
1397              int *invalid ATTRIBUTE_UNUSED)
1398 {
1399   return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1400 }
1401
1402 /* Some dialects have 8 SPRG registers instead of the standard 4.  */
1403
1404 static unsigned long
1405 insert_sprg (unsigned long insn,
1406              long value,
1407              int dialect,
1408              const char **errmsg)
1409 {
1410   /* This check uses PPC_OPCODE_403 because PPC405 is later defined
1411      as a synonym.  If ever a 405 specific dialect is added this
1412      check should use that instead.  */
1413   if (value > 7
1414       || (value > 3
1415           && (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_403)) == 0))
1416     *errmsg = _("invalid sprg number");
1417
1418   /* If this is mfsprg4..7 then use spr 260..263 which can be read in
1419      user mode.  Anything else must use spr 272..279.  */
1420   if (value <= 3 || (insn & 0x100) != 0)
1421     value |= 0x10;
1422
1423   return insn | ((value & 0x17) << 16);
1424 }
1425
1426 static long
1427 extract_sprg (unsigned long insn,
1428               int dialect,
1429               int *invalid)
1430 {
1431   unsigned long val = (insn >> 16) & 0x1f;
1432
1433   /* mfsprg can use 260..263 and 272..279.  mtsprg only uses spr 272..279
1434      If not BOOKE or 405, then both use only 272..275.  */
1435   if (val <= 3
1436       || (val < 0x10 && (insn & 0x100) != 0)
1437       || (val - 0x10 > 3
1438           && (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_403)) == 0))
1439     *invalid = 1;
1440   return val & 7;
1441 }
1442
1443 /* The TBR field in an XFX instruction.  This is just like SPR, but it
1444    is optional.  When TBR is omitted, it must be inserted as 268 (the
1445    magic number of the TB register).  These functions treat 0
1446    (indicating an omitted optional operand) as 268.  This means that
1447    ``mftb 4,0'' is not handled correctly.  This does not matter very
1448    much, since the architecture manual does not define mftb as
1449    accepting any values other than 268 or 269.  */
1450
1451 #define TB (268)
1452
1453 static unsigned long
1454 insert_tbr (unsigned long insn,
1455             long value,
1456             int dialect ATTRIBUTE_UNUSED,
1457             const char **errmsg ATTRIBUTE_UNUSED)
1458 {
1459   if (value == 0)
1460     value = TB;
1461   return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1462 }
1463
1464 static long
1465 extract_tbr (unsigned long insn,
1466              int dialect ATTRIBUTE_UNUSED,
1467              int *invalid ATTRIBUTE_UNUSED)
1468 {
1469   long ret;
1470
1471   ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1472   if (ret == TB)
1473     ret = 0;
1474   return ret;
1475 }
1476 \f
1477 /* Macros used to form opcodes.  */
1478
1479 /* The main opcode.  */
1480 #define OP(x) ((((unsigned long)(x)) & 0x3f) << 26)
1481 #define OP_MASK OP (0x3f)
1482
1483 /* The main opcode combined with a trap code in the TO field of a D
1484    form instruction.  Used for extended mnemonics for the trap
1485    instructions.  */
1486 #define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21))
1487 #define OPTO_MASK (OP_MASK | TO_MASK)
1488
1489 /* The main opcode combined with a comparison size bit in the L field
1490    of a D form or X form instruction.  Used for extended mnemonics for
1491    the comparison instructions.  */
1492 #define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21))
1493 #define OPL_MASK OPL (0x3f,1)
1494
1495 /* An A form instruction.  */
1496 #define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1))
1497 #define A_MASK A (0x3f, 0x1f, 1)
1498
1499 /* An A_MASK with the FRB field fixed.  */
1500 #define AFRB_MASK (A_MASK | FRB_MASK)
1501
1502 /* An A_MASK with the FRC field fixed.  */
1503 #define AFRC_MASK (A_MASK | FRC_MASK)
1504
1505 /* An A_MASK with the FRA and FRC fields fixed.  */
1506 #define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
1507
1508 /* A B form instruction.  */
1509 #define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1))
1510 #define B_MASK B (0x3f, 1, 1)
1511
1512 /* A B form instruction setting the BO field.  */
1513 #define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1514 #define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
1515
1516 /* A BBO_MASK with the y bit of the BO field removed.  This permits
1517    matching a conditional branch regardless of the setting of the y
1518    bit.  Similarly for the 'at' bits used for power4 branch hints.  */
1519 #define Y_MASK   (((unsigned long) 1) << 21)
1520 #define AT1_MASK (((unsigned long) 3) << 21)
1521 #define AT2_MASK (((unsigned long) 9) << 21)
1522 #define BBOY_MASK  (BBO_MASK &~ Y_MASK)
1523 #define BBOAT_MASK (BBO_MASK &~ AT1_MASK)
1524
1525 /* A B form instruction setting the BO field and the condition bits of
1526    the BI field.  */
1527 #define BBOCB(op, bo, cb, aa, lk) \
1528   (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16))
1529 #define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
1530
1531 /* A BBOCB_MASK with the y bit of the BO field removed.  */
1532 #define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
1533 #define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK)
1534 #define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK)
1535
1536 /* A BBOYCB_MASK in which the BI field is fixed.  */
1537 #define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
1538 #define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK)
1539
1540 /* An Context form instruction.  */
1541 #define CTX(op, xop)   (OP (op) | (((unsigned long)(xop)) & 0x7))
1542 #define CTX_MASK CTX(0x3f, 0x7)
1543
1544 /* An User Context form instruction.  */
1545 #define UCTX(op, xop)  (OP (op) | (((unsigned long)(xop)) & 0x1f))
1546 #define UCTX_MASK UCTX(0x3f, 0x1f)
1547
1548 /* The main opcode mask with the RA field clear.  */
1549 #define DRA_MASK (OP_MASK | RA_MASK)
1550
1551 /* A DS form instruction.  */
1552 #define DSO(op, xop) (OP (op) | ((xop) & 0x3))
1553 #define DS_MASK DSO (0x3f, 3)
1554
1555 /* A DE form instruction.  */
1556 #define DEO(op, xop) (OP (op) | ((xop) & 0xf))
1557 #define DE_MASK DEO (0x3e, 0xf)
1558
1559 /* An EVSEL form instruction.  */
1560 #define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3)
1561 #define EVSEL_MASK EVSEL(0x3f, 0xff)
1562
1563 /* An M form instruction.  */
1564 #define M(op, rc) (OP (op) | ((rc) & 1))
1565 #define M_MASK M (0x3f, 1)
1566
1567 /* An M form instruction with the ME field specified.  */
1568 #define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1))
1569
1570 /* An M_MASK with the MB and ME fields fixed.  */
1571 #define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
1572
1573 /* An M_MASK with the SH and ME fields fixed.  */
1574 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
1575
1576 /* An MD form instruction.  */
1577 #define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1))
1578 #define MD_MASK MD (0x3f, 0x7, 1)
1579
1580 /* An MD_MASK with the MB field fixed.  */
1581 #define MDMB_MASK (MD_MASK | MB6_MASK)
1582
1583 /* An MD_MASK with the SH field fixed.  */
1584 #define MDSH_MASK (MD_MASK | SH6_MASK)
1585
1586 /* An MDS form instruction.  */
1587 #define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1))
1588 #define MDS_MASK MDS (0x3f, 0xf, 1)
1589
1590 /* An MDS_MASK with the MB field fixed.  */
1591 #define MDSMB_MASK (MDS_MASK | MB6_MASK)
1592
1593 /* An SC form instruction.  */
1594 #define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
1595 #define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
1596
1597 /* An VX form instruction.  */
1598 #define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
1599
1600 /* The mask for an VX form instruction.  */
1601 #define VX_MASK VX(0x3f, 0x7ff)
1602
1603 /* An VA form instruction.  */
1604 #define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
1605
1606 /* The mask for an VA form instruction.  */
1607 #define VXA_MASK VXA(0x3f, 0x3f)
1608
1609 /* An VXR form instruction.  */
1610 #define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
1611
1612 /* The mask for a VXR form instruction.  */
1613 #define VXR_MASK VXR(0x3f, 0x3ff, 1)
1614
1615 /* An X form instruction.  */
1616 #define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1617
1618 /* An X form instruction with the RC bit specified.  */
1619 #define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
1620
1621 /* The mask for an X form instruction.  */
1622 #define X_MASK XRC (0x3f, 0x3ff, 1)
1623
1624 /* An X_MASK with the RA field fixed.  */
1625 #define XRA_MASK (X_MASK | RA_MASK)
1626
1627 /* An X_MASK with the RB field fixed.  */
1628 #define XRB_MASK (X_MASK | RB_MASK)
1629
1630 /* An X_MASK with the RT field fixed.  */
1631 #define XRT_MASK (X_MASK | RT_MASK)
1632
1633 /* An X_MASK with the RA and RB fields fixed.  */
1634 #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
1635
1636 /* An XRARB_MASK, but with the L bit clear.  */
1637 #define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16))
1638
1639 /* An X_MASK with the RT and RA fields fixed.  */
1640 #define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
1641
1642 /* An XRTRA_MASK, but with L bit clear.  */
1643 #define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21))
1644
1645 /* An X form instruction with the L bit specified.  */
1646 #define XOPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
1647
1648 /* The mask for an X form comparison instruction.  */
1649 #define XCMP_MASK (X_MASK | (((unsigned long)1) << 22))
1650
1651 /* The mask for an X form comparison instruction with the L field
1652    fixed.  */
1653 #define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21))
1654
1655 /* An X form trap instruction with the TO field specified.  */
1656 #define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21))
1657 #define XTO_MASK (X_MASK | TO_MASK)
1658
1659 /* An X form tlb instruction with the SH field specified.  */
1660 #define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11))
1661 #define XTLB_MASK (X_MASK | SH_MASK)
1662
1663 /* An X form sync instruction.  */
1664 #define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
1665
1666 /* An X form sync instruction with everything filled in except the LS field.  */
1667 #define XSYNC_MASK (0xff9fffff)
1668
1669 /* An X form AltiVec dss instruction.  */
1670 #define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25))
1671 #define XDSS_MASK XDSS(0x3f, 0x3ff, 1)
1672
1673 /* An XFL form instruction.  */
1674 #define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
1675 #define XFL_MASK (XFL (0x3f, 0x3ff, 1) | (((unsigned long)1) << 25) | (((unsigned long)1) << 16))
1676
1677 /* An X form isel instruction.  */
1678 #define XISEL(op, xop)  (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
1679 #define XISEL_MASK      XISEL(0x3f, 0x1f)
1680
1681 /* An XL form instruction with the LK field set to 0.  */
1682 #define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1683
1684 /* An XL form instruction which uses the LK field.  */
1685 #define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
1686
1687 /* The mask for an XL form instruction.  */
1688 #define XL_MASK XLLK (0x3f, 0x3ff, 1)
1689
1690 /* An XL form instruction which explicitly sets the BO field.  */
1691 #define XLO(op, bo, xop, lk) \
1692   (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1693 #define XLO_MASK (XL_MASK | BO_MASK)
1694
1695 /* An XL form instruction which explicitly sets the y bit of the BO
1696    field.  */
1697 #define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21))
1698 #define XLYLK_MASK (XL_MASK | Y_MASK)
1699
1700 /* An XL form instruction which sets the BO field and the condition
1701    bits of the BI field.  */
1702 #define XLOCB(op, bo, cb, xop, lk) \
1703   (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16))
1704 #define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
1705
1706 /* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed.  */
1707 #define XLBB_MASK (XL_MASK | BB_MASK)
1708 #define XLYBB_MASK (XLYLK_MASK | BB_MASK)
1709 #define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
1710
1711 /* A mask for branch instructions using the BH field.  */
1712 #define XLBH_MASK (XL_MASK | (0x1c << 11))
1713
1714 /* An XL_MASK with the BO and BB fields fixed.  */
1715 #define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
1716
1717 /* An XL_MASK with the BO, BI and BB fields fixed.  */
1718 #define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
1719
1720 /* An XO form instruction.  */
1721 #define XO(op, xop, oe, rc) \
1722   (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1))
1723 #define XO_MASK XO (0x3f, 0x1ff, 1, 1)
1724
1725 /* An XO_MASK with the RB field fixed.  */
1726 #define XORB_MASK (XO_MASK | RB_MASK)
1727
1728 /* An XS form instruction.  */
1729 #define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1))
1730 #define XS_MASK XS (0x3f, 0x1ff, 1)
1731
1732 /* A mask for the FXM version of an XFX form instruction.  */
1733 #define XFXFXM_MASK (X_MASK | (1 << 11) | (1 << 20))
1734
1735 /* An XFX form instruction with the FXM field filled in.  */
1736 #define XFXM(op, xop, fxm, p4) \
1737   (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12) \
1738    | ((unsigned long)(p4) << 20))
1739
1740 /* An XFX form instruction with the SPR field filled in.  */
1741 #define XSPR(op, xop, spr) \
1742   (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6))
1743 #define XSPR_MASK (X_MASK | SPR_MASK)
1744
1745 /* An XFX form instruction with the SPR field filled in except for the
1746    SPRBAT field.  */
1747 #define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
1748
1749 /* An XFX form instruction with the SPR field filled in except for the
1750    SPRG field.  */
1751 #define XSPRG_MASK (XSPR_MASK & ~(0x17 << 16))
1752
1753 /* An X form instruction with everything filled in except the E field.  */
1754 #define XE_MASK (0xffff7fff)
1755
1756 /* An X form user context instruction.  */
1757 #define XUC(op, xop)  (OP (op) | (((unsigned long)(xop)) & 0x1f))
1758 #define XUC_MASK      XUC(0x3f, 0x1f)
1759
1760 /* The BO encodings used in extended conditional branch mnemonics.  */
1761 #define BODNZF  (0x0)
1762 #define BODNZFP (0x1)
1763 #define BODZF   (0x2)
1764 #define BODZFP  (0x3)
1765 #define BODNZT  (0x8)
1766 #define BODNZTP (0x9)
1767 #define BODZT   (0xa)
1768 #define BODZTP  (0xb)
1769
1770 #define BOF     (0x4)
1771 #define BOFP    (0x5)
1772 #define BOFM4   (0x6)
1773 #define BOFP4   (0x7)
1774 #define BOT     (0xc)
1775 #define BOTP    (0xd)
1776 #define BOTM4   (0xe)
1777 #define BOTP4   (0xf)
1778
1779 #define BODNZ   (0x10)
1780 #define BODNZP  (0x11)
1781 #define BODZ    (0x12)
1782 #define BODZP   (0x13)
1783 #define BODNZM4 (0x18)
1784 #define BODNZP4 (0x19)
1785 #define BODZM4  (0x1a)
1786 #define BODZP4  (0x1b)
1787
1788 #define BOU     (0x14)
1789
1790 /* The BI condition bit encodings used in extended conditional branch
1791    mnemonics.  */
1792 #define CBLT    (0)
1793 #define CBGT    (1)
1794 #define CBEQ    (2)
1795 #define CBSO    (3)
1796
1797 /* The TO encodings used in extended trap mnemonics.  */
1798 #define TOLGT   (0x1)
1799 #define TOLLT   (0x2)
1800 #define TOEQ    (0x4)
1801 #define TOLGE   (0x5)
1802 #define TOLNL   (0x5)
1803 #define TOLLE   (0x6)
1804 #define TOLNG   (0x6)
1805 #define TOGT    (0x8)
1806 #define TOGE    (0xc)
1807 #define TONL    (0xc)
1808 #define TOLT    (0x10)
1809 #define TOLE    (0x14)
1810 #define TONG    (0x14)
1811 #define TONE    (0x18)
1812 #define TOU     (0x1f)
1813 \f
1814 /* Smaller names for the flags so each entry in the opcodes table will
1815    fit on a single line.  */
1816 #undef  PPC
1817 #define PPC     PPC_OPCODE_PPC
1818 #define PPCCOM  PPC_OPCODE_PPC | PPC_OPCODE_COMMON
1819 #define NOPOWER4 PPC_OPCODE_NOPOWER4 | PPCCOM
1820 #define POWER4  PPC_OPCODE_POWER4
1821 #define PPC32   PPC_OPCODE_32 | PPC_OPCODE_PPC
1822 #define PPC64   PPC_OPCODE_64 | PPC_OPCODE_PPC
1823 #define PPC403  PPC_OPCODE_403
1824 #define PPC405  PPC403
1825 #define PPC440  PPC_OPCODE_440
1826 #define PPC750  PPC
1827 #define PPC860  PPC
1828 #define PPCVEC  PPC_OPCODE_ALTIVEC
1829 #define POWER   PPC_OPCODE_POWER
1830 #define POWER2  PPC_OPCODE_POWER | PPC_OPCODE_POWER2
1831 #define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2
1832 #define POWER32 PPC_OPCODE_POWER | PPC_OPCODE_32
1833 #define COM     PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON
1834 #define COM32   PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_32
1835 #define M601    PPC_OPCODE_POWER | PPC_OPCODE_601
1836 #define PWRCOM  PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON
1837 #define MFDEC1  PPC_OPCODE_POWER
1838 #define MFDEC2  PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE
1839 #define BOOKE   PPC_OPCODE_BOOKE
1840 #define BOOKE64 PPC_OPCODE_BOOKE64
1841 #define CLASSIC PPC_OPCODE_CLASSIC
1842 #define PPCSPE  PPC_OPCODE_SPE
1843 #define PPCISEL PPC_OPCODE_ISEL
1844 #define PPCEFS  PPC_OPCODE_EFS
1845 #define PPCBRLK PPC_OPCODE_BRLOCK
1846 #define PPCPMR  PPC_OPCODE_PMR
1847 #define PPCCHLK PPC_OPCODE_CACHELCK
1848 #define PPCCHLK64       PPC_OPCODE_CACHELCK | PPC_OPCODE_BOOKE64
1849 #define PPCRFMCI        PPC_OPCODE_RFMCI
1850 \f
1851 /* The opcode table.
1852
1853    The format of the opcode table is:
1854
1855    NAME      OPCODE     MASK            FLAGS           { OPERANDS }
1856
1857    NAME is the name of the instruction.
1858    OPCODE is the instruction opcode.
1859    MASK is the opcode mask; this is used to tell the disassembler
1860      which bits in the actual opcode must match OPCODE.
1861    FLAGS are flags indicated what processors support the instruction.
1862    OPERANDS is the list of operands.
1863
1864    The disassembler reads the table in order and prints the first
1865    instruction which matches, so this table is sorted to put more
1866    specific instructions before more general instructions.  It is also
1867    sorted by major opcode.  */
1868
1869 const struct powerpc_opcode powerpc_opcodes[] = {
1870 { "attn",    X(0,256), X_MASK,          POWER4,         { 0 } },
1871 { "tdlgti",  OPTO(2,TOLGT), OPTO_MASK,  PPC64,          { RA, SI } },
1872 { "tdllti",  OPTO(2,TOLLT), OPTO_MASK,  PPC64,          { RA, SI } },
1873 { "tdeqi",   OPTO(2,TOEQ), OPTO_MASK,   PPC64,          { RA, SI } },
1874 { "tdlgei",  OPTO(2,TOLGE), OPTO_MASK,  PPC64,          { RA, SI } },
1875 { "tdlnli",  OPTO(2,TOLNL), OPTO_MASK,  PPC64,          { RA, SI } },
1876 { "tdllei",  OPTO(2,TOLLE), OPTO_MASK,  PPC64,          { RA, SI } },
1877 { "tdlngi",  OPTO(2,TOLNG), OPTO_MASK,  PPC64,          { RA, SI } },
1878 { "tdgti",   OPTO(2,TOGT), OPTO_MASK,   PPC64,          { RA, SI } },
1879 { "tdgei",   OPTO(2,TOGE), OPTO_MASK,   PPC64,          { RA, SI } },
1880 { "tdnli",   OPTO(2,TONL), OPTO_MASK,   PPC64,          { RA, SI } },
1881 { "tdlti",   OPTO(2,TOLT), OPTO_MASK,   PPC64,          { RA, SI } },
1882 { "tdlei",   OPTO(2,TOLE), OPTO_MASK,   PPC64,          { RA, SI } },
1883 { "tdngi",   OPTO(2,TONG), OPTO_MASK,   PPC64,          { RA, SI } },
1884 { "tdnei",   OPTO(2,TONE), OPTO_MASK,   PPC64,          { RA, SI } },
1885 { "tdi",     OP(2),     OP_MASK,        PPC64,          { TO, RA, SI } },
1886
1887 { "twlgti",  OPTO(3,TOLGT), OPTO_MASK,  PPCCOM,         { RA, SI } },
1888 { "tlgti",   OPTO(3,TOLGT), OPTO_MASK,  PWRCOM,         { RA, SI } },
1889 { "twllti",  OPTO(3,TOLLT), OPTO_MASK,  PPCCOM,         { RA, SI } },
1890 { "tllti",   OPTO(3,TOLLT), OPTO_MASK,  PWRCOM,         { RA, SI } },
1891 { "tweqi",   OPTO(3,TOEQ), OPTO_MASK,   PPCCOM,         { RA, SI } },
1892 { "teqi",    OPTO(3,TOEQ), OPTO_MASK,   PWRCOM,         { RA, SI } },
1893 { "twlgei",  OPTO(3,TOLGE), OPTO_MASK,  PPCCOM,         { RA, SI } },
1894 { "tlgei",   OPTO(3,TOLGE), OPTO_MASK,  PWRCOM,         { RA, SI } },
1895 { "twlnli",  OPTO(3,TOLNL), OPTO_MASK,  PPCCOM,         { RA, SI } },
1896 { "tlnli",   OPTO(3,TOLNL), OPTO_MASK,  PWRCOM,         { RA, SI } },
1897 { "twllei",  OPTO(3,TOLLE), OPTO_MASK,  PPCCOM,         { RA, SI } },
1898 { "tllei",   OPTO(3,TOLLE), OPTO_MASK,  PWRCOM,         { RA, SI } },
1899 { "twlngi",  OPTO(3,TOLNG), OPTO_MASK,  PPCCOM,         { RA, SI } },
1900 { "tlngi",   OPTO(3,TOLNG), OPTO_MASK,  PWRCOM,         { RA, SI } },
1901 { "twgti",   OPTO(3,TOGT), OPTO_MASK,   PPCCOM,         { RA, SI } },
1902 { "tgti",    OPTO(3,TOGT), OPTO_MASK,   PWRCOM,         { RA, SI } },
1903 { "twgei",   OPTO(3,TOGE), OPTO_MASK,   PPCCOM,         { RA, SI } },
1904 { "tgei",    OPTO(3,TOGE), OPTO_MASK,   PWRCOM,         { RA, SI } },
1905 { "twnli",   OPTO(3,TONL), OPTO_MASK,   PPCCOM,         { RA, SI } },
1906 { "tnli",    OPTO(3,TONL), OPTO_MASK,   PWRCOM,         { RA, SI } },
1907 { "twlti",   OPTO(3,TOLT), OPTO_MASK,   PPCCOM,         { RA, SI } },
1908 { "tlti",    OPTO(3,TOLT), OPTO_MASK,   PWRCOM,         { RA, SI } },
1909 { "twlei",   OPTO(3,TOLE), OPTO_MASK,   PPCCOM,         { RA, SI } },
1910 { "tlei",    OPTO(3,TOLE), OPTO_MASK,   PWRCOM,         { RA, SI } },
1911 { "twngi",   OPTO(3,TONG), OPTO_MASK,   PPCCOM,         { RA, SI } },
1912 { "tngi",    OPTO(3,TONG), OPTO_MASK,   PWRCOM,         { RA, SI } },
1913 { "twnei",   OPTO(3,TONE), OPTO_MASK,   PPCCOM,         { RA, SI } },
1914 { "tnei",    OPTO(3,TONE), OPTO_MASK,   PWRCOM,         { RA, SI } },
1915 { "twi",     OP(3),     OP_MASK,        PPCCOM,         { TO, RA, SI } },
1916 { "ti",      OP(3),     OP_MASK,        PWRCOM,         { TO, RA, SI } },
1917
1918 { "macchw",     XO(4,172,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1919 { "macchw.",    XO(4,172,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1920 { "macchwo",    XO(4,172,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1921 { "macchwo.",   XO(4,172,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1922 { "macchws",    XO(4,236,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1923 { "macchws.",   XO(4,236,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1924 { "macchwso",   XO(4,236,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1925 { "macchwso.",  XO(4,236,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1926 { "macchwsu",   XO(4,204,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1927 { "macchwsu.",  XO(4,204,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1928 { "macchwsuo",  XO(4,204,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1929 { "macchwsuo.", XO(4,204,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1930 { "macchwu",    XO(4,140,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1931 { "macchwu.",   XO(4,140,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1932 { "macchwuo",   XO(4,140,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1933 { "macchwuo.",  XO(4,140,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1934 { "machhw",     XO(4,44,0,0),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1935 { "machhw.",    XO(4,44,0,1),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1936 { "machhwo",    XO(4,44,1,0),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1937 { "machhwo.",   XO(4,44,1,1),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1938 { "machhws",    XO(4,108,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1939 { "machhws.",   XO(4,108,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1940 { "machhwso",   XO(4,108,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1941 { "machhwso.",  XO(4,108,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1942 { "machhwsu",   XO(4,76,0,0),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1943 { "machhwsu.",  XO(4,76,0,1),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1944 { "machhwsuo",  XO(4,76,1,0),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1945 { "machhwsuo.", XO(4,76,1,1),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1946 { "machhwu",    XO(4,12,0,0),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1947 { "machhwu.",   XO(4,12,0,1),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1948 { "machhwuo",   XO(4,12,1,0),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1949 { "machhwuo.",  XO(4,12,1,1),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1950 { "maclhw",     XO(4,428,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1951 { "maclhw.",    XO(4,428,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1952 { "maclhwo",    XO(4,428,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1953 { "maclhwo.",   XO(4,428,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1954 { "maclhws",    XO(4,492,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1955 { "maclhws.",   XO(4,492,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1956 { "maclhwso",   XO(4,492,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1957 { "maclhwso.",  XO(4,492,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1958 { "maclhwsu",   XO(4,460,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1959 { "maclhwsu.",  XO(4,460,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1960 { "maclhwsuo",  XO(4,460,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1961 { "maclhwsuo.", XO(4,460,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1962 { "maclhwu",    XO(4,396,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1963 { "maclhwu.",   XO(4,396,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1964 { "maclhwuo",   XO(4,396,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1965 { "maclhwuo.",  XO(4,396,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1966 { "mulchw",     XRC(4,168,0),  X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
1967 { "mulchw.",    XRC(4,168,1),  X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
1968 { "mulchwu",    XRC(4,136,0),  X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
1969 { "mulchwu.",   XRC(4,136,1),  X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
1970 { "mulhhw",     XRC(4,40,0),   X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
1971 { "mulhhw.",    XRC(4,40,1),   X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
1972 { "mulhhwu",    XRC(4,8,0),    X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
1973 { "mulhhwu.",   XRC(4,8,1),    X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
1974 { "mullhw",     XRC(4,424,0),  X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
1975 { "mullhw.",    XRC(4,424,1),  X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
1976 { "mullhwu",    XRC(4,392,0),  X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
1977 { "mullhwu.",   XRC(4,392,1),  X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
1978 { "nmacchw",    XO(4,174,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1979 { "nmacchw.",   XO(4,174,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1980 { "nmacchwo",   XO(4,174,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1981 { "nmacchwo.",  XO(4,174,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1982 { "nmacchws",   XO(4,238,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1983 { "nmacchws.",  XO(4,238,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1984 { "nmacchwso",  XO(4,238,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1985 { "nmacchwso.", XO(4,238,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1986 { "nmachhw",    XO(4,46,0,0),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1987 { "nmachhw.",   XO(4,46,0,1),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1988 { "nmachhwo",   XO(4,46,1,0),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1989 { "nmachhwo.",  XO(4,46,1,1),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1990 { "nmachhws",   XO(4,110,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1991 { "nmachhws.",  XO(4,110,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1992 { "nmachhwso",  XO(4,110,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1993 { "nmachhwso.", XO(4,110,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1994 { "nmaclhw",    XO(4,430,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1995 { "nmaclhw.",   XO(4,430,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1996 { "nmaclhwo",   XO(4,430,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1997 { "nmaclhwo.",  XO(4,430,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1998 { "nmaclhws",   XO(4,494,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1999 { "nmaclhws.",  XO(4,494,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
2000 { "nmaclhwso",  XO(4,494,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
2001 { "nmaclhwso.", XO(4,494,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
2002 { "mfvscr",  VX(4, 1540), VX_MASK,      PPCVEC,         { VD } },
2003 { "mtvscr",  VX(4, 1604), VX_MASK,      PPCVEC,         { VB } },
2004
2005   /* Double-precision opcodes.  */
2006   /* Some of these conflict with AltiVec, so move them before, since
2007      PPCVEC includes the PPC_OPCODE_PPC set.  */
2008 { "efscfd",   VX(4, 719), VX_MASK,      PPCEFS,         { RS, RB } },
2009 { "efdabs",   VX(4, 740), VX_MASK,      PPCEFS,         { RS, RA } },
2010 { "efdnabs",  VX(4, 741), VX_MASK,      PPCEFS,         { RS, RA } },
2011 { "efdneg",   VX(4, 742), VX_MASK,      PPCEFS,         { RS, RA } },
2012 { "efdadd",   VX(4, 736), VX_MASK,      PPCEFS,         { RS, RA, RB } },
2013 { "efdsub",   VX(4, 737), VX_MASK,      PPCEFS,         { RS, RA, RB } },
2014 { "efdmul",   VX(4, 744), VX_MASK,      PPCEFS,         { RS, RA, RB } },
2015 { "efddiv",   VX(4, 745), VX_MASK,      PPCEFS,         { RS, RA, RB } },
2016 { "efdcmpgt", VX(4, 748), VX_MASK,      PPCEFS,         { CRFD, RA, RB } },
2017 { "efdcmplt", VX(4, 749), VX_MASK,      PPCEFS,         { CRFD, RA, RB } },
2018 { "efdcmpeq", VX(4, 750), VX_MASK,      PPCEFS,         { CRFD, RA, RB } },
2019 { "efdtstgt", VX(4, 764), VX_MASK,      PPCEFS,         { CRFD, RA, RB } },
2020 { "efdtstlt", VX(4, 765), VX_MASK,      PPCEFS,         { CRFD, RA, RB } },
2021 { "efdtsteq", VX(4, 766), VX_MASK,      PPCEFS,         { CRFD, RA, RB } },
2022 { "efdcfsi",  VX(4, 753), VX_MASK,      PPCEFS,         { RS, RB } },
2023 { "efdcfsid", VX(4, 739), VX_MASK,      PPCEFS,         { RS, RB } },
2024 { "efdcfui",  VX(4, 752), VX_MASK,      PPCEFS,         { RS, RB } },
2025 { "efdcfuid", VX(4, 738), VX_MASK,      PPCEFS,         { RS, RB } },
2026 { "efdcfsf",  VX(4, 755), VX_MASK,      PPCEFS,         { RS, RB } },
2027 { "efdcfuf",  VX(4, 754), VX_MASK,      PPCEFS,         { RS, RB } },
2028 { "efdctsi",  VX(4, 757), VX_MASK,      PPCEFS,         { RS, RB } },
2029 { "efdctsidz",VX(4, 747), VX_MASK,      PPCEFS,         { RS, RB } },
2030 { "efdctsiz", VX(4, 762), VX_MASK,      PPCEFS,         { RS, RB } },
2031 { "efdctui",  VX(4, 756), VX_MASK,      PPCEFS,         { RS, RB } },
2032 { "efdctuidz",VX(4, 746), VX_MASK,      PPCEFS,         { RS, RB } },
2033 { "efdctuiz", VX(4, 760), VX_MASK,      PPCEFS,         { RS, RB } },
2034 { "efdctsf",  VX(4, 759), VX_MASK,      PPCEFS,         { RS, RB } },
2035 { "efdctuf",  VX(4, 758), VX_MASK,      PPCEFS,         { RS, RB } },
2036 { "efdcfs",   VX(4, 751), VX_MASK,      PPCEFS,         { RS, RB } },
2037   /* End of double-precision opcodes.  */
2038
2039 { "vaddcuw", VX(4,  384), VX_MASK,      PPCVEC,         { VD, VA, VB } },
2040 { "vaddfp",  VX(4,   10), VX_MASK,      PPCVEC,         { VD, VA, VB } },
2041 { "vaddsbs", VX(4,  768), VX_MASK,      PPCVEC,         { VD, VA, VB } },
2042 { "vaddshs", VX(4,  832), VX_MASK,      PPCVEC,         { VD, VA, VB } },
2043 { "vaddsws", VX(4,  896), VX_MASK,      PPCVEC,         { VD, VA, VB } },
2044 { "vaddubm", VX(4,    0), VX_MASK,      PPCVEC,         { VD, VA, VB } },
2045 { "vaddubs", VX(4,  512), VX_MASK,      PPCVEC,         { VD, VA, VB } },
2046 { "vadduhm", VX(4,   64), VX_MASK,      PPCVEC,         { VD, VA, VB } },
2047 { "vadduhs", VX(4,  576), VX_MASK,      PPCVEC,         { VD, VA, VB } },
2048 { "vadduwm", VX(4,  128), VX_MASK,      PPCVEC,         { VD, VA, VB } },
2049 { "vadduws", VX(4,  640), VX_MASK,      PPCVEC,         { VD, VA, VB } },
2050 { "vand",    VX(4, 1028), VX_MASK,      PPCVEC,         { VD, VA, VB } },
2051 { "vandc",   VX(4, 1092), VX_MASK,      PPCVEC,         { VD, VA, VB } },
2052 { "vavgsb",  VX(4, 1282), VX_MASK,      PPCVEC,         { VD, VA, VB } },
2053 { "vavgsh",  VX(4, 1346), VX_MASK,      PPCVEC,         { VD, VA, VB } },
2054 { "vavgsw",  VX(4, 1410), VX_MASK,      PPCVEC,         { VD, VA, VB } },
2055 { "vavgub",  VX(4, 1026), VX_MASK,      PPCVEC,         { VD, VA, VB } },
2056 { "vavguh",  VX(4, 1090), VX_MASK,      PPCVEC,         { VD, VA, VB } },
2057 { "vavguw",  VX(4, 1154), VX_MASK,      PPCVEC,         { VD, VA, VB } },
2058 { "vcfsx",   VX(4,  842), VX_MASK,      PPCVEC,         { VD, VB, UIMM } },
2059 { "vcfux",   VX(4,  778), VX_MASK,      PPCVEC,         { VD, VB, UIMM } },
2060 { "vcmpbfp",   VXR(4, 966, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
2061 { "vcmpbfp.",  VXR(4, 966, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
2062 { "vcmpeqfp",  VXR(4, 198, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
2063 { "vcmpeqfp.", VXR(4, 198, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
2064 { "vcmpequb",  VXR(4,   6, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
2065 { "vcmpequb.", VXR(4,   6, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
2066 { "vcmpequh",  VXR(4,  70, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
2067 { "vcmpequh.", VXR(4,  70, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
2068 { "vcmpequw",  VXR(4, 134, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
2069 { "vcmpequw.", VXR(4, 134, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
2070 { "vcmpgefp",  VXR(4, 454, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
2071 { "vcmpgefp.", VXR(4, 454, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
2072 { "vcmpgtfp",  VXR(4, 710, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
2073 { "vcmpgtfp.", VXR(4, 710, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
2074 { "vcmpgtsb",  VXR(4, 774, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
2075 { "vcmpgtsb.", VXR(4, 774, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
2076 { "vcmpgtsh",  VXR(4, 838, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
2077 { "vcmpgtsh.", VXR(4, 838, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
2078 { "vcmpgtsw",  VXR(4, 902, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
2079 { "vcmpgtsw.", VXR(4, 902, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
2080 { "vcmpgtub",  VXR(4, 518, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
2081 { "vcmpgtub.", VXR(4, 518, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
2082 { "vcmpgtuh",  VXR(4, 582, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
2083 { "vcmpgtuh.", VXR(4, 582, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
2084 { "vcmpgtuw",  VXR(4, 646, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
2085 { "vcmpgtuw.", VXR(4, 646, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
2086 { "vctsxs",    VX(4,  970), VX_MASK,    PPCVEC,         { VD, VB, UIMM } },
2087 { "vctuxs",    VX(4,  906), VX_MASK,    PPCVEC,         { VD, VB, UIMM } },
2088 { "vexptefp",  VX(4,  394), VX_MASK,    PPCVEC,         { VD, VB } },
2089 { "vlogefp",   VX(4,  458), VX_MASK,    PPCVEC,         { VD, VB } },
2090 { "vmaddfp",   VXA(4,  46), VXA_MASK,   PPCVEC,         { VD, VA, VC, VB } },
2091 { "vmaxfp",    VX(4, 1034), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2092 { "vmaxsb",    VX(4,  258), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2093 { "vmaxsh",    VX(4,  322), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2094 { "vmaxsw",    VX(4,  386), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2095 { "vmaxub",    VX(4,    2), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2096 { "vmaxuh",    VX(4,   66), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2097 { "vmaxuw",    VX(4,  130), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2098 { "vmhaddshs", VXA(4,  32), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
2099 { "vmhraddshs", VXA(4, 33), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
2100 { "vminfp",    VX(4, 1098), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2101 { "vminsb",    VX(4,  770), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2102 { "vminsh",    VX(4,  834), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2103 { "vminsw",    VX(4,  898), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2104 { "vminub",    VX(4,  514), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2105 { "vminuh",    VX(4,  578), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2106 { "vminuw",    VX(4,  642), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2107 { "vmladduhm", VXA(4,  34), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
2108 { "vmrghb",    VX(4,   12), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2109 { "vmrghh",    VX(4,   76), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2110 { "vmrghw",    VX(4,  140), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2111 { "vmrglb",    VX(4,  268), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2112 { "vmrglh",    VX(4,  332), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2113 { "vmrglw",    VX(4,  396), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2114 { "vmsummbm",  VXA(4,  37), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
2115 { "vmsumshm",  VXA(4,  40), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
2116 { "vmsumshs",  VXA(4,  41), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
2117 { "vmsumubm",  VXA(4,  36), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
2118 { "vmsumuhm",  VXA(4,  38), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
2119 { "vmsumuhs",  VXA(4,  39), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
2120 { "vmulesb",   VX(4,  776), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2121 { "vmulesh",   VX(4,  840), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2122 { "vmuleub",   VX(4,  520), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2123 { "vmuleuh",   VX(4,  584), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2124 { "vmulosb",   VX(4,  264), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2125 { "vmulosh",   VX(4,  328), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2126 { "vmuloub",   VX(4,    8), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2127 { "vmulouh",   VX(4,   72), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2128 { "vnmsubfp",  VXA(4,  47), VXA_MASK,   PPCVEC,         { VD, VA, VC, VB } },
2129 { "vnor",      VX(4, 1284), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2130 { "vor",       VX(4, 1156), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2131 { "vperm",     VXA(4,  43), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
2132 { "vpkpx",     VX(4,  782), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2133 { "vpkshss",   VX(4,  398), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2134 { "vpkshus",   VX(4,  270), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2135 { "vpkswss",   VX(4,  462), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2136 { "vpkswus",   VX(4,  334), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2137 { "vpkuhum",   VX(4,   14), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2138 { "vpkuhus",   VX(4,  142), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2139 { "vpkuwum",   VX(4,   78), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2140 { "vpkuwus",   VX(4,  206), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2141 { "vrefp",     VX(4,  266), VX_MASK,    PPCVEC,         { VD, VB } },
2142 { "vrfim",     VX(4,  714), VX_MASK,    PPCVEC,         { VD, VB } },
2143 { "vrfin",     VX(4,  522), VX_MASK,    PPCVEC,         { VD, VB } },
2144 { "vrfip",     VX(4,  650), VX_MASK,    PPCVEC,         { VD, VB } },
2145 { "vrfiz",     VX(4,  586), VX_MASK,    PPCVEC,         { VD, VB } },
2146 { "vrlb",      VX(4,    4), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2147 { "vrlh",      VX(4,   68), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2148 { "vrlw",      VX(4,  132), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2149 { "vrsqrtefp", VX(4,  330), VX_MASK,    PPCVEC,         { VD, VB } },
2150 { "vsel",      VXA(4,  42), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
2151 { "vsl",       VX(4,  452), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2152 { "vslb",      VX(4,  260), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2153 { "vsldoi",    VXA(4,  44), VXA_MASK,   PPCVEC,         { VD, VA, VB, SHB } },
2154 { "vslh",      VX(4,  324), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2155 { "vslo",      VX(4, 1036), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2156 { "vslw",      VX(4,  388), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2157 { "vspltb",    VX(4,  524), VX_MASK,    PPCVEC,         { VD, VB, UIMM } },
2158 { "vsplth",    VX(4,  588), VX_MASK,    PPCVEC,         { VD, VB, UIMM } },
2159 { "vspltisb",  VX(4,  780), VX_MASK,    PPCVEC,         { VD, SIMM } },
2160 { "vspltish",  VX(4,  844), VX_MASK,    PPCVEC,         { VD, SIMM } },
2161 { "vspltisw",  VX(4,  908), VX_MASK,    PPCVEC,         { VD, SIMM } },
2162 { "vspltw",    VX(4,  652), VX_MASK,    PPCVEC,         { VD, VB, UIMM } },
2163 { "vsr",       VX(4,  708), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2164 { "vsrab",     VX(4,  772), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2165 { "vsrah",     VX(4,  836), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2166 { "vsraw",     VX(4,  900), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2167 { "vsrb",      VX(4,  516), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2168 { "vsrh",      VX(4,  580), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2169 { "vsro",      VX(4, 1100), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2170 { "vsrw",      VX(4,  644), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2171 { "vsubcuw",   VX(4, 1408), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2172 { "vsubfp",    VX(4,   74), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2173 { "vsubsbs",   VX(4, 1792), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2174 { "vsubshs",   VX(4, 1856), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2175 { "vsubsws",   VX(4, 1920), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2176 { "vsububm",   VX(4, 1024), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2177 { "vsububs",   VX(4, 1536), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2178 { "vsubuhm",   VX(4, 1088), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2179 { "vsubuhs",   VX(4, 1600), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2180 { "vsubuwm",   VX(4, 1152), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2181 { "vsubuws",   VX(4, 1664), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2182 { "vsumsws",   VX(4, 1928), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2183 { "vsum2sws",  VX(4, 1672), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2184 { "vsum4sbs",  VX(4, 1800), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2185 { "vsum4shs",  VX(4, 1608), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2186 { "vsum4ubs",  VX(4, 1544), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2187 { "vupkhpx",   VX(4,  846), VX_MASK,    PPCVEC,         { VD, VB } },
2188 { "vupkhsb",   VX(4,  526), VX_MASK,    PPCVEC,         { VD, VB } },
2189 { "vupkhsh",   VX(4,  590), VX_MASK,    PPCVEC,         { VD, VB } },
2190 { "vupklpx",   VX(4,  974), VX_MASK,    PPCVEC,         { VD, VB } },
2191 { "vupklsb",   VX(4,  654), VX_MASK,    PPCVEC,         { VD, VB } },
2192 { "vupklsh",   VX(4,  718), VX_MASK,    PPCVEC,         { VD, VB } },
2193 { "vxor",      VX(4, 1220), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2194
2195 { "evaddw",    VX(4, 512), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2196 { "evaddiw",   VX(4, 514), VX_MASK,     PPCSPE,         { RS, RB, UIMM } },
2197 { "evsubfw",   VX(4, 516), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2198 { "evsubw",    VX(4, 516), VX_MASK,     PPCSPE,         { RS, RB, RA } },
2199 { "evsubifw",  VX(4, 518), VX_MASK,     PPCSPE,         { RS, UIMM, RB } },
2200 { "evsubiw",   VX(4, 518), VX_MASK,     PPCSPE,         { RS, RB, UIMM } },
2201 { "evabs",     VX(4, 520), VX_MASK,     PPCSPE,         { RS, RA } },
2202 { "evneg",     VX(4, 521), VX_MASK,     PPCSPE,         { RS, RA } },
2203 { "evextsb",   VX(4, 522), VX_MASK,     PPCSPE,         { RS, RA } },
2204 { "evextsh",   VX(4, 523), VX_MASK,     PPCSPE,         { RS, RA } },
2205 { "evrndw",    VX(4, 524), VX_MASK,     PPCSPE,         { RS, RA } },
2206 { "evcntlzw",  VX(4, 525), VX_MASK,     PPCSPE,         { RS, RA } },
2207 { "evcntlsw",  VX(4, 526), VX_MASK,     PPCSPE,         { RS, RA } },
2208
2209 { "brinc",     VX(4, 527), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2210
2211 { "evand",     VX(4, 529), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2212 { "evandc",    VX(4, 530), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2213 { "evmr",      VX(4, 535), VX_MASK,     PPCSPE,         { RS, RA, BBA } },
2214 { "evor",      VX(4, 535), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2215 { "evorc",     VX(4, 539), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2216 { "evxor",     VX(4, 534), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2217 { "eveqv",     VX(4, 537), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2218 { "evnand",    VX(4, 542), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2219 { "evnot",     VX(4, 536), VX_MASK,     PPCSPE,         { RS, RA, BBA } },
2220 { "evnor",     VX(4, 536), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2221
2222 { "evrlw",     VX(4, 552), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2223 { "evrlwi",    VX(4, 554), VX_MASK,     PPCSPE,         { RS, RA, EVUIMM } },
2224 { "evslw",     VX(4, 548), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2225 { "evslwi",    VX(4, 550), VX_MASK,     PPCSPE,         { RS, RA, EVUIMM } },
2226 { "evsrws",    VX(4, 545), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2227 { "evsrwu",    VX(4, 544), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2228 { "evsrwis",   VX(4, 547), VX_MASK,     PPCSPE,         { RS, RA, EVUIMM } },
2229 { "evsrwiu",   VX(4, 546), VX_MASK,     PPCSPE,         { RS, RA, EVUIMM } },
2230 { "evsplati",  VX(4, 553), VX_MASK,     PPCSPE,         { RS, SIMM } },
2231 { "evsplatfi", VX(4, 555), VX_MASK,     PPCSPE,         { RS, SIMM } },
2232 { "evmergehi", VX(4, 556), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2233 { "evmergelo", VX(4, 557), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2234 { "evmergehilo",VX(4,558), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2235 { "evmergelohi",VX(4,559), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2236
2237 { "evcmpgts",  VX(4, 561), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
2238 { "evcmpgtu",  VX(4, 560), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
2239 { "evcmplts",  VX(4, 563), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
2240 { "evcmpltu",  VX(4, 562), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
2241 { "evcmpeq",   VX(4, 564), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
2242 { "evsel",     EVSEL(4,79),EVSEL_MASK,  PPCSPE,         { RS, RA, RB, CRFS } },
2243
2244 { "evldd",     VX(4, 769), VX_MASK,     PPCSPE,         { RS, EVUIMM_8, RA } },
2245 { "evlddx",    VX(4, 768), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2246 { "evldw",     VX(4, 771), VX_MASK,     PPCSPE,         { RS, EVUIMM_8, RA } },
2247 { "evldwx",    VX(4, 770), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2248 { "evldh",     VX(4, 773), VX_MASK,     PPCSPE,         { RS, EVUIMM_8, RA } },
2249 { "evldhx",    VX(4, 772), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2250 { "evlwhe",    VX(4, 785), VX_MASK,     PPCSPE,         { RS, EVUIMM_4, RA } },
2251 { "evlwhex",   VX(4, 784), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2252 { "evlwhou",   VX(4, 789), VX_MASK,     PPCSPE,         { RS, EVUIMM_4, RA } },
2253 { "evlwhoux",  VX(4, 788), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2254 { "evlwhos",   VX(4, 791), VX_MASK,     PPCSPE,         { RS, EVUIMM_4, RA } },
2255 { "evlwhosx",  VX(4, 790), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2256 { "evlwwsplat",VX(4, 793), VX_MASK,     PPCSPE,         { RS, EVUIMM_4, RA } },
2257 { "evlwwsplatx",VX(4, 792), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2258 { "evlwhsplat",VX(4, 797), VX_MASK,     PPCSPE,         { RS, EVUIMM_4, RA } },
2259 { "evlwhsplatx",VX(4, 796), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2260 { "evlhhesplat",VX(4, 777), VX_MASK,    PPCSPE,         { RS, EVUIMM_2, RA } },
2261 { "evlhhesplatx",VX(4, 776), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2262 { "evlhhousplat",VX(4, 781), VX_MASK,   PPCSPE,         { RS, EVUIMM_2, RA } },
2263 { "evlhhousplatx",VX(4, 780), VX_MASK,  PPCSPE,         { RS, RA, RB } },
2264 { "evlhhossplat",VX(4, 783), VX_MASK,   PPCSPE,         { RS, EVUIMM_2, RA } },
2265 { "evlhhossplatx",VX(4, 782), VX_MASK,  PPCSPE,         { RS, RA, RB } },
2266
2267 { "evstdd",    VX(4, 801), VX_MASK,     PPCSPE,         { RS, EVUIMM_8, RA } },
2268 { "evstddx",   VX(4, 800), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2269 { "evstdw",    VX(4, 803), VX_MASK,     PPCSPE,         { RS, EVUIMM_8, RA } },
2270 { "evstdwx",   VX(4, 802), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2271 { "evstdh",    VX(4, 805), VX_MASK,     PPCSPE,         { RS, EVUIMM_8, RA } },
2272 { "evstdhx",   VX(4, 804), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2273 { "evstwwe",   VX(4, 825), VX_MASK,     PPCSPE,         { RS, EVUIMM_4, RA } },
2274 { "evstwwex",  VX(4, 824), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2275 { "evstwwo",   VX(4, 829), VX_MASK,     PPCSPE,         { RS, EVUIMM_4, RA } },
2276 { "evstwwox",  VX(4, 828), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2277 { "evstwhe",   VX(4, 817), VX_MASK,     PPCSPE,         { RS, EVUIMM_4, RA } },
2278 { "evstwhex",  VX(4, 816), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2279 { "evstwho",   VX(4, 821), VX_MASK,     PPCSPE,         { RS, EVUIMM_4, RA } },
2280 { "evstwhox",  VX(4, 820), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2281
2282 { "evfsabs",   VX(4, 644), VX_MASK,     PPCSPE,         { RS, RA } },
2283 { "evfsnabs",  VX(4, 645), VX_MASK,     PPCSPE,         { RS, RA } },
2284 { "evfsneg",   VX(4, 646), VX_MASK,     PPCSPE,         { RS, RA } },
2285 { "evfsadd",   VX(4, 640), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2286 { "evfssub",   VX(4, 641), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2287 { "evfsmul",   VX(4, 648), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2288 { "evfsdiv",   VX(4, 649), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2289 { "evfscmpgt", VX(4, 652), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
2290 { "evfscmplt", VX(4, 653), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
2291 { "evfscmpeq", VX(4, 654), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
2292 { "evfststgt", VX(4, 668), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
2293 { "evfststlt", VX(4, 669), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
2294 { "evfststeq", VX(4, 670), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
2295 { "evfscfui",  VX(4, 656), VX_MASK,     PPCSPE,         { RS, RB } },
2296 { "evfsctuiz", VX(4, 664), VX_MASK,     PPCSPE,         { RS, RB } },
2297 { "evfscfsi",  VX(4, 657), VX_MASK,     PPCSPE,         { RS, RB } },
2298 { "evfscfuf",  VX(4, 658), VX_MASK,     PPCSPE,         { RS, RB } },
2299 { "evfscfsf",  VX(4, 659), VX_MASK,     PPCSPE,         { RS, RB } },
2300 { "evfsctui",  VX(4, 660), VX_MASK,     PPCSPE,         { RS, RB } },
2301 { "evfsctsi",  VX(4, 661), VX_MASK,     PPCSPE,         { RS, RB } },
2302 { "evfsctsiz", VX(4, 666), VX_MASK,     PPCSPE,         { RS, RB } },
2303 { "evfsctuf",  VX(4, 662), VX_MASK,     PPCSPE,         { RS, RB } },
2304 { "evfsctsf",  VX(4, 663), VX_MASK,     PPCSPE,         { RS, RB } },
2305
2306 { "efsabs",   VX(4, 708), VX_MASK,      PPCEFS,         { RS, RA } },
2307 { "efsnabs",  VX(4, 709), VX_MASK,      PPCEFS,         { RS, RA } },
2308 { "efsneg",   VX(4, 710), VX_MASK,      PPCEFS,         { RS, RA } },
2309 { "efsadd",   VX(4, 704), VX_MASK,      PPCEFS,         { RS, RA, RB } },
2310 { "efssub",   VX(4, 705), VX_MASK,      PPCEFS,         { RS, RA, RB } },
2311 { "efsmul",   VX(4, 712), VX_MASK,      PPCEFS,         { RS, RA, RB } },
2312 { "efsdiv",   VX(4, 713), VX_MASK,      PPCEFS,         { RS, RA, RB } },
2313 { "efscmpgt", VX(4, 716), VX_MASK,      PPCEFS,         { CRFD, RA, RB } },
2314 { "efscmplt", VX(4, 717), VX_MASK,      PPCEFS,         { CRFD, RA, RB } },
2315 { "efscmpeq", VX(4, 718), VX_MASK,      PPCEFS,         { CRFD, RA, RB } },
2316 { "efststgt", VX(4, 732), VX_MASK,      PPCEFS,         { CRFD, RA, RB } },
2317 { "efststlt", VX(4, 733), VX_MASK,      PPCEFS,         { CRFD, RA, RB } },
2318 { "efststeq", VX(4, 734), VX_MASK,      PPCEFS,         { CRFD, RA, RB } },
2319 { "efscfui",  VX(4, 720), VX_MASK,      PPCEFS,         { RS, RB } },
2320 { "efsctuiz", VX(4, 728), VX_MASK,      PPCEFS,         { RS, RB } },
2321 { "efscfsi",  VX(4, 721), VX_MASK,      PPCEFS,         { RS, RB } },
2322 { "efscfuf",  VX(4, 722), VX_MASK,      PPCEFS,         { RS, RB } },
2323 { "efscfsf",  VX(4, 723), VX_MASK,      PPCEFS,         { RS, RB } },
2324 { "efsctui",  VX(4, 724), VX_MASK,      PPCEFS,         { RS, RB } },
2325 { "efsctsi",  VX(4, 725), VX_MASK,      PPCEFS,         { RS, RB } },
2326 { "efsctsiz", VX(4, 730), VX_MASK,      PPCEFS,         { RS, RB } },
2327 { "efsctuf",  VX(4, 726), VX_MASK,      PPCEFS,         { RS, RB } },
2328 { "efsctsf",  VX(4, 727), VX_MASK,      PPCEFS,         { RS, RB } },
2329
2330 { "evmhossf",  VX(4, 1031), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2331 { "evmhossfa", VX(4, 1063), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2332 { "evmhosmf",  VX(4, 1039), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2333 { "evmhosmfa", VX(4, 1071), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2334 { "evmhosmi",  VX(4, 1037), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2335 { "evmhosmia", VX(4, 1069), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2336 { "evmhoumi",  VX(4, 1036), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2337 { "evmhoumia", VX(4, 1068), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2338 { "evmhessf",  VX(4, 1027), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2339 { "evmhessfa", VX(4, 1059), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2340 { "evmhesmf",  VX(4, 1035), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2341 { "evmhesmfa", VX(4, 1067), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2342 { "evmhesmi",  VX(4, 1033), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2343 { "evmhesmia", VX(4, 1065), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2344 { "evmheumi",  VX(4, 1032), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2345 { "evmheumia", VX(4, 1064), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2346
2347 { "evmhossfaaw",VX(4, 1287), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2348 { "evmhossiaaw",VX(4, 1285), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2349 { "evmhosmfaaw",VX(4, 1295), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2350 { "evmhosmiaaw",VX(4, 1293), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2351 { "evmhousiaaw",VX(4, 1284), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2352 { "evmhoumiaaw",VX(4, 1292), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2353 { "evmhessfaaw",VX(4, 1283), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2354 { "evmhessiaaw",VX(4, 1281), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2355 { "evmhesmfaaw",VX(4, 1291), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2356 { "evmhesmiaaw",VX(4, 1289), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2357 { "evmheusiaaw",VX(4, 1280), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2358 { "evmheumiaaw",VX(4, 1288), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2359
2360 { "evmhossfanw",VX(4, 1415), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2361 { "evmhossianw",VX(4, 1413), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2362 { "evmhosmfanw",VX(4, 1423), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2363 { "evmhosmianw",VX(4, 1421), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2364 { "evmhousianw",VX(4, 1412), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2365 { "evmhoumianw",VX(4, 1420), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2366 { "evmhessfanw",VX(4, 1411), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2367 { "evmhessianw",VX(4, 1409), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2368 { "evmhesmfanw",VX(4, 1419), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2369 { "evmhesmianw",VX(4, 1417), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2370 { "evmheusianw",VX(4, 1408), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2371 { "evmheumianw",VX(4, 1416), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2372
2373 { "evmhogsmfaa",VX(4, 1327), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2374 { "evmhogsmiaa",VX(4, 1325), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2375 { "evmhogumiaa",VX(4, 1324), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2376 { "evmhegsmfaa",VX(4, 1323), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2377 { "evmhegsmiaa",VX(4, 1321), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2378 { "evmhegumiaa",VX(4, 1320), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2379
2380 { "evmhogsmfan",VX(4, 1455), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2381 { "evmhogsmian",VX(4, 1453), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2382 { "evmhogumian",VX(4, 1452), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2383 { "evmhegsmfan",VX(4, 1451), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2384 { "evmhegsmian",VX(4, 1449), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2385 { "evmhegumian",VX(4, 1448), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2386
2387 { "evmwhssf",  VX(4, 1095), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2388 { "evmwhssfa", VX(4, 1127), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2389 { "evmwhsmf",  VX(4, 1103), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2390 { "evmwhsmfa", VX(4, 1135), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2391 { "evmwhsmi",  VX(4, 1101), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2392 { "evmwhsmia", VX(4, 1133), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2393 { "evmwhumi",  VX(4, 1100), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2394 { "evmwhumia", VX(4, 1132), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2395
2396 { "evmwlumi",  VX(4, 1096), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2397 { "evmwlumia", VX(4, 1128), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2398
2399 { "evmwlssiaaw",VX(4, 1345), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2400 { "evmwlsmiaaw",VX(4, 1353), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2401 { "evmwlusiaaw",VX(4, 1344), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2402 { "evmwlumiaaw",VX(4, 1352), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2403
2404 { "evmwlssianw",VX(4, 1473), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2405 { "evmwlsmianw",VX(4, 1481), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2406 { "evmwlusianw",VX(4, 1472), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2407 { "evmwlumianw",VX(4, 1480), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2408
2409 { "evmwssf",   VX(4, 1107), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2410 { "evmwssfa",  VX(4, 1139), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2411 { "evmwsmf",   VX(4, 1115), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2412 { "evmwsmfa",  VX(4, 1147), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2413 { "evmwsmi",   VX(4, 1113), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2414 { "evmwsmia",  VX(4, 1145), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2415 { "evmwumi",   VX(4, 1112), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2416 { "evmwumia",  VX(4, 1144), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2417
2418 { "evmwssfaa", VX(4, 1363), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2419 { "evmwsmfaa", VX(4, 1371), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2420 { "evmwsmiaa", VX(4, 1369), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2421 { "evmwumiaa", VX(4, 1368), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2422
2423 { "evmwssfan", VX(4, 1491), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2424 { "evmwsmfan", VX(4, 1499), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2425 { "evmwsmian", VX(4, 1497), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2426 { "evmwumian", VX(4, 1496), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2427
2428 { "evaddssiaaw",VX(4, 1217), VX_MASK,   PPCSPE,         { RS, RA } },
2429 { "evaddsmiaaw",VX(4, 1225), VX_MASK,   PPCSPE,         { RS, RA } },
2430 { "evaddusiaaw",VX(4, 1216), VX_MASK,   PPCSPE,         { RS, RA } },
2431 { "evaddumiaaw",VX(4, 1224), VX_MASK,   PPCSPE,         { RS, RA } },
2432
2433 { "evsubfssiaaw",VX(4, 1219), VX_MASK,  PPCSPE,         { RS, RA } },
2434 { "evsubfsmiaaw",VX(4, 1227), VX_MASK,  PPCSPE,         { RS, RA } },
2435 { "evsubfusiaaw",VX(4, 1218), VX_MASK,  PPCSPE,         { RS, RA } },
2436 { "evsubfumiaaw",VX(4, 1226), VX_MASK,  PPCSPE,         { RS, RA } },
2437
2438 { "evmra",    VX(4, 1220), VX_MASK,     PPCSPE,         { RS, RA } },
2439
2440 { "evdivws",  VX(4, 1222), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2441 { "evdivwu",  VX(4, 1223), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2442
2443 { "mulli",   OP(7),     OP_MASK,        PPCCOM,         { RT, RA, SI } },
2444 { "muli",    OP(7),     OP_MASK,        PWRCOM,         { RT, RA, SI } },
2445
2446 { "subfic",  OP(8),     OP_MASK,        PPCCOM,         { RT, RA, SI } },
2447 { "sfi",     OP(8),     OP_MASK,        PWRCOM,         { RT, RA, SI } },
2448
2449 { "dozi",    OP(9),     OP_MASK,        M601,           { RT, RA, SI } },
2450
2451 { "bce",     B(9,0,0),  B_MASK,         BOOKE64,        { BO, BI, BD } },
2452 { "bcel",    B(9,0,1),  B_MASK,         BOOKE64,        { BO, BI, BD } },
2453 { "bcea",    B(9,1,0),  B_MASK,         BOOKE64,        { BO, BI, BDA } },
2454 { "bcela",   B(9,1,1),  B_MASK,         BOOKE64,        { BO, BI, BDA } },
2455
2456 { "cmplwi",  OPL(10,0), OPL_MASK,       PPCCOM,         { OBF, RA, UI } },
2457 { "cmpldi",  OPL(10,1), OPL_MASK,       PPC64,          { OBF, RA, UI } },
2458 { "cmpli",   OP(10),    OP_MASK,        PPC,            { BF, L, RA, UI } },
2459 { "cmpli",   OP(10),    OP_MASK,        PWRCOM,         { BF, RA, UI } },
2460
2461 { "cmpwi",   OPL(11,0), OPL_MASK,       PPCCOM,         { OBF, RA, SI } },
2462 { "cmpdi",   OPL(11,1), OPL_MASK,       PPC64,          { OBF, RA, SI } },
2463 { "cmpi",    OP(11),    OP_MASK,        PPC,            { BF, L, RA, SI } },
2464 { "cmpi",    OP(11),    OP_MASK,        PWRCOM,         { BF, RA, SI } },
2465
2466 { "addic",   OP(12),    OP_MASK,        PPCCOM,         { RT, RA, SI } },
2467 { "ai",      OP(12),    OP_MASK,        PWRCOM,         { RT, RA, SI } },
2468 { "subic",   OP(12),    OP_MASK,        PPCCOM,         { RT, RA, NSI } },
2469
2470 { "addic.",  OP(13),    OP_MASK,        PPCCOM,         { RT, RA, SI } },
2471 { "ai.",     OP(13),    OP_MASK,        PWRCOM,         { RT, RA, SI } },
2472 { "subic.",  OP(13),    OP_MASK,        PPCCOM,         { RT, RA, NSI } },
2473
2474 { "li",      OP(14),    DRA_MASK,       PPCCOM,         { RT, SI } },
2475 { "lil",     OP(14),    DRA_MASK,       PWRCOM,         { RT, SI } },
2476 { "addi",    OP(14),    OP_MASK,        PPCCOM,         { RT, RA0, SI } },
2477 { "cal",     OP(14),    OP_MASK,        PWRCOM,         { RT, D, RA0 } },
2478 { "subi",    OP(14),    OP_MASK,        PPCCOM,         { RT, RA0, NSI } },
2479 { "la",      OP(14),    OP_MASK,        PPCCOM,         { RT, D, RA0 } },
2480
2481 { "lis",     OP(15),    DRA_MASK,       PPCCOM,         { RT, SISIGNOPT } },
2482 { "liu",     OP(15),    DRA_MASK,       PWRCOM,         { RT, SISIGNOPT } },
2483 { "addis",   OP(15),    OP_MASK,        PPCCOM,         { RT,RA0,SISIGNOPT } },
2484 { "cau",     OP(15),    OP_MASK,        PWRCOM,         { RT,RA0,SISIGNOPT } },
2485 { "subis",   OP(15),    OP_MASK,        PPCCOM,         { RT, RA0, NSI } },
2486
2487 { "bdnz-",   BBO(16,BODNZ,0,0),      BBOATBI_MASK, PPCCOM,      { BDM } },
2488 { "bdnz+",   BBO(16,BODNZ,0,0),      BBOATBI_MASK, PPCCOM,      { BDP } },
2489 { "bdnz",    BBO(16,BODNZ,0,0),      BBOATBI_MASK, PPCCOM,      { BD } },
2490 { "bdn",     BBO(16,BODNZ,0,0),      BBOATBI_MASK, PWRCOM,      { BD } },
2491 { "bdnzl-",  BBO(16,BODNZ,0,1),      BBOATBI_MASK, PPCCOM,      { BDM } },
2492 { "bdnzl+",  BBO(16,BODNZ,0,1),      BBOATBI_MASK, PPCCOM,      { BDP } },
2493 { "bdnzl",   BBO(16,BODNZ,0,1),      BBOATBI_MASK, PPCCOM,      { BD } },
2494 { "bdnl",    BBO(16,BODNZ,0,1),      BBOATBI_MASK, PWRCOM,      { BD } },
2495 { "bdnza-",  BBO(16,BODNZ,1,0),      BBOATBI_MASK, PPCCOM,      { BDMA } },
2496 { "bdnza+",  BBO(16,BODNZ,1,0),      BBOATBI_MASK, PPCCOM,      { BDPA } },
2497 { "bdnza",   BBO(16,BODNZ,1,0),      BBOATBI_MASK, PPCCOM,      { BDA } },
2498 { "bdna",    BBO(16,BODNZ,1,0),      BBOATBI_MASK, PWRCOM,      { BDA } },
2499 { "bdnzla-", BBO(16,BODNZ,1,1),      BBOATBI_MASK, PPCCOM,      { BDMA } },
2500 { "bdnzla+", BBO(16,BODNZ,1,1),      BBOATBI_MASK, PPCCOM,      { BDPA } },
2501 { "bdnzla",  BBO(16,BODNZ,1,1),      BBOATBI_MASK, PPCCOM,      { BDA } },
2502 { "bdnla",   BBO(16,BODNZ,1,1),      BBOATBI_MASK, PWRCOM,      { BDA } },
2503 { "bdz-",    BBO(16,BODZ,0,0),       BBOATBI_MASK, PPCCOM,      { BDM } },
2504 { "bdz+",    BBO(16,BODZ,0,0),       BBOATBI_MASK, PPCCOM,      { BDP } },
2505 { "bdz",     BBO(16,BODZ,0,0),       BBOATBI_MASK, COM,         { BD } },
2506 { "bdzl-",   BBO(16,BODZ,0,1),       BBOATBI_MASK, PPCCOM,      { BDM } },
2507 { "bdzl+",   BBO(16,BODZ,0,1),       BBOATBI_MASK, PPCCOM,      { BDP } },
2508 { "bdzl",    BBO(16,BODZ,0,1),       BBOATBI_MASK, COM,         { BD } },
2509 { "bdza-",   BBO(16,BODZ,1,0),       BBOATBI_MASK, PPCCOM,      { BDMA } },
2510 { "bdza+",   BBO(16,BODZ,1,0),       BBOATBI_MASK, PPCCOM,      { BDPA } },
2511 { "bdza",    BBO(16,BODZ,1,0),       BBOATBI_MASK, COM,         { BDA } },
2512 { "bdzla-",  BBO(16,BODZ,1,1),       BBOATBI_MASK, PPCCOM,      { BDMA } },
2513 { "bdzla+",  BBO(16,BODZ,1,1),       BBOATBI_MASK, PPCCOM,      { BDPA } },
2514 { "bdzla",   BBO(16,BODZ,1,1),       BBOATBI_MASK, COM,         { BDA } },
2515 { "blt-",    BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2516 { "blt+",    BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2517 { "blt",     BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM,         { CR, BD } },
2518 { "bltl-",   BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2519 { "bltl+",   BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2520 { "bltl",    BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, COM,         { CR, BD } },
2521 { "blta-",   BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2522 { "blta+",   BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2523 { "blta",    BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
2524 { "bltla-",  BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2525 { "bltla+",  BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2526 { "bltla",   BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
2527 { "bgt-",    BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2528 { "bgt+",    BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2529 { "bgt",     BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, COM,         { CR, BD } },
2530 { "bgtl-",   BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2531 { "bgtl+",   BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2532 { "bgtl",    BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, COM,         { CR, BD } },
2533 { "bgta-",   BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2534 { "bgta+",   BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2535 { "bgta",    BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
2536 { "bgtla-",  BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2537 { "bgtla+",  BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2538 { "bgtla",   BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
2539 { "beq-",    BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2540 { "beq+",    BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2541 { "beq",     BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, COM,         { CR, BD } },
2542 { "beql-",   BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2543 { "beql+",   BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2544 { "beql",    BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, COM,         { CR, BD } },
2545 { "beqa-",   BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2546 { "beqa+",   BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2547 { "beqa",    BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
2548 { "beqla-",  BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2549 { "beqla+",  BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2550 { "beqla",   BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
2551 { "bso-",    BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2552 { "bso+",    BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2553 { "bso",     BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, COM,         { CR, BD } },
2554 { "bsol-",   BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2555 { "bsol+",   BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2556 { "bsol",    BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, COM,         { CR, BD } },
2557 { "bsoa-",   BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2558 { "bsoa+",   BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2559 { "bsoa",    BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
2560 { "bsola-",  BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2561 { "bsola+",  BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2562 { "bsola",   BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
2563 { "bun-",    BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2564 { "bun+",    BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2565 { "bun",     BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BD } },
2566 { "bunl-",   BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2567 { "bunl+",   BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2568 { "bunl",    BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BD } },
2569 { "buna-",   BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2570 { "buna+",   BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2571 { "buna",    BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDA } },
2572 { "bunla-",  BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2573 { "bunla+",  BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2574 { "bunla",   BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDA } },
2575 { "bge-",    BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2576 { "bge+",    BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2577 { "bge",     BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM,         { CR, BD } },
2578 { "bgel-",   BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2579 { "bgel+",   BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2580 { "bgel",    BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM,         { CR, BD } },
2581 { "bgea-",   BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2582 { "bgea+",   BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2583 { "bgea",    BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
2584 { "bgela-",  BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2585 { "bgela+",  BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2586 { "bgela",   BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
2587 { "bnl-",    BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2588 { "bnl+",    BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2589 { "bnl",     BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM,         { CR, BD } },
2590 { "bnll-",   BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2591 { "bnll+",   BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2592 { "bnll",    BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM,         { CR, BD } },
2593 { "bnla-",   BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2594 { "bnla+",   BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2595 { "bnla",    BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
2596 { "bnlla-",  BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2597 { "bnlla+",  BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2598 { "bnlla",   BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
2599 { "ble-",    BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2600 { "ble+",    BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2601 { "ble",     BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM,         { CR, BD } },
2602 { "blel-",   BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2603 { "blel+",   BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2604 { "blel",    BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM,         { CR, BD } },
2605 { "blea-",   BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2606 { "blea+",   BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2607 { "blea",    BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
2608 { "blela-",  BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2609 { "blela+",  BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2610 { "blela",   BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
2611 { "bng-",    BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2612 { "bng+",    BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2613 { "bng",     BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM,         { CR, BD } },
2614 { "bngl-",   BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2615 { "bngl+",   BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2616 { "bngl",    BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM,         { CR, BD } },
2617 { "bnga-",   BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2618 { "bnga+",   BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2619 { "bnga",    BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
2620 { "bngla-",  BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2621 { "bngla+",  BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2622 { "bngla",   BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
2623 { "bne-",    BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2624 { "bne+",    BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2625 { "bne",     BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, COM,         { CR, BD } },
2626 { "bnel-",   BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2627 { "bnel+",   BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2628 { "bnel",    BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, COM,         { CR, BD } },
2629 { "bnea-",   BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2630 { "bnea+",   BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2631 { "bnea",    BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
2632 { "bnela-",  BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2633 { "bnela+",  BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2634 { "bnela",   BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
2635 { "bns-",    BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2636 { "bns+",    BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2637 { "bns",     BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, COM,         { CR, BD } },
2638 { "bnsl-",   BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2639 { "bnsl+",   BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2640 { "bnsl",    BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, COM,         { CR, BD } },
2641 { "bnsa-",   BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2642 { "bnsa+",   BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2643 { "bnsa",    BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
2644 { "bnsla-",  BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2645 { "bnsla+",  BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2646 { "bnsla",   BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
2647 { "bnu-",    BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2648 { "bnu+",    BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2649 { "bnu",     BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BD } },
2650 { "bnul-",   BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2651 { "bnul+",   BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2652 { "bnul",    BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BD } },
2653 { "bnua-",   BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2654 { "bnua+",   BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2655 { "bnua",    BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDA } },
2656 { "bnula-",  BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2657 { "bnula+",  BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2658 { "bnula",   BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDA } },
2659 { "bdnzt-",  BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4,   { BI, BDM } },
2660 { "bdnzt+",  BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4,   { BI, BDP } },
2661 { "bdnzt",   BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM,     { BI, BD } },
2662 { "bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4,   { BI, BDM } },
2663 { "bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4,   { BI, BDP } },
2664 { "bdnztl",  BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM,     { BI, BD } },
2665 { "bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4,   { BI, BDMA } },
2666 { "bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4,   { BI, BDPA } },
2667 { "bdnzta",  BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM,     { BI, BDA } },
2668 { "bdnztla-",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4,   { BI, BDMA } },
2669 { "bdnztla+",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4,   { BI, BDPA } },
2670 { "bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM,     { BI, BDA } },
2671 { "bdnzf-",  BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4,   { BI, BDM } },
2672 { "bdnzf+",  BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4,   { BI, BDP } },
2673 { "bdnzf",   BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM,     { BI, BD } },
2674 { "bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4,   { BI, BDM } },
2675 { "bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4,   { BI, BDP } },
2676 { "bdnzfl",  BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM,     { BI, BD } },
2677 { "bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4,   { BI, BDMA } },
2678 { "bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4,   { BI, BDPA } },
2679 { "bdnzfa",  BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM,     { BI, BDA } },
2680 { "bdnzfla-",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4,   { BI, BDMA } },
2681 { "bdnzfla+",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4,   { BI, BDPA } },
2682 { "bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM,     { BI, BDA } },
2683 { "bt-",     BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM,       { BI, BDM } },
2684 { "bt+",     BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM,       { BI, BDP } },
2685 { "bt",      BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM,       { BI, BD } },
2686 { "bbt",     BBO(16,BOT,0,0), BBOAT_MASK, PWRCOM,       { BI, BD } },
2687 { "btl-",    BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM,       { BI, BDM } },
2688 { "btl+",    BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM,       { BI, BDP } },
2689 { "btl",     BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM,       { BI, BD } },
2690 { "bbtl",    BBO(16,BOT,0,1), BBOAT_MASK, PWRCOM,       { BI, BD } },
2691 { "bta-",    BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM,       { BI, BDMA } },
2692 { "bta+",    BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM,       { BI, BDPA } },
2693 { "bta",     BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM,       { BI, BDA } },
2694 { "bbta",    BBO(16,BOT,1,0), BBOAT_MASK, PWRCOM,       { BI, BDA } },
2695 { "btla-",   BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM,       { BI, BDMA } },
2696 { "btla+",   BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM,       { BI, BDPA } },
2697 { "btla",    BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM,       { BI, BDA } },
2698 { "bbtla",   BBO(16,BOT,1,1), BBOAT_MASK, PWRCOM,       { BI, BDA } },
2699 { "bf-",     BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM,       { BI, BDM } },
2700 { "bf+",     BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM,       { BI, BDP } },
2701 { "bf",      BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM,       { BI, BD } },
2702 { "bbf",     BBO(16,BOF,0,0), BBOAT_MASK, PWRCOM,       { BI, BD } },
2703 { "bfl-",    BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM,       { BI, BDM } },
2704 { "bfl+",    BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM,       { BI, BDP } },
2705 { "bfl",     BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM,       { BI, BD } },
2706 { "bbfl",    BBO(16,BOF,0,1), BBOAT_MASK, PWRCOM,       { BI, BD } },
2707 { "bfa-",    BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM,       { BI, BDMA } },
2708 { "bfa+",    BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM,       { BI, BDPA } },
2709 { "bfa",     BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM,       { BI, BDA } },
2710 { "bbfa",    BBO(16,BOF,1,0), BBOAT_MASK, PWRCOM,       { BI, BDA } },
2711 { "bfla-",   BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM,       { BI, BDMA } },
2712 { "bfla+",   BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM,       { BI, BDPA } },
2713 { "bfla",    BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM,       { BI, BDA } },
2714 { "bbfla",   BBO(16,BOF,1,1), BBOAT_MASK, PWRCOM,       { BI, BDA } },
2715 { "bdzt-",   BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4,    { BI, BDM } },
2716 { "bdzt+",   BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4,    { BI, BDP } },
2717 { "bdzt",    BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM,      { BI, BD } },
2718 { "bdztl-",  BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4,    { BI, BDM } },
2719 { "bdztl+",  BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4,    { BI, BDP } },
2720 { "bdztl",   BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM,      { BI, BD } },
2721 { "bdzta-",  BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4,    { BI, BDMA } },
2722 { "bdzta+",  BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4,    { BI, BDPA } },
2723 { "bdzta",   BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM,      { BI, BDA } },
2724 { "bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4,    { BI, BDMA } },
2725 { "bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4,    { BI, BDPA } },
2726 { "bdztla",  BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM,      { BI, BDA } },
2727 { "bdzf-",   BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4,    { BI, BDM } },
2728 { "bdzf+",   BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4,    { BI, BDP } },
2729 { "bdzf",    BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM,      { BI, BD } },
2730 { "bdzfl-",  BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4,    { BI, BDM } },
2731 { "bdzfl+",  BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4,    { BI, BDP } },
2732 { "bdzfl",   BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM,      { BI, BD } },
2733 { "bdzfa-",  BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4,    { BI, BDMA } },
2734 { "bdzfa+",  BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4,    { BI, BDPA } },
2735 { "bdzfa",   BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM,      { BI, BDA } },
2736 { "bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4,    { BI, BDMA } },
2737 { "bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4,    { BI, BDPA } },
2738 { "bdzfla",  BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM,      { BI, BDA } },
2739 { "bc-",     B(16,0,0), B_MASK,         PPCCOM,         { BOE, BI, BDM } },
2740 { "bc+",     B(16,0,0), B_MASK,         PPCCOM,         { BOE, BI, BDP } },
2741 { "bc",      B(16,0,0), B_MASK,         COM,            { BO, BI, BD } },
2742 { "bcl-",    B(16,0,1), B_MASK,         PPCCOM,         { BOE, BI, BDM } },
2743 { "bcl+",    B(16,0,1), B_MASK,         PPCCOM,         { BOE, BI, BDP } },
2744 { "bcl",     B(16,0,1), B_MASK,         COM,            { BO, BI, BD } },
2745 { "bca-",    B(16,1,0), B_MASK,         PPCCOM,         { BOE, BI, BDMA } },
2746 { "bca+",    B(16,1,0), B_MASK,         PPCCOM,         { BOE, BI, BDPA } },
2747 { "bca",     B(16,1,0), B_MASK,         COM,            { BO, BI, BDA } },
2748 { "bcla-",   B(16,1,1), B_MASK,         PPCCOM,         { BOE, BI, BDMA } },
2749 { "bcla+",   B(16,1,1), B_MASK,         PPCCOM,         { BOE, BI, BDPA } },
2750 { "bcla",    B(16,1,1), B_MASK,         COM,            { BO, BI, BDA } },
2751
2752 { "sc",      SC(17,1,0), 0xffffffff,    PPC,            { 0 } },
2753 { "svc",     SC(17,0,0), SC_MASK,       POWER,          { LEV, FL1, FL2 } },
2754 { "svcl",    SC(17,0,1), SC_MASK,       POWER,          { LEV, FL1, FL2 } },
2755 { "svca",    SC(17,1,0), SC_MASK,       PWRCOM,         { SV } },
2756 { "svcla",   SC(17,1,1), SC_MASK,       POWER,          { SV } },
2757
2758 { "b",       B(18,0,0), B_MASK,         COM,            { LI } },
2759 { "bl",      B(18,0,1), B_MASK,         COM,            { LI } },
2760 { "ba",      B(18,1,0), B_MASK,         COM,            { LIA } },
2761 { "bla",     B(18,1,1), B_MASK,         COM,            { LIA } },
2762
2763 { "mcrf",    XL(19,0),  XLBB_MASK|(3 << 21)|(3 << 16), COM,     { BF, BFA } },
2764
2765 { "blr",     XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM,   { 0 } },
2766 { "br",      XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM,   { 0 } },
2767 { "blrl",    XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM,   { 0 } },
2768 { "brl",     XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM,   { 0 } },
2769 { "bdnzlr",  XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
2770 { "bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, NOPOWER4,       { 0 } },
2771 { "bdnzlr-", XLO(19,BODNZM4,16,0), XLBOBIBB_MASK, POWER4,       { 0 } },
2772 { "bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, NOPOWER4,      { 0 } },
2773 { "bdnzlr+", XLO(19,BODNZP4,16,0), XLBOBIBB_MASK, POWER4,       { 0 } },
2774 { "bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
2775 { "bdnzlrl-",XLO(19,BODNZ,16,1), XLBOBIBB_MASK, NOPOWER4,       { 0 } },
2776 { "bdnzlrl-",XLO(19,BODNZM4,16,1), XLBOBIBB_MASK, POWER4,       { 0 } },
2777 { "bdnzlrl+",XLO(19,BODNZP,16,1), XLBOBIBB_MASK, NOPOWER4,      { 0 } },
2778 { "bdnzlrl+",XLO(19,BODNZP4,16,1), XLBOBIBB_MASK, POWER4,       { 0 } },
2779 { "bdzlr",   XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM,  { 0 } },
2780 { "bdzlr-",  XLO(19,BODZ,16,0), XLBOBIBB_MASK, NOPOWER4,        { 0 } },
2781 { "bdzlr-",  XLO(19,BODZM4,16,0), XLBOBIBB_MASK, POWER4,        { 0 } },
2782 { "bdzlr+",  XLO(19,BODZP,16,0), XLBOBIBB_MASK, NOPOWER4,       { 0 } },
2783 { "bdzlr+",  XLO(19,BODZP4,16,0), XLBOBIBB_MASK, POWER4,        { 0 } },
2784 { "bdzlrl",  XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM,  { 0 } },
2785 { "bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, NOPOWER4,        { 0 } },
2786 { "bdzlrl-", XLO(19,BODZM4,16,1), XLBOBIBB_MASK, POWER4,        { 0 } },
2787 { "bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, NOPOWER4,       { 0 } },
2788 { "bdzlrl+", XLO(19,BODZP4,16,1), XLBOBIBB_MASK, POWER4,        { 0 } },
2789 { "bltlr",   XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2790 { "bltlr-",  XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2791 { "bltlr-",  XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2792 { "bltlr+",  XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2793 { "bltlr+",  XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2794 { "bltr",    XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2795 { "bltlrl",  XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2796 { "bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2797 { "bltlrl-", XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2798 { "bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2799 { "bltlrl+", XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2800 { "bltrl",   XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2801 { "bgtlr",   XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2802 { "bgtlr-",  XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2803 { "bgtlr-",  XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2804 { "bgtlr+",  XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2805 { "bgtlr+",  XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2806 { "bgtr",    XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2807 { "bgtlrl",  XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2808 { "bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2809 { "bgtlrl-", XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2810 { "bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2811 { "bgtlrl+", XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2812 { "bgtrl",   XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2813 { "beqlr",   XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2814 { "beqlr-",  XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2815 { "beqlr-",  XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2816 { "beqlr+",  XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2817 { "beqlr+",  XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2818 { "beqr",    XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2819 { "beqlrl",  XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2820 { "beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2821 { "beqlrl-", XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2822 { "beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2823 { "beqlrl+", XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2824 { "beqrl",   XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2825 { "bsolr",   XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2826 { "bsolr-",  XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2827 { "bsolr-",  XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2828 { "bsolr+",  XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2829 { "bsolr+",  XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2830 { "bsor",    XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2831 { "bsolrl",  XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2832 { "bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2833 { "bsolrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2834 { "bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2835 { "bsolrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2836 { "bsorl",   XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2837 { "bunlr",   XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2838 { "bunlr-",  XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2839 { "bunlr-",  XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2840 { "bunlr+",  XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2841 { "bunlr+",  XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2842 { "bunlrl",  XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2843 { "bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2844 { "bunlrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2845 { "bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2846 { "bunlrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2847 { "bgelr",   XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2848 { "bgelr-",  XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2849 { "bgelr-",  XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2850 { "bgelr+",  XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2851 { "bgelr+",  XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2852 { "bger",    XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2853 { "bgelrl",  XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2854 { "bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2855 { "bgelrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2856 { "bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2857 { "bgelrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2858 { "bgerl",   XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2859 { "bnllr",   XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2860 { "bnllr-",  XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2861 { "bnllr-",  XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2862 { "bnllr+",  XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2863 { "bnllr+",  XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2864 { "bnlr",    XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2865 { "bnllrl",  XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2866 { "bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2867 { "bnllrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2868 { "bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2869 { "bnllrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2870 { "bnlrl",   XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2871 { "blelr",   XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2872 { "blelr-",  XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2873 { "blelr-",  XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2874 { "blelr+",  XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2875 { "blelr+",  XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2876 { "bler",    XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2877 { "blelrl",  XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2878 { "blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2879 { "blelrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2880 { "blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2881 { "blelrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2882 { "blerl",   XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2883 { "bnglr",   XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2884 { "bnglr-",  XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2885 { "bnglr-",  XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2886 { "bnglr+",  XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2887 { "bnglr+",  XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2888 { "bngr",    XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2889 { "bnglrl",  XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2890 { "bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2891 { "bnglrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2892 { "bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2893 { "bnglrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2894 { "bngrl",   XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2895 { "bnelr",   XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2896 { "bnelr-",  XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2897 { "bnelr-",  XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2898 { "bnelr+",  XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2899 { "bnelr+",  XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2900 { "bner",    XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2901 { "bnelrl",  XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2902 { "bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2903 { "bnelrl-", XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2904 { "bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2905 { "bnelrl+", XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2906 { "bnerl",   XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2907 { "bnslr",   XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2908 { "bnslr-",  XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2909 { "bnslr-",  XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2910 { "bnslr+",  XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2911 { "bnslr+",  XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2912 { "bnsr",    XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2913 { "bnslrl",  XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2914 { "bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2915 { "bnslrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2916 { "bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2917 { "bnslrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2918 { "bnsrl",   XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2919 { "bnulr",   XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2920 { "bnulr-",  XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2921 { "bnulr-",  XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2922 { "bnulr+",  XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2923 { "bnulr+",  XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2924 { "bnulrl",  XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2925 { "bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2926 { "bnulrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2927 { "bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2928 { "bnulrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2929 { "btlr",    XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM,     { BI } },
2930 { "btlr-",   XLO(19,BOT,16,0), XLBOBB_MASK, NOPOWER4,   { BI } },
2931 { "btlr-",   XLO(19,BOTM4,16,0), XLBOBB_MASK, POWER4,   { BI } },
2932 { "btlr+",   XLO(19,BOTP,16,0), XLBOBB_MASK, NOPOWER4,  { BI } },
2933 { "btlr+",   XLO(19,BOTP4,16,0), XLBOBB_MASK, POWER4,   { BI } },
2934 { "bbtr",    XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM,     { BI } },
2935 { "btlrl",   XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM,     { BI } },
2936 { "btlrl-",  XLO(19,BOT,16,1), XLBOBB_MASK, NOPOWER4,   { BI } },
2937 { "btlrl-",  XLO(19,BOTM4,16,1), XLBOBB_MASK, POWER4,   { BI } },
2938 { "btlrl+",  XLO(19,BOTP,16,1), XLBOBB_MASK, NOPOWER4,  { BI } },
2939 { "btlrl+",  XLO(19,BOTP4,16,1), XLBOBB_MASK, POWER4,   { BI } },
2940 { "bbtrl",   XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM,     { BI } },
2941 { "bflr",    XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM,     { BI } },
2942 { "bflr-",   XLO(19,BOF,16,0), XLBOBB_MASK, NOPOWER4,   { BI } },
2943 { "bflr-",   XLO(19,BOFM4,16,0), XLBOBB_MASK, POWER4,   { BI } },
2944 { "bflr+",   XLO(19,BOFP,16,0), XLBOBB_MASK, NOPOWER4,  { BI } },
2945 { "bflr+",   XLO(19,BOFP4,16,0), XLBOBB_MASK, POWER4,   { BI } },
2946 { "bbfr",    XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM,     { BI } },
2947 { "bflrl",   XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM,     { BI } },
2948 { "bflrl-",  XLO(19,BOF,16,1), XLBOBB_MASK, NOPOWER4,   { BI } },
2949 { "bflrl-",  XLO(19,BOFM4,16,1), XLBOBB_MASK, POWER4,   { BI } },
2950 { "bflrl+",  XLO(19,BOFP,16,1), XLBOBB_MASK, NOPOWER4,  { BI } },
2951 { "bflrl+",  XLO(19,BOFP4,16,1), XLBOBB_MASK, POWER4,   { BI } },
2952 { "bbfrl",   XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM,     { BI } },
2953 { "bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM,  { BI } },
2954 { "bdnztlr-",XLO(19,BODNZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2955 { "bdnztlr+",XLO(19,BODNZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2956 { "bdnztlrl",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM,  { BI } },
2957 { "bdnztlrl-",XLO(19,BODNZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2958 { "bdnztlrl+",XLO(19,BODNZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2959 { "bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM,  { BI } },
2960 { "bdnzflr-",XLO(19,BODNZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2961 { "bdnzflr+",XLO(19,BODNZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2962 { "bdnzflrl",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM,  { BI } },
2963 { "bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2964 { "bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2965 { "bdztlr",  XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM,   { BI } },
2966 { "bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2967 { "bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2968 { "bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM,   { BI } },
2969 { "bdztlrl-",XLO(19,BODZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2970 { "bdztlrl+",XLO(19,BODZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2971 { "bdzflr",  XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM,   { BI } },
2972 { "bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2973 { "bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2974 { "bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM,   { BI } },
2975 { "bdzflrl-",XLO(19,BODZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2976 { "bdzflrl+",XLO(19,BODZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2977 { "bclr+",   XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM,      { BOE, BI } },
2978 { "bclrl+",  XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM,      { BOE, BI } },
2979 { "bclr-",   XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM,      { BOE, BI } },
2980 { "bclrl-",  XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM,      { BOE, BI } },
2981 { "bclr",    XLLK(19,16,0), XLBH_MASK,  PPCCOM,         { BO, BI, BH } },
2982 { "bclrl",   XLLK(19,16,1), XLBH_MASK,  PPCCOM,         { BO, BI, BH } },
2983 { "bcr",     XLLK(19,16,0), XLBB_MASK,  PWRCOM,         { BO, BI } },
2984 { "bcrl",    XLLK(19,16,1), XLBB_MASK,  PWRCOM,         { BO, BI } },
2985 { "bclre",   XLLK(19,17,0), XLBB_MASK,  BOOKE64,        { BO, BI } },
2986 { "bclrel",  XLLK(19,17,1), XLBB_MASK,  BOOKE64,        { BO, BI } },
2987
2988 { "rfid",    XL(19,18), 0xffffffff,     PPC64,          { 0 } },
2989
2990 { "crnot",   XL(19,33), XL_MASK,        PPCCOM,         { BT, BA, BBA } },
2991 { "crnor",   XL(19,33), XL_MASK,        COM,            { BT, BA, BB } },
2992 { "rfmci",    X(19,38), 0xffffffff,     PPCRFMCI,       { 0 } },
2993
2994 { "rfi",     XL(19,50), 0xffffffff,     COM,            { 0 } },
2995 { "rfci",    XL(19,51), 0xffffffff,     PPC403 | BOOKE, { 0 } },
2996
2997 { "rfsvc",   XL(19,82), 0xffffffff,     POWER,          { 0 } },
2998
2999 { "crandc",  XL(19,129), XL_MASK,       COM,            { BT, BA, BB } },
3000
3001 { "isync",   XL(19,150), 0xffffffff,    PPCCOM,         { 0 } },
3002 { "ics",     XL(19,150), 0xffffffff,    PWRCOM,         { 0 } },
3003
3004 { "crclr",   XL(19,193), XL_MASK,       PPCCOM,         { BT, BAT, BBA } },
3005 { "crxor",   XL(19,193), XL_MASK,       COM,            { BT, BA, BB } },
3006
3007 { "crnand",  XL(19,225), XL_MASK,       COM,            { BT, BA, BB } },
3008
3009 { "crand",   XL(19,257), XL_MASK,       COM,            { BT, BA, BB } },
3010
3011 { "crset",   XL(19,289), XL_MASK,       PPCCOM,         { BT, BAT, BBA } },
3012 { "creqv",   XL(19,289), XL_MASK,       COM,            { BT, BA, BB } },
3013
3014 { "crorc",   XL(19,417), XL_MASK,       COM,            { BT, BA, BB } },
3015
3016 { "crmove",  XL(19,449), XL_MASK,       PPCCOM,         { BT, BA, BBA } },
3017 { "cror",    XL(19,449), XL_MASK,       COM,            { BT, BA, BB } },
3018
3019 { "bctr",    XLO(19,BOU,528,0), XLBOBIBB_MASK, COM,     { 0 } },
3020 { "bctrl",   XLO(19,BOU,528,1), XLBOBIBB_MASK, COM,     { 0 } },
3021 { "bltctr",  XLOCB(19,BOT,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
3022 { "bltctr-", XLOCB(19,BOT,CBLT,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3023 { "bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3024 { "bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3025 { "bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3026 { "bltctrl", XLOCB(19,BOT,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
3027 { "bltctrl-",XLOCB(19,BOT,CBLT,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3028 { "bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3029 { "bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3030 { "bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3031 { "bgtctr",  XLOCB(19,BOT,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
3032 { "bgtctr-", XLOCB(19,BOT,CBGT,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3033 { "bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3034 { "bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3035 { "bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3036 { "bgtctrl", XLOCB(19,BOT,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
3037 { "bgtctrl-",XLOCB(19,BOT,CBGT,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3038 { "bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3039 { "bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3040 { "bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3041 { "beqctr",  XLOCB(19,BOT,CBEQ,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
3042 { "beqctr-", XLOCB(19,BOT,CBEQ,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3043 { "beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3044 { "beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3045 { "beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3046 { "beqctrl", XLOCB(19,BOT,CBEQ,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
3047 { "beqctrl-",XLOCB(19,BOT,CBEQ,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3048 { "beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3049 { "beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3050 { "beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3051 { "bsoctr",  XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
3052 { "bsoctr-", XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3053 { "bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3054 { "bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3055 { "bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3056 { "bsoctrl", XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
3057 { "bsoctrl-",XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3058 { "bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3059 { "bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3060 { "bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3061 { "bunctr",  XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
3062 { "bunctr-", XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3063 { "bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3064 { "bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3065 { "bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3066 { "bunctrl", XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
3067 { "bunctrl-",XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3068 { "bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3069 { "bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3070 { "bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3071 { "bgectr",  XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
3072 { "bgectr-", XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3073 { "bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3074 { "bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3075 { "bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3076 { "bgectrl", XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
3077 { "bgectrl-",XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3078 { "bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3079 { "bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3080 { "bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3081 { "bnlctr",  XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
3082 { "bnlctr-", XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3083 { "bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3084 { "bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3085 { "bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3086 { "bnlctrl", XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
3087 { "bnlctrl-",XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3088 { "bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3089 { "bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3090 { "bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3091 { "blectr",  XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
3092 { "blectr-", XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3093 { "blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3094 { "blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3095 { "blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3096 { "blectrl", XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
3097 { "blectrl-",XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3098 { "blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3099 { "blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3100 { "blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3101 { "bngctr",  XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
3102 { "bngctr-", XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3103 { "bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3104 { "bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3105 { "bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3106 { "bngctrl", XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
3107 { "bngctrl-",XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3108 { "bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3109 { "bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3110 { "bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3111 { "bnectr",  XLOCB(19,BOF,CBEQ,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
3112 { "bnectr-", XLOCB(19,BOF,CBEQ,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3113 { "bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3114 { "bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3115 { "bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3116 { "bnectrl", XLOCB(19,BOF,CBEQ,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
3117 { "bnectrl-",XLOCB(19,BOF,CBEQ,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3118 { "bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3119 { "bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3120 { "bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3121 { "bnsctr",  XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
3122 { "bnsctr-", XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3123 { "bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3124 { "bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3125 { "bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3126 { "bnsctrl", XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
3127 { "bnsctrl-",XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3128 { "bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3129 { "bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3130 { "bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3131 { "bnuctr",  XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
3132 { "bnuctr-", XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3133 { "bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3134 { "bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3135 { "bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3136 { "bnuctrl", XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
3137 { "bnuctrl-",XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3138 { "bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3139 { "bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3140 { "bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3141 { "btctr",   XLO(19,BOT,528,0),  XLBOBB_MASK, PPCCOM,   { BI } },
3142 { "btctr-",  XLO(19,BOT,528,0),  XLBOBB_MASK, NOPOWER4, { BI } },
3143 { "btctr-",  XLO(19,BOTM4,528,0), XLBOBB_MASK, POWER4, { BI } },
3144 { "btctr+",  XLO(19,BOTP,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
3145 { "btctr+",  XLO(19,BOTP4,528,0), XLBOBB_MASK, POWER4, { BI } },
3146 { "btctrl",  XLO(19,BOT,528,1),  XLBOBB_MASK, PPCCOM,   { BI } },
3147 { "btctrl-", XLO(19,BOT,528,1),  XLBOBB_MASK, NOPOWER4, { BI } },
3148 { "btctrl-", XLO(19,BOTM4,528,1), XLBOBB_MASK, POWER4, { BI } },
3149 { "btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
3150 { "btctrl+", XLO(19,BOTP4,528,1), XLBOBB_MASK, POWER4, { BI } },
3151 { "bfctr",   XLO(19,BOF,528,0),  XLBOBB_MASK, PPCCOM,   { BI } },
3152 { "bfctr-",  XLO(19,BOF,528,0),  XLBOBB_MASK, NOPOWER4, { BI } },
3153 { "bfctr-",  XLO(19,BOFM4,528,0), XLBOBB_MASK, POWER4, { BI } },
3154 { "bfctr+",  XLO(19,BOFP,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
3155 { "bfctr+",  XLO(19,BOFP4,528,0), XLBOBB_MASK, POWER4, { BI } },
3156 { "bfctrl",  XLO(19,BOF,528,1),  XLBOBB_MASK, PPCCOM,   { BI } },
3157 { "bfctrl-", XLO(19,BOF,528,1),  XLBOBB_MASK, NOPOWER4, { BI } },
3158 { "bfctrl-", XLO(19,BOFM4,528,1), XLBOBB_MASK, POWER4, { BI } },
3159 { "bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
3160 { "bfctrl+", XLO(19,BOFP4,528,1), XLBOBB_MASK, POWER4, { BI } },
3161 { "bcctr-",  XLYLK(19,528,0,0),  XLYBB_MASK,  PPCCOM,   { BOE, BI } },
3162 { "bcctr+",  XLYLK(19,528,1,0),  XLYBB_MASK,  PPCCOM,   { BOE, BI } },
3163 { "bcctrl-", XLYLK(19,528,0,1),  XLYBB_MASK,  PPCCOM,   { BOE, BI } },
3164 { "bcctrl+", XLYLK(19,528,1,1),  XLYBB_MASK,  PPCCOM,   { BOE, BI } },
3165 { "bcctr",   XLLK(19,528,0),     XLBH_MASK,   PPCCOM,   { BO, BI, BH } },
3166 { "bcctrl",  XLLK(19,528,1),     XLBH_MASK,   PPCCOM,   { BO, BI, BH } },
3167 { "bcc",     XLLK(19,528,0),     XLBB_MASK,   PWRCOM,   { BO, BI } },
3168 { "bccl",    XLLK(19,528,1),     XLBB_MASK,   PWRCOM,   { BO, BI } },
3169 { "bcctre",  XLLK(19,529,0),     XLYBB_MASK,  BOOKE64,  { BO, BI } },
3170 { "bcctrel", XLLK(19,529,1),     XLYBB_MASK,  BOOKE64,  { BO, BI } },
3171
3172 { "rlwimi",  M(20,0),   M_MASK,         PPCCOM,         { RA,RS,SH,MBE,ME } },
3173 { "rlimi",   M(20,0),   M_MASK,         PWRCOM,         { RA,RS,SH,MBE,ME } },
3174
3175 { "rlwimi.", M(20,1),   M_MASK,         PPCCOM,         { RA,RS,SH,MBE,ME } },
3176 { "rlimi.",  M(20,1),   M_MASK,         PWRCOM,         { RA,RS,SH,MBE,ME } },
3177
3178 { "rotlwi",  MME(21,31,0), MMBME_MASK,  PPCCOM,         { RA, RS, SH } },
3179 { "clrlwi",  MME(21,31,0), MSHME_MASK,  PPCCOM,         { RA, RS, MB } },
3180 { "rlwinm",  M(21,0),   M_MASK,         PPCCOM,         { RA,RS,SH,MBE,ME } },
3181 { "rlinm",   M(21,0),   M_MASK,         PWRCOM,         { RA,RS,SH,MBE,ME } },
3182 { "rotlwi.", MME(21,31,1), MMBME_MASK,  PPCCOM,         { RA,RS,SH } },
3183 { "clrlwi.", MME(21,31,1), MSHME_MASK,  PPCCOM,         { RA, RS, MB } },
3184 { "rlwinm.", M(21,1),   M_MASK,         PPCCOM,         { RA,RS,SH,MBE,ME } },
3185 { "rlinm.",  M(21,1),   M_MASK,         PWRCOM,         { RA,RS,SH,MBE,ME } },
3186
3187 { "rlmi",    M(22,0),   M_MASK,         M601,           { RA,RS,RB,MBE,ME } },
3188 { "rlmi.",   M(22,1),   M_MASK,         M601,           { RA,RS,RB,MBE,ME } },
3189
3190 { "be",      B(22,0,0), B_MASK,         BOOKE64,        { LI } },
3191 { "bel",     B(22,0,1), B_MASK,         BOOKE64,        { LI } },
3192 { "bea",     B(22,1,0), B_MASK,         BOOKE64,        { LIA } },
3193 { "bela",    B(22,1,1), B_MASK,         BOOKE64,        { LIA } },
3194
3195 { "rotlw",   MME(23,31,0), MMBME_MASK,  PPCCOM,         { RA, RS, RB } },
3196 { "rlwnm",   M(23,0),   M_MASK,         PPCCOM,         { RA,RS,RB,MBE,ME } },
3197 { "rlnm",    M(23,0),   M_MASK,         PWRCOM,         { RA,RS,RB,MBE,ME } },
3198 { "rotlw.",  MME(23,31,1), MMBME_MASK,  PPCCOM,         { RA, RS, RB } },
3199 { "rlwnm.",  M(23,1),   M_MASK,         PPCCOM,         { RA,RS,RB,MBE,ME } },
3200 { "rlnm.",   M(23,1),   M_MASK,         PWRCOM,         { RA,RS,RB,MBE,ME } },
3201
3202 { "nop",     OP(24),    0xffffffff,     PPCCOM,         { 0 } },
3203 { "ori",     OP(24),    OP_MASK,        PPCCOM,         { RA, RS, UI } },
3204 { "oril",    OP(24),    OP_MASK,        PWRCOM,         { RA, RS, UI } },
3205
3206 { "oris",    OP(25),    OP_MASK,        PPCCOM,         { RA, RS, UI } },
3207 { "oriu",    OP(25),    OP_MASK,        PWRCOM,         { RA, RS, UI } },
3208
3209 { "xori",    OP(26),    OP_MASK,        PPCCOM,         { RA, RS, UI } },
3210 { "xoril",   OP(26),    OP_MASK,        PWRCOM,         { RA, RS, UI } },
3211
3212 { "xoris",   OP(27),    OP_MASK,        PPCCOM,         { RA, RS, UI } },
3213 { "xoriu",   OP(27),    OP_MASK,        PWRCOM,         { RA, RS, UI } },
3214
3215 { "andi.",   OP(28),    OP_MASK,        PPCCOM,         { RA, RS, UI } },
3216 { "andil.",  OP(28),    OP_MASK,        PWRCOM,         { RA, RS, UI } },
3217
3218 { "andis.",  OP(29),    OP_MASK,        PPCCOM,         { RA, RS, UI } },
3219 { "andiu.",  OP(29),    OP_MASK,        PWRCOM,         { RA, RS, UI } },
3220
3221 { "rotldi",  MD(30,0,0), MDMB_MASK,     PPC64,          { RA, RS, SH6 } },
3222 { "clrldi",  MD(30,0,0), MDSH_MASK,     PPC64,          { RA, RS, MB6 } },
3223 { "rldicl",  MD(30,0,0), MD_MASK,       PPC64,          { RA, RS, SH6, MB6 } },
3224 { "rotldi.", MD(30,0,1), MDMB_MASK,     PPC64,          { RA, RS, SH6 } },
3225 { "clrldi.", MD(30,0,1), MDSH_MASK,     PPC64,          { RA, RS, MB6 } },
3226 { "rldicl.", MD(30,0,1), MD_MASK,       PPC64,          { RA, RS, SH6, MB6 } },
3227
3228 { "rldicr",  MD(30,1,0), MD_MASK,       PPC64,          { RA, RS, SH6, ME6 } },
3229 { "rldicr.", MD(30,1,1), MD_MASK,       PPC64,          { RA, RS, SH6, ME6 } },
3230
3231 { "rldic",   MD(30,2,0), MD_MASK,       PPC64,          { RA, RS, SH6, MB6 } },
3232 { "rldic.",  MD(30,2,1), MD_MASK,       PPC64,          { RA, RS, SH6, MB6 } },
3233
3234 { "rldimi",  MD(30,3,0), MD_MASK,       PPC64,          { RA, RS, SH6, MB6 } },
3235 { "rldimi.", MD(30,3,1), MD_MASK,       PPC64,          { RA, RS, SH6, MB6 } },
3236
3237 { "rotld",   MDS(30,8,0), MDSMB_MASK,   PPC64,          { RA, RS, RB } },
3238 { "rldcl",   MDS(30,8,0), MDS_MASK,     PPC64,          { RA, RS, RB, MB6 } },
3239 { "rotld.",  MDS(30,8,1), MDSMB_MASK,   PPC64,          { RA, RS, RB } },
3240 { "rldcl.",  MDS(30,8,1), MDS_MASK,     PPC64,          { RA, RS, RB, MB6 } },
3241
3242 { "rldcr",   MDS(30,9,0), MDS_MASK,     PPC64,          { RA, RS, RB, ME6 } },
3243 { "rldcr.",  MDS(30,9,1), MDS_MASK,     PPC64,          { RA, RS, RB, ME6 } },
3244
3245 { "cmpw",    XOPL(31,0,0), XCMPL_MASK, PPCCOM,          { OBF, RA, RB } },
3246 { "cmpd",    XOPL(31,0,1), XCMPL_MASK, PPC64,           { OBF, RA, RB } },
3247 { "cmp",     X(31,0),   XCMP_MASK,      PPC,            { BF, L, RA, RB } },
3248 { "cmp",     X(31,0),   XCMPL_MASK,     PWRCOM,         { BF, RA, RB } },
3249
3250 { "twlgt",   XTO(31,4,TOLGT), XTO_MASK, PPCCOM,         { RA, RB } },
3251 { "tlgt",    XTO(31,4,TOLGT), XTO_MASK, PWRCOM,         { RA, RB } },
3252 { "twllt",   XTO(31,4,TOLLT), XTO_MASK, PPCCOM,         { RA, RB } },
3253 { "tllt",    XTO(31,4,TOLLT), XTO_MASK, PWRCOM,         { RA, RB } },
3254 { "tweq",    XTO(31,4,TOEQ), XTO_MASK,  PPCCOM,         { RA, RB } },
3255 { "teq",     XTO(31,4,TOEQ), XTO_MASK,  PWRCOM,         { RA, RB } },
3256 { "twlge",   XTO(31,4,TOLGE), XTO_MASK, PPCCOM,         { RA, RB } },
3257 { "tlge",    XTO(31,4,TOLGE), XTO_MASK, PWRCOM,         { RA, RB } },
3258 { "twlnl",   XTO(31,4,TOLNL), XTO_MASK, PPCCOM,         { RA, RB } },
3259 { "tlnl",    XTO(31,4,TOLNL), XTO_MASK, PWRCOM,         { RA, RB } },
3260 { "twlle",   XTO(31,4,TOLLE), XTO_MASK, PPCCOM,         { RA, RB } },
3261 { "tlle",    XTO(31,4,TOLLE), XTO_MASK, PWRCOM,         { RA, RB } },
3262 { "twlng",   XTO(31,4,TOLNG), XTO_MASK, PPCCOM,         { RA, RB } },
3263 { "tlng",    XTO(31,4,TOLNG), XTO_MASK, PWRCOM,         { RA, RB } },
3264 { "twgt",    XTO(31,4,TOGT), XTO_MASK,  PPCCOM,         { RA, RB } },
3265 { "tgt",     XTO(31,4,TOGT), XTO_MASK,  PWRCOM,         { RA, RB } },
3266 { "twge",    XTO(31,4,TOGE), XTO_MASK,  PPCCOM,         { RA, RB } },
3267 { "tge",     XTO(31,4,TOGE), XTO_MASK,  PWRCOM,         { RA, RB } },
3268 { "twnl",    XTO(31,4,TONL), XTO_MASK,  PPCCOM,         { RA, RB } },
3269 { "tnl",     XTO(31,4,TONL), XTO_MASK,  PWRCOM,         { RA, RB } },
3270 { "twlt",    XTO(31,4,TOLT), XTO_MASK,  PPCCOM,         { RA, RB } },
3271 { "tlt",     XTO(31,4,TOLT), XTO_MASK,  PWRCOM,         { RA, RB } },
3272 { "twle",    XTO(31,4,TOLE), XTO_MASK,  PPCCOM,         { RA, RB } },
3273 { "tle",     XTO(31,4,TOLE), XTO_MASK,  PWRCOM,         { RA, RB } },
3274 { "twng",    XTO(31,4,TONG), XTO_MASK,  PPCCOM,         { RA, RB } },
3275 { "tng",     XTO(31,4,TONG), XTO_MASK,  PWRCOM,         { RA, RB } },
3276 { "twne",    XTO(31,4,TONE), XTO_MASK,  PPCCOM,         { RA, RB } },
3277 { "tne",     XTO(31,4,TONE), XTO_MASK,  PWRCOM,         { RA, RB } },
3278 { "trap",    XTO(31,4,TOU), 0xffffffff, PPCCOM,         { 0 } },
3279 { "tw",      X(31,4),   X_MASK,         PPCCOM,         { TO, RA, RB } },
3280 { "t",       X(31,4),   X_MASK,         PWRCOM,         { TO, RA, RB } },
3281
3282 { "subfc",   XO(31,8,0,0), XO_MASK,     PPCCOM,         { RT, RA, RB } },
3283 { "sf",      XO(31,8,0,0), XO_MASK,     PWRCOM,         { RT, RA, RB } },
3284 { "subc",    XO(31,8,0,0), XO_MASK,     PPC,            { RT, RB, RA } },
3285 { "subfc.",  XO(31,8,0,1), XO_MASK,     PPCCOM,         { RT, RA, RB } },
3286 { "sf.",     XO(31,8,0,1), XO_MASK,     PWRCOM,         { RT, RA, RB } },
3287 { "subc.",   XO(31,8,0,1), XO_MASK,     PPCCOM,         { RT, RB, RA } },
3288 { "subfco",  XO(31,8,1,0), XO_MASK,     PPCCOM,         { RT, RA, RB } },
3289 { "sfo",     XO(31,8,1,0), XO_MASK,     PWRCOM,         { RT, RA, RB } },
3290 { "subco",   XO(31,8,1,0), XO_MASK,     PPC,            { RT, RB, RA } },
3291 { "subfco.", XO(31,8,1,1), XO_MASK,     PPCCOM,         { RT, RA, RB } },
3292 { "sfo.",    XO(31,8,1,1), XO_MASK,     PWRCOM,         { RT, RA, RB } },
3293 { "subco.",  XO(31,8,1,1), XO_MASK,     PPC,            { RT, RB, RA } },
3294
3295 { "mulhdu",  XO(31,9,0,0), XO_MASK,     PPC64,          { RT, RA, RB } },
3296 { "mulhdu.", XO(31,9,0,1), XO_MASK,     PPC64,          { RT, RA, RB } },
3297
3298 { "addc",    XO(31,10,0,0), XO_MASK,    PPCCOM,         { RT, RA, RB } },
3299 { "a",       XO(31,10,0,0), XO_MASK,    PWRCOM,         { RT, RA, RB } },
3300 { "addc.",   XO(31,10,0,1), XO_MASK,    PPCCOM,         { RT, RA, RB } },
3301 { "a.",      XO(31,10,0,1), XO_MASK,    PWRCOM,         { RT, RA, RB } },
3302 { "addco",   XO(31,10,1,0), XO_MASK,    PPCCOM,         { RT, RA, RB } },
3303 { "ao",      XO(31,10,1,0), XO_MASK,    PWRCOM,         { RT, RA, RB } },
3304 { "addco.",  XO(31,10,1,1), XO_MASK,    PPCCOM,         { RT, RA, RB } },
3305 { "ao.",     XO(31,10,1,1), XO_MASK,    PWRCOM,         { RT, RA, RB } },
3306
3307 { "mulhwu",  XO(31,11,0,0), XO_MASK,    PPC,            { RT, RA, RB } },
3308 { "mulhwu.", XO(31,11,0,1), XO_MASK,    PPC,            { RT, RA, RB } },
3309
3310 { "isellt",  X(31,15),      X_MASK,     PPCISEL,        { RT, RA, RB } },
3311 { "iselgt",  X(31,47),      X_MASK,     PPCISEL,        { RT, RA, RB } },
3312 { "iseleq",  X(31,79),      X_MASK,     PPCISEL,        { RT, RA, RB } },
3313 { "isel",    XISEL(31,15),  XISEL_MASK, PPCISEL,        { RT, RA, RB, CRB } },
3314
3315 { "mfocrf",  XFXM(31,19,0,1), XFXFXM_MASK, COM,         { RT, FXM } },
3316 { "mfcr",    X(31,19),  XRARB_MASK,     NOPOWER4,       { RT } },
3317 { "mfcr",    X(31,19),  XFXFXM_MASK,    POWER4,         { RT, FXM4 } },
3318
3319 { "lwarx",   X(31,20),  X_MASK,         PPC,            { RT, RA0, RB } },
3320
3321 { "ldx",     X(31,21),  X_MASK,         PPC64,          { RT, RA0, RB } },
3322
3323 { "icbt",    X(31,22),  X_MASK,         BOOKE,          { CT, RA, RB } },
3324 { "icbt",    X(31,262), XRT_MASK,       PPC403,         { RA, RB } },
3325
3326 { "lwzx",    X(31,23),  X_MASK,         PPCCOM,         { RT, RA0, RB } },
3327 { "lx",      X(31,23),  X_MASK,         PWRCOM,         { RT, RA, RB } },
3328
3329 { "slw",     XRC(31,24,0), X_MASK,      PPCCOM,         { RA, RS, RB } },
3330 { "sl",      XRC(31,24,0), X_MASK,      PWRCOM,         { RA, RS, RB } },
3331 { "slw.",    XRC(31,24,1), X_MASK,      PPCCOM,         { RA, RS, RB } },
3332 { "sl.",     XRC(31,24,1), X_MASK,      PWRCOM,         { RA, RS, RB } },
3333
3334 { "cntlzw",  XRC(31,26,0), XRB_MASK,    PPCCOM,         { RA, RS } },
3335 { "cntlz",   XRC(31,26,0), XRB_MASK,    PWRCOM,         { RA, RS } },
3336 { "cntlzw.", XRC(31,26,1), XRB_MASK,    PPCCOM,         { RA, RS } },
3337 { "cntlz.",  XRC(31,26,1), XRB_MASK,    PWRCOM,         { RA, RS } },
3338
3339 { "sld",     XRC(31,27,0), X_MASK,      PPC64,          { RA, RS, RB } },
3340 { "sld.",    XRC(31,27,1), X_MASK,      PPC64,          { RA, RS, RB } },
3341
3342 { "and",     XRC(31,28,0), X_MASK,      COM,            { RA, RS, RB } },
3343 { "and.",    XRC(31,28,1), X_MASK,      COM,            { RA, RS, RB } },
3344
3345 { "maskg",   XRC(31,29,0), X_MASK,      M601,           { RA, RS, RB } },
3346 { "maskg.",  XRC(31,29,1), X_MASK,      M601,           { RA, RS, RB } },
3347
3348 { "icbte",   X(31,30),  X_MASK,         BOOKE64,        { CT, RA, RB } },
3349
3350 { "lwzxe",   X(31,31),  X_MASK,         BOOKE64,        { RT, RA0, RB } },
3351
3352 { "cmplw",   XOPL(31,32,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } },
3353 { "cmpld",   XOPL(31,32,1), XCMPL_MASK, PPC64,          { OBF, RA, RB } },
3354 { "cmpl",    X(31,32),  XCMP_MASK,       PPC,           { BF, L, RA, RB } },
3355 { "cmpl",    X(31,32),  XCMPL_MASK,      PWRCOM,        { BF, RA, RB } },
3356
3357 { "subf",    XO(31,40,0,0), XO_MASK,    PPC,            { RT, RA, RB } },
3358 { "sub",     XO(31,40,0,0), XO_MASK,    PPC,            { RT, RB, RA } },
3359 { "subf.",   XO(31,40,0,1), XO_MASK,    PPC,            { RT, RA, RB } },
3360 { "sub.",    XO(31,40,0,1), XO_MASK,    PPC,            { RT, RB, RA } },
3361 { "subfo",   XO(31,40,1,0), XO_MASK,    PPC,            { RT, RA, RB } },
3362 { "subo",    XO(31,40,1,0), XO_MASK,    PPC,            { RT, RB, RA } },
3363 { "subfo.",  XO(31,40,1,1), XO_MASK,    PPC,            { RT, RA, RB } },
3364 { "subo.",   XO(31,40,1,1), XO_MASK,    PPC,            { RT, RB, RA } },
3365
3366 { "ldux",    X(31,53),  X_MASK,         PPC64,          { RT, RAL, RB } },
3367
3368 { "dcbst",   X(31,54),  XRT_MASK,       PPC,            { RA, RB } },
3369
3370 { "lwzux",   X(31,55),  X_MASK,         PPCCOM,         { RT, RAL, RB } },
3371 { "lux",     X(31,55),  X_MASK,         PWRCOM,         { RT, RA, RB } },
3372
3373 { "dcbste",  X(31,62),  XRT_MASK,       BOOKE64,        { RA, RB } },
3374
3375 { "lwzuxe",  X(31,63),  X_MASK,         BOOKE64,        { RT, RAL, RB } },
3376
3377 { "cntlzd",  XRC(31,58,0), XRB_MASK,    PPC64,          { RA, RS } },
3378 { "cntlzd.", XRC(31,58,1), XRB_MASK,    PPC64,          { RA, RS } },
3379
3380 { "andc",    XRC(31,60,0), X_MASK,      COM,            { RA, RS, RB } },
3381 { "andc.",   XRC(31,60,1), X_MASK,      COM,            { RA, RS, RB } },
3382
3383 { "tdlgt",   XTO(31,68,TOLGT), XTO_MASK, PPC64,         { RA, RB } },
3384 { "tdllt",   XTO(31,68,TOLLT), XTO_MASK, PPC64,         { RA, RB } },
3385 { "tdeq",    XTO(31,68,TOEQ), XTO_MASK,  PPC64,         { RA, RB } },
3386 { "tdlge",   XTO(31,68,TOLGE), XTO_MASK, PPC64,         { RA, RB } },
3387 { "tdlnl",   XTO(31,68,TOLNL), XTO_MASK, PPC64,         { RA, RB } },
3388 { "tdlle",   XTO(31,68,TOLLE), XTO_MASK, PPC64,         { RA, RB } },
3389 { "tdlng",   XTO(31,68,TOLNG), XTO_MASK, PPC64,         { RA, RB } },
3390 { "tdgt",    XTO(31,68,TOGT), XTO_MASK,  PPC64,         { RA, RB } },
3391 { "tdge",    XTO(31,68,TOGE), XTO_MASK,  PPC64,         { RA, RB } },
3392 { "tdnl",    XTO(31,68,TONL), XTO_MASK,  PPC64,         { RA, RB } },
3393 { "tdlt",    XTO(31,68,TOLT), XTO_MASK,  PPC64,         { RA, RB } },
3394 { "tdle",    XTO(31,68,TOLE), XTO_MASK,  PPC64,         { RA, RB } },
3395 { "tdng",    XTO(31,68,TONG), XTO_MASK,  PPC64,         { RA, RB } },
3396 { "tdne",    XTO(31,68,TONE), XTO_MASK,  PPC64,         { RA, RB } },
3397 { "td",      X(31,68),  X_MASK,          PPC64,         { TO, RA, RB } },
3398
3399 { "mulhd",   XO(31,73,0,0), XO_MASK,     PPC64,         { RT, RA, RB } },
3400 { "mulhd.",  XO(31,73,0,1), XO_MASK,     PPC64,         { RT, RA, RB } },
3401
3402 { "mulhw",   XO(31,75,0,0), XO_MASK,    PPC,            { RT, RA, RB } },
3403 { "mulhw.",  XO(31,75,0,1), XO_MASK,    PPC,            { RT, RA, RB } },
3404
3405 { "dlmzb",   XRC(31,78,0),  X_MASK,     PPC403|PPC440,  { RA, RS, RB } },
3406 { "dlmzb.",  XRC(31,78,1),  X_MASK,     PPC403|PPC440,  { RA, RS, RB } },
3407
3408 { "mtsrd",   X(31,82),  XRB_MASK|(1<<20), PPC64,        { SR, RS } },
3409
3410 { "mfmsr",   X(31,83),  XRARB_MASK,     COM,            { RT } },
3411
3412 { "ldarx",   X(31,84),  X_MASK,         PPC64,          { RT, RA0, RB } },
3413
3414 { "dcbf",    X(31,86),  XRT_MASK,       PPC,            { RA, RB } },
3415
3416 { "lbzx",    X(31,87),  X_MASK,         COM,            { RT, RA0, RB } },
3417
3418 { "dcbfe",   X(31,94),  XRT_MASK,       BOOKE64,        { RA, RB } },
3419
3420 { "lbzxe",   X(31,95),  X_MASK,         BOOKE64,        { RT, RA0, RB } },
3421
3422 { "neg",     XO(31,104,0,0), XORB_MASK, COM,            { RT, RA } },
3423 { "neg.",    XO(31,104,0,1), XORB_MASK, COM,            { RT, RA } },
3424 { "nego",    XO(31,104,1,0), XORB_MASK, COM,            { RT, RA } },
3425 { "nego.",   XO(31,104,1,1), XORB_MASK, COM,            { RT, RA } },
3426
3427 { "mul",     XO(31,107,0,0), XO_MASK,   M601,           { RT, RA, RB } },
3428 { "mul.",    XO(31,107,0,1), XO_MASK,   M601,           { RT, RA, RB } },
3429 { "mulo",    XO(31,107,1,0), XO_MASK,   M601,           { RT, RA, RB } },
3430 { "mulo.",   XO(31,107,1,1), XO_MASK,   M601,           { RT, RA, RB } },
3431
3432 { "mtsrdin", X(31,114), XRA_MASK,       PPC64,          { RS, RB } },
3433
3434 { "clf",     X(31,118), XTO_MASK,       POWER,          { RA, RB } },
3435
3436 { "lbzux",   X(31,119), X_MASK,         COM,            { RT, RAL, RB } },
3437
3438 { "not",     XRC(31,124,0), X_MASK,     COM,            { RA, RS, RBS } },
3439 { "nor",     XRC(31,124,0), X_MASK,     COM,            { RA, RS, RB } },
3440 { "not.",    XRC(31,124,1), X_MASK,     COM,            { RA, RS, RBS } },
3441 { "nor.",    XRC(31,124,1), X_MASK,     COM,            { RA, RS, RB } },
3442
3443 { "lwarxe",  X(31,126), X_MASK,         BOOKE64,        { RT, RA0, RB } },
3444
3445 { "lbzuxe",  X(31,127), X_MASK,         BOOKE64,        { RT, RAL, RB } },
3446
3447 { "wrtee",   X(31,131), XRARB_MASK,     PPC403 | BOOKE, { RS } },
3448
3449 { "dcbtstls",X(31,134), X_MASK,         PPCCHLK,        { CT, RA, RB }},
3450
3451 { "subfe",   XO(31,136,0,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3452 { "sfe",     XO(31,136,0,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3453 { "subfe.",  XO(31,136,0,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3454 { "sfe.",    XO(31,136,0,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3455 { "subfeo",  XO(31,136,1,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3456 { "sfeo",    XO(31,136,1,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3457 { "subfeo.", XO(31,136,1,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3458 { "sfeo.",   XO(31,136,1,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3459
3460 { "adde",    XO(31,138,0,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3461 { "ae",      XO(31,138,0,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3462 { "adde.",   XO(31,138,0,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3463 { "ae.",     XO(31,138,0,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3464 { "addeo",   XO(31,138,1,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3465 { "aeo",     XO(31,138,1,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3466 { "addeo.",  XO(31,138,1,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3467 { "aeo.",    XO(31,138,1,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3468
3469 { "dcbtstlse",X(31,142),X_MASK,         PPCCHLK64,      { CT, RA, RB }},
3470
3471 { "mtocrf",  XFXM(31,144,0,1), XFXFXM_MASK, COM,        { FXM, RS } },
3472 { "mtcr",    XFXM(31,144,0xff,0), XRARB_MASK, COM,      { RS }},
3473 { "mtcrf",   X(31,144), XFXFXM_MASK,    COM,            { FXM, RS } },
3474
3475 { "mtmsr",   X(31,146), XRARB_MASK,     COM,            { RS } },
3476
3477 { "stdx",    X(31,149), X_MASK,         PPC64,          { RS, RA0, RB } },
3478
3479 { "stwcx.",  XRC(31,150,1), X_MASK,     PPC,            { RS, RA0, RB } },
3480
3481 { "stwx",    X(31,151), X_MASK,         PPCCOM,         { RS, RA0, RB } },
3482 { "stx",     X(31,151), X_MASK,         PWRCOM,         { RS, RA, RB } },
3483
3484 { "stwcxe.", XRC(31,158,1), X_MASK,     BOOKE64,        { RS, RA0, RB } },
3485
3486 { "stwxe",   X(31,159), X_MASK,         BOOKE64,        { RS, RA0, RB } },
3487
3488 { "slq",     XRC(31,152,0), X_MASK,     M601,           { RA, RS, RB } },
3489 { "slq.",    XRC(31,152,1), X_MASK,     M601,           { RA, RS, RB } },
3490
3491 { "sle",     XRC(31,153,0), X_MASK,     M601,           { RA, RS, RB } },
3492 { "sle.",    XRC(31,153,1), X_MASK,     M601,           { RA, RS, RB } },
3493
3494 { "wrteei",  X(31,163), XE_MASK,        PPC403 | BOOKE, { E } },
3495
3496 { "dcbtls",  X(31,166), X_MASK,         PPCCHLK,        { CT, RA, RB }},
3497 { "dcbtlse", X(31,174), X_MASK,         PPCCHLK64,      { CT, RA, RB }},
3498
3499 { "mtmsrd",  X(31,178), XRLARB_MASK,    PPC64,          { RS, MTMSRD_L } },
3500
3501 { "stdux",   X(31,181), X_MASK,         PPC64,          { RS, RAS, RB } },
3502
3503 { "stwux",   X(31,183), X_MASK,         PPCCOM,         { RS, RAS, RB } },
3504 { "stux",    X(31,183), X_MASK,         PWRCOM,         { RS, RA0, RB } },
3505
3506 { "sliq",    XRC(31,184,0), X_MASK,     M601,           { RA, RS, SH } },
3507 { "sliq.",   XRC(31,184,1), X_MASK,     M601,           { RA, RS, SH } },
3508
3509 { "stwuxe",  X(31,191), X_MASK,         BOOKE64,        { RS, RAS, RB } },
3510
3511 { "subfze",  XO(31,200,0,0), XORB_MASK, PPCCOM,         { RT, RA } },
3512 { "sfze",    XO(31,200,0,0), XORB_MASK, PWRCOM,         { RT, RA } },
3513 { "subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM,         { RT, RA } },
3514 { "sfze.",   XO(31,200,0,1), XORB_MASK, PWRCOM,         { RT, RA } },
3515 { "subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM,         { RT, RA } },
3516 { "sfzeo",   XO(31,200,1,0), XORB_MASK, PWRCOM,         { RT, RA } },
3517 { "subfzeo.",XO(31,200,1,1), XORB_MASK, PPCCOM,         { RT, RA } },
3518 { "sfzeo.",  XO(31,200,1,1), XORB_MASK, PWRCOM,         { RT, RA } },
3519
3520 { "addze",   XO(31,202,0,0), XORB_MASK, PPCCOM,         { RT, RA } },
3521 { "aze",     XO(31,202,0,0), XORB_MASK, PWRCOM,         { RT, RA } },
3522 { "addze.",  XO(31,202,0,1), XORB_MASK, PPCCOM,         { RT, RA } },
3523 { "aze.",    XO(31,202,0,1), XORB_MASK, PWRCOM,         { RT, RA } },
3524 { "addzeo",  XO(31,202,1,0), XORB_MASK, PPCCOM,         { RT, RA } },
3525 { "azeo",    XO(31,202,1,0), XORB_MASK, PWRCOM,         { RT, RA } },
3526 { "addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM,         { RT, RA } },
3527 { "azeo.",   XO(31,202,1,1), XORB_MASK, PWRCOM,         { RT, RA } },
3528
3529 { "mtsr",    X(31,210), XRB_MASK|(1<<20), COM32,        { SR, RS } },
3530
3531 { "stdcx.",  XRC(31,214,1), X_MASK,     PPC64,          { RS, RA0, RB } },
3532
3533 { "stbx",    X(31,215), X_MASK,         COM,            { RS, RA0, RB } },
3534
3535 { "sllq",    XRC(31,216,0), X_MASK,     M601,           { RA, RS, RB } },
3536 { "sllq.",   XRC(31,216,1), X_MASK,     M601,           { RA, RS, RB } },
3537
3538 { "sleq",    XRC(31,217,0), X_MASK,     M601,           { RA, RS, RB } },
3539 { "sleq.",   XRC(31,217,1), X_MASK,     M601,           { RA, RS, RB } },
3540
3541 { "stbxe",   X(31,223), X_MASK,         BOOKE64,        { RS, RA0, RB } },
3542
3543 { "icblc",   X(31,230), X_MASK,         PPCCHLK,        { CT, RA, RB }},
3544
3545 { "subfme",  XO(31,232,0,0), XORB_MASK, PPCCOM,         { RT, RA } },
3546 { "sfme",    XO(31,232,0,0), XORB_MASK, PWRCOM,         { RT, RA } },
3547 { "subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM,         { RT, RA } },
3548 { "sfme.",   XO(31,232,0,1), XORB_MASK, PWRCOM,         { RT, RA } },
3549 { "subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM,         { RT, RA } },
3550 { "sfmeo",   XO(31,232,1,0), XORB_MASK, PWRCOM,         { RT, RA } },
3551 { "subfmeo.",XO(31,232,1,1), XORB_MASK, PPCCOM,         { RT, RA } },
3552 { "sfmeo.",  XO(31,232,1,1), XORB_MASK, PWRCOM,         { RT, RA } },
3553
3554 { "mulld",   XO(31,233,0,0), XO_MASK,   PPC64,          { RT, RA, RB } },
3555 { "mulld.",  XO(31,233,0,1), XO_MASK,   PPC64,          { RT, RA, RB } },
3556 { "mulldo",  XO(31,233,1,0), XO_MASK,   PPC64,          { RT, RA, RB } },
3557 { "mulldo.", XO(31,233,1,1), XO_MASK,   PPC64,          { RT, RA, RB } },
3558
3559 { "addme",   XO(31,234,0,0), XORB_MASK, PPCCOM,         { RT, RA } },
3560 { "ame",     XO(31,234,0,0), XORB_MASK, PWRCOM,         { RT, RA } },
3561 { "addme.",  XO(31,234,0,1), XORB_MASK, PPCCOM,         { RT, RA } },
3562 { "ame.",    XO(31,234,0,1), XORB_MASK, PWRCOM,         { RT, RA } },
3563 { "addmeo",  XO(31,234,1,0), XORB_MASK, PPCCOM,         { RT, RA } },
3564 { "ameo",    XO(31,234,1,0), XORB_MASK, PWRCOM,         { RT, RA } },
3565 { "addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM,         { RT, RA } },
3566 { "ameo.",   XO(31,234,1,1), XORB_MASK, PWRCOM,         { RT, RA } },
3567
3568 { "mullw",   XO(31,235,0,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3569 { "muls",    XO(31,235,0,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3570 { "mullw.",  XO(31,235,0,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3571 { "muls.",   XO(31,235,0,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3572 { "mullwo",  XO(31,235,1,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3573 { "mulso",   XO(31,235,1,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3574 { "mullwo.", XO(31,235,1,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3575 { "mulso.",  XO(31,235,1,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3576
3577 { "icblce",  X(31,238), X_MASK,         PPCCHLK64,      { CT, RA, RB }},
3578 { "mtsrin",  X(31,242), XRA_MASK,       PPC32,          { RS, RB } },
3579 { "mtsri",   X(31,242), XRA_MASK,       POWER32,        { RS, RB } },
3580
3581 { "dcbtst",  X(31,246), X_MASK, PPC,                    { CT, RA, RB } },
3582
3583 { "stbux",   X(31,247), X_MASK,         COM,            { RS, RAS, RB } },
3584
3585 { "slliq",   XRC(31,248,0), X_MASK,     M601,           { RA, RS, SH } },
3586 { "slliq.",  XRC(31,248,1), X_MASK,     M601,           { RA, RS, SH } },
3587
3588 { "dcbtste", X(31,253), X_MASK,         BOOKE64,        { CT, RA, RB } },
3589
3590 { "stbuxe",  X(31,255), X_MASK,         BOOKE64,        { RS, RAS, RB } },
3591
3592 { "mfdcrx",  X(31,259), X_MASK,         BOOKE,          { RS, RA } },
3593
3594 { "doz",     XO(31,264,0,0), XO_MASK,   M601,           { RT, RA, RB } },
3595 { "doz.",    XO(31,264,0,1), XO_MASK,   M601,           { RT, RA, RB } },
3596 { "dozo",    XO(31,264,1,0), XO_MASK,   M601,           { RT, RA, RB } },
3597 { "dozo.",   XO(31,264,1,1), XO_MASK,   M601,           { RT, RA, RB } },
3598
3599 { "add",     XO(31,266,0,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3600 { "cax",     XO(31,266,0,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3601 { "add.",    XO(31,266,0,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3602 { "cax.",    XO(31,266,0,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3603 { "addo",    XO(31,266,1,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3604 { "caxo",    XO(31,266,1,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3605 { "addo.",   XO(31,266,1,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3606 { "caxo.",   XO(31,266,1,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3607
3608 { "tlbiel",  X(31,274), XRTLRA_MASK,    POWER4,         { RB, L } },
3609
3610 { "mfapidi", X(31,275), X_MASK,         BOOKE,          { RT, RA } },
3611
3612 { "lscbx",   XRC(31,277,0), X_MASK,     M601,           { RT, RA, RB } },
3613 { "lscbx.",  XRC(31,277,1), X_MASK,     M601,           { RT, RA, RB } },
3614
3615 { "dcbt",    X(31,278), X_MASK, PPC,                    { CT, RA, RB } },
3616
3617 { "lhzx",    X(31,279), X_MASK,         COM,            { RT, RA0, RB } },
3618
3619 { "eqv",     XRC(31,284,0), X_MASK,     COM,            { RA, RS, RB } },
3620 { "eqv.",    XRC(31,284,1), X_MASK,     COM,            { RA, RS, RB } },
3621
3622 { "dcbte",   X(31,286), X_MASK,         BOOKE64,        { CT, RA, RB } },
3623
3624 { "lhzxe",   X(31,287), X_MASK,         BOOKE64,        { RT, RA0, RB } },
3625
3626 { "tlbie",   X(31,306), XRTLRA_MASK,    PPC,            { RB, L } },
3627 { "tlbi",    X(31,306), XRT_MASK,       POWER,          { RA0, RB } },
3628
3629 { "eciwx",   X(31,310), X_MASK,         PPC,            { RT, RA, RB } },
3630
3631 { "lhzux",   X(31,311), X_MASK,         COM,            { RT, RAL, RB } },
3632
3633 { "xor",     XRC(31,316,0), X_MASK,     COM,            { RA, RS, RB } },
3634 { "xor.",    XRC(31,316,1), X_MASK,     COM,            { RA, RS, RB } },
3635
3636 { "lhzuxe",  X(31,319), X_MASK,         BOOKE64,        { RT, RAL, RB } },
3637
3638 { "mfexisr",  XSPR(31,323,64),  XSPR_MASK, PPC403,      { RT } },
3639 { "mfexier",  XSPR(31,323,66),  XSPR_MASK, PPC403,      { RT } },
3640 { "mfbr0",    XSPR(31,323,128), XSPR_MASK, PPC403,      { RT } },
3641 { "mfbr1",    XSPR(31,323,129), XSPR_MASK, PPC403,      { RT } },
3642 { "mfbr2",    XSPR(31,323,130), XSPR_MASK, PPC403,      { RT } },
3643 { "mfbr3",    XSPR(31,323,131), XSPR_MASK, PPC403,      { RT } },
3644 { "mfbr4",    XSPR(31,323,132), XSPR_MASK, PPC403,      { RT } },
3645 { "mfbr5",    XSPR(31,323,133), XSPR_MASK, PPC403,      { RT } },
3646 { "mfbr6",    XSPR(31,323,134), XSPR_MASK, PPC403,      { RT } },
3647 { "mfbr7",    XSPR(31,323,135), XSPR_MASK, PPC403,      { RT } },
3648 { "mfbear",   XSPR(31,323,144), XSPR_MASK, PPC403,      { RT } },
3649 { "mfbesr",   XSPR(31,323,145), XSPR_MASK, PPC403,      { RT } },
3650 { "mfiocr",   XSPR(31,323,160), XSPR_MASK, PPC403,      { RT } },
3651 { "mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403,      { RT } },
3652 { "mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403,      { RT } },
3653 { "mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403,      { RT } },
3654 { "mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403,      { RT } },
3655 { "mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403,      { RT } },
3656 { "mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403,      { RT } },
3657 { "mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403,      { RT } },
3658 { "mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403,      { RT } },
3659 { "mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403,      { RT } },
3660 { "mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403,      { RT } },
3661 { "mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403,      { RT } },
3662 { "mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403,      { RT } },
3663 { "mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403,      { RT } },
3664 { "mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403,      { RT } },
3665 { "mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403,      { RT } },
3666 { "mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403,      { RT } },
3667 { "mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403,      { RT } },
3668 { "mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403,      { RT } },
3669 { "mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403,      { RT } },
3670 { "mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403,      { RT } },
3671 { "mfdmasr",  XSPR(31,323,224), XSPR_MASK, PPC403,      { RT } },
3672 { "mfdcr",    X(31,323),        X_MASK, PPC403 | BOOKE, { RT, SPR } },
3673
3674 { "div",     XO(31,331,0,0), XO_MASK,   M601,           { RT, RA, RB } },
3675 { "div.",    XO(31,331,0,1), XO_MASK,   M601,           { RT, RA, RB } },
3676 { "divo",    XO(31,331,1,0), XO_MASK,   M601,           { RT, RA, RB } },
3677 { "divo.",   XO(31,331,1,1), XO_MASK,   M601,           { RT, RA, RB } },
3678
3679 { "mfpmr",   X(31,334), X_MASK,         PPCPMR,         { RT, PMR }},
3680
3681 { "mfmq",       XSPR(31,339,0),    XSPR_MASK, M601,     { RT } },
3682 { "mfxer",      XSPR(31,339,1),    XSPR_MASK, COM,      { RT } },
3683 { "mfrtcu",     XSPR(31,339,4),    XSPR_MASK, COM,      { RT } },
3684 { "mfrtcl",     XSPR(31,339,5),    XSPR_MASK, COM,      { RT } },
3685 { "mfdec",      XSPR(31,339,6),    XSPR_MASK, MFDEC1,   { RT } },
3686 { "mfdec",      XSPR(31,339,22),   XSPR_MASK, MFDEC2,   { RT } },
3687 { "mflr",       XSPR(31,339,8),    XSPR_MASK, COM,      { RT } },
3688 { "mfctr",      XSPR(31,339,9),    XSPR_MASK, COM,      { RT } },
3689 { "mftid",      XSPR(31,339,17),   XSPR_MASK, POWER,    { RT } },
3690 { "mfdsisr",    XSPR(31,339,18),   XSPR_MASK, COM,      { RT } },
3691 { "mfdar",      XSPR(31,339,19),   XSPR_MASK, COM,      { RT } },
3692 { "mfsdr0",     XSPR(31,339,24),   XSPR_MASK, POWER,    { RT } },
3693 { "mfsdr1",     XSPR(31,339,25),   XSPR_MASK, COM,      { RT } },
3694 { "mfsrr0",     XSPR(31,339,26),   XSPR_MASK, COM,      { RT } },
3695 { "mfsrr1",     XSPR(31,339,27),   XSPR_MASK, COM,      { RT } },
3696 { "mfpid",      XSPR(31,339,48),   XSPR_MASK, BOOKE,    { RT } },
3697 { "mfpid",      XSPR(31,339,945),  XSPR_MASK, PPC403,   { RT } },
3698 { "mfcsrr0",    XSPR(31,339,58),   XSPR_MASK, BOOKE,    { RT } },
3699 { "mfcsrr1",    XSPR(31,339,59),   XSPR_MASK, BOOKE,    { RT } },
3700 { "mfdear",     XSPR(31,339,61),   XSPR_MASK, BOOKE,    { RT } },
3701 { "mfdear",     XSPR(31,339,981),  XSPR_MASK, PPC403,   { RT } },
3702 { "mfesr",      XSPR(31,339,62),   XSPR_MASK, BOOKE,    { RT } },
3703 { "mfesr",      XSPR(31,339,980),  XSPR_MASK, PPC403,   { RT } },
3704 { "mfivpr",     XSPR(31,339,63),   XSPR_MASK, BOOKE,    { RT } },
3705 { "mfcmpa",     XSPR(31,339,144),  XSPR_MASK, PPC860,   { RT } },
3706 { "mfcmpb",     XSPR(31,339,145),  XSPR_MASK, PPC860,   { RT } },
3707 { "mfcmpc",     XSPR(31,339,146),  XSPR_MASK, PPC860,   { RT } },
3708 { "mfcmpd",     XSPR(31,339,147),  XSPR_MASK, PPC860,   { RT } },
3709 { "mficr",      XSPR(31,339,148),  XSPR_MASK, PPC860,   { RT } },
3710 { "mfder",      XSPR(31,339,149),  XSPR_MASK, PPC860,   { RT } },
3711 { "mfcounta",   XSPR(31,339,150),  XSPR_MASK, PPC860,   { RT } },
3712 { "mfcountb",   XSPR(31,339,151),  XSPR_MASK, PPC860,   { RT } },
3713 { "mfcmpe",     XSPR(31,339,152),  XSPR_MASK, PPC860,   { RT } },
3714 { "mfcmpf",     XSPR(31,339,153),  XSPR_MASK, PPC860,   { RT } },
3715 { "mfcmpg",     XSPR(31,339,154),  XSPR_MASK, PPC860,   { RT } },
3716 { "mfcmph",     XSPR(31,339,155),  XSPR_MASK, PPC860,   { RT } },
3717 { "mflctrl1",   XSPR(31,339,156),  XSPR_MASK, PPC860,   { RT } },
3718 { "mflctrl2",   XSPR(31,339,157),  XSPR_MASK, PPC860,   { RT } },
3719 { "mfictrl",    XSPR(31,339,158),  XSPR_MASK, PPC860,   { RT } },
3720 { "mfbar",      XSPR(31,339,159),  XSPR_MASK, PPC860,   { RT } },
3721 { "mfvrsave",   XSPR(31,339,256),  XSPR_MASK, PPCVEC,   { RT } },
3722 { "mfusprg0",   XSPR(31,339,256),  XSPR_MASK, BOOKE,    { RT } },
3723 { "mftb",       X(31,371),         X_MASK,    CLASSIC,  { RT, TBR } },
3724 { "mftb",       XSPR(31,339,268),  XSPR_MASK, BOOKE,    { RT } },
3725 { "mftbl",      XSPR(31,371,268),  XSPR_MASK, CLASSIC,  { RT } },
3726 { "mftbl",      XSPR(31,339,268),  XSPR_MASK, BOOKE,    { RT } },
3727 { "mftbu",      XSPR(31,371,269),  XSPR_MASK, CLASSIC,  { RT } },
3728 { "mftbu",      XSPR(31,339,269),  XSPR_MASK, BOOKE,    { RT } },
3729 { "mfsprg",     XSPR(31,339,256),  XSPRG_MASK, PPC,     { RT, SPRG } },
3730 { "mfsprg0",    XSPR(31,339,272),  XSPR_MASK, PPC,      { RT } },
3731 { "mfsprg1",    XSPR(31,339,273),  XSPR_MASK, PPC,      { RT } },
3732 { "mfsprg2",    XSPR(31,339,274),  XSPR_MASK, PPC,      { RT } },
3733 { "mfsprg3",    XSPR(31,339,275),  XSPR_MASK, PPC,      { RT } },
3734 { "mfsprg4",    XSPR(31,339,260),  XSPR_MASK, PPC405 | BOOKE,   { RT } },
3735 { "mfsprg5",    XSPR(31,339,261),  XSPR_MASK, PPC405 | BOOKE,   { RT } },
3736 { "mfsprg6",    XSPR(31,339,262),  XSPR_MASK, PPC405 | BOOKE,   { RT } },
3737 { "mfsprg7",    XSPR(31,339,263),  XSPR_MASK, PPC405 | BOOKE,   { RT } },
3738 { "mfasr",      XSPR(31,339,280),  XSPR_MASK, PPC64,    { RT } },
3739 { "mfear",      XSPR(31,339,282),  XSPR_MASK, PPC,      { RT } },
3740 { "mfpir",      XSPR(31,339,286),  XSPR_MASK, BOOKE,    { RT } },
3741 { "mfpvr",      XSPR(31,339,287),  XSPR_MASK, PPC,      { RT } },
3742 { "mfdbsr",     XSPR(31,339,304),  XSPR_MASK, BOOKE,    { RT } },
3743 { "mfdbsr",     XSPR(31,339,1008), XSPR_MASK, PPC403,   { RT } },
3744 { "mfdbcr0",    XSPR(31,339,308),  XSPR_MASK, BOOKE,    { RT } },
3745 { "mfdbcr0",    XSPR(31,339,1010), XSPR_MASK, PPC405,   { RT } },
3746 { "mfdbcr1",    XSPR(31,339,309),  XSPR_MASK, BOOKE,    { RT } },
3747 { "mfdbcr1",    XSPR(31,339,957),  XSPR_MASK, PPC405,   { RT } },
3748 { "mfdbcr2",    XSPR(31,339,310),  XSPR_MASK, BOOKE,    { RT } },
3749 { "mfiac1",     XSPR(31,339,312),  XSPR_MASK, BOOKE,    { RT } },
3750 { "mfiac1",     XSPR(31,339,1012), XSPR_MASK, PPC403,   { RT } },
3751 { "mfiac2",     XSPR(31,339,313),  XSPR_MASK, BOOKE,    { RT } },
3752 { "mfiac2",     XSPR(31,339,1013), XSPR_MASK, PPC403,   { RT } },
3753 { "mfiac3",     XSPR(31,339,314),  XSPR_MASK, BOOKE,    { RT } },
3754 { "mfiac3",     XSPR(31,339,948),  XSPR_MASK, PPC405,   { RT } },
3755 { "mfiac4",     XSPR(31,339,315),  XSPR_MASK, BOOKE,    { RT } },
3756 { "mfiac4",     XSPR(31,339,949),  XSPR_MASK, PPC405,   { RT } },
3757 { "mfdac1",     XSPR(31,339,316),  XSPR_MASK, BOOKE,    { RT } },
3758 { "mfdac1",     XSPR(31,339,1014), XSPR_MASK, PPC403,   { RT } },
3759 { "mfdac2",     XSPR(31,339,317),  XSPR_MASK, BOOKE,    { RT } },
3760 { "mfdac2",     XSPR(31,339,1015), XSPR_MASK, PPC403,   { RT } },
3761 { "mfdvc1",     XSPR(31,339,318),  XSPR_MASK, BOOKE,    { RT } },
3762 { "mfdvc1",     XSPR(31,339,950),  XSPR_MASK, PPC405,   { RT } },
3763 { "mfdvc2",     XSPR(31,339,319),  XSPR_MASK, BOOKE,    { RT } },
3764 { "mfdvc2",     XSPR(31,339,951),  XSPR_MASK, PPC405,   { RT } },
3765 { "mftsr",      XSPR(31,339,336),  XSPR_MASK, BOOKE,    { RT } },
3766 { "mftsr",      XSPR(31,339,984),  XSPR_MASK, PPC403,   { RT } },
3767 { "mftcr",      XSPR(31,339,340),  XSPR_MASK, BOOKE,    { RT } },
3768 { "mftcr",      XSPR(31,339,986),  XSPR_MASK, PPC403,   { RT } },
3769 { "mfivor0",    XSPR(31,339,400),  XSPR_MASK, BOOKE,    { RT } },
3770 { "mfivor1",    XSPR(31,339,401),  XSPR_MASK, BOOKE,    { RT } },
3771 { "mfivor2",    XSPR(31,339,402),  XSPR_MASK, BOOKE,    { RT } },
3772 { "mfivor3",    XSPR(31,339,403),  XSPR_MASK, BOOKE,    { RT } },
3773 { "mfivor4",    XSPR(31,339,404),  XSPR_MASK, BOOKE,    { RT } },
3774 { "mfivor5",    XSPR(31,339,405),  XSPR_MASK, BOOKE,    { RT } },
3775 { "mfivor6",    XSPR(31,339,406),  XSPR_MASK, BOOKE,    { RT } },
3776 { "mfivor7",    XSPR(31,339,407),  XSPR_MASK, BOOKE,    { RT } },
3777 { "mfivor8",    XSPR(31,339,408),  XSPR_MASK, BOOKE,    { RT } },
3778 { "mfivor9",    XSPR(31,339,409),  XSPR_MASK, BOOKE,    { RT } },
3779 { "mfivor10",   XSPR(31,339,410),  XSPR_MASK, BOOKE,    { RT } },
3780 { "mfivor11",   XSPR(31,339,411),  XSPR_MASK, BOOKE,    { RT } },
3781 { "mfivor12",   XSPR(31,339,412),  XSPR_MASK, BOOKE,    { RT } },
3782 { "mfivor13",   XSPR(31,339,413),  XSPR_MASK, BOOKE,    { RT } },
3783 { "mfivor14",   XSPR(31,339,414),  XSPR_MASK, BOOKE,    { RT } },
3784 { "mfivor15",   XSPR(31,339,415),  XSPR_MASK, BOOKE,    { RT } },
3785 { "mfspefscr",  XSPR(31,339,512),  XSPR_MASK, PPCSPE,   { RT } },
3786 { "mfbbear",    XSPR(31,339,513),  XSPR_MASK, PPCBRLK,  { RT } },
3787 { "mfbbtar",    XSPR(31,339,514),  XSPR_MASK, PPCBRLK,  { RT } },
3788 { "mfivor32",   XSPR(31,339,528),  XSPR_MASK, PPCSPE,   { RT } },
3789 { "mfivor33",   XSPR(31,339,529),  XSPR_MASK, PPCSPE,   { RT } },
3790 { "mfivor34",   XSPR(31,339,530),  XSPR_MASK, PPCSPE,   { RT } },
3791 { "mfivor35",   XSPR(31,339,531),  XSPR_MASK, PPCPMR,   { RT } },
3792 { "mfibatu",    XSPR(31,339,528),  XSPRBAT_MASK, PPC,   { RT, SPRBAT } },
3793 { "mfibatl",    XSPR(31,339,529),  XSPRBAT_MASK, PPC,   { RT, SPRBAT } },
3794 { "mfdbatu",    XSPR(31,339,536),  XSPRBAT_MASK, PPC,   { RT, SPRBAT } },
3795 { "mfdbatl",    XSPR(31,339,537),  XSPRBAT_MASK, PPC,   { RT, SPRBAT } },
3796 { "mfic_cst",   XSPR(31,339,560),  XSPR_MASK, PPC860,   { RT } },
3797 { "mfic_adr",   XSPR(31,339,561),  XSPR_MASK, PPC860,   { RT } },
3798 { "mfic_dat",   XSPR(31,339,562),  XSPR_MASK, PPC860,   { RT } },
3799 { "mfdc_cst",   XSPR(31,339,568),  XSPR_MASK, PPC860,   { RT } },
3800 { "mfdc_adr",   XSPR(31,339,569),  XSPR_MASK, PPC860,   { RT } },
3801 { "mfmcsrr0",   XSPR(31,339,570),  XSPR_MASK, PPCRFMCI, { RT } },
3802 { "mfdc_dat",   XSPR(31,339,570),  XSPR_MASK, PPC860,   { RT } },
3803 { "mfmcsrr1",   XSPR(31,339,571),  XSPR_MASK, PPCRFMCI, { RT } },
3804 { "mfmcsr",     XSPR(31,339,572),  XSPR_MASK, PPCRFMCI, { RT } },
3805 { "mfmcar",     XSPR(31,339,573),  XSPR_MASK, PPCRFMCI, { RT } },
3806 { "mfdpdr",     XSPR(31,339,630),  XSPR_MASK, PPC860,   { RT } },
3807 { "mfdpir",     XSPR(31,339,631),  XSPR_MASK, PPC860,   { RT } },
3808 { "mfimmr",     XSPR(31,339,638),  XSPR_MASK, PPC860,   { RT } },
3809 { "mfmi_ctr",   XSPR(31,339,784),  XSPR_MASK, PPC860,   { RT } },
3810 { "mfmi_ap",    XSPR(31,339,786),  XSPR_MASK, PPC860,   { RT } },
3811 { "mfmi_epn",   XSPR(31,339,787),  XSPR_MASK, PPC860,   { RT } },
3812 { "mfmi_twc",   XSPR(31,339,789),  XSPR_MASK, PPC860,   { RT } },
3813 { "mfmi_rpn",   XSPR(31,339,790),  XSPR_MASK, PPC860,   { RT } },
3814 { "mfmd_ctr",   XSPR(31,339,792),  XSPR_MASK, PPC860,   { RT } },
3815 { "mfm_casid",  XSPR(31,339,793),  XSPR_MASK, PPC860,   { RT } },
3816 { "mfmd_ap",    XSPR(31,339,794),  XSPR_MASK, PPC860,   { RT } },
3817 { "mfmd_epn",   XSPR(31,339,795),  XSPR_MASK, PPC860,   { RT } },
3818 { "mfmd_twb",   XSPR(31,339,796),  XSPR_MASK, PPC860,   { RT } },
3819 { "mfmd_twc",   XSPR(31,339,797),  XSPR_MASK, PPC860,   { RT } },
3820 { "mfmd_rpn",   XSPR(31,339,798),  XSPR_MASK, PPC860,   { RT } },
3821 { "mfm_tw",     XSPR(31,339,799),  XSPR_MASK, PPC860,   { RT } },
3822 { "mfmi_dbcam", XSPR(31,339,816),  XSPR_MASK, PPC860,   { RT } },
3823 { "mfmi_dbram0",XSPR(31,339,817),  XSPR_MASK, PPC860,   { RT } },
3824 { "mfmi_dbram1",XSPR(31,339,818),  XSPR_MASK, PPC860,   { RT } },
3825 { "mfmd_dbcam", XSPR(31,339,824),  XSPR_MASK, PPC860,   { RT } },
3826 { "mfmd_dbram0",XSPR(31,339,825),  XSPR_MASK, PPC860,   { RT } },
3827 { "mfmd_dbram1",XSPR(31,339,826),  XSPR_MASK, PPC860,   { RT } },
3828 { "mfummcr0",   XSPR(31,339,936),  XSPR_MASK, PPC750,   { RT } },
3829 { "mfupmc1",    XSPR(31,339,937),  XSPR_MASK, PPC750,   { RT } },
3830 { "mfupmc2",    XSPR(31,339,938),  XSPR_MASK, PPC750,   { RT } },
3831 { "mfusia",     XSPR(31,339,939),  XSPR_MASK, PPC750,   { RT } },
3832 { "mfummcr1",   XSPR(31,339,940),  XSPR_MASK, PPC750,   { RT } },
3833 { "mfupmc3",    XSPR(31,339,941),  XSPR_MASK, PPC750,   { RT } },
3834 { "mfupmc4",    XSPR(31,339,942),  XSPR_MASK, PPC750,   { RT } },
3835 { "mfzpr",      XSPR(31,339,944),  XSPR_MASK, PPC403,   { RT } },
3836 { "mfccr0",     XSPR(31,339,947),  XSPR_MASK, PPC405,   { RT } },
3837 { "mfmmcr0",    XSPR(31,339,952),  XSPR_MASK, PPC750,   { RT } },
3838 { "mfpmc1",     XSPR(31,339,953),  XSPR_MASK, PPC750,   { RT } },
3839 { "mfsgr",      XSPR(31,339,953),  XSPR_MASK, PPC403,   { RT } },
3840 { "mfpmc2",     XSPR(31,339,954),  XSPR_MASK, PPC750,   { RT } },
3841 { "mfdcwr",     XSPR(31,339,954),  XSPR_MASK, PPC403,   { RT } },
3842 { "mfsia",      XSPR(31,339,955),  XSPR_MASK, PPC750,   { RT } },
3843 { "mfsler",     XSPR(31,339,955),  XSPR_MASK, PPC405,   { RT } },
3844 { "mfmmcr1",    XSPR(31,339,956),  XSPR_MASK, PPC750,   { RT } },
3845 { "mfsu0r",     XSPR(31,339,956),  XSPR_MASK, PPC405,   { RT } },
3846 { "mfpmc3",     XSPR(31,339,957),  XSPR_MASK, PPC750,   { RT } },
3847 { "mfpmc4",     XSPR(31,339,958),  XSPR_MASK, PPC750,   { RT } },
3848 { "mficdbdr",   XSPR(31,339,979),  XSPR_MASK, PPC403,   { RT } },
3849 { "mfevpr",     XSPR(31,339,982),  XSPR_MASK, PPC403,   { RT } },
3850 { "mfcdbcr",    XSPR(31,339,983),  XSPR_MASK, PPC403,   { RT } },
3851 { "mfpit",      XSPR(31,339,987),  XSPR_MASK, PPC403,   { RT } },
3852 { "mftbhi",     XSPR(31,339,988),  XSPR_MASK, PPC403,   { RT } },
3853 { "mftblo",     XSPR(31,339,989),  XSPR_MASK, PPC403,   { RT } },
3854 { "mfsrr2",     XSPR(31,339,990),  XSPR_MASK, PPC403,   { RT } },
3855 { "mfsrr3",     XSPR(31,339,991),  XSPR_MASK, PPC403,   { RT } },
3856 { "mfl2cr",     XSPR(31,339,1017), XSPR_MASK, PPC750,   { RT } },
3857 { "mfdccr",     XSPR(31,339,1018), XSPR_MASK, PPC403,   { RT } },
3858 { "mficcr",     XSPR(31,339,1019), XSPR_MASK, PPC403,   { RT } },
3859 { "mfictc",     XSPR(31,339,1019), XSPR_MASK, PPC750,   { RT } },
3860 { "mfpbl1",     XSPR(31,339,1020), XSPR_MASK, PPC403,   { RT } },
3861 { "mfthrm1",    XSPR(31,339,1020), XSPR_MASK, PPC750,   { RT } },
3862 { "mfpbu1",     XSPR(31,339,1021), XSPR_MASK, PPC403,   { RT } },
3863 { "mfthrm2",    XSPR(31,339,1021), XSPR_MASK, PPC750,   { RT } },
3864 { "mfpbl2",     XSPR(31,339,1022), XSPR_MASK, PPC403,   { RT } },
3865 { "mfthrm3",    XSPR(31,339,1022), XSPR_MASK, PPC750,   { RT } },
3866 { "mfpbu2",     XSPR(31,339,1023), XSPR_MASK, PPC403,   { RT } },
3867 { "mfspr",      X(31,339),         X_MASK,    COM,      { RT, SPR } },
3868
3869 { "lwax",    X(31,341), X_MASK,         PPC64,          { RT, RA0, RB } },
3870
3871 { "dst",     XDSS(31,342,0), XDSS_MASK, PPCVEC,         { RA, RB, STRM } },
3872 { "dstt",    XDSS(31,342,1), XDSS_MASK, PPCVEC,         { RA, RB, STRM } },
3873
3874 { "lhax",    X(31,343), X_MASK,         COM,            { RT, RA0, RB } },
3875
3876 { "lhaxe",   X(31,351), X_MASK,         BOOKE64,        { RT, RA0, RB } },
3877
3878 { "dstst",   XDSS(31,374,0), XDSS_MASK, PPCVEC,         { RA, RB, STRM } },
3879 { "dststt",  XDSS(31,374,1), XDSS_MASK, PPCVEC,         { RA, RB, STRM } },
3880
3881 { "dccci",   X(31,454), XRT_MASK,       PPC403|PPC440,  { RA, RB } },
3882
3883 { "abs",     XO(31,360,0,0), XORB_MASK, M601,           { RT, RA } },
3884 { "abs.",    XO(31,360,0,1), XORB_MASK, M601,           { RT, RA } },
3885 { "abso",    XO(31,360,1,0), XORB_MASK, M601,           { RT, RA } },
3886 { "abso.",   XO(31,360,1,1), XORB_MASK, M601,           { RT, RA } },
3887
3888 { "divs",    XO(31,363,0,0), XO_MASK,   M601,           { RT, RA, RB } },
3889 { "divs.",   XO(31,363,0,1), XO_MASK,   M601,           { RT, RA, RB } },
3890 { "divso",   XO(31,363,1,0), XO_MASK,   M601,           { RT, RA, RB } },
3891 { "divso.",  XO(31,363,1,1), XO_MASK,   M601,           { RT, RA, RB } },
3892
3893 { "tlbia",   X(31,370), 0xffffffff,     PPC,            { 0 } },
3894
3895 { "lwaux",   X(31,373), X_MASK,         PPC64,          { RT, RAL, RB } },
3896
3897 { "lhaux",   X(31,375), X_MASK,         COM,            { RT, RAL, RB } },
3898
3899 { "lhauxe",  X(31,383), X_MASK,         BOOKE64,        { RT, RAL, RB } },
3900
3901 { "mtdcrx",  X(31,387), X_MASK,         BOOKE,          { RA, RS } },
3902
3903 { "dcblc",   X(31,390), X_MASK,         PPCCHLK,        { CT, RA, RB }},
3904
3905 { "subfe64", XO(31,392,0,0), XO_MASK,   BOOKE64,        { RT, RA, RB } },
3906 { "subfe64o",XO(31,392,1,0), XO_MASK,   BOOKE64,        { RT, RA, RB } },
3907
3908 { "adde64",  XO(31,394,0,0), XO_MASK,   BOOKE64,        { RT, RA, RB } },
3909 { "adde64o", XO(31,394,1,0), XO_MASK,   BOOKE64,        { RT, RA, RB } },
3910
3911 { "dcblce",  X(31,398), X_MASK,         PPCCHLK64,      { CT, RA, RB }},
3912
3913 { "slbmte",  X(31,402), XRA_MASK,       PPC64,          { RS, RB } },
3914
3915 { "sthx",    X(31,407), X_MASK,         COM,            { RS, RA0, RB } },
3916
3917 { "lfqx",    X(31,791), X_MASK,         POWER2,         { FRT, RA, RB } },
3918
3919 { "lfqux",   X(31,823), X_MASK,         POWER2,         { FRT, RA, RB } },
3920
3921 { "stfqx",   X(31,919), X_MASK,         POWER2,         { FRS, RA, RB } },
3922
3923 { "stfqux",  X(31,951), X_MASK,         POWER2,         { FRS, RA, RB } },
3924
3925 { "orc",     XRC(31,412,0), X_MASK,     COM,            { RA, RS, RB } },
3926 { "orc.",    XRC(31,412,1), X_MASK,     COM,            { RA, RS, RB } },
3927
3928 { "sradi",   XS(31,413,0), XS_MASK,     PPC64,          { RA, RS, SH6 } },
3929 { "sradi.",  XS(31,413,1), XS_MASK,     PPC64,          { RA, RS, SH6 } },
3930
3931 { "sthxe",   X(31,415), X_MASK,         BOOKE64,        { RS, RA0, RB } },
3932
3933 { "slbie",   X(31,434), XRTRA_MASK,     PPC64,          { RB } },
3934
3935 { "ecowx",   X(31,438), X_MASK,         PPC,            { RT, RA, RB } },
3936
3937 { "sthux",   X(31,439), X_MASK,         COM,            { RS, RAS, RB } },
3938
3939 { "sthuxe",  X(31,447), X_MASK,         BOOKE64,        { RS, RAS, RB } },
3940
3941 { "mr",      XRC(31,444,0), X_MASK,     COM,            { RA, RS, RBS } },
3942 { "or",      XRC(31,444,0), X_MASK,     COM,            { RA, RS, RB } },
3943 { "mr.",     XRC(31,444,1), X_MASK,     COM,            { RA, RS, RBS } },
3944 { "or.",     XRC(31,444,1), X_MASK,     COM,            { RA, RS, RB } },
3945
3946 { "mtexisr",  XSPR(31,451,64),  XSPR_MASK, PPC403,      { RS } },
3947 { "mtexier",  XSPR(31,451,66),  XSPR_MASK, PPC403,      { RS } },
3948 { "mtbr0",    XSPR(31,451,128), XSPR_MASK, PPC403,      { RS } },
3949 { "mtbr1",    XSPR(31,451,129), XSPR_MASK, PPC403,      { RS } },
3950 { "mtbr2",    XSPR(31,451,130), XSPR_MASK, PPC403,      { RS } },
3951 { "mtbr3",    XSPR(31,451,131), XSPR_MASK, PPC403,      { RS } },
3952 { "mtbr4",    XSPR(31,451,132), XSPR_MASK, PPC403,      { RS } },
3953 { "mtbr5",    XSPR(31,451,133), XSPR_MASK, PPC403,      { RS } },
3954 { "mtbr6",    XSPR(31,451,134), XSPR_MASK, PPC403,      { RS } },
3955 { "mtbr7",    XSPR(31,451,135), XSPR_MASK, PPC403,      { RS } },
3956 { "mtbear",   XSPR(31,451,144), XSPR_MASK, PPC403,      { RS } },
3957 { "mtbesr",   XSPR(31,451,145), XSPR_MASK, PPC403,      { RS } },
3958 { "mtiocr",   XSPR(31,451,160), XSPR_MASK, PPC403,      { RS } },
3959 { "mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403,      { RS } },
3960 { "mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403,      { RS } },
3961 { "mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403,      { RS } },
3962 { "mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403,      { RS } },
3963 { "mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403,      { RS } },
3964 { "mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403,      { RS } },
3965 { "mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403,      { RS } },
3966 { "mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403,      { RS } },
3967 { "mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403,      { RS } },
3968 { "mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403,      { RS } },
3969 { "mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403,      { RS } },
3970 { "mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403,      { RS } },
3971 { "mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403,      { RS } },
3972 { "mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403,      { RS } },
3973 { "mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403,      { RS } },
3974 { "mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403,      { RS } },
3975 { "mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403,      { RS } },
3976 { "mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403,      { RS } },
3977 { "mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403,      { RS } },
3978 { "mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403,      { RS } },
3979 { "mtdmasr",  XSPR(31,451,224), XSPR_MASK, PPC403,      { RS } },
3980 { "mtdcr",    X(31,451),        X_MASK, PPC403 | BOOKE, { SPR, RS } },
3981
3982 { "subfze64",XO(31,456,0,0), XORB_MASK, BOOKE64,        { RT, RA } },
3983 { "subfze64o",XO(31,456,1,0), XORB_MASK, BOOKE64,       { RT, RA } },
3984
3985 { "divdu",   XO(31,457,0,0), XO_MASK,   PPC64,          { RT, RA, RB } },
3986 { "divdu.",  XO(31,457,0,1), XO_MASK,   PPC64,          { RT, RA, RB } },
3987 { "divduo",  XO(31,457,1,0), XO_MASK,   PPC64,          { RT, RA, RB } },
3988 { "divduo.", XO(31,457,1,1), XO_MASK,   PPC64,          { RT, RA, RB } },
3989
3990 { "addze64", XO(31,458,0,0), XORB_MASK, BOOKE64,        { RT, RA } },
3991 { "addze64o",XO(31,458,1,0), XORB_MASK, BOOKE64,        { RT, RA } },
3992
3993 { "divwu",   XO(31,459,0,0), XO_MASK,   PPC,            { RT, RA, RB } },
3994 { "divwu.",  XO(31,459,0,1), XO_MASK,   PPC,            { RT, RA, RB } },
3995 { "divwuo",  XO(31,459,1,0), XO_MASK,   PPC,            { RT, RA, RB } },
3996 { "divwuo.", XO(31,459,1,1), XO_MASK,   PPC,            { RT, RA, RB } },
3997
3998 { "mtmq",      XSPR(31,467,0),    XSPR_MASK, M601,      { RS } },
3999 { "mtxer",     XSPR(31,467,1),    XSPR_MASK, COM,       { RS } },
4000 { "mtlr",      XSPR(31,467,8),    XSPR_MASK, COM,       { RS } },
4001 { "mtctr",     XSPR(31,467,9),    XSPR_MASK, COM,       { RS } },
4002 { "mttid",     XSPR(31,467,17),   XSPR_MASK, POWER,     { RS } },
4003 { "mtdsisr",   XSPR(31,467,18),   XSPR_MASK, COM,       { RS } },
4004 { "mtdar",     XSPR(31,467,19),   XSPR_MASK, COM,       { RS } },
4005 { "mtrtcu",    XSPR(31,467,20),   XSPR_MASK, COM,       { RS } },
4006 { "mtrtcl",    XSPR(31,467,21),   XSPR_MASK, COM,       { RS } },
4007 { "mtdec",     XSPR(31,467,22),   XSPR_MASK, COM,       { RS } },
4008 { "mtsdr0",    XSPR(31,467,24),   XSPR_MASK, POWER,     { RS } },
4009 { "mtsdr1",    XSPR(31,467,25),   XSPR_MASK, COM,       { RS } },
4010 { "mtsrr0",    XSPR(31,467,26),   XSPR_MASK, COM,       { RS } },
4011 { "mtsrr1",    XSPR(31,467,27),   XSPR_MASK, COM,       { RS } },
4012 { "mtpid",     XSPR(31,467,48),   XSPR_MASK, BOOKE,     { RS } },
4013 { "mtpid",     XSPR(31,467,945),  XSPR_MASK, PPC403,    { RS } },
4014 { "mtdecar",   XSPR(31,467,54),   XSPR_MASK, BOOKE,     { RS } },
4015 { "mtcsrr0",   XSPR(31,467,58),   XSPR_MASK, BOOKE,     { RS } },
4016 { "mtcsrr1",   XSPR(31,467,59),   XSPR_MASK, BOOKE,     { RS } },
4017 { "mtdear",    XSPR(31,467,61),   XSPR_MASK, BOOKE,     { RS } },
4018 { "mtdear",    XSPR(31,467,981),  XSPR_MASK, PPC403,    { RS } },
4019 { "mtesr",     XSPR(31,467,62),   XSPR_MASK, BOOKE,     { RS } },
4020 { "mtesr",     XSPR(31,467,980),  XSPR_MASK, PPC403,    { RS } },
4021 { "mtivpr",    XSPR(31,467,63),   XSPR_MASK, BOOKE,     { RS } },
4022 { "mtcmpa",    XSPR(31,467,144),  XSPR_MASK, PPC860,    { RS } },
4023 { "mtcmpb",    XSPR(31,467,145),  XSPR_MASK, PPC860,    { RS } },
4024 { "mtcmpc",    XSPR(31,467,146),  XSPR_MASK, PPC860,    { RS } },
4025 { "mtcmpd",    XSPR(31,467,147),  XSPR_MASK, PPC860,    { RS } },
4026 { "mticr",     XSPR(31,467,148),  XSPR_MASK, PPC860,    { RS } },
4027 { "mtder",     XSPR(31,467,149),  XSPR_MASK, PPC860,    { RS } },
4028 { "mtcounta",  XSPR(31,467,150),  XSPR_MASK, PPC860,    { RS } },
4029 { "mtcountb",  XSPR(31,467,151),  XSPR_MASK, PPC860,    { RS } },
4030 { "mtcmpe",    XSPR(31,467,152),  XSPR_MASK, PPC860,    { RS } },
4031 { "mtcmpf",    XSPR(31,467,153),  XSPR_MASK, PPC860,    { RS } },
4032 { "mtcmpg",    XSPR(31,467,154),  XSPR_MASK, PPC860,    { RS } },
4033 { "mtcmph",    XSPR(31,467,155),  XSPR_MASK, PPC860,    { RS } },
4034 { "mtlctrl1",  XSPR(31,467,156),  XSPR_MASK, PPC860,    { RS } },
4035 { "mtlctrl2",  XSPR(31,467,157),  XSPR_MASK, PPC860,    { RS } },
4036 { "mtictrl",   XSPR(31,467,158),  XSPR_MASK, PPC860,    { RS } },
4037 { "mtbar",     XSPR(31,467,159),  XSPR_MASK, PPC860,    { RS } },
4038 { "mtvrsave",  XSPR(31,467,256),  XSPR_MASK, PPCVEC,    { RS } },
4039 { "mtusprg0",  XSPR(31,467,256),  XSPR_MASK, BOOKE,     { RS } },
4040 { "mtsprg",    XSPR(31,467,256),  XSPRG_MASK,PPC,       { SPRG, RS } },
4041 { "mtsprg0",   XSPR(31,467,272),  XSPR_MASK, PPC,       { RS } },
4042 { "mtsprg1",   XSPR(31,467,273),  XSPR_MASK, PPC,       { RS } },
4043 { "mtsprg2",   XSPR(31,467,274),  XSPR_MASK, PPC,       { RS } },
4044 { "mtsprg3",   XSPR(31,467,275),  XSPR_MASK, PPC,       { RS } },
4045 { "mtsprg4",   XSPR(31,467,276),  XSPR_MASK, PPC405 | BOOKE, { RS } },
4046 { "mtsprg5",   XSPR(31,467,277),  XSPR_MASK, PPC405 | BOOKE, { RS } },
4047 { "mtsprg6",   XSPR(31,467,278),  XSPR_MASK, PPC405 | BOOKE, { RS } },
4048 { "mtsprg7",   XSPR(31,467,279),  XSPR_MASK, PPC405 | BOOKE, { RS } },
4049 { "mtasr",     XSPR(31,467,280),  XSPR_MASK, PPC64,     { RS } },
4050 { "mtear",     XSPR(31,467,282),  XSPR_MASK, PPC,       { RS } },
4051 { "mttbl",     XSPR(31,467,284),  XSPR_MASK, PPC,       { RS } },
4052 { "mttbu",     XSPR(31,467,285),  XSPR_MASK, PPC,       { RS } },
4053 { "mtdbsr",    XSPR(31,467,304),  XSPR_MASK, BOOKE,     { RS } },
4054 { "mtdbsr",    XSPR(31,467,1008), XSPR_MASK, PPC403,    { RS } },
4055 { "mtdbcr0",   XSPR(31,467,308),  XSPR_MASK, BOOKE,     { RS } },
4056 { "mtdbcr0",   XSPR(31,467,1010), XSPR_MASK, PPC405,    { RS } },
4057 { "mtdbcr1",   XSPR(31,467,309),  XSPR_MASK, BOOKE,     { RS } },
4058 { "mtdbcr1",   XSPR(31,467,957),  XSPR_MASK, PPC405,    { RS } },
4059 { "mtdbcr2",   XSPR(31,467,310),  XSPR_MASK, BOOKE,     { RS } },
4060 { "mtiac1",    XSPR(31,467,312),  XSPR_MASK, BOOKE,     { RS } },
4061 { "mtiac1",    XSPR(31,467,1012), XSPR_MASK, PPC403,    { RS } },
4062 { "mtiac2",    XSPR(31,467,313),  XSPR_MASK, BOOKE,     { RS } },
4063 { "mtiac2",    XSPR(31,467,1013), XSPR_MASK, PPC403,    { RS } },
4064 { "mtiac3",    XSPR(31,467,314),  XSPR_MASK, BOOKE,     { RS } },
4065 { "mtiac3",    XSPR(31,467,948),  XSPR_MASK, PPC405,    { RS } },
4066 { "mtiac4",    XSPR(31,467,315),  XSPR_MASK, BOOKE,     { RS } },
4067 { "mtiac4",    XSPR(31,467,949),  XSPR_MASK, PPC405,    { RS } },
4068 { "mtdac1",    XSPR(31,467,316),  XSPR_MASK, BOOKE,     { RS } },
4069 { "mtdac1",    XSPR(31,467,1014), XSPR_MASK, PPC403,    { RS } },
4070 { "mtdac2",    XSPR(31,467,317),  XSPR_MASK, BOOKE,     { RS } },
4071 { "mtdac2",    XSPR(31,467,1015), XSPR_MASK, PPC403,    { RS } },
4072 { "mtdvc1",    XSPR(31,467,318),  XSPR_MASK, BOOKE,     { RS } },
4073 { "mtdvc1",    XSPR(31,467,950),  XSPR_MASK, PPC405,    { RS } },
4074 { "mtdvc2",    XSPR(31,467,319),  XSPR_MASK, BOOKE,     { RS } },
4075 { "mtdvc2",    XSPR(31,467,951),  XSPR_MASK, PPC405,    { RS } },
4076 { "mttsr",     XSPR(31,467,336),  XSPR_MASK, BOOKE,     { RS } },
4077 { "mttsr",     XSPR(31,467,984),  XSPR_MASK, PPC403,    { RS } },
4078 { "mttcr",     XSPR(31,467,340),  XSPR_MASK, BOOKE,     { RS } },
4079 { "mttcr",     XSPR(31,467,986),  XSPR_MASK, PPC403,    { RS } },
4080 { "mtivor0",   XSPR(31,467,400),  XSPR_MASK, BOOKE,     { RS } },
4081 { "mtivor1",   XSPR(31,467,401),  XSPR_MASK, BOOKE,     { RS } },
4082 { "mtivor2",   XSPR(31,467,402),  XSPR_MASK, BOOKE,     { RS } },
4083 { "mtivor3",   XSPR(31,467,403),  XSPR_MASK, BOOKE,     { RS } },
4084 { "mtivor4",   XSPR(31,467,404),  XSPR_MASK, BOOKE,     { RS } },
4085 { "mtivor5",   XSPR(31,467,405),  XSPR_MASK, BOOKE,     { RS } },
4086 { "mtivor6",   XSPR(31,467,406),  XSPR_MASK, BOOKE,     { RS } },
4087 { "mtivor7",   XSPR(31,467,407),  XSPR_MASK, BOOKE,     { RS } },
4088 { "mtivor8",   XSPR(31,467,408),  XSPR_MASK, BOOKE,     { RS } },
4089 { "mtivor9",   XSPR(31,467,409),  XSPR_MASK, BOOKE,     { RS } },
4090 { "mtivor10",  XSPR(31,467,410),  XSPR_MASK, BOOKE,     { RS } },
4091 { "mtivor11",  XSPR(31,467,411),  XSPR_MASK, BOOKE,     { RS } },
4092 { "mtivor12",  XSPR(31,467,412),  XSPR_MASK, BOOKE,     { RS } },
4093 { "mtivor13",  XSPR(31,467,413),  XSPR_MASK, BOOKE,     { RS } },
4094 { "mtivor14",  XSPR(31,467,414),  XSPR_MASK, BOOKE,     { RS } },
4095 { "mtivor15",  XSPR(31,467,415),  XSPR_MASK, BOOKE,     { RS } },
4096 { "mtspefscr",  XSPR(31,467,512),  XSPR_MASK, PPCSPE,   { RS } },
4097 { "mtbbear",   XSPR(31,467,513),  XSPR_MASK, PPCBRLK,   { RS } },
4098 { "mtbbtar",   XSPR(31,467,514),  XSPR_MASK, PPCBRLK,  { RS } },
4099 { "mtivor32",  XSPR(31,467,528),  XSPR_MASK, PPCSPE,    { RS } },
4100 { "mtivor33",  XSPR(31,467,529),  XSPR_MASK, PPCSPE,    { RS } },
4101 { "mtivor34",  XSPR(31,467,530),  XSPR_MASK, PPCSPE,    { RS } },
4102 { "mtivor35",  XSPR(31,467,531),  XSPR_MASK, PPCPMR,    { RS } },
4103 { "mtibatu",   XSPR(31,467,528),  XSPRBAT_MASK, PPC,    { SPRBAT, RS } },
4104 { "mtibatl",   XSPR(31,467,529),  XSPRBAT_MASK, PPC,    { SPRBAT, RS } },
4105 { "mtdbatu",   XSPR(31,467,536),  XSPRBAT_MASK, PPC,    { SPRBAT, RS } },
4106 { "mtdbatl",   XSPR(31,467,537),  XSPRBAT_MASK, PPC,    { SPRBAT, RS } },
4107 { "mtmcsrr0",  XSPR(31,467,570),  XSPR_MASK, PPCRFMCI,  { RS } },
4108 { "mtmcsrr1",  XSPR(31,467,571),  XSPR_MASK, PPCRFMCI,  { RS } },
4109 { "mtmcsr",    XSPR(31,467,572),  XSPR_MASK, PPCRFMCI,  { RS } },
4110 { "mtummcr0",  XSPR(31,467,936),  XSPR_MASK, PPC750,    { RS } },
4111 { "mtupmc1",   XSPR(31,467,937),  XSPR_MASK, PPC750,    { RS } },
4112 { "mtupmc2",   XSPR(31,467,938),  XSPR_MASK, PPC750,    { RS } },
4113 { "mtusia",    XSPR(31,467,939),  XSPR_MASK, PPC750,    { RS } },
4114 { "mtummcr1",  XSPR(31,467,940),  XSPR_MASK, PPC750,    { RS } },
4115 { "mtupmc3",   XSPR(31,467,941),  XSPR_MASK, PPC750,    { RS } },
4116 { "mtupmc4",   XSPR(31,467,942),  XSPR_MASK, PPC750,    { RS } },
4117 { "mtzpr",     XSPR(31,467,944),  XSPR_MASK, PPC403,    { RS } },
4118 { "mtccr0",    XSPR(31,467,947),  XSPR_MASK, PPC405,    { RS } },
4119 { "mtmmcr0",   XSPR(31,467,952),  XSPR_MASK, PPC750,    { RS } },
4120 { "mtsgr",     XSPR(31,467,953),  XSPR_MASK, PPC403,    { RS } },
4121 { "mtpmc1",    XSPR(31,467,953),  XSPR_MASK, PPC750,    { RS } },
4122 { "mtdcwr",    XSPR(31,467,954),  XSPR_MASK, PPC403,    { RS } },
4123 { "mtpmc2",    XSPR(31,467,954),  XSPR_MASK, PPC750,    { RS } },
4124 { "mtsler",    XSPR(31,467,955),  XSPR_MASK, PPC405,    { RS } },
4125 { "mtsia",     XSPR(31,467,955),  XSPR_MASK, PPC750,    { RS } },
4126 { "mtsu0r",    XSPR(31,467,956),  XSPR_MASK, PPC405,    { RS } },
4127 { "mtmmcr1",   XSPR(31,467,956),  XSPR_MASK, PPC750,    { RS } },
4128 { "mtpmc3",    XSPR(31,467,957),  XSPR_MASK, PPC750,    { RS } },
4129 { "mtpmc4",    XSPR(31,467,958),  XSPR_MASK, PPC750,    { RS } },
4130 { "mticdbdr",  XSPR(31,467,979),  XSPR_MASK, PPC403,    { RS } },
4131 { "mtevpr",    XSPR(31,467,982),  XSPR_MASK, PPC403,    { RS } },
4132 { "mtcdbcr",   XSPR(31,467,983),  XSPR_MASK, PPC403,    { RS } },
4133 { "mtpit",     XSPR(31,467,987),  XSPR_MASK, PPC403,    { RS } },
4134 { "mttbhi",    XSPR(31,467,988),  XSPR_MASK, PPC403,    { RS } },
4135 { "mttblo",    XSPR(31,467,989),  XSPR_MASK, PPC403,    { RS } },
4136 { "mtsrr2",    XSPR(31,467,990),  XSPR_MASK, PPC403,    { RS } },
4137 { "mtsrr3",    XSPR(31,467,991),  XSPR_MASK, PPC403,    { RS } },
4138 { "mtl2cr",    XSPR(31,467,1017), XSPR_MASK, PPC750,    { RS } },
4139 { "mtdccr",    XSPR(31,467,1018), XSPR_MASK, PPC403,    { RS } },
4140 { "mticcr",    XSPR(31,467,1019), XSPR_MASK, PPC403,    { RS } },
4141 { "mtictc",    XSPR(31,467,1019), XSPR_MASK, PPC750,    { RS } },
4142 { "mtpbl1",    XSPR(31,467,1020), XSPR_MASK, PPC403,    { RS } },
4143 { "mtthrm1",   XSPR(31,467,1020), XSPR_MASK, PPC750,    { RS } },
4144 { "mtpbu1",    XSPR(31,467,1021), XSPR_MASK, PPC403,    { RS } },
4145 { "mtthrm2",   XSPR(31,467,1021), XSPR_MASK, PPC750,    { RS } },
4146 { "mtpbl2",    XSPR(31,467,1022), XSPR_MASK, PPC403,    { RS } },
4147 { "mtthrm3",   XSPR(31,467,1022), XSPR_MASK, PPC750,    { RS } },
4148 { "mtpbu2",    XSPR(31,467,1023), XSPR_MASK, PPC403,    { RS } },
4149 { "mtspr",     X(31,467),         X_MASK,    COM,       { SPR, RS } },
4150
4151 { "dcbi",    X(31,470), XRT_MASK,       PPC,            { RA, RB } },
4152
4153 { "nand",    XRC(31,476,0), X_MASK,     COM,            { RA, RS, RB } },
4154 { "nand.",   XRC(31,476,1), X_MASK,     COM,            { RA, RS, RB } },
4155
4156 { "dcbie",   X(31,478), XRT_MASK,       BOOKE64,        { RA, RB } },
4157
4158 { "dcread",  X(31,486), X_MASK,         PPC403|PPC440,  { RT, RA, RB }},
4159
4160 { "mtpmr",   X(31,462), X_MASK,         PPCPMR,         { PMR, RS }},
4161
4162 { "icbtls",  X(31,486), X_MASK,         PPCCHLK,        { CT, RA, RB }},
4163
4164 { "nabs",    XO(31,488,0,0), XORB_MASK, M601,           { RT, RA } },
4165 { "subfme64",XO(31,488,0,0), XORB_MASK, BOOKE64,        { RT, RA } },
4166 { "nabs.",   XO(31,488,0,1), XORB_MASK, M601,           { RT, RA } },
4167 { "nabso",   XO(31,488,1,0), XORB_MASK, M601,           { RT, RA } },
4168 { "subfme64o",XO(31,488,1,0), XORB_MASK, BOOKE64,       { RT, RA } },
4169 { "nabso.",  XO(31,488,1,1), XORB_MASK, M601,           { RT, RA } },
4170
4171 { "divd",    XO(31,489,0,0), XO_MASK,   PPC64,          { RT, RA, RB } },
4172 { "divd.",   XO(31,489,0,1), XO_MASK,   PPC64,          { RT, RA, RB } },
4173 { "divdo",   XO(31,489,1,0), XO_MASK,   PPC64,          { RT, RA, RB } },
4174 { "divdo.",  XO(31,489,1,1), XO_MASK,   PPC64,          { RT, RA, RB } },
4175
4176 { "addme64", XO(31,490,0,0), XORB_MASK, BOOKE64,        { RT, RA } },
4177 { "addme64o",XO(31,490,1,0), XORB_MASK, BOOKE64,        { RT, RA } },
4178
4179 { "divw",    XO(31,491,0,0), XO_MASK,   PPC,            { RT, RA, RB } },
4180 { "divw.",   XO(31,491,0,1), XO_MASK,   PPC,            { RT, RA, RB } },
4181 { "divwo",   XO(31,491,1,0), XO_MASK,   PPC,            { RT, RA, RB } },
4182 { "divwo.",  XO(31,491,1,1), XO_MASK,   PPC,            { RT, RA, RB } },
4183
4184 { "icbtlse", X(31,494), X_MASK,         PPCCHLK64,      { CT, RA, RB }},
4185
4186 { "slbia",   X(31,498), 0xffffffff,     PPC64,          { 0 } },
4187
4188 { "cli",     X(31,502), XRB_MASK,       POWER,          { RT, RA } },
4189
4190 { "stdcxe.", XRC(31,511,1), X_MASK,     BOOKE64,        { RS, RA, RB } },
4191
4192 { "mcrxr",   X(31,512), XRARB_MASK|(3<<21), COM,        { BF } },
4193
4194 { "bblels",  X(31,518), X_MASK,         PPCBRLK,        { 0 }},
4195 { "mcrxr64", X(31,544), XRARB_MASK|(3<<21), BOOKE64,    { BF } },
4196
4197 { "clcs",    X(31,531), XRB_MASK,       M601,           { RT, RA } },
4198
4199 { "lswx",    X(31,533), X_MASK,         PPCCOM,         { RT, RA0, RB } },
4200 { "lsx",     X(31,533), X_MASK,         PWRCOM,         { RT, RA, RB } },
4201
4202 { "lwbrx",   X(31,534), X_MASK,         PPCCOM,         { RT, RA0, RB } },
4203 { "lbrx",    X(31,534), X_MASK,         PWRCOM,         { RT, RA, RB } },
4204
4205 { "lfsx",    X(31,535), X_MASK,         COM,            { FRT, RA0, RB } },
4206
4207 { "srw",     XRC(31,536,0), X_MASK,     PPCCOM,         { RA, RS, RB } },
4208 { "sr",      XRC(31,536,0), X_MASK,     PWRCOM,         { RA, RS, RB } },
4209 { "srw.",    XRC(31,536,1), X_MASK,     PPCCOM,         { RA, RS, RB } },
4210 { "sr.",     XRC(31,536,1), X_MASK,     PWRCOM,         { RA, RS, RB } },
4211
4212 { "rrib",    XRC(31,537,0), X_MASK,     M601,           { RA, RS, RB } },
4213 { "rrib.",   XRC(31,537,1), X_MASK,     M601,           { RA, RS, RB } },
4214
4215 { "srd",     XRC(31,539,0), X_MASK,     PPC64,          { RA, RS, RB } },
4216 { "srd.",    XRC(31,539,1), X_MASK,     PPC64,          { RA, RS, RB } },
4217
4218 { "maskir",  XRC(31,541,0), X_MASK,     M601,           { RA, RS, RB } },
4219 { "maskir.", XRC(31,541,1), X_MASK,     M601,           { RA, RS, RB } },
4220
4221 { "lwbrxe",  X(31,542), X_MASK,         BOOKE64,        { RT, RA0, RB } },
4222
4223 { "lfsxe",   X(31,543), X_MASK,         BOOKE64,        { FRT, RA0, RB } },
4224
4225 { "bbelr",   X(31,550), X_MASK,         PPCBRLK,        { 0 }},
4226
4227 { "tlbsync", X(31,566), 0xffffffff,     PPC,            { 0 } },
4228
4229 { "lfsux",   X(31,567), X_MASK,         COM,            { FRT, RAS, RB } },
4230
4231 { "lfsuxe",  X(31,575), X_MASK,         BOOKE64,        { FRT, RAS, RB } },
4232
4233 { "mfsr",    X(31,595), XRB_MASK|(1<<20), COM32,        { RT, SR } },
4234
4235 { "lswi",    X(31,597), X_MASK,         PPCCOM,         { RT, RA0, NB } },
4236 { "lsi",     X(31,597), X_MASK,         PWRCOM,         { RT, RA0, NB } },
4237
4238 { "lwsync",  XSYNC(31,598,1), 0xffffffff, PPC,          { 0 } },
4239 { "ptesync", XSYNC(31,598,2), 0xffffffff, PPC64,        { 0 } },
4240 { "msync",   X(31,598), 0xffffffff,     BOOKE,          { 0 } },
4241 { "sync",    X(31,598), XSYNC_MASK,     PPCCOM,         { LS } },
4242 { "dcs",     X(31,598), 0xffffffff,     PWRCOM,         { 0 } },
4243
4244 { "lfdx",    X(31,599), X_MASK,         COM,            { FRT, RA0, RB } },
4245
4246 { "lfdxe",   X(31,607), X_MASK,         BOOKE64,        { FRT, RA0, RB } },
4247
4248 { "mfsri",   X(31,627), X_MASK,         PWRCOM,         { RT, RA, RB } },
4249
4250 { "dclst",   X(31,630), XRB_MASK,       PWRCOM,         { RS, RA } },
4251
4252 { "lfdux",   X(31,631), X_MASK,         COM,            { FRT, RAS, RB } },
4253
4254 { "lfduxe",  X(31,639), X_MASK,         BOOKE64,        { FRT, RAS, RB } },
4255
4256 { "mfsrin",  X(31,659), XRA_MASK,       PPC32,          { RT, RB } },
4257
4258 { "stswx",   X(31,661), X_MASK,         PPCCOM,         { RS, RA0, RB } },
4259 { "stsx",    X(31,661), X_MASK,         PWRCOM,         { RS, RA0, RB } },
4260
4261 { "stwbrx",  X(31,662), X_MASK,         PPCCOM,         { RS, RA0, RB } },
4262 { "stbrx",   X(31,662), X_MASK,         PWRCOM,         { RS, RA0, RB } },
4263
4264 { "stfsx",   X(31,663), X_MASK,         COM,            { FRS, RA0, RB } },
4265
4266 { "srq",     XRC(31,664,0), X_MASK,     M601,           { RA, RS, RB } },
4267 { "srq.",    XRC(31,664,1), X_MASK,     M601,           { RA, RS, RB } },
4268
4269 { "sre",     XRC(31,665,0), X_MASK,     M601,           { RA, RS, RB } },
4270 { "sre.",    XRC(31,665,1), X_MASK,     M601,           { RA, RS, RB } },
4271
4272 { "stwbrxe", X(31,670), X_MASK,         BOOKE64,        { RS, RA0, RB } },
4273
4274 { "stfsxe",  X(31,671), X_MASK,         BOOKE64,        { FRS, RA0, RB } },
4275
4276 { "stfsux",  X(31,695), X_MASK,         COM,            { FRS, RAS, RB } },
4277
4278 { "sriq",    XRC(31,696,0), X_MASK,     M601,           { RA, RS, SH } },
4279 { "sriq.",   XRC(31,696,1), X_MASK,     M601,           { RA, RS, SH } },
4280
4281 { "stfsuxe", X(31,703), X_MASK,         BOOKE64,        { FRS, RAS, RB } },
4282
4283 { "stswi",   X(31,725), X_MASK,         PPCCOM,         { RS, RA0, NB } },
4284 { "stsi",    X(31,725), X_MASK,         PWRCOM,         { RS, RA0, NB } },
4285
4286 { "stfdx",   X(31,727), X_MASK,         COM,            { FRS, RA0, RB } },
4287
4288 { "srlq",    XRC(31,728,0), X_MASK,     M601,           { RA, RS, RB } },
4289 { "srlq.",   XRC(31,728,1), X_MASK,     M601,           { RA, RS, RB } },
4290
4291 { "sreq",    XRC(31,729,0), X_MASK,     M601,           { RA, RS, RB } },
4292 { "sreq.",   XRC(31,729,1), X_MASK,     M601,           { RA, RS, RB } },
4293
4294 { "stfdxe",  X(31,735), X_MASK,         BOOKE64,        { FRS, RA0, RB } },
4295
4296 { "dcba",    X(31,758), XRT_MASK,       PPC405 | BOOKE, { RA, RB } },
4297
4298 { "stfdux",  X(31,759), X_MASK,         COM,            { FRS, RAS, RB } },
4299
4300 { "srliq",   XRC(31,760,0), X_MASK,     M601,           { RA, RS, SH } },
4301 { "srliq.",  XRC(31,760,1), X_MASK,     M601,           { RA, RS, SH } },
4302
4303 { "dcbae",   X(31,766), XRT_MASK,       BOOKE64,        { RA, RB } },
4304
4305 { "stfduxe", X(31,767), X_MASK,         BOOKE64,        { FRS, RAS, RB } },
4306
4307 { "tlbivax", X(31,786), XRT_MASK,       BOOKE,          { RA, RB } },
4308 { "tlbivaxe",X(31,787), XRT_MASK,       BOOKE64,        { RA, RB } },
4309
4310 { "lhbrx",   X(31,790), X_MASK,         COM,            { RT, RA0, RB } },
4311
4312 { "sraw",    XRC(31,792,0), X_MASK,     PPCCOM,         { RA, RS, RB } },
4313 { "sra",     XRC(31,792,0), X_MASK,     PWRCOM,         { RA, RS, RB } },
4314 { "sraw.",   XRC(31,792,1), X_MASK,     PPCCOM,         { RA, RS, RB } },
4315 { "sra.",    XRC(31,792,1), X_MASK,     PWRCOM,         { RA, RS, RB } },
4316
4317 { "srad",    XRC(31,794,0), X_MASK,     PPC64,          { RA, RS, RB } },
4318 { "srad.",   XRC(31,794,1), X_MASK,     PPC64,          { RA, RS, RB } },
4319
4320 { "lhbrxe",  X(31,798), X_MASK,         BOOKE64,        { RT, RA0, RB } },
4321
4322 { "ldxe",    X(31,799), X_MASK,         BOOKE64,        { RT, RA0, RB } },
4323 { "lduxe",   X(31,831), X_MASK,         BOOKE64,        { RT, RA0, RB } },
4324
4325 { "rac",     X(31,818), X_MASK,         PWRCOM,         { RT, RA, RB } },
4326
4327 { "dss",     XDSS(31,822,0), XDSS_MASK, PPCVEC,         { STRM } },
4328 { "dssall",  XDSS(31,822,1), XDSS_MASK, PPCVEC,         { 0 } },
4329
4330 { "srawi",   XRC(31,824,0), X_MASK,     PPCCOM,         { RA, RS, SH } },
4331 { "srai",    XRC(31,824,0), X_MASK,     PWRCOM,         { RA, RS, SH } },
4332 { "srawi.",  XRC(31,824,1), X_MASK,     PPCCOM,         { RA, RS, SH } },
4333 { "srai.",   XRC(31,824,1), X_MASK,     PWRCOM,         { RA, RS, SH } },
4334
4335 { "slbmfev", X(31,851), XRA_MASK,       PPC64,          { RT, RB } },
4336
4337 { "mbar",    X(31,854), X_MASK,         BOOKE,          { MO } },
4338 { "eieio",   X(31,854), 0xffffffff,     PPC,            { 0 } },
4339
4340 { "tlbsx",   XRC(31,914,0), X_MASK,     PPC403|BOOKE,   { RTO, RA, RB } },
4341 { "tlbsx.",  XRC(31,914,1), X_MASK,     PPC403|BOOKE,   { RTO, RA, RB } },
4342 { "tlbsxe",  XRC(31,915,0), X_MASK,     BOOKE64,        { RA, RB } },
4343 { "tlbsxe.", XRC(31,915,1), X_MASK,     BOOKE64,        { RA, RB } },
4344
4345 { "slbmfee", X(31,915), XRA_MASK,       PPC64,          { RT, RB } },
4346
4347 { "sthbrx",  X(31,918), X_MASK,         COM,            { RS, RA0, RB } },
4348
4349 { "sraq",    XRC(31,920,0), X_MASK,     M601,           { RA, RS, RB } },
4350 { "sraq.",   XRC(31,920,1), X_MASK,     M601,           { RA, RS, RB } },
4351
4352 { "srea",    XRC(31,921,0), X_MASK,     M601,           { RA, RS, RB } },
4353 { "srea.",   XRC(31,921,1), X_MASK,     M601,           { RA, RS, RB } },
4354
4355 { "extsh",   XRC(31,922,0), XRB_MASK,   PPCCOM,         { RA, RS } },
4356 { "exts",    XRC(31,922,0), XRB_MASK,   PWRCOM,         { RA, RS } },
4357 { "extsh.",  XRC(31,922,1), XRB_MASK,   PPCCOM,         { RA, RS } },
4358 { "exts.",   XRC(31,922,1), XRB_MASK,   PWRCOM,         { RA, RS } },
4359
4360 { "sthbrxe", X(31,926), X_MASK,         BOOKE64,        { RS, RA0, RB } },
4361
4362 { "stdxe",   X(31,927), X_MASK,         BOOKE64,        { RS, RA0, RB } },
4363
4364 { "tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403,         { RT, RA } },
4365 { "tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403,         { RT, RA } },
4366 { "tlbre",   X(31,946), X_MASK,         PPC403|BOOKE,   { RSO, RAOPT, SHO } },
4367
4368 { "sraiq",   XRC(31,952,0), X_MASK,     M601,           { RA, RS, SH } },
4369 { "sraiq.",  XRC(31,952,1), X_MASK,     M601,           { RA, RS, SH } },
4370
4371 { "extsb",   XRC(31,954,0), XRB_MASK,   PPC,            { RA, RS} },
4372 { "extsb.",  XRC(31,954,1), XRB_MASK,   PPC,            { RA, RS} },
4373
4374 { "stduxe",  X(31,959), X_MASK,         BOOKE64,        { RS, RAS, RB } },
4375
4376 { "iccci",   X(31,966), XRT_MASK,       PPC403|PPC440,  { RA, RB } },
4377
4378 { "tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403,         { RT, RA } },
4379 { "tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403,         { RT, RA } },
4380 { "tlbwe",   X(31,978), X_MASK,         PPC403|BOOKE,   { RSO, RAOPT, SHO } },
4381 { "tlbld",   X(31,978), XRTRA_MASK,     PPC,            { RB } },
4382
4383 { "icbi",    X(31,982), XRT_MASK,       PPC,            { RA, RB } },
4384
4385 { "stfiwx",  X(31,983), X_MASK,         PPC,            { FRS, RA0, RB } },
4386
4387 { "extsw",   XRC(31,986,0), XRB_MASK,   PPC64 | BOOKE64,{ RA, RS } },
4388 { "extsw.",  XRC(31,986,1), XRB_MASK,   PPC64,          { RA, RS } },
4389
4390 { "icread",  X(31,998), XRT_MASK,       PPC403|PPC440,  { RA, RB } },
4391
4392 { "icbie",   X(31,990), XRT_MASK,       BOOKE64,        { RA, RB } },
4393 { "stfiwxe", X(31,991), X_MASK,         BOOKE64,        { FRS, RA0, RB } },
4394
4395 { "tlbli",   X(31,1010), XRTRA_MASK,    PPC,            { RB } },
4396
4397 { "dcbzl",   XOPL(31,1014,1), XRT_MASK,POWER4,            { RA, RB } },
4398 { "dcbz",    X(31,1014), XRT_MASK,      PPC,            { RA, RB } },
4399 { "dclz",    X(31,1014), XRT_MASK,      PPC,            { RA, RB } },
4400
4401 { "dcbze",   X(31,1022), XRT_MASK,      BOOKE64,        { RA, RB } },
4402
4403 { "lvebx",   X(31,   7), X_MASK,        PPCVEC,         { VD, RA, RB } },
4404 { "lvehx",   X(31,  39), X_MASK,        PPCVEC,         { VD, RA, RB } },
4405 { "lvewx",   X(31,  71), X_MASK,        PPCVEC,         { VD, RA, RB } },
4406 { "lvsl",    X(31,   6), X_MASK,        PPCVEC,         { VD, RA, RB } },
4407 { "lvsr",    X(31,  38), X_MASK,        PPCVEC,         { VD, RA, RB } },
4408 { "lvx",     X(31, 103), X_MASK,        PPCVEC,         { VD, RA, RB } },
4409 { "lvxl",    X(31, 359), X_MASK,        PPCVEC,         { VD, RA, RB } },
4410 { "stvebx",  X(31, 135), X_MASK,        PPCVEC,         { VS, RA, RB } },
4411 { "stvehx",  X(31, 167), X_MASK,        PPCVEC,         { VS, RA, RB } },
4412 { "stvewx",  X(31, 199), X_MASK,        PPCVEC,         { VS, RA, RB } },
4413 { "stvx",    X(31, 231), X_MASK,        PPCVEC,         { VS, RA, RB } },
4414 { "stvxl",   X(31, 487), X_MASK,        PPCVEC,         { VS, RA, RB } },
4415
4416 { "lwz",     OP(32),    OP_MASK,        PPCCOM,         { RT, D, RA0 } },
4417 { "l",       OP(32),    OP_MASK,        PWRCOM,         { RT, D, RA0 } },
4418
4419 { "lwzu",    OP(33),    OP_MASK,        PPCCOM,         { RT, D, RAL } },
4420 { "lu",      OP(33),    OP_MASK,        PWRCOM,         { RT, D, RA0 } },
4421
4422 { "lbz",     OP(34),    OP_MASK,        COM,            { RT, D, RA0 } },
4423
4424 { "lbzu",    OP(35),    OP_MASK,        COM,            { RT, D, RAL } },
4425
4426 { "stw",     OP(36),    OP_MASK,        PPCCOM,         { RS, D, RA0 } },
4427 { "st",      OP(36),    OP_MASK,        PWRCOM,         { RS, D, RA0 } },
4428
4429 { "stwu",    OP(37),    OP_MASK,        PPCCOM,         { RS, D, RAS } },
4430 { "stu",     OP(37),    OP_MASK,        PWRCOM,         { RS, D, RA0 } },
4431
4432 { "stb",     OP(38),    OP_MASK,        COM,            { RS, D, RA0 } },
4433
4434 { "stbu",    OP(39),    OP_MASK,        COM,            { RS, D, RAS } },
4435
4436 { "lhz",     OP(40),    OP_MASK,        COM,            { RT, D, RA0 } },
4437
4438 { "lhzu",    OP(41),    OP_MASK,        COM,            { RT, D, RAL } },
4439
4440 { "lha",     OP(42),    OP_MASK,        COM,            { RT, D, RA0 } },
4441
4442 { "lhau",    OP(43),    OP_MASK,        COM,            { RT, D, RAL } },
4443
4444 { "sth",     OP(44),    OP_MASK,        COM,            { RS, D, RA0 } },
4445
4446 { "sthu",    OP(45),    OP_MASK,        COM,            { RS, D, RAS } },
4447
4448 { "lmw",     OP(46),    OP_MASK,        PPCCOM,         { RT, D, RAM } },
4449 { "lm",      OP(46),    OP_MASK,        PWRCOM,         { RT, D, RA0 } },
4450
4451 { "stmw",    OP(47),    OP_MASK,        PPCCOM,         { RS, D, RA0 } },
4452 { "stm",     OP(47),    OP_MASK,        PWRCOM,         { RS, D, RA0 } },
4453
4454 { "lfs",     OP(48),    OP_MASK,        COM,            { FRT, D, RA0 } },
4455
4456 { "lfsu",    OP(49),    OP_MASK,        COM,            { FRT, D, RAS } },
4457
4458 { "lfd",     OP(50),    OP_MASK,        COM,            { FRT, D, RA0 } },
4459
4460 { "lfdu",    OP(51),    OP_MASK,        COM,            { FRT, D, RAS } },
4461
4462 { "stfs",    OP(52),    OP_MASK,        COM,            { FRS, D, RA0 } },
4463
4464 { "stfsu",   OP(53),    OP_MASK,        COM,            { FRS, D, RAS } },
4465
4466 { "stfd",    OP(54),    OP_MASK,        COM,            { FRS, D, RA0 } },
4467
4468 { "stfdu",   OP(55),    OP_MASK,        COM,            { FRS, D, RAS } },
4469
4470 { "lq",      OP(56),    OP_MASK,        POWER4,         { RTQ, DQ, RAQ } },
4471
4472 { "lfq",     OP(56),    OP_MASK,        POWER2,         { FRT, D, RA0 } },
4473
4474 { "lfqu",    OP(57),    OP_MASK,        POWER2,         { FRT, D, RA0 } },
4475
4476 { "lbze",    DEO(58,0), DE_MASK,        BOOKE64,        { RT, DE, RA0 } },
4477 { "lbzue",   DEO(58,1), DE_MASK,        BOOKE64,        { RT, DE, RAL } },
4478 { "lhze",    DEO(58,2), DE_MASK,        BOOKE64,        { RT, DE, RA0 } },
4479 { "lhzue",   DEO(58,3), DE_MASK,        BOOKE64,        { RT, DE, RAL } },
4480 { "lhae",    DEO(58,4), DE_MASK,        BOOKE64,        { RT, DE, RA0 } },
4481 { "lhaue",   DEO(58,5), DE_MASK,        BOOKE64,        { RT, DE, RAL } },
4482 { "lwze",    DEO(58,6), DE_MASK,        BOOKE64,        { RT, DE, RA0 } },
4483 { "lwzue",   DEO(58,7), DE_MASK,        BOOKE64,        { RT, DE, RAL } },
4484 { "stbe",    DEO(58,8), DE_MASK,        BOOKE64,        { RS, DE, RA0 } },
4485 { "stbue",   DEO(58,9), DE_MASK,        BOOKE64,        { RS, DE, RAS } },
4486 { "sthe",    DEO(58,10), DE_MASK,       BOOKE64,        { RS, DE, RA0 } },
4487 { "sthue",   DEO(58,11), DE_MASK,       BOOKE64,        { RS, DE, RAS } },
4488 { "stwe",    DEO(58,14), DE_MASK,       BOOKE64,        { RS, DE, RA0 } },
4489 { "stwue",   DEO(58,15), DE_MASK,       BOOKE64,        { RS, DE, RAS } },
4490
4491 { "ld",      DSO(58,0), DS_MASK,        PPC64,          { RT, DS, RA0 } },
4492
4493 { "ldu",     DSO(58,1), DS_MASK,        PPC64,          { RT, DS, RAL } },
4494
4495 { "lwa",     DSO(58,2), DS_MASK,        PPC64,          { RT, DS, RA0 } },
4496
4497 { "fdivs",   A(59,18,0), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
4498 { "fdivs.",  A(59,18,1), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
4499
4500 { "fsubs",   A(59,20,0), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
4501 { "fsubs.",  A(59,20,1), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
4502
4503 { "fadds",   A(59,21,0), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
4504 { "fadds.",  A(59,21,1), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
4505
4506 { "fsqrts",  A(59,22,0), AFRAFRC_MASK,  PPC,            { FRT, FRB } },
4507 { "fsqrts.", A(59,22,1), AFRAFRC_MASK,  PPC,            { FRT, FRB } },
4508
4509 { "fres",    A(59,24,0), AFRAFRC_MASK,  PPC,            { FRT, FRB } },
4510 { "fres.",   A(59,24,1), AFRAFRC_MASK,  PPC,            { FRT, FRB } },
4511
4512 { "fmuls",   A(59,25,0), AFRB_MASK,     PPC,            { FRT, FRA, FRC } },
4513 { "fmuls.",  A(59,25,1), AFRB_MASK,     PPC,            { FRT, FRA, FRC } },
4514
4515 { "fmsubs",  A(59,28,0), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
4516 { "fmsubs.", A(59,28,1), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
4517
4518 { "fmadds",  A(59,29,0), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
4519 { "fmadds.", A(59,29,1), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
4520
4521 { "fnmsubs", A(59,30,0), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
4522 { "fnmsubs.",A(59,30,1), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
4523
4524 { "fnmadds", A(59,31,0), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
4525 { "fnmadds.",A(59,31,1), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
4526
4527 { "stfq",    OP(60),    OP_MASK,        POWER2,         { FRS, D, RA } },
4528
4529 { "stfqu",   OP(61),    OP_MASK,        POWER2,         { FRS, D, RA } },
4530
4531 { "lde",     DEO(62,0), DE_MASK,        BOOKE64,        { RT, DES, RA0 } },
4532 { "ldue",    DEO(62,1), DE_MASK,        BOOKE64,        { RT, DES, RA0 } },
4533 { "lfse",    DEO(62,4), DE_MASK,        BOOKE64,        { FRT, DES, RA0 } },
4534 { "lfsue",   DEO(62,5), DE_MASK,        BOOKE64,        { FRT, DES, RAS } },
4535 { "lfde",    DEO(62,6), DE_MASK,        BOOKE64,        { FRT, DES, RA0 } },
4536 { "lfdue",   DEO(62,7), DE_MASK,        BOOKE64,        { FRT, DES, RAS } },
4537 { "stde",    DEO(62,8), DE_MASK,        BOOKE64,        { RS, DES, RA0 } },
4538 { "stdue",   DEO(62,9), DE_MASK,        BOOKE64,        { RS, DES, RAS } },
4539 { "stfse",   DEO(62,12), DE_MASK,       BOOKE64,        { FRS, DES, RA0 } },
4540 { "stfsue",  DEO(62,13), DE_MASK,       BOOKE64,        { FRS, DES, RAS } },
4541 { "stfde",   DEO(62,14), DE_MASK,       BOOKE64,        { FRS, DES, RA0 } },
4542 { "stfdue",  DEO(62,15), DE_MASK,       BOOKE64,        { FRS, DES, RAS } },
4543
4544 { "std",     DSO(62,0), DS_MASK,        PPC64,          { RS, DS, RA0 } },
4545
4546 { "stdu",    DSO(62,1), DS_MASK,        PPC64,          { RS, DS, RAS } },
4547
4548 { "stq",     DSO(62,2), DS_MASK,        POWER4,         { RSQ, DS, RA0 } },
4549
4550 { "fcmpu",   X(63,0),   X_MASK|(3<<21), COM,            { BF, FRA, FRB } },
4551
4552 { "frsp",    XRC(63,12,0), XRA_MASK,    COM,            { FRT, FRB } },
4553 { "frsp.",   XRC(63,12,1), XRA_MASK,    COM,            { FRT, FRB } },
4554
4555 { "fctiw",   XRC(63,14,0), XRA_MASK,    PPCCOM,         { FRT, FRB } },
4556 { "fcir",    XRC(63,14,0), XRA_MASK,    POWER2,         { FRT, FRB } },
4557 { "fctiw.",  XRC(63,14,1), XRA_MASK,    PPCCOM,         { FRT, FRB } },
4558 { "fcir.",   XRC(63,14,1), XRA_MASK,    POWER2,         { FRT, FRB } },
4559
4560 { "fctiwz",  XRC(63,15,0), XRA_MASK,    PPCCOM,         { FRT, FRB } },
4561 { "fcirz",   XRC(63,15,0), XRA_MASK,    POWER2,         { FRT, FRB } },
4562 { "fctiwz.", XRC(63,15,1), XRA_MASK,    PPCCOM,         { FRT, FRB } },
4563 { "fcirz.",  XRC(63,15,1), XRA_MASK,    POWER2,         { FRT, FRB } },
4564
4565 { "fdiv",    A(63,18,0), AFRC_MASK,     PPCCOM,         { FRT, FRA, FRB } },
4566 { "fd",      A(63,18,0), AFRC_MASK,     PWRCOM,         { FRT, FRA, FRB } },
4567 { "fdiv.",   A(63,18,1), AFRC_MASK,     PPCCOM,         { FRT, FRA, FRB } },
4568 { "fd.",     A(63,18,1), AFRC_MASK,     PWRCOM,         { FRT, FRA, FRB } },
4569
4570 { "fsub",    A(63,20,0), AFRC_MASK,     PPCCOM,         { FRT, FRA, FRB } },
4571 { "fs",      A(63,20,0), AFRC_MASK,     PWRCOM,         { FRT, FRA, FRB } },
4572 { "fsub.",   A(63,20,1), AFRC_MASK,     PPCCOM,         { FRT, FRA, FRB } },
4573 { "fs.",     A(63,20,1), AFRC_MASK,     PWRCOM,         { FRT, FRA, FRB } },
4574
4575 { "fadd",    A(63,21,0), AFRC_MASK,     PPCCOM,         { FRT, FRA, FRB } },
4576 { "fa",      A(63,21,0), AFRC_MASK,     PWRCOM,         { FRT, FRA, FRB } },
4577 { "fadd.",   A(63,21,1), AFRC_MASK,     PPCCOM,         { FRT, FRA, FRB } },
4578 { "fa.",     A(63,21,1), AFRC_MASK,     PWRCOM,         { FRT, FRA, FRB } },
4579
4580 { "fsqrt",   A(63,22,0), AFRAFRC_MASK,  PPCPWR2,        { FRT, FRB } },
4581 { "fsqrt.",  A(63,22,1), AFRAFRC_MASK,  PPCPWR2,        { FRT, FRB } },
4582
4583 { "fsel",    A(63,23,0), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
4584 { "fsel.",   A(63,23,1), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
4585
4586 { "fmul",    A(63,25,0), AFRB_MASK,     PPCCOM,         { FRT, FRA, FRC } },
4587 { "fm",      A(63,25,0), AFRB_MASK,     PWRCOM,         { FRT, FRA, FRC } },
4588 { "fmul.",   A(63,25,1), AFRB_MASK,     PPCCOM,         { FRT, FRA, FRC } },
4589 { "fm.",     A(63,25,1), AFRB_MASK,     PWRCOM,         { FRT, FRA, FRC } },
4590
4591 { "frsqrte", A(63,26,0), AFRAFRC_MASK,  PPC,            { FRT, FRB } },
4592 { "frsqrte.",A(63,26,1), AFRAFRC_MASK,  PPC,            { FRT, FRB } },
4593
4594 { "fmsub",   A(63,28,0), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
4595 { "fms",     A(63,28,0), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
4596 { "fmsub.",  A(63,28,1), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
4597 { "fms.",    A(63,28,1), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
4598
4599 { "fmadd",   A(63,29,0), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
4600 { "fma",     A(63,29,0), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
4601 { "fmadd.",  A(63,29,1), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
4602 { "fma.",    A(63,29,1), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
4603
4604 { "fnmsub",  A(63,30,0), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
4605 { "fnms",    A(63,30,0), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
4606 { "fnmsub.", A(63,30,1), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
4607 { "fnms.",   A(63,30,1), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
4608
4609 { "fnmadd",  A(63,31,0), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
4610 { "fnma",    A(63,31,0), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
4611 { "fnmadd.", A(63,31,1), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
4612 { "fnma.",   A(63,31,1), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
4613
4614 { "fcmpo",   X(63,32),  X_MASK|(3<<21), COM,            { BF, FRA, FRB } },
4615
4616 { "mtfsb1",  XRC(63,38,0), XRARB_MASK,  COM,            { BT } },
4617 { "mtfsb1.", XRC(63,38,1), XRARB_MASK,  COM,            { BT } },
4618
4619 { "fneg",    XRC(63,40,0), XRA_MASK,    COM,            { FRT, FRB } },
4620 { "fneg.",   XRC(63,40,1), XRA_MASK,    COM,            { FRT, FRB } },
4621
4622 { "mcrfs",   X(63,64),  XRB_MASK|(3<<21)|(3<<16), COM,  { BF, BFA } },
4623
4624 { "mtfsb0",  XRC(63,70,0), XRARB_MASK,  COM,            { BT } },
4625 { "mtfsb0.", XRC(63,70,1), XRARB_MASK,  COM,            { BT } },
4626
4627 { "fmr",     XRC(63,72,0), XRA_MASK,    COM,            { FRT, FRB } },
4628 { "fmr.",    XRC(63,72,1), XRA_MASK,    COM,            { FRT, FRB } },
4629
4630 { "mtfsfi",  XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } },
4631 { "mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } },
4632
4633 { "fnabs",   XRC(63,136,0), XRA_MASK,   COM,            { FRT, FRB } },
4634 { "fnabs.",  XRC(63,136,1), XRA_MASK,   COM,            { FRT, FRB } },
4635
4636 { "fabs",    XRC(63,264,0), XRA_MASK,   COM,            { FRT, FRB } },
4637 { "fabs.",   XRC(63,264,1), XRA_MASK,   COM,            { FRT, FRB } },
4638
4639 { "mffs",    XRC(63,583,0), XRARB_MASK, COM,            { FRT } },
4640 { "mffs.",   XRC(63,583,1), XRARB_MASK, COM,            { FRT } },
4641
4642 { "mtfsf",   XFL(63,711,0), XFL_MASK,   COM,            { FLM, FRB } },
4643 { "mtfsf.",  XFL(63,711,1), XFL_MASK,   COM,            { FLM, FRB } },
4644
4645 { "fctid",   XRC(63,814,0), XRA_MASK,   PPC64,          { FRT, FRB } },
4646 { "fctid.",  XRC(63,814,1), XRA_MASK,   PPC64,          { FRT, FRB } },
4647
4648 { "fctidz",  XRC(63,815,0), XRA_MASK,   PPC64,          { FRT, FRB } },
4649 { "fctidz.", XRC(63,815,1), XRA_MASK,   PPC64,          { FRT, FRB } },
4650
4651 { "fcfid",   XRC(63,846,0), XRA_MASK,   PPC64,          { FRT, FRB } },
4652 { "fcfid.",  XRC(63,846,1), XRA_MASK,   PPC64,          { FRT, FRB } },
4653
4654 };
4655
4656 const int powerpc_num_opcodes =
4657   sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]);
4658 \f
4659 /* The macro table.  This is only used by the assembler.  */
4660
4661 /* The expressions of the form (-x ! 31) & (x | 31) have the value 0
4662    when x=0; 32-x when x is between 1 and 31; are negative if x is
4663    negative; and are 32 or more otherwise.  This is what you want
4664    when, for instance, you are emulating a right shift by a
4665    rotate-left-and-mask, because the underlying instructions support
4666    shifts of size 0 but not shifts of size 32.  By comparison, when
4667    extracting x bits from some word you want to use just 32-x, because
4668    the underlying instructions don't support extracting 0 bits but do
4669    support extracting the whole word (32 bits in this case).  */
4670
4671 const struct powerpc_macro powerpc_macros[] = {
4672 { "extldi",  4,   PPC64,        "rldicr %0,%1,%3,(%2)-1" },
4673 { "extldi.", 4,   PPC64,        "rldicr. %0,%1,%3,(%2)-1" },
4674 { "extrdi",  4,   PPC64,        "rldicl %0,%1,(%2)+(%3),64-(%2)" },
4675 { "extrdi.", 4,   PPC64,        "rldicl. %0,%1,(%2)+(%3),64-(%2)" },
4676 { "insrdi",  4,   PPC64,        "rldimi %0,%1,64-((%2)+(%3)),%3" },
4677 { "insrdi.", 4,   PPC64,        "rldimi. %0,%1,64-((%2)+(%3)),%3" },
4678 { "rotrdi",  3,   PPC64,        "rldicl %0,%1,(-(%2)!63)&((%2)|63),0" },
4679 { "rotrdi.", 3,   PPC64,        "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0" },
4680 { "sldi",    3,   PPC64,        "rldicr %0,%1,%2,63-(%2)" },
4681 { "sldi.",   3,   PPC64,        "rldicr. %0,%1,%2,63-(%2)" },
4682 { "srdi",    3,   PPC64,        "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2" },
4683 { "srdi.",   3,   PPC64,        "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2" },
4684 { "clrrdi",  3,   PPC64,        "rldicr %0,%1,0,63-(%2)" },
4685 { "clrrdi.", 3,   PPC64,        "rldicr. %0,%1,0,63-(%2)" },
4686 { "clrlsldi",4,   PPC64,        "rldic %0,%1,%3,(%2)-(%3)" },
4687 { "clrlsldi.",4,  PPC64,        "rldic. %0,%1,%3,(%2)-(%3)" },
4688
4689 { "extlwi",  4,   PPCCOM,       "rlwinm %0,%1,%3,0,(%2)-1" },
4690 { "extlwi.", 4,   PPCCOM,       "rlwinm. %0,%1,%3,0,(%2)-1" },
4691 { "extrwi",  4,   PPCCOM,       "rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31" },
4692 { "extrwi.", 4,   PPCCOM,       "rlwinm. %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31" },
4693 { "inslwi",  4,   PPCCOM,       "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1" },
4694 { "inslwi.", 4,   PPCCOM,       "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
4695 { "insrwi",  4,   PPCCOM,       "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1" },
4696 { "insrwi.", 4,   PPCCOM,       "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
4697 { "rotrwi",  3,   PPCCOM,       "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31" },
4698 { "rotrwi.", 3,   PPCCOM,       "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31" },
4699 { "slwi",    3,   PPCCOM,       "rlwinm %0,%1,%2,0,31-(%2)" },
4700 { "sli",     3,   PWRCOM,       "rlinm %0,%1,%2,0,31-(%2)" },
4701 { "slwi.",   3,   PPCCOM,       "rlwinm. %0,%1,%2,0,31-(%2)" },
4702 { "sli.",    3,   PWRCOM,       "rlinm. %0,%1,%2,0,31-(%2)" },
4703 { "srwi",    3,   PPCCOM,       "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4704 { "sri",     3,   PWRCOM,       "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4705 { "srwi.",   3,   PPCCOM,       "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4706 { "sri.",    3,   PWRCOM,       "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4707 { "clrrwi",  3,   PPCCOM,       "rlwinm %0,%1,0,0,31-(%2)" },
4708 { "clrrwi.", 3,   PPCCOM,       "rlwinm. %0,%1,0,0,31-(%2)" },
4709 { "clrlslwi",4,   PPCCOM,       "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)" },
4710 { "clrlslwi.",4,  PPCCOM,       "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)" },
4711 };
4712
4713 const int powerpc_num_macros =
4714   sizeof (powerpc_macros) / sizeof (powerpc_macros[0]);