opcodes/ia64-opc.h

   1 /* ia64-opc.h -- IA-64 opcode table.
   2    Copyright 1998, 1999, 2000, 2002 Free Software Foundation, Inc.
   3    Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
   4
   5    This file is part of GDB, GAS, and the GNU binutils.
   6
   7    GDB, GAS, and the GNU binutils are free software; you can redistribute
   8    them and/or modify them under the terms of the GNU General Public
   9    License as published by the Free Software Foundation; either version
  10    2, or (at your option) any later version.
  11
  12    GDB, GAS, and the GNU binutils are distributed in the hope that they
  13    will be useful, but WITHOUT ANY WARRANTY; without even the implied
  14    warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
  15    the GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this file; see the file COPYING.  If not, write to the
  19    Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA
  20    02111-1307, USA.  */
  21
  22 #ifndef IA64_OPC_H
  23 #define IA64_OPC_H
  24
  25 #include "opcode/ia64.h"
  26
  27 /* define a couple of abbreviations: */
  28
  29 #define bOp(x)  (((ia64_insn) ((x) & 0xf)) << 37)
  30 #define mOp     bOp (-1)
  31 #define Op(x)   bOp (x), mOp
  32
  33 #define FIRST           IA64_OPCODE_FIRST
  34 #define X_IN_MLX        IA64_OPCODE_X_IN_MLX
  35 #define LAST            IA64_OPCODE_LAST
  36 #define PRIV            IA64_OPCODE_PRIV
  37 #define NO_PRED         IA64_OPCODE_NO_PRED
  38 #define SLOT2           IA64_OPCODE_SLOT2
  39 #define PSEUDO          IA64_OPCODE_PSEUDO
  40 #define F2_EQ_F3        IA64_OPCODE_F2_EQ_F3
  41 #define LEN_EQ_64MCNT   IA64_OPCODE_LEN_EQ_64MCNT
  42 #define MOD_RRBS        IA64_OPCODE_MOD_RRBS
  43 #define POSTINC         IA64_OPCODE_POSTINC
  44
  45 #define AR_CCV  IA64_OPND_AR_CCV
  46 #define AR_PFS  IA64_OPND_AR_PFS
  47 #define AR_CSD  IA64_OPND_AR_CSD
  48 #define C1      IA64_OPND_C1
  49 #define C8      IA64_OPND_C8
  50 #define C16     IA64_OPND_C16
  51 #define GR0     IA64_OPND_GR0
  52 #define IP      IA64_OPND_IP
  53 #define PR      IA64_OPND_PR
  54 #define PR_ROT  IA64_OPND_PR_ROT
  55 #define PSR     IA64_OPND_PSR
  56 #define PSR_L   IA64_OPND_PSR_L
  57 #define PSR_UM  IA64_OPND_PSR_UM
  58
  59 #define AR3     IA64_OPND_AR3
  60 #define B1      IA64_OPND_B1
  61 #define B2      IA64_OPND_B2
  62 #define CR3     IA64_OPND_CR3
  63 #define F1      IA64_OPND_F1
  64 #define F2      IA64_OPND_F2
  65 #define F3      IA64_OPND_F3
  66 #define F4      IA64_OPND_F4
  67 #define P1      IA64_OPND_P1
  68 #define P2      IA64_OPND_P2
  69 #define R1      IA64_OPND_R1
  70 #define R2      IA64_OPND_R2
  71 #define R3      IA64_OPND_R3
  72 #define R3_2    IA64_OPND_R3_2
  73
  74 #define CPUID_R3 IA64_OPND_CPUID_R3
  75 #define DBR_R3  IA64_OPND_DBR_R3
  76 #define DTR_R3  IA64_OPND_DTR_R3
  77 #define ITR_R3  IA64_OPND_ITR_R3
  78 #define IBR_R3  IA64_OPND_IBR_R3
  79 #define MR3     IA64_OPND_MR3
  80 #define MSR_R3  IA64_OPND_MSR_R3
  81 #define PKR_R3  IA64_OPND_PKR_R3
  82 #define PMC_R3  IA64_OPND_PMC_R3
  83 #define PMD_R3  IA64_OPND_PMD_R3
  84 #define RR_R3   IA64_OPND_RR_R3
  85
  86 #define CCNT5   IA64_OPND_CCNT5
  87 #define CNT2a   IA64_OPND_CNT2a
  88 #define CNT2b   IA64_OPND_CNT2b
  89 #define CNT2c   IA64_OPND_CNT2c
  90 #define CNT5    IA64_OPND_CNT5
  91 #define CNT6    IA64_OPND_CNT6
  92 #define CPOS6a  IA64_OPND_CPOS6a
  93 #define CPOS6b  IA64_OPND_CPOS6b
  94 #define CPOS6c  IA64_OPND_CPOS6c
  95 #define IMM1    IA64_OPND_IMM1
  96 #define IMM14   IA64_OPND_IMM14
  97 #define IMM17   IA64_OPND_IMM17
  98 #define IMM22   IA64_OPND_IMM22
  99 #define IMM44   IA64_OPND_IMM44
 100 #define SOF     IA64_OPND_SOF
 101 #define SOL     IA64_OPND_SOL
 102 #define SOR     IA64_OPND_SOR
 103 #define IMM8    IA64_OPND_IMM8
 104 #define IMM8U4  IA64_OPND_IMM8U4
 105 #define IMM8M1  IA64_OPND_IMM8M1
 106 #define IMM8M1U4 IA64_OPND_IMM8M1U4
 107 #define IMM8M1U8 IA64_OPND_IMM8M1U8
 108 #define IMM9a   IA64_OPND_IMM9a
 109 #define IMM9b   IA64_OPND_IMM9b
 110 #define IMMU2   IA64_OPND_IMMU2
 111 #define IMMU21  IA64_OPND_IMMU21
 112 #define IMMU24  IA64_OPND_IMMU24
 113 #define IMMU62  IA64_OPND_IMMU62
 114 #define IMMU64  IA64_OPND_IMMU64
 115 #define IMMU7a  IA64_OPND_IMMU7a
 116 #define IMMU7b  IA64_OPND_IMMU7b
 117 #define IMMU9   IA64_OPND_IMMU9
 118 #define INC3    IA64_OPND_INC3
 119 #define LEN4    IA64_OPND_LEN4
 120 #define LEN6    IA64_OPND_LEN6
 121 #define MBTYPE4 IA64_OPND_MBTYPE4
 122 #define MHTYPE8 IA64_OPND_MHTYPE8
 123 #define POS6    IA64_OPND_POS6
 124 #define TAG13   IA64_OPND_TAG13
 125 #define TAG13b  IA64_OPND_TAG13b
 126 #define TGT25   IA64_OPND_TGT25
 127 #define TGT25b  IA64_OPND_TGT25b
 128 #define TGT25c  IA64_OPND_TGT25c
 129 #define TGT64   IA64_OPND_TGT64
 130
 131 #endif