opcodes/crx-opc.c

   1 /* crx-opc.c -- Table of opcodes for the CRX processor.
   2    Copyright 2004 Free Software Foundation, Inc.
   3    Contributed by Tomer Levi NSC, Israel.
   4    Originally written for GAS 2.12 by Tomer Levi.
   5
   6    This file is part of GAS, GDB and the GNU binutils.
   7
   8    GAS, GDB, and GNU binutils is free software; you can redistribute it
   9    and/or modify it under the terms of the GNU General Public License as
  10    published by the Free Software Foundation; either version 2, or (at your
  11    option) any later version.
  12
  13    GAS, GDB, and GNU binutils are distributed in the hope that they will be
  14    useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; if not, write to the Free Software
  20    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  21
  22 #include <stdio.h>
  23 #include "libiberty.h"
  24 #include "symcat.h"
  25 #include "opcode/crx.h"
  26
  27 const inst crx_instruction[] =
  28 {
  29 /* Create an arithmetic instruction - INST[bw].  */
  30 #define  ARITH_BYTE_INST(NAME, OPC) \
  31   /* opc8 cst4 r */                                                             \
  32   {NAME, 1, OPC,  24, ARITH_BYTE_INS | CST4MAP, {{cst4,20}, {regr,16}}},        \
  33   /* opc8 i16 r */                                                              \
  34   {NAME, 2, (OPC<<4)+0xE, 20, ARITH_BYTE_INS | CST4MAP, {{i16,0}, {regr,16}}},  \
  35   /* opc8 r r */                                                                \
  36   {NAME, 1, OPC+0x40, 24, ARITH_BYTE_INS, {{regr,20}, {regr,16}}}
  37
  38   ARITH_BYTE_INST ("addub", 0x0),
  39   ARITH_BYTE_INST ("addb",  0x1),
  40   ARITH_BYTE_INST ("addcb", 0x2),
  41   ARITH_BYTE_INST ("andb",  0x3),
  42   ARITH_BYTE_INST ("cmpb",  0x4),
  43   ARITH_BYTE_INST ("movb",  0x5),
  44   ARITH_BYTE_INST ("orb",   0x6),
  45   ARITH_BYTE_INST ("subb",  0x7),
  46   ARITH_BYTE_INST ("subcb", 0x8),
  47   ARITH_BYTE_INST ("xorb",  0x9),
  48   ARITH_BYTE_INST ("mulb",  0xA),
  49
  50   ARITH_BYTE_INST ("adduw", 0x10),
  51   ARITH_BYTE_INST ("addw",  0x11),
  52   ARITH_BYTE_INST ("addcw", 0x12),
  53   ARITH_BYTE_INST ("andw",  0x13),
  54   ARITH_BYTE_INST ("cmpw",  0x14),
  55   ARITH_BYTE_INST ("movw",  0x15),
  56   ARITH_BYTE_INST ("orw",   0x16),
  57   ARITH_BYTE_INST ("subw",  0x17),
  58   ARITH_BYTE_INST ("subcw", 0x18),
  59   ARITH_BYTE_INST ("xorw",  0x19),
  60   ARITH_BYTE_INST ("mulw",  0x1A),
  61
  62 /* Create an arithmetic instruction - INST[d].  */
  63 #define  ARITH_INST(NAME, OPC) \
  64   /* opc8 cst4 r */                                                         \
  65   {NAME, 1, OPC,  24, ARITH_INS | CST4MAP, {{cst4,20}, {regr,16}}},         \
  66   /* opc8 i16 r */                                                          \
  67   {NAME, 2, (OPC<<4)+0xE, 20, ARITH_INS | CST4MAP, {{i16,0},  {regr,16}}},  \
  68   /* opc8 i32 r */                                                          \
  69   {NAME, 3, (OPC<<4)+0xF, 20, ARITH_INS, {{i32,0},  {regr,16}}},            \
  70   /* opc8 r r */                                                            \
  71   {NAME, 1, OPC+0x40, 24, ARITH_INS, {{regr,20}, {regr,16}}}
  72
  73   ARITH_INST ("addud", 0x20),
  74   ARITH_INST ("addd",  0x21),
  75   ARITH_INST ("addcd", 0x22),
  76   ARITH_INST ("andd",  0x23),
  77   ARITH_INST ("cmpd",  0x24),
  78   ARITH_INST ("movd",  0x25),
  79   ARITH_INST ("ord",   0x26),
  80   ARITH_INST ("subd",  0x27),
  81   ARITH_INST ("subcd", 0x28),
  82   ARITH_INST ("xord",  0x29),
  83   ARITH_INST ("muld",  0x2A),
  84
  85 /* Create a shift instruction.  */
  86 #define  SHIFT_INST(NAME, OPRD, OPC1, SHIFT1, OPC2) \
  87   /* OPRD=ui3 -->> opc9 ui3 r */                              \
  88   /* OPRD=ui4 -->> opc8 ui4 r */                              \
  89   /* OPRD=ui5 -->> opc7 ui5 r */                              \
  90   {NAME, 1, OPC1, SHIFT1, SHIFT_INS, {{OPRD,20}, {regr,16}}}, \
  91   /* opc8 r r */                                              \
  92   {NAME, 1, OPC2, 24, SHIFT_INS, {{regr,20}, {regr,16}}}
  93
  94   SHIFT_INST ("sllb", ui3, 0x1F8, 23, 0x4D),
  95   SHIFT_INST ("srlb", ui3, 0x1F9, 23, 0x4E),
  96   SHIFT_INST ("srab", ui3, 0x1FA, 23, 0x4F),
  97
  98   SHIFT_INST ("sllw", ui4, 0xB6,  24, 0x5D),
  99   SHIFT_INST ("srlw", ui4, 0xB7,  24, 0x5E),
 100   SHIFT_INST ("sraw", ui4, 0xB8,  24, 0x5F),
 101
 102   SHIFT_INST ("slld", ui5, 0x78,  25, 0x6D),
 103   SHIFT_INST ("srld", ui5, 0x79,  25, 0x6E),
 104   SHIFT_INST ("srad", ui5, 0x7A,  25, 0x6F),
 105
 106 /* Create a conditional branch instruction.  */
 107 #define  BRANCH_INST(NAME, OPC) \
 108   /* opc4 c4 dispe9 */                                                  \
 109   {NAME,  1, OPC, 24, BRANCH_INS | RELAXABLE, {{dispe9,16}}},           \
 110   /* opc4 c4 disps17 */                                                 \
 111   {NAME,  2, (OPC<<8)+0x7E, 16, BRANCH_INS | RELAXABLE, {{disps17,0}}}, \
 112   /* opc4 c4 disps32 */                                                 \
 113   {NAME,  3, (OPC<<8)+0x7F, 16, BRANCH_INS | RELAXABLE, {{disps32,0}}}
 114
 115   BRANCH_INST ("beq", 0x70),
 116   BRANCH_INST ("bne", 0x71),
 117   BRANCH_INST ("bcs", 0x72),
 118   BRANCH_INST ("bcc", 0x73),
 119   BRANCH_INST ("bhi", 0x74),
 120   BRANCH_INST ("bls", 0x75),
 121   BRANCH_INST ("bgt", 0x76),
 122   BRANCH_INST ("ble", 0x77),
 123   BRANCH_INST ("bfs", 0x78),
 124   BRANCH_INST ("bfc", 0x79),
 125   BRANCH_INST ("blo", 0x7A),
 126   BRANCH_INST ("bhs", 0x7B),
 127   BRANCH_INST ("blt", 0x7C),
 128   BRANCH_INST ("bge", 0x7D),
 129   BRANCH_INST ("br",  0x7E),
 130
 131 /* Create a 'Branch if Equal to 0' instruction.  */
 132 #define  BRANCH_NEQ_INST(NAME, OPC) \
 133   /* opc8 dispu5 r */                                           \
 134   {NAME,  1, OPC, 24, BRANCH_NEQ_INS, {{regr,16}, {dispu5,20}}}
 135
 136   BRANCH_NEQ_INST ("beq0b",  0xB0),
 137   BRANCH_NEQ_INST ("bne0b",  0xB1),
 138   BRANCH_NEQ_INST ("beq0w",  0xB2),
 139   BRANCH_NEQ_INST ("bne0w",  0xB3),
 140   BRANCH_NEQ_INST ("beq0d",  0xB4),
 141   BRANCH_NEQ_INST ("bne0d",  0xB5),
 142
 143 /* Create instruction with no operands.  */
 144 #define  NO_OP_INST(NAME, OPC) \
 145   /* opc16 */                       \
 146   {NAME,  1, OPC, 16, 0, {{0, 0}}}
 147
 148   NO_OP_INST ("nop",    0x3002),
 149   NO_OP_INST ("retx",   0x3003),
 150   NO_OP_INST ("di",     0x3004),
 151   NO_OP_INST ("ei",     0x3005),
 152   NO_OP_INST ("wait",   0x3006),
 153   NO_OP_INST ("eiwait", 0x3007),
 154
 155 /* Create a 'Compare & Branch' instruction.  */
 156 #define  CMPBR_INST(NAME, OPC1, OPC2, C4) \
 157   /* opc12 r r c4 disps9 */                                           \
 158   {NAME, 2, ((0x300+OPC1)<<12)+C4,  8, CMPBR_INS | FMT_3| RELAXABLE,  \
 159       {{regr,16}, {regr,12}, {disps9,0}}},                            \
 160   /* opc12 r r c4 disps25 */                                          \
 161   {NAME, 3, ((0x310+OPC1)<<12)+C4,  8, CMPBR_INS | FMT_3 | RELAXABLE, \
 162       {{regr,16}, {regr,12}, {disps25,0}}},                           \
 163   /* opc12 i4cst4 r c4 disps9 */                                      \
 164   {NAME, 2, ((0x300+OPC2)<<12)+C4,  8, CMPBR_INS | FMT_3 | RELAXABLE, \
 165       {{cst4,16}, {regr,12}, {disps9,0}}},                            \
 166   /* opc12 i4cst4 r c4 disps25 */                                     \
 167   {NAME, 3, ((0x310+OPC2)<<12)+C4,  8, CMPBR_INS | FMT_3 | RELAXABLE, \
 168       {{cst4,16}, {regr,12}, {disps25,0}}}
 169
 170   CMPBR_INST ("cmpbeqb", 0x8, 0xC, 0x0),
 171   CMPBR_INST ("cmpbneb", 0x8, 0xC, 0x1),
 172   CMPBR_INST ("cmpbhib", 0x8, 0xC, 0x4),
 173   CMPBR_INST ("cmpblsb", 0x8, 0xC, 0x5),
 174   CMPBR_INST ("cmpbgtb", 0x8, 0xC, 0x6),
 175   CMPBR_INST ("cmpbleb", 0x8, 0xC, 0x7),
 176   CMPBR_INST ("cmpblob", 0x8, 0xC, 0xA),
 177   CMPBR_INST ("cmpbhsb", 0x8, 0xC, 0xB),
 178   CMPBR_INST ("cmpbltb", 0x8, 0xC, 0xC),
 179   CMPBR_INST ("cmpbgeb", 0x8, 0xC, 0xD),
 180
 181   CMPBR_INST ("cmpbeqw", 0x9, 0xD, 0x0),
 182   CMPBR_INST ("cmpbnew", 0x9, 0xD, 0x1),
 183   CMPBR_INST ("cmpbhiw", 0x9, 0xD, 0x4),
 184   CMPBR_INST ("cmpblsw", 0x9, 0xD, 0x5),
 185   CMPBR_INST ("cmpbgtw", 0x9, 0xD, 0x6),
 186   CMPBR_INST ("cmpblew", 0x9, 0xD, 0x7),
 187   CMPBR_INST ("cmpblow", 0x9, 0xD, 0xA),
 188   CMPBR_INST ("cmpbhsw", 0x9, 0xD, 0xB),
 189   CMPBR_INST ("cmpbltw", 0x9, 0xD, 0xC),
 190   CMPBR_INST ("cmpbgew", 0x9, 0xD, 0xD),
 191
 192   CMPBR_INST ("cmpbeqd", 0xA, 0xE, 0x0),
 193   CMPBR_INST ("cmpbned", 0xA, 0xE, 0x1),
 194   CMPBR_INST ("cmpbhid", 0xA, 0xE, 0x4),
 195   CMPBR_INST ("cmpblsd", 0xA, 0xE, 0x5),
 196   CMPBR_INST ("cmpbgtd", 0xA, 0xE, 0x6),
 197   CMPBR_INST ("cmpbled", 0xA, 0xE, 0x7),
 198   CMPBR_INST ("cmpblod", 0xA, 0xE, 0xA),
 199   CMPBR_INST ("cmpbhsd", 0xA, 0xE, 0xB),
 200   CMPBR_INST ("cmpbltd", 0xA, 0xE, 0xC),
 201   CMPBR_INST ("cmpbged", 0xA, 0xE, 0xD),
 202
 203 /* Create an instruction using a single register operand.  */
 204 #define  REG1_INST(NAME, OPC) \
 205   /* opc8 c4 r */                               \
 206   {NAME,  1, OPC, 20, NO_TYPE_INS, {{regr,16}}}
 207
 208 /* Same as REG1_INST, with additional FLAGS.  */
 209 #define  REG1_FLAG_INST(NAME, OPC, FLAGS) \
 210   /* opc8 c4 r */                                       \
 211   {NAME,  1, OPC, 20, NO_TYPE_INS | FLAGS, {{regr,16}}}
 212
 213   /* JCond instructions */
 214   REG1_INST ("jeq",  0xBA0),
 215   REG1_INST ("jne",  0xBA1),
 216   REG1_INST ("jcs",  0xBA2),
 217   REG1_INST ("jcc",  0xBA3),
 218   REG1_INST ("jhi",  0xBA4),
 219   REG1_INST ("jls",  0xBA5),
 220   REG1_INST ("jgt",  0xBA6),
 221   REG1_INST ("jle",  0xBA7),
 222   REG1_INST ("jfs",  0xBA8),
 223   REG1_INST ("jfc",  0xBA9),
 224   REG1_INST ("jlo",  0xBAA),
 225   REG1_INST ("jhs",  0xBAB),
 226   REG1_INST ("jlt",  0xBAC),
 227   REG1_INST ("jge",  0xBAD),
 228   REG1_INST ("jump", 0xBAE),
 229
 230   /* SCond instructions */
 231   REG1_INST ("seq",  0xBB0),
 232   REG1_INST ("sne",  0xBB1),
 233   REG1_INST ("scs",  0xBB2),
 234   REG1_INST ("scc",  0xBB3),
 235   REG1_INST ("shi",  0xBB4),
 236   REG1_INST ("sls",  0xBB5),
 237   REG1_INST ("sgt",  0xBB6),
 238   REG1_INST ("sle",  0xBB7),
 239   REG1_INST ("sfs",  0xBB8),
 240   REG1_INST ("sfc",  0xBB9),
 241   REG1_INST ("slo",  0xBBA),
 242   REG1_INST ("shs",  0xBBB),
 243   REG1_INST ("slt",  0xBBC),
 244   REG1_INST ("sge",  0xBBD),
 245
 246 /* Create an instruction using two register operands.  */
 247 #define  REG2_INST(NAME, OPC) \
 248   /* opc24 r r  OR  opc20 c4 r r */                     \
 249   {NAME,  2, 0x300800+OPC,  8, NO_TYPE_INS, {{regr,4}, {regr,0}}}
 250
 251   /* MULTIPLY INSTRUCTIONS */
 252   REG2_INST ("macsb",  0x40),
 253   REG2_INST ("macub",  0x41),
 254   REG2_INST ("macqb",  0x42),
 255
 256   REG2_INST ("macsw",  0x50),
 257   REG2_INST ("macuw",  0x51),
 258   REG2_INST ("macqw",  0x52),
 259
 260   REG2_INST ("macsd",  0x60),
 261   REG2_INST ("macud",  0x61),
 262   REG2_INST ("macqd",  0x62),
 263
 264   REG2_INST ("mullsd", 0x65),
 265   REG2_INST ("mullud", 0x66),
 266
 267   REG2_INST ("mulsbw", 0x3B),
 268   REG2_INST ("mulubw", 0x3C),
 269   REG2_INST ("mulswd", 0x3D),
 270   REG2_INST ("muluwd", 0x3E),
 271
 272   /*  SIGNEXTEND STUFF    */
 273   REG2_INST ("sextbw", 0x30),
 274   REG2_INST ("sextbd", 0x31),
 275   REG2_INST ("sextwd", 0x32),
 276   REG2_INST ("zextbw", 0x34),
 277   REG2_INST ("zextbd", 0x35),
 278   REG2_INST ("zextwd", 0x36),
 279
 280   REG2_INST ("bswap",  0x3F),
 281
 282   REG2_INST ("maxsb",  0x80),
 283   REG2_INST ("minsb",  0x81),
 284   REG2_INST ("maxub",  0x82),
 285   REG2_INST ("minub",  0x83),
 286   REG2_INST ("absb",   0x84),
 287   REG2_INST ("negb",   0x85),
 288   REG2_INST ("cntl0b", 0x86),
 289   REG2_INST ("cntl1b", 0x87),
 290   REG2_INST ("popcntb",0x88),
 291   REG2_INST ("rotlb",  0x89),
 292   REG2_INST ("rotrb",  0x8A),
 293   REG2_INST ("mulqb",  0x8B),
 294   REG2_INST ("addqb",  0x8C),
 295   REG2_INST ("subqb",  0x8D),
 296   REG2_INST ("cntlsb", 0x8E),
 297
 298   REG2_INST ("maxsw",  0x90),
 299   REG2_INST ("minsw",  0x91),
 300   REG2_INST ("maxuw",  0x92),
 301   REG2_INST ("minuw",  0x93),
 302   REG2_INST ("absw",   0x94),
 303   REG2_INST ("negw",   0x95),
 304   REG2_INST ("cntl0w", 0x96),
 305   REG2_INST ("cntl1w", 0x97),
 306   REG2_INST ("popcntw",0x98),
 307   REG2_INST ("rotlw",  0x99),
 308   REG2_INST ("rotrw",  0x9A),
 309   REG2_INST ("mulqw",  0x9B),
 310   REG2_INST ("addqw",  0x9C),
 311   REG2_INST ("subqw",  0x9D),
 312   REG2_INST ("cntlsw", 0x9E),
 313
 314   REG2_INST ("maxsd",  0xA0),
 315   REG2_INST ("minsd",  0xA1),
 316   REG2_INST ("maxud",  0xA2),
 317   REG2_INST ("minud",  0xA3),
 318   REG2_INST ("absd",   0xA4),
 319   REG2_INST ("negd",   0xA5),
 320   REG2_INST ("cntl0d", 0xA6),
 321   REG2_INST ("cntl1d", 0xA7),
 322   REG2_INST ("popcntd",0xA8),
 323   REG2_INST ("rotld",  0xA9),
 324   REG2_INST ("rotrd",  0xAA),
 325   REG2_INST ("mulqd",  0xAB),
 326   REG2_INST ("addqd",  0xAC),
 327   REG2_INST ("subqd",  0xAD),
 328   REG2_INST ("cntlsd", 0xAE),
 329
 330 /* Conditional move instructions */
 331   REG2_INST ("cmoveqd", 0x70),
 332   REG2_INST ("cmovned", 0x71),
 333   REG2_INST ("cmovcsd", 0x72),
 334   REG2_INST ("cmovccd", 0x73),
 335   REG2_INST ("cmovhid", 0x74),
 336   REG2_INST ("cmovlsd", 0x75),
 337   REG2_INST ("cmovgtd", 0x76),
 338   REG2_INST ("cmovled", 0x77),
 339   REG2_INST ("cmovfsd", 0x78),
 340   REG2_INST ("cmovfcd", 0x79),
 341   REG2_INST ("cmovlod", 0x7A),
 342   REG2_INST ("cmovhsd", 0x7B),
 343   REG2_INST ("cmovltd", 0x7C),
 344   REG2_INST ("cmovged", 0x7D),
 345
 346 /* Load instructions (from memory to register).  */
 347 #define  LD_REG_INST(NAME, OPC1, OPC2, DISP) \
 348   /* opc12 r abs16 */                                                       \
 349   {NAME,  2, 0x320+OPC1,  20, LD_STOR_INS | REVERSE_MATCH,                  \
 350       {{abs16,0}, {regr,16}}},                                              \
 351   /* opc12 r abs32 */                                                       \
 352   {NAME,  3, 0x330+OPC1,  20, LD_STOR_INS | REVERSE_MATCH,                  \
 353       {{abs32,0}, {regr,16}}},                                              \
 354   /* opc4 r rbase dispu[bwd]4 */                                            \
 355   {NAME,  1, 0x8+OPC2,  28, LD_STOR_INS | DISP | REVERSE_MATCH,             \
 356       {{rbase_dispu4,16}, {regr,24}}},                                      \
 357   /* opc4 r rbase disps16 */                                                \
 358   {NAME,  2, ((0x8+OPC2)<<8)+0xE, 20, LD_STOR_INS | FMT_1 | REVERSE_MATCH,  \
 359       {{rbase_disps16,16}, {regr,24}}},                                     \
 360   /* opc4 r rbase disps32 */                                                \
 361   {NAME,  3, ((0x8+OPC2)<<8)+0xF,  20, LD_STOR_INS | FMT_1 | REVERSE_MATCH, \
 362       {{rbase_disps32,16}, {regr,24}}},                                     \
 363   /* opc12 r rbase ridx scl2 disps6 */                                      \
 364   {NAME,  2, 0x32C+OPC1,  20, LD_STOR_INS | REVERSE_MATCH,                  \
 365       {{rindex_disps6,0}, {regr,16}}},                                      \
 366   /* opc12 r rbase ridx scl2 disps22 */                                     \
 367   {NAME,  3, 0x33C+OPC1,  20, LD_STOR_INS | REVERSE_MATCH,                  \
 368       {{rindex_disps22,0}, {regr,16}}},                                     \
 369   /* opc12 r rbase disps12 */                                               \
 370   {NAME,  2, 0x328+OPC1,  20, LD_STOR_INS_INC | REVERSE_MATCH,              \
 371       {{rbase_disps12,12}, {regr,16}}}
 372
 373   LD_REG_INST ("loadb", 0x0, 0x0, DISPUB4),
 374   LD_REG_INST ("loadw", 0x1, 0x1, DISPUW4),
 375   LD_REG_INST ("loadd", 0x2, 0x2, DISPUD4),
 376
 377 /* Store instructions (from Register to Memory).  */
 378 #define  ST_REG_INST(NAME, OPC1, OPC2, DISP) \
 379   /* opc12 r abs16 */                                                         \
 380   {NAME,  2, 0x320+OPC1,  20, LD_STOR_INS, {{regr,16}, {abs16,0}}},           \
 381   /* opc12 r abs32 */                                                         \
 382   {NAME,  3, 0x330+OPC1,  20, LD_STOR_INS, {{regr,16}, {abs32,0}}},           \
 383   /* opc4 r rbase dispu[bwd]4 */                                              \
 384   {NAME,  1, 0x8+OPC2,  28, LD_STOR_INS | DISP,                               \
 385       {{regr,24}, {rbase_dispu4,16}}},                                        \
 386   /* opc4 r rbase disps16 */                                                  \
 387   {NAME,  2, ((0x8+OPC2)<<8)+0xE,  20, LD_STOR_INS | FMT_1,                   \
 388       {{regr,24}, {rbase_disps16,16}}},                                       \
 389   /* opc4 r rbase disps32 */                                                  \
 390   {NAME,  3, ((0x8+OPC2)<<8)+0xF,  20, LD_STOR_INS | FMT_1,                   \
 391       {{regr,24}, {rbase_disps32,16}}},                                       \
 392   /* opc12 r rbase ridx scl2 disps6 */                                        \
 393   {NAME,  2, 0x32C+OPC1,  20, LD_STOR_INS,                                    \
 394       {{regr,16}, {rindex_disps6,0}}},                                        \
 395   /* opc12 r rbase ridx scl2 disps22 */                                       \
 396   {NAME,  3, 0x33C+OPC1,  20, LD_STOR_INS, {{regr,16}, {rindex_disps22,0}}},  \
 397   /* opc12 r rbase disps12 */                                                 \
 398   {NAME,  2, 0x328+OPC1,  20, LD_STOR_INS_INC, {{regr,16}, {rbase_disps12,12}}}
 399
 400 /* Store instructions (Immediate to Memory).  */
 401 #define  ST_I_INST(NAME, OPC) \
 402   /* opc12 ui4 rbase disps12 */                                               \
 403   {NAME,  2, 0x368+OPC, 20, LD_STOR_INS_INC, {{ui4,16}, {rbase_disps12,12}}}, \
 404   /* opc12 ui4 abs16 */                                                       \
 405   {NAME,  2, 0x360+OPC, 20, STOR_IMM_INS, {{ui4,16}, {abs16,0}}},             \
 406   /* opc12 ui4 abs32 */                                                       \
 407   {NAME,  3, 0x370+OPC, 20, STOR_IMM_INS, {{ui4,16}, {abs32,0}}},             \
 408   /* opc12 ui4 rbase disps12 */                                               \
 409   {NAME,  2, 0x364+OPC, 20, STOR_IMM_INS, {{ui4,16}, {rbase_disps12,12}}},    \
 410   /* opc12 ui4 rbase disps28 */                                               \
 411   {NAME,  3, 0x374+OPC, 20, STOR_IMM_INS, {{ui4,16}, {rbase_disps28,12}}},    \
 412   /* opc12 ui4 rbase ridx scl2 disps6 */                                      \
 413   {NAME,  2, 0x36C+OPC, 20, STOR_IMM_INS, {{ui4,16}, {rindex_disps6,0}}},     \
 414   /* opc12 ui4 rbase ridx scl2 disps22 */                                     \
 415   {NAME,  3, 0x37C+OPC, 20, STOR_IMM_INS, {{ui4,16}, {rindex_disps22,0}}}
 416
 417   ST_REG_INST ("storb", 0x20, 0x4, DISPUB4),
 418   ST_I_INST ("storb",  0x0),
 419
 420   ST_REG_INST ("storw", 0x21, 0x5, DISPUW4),
 421   ST_I_INST ("storw",  0x1),
 422
 423   ST_REG_INST ("stord", 0x22, 0x6, DISPUD4),
 424   ST_I_INST ("stord",  0x2),
 425
 426 /* Create a bit instruction.  */
 427 #define  CSTBIT_INST(NAME, OP, OPC1, DIFF, SHIFT, OPC2) \
 428   /* OP=ui3 -->> opc13 ui3 */                                                 \
 429   /* OP=ui4 -->> opc12 ui4 */                                                 \
 430   /* OP=ui5 -->> opc11 ui5 */                                                 \
 431                                                                               \
 432   /* opcNN iN abs16 */                                                        \
 433   {NAME,  2, OPC1+0*DIFF, SHIFT, CSTBIT_INS, {{OP,16}, {abs16,0}}},           \
 434   /* opcNN iN abs32 */                                                        \
 435   {NAME,  3, OPC1+1*DIFF, SHIFT, CSTBIT_INS, {{OP,16}, {abs32,0}}},           \
 436   /* opcNN iN rbase */                                                        \
 437   {NAME,  1, OPC2,  SHIFT+4,  CSTBIT_INS, {{OP,20}, {rbase,16}}},             \
 438   /* opcNN iN rbase disps12 */                                                \
 439   {NAME,  2, OPC1+2*DIFF, SHIFT, CSTBIT_INS, {{OP,16}, {rbase_disps12,12}}},  \
 440   /* opcNN iN rbase disps28 */                                                \
 441   {NAME,  3, OPC1+3*DIFF, SHIFT, CSTBIT_INS, {{OP,16}, {rbase_disps28,12}}},  \
 442   /* opcNN iN rbase ridx scl2 disps6 */                                       \
 443   {NAME,  2, OPC1+4*DIFF, SHIFT, CSTBIT_INS, {{OP,16}, {rindex_disps6,0}}},   \
 444   /* opcNN iN rbase ridx scl2 disps22 */                                      \
 445   {NAME,  3, OPC1+5*DIFF, SHIFT, CSTBIT_INS, {{OP,16}, {rindex_disps22,0}}}
 446
 447   CSTBIT_INST ("cbitb", ui3, 0x700, 0x20, 19, 0x1FC),
 448   CSTBIT_INST ("cbitw", ui4, 0x382, 0x10, 20, 0xBD),
 449   CSTBIT_INST ("cbitd", ui5, 0x1C3, 0x8,  21, 0x7B),
 450   {"cbitd",   2, 0x300838,  8, CSTBIT_INS, {{regr,4}, {regr,0}}},
 451   {"cbitd",   2, 0x18047B,  9, CSTBIT_INS, {{ui5,4}, {regr,0}}},
 452
 453   CSTBIT_INST ("sbitb", ui3, 0x701, 0x20, 19, 0x1FD),
 454   CSTBIT_INST ("sbitw", ui4, 0x383, 0x10, 20, 0xBE),
 455   CSTBIT_INST ("sbitd", ui5, 0x1C4, 0x8,  21, 0x7C),
 456   {"sbitd",   2, 0x300839,  8, CSTBIT_INS, {{regr,4}, {regr,0}}},
 457   {"sbitd",   2, 0x18047C,  9, CSTBIT_INS, {{ui5,4}, {regr,0}}},
 458
 459   CSTBIT_INST ("tbitb", ui3, 0x702, 0x20, 19, 0x1FE),
 460   CSTBIT_INST ("tbitw", ui4, 0x384, 0x10, 20, 0xBF),
 461   CSTBIT_INST ("tbitd", ui5, 0x1C5, 0x8,  21, 0x7D),
 462   {"tbitd",   2, 0x30083A,  8, CSTBIT_INS, {{regr,4}, {regr,0}}},
 463   {"tbitd",   2, 0x18047D,  9, CSTBIT_INS, {{ui5,4}, {regr,0}}},
 464
 465 /* Instructions including a register list (opcode is represented as a mask).  */
 466 #define  REGLIST_INST(NAME, OPC, FLAG) \
 467   /* opc12 r mask16 */                                                      \
 468   {NAME,  2, OPC, 20, NO_TYPE_INS | REG_LIST | FLAG, {{regr,16}, {ui16,0}}}
 469
 470   REG1_INST ("getrfid", 0xFF9),
 471   REG1_INST ("setrfid", 0xFFA),
 472
 473   REGLIST_INST ("push",  0x346,  NO_RPTR),
 474   REG1_FLAG_INST ("push", 0xFFB, NO_SP),
 475   REGLIST_INST ("pushx", 0x347,  NO_RPTR),
 476
 477   REGLIST_INST ("pop",   0x324,  NO_RPTR),
 478   REG1_FLAG_INST ("pop", 0xFFC,  NO_SP),
 479   REGLIST_INST ("popx",  0x327,  NO_RPTR),
 480
 481   REGLIST_INST ("popret", 0x326, NO_RPTR),
 482   REG1_FLAG_INST ("popret",0xFFD,NO_SP),
 483
 484   REGLIST_INST ("loadm",  0x324, NO_RPTR),
 485   REGLIST_INST ("loadma", 0x325, USER_REG),
 486
 487   REGLIST_INST ("storm",  0x344, NO_RPTR),
 488   REGLIST_INST ("storma", 0x345, USER_REG),
 489
 490 /* Create a branch instruction.  */
 491 #define  BR_INST(NAME, OPC1, OPC2, INS_TYPE) \
 492   /* opc12 r disps17 */                                                   \
 493   {NAME,  2, OPC1,  20, INS_TYPE | RELAXABLE, {{regr,16}, {disps17,0}}},  \
 494   /* opc12 r disps32 */                                                   \
 495   {NAME,  3, OPC2,  20, INS_TYPE | RELAXABLE, {{regr,16}, {disps32,0}}}
 496
 497   BR_INST ("bal",   0x307, 0x317, NO_TYPE_INS),
 498
 499   /* Decrement and Branch instructions.  */
 500   BR_INST ("dbnzb", 0x304, 0x314, DCR_BRANCH_INS),
 501   BR_INST ("dbnzw", 0x305, 0x315, DCR_BRANCH_INS),
 502   BR_INST ("dbnzd", 0x306, 0x316, DCR_BRANCH_INS),
 503
 504   /* Jump and link instructions.  */
 505   REG1_INST ("jal",    0xFF8),
 506   REG2_INST ("jal",    0x37),
 507   REG2_INST ("jalid",  0x33),
 508
 509 /* Create a CO-processor instruction.  */
 510   /* esc12 c4 ui16 */
 511   {"cpi",  2, 0x301,  20, COP_REG_INS, {{ui4,16}, {ui16,0}}},
 512   /* esc12 c4 ui16 ui16 */
 513   {"cpi",  3, 0x311,  20, COP_REG_INS, {{ui4,16}, {ui16,0}, {ui16,16}}},
 514
 515 #define  COP_INST(NAME, OPC, TYPE, REG1, REG2) \
 516   /* opc12 c4 opc8 REG1 REG2 */                                               \
 517   {NAME,  2, 0x301030+OPC,  8, TYPE | FMT_2, {{ui4,16}, {REG1,4}, {REG2,0}}}
 518 /* A reverse form of the above macro.  */
 519 #define  REV_COP_INST(NAME, OPC, TYPE, REG1, REG2) \
 520   /* opc12 c4 opc8 REG2 REG1 */                                               \
 521   {NAME,  2, 0x301030+OPC,  8, TYPE | FMT_2, {{ui4,16}, {REG1,0}, {REG2,4}}}
 522
 523   COP_INST      ("mtcr",   0, COP_REG_INS,      regr,     copregr),
 524   COP_INST      ("mfcr",   1, COP_REG_INS,      copregr,  regr),
 525   COP_INST      ("mtcsr",  2, COPS_REG_INS,     regr,     copsregr),
 526   COP_INST      ("mfcsr",  3, COPS_REG_INS,     copsregr, regr),
 527   COP_INST      ("ldcr",   4, COP_REG_INS,      regr,     copregr),
 528   REV_COP_INST  ("stcr",   5, COP_REG_INS,      copregr,  regr),
 529   COP_INST      ("ldcsr",  6, COPS_REG_INS,     regr,     copsregr),
 530   REV_COP_INST  ("stcsr",  7, COPS_REG_INS,     copsregr, regr),
 531
 532 /* Create a memory-related CO-processor instruction.  */
 533 #define  COPMEM_INST(NAME, OPC, TYPE) \
 534   /* opc12 c4 opc12 r mask16 */                           \
 535   {NAME,  3, 0x3110300+OPC,  4, TYPE | REG_LIST | FMT_5,  \
 536       {{ui4,16}, {regr,0}, {ui16,16}}}
 537
 538   COPMEM_INST("loadmcr",  0,  COP_REG_INS),
 539   COPMEM_INST("stormcr",  1,  COP_REG_INS),
 540   COPMEM_INST("loadmcsr", 2,  COPS_REG_INS),
 541   COPMEM_INST("stormcsr", 3,  COPS_REG_INS),
 542
 543   /* CO-processor extensions.  */
 544   /* opc12 c4 opc4 ui4 disps9 */
 545   {"bcop",    2, 0x30107, 12, COP_BRANCH_INS | FMT_4 | RELAXABLE,
 546       {{ui4,8}, {ui4,16}, {disps9,0}}},
 547   /* opc12 c4 opc4 ui4 disps25 */
 548   {"bcop",    3, 0x31107, 12, COP_BRANCH_INS | FMT_4 | RELAXABLE,
 549       {{ui4,8}, {ui4,16}, {disps25,0}}},
 550   /* opc12 c4 opc4 cpdo r r */
 551   {"cpdop",   2, 0x3010B, 12, COP_REG_INS | FMT_4,
 552       {{ui4,16}, {ui4,8}, {regr,4}, {regr,0}}},
 553   /* opc12 c4 opc4 cpdo r r cpdo16 */
 554   {"cpdop",   3, 0x3110B, 12, COP_REG_INS | FMT_4,
 555       {{ui4,16}, {ui4,8}, {regr,4}, {regr,0}, {ui16,16}}},
 556   /* esc16 r procreg */
 557   {"mtpr",    2, 0x3009,  16, NO_TYPE_INS, {{regr8,8}, {regr8,0}}},
 558   /* esc16 procreg r */
 559   {"mfpr",    2, 0x300A,  16, NO_TYPE_INS, {{regr8,8}, {regr8,0}}},
 560
 561   /* Miscellaneous.  */
 562   /* opc12 ui4 */
 563   {"excp",    1, 0xFFF, 20, NO_TYPE_INS, {{ui4,16}}},
 564   /* opc28 ui4 */
 565   {"cinv",    2, 0x3010000, 4,  NO_TYPE_INS, {{ui4,0}}},
 566
 567   /* opc9 ui5 ui5 ui5 r r */
 568   {"ram", 2, 0x7C,  23, NO_TYPE_INS,
 569       {{ui5,18}, {ui5,13}, {ui5,8}, {regr,4}, {regr,0}}},
 570   {"rim", 2, 0x7D,  23, NO_TYPE_INS,
 571       {{ui5,18}, {ui5,13}, {ui5,8}, {regr,4}, {regr,0}}},
 572
 573   /* opc9 ui3 r */
 574   {"rotb",    1, 0x1FB, 23, NO_TYPE_INS, {{ui3,20}, {regr,16}}},
 575   /* opc8 ui4 r */
 576   {"rotw",    1, 0xB9,  24, NO_TYPE_INS, {{ui4,20}, {regr,16}}},
 577   /* opc23 ui5 r */
 578   {"rotd",    2, 0x180478,  9, NO_TYPE_INS, {{ui5,4}, {regr,0}}},
 579
 580   {NULL,      0, 0, 0,  0, {{0, 0}}}
 581 };
 582
 583 const int crx_num_opcodes = ARRAY_SIZE (crx_instruction);
 584
 585 /* Macro to build a reg_entry, which have an opcode image :
 586    For example :
 587       REG(u4, 0x84, CRX_U_REGTYPE)
 588    is interpreted as :
 589       {"u4",  u4, 0x84, CRX_U_REGTYPE}  */
 590 #define REG(NAME, N, TYPE)    {STRINGX(NAME), {NAME}, N, TYPE}
 591
 592 const reg_entry crx_regtab[] =
 593 {
 594 /* Build a general purpose register r<N>.  */
 595 #define REG_R(N)    REG(CONCAT2(r,N), N, CRX_R_REGTYPE)
 596
 597   REG_R(0),  REG_R(1),  REG_R(2),  REG_R(3),
 598   REG_R(4),  REG_R(5),  REG_R(6),  REG_R(7),
 599   REG_R(8),  REG_R(9),  REG_R(10), REG_R(11),
 600   REG_R(12), REG_R(13), REG_R(14), REG_R(15),
 601   REG(ra, 0xe, CRX_R_REGTYPE),
 602   REG(sp, 0xf, CRX_R_REGTYPE),
 603
 604 /* Build a user register u<N>.  */
 605 #define REG_U(N)    REG(CONCAT2(u,N), 0x80 + N, CRX_U_REGTYPE)
 606
 607   REG_U(0),  REG_U(1),  REG_U(2),  REG_U(3),
 608   REG_U(4),  REG_U(5),  REG_U(6),  REG_U(7),
 609   REG_U(8),  REG_U(9),  REG_U(10), REG_U(11),
 610   REG_U(12), REG_U(13), REG_U(14), REG_U(15),
 611   REG(ura, 0x8e, CRX_U_REGTYPE),
 612   REG(usp, 0x8f, CRX_U_REGTYPE),
 613
 614 /* Build a configuration register.  */
 615 #define REG_CFG(NAME, N)    REG(NAME, N, CRX_CFG_REGTYPE)
 616
 617   REG_CFG(hi,       0x10),
 618   REG_CFG(lo,       0x11),
 619   REG_CFG(uhi,      0x90),
 620   REG_CFG(ulo,      0x91),
 621   REG_CFG(psr,      0x12),
 622   REG_CFG(intbase,  0x13),
 623   REG_CFG(isp,      0x14),
 624   REG_CFG(cfg,      0x15),
 625   REG_CFG(cpcfg,    0x16),
 626   REG_CFG(cen,      0x17)
 627 };
 628
 629 const int crx_num_regs = ARRAY_SIZE (crx_regtab);
 630
 631 const reg_entry crx_copregtab[] =
 632 {
 633 /* Build a Coprocessor register c<N>.  */
 634 #define REG_C(N)    REG(CONCAT2(c,N), N, CRX_C_REGTYPE)
 635
 636   REG_C(0),  REG_C(1),  REG_C(2),  REG_C(3),
 637   REG_C(4),  REG_C(5),  REG_C(6),  REG_C(7),
 638   REG_C(8),  REG_C(9),  REG_C(10), REG_C(11),
 639   REG_C(12), REG_C(13), REG_C(14), REG_C(15),
 640
 641 /* Build a Coprocessor Special register cs<N>.  */
 642 #define REG_CS(N)    REG(CONCAT2(cs,N), N, CRX_CS_REGTYPE)
 643
 644   REG_CS(0),  REG_CS(1),  REG_CS(2),  REG_CS(3),
 645   REG_CS(4),  REG_CS(5),  REG_CS(6),  REG_CS(7),
 646   REG_CS(8),  REG_CS(9),  REG_CS(10), REG_CS(11),
 647   REG_CS(12), REG_CS(13), REG_CS(14), REG_CS(15)
 648 };
 649
 650 const int crx_num_copregs = ARRAY_SIZE (crx_copregtab);
 651
 652 /* CRX operands table.  */
 653 const operand_entry crx_optab[] =
 654 {
 655   /* Index 0 is dummy, so we can count the instruction's operands.  */
 656   {0,   nullargs,   0},                                 /* dummy */
 657   {4,   arg_ic,     OP_CST4},                           /* cst4 */
 658   {16,  arg_ic,     OP_SIGNED},                         /* i16 */
 659   {32,  arg_ic,     OP_SIGNED},                         /* i32 */
 660   {3,   arg_ic,     OP_UNSIGNED},                       /* ui3 */
 661   {4,   arg_ic,     OP_UNSIGNED},                       /* ui4 */
 662   {5,   arg_ic,     OP_UNSIGNED},                       /* ui5 */
 663   {16,  arg_ic,     OP_UNSIGNED},                       /* ui16 */
 664   {8,   arg_c,      OP_EVEN|OP_SHIFT|OP_SIGNED},        /* disps9 */
 665   {16,  arg_c,      OP_EVEN|OP_SHIFT|OP_SIGNED},        /* disps17 */
 666   {24,  arg_c,      OP_EVEN|OP_SHIFT|OP_SIGNED},        /* disps25 */
 667   {32,  arg_c,      OP_EVEN|OP_SHIFT|OP_SIGNED},        /* disps32 */
 668   {4,   arg_c,      OP_EVEN|OP_SHIFT_DEC|OP_UNSIGNED},  /* dispu5 */
 669   {8,   arg_c,      OP_EVEN|OP_SHIFT|OP_SIGNED|OP_ESC}, /* dispe9 */
 670   {16,  arg_c,      OP_UNSIGNED|OP_UPPER_64KB},         /* abs16 */
 671   {32,  arg_c,      OP_UNSIGNED},                       /* abs32 */
 672   {4,   arg_rbase,  0},                                 /* rbase */
 673   {4,   arg_cr,     OP_DISPU4},                         /* rbase_dispu4 */
 674   {12,  arg_cr,     OP_SIGNED},                         /* rbase_disps12 */
 675   {16,  arg_cr,     OP_SIGNED},                         /* rbase_disps16 */
 676   {28,  arg_cr,     OP_SIGNED},                         /* rbase_disps28 */
 677   {32,  arg_cr,     OP_SIGNED},                         /* rbase_disps32 */
 678   {6,   arg_idxr,   OP_SIGNED},                         /* rindex_disps6 */
 679   {22,  arg_idxr,   OP_SIGNED},                         /* rindex_disps22 */
 680   {4,   arg_r,      0},                                 /* regr */
 681   {8,   arg_r,      0},                                 /* regr8 */
 682   {4,   arg_copr,   0},                                 /* copregr */
 683   {4,   arg_copsr,  0}                                  /* copsregr */
 684 };
 685
 686 /* CRX traps/interrupts.  */
 687 const trap_entry crx_traps[] =
 688 {
 689   {"nmi", 1}, {"svc", 5}, {"dvz", 6}, {"flg", 7},
 690   {"bpt", 8}, {"und", 10}, {"prv", 11}, {"iberr", 12}
 691 };
 692
 693 const int crx_num_traps = ARRAY_SIZE (crx_traps);
 694
 695 /* cst4 operand mapping:
 696 The value in entry <N> is mapped to the value <N>
 697       Value               Binary mapping
 698     cst4_map[N]   -->>          N
 699
 700 Example (for N=5):
 701
 702     cst4_map[5]=-4  -->>        5               */
 703 const long cst4_map[] =
 704 {
 705   0, 1, 2, 3, 4, -4, -1, 7, 8, 16, 32, 20, 12, 48
 706 };
 707
 708 const int cst4_maps = ARRAY_SIZE (cst4_map);
 709
 710 /* CRX instructions that don't have arguments.  */
 711 const char* no_op_insn[] =
 712 {
 713   "di", "ei", "eiwait", "nop", "retx", "wait", NULL
 714 };