1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "elf/x86-64.h"
36 #include "opcodes/i386-init.h"
38 #ifndef REGISTER_WARNINGS
39 #define REGISTER_WARNINGS 1
42 #ifndef INFER_ADDR_PREFIX
43 #define INFER_ADDR_PREFIX 1
47 #define DEFAULT_ARCH "i386"
52 #define INLINE __inline__
58 /* Prefixes will be emitted in the order defined below.
59 WAIT_PREFIX must be the first prefix since FWAIT is really is an
60 instruction, and so must come before any prefixes.
61 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
67 #define LOCKREP_PREFIX 4
68 #define REX_PREFIX 5 /* must come last. */
69 #define MAX_PREFIXES 6 /* max prefixes per opcode */
71 /* we define the syntax here (modulo base,index,scale syntax) */
72 #define REGISTER_PREFIX '%'
73 #define IMMEDIATE_PREFIX '$'
74 #define ABSOLUTE_PREFIX '*'
76 /* these are the instruction mnemonic suffixes in AT&T syntax or
77 memory operand size in Intel syntax. */
78 #define WORD_MNEM_SUFFIX 'w'
79 #define BYTE_MNEM_SUFFIX 'b'
80 #define SHORT_MNEM_SUFFIX 's'
81 #define LONG_MNEM_SUFFIX 'l'
82 #define QWORD_MNEM_SUFFIX 'q'
83 #define XMMWORD_MNEM_SUFFIX 'x'
84 #define YMMWORD_MNEM_SUFFIX 'y'
85 /* Intel Syntax. Use a non-ascii letter since since it never appears
87 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
89 #define END_OF_INSN '\0'
92 'templates' is for grouping together 'template' structures for opcodes
93 of the same name. This is only used for storing the insns in the grand
94 ole hash table of insns.
95 The templates themselves start at START and range up to (but not including)
100 const template *start
;
105 /* 386 operand encoding bytes: see 386 book for details of this. */
108 unsigned int regmem
; /* codes register or memory operand */
109 unsigned int reg
; /* codes register operand (or extended opcode) */
110 unsigned int mode
; /* how to interpret regmem & reg */
114 /* x86-64 extension prefix. */
115 typedef int rex_byte
;
117 /* The SSE5 instructions have a two bit instruction modifier (OC) that
118 is stored in two separate bytes in the instruction. Pick apart OC
119 into the 2 separate bits for instruction. */
120 #define DREX_OC0(x) (((x) & 1) != 0)
121 #define DREX_OC1(x) (((x) & 2) != 0)
123 #define DREX_OC0_MASK (1 << 3) /* set OC0 in byte 4 */
124 #define DREX_OC1_MASK (1 << 2) /* set OC1 in byte 3 */
127 #define DREX_XMEM_X1_X2_X2 0 /* 4 op insn, dest = src3, src1 = reg/mem */
128 #define DREX_X1_XMEM_X2_X2 1 /* 4 op insn, dest = src3, src2 = reg/mem */
129 #define DREX_X1_XMEM_X2_X1 2 /* 4 op insn, dest = src1, src2 = reg/mem */
130 #define DREX_X1_X2_XMEM_X1 3 /* 4 op insn, dest = src1, src3 = reg/mem */
132 #define DREX_XMEM_X1_X2 0 /* 3 op insn, src1 = reg/mem */
133 #define DREX_X1_XMEM_X2 1 /* 3 op insn, src1 = reg/mem */
135 /* Information needed to create the DREX byte in SSE5 instructions. */
138 unsigned int reg
; /* register */
139 unsigned int rex
; /* REX flags */
140 unsigned int modrm_reg
; /* which arg goes in the modrm.reg field */
141 unsigned int modrm_regmem
; /* which arg goes in the modrm.regmem field */
144 /* 386 opcode byte to code indirect addressing. */
153 /* x86 arch names, types and features */
156 const char *name
; /* arch name */
157 enum processor_type type
; /* arch type */
158 i386_cpu_flags flags
; /* cpu feature flags */
162 static void set_code_flag (int);
163 static void set_16bit_gcc_code_flag (int);
164 static void set_intel_syntax (int);
165 static void set_intel_mnemonic (int);
166 static void set_allow_index_reg (int);
167 static void set_sse_check (int);
168 static void set_cpu_arch (int);
170 static void pe_directive_secrel (int);
172 static void signed_cons (int);
173 static char *output_invalid (int c
);
174 static int i386_att_operand (char *);
175 static int i386_intel_operand (char *, int);
176 static const reg_entry
*parse_register (char *, char **);
177 static char *parse_insn (char *, char *);
178 static char *parse_operands (char *, const char *);
179 static void swap_operands (void);
180 static void swap_2_operands (int, int);
181 static void optimize_imm (void);
182 static void optimize_disp (void);
183 static int match_template (void);
184 static int check_string (void);
185 static int process_suffix (void);
186 static int check_byte_reg (void);
187 static int check_long_reg (void);
188 static int check_qword_reg (void);
189 static int check_word_reg (void);
190 static int finalize_imm (void);
191 static void process_drex (void);
192 static int process_operands (void);
193 static const seg_entry
*build_modrm_byte (void);
194 static void output_insn (void);
195 static void output_imm (fragS
*, offsetT
);
196 static void output_disp (fragS
*, offsetT
);
198 static void s_bss (int);
200 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
201 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
204 static const char *default_arch
= DEFAULT_ARCH
;
209 /* VEX prefix is either 2 byte or 3 byte. */
210 unsigned char bytes
[3];
212 /* Destination or source register specifier. */
213 const reg_entry
*register_specifier
;
216 /* 'md_assemble ()' gathers together information and puts it into a
223 const reg_entry
*regs
;
228 /* TM holds the template for the insn were currently assembling. */
231 /* SUFFIX holds the instruction size suffix for byte, word, dword
232 or qword, if given. */
235 /* OPERANDS gives the number of given operands. */
236 unsigned int operands
;
238 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
239 of given register, displacement, memory operands and immediate
241 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
243 /* TYPES [i] is the type (see above #defines) which tells us how to
244 use OP[i] for the corresponding operand. */
245 i386_operand_type types
[MAX_OPERANDS
];
247 /* Displacement expression, immediate expression, or register for each
249 union i386_op op
[MAX_OPERANDS
];
251 /* Flags for operands. */
252 unsigned int flags
[MAX_OPERANDS
];
253 #define Operand_PCrel 1
255 /* Relocation type for operand */
256 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
258 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
259 the base index byte below. */
260 const reg_entry
*base_reg
;
261 const reg_entry
*index_reg
;
262 unsigned int log2_scale_factor
;
264 /* SEG gives the seg_entries of this insn. They are zero unless
265 explicit segment overrides are given. */
266 const seg_entry
*seg
[2];
268 /* PREFIX holds all the given prefix opcodes (usually null).
269 PREFIXES is the number of prefix opcodes. */
270 unsigned int prefixes
;
271 unsigned char prefix
[MAX_PREFIXES
];
273 /* RM and SIB are the modrm byte and the sib byte where the
274 addressing modes of this insn are encoded. DREX is the byte
275 added by the SSE5 instructions. */
284 typedef struct _i386_insn i386_insn
;
286 /* List of chars besides those in app.c:symbol_chars that can start an
287 operand. Used to prevent the scrubber eating vital white-space. */
288 const char extra_symbol_chars
[] = "*%-(["
297 #if (defined (TE_I386AIX) \
298 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
299 && !defined (TE_GNU) \
300 && !defined (TE_LINUX) \
301 && !defined (TE_NETWARE) \
302 && !defined (TE_FreeBSD) \
303 && !defined (TE_NetBSD)))
304 /* This array holds the chars that always start a comment. If the
305 pre-processor is disabled, these aren't very useful. The option
306 --divide will remove '/' from this list. */
307 const char *i386_comment_chars
= "#/";
308 #define SVR4_COMMENT_CHARS 1
309 #define PREFIX_SEPARATOR '\\'
312 const char *i386_comment_chars
= "#";
313 #define PREFIX_SEPARATOR '/'
316 /* This array holds the chars that only start a comment at the beginning of
317 a line. If the line seems to have the form '# 123 filename'
318 .line and .file directives will appear in the pre-processed output.
319 Note that input_file.c hand checks for '#' at the beginning of the
320 first line of the input file. This is because the compiler outputs
321 #NO_APP at the beginning of its output.
322 Also note that comments started like this one will always work if
323 '/' isn't otherwise defined. */
324 const char line_comment_chars
[] = "#/";
326 const char line_separator_chars
[] = ";";
328 /* Chars that can be used to separate mant from exp in floating point
330 const char EXP_CHARS
[] = "eE";
332 /* Chars that mean this number is a floating point constant
335 const char FLT_CHARS
[] = "fFdDxX";
337 /* Tables for lexical analysis. */
338 static char mnemonic_chars
[256];
339 static char register_chars
[256];
340 static char operand_chars
[256];
341 static char identifier_chars
[256];
342 static char digit_chars
[256];
344 /* Lexical macros. */
345 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
346 #define is_operand_char(x) (operand_chars[(unsigned char) x])
347 #define is_register_char(x) (register_chars[(unsigned char) x])
348 #define is_space_char(x) ((x) == ' ')
349 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
350 #define is_digit_char(x) (digit_chars[(unsigned char) x])
352 /* All non-digit non-letter characters that may occur in an operand. */
353 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
355 /* md_assemble() always leaves the strings it's passed unaltered. To
356 effect this we maintain a stack of saved characters that we've smashed
357 with '\0's (indicating end of strings for various sub-fields of the
358 assembler instruction). */
359 static char save_stack
[32];
360 static char *save_stack_p
;
361 #define END_STRING_AND_SAVE(s) \
362 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
363 #define RESTORE_END_STRING(s) \
364 do { *(s) = *--save_stack_p; } while (0)
366 /* The instruction we're assembling. */
369 /* Possible templates for current insn. */
370 static const templates
*current_templates
;
372 /* Per instruction expressionS buffers: max displacements & immediates. */
373 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
374 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
376 /* Current operand we are working on. */
377 static int this_operand
;
379 /* We support four different modes. FLAG_CODE variable is used to distinguish
387 static enum flag_code flag_code
;
388 static unsigned int object_64bit
;
389 static int use_rela_relocations
= 0;
391 /* The names used to print error messages. */
392 static const char *flag_code_names
[] =
399 /* 1 for intel syntax,
401 static int intel_syntax
= 0;
403 /* 1 for intel mnemonic,
404 0 if att mnemonic. */
405 static int intel_mnemonic
= !SYSV386_COMPAT
;
407 /* 1 if support old (<= 2.8.1) versions of gcc. */
408 static int old_gcc
= OLDGCC_COMPAT
;
410 /* 1 if pseudo registers are permitted. */
411 static int allow_pseudo_reg
= 0;
413 /* 1 if register prefix % not required. */
414 static int allow_naked_reg
= 0;
416 /* 1 if pseudo index register, eiz/riz, is allowed . */
417 static int allow_index_reg
= 0;
427 /* Register prefix used for error message. */
428 static const char *register_prefix
= "%";
430 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
431 leave, push, and pop instructions so that gcc has the same stack
432 frame as in 32 bit mode. */
433 static char stackop_size
= '\0';
435 /* Non-zero to optimize code alignment. */
436 int optimize_align_code
= 1;
438 /* Non-zero to quieten some warnings. */
439 static int quiet_warnings
= 0;
442 static const char *cpu_arch_name
= NULL
;
443 static char *cpu_sub_arch_name
= NULL
;
445 /* CPU feature flags. */
446 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
448 /* If we have selected a cpu we are generating instructions for. */
449 static int cpu_arch_tune_set
= 0;
451 /* Cpu we are generating instructions for. */
452 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
454 /* CPU feature flags of cpu we are generating instructions for. */
455 static i386_cpu_flags cpu_arch_tune_flags
;
457 /* CPU instruction set architecture used. */
458 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
460 /* CPU feature flags of instruction set architecture used. */
461 i386_cpu_flags cpu_arch_isa_flags
;
463 /* If set, conditional jumps are not automatically promoted to handle
464 larger than a byte offset. */
465 static unsigned int no_cond_jump_promotion
= 0;
467 /* Encode SSE instructions with VEX prefix. */
468 static unsigned int sse2avx
;
470 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
471 static symbolS
*GOT_symbol
;
473 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
474 unsigned int x86_dwarf2_return_column
;
476 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
477 int x86_cie_data_alignment
;
479 /* Interface to relax_segment.
480 There are 3 major relax states for 386 jump insns because the
481 different types of jumps add different sizes to frags when we're
482 figuring out what sort of jump to choose to reach a given label. */
485 #define UNCOND_JUMP 0
487 #define COND_JUMP86 2
492 #define SMALL16 (SMALL | CODE16)
494 #define BIG16 (BIG | CODE16)
498 #define INLINE __inline__
504 #define ENCODE_RELAX_STATE(type, size) \
505 ((relax_substateT) (((type) << 2) | (size)))
506 #define TYPE_FROM_RELAX_STATE(s) \
508 #define DISP_SIZE_FROM_RELAX_STATE(s) \
509 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
511 /* This table is used by relax_frag to promote short jumps to long
512 ones where necessary. SMALL (short) jumps may be promoted to BIG
513 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
514 don't allow a short jump in a 32 bit code segment to be promoted to
515 a 16 bit offset jump because it's slower (requires data size
516 prefix), and doesn't work, unless the destination is in the bottom
517 64k of the code segment (The top 16 bits of eip are zeroed). */
519 const relax_typeS md_relax_table
[] =
522 1) most positive reach of this state,
523 2) most negative reach of this state,
524 3) how many bytes this mode will have in the variable part of the frag
525 4) which index into the table to try if we can't fit into this one. */
527 /* UNCOND_JUMP states. */
528 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
529 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
530 /* dword jmp adds 4 bytes to frag:
531 0 extra opcode bytes, 4 displacement bytes. */
533 /* word jmp adds 2 byte2 to frag:
534 0 extra opcode bytes, 2 displacement bytes. */
537 /* COND_JUMP states. */
538 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
539 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
540 /* dword conditionals adds 5 bytes to frag:
541 1 extra opcode byte, 4 displacement bytes. */
543 /* word conditionals add 3 bytes to frag:
544 1 extra opcode byte, 2 displacement bytes. */
547 /* COND_JUMP86 states. */
548 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
549 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
550 /* dword conditionals adds 5 bytes to frag:
551 1 extra opcode byte, 4 displacement bytes. */
553 /* word conditionals add 4 bytes to frag:
554 1 displacement byte and a 3 byte long branch insn. */
558 static const arch_entry cpu_arch
[] =
560 { "generic32", PROCESSOR_GENERIC32
,
561 CPU_GENERIC32_FLAGS
},
562 { "generic64", PROCESSOR_GENERIC64
,
563 CPU_GENERIC64_FLAGS
},
564 { "i8086", PROCESSOR_UNKNOWN
,
566 { "i186", PROCESSOR_UNKNOWN
,
568 { "i286", PROCESSOR_UNKNOWN
,
570 { "i386", PROCESSOR_I386
,
572 { "i486", PROCESSOR_I486
,
574 { "i586", PROCESSOR_PENTIUM
,
576 { "i686", PROCESSOR_PENTIUMPRO
,
578 { "pentium", PROCESSOR_PENTIUM
,
580 { "pentiumpro", PROCESSOR_PENTIUMPRO
,
582 { "pentiumii", PROCESSOR_PENTIUMPRO
,
584 { "pentiumiii",PROCESSOR_PENTIUMPRO
,
586 { "pentium4", PROCESSOR_PENTIUM4
,
588 { "prescott", PROCESSOR_NOCONA
,
590 { "nocona", PROCESSOR_NOCONA
,
592 { "yonah", PROCESSOR_CORE
,
594 { "core", PROCESSOR_CORE
,
596 { "merom", PROCESSOR_CORE2
,
598 { "core2", PROCESSOR_CORE2
,
600 { "k6", PROCESSOR_K6
,
602 { "k6_2", PROCESSOR_K6
,
604 { "athlon", PROCESSOR_ATHLON
,
606 { "sledgehammer", PROCESSOR_K8
,
608 { "opteron", PROCESSOR_K8
,
610 { "k8", PROCESSOR_K8
,
612 { "amdfam10", PROCESSOR_AMDFAM10
,
613 CPU_AMDFAM10_FLAGS
},
614 { ".mmx", PROCESSOR_UNKNOWN
,
616 { ".sse", PROCESSOR_UNKNOWN
,
618 { ".sse2", PROCESSOR_UNKNOWN
,
620 { ".sse3", PROCESSOR_UNKNOWN
,
622 { ".ssse3", PROCESSOR_UNKNOWN
,
624 { ".sse4.1", PROCESSOR_UNKNOWN
,
626 { ".sse4.2", PROCESSOR_UNKNOWN
,
628 { ".sse4", PROCESSOR_UNKNOWN
,
630 { ".avx", PROCESSOR_UNKNOWN
,
632 { ".vmx", PROCESSOR_UNKNOWN
,
634 { ".smx", PROCESSOR_UNKNOWN
,
636 { ".xsave", PROCESSOR_UNKNOWN
,
638 { ".aes", PROCESSOR_UNKNOWN
,
640 { ".pclmul", PROCESSOR_UNKNOWN
,
642 { ".clmul", PROCESSOR_UNKNOWN
,
644 { ".fma", PROCESSOR_UNKNOWN
,
646 { ".movbe", PROCESSOR_UNKNOWN
,
648 { ".ept", PROCESSOR_UNKNOWN
,
650 { ".3dnow", PROCESSOR_UNKNOWN
,
652 { ".3dnowa", PROCESSOR_UNKNOWN
,
654 { ".padlock", PROCESSOR_UNKNOWN
,
656 { ".pacifica", PROCESSOR_UNKNOWN
,
658 { ".svme", PROCESSOR_UNKNOWN
,
660 { ".sse4a", PROCESSOR_UNKNOWN
,
662 { ".abm", PROCESSOR_UNKNOWN
,
664 { ".sse5", PROCESSOR_UNKNOWN
,
669 /* Like s_lcomm_internal in gas/read.c but the alignment string
670 is allowed to be optional. */
673 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
680 && *input_line_pointer
== ',')
682 align
= parse_align (needs_align
- 1);
684 if (align
== (addressT
) -1)
699 bss_alloc (symbolP
, size
, align
);
704 pe_lcomm (int needs_align
)
706 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
710 const pseudo_typeS md_pseudo_table
[] =
712 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
713 {"align", s_align_bytes
, 0},
715 {"align", s_align_ptwo
, 0},
717 {"arch", set_cpu_arch
, 0},
721 {"lcomm", pe_lcomm
, 1},
723 {"ffloat", float_cons
, 'f'},
724 {"dfloat", float_cons
, 'd'},
725 {"tfloat", float_cons
, 'x'},
727 {"slong", signed_cons
, 4},
728 {"noopt", s_ignore
, 0},
729 {"optim", s_ignore
, 0},
730 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
731 {"code16", set_code_flag
, CODE_16BIT
},
732 {"code32", set_code_flag
, CODE_32BIT
},
733 {"code64", set_code_flag
, CODE_64BIT
},
734 {"intel_syntax", set_intel_syntax
, 1},
735 {"att_syntax", set_intel_syntax
, 0},
736 {"intel_mnemonic", set_intel_mnemonic
, 1},
737 {"att_mnemonic", set_intel_mnemonic
, 0},
738 {"allow_index_reg", set_allow_index_reg
, 1},
739 {"disallow_index_reg", set_allow_index_reg
, 0},
740 {"sse_check", set_sse_check
, 0},
741 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
742 {"largecomm", handle_large_common
, 0},
744 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
745 {"loc", dwarf2_directive_loc
, 0},
746 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
749 {"secrel32", pe_directive_secrel
, 0},
754 /* For interface with expression (). */
755 extern char *input_line_pointer
;
757 /* Hash table for instruction mnemonic lookup. */
758 static struct hash_control
*op_hash
;
760 /* Hash table for register lookup. */
761 static struct hash_control
*reg_hash
;
764 i386_align_code (fragS
*fragP
, int count
)
766 /* Various efficient no-op patterns for aligning code labels.
767 Note: Don't try to assemble the instructions in the comments.
768 0L and 0w are not legal. */
769 static const char f32_1
[] =
771 static const char f32_2
[] =
772 {0x66,0x90}; /* xchg %ax,%ax */
773 static const char f32_3
[] =
774 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
775 static const char f32_4
[] =
776 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
777 static const char f32_5
[] =
779 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
780 static const char f32_6
[] =
781 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
782 static const char f32_7
[] =
783 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
784 static const char f32_8
[] =
786 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
787 static const char f32_9
[] =
788 {0x89,0xf6, /* movl %esi,%esi */
789 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
790 static const char f32_10
[] =
791 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
792 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
793 static const char f32_11
[] =
794 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
795 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
796 static const char f32_12
[] =
797 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
798 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
799 static const char f32_13
[] =
800 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
801 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
802 static const char f32_14
[] =
803 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
804 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
805 static const char f16_3
[] =
806 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
807 static const char f16_4
[] =
808 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
809 static const char f16_5
[] =
811 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
812 static const char f16_6
[] =
813 {0x89,0xf6, /* mov %si,%si */
814 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
815 static const char f16_7
[] =
816 {0x8d,0x74,0x00, /* lea 0(%si),%si */
817 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
818 static const char f16_8
[] =
819 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
820 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
821 static const char jump_31
[] =
822 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
823 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
824 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
825 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
826 static const char *const f32_patt
[] = {
827 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
828 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
830 static const char *const f16_patt
[] = {
831 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
834 static const char alt_3
[] =
836 /* nopl 0(%[re]ax) */
837 static const char alt_4
[] =
838 {0x0f,0x1f,0x40,0x00};
839 /* nopl 0(%[re]ax,%[re]ax,1) */
840 static const char alt_5
[] =
841 {0x0f,0x1f,0x44,0x00,0x00};
842 /* nopw 0(%[re]ax,%[re]ax,1) */
843 static const char alt_6
[] =
844 {0x66,0x0f,0x1f,0x44,0x00,0x00};
845 /* nopl 0L(%[re]ax) */
846 static const char alt_7
[] =
847 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
848 /* nopl 0L(%[re]ax,%[re]ax,1) */
849 static const char alt_8
[] =
850 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
851 /* nopw 0L(%[re]ax,%[re]ax,1) */
852 static const char alt_9
[] =
853 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
854 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
855 static const char alt_10
[] =
856 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
858 nopw %cs:0L(%[re]ax,%[re]ax,1) */
859 static const char alt_long_11
[] =
861 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
864 nopw %cs:0L(%[re]ax,%[re]ax,1) */
865 static const char alt_long_12
[] =
868 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
872 nopw %cs:0L(%[re]ax,%[re]ax,1) */
873 static const char alt_long_13
[] =
877 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
882 nopw %cs:0L(%[re]ax,%[re]ax,1) */
883 static const char alt_long_14
[] =
888 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
894 nopw %cs:0L(%[re]ax,%[re]ax,1) */
895 static const char alt_long_15
[] =
901 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
902 /* nopl 0(%[re]ax,%[re]ax,1)
903 nopw 0(%[re]ax,%[re]ax,1) */
904 static const char alt_short_11
[] =
905 {0x0f,0x1f,0x44,0x00,0x00,
906 0x66,0x0f,0x1f,0x44,0x00,0x00};
907 /* nopw 0(%[re]ax,%[re]ax,1)
908 nopw 0(%[re]ax,%[re]ax,1) */
909 static const char alt_short_12
[] =
910 {0x66,0x0f,0x1f,0x44,0x00,0x00,
911 0x66,0x0f,0x1f,0x44,0x00,0x00};
912 /* nopw 0(%[re]ax,%[re]ax,1)
914 static const char alt_short_13
[] =
915 {0x66,0x0f,0x1f,0x44,0x00,0x00,
916 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
919 static const char alt_short_14
[] =
920 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
921 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
923 nopl 0L(%[re]ax,%[re]ax,1) */
924 static const char alt_short_15
[] =
925 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
926 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
927 static const char *const alt_short_patt
[] = {
928 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
929 alt_9
, alt_10
, alt_short_11
, alt_short_12
, alt_short_13
,
930 alt_short_14
, alt_short_15
932 static const char *const alt_long_patt
[] = {
933 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
934 alt_9
, alt_10
, alt_long_11
, alt_long_12
, alt_long_13
,
935 alt_long_14
, alt_long_15
938 /* Only align for at least a positive non-zero boundary. */
939 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
942 /* We need to decide which NOP sequence to use for 32bit and
943 64bit. When -mtune= is used:
945 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
946 PROCESSOR_GENERIC32, f32_patt will be used.
947 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
948 PROCESSOR_CORE, PROCESSOR_CORE2, and PROCESSOR_GENERIC64,
949 alt_long_patt will be used.
950 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
951 PROCESSOR_AMDFAM10, alt_short_patt will be used.
953 When -mtune= isn't used, alt_long_patt will be used if
954 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
957 When -march= or .arch is used, we can't use anything beyond
958 cpu_arch_isa_flags. */
960 if (flag_code
== CODE_16BIT
)
964 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
966 /* Adjust jump offset. */
967 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
970 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
971 f16_patt
[count
- 1], count
);
975 const char *const *patt
= NULL
;
977 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
979 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
980 switch (cpu_arch_tune
)
982 case PROCESSOR_UNKNOWN
:
983 /* We use cpu_arch_isa_flags to check if we SHOULD
984 optimize for Cpu686. */
985 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpui686
)
986 patt
= alt_long_patt
;
990 case PROCESSOR_PENTIUMPRO
:
991 case PROCESSOR_PENTIUM4
:
992 case PROCESSOR_NOCONA
:
994 case PROCESSOR_CORE2
:
995 case PROCESSOR_GENERIC64
:
996 patt
= alt_long_patt
;
999 case PROCESSOR_ATHLON
:
1001 case PROCESSOR_AMDFAM10
:
1002 patt
= alt_short_patt
;
1004 case PROCESSOR_I386
:
1005 case PROCESSOR_I486
:
1006 case PROCESSOR_PENTIUM
:
1007 case PROCESSOR_GENERIC32
:
1014 switch (fragP
->tc_frag_data
.tune
)
1016 case PROCESSOR_UNKNOWN
:
1017 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1018 PROCESSOR_UNKNOWN. */
1022 case PROCESSOR_I386
:
1023 case PROCESSOR_I486
:
1024 case PROCESSOR_PENTIUM
:
1026 case PROCESSOR_ATHLON
:
1028 case PROCESSOR_AMDFAM10
:
1029 case PROCESSOR_GENERIC32
:
1030 /* We use cpu_arch_isa_flags to check if we CAN optimize
1032 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpui686
)
1033 patt
= alt_short_patt
;
1037 case PROCESSOR_PENTIUMPRO
:
1038 case PROCESSOR_PENTIUM4
:
1039 case PROCESSOR_NOCONA
:
1040 case PROCESSOR_CORE
:
1041 case PROCESSOR_CORE2
:
1042 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpui686
)
1043 patt
= alt_long_patt
;
1047 case PROCESSOR_GENERIC64
:
1048 patt
= alt_long_patt
;
1053 if (patt
== f32_patt
)
1055 /* If the padding is less than 15 bytes, we use the normal
1056 ones. Otherwise, we use a jump instruction and adjust
1059 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1060 patt
[count
- 1], count
);
1063 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1065 /* Adjust jump offset. */
1066 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1071 /* Maximum length of an instruction is 15 byte. If the
1072 padding is greater than 15 bytes and we don't use jump,
1073 we have to break it into smaller pieces. */
1074 int padding
= count
;
1075 while (padding
> 15)
1078 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1083 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1084 patt
[padding
- 1], padding
);
1087 fragP
->fr_var
= count
;
1091 operand_type_all_zero (const union i386_operand_type
*x
)
1093 switch (ARRAY_SIZE(x
->array
))
1102 return !x
->array
[0];
1109 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1111 switch (ARRAY_SIZE(x
->array
))
1126 operand_type_equal (const union i386_operand_type
*x
,
1127 const union i386_operand_type
*y
)
1129 switch (ARRAY_SIZE(x
->array
))
1132 if (x
->array
[2] != y
->array
[2])
1135 if (x
->array
[1] != y
->array
[1])
1138 return x
->array
[0] == y
->array
[0];
1146 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1148 switch (ARRAY_SIZE(x
->array
))
1157 return !x
->array
[0];
1164 cpu_flags_set (union i386_cpu_flags
*x
, unsigned int v
)
1166 switch (ARRAY_SIZE(x
->array
))
1181 cpu_flags_equal (const union i386_cpu_flags
*x
,
1182 const union i386_cpu_flags
*y
)
1184 switch (ARRAY_SIZE(x
->array
))
1187 if (x
->array
[2] != y
->array
[2])
1190 if (x
->array
[1] != y
->array
[1])
1193 return x
->array
[0] == y
->array
[0];
1201 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1203 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1204 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1207 static INLINE i386_cpu_flags
1208 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1210 switch (ARRAY_SIZE (x
.array
))
1213 x
.array
[2] &= y
.array
[2];
1215 x
.array
[1] &= y
.array
[1];
1217 x
.array
[0] &= y
.array
[0];
1225 static INLINE i386_cpu_flags
1226 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1228 switch (ARRAY_SIZE (x
.array
))
1231 x
.array
[2] |= y
.array
[2];
1233 x
.array
[1] |= y
.array
[1];
1235 x
.array
[0] |= y
.array
[0];
1243 #define CPU_FLAGS_ARCH_MATCH 0x1
1244 #define CPU_FLAGS_64BIT_MATCH 0x2
1245 #define CPU_FLAGS_AES_MATCH 0x4
1246 #define CPU_FLAGS_AVX_MATCH 0x8
1248 #define CPU_FLAGS_32BIT_MATCH \
1249 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH | CPU_FLAGS_AVX_MATCH)
1250 #define CPU_FLAGS_PERFECT_MATCH \
1251 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1253 /* Return CPU flags match bits. */
1256 cpu_flags_match (const template *t
)
1258 i386_cpu_flags x
= t
->cpu_flags
;
1259 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1261 x
.bitfield
.cpu64
= 0;
1262 x
.bitfield
.cpuno64
= 0;
1264 if (cpu_flags_all_zero (&x
))
1266 /* This instruction is available on all archs. */
1267 match
|= CPU_FLAGS_32BIT_MATCH
;
1271 /* This instruction is available only on some archs. */
1272 i386_cpu_flags cpu
= cpu_arch_flags
;
1274 cpu
.bitfield
.cpu64
= 0;
1275 cpu
.bitfield
.cpuno64
= 0;
1276 cpu
= cpu_flags_and (x
, cpu
);
1277 if (!cpu_flags_all_zero (&cpu
))
1279 if (x
.bitfield
.cpuavx
)
1281 /* We only need to check AES/SSE2AVX with AVX. */
1282 if (cpu
.bitfield
.cpuavx
)
1284 /* Check SSE2AVX. */
1285 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1287 match
|= (CPU_FLAGS_ARCH_MATCH
1288 | CPU_FLAGS_AVX_MATCH
);
1290 if (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1291 match
|= CPU_FLAGS_AES_MATCH
;
1295 match
|= CPU_FLAGS_ARCH_MATCH
;
1298 match
|= CPU_FLAGS_32BIT_MATCH
;
1304 static INLINE i386_operand_type
1305 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1307 switch (ARRAY_SIZE (x
.array
))
1310 x
.array
[2] &= y
.array
[2];
1312 x
.array
[1] &= y
.array
[1];
1314 x
.array
[0] &= y
.array
[0];
1322 static INLINE i386_operand_type
1323 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1325 switch (ARRAY_SIZE (x
.array
))
1328 x
.array
[2] |= y
.array
[2];
1330 x
.array
[1] |= y
.array
[1];
1332 x
.array
[0] |= y
.array
[0];
1340 static INLINE i386_operand_type
1341 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1343 switch (ARRAY_SIZE (x
.array
))
1346 x
.array
[2] ^= y
.array
[2];
1348 x
.array
[1] ^= y
.array
[1];
1350 x
.array
[0] ^= y
.array
[0];
1358 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1359 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1360 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1361 static const i386_operand_type inoutportreg
1362 = OPERAND_TYPE_INOUTPORTREG
;
1363 static const i386_operand_type reg16_inoutportreg
1364 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1365 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1366 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1367 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1368 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1369 static const i386_operand_type anydisp
1370 = OPERAND_TYPE_ANYDISP
;
1371 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1372 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1373 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1374 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1375 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1376 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1377 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1378 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1379 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1380 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1381 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1382 static const i386_operand_type vex_imm4
= OPERAND_TYPE_VEX_IMM4
;
1393 operand_type_check (i386_operand_type t
, enum operand_type c
)
1398 return (t
.bitfield
.reg8
1401 || t
.bitfield
.reg64
);
1404 return (t
.bitfield
.imm8
1408 || t
.bitfield
.imm32s
1409 || t
.bitfield
.imm64
);
1412 return (t
.bitfield
.disp8
1413 || t
.bitfield
.disp16
1414 || t
.bitfield
.disp32
1415 || t
.bitfield
.disp32s
1416 || t
.bitfield
.disp64
);
1419 return (t
.bitfield
.disp8
1420 || t
.bitfield
.disp16
1421 || t
.bitfield
.disp32
1422 || t
.bitfield
.disp32s
1423 || t
.bitfield
.disp64
1424 || t
.bitfield
.baseindex
);
1433 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1434 operand J for instruction template T. */
1437 match_reg_size (const template *t
, unsigned int j
)
1439 return !((i
.types
[j
].bitfield
.byte
1440 && !t
->operand_types
[j
].bitfield
.byte
)
1441 || (i
.types
[j
].bitfield
.word
1442 && !t
->operand_types
[j
].bitfield
.word
)
1443 || (i
.types
[j
].bitfield
.dword
1444 && !t
->operand_types
[j
].bitfield
.dword
)
1445 || (i
.types
[j
].bitfield
.qword
1446 && !t
->operand_types
[j
].bitfield
.qword
));
1449 /* Return 1 if there is no conflict in any size on operand J for
1450 instruction template T. */
1453 match_mem_size (const template *t
, unsigned int j
)
1455 return (match_reg_size (t
, j
)
1456 && !((i
.types
[j
].bitfield
.unspecified
1457 && !t
->operand_types
[j
].bitfield
.unspecified
)
1458 || (i
.types
[j
].bitfield
.fword
1459 && !t
->operand_types
[j
].bitfield
.fword
)
1460 || (i
.types
[j
].bitfield
.tbyte
1461 && !t
->operand_types
[j
].bitfield
.tbyte
)
1462 || (i
.types
[j
].bitfield
.xmmword
1463 && !t
->operand_types
[j
].bitfield
.xmmword
)
1464 || (i
.types
[j
].bitfield
.ymmword
1465 && !t
->operand_types
[j
].bitfield
.ymmword
)));
1468 /* Return 1 if there is no size conflict on any operands for
1469 instruction template T. */
1472 operand_size_match (const template *t
)
1477 /* Don't check jump instructions. */
1478 if (t
->opcode_modifier
.jump
1479 || t
->opcode_modifier
.jumpbyte
1480 || t
->opcode_modifier
.jumpdword
1481 || t
->opcode_modifier
.jumpintersegment
)
1484 /* Check memory and accumulator operand size. */
1485 for (j
= 0; j
< i
.operands
; j
++)
1487 if (t
->operand_types
[j
].bitfield
.anysize
)
1490 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1496 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1504 || (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
))
1507 /* Check reverse. */
1508 assert (i
.operands
== 2);
1511 for (j
= 0; j
< 2; j
++)
1513 if (t
->operand_types
[j
].bitfield
.acc
1514 && !match_reg_size (t
, j
? 0 : 1))
1520 if (i
.types
[j
].bitfield
.mem
1521 && !match_mem_size (t
, j
? 0 : 1))
1532 operand_type_match (i386_operand_type overlap
,
1533 i386_operand_type given
)
1535 i386_operand_type temp
= overlap
;
1537 temp
.bitfield
.jumpabsolute
= 0;
1538 temp
.bitfield
.unspecified
= 0;
1539 temp
.bitfield
.byte
= 0;
1540 temp
.bitfield
.word
= 0;
1541 temp
.bitfield
.dword
= 0;
1542 temp
.bitfield
.fword
= 0;
1543 temp
.bitfield
.qword
= 0;
1544 temp
.bitfield
.tbyte
= 0;
1545 temp
.bitfield
.xmmword
= 0;
1546 temp
.bitfield
.ymmword
= 0;
1547 if (operand_type_all_zero (&temp
))
1550 return (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1551 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
);
1554 /* If given types g0 and g1 are registers they must be of the same type
1555 unless the expected operand type register overlap is null.
1556 Note that Acc in a template matches every size of reg. */
1559 operand_type_register_match (i386_operand_type m0
,
1560 i386_operand_type g0
,
1561 i386_operand_type t0
,
1562 i386_operand_type m1
,
1563 i386_operand_type g1
,
1564 i386_operand_type t1
)
1566 if (!operand_type_check (g0
, reg
))
1569 if (!operand_type_check (g1
, reg
))
1572 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1573 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1574 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1575 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1578 if (m0
.bitfield
.acc
)
1580 t0
.bitfield
.reg8
= 1;
1581 t0
.bitfield
.reg16
= 1;
1582 t0
.bitfield
.reg32
= 1;
1583 t0
.bitfield
.reg64
= 1;
1586 if (m1
.bitfield
.acc
)
1588 t1
.bitfield
.reg8
= 1;
1589 t1
.bitfield
.reg16
= 1;
1590 t1
.bitfield
.reg32
= 1;
1591 t1
.bitfield
.reg64
= 1;
1594 return (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1595 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1596 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1597 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
));
1600 static INLINE
unsigned int
1601 mode_from_disp_size (i386_operand_type t
)
1603 if (t
.bitfield
.disp8
)
1605 else if (t
.bitfield
.disp16
1606 || t
.bitfield
.disp32
1607 || t
.bitfield
.disp32s
)
1614 fits_in_signed_byte (offsetT num
)
1616 return (num
>= -128) && (num
<= 127);
1620 fits_in_unsigned_byte (offsetT num
)
1622 return (num
& 0xff) == num
;
1626 fits_in_unsigned_word (offsetT num
)
1628 return (num
& 0xffff) == num
;
1632 fits_in_signed_word (offsetT num
)
1634 return (-32768 <= num
) && (num
<= 32767);
1638 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED
)
1643 return (!(((offsetT
) -1 << 31) & num
)
1644 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
1646 } /* fits_in_signed_long() */
1649 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED
)
1654 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
1656 } /* fits_in_unsigned_long() */
1659 fits_in_imm4 (offsetT num
)
1661 return (num
& 0xf) == num
;
1664 static i386_operand_type
1665 smallest_imm_type (offsetT num
)
1667 i386_operand_type t
;
1669 operand_type_set (&t
, 0);
1670 t
.bitfield
.imm64
= 1;
1672 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
1674 /* This code is disabled on the 486 because all the Imm1 forms
1675 in the opcode table are slower on the i486. They're the
1676 versions with the implicitly specified single-position
1677 displacement, which has another syntax if you really want to
1679 t
.bitfield
.imm1
= 1;
1680 t
.bitfield
.imm8
= 1;
1681 t
.bitfield
.imm8s
= 1;
1682 t
.bitfield
.imm16
= 1;
1683 t
.bitfield
.imm32
= 1;
1684 t
.bitfield
.imm32s
= 1;
1686 else if (fits_in_signed_byte (num
))
1688 t
.bitfield
.imm8
= 1;
1689 t
.bitfield
.imm8s
= 1;
1690 t
.bitfield
.imm16
= 1;
1691 t
.bitfield
.imm32
= 1;
1692 t
.bitfield
.imm32s
= 1;
1694 else if (fits_in_unsigned_byte (num
))
1696 t
.bitfield
.imm8
= 1;
1697 t
.bitfield
.imm16
= 1;
1698 t
.bitfield
.imm32
= 1;
1699 t
.bitfield
.imm32s
= 1;
1701 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
1703 t
.bitfield
.imm16
= 1;
1704 t
.bitfield
.imm32
= 1;
1705 t
.bitfield
.imm32s
= 1;
1707 else if (fits_in_signed_long (num
))
1709 t
.bitfield
.imm32
= 1;
1710 t
.bitfield
.imm32s
= 1;
1712 else if (fits_in_unsigned_long (num
))
1713 t
.bitfield
.imm32
= 1;
1719 offset_in_range (offsetT val
, int size
)
1725 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
1726 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
1727 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
1729 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
1734 /* If BFD64, sign extend val. */
1735 if (!use_rela_relocations
)
1736 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
1737 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
1739 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
1741 char buf1
[40], buf2
[40];
1743 sprint_value (buf1
, val
);
1744 sprint_value (buf2
, val
& mask
);
1745 as_warn (_("%s shortened to %s"), buf1
, buf2
);
1750 /* Returns 0 if attempting to add a prefix where one from the same
1751 class already exists, 1 if non rep/repne added, 2 if rep/repne
1754 add_prefix (unsigned int prefix
)
1759 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
1760 && flag_code
== CODE_64BIT
)
1762 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
1763 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
1764 && (prefix
& (REX_R
| REX_X
| REX_B
))))
1775 case CS_PREFIX_OPCODE
:
1776 case DS_PREFIX_OPCODE
:
1777 case ES_PREFIX_OPCODE
:
1778 case FS_PREFIX_OPCODE
:
1779 case GS_PREFIX_OPCODE
:
1780 case SS_PREFIX_OPCODE
:
1784 case REPNE_PREFIX_OPCODE
:
1785 case REPE_PREFIX_OPCODE
:
1788 case LOCK_PREFIX_OPCODE
:
1796 case ADDR_PREFIX_OPCODE
:
1800 case DATA_PREFIX_OPCODE
:
1804 if (i
.prefix
[q
] != 0)
1812 i
.prefix
[q
] |= prefix
;
1815 as_bad (_("same type of prefix used twice"));
1821 set_code_flag (int value
)
1824 if (flag_code
== CODE_64BIT
)
1826 cpu_arch_flags
.bitfield
.cpu64
= 1;
1827 cpu_arch_flags
.bitfield
.cpuno64
= 0;
1831 cpu_arch_flags
.bitfield
.cpu64
= 0;
1832 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1834 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
1836 as_bad (_("64bit mode not supported on this CPU."));
1838 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
1840 as_bad (_("32bit mode not supported on this CPU."));
1842 stackop_size
= '\0';
1846 set_16bit_gcc_code_flag (int new_code_flag
)
1848 flag_code
= new_code_flag
;
1849 if (flag_code
!= CODE_16BIT
)
1851 cpu_arch_flags
.bitfield
.cpu64
= 0;
1852 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1853 stackop_size
= LONG_MNEM_SUFFIX
;
1857 set_intel_syntax (int syntax_flag
)
1859 /* Find out if register prefixing is specified. */
1860 int ask_naked_reg
= 0;
1863 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1865 char *string
= input_line_pointer
;
1866 int e
= get_symbol_end ();
1868 if (strcmp (string
, "prefix") == 0)
1870 else if (strcmp (string
, "noprefix") == 0)
1873 as_bad (_("bad argument to syntax directive."));
1874 *input_line_pointer
= e
;
1876 demand_empty_rest_of_line ();
1878 intel_syntax
= syntax_flag
;
1880 if (ask_naked_reg
== 0)
1881 allow_naked_reg
= (intel_syntax
1882 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
1884 allow_naked_reg
= (ask_naked_reg
< 0);
1886 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
1887 identifier_chars
['$'] = intel_syntax
? '$' : 0;
1888 register_prefix
= allow_naked_reg
? "" : "%";
1892 set_intel_mnemonic (int mnemonic_flag
)
1894 intel_mnemonic
= mnemonic_flag
;
1898 set_allow_index_reg (int flag
)
1900 allow_index_reg
= flag
;
1904 set_sse_check (int dummy ATTRIBUTE_UNUSED
)
1908 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1910 char *string
= input_line_pointer
;
1911 int e
= get_symbol_end ();
1913 if (strcmp (string
, "none") == 0)
1914 sse_check
= sse_check_none
;
1915 else if (strcmp (string
, "warning") == 0)
1916 sse_check
= sse_check_warning
;
1917 else if (strcmp (string
, "error") == 0)
1918 sse_check
= sse_check_error
;
1920 as_bad (_("bad argument to sse_check directive."));
1921 *input_line_pointer
= e
;
1924 as_bad (_("missing argument for sse_check directive"));
1926 demand_empty_rest_of_line ();
1930 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
1934 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1936 char *string
= input_line_pointer
;
1937 int e
= get_symbol_end ();
1939 i386_cpu_flags flags
;
1941 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
1943 if (strcmp (string
, cpu_arch
[i
].name
) == 0)
1947 cpu_arch_name
= cpu_arch
[i
].name
;
1948 cpu_sub_arch_name
= NULL
;
1949 cpu_arch_flags
= cpu_arch
[i
].flags
;
1950 if (flag_code
== CODE_64BIT
)
1952 cpu_arch_flags
.bitfield
.cpu64
= 1;
1953 cpu_arch_flags
.bitfield
.cpuno64
= 0;
1957 cpu_arch_flags
.bitfield
.cpu64
= 0;
1958 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1960 cpu_arch_isa
= cpu_arch
[i
].type
;
1961 cpu_arch_isa_flags
= cpu_arch
[i
].flags
;
1962 if (!cpu_arch_tune_set
)
1964 cpu_arch_tune
= cpu_arch_isa
;
1965 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
1970 flags
= cpu_flags_or (cpu_arch_flags
,
1972 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
1974 if (cpu_sub_arch_name
)
1976 char *name
= cpu_sub_arch_name
;
1977 cpu_sub_arch_name
= concat (name
,
1979 (const char *) NULL
);
1983 cpu_sub_arch_name
= xstrdup (cpu_arch
[i
].name
);
1984 cpu_arch_flags
= flags
;
1986 *input_line_pointer
= e
;
1987 demand_empty_rest_of_line ();
1991 if (i
>= ARRAY_SIZE (cpu_arch
))
1992 as_bad (_("no such architecture: `%s'"), string
);
1994 *input_line_pointer
= e
;
1997 as_bad (_("missing cpu architecture"));
1999 no_cond_jump_promotion
= 0;
2000 if (*input_line_pointer
== ','
2001 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2003 char *string
= ++input_line_pointer
;
2004 int e
= get_symbol_end ();
2006 if (strcmp (string
, "nojumps") == 0)
2007 no_cond_jump_promotion
= 1;
2008 else if (strcmp (string
, "jumps") == 0)
2011 as_bad (_("no such architecture modifier: `%s'"), string
);
2013 *input_line_pointer
= e
;
2016 demand_empty_rest_of_line ();
2022 if (!strcmp (default_arch
, "x86_64"))
2023 return bfd_mach_x86_64
;
2024 else if (!strcmp (default_arch
, "i386"))
2025 return bfd_mach_i386_i386
;
2027 as_fatal (_("Unknown architecture"));
2033 const char *hash_err
;
2035 /* Initialize op_hash hash table. */
2036 op_hash
= hash_new ();
2039 const template *optab
;
2040 templates
*core_optab
;
2042 /* Setup for loop. */
2044 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2045 core_optab
->start
= optab
;
2050 if (optab
->name
== NULL
2051 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2053 /* different name --> ship out current template list;
2054 add to hash table; & begin anew. */
2055 core_optab
->end
= optab
;
2056 hash_err
= hash_insert (op_hash
,
2058 (void *) core_optab
);
2061 as_fatal (_("Internal Error: Can't hash %s: %s"),
2065 if (optab
->name
== NULL
)
2067 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2068 core_optab
->start
= optab
;
2073 /* Initialize reg_hash hash table. */
2074 reg_hash
= hash_new ();
2076 const reg_entry
*regtab
;
2077 unsigned int regtab_size
= i386_regtab_size
;
2079 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2081 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2083 as_fatal (_("Internal Error: Can't hash %s: %s"),
2089 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2094 for (c
= 0; c
< 256; c
++)
2099 mnemonic_chars
[c
] = c
;
2100 register_chars
[c
] = c
;
2101 operand_chars
[c
] = c
;
2103 else if (ISLOWER (c
))
2105 mnemonic_chars
[c
] = c
;
2106 register_chars
[c
] = c
;
2107 operand_chars
[c
] = c
;
2109 else if (ISUPPER (c
))
2111 mnemonic_chars
[c
] = TOLOWER (c
);
2112 register_chars
[c
] = mnemonic_chars
[c
];
2113 operand_chars
[c
] = c
;
2116 if (ISALPHA (c
) || ISDIGIT (c
))
2117 identifier_chars
[c
] = c
;
2120 identifier_chars
[c
] = c
;
2121 operand_chars
[c
] = c
;
2126 identifier_chars
['@'] = '@';
2129 identifier_chars
['?'] = '?';
2130 operand_chars
['?'] = '?';
2132 digit_chars
['-'] = '-';
2133 mnemonic_chars
['_'] = '_';
2134 mnemonic_chars
['-'] = '-';
2135 mnemonic_chars
['.'] = '.';
2136 identifier_chars
['_'] = '_';
2137 identifier_chars
['.'] = '.';
2139 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2140 operand_chars
[(unsigned char) *p
] = *p
;
2143 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2146 record_alignment (text_section
, 2);
2147 record_alignment (data_section
, 2);
2148 record_alignment (bss_section
, 2);
2152 if (flag_code
== CODE_64BIT
)
2154 x86_dwarf2_return_column
= 16;
2155 x86_cie_data_alignment
= -8;
2159 x86_dwarf2_return_column
= 8;
2160 x86_cie_data_alignment
= -4;
2165 i386_print_statistics (FILE *file
)
2167 hash_print_statistics (file
, "i386 opcode", op_hash
);
2168 hash_print_statistics (file
, "i386 register", reg_hash
);
2173 /* Debugging routines for md_assemble. */
2174 static void pte (template *);
2175 static void pt (i386_operand_type
);
2176 static void pe (expressionS
*);
2177 static void ps (symbolS
*);
2180 pi (char *line
, i386_insn
*x
)
2184 fprintf (stdout
, "%s: template ", line
);
2186 fprintf (stdout
, " address: base %s index %s scale %x\n",
2187 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2188 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2189 x
->log2_scale_factor
);
2190 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2191 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2192 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2193 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2194 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2195 (x
->rex
& REX_W
) != 0,
2196 (x
->rex
& REX_R
) != 0,
2197 (x
->rex
& REX_X
) != 0,
2198 (x
->rex
& REX_B
) != 0);
2199 fprintf (stdout
, " drex: reg %d rex 0x%x\n",
2200 x
->drex
.reg
, x
->drex
.rex
);
2201 for (i
= 0; i
< x
->operands
; i
++)
2203 fprintf (stdout
, " #%d: ", i
+ 1);
2205 fprintf (stdout
, "\n");
2206 if (x
->types
[i
].bitfield
.reg8
2207 || x
->types
[i
].bitfield
.reg16
2208 || x
->types
[i
].bitfield
.reg32
2209 || x
->types
[i
].bitfield
.reg64
2210 || x
->types
[i
].bitfield
.regmmx
2211 || x
->types
[i
].bitfield
.regxmm
2212 || x
->types
[i
].bitfield
.regymm
2213 || x
->types
[i
].bitfield
.sreg2
2214 || x
->types
[i
].bitfield
.sreg3
2215 || x
->types
[i
].bitfield
.control
2216 || x
->types
[i
].bitfield
.debug
2217 || x
->types
[i
].bitfield
.test
)
2218 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
2219 if (operand_type_check (x
->types
[i
], imm
))
2221 if (operand_type_check (x
->types
[i
], disp
))
2222 pe (x
->op
[i
].disps
);
2230 fprintf (stdout
, " %d operands ", t
->operands
);
2231 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2232 if (t
->extension_opcode
!= None
)
2233 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2234 if (t
->opcode_modifier
.d
)
2235 fprintf (stdout
, "D");
2236 if (t
->opcode_modifier
.w
)
2237 fprintf (stdout
, "W");
2238 fprintf (stdout
, "\n");
2239 for (i
= 0; i
< t
->operands
; i
++)
2241 fprintf (stdout
, " #%d type ", i
+ 1);
2242 pt (t
->operand_types
[i
]);
2243 fprintf (stdout
, "\n");
2250 fprintf (stdout
, " operation %d\n", e
->X_op
);
2251 fprintf (stdout
, " add_number %ld (%lx)\n",
2252 (long) e
->X_add_number
, (long) e
->X_add_number
);
2253 if (e
->X_add_symbol
)
2255 fprintf (stdout
, " add_symbol ");
2256 ps (e
->X_add_symbol
);
2257 fprintf (stdout
, "\n");
2261 fprintf (stdout
, " op_symbol ");
2262 ps (e
->X_op_symbol
);
2263 fprintf (stdout
, "\n");
2270 fprintf (stdout
, "%s type %s%s",
2272 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2273 segment_name (S_GET_SEGMENT (s
)));
2276 static struct type_name
2278 i386_operand_type mask
;
2281 const type_names
[] =
2283 { OPERAND_TYPE_REG8
, "r8" },
2284 { OPERAND_TYPE_REG16
, "r16" },
2285 { OPERAND_TYPE_REG32
, "r32" },
2286 { OPERAND_TYPE_REG64
, "r64" },
2287 { OPERAND_TYPE_IMM8
, "i8" },
2288 { OPERAND_TYPE_IMM8
, "i8s" },
2289 { OPERAND_TYPE_IMM16
, "i16" },
2290 { OPERAND_TYPE_IMM32
, "i32" },
2291 { OPERAND_TYPE_IMM32S
, "i32s" },
2292 { OPERAND_TYPE_IMM64
, "i64" },
2293 { OPERAND_TYPE_IMM1
, "i1" },
2294 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2295 { OPERAND_TYPE_DISP8
, "d8" },
2296 { OPERAND_TYPE_DISP16
, "d16" },
2297 { OPERAND_TYPE_DISP32
, "d32" },
2298 { OPERAND_TYPE_DISP32S
, "d32s" },
2299 { OPERAND_TYPE_DISP64
, "d64" },
2300 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2301 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2302 { OPERAND_TYPE_CONTROL
, "control reg" },
2303 { OPERAND_TYPE_TEST
, "test reg" },
2304 { OPERAND_TYPE_DEBUG
, "debug reg" },
2305 { OPERAND_TYPE_FLOATREG
, "FReg" },
2306 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2307 { OPERAND_TYPE_SREG2
, "SReg2" },
2308 { OPERAND_TYPE_SREG3
, "SReg3" },
2309 { OPERAND_TYPE_ACC
, "Acc" },
2310 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2311 { OPERAND_TYPE_REGMMX
, "rMMX" },
2312 { OPERAND_TYPE_REGXMM
, "rXMM" },
2313 { OPERAND_TYPE_ESSEG
, "es" },
2314 { OPERAND_TYPE_VEX_IMM4
, "VEX i4" },
2318 pt (i386_operand_type t
)
2321 i386_operand_type a
;
2323 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2325 a
= operand_type_and (t
, type_names
[j
].mask
);
2326 if (!UINTS_ALL_ZERO (a
))
2327 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2332 #endif /* DEBUG386 */
2334 static bfd_reloc_code_real_type
2335 reloc (unsigned int size
,
2338 bfd_reloc_code_real_type other
)
2340 if (other
!= NO_RELOC
)
2342 reloc_howto_type
*reloc
;
2347 case BFD_RELOC_X86_64_GOT32
:
2348 return BFD_RELOC_X86_64_GOT64
;
2350 case BFD_RELOC_X86_64_PLTOFF64
:
2351 return BFD_RELOC_X86_64_PLTOFF64
;
2353 case BFD_RELOC_X86_64_GOTPC32
:
2354 other
= BFD_RELOC_X86_64_GOTPC64
;
2356 case BFD_RELOC_X86_64_GOTPCREL
:
2357 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2359 case BFD_RELOC_X86_64_TPOFF32
:
2360 other
= BFD_RELOC_X86_64_TPOFF64
;
2362 case BFD_RELOC_X86_64_DTPOFF32
:
2363 other
= BFD_RELOC_X86_64_DTPOFF64
;
2369 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2370 if (size
== 4 && flag_code
!= CODE_64BIT
)
2373 reloc
= bfd_reloc_type_lookup (stdoutput
, other
);
2375 as_bad (_("unknown relocation (%u)"), other
);
2376 else if (size
!= bfd_get_reloc_size (reloc
))
2377 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2378 bfd_get_reloc_size (reloc
),
2380 else if (pcrel
&& !reloc
->pc_relative
)
2381 as_bad (_("non-pc-relative relocation for pc-relative field"));
2382 else if ((reloc
->complain_on_overflow
== complain_overflow_signed
2384 || (reloc
->complain_on_overflow
== complain_overflow_unsigned
2386 as_bad (_("relocated field and relocation type differ in signedness"));
2395 as_bad (_("there are no unsigned pc-relative relocations"));
2398 case 1: return BFD_RELOC_8_PCREL
;
2399 case 2: return BFD_RELOC_16_PCREL
;
2400 case 4: return BFD_RELOC_32_PCREL
;
2401 case 8: return BFD_RELOC_64_PCREL
;
2403 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
2410 case 4: return BFD_RELOC_X86_64_32S
;
2415 case 1: return BFD_RELOC_8
;
2416 case 2: return BFD_RELOC_16
;
2417 case 4: return BFD_RELOC_32
;
2418 case 8: return BFD_RELOC_64
;
2420 as_bad (_("cannot do %s %u byte relocation"),
2421 sign
> 0 ? "signed" : "unsigned", size
);
2425 return BFD_RELOC_NONE
;
2428 /* Here we decide which fixups can be adjusted to make them relative to
2429 the beginning of the section instead of the symbol. Basically we need
2430 to make sure that the dynamic relocations are done correctly, so in
2431 some cases we force the original symbol to be used. */
2434 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
2436 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2440 /* Don't adjust pc-relative references to merge sections in 64-bit
2442 if (use_rela_relocations
2443 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
2447 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2448 and changed later by validate_fix. */
2449 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
2450 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
2453 /* adjust_reloc_syms doesn't know about the GOT. */
2454 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
2455 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
2456 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
2457 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
2458 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
2459 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
2460 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
2461 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
2462 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
2463 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
2464 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
2465 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
2466 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
2467 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
2468 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
2469 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
2470 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
2471 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
2472 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
2473 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
2474 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
2475 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
2476 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
2477 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
2478 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
2479 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
2480 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
2481 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
2488 intel_float_operand (const char *mnemonic
)
2490 /* Note that the value returned is meaningful only for opcodes with (memory)
2491 operands, hence the code here is free to improperly handle opcodes that
2492 have no operands (for better performance and smaller code). */
2494 if (mnemonic
[0] != 'f')
2495 return 0; /* non-math */
2497 switch (mnemonic
[1])
2499 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2500 the fs segment override prefix not currently handled because no
2501 call path can make opcodes without operands get here */
2503 return 2 /* integer op */;
2505 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
2506 return 3; /* fldcw/fldenv */
2509 if (mnemonic
[2] != 'o' /* fnop */)
2510 return 3; /* non-waiting control op */
2513 if (mnemonic
[2] == 's')
2514 return 3; /* frstor/frstpm */
2517 if (mnemonic
[2] == 'a')
2518 return 3; /* fsave */
2519 if (mnemonic
[2] == 't')
2521 switch (mnemonic
[3])
2523 case 'c': /* fstcw */
2524 case 'd': /* fstdw */
2525 case 'e': /* fstenv */
2526 case 's': /* fsts[gw] */
2532 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
2533 return 0; /* fxsave/fxrstor are not really math ops */
2540 /* Build the VEX prefix. */
2543 build_vex_prefix (void)
2545 unsigned int register_specifier
;
2546 unsigned int implied_prefix
;
2547 unsigned int vector_length
;
2549 /* Check register specifier. */
2550 if (i
.vex
.register_specifier
)
2552 register_specifier
= i
.vex
.register_specifier
->reg_num
;
2553 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
2554 register_specifier
+= 8;
2555 register_specifier
= ~register_specifier
& 0xf;
2558 register_specifier
= 0xf;
2560 vector_length
= i
.tm
.opcode_modifier
.vex256
? 1 : 0;
2562 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
2567 case DATA_PREFIX_OPCODE
:
2570 case REPE_PREFIX_OPCODE
:
2573 case REPNE_PREFIX_OPCODE
:
2580 /* Use 2-byte VEX prefix if possible. */
2581 if (i
.tm
.opcode_modifier
.vex0f
2582 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
2584 /* 2-byte VEX prefix. */
2588 i
.vex
.bytes
[0] = 0xc5;
2590 /* Check the REX.R bit. */
2591 r
= (i
.rex
& REX_R
) ? 0 : 1;
2592 i
.vex
.bytes
[1] = (r
<< 7
2593 | register_specifier
<< 3
2594 | vector_length
<< 2
2599 /* 3-byte VEX prefix. */
2602 if (i
.tm
.opcode_modifier
.vex0f
)
2604 else if (i
.tm
.opcode_modifier
.vex0f38
)
2606 else if (i
.tm
.opcode_modifier
.vex0f3a
)
2612 i
.vex
.bytes
[0] = 0xc4;
2614 /* The high 3 bits of the second VEX byte are 1's compliment
2615 of RXB bits from REX. */
2616 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
2618 /* Check the REX.W bit. */
2619 w
= (i
.rex
& REX_W
) ? 1 : 0;
2620 if (i
.tm
.opcode_modifier
.vexw0
|| i
.tm
.opcode_modifier
.vexw1
)
2625 if (i
.tm
.opcode_modifier
.vexw1
)
2629 i
.vex
.bytes
[2] = (w
<< 7
2630 | register_specifier
<< 3
2631 | vector_length
<< 2
2637 process_immext (void)
2641 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
&& i
.operands
> 0)
2643 /* SSE3 Instructions have the fixed operands with an opcode
2644 suffix which is coded in the same place as an 8-bit immediate
2645 field would be. Here we check those operands and remove them
2649 for (x
= 0; x
< i
.operands
; x
++)
2650 if (i
.op
[x
].regs
->reg_num
!= x
)
2651 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
2652 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
2658 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
2659 which is coded in the same place as an 8-bit immediate field
2660 would be. Here we fake an 8-bit immediate operand from the
2661 opcode suffix stored in tm.extension_opcode.
2663 SSE5 and AVX instructions also use this encoding, for some of
2664 3 argument instructions. */
2666 assert (i
.imm_operands
== 0
2668 || (i
.tm
.cpu_flags
.bitfield
.cpusse5
2670 || (i
.tm
.opcode_modifier
.vex
2671 && i
.operands
<= 4)));
2673 exp
= &im_expressions
[i
.imm_operands
++];
2674 i
.op
[i
.operands
].imms
= exp
;
2675 i
.types
[i
.operands
] = imm8
;
2677 exp
->X_op
= O_constant
;
2678 exp
->X_add_number
= i
.tm
.extension_opcode
;
2679 i
.tm
.extension_opcode
= None
;
2682 /* This is the guts of the machine-dependent assembler. LINE points to a
2683 machine dependent instruction. This function is supposed to emit
2684 the frags/bytes it assembles to. */
2687 md_assemble (char *line
)
2690 char mnemonic
[MAX_MNEM_SIZE
];
2692 /* Initialize globals. */
2693 memset (&i
, '\0', sizeof (i
));
2694 for (j
= 0; j
< MAX_OPERANDS
; j
++)
2695 i
.reloc
[j
] = NO_RELOC
;
2696 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
2697 memset (im_expressions
, '\0', sizeof (im_expressions
));
2698 save_stack_p
= save_stack
;
2700 /* First parse an instruction mnemonic & call i386_operand for the operands.
2701 We assume that the scrubber has arranged it so that line[0] is the valid
2702 start of a (possibly prefixed) mnemonic. */
2704 line
= parse_insn (line
, mnemonic
);
2708 line
= parse_operands (line
, mnemonic
);
2712 /* Now we've parsed the mnemonic into a set of templates, and have the
2713 operands at hand. */
2715 /* All intel opcodes have reversed operands except for "bound" and
2716 "enter". We also don't reverse intersegment "jmp" and "call"
2717 instructions with 2 immediate operands so that the immediate segment
2718 precedes the offset, as it does when in AT&T mode. */
2721 && (strcmp (mnemonic
, "bound") != 0)
2722 && (strcmp (mnemonic
, "invlpga") != 0)
2723 && !(operand_type_check (i
.types
[0], imm
)
2724 && operand_type_check (i
.types
[1], imm
)))
2727 /* The order of the immediates should be reversed
2728 for 2 immediates extrq and insertq instructions */
2729 if (i
.imm_operands
== 2
2730 && (strcmp (mnemonic
, "extrq") == 0
2731 || strcmp (mnemonic
, "insertq") == 0))
2732 swap_2_operands (0, 1);
2737 /* Don't optimize displacement for movabs since it only takes 64bit
2740 && (flag_code
!= CODE_64BIT
2741 || strcmp (mnemonic
, "movabs") != 0))
2744 /* Next, we find a template that matches the given insn,
2745 making sure the overlap of the given operands types is consistent
2746 with the template operand types. */
2748 if (!match_template ())
2751 if (sse_check
!= sse_check_none
2752 && !i
.tm
.opcode_modifier
.noavx
2753 && (i
.tm
.cpu_flags
.bitfield
.cpusse
2754 || i
.tm
.cpu_flags
.bitfield
.cpusse2
2755 || i
.tm
.cpu_flags
.bitfield
.cpusse3
2756 || i
.tm
.cpu_flags
.bitfield
.cpussse3
2757 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
2758 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
2760 (sse_check
== sse_check_warning
2762 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
2765 /* Zap movzx and movsx suffix. The suffix has been set from
2766 "word ptr" or "byte ptr" on the source operand in Intel syntax
2767 or extracted from mnemonic in AT&T syntax. But we'll use
2768 the destination register to choose the suffix for encoding. */
2769 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
2771 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
2772 there is no suffix, the default will be byte extension. */
2773 if (i
.reg_operands
!= 2
2776 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
2781 if (i
.tm
.opcode_modifier
.fwait
)
2782 if (!add_prefix (FWAIT_OPCODE
))
2785 /* Check string instruction segment overrides. */
2786 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
2788 if (!check_string ())
2790 i
.disp_operands
= 0;
2793 if (!process_suffix ())
2796 /* Make still unresolved immediate matches conform to size of immediate
2797 given in i.suffix. */
2798 if (!finalize_imm ())
2801 if (i
.types
[0].bitfield
.imm1
)
2802 i
.imm_operands
= 0; /* kludge for shift insns. */
2804 for (j
= 0; j
< 3; j
++)
2805 if (i
.types
[j
].bitfield
.inoutportreg
2806 || i
.types
[j
].bitfield
.shiftcount
2807 || i
.types
[j
].bitfield
.acc
2808 || i
.types
[j
].bitfield
.floatacc
)
2811 /* ImmExt should be processed after SSE2AVX. */
2812 if (!i
.tm
.opcode_modifier
.sse2avx
2813 && i
.tm
.opcode_modifier
.immext
)
2816 /* For insns with operands there are more diddles to do to the opcode. */
2819 if (!process_operands ())
2822 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
2824 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2825 as_warn (_("translating to `%sp'"), i
.tm
.name
);
2828 if (i
.tm
.opcode_modifier
.vex
)
2829 build_vex_prefix ();
2831 /* Handle conversion of 'int $3' --> special int3 insn. */
2832 if (i
.tm
.base_opcode
== INT_OPCODE
&& i
.op
[0].imms
->X_add_number
== 3)
2834 i
.tm
.base_opcode
= INT3_OPCODE
;
2838 if ((i
.tm
.opcode_modifier
.jump
2839 || i
.tm
.opcode_modifier
.jumpbyte
2840 || i
.tm
.opcode_modifier
.jumpdword
)
2841 && i
.op
[0].disps
->X_op
== O_constant
)
2843 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2844 the absolute address given by the constant. Since ix86 jumps and
2845 calls are pc relative, we need to generate a reloc. */
2846 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
2847 i
.op
[0].disps
->X_op
= O_symbol
;
2850 if (i
.tm
.opcode_modifier
.rex64
)
2853 /* For 8 bit registers we need an empty rex prefix. Also if the
2854 instruction already has a prefix, we need to convert old
2855 registers to new ones. */
2857 if ((i
.types
[0].bitfield
.reg8
2858 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
2859 || (i
.types
[1].bitfield
.reg8
2860 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
2861 || ((i
.types
[0].bitfield
.reg8
2862 || i
.types
[1].bitfield
.reg8
)
2867 i
.rex
|= REX_OPCODE
;
2868 for (x
= 0; x
< 2; x
++)
2870 /* Look for 8 bit operand that uses old registers. */
2871 if (i
.types
[x
].bitfield
.reg8
2872 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
2874 /* In case it is "hi" register, give up. */
2875 if (i
.op
[x
].regs
->reg_num
> 3)
2876 as_bad (_("can't encode register '%s%s' in an "
2877 "instruction requiring REX prefix."),
2878 register_prefix
, i
.op
[x
].regs
->reg_name
);
2880 /* Otherwise it is equivalent to the extended register.
2881 Since the encoding doesn't change this is merely
2882 cosmetic cleanup for debug output. */
2884 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
2889 /* If the instruction has the DREX attribute (aka SSE5), don't emit a
2891 if (i
.tm
.opcode_modifier
.drex
|| i
.tm
.opcode_modifier
.drexc
)
2896 else if (i
.rex
!= 0)
2897 add_prefix (REX_OPCODE
| i
.rex
);
2899 /* We are ready to output the insn. */
2904 parse_insn (char *line
, char *mnemonic
)
2907 char *token_start
= l
;
2912 /* Non-zero if we found a prefix only acceptable with string insns. */
2913 const char *expecting_string_instruction
= NULL
;
2918 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
2921 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
2923 as_bad (_("no such instruction: `%s'"), token_start
);
2928 if (!is_space_char (*l
)
2929 && *l
!= END_OF_INSN
2931 || (*l
!= PREFIX_SEPARATOR
2934 as_bad (_("invalid character %s in mnemonic"),
2935 output_invalid (*l
));
2938 if (token_start
== l
)
2940 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
2941 as_bad (_("expecting prefix; got nothing"));
2943 as_bad (_("expecting mnemonic; got nothing"));
2947 /* Look up instruction (or prefix) via hash table. */
2948 current_templates
= hash_find (op_hash
, mnemonic
);
2950 if (*l
!= END_OF_INSN
2951 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
2952 && current_templates
2953 && current_templates
->start
->opcode_modifier
.isprefix
)
2955 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
2957 as_bad ((flag_code
!= CODE_64BIT
2958 ? _("`%s' is only supported in 64-bit mode")
2959 : _("`%s' is not supported in 64-bit mode")),
2960 current_templates
->start
->name
);
2963 /* If we are in 16-bit mode, do not allow addr16 or data16.
2964 Similarly, in 32-bit mode, do not allow addr32 or data32. */
2965 if ((current_templates
->start
->opcode_modifier
.size16
2966 || current_templates
->start
->opcode_modifier
.size32
)
2967 && flag_code
!= CODE_64BIT
2968 && (current_templates
->start
->opcode_modifier
.size32
2969 ^ (flag_code
== CODE_16BIT
)))
2971 as_bad (_("redundant %s prefix"),
2972 current_templates
->start
->name
);
2975 /* Add prefix, checking for repeated prefixes. */
2976 switch (add_prefix (current_templates
->start
->base_opcode
))
2981 expecting_string_instruction
= current_templates
->start
->name
;
2984 /* Skip past PREFIX_SEPARATOR and reset token_start. */
2991 if (!current_templates
)
2993 /* See if we can get a match by trimming off a suffix. */
2996 case WORD_MNEM_SUFFIX
:
2997 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
2998 i
.suffix
= SHORT_MNEM_SUFFIX
;
3000 case BYTE_MNEM_SUFFIX
:
3001 case QWORD_MNEM_SUFFIX
:
3002 i
.suffix
= mnem_p
[-1];
3004 current_templates
= hash_find (op_hash
, mnemonic
);
3006 case SHORT_MNEM_SUFFIX
:
3007 case LONG_MNEM_SUFFIX
:
3010 i
.suffix
= mnem_p
[-1];
3012 current_templates
= hash_find (op_hash
, mnemonic
);
3020 if (intel_float_operand (mnemonic
) == 1)
3021 i
.suffix
= SHORT_MNEM_SUFFIX
;
3023 i
.suffix
= LONG_MNEM_SUFFIX
;
3025 current_templates
= hash_find (op_hash
, mnemonic
);
3029 if (!current_templates
)
3031 as_bad (_("no such instruction: `%s'"), token_start
);
3036 if (current_templates
->start
->opcode_modifier
.jump
3037 || current_templates
->start
->opcode_modifier
.jumpbyte
)
3039 /* Check for a branch hint. We allow ",pt" and ",pn" for
3040 predict taken and predict not taken respectively.
3041 I'm not sure that branch hints actually do anything on loop
3042 and jcxz insns (JumpByte) for current Pentium4 chips. They
3043 may work in the future and it doesn't hurt to accept them
3045 if (l
[0] == ',' && l
[1] == 'p')
3049 if (!add_prefix (DS_PREFIX_OPCODE
))
3053 else if (l
[2] == 'n')
3055 if (!add_prefix (CS_PREFIX_OPCODE
))
3061 /* Any other comma loses. */
3064 as_bad (_("invalid character %s in mnemonic"),
3065 output_invalid (*l
));
3069 /* Check if instruction is supported on specified architecture. */
3071 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3073 supported
|= cpu_flags_match (t
);
3074 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
3078 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
3080 as_bad (flag_code
== CODE_64BIT
3081 ? _("`%s' is not supported in 64-bit mode")
3082 : _("`%s' is only supported in 64-bit mode"),
3083 current_templates
->start
->name
);
3086 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
3088 as_bad (_("`%s' is not supported on `%s%s'"),
3089 current_templates
->start
->name
, cpu_arch_name
,
3090 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
3095 if (!cpu_arch_flags
.bitfield
.cpui386
3096 && (flag_code
!= CODE_16BIT
))
3098 as_warn (_("use .code16 to ensure correct addressing mode"));
3101 /* Check for rep/repne without a string instruction. */
3102 if (expecting_string_instruction
)
3104 static templates override
;
3106 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3107 if (t
->opcode_modifier
.isstring
)
3109 if (t
>= current_templates
->end
)
3111 as_bad (_("expecting string instruction after `%s'"),
3112 expecting_string_instruction
);
3115 for (override
.start
= t
; t
< current_templates
->end
; ++t
)
3116 if (!t
->opcode_modifier
.isstring
)
3119 current_templates
= &override
;
3126 parse_operands (char *l
, const char *mnemonic
)
3130 /* 1 if operand is pending after ','. */
3131 unsigned int expecting_operand
= 0;
3133 /* Non-zero if operand parens not balanced. */
3134 unsigned int paren_not_balanced
;
3136 while (*l
!= END_OF_INSN
)
3138 /* Skip optional white space before operand. */
3139 if (is_space_char (*l
))
3141 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
3143 as_bad (_("invalid character %s before operand %d"),
3144 output_invalid (*l
),
3148 token_start
= l
; /* after white space */
3149 paren_not_balanced
= 0;
3150 while (paren_not_balanced
|| *l
!= ',')
3152 if (*l
== END_OF_INSN
)
3154 if (paren_not_balanced
)
3157 as_bad (_("unbalanced parenthesis in operand %d."),
3160 as_bad (_("unbalanced brackets in operand %d."),
3165 break; /* we are done */
3167 else if (!is_operand_char (*l
) && !is_space_char (*l
))
3169 as_bad (_("invalid character %s in operand %d"),
3170 output_invalid (*l
),
3177 ++paren_not_balanced
;
3179 --paren_not_balanced
;
3184 ++paren_not_balanced
;
3186 --paren_not_balanced
;
3190 if (l
!= token_start
)
3191 { /* Yes, we've read in another operand. */
3192 unsigned int operand_ok
;
3193 this_operand
= i
.operands
++;
3194 i
.types
[this_operand
].bitfield
.unspecified
= 1;
3195 if (i
.operands
> MAX_OPERANDS
)
3197 as_bad (_("spurious operands; (%d operands/instruction max)"),
3201 /* Now parse operand adding info to 'i' as we go along. */
3202 END_STRING_AND_SAVE (l
);
3206 i386_intel_operand (token_start
,
3207 intel_float_operand (mnemonic
));
3209 operand_ok
= i386_att_operand (token_start
);
3211 RESTORE_END_STRING (l
);
3217 if (expecting_operand
)
3219 expecting_operand_after_comma
:
3220 as_bad (_("expecting operand after ','; got nothing"));
3225 as_bad (_("expecting operand before ','; got nothing"));
3230 /* Now *l must be either ',' or END_OF_INSN. */
3233 if (*++l
== END_OF_INSN
)
3235 /* Just skip it, if it's \n complain. */
3236 goto expecting_operand_after_comma
;
3238 expecting_operand
= 1;
3245 swap_2_operands (int xchg1
, int xchg2
)
3247 union i386_op temp_op
;
3248 i386_operand_type temp_type
;
3249 enum bfd_reloc_code_real temp_reloc
;
3251 temp_type
= i
.types
[xchg2
];
3252 i
.types
[xchg2
] = i
.types
[xchg1
];
3253 i
.types
[xchg1
] = temp_type
;
3254 temp_op
= i
.op
[xchg2
];
3255 i
.op
[xchg2
] = i
.op
[xchg1
];
3256 i
.op
[xchg1
] = temp_op
;
3257 temp_reloc
= i
.reloc
[xchg2
];
3258 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
3259 i
.reloc
[xchg1
] = temp_reloc
;
3263 swap_operands (void)
3269 swap_2_operands (1, i
.operands
- 2);
3272 swap_2_operands (0, i
.operands
- 1);
3278 if (i
.mem_operands
== 2)
3280 const seg_entry
*temp_seg
;
3281 temp_seg
= i
.seg
[0];
3282 i
.seg
[0] = i
.seg
[1];
3283 i
.seg
[1] = temp_seg
;
3287 /* Try to ensure constant immediates are represented in the smallest
3292 char guess_suffix
= 0;
3296 guess_suffix
= i
.suffix
;
3297 else if (i
.reg_operands
)
3299 /* Figure out a suffix from the last register operand specified.
3300 We can't do this properly yet, ie. excluding InOutPortReg,
3301 but the following works for instructions with immediates.
3302 In any case, we can't set i.suffix yet. */
3303 for (op
= i
.operands
; --op
>= 0;)
3304 if (i
.types
[op
].bitfield
.reg8
)
3306 guess_suffix
= BYTE_MNEM_SUFFIX
;
3309 else if (i
.types
[op
].bitfield
.reg16
)
3311 guess_suffix
= WORD_MNEM_SUFFIX
;
3314 else if (i
.types
[op
].bitfield
.reg32
)
3316 guess_suffix
= LONG_MNEM_SUFFIX
;
3319 else if (i
.types
[op
].bitfield
.reg64
)
3321 guess_suffix
= QWORD_MNEM_SUFFIX
;
3325 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
3326 guess_suffix
= WORD_MNEM_SUFFIX
;
3328 for (op
= i
.operands
; --op
>= 0;)
3329 if (operand_type_check (i
.types
[op
], imm
))
3331 switch (i
.op
[op
].imms
->X_op
)
3334 /* If a suffix is given, this operand may be shortened. */
3335 switch (guess_suffix
)
3337 case LONG_MNEM_SUFFIX
:
3338 i
.types
[op
].bitfield
.imm32
= 1;
3339 i
.types
[op
].bitfield
.imm64
= 1;
3341 case WORD_MNEM_SUFFIX
:
3342 i
.types
[op
].bitfield
.imm16
= 1;
3343 i
.types
[op
].bitfield
.imm32
= 1;
3344 i
.types
[op
].bitfield
.imm32s
= 1;
3345 i
.types
[op
].bitfield
.imm64
= 1;
3347 case BYTE_MNEM_SUFFIX
:
3348 i
.types
[op
].bitfield
.imm8
= 1;
3349 i
.types
[op
].bitfield
.imm8s
= 1;
3350 i
.types
[op
].bitfield
.imm16
= 1;
3351 i
.types
[op
].bitfield
.imm32
= 1;
3352 i
.types
[op
].bitfield
.imm32s
= 1;
3353 i
.types
[op
].bitfield
.imm64
= 1;
3357 /* If this operand is at most 16 bits, convert it
3358 to a signed 16 bit number before trying to see
3359 whether it will fit in an even smaller size.
3360 This allows a 16-bit operand such as $0xffe0 to
3361 be recognised as within Imm8S range. */
3362 if ((i
.types
[op
].bitfield
.imm16
)
3363 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
3365 i
.op
[op
].imms
->X_add_number
=
3366 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
3368 if ((i
.types
[op
].bitfield
.imm32
)
3369 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
3372 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
3373 ^ ((offsetT
) 1 << 31))
3374 - ((offsetT
) 1 << 31));
3377 = operand_type_or (i
.types
[op
],
3378 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
3380 /* We must avoid matching of Imm32 templates when 64bit
3381 only immediate is available. */
3382 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
3383 i
.types
[op
].bitfield
.imm32
= 0;
3390 /* Symbols and expressions. */
3392 /* Convert symbolic operand to proper sizes for matching, but don't
3393 prevent matching a set of insns that only supports sizes other
3394 than those matching the insn suffix. */
3396 i386_operand_type mask
, allowed
;
3399 operand_type_set (&mask
, 0);
3400 operand_type_set (&allowed
, 0);
3402 for (t
= current_templates
->start
;
3403 t
< current_templates
->end
;
3405 allowed
= operand_type_or (allowed
,
3406 t
->operand_types
[op
]);
3407 switch (guess_suffix
)
3409 case QWORD_MNEM_SUFFIX
:
3410 mask
.bitfield
.imm64
= 1;
3411 mask
.bitfield
.imm32s
= 1;
3413 case LONG_MNEM_SUFFIX
:
3414 mask
.bitfield
.imm32
= 1;
3416 case WORD_MNEM_SUFFIX
:
3417 mask
.bitfield
.imm16
= 1;
3419 case BYTE_MNEM_SUFFIX
:
3420 mask
.bitfield
.imm8
= 1;
3425 allowed
= operand_type_and (mask
, allowed
);
3426 if (!operand_type_all_zero (&allowed
))
3427 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
3434 /* Try to use the smallest displacement type too. */
3436 optimize_disp (void)
3440 for (op
= i
.operands
; --op
>= 0;)
3441 if (operand_type_check (i
.types
[op
], disp
))
3443 if (i
.op
[op
].disps
->X_op
== O_constant
)
3445 offsetT disp
= i
.op
[op
].disps
->X_add_number
;
3447 if (i
.types
[op
].bitfield
.disp16
3448 && (disp
& ~(offsetT
) 0xffff) == 0)
3450 /* If this operand is at most 16 bits, convert
3451 to a signed 16 bit number and don't use 64bit
3453 disp
= (((disp
& 0xffff) ^ 0x8000) - 0x8000);
3454 i
.types
[op
].bitfield
.disp64
= 0;
3456 if (i
.types
[op
].bitfield
.disp32
3457 && (disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
3459 /* If this operand is at most 32 bits, convert
3460 to a signed 32 bit number and don't use 64bit
3462 disp
&= (((offsetT
) 2 << 31) - 1);
3463 disp
= (disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
3464 i
.types
[op
].bitfield
.disp64
= 0;
3466 if (!disp
&& i
.types
[op
].bitfield
.baseindex
)
3468 i
.types
[op
].bitfield
.disp8
= 0;
3469 i
.types
[op
].bitfield
.disp16
= 0;
3470 i
.types
[op
].bitfield
.disp32
= 0;
3471 i
.types
[op
].bitfield
.disp32s
= 0;
3472 i
.types
[op
].bitfield
.disp64
= 0;
3476 else if (flag_code
== CODE_64BIT
)
3478 if (fits_in_signed_long (disp
))
3480 i
.types
[op
].bitfield
.disp64
= 0;
3481 i
.types
[op
].bitfield
.disp32s
= 1;
3483 if (fits_in_unsigned_long (disp
))
3484 i
.types
[op
].bitfield
.disp32
= 1;
3486 if ((i
.types
[op
].bitfield
.disp32
3487 || i
.types
[op
].bitfield
.disp32s
3488 || i
.types
[op
].bitfield
.disp16
)
3489 && fits_in_signed_byte (disp
))
3490 i
.types
[op
].bitfield
.disp8
= 1;
3492 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
3493 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
3495 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
3496 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
3497 i
.types
[op
].bitfield
.disp8
= 0;
3498 i
.types
[op
].bitfield
.disp16
= 0;
3499 i
.types
[op
].bitfield
.disp32
= 0;
3500 i
.types
[op
].bitfield
.disp32s
= 0;
3501 i
.types
[op
].bitfield
.disp64
= 0;
3504 /* We only support 64bit displacement on constants. */
3505 i
.types
[op
].bitfield
.disp64
= 0;
3509 /* Check if operands are valid for the instrucrtion. Update VEX
3513 VEX_check_operands (const template *t
)
3515 if (!t
->opcode_modifier
.vex
)
3518 /* Only check VEX_Imm4, which must be the first operand. */
3519 if (t
->operand_types
[0].bitfield
.vex_imm4
)
3521 if (i
.op
[0].imms
->X_op
!= O_constant
3522 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
3525 /* Turn off Imm8 so that update_imm won't complain. */
3526 i
.types
[0] = vex_imm4
;
3533 match_template (void)
3535 /* Points to template once we've found it. */
3537 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
3538 i386_operand_type overlap4
;
3539 unsigned int found_reverse_match
;
3540 i386_opcode_modifier suffix_check
;
3541 i386_operand_type operand_types
[MAX_OPERANDS
];
3542 int addr_prefix_disp
;
3544 unsigned int found_cpu_match
;
3545 unsigned int check_register
;
3547 #if MAX_OPERANDS != 5
3548 # error "MAX_OPERANDS must be 5."
3551 found_reverse_match
= 0;
3552 addr_prefix_disp
= -1;
3554 memset (&suffix_check
, 0, sizeof (suffix_check
));
3555 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
3556 suffix_check
.no_bsuf
= 1;
3557 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
3558 suffix_check
.no_wsuf
= 1;
3559 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
3560 suffix_check
.no_ssuf
= 1;
3561 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
3562 suffix_check
.no_lsuf
= 1;
3563 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
3564 suffix_check
.no_qsuf
= 1;
3565 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
3566 suffix_check
.no_ldsuf
= 1;
3568 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
3570 addr_prefix_disp
= -1;
3572 /* Must have right number of operands. */
3573 if (i
.operands
!= t
->operands
)
3576 /* Check processor support. */
3577 found_cpu_match
= (cpu_flags_match (t
)
3578 == CPU_FLAGS_PERFECT_MATCH
);
3579 if (!found_cpu_match
)
3582 /* Check old gcc support. */
3583 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
3586 /* Check AT&T mnemonic. */
3587 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
3590 /* Check AT&T syntax Intel syntax. */
3591 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
3592 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
3595 /* Check the suffix, except for some instructions in intel mode. */
3596 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
3597 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
3598 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
3599 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
3600 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
3601 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
3602 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
3605 if (!operand_size_match (t
))
3608 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3609 operand_types
[j
] = t
->operand_types
[j
];
3611 /* In general, don't allow 64-bit operands in 32-bit mode. */
3612 if (i
.suffix
== QWORD_MNEM_SUFFIX
3613 && flag_code
!= CODE_64BIT
3615 ? (!t
->opcode_modifier
.ignoresize
3616 && !intel_float_operand (t
->name
))
3617 : intel_float_operand (t
->name
) != 2)
3618 && ((!operand_types
[0].bitfield
.regmmx
3619 && !operand_types
[0].bitfield
.regxmm
3620 && !operand_types
[0].bitfield
.regymm
)
3621 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
3622 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
3623 && !!operand_types
[t
->operands
> 1].bitfield
.regymm
))
3624 && (t
->base_opcode
!= 0x0fc7
3625 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
3628 /* In general, don't allow 32-bit operands on pre-386. */
3629 else if (i
.suffix
== LONG_MNEM_SUFFIX
3630 && !cpu_arch_flags
.bitfield
.cpui386
3632 ? (!t
->opcode_modifier
.ignoresize
3633 && !intel_float_operand (t
->name
))
3634 : intel_float_operand (t
->name
) != 2)
3635 && ((!operand_types
[0].bitfield
.regmmx
3636 && !operand_types
[0].bitfield
.regxmm
)
3637 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
3638 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
3641 /* Do not verify operands when there are none. */
3645 /* We've found a match; break out of loop. */
3649 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3650 into Disp32/Disp16/Disp32 operand. */
3651 if (i
.prefix
[ADDR_PREFIX
] != 0)
3653 /* There should be only one Disp operand. */
3657 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3659 if (operand_types
[j
].bitfield
.disp16
)
3661 addr_prefix_disp
= j
;
3662 operand_types
[j
].bitfield
.disp32
= 1;
3663 operand_types
[j
].bitfield
.disp16
= 0;
3669 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3671 if (operand_types
[j
].bitfield
.disp32
)
3673 addr_prefix_disp
= j
;
3674 operand_types
[j
].bitfield
.disp32
= 0;
3675 operand_types
[j
].bitfield
.disp16
= 1;
3681 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3683 if (operand_types
[j
].bitfield
.disp64
)
3685 addr_prefix_disp
= j
;
3686 operand_types
[j
].bitfield
.disp64
= 0;
3687 operand_types
[j
].bitfield
.disp32
= 1;
3695 /* We check register size only if size of operands can be
3696 encoded the canonical way. */
3697 check_register
= t
->opcode_modifier
.w
;
3698 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
3699 switch (t
->operands
)
3702 if (!operand_type_match (overlap0
, i
.types
[0]))
3706 /* xchg %eax, %eax is a special case. It is an aliase for nop
3707 only in 32bit mode and we can use opcode 0x90. In 64bit
3708 mode, we can't use 0x90 for xchg %eax, %eax since it should
3709 zero-extend %eax to %rax. */
3710 if (flag_code
== CODE_64BIT
3711 && t
->base_opcode
== 0x90
3712 && operand_type_equal (&i
.types
[0], &acc32
)
3713 && operand_type_equal (&i
.types
[1], &acc32
))
3718 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
3719 if (!operand_type_match (overlap0
, i
.types
[0])
3720 || !operand_type_match (overlap1
, i
.types
[1])
3722 && !operand_type_register_match (overlap0
, i
.types
[0],
3724 overlap1
, i
.types
[1],
3727 /* Check if other direction is valid ... */
3728 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
3731 /* Try reversing direction of operands. */
3732 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
3733 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
3734 if (!operand_type_match (overlap0
, i
.types
[0])
3735 || !operand_type_match (overlap1
, i
.types
[1])
3737 && !operand_type_register_match (overlap0
,
3744 /* Does not match either direction. */
3747 /* found_reverse_match holds which of D or FloatDR
3749 if (t
->opcode_modifier
.d
)
3750 found_reverse_match
= Opcode_D
;
3751 else if (t
->opcode_modifier
.floatd
)
3752 found_reverse_match
= Opcode_FloatD
;
3754 found_reverse_match
= 0;
3755 if (t
->opcode_modifier
.floatr
)
3756 found_reverse_match
|= Opcode_FloatR
;
3760 /* Found a forward 2 operand match here. */
3761 switch (t
->operands
)
3764 overlap4
= operand_type_and (i
.types
[4],
3767 overlap3
= operand_type_and (i
.types
[3],
3770 overlap2
= operand_type_and (i
.types
[2],
3775 switch (t
->operands
)
3778 if (!operand_type_match (overlap4
, i
.types
[4])
3779 || !operand_type_register_match (overlap3
,
3787 if (!operand_type_match (overlap3
, i
.types
[3])
3789 && !operand_type_register_match (overlap2
,
3797 /* Here we make use of the fact that there are no
3798 reverse match 3 operand instructions, and all 3
3799 operand instructions only need to be checked for
3800 register consistency between operands 2 and 3. */
3801 if (!operand_type_match (overlap2
, i
.types
[2])
3803 && !operand_type_register_match (overlap1
,
3813 /* Found either forward/reverse 2, 3 or 4 operand match here:
3814 slip through to break. */
3816 if (!found_cpu_match
)
3818 found_reverse_match
= 0;
3822 /* Check if VEX operands are valid. */
3823 if (VEX_check_operands (t
))
3826 /* We've found a match; break out of loop. */
3830 if (t
== current_templates
->end
)
3832 /* We found no match. */
3834 as_bad (_("ambiguous operand size or operands invalid for `%s'"),
3835 current_templates
->start
->name
);
3837 as_bad (_("suffix or operands invalid for `%s'"),
3838 current_templates
->start
->name
);
3842 if (!quiet_warnings
)
3845 && (i
.types
[0].bitfield
.jumpabsolute
3846 != operand_types
[0].bitfield
.jumpabsolute
))
3848 as_warn (_("indirect %s without `*'"), t
->name
);
3851 if (t
->opcode_modifier
.isprefix
3852 && t
->opcode_modifier
.ignoresize
)
3854 /* Warn them that a data or address size prefix doesn't
3855 affect assembly of the next line of code. */
3856 as_warn (_("stand-alone `%s' prefix"), t
->name
);
3860 /* Copy the template we found. */
3863 if (addr_prefix_disp
!= -1)
3864 i
.tm
.operand_types
[addr_prefix_disp
]
3865 = operand_types
[addr_prefix_disp
];
3867 if (found_reverse_match
)
3869 /* If we found a reverse match we must alter the opcode
3870 direction bit. found_reverse_match holds bits to change
3871 (different for int & float insns). */
3873 i
.tm
.base_opcode
^= found_reverse_match
;
3875 i
.tm
.operand_types
[0] = operand_types
[1];
3876 i
.tm
.operand_types
[1] = operand_types
[0];
3885 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
3886 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
3888 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
3890 as_bad (_("`%s' operand %d must use `%ses' segment"),
3896 /* There's only ever one segment override allowed per instruction.
3897 This instruction possibly has a legal segment override on the
3898 second operand, so copy the segment to where non-string
3899 instructions store it, allowing common code. */
3900 i
.seg
[0] = i
.seg
[1];
3902 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
3904 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
3906 as_bad (_("`%s' operand %d must use `%ses' segment"),
3917 process_suffix (void)
3919 /* If matched instruction specifies an explicit instruction mnemonic
3921 if (i
.tm
.opcode_modifier
.size16
)
3922 i
.suffix
= WORD_MNEM_SUFFIX
;
3923 else if (i
.tm
.opcode_modifier
.size32
)
3924 i
.suffix
= LONG_MNEM_SUFFIX
;
3925 else if (i
.tm
.opcode_modifier
.size64
)
3926 i
.suffix
= QWORD_MNEM_SUFFIX
;
3927 else if (i
.reg_operands
)
3929 /* If there's no instruction mnemonic suffix we try to invent one
3930 based on register operands. */
3933 /* We take i.suffix from the last register operand specified,
3934 Destination register type is more significant than source
3935 register type. crc32 in SSE4.2 prefers source register
3937 if (i
.tm
.base_opcode
== 0xf20f38f1)
3939 if (i
.types
[0].bitfield
.reg16
)
3940 i
.suffix
= WORD_MNEM_SUFFIX
;
3941 else if (i
.types
[0].bitfield
.reg32
)
3942 i
.suffix
= LONG_MNEM_SUFFIX
;
3943 else if (i
.types
[0].bitfield
.reg64
)
3944 i
.suffix
= QWORD_MNEM_SUFFIX
;
3946 else if (i
.tm
.base_opcode
== 0xf20f38f0)
3948 if (i
.types
[0].bitfield
.reg8
)
3949 i
.suffix
= BYTE_MNEM_SUFFIX
;
3956 if (i
.tm
.base_opcode
== 0xf20f38f1
3957 || i
.tm
.base_opcode
== 0xf20f38f0)
3959 /* We have to know the operand size for crc32. */
3960 as_bad (_("ambiguous memory operand size for `%s`"),
3965 for (op
= i
.operands
; --op
>= 0;)
3966 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
3968 if (i
.types
[op
].bitfield
.reg8
)
3970 i
.suffix
= BYTE_MNEM_SUFFIX
;
3973 else if (i
.types
[op
].bitfield
.reg16
)
3975 i
.suffix
= WORD_MNEM_SUFFIX
;
3978 else if (i
.types
[op
].bitfield
.reg32
)
3980 i
.suffix
= LONG_MNEM_SUFFIX
;
3983 else if (i
.types
[op
].bitfield
.reg64
)
3985 i
.suffix
= QWORD_MNEM_SUFFIX
;
3991 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
3993 if (!check_byte_reg ())
3996 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
3998 if (!check_long_reg ())
4001 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4004 && i
.tm
.opcode_modifier
.ignoresize
4005 && i
.tm
.opcode_modifier
.no_qsuf
)
4007 else if (!check_qword_reg ())
4010 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4012 if (!check_word_reg ())
4015 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
4016 || i
.suffix
== YMMWORD_MNEM_SUFFIX
)
4018 /* Skip if the instruction has x/y suffix. match_template
4019 should check if it is a valid suffix. */
4021 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
4022 /* Do nothing if the instruction is going to ignore the prefix. */
4027 else if (i
.tm
.opcode_modifier
.defaultsize
4029 /* exclude fldenv/frstor/fsave/fstenv */
4030 && i
.tm
.opcode_modifier
.no_ssuf
)
4032 i
.suffix
= stackop_size
;
4034 else if (intel_syntax
4036 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
4037 || i
.tm
.opcode_modifier
.jumpbyte
4038 || i
.tm
.opcode_modifier
.jumpintersegment
4039 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
4040 && i
.tm
.extension_opcode
<= 3)))
4045 if (!i
.tm
.opcode_modifier
.no_qsuf
)
4047 i
.suffix
= QWORD_MNEM_SUFFIX
;
4051 if (!i
.tm
.opcode_modifier
.no_lsuf
)
4052 i
.suffix
= LONG_MNEM_SUFFIX
;
4055 if (!i
.tm
.opcode_modifier
.no_wsuf
)
4056 i
.suffix
= WORD_MNEM_SUFFIX
;
4065 if (i
.tm
.opcode_modifier
.w
)
4067 as_bad (_("no instruction mnemonic suffix given and "
4068 "no register operands; can't size instruction"));
4074 unsigned int suffixes
;
4076 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
4077 if (!i
.tm
.opcode_modifier
.no_wsuf
)
4079 if (!i
.tm
.opcode_modifier
.no_lsuf
)
4081 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
4083 if (!i
.tm
.opcode_modifier
.no_ssuf
)
4085 if (!i
.tm
.opcode_modifier
.no_qsuf
)
4088 /* There are more than suffix matches. */
4089 if (i
.tm
.opcode_modifier
.w
4090 || ((suffixes
& (suffixes
- 1))
4091 && !i
.tm
.opcode_modifier
.defaultsize
4092 && !i
.tm
.opcode_modifier
.ignoresize
))
4094 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
4100 /* Change the opcode based on the operand size given by i.suffix;
4101 We don't need to change things for byte insns. */
4104 && i
.suffix
!= BYTE_MNEM_SUFFIX
4105 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
4106 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
)
4108 /* It's not a byte, select word/dword operation. */
4109 if (i
.tm
.opcode_modifier
.w
)
4111 if (i
.tm
.opcode_modifier
.shortform
)
4112 i
.tm
.base_opcode
|= 8;
4114 i
.tm
.base_opcode
|= 1;
4117 /* Now select between word & dword operations via the operand
4118 size prefix, except for instructions that will ignore this
4120 if (i
.tm
.opcode_modifier
.addrprefixop0
)
4122 /* The address size override prefix changes the size of the
4124 if ((flag_code
== CODE_32BIT
4125 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
4126 || (flag_code
!= CODE_32BIT
4127 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
4128 if (!add_prefix (ADDR_PREFIX_OPCODE
))
4131 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
4132 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
4133 && !i
.tm
.opcode_modifier
.ignoresize
4134 && !i
.tm
.opcode_modifier
.floatmf
4135 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
4136 || (flag_code
== CODE_64BIT
4137 && i
.tm
.opcode_modifier
.jumpbyte
)))
4139 unsigned int prefix
= DATA_PREFIX_OPCODE
;
4141 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
4142 prefix
= ADDR_PREFIX_OPCODE
;
4144 if (!add_prefix (prefix
))
4148 /* Set mode64 for an operand. */
4149 if (i
.suffix
== QWORD_MNEM_SUFFIX
4150 && flag_code
== CODE_64BIT
4151 && !i
.tm
.opcode_modifier
.norex64
)
4153 /* Special case for xchg %rax,%rax. It is NOP and doesn't
4154 need rex64. cmpxchg8b is also a special case. */
4155 if (! (i
.operands
== 2
4156 && i
.tm
.base_opcode
== 0x90
4157 && i
.tm
.extension_opcode
== None
4158 && operand_type_equal (&i
.types
[0], &acc64
)
4159 && operand_type_equal (&i
.types
[1], &acc64
))
4160 && ! (i
.operands
== 1
4161 && i
.tm
.base_opcode
== 0xfc7
4162 && i
.tm
.extension_opcode
== 1
4163 && !operand_type_check (i
.types
[0], reg
)
4164 && operand_type_check (i
.types
[0], anymem
)))
4168 /* Size floating point instruction. */
4169 if (i
.suffix
== LONG_MNEM_SUFFIX
)
4170 if (i
.tm
.opcode_modifier
.floatmf
)
4171 i
.tm
.base_opcode
^= 4;
4178 check_byte_reg (void)
4182 for (op
= i
.operands
; --op
>= 0;)
4184 /* If this is an eight bit register, it's OK. If it's the 16 or
4185 32 bit version of an eight bit register, we will just use the
4186 low portion, and that's OK too. */
4187 if (i
.types
[op
].bitfield
.reg8
)
4190 /* Don't generate this warning if not needed. */
4191 if (intel_syntax
&& i
.tm
.opcode_modifier
.byteokintel
)
4194 /* crc32 doesn't generate this warning. */
4195 if (i
.tm
.base_opcode
== 0xf20f38f0)
4198 if ((i
.types
[op
].bitfield
.reg16
4199 || i
.types
[op
].bitfield
.reg32
4200 || i
.types
[op
].bitfield
.reg64
)
4201 && i
.op
[op
].regs
->reg_num
< 4)
4203 /* Prohibit these changes in the 64bit mode, since the
4204 lowering is more complicated. */
4205 if (flag_code
== CODE_64BIT
4206 && !i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4208 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4209 register_prefix
, i
.op
[op
].regs
->reg_name
,
4213 #if REGISTER_WARNINGS
4215 && !i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4216 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4218 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
4219 ? REGNAM_AL
- REGNAM_AX
4220 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
4222 i
.op
[op
].regs
->reg_name
,
4227 /* Any other register is bad. */
4228 if (i
.types
[op
].bitfield
.reg16
4229 || i
.types
[op
].bitfield
.reg32
4230 || i
.types
[op
].bitfield
.reg64
4231 || i
.types
[op
].bitfield
.regmmx
4232 || i
.types
[op
].bitfield
.regxmm
4233 || i
.types
[op
].bitfield
.regymm
4234 || i
.types
[op
].bitfield
.sreg2
4235 || i
.types
[op
].bitfield
.sreg3
4236 || i
.types
[op
].bitfield
.control
4237 || i
.types
[op
].bitfield
.debug
4238 || i
.types
[op
].bitfield
.test
4239 || i
.types
[op
].bitfield
.floatreg
4240 || i
.types
[op
].bitfield
.floatacc
)
4242 as_bad (_("`%s%s' not allowed with `%s%c'"),
4244 i
.op
[op
].regs
->reg_name
,
4254 check_long_reg (void)
4258 for (op
= i
.operands
; --op
>= 0;)
4259 /* Reject eight bit registers, except where the template requires
4260 them. (eg. movzb) */
4261 if (i
.types
[op
].bitfield
.reg8
4262 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4263 || i
.tm
.operand_types
[op
].bitfield
.reg32
4264 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4266 as_bad (_("`%s%s' not allowed with `%s%c'"),
4268 i
.op
[op
].regs
->reg_name
,
4273 /* Warn if the e prefix on a general reg is missing. */
4274 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4275 && i
.types
[op
].bitfield
.reg16
4276 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4277 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4279 /* Prohibit these changes in the 64bit mode, since the
4280 lowering is more complicated. */
4281 if (flag_code
== CODE_64BIT
)
4283 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4284 register_prefix
, i
.op
[op
].regs
->reg_name
,
4288 #if REGISTER_WARNINGS
4290 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4292 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
4294 i
.op
[op
].regs
->reg_name
,
4298 /* Warn if the r prefix on a general reg is missing. */
4299 else if (i
.types
[op
].bitfield
.reg64
4300 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4301 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4304 && i
.tm
.opcode_modifier
.toqword
4305 && !i
.types
[0].bitfield
.regxmm
)
4307 /* Convert to QWORD. We want REX byte. */
4308 i
.suffix
= QWORD_MNEM_SUFFIX
;
4312 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4313 register_prefix
, i
.op
[op
].regs
->reg_name
,
4322 check_qword_reg (void)
4326 for (op
= i
.operands
; --op
>= 0; )
4327 /* Reject eight bit registers, except where the template requires
4328 them. (eg. movzb) */
4329 if (i
.types
[op
].bitfield
.reg8
4330 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4331 || i
.tm
.operand_types
[op
].bitfield
.reg32
4332 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4334 as_bad (_("`%s%s' not allowed with `%s%c'"),
4336 i
.op
[op
].regs
->reg_name
,
4341 /* Warn if the e prefix on a general reg is missing. */
4342 else if ((i
.types
[op
].bitfield
.reg16
4343 || i
.types
[op
].bitfield
.reg32
)
4344 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4345 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4347 /* Prohibit these changes in the 64bit mode, since the
4348 lowering is more complicated. */
4350 && i
.tm
.opcode_modifier
.todword
4351 && !i
.types
[0].bitfield
.regxmm
)
4353 /* Convert to DWORD. We don't want REX byte. */
4354 i
.suffix
= LONG_MNEM_SUFFIX
;
4358 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4359 register_prefix
, i
.op
[op
].regs
->reg_name
,
4368 check_word_reg (void)
4371 for (op
= i
.operands
; --op
>= 0;)
4372 /* Reject eight bit registers, except where the template requires
4373 them. (eg. movzb) */
4374 if (i
.types
[op
].bitfield
.reg8
4375 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4376 || i
.tm
.operand_types
[op
].bitfield
.reg32
4377 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4379 as_bad (_("`%s%s' not allowed with `%s%c'"),
4381 i
.op
[op
].regs
->reg_name
,
4386 /* Warn if the e prefix on a general reg is present. */
4387 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4388 && i
.types
[op
].bitfield
.reg32
4389 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4390 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4392 /* Prohibit these changes in the 64bit mode, since the
4393 lowering is more complicated. */
4394 if (flag_code
== CODE_64BIT
)
4396 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4397 register_prefix
, i
.op
[op
].regs
->reg_name
,
4402 #if REGISTER_WARNINGS
4403 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4405 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
4407 i
.op
[op
].regs
->reg_name
,
4415 update_imm (unsigned int j
)
4417 i386_operand_type overlap
;
4419 overlap
= operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
4420 if ((overlap
.bitfield
.imm8
4421 || overlap
.bitfield
.imm8s
4422 || overlap
.bitfield
.imm16
4423 || overlap
.bitfield
.imm32
4424 || overlap
.bitfield
.imm32s
4425 || overlap
.bitfield
.imm64
)
4426 && !operand_type_equal (&overlap
, &imm8
)
4427 && !operand_type_equal (&overlap
, &imm8s
)
4428 && !operand_type_equal (&overlap
, &imm16
)
4429 && !operand_type_equal (&overlap
, &imm32
)
4430 && !operand_type_equal (&overlap
, &imm32s
)
4431 && !operand_type_equal (&overlap
, &imm64
))
4435 i386_operand_type temp
;
4437 operand_type_set (&temp
, 0);
4438 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4440 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
4441 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
4443 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4444 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
4445 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4447 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
4448 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
4451 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
4454 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
4455 || operand_type_equal (&overlap
, &imm16_32
)
4456 || operand_type_equal (&overlap
, &imm16_32s
))
4458 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4463 if (!operand_type_equal (&overlap
, &imm8
)
4464 && !operand_type_equal (&overlap
, &imm8s
)
4465 && !operand_type_equal (&overlap
, &imm16
)
4466 && !operand_type_equal (&overlap
, &imm32
)
4467 && !operand_type_equal (&overlap
, &imm32s
)
4468 && !operand_type_equal (&overlap
, &imm64
))
4470 as_bad (_("no instruction mnemonic suffix given; "
4471 "can't determine immediate size"));
4475 i
.types
[j
] = overlap
;
4485 for (j
= 0; j
< 2; j
++)
4486 if (update_imm (j
) == 0)
4489 i
.types
[2] = operand_type_and (i
.types
[2], i
.tm
.operand_types
[2]);
4490 assert (operand_type_check (i
.types
[2], imm
) == 0);
4498 i
.drex
.modrm_reg
= 0;
4499 i
.drex
.modrm_regmem
= 0;
4501 /* SSE5 4 operand instructions must have the destination the same as
4502 one of the inputs. Figure out the destination register and cache
4503 it away in the drex field, and remember which fields to use for
4505 if (i
.tm
.opcode_modifier
.drex
4506 && i
.tm
.opcode_modifier
.drexv
4509 i
.tm
.extension_opcode
= None
;
4511 /* Case 1: 4 operand insn, dest = src1, src3 = register. */
4512 if (i
.types
[0].bitfield
.regxmm
!= 0
4513 && i
.types
[1].bitfield
.regxmm
!= 0
4514 && i
.types
[2].bitfield
.regxmm
!= 0
4515 && i
.types
[3].bitfield
.regxmm
!= 0
4516 && i
.op
[0].regs
->reg_num
== i
.op
[3].regs
->reg_num
4517 && i
.op
[0].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4519 /* Clear the arguments that are stored in drex. */
4520 operand_type_set (&i
.types
[0], 0);
4521 operand_type_set (&i
.types
[3], 0);
4522 i
.reg_operands
-= 2;
4524 /* There are two different ways to encode a 4 operand
4525 instruction with all registers that uses OC1 set to
4526 0 or 1. Favor setting OC1 to 0 since this mimics the
4527 actions of other SSE5 assemblers. Use modrm encoding 2
4528 for register/register. Include the high order bit that
4529 is normally stored in the REX byte in the register
4531 i
.tm
.extension_opcode
= DREX_X1_XMEM_X2_X1
;
4532 i
.drex
.modrm_reg
= 2;
4533 i
.drex
.modrm_regmem
= 1;
4534 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4535 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4538 /* Case 2: 4 operand insn, dest = src1, src3 = memory. */
4539 else if (i
.types
[0].bitfield
.regxmm
!= 0
4540 && i
.types
[1].bitfield
.regxmm
!= 0
4541 && (i
.types
[2].bitfield
.regxmm
4542 || operand_type_check (i
.types
[2], anymem
))
4543 && i
.types
[3].bitfield
.regxmm
!= 0
4544 && i
.op
[0].regs
->reg_num
== i
.op
[3].regs
->reg_num
4545 && i
.op
[0].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4547 /* clear the arguments that are stored in drex */
4548 operand_type_set (&i
.types
[0], 0);
4549 operand_type_set (&i
.types
[3], 0);
4550 i
.reg_operands
-= 2;
4552 /* Specify the modrm encoding for memory addressing. Include
4553 the high order bit that is normally stored in the REX byte
4554 in the register field. */
4555 i
.tm
.extension_opcode
= DREX_X1_X2_XMEM_X1
;
4556 i
.drex
.modrm_reg
= 1;
4557 i
.drex
.modrm_regmem
= 2;
4558 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4559 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4562 /* Case 3: 4 operand insn, dest = src1, src2 = memory. */
4563 else if (i
.types
[0].bitfield
.regxmm
!= 0
4564 && operand_type_check (i
.types
[1], anymem
) != 0
4565 && i
.types
[2].bitfield
.regxmm
!= 0
4566 && i
.types
[3].bitfield
.regxmm
!= 0
4567 && i
.op
[0].regs
->reg_num
== i
.op
[3].regs
->reg_num
4568 && i
.op
[0].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4570 /* Clear the arguments that are stored in drex. */
4571 operand_type_set (&i
.types
[0], 0);
4572 operand_type_set (&i
.types
[3], 0);
4573 i
.reg_operands
-= 2;
4575 /* Specify the modrm encoding for memory addressing. Include
4576 the high order bit that is normally stored in the REX byte
4577 in the register field. */
4578 i
.tm
.extension_opcode
= DREX_X1_XMEM_X2_X1
;
4579 i
.drex
.modrm_reg
= 2;
4580 i
.drex
.modrm_regmem
= 1;
4581 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4582 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4585 /* Case 4: 4 operand insn, dest = src3, src2 = register. */
4586 else if (i
.types
[0].bitfield
.regxmm
!= 0
4587 && i
.types
[1].bitfield
.regxmm
!= 0
4588 && i
.types
[2].bitfield
.regxmm
!= 0
4589 && i
.types
[3].bitfield
.regxmm
!= 0
4590 && i
.op
[2].regs
->reg_num
== i
.op
[3].regs
->reg_num
4591 && i
.op
[2].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4593 /* clear the arguments that are stored in drex */
4594 operand_type_set (&i
.types
[2], 0);
4595 operand_type_set (&i
.types
[3], 0);
4596 i
.reg_operands
-= 2;
4598 /* There are two different ways to encode a 4 operand
4599 instruction with all registers that uses OC1 set to
4600 0 or 1. Favor setting OC1 to 0 since this mimics the
4601 actions of other SSE5 assemblers. Use modrm encoding
4602 2 for register/register. Include the high order bit that
4603 is normally stored in the REX byte in the register
4605 i
.tm
.extension_opcode
= DREX_XMEM_X1_X2_X2
;
4606 i
.drex
.modrm_reg
= 1;
4607 i
.drex
.modrm_regmem
= 0;
4609 /* Remember the register, including the upper bits */
4610 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4611 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4614 /* Case 5: 4 operand insn, dest = src3, src2 = memory. */
4615 else if (i
.types
[0].bitfield
.regxmm
!= 0
4616 && (i
.types
[1].bitfield
.regxmm
4617 || operand_type_check (i
.types
[1], anymem
))
4618 && i
.types
[2].bitfield
.regxmm
!= 0
4619 && i
.types
[3].bitfield
.regxmm
!= 0
4620 && i
.op
[2].regs
->reg_num
== i
.op
[3].regs
->reg_num
4621 && i
.op
[2].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4623 /* Clear the arguments that are stored in drex. */
4624 operand_type_set (&i
.types
[2], 0);
4625 operand_type_set (&i
.types
[3], 0);
4626 i
.reg_operands
-= 2;
4628 /* Specify the modrm encoding and remember the register
4629 including the bits normally stored in the REX byte. */
4630 i
.tm
.extension_opcode
= DREX_X1_XMEM_X2_X2
;
4631 i
.drex
.modrm_reg
= 0;
4632 i
.drex
.modrm_regmem
= 1;
4633 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4634 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4637 /* Case 6: 4 operand insn, dest = src3, src1 = memory. */
4638 else if (operand_type_check (i
.types
[0], anymem
) != 0
4639 && i
.types
[1].bitfield
.regxmm
!= 0
4640 && i
.types
[2].bitfield
.regxmm
!= 0
4641 && i
.types
[3].bitfield
.regxmm
!= 0
4642 && i
.op
[2].regs
->reg_num
== i
.op
[3].regs
->reg_num
4643 && i
.op
[2].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4645 /* clear the arguments that are stored in drex */
4646 operand_type_set (&i
.types
[2], 0);
4647 operand_type_set (&i
.types
[3], 0);
4648 i
.reg_operands
-= 2;
4650 /* Specify the modrm encoding and remember the register
4651 including the bits normally stored in the REX byte. */
4652 i
.tm
.extension_opcode
= DREX_XMEM_X1_X2_X2
;
4653 i
.drex
.modrm_reg
= 1;
4654 i
.drex
.modrm_regmem
= 0;
4655 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4656 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4660 as_bad (_("Incorrect operands for the '%s' instruction"),
4664 /* SSE5 instructions with the DREX byte where the only memory operand
4665 is in the 2nd argument, and the first and last xmm register must
4666 match, and is encoded in the DREX byte. */
4667 else if (i
.tm
.opcode_modifier
.drex
4668 && !i
.tm
.opcode_modifier
.drexv
4671 /* Case 1: 4 operand insn, dest = src1, src3 = reg/mem. */
4672 if (i
.types
[0].bitfield
.regxmm
!= 0
4673 && (i
.types
[1].bitfield
.regxmm
4674 || operand_type_check(i
.types
[1], anymem
))
4675 && i
.types
[2].bitfield
.regxmm
!= 0
4676 && i
.types
[3].bitfield
.regxmm
!= 0
4677 && i
.op
[0].regs
->reg_num
== i
.op
[3].regs
->reg_num
4678 && i
.op
[0].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4680 /* clear the arguments that are stored in drex */
4681 operand_type_set (&i
.types
[0], 0);
4682 operand_type_set (&i
.types
[3], 0);
4683 i
.reg_operands
-= 2;
4685 /* Specify the modrm encoding and remember the register
4686 including the high bit normally stored in the REX
4688 i
.drex
.modrm_reg
= 2;
4689 i
.drex
.modrm_regmem
= 1;
4690 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4691 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4695 as_bad (_("Incorrect operands for the '%s' instruction"),
4699 /* SSE5 3 operand instructions that the result is a register, being
4700 either operand can be a memory operand, using OC0 to note which
4701 one is the memory. */
4702 else if (i
.tm
.opcode_modifier
.drex
4703 && i
.tm
.opcode_modifier
.drexv
4706 i
.tm
.extension_opcode
= None
;
4708 /* Case 1: 3 operand insn, src1 = register. */
4709 if (i
.types
[0].bitfield
.regxmm
!= 0
4710 && i
.types
[1].bitfield
.regxmm
!= 0
4711 && i
.types
[2].bitfield
.regxmm
!= 0)
4713 /* Clear the arguments that are stored in drex. */
4714 operand_type_set (&i
.types
[2], 0);
4717 /* Specify the modrm encoding and remember the register
4718 including the high bit normally stored in the REX byte. */
4719 i
.tm
.extension_opcode
= DREX_XMEM_X1_X2
;
4720 i
.drex
.modrm_reg
= 1;
4721 i
.drex
.modrm_regmem
= 0;
4722 i
.drex
.reg
= (i
.op
[2].regs
->reg_num
4723 + ((i
.op
[2].regs
->reg_flags
& RegRex
) ? 8 : 0));
4726 /* Case 2: 3 operand insn, src1 = memory. */
4727 else if (operand_type_check (i
.types
[0], anymem
) != 0
4728 && i
.types
[1].bitfield
.regxmm
!= 0
4729 && i
.types
[2].bitfield
.regxmm
!= 0)
4731 /* Clear the arguments that are stored in drex. */
4732 operand_type_set (&i
.types
[2], 0);
4735 /* Specify the modrm encoding and remember the register
4736 including the high bit normally stored in the REX
4738 i
.tm
.extension_opcode
= DREX_XMEM_X1_X2
;
4739 i
.drex
.modrm_reg
= 1;
4740 i
.drex
.modrm_regmem
= 0;
4741 i
.drex
.reg
= (i
.op
[2].regs
->reg_num
4742 + ((i
.op
[2].regs
->reg_flags
& RegRex
) ? 8 : 0));
4745 /* Case 3: 3 operand insn, src2 = memory. */
4746 else if (i
.types
[0].bitfield
.regxmm
!= 0
4747 && operand_type_check (i
.types
[1], anymem
) != 0
4748 && i
.types
[2].bitfield
.regxmm
!= 0)
4750 /* Clear the arguments that are stored in drex. */
4751 operand_type_set (&i
.types
[2], 0);
4754 /* Specify the modrm encoding and remember the register
4755 including the high bit normally stored in the REX byte. */
4756 i
.tm
.extension_opcode
= DREX_X1_XMEM_X2
;
4757 i
.drex
.modrm_reg
= 0;
4758 i
.drex
.modrm_regmem
= 1;
4759 i
.drex
.reg
= (i
.op
[2].regs
->reg_num
4760 + ((i
.op
[2].regs
->reg_flags
& RegRex
) ? 8 : 0));
4764 as_bad (_("Incorrect operands for the '%s' instruction"),
4768 /* SSE5 4 operand instructions that are the comparison instructions
4769 where the first operand is the immediate value of the comparison
4771 else if (i
.tm
.opcode_modifier
.drexc
!= 0 && i
.operands
== 4)
4773 /* Case 1: 4 operand insn, src1 = reg/memory. */
4774 if (operand_type_check (i
.types
[0], imm
) != 0
4775 && (i
.types
[1].bitfield
.regxmm
4776 || operand_type_check (i
.types
[1], anymem
))
4777 && i
.types
[2].bitfield
.regxmm
!= 0
4778 && i
.types
[3].bitfield
.regxmm
!= 0)
4780 /* clear the arguments that are stored in drex */
4781 operand_type_set (&i
.types
[3], 0);
4784 /* Specify the modrm encoding and remember the register
4785 including the high bit normally stored in the REX byte. */
4786 i
.drex
.modrm_reg
= 2;
4787 i
.drex
.modrm_regmem
= 1;
4788 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4789 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4792 /* Case 2: 3 operand insn with ImmExt that places the
4793 opcode_extension as an immediate argument. This is used for
4794 all of the varients of comparison that supplies the appropriate
4795 value as part of the instruction. */
4796 else if ((i
.types
[0].bitfield
.regxmm
4797 || operand_type_check (i
.types
[0], anymem
))
4798 && i
.types
[1].bitfield
.regxmm
!= 0
4799 && i
.types
[2].bitfield
.regxmm
!= 0
4800 && operand_type_check (i
.types
[3], imm
) != 0)
4802 /* clear the arguments that are stored in drex */
4803 operand_type_set (&i
.types
[2], 0);
4806 /* Specify the modrm encoding and remember the register
4807 including the high bit normally stored in the REX byte. */
4808 i
.drex
.modrm_reg
= 1;
4809 i
.drex
.modrm_regmem
= 0;
4810 i
.drex
.reg
= (i
.op
[2].regs
->reg_num
4811 + ((i
.op
[2].regs
->reg_flags
& RegRex
) ? 8 : 0));
4815 as_bad (_("Incorrect operands for the '%s' instruction"),
4819 else if (i
.tm
.opcode_modifier
.drex
4820 || i
.tm
.opcode_modifier
.drexv
4821 || i
.tm
.opcode_modifier
.drexc
)
4822 as_bad (_("Internal error for the '%s' instruction"), i
.tm
.name
);
4826 bad_implicit_operand (int xmm
)
4828 const char *reg
= xmm
? "xmm0" : "ymm0";
4830 as_bad (_("the last operand of `%s' must be `%s%s'"),
4831 i
.tm
.name
, register_prefix
, reg
);
4833 as_bad (_("the first operand of `%s' must be `%s%s'"),
4834 i
.tm
.name
, register_prefix
, reg
);
4839 process_operands (void)
4841 /* Default segment register this instruction will use for memory
4842 accesses. 0 means unknown. This is only for optimizing out
4843 unnecessary segment overrides. */
4844 const seg_entry
*default_seg
= 0;
4846 /* Handle all of the DREX munging that SSE5 needs. */
4847 if (i
.tm
.opcode_modifier
.drex
4848 || i
.tm
.opcode_modifier
.drexv
4849 || i
.tm
.opcode_modifier
.drexc
)
4852 if (i
.tm
.opcode_modifier
.sse2avx
4853 && (i
.tm
.opcode_modifier
.vexnds
4854 || i
.tm
.opcode_modifier
.vexndd
))
4856 unsigned int dup
= i
.operands
;
4857 unsigned int dest
= dup
- 1;
4860 /* The destination must be an xmm register. */
4861 assert (i
.reg_operands
4862 && MAX_OPERANDS
> dup
4863 && operand_type_equal (&i
.types
[dest
], ®xmm
));
4865 if (i
.tm
.opcode_modifier
.firstxmm0
)
4867 /* The first operand is implicit and must be xmm0. */
4868 assert (operand_type_equal (&i
.types
[0], ®xmm
));
4869 if (i
.op
[0].regs
->reg_num
!= 0)
4870 return bad_implicit_operand (1);
4872 if (i
.tm
.opcode_modifier
.vex3sources
)
4874 /* Keep xmm0 for instructions with VEX prefix and 3
4880 /* We remove the first xmm0 and keep the number of
4881 operands unchanged, which in fact duplicates the
4883 for (j
= 1; j
< i
.operands
; j
++)
4885 i
.op
[j
- 1] = i
.op
[j
];
4886 i
.types
[j
- 1] = i
.types
[j
];
4887 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
4891 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
4893 assert ((MAX_OPERANDS
- 1) > dup
4894 && i
.tm
.opcode_modifier
.vex3sources
);
4896 /* Add the implicit xmm0 for instructions with VEX prefix
4898 for (j
= i
.operands
; j
> 0; j
--)
4900 i
.op
[j
] = i
.op
[j
- 1];
4901 i
.types
[j
] = i
.types
[j
- 1];
4902 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
4905 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
4906 i
.types
[0] = regxmm
;
4907 i
.tm
.operand_types
[0] = regxmm
;
4910 i
.reg_operands
+= 2;
4915 i
.op
[dup
] = i
.op
[dest
];
4916 i
.types
[dup
] = i
.types
[dest
];
4917 i
.tm
.operand_types
[dup
] = i
.tm
.operand_types
[dest
];
4926 i
.op
[dup
] = i
.op
[dest
];
4927 i
.types
[dup
] = i
.types
[dest
];
4928 i
.tm
.operand_types
[dup
] = i
.tm
.operand_types
[dest
];
4931 if (i
.tm
.opcode_modifier
.immext
)
4934 else if (i
.tm
.opcode_modifier
.firstxmm0
)
4938 /* The first operand is implicit and must be xmm0/ymm0. */
4939 assert (i
.reg_operands
4940 && (operand_type_equal (&i
.types
[0], ®xmm
)
4941 || operand_type_equal (&i
.types
[0], ®ymm
)));
4942 if (i
.op
[0].regs
->reg_num
!= 0)
4943 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
4945 for (j
= 1; j
< i
.operands
; j
++)
4947 i
.op
[j
- 1] = i
.op
[j
];
4948 i
.types
[j
- 1] = i
.types
[j
];
4950 /* We need to adjust fields in i.tm since they are used by
4951 build_modrm_byte. */
4952 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
4959 else if (i
.tm
.opcode_modifier
.regkludge
)
4961 /* The imul $imm, %reg instruction is converted into
4962 imul $imm, %reg, %reg, and the clr %reg instruction
4963 is converted into xor %reg, %reg. */
4965 unsigned int first_reg_op
;
4967 if (operand_type_check (i
.types
[0], reg
))
4971 /* Pretend we saw the extra register operand. */
4972 assert (i
.reg_operands
== 1
4973 && i
.op
[first_reg_op
+ 1].regs
== 0);
4974 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
4975 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
4980 if (i
.tm
.opcode_modifier
.shortform
)
4982 if (i
.types
[0].bitfield
.sreg2
4983 || i
.types
[0].bitfield
.sreg3
)
4985 if (i
.tm
.base_opcode
== POP_SEG_SHORT
4986 && i
.op
[0].regs
->reg_num
== 1)
4988 as_bad (_("you can't `pop %scs'"), register_prefix
);
4991 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
4992 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
4997 /* The register or float register operand is in operand
5001 if (i
.types
[0].bitfield
.floatreg
5002 || operand_type_check (i
.types
[0], reg
))
5006 /* Register goes in low 3 bits of opcode. */
5007 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
5008 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5010 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
5012 /* Warn about some common errors, but press on regardless.
5013 The first case can be generated by gcc (<= 2.8.1). */
5014 if (i
.operands
== 2)
5016 /* Reversed arguments on faddp, fsubp, etc. */
5017 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
5018 register_prefix
, i
.op
[1].regs
->reg_name
,
5019 register_prefix
, i
.op
[0].regs
->reg_name
);
5023 /* Extraneous `l' suffix on fp insn. */
5024 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
5025 register_prefix
, i
.op
[0].regs
->reg_name
);
5030 else if (i
.tm
.opcode_modifier
.modrm
)
5032 /* The opcode is completed (modulo i.tm.extension_opcode which
5033 must be put into the modrm byte). Now, we make the modrm and
5034 index base bytes based on all the info we've collected. */
5036 default_seg
= build_modrm_byte ();
5038 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
5042 else if (i
.tm
.opcode_modifier
.isstring
)
5044 /* For the string instructions that allow a segment override
5045 on one of their operands, the default segment is ds. */
5049 if (i
.tm
.base_opcode
== 0x8d /* lea */
5052 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
5054 /* If a segment was explicitly specified, and the specified segment
5055 is not the default, use an opcode prefix to select it. If we
5056 never figured out what the default segment is, then default_seg
5057 will be zero at this point, and the specified segment prefix will
5059 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
5061 if (!add_prefix (i
.seg
[0]->seg_prefix
))
5067 static const seg_entry
*
5068 build_modrm_byte (void)
5070 const seg_entry
*default_seg
= 0;
5071 unsigned int source
, dest
;
5074 /* The first operand of instructions with VEX prefix and 3 sources
5075 must be VEX_Imm4. */
5076 vex_3_sources
= i
.tm
.opcode_modifier
.vex3sources
;
5079 unsigned int nds
, reg
;
5081 if (i
.tm
.opcode_modifier
.veximmext
5082 && i
.tm
.opcode_modifier
.immext
)
5084 dest
= i
.operands
- 2;
5088 dest
= i
.operands
- 1;
5091 /* There are 2 kinds of instructions:
5092 1. 5 operands: one immediate operand and 4 register
5093 operands or 3 register operands plus 1 memory operand.
5094 It must have VexNDS and VexW0 or VexW1. The destination
5095 must be either XMM or YMM register.
5096 2. 4 operands: 4 register operands or 3 register operands
5097 plus 1 memory operand. It must have VexNDS and VexImmExt. */
5098 if (!((i
.reg_operands
== 4
5099 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
5100 && i
.tm
.opcode_modifier
.vexnds
5101 && (operand_type_equal (&i
.tm
.operand_types
[dest
], ®xmm
)
5102 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®ymm
))
5104 && i
.imm_operands
== 1
5105 && i
.types
[0].bitfield
.vex_imm4
5106 && (i
.tm
.opcode_modifier
.vexw0
5107 || i
.tm
.opcode_modifier
.vexw1
))
5109 && (i
.imm_operands
== 0
5110 || (i
.imm_operands
== 1
5111 && i
.tm
.opcode_modifier
.immext
))
5112 && i
.tm
.opcode_modifier
.veximmext
))))
5115 if (i
.imm_operands
== 0)
5117 /* When there is no immediate operand, generate an 8bit
5118 immediate operand to encode the first operand. */
5119 expressionS
*exp
= &im_expressions
[i
.imm_operands
++];
5120 i
.op
[i
.operands
].imms
= exp
;
5121 i
.types
[i
.operands
] = imm8
;
5123 /* If VexW1 is set, the first operand is the source and
5124 the second operand is encoded in the immediate operand. */
5125 if (i
.tm
.opcode_modifier
.vexw1
)
5136 /* FMA swaps REG and NDS. */
5137 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
5145 assert (operand_type_equal (&i
.tm
.operand_types
[reg
], ®xmm
)
5146 || operand_type_equal (&i
.tm
.operand_types
[reg
],
5148 exp
->X_op
= O_constant
;
5150 = ((i
.op
[reg
].regs
->reg_num
5151 + ((i
.op
[reg
].regs
->reg_flags
& RegRex
) ? 8 : 0)) << 4);
5157 if (i
.tm
.opcode_modifier
.vexw0
)
5159 /* If VexW0 is set, the third operand is the source and
5160 the second operand is encoded in the immediate
5167 /* VexW1 is set, the second operand is the source and
5168 the third operand is encoded in the immediate
5174 if (i
.tm
.opcode_modifier
.immext
)
5176 /* When ImmExt is set, the immdiate byte is the last
5178 imm
= i
.operands
- 1;
5186 /* Turn on Imm8 so that output_imm will generate it. */
5187 i
.types
[imm
].bitfield
.imm8
= 1;
5190 assert (operand_type_equal (&i
.tm
.operand_types
[reg
], ®xmm
)
5191 || operand_type_equal (&i
.tm
.operand_types
[reg
],
5193 i
.op
[imm
].imms
->X_add_number
5194 |= ((i
.op
[reg
].regs
->reg_num
5195 + ((i
.op
[reg
].regs
->reg_flags
& RegRex
) ? 8 : 0)) << 4);
5198 assert (operand_type_equal (&i
.tm
.operand_types
[nds
], ®xmm
)
5199 || operand_type_equal (&i
.tm
.operand_types
[nds
], ®ymm
));
5200 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
5206 /* SSE5 4 operand instructions are encoded in such a way that one of
5207 the inputs must match the destination register. Process_drex hides
5208 the 3rd argument in the drex field, so that by the time we get
5209 here, it looks to GAS as if this is a 2 operand instruction. */
5210 if ((i
.tm
.opcode_modifier
.drex
5211 || i
.tm
.opcode_modifier
.drexv
5212 || i
.tm
.opcode_modifier
.drexc
)
5213 && i
.reg_operands
== 2)
5215 const reg_entry
*reg
= i
.op
[i
.drex
.modrm_reg
].regs
;
5216 const reg_entry
*regmem
= i
.op
[i
.drex
.modrm_regmem
].regs
;
5218 i
.rm
.reg
= reg
->reg_num
;
5219 i
.rm
.regmem
= regmem
->reg_num
;
5221 if ((reg
->reg_flags
& RegRex
) != 0)
5223 if ((regmem
->reg_flags
& RegRex
) != 0)
5227 /* i.reg_operands MUST be the number of real register operands;
5228 implicit registers do not count. If there are 3 register
5229 operands, it must be a instruction with VexNDS. For a
5230 instruction with VexNDD, the destination register is encoded
5231 in VEX prefix. If there are 4 register operands, it must be
5232 a instruction with VEX prefix and 3 sources. */
5233 else if (i
.mem_operands
== 0
5234 && ((i
.reg_operands
== 2
5235 && !i
.tm
.opcode_modifier
.vexndd
)
5236 || (i
.reg_operands
== 3
5237 && i
.tm
.opcode_modifier
.vexnds
)
5238 || (i
.reg_operands
== 4 && vex_3_sources
)))
5246 /* When there are 3 operands, one of them may be immediate,
5247 which may be the first or the last operand. Otherwise,
5248 the first operand must be shift count register (cl) or it
5249 is an instruction with VexNDS. */
5250 assert (i
.imm_operands
== 1
5251 || (i
.imm_operands
== 0
5252 && (i
.tm
.opcode_modifier
.vexnds
5253 || i
.types
[0].bitfield
.shiftcount
)));
5254 if (operand_type_check (i
.types
[0], imm
)
5255 || i
.types
[0].bitfield
.shiftcount
)
5261 /* When there are 4 operands, the first two must be 8bit
5262 immediate operands. The source operand will be the 3rd
5265 For instructions with VexNDS, if the first operand
5266 an imm8, the source operand is the 2nd one. If the last
5267 operand is imm8, the source operand is the first one. */
5268 assert ((i
.imm_operands
== 2
5269 && i
.types
[0].bitfield
.imm8
5270 && i
.types
[1].bitfield
.imm8
)
5271 || (i
.tm
.opcode_modifier
.vexnds
5272 && i
.imm_operands
== 1
5273 && (i
.types
[0].bitfield
.imm8
5274 || i
.types
[i
.operands
- 1].bitfield
.imm8
)));
5275 if (i
.tm
.opcode_modifier
.vexnds
)
5277 if (i
.types
[0].bitfield
.imm8
)
5295 if (i
.tm
.opcode_modifier
.vexnds
)
5297 /* For instructions with VexNDS, the register-only
5298 source operand must be XMM or YMM register. It is
5299 encoded in VEX prefix. */
5300 if ((dest
+ 1) >= i
.operands
5301 || (!operand_type_equal (&i
.tm
.operand_types
[dest
],
5303 && !operand_type_equal (&i
.tm
.operand_types
[dest
],
5306 i
.vex
.register_specifier
= i
.op
[dest
].regs
;
5312 /* One of the register operands will be encoded in the i.tm.reg
5313 field, the other in the combined i.tm.mode and i.tm.regmem
5314 fields. If no form of this instruction supports a memory
5315 destination operand, then we assume the source operand may
5316 sometimes be a memory operand and so we need to store the
5317 destination in the i.rm.reg field. */
5318 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
5319 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
5321 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
5322 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
5323 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
5325 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
5330 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
5331 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
5332 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
5334 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
5337 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
5339 if (!i
.types
[0].bitfield
.control
5340 && !i
.types
[1].bitfield
.control
)
5342 i
.rex
&= ~(REX_R
| REX_B
);
5343 add_prefix (LOCK_PREFIX_OPCODE
);
5347 { /* If it's not 2 reg operands... */
5352 unsigned int fake_zero_displacement
= 0;
5355 /* This has been precalculated for SSE5 instructions
5356 that have a DREX field earlier in process_drex. */
5357 if (i
.tm
.opcode_modifier
.drex
5358 || i
.tm
.opcode_modifier
.drexv
5359 || i
.tm
.opcode_modifier
.drexc
)
5360 op
= i
.drex
.modrm_regmem
;
5363 for (op
= 0; op
< i
.operands
; op
++)
5364 if (operand_type_check (i
.types
[op
], anymem
))
5366 assert (op
< i
.operands
);
5371 if (i
.base_reg
== 0)
5374 if (!i
.disp_operands
)
5375 fake_zero_displacement
= 1;
5376 if (i
.index_reg
== 0)
5378 /* Operand is just <disp> */
5379 if (flag_code
== CODE_64BIT
)
5381 /* 64bit mode overwrites the 32bit absolute
5382 addressing by RIP relative addressing and
5383 absolute addressing is encoded by one of the
5384 redundant SIB forms. */
5385 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5386 i
.sib
.base
= NO_BASE_REGISTER
;
5387 i
.sib
.index
= NO_INDEX_REGISTER
;
5388 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
5389 ? disp32s
: disp32
);
5391 else if ((flag_code
== CODE_16BIT
)
5392 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
5394 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
5395 i
.types
[op
] = disp16
;
5399 i
.rm
.regmem
= NO_BASE_REGISTER
;
5400 i
.types
[op
] = disp32
;
5403 else /* !i.base_reg && i.index_reg */
5405 if (i
.index_reg
->reg_num
== RegEiz
5406 || i
.index_reg
->reg_num
== RegRiz
)
5407 i
.sib
.index
= NO_INDEX_REGISTER
;
5409 i
.sib
.index
= i
.index_reg
->reg_num
;
5410 i
.sib
.base
= NO_BASE_REGISTER
;
5411 i
.sib
.scale
= i
.log2_scale_factor
;
5412 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5413 i
.types
[op
].bitfield
.disp8
= 0;
5414 i
.types
[op
].bitfield
.disp16
= 0;
5415 i
.types
[op
].bitfield
.disp64
= 0;
5416 if (flag_code
!= CODE_64BIT
)
5418 /* Must be 32 bit */
5419 i
.types
[op
].bitfield
.disp32
= 1;
5420 i
.types
[op
].bitfield
.disp32s
= 0;
5424 i
.types
[op
].bitfield
.disp32
= 0;
5425 i
.types
[op
].bitfield
.disp32s
= 1;
5427 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5431 /* RIP addressing for 64bit mode. */
5432 else if (i
.base_reg
->reg_num
== RegRip
||
5433 i
.base_reg
->reg_num
== RegEip
)
5435 i
.rm
.regmem
= NO_BASE_REGISTER
;
5436 i
.types
[op
].bitfield
.disp8
= 0;
5437 i
.types
[op
].bitfield
.disp16
= 0;
5438 i
.types
[op
].bitfield
.disp32
= 0;
5439 i
.types
[op
].bitfield
.disp32s
= 1;
5440 i
.types
[op
].bitfield
.disp64
= 0;
5441 i
.flags
[op
] |= Operand_PCrel
;
5442 if (! i
.disp_operands
)
5443 fake_zero_displacement
= 1;
5445 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
5447 switch (i
.base_reg
->reg_num
)
5450 if (i
.index_reg
== 0)
5452 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
5453 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
5457 if (i
.index_reg
== 0)
5460 if (operand_type_check (i
.types
[op
], disp
) == 0)
5462 /* fake (%bp) into 0(%bp) */
5463 i
.types
[op
].bitfield
.disp8
= 1;
5464 fake_zero_displacement
= 1;
5467 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
5468 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
5470 default: /* (%si) -> 4 or (%di) -> 5 */
5471 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
5473 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5475 else /* i.base_reg and 32/64 bit mode */
5477 if (flag_code
== CODE_64BIT
5478 && operand_type_check (i
.types
[op
], disp
))
5480 i386_operand_type temp
;
5481 operand_type_set (&temp
, 0);
5482 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
5484 if (i
.prefix
[ADDR_PREFIX
] == 0)
5485 i
.types
[op
].bitfield
.disp32s
= 1;
5487 i
.types
[op
].bitfield
.disp32
= 1;
5490 i
.rm
.regmem
= i
.base_reg
->reg_num
;
5491 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
5493 i
.sib
.base
= i
.base_reg
->reg_num
;
5494 /* x86-64 ignores REX prefix bit here to avoid decoder
5496 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
5499 if (i
.disp_operands
== 0)
5501 fake_zero_displacement
= 1;
5502 i
.types
[op
].bitfield
.disp8
= 1;
5505 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
5509 i
.sib
.scale
= i
.log2_scale_factor
;
5510 if (i
.index_reg
== 0)
5512 /* <disp>(%esp) becomes two byte modrm with no index
5513 register. We've already stored the code for esp
5514 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5515 Any base register besides %esp will not use the
5516 extra modrm byte. */
5517 i
.sib
.index
= NO_INDEX_REGISTER
;
5521 if (i
.index_reg
->reg_num
== RegEiz
5522 || i
.index_reg
->reg_num
== RegRiz
)
5523 i
.sib
.index
= NO_INDEX_REGISTER
;
5525 i
.sib
.index
= i
.index_reg
->reg_num
;
5526 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5527 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5532 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5533 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
5536 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5539 if (fake_zero_displacement
)
5541 /* Fakes a zero displacement assuming that i.types[op]
5542 holds the correct displacement size. */
5545 assert (i
.op
[op
].disps
== 0);
5546 exp
= &disp_expressions
[i
.disp_operands
++];
5547 i
.op
[op
].disps
= exp
;
5548 exp
->X_op
= O_constant
;
5549 exp
->X_add_number
= 0;
5550 exp
->X_add_symbol
= (symbolS
*) 0;
5551 exp
->X_op_symbol
= (symbolS
*) 0;
5559 /* Fill in i.rm.reg or i.rm.regmem field with register operand
5560 (if any) based on i.tm.extension_opcode. Again, we must be
5561 careful to make sure that segment/control/debug/test/MMX
5562 registers are coded into the i.rm.reg field. */
5567 /* This has been precalculated for SSE5 instructions
5568 that have a DREX field earlier in process_drex. */
5569 if (i
.tm
.opcode_modifier
.drex
5570 || i
.tm
.opcode_modifier
.drexv
5571 || i
.tm
.opcode_modifier
.drexc
)
5573 op
= i
.drex
.modrm_reg
;
5574 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
5575 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5580 unsigned int vex_reg
= ~0;
5582 for (op
= 0; op
< i
.operands
; op
++)
5583 if (i
.types
[op
].bitfield
.reg8
5584 || i
.types
[op
].bitfield
.reg16
5585 || i
.types
[op
].bitfield
.reg32
5586 || i
.types
[op
].bitfield
.reg64
5587 || i
.types
[op
].bitfield
.regmmx
5588 || i
.types
[op
].bitfield
.regxmm
5589 || i
.types
[op
].bitfield
.regymm
5590 || i
.types
[op
].bitfield
.sreg2
5591 || i
.types
[op
].bitfield
.sreg3
5592 || i
.types
[op
].bitfield
.control
5593 || i
.types
[op
].bitfield
.debug
5594 || i
.types
[op
].bitfield
.test
)
5599 else if (i
.tm
.opcode_modifier
.vexnds
)
5601 /* For instructions with VexNDS, the register-only
5602 source operand is encoded in VEX prefix. */
5603 assert (mem
!= (unsigned int) ~0);
5608 assert (op
< i
.operands
);
5613 assert (vex_reg
< i
.operands
);
5616 else if (i
.tm
.opcode_modifier
.vexndd
)
5618 /* For instructions with VexNDD, there should be
5619 no memory operand and the register destination
5620 is encoded in VEX prefix. */
5621 assert (i
.mem_operands
== 0
5622 && (op
+ 2) == i
.operands
);
5626 assert (op
< i
.operands
);
5628 if (vex_reg
!= (unsigned int) ~0)
5630 assert (i
.reg_operands
== 2);
5632 if (!operand_type_equal (&i
.tm
.operand_types
[vex_reg
],
5634 && !operand_type_equal (&i
.tm
.operand_types
[vex_reg
],
5637 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
5640 /* If there is an extension opcode to put here, the
5641 register number must be put into the regmem field. */
5642 if (i
.tm
.extension_opcode
!= None
)
5644 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
5645 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5650 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
5651 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5656 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
5657 must set it to 3 to indicate this is a register operand
5658 in the regmem field. */
5659 if (!i
.mem_operands
)
5663 /* Fill in i.rm.reg field with extension opcode (if any). */
5664 if (i
.tm
.extension_opcode
!= None
5665 && !(i
.tm
.opcode_modifier
.drex
5666 || i
.tm
.opcode_modifier
.drexv
5667 || i
.tm
.opcode_modifier
.drexc
))
5668 i
.rm
.reg
= i
.tm
.extension_opcode
;
5674 output_branch (void)
5679 relax_substateT subtype
;
5684 if (flag_code
== CODE_16BIT
)
5688 if (i
.prefix
[DATA_PREFIX
] != 0)
5694 /* Pentium4 branch hints. */
5695 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
5696 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
5701 if (i
.prefix
[REX_PREFIX
] != 0)
5707 if (i
.prefixes
!= 0 && !intel_syntax
)
5708 as_warn (_("skipping prefixes on this instruction"));
5710 /* It's always a symbol; End frag & setup for relax.
5711 Make sure there is enough room in this frag for the largest
5712 instruction we may generate in md_convert_frag. This is 2
5713 bytes for the opcode and room for the prefix and largest
5715 frag_grow (prefix
+ 2 + 4);
5716 /* Prefix and 1 opcode byte go in fr_fix. */
5717 p
= frag_more (prefix
+ 1);
5718 if (i
.prefix
[DATA_PREFIX
] != 0)
5719 *p
++ = DATA_PREFIX_OPCODE
;
5720 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
5721 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
5722 *p
++ = i
.prefix
[SEG_PREFIX
];
5723 if (i
.prefix
[REX_PREFIX
] != 0)
5724 *p
++ = i
.prefix
[REX_PREFIX
];
5725 *p
= i
.tm
.base_opcode
;
5727 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
5728 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
);
5729 else if (cpu_arch_flags
.bitfield
.cpui386
)
5730 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, SMALL
);
5732 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, SMALL
);
5735 sym
= i
.op
[0].disps
->X_add_symbol
;
5736 off
= i
.op
[0].disps
->X_add_number
;
5738 if (i
.op
[0].disps
->X_op
!= O_constant
5739 && i
.op
[0].disps
->X_op
!= O_symbol
)
5741 /* Handle complex expressions. */
5742 sym
= make_expr_symbol (i
.op
[0].disps
);
5746 /* 1 possible extra opcode + 4 byte displacement go in var part.
5747 Pass reloc in fr_var. */
5748 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
5758 if (i
.tm
.opcode_modifier
.jumpbyte
)
5760 /* This is a loop or jecxz type instruction. */
5762 if (i
.prefix
[ADDR_PREFIX
] != 0)
5764 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
5767 /* Pentium4 branch hints. */
5768 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
5769 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
5771 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
5780 if (flag_code
== CODE_16BIT
)
5783 if (i
.prefix
[DATA_PREFIX
] != 0)
5785 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
5795 if (i
.prefix
[REX_PREFIX
] != 0)
5797 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
5801 if (i
.prefixes
!= 0 && !intel_syntax
)
5802 as_warn (_("skipping prefixes on this instruction"));
5804 p
= frag_more (1 + size
);
5805 *p
++ = i
.tm
.base_opcode
;
5807 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5808 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
5810 /* All jumps handled here are signed, but don't use a signed limit
5811 check for 32 and 16 bit jumps as we want to allow wrap around at
5812 4G and 64k respectively. */
5814 fixP
->fx_signed
= 1;
5818 output_interseg_jump (void)
5826 if (flag_code
== CODE_16BIT
)
5830 if (i
.prefix
[DATA_PREFIX
] != 0)
5836 if (i
.prefix
[REX_PREFIX
] != 0)
5846 if (i
.prefixes
!= 0 && !intel_syntax
)
5847 as_warn (_("skipping prefixes on this instruction"));
5849 /* 1 opcode; 2 segment; offset */
5850 p
= frag_more (prefix
+ 1 + 2 + size
);
5852 if (i
.prefix
[DATA_PREFIX
] != 0)
5853 *p
++ = DATA_PREFIX_OPCODE
;
5855 if (i
.prefix
[REX_PREFIX
] != 0)
5856 *p
++ = i
.prefix
[REX_PREFIX
];
5858 *p
++ = i
.tm
.base_opcode
;
5859 if (i
.op
[1].imms
->X_op
== O_constant
)
5861 offsetT n
= i
.op
[1].imms
->X_add_number
;
5864 && !fits_in_unsigned_word (n
)
5865 && !fits_in_signed_word (n
))
5867 as_bad (_("16-bit jump out of range"));
5870 md_number_to_chars (p
, n
, size
);
5873 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5874 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
5875 if (i
.op
[0].imms
->X_op
!= O_constant
)
5876 as_bad (_("can't handle non absolute segment in `%s'"),
5878 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
5884 fragS
*insn_start_frag
;
5885 offsetT insn_start_off
;
5887 /* Tie dwarf2 debug info to the address at the start of the insn.
5888 We can't do this after the insn has been output as the current
5889 frag may have been closed off. eg. by frag_var. */
5890 dwarf2_emit_insn (0);
5892 insn_start_frag
= frag_now
;
5893 insn_start_off
= frag_now_fix ();
5896 if (i
.tm
.opcode_modifier
.jump
)
5898 else if (i
.tm
.opcode_modifier
.jumpbyte
5899 || i
.tm
.opcode_modifier
.jumpdword
)
5901 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
5902 output_interseg_jump ();
5905 /* Output normal instructions here. */
5909 unsigned int prefix
;
5911 /* Since the VEX prefix contains the implicit prefix, we don't
5912 need the explicit prefix. */
5913 if (!i
.tm
.opcode_modifier
.vex
)
5915 switch (i
.tm
.opcode_length
)
5918 if (i
.tm
.base_opcode
& 0xff000000)
5920 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
5925 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
5927 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
5928 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
5931 if (prefix
!= REPE_PREFIX_OPCODE
5932 || (i
.prefix
[LOCKREP_PREFIX
]
5933 != REPE_PREFIX_OPCODE
))
5934 add_prefix (prefix
);
5937 add_prefix (prefix
);
5946 /* The prefix bytes. */
5947 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
5949 FRAG_APPEND_1_CHAR (*q
);
5952 if (i
.tm
.opcode_modifier
.vex
)
5954 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
5959 /* REX byte is encoded in VEX prefix. */
5963 FRAG_APPEND_1_CHAR (*q
);
5966 /* There should be no other prefixes for instructions
5971 /* Now the VEX prefix. */
5972 p
= frag_more (i
.vex
.length
);
5973 for (j
= 0; j
< i
.vex
.length
; j
++)
5974 p
[j
] = i
.vex
.bytes
[j
];
5977 /* Now the opcode; be careful about word order here! */
5978 if (i
.tm
.opcode_length
== 1)
5980 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
5984 switch (i
.tm
.opcode_length
)
5988 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
5998 /* Put out high byte first: can't use md_number_to_chars! */
5999 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
6000 *p
= i
.tm
.base_opcode
& 0xff;
6002 /* On SSE5, encode the OC1 bit in the DREX field if this
6003 encoding has multiple formats. */
6004 if (i
.tm
.opcode_modifier
.drex
6005 && i
.tm
.opcode_modifier
.drexv
6006 && DREX_OC1 (i
.tm
.extension_opcode
))
6007 *p
|= DREX_OC1_MASK
;
6010 /* Now the modrm byte and sib byte (if present). */
6011 if (i
.tm
.opcode_modifier
.modrm
)
6013 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
6016 /* If i.rm.regmem == ESP (4)
6017 && i.rm.mode != (Register mode)
6019 ==> need second modrm byte. */
6020 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
6022 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
6023 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
6025 | i
.sib
.scale
<< 6));
6028 /* Write the DREX byte if needed. */
6029 if (i
.tm
.opcode_modifier
.drex
|| i
.tm
.opcode_modifier
.drexc
)
6032 *p
= (((i
.drex
.reg
& 0xf) << 4) | (i
.drex
.rex
& 0x7));
6034 /* Encode the OC0 bit if this encoding has multiple
6036 if ((i
.tm
.opcode_modifier
.drex
6037 || i
.tm
.opcode_modifier
.drexv
)
6038 && DREX_OC0 (i
.tm
.extension_opcode
))
6039 *p
|= DREX_OC0_MASK
;
6042 if (i
.disp_operands
)
6043 output_disp (insn_start_frag
, insn_start_off
);
6046 output_imm (insn_start_frag
, insn_start_off
);
6052 pi ("" /*line*/, &i
);
6054 #endif /* DEBUG386 */
6057 /* Return the size of the displacement operand N. */
6060 disp_size (unsigned int n
)
6063 if (i
.types
[n
].bitfield
.disp64
)
6065 else if (i
.types
[n
].bitfield
.disp8
)
6067 else if (i
.types
[n
].bitfield
.disp16
)
6072 /* Return the size of the immediate operand N. */
6075 imm_size (unsigned int n
)
6078 if (i
.types
[n
].bitfield
.imm64
)
6080 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
6082 else if (i
.types
[n
].bitfield
.imm16
)
6088 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
6093 for (n
= 0; n
< i
.operands
; n
++)
6095 if (operand_type_check (i
.types
[n
], disp
))
6097 if (i
.op
[n
].disps
->X_op
== O_constant
)
6099 int size
= disp_size (n
);
6102 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
6104 p
= frag_more (size
);
6105 md_number_to_chars (p
, val
, size
);
6109 enum bfd_reloc_code_real reloc_type
;
6110 int size
= disp_size (n
);
6111 int sign
= i
.types
[n
].bitfield
.disp32s
;
6112 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
6114 /* We can't have 8 bit displacement here. */
6115 assert (!i
.types
[n
].bitfield
.disp8
);
6117 /* The PC relative address is computed relative
6118 to the instruction boundary, so in case immediate
6119 fields follows, we need to adjust the value. */
6120 if (pcrel
&& i
.imm_operands
)
6125 for (n1
= 0; n1
< i
.operands
; n1
++)
6126 if (operand_type_check (i
.types
[n1
], imm
))
6128 /* Only one immediate is allowed for PC
6129 relative address. */
6132 i
.op
[n
].disps
->X_add_number
-= sz
;
6134 /* We should find the immediate. */
6138 p
= frag_more (size
);
6139 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
6141 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
6142 && (((reloc_type
== BFD_RELOC_32
6143 || reloc_type
== BFD_RELOC_X86_64_32S
6144 || (reloc_type
== BFD_RELOC_64
6146 && (i
.op
[n
].disps
->X_op
== O_symbol
6147 || (i
.op
[n
].disps
->X_op
== O_add
6148 && ((symbol_get_value_expression
6149 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
6151 || reloc_type
== BFD_RELOC_32_PCREL
))
6155 if (insn_start_frag
== frag_now
)
6156 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
6161 add
= insn_start_frag
->fr_fix
- insn_start_off
;
6162 for (fr
= insn_start_frag
->fr_next
;
6163 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
6165 add
+= p
- frag_now
->fr_literal
;
6170 reloc_type
= BFD_RELOC_386_GOTPC
;
6171 i
.op
[n
].imms
->X_add_number
+= add
;
6173 else if (reloc_type
== BFD_RELOC_64
)
6174 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
6176 /* Don't do the adjustment for x86-64, as there
6177 the pcrel addressing is relative to the _next_
6178 insn, and that is taken care of in other code. */
6179 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
6181 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6182 i
.op
[n
].disps
, pcrel
, reloc_type
);
6189 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
6194 for (n
= 0; n
< i
.operands
; n
++)
6196 if (operand_type_check (i
.types
[n
], imm
))
6198 if (i
.op
[n
].imms
->X_op
== O_constant
)
6200 int size
= imm_size (n
);
6203 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
6205 p
= frag_more (size
);
6206 md_number_to_chars (p
, val
, size
);
6210 /* Not absolute_section.
6211 Need a 32-bit fixup (don't support 8bit
6212 non-absolute imms). Try to support other
6214 enum bfd_reloc_code_real reloc_type
;
6215 int size
= imm_size (n
);
6218 if (i
.types
[n
].bitfield
.imm32s
6219 && (i
.suffix
== QWORD_MNEM_SUFFIX
6220 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
6225 p
= frag_more (size
);
6226 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
6228 /* This is tough to explain. We end up with this one if we
6229 * have operands that look like
6230 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
6231 * obtain the absolute address of the GOT, and it is strongly
6232 * preferable from a performance point of view to avoid using
6233 * a runtime relocation for this. The actual sequence of
6234 * instructions often look something like:
6239 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
6241 * The call and pop essentially return the absolute address
6242 * of the label .L66 and store it in %ebx. The linker itself
6243 * will ultimately change the first operand of the addl so
6244 * that %ebx points to the GOT, but to keep things simple, the
6245 * .o file must have this operand set so that it generates not
6246 * the absolute address of .L66, but the absolute address of
6247 * itself. This allows the linker itself simply treat a GOTPC
6248 * relocation as asking for a pcrel offset to the GOT to be
6249 * added in, and the addend of the relocation is stored in the
6250 * operand field for the instruction itself.
6252 * Our job here is to fix the operand so that it would add
6253 * the correct offset so that %ebx would point to itself. The
6254 * thing that is tricky is that .-.L66 will point to the
6255 * beginning of the instruction, so we need to further modify
6256 * the operand so that it will point to itself. There are
6257 * other cases where you have something like:
6259 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
6261 * and here no correction would be required. Internally in
6262 * the assembler we treat operands of this form as not being
6263 * pcrel since the '.' is explicitly mentioned, and I wonder
6264 * whether it would simplify matters to do it this way. Who
6265 * knows. In earlier versions of the PIC patches, the
6266 * pcrel_adjust field was used to store the correction, but
6267 * since the expression is not pcrel, I felt it would be
6268 * confusing to do it this way. */
6270 if ((reloc_type
== BFD_RELOC_32
6271 || reloc_type
== BFD_RELOC_X86_64_32S
6272 || reloc_type
== BFD_RELOC_64
)
6274 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
6275 && (i
.op
[n
].imms
->X_op
== O_symbol
6276 || (i
.op
[n
].imms
->X_op
== O_add
6277 && ((symbol_get_value_expression
6278 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
6283 if (insn_start_frag
== frag_now
)
6284 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
6289 add
= insn_start_frag
->fr_fix
- insn_start_off
;
6290 for (fr
= insn_start_frag
->fr_next
;
6291 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
6293 add
+= p
- frag_now
->fr_literal
;
6297 reloc_type
= BFD_RELOC_386_GOTPC
;
6299 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
6301 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
6302 i
.op
[n
].imms
->X_add_number
+= add
;
6304 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6305 i
.op
[n
].imms
, 0, reloc_type
);
6311 /* x86_cons_fix_new is called via the expression parsing code when a
6312 reloc is needed. We use this hook to get the correct .got reloc. */
6313 static enum bfd_reloc_code_real got_reloc
= NO_RELOC
;
6314 static int cons_sign
= -1;
6317 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
6320 enum bfd_reloc_code_real r
= reloc (len
, 0, cons_sign
, got_reloc
);
6322 got_reloc
= NO_RELOC
;
6325 if (exp
->X_op
== O_secrel
)
6327 exp
->X_op
= O_symbol
;
6328 r
= BFD_RELOC_32_SECREL
;
6332 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
6335 #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
6336 # define lex_got(reloc, adjust, types) NULL
6338 /* Parse operands of the form
6339 <symbol>@GOTOFF+<nnn>
6340 and similar .plt or .got references.
6342 If we find one, set up the correct relocation in RELOC and copy the
6343 input string, minus the `@GOTOFF' into a malloc'd buffer for
6344 parsing by the calling routine. Return this buffer, and if ADJUST
6345 is non-null set it to the length of the string we removed from the
6346 input line. Otherwise return NULL. */
6348 lex_got (enum bfd_reloc_code_real
*reloc
,
6350 i386_operand_type
*types
)
6352 /* Some of the relocations depend on the size of what field is to
6353 be relocated. But in our callers i386_immediate and i386_displacement
6354 we don't yet know the operand size (this will be set by insn
6355 matching). Hence we record the word32 relocation here,
6356 and adjust the reloc according to the real size in reloc(). */
6357 static const struct {
6359 const enum bfd_reloc_code_real rel
[2];
6360 const i386_operand_type types64
;
6363 BFD_RELOC_X86_64_PLTOFF64
},
6364 OPERAND_TYPE_IMM64
},
6365 { "PLT", { BFD_RELOC_386_PLT32
,
6366 BFD_RELOC_X86_64_PLT32
},
6367 OPERAND_TYPE_IMM32_32S_DISP32
},
6369 BFD_RELOC_X86_64_GOTPLT64
},
6370 OPERAND_TYPE_IMM64_DISP64
},
6371 { "GOTOFF", { BFD_RELOC_386_GOTOFF
,
6372 BFD_RELOC_X86_64_GOTOFF64
},
6373 OPERAND_TYPE_IMM64_DISP64
},
6375 BFD_RELOC_X86_64_GOTPCREL
},
6376 OPERAND_TYPE_IMM32_32S_DISP32
},
6377 { "TLSGD", { BFD_RELOC_386_TLS_GD
,
6378 BFD_RELOC_X86_64_TLSGD
},
6379 OPERAND_TYPE_IMM32_32S_DISP32
},
6380 { "TLSLDM", { BFD_RELOC_386_TLS_LDM
,
6382 OPERAND_TYPE_NONE
},
6384 BFD_RELOC_X86_64_TLSLD
},
6385 OPERAND_TYPE_IMM32_32S_DISP32
},
6386 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32
,
6387 BFD_RELOC_X86_64_GOTTPOFF
},
6388 OPERAND_TYPE_IMM32_32S_DISP32
},
6389 { "TPOFF", { BFD_RELOC_386_TLS_LE_32
,
6390 BFD_RELOC_X86_64_TPOFF32
},
6391 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6392 { "NTPOFF", { BFD_RELOC_386_TLS_LE
,
6394 OPERAND_TYPE_NONE
},
6395 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32
,
6396 BFD_RELOC_X86_64_DTPOFF32
},
6398 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6399 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE
,
6401 OPERAND_TYPE_NONE
},
6402 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE
,
6404 OPERAND_TYPE_NONE
},
6405 { "GOT", { BFD_RELOC_386_GOT32
,
6406 BFD_RELOC_X86_64_GOT32
},
6407 OPERAND_TYPE_IMM32_32S_64_DISP32
},
6408 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC
,
6409 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
6410 OPERAND_TYPE_IMM32_32S_DISP32
},
6411 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL
,
6412 BFD_RELOC_X86_64_TLSDESC_CALL
},
6413 OPERAND_TYPE_IMM32_32S_DISP32
},
6421 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
6422 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
6425 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
6429 len
= strlen (gotrel
[j
].str
);
6430 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
6432 if (gotrel
[j
].rel
[object_64bit
] != 0)
6435 char *tmpbuf
, *past_reloc
;
6437 *reloc
= gotrel
[j
].rel
[object_64bit
];
6443 if (flag_code
!= CODE_64BIT
)
6445 types
->bitfield
.imm32
= 1;
6446 types
->bitfield
.disp32
= 1;
6449 *types
= gotrel
[j
].types64
;
6452 if (GOT_symbol
== NULL
)
6453 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
6455 /* The length of the first part of our input line. */
6456 first
= cp
- input_line_pointer
;
6458 /* The second part goes from after the reloc token until
6459 (and including) an end_of_line char or comma. */
6460 past_reloc
= cp
+ 1 + len
;
6462 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
6464 second
= cp
+ 1 - past_reloc
;
6466 /* Allocate and copy string. The trailing NUL shouldn't
6467 be necessary, but be safe. */
6468 tmpbuf
= xmalloc (first
+ second
+ 2);
6469 memcpy (tmpbuf
, input_line_pointer
, first
);
6470 if (second
!= 0 && *past_reloc
!= ' ')
6471 /* Replace the relocation token with ' ', so that
6472 errors like foo@GOTOFF1 will be detected. */
6473 tmpbuf
[first
++] = ' ';
6474 memcpy (tmpbuf
+ first
, past_reloc
, second
);
6475 tmpbuf
[first
+ second
] = '\0';
6479 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6480 gotrel
[j
].str
, 1 << (5 + object_64bit
));
6485 /* Might be a symbol version string. Don't as_bad here. */
6490 x86_cons (expressionS
*exp
, int size
)
6492 if (size
== 4 || (object_64bit
&& size
== 8))
6494 /* Handle @GOTOFF and the like in an expression. */
6496 char *gotfree_input_line
;
6499 save
= input_line_pointer
;
6500 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
6501 if (gotfree_input_line
)
6502 input_line_pointer
= gotfree_input_line
;
6506 if (gotfree_input_line
)
6508 /* expression () has merrily parsed up to the end of line,
6509 or a comma - in the wrong buffer. Transfer how far
6510 input_line_pointer has moved to the right buffer. */
6511 input_line_pointer
= (save
6512 + (input_line_pointer
- gotfree_input_line
)
6514 free (gotfree_input_line
);
6515 if (exp
->X_op
== O_constant
6516 || exp
->X_op
== O_absent
6517 || exp
->X_op
== O_illegal
6518 || exp
->X_op
== O_register
6519 || exp
->X_op
== O_big
)
6521 char c
= *input_line_pointer
;
6522 *input_line_pointer
= 0;
6523 as_bad (_("missing or invalid expression `%s'"), save
);
6524 *input_line_pointer
= c
;
6533 static void signed_cons (int size
)
6535 if (flag_code
== CODE_64BIT
)
6543 pe_directive_secrel (dummy
)
6544 int dummy ATTRIBUTE_UNUSED
;
6551 if (exp
.X_op
== O_symbol
)
6552 exp
.X_op
= O_secrel
;
6554 emit_expr (&exp
, 4);
6556 while (*input_line_pointer
++ == ',');
6558 input_line_pointer
--;
6559 demand_empty_rest_of_line ();
6564 i386_immediate (char *imm_start
)
6566 char *save_input_line_pointer
;
6567 char *gotfree_input_line
;
6570 i386_operand_type types
;
6572 operand_type_set (&types
, ~0);
6574 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
6576 as_bad (_("at most %d immediate operands are allowed"),
6577 MAX_IMMEDIATE_OPERANDS
);
6581 exp
= &im_expressions
[i
.imm_operands
++];
6582 i
.op
[this_operand
].imms
= exp
;
6584 if (is_space_char (*imm_start
))
6587 save_input_line_pointer
= input_line_pointer
;
6588 input_line_pointer
= imm_start
;
6590 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
6591 if (gotfree_input_line
)
6592 input_line_pointer
= gotfree_input_line
;
6594 exp_seg
= expression (exp
);
6597 if (*input_line_pointer
)
6598 as_bad (_("junk `%s' after expression"), input_line_pointer
);
6600 input_line_pointer
= save_input_line_pointer
;
6601 if (gotfree_input_line
)
6602 free (gotfree_input_line
);
6604 if (exp
->X_op
== O_absent
6605 || exp
->X_op
== O_illegal
6606 || exp
->X_op
== O_big
6607 || (gotfree_input_line
6608 && (exp
->X_op
== O_constant
6609 || exp
->X_op
== O_register
)))
6611 as_bad (_("missing or invalid immediate expression `%s'"),
6615 else if (exp
->X_op
== O_constant
)
6617 /* Size it properly later. */
6618 i
.types
[this_operand
].bitfield
.imm64
= 1;
6619 /* If BFD64, sign extend val. */
6620 if (!use_rela_relocations
6621 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
6623 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
6625 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6626 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
6627 && exp_seg
!= absolute_section
6628 && exp_seg
!= text_section
6629 && exp_seg
!= data_section
6630 && exp_seg
!= bss_section
6631 && exp_seg
!= undefined_section
6632 && !bfd_is_com_section (exp_seg
))
6634 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
6638 else if (!intel_syntax
&& exp
->X_op
== O_register
)
6640 as_bad (_("illegal immediate register operand %s"), imm_start
);
6645 /* This is an address. The size of the address will be
6646 determined later, depending on destination register,
6647 suffix, or the default for the section. */
6648 i
.types
[this_operand
].bitfield
.imm8
= 1;
6649 i
.types
[this_operand
].bitfield
.imm16
= 1;
6650 i
.types
[this_operand
].bitfield
.imm32
= 1;
6651 i
.types
[this_operand
].bitfield
.imm32s
= 1;
6652 i
.types
[this_operand
].bitfield
.imm64
= 1;
6653 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
6661 i386_scale (char *scale
)
6664 char *save
= input_line_pointer
;
6666 input_line_pointer
= scale
;
6667 val
= get_absolute_expression ();
6672 i
.log2_scale_factor
= 0;
6675 i
.log2_scale_factor
= 1;
6678 i
.log2_scale_factor
= 2;
6681 i
.log2_scale_factor
= 3;
6685 char sep
= *input_line_pointer
;
6687 *input_line_pointer
= '\0';
6688 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
6690 *input_line_pointer
= sep
;
6691 input_line_pointer
= save
;
6695 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
6697 as_warn (_("scale factor of %d without an index register"),
6698 1 << i
.log2_scale_factor
);
6699 i
.log2_scale_factor
= 0;
6701 scale
= input_line_pointer
;
6702 input_line_pointer
= save
;
6707 i386_displacement (char *disp_start
, char *disp_end
)
6711 char *save_input_line_pointer
;
6712 char *gotfree_input_line
;
6714 i386_operand_type bigdisp
, types
= anydisp
;
6717 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
6719 as_bad (_("at most %d displacement operands are allowed"),
6720 MAX_MEMORY_OPERANDS
);
6724 operand_type_set (&bigdisp
, 0);
6725 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
6726 || (!current_templates
->start
->opcode_modifier
.jump
6727 && !current_templates
->start
->opcode_modifier
.jumpdword
))
6729 bigdisp
.bitfield
.disp32
= 1;
6730 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
6731 if (flag_code
== CODE_64BIT
)
6735 bigdisp
.bitfield
.disp32s
= 1;
6736 bigdisp
.bitfield
.disp64
= 1;
6739 else if ((flag_code
== CODE_16BIT
) ^ override
)
6741 bigdisp
.bitfield
.disp32
= 0;
6742 bigdisp
.bitfield
.disp16
= 1;
6747 /* For PC-relative branches, the width of the displacement
6748 is dependent upon data size, not address size. */
6749 override
= (i
.prefix
[DATA_PREFIX
] != 0);
6750 if (flag_code
== CODE_64BIT
)
6752 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
6753 bigdisp
.bitfield
.disp16
= 1;
6756 bigdisp
.bitfield
.disp32
= 1;
6757 bigdisp
.bitfield
.disp32s
= 1;
6763 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
6765 : LONG_MNEM_SUFFIX
));
6766 bigdisp
.bitfield
.disp32
= 1;
6767 if ((flag_code
== CODE_16BIT
) ^ override
)
6769 bigdisp
.bitfield
.disp32
= 0;
6770 bigdisp
.bitfield
.disp16
= 1;
6774 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
6777 exp
= &disp_expressions
[i
.disp_operands
];
6778 i
.op
[this_operand
].disps
= exp
;
6780 save_input_line_pointer
= input_line_pointer
;
6781 input_line_pointer
= disp_start
;
6782 END_STRING_AND_SAVE (disp_end
);
6784 #ifndef GCC_ASM_O_HACK
6785 #define GCC_ASM_O_HACK 0
6788 END_STRING_AND_SAVE (disp_end
+ 1);
6789 if (i
.types
[this_operand
].bitfield
.baseIndex
6790 && displacement_string_end
[-1] == '+')
6792 /* This hack is to avoid a warning when using the "o"
6793 constraint within gcc asm statements.
6796 #define _set_tssldt_desc(n,addr,limit,type) \
6797 __asm__ __volatile__ ( \
6799 "movw %w1,2+%0\n\t" \
6801 "movb %b1,4+%0\n\t" \
6802 "movb %4,5+%0\n\t" \
6803 "movb $0,6+%0\n\t" \
6804 "movb %h1,7+%0\n\t" \
6806 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
6808 This works great except that the output assembler ends
6809 up looking a bit weird if it turns out that there is
6810 no offset. You end up producing code that looks like:
6823 So here we provide the missing zero. */
6825 *displacement_string_end
= '0';
6828 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
6829 if (gotfree_input_line
)
6830 input_line_pointer
= gotfree_input_line
;
6832 exp_seg
= expression (exp
);
6835 if (*input_line_pointer
)
6836 as_bad (_("junk `%s' after expression"), input_line_pointer
);
6838 RESTORE_END_STRING (disp_end
+ 1);
6840 input_line_pointer
= save_input_line_pointer
;
6841 if (gotfree_input_line
)
6842 free (gotfree_input_line
);
6845 /* We do this to make sure that the section symbol is in
6846 the symbol table. We will ultimately change the relocation
6847 to be relative to the beginning of the section. */
6848 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
6849 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
6850 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
6852 if (exp
->X_op
!= O_symbol
)
6855 if (S_IS_LOCAL (exp
->X_add_symbol
)
6856 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
6857 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
6858 exp
->X_op
= O_subtract
;
6859 exp
->X_op_symbol
= GOT_symbol
;
6860 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
6861 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
6862 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
6863 i
.reloc
[this_operand
] = BFD_RELOC_64
;
6865 i
.reloc
[this_operand
] = BFD_RELOC_32
;
6868 else if (exp
->X_op
== O_absent
6869 || exp
->X_op
== O_illegal
6870 || exp
->X_op
== O_big
6871 || (gotfree_input_line
6872 && (exp
->X_op
== O_constant
6873 || exp
->X_op
== O_register
)))
6876 as_bad (_("missing or invalid displacement expression `%s'"),
6881 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6882 else if (exp
->X_op
!= O_constant
6883 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
6884 && exp_seg
!= absolute_section
6885 && exp_seg
!= text_section
6886 && exp_seg
!= data_section
6887 && exp_seg
!= bss_section
6888 && exp_seg
!= undefined_section
6889 && !bfd_is_com_section (exp_seg
))
6891 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
6896 RESTORE_END_STRING (disp_end
);
6898 /* Check if this is a displacement only operand. */
6899 bigdisp
= i
.types
[this_operand
];
6900 bigdisp
.bitfield
.disp8
= 0;
6901 bigdisp
.bitfield
.disp16
= 0;
6902 bigdisp
.bitfield
.disp32
= 0;
6903 bigdisp
.bitfield
.disp32s
= 0;
6904 bigdisp
.bitfield
.disp64
= 0;
6905 if (operand_type_all_zero (&bigdisp
))
6906 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
6912 /* Make sure the memory operand we've been dealt is valid.
6913 Return 1 on success, 0 on a failure. */
6916 i386_index_check (const char *operand_string
)
6919 const char *kind
= "base/index";
6920 #if INFER_ADDR_PREFIX
6926 if (current_templates
->start
->opcode_modifier
.isstring
6927 && !current_templates
->start
->opcode_modifier
.immext
6928 && (current_templates
->end
[-1].opcode_modifier
.isstring
6931 /* Memory operands of string insns are special in that they only allow
6932 a single register (rDI, rSI, or rBX) as their memory address. */
6933 unsigned int expected
;
6935 kind
= "string address";
6937 if (current_templates
->start
->opcode_modifier
.w
)
6939 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
6941 if (!type
.bitfield
.baseindex
6942 || ((!i
.mem_operands
!= !intel_syntax
)
6943 && current_templates
->end
[-1].operand_types
[1]
6944 .bitfield
.baseindex
))
6945 type
= current_templates
->end
[-1].operand_types
[1];
6946 expected
= type
.bitfield
.esseg
? 7 /* rDI */ : 6 /* rSI */;
6949 expected
= 3 /* rBX */;
6951 if (!i
.base_reg
|| i
.index_reg
6952 || operand_type_check (i
.types
[this_operand
], disp
))
6954 else if (!(flag_code
== CODE_64BIT
6955 ? i
.prefix
[ADDR_PREFIX
]
6956 ? i
.base_reg
->reg_type
.bitfield
.reg32
6957 : i
.base_reg
->reg_type
.bitfield
.reg64
6958 : (flag_code
== CODE_16BIT
) ^ !i
.prefix
[ADDR_PREFIX
]
6959 ? i
.base_reg
->reg_type
.bitfield
.reg32
6960 : i
.base_reg
->reg_type
.bitfield
.reg16
))
6962 else if (i
.base_reg
->reg_num
!= expected
)
6969 for (j
= 0; j
< i386_regtab_size
; ++j
)
6970 if ((flag_code
== CODE_64BIT
6971 ? i
.prefix
[ADDR_PREFIX
]
6972 ? i386_regtab
[j
].reg_type
.bitfield
.reg32
6973 : i386_regtab
[j
].reg_type
.bitfield
.reg64
6974 : (flag_code
== CODE_16BIT
) ^ !i
.prefix
[ADDR_PREFIX
]
6975 ? i386_regtab
[j
].reg_type
.bitfield
.reg32
6976 : i386_regtab
[j
].reg_type
.bitfield
.reg16
)
6977 && i386_regtab
[j
].reg_num
== expected
)
6979 assert (j
< i386_regtab_size
);
6980 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
6982 intel_syntax
? '[' : '(',
6984 i386_regtab
[j
].reg_name
,
6985 intel_syntax
? ']' : ')');
6989 else if (flag_code
== CODE_64BIT
)
6992 && ((i
.prefix
[ADDR_PREFIX
] == 0
6993 && !i
.base_reg
->reg_type
.bitfield
.reg64
)
6994 || (i
.prefix
[ADDR_PREFIX
]
6995 && !i
.base_reg
->reg_type
.bitfield
.reg32
))
6997 || i
.base_reg
->reg_num
!=
6998 (i
.prefix
[ADDR_PREFIX
] == 0 ? RegRip
: RegEip
)))
7000 && (!i
.index_reg
->reg_type
.bitfield
.baseindex
7001 || (i
.prefix
[ADDR_PREFIX
] == 0
7002 && i
.index_reg
->reg_num
!= RegRiz
7003 && !i
.index_reg
->reg_type
.bitfield
.reg64
7005 || (i
.prefix
[ADDR_PREFIX
]
7006 && i
.index_reg
->reg_num
!= RegEiz
7007 && !i
.index_reg
->reg_type
.bitfield
.reg32
))))
7012 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
7016 && (!i
.base_reg
->reg_type
.bitfield
.reg16
7017 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
7019 && (!i
.index_reg
->reg_type
.bitfield
.reg16
7020 || !i
.index_reg
->reg_type
.bitfield
.baseindex
7022 && i
.base_reg
->reg_num
< 6
7023 && i
.index_reg
->reg_num
>= 6
7024 && i
.log2_scale_factor
== 0))))
7031 && !i
.base_reg
->reg_type
.bitfield
.reg32
)
7033 && ((!i
.index_reg
->reg_type
.bitfield
.reg32
7034 && i
.index_reg
->reg_num
!= RegEiz
)
7035 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
7041 #if INFER_ADDR_PREFIX
7042 if (!i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
7044 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
7046 /* Change the size of any displacement too. At most one of
7047 Disp16 or Disp32 is set.
7048 FIXME. There doesn't seem to be any real need for separate
7049 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
7050 Removing them would probably clean up the code quite a lot. */
7051 if (flag_code
!= CODE_64BIT
7052 && (i
.types
[this_operand
].bitfield
.disp16
7053 || i
.types
[this_operand
].bitfield
.disp32
))
7054 i
.types
[this_operand
]
7055 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
7060 as_bad (_("`%s' is not a valid %s expression"),
7065 as_bad (_("`%s' is not a valid %s-bit %s expression"),
7067 flag_code_names
[i
.prefix
[ADDR_PREFIX
]
7068 ? flag_code
== CODE_32BIT
7077 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
7081 i386_att_operand (char *operand_string
)
7085 char *op_string
= operand_string
;
7087 if (is_space_char (*op_string
))
7090 /* We check for an absolute prefix (differentiating,
7091 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
7092 if (*op_string
== ABSOLUTE_PREFIX
)
7095 if (is_space_char (*op_string
))
7097 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
7100 /* Check if operand is a register. */
7101 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
7103 i386_operand_type temp
;
7105 /* Check for a segment override by searching for ':' after a
7106 segment register. */
7108 if (is_space_char (*op_string
))
7110 if (*op_string
== ':'
7111 && (r
->reg_type
.bitfield
.sreg2
7112 || r
->reg_type
.bitfield
.sreg3
))
7117 i
.seg
[i
.mem_operands
] = &es
;
7120 i
.seg
[i
.mem_operands
] = &cs
;
7123 i
.seg
[i
.mem_operands
] = &ss
;
7126 i
.seg
[i
.mem_operands
] = &ds
;
7129 i
.seg
[i
.mem_operands
] = &fs
;
7132 i
.seg
[i
.mem_operands
] = &gs
;
7136 /* Skip the ':' and whitespace. */
7138 if (is_space_char (*op_string
))
7141 if (!is_digit_char (*op_string
)
7142 && !is_identifier_char (*op_string
)
7143 && *op_string
!= '('
7144 && *op_string
!= ABSOLUTE_PREFIX
)
7146 as_bad (_("bad memory operand `%s'"), op_string
);
7149 /* Handle case of %es:*foo. */
7150 if (*op_string
== ABSOLUTE_PREFIX
)
7153 if (is_space_char (*op_string
))
7155 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
7157 goto do_memory_reference
;
7161 as_bad (_("junk `%s' after register"), op_string
);
7165 temp
.bitfield
.baseindex
= 0;
7166 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
7168 i
.types
[this_operand
].bitfield
.unspecified
= 0;
7169 i
.op
[this_operand
].regs
= r
;
7172 else if (*op_string
== REGISTER_PREFIX
)
7174 as_bad (_("bad register name `%s'"), op_string
);
7177 else if (*op_string
== IMMEDIATE_PREFIX
)
7180 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
7182 as_bad (_("immediate operand illegal with absolute jump"));
7185 if (!i386_immediate (op_string
))
7188 else if (is_digit_char (*op_string
)
7189 || is_identifier_char (*op_string
)
7190 || *op_string
== '(')
7192 /* This is a memory reference of some sort. */
7195 /* Start and end of displacement string expression (if found). */
7196 char *displacement_string_start
;
7197 char *displacement_string_end
;
7199 do_memory_reference
:
7200 if ((i
.mem_operands
== 1
7201 && !current_templates
->start
->opcode_modifier
.isstring
)
7202 || i
.mem_operands
== 2)
7204 as_bad (_("too many memory references for `%s'"),
7205 current_templates
->start
->name
);
7209 /* Check for base index form. We detect the base index form by
7210 looking for an ')' at the end of the operand, searching
7211 for the '(' matching it, and finding a REGISTER_PREFIX or ','
7213 base_string
= op_string
+ strlen (op_string
);
7216 if (is_space_char (*base_string
))
7219 /* If we only have a displacement, set-up for it to be parsed later. */
7220 displacement_string_start
= op_string
;
7221 displacement_string_end
= base_string
+ 1;
7223 if (*base_string
== ')')
7226 unsigned int parens_balanced
= 1;
7227 /* We've already checked that the number of left & right ()'s are
7228 equal, so this loop will not be infinite. */
7232 if (*base_string
== ')')
7234 if (*base_string
== '(')
7237 while (parens_balanced
);
7239 temp_string
= base_string
;
7241 /* Skip past '(' and whitespace. */
7243 if (is_space_char (*base_string
))
7246 if (*base_string
== ','
7247 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
7250 displacement_string_end
= temp_string
;
7252 i
.types
[this_operand
].bitfield
.baseindex
= 1;
7256 base_string
= end_op
;
7257 if (is_space_char (*base_string
))
7261 /* There may be an index reg or scale factor here. */
7262 if (*base_string
== ',')
7265 if (is_space_char (*base_string
))
7268 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
7271 base_string
= end_op
;
7272 if (is_space_char (*base_string
))
7274 if (*base_string
== ',')
7277 if (is_space_char (*base_string
))
7280 else if (*base_string
!= ')')
7282 as_bad (_("expecting `,' or `)' "
7283 "after index register in `%s'"),
7288 else if (*base_string
== REGISTER_PREFIX
)
7290 as_bad (_("bad register name `%s'"), base_string
);
7294 /* Check for scale factor. */
7295 if (*base_string
!= ')')
7297 char *end_scale
= i386_scale (base_string
);
7302 base_string
= end_scale
;
7303 if (is_space_char (*base_string
))
7305 if (*base_string
!= ')')
7307 as_bad (_("expecting `)' "
7308 "after scale factor in `%s'"),
7313 else if (!i
.index_reg
)
7315 as_bad (_("expecting index register or scale factor "
7316 "after `,'; got '%c'"),
7321 else if (*base_string
!= ')')
7323 as_bad (_("expecting `,' or `)' "
7324 "after base register in `%s'"),
7329 else if (*base_string
== REGISTER_PREFIX
)
7331 as_bad (_("bad register name `%s'"), base_string
);
7336 /* If there's an expression beginning the operand, parse it,
7337 assuming displacement_string_start and
7338 displacement_string_end are meaningful. */
7339 if (displacement_string_start
!= displacement_string_end
)
7341 if (!i386_displacement (displacement_string_start
,
7342 displacement_string_end
))
7346 /* Special case for (%dx) while doing input/output op. */
7348 && operand_type_equal (&i
.base_reg
->reg_type
,
7349 ®16_inoutportreg
)
7351 && i
.log2_scale_factor
== 0
7352 && i
.seg
[i
.mem_operands
] == 0
7353 && !operand_type_check (i
.types
[this_operand
], disp
))
7355 i
.types
[this_operand
] = inoutportreg
;
7359 if (i386_index_check (operand_string
) == 0)
7361 i
.types
[this_operand
].bitfield
.mem
= 1;
7366 /* It's not a memory operand; argh! */
7367 as_bad (_("invalid char %s beginning operand %d `%s'"),
7368 output_invalid (*op_string
),
7373 return 1; /* Normal return. */
7376 /* md_estimate_size_before_relax()
7378 Called just before relax() for rs_machine_dependent frags. The x86
7379 assembler uses these frags to handle variable size jump
7382 Any symbol that is now undefined will not become defined.
7383 Return the correct fr_subtype in the frag.
7384 Return the initial "guess for variable size of frag" to caller.
7385 The guess is actually the growth beyond the fixed part. Whatever
7386 we do to grow the fixed or variable part contributes to our
7390 md_estimate_size_before_relax (fragP
, segment
)
7394 /* We've already got fragP->fr_subtype right; all we have to do is
7395 check for un-relaxable symbols. On an ELF system, we can't relax
7396 an externally visible symbol, because it may be overridden by a
7398 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
7399 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7401 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
7402 || S_IS_WEAK (fragP
->fr_symbol
)))
7406 /* Symbol is undefined in this segment, or we need to keep a
7407 reloc so that weak symbols can be overridden. */
7408 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
7409 enum bfd_reloc_code_real reloc_type
;
7410 unsigned char *opcode
;
7413 if (fragP
->fr_var
!= NO_RELOC
)
7414 reloc_type
= fragP
->fr_var
;
7416 reloc_type
= BFD_RELOC_16_PCREL
;
7418 reloc_type
= BFD_RELOC_32_PCREL
;
7420 old_fr_fix
= fragP
->fr_fix
;
7421 opcode
= (unsigned char *) fragP
->fr_opcode
;
7423 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
7426 /* Make jmp (0xeb) a (d)word displacement jump. */
7428 fragP
->fr_fix
+= size
;
7429 fix_new (fragP
, old_fr_fix
, size
,
7431 fragP
->fr_offset
, 1,
7437 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
7439 /* Negate the condition, and branch past an
7440 unconditional jump. */
7443 /* Insert an unconditional jump. */
7445 /* We added two extra opcode bytes, and have a two byte
7447 fragP
->fr_fix
+= 2 + 2;
7448 fix_new (fragP
, old_fr_fix
+ 2, 2,
7450 fragP
->fr_offset
, 1,
7457 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
7462 fixP
= fix_new (fragP
, old_fr_fix
, 1,
7464 fragP
->fr_offset
, 1,
7466 fixP
->fx_signed
= 1;
7470 /* This changes the byte-displacement jump 0x7N
7471 to the (d)word-displacement jump 0x0f,0x8N. */
7472 opcode
[1] = opcode
[0] + 0x10;
7473 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7474 /* We've added an opcode byte. */
7475 fragP
->fr_fix
+= 1 + size
;
7476 fix_new (fragP
, old_fr_fix
+ 1, size
,
7478 fragP
->fr_offset
, 1,
7483 BAD_CASE (fragP
->fr_subtype
);
7487 return fragP
->fr_fix
- old_fr_fix
;
7490 /* Guess size depending on current relax state. Initially the relax
7491 state will correspond to a short jump and we return 1, because
7492 the variable part of the frag (the branch offset) is one byte
7493 long. However, we can relax a section more than once and in that
7494 case we must either set fr_subtype back to the unrelaxed state,
7495 or return the value for the appropriate branch. */
7496 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
7499 /* Called after relax() is finished.
7501 In: Address of frag.
7502 fr_type == rs_machine_dependent.
7503 fr_subtype is what the address relaxed to.
7505 Out: Any fixSs and constants are set up.
7506 Caller will turn frag into a ".space 0". */
7509 md_convert_frag (abfd
, sec
, fragP
)
7510 bfd
*abfd ATTRIBUTE_UNUSED
;
7511 segT sec ATTRIBUTE_UNUSED
;
7514 unsigned char *opcode
;
7515 unsigned char *where_to_put_displacement
= NULL
;
7516 offsetT target_address
;
7517 offsetT opcode_address
;
7518 unsigned int extension
= 0;
7519 offsetT displacement_from_opcode_start
;
7521 opcode
= (unsigned char *) fragP
->fr_opcode
;
7523 /* Address we want to reach in file space. */
7524 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
7526 /* Address opcode resides at in file space. */
7527 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
7529 /* Displacement from opcode start to fill into instruction. */
7530 displacement_from_opcode_start
= target_address
- opcode_address
;
7532 if ((fragP
->fr_subtype
& BIG
) == 0)
7534 /* Don't have to change opcode. */
7535 extension
= 1; /* 1 opcode + 1 displacement */
7536 where_to_put_displacement
= &opcode
[1];
7540 if (no_cond_jump_promotion
7541 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
7542 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
7543 _("long jump required"));
7545 switch (fragP
->fr_subtype
)
7547 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
7548 extension
= 4; /* 1 opcode + 4 displacement */
7550 where_to_put_displacement
= &opcode
[1];
7553 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
7554 extension
= 2; /* 1 opcode + 2 displacement */
7556 where_to_put_displacement
= &opcode
[1];
7559 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
7560 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
7561 extension
= 5; /* 2 opcode + 4 displacement */
7562 opcode
[1] = opcode
[0] + 0x10;
7563 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7564 where_to_put_displacement
= &opcode
[2];
7567 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
7568 extension
= 3; /* 2 opcode + 2 displacement */
7569 opcode
[1] = opcode
[0] + 0x10;
7570 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7571 where_to_put_displacement
= &opcode
[2];
7574 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
7579 where_to_put_displacement
= &opcode
[3];
7583 BAD_CASE (fragP
->fr_subtype
);
7588 /* If size if less then four we are sure that the operand fits,
7589 but if it's 4, then it could be that the displacement is larger
7591 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
7593 && ((addressT
) (displacement_from_opcode_start
- extension
7594 + ((addressT
) 1 << 31))
7595 > (((addressT
) 2 << 31) - 1)))
7597 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
7598 _("jump target out of range"));
7599 /* Make us emit 0. */
7600 displacement_from_opcode_start
= extension
;
7602 /* Now put displacement after opcode. */
7603 md_number_to_chars ((char *) where_to_put_displacement
,
7604 (valueT
) (displacement_from_opcode_start
- extension
),
7605 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
7606 fragP
->fr_fix
+= extension
;
7609 /* Apply a fixup (fixS) to segment data, once it has been determined
7610 by our caller that we have all the info we need to fix it up.
7612 On the 386, immediates, displacements, and data pointers are all in
7613 the same (little-endian) format, so we don't need to care about which
7617 md_apply_fix (fixP
, valP
, seg
)
7618 /* The fix we're to put in. */
7620 /* Pointer to the value of the bits. */
7622 /* Segment fix is from. */
7623 segT seg ATTRIBUTE_UNUSED
;
7625 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
7626 valueT value
= *valP
;
7628 #if !defined (TE_Mach)
7631 switch (fixP
->fx_r_type
)
7637 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
7640 case BFD_RELOC_X86_64_32S
:
7641 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
7644 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
7647 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
7652 if (fixP
->fx_addsy
!= NULL
7653 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
7654 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
7655 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
7656 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
7657 && !use_rela_relocations
)
7659 /* This is a hack. There should be a better way to handle this.
7660 This covers for the fact that bfd_install_relocation will
7661 subtract the current location (for partial_inplace, PC relative
7662 relocations); see more below. */
7666 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
7669 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7671 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7674 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
7677 || (symbol_section_p (fixP
->fx_addsy
)
7678 && sym_seg
!= absolute_section
))
7679 && !generic_force_reloc (fixP
))
7681 /* Yes, we add the values in twice. This is because
7682 bfd_install_relocation subtracts them out again. I think
7683 bfd_install_relocation is broken, but I don't dare change
7685 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7689 #if defined (OBJ_COFF) && defined (TE_PE)
7690 /* For some reason, the PE format does not store a
7691 section address offset for a PC relative symbol. */
7692 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
7693 || S_IS_WEAK (fixP
->fx_addsy
))
7694 value
+= md_pcrel_from (fixP
);
7698 /* Fix a few things - the dynamic linker expects certain values here,
7699 and we must not disappoint it. */
7700 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7701 if (IS_ELF
&& fixP
->fx_addsy
)
7702 switch (fixP
->fx_r_type
)
7704 case BFD_RELOC_386_PLT32
:
7705 case BFD_RELOC_X86_64_PLT32
:
7706 /* Make the jump instruction point to the address of the operand. At
7707 runtime we merely add the offset to the actual PLT entry. */
7711 case BFD_RELOC_386_TLS_GD
:
7712 case BFD_RELOC_386_TLS_LDM
:
7713 case BFD_RELOC_386_TLS_IE_32
:
7714 case BFD_RELOC_386_TLS_IE
:
7715 case BFD_RELOC_386_TLS_GOTIE
:
7716 case BFD_RELOC_386_TLS_GOTDESC
:
7717 case BFD_RELOC_X86_64_TLSGD
:
7718 case BFD_RELOC_X86_64_TLSLD
:
7719 case BFD_RELOC_X86_64_GOTTPOFF
:
7720 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
7721 value
= 0; /* Fully resolved at runtime. No addend. */
7723 case BFD_RELOC_386_TLS_LE
:
7724 case BFD_RELOC_386_TLS_LDO_32
:
7725 case BFD_RELOC_386_TLS_LE_32
:
7726 case BFD_RELOC_X86_64_DTPOFF32
:
7727 case BFD_RELOC_X86_64_DTPOFF64
:
7728 case BFD_RELOC_X86_64_TPOFF32
:
7729 case BFD_RELOC_X86_64_TPOFF64
:
7730 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7733 case BFD_RELOC_386_TLS_DESC_CALL
:
7734 case BFD_RELOC_X86_64_TLSDESC_CALL
:
7735 value
= 0; /* Fully resolved at runtime. No addend. */
7736 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7740 case BFD_RELOC_386_GOT32
:
7741 case BFD_RELOC_X86_64_GOT32
:
7742 value
= 0; /* Fully resolved at runtime. No addend. */
7745 case BFD_RELOC_VTABLE_INHERIT
:
7746 case BFD_RELOC_VTABLE_ENTRY
:
7753 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
7755 #endif /* !defined (TE_Mach) */
7757 /* Are we finished with this relocation now? */
7758 if (fixP
->fx_addsy
== NULL
)
7760 else if (use_rela_relocations
)
7762 fixP
->fx_no_overflow
= 1;
7763 /* Remember value for tc_gen_reloc. */
7764 fixP
->fx_addnumber
= value
;
7768 md_number_to_chars (p
, value
, fixP
->fx_size
);
7772 md_atof (int type
, char *litP
, int *sizeP
)
7774 /* This outputs the LITTLENUMs in REVERSE order;
7775 in accord with the bigendian 386. */
7776 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
7779 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
7782 output_invalid (int c
)
7785 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
7788 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
7789 "(0x%x)", (unsigned char) c
);
7790 return output_invalid_buf
;
7793 /* REG_STRING starts *before* REGISTER_PREFIX. */
7795 static const reg_entry
*
7796 parse_real_register (char *reg_string
, char **end_op
)
7798 char *s
= reg_string
;
7800 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
7803 /* Skip possible REGISTER_PREFIX and possible whitespace. */
7804 if (*s
== REGISTER_PREFIX
)
7807 if (is_space_char (*s
))
7811 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
7813 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
7814 return (const reg_entry
*) NULL
;
7818 /* For naked regs, make sure that we are not dealing with an identifier.
7819 This prevents confusing an identifier like `eax_var' with register
7821 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
7822 return (const reg_entry
*) NULL
;
7826 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
7828 /* Handle floating point regs, allowing spaces in the (i) part. */
7829 if (r
== i386_regtab
/* %st is first entry of table */)
7831 if (is_space_char (*s
))
7836 if (is_space_char (*s
))
7838 if (*s
>= '0' && *s
<= '7')
7842 if (is_space_char (*s
))
7847 r
= hash_find (reg_hash
, "st(0)");
7852 /* We have "%st(" then garbage. */
7853 return (const reg_entry
*) NULL
;
7857 if (r
== NULL
|| allow_pseudo_reg
)
7860 if (operand_type_all_zero (&r
->reg_type
))
7861 return (const reg_entry
*) NULL
;
7863 if ((r
->reg_type
.bitfield
.reg32
7864 || r
->reg_type
.bitfield
.sreg3
7865 || r
->reg_type
.bitfield
.control
7866 || r
->reg_type
.bitfield
.debug
7867 || r
->reg_type
.bitfield
.test
)
7868 && !cpu_arch_flags
.bitfield
.cpui386
)
7869 return (const reg_entry
*) NULL
;
7871 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
7872 return (const reg_entry
*) NULL
;
7874 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpusse
)
7875 return (const reg_entry
*) NULL
;
7877 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuavx
)
7878 return (const reg_entry
*) NULL
;
7880 /* Don't allow fake index register unless allow_index_reg isn't 0. */
7881 if (!allow_index_reg
7882 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
7883 return (const reg_entry
*) NULL
;
7885 if (((r
->reg_flags
& (RegRex64
| RegRex
))
7886 || r
->reg_type
.bitfield
.reg64
)
7887 && (!cpu_arch_flags
.bitfield
.cpulm
7888 || !operand_type_equal (&r
->reg_type
, &control
))
7889 && flag_code
!= CODE_64BIT
)
7890 return (const reg_entry
*) NULL
;
7892 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
7893 return (const reg_entry
*) NULL
;
7898 /* REG_STRING starts *before* REGISTER_PREFIX. */
7900 static const reg_entry
*
7901 parse_register (char *reg_string
, char **end_op
)
7905 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
7906 r
= parse_real_register (reg_string
, end_op
);
7911 char *save
= input_line_pointer
;
7915 input_line_pointer
= reg_string
;
7916 c
= get_symbol_end ();
7917 symbolP
= symbol_find (reg_string
);
7918 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
7920 const expressionS
*e
= symbol_get_value_expression (symbolP
);
7922 know (e
->X_op
== O_register
);
7923 know (e
->X_add_number
>= 0
7924 && (valueT
) e
->X_add_number
< i386_regtab_size
);
7925 r
= i386_regtab
+ e
->X_add_number
;
7926 *end_op
= input_line_pointer
;
7928 *input_line_pointer
= c
;
7929 input_line_pointer
= save
;
7935 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
7938 char *end
= input_line_pointer
;
7941 r
= parse_register (name
, &input_line_pointer
);
7942 if (r
&& end
<= input_line_pointer
)
7944 *nextcharP
= *input_line_pointer
;
7945 *input_line_pointer
= 0;
7946 e
->X_op
= O_register
;
7947 e
->X_add_number
= r
- i386_regtab
;
7950 input_line_pointer
= end
;
7956 md_operand (expressionS
*e
)
7958 if (*input_line_pointer
== REGISTER_PREFIX
)
7961 const reg_entry
*r
= parse_real_register (input_line_pointer
, &end
);
7965 e
->X_op
= O_register
;
7966 e
->X_add_number
= r
- i386_regtab
;
7967 input_line_pointer
= end
;
7973 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7974 const char *md_shortopts
= "kVQ:sqn";
7976 const char *md_shortopts
= "qn";
7979 #define OPTION_32 (OPTION_MD_BASE + 0)
7980 #define OPTION_64 (OPTION_MD_BASE + 1)
7981 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
7982 #define OPTION_MARCH (OPTION_MD_BASE + 3)
7983 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
7984 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
7985 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
7986 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
7987 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
7988 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
7989 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
7990 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
7992 struct option md_longopts
[] =
7994 {"32", no_argument
, NULL
, OPTION_32
},
7995 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
7996 {"64", no_argument
, NULL
, OPTION_64
},
7998 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
7999 {"march", required_argument
, NULL
, OPTION_MARCH
},
8000 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
8001 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
8002 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
8003 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
8004 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
8005 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
8006 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
8007 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
8008 {NULL
, no_argument
, NULL
, 0}
8010 size_t md_longopts_size
= sizeof (md_longopts
);
8013 md_parse_option (int c
, char *arg
)
8021 optimize_align_code
= 0;
8028 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8029 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
8030 should be emitted or not. FIXME: Not implemented. */
8034 /* -V: SVR4 argument to print version ID. */
8036 print_version_id ();
8039 /* -k: Ignore for FreeBSD compatibility. */
8044 /* -s: On i386 Solaris, this tells the native assembler to use
8045 .stab instead of .stab.excl. We always use .stab anyhow. */
8048 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
8051 const char **list
, **l
;
8053 list
= bfd_target_list ();
8054 for (l
= list
; *l
!= NULL
; l
++)
8055 if (CONST_STRNEQ (*l
, "elf64-x86-64")
8056 || strcmp (*l
, "coff-x86-64") == 0
8057 || strcmp (*l
, "pe-x86-64") == 0
8058 || strcmp (*l
, "pei-x86-64") == 0)
8060 default_arch
= "x86_64";
8064 as_fatal (_("No compiled in support for x86_64"));
8071 default_arch
= "i386";
8075 #ifdef SVR4_COMMENT_CHARS
8080 n
= (char *) xmalloc (strlen (i386_comment_chars
) + 1);
8082 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
8086 i386_comment_chars
= n
;
8092 arch
= xstrdup (arg
);
8096 as_fatal (_("Invalid -march= option: `%s'"), arg
);
8097 next
= strchr (arch
, '+');
8100 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
8102 if (strcmp (arch
, cpu_arch
[i
].name
) == 0)
8105 cpu_arch_name
= cpu_arch
[i
].name
;
8106 cpu_sub_arch_name
= NULL
;
8107 cpu_arch_flags
= cpu_arch
[i
].flags
;
8108 cpu_arch_isa
= cpu_arch
[i
].type
;
8109 cpu_arch_isa_flags
= cpu_arch
[i
].flags
;
8110 if (!cpu_arch_tune_set
)
8112 cpu_arch_tune
= cpu_arch_isa
;
8113 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
8117 else if (*cpu_arch
[i
].name
== '.'
8118 && strcmp (arch
, cpu_arch
[i
].name
+ 1) == 0)
8120 /* ISA entension. */
8121 i386_cpu_flags flags
;
8122 flags
= cpu_flags_or (cpu_arch_flags
,
8124 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
8126 if (cpu_sub_arch_name
)
8128 char *name
= cpu_sub_arch_name
;
8129 cpu_sub_arch_name
= concat (name
,
8131 (const char *) NULL
);
8135 cpu_sub_arch_name
= xstrdup (cpu_arch
[i
].name
);
8136 cpu_arch_flags
= flags
;
8142 if (i
>= ARRAY_SIZE (cpu_arch
))
8143 as_fatal (_("Invalid -march= option: `%s'"), arg
);
8147 while (next
!= NULL
);
8152 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
8153 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
8155 if (strcmp (arg
, cpu_arch
[i
].name
) == 0)
8157 cpu_arch_tune_set
= 1;
8158 cpu_arch_tune
= cpu_arch
[i
].type
;
8159 cpu_arch_tune_flags
= cpu_arch
[i
].flags
;
8163 if (i
>= ARRAY_SIZE (cpu_arch
))
8164 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
8167 case OPTION_MMNEMONIC
:
8168 if (strcasecmp (arg
, "att") == 0)
8170 else if (strcasecmp (arg
, "intel") == 0)
8173 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg
);
8176 case OPTION_MSYNTAX
:
8177 if (strcasecmp (arg
, "att") == 0)
8179 else if (strcasecmp (arg
, "intel") == 0)
8182 as_fatal (_("Invalid -msyntax= option: `%s'"), arg
);
8185 case OPTION_MINDEX_REG
:
8186 allow_index_reg
= 1;
8189 case OPTION_MNAKED_REG
:
8190 allow_naked_reg
= 1;
8193 case OPTION_MOLD_GCC
:
8197 case OPTION_MSSE2AVX
:
8201 case OPTION_MSSE_CHECK
:
8202 if (strcasecmp (arg
, "error") == 0)
8203 sse_check
= sse_check_error
;
8204 else if (strcasecmp (arg
, "warning") == 0)
8205 sse_check
= sse_check_warning
;
8206 else if (strcasecmp (arg
, "none") == 0)
8207 sse_check
= sse_check_none
;
8209 as_fatal (_("Invalid -msse-check= option: `%s'"), arg
);
8219 md_show_usage (stream
)
8222 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8223 fprintf (stream
, _("\
8225 -V print assembler version number\n\
8228 fprintf (stream
, _("\
8229 -n Do not optimize code alignment\n\
8230 -q quieten some warnings\n"));
8231 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8232 fprintf (stream
, _("\
8235 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
8236 fprintf (stream
, _("\
8237 --32/--64 generate 32bit/64bit code\n"));
8239 #ifdef SVR4_COMMENT_CHARS
8240 fprintf (stream
, _("\
8241 --divide do not treat `/' as a comment character\n"));
8243 fprintf (stream
, _("\
8244 --divide ignored\n"));
8246 fprintf (stream
, _("\
8247 -march=CPU[,+EXTENSION...]\n\
8248 generate code for CPU and EXTENSION, CPU is one of:\n\
8249 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
8250 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
8251 core, core2, k6, k6_2, athlon, k8, amdfam10,\n\
8252 generic32, generic64\n\
8253 EXTENSION is combination of:\n\
8254 mmx, sse, sse2, sse3, ssse3, sse4.1, sse4.2, sse4,\n\
8255 avx, vmx, smx, xsave, movbe, ept, aes, pclmul, fma,\n\
8256 3dnow, 3dnowa, sse4a, sse5, svme, abm, padlock\n"));
8257 fprintf (stream
, _("\
8258 -mtune=CPU optimize for CPU, CPU is one of:\n\
8259 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
8260 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
8261 core, core2, k6, k6_2, athlon, k8, amdfam10,\n\
8262 generic32, generic64\n"));
8263 fprintf (stream
, _("\
8264 -msse2avx encode SSE instructions with VEX prefix\n"));
8265 fprintf (stream
, _("\
8266 -msse-check=[none|error|warning]\n\
8267 check SSE instructions\n"));
8268 fprintf (stream
, _("\
8269 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
8270 fprintf (stream
, _("\
8271 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
8272 fprintf (stream
, _("\
8273 -mindex-reg support pseudo index registers\n"));
8274 fprintf (stream
, _("\
8275 -mnaked-reg don't require `%%' prefix for registers\n"));
8276 fprintf (stream
, _("\
8277 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
8280 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
8281 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (TE_PEP))
8283 /* Pick the target format to use. */
8286 i386_target_format (void)
8288 if (!strcmp (default_arch
, "x86_64"))
8290 set_code_flag (CODE_64BIT
);
8291 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
8293 cpu_arch_isa_flags
.bitfield
.cpui186
= 1;
8294 cpu_arch_isa_flags
.bitfield
.cpui286
= 1;
8295 cpu_arch_isa_flags
.bitfield
.cpui386
= 1;
8296 cpu_arch_isa_flags
.bitfield
.cpui486
= 1;
8297 cpu_arch_isa_flags
.bitfield
.cpui586
= 1;
8298 cpu_arch_isa_flags
.bitfield
.cpui686
= 1;
8299 cpu_arch_isa_flags
.bitfield
.cpup4
= 1;
8300 cpu_arch_isa_flags
.bitfield
.cpummx
= 1;
8301 cpu_arch_isa_flags
.bitfield
.cpusse
= 1;
8302 cpu_arch_isa_flags
.bitfield
.cpusse2
= 1;
8304 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
8306 cpu_arch_tune_flags
.bitfield
.cpui186
= 1;
8307 cpu_arch_tune_flags
.bitfield
.cpui286
= 1;
8308 cpu_arch_tune_flags
.bitfield
.cpui386
= 1;
8309 cpu_arch_tune_flags
.bitfield
.cpui486
= 1;
8310 cpu_arch_tune_flags
.bitfield
.cpui586
= 1;
8311 cpu_arch_tune_flags
.bitfield
.cpui686
= 1;
8312 cpu_arch_tune_flags
.bitfield
.cpup4
= 1;
8313 cpu_arch_tune_flags
.bitfield
.cpummx
= 1;
8314 cpu_arch_tune_flags
.bitfield
.cpusse
= 1;
8315 cpu_arch_tune_flags
.bitfield
.cpusse2
= 1;
8318 else if (!strcmp (default_arch
, "i386"))
8320 set_code_flag (CODE_32BIT
);
8321 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
8323 cpu_arch_isa_flags
.bitfield
.cpui186
= 1;
8324 cpu_arch_isa_flags
.bitfield
.cpui286
= 1;
8325 cpu_arch_isa_flags
.bitfield
.cpui386
= 1;
8327 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
8329 cpu_arch_tune_flags
.bitfield
.cpui186
= 1;
8330 cpu_arch_tune_flags
.bitfield
.cpui286
= 1;
8331 cpu_arch_tune_flags
.bitfield
.cpui386
= 1;
8335 as_fatal (_("Unknown architecture"));
8336 switch (OUTPUT_FLAVOR
)
8339 case bfd_target_coff_flavour
:
8340 return flag_code
== CODE_64BIT
? COFF_TARGET_FORMAT
: "coff-i386";
8343 #ifdef OBJ_MAYBE_AOUT
8344 case bfd_target_aout_flavour
:
8345 return AOUT_TARGET_FORMAT
;
8347 #ifdef OBJ_MAYBE_COFF
8348 case bfd_target_coff_flavour
:
8351 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8352 case bfd_target_elf_flavour
:
8354 if (flag_code
== CODE_64BIT
)
8357 use_rela_relocations
= 1;
8359 return flag_code
== CODE_64BIT
? ELF_TARGET_FORMAT64
: ELF_TARGET_FORMAT
;
8368 #endif /* OBJ_MAYBE_ more than one */
8370 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
8372 i386_elf_emit_arch_note (void)
8374 if (IS_ELF
&& cpu_arch_name
!= NULL
)
8377 asection
*seg
= now_seg
;
8378 subsegT subseg
= now_subseg
;
8379 Elf_Internal_Note i_note
;
8380 Elf_External_Note e_note
;
8381 asection
*note_secp
;
8384 /* Create the .note section. */
8385 note_secp
= subseg_new (".note", 0);
8386 bfd_set_section_flags (stdoutput
,
8388 SEC_HAS_CONTENTS
| SEC_READONLY
);
8390 /* Process the arch string. */
8391 len
= strlen (cpu_arch_name
);
8393 i_note
.namesz
= len
+ 1;
8395 i_note
.type
= NT_ARCH
;
8396 p
= frag_more (sizeof (e_note
.namesz
));
8397 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
8398 p
= frag_more (sizeof (e_note
.descsz
));
8399 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
8400 p
= frag_more (sizeof (e_note
.type
));
8401 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
8402 p
= frag_more (len
+ 1);
8403 strcpy (p
, cpu_arch_name
);
8405 frag_align (2, 0, 0);
8407 subseg_set (seg
, subseg
);
8413 md_undefined_symbol (name
)
8416 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
8417 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
8418 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
8419 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
8423 if (symbol_find (name
))
8424 as_bad (_("GOT already in symbol table"));
8425 GOT_symbol
= symbol_new (name
, undefined_section
,
8426 (valueT
) 0, &zero_address_frag
);
8433 /* Round up a section size to the appropriate boundary. */
8436 md_section_align (segment
, size
)
8437 segT segment ATTRIBUTE_UNUSED
;
8440 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8441 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
8443 /* For a.out, force the section size to be aligned. If we don't do
8444 this, BFD will align it for us, but it will not write out the
8445 final bytes of the section. This may be a bug in BFD, but it is
8446 easier to fix it here since that is how the other a.out targets
8450 align
= bfd_get_section_alignment (stdoutput
, segment
);
8451 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
8458 /* On the i386, PC-relative offsets are relative to the start of the
8459 next instruction. That is, the address of the offset, plus its
8460 size, since the offset is always the last part of the insn. */
8463 md_pcrel_from (fixS
*fixP
)
8465 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
8471 s_bss (int ignore ATTRIBUTE_UNUSED
)
8475 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8477 obj_elf_section_change_hook ();
8479 temp
= get_absolute_expression ();
8480 subseg_set (bss_section
, (subsegT
) temp
);
8481 demand_empty_rest_of_line ();
8487 i386_validate_fix (fixS
*fixp
)
8489 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
8491 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
8495 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
8500 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
8502 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
8509 tc_gen_reloc (section
, fixp
)
8510 asection
*section ATTRIBUTE_UNUSED
;
8514 bfd_reloc_code_real_type code
;
8516 switch (fixp
->fx_r_type
)
8518 case BFD_RELOC_X86_64_PLT32
:
8519 case BFD_RELOC_X86_64_GOT32
:
8520 case BFD_RELOC_X86_64_GOTPCREL
:
8521 case BFD_RELOC_386_PLT32
:
8522 case BFD_RELOC_386_GOT32
:
8523 case BFD_RELOC_386_GOTOFF
:
8524 case BFD_RELOC_386_GOTPC
:
8525 case BFD_RELOC_386_TLS_GD
:
8526 case BFD_RELOC_386_TLS_LDM
:
8527 case BFD_RELOC_386_TLS_LDO_32
:
8528 case BFD_RELOC_386_TLS_IE_32
:
8529 case BFD_RELOC_386_TLS_IE
:
8530 case BFD_RELOC_386_TLS_GOTIE
:
8531 case BFD_RELOC_386_TLS_LE_32
:
8532 case BFD_RELOC_386_TLS_LE
:
8533 case BFD_RELOC_386_TLS_GOTDESC
:
8534 case BFD_RELOC_386_TLS_DESC_CALL
:
8535 case BFD_RELOC_X86_64_TLSGD
:
8536 case BFD_RELOC_X86_64_TLSLD
:
8537 case BFD_RELOC_X86_64_DTPOFF32
:
8538 case BFD_RELOC_X86_64_DTPOFF64
:
8539 case BFD_RELOC_X86_64_GOTTPOFF
:
8540 case BFD_RELOC_X86_64_TPOFF32
:
8541 case BFD_RELOC_X86_64_TPOFF64
:
8542 case BFD_RELOC_X86_64_GOTOFF64
:
8543 case BFD_RELOC_X86_64_GOTPC32
:
8544 case BFD_RELOC_X86_64_GOT64
:
8545 case BFD_RELOC_X86_64_GOTPCREL64
:
8546 case BFD_RELOC_X86_64_GOTPC64
:
8547 case BFD_RELOC_X86_64_GOTPLT64
:
8548 case BFD_RELOC_X86_64_PLTOFF64
:
8549 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
8550 case BFD_RELOC_X86_64_TLSDESC_CALL
:
8552 case BFD_RELOC_VTABLE_ENTRY
:
8553 case BFD_RELOC_VTABLE_INHERIT
:
8555 case BFD_RELOC_32_SECREL
:
8557 code
= fixp
->fx_r_type
;
8559 case BFD_RELOC_X86_64_32S
:
8560 if (!fixp
->fx_pcrel
)
8562 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
8563 code
= fixp
->fx_r_type
;
8569 switch (fixp
->fx_size
)
8572 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8573 _("can not do %d byte pc-relative relocation"),
8575 code
= BFD_RELOC_32_PCREL
;
8577 case 1: code
= BFD_RELOC_8_PCREL
; break;
8578 case 2: code
= BFD_RELOC_16_PCREL
; break;
8579 case 4: code
= BFD_RELOC_32_PCREL
; break;
8581 case 8: code
= BFD_RELOC_64_PCREL
; break;
8587 switch (fixp
->fx_size
)
8590 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8591 _("can not do %d byte relocation"),
8593 code
= BFD_RELOC_32
;
8595 case 1: code
= BFD_RELOC_8
; break;
8596 case 2: code
= BFD_RELOC_16
; break;
8597 case 4: code
= BFD_RELOC_32
; break;
8599 case 8: code
= BFD_RELOC_64
; break;
8606 if ((code
== BFD_RELOC_32
8607 || code
== BFD_RELOC_32_PCREL
8608 || code
== BFD_RELOC_X86_64_32S
)
8610 && fixp
->fx_addsy
== GOT_symbol
)
8613 code
= BFD_RELOC_386_GOTPC
;
8615 code
= BFD_RELOC_X86_64_GOTPC32
;
8617 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
8619 && fixp
->fx_addsy
== GOT_symbol
)
8621 code
= BFD_RELOC_X86_64_GOTPC64
;
8624 rel
= (arelent
*) xmalloc (sizeof (arelent
));
8625 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
8626 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
8628 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
8630 if (!use_rela_relocations
)
8632 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
8633 vtable entry to be used in the relocation's section offset. */
8634 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
8635 rel
->address
= fixp
->fx_offset
;
8639 /* Use the rela in 64bit mode. */
8642 if (!fixp
->fx_pcrel
)
8643 rel
->addend
= fixp
->fx_offset
;
8647 case BFD_RELOC_X86_64_PLT32
:
8648 case BFD_RELOC_X86_64_GOT32
:
8649 case BFD_RELOC_X86_64_GOTPCREL
:
8650 case BFD_RELOC_X86_64_TLSGD
:
8651 case BFD_RELOC_X86_64_TLSLD
:
8652 case BFD_RELOC_X86_64_GOTTPOFF
:
8653 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
8654 case BFD_RELOC_X86_64_TLSDESC_CALL
:
8655 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
8658 rel
->addend
= (section
->vma
8660 + fixp
->fx_addnumber
8661 + md_pcrel_from (fixp
));
8666 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
8667 if (rel
->howto
== NULL
)
8669 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8670 _("cannot represent relocation type %s"),
8671 bfd_get_reloc_code_name (code
));
8672 /* Set howto to a garbage value so that we can keep going. */
8673 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
8674 assert (rel
->howto
!= NULL
);
8681 /* Parse operands using Intel syntax. This implements a recursive descent
8682 parser based on the BNF grammar published in Appendix B of the MASM 6.1
8685 FIXME: We do not recognize the full operand grammar defined in the MASM
8686 documentation. In particular, all the structure/union and
8687 high-level macro operands are missing.
8689 Uppercase words are terminals, lower case words are non-terminals.
8690 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
8691 bars '|' denote choices. Most grammar productions are implemented in
8692 functions called 'intel_<production>'.
8694 Initial production is 'expr'.
8700 binOp & | AND | \| | OR | ^ | XOR
8702 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
8704 constant digits [[ radixOverride ]]
8706 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD | YMMWORD
8744 => expr expr cmpOp e04
8747 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
8748 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
8750 hexdigit a | b | c | d | e | f
8751 | A | B | C | D | E | F
8757 mulOp * | / | % | MOD | << | SHL | >> | SHR
8761 register specialRegister
8765 segmentRegister CS | DS | ES | FS | GS | SS
8767 specialRegister CR0 | CR2 | CR3 | CR4
8768 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
8769 | TR3 | TR4 | TR5 | TR6 | TR7
8771 We simplify the grammar in obvious places (e.g., register parsing is
8772 done by calling parse_register) and eliminate immediate left recursion
8773 to implement a recursive-descent parser.
8777 expr' cmpOp e04 expr'
8829 /* Parsing structure for the intel syntax parser. Used to implement the
8830 semantic actions for the operand grammar. */
8831 struct intel_parser_s
8833 char *op_string
; /* The string being parsed. */
8834 int got_a_float
; /* Whether the operand is a float. */
8835 int op_modifier
; /* Operand modifier. */
8836 int is_mem
; /* 1 if operand is memory reference. */
8837 int in_offset
; /* >=1 if parsing operand of offset. */
8838 int in_bracket
; /* >=1 if parsing operand in brackets. */
8839 const reg_entry
*reg
; /* Last register reference found. */
8840 char *disp
; /* Displacement string being built. */
8841 char *next_operand
; /* Resume point when splitting operands. */
8844 static struct intel_parser_s intel_parser
;
8846 /* Token structure for parsing intel syntax. */
8849 int code
; /* Token code. */
8850 const reg_entry
*reg
; /* Register entry for register tokens. */
8851 char *str
; /* String representation. */
8854 static struct intel_token cur_token
, prev_token
;
8856 /* Token codes for the intel parser. Since T_SHORT is already used
8857 by COFF, undefine it first to prevent a warning. */
8875 #define T_YMMWORD 16
8877 /* Prototypes for intel parser functions. */
8878 static int intel_match_token (int);
8879 static void intel_putback_token (void);
8880 static void intel_get_token (void);
8881 static int intel_expr (void);
8882 static int intel_e04 (void);
8883 static int intel_e05 (void);
8884 static int intel_e06 (void);
8885 static int intel_e09 (void);
8886 static int intel_e10 (void);
8887 static int intel_e11 (void);
8890 i386_intel_operand (char *operand_string
, int got_a_float
)
8894 const reg_entry
*final_base
= i
.base_reg
;
8895 const reg_entry
*final_index
= i
.index_reg
;
8897 p
= intel_parser
.op_string
= xstrdup (operand_string
);
8898 intel_parser
.disp
= (char *) xmalloc (strlen (operand_string
) + 1);
8902 /* Initialize token holders. */
8903 cur_token
.code
= prev_token
.code
= T_NIL
;
8904 cur_token
.reg
= prev_token
.reg
= NULL
;
8905 cur_token
.str
= prev_token
.str
= NULL
;
8907 /* Initialize parser structure. */
8908 intel_parser
.got_a_float
= got_a_float
;
8909 intel_parser
.op_modifier
= 0;
8910 intel_parser
.is_mem
= 0;
8911 intel_parser
.in_offset
= 0;
8912 intel_parser
.in_bracket
= 0;
8913 intel_parser
.reg
= NULL
;
8914 intel_parser
.disp
[0] = '\0';
8915 intel_parser
.next_operand
= NULL
;
8920 /* Read the first token and start the parser. */
8922 ret
= intel_expr ();
8927 if (cur_token
.code
!= T_NIL
)
8929 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
8930 current_templates
->start
->name
, cur_token
.str
);
8933 /* If we found a memory reference, hand it over to i386_displacement
8934 to fill in the rest of the operand fields. */
8935 else if (intel_parser
.is_mem
)
8937 if ((i
.mem_operands
== 1
8938 && !current_templates
->start
->opcode_modifier
.isstring
)
8939 || i
.mem_operands
== 2)
8941 as_bad (_("too many memory references for '%s'"),
8942 current_templates
->start
->name
);
8947 char *s
= intel_parser
.disp
;
8949 if (!quiet_warnings
&& intel_parser
.is_mem
< 0)
8950 /* See the comments in intel_bracket_expr. */
8951 as_warn (_("Treating `%s' as memory reference"), operand_string
);
8953 /* Add the displacement expression. */
8955 ret
= i386_displacement (s
, s
+ strlen (s
));
8958 /* Swap base and index in 16-bit memory operands like
8959 [si+bx]. Since i386_index_check is also used in AT&T
8960 mode we have to do that here. */
8963 && i
.base_reg
->reg_type
.bitfield
.reg16
8964 && i
.index_reg
->reg_type
.bitfield
.reg16
8965 && i
.base_reg
->reg_num
>= 6
8966 && i
.index_reg
->reg_num
< 6)
8968 const reg_entry
*base
= i
.index_reg
;
8970 i
.index_reg
= i
.base_reg
;
8973 ret
= i386_index_check (operand_string
);
8977 i
.types
[this_operand
].bitfield
.mem
= 1;
8983 /* Constant and OFFSET expressions are handled by i386_immediate. */
8984 else if ((intel_parser
.op_modifier
& (1 << T_OFFSET
))
8985 || intel_parser
.reg
== NULL
)
8987 if (i
.mem_operands
< 2 && i
.seg
[i
.mem_operands
])
8989 if (!(intel_parser
.op_modifier
& (1 << T_OFFSET
)))
8990 as_warn (_("Segment override ignored"));
8991 i
.seg
[i
.mem_operands
] = NULL
;
8993 ret
= i386_immediate (intel_parser
.disp
);
8996 if (!final_base
&& !final_index
)
8998 final_base
= i
.base_reg
;
8999 final_index
= i
.index_reg
;
9002 if (intel_parser
.next_operand
&& this_operand
>= MAX_OPERANDS
- 1)
9004 if (!ret
|| !intel_parser
.next_operand
)
9006 intel_parser
.op_string
= intel_parser
.next_operand
;
9007 this_operand
= i
.operands
++;
9008 i
.types
[this_operand
].bitfield
.unspecified
= 1;
9012 free (intel_parser
.disp
);
9014 if (final_base
|| final_index
)
9016 i
.base_reg
= final_base
;
9017 i
.index_reg
= final_index
;
9023 #define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
9027 expr' cmpOp e04 expr'
9032 /* XXX Implement the comparison operators. */
9033 return intel_e04 ();
9050 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
9051 i
.base_reg
= i386_regtab
+ REGNAM_AL
; /* al is invalid as base */
9053 if (cur_token
.code
== '+')
9055 else if (cur_token
.code
== '-')
9056 nregs
= NUM_ADDRESS_REGS
;
9060 strcat (intel_parser
.disp
, cur_token
.str
);
9061 intel_match_token (cur_token
.code
);
9072 int nregs
= ~NUM_ADDRESS_REGS
;
9079 if (cur_token
.code
== '&'
9080 || cur_token
.code
== '|'
9081 || cur_token
.code
== '^')
9085 str
[0] = cur_token
.code
;
9087 strcat (intel_parser
.disp
, str
);
9092 intel_match_token (cur_token
.code
);
9097 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
9098 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 1; /* cl is invalid as base */
9109 int nregs
= ~NUM_ADDRESS_REGS
;
9116 if (cur_token
.code
== '*'
9117 || cur_token
.code
== '/'
9118 || cur_token
.code
== '%')
9122 str
[0] = cur_token
.code
;
9124 strcat (intel_parser
.disp
, str
);
9126 else if (cur_token
.code
== T_SHL
)
9127 strcat (intel_parser
.disp
, "<<");
9128 else if (cur_token
.code
== T_SHR
)
9129 strcat (intel_parser
.disp
, ">>");
9133 intel_match_token (cur_token
.code
);
9138 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
9139 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 2; /* dl is invalid as base */
9157 int nregs
= ~NUM_ADDRESS_REGS
;
9162 /* Don't consume constants here. */
9163 if (cur_token
.code
== '+' || cur_token
.code
== '-')
9165 /* Need to look one token ahead - if the next token
9166 is a constant, the current token is its sign. */
9169 intel_match_token (cur_token
.code
);
9170 next_code
= cur_token
.code
;
9171 intel_putback_token ();
9172 if (next_code
== T_CONST
)
9176 /* e09 OFFSET e09 */
9177 if (cur_token
.code
== T_OFFSET
)
9180 ++intel_parser
.in_offset
;
9184 else if (cur_token
.code
== T_SHORT
)
9185 intel_parser
.op_modifier
|= 1 << T_SHORT
;
9188 else if (cur_token
.code
== '+')
9189 strcat (intel_parser
.disp
, "+");
9194 else if (cur_token
.code
== '-' || cur_token
.code
== '~')
9200 str
[0] = cur_token
.code
;
9202 strcat (intel_parser
.disp
, str
);
9209 intel_match_token (cur_token
.code
);
9217 /* e09' PTR e10 e09' */
9218 if (cur_token
.code
== T_PTR
)
9222 if (prev_token
.code
== T_BYTE
)
9224 suffix
= BYTE_MNEM_SUFFIX
;
9225 i
.types
[this_operand
].bitfield
.byte
= 1;
9228 else if (prev_token
.code
== T_WORD
)
9230 if ((current_templates
->start
->name
[0] == 'l'
9231 && current_templates
->start
->name
[2] == 's'
9232 && current_templates
->start
->name
[3] == 0)
9233 || current_templates
->start
->base_opcode
== 0x62 /* bound */)
9234 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
9235 else if (intel_parser
.got_a_float
== 2) /* "fi..." */
9236 suffix
= SHORT_MNEM_SUFFIX
;
9238 suffix
= WORD_MNEM_SUFFIX
;
9239 i
.types
[this_operand
].bitfield
.word
= 1;
9242 else if (prev_token
.code
== T_DWORD
)
9244 if ((current_templates
->start
->name
[0] == 'l'
9245 && current_templates
->start
->name
[2] == 's'
9246 && current_templates
->start
->name
[3] == 0)
9247 || current_templates
->start
->base_opcode
== 0x62 /* bound */)
9248 suffix
= WORD_MNEM_SUFFIX
;
9249 else if (flag_code
== CODE_16BIT
9250 && (current_templates
->start
->opcode_modifier
.jump
9251 || current_templates
->start
->opcode_modifier
.jumpdword
))
9252 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
9253 else if (intel_parser
.got_a_float
== 1) /* "f..." */
9254 suffix
= SHORT_MNEM_SUFFIX
;
9256 suffix
= LONG_MNEM_SUFFIX
;
9257 i
.types
[this_operand
].bitfield
.dword
= 1;
9260 else if (prev_token
.code
== T_FWORD
)
9262 if (current_templates
->start
->name
[0] == 'l'
9263 && current_templates
->start
->name
[2] == 's'
9264 && current_templates
->start
->name
[3] == 0)
9265 suffix
= LONG_MNEM_SUFFIX
;
9266 else if (!intel_parser
.got_a_float
)
9268 if (flag_code
== CODE_16BIT
)
9269 add_prefix (DATA_PREFIX_OPCODE
);
9270 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
9273 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
9274 i
.types
[this_operand
].bitfield
.fword
= 1;
9277 else if (prev_token
.code
== T_QWORD
)
9279 if (current_templates
->start
->base_opcode
== 0x62 /* bound */
9280 || intel_parser
.got_a_float
== 1) /* "f..." */
9281 suffix
= LONG_MNEM_SUFFIX
;
9283 suffix
= QWORD_MNEM_SUFFIX
;
9284 i
.types
[this_operand
].bitfield
.qword
= 1;
9287 else if (prev_token
.code
== T_TBYTE
)
9289 if (intel_parser
.got_a_float
== 1)
9290 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
9292 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
9295 else if (prev_token
.code
== T_XMMWORD
)
9297 suffix
= XMMWORD_MNEM_SUFFIX
;
9298 i
.types
[this_operand
].bitfield
.xmmword
= 1;
9301 else if (prev_token
.code
== T_YMMWORD
)
9303 suffix
= YMMWORD_MNEM_SUFFIX
;
9304 i
.types
[this_operand
].bitfield
.ymmword
= 1;
9309 as_bad (_("Unknown operand modifier `%s'"), prev_token
.str
);
9313 i
.types
[this_operand
].bitfield
.unspecified
= 0;
9315 /* Operands for jump/call using 'ptr' notation denote absolute
9317 if (current_templates
->start
->opcode_modifier
.jump
9318 || current_templates
->start
->opcode_modifier
.jumpdword
)
9319 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
9321 if (current_templates
->start
->base_opcode
== 0x8d /* lea */)
9325 else if (i
.suffix
!= suffix
)
9327 as_bad (_("Conflicting operand modifiers"));
9333 /* e09' : e10 e09' */
9334 else if (cur_token
.code
== ':')
9336 if (prev_token
.code
!= T_REG
)
9338 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
9339 segment/group identifier (which we don't have), using comma
9340 as the operand separator there is even less consistent, since
9341 there all branches only have a single operand. */
9342 if (this_operand
!= 0
9343 || intel_parser
.in_offset
9344 || intel_parser
.in_bracket
9345 || (!current_templates
->start
->opcode_modifier
.jump
9346 && !current_templates
->start
->opcode_modifier
.jumpdword
9347 && !current_templates
->start
->opcode_modifier
.jumpintersegment
9348 && !current_templates
->start
->operand_types
[0].bitfield
.jumpabsolute
))
9349 return intel_match_token (T_NIL
);
9350 /* Remember the start of the 2nd operand and terminate 1st
9352 XXX This isn't right, yet (when SSSS:OOOO is right operand of
9353 another expression), but it gets at least the simplest case
9354 (a plain number or symbol on the left side) right. */
9355 intel_parser
.next_operand
= intel_parser
.op_string
;
9356 *--intel_parser
.op_string
= '\0';
9357 return intel_match_token (':');
9365 intel_match_token (cur_token
.code
);
9371 --intel_parser
.in_offset
;
9374 if (NUM_ADDRESS_REGS
> nregs
)
9376 as_bad (_("Invalid operand to `OFFSET'"));
9379 intel_parser
.op_modifier
|= 1 << T_OFFSET
;
9382 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
9383 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 3; /* bl is invalid as base */
9388 intel_bracket_expr (void)
9390 int was_offset
= intel_parser
.op_modifier
& (1 << T_OFFSET
);
9391 const char *start
= intel_parser
.op_string
;
9394 if (i
.op
[this_operand
].regs
)
9395 return intel_match_token (T_NIL
);
9397 intel_match_token ('[');
9399 /* Mark as a memory operand only if it's not already known to be an
9400 offset expression. If it's an offset expression, we need to keep
9402 if (!intel_parser
.in_offset
)
9404 ++intel_parser
.in_bracket
;
9406 /* Operands for jump/call inside brackets denote absolute addresses. */
9407 if (current_templates
->start
->opcode_modifier
.jump
9408 || current_templates
->start
->opcode_modifier
.jumpdword
)
9409 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
9411 /* Unfortunately gas always diverged from MASM in a respect that can't
9412 be easily fixed without risking to break code sequences likely to be
9413 encountered (the testsuite even check for this): MASM doesn't consider
9414 an expression inside brackets unconditionally as a memory reference.
9415 When that is e.g. a constant, an offset expression, or the sum of the
9416 two, this is still taken as a constant load. gas, however, always
9417 treated these as memory references. As a compromise, we'll try to make
9418 offset expressions inside brackets work the MASM way (since that's
9419 less likely to be found in real world code), but make constants alone
9420 continue to work the traditional gas way. In either case, issue a
9422 intel_parser
.op_modifier
&= ~was_offset
;
9425 strcat (intel_parser
.disp
, "[");
9427 /* Add a '+' to the displacement string if necessary. */
9428 if (*intel_parser
.disp
!= '\0'
9429 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
9430 strcat (intel_parser
.disp
, "+");
9433 && (len
= intel_parser
.op_string
- start
- 1,
9434 intel_match_token (']')))
9436 /* Preserve brackets when the operand is an offset expression. */
9437 if (intel_parser
.in_offset
)
9438 strcat (intel_parser
.disp
, "]");
9441 --intel_parser
.in_bracket
;
9442 if (i
.base_reg
|| i
.index_reg
)
9443 intel_parser
.is_mem
= 1;
9444 if (!intel_parser
.is_mem
)
9446 if (!(intel_parser
.op_modifier
& (1 << T_OFFSET
)))
9447 /* Defer the warning until all of the operand was parsed. */
9448 intel_parser
.is_mem
= -1;
9449 else if (!quiet_warnings
)
9450 as_warn (_("`[%.*s]' taken to mean just `%.*s'"),
9451 len
, start
, len
, start
);
9454 intel_parser
.op_modifier
|= was_offset
;
9471 while (cur_token
.code
== '[')
9473 if (!intel_bracket_expr ())
9499 switch (cur_token
.code
)
9503 intel_match_token ('(');
9504 strcat (intel_parser
.disp
, "(");
9506 if (intel_expr () && intel_match_token (')'))
9508 strcat (intel_parser
.disp
, ")");
9515 return intel_bracket_expr ();
9520 strcat (intel_parser
.disp
, cur_token
.str
);
9521 intel_match_token (cur_token
.code
);
9523 /* Mark as a memory operand only if it's not already known to be an
9524 offset expression. */
9525 if (!intel_parser
.in_offset
)
9526 intel_parser
.is_mem
= 1;
9533 const reg_entry
*reg
= intel_parser
.reg
= cur_token
.reg
;
9535 intel_match_token (T_REG
);
9537 /* Check for segment change. */
9538 if (cur_token
.code
== ':')
9540 if (!reg
->reg_type
.bitfield
.sreg2
9541 && !reg
->reg_type
.bitfield
.sreg3
)
9543 as_bad (_("`%s' is not a valid segment register"),
9547 else if (i
.mem_operands
>= 2)
9548 as_warn (_("Segment override ignored"));
9549 else if (i
.seg
[i
.mem_operands
])
9550 as_warn (_("Extra segment override ignored"));
9553 if (!intel_parser
.in_offset
)
9554 intel_parser
.is_mem
= 1;
9555 switch (reg
->reg_num
)
9558 i
.seg
[i
.mem_operands
] = &es
;
9561 i
.seg
[i
.mem_operands
] = &cs
;
9564 i
.seg
[i
.mem_operands
] = &ss
;
9567 i
.seg
[i
.mem_operands
] = &ds
;
9570 i
.seg
[i
.mem_operands
] = &fs
;
9573 i
.seg
[i
.mem_operands
] = &gs
;
9579 else if (reg
->reg_type
.bitfield
.sreg3
&& reg
->reg_num
== RegFlat
)
9581 as_bad (_("cannot use `FLAT' here"));
9585 /* Not a segment register. Check for register scaling. */
9586 else if (cur_token
.code
== '*')
9588 if (!intel_parser
.in_bracket
)
9590 as_bad (_("Register scaling only allowed in memory operands"));
9594 if (reg
->reg_type
.bitfield
.reg16
) /* Disallow things like [si*1]. */
9595 reg
= i386_regtab
+ REGNAM_AX
+ 4; /* sp is invalid as index */
9596 else if (i
.index_reg
)
9597 reg
= i386_regtab
+ REGNAM_EAX
+ 4; /* esp is invalid as index */
9599 /* What follows must be a valid scale. */
9600 intel_match_token ('*');
9602 i
.types
[this_operand
].bitfield
.baseindex
= 1;
9604 /* Set the scale after setting the register (otherwise,
9605 i386_scale will complain) */
9606 if (cur_token
.code
== '+' || cur_token
.code
== '-')
9608 char *str
, sign
= cur_token
.code
;
9609 intel_match_token (cur_token
.code
);
9610 if (cur_token
.code
!= T_CONST
)
9612 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
9616 str
= (char *) xmalloc (strlen (cur_token
.str
) + 2);
9617 strcpy (str
+ 1, cur_token
.str
);
9619 if (!i386_scale (str
))
9623 else if (!i386_scale (cur_token
.str
))
9625 intel_match_token (cur_token
.code
);
9628 /* No scaling. If this is a memory operand, the register is either a
9629 base register (first occurrence) or an index register (second
9631 else if (intel_parser
.in_bracket
)
9636 else if (!i
.index_reg
)
9640 as_bad (_("Too many register references in memory operand"));
9644 i
.types
[this_operand
].bitfield
.baseindex
= 1;
9647 /* It's neither base nor index. */
9648 else if (!intel_parser
.in_offset
&& !intel_parser
.is_mem
)
9650 i386_operand_type temp
= reg
->reg_type
;
9651 temp
.bitfield
.baseindex
= 0;
9652 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
9654 i
.types
[this_operand
].bitfield
.unspecified
= 0;
9655 i
.op
[this_operand
].regs
= reg
;
9660 as_bad (_("Invalid use of register"));
9664 /* Since registers are not part of the displacement string (except
9665 when we're parsing offset operands), we may need to remove any
9666 preceding '+' from the displacement string. */
9667 if (*intel_parser
.disp
!= '\0'
9668 && !intel_parser
.in_offset
)
9670 char *s
= intel_parser
.disp
;
9671 s
+= strlen (s
) - 1;
9696 intel_match_token (cur_token
.code
);
9698 if (cur_token
.code
== T_PTR
)
9701 /* It must have been an identifier. */
9702 intel_putback_token ();
9703 cur_token
.code
= T_ID
;
9709 if (!intel_parser
.in_offset
&& intel_parser
.is_mem
<= 0)
9713 /* The identifier represents a memory reference only if it's not
9714 preceded by an offset modifier and if it's not an equate. */
9715 symbolP
= symbol_find(cur_token
.str
);
9716 if (!symbolP
|| S_GET_SEGMENT(symbolP
) != absolute_section
)
9717 intel_parser
.is_mem
= 1;
9725 char *save_str
, sign
= 0;
9727 /* Allow constants that start with `+' or `-'. */
9728 if (cur_token
.code
== '-' || cur_token
.code
== '+')
9730 sign
= cur_token
.code
;
9731 intel_match_token (cur_token
.code
);
9732 if (cur_token
.code
!= T_CONST
)
9734 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
9740 save_str
= (char *) xmalloc (strlen (cur_token
.str
) + 2);
9741 strcpy (save_str
+ !!sign
, cur_token
.str
);
9745 /* Get the next token to check for register scaling. */
9746 intel_match_token (cur_token
.code
);
9748 /* Check if this constant is a scaling factor for an
9750 if (cur_token
.code
== '*')
9752 if (intel_match_token ('*') && cur_token
.code
== T_REG
)
9754 const reg_entry
*reg
= cur_token
.reg
;
9756 if (!intel_parser
.in_bracket
)
9758 as_bad (_("Register scaling only allowed "
9759 "in memory operands"));
9763 /* Disallow things like [1*si].
9764 sp and esp are invalid as index. */
9765 if (reg
->reg_type
.bitfield
.reg16
)
9766 reg
= i386_regtab
+ REGNAM_AX
+ 4;
9767 else if (i
.index_reg
)
9768 reg
= i386_regtab
+ REGNAM_EAX
+ 4;
9770 /* The constant is followed by `* reg', so it must be
9773 i
.types
[this_operand
].bitfield
.baseindex
= 1;
9775 /* Set the scale after setting the register (otherwise,
9776 i386_scale will complain) */
9777 if (!i386_scale (save_str
))
9779 intel_match_token (T_REG
);
9781 /* Since registers are not part of the displacement
9782 string, we may need to remove any preceding '+' from
9783 the displacement string. */
9784 if (*intel_parser
.disp
!= '\0')
9786 char *s
= intel_parser
.disp
;
9787 s
+= strlen (s
) - 1;
9797 /* The constant was not used for register scaling. Since we have
9798 already consumed the token following `*' we now need to put it
9799 back in the stream. */
9800 intel_putback_token ();
9803 /* Add the constant to the displacement string. */
9804 strcat (intel_parser
.disp
, save_str
);
9811 as_bad (_("Unrecognized token '%s'"), cur_token
.str
);
9815 /* Match the given token against cur_token. If they match, read the next
9816 token from the operand string. */
9818 intel_match_token (int code
)
9820 if (cur_token
.code
== code
)
9827 as_bad (_("Unexpected token `%s'"), cur_token
.str
);
9832 /* Read a new token from intel_parser.op_string and store it in cur_token. */
9834 intel_get_token (void)
9837 const reg_entry
*reg
;
9838 struct intel_token new_token
;
9840 new_token
.code
= T_NIL
;
9841 new_token
.reg
= NULL
;
9842 new_token
.str
= NULL
;
9844 /* Free the memory allocated to the previous token and move
9845 cur_token to prev_token. */
9847 free (prev_token
.str
);
9849 prev_token
= cur_token
;
9851 /* Skip whitespace. */
9852 while (is_space_char (*intel_parser
.op_string
))
9853 intel_parser
.op_string
++;
9855 /* Return an empty token if we find nothing else on the line. */
9856 if (*intel_parser
.op_string
== '\0')
9858 cur_token
= new_token
;
9862 /* The new token cannot be larger than the remainder of the operand
9864 new_token
.str
= (char *) xmalloc (strlen (intel_parser
.op_string
) + 1);
9865 new_token
.str
[0] = '\0';
9867 if (strchr ("0123456789", *intel_parser
.op_string
))
9869 char *p
= new_token
.str
;
9870 char *q
= intel_parser
.op_string
;
9871 new_token
.code
= T_CONST
;
9873 /* Allow any kind of identifier char to encompass floating point and
9874 hexadecimal numbers. */
9875 while (is_identifier_char (*q
))
9879 /* Recognize special symbol names [0-9][bf]. */
9880 if (strlen (intel_parser
.op_string
) == 2
9881 && (intel_parser
.op_string
[1] == 'b'
9882 || intel_parser
.op_string
[1] == 'f'))
9883 new_token
.code
= T_ID
;
9886 else if ((reg
= parse_register (intel_parser
.op_string
, &end_op
)) != NULL
)
9888 size_t len
= end_op
- intel_parser
.op_string
;
9890 new_token
.code
= T_REG
;
9891 new_token
.reg
= reg
;
9893 memcpy (new_token
.str
, intel_parser
.op_string
, len
);
9894 new_token
.str
[len
] = '\0';
9897 else if (is_identifier_char (*intel_parser
.op_string
))
9899 char *p
= new_token
.str
;
9900 char *q
= intel_parser
.op_string
;
9902 /* A '.' or '$' followed by an identifier char is an identifier.
9903 Otherwise, it's operator '.' followed by an expression. */
9904 if ((*q
== '.' || *q
== '$') && !is_identifier_char (*(q
+ 1)))
9906 new_token
.code
= '.';
9907 new_token
.str
[0] = '.';
9908 new_token
.str
[1] = '\0';
9912 while (is_identifier_char (*q
) || *q
== '@')
9916 if (strcasecmp (new_token
.str
, "NOT") == 0)
9917 new_token
.code
= '~';
9919 else if (strcasecmp (new_token
.str
, "MOD") == 0)
9920 new_token
.code
= '%';
9922 else if (strcasecmp (new_token
.str
, "AND") == 0)
9923 new_token
.code
= '&';
9925 else if (strcasecmp (new_token
.str
, "OR") == 0)
9926 new_token
.code
= '|';
9928 else if (strcasecmp (new_token
.str
, "XOR") == 0)
9929 new_token
.code
= '^';
9931 else if (strcasecmp (new_token
.str
, "SHL") == 0)
9932 new_token
.code
= T_SHL
;
9934 else if (strcasecmp (new_token
.str
, "SHR") == 0)
9935 new_token
.code
= T_SHR
;
9937 else if (strcasecmp (new_token
.str
, "BYTE") == 0)
9938 new_token
.code
= T_BYTE
;
9940 else if (strcasecmp (new_token
.str
, "WORD") == 0)
9941 new_token
.code
= T_WORD
;
9943 else if (strcasecmp (new_token
.str
, "DWORD") == 0)
9944 new_token
.code
= T_DWORD
;
9946 else if (strcasecmp (new_token
.str
, "FWORD") == 0)
9947 new_token
.code
= T_FWORD
;
9949 else if (strcasecmp (new_token
.str
, "QWORD") == 0)
9950 new_token
.code
= T_QWORD
;
9952 else if (strcasecmp (new_token
.str
, "TBYTE") == 0
9953 /* XXX remove (gcc still uses it) */
9954 || strcasecmp (new_token
.str
, "XWORD") == 0)
9955 new_token
.code
= T_TBYTE
;
9957 else if (strcasecmp (new_token
.str
, "XMMWORD") == 0
9958 || strcasecmp (new_token
.str
, "OWORD") == 0)
9959 new_token
.code
= T_XMMWORD
;
9961 else if (strcasecmp (new_token
.str
, "YMMWORD") == 0)
9962 new_token
.code
= T_YMMWORD
;
9964 else if (strcasecmp (new_token
.str
, "PTR") == 0)
9965 new_token
.code
= T_PTR
;
9967 else if (strcasecmp (new_token
.str
, "SHORT") == 0)
9968 new_token
.code
= T_SHORT
;
9970 else if (strcasecmp (new_token
.str
, "OFFSET") == 0)
9972 new_token
.code
= T_OFFSET
;
9974 /* ??? This is not mentioned in the MASM grammar but gcc
9975 makes use of it with -mintel-syntax. OFFSET may be
9976 followed by FLAT: */
9977 if (strncasecmp (q
, " FLAT:", 6) == 0)
9978 strcat (new_token
.str
, " FLAT:");
9982 new_token
.code
= T_ID
;
9986 else if (strchr ("+-/*%|&^:[]()~", *intel_parser
.op_string
))
9988 new_token
.code
= *intel_parser
.op_string
;
9989 new_token
.str
[0] = *intel_parser
.op_string
;
9990 new_token
.str
[1] = '\0';
9993 else if (strchr ("<>", *intel_parser
.op_string
)
9994 && *intel_parser
.op_string
== *(intel_parser
.op_string
+ 1))
9996 new_token
.code
= *intel_parser
.op_string
== '<' ? T_SHL
: T_SHR
;
9997 new_token
.str
[0] = *intel_parser
.op_string
;
9998 new_token
.str
[1] = *intel_parser
.op_string
;
9999 new_token
.str
[2] = '\0';
10003 as_bad (_("Unrecognized token `%s'"), intel_parser
.op_string
);
10005 intel_parser
.op_string
+= strlen (new_token
.str
);
10006 cur_token
= new_token
;
10009 /* Put cur_token back into the token stream and make cur_token point to
10012 intel_putback_token (void)
10014 if (cur_token
.code
!= T_NIL
)
10016 intel_parser
.op_string
-= strlen (cur_token
.str
);
10017 free (cur_token
.str
);
10019 cur_token
= prev_token
;
10021 /* Forget prev_token. */
10022 prev_token
.code
= T_NIL
;
10023 prev_token
.reg
= NULL
;
10024 prev_token
.str
= NULL
;
10028 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
10030 int saved_naked_reg
;
10031 char saved_register_dot
;
10033 saved_naked_reg
= allow_naked_reg
;
10034 allow_naked_reg
= 1;
10035 saved_register_dot
= register_chars
['.'];
10036 register_chars
['.'] = '.';
10037 allow_pseudo_reg
= 1;
10038 expression_and_evaluate (exp
);
10039 allow_pseudo_reg
= 0;
10040 register_chars
['.'] = saved_register_dot
;
10041 allow_naked_reg
= saved_naked_reg
;
10043 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
10045 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
10047 exp
->X_op
= O_constant
;
10048 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
10049 .dw2_regnum
[flag_code
>> 1];
10052 exp
->X_op
= O_illegal
;
10057 tc_x86_frame_initial_instructions (void)
10059 static unsigned int sp_regno
[2];
10061 if (!sp_regno
[flag_code
>> 1])
10063 char *saved_input
= input_line_pointer
;
10064 char sp
[][4] = {"esp", "rsp"};
10067 input_line_pointer
= sp
[flag_code
>> 1];
10068 tc_x86_parse_to_dw2regnum (&exp
);
10069 assert (exp
.X_op
== O_constant
);
10070 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
10071 input_line_pointer
= saved_input
;
10074 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
10075 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
10079 i386_elf_section_type (const char *str
, size_t len
)
10081 if (flag_code
== CODE_64BIT
10082 && len
== sizeof ("unwind") - 1
10083 && strncmp (str
, "unwind", 6) == 0)
10084 return SHT_X86_64_UNWIND
;
10091 i386_solaris_fix_up_eh_frame (segT sec
)
10093 if (flag_code
== CODE_64BIT
)
10094 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
10100 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
10104 expr
.X_op
= O_secrel
;
10105 expr
.X_add_symbol
= symbol
;
10106 expr
.X_add_number
= 0;
10107 emit_expr (&expr
, size
);
10111 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10112 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
10115 x86_64_section_letter (int letter
, char **ptr_msg
)
10117 if (flag_code
== CODE_64BIT
)
10120 return SHF_X86_64_LARGE
;
10122 *ptr_msg
= _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
10125 *ptr_msg
= _("Bad .section directive: want a,w,x,M,S,G,T in string");
10130 x86_64_section_word (char *str
, size_t len
)
10132 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
10133 return SHF_X86_64_LARGE
;
10139 handle_large_common (int small ATTRIBUTE_UNUSED
)
10141 if (flag_code
!= CODE_64BIT
)
10143 s_comm_internal (0, elf_common_parse
);
10144 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
10148 static segT lbss_section
;
10149 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
10150 asection
*saved_bss_section
= bss_section
;
10152 if (lbss_section
== NULL
)
10154 flagword applicable
;
10155 segT seg
= now_seg
;
10156 subsegT subseg
= now_subseg
;
10158 /* The .lbss section is for local .largecomm symbols. */
10159 lbss_section
= subseg_new (".lbss", 0);
10160 applicable
= bfd_applicable_section_flags (stdoutput
);
10161 bfd_set_section_flags (stdoutput
, lbss_section
,
10162 applicable
& SEC_ALLOC
);
10163 seg_info (lbss_section
)->bss
= 1;
10165 subseg_set (seg
, subseg
);
10168 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
10169 bss_section
= lbss_section
;
10171 s_comm_internal (0, elf_common_parse
);
10173 elf_com_section_ptr
= saved_com_section_ptr
;
10174 bss_section
= saved_bss_section
;
10177 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */