1 /* tc-m68k.c -- Assemble for the m68k family
2 Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
27 #include "dwarf2dbg.h"
29 #include "opcode/m68k.h"
30 #include "m68k-parse.h"
36 /* This string holds the chars that always start a comment. If the
37 pre-processor is disabled, these aren't very useful. The macro
38 tc_comment_chars points to this. We use this, rather than the
39 usual comment_chars, so that the --bitwise-or option will work. */
40 #if defined (TE_SVR4) || defined (TE_DELTA)
41 const char *m68k_comment_chars
= "|#";
43 const char *m68k_comment_chars
= "|";
46 /* This array holds the chars that only start a comment at the beginning of
47 a line. If the line seems to have the form '# 123 filename'
48 .line and .file directives will appear in the pre-processed output */
49 /* Note that input_file.c hand checks for '#' at the beginning of the
50 first line of the input file. This is because the compiler outputs
51 #NO_APP at the beginning of its output. */
52 /* Also note that comments like this one will always work. */
53 const char line_comment_chars
[] = "#*";
55 const char line_separator_chars
[] = ";";
57 /* Chars that can be used to separate mant from exp in floating point nums */
58 CONST
char EXP_CHARS
[] = "eE";
60 /* Chars that mean this number is a floating point constant, as
61 in "0f12.456" or "0d1.2345e12". */
63 CONST
char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
65 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
66 changed in read.c . Ideally it shouldn't have to know about it at all,
67 but nothing is ideal around here. */
69 const int md_reloc_size
= 8; /* Size of relocation record */
71 /* Are we trying to generate PIC code? If so, absolute references
72 ought to be made into linkage table references or pc-relative
73 references. Not implemented. For ELF there are other means
74 to denote pic relocations. */
77 static int flag_short_refs
; /* -l option */
78 static int flag_long_jumps
; /* -S option */
79 static int flag_keep_pcrel
; /* --pcrel option. */
81 #ifdef REGISTER_PREFIX_OPTIONAL
82 int flag_reg_prefix_optional
= REGISTER_PREFIX_OPTIONAL
;
84 int flag_reg_prefix_optional
;
87 /* Whether --register-prefix-optional was used on the command line. */
88 static int reg_prefix_optional_seen
;
90 /* The floating point coprocessor to use by default. */
91 static enum m68k_register m68k_float_copnum
= COP1
;
93 /* If this is non-zero, then references to number(%pc) will be taken
94 to refer to number, rather than to %pc + number. */
95 static int m68k_abspcadd
;
97 /* If this is non-zero, then the quick forms of the move, add, and sub
98 instructions are used when possible. */
99 static int m68k_quick
= 1;
101 /* If this is non-zero, then if the size is not specified for a base
102 or outer displacement, the assembler assumes that the size should
104 static int m68k_rel32
= 1;
106 /* This is non-zero if m68k_rel32 was set from the command line. */
107 static int m68k_rel32_from_cmdline
;
109 /* The default width to use for an index register when using a base
111 static enum m68k_size m68k_index_width_default
= SIZE_LONG
;
113 /* We want to warn if any text labels are misaligned. In order to get
114 the right line number, we need to record the line number for each
119 struct label_line
*next
;
126 /* The list of labels. */
128 static struct label_line
*labels
;
130 /* The current label. */
132 static struct label_line
*current_label
;
134 /* Its an arbitrary name: This means I don't approve of it */
135 /* See flames below */
136 static struct obstack robyn
;
140 const char *m_operands
;
141 unsigned long m_opcode
;
145 struct m68k_incant
*m_next
;
148 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
149 #define gettwo(x) (((x)->m_opcode)&0xffff)
151 static const enum m68k_register m68000_control_regs
[] = { 0 };
152 static const enum m68k_register m68010_control_regs
[] = {
156 static const enum m68k_register m68020_control_regs
[] = {
157 SFC
, DFC
, USP
, VBR
, CACR
, CAAR
, MSP
, ISP
,
160 static const enum m68k_register m68040_control_regs
[] = {
161 SFC
, DFC
, CACR
, TC
, ITT0
, ITT1
, DTT0
, DTT1
,
162 USP
, VBR
, MSP
, ISP
, MMUSR
, URP
, SRP
,
165 static const enum m68k_register m68060_control_regs
[] = {
166 SFC
, DFC
, CACR
, TC
, ITT0
, ITT1
, DTT0
, DTT1
, BUSCR
,
167 USP
, VBR
, URP
, SRP
, PCR
,
170 static const enum m68k_register mcf_control_regs
[] = {
171 CACR
, TC
, ITT0
, ITT1
, DTT0
, DTT1
, VBR
, ROMBAR
,
172 RAMBAR0
, RAMBAR1
, MBAR
,
175 #define cpu32_control_regs m68010_control_regs
177 static const enum m68k_register
*control_regs
;
179 /* internal form of a 68020 instruction */
183 const char *args
; /* list of opcode info */
186 int numo
; /* Number of shorts in opcode */
189 struct m68k_op operands
[6];
191 int nexp
; /* number of exprs in use */
192 struct m68k_exp exprs
[4];
194 int nfrag
; /* Number of frags we have to produce */
197 int fragoff
; /* Where in the current opcode the frag ends */
204 int nrel
; /* Num of reloc strucs in use */
211 /* In a pc relative address the difference between the address
212 of the offset and the address that the offset is relative
213 to. This depends on the addressing mode. Basically this
214 is the value to put in the offset field to address the
215 first byte of the offset, without regarding the special
216 significance of some values (in the branch instruction, for
220 /* Whether this expression needs special pic relocation, and if
222 enum pic_relocation pic_reloc
;
225 reloc
[5]; /* Five is enough??? */
228 #define cpu_of_arch(x) ((x) & (m68000up|mcf))
229 #define float_of_arch(x) ((x) & mfloat)
230 #define mmu_of_arch(x) ((x) & mmmu)
231 #define arch_coldfire_p(x) (((x) & mcf) != 0)
233 /* Macros for determining if cpu supports a specific addressing mode */
234 #define HAVE_LONG_BRANCH(x) ((x) & (m68020|m68030|m68040|m68060|cpu32|mcf5407))
236 static struct m68k_it the_ins
; /* the instruction being assembled */
238 #define op(ex) ((ex)->exp.X_op)
239 #define adds(ex) ((ex)->exp.X_add_symbol)
240 #define subs(ex) ((ex)->exp.X_op_symbol)
241 #define offs(ex) ((ex)->exp.X_add_number)
243 /* Macros for adding things to the m68k_it struct */
245 #define addword(w) the_ins.opcode[the_ins.numo++]=(w)
247 /* Static functions. */
249 static void insop
PARAMS ((int, const struct m68k_incant
*));
250 static void add_fix
PARAMS ((int, struct m68k_exp
*, int, int));
251 static void add_frag
PARAMS ((symbolS
*, offsetT
, int));
253 /* Like addword, but goes BEFORE general operands */
257 const struct m68k_incant
*opcode
;
260 for (z
= the_ins
.numo
; z
> opcode
->m_codenum
; --z
)
261 the_ins
.opcode
[z
]=the_ins
.opcode
[z
-1];
262 for (z
= 0;z
< the_ins
.nrel
; z
++)
263 the_ins
.reloc
[z
].n
+=2;
264 for (z
= 0; z
< the_ins
.nfrag
; z
++)
265 the_ins
.fragb
[z
].fragoff
++;
266 the_ins
.opcode
[opcode
->m_codenum
]=w
;
270 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
273 add_fix (width
, exp
, pc_rel
, pc_fix
)
275 struct m68k_exp
*exp
;
279 the_ins
.reloc
[the_ins
.nrel
].n
= ((width
== 'B' || width
== '3')
283 : (the_ins
.numo
*2)));
284 the_ins
.reloc
[the_ins
.nrel
].exp
= exp
->exp
;
285 the_ins
.reloc
[the_ins
.nrel
].wid
= width
;
286 the_ins
.reloc
[the_ins
.nrel
].pcrel_fix
= pc_fix
;
288 the_ins
.reloc
[the_ins
.nrel
].pic_reloc
= exp
->pic_reloc
;
290 the_ins
.reloc
[the_ins
.nrel
++].pcrel
= pc_rel
;
293 /* Cause an extra frag to be generated here, inserting up to 10 bytes
294 (that value is chosen in the frag_var call in md_assemble). TYPE
295 is the subtype of the frag to be generated; its primary type is
296 rs_machine_dependent.
298 The TYPE parameter is also used by md_convert_frag_1 and
299 md_estimate_size_before_relax. The appropriate type of fixup will
300 be emitted by md_convert_frag_1.
302 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
304 add_frag (add
, off
, type
)
309 the_ins
.fragb
[the_ins
.nfrag
].fragoff
=the_ins
.numo
;
310 the_ins
.fragb
[the_ins
.nfrag
].fadd
=add
;
311 the_ins
.fragb
[the_ins
.nfrag
].foff
=off
;
312 the_ins
.fragb
[the_ins
.nfrag
++].fragty
=type
;
316 (op (ex) != O_constant && op (ex) != O_big)
318 static char *crack_operand
PARAMS ((char *str
, struct m68k_op
*opP
));
319 static int get_num
PARAMS ((struct m68k_exp
*exp
, int ok
));
320 static void m68k_ip
PARAMS ((char *));
321 static void insert_reg
PARAMS ((const char *, int));
322 static void select_control_regs
PARAMS ((void));
323 static void init_regtable
PARAMS ((void));
324 static int reverse_16_bits
PARAMS ((int in
));
325 static int reverse_8_bits
PARAMS ((int in
));
326 static void install_gen_operand
PARAMS ((int mode
, int val
));
327 static void install_operand
PARAMS ((int mode
, int val
));
328 static void s_bss
PARAMS ((int));
329 static void s_data1
PARAMS ((int));
330 static void s_data2
PARAMS ((int));
331 static void s_even
PARAMS ((int));
332 static void s_proc
PARAMS ((int));
333 static void mri_chip
PARAMS ((void));
334 static void s_chip
PARAMS ((int));
335 static void s_fopt
PARAMS ((int));
336 static void s_opt
PARAMS ((int));
337 static void s_reg
PARAMS ((int));
338 static void s_restore
PARAMS ((int));
339 static void s_save
PARAMS ((int));
340 static void s_mri_if
PARAMS ((int));
341 static void s_mri_else
PARAMS ((int));
342 static void s_mri_endi
PARAMS ((int));
343 static void s_mri_break
PARAMS ((int));
344 static void s_mri_next
PARAMS ((int));
345 static void s_mri_for
PARAMS ((int));
346 static void s_mri_endf
PARAMS ((int));
347 static void s_mri_repeat
PARAMS ((int));
348 static void s_mri_until
PARAMS ((int));
349 static void s_mri_while
PARAMS ((int));
350 static void s_mri_endw
PARAMS ((int));
351 static void md_apply_fix_2
PARAMS ((fixS
*, offsetT
));
352 static void md_convert_frag_1
PARAMS ((fragS
*));
354 static int current_architecture
;
363 static const struct m68k_cpu archs
[] =
365 { m68000
, "68000", 0 },
366 { m68010
, "68010", 0 },
367 { m68020
, "68020", 0 },
368 { m68030
, "68030", 0 },
369 { m68040
, "68040", 0 },
370 { m68060
, "68060", 0 },
371 { cpu32
, "cpu32", 0 },
372 { m68881
, "68881", 0 },
373 { m68851
, "68851", 0 },
374 { mcf5200
, "5200", 0 },
375 { mcf5206e
, "5206e", 0 },
376 { mcf5307
, "5307", 0},
377 { mcf5407
, "5407", 0},
378 /* Aliases (effectively, so far as gas is concerned) for the above
380 { m68020
, "68k", 1 },
381 { m68000
, "68008", 1 },
382 { m68000
, "68302", 1 },
383 { m68000
, "68306", 1 },
384 { m68000
, "68307", 1 },
385 { m68000
, "68322", 1 },
386 { m68000
, "68356", 1 },
387 { m68000
, "68ec000", 1 },
388 { m68000
, "68hc000", 1 },
389 { m68000
, "68hc001", 1 },
390 { m68020
, "68ec020", 1 },
391 { m68030
, "68ec030", 1 },
392 { m68040
, "68ec040", 1 },
393 { m68060
, "68ec060", 1 },
394 { cpu32
, "68330", 1 },
395 { cpu32
, "68331", 1 },
396 { cpu32
, "68332", 1 },
397 { cpu32
, "68333", 1 },
398 { cpu32
, "68334", 1 },
399 { cpu32
, "68336", 1 },
400 { cpu32
, "68340", 1 },
401 { cpu32
, "68341", 1 },
402 { cpu32
, "68349", 1 },
403 { cpu32
, "68360", 1 },
404 { m68881
, "68882", 1 },
405 { mcf5200
, "5202", 1 },
406 { mcf5200
, "5204", 1 },
407 { mcf5200
, "5206", 1 },
410 static const int n_archs
= sizeof (archs
) / sizeof (archs
[0]);
412 /* This is the assembler relaxation table for m68k. m68k is a rich CISC
413 architecture and we have a lot of relaxation modes. */
415 /* Macros used in the relaxation code. */
416 #define TAB(x,y) (((x) << 2) + (y))
417 #define TABTYPE(x) ((x) >> 2)
419 /* Relaxation states. */
425 /* Here are all the relaxation modes we support. First we can relax ordinary
426 branches. On 68020 and higher and on CPU32 all branch instructions take
427 three forms, so on these CPUs all branches always remain as such. When we
428 have to expand to the LONG form on a 68000, though, we substitute an
429 absolute jump instead. This is a direct replacement for unconditional
430 branches and a branch over a jump for conditional branches. However, if the
431 user requires PIC and disables this with --pcrel, we can only relax between
432 BYTE and SHORT forms, punting if that isn't enough. This gives us four
433 different relaxation modes for branches: */
435 #define BRANCHBWL 0 /* branch byte, word, or long */
436 #define BRABSJUNC 1 /* absolute jump for LONG, unconditional */
437 #define BRABSJCOND 2 /* absolute jump for LONG, conditional */
438 #define BRANCHBW 3 /* branch byte or word */
440 /* We also relax coprocessor branches and DBcc's. All CPUs that support
441 coprocessor branches support them in word and long forms, so we have only
442 one relaxation mode for them. DBcc's are word only on all CPUs. We can
443 relax them to the LONG form with a branch-around sequence. This sequence
444 can use a long branch (if available) or an absolute jump (if acceptable).
445 This gives us two relaxation modes. If long branches are not available and
446 absolute jumps are not acceptable, we don't relax DBcc's. */
448 #define FBRANCH 4 /* coprocessor branch */
449 #define DBCCLBR 5 /* DBcc relaxable with a long branch */
450 #define DBCCABSJ 6 /* DBcc relaxable with an absolute jump */
452 /* That's all for instruction relaxation. However, we also relax PC-relative
453 operands. Specifically, we have three operand relaxation modes. On the
454 68000 PC-relative operands can only be 16-bit, but on 68020 and higher and
455 on CPU32 they may be 16-bit or 32-bit. For the latter we relax between the
456 two. Also PC+displacement+index operands in their simple form (with a non-
457 suppressed index without memory indirection) are supported on all CPUs, but
458 on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher
459 and on CPU32 we relax it to SHORT and LONG forms as well using the extended
460 form of the PC+displacement+index operand. Finally, some absolute operands
461 can be relaxed down to 16-bit PC-relative. */
463 #define PCREL1632 7 /* 16-bit or 32-bit PC-relative */
464 #define PCINDEX 8 /* PC+displacement+index */
465 #define ABSTOPCREL 9 /* absolute relax down to 16-bit PC-relative */
467 /* Note that calls to frag_var need to specify the maximum expansion
468 needed; this is currently 10 bytes for DBCC. */
471 How far Forward this mode will reach:
472 How far Backward this mode will reach:
473 How many bytes this mode will add to the size of the frag
474 Which mode to go to if the offset won't fit in this one
476 relax_typeS md_relax_table
[] =
478 { 127, -128, 0, TAB (BRANCHBWL
, SHORT
) },
479 { 32767, -32768, 2, TAB (BRANCHBWL
, LONG
) },
483 { 127, -128, 0, TAB (BRABSJUNC
, SHORT
) },
484 { 32767, -32768, 2, TAB (BRABSJUNC
, LONG
) },
488 { 127, -128, 0, TAB (BRABSJCOND
, SHORT
) },
489 { 32767, -32768, 2, TAB (BRABSJCOND
, LONG
) },
493 { 127, -128, 0, TAB (BRANCHBW
, SHORT
) },
498 { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE */
499 { 32767, -32768, 2, TAB (FBRANCH
, LONG
) },
503 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE */
504 { 32767, -32768, 2, TAB (DBCCLBR
, LONG
) },
508 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE */
509 { 32767, -32768, 2, TAB (DBCCABSJ
, LONG
) },
513 { 1, 1, 0, 0 }, /* PCREL1632 doesn't come BYTE */
514 { 32767, -32768, 2, TAB (PCREL1632
, LONG
) },
518 { 125, -130, 0, TAB (PCINDEX
, SHORT
) },
519 { 32765, -32770, 2, TAB (PCINDEX
, LONG
) },
523 { 1, 1, 0, 0 }, /* ABSTOPCREL doesn't come BYTE */
524 { 32767, -32768, 2, TAB (ABSTOPCREL
, LONG
) },
529 /* These are the machine dependent pseudo-ops. These are included so
530 the assembler can work on the output from the SUN C compiler, which
534 /* This table describes all the machine specific pseudo-ops the assembler
535 has to support. The fields are:
536 pseudo-op name without dot
537 function to call to execute this pseudo-op
538 Integer arg to pass to the function
540 const pseudo_typeS md_pseudo_table
[] =
542 {"data1", s_data1
, 0},
543 {"data2", s_data2
, 0},
546 {"skip", s_space
, 0},
548 #if defined (TE_SUN3) || defined (OBJ_ELF)
549 {"align", s_align_bytes
, 0},
552 {"swbeg", s_ignore
, 0},
554 {"extend", float_cons
, 'x'},
555 {"ldouble", float_cons
, 'x'},
558 /* Dwarf2 support for Gcc. */
559 {"file", dwarf2_directive_file
, 0},
560 {"loc", dwarf2_directive_loc
, 0},
563 /* The following pseudo-ops are supported for MRI compatibility. */
565 {"comline", s_space
, 1},
567 {"mask2", s_ignore
, 0},
570 {"restore", s_restore
, 0},
574 {"if.b", s_mri_if
, 'b'},
575 {"if.w", s_mri_if
, 'w'},
576 {"if.l", s_mri_if
, 'l'},
577 {"else", s_mri_else
, 0},
578 {"else.s", s_mri_else
, 's'},
579 {"else.l", s_mri_else
, 'l'},
580 {"endi", s_mri_endi
, 0},
581 {"break", s_mri_break
, 0},
582 {"break.s", s_mri_break
, 's'},
583 {"break.l", s_mri_break
, 'l'},
584 {"next", s_mri_next
, 0},
585 {"next.s", s_mri_next
, 's'},
586 {"next.l", s_mri_next
, 'l'},
587 {"for", s_mri_for
, 0},
588 {"for.b", s_mri_for
, 'b'},
589 {"for.w", s_mri_for
, 'w'},
590 {"for.l", s_mri_for
, 'l'},
591 {"endf", s_mri_endf
, 0},
592 {"repeat", s_mri_repeat
, 0},
593 {"until", s_mri_until
, 0},
594 {"until.b", s_mri_until
, 'b'},
595 {"until.w", s_mri_until
, 'w'},
596 {"until.l", s_mri_until
, 'l'},
597 {"while", s_mri_while
, 0},
598 {"while.b", s_mri_while
, 'b'},
599 {"while.w", s_mri_while
, 'w'},
600 {"while.l", s_mri_while
, 'l'},
601 {"endw", s_mri_endw
, 0},
606 /* The mote pseudo ops are put into the opcode table, since they
607 don't start with a . they look like opcodes to gas.
611 extern void obj_coff_section
PARAMS ((int));
614 CONST pseudo_typeS mote_pseudo_table
[] =
627 {"xdef", s_globl
, 0},
629 {"align", s_align_bytes
, 0},
631 {"align", s_align_ptwo
, 0},
634 {"sect", obj_coff_section
, 0},
635 {"section", obj_coff_section
, 0},
640 #define issbyte(x) ((x)>=-128 && (x)<=127)
641 #define isubyte(x) ((x)>=0 && (x)<=255)
642 #define issword(x) ((x)>=-32768 && (x)<=32767)
643 #define isuword(x) ((x)>=0 && (x)<=65535)
645 #define isbyte(x) ((x)>= -255 && (x)<=255)
646 #define isword(x) ((x)>=-65536 && (x)<=65535)
647 #define islong(x) (1)
649 extern char *input_line_pointer
;
651 static char mklower_table
[256];
652 #define mklower(c) (mklower_table[(unsigned char) (c)])
653 static char notend_table
[256];
654 static char alt_notend_table
[256];
656 (! (notend_table[(unsigned char) *s] \
658 && alt_notend_table[(unsigned char) s[1]])))
660 #if defined (M68KCOFF) && !defined (BFD_ASSEMBLER)
662 #ifdef NO_PCREL_RELOCS
665 make_pcrel_absolute(fixP
, add_number
)
669 register unsigned char *opcode
= fixP
->fx_frag
->fr_opcode
;
671 /* rewrite the PC relative instructions to absolute address ones.
672 * these are rumoured to be faster, and the apollo linker refuses
673 * to deal with the PC relative relocations.
675 if (opcode
[0] == 0x60 && opcode
[1] == 0xff) /* BRA -> JMP */
680 else if (opcode
[0] == 0x61 && opcode
[1] == 0xff) /* BSR -> JSR */
686 as_fatal (_("Unknown PC relative instruction"));
691 #endif /* NO_PCREL_RELOCS */
694 tc_coff_fix2rtype (fixP
)
697 if (fixP
->fx_tcbit
&& fixP
->fx_size
== 4)
698 return R_RELLONG_NEG
;
699 #ifdef NO_PCREL_RELOCS
700 know (fixP
->fx_pcrel
== 0);
701 return (fixP
->fx_size
== 1 ? R_RELBYTE
702 : fixP
->fx_size
== 2 ? R_DIR16
705 return (fixP
->fx_pcrel
?
706 (fixP
->fx_size
== 1 ? R_PCRBYTE
:
707 fixP
->fx_size
== 2 ? R_PCRWORD
:
709 (fixP
->fx_size
== 1 ? R_RELBYTE
:
710 fixP
->fx_size
== 2 ? R_RELWORD
:
719 /* Return zero if the reference to SYMBOL from within the same segment may
722 /* On an ELF system, we can't relax an externally visible symbol,
723 because it may be overridden by a shared library. However, if
724 TARGET_OS is "elf", then we presume that we are assembling for an
725 embedded system, in which case we don't have to worry about shared
726 libraries, and we can relax any external sym. */
728 #define relaxable_symbol(symbol) \
729 (!((S_IS_EXTERNAL (symbol) && strcmp (TARGET_OS, "elf") != 0) \
730 || S_IS_WEAK (symbol)))
732 /* Compute the relocation code for a fixup of SIZE bytes, using pc
733 relative relocation if PCREL is non-zero. PIC says whether a special
734 pic relocation was requested. */
736 static bfd_reloc_code_real_type get_reloc_code
737 PARAMS ((int, int, enum pic_relocation
));
739 static bfd_reloc_code_real_type
740 get_reloc_code (size
, pcrel
, pic
)
743 enum pic_relocation pic
;
751 return BFD_RELOC_8_GOT_PCREL
;
753 return BFD_RELOC_16_GOT_PCREL
;
755 return BFD_RELOC_32_GOT_PCREL
;
763 return BFD_RELOC_8_GOTOFF
;
765 return BFD_RELOC_16_GOTOFF
;
767 return BFD_RELOC_32_GOTOFF
;
775 return BFD_RELOC_8_PLT_PCREL
;
777 return BFD_RELOC_16_PLT_PCREL
;
779 return BFD_RELOC_32_PLT_PCREL
;
787 return BFD_RELOC_8_PLTOFF
;
789 return BFD_RELOC_16_PLTOFF
;
791 return BFD_RELOC_32_PLTOFF
;
801 return BFD_RELOC_8_PCREL
;
803 return BFD_RELOC_16_PCREL
;
805 return BFD_RELOC_32_PCREL
;
825 as_bad (_("Can not do %d byte pc-relative relocation"), size
);
827 as_bad (_("Can not do %d byte pc-relative pic relocation"), size
);
832 as_bad (_("Can not do %d byte relocation"), size
);
834 as_bad (_("Can not do %d byte pic relocation"), size
);
837 return BFD_RELOC_NONE
;
840 /* Here we decide which fixups can be adjusted to make them relative
841 to the beginning of the section instead of the symbol. Basically
842 we need to make sure that the dynamic relocations are done
843 correctly, so in some cases we force the original symbol to be
846 tc_m68k_fix_adjustable (fixP
)
849 /* Prevent all adjustments to global symbols. */
850 if (! relaxable_symbol (fixP
->fx_addsy
))
853 /* adjust_reloc_syms doesn't know about the GOT */
854 switch (fixP
->fx_r_type
)
856 case BFD_RELOC_8_GOT_PCREL
:
857 case BFD_RELOC_16_GOT_PCREL
:
858 case BFD_RELOC_32_GOT_PCREL
:
859 case BFD_RELOC_8_GOTOFF
:
860 case BFD_RELOC_16_GOTOFF
:
861 case BFD_RELOC_32_GOTOFF
:
862 case BFD_RELOC_8_PLT_PCREL
:
863 case BFD_RELOC_16_PLT_PCREL
:
864 case BFD_RELOC_32_PLT_PCREL
:
865 case BFD_RELOC_8_PLTOFF
:
866 case BFD_RELOC_16_PLTOFF
:
867 case BFD_RELOC_32_PLTOFF
:
870 case BFD_RELOC_VTABLE_INHERIT
:
871 case BFD_RELOC_VTABLE_ENTRY
:
881 #define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
883 #define relaxable_symbol(symbol) 1
890 tc_gen_reloc (section
, fixp
)
895 bfd_reloc_code_real_type code
;
897 /* If the tcbit is set, then this was a fixup of a negative value
898 that was never resolved. We do not have a reloc to handle this,
899 so just return. We assume that other code will have detected this
900 situation and produced a helpful error message, so we just tell the
901 user that the reloc cannot be produced. */
905 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
906 _("Unable to produce reloc against symbol '%s'"),
907 S_GET_NAME (fixp
->fx_addsy
));
911 if (fixp
->fx_r_type
!= BFD_RELOC_NONE
)
913 code
= fixp
->fx_r_type
;
915 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
916 that fixup_segment converted a non-PC relative reloc into a
917 PC relative reloc. In such a case, we need to convert the
924 code
= BFD_RELOC_8_PCREL
;
927 code
= BFD_RELOC_16_PCREL
;
930 code
= BFD_RELOC_32_PCREL
;
932 case BFD_RELOC_8_PCREL
:
933 case BFD_RELOC_16_PCREL
:
934 case BFD_RELOC_32_PCREL
:
935 case BFD_RELOC_8_GOT_PCREL
:
936 case BFD_RELOC_16_GOT_PCREL
:
937 case BFD_RELOC_32_GOT_PCREL
:
938 case BFD_RELOC_8_GOTOFF
:
939 case BFD_RELOC_16_GOTOFF
:
940 case BFD_RELOC_32_GOTOFF
:
941 case BFD_RELOC_8_PLT_PCREL
:
942 case BFD_RELOC_16_PLT_PCREL
:
943 case BFD_RELOC_32_PLT_PCREL
:
944 case BFD_RELOC_8_PLTOFF
:
945 case BFD_RELOC_16_PLTOFF
:
946 case BFD_RELOC_32_PLTOFF
:
949 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
950 _("Cannot make %s relocation PC relative"),
951 bfd_get_reloc_code_name (code
));
957 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
958 switch (F (fixp
->fx_size
, fixp
->fx_pcrel
))
960 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
961 MAP (1, 0, BFD_RELOC_8
);
962 MAP (2, 0, BFD_RELOC_16
);
963 MAP (4, 0, BFD_RELOC_32
);
964 MAP (1, 1, BFD_RELOC_8_PCREL
);
965 MAP (2, 1, BFD_RELOC_16_PCREL
);
966 MAP (4, 1, BFD_RELOC_32_PCREL
);
974 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
975 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
976 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
977 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
980 reloc
->addend
= fixp
->fx_addnumber
;
985 reloc
->addend
= fixp
->fx_addnumber
;
987 reloc
->addend
= (section
->vma
988 /* Explicit sign extension in case char is
990 + ((fixp
->fx_pcrel_adjust
& 0xff) ^ 0x80) - 0x80
992 + md_pcrel_from (fixp
));
995 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
996 assert (reloc
->howto
!= 0);
1001 #endif /* BFD_ASSEMBLER */
1003 /* Handle of the OPCODE hash table. NULL means any use before
1004 m68k_ip_begin() will crash. */
1005 static struct hash_control
*op_hash
;
1007 /* Assemble an m68k instruction. */
1014 register struct m68k_op
*opP
;
1015 register const struct m68k_incant
*opcode
;
1016 register const char *s
;
1017 register int tmpreg
= 0, baseo
= 0, outro
= 0, nextword
;
1018 char *pdot
, *pdotmove
;
1019 enum m68k_size siz1
, siz2
;
1023 LITTLENUM_TYPE words
[6];
1024 LITTLENUM_TYPE
*wordp
;
1025 unsigned long ok_arch
= 0;
1027 if (*instring
== ' ')
1028 instring
++; /* skip leading whitespace */
1030 /* Scan up to end of operation-code, which MUST end in end-of-string
1031 or exactly 1 space. */
1033 for (p
= instring
; *p
!= '\0'; p
++)
1043 the_ins
.error
= _("No operator");
1047 /* p now points to the end of the opcode name, probably whitespace.
1048 Make sure the name is null terminated by clobbering the
1049 whitespace, look it up in the hash table, then fix it back.
1050 Remove a dot, first, since the opcode tables have none. */
1053 for (pdotmove
= pdot
; pdotmove
< p
; pdotmove
++)
1054 *pdotmove
= pdotmove
[1];
1060 opcode
= (const struct m68k_incant
*) hash_find (op_hash
, instring
);
1065 for (pdotmove
= p
; pdotmove
> pdot
; pdotmove
--)
1066 *pdotmove
= pdotmove
[-1];
1073 the_ins
.error
= _("Unknown operator");
1077 /* found a legitimate opcode, start matching operands */
1081 if (opcode
->m_operands
== 0)
1083 char *old
= input_line_pointer
;
1085 input_line_pointer
= p
;
1086 /* Ahh - it's a motorola style psuedo op */
1087 mote_pseudo_table
[opcode
->m_opnum
].poc_handler
1088 (mote_pseudo_table
[opcode
->m_opnum
].poc_val
);
1089 input_line_pointer
= old
;
1095 if (flag_mri
&& opcode
->m_opnum
== 0)
1097 /* In MRI mode, random garbage is allowed after an instruction
1098 which accepts no operands. */
1099 the_ins
.args
= opcode
->m_operands
;
1100 the_ins
.numargs
= opcode
->m_opnum
;
1101 the_ins
.numo
= opcode
->m_codenum
;
1102 the_ins
.opcode
[0] = getone (opcode
);
1103 the_ins
.opcode
[1] = gettwo (opcode
);
1107 for (opP
= &the_ins
.operands
[0]; *p
; opP
++)
1109 p
= crack_operand (p
, opP
);
1113 the_ins
.error
= opP
->error
;
1118 opsfound
= opP
- &the_ins
.operands
[0];
1120 /* This ugly hack is to support the floating pt opcodes in their
1121 standard form. Essentially, we fake a first enty of type COP#1 */
1122 if (opcode
->m_operands
[0] == 'I')
1126 for (n
= opsfound
; n
> 0; --n
)
1127 the_ins
.operands
[n
] = the_ins
.operands
[n
- 1];
1129 memset ((char *) (&the_ins
.operands
[0]), '\0',
1130 sizeof (the_ins
.operands
[0]));
1131 the_ins
.operands
[0].mode
= CONTROL
;
1132 the_ins
.operands
[0].reg
= m68k_float_copnum
;
1136 /* We've got the operands. Find an opcode that'll accept them */
1139 /* If we didn't get the right number of ops, or we have no
1140 common model with this pattern then reject this pattern. */
1142 ok_arch
|= opcode
->m_arch
;
1143 if (opsfound
!= opcode
->m_opnum
1144 || ((opcode
->m_arch
& current_architecture
) == 0))
1148 for (s
= opcode
->m_operands
, opP
= &the_ins
.operands
[0];
1152 /* Warning: this switch is huge! */
1153 /* I've tried to organize the cases into this order:
1154 non-alpha first, then alpha by letter. Lower-case
1155 goes directly before uppercase counterpart. */
1156 /* Code with multiple case ...: gets sorted by the lowest
1157 case ... it belongs to. I hope this makes sense. */
1263 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
1280 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
1299 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
1309 if (opP
->mode
!= IMMED
)
1311 else if (s
[1] == 'b'
1312 && ! isvar (&opP
->disp
)
1313 && (opP
->disp
.exp
.X_op
!= O_constant
1314 || ! isbyte (opP
->disp
.exp
.X_add_number
)))
1316 else if (s
[1] == 'B'
1317 && ! isvar (&opP
->disp
)
1318 && (opP
->disp
.exp
.X_op
!= O_constant
1319 || ! issbyte (opP
->disp
.exp
.X_add_number
)))
1321 else if (s
[1] == 'w'
1322 && ! isvar (&opP
->disp
)
1323 && (opP
->disp
.exp
.X_op
!= O_constant
1324 || ! isword (opP
->disp
.exp
.X_add_number
)))
1326 else if (s
[1] == 'W'
1327 && ! isvar (&opP
->disp
)
1328 && (opP
->disp
.exp
.X_op
!= O_constant
1329 || ! issword (opP
->disp
.exp
.X_add_number
)))
1335 if (opP
->mode
!= IMMED
)
1340 if (opP
->mode
== AREG
1341 || opP
->mode
== CONTROL
1342 || opP
->mode
== FPREG
1343 || opP
->mode
== IMMED
1344 || opP
->mode
== REGLST
1345 || (opP
->mode
!= ABSL
1347 || opP
->reg
== ZPC
)))
1352 if (opP
->mode
== CONTROL
1353 || opP
->mode
== FPREG
1354 || opP
->mode
== REGLST
1355 || opP
->mode
== IMMED
1356 || (opP
->mode
!= ABSL
1358 || opP
->reg
== ZPC
)))
1386 if (opP
->mode
== CONTROL
1387 || opP
->mode
== FPREG
1388 || opP
->mode
== REGLST
)
1393 if (opP
->mode
!= AINC
)
1398 if (opP
->mode
!= ADEC
)
1448 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
1469 case '~': /* For now! (JF FOO is this right?) */
1491 if (opP
->mode
!= CONTROL
1492 || (opP
->reg
!= TT0
&& opP
->reg
!= TT1
))
1497 if (opP
->mode
!= AREG
)
1502 if (opP
->mode
!= AINDR
)
1507 if (opP
->mode
!= ABSL
1509 && strncmp (instring
, "jbsr", 4) == 0))
1514 if (opP
->mode
!= CONTROL
|| opP
->reg
!= CCR
)
1519 if (opP
->mode
!= DISP
1521 || opP
->reg
> ADDR7
)
1526 if (opP
->mode
!= DREG
)
1531 if (opP
->reg
!= ACC
)
1536 if (opP
->mode
!= FPREG
)
1541 if (opP
->reg
!= MACSR
)
1546 if (opP
->reg
!= MASK
)
1551 if (opP
->mode
!= CONTROL
1558 if (opP
->mode
!= CONTROL
1560 || opP
->reg
> last_movec_reg
)
1564 const enum m68k_register
*rp
;
1565 for (rp
= control_regs
; *rp
; rp
++)
1566 if (*rp
== opP
->reg
)
1574 if (opP
->mode
!= IMMED
)
1580 if (opP
->mode
== DREG
1581 || opP
->mode
== AREG
1582 || opP
->mode
== FPREG
)
1591 opP
->mask
= 1 << (opP
->reg
- DATA0
);
1594 opP
->mask
= 1 << (opP
->reg
- ADDR0
+ 8);
1597 opP
->mask
= 1 << (opP
->reg
- FP0
+ 16);
1605 else if (opP
->mode
== CONTROL
)
1614 opP
->mask
= 1 << 24;
1617 opP
->mask
= 1 << 25;
1620 opP
->mask
= 1 << 26;
1629 else if (opP
->mode
!= REGLST
)
1631 else if (s
[1] == '8' && (opP
->mask
& 0x0ffffff) != 0)
1633 else if (s
[1] == '3' && (opP
->mask
& 0x7000000) != 0)
1638 if (opP
->mode
!= IMMED
)
1640 else if (opP
->disp
.exp
.X_op
!= O_constant
1641 || ! issbyte (opP
->disp
.exp
.X_add_number
))
1643 else if (! m68k_quick
1644 && instring
[3] != 'q'
1645 && instring
[4] != 'q')
1650 if (opP
->mode
!= DREG
1651 && opP
->mode
!= IMMED
1652 && opP
->mode
!= ABSL
)
1657 if (opP
->mode
!= IMMED
)
1659 else if (opP
->disp
.exp
.X_op
!= O_constant
1660 || opP
->disp
.exp
.X_add_number
< 1
1661 || opP
->disp
.exp
.X_add_number
> 8)
1663 else if (! m68k_quick
1664 && (strncmp (instring
, "add", 3) == 0
1665 || strncmp (instring
, "sub", 3) == 0)
1666 && instring
[3] != 'q')
1671 if (opP
->mode
!= DREG
&& opP
->mode
!= AREG
)
1676 if (opP
->mode
!= AINDR
1677 && (opP
->mode
!= BASE
1679 && opP
->reg
!= ZADDR0
)
1680 || opP
->disp
.exp
.X_op
!= O_absent
1681 || ((opP
->index
.reg
< DATA0
1682 || opP
->index
.reg
> DATA7
)
1683 && (opP
->index
.reg
< ADDR0
1684 || opP
->index
.reg
> ADDR7
))
1685 || opP
->index
.size
!= SIZE_UNSPEC
1686 || opP
->index
.scale
!= 1))
1691 if (opP
->mode
!= CONTROL
1692 || ! (opP
->reg
== FPI
1694 || opP
->reg
== FPC
))
1699 if (opP
->mode
!= CONTROL
|| opP
->reg
!= SR
)
1704 if (opP
->mode
!= IMMED
)
1706 else if (opP
->disp
.exp
.X_op
!= O_constant
1707 || opP
->disp
.exp
.X_add_number
< 0
1708 || opP
->disp
.exp
.X_add_number
> 7)
1713 if (opP
->mode
!= CONTROL
|| opP
->reg
!= USP
)
1717 /* JF these are out of order. We could put them
1718 in order if we were willing to put up with
1719 bunches of #ifdef m68851s in the code.
1721 Don't forget that you need these operands
1722 to use 68030 MMU instructions. */
1724 /* Memory addressing mode used by pflushr */
1726 if (opP
->mode
== CONTROL
1727 || opP
->mode
== FPREG
1728 || opP
->mode
== DREG
1729 || opP
->mode
== AREG
1730 || opP
->mode
== REGLST
)
1732 /* We should accept immediate operands, but they
1733 supposedly have to be quad word, and we don't
1734 handle that. I would like to see what a Motorola
1735 assembler does before doing something here. */
1736 if (opP
->mode
== IMMED
)
1741 if (opP
->mode
!= CONTROL
1742 || (opP
->reg
!= SFC
&& opP
->reg
!= DFC
))
1747 if (opP
->mode
!= CONTROL
|| opP
->reg
!= TC
)
1752 if (opP
->mode
!= CONTROL
|| opP
->reg
!= AC
)
1757 if (opP
->mode
!= CONTROL
1760 && opP
->reg
!= SCC
))
1765 if (opP
->mode
!= CONTROL
1771 if (opP
->mode
!= CONTROL
1774 && opP
->reg
!= CRP
))
1779 if (opP
->mode
!= CONTROL
1780 || (!(opP
->reg
>= BAD
&& opP
->reg
<= BAD
+ 7)
1781 && !(opP
->reg
>= BAC
&& opP
->reg
<= BAC
+ 7)))
1786 if (opP
->mode
!= CONTROL
|| opP
->reg
!= PSR
)
1791 if (opP
->mode
!= CONTROL
|| opP
->reg
!= PCSR
)
1796 if (opP
->mode
!= CONTROL
1803 } /* not a cache specifier. */
1807 if (opP
->mode
!= ABSL
)
1812 if (opP
->reg
< DATA0L
|| opP
->reg
> ADDR7U
)
1814 /* FIXME: kludge instead of fixing parser:
1815 upper/lower registers are *not* CONTROL
1816 registers, but ordinary ones. */
1817 if ((opP
->reg
>= DATA0L
&& opP
->reg
<= DATA7L
)
1818 || (opP
->reg
>= DATA0U
&& opP
->reg
<= DATA7U
))
1826 } /* switch on type of operand */
1830 } /* for each operand */
1831 } /* if immediately wrong */
1838 opcode
= opcode
->m_next
;
1843 && !(ok_arch
& current_architecture
))
1848 _("invalid instruction for this architecture; needs "));
1849 cp
= buf
+ strlen (buf
);
1853 strcpy (cp
, _("fpu (68040, 68060 or 68881/68882)"));
1856 strcpy (cp
, _("mmu (68030 or 68851)"));
1859 strcpy (cp
, _("68020 or higher"));
1862 strcpy (cp
, _("68000 or higher"));
1865 strcpy (cp
, _("68010 or higher"));
1869 int got_one
= 0, idx
;
1871 idx
< (int) (sizeof (archs
) / sizeof (archs
[0]));
1874 if ((archs
[idx
].arch
& ok_arch
)
1875 && ! archs
[idx
].alias
)
1879 strcpy (cp
, " or ");
1883 strcpy (cp
, archs
[idx
].name
);
1889 cp
= xmalloc (strlen (buf
) + 1);
1894 the_ins
.error
= _("operands mismatch");
1896 } /* Fell off the end */
1901 /* now assemble it */
1903 the_ins
.args
= opcode
->m_operands
;
1904 the_ins
.numargs
= opcode
->m_opnum
;
1905 the_ins
.numo
= opcode
->m_codenum
;
1906 the_ins
.opcode
[0] = getone (opcode
);
1907 the_ins
.opcode
[1] = gettwo (opcode
);
1909 for (s
= the_ins
.args
, opP
= &the_ins
.operands
[0]; *s
; s
+= 2, opP
++)
1911 /* This switch is a doozy.
1912 Watch the first step; its a big one! */
1940 tmpreg
= 0x3c; /* 7.4 */
1941 if (strchr ("bwl", s
[1]))
1942 nextword
= get_num (&opP
->disp
, 80);
1944 nextword
= get_num (&opP
->disp
, 0);
1945 if (isvar (&opP
->disp
))
1946 add_fix (s
[1], &opP
->disp
, 0, 0);
1950 if (!isbyte (nextword
))
1951 opP
->error
= _("operand out of range");
1956 if (!isword (nextword
))
1957 opP
->error
= _("operand out of range");
1962 if (!issword (nextword
))
1963 opP
->error
= _("operand out of range");
1968 addword (nextword
>> 16);
1995 /* We gotta put out some float */
1996 if (op (&opP
->disp
) != O_big
)
2001 /* Can other cases happen here? */
2002 if (op (&opP
->disp
) != O_constant
)
2005 val
= (valueT
) offs (&opP
->disp
);
2009 generic_bignum
[gencnt
] = (LITTLENUM_TYPE
) val
;
2010 val
>>= LITTLENUM_NUMBER_OF_BITS
;
2014 offs (&opP
->disp
) = gencnt
;
2016 if (offs (&opP
->disp
) > 0)
2018 if (offs (&opP
->disp
) > baseo
)
2020 as_warn (_("Bignum too big for %c format; truncated"),
2022 offs (&opP
->disp
) = baseo
;
2024 baseo
-= offs (&opP
->disp
);
2027 for (wordp
= generic_bignum
+ offs (&opP
->disp
) - 1;
2028 offs (&opP
->disp
)--;
2033 gen_to_words (words
, baseo
, (long) outro
);
2034 for (wordp
= words
; baseo
--; wordp
++)
2038 tmpreg
= opP
->reg
- DATA
; /* 0.dreg */
2041 tmpreg
= 0x08 + opP
->reg
- ADDR
; /* 1.areg */
2044 tmpreg
= 0x10 + opP
->reg
- ADDR
; /* 2.areg */
2047 tmpreg
= 0x20 + opP
->reg
- ADDR
; /* 4.areg */
2050 tmpreg
= 0x18 + opP
->reg
- ADDR
; /* 3.areg */
2054 nextword
= get_num (&opP
->disp
, 80);
2057 && ! isvar (&opP
->disp
)
2060 opP
->disp
.exp
.X_op
= O_symbol
;
2061 #ifndef BFD_ASSEMBLER
2062 opP
->disp
.exp
.X_add_symbol
= &abs_symbol
;
2064 opP
->disp
.exp
.X_add_symbol
=
2065 section_symbol (absolute_section
);
2069 /* Force into index mode. Hope this works */
2071 /* We do the first bit for 32-bit displacements, and the
2072 second bit for 16 bit ones. It is possible that we
2073 should make the default be WORD instead of LONG, but
2074 I think that'd break GCC, so we put up with a little
2075 inefficiency for the sake of working output. */
2077 if (!issword (nextword
)
2078 || (isvar (&opP
->disp
)
2079 && ((opP
->disp
.size
== SIZE_UNSPEC
2080 && flag_short_refs
== 0
2081 && cpu_of_arch (current_architecture
) >= m68020
2082 && ! arch_coldfire_p (current_architecture
))
2083 || opP
->disp
.size
== SIZE_LONG
)))
2085 if (cpu_of_arch (current_architecture
) < m68020
2086 || arch_coldfire_p (current_architecture
))
2088 _("displacement too large for this architecture; needs 68020 or higher");
2090 tmpreg
= 0x3B; /* 7.3 */
2092 tmpreg
= 0x30 + opP
->reg
- ADDR
; /* 6.areg */
2093 if (isvar (&opP
->disp
))
2097 if (opP
->disp
.size
== SIZE_LONG
2099 /* If the displacement needs pic
2100 relocation it cannot be relaxed. */
2101 || opP
->disp
.pic_reloc
!= pic_none
2106 add_fix ('l', &opP
->disp
, 1, 2);
2110 add_frag (adds (&opP
->disp
),
2112 TAB (PCREL1632
, SZ_UNDEF
));
2119 add_fix ('l', &opP
->disp
, 0, 0);
2124 addword (nextword
>> 16);
2129 tmpreg
= 0x3A; /* 7.2 */
2131 tmpreg
= 0x28 + opP
->reg
- ADDR
; /* 5.areg */
2133 if (isvar (&opP
->disp
))
2137 add_fix ('w', &opP
->disp
, 1, 0);
2140 add_fix ('w', &opP
->disp
, 0, 0);
2150 baseo
= get_num (&opP
->disp
, 80);
2151 if (opP
->mode
== POST
|| opP
->mode
== PRE
)
2152 outro
= get_num (&opP
->odisp
, 80);
2153 /* Figure out the `addressing mode'.
2154 Also turn on the BASE_DISABLE bit, if needed. */
2155 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
2157 tmpreg
= 0x3b; /* 7.3 */
2158 if (opP
->reg
== ZPC
)
2161 else if (opP
->reg
== 0)
2164 tmpreg
= 0x30; /* 6.garbage */
2166 else if (opP
->reg
>= ZADDR0
&& opP
->reg
<= ZADDR7
)
2169 tmpreg
= 0x30 + opP
->reg
- ZADDR0
;
2172 tmpreg
= 0x30 + opP
->reg
- ADDR
; /* 6.areg */
2174 siz1
= opP
->disp
.size
;
2175 if (opP
->mode
== POST
|| opP
->mode
== PRE
)
2176 siz2
= opP
->odisp
.size
;
2180 /* Index register stuff */
2181 if (opP
->index
.reg
!= 0
2182 && opP
->index
.reg
>= DATA
2183 && opP
->index
.reg
<= ADDR7
)
2185 nextword
|= (opP
->index
.reg
- DATA
) << 12;
2187 if (opP
->index
.size
== SIZE_LONG
2188 || (opP
->index
.size
== SIZE_UNSPEC
2189 && m68k_index_width_default
== SIZE_LONG
))
2192 if ((opP
->index
.scale
!= 1
2193 && cpu_of_arch (current_architecture
) < m68020
)
2194 || (opP
->index
.scale
== 8
2195 && arch_coldfire_p (current_architecture
)))
2198 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
2201 if (arch_coldfire_p (current_architecture
)
2202 && opP
->index
.size
== SIZE_WORD
)
2203 opP
->error
= _("invalid index size for coldfire");
2205 switch (opP
->index
.scale
)
2222 GET US OUT OF HERE! */
2224 /* Must be INDEX, with an index register. Address
2225 register cannot be ZERO-PC, and either :b was
2226 forced, or we know it will fit. For a 68000 or
2227 68010, force this mode anyways, because the
2228 larger modes aren't supported. */
2229 if (opP
->mode
== BASE
2230 && ((opP
->reg
>= ADDR0
2231 && opP
->reg
<= ADDR7
)
2234 if (siz1
== SIZE_BYTE
2235 || cpu_of_arch (current_architecture
) < m68020
2236 || arch_coldfire_p (current_architecture
)
2237 || (siz1
== SIZE_UNSPEC
2238 && ! isvar (&opP
->disp
)
2239 && issbyte (baseo
)))
2241 nextword
+= baseo
& 0xff;
2243 if (isvar (&opP
->disp
))
2245 /* Do a byte relocation. If it doesn't
2246 fit (possible on m68000) let the
2247 fixup processing complain later. */
2249 add_fix ('B', &opP
->disp
, 1, 1);
2251 add_fix ('B', &opP
->disp
, 0, 0);
2253 else if (siz1
!= SIZE_BYTE
)
2255 if (siz1
!= SIZE_UNSPEC
)
2256 as_warn (_("Forcing byte displacement"));
2257 if (! issbyte (baseo
))
2258 opP
->error
= _("byte displacement out of range");
2263 else if (siz1
== SIZE_UNSPEC
2265 && isvar (&opP
->disp
)
2266 && subs (&opP
->disp
) == NULL
2268 /* If the displacement needs pic
2269 relocation it cannot be relaxed. */
2270 && opP
->disp
.pic_reloc
== pic_none
2274 /* The code in md_convert_frag_1 needs to be
2275 able to adjust nextword. Call frag_grow
2276 to ensure that we have enough space in
2277 the frag obstack to make all the bytes
2280 nextword
+= baseo
& 0xff;
2282 add_frag (adds (&opP
->disp
), offs (&opP
->disp
),
2283 TAB (PCINDEX
, SZ_UNDEF
));
2291 nextword
|= 0x40; /* No index reg */
2292 if (opP
->index
.reg
>= ZDATA0
2293 && opP
->index
.reg
<= ZDATA7
)
2294 nextword
|= (opP
->index
.reg
- ZDATA0
) << 12;
2295 else if (opP
->index
.reg
>= ZADDR0
2296 || opP
->index
.reg
<= ZADDR7
)
2297 nextword
|= (opP
->index
.reg
- ZADDR0
+ 8) << 12;
2300 /* It isn't simple. */
2302 if (cpu_of_arch (current_architecture
) < m68020
2303 || arch_coldfire_p (current_architecture
))
2305 _("invalid operand mode for this architecture; needs 68020 or higher");
2308 /* If the guy specified a width, we assume that it is
2309 wide enough. Maybe it isn't. If so, we lose. */
2313 if (isvar (&opP
->disp
)
2315 : ! issword (baseo
))
2320 else if (! isvar (&opP
->disp
) && baseo
== 0)
2329 as_warn (_(":b not permitted; defaulting to :w"));
2339 /* Figure out innner displacement stuff */
2340 if (opP
->mode
== POST
|| opP
->mode
== PRE
)
2342 if (cpu_of_arch (current_architecture
) & cpu32
)
2343 opP
->error
= _("invalid operand mode for this architecture; needs 68020 or higher");
2347 if (isvar (&opP
->odisp
)
2349 : ! issword (outro
))
2354 else if (! isvar (&opP
->odisp
) && outro
== 0)
2363 as_warn (_(":b not permitted; defaulting to :w"));
2372 if (opP
->mode
== POST
2373 && (nextword
& 0x40) == 0)
2378 if (siz1
!= SIZE_UNSPEC
&& isvar (&opP
->disp
))
2380 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
2381 add_fix (siz1
== SIZE_LONG
? 'l' : 'w', &opP
->disp
, 1, 2);
2383 add_fix (siz1
== SIZE_LONG
? 'l' : 'w', &opP
->disp
, 0, 0);
2385 if (siz1
== SIZE_LONG
)
2386 addword (baseo
>> 16);
2387 if (siz1
!= SIZE_UNSPEC
)
2390 if (siz2
!= SIZE_UNSPEC
&& isvar (&opP
->odisp
))
2391 add_fix (siz2
== SIZE_LONG
? 'l' : 'w', &opP
->odisp
, 0, 0);
2392 if (siz2
== SIZE_LONG
)
2393 addword (outro
>> 16);
2394 if (siz2
!= SIZE_UNSPEC
)
2400 nextword
= get_num (&opP
->disp
, 80);
2401 switch (opP
->disp
.size
)
2406 if (!isvar (&opP
->disp
) && issword (offs (&opP
->disp
)))
2408 tmpreg
= 0x38; /* 7.0 */
2412 if (isvar (&opP
->disp
)
2413 && !subs (&opP
->disp
)
2414 && adds (&opP
->disp
)
2416 /* If the displacement needs pic relocation it
2417 cannot be relaxed. */
2418 && opP
->disp
.pic_reloc
== pic_none
2421 && !strchr ("~%&$?", s
[0]))
2423 tmpreg
= 0x3A; /* 7.2 */
2424 add_frag (adds (&opP
->disp
),
2426 TAB (ABSTOPCREL
, SZ_UNDEF
));
2429 /* Fall through into long */
2431 if (isvar (&opP
->disp
))
2432 add_fix ('l', &opP
->disp
, 0, 0);
2434 tmpreg
= 0x39;/* 7.1 mode */
2435 addword (nextword
>> 16);
2440 as_bad (_("unsupported byte value; use a different suffix"));
2442 case SIZE_WORD
: /* Word */
2443 if (isvar (&opP
->disp
))
2444 add_fix ('w', &opP
->disp
, 0, 0);
2446 tmpreg
= 0x38;/* 7.0 mode */
2454 as_bad (_("unknown/incorrect operand"));
2457 install_gen_operand (s
[1], tmpreg
);
2463 { /* JF: I hate floating point! */
2478 tmpreg
= get_num (&opP
->disp
, tmpreg
);
2479 if (isvar (&opP
->disp
))
2480 add_fix (s
[1], &opP
->disp
, 0, 0);
2483 case 'b': /* Danger: These do no check for
2484 certain types of overflow.
2486 if (!isbyte (tmpreg
))
2487 opP
->error
= _("out of range");
2488 insop (tmpreg
, opcode
);
2489 if (isvar (&opP
->disp
))
2490 the_ins
.reloc
[the_ins
.nrel
- 1].n
=
2491 (opcode
->m_codenum
) * 2 + 1;
2494 if (!issbyte (tmpreg
))
2495 opP
->error
= _("out of range");
2496 the_ins
.opcode
[the_ins
.numo
- 1] |= tmpreg
& 0xff;
2497 if (isvar (&opP
->disp
))
2498 the_ins
.reloc
[the_ins
.nrel
- 1].n
= opcode
->m_codenum
* 2 - 1;
2501 if (!isword (tmpreg
))
2502 opP
->error
= _("out of range");
2503 insop (tmpreg
, opcode
);
2504 if (isvar (&opP
->disp
))
2505 the_ins
.reloc
[the_ins
.nrel
- 1].n
= (opcode
->m_codenum
) * 2;
2508 if (!issword (tmpreg
))
2509 opP
->error
= _("out of range");
2510 insop (tmpreg
, opcode
);
2511 if (isvar (&opP
->disp
))
2512 the_ins
.reloc
[the_ins
.nrel
- 1].n
= (opcode
->m_codenum
) * 2;
2515 /* Because of the way insop works, we put these two out
2517 insop (tmpreg
, opcode
);
2518 insop (tmpreg
>> 16, opcode
);
2519 if (isvar (&opP
->disp
))
2520 the_ins
.reloc
[the_ins
.nrel
- 1].n
= (opcode
->m_codenum
) * 2;
2527 install_operand (s
[1], tmpreg
);
2538 install_operand (s
[1], opP
->reg
- ADDR
);
2542 tmpreg
= get_num (&opP
->disp
, 80);
2546 add_fix ('B', &opP
->disp
, 1, -1);
2549 add_fix ('w', &opP
->disp
, 1, 0);
2554 if (! HAVE_LONG_BRANCH (current_architecture
))
2555 as_warn (_("Can't use long branches on 68000/68010/5200"));
2556 the_ins
.opcode
[0] |= 0xff;
2557 add_fix ('l', &opP
->disp
, 1, 0);
2562 if (subs (&opP
->disp
)) /* We can't relax it */
2566 /* If the displacement needs pic relocation it cannot be
2568 if (opP
->disp
.pic_reloc
!= pic_none
)
2571 /* This could either be a symbol, or an absolute
2572 address. If it's an absolute address, turn it into
2573 an absolute jump right here and keep it out of the
2575 if (adds (&opP
->disp
) == 0)
2577 if (the_ins
.opcode
[0] == 0x6000) /* jbra */
2578 the_ins
.opcode
[0] = 0x4EF1;
2579 else if (the_ins
.opcode
[0] == 0x6100) /* jbsr */
2580 the_ins
.opcode
[0] = 0x4EB1;
2583 the_ins
.opcode
[0] ^= 0x0100;
2584 the_ins
.opcode
[0] |= 0x0006;
2587 add_fix ('l', &opP
->disp
, 0, 0);
2593 /* Now we know it's going into the relaxer. Now figure
2594 out which mode. We try in this order of preference:
2595 long branch, absolute jump, byte/word branches only. */
2596 if (HAVE_LONG_BRANCH (current_architecture
))
2597 add_frag (adds (&opP
->disp
), offs (&opP
->disp
),
2598 TAB (BRANCHBWL
, SZ_UNDEF
));
2599 else if (! flag_keep_pcrel
)
2601 if ((the_ins
.opcode
[0] == 0x6000)
2602 || (the_ins
.opcode
[0] == 0x6100))
2603 add_frag (adds (&opP
->disp
), offs (&opP
->disp
),
2604 TAB (BRABSJUNC
, SZ_UNDEF
));
2606 add_frag (adds (&opP
->disp
), offs (&opP
->disp
),
2607 TAB (BRABSJCOND
, SZ_UNDEF
));
2610 add_frag (adds (&opP
->disp
), offs (&opP
->disp
),
2611 TAB (BRANCHBW
, SZ_UNDEF
));
2614 if (isvar (&opP
->disp
))
2616 /* Check for DBcc instructions. We can relax them,
2617 but only if we have long branches and/or absolute
2619 if (((the_ins
.opcode
[0] & 0xf0f8) == 0x50c8)
2620 && (HAVE_LONG_BRANCH (current_architecture
)
2621 || (! flag_keep_pcrel
)))
2623 if (HAVE_LONG_BRANCH (current_architecture
))
2624 add_frag (adds (&opP
->disp
), offs (&opP
->disp
),
2625 TAB (DBCCLBR
, SZ_UNDEF
));
2627 add_frag (adds (&opP
->disp
), offs (&opP
->disp
),
2628 TAB (DBCCABSJ
, SZ_UNDEF
));
2631 add_fix ('w', &opP
->disp
, 1, 0);
2635 case 'C': /* Fixed size LONG coproc branches */
2636 add_fix ('l', &opP
->disp
, 1, 0);
2640 case 'c': /* Var size Coprocesssor branches */
2641 if (subs (&opP
->disp
) || (adds (&opP
->disp
) == 0))
2643 the_ins
.opcode
[the_ins
.numo
- 1] |= 0x40;
2644 add_fix ('l', &opP
->disp
, 1, 0);
2649 add_frag (adds (&opP
->disp
), offs (&opP
->disp
),
2650 TAB (FBRANCH
, SZ_UNDEF
));
2657 case 'C': /* Ignore it */
2660 case 'd': /* JF this is a kludge */
2661 install_operand ('s', opP
->reg
- ADDR
);
2662 tmpreg
= get_num (&opP
->disp
, 80);
2663 if (!issword (tmpreg
))
2665 as_warn (_("Expression out of range, using 0"));
2672 install_operand (s
[1], opP
->reg
- DATA
);
2675 case 'E': /* Ignore it */
2679 install_operand (s
[1], opP
->reg
- FP0
);
2682 case 'G': /* Ignore it */
2687 tmpreg
= opP
->reg
- COP0
;
2688 install_operand (s
[1], tmpreg
);
2691 case 'J': /* JF foo */
2764 install_operand (s
[1], tmpreg
);
2768 tmpreg
= get_num (&opP
->disp
, 55);
2769 install_operand (s
[1], tmpreg
& 0x7f);
2776 if (tmpreg
& 0x7FF0000)
2777 as_bad (_("Floating point register in register list"));
2778 insop (reverse_16_bits (tmpreg
), opcode
);
2782 if (tmpreg
& 0x700FFFF)
2783 as_bad (_("Wrong register in floating-point reglist"));
2784 install_operand (s
[1], reverse_8_bits (tmpreg
>> 16));
2792 if (tmpreg
& 0x7FF0000)
2793 as_bad (_("Floating point register in register list"));
2794 insop (tmpreg
, opcode
);
2796 else if (s
[1] == '8')
2798 if (tmpreg
& 0x0FFFFFF)
2799 as_bad (_("incorrect register in reglist"));
2800 install_operand (s
[1], tmpreg
>> 24);
2804 if (tmpreg
& 0x700FFFF)
2805 as_bad (_("wrong register in floating-point reglist"));
2807 install_operand (s
[1], tmpreg
>> 16);
2812 install_operand (s
[1], get_num (&opP
->disp
, 60));
2816 tmpreg
= ((opP
->mode
== DREG
)
2817 ? 0x20 + (int) (opP
->reg
- DATA
)
2818 : (get_num (&opP
->disp
, 40) & 0x1F));
2819 install_operand (s
[1], tmpreg
);
2823 tmpreg
= get_num (&opP
->disp
, 10);
2826 install_operand (s
[1], tmpreg
);
2830 /* This depends on the fact that ADDR registers are eight
2831 more than their corresponding DATA regs, so the result
2832 will have the ADDR_REG bit set */
2833 install_operand (s
[1], opP
->reg
- DATA
);
2837 if (opP
->mode
== AINDR
)
2838 install_operand (s
[1], opP
->reg
- DATA
);
2840 install_operand (s
[1], opP
->index
.reg
- DATA
);
2844 if (opP
->reg
== FPI
)
2846 else if (opP
->reg
== FPS
)
2848 else if (opP
->reg
== FPC
)
2852 install_operand (s
[1], tmpreg
);
2855 case 'S': /* Ignore it */
2859 install_operand (s
[1], get_num (&opP
->disp
, 30));
2862 case 'U': /* Ignore it */
2881 as_fatal (_("failed sanity check"));
2882 } /* switch on cache token */
2883 install_operand (s
[1], tmpreg
);
2886 /* JF: These are out of order, I fear. */
2899 install_operand (s
[1], tmpreg
);
2925 install_operand (s
[1], tmpreg
);
2929 if (opP
->reg
== VAL
)
2948 install_operand (s
[1], tmpreg
);
2962 tmpreg
= (4 << 10) | ((opP
->reg
- BAD
) << 2);
2973 tmpreg
= (5 << 10) | ((opP
->reg
- BAC
) << 2);
2979 install_operand (s
[1], tmpreg
);
2982 know (opP
->reg
== PSR
);
2985 know (opP
->reg
== PCSR
);
3000 install_operand (s
[1], tmpreg
);
3003 tmpreg
= get_num (&opP
->disp
, 20);
3004 install_operand (s
[1], tmpreg
);
3006 case '_': /* used only for move16 absolute 32-bit address */
3007 if (isvar (&opP
->disp
))
3008 add_fix ('l', &opP
->disp
, 0, 0);
3009 tmpreg
= get_num (&opP
->disp
, 80);
3010 addword (tmpreg
>> 16);
3011 addword (tmpreg
& 0xFFFF);
3014 install_operand (s
[1], opP
->reg
- DATA0L
);
3015 opP
->reg
-= (DATA0L
);
3016 opP
->reg
&= 0x0F; /* remove upper/lower bit */
3023 /* By the time whe get here (FINALLY) the_ins contains the complete
3024 instruction, ready to be emitted. . . */
3028 reverse_16_bits (in
)
3034 static int mask
[16] =
3036 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3037 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
3039 for (n
= 0; n
< 16; n
++)
3042 out
|= mask
[15 - n
];
3045 } /* reverse_16_bits() */
3054 static int mask
[8] =
3056 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3059 for (n
= 0; n
< 8; n
++)
3065 } /* reverse_8_bits() */
3067 /* Cause an extra frag to be generated here, inserting up to 10 bytes
3068 (that value is chosen in the frag_var call in md_assemble). TYPE
3069 is the subtype of the frag to be generated; its primary type is
3070 rs_machine_dependent.
3072 The TYPE parameter is also used by md_convert_frag_1 and
3073 md_estimate_size_before_relax. The appropriate type of fixup will
3074 be emitted by md_convert_frag_1.
3076 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
3078 install_operand (mode
, val
)
3085 the_ins
.opcode
[0] |= val
& 0xFF; /* JF FF is for M kludge */
3088 the_ins
.opcode
[0] |= val
<< 9;
3091 the_ins
.opcode
[1] |= val
<< 12;
3094 the_ins
.opcode
[1] |= val
<< 6;
3097 the_ins
.opcode
[1] |= val
;
3100 the_ins
.opcode
[2] |= val
<< 12;
3103 the_ins
.opcode
[2] |= val
<< 6;
3106 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
3107 three words long! */
3109 the_ins
.opcode
[2] |= val
;
3112 the_ins
.opcode
[1] |= val
<< 7;
3115 the_ins
.opcode
[1] |= val
<< 10;
3119 the_ins
.opcode
[1] |= val
<< 5;
3124 the_ins
.opcode
[1] |= (val
<< 10) | (val
<< 7);
3127 the_ins
.opcode
[1] |= (val
<< 12) | val
;
3130 the_ins
.opcode
[0] |= val
= 0xff;
3133 the_ins
.opcode
[0] |= val
<< 9;
3136 the_ins
.opcode
[1] |= val
;
3139 the_ins
.opcode
[1] |= val
;
3140 the_ins
.numo
++; /* What a hack */
3143 the_ins
.opcode
[1] |= val
<< 4;
3151 the_ins
.opcode
[0] |= (val
<< 6);
3154 the_ins
.opcode
[1] = (val
>> 16);
3155 the_ins
.opcode
[2] = val
& 0xffff;
3158 the_ins
.opcode
[0] |= ((val
& 0x8) << (6 - 3));
3159 the_ins
.opcode
[0] |= ((val
& 0x7) << 9);
3160 the_ins
.opcode
[1] |= ((val
& 0x10) << (7 - 4));
3163 the_ins
.opcode
[0] |= ((val
& 0x8) << (6 - 3));
3164 the_ins
.opcode
[0] |= ((val
& 0x7) << 9);
3167 the_ins
.opcode
[1] |= val
<< 12;
3168 the_ins
.opcode
[1] |= ((val
& 0x10) << (7 - 4));
3171 the_ins
.opcode
[0] |= (val
& 0xF);
3172 the_ins
.opcode
[1] |= ((val
& 0x10) << (6 - 4));
3175 the_ins
.opcode
[1] |= (val
& 0xF);
3176 the_ins
.opcode
[1] |= ((val
& 0x10) << (6 - 4));
3179 the_ins
.opcode
[1] |= ((val
!= 1) << 10);
3183 as_fatal (_("failed sanity check."));
3185 } /* install_operand() */
3188 install_gen_operand (mode
, val
)
3195 the_ins
.opcode
[0] |= val
;
3198 /* This is a kludge!!! */
3199 the_ins
.opcode
[0] |= (val
& 0x07) << 9 | (val
& 0x38) << 3;
3208 the_ins
.opcode
[0] |= val
;
3210 /* more stuff goes here */
3212 as_fatal (_("failed sanity check."));
3214 } /* install_gen_operand() */
3217 * verify that we have some number of paren pairs, do m68k_ip_op(), and
3218 * then deal with the bitfield hack.
3222 crack_operand (str
, opP
)
3224 register struct m68k_op
*opP
;
3226 register int parens
;
3228 register char *beg_str
;
3236 for (parens
= 0; *str
&& (parens
> 0 || inquote
|| notend (str
)); str
++)
3242 else if (*str
== ')')
3246 opP
->error
= _("Extra )");
3252 if (flag_mri
&& *str
== '\'')
3253 inquote
= ! inquote
;
3255 if (!*str
&& parens
)
3257 opP
->error
= _("Missing )");
3262 if (m68k_ip_op (beg_str
, opP
) != 0)
3269 c
= *++str
; /* JF bitfield hack */
3274 as_bad (_("Missing operand"));
3277 /* Detect MRI REG symbols and convert them to REGLSTs. */
3278 if (opP
->mode
== CONTROL
&& (int)opP
->reg
< 0)
3281 opP
->mask
= ~(int)opP
->reg
;
3288 /* This is the guts of the machine-dependent assembler. STR points to a
3289 machine dependent instruction. This function is supposed to emit
3290 the frags/bytes it assembles to.
3294 insert_reg (regname
, regnum
)
3295 const char *regname
;
3301 #ifdef REGISTER_PREFIX
3302 if (!flag_reg_prefix_optional
)
3304 buf
[0] = REGISTER_PREFIX
;
3305 strcpy (buf
+ 1, regname
);
3310 symbol_table_insert (symbol_new (regname
, reg_section
, regnum
,
3311 &zero_address_frag
));
3313 for (i
= 0; regname
[i
]; i
++)
3314 buf
[i
] = islower (regname
[i
]) ? toupper (regname
[i
]) : regname
[i
];
3317 symbol_table_insert (symbol_new (buf
, reg_section
, regnum
,
3318 &zero_address_frag
));
3327 static const struct init_entry init_table
[] =
3386 /* control registers */
3387 { "sfc", SFC
}, /* Source Function Code */
3389 { "dfc", DFC
}, /* Destination Function Code */
3391 { "cacr", CACR
}, /* Cache Control Register */
3392 { "caar", CAAR
}, /* Cache Address Register */
3394 { "usp", USP
}, /* User Stack Pointer */
3395 { "vbr", VBR
}, /* Vector Base Register */
3396 { "msp", MSP
}, /* Master Stack Pointer */
3397 { "isp", ISP
}, /* Interrupt Stack Pointer */
3399 { "itt0", ITT0
}, /* Instruction Transparent Translation Reg 0 */
3400 { "itt1", ITT1
}, /* Instruction Transparent Translation Reg 1 */
3401 { "dtt0", DTT0
}, /* Data Transparent Translation Register 0 */
3402 { "dtt1", DTT1
}, /* Data Transparent Translation Register 1 */
3404 /* 68ec040 versions of same */
3405 { "iacr0", ITT0
}, /* Instruction Access Control Register 0 */
3406 { "iacr1", ITT1
}, /* Instruction Access Control Register 0 */
3407 { "dacr0", DTT0
}, /* Data Access Control Register 0 */
3408 { "dacr1", DTT1
}, /* Data Access Control Register 0 */
3410 /* mcf5200 versions of same. The ColdFire programmer's reference
3411 manual indicated that the order is 2,3,0,1, but Ken Rose
3412 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3413 { "acr0", ITT0
}, /* Access Control Unit 0 */
3414 { "acr1", ITT1
}, /* Access Control Unit 1 */
3415 { "acr2", DTT0
}, /* Access Control Unit 2 */
3416 { "acr3", DTT1
}, /* Access Control Unit 3 */
3418 { "tc", TC
}, /* MMU Translation Control Register */
3421 { "mmusr", MMUSR
}, /* MMU Status Register */
3422 { "srp", SRP
}, /* User Root Pointer */
3423 { "urp", URP
}, /* Supervisor Root Pointer */
3428 { "rombar", ROMBAR
}, /* ROM Base Address Register */
3429 { "rambar0", RAMBAR0
}, /* ROM Base Address Register */
3430 { "rambar1", RAMBAR1
}, /* ROM Base Address Register */
3431 { "mbar", MBAR
}, /* Module Base Address Register */
3432 /* end of control registers */
3466 /* 68ec030 versions of same */
3469 /* 68ec030 access control unit, identical to 030 MMU status reg */
3472 /* Suppressed data and address registers. */
3490 /* Upper and lower data and address registers, used by macw and msacw. */
3534 for (i
= 0; init_table
[i
].name
; i
++)
3535 insert_reg (init_table
[i
].name
, init_table
[i
].number
);
3538 static int no_68851
, no_68881
;
3541 /* a.out machine type. Default to 68020. */
3542 int m68k_aout_machtype
= 2;
3554 int shorts_this_frag
;
3557 /* In MRI mode, the instruction and operands are separated by a
3558 space. Anything following the operands is a comment. The label
3559 has already been removed. */
3567 for (s
= str
; *s
!= '\0'; s
++)
3569 if ((*s
== ' ' || *s
== '\t') && ! inquote
)
3587 inquote
= ! inquote
;
3592 memset ((char *) (&the_ins
), '\0', sizeof (the_ins
));
3597 for (n
= 0; n
< the_ins
.numargs
; n
++)
3598 if (the_ins
.operands
[n
].error
)
3600 er
= the_ins
.operands
[n
].error
;
3606 as_bad (_("%s -- statement `%s' ignored"), er
, str
);
3610 /* If there is a current label, record that it marks an instruction. */
3611 if (current_label
!= NULL
)
3613 current_label
->text
= 1;
3614 current_label
= NULL
;
3618 /* Tie dwarf2 debug info to the address at the start of the insn. */
3619 dwarf2_emit_insn (0);
3622 if (the_ins
.nfrag
== 0)
3624 /* No frag hacking involved; just put it out */
3625 toP
= frag_more (2 * the_ins
.numo
);
3626 fromP
= &the_ins
.opcode
[0];
3627 for (m
= the_ins
.numo
; m
; --m
)
3629 md_number_to_chars (toP
, (long) (*fromP
), 2);
3633 /* put out symbol-dependent info */
3634 for (m
= 0; m
< the_ins
.nrel
; m
++)
3636 switch (the_ins
.reloc
[m
].wid
)
3655 as_fatal (_("Don't know how to figure width of %c in md_assemble()"),
3656 the_ins
.reloc
[m
].wid
);
3659 fixP
= fix_new_exp (frag_now
,
3660 ((toP
- frag_now
->fr_literal
)
3661 - the_ins
.numo
* 2 + the_ins
.reloc
[m
].n
),
3663 &the_ins
.reloc
[m
].exp
,
3664 the_ins
.reloc
[m
].pcrel
,
3665 get_reloc_code (n
, the_ins
.reloc
[m
].pcrel
,
3666 the_ins
.reloc
[m
].pic_reloc
));
3667 fixP
->fx_pcrel_adjust
= the_ins
.reloc
[m
].pcrel_fix
;
3668 if (the_ins
.reloc
[m
].wid
== 'B')
3669 fixP
->fx_signed
= 1;
3674 /* There's some frag hacking */
3676 /* Calculate the max frag size. */
3679 wid
= 2 * the_ins
.fragb
[0].fragoff
;
3680 for (n
= 1; n
< the_ins
.nfrag
; n
++)
3681 wid
+= 2 * (the_ins
.numo
- the_ins
.fragb
[n
- 1].fragoff
);
3682 /* frag_var part. */
3684 /* Make sure the whole insn fits in one chunk, in particular that
3685 the var part is attached, as we access one byte before the
3686 variable frag for byte branches. */
3690 for (n
= 0, fromP
= &the_ins
.opcode
[0]; n
< the_ins
.nfrag
; n
++)
3695 wid
= 2 * the_ins
.fragb
[n
].fragoff
;
3697 wid
= 2 * (the_ins
.numo
- the_ins
.fragb
[n
- 1].fragoff
);
3698 toP
= frag_more (wid
);
3700 shorts_this_frag
= 0;
3701 for (m
= wid
/ 2; m
; --m
)
3703 md_number_to_chars (toP
, (long) (*fromP
), 2);
3708 for (m
= 0; m
< the_ins
.nrel
; m
++)
3710 if ((the_ins
.reloc
[m
].n
) >= 2 * shorts_this_frag
)
3712 the_ins
.reloc
[m
].n
-= 2 * shorts_this_frag
;
3715 wid
= the_ins
.reloc
[m
].wid
;
3718 the_ins
.reloc
[m
].wid
= 0;
3719 wid
= (wid
== 'b') ? 1 : (wid
== 'w') ? 2 : (wid
== 'l') ? 4 : 4000;
3721 fixP
= fix_new_exp (frag_now
,
3722 ((toP
- frag_now
->fr_literal
)
3723 - the_ins
.numo
* 2 + the_ins
.reloc
[m
].n
),
3725 &the_ins
.reloc
[m
].exp
,
3726 the_ins
.reloc
[m
].pcrel
,
3727 get_reloc_code (wid
, the_ins
.reloc
[m
].pcrel
,
3728 the_ins
.reloc
[m
].pic_reloc
));
3729 fixP
->fx_pcrel_adjust
= the_ins
.reloc
[m
].pcrel_fix
;
3731 (void) frag_var (rs_machine_dependent
, 10, 0,
3732 (relax_substateT
) (the_ins
.fragb
[n
].fragty
),
3733 the_ins
.fragb
[n
].fadd
, the_ins
.fragb
[n
].foff
, to_beg_P
);
3735 n
= (the_ins
.numo
- the_ins
.fragb
[n
- 1].fragoff
);
3736 shorts_this_frag
= 0;
3739 toP
= frag_more (n
* sizeof (short));
3742 md_number_to_chars (toP
, (long) (*fromP
), 2);
3748 for (m
= 0; m
< the_ins
.nrel
; m
++)
3752 wid
= the_ins
.reloc
[m
].wid
;
3755 the_ins
.reloc
[m
].wid
= 0;
3756 wid
= (wid
== 'b') ? 1 : (wid
== 'w') ? 2 : (wid
== 'l') ? 4 : 4000;
3758 fixP
= fix_new_exp (frag_now
,
3759 ((the_ins
.reloc
[m
].n
+ toP
- frag_now
->fr_literal
)
3760 - shorts_this_frag
* 2),
3762 &the_ins
.reloc
[m
].exp
,
3763 the_ins
.reloc
[m
].pcrel
,
3764 get_reloc_code (wid
, the_ins
.reloc
[m
].pcrel
,
3765 the_ins
.reloc
[m
].pic_reloc
));
3766 fixP
->fx_pcrel_adjust
= the_ins
.reloc
[m
].pcrel_fix
;
3774 * md_begin -- set up hash tables with 68000 instructions.
3775 * similar to what the vax assembler does. ---phr
3777 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
3778 a copy of it at runtime, adding in the information we want but isn't
3779 there. I think it'd be better to have an awk script hack the table
3780 at compile time. Or even just xstr the table and use it as-is. But
3781 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
3784 register const struct m68k_opcode
*ins
;
3785 register struct m68k_incant
*hack
, *slak
;
3786 register const char *retval
= 0; /* empty string, or error msg text */
3792 flag_reg_prefix_optional
= 1;
3794 if (! m68k_rel32_from_cmdline
)
3798 op_hash
= hash_new ();
3800 obstack_begin (&robyn
, 4000);
3801 for (i
= 0; i
< m68k_numopcodes
; i
++)
3803 hack
= slak
= (struct m68k_incant
*) obstack_alloc (&robyn
, sizeof (struct m68k_incant
));
3806 ins
= &m68k_opcodes
[i
];
3807 /* We *could* ignore insns that don't match our arch here
3808 but just leaving them out of the hash. */
3809 slak
->m_operands
= ins
->args
;
3810 slak
->m_opnum
= strlen (slak
->m_operands
) / 2;
3811 slak
->m_arch
= ins
->arch
;
3812 slak
->m_opcode
= ins
->opcode
;
3813 /* This is kludgey */
3814 slak
->m_codenum
= ((ins
->match
) & 0xffffL
) ? 2 : 1;
3815 if (i
+ 1 != m68k_numopcodes
3816 && !strcmp (ins
->name
, m68k_opcodes
[i
+ 1].name
))
3818 slak
->m_next
= (struct m68k_incant
*) obstack_alloc (&robyn
, sizeof (struct m68k_incant
));
3823 slak
= slak
->m_next
;
3827 retval
= hash_insert (op_hash
, ins
->name
, (char *) hack
);
3829 as_fatal (_("Internal Error: Can't hash %s: %s"), ins
->name
, retval
);
3832 for (i
= 0; i
< m68k_numaliases
; i
++)
3834 const char *name
= m68k_opcode_aliases
[i
].primary
;
3835 const char *alias
= m68k_opcode_aliases
[i
].alias
;
3836 PTR val
= hash_find (op_hash
, name
);
3838 as_fatal (_("Internal Error: Can't find %s in hash table"), name
);
3839 retval
= hash_insert (op_hash
, alias
, val
);
3841 as_fatal (_("Internal Error: Can't hash %s: %s"), alias
, retval
);
3844 /* In MRI mode, all unsized branches are variable sized. Normally,
3845 they are word sized. */
3848 static struct m68k_opcode_alias mri_aliases
[] =
3869 i
< (int) (sizeof mri_aliases
/ sizeof mri_aliases
[0]);
3872 const char *name
= mri_aliases
[i
].primary
;
3873 const char *alias
= mri_aliases
[i
].alias
;
3874 PTR val
= hash_find (op_hash
, name
);
3876 as_fatal (_("Internal Error: Can't find %s in hash table"), name
);
3877 retval
= hash_jam (op_hash
, alias
, val
);
3879 as_fatal (_("Internal Error: Can't hash %s: %s"), alias
, retval
);
3883 for (i
= 0; i
< (int) sizeof (mklower_table
); i
++)
3884 mklower_table
[i
] = (isupper (c
= (char) i
)) ? tolower (c
) : c
;
3886 for (i
= 0; i
< (int) sizeof (notend_table
); i
++)
3888 notend_table
[i
] = 0;
3889 alt_notend_table
[i
] = 0;
3891 notend_table
[','] = 1;
3892 notend_table
['{'] = 1;
3893 notend_table
['}'] = 1;
3894 alt_notend_table
['a'] = 1;
3895 alt_notend_table
['A'] = 1;
3896 alt_notend_table
['d'] = 1;
3897 alt_notend_table
['D'] = 1;
3898 alt_notend_table
['#'] = 1;
3899 alt_notend_table
['&'] = 1;
3900 alt_notend_table
['f'] = 1;
3901 alt_notend_table
['F'] = 1;
3902 #ifdef REGISTER_PREFIX
3903 alt_notend_table
[REGISTER_PREFIX
] = 1;
3906 /* We need to put '(' in alt_notend_table to handle
3907 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1)
3909 alt_notend_table
['('] = 1;
3911 /* We need to put '@' in alt_notend_table to handle
3912 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1)
3914 alt_notend_table
['@'] = 1;
3916 /* We need to put digits in alt_notend_table to handle
3917 bfextu %d0{24:1},%d0
3919 alt_notend_table
['0'] = 1;
3920 alt_notend_table
['1'] = 1;
3921 alt_notend_table
['2'] = 1;
3922 alt_notend_table
['3'] = 1;
3923 alt_notend_table
['4'] = 1;
3924 alt_notend_table
['5'] = 1;
3925 alt_notend_table
['6'] = 1;
3926 alt_notend_table
['7'] = 1;
3927 alt_notend_table
['8'] = 1;
3928 alt_notend_table
['9'] = 1;
3930 #ifndef MIT_SYNTAX_ONLY
3931 /* Insert pseudo ops, these have to go into the opcode table since
3932 gas expects pseudo ops to start with a dot */
3935 while (mote_pseudo_table
[n
].poc_name
)
3937 hack
= (struct m68k_incant
*)
3938 obstack_alloc (&robyn
, sizeof (struct m68k_incant
));
3939 hash_insert (op_hash
,
3940 mote_pseudo_table
[n
].poc_name
, (char *) hack
);
3941 hack
->m_operands
= 0;
3951 record_alignment (text_section
, 2);
3952 record_alignment (data_section
, 2);
3953 record_alignment (bss_section
, 2);
3958 select_control_regs ()
3960 /* Note which set of "movec" control registers is available. */
3961 switch (cpu_of_arch (current_architecture
))
3964 control_regs
= m68000_control_regs
;
3967 control_regs
= m68010_control_regs
;
3971 control_regs
= m68020_control_regs
;
3974 control_regs
= m68040_control_regs
;
3977 control_regs
= m68060_control_regs
;
3980 control_regs
= cpu32_control_regs
;
3986 control_regs
= mcf_control_regs
;
3994 m68k_init_after_args ()
3996 if (cpu_of_arch (current_architecture
) == 0)
3999 const char *default_cpu
= TARGET_CPU
;
4001 if (*default_cpu
== 'm')
4003 for (i
= 0; i
< n_archs
; i
++)
4004 if (strcasecmp (default_cpu
, archs
[i
].name
) == 0)
4008 as_bad (_("unrecognized default cpu `%s' ???"), TARGET_CPU
);
4009 current_architecture
|= m68020
;
4012 current_architecture
|= archs
[i
].arch
;
4014 /* Permit m68881 specification with all cpus; those that can't work
4015 with a coprocessor could be doing emulation. */
4016 if (current_architecture
& m68851
)
4018 if (current_architecture
& m68040
)
4020 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
4023 /* What other incompatibilities could we check for? */
4025 /* Toss in some default assumptions about coprocessors. */
4027 && (cpu_of_arch (current_architecture
)
4028 /* Can CPU32 have a 68881 coprocessor?? */
4029 & (m68020
| m68030
| cpu32
)))
4031 current_architecture
|= m68881
;
4034 && (cpu_of_arch (current_architecture
) & m68020up
) != 0
4035 && (cpu_of_arch (current_architecture
) & m68040up
) == 0)
4037 current_architecture
|= m68851
;
4039 if (no_68881
&& (current_architecture
& m68881
))
4040 as_bad (_("options for 68881 and no-68881 both given"));
4041 if (no_68851
&& (current_architecture
& m68851
))
4042 as_bad (_("options for 68851 and no-68851 both given"));
4045 /* Work out the magic number. This isn't very general. */
4046 if (current_architecture
& m68000
)
4047 m68k_aout_machtype
= 0;
4048 else if (current_architecture
& m68010
)
4049 m68k_aout_machtype
= 1;
4050 else if (current_architecture
& m68020
)
4051 m68k_aout_machtype
= 2;
4053 m68k_aout_machtype
= 2;
4056 /* Note which set of "movec" control registers is available. */
4057 select_control_regs ();
4059 if (cpu_of_arch (current_architecture
) < m68020
4060 || arch_coldfire_p (current_architecture
))
4061 md_relax_table
[TAB (PCINDEX
, BYTE
)].rlx_more
= 0;
4064 /* This is called when a label is defined. */
4067 m68k_frob_label (sym
)
4070 struct label_line
*n
;
4072 n
= (struct label_line
*) xmalloc (sizeof *n
);
4075 as_where (&n
->file
, &n
->line
);
4081 /* This is called when a value that is not an instruction is emitted. */
4084 m68k_flush_pending_output ()
4086 current_label
= NULL
;
4089 /* This is called at the end of the assembly, when the final value of
4090 the label is known. We warn if this is a text symbol aligned at an
4094 m68k_frob_symbol (sym
)
4097 if (S_GET_SEGMENT (sym
) == reg_section
4098 && (int) S_GET_VALUE (sym
) < 0)
4100 S_SET_SEGMENT (sym
, absolute_section
);
4101 S_SET_VALUE (sym
, ~(int)S_GET_VALUE (sym
));
4103 else if ((S_GET_VALUE (sym
) & 1) != 0)
4105 struct label_line
*l
;
4107 for (l
= labels
; l
!= NULL
; l
= l
->next
)
4109 if (l
->label
== sym
)
4112 as_warn_where (l
->file
, l
->line
,
4113 _("text label `%s' aligned to odd boundary"),
4121 /* This is called if we go in or out of MRI mode because of the .mri
4125 m68k_mri_mode_change (on
)
4130 if (! flag_reg_prefix_optional
)
4132 flag_reg_prefix_optional
= 1;
4133 #ifdef REGISTER_PREFIX
4138 if (! m68k_rel32_from_cmdline
)
4143 if (! reg_prefix_optional_seen
)
4145 #ifdef REGISTER_PREFIX_OPTIONAL
4146 flag_reg_prefix_optional
= REGISTER_PREFIX_OPTIONAL
;
4148 flag_reg_prefix_optional
= 0;
4150 #ifdef REGISTER_PREFIX
4155 if (! m68k_rel32_from_cmdline
)
4160 /* Equal to MAX_PRECISION in atof-ieee.c */
4161 #define MAX_LITTLENUMS 6
4163 /* Turn a string in input_line_pointer into a floating point constant
4164 of type TYPE, and store the appropriate bytes in *LITP. The number
4165 of LITTLENUMS emitted is stored in *SIZEP. An error message is
4166 returned, or NULL on OK. */
4169 md_atof (type
, litP
, sizeP
)
4175 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4176 LITTLENUM_TYPE
*wordP
;
4207 return _("Bad call to MD_ATOF()");
4209 t
= atof_ieee (input_line_pointer
, type
, words
);
4211 input_line_pointer
= t
;
4213 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
4214 for (wordP
= words
; prec
--;)
4216 md_number_to_chars (litP
, (long) (*wordP
++), sizeof (LITTLENUM_TYPE
));
4217 litP
+= sizeof (LITTLENUM_TYPE
);
4223 md_number_to_chars (buf
, val
, n
)
4228 number_to_chars_bigendian (buf
, val
, n
);
4232 md_apply_fix_2 (fixP
, val
)
4236 addressT upper_limit
;
4237 offsetT lower_limit
;
4239 /* This is unnecessary but it convinces the native rs6000 compiler
4240 to generate the code we want. */
4241 char *buf
= fixP
->fx_frag
->fr_literal
;
4242 buf
+= fixP
->fx_where
;
4243 /* end ibm compiler workaround */
4245 val
= ((val
& 0xffffffff) ^ 0x80000000) - 0x80000000;
4250 memset (buf
, 0, fixP
->fx_size
);
4251 fixP
->fx_addnumber
= val
; /* Remember value for emit_reloc */
4253 if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
4254 && !S_IS_DEFINED (fixP
->fx_addsy
)
4255 && !S_IS_WEAK (fixP
->fx_addsy
))
4256 S_SET_WEAK (fixP
->fx_addsy
);
4261 #ifdef BFD_ASSEMBLER
4262 if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
4263 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
4267 switch (fixP
->fx_size
)
4269 /* The cast to offsetT below are necessary to make code correct for
4270 machines where ints are smaller than offsetT */
4274 lower_limit
= - (offsetT
) 0x80;
4277 *buf
++ = (val
>> 8);
4279 upper_limit
= 0x7fff;
4280 lower_limit
= - (offsetT
) 0x8000;
4283 *buf
++ = (val
>> 24);
4284 *buf
++ = (val
>> 16);
4285 *buf
++ = (val
>> 8);
4287 upper_limit
= 0x7fffffff;
4288 lower_limit
= - (offsetT
) 0x7fffffff - 1; /* avoid constant overflow */
4291 BAD_CASE (fixP
->fx_size
);
4294 /* Fix up a negative reloc. */
4295 if (fixP
->fx_addsy
== NULL
&& fixP
->fx_subsy
!= NULL
)
4297 fixP
->fx_addsy
= fixP
->fx_subsy
;
4298 fixP
->fx_subsy
= NULL
;
4302 /* For non-pc-relative values, it's conceivable we might get something
4303 like "0xff" for a byte field. So extend the upper part of the range
4304 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4305 so that we can do any range checking at all. */
4306 if (! fixP
->fx_pcrel
&& ! fixP
->fx_signed
)
4307 upper_limit
= upper_limit
* 2 + 1;
4309 if ((addressT
) val
> upper_limit
4310 && (val
> 0 || val
< lower_limit
))
4311 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, _("value out of range"));
4313 /* A one byte PC-relative reloc means a short branch. We can't use
4314 a short branch with a value of 0 or -1, because those indicate
4315 different opcodes (branches with longer offsets). fixup_segment
4316 in write.c may have clobbered fx_pcrel, so we need to examine the
4319 #ifdef BFD_ASSEMBLER
4320 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
4323 && fixP
->fx_size
== 1
4324 && (fixP
->fx_addsy
== NULL
4325 || S_IS_DEFINED (fixP
->fx_addsy
))
4326 && (val
== 0 || val
== -1))
4327 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, _("invalid byte branch offset"));
4330 #ifdef BFD_ASSEMBLER
4332 md_apply_fix (fixP
, valp
)
4336 md_apply_fix_2 (fixP
, (addressT
) *valp
);
4340 void md_apply_fix (fixP
, val
)
4344 md_apply_fix_2 (fixP
, (addressT
) val
);
4348 /* *fragP has been relaxed to its final size, and now needs to have
4349 the bytes inside it modified to conform to the new size There is UGLY
4353 md_convert_frag_1 (fragP
)
4354 register fragS
*fragP
;
4359 /* Address in object code of the displacement. */
4360 register int object_address
= fragP
->fr_fix
+ fragP
->fr_address
;
4362 /* Address in gas core of the place to store the displacement. */
4363 /* This convinces the native rs6000 compiler to generate the code we
4365 register char *buffer_address
= fragP
->fr_literal
;
4366 buffer_address
+= fragP
->fr_fix
;
4367 /* end ibm compiler workaround */
4369 /* The displacement of the address, from current location. */
4370 disp
= fragP
->fr_symbol
? S_GET_VALUE (fragP
->fr_symbol
) : 0;
4371 disp
= (disp
+ fragP
->fr_offset
) - object_address
;
4373 switch (fragP
->fr_subtype
)
4375 case TAB (BRANCHBWL
, BYTE
):
4376 case TAB (BRABSJUNC
, BYTE
):
4377 case TAB (BRABSJCOND
, BYTE
):
4378 case TAB (BRANCHBW
, BYTE
):
4379 know (issbyte (disp
));
4381 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
4382 _("short branch with zero offset: use :w"));
4383 fixP
= fix_new (fragP
, fragP
->fr_fix
- 1, 1, fragP
->fr_symbol
,
4384 fragP
->fr_offset
, 1, RELAX_RELOC_PC8
);
4385 fixP
->fx_pcrel_adjust
= -1;
4387 case TAB (BRANCHBWL
, SHORT
):
4388 case TAB (BRABSJUNC
, SHORT
):
4389 case TAB (BRABSJCOND
, SHORT
):
4390 case TAB (BRANCHBW
, SHORT
):
4391 fragP
->fr_opcode
[1] = 0x00;
4392 fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
, fragP
->fr_offset
,
4393 1, RELAX_RELOC_PC16
);
4396 case TAB (BRANCHBWL
, LONG
):
4397 fragP
->fr_opcode
[1] = (char) 0xFF;
4398 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
, fragP
->fr_offset
,
4399 1, RELAX_RELOC_PC32
);
4402 case TAB (BRABSJUNC
, LONG
):
4403 if (fragP
->fr_opcode
[0] == 0x61) /* jbsr */
4405 fragP
->fr_opcode
[0] = 0x4E;
4406 fragP
->fr_opcode
[1] = (char) 0xB9; /* JSR with ABSL LONG operand */
4407 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
, fragP
->fr_offset
,
4408 0, RELAX_RELOC_ABS32
);
4411 else if (fragP
->fr_opcode
[0] == 0x60) /* jbra */
4413 fragP
->fr_opcode
[0] = 0x4E;
4414 fragP
->fr_opcode
[1] = (char) 0xF9; /* JMP with ABSL LONG operand */
4415 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
, fragP
->fr_offset
,
4416 0, RELAX_RELOC_ABS32
);
4421 /* This cannot happen, because jbsr and jbra are the only two
4422 unconditional branches. */
4426 case TAB (BRABSJCOND
, LONG
):
4427 /* Only Bcc 68000 instructions can come here. */
4428 /* Change bcc into b!cc/jmp absl long. */
4430 fragP
->fr_opcode
[0] ^= 0x01; /* invert bcc */
4431 fragP
->fr_opcode
[1] = 0x6;/* branch offset = 6 */
4433 /* JF: these used to be fr_opcode[2,3], but they may be in a
4434 different frag, in which case refering to them is a no-no.
4435 Only fr_opcode[0,1] are guaranteed to work. */
4436 *buffer_address
++ = 0x4e; /* put in jmp long (0x4ef9) */
4437 *buffer_address
++ = (char) 0xf9;
4438 fragP
->fr_fix
+= 2; /* account for jmp instruction */
4439 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
,
4440 fragP
->fr_offset
, 0, RELAX_RELOC_ABS32
);
4443 case TAB (FBRANCH
, SHORT
):
4444 know ((fragP
->fr_opcode
[1] & 0x40) == 0);
4445 fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
, fragP
->fr_offset
,
4446 1, RELAX_RELOC_PC16
);
4449 case TAB (FBRANCH
, LONG
):
4450 fragP
->fr_opcode
[1] |= 0x40; /* Turn on LONG bit */
4451 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
, fragP
->fr_offset
,
4452 1, RELAX_RELOC_PC32
);
4455 case TAB (DBCCLBR
, SHORT
):
4456 case TAB (DBCCABSJ
, SHORT
):
4457 fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
, fragP
->fr_offset
,
4458 1, RELAX_RELOC_PC16
);
4461 case TAB (DBCCLBR
, LONG
):
4462 /* only DBcc instructions can come here */
4463 /* Change dbcc into dbcc/bral. */
4465 /* JF: these used to be fr_opcode[2-7], but that's wrong */
4466 *buffer_address
++ = 0x00; /* branch offset = 4 */
4467 *buffer_address
++ = 0x04;
4468 *buffer_address
++ = 0x60; /* put in bra pc+6 */
4469 *buffer_address
++ = 0x06;
4470 *buffer_address
++ = 0x60; /* Put in bral (0x60ff). */
4471 *buffer_address
++ = (char) 0xff;
4473 fragP
->fr_fix
+= 6; /* account for bra/jmp instructions */
4474 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
, fragP
->fr_offset
, 1,
4478 case TAB (DBCCABSJ
, LONG
):
4479 /* only DBcc instructions can come here */
4480 /* Change dbcc into dbcc/jmp. */
4482 /* JF: these used to be fr_opcode[2-7], but that's wrong */
4483 *buffer_address
++ = 0x00; /* branch offset = 4 */
4484 *buffer_address
++ = 0x04;
4485 *buffer_address
++ = 0x60; /* put in bra pc+6 */
4486 *buffer_address
++ = 0x06;
4487 *buffer_address
++ = 0x4e; /* Put in jmp long (0x4ef9). */
4488 *buffer_address
++ = (char) 0xf9;
4490 fragP
->fr_fix
+= 6; /* account for bra/jmp instructions */
4491 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
, fragP
->fr_offset
, 0,
4495 case TAB (PCREL1632
, SHORT
):
4496 fragP
->fr_opcode
[1] &= ~0x3F;
4497 fragP
->fr_opcode
[1] |= 0x3A; /* 072 - mode 7.2 */
4498 fix_new (fragP
, (int) (fragP
->fr_fix
), 2, fragP
->fr_symbol
,
4499 fragP
->fr_offset
, 1, RELAX_RELOC_PC16
);
4502 case TAB (PCREL1632
, LONG
):
4503 /* Already set to mode 7.3; this indicates: PC indirect with
4504 suppressed index, 32-bit displacement. */
4505 *buffer_address
++ = 0x01;
4506 *buffer_address
++ = 0x70;
4508 fixP
= fix_new (fragP
, (int) (fragP
->fr_fix
), 4, fragP
->fr_symbol
,
4509 fragP
->fr_offset
, 1, RELAX_RELOC_PC32
);
4510 fixP
->fx_pcrel_adjust
= 2;
4513 case TAB (PCINDEX
, BYTE
):
4514 assert (fragP
->fr_fix
>= 2);
4515 buffer_address
[-2] &= ~1;
4516 fixP
= fix_new (fragP
, fragP
->fr_fix
- 1, 1, fragP
->fr_symbol
,
4517 fragP
->fr_offset
, 1, RELAX_RELOC_PC8
);
4518 fixP
->fx_pcrel_adjust
= 1;
4520 case TAB (PCINDEX
, SHORT
):
4521 assert (fragP
->fr_fix
>= 2);
4522 buffer_address
[-2] |= 0x1;
4523 buffer_address
[-1] = 0x20;
4524 fixP
= fix_new (fragP
, (int) (fragP
->fr_fix
), 2, fragP
->fr_symbol
,
4525 fragP
->fr_offset
, 1, RELAX_RELOC_PC16
);
4526 fixP
->fx_pcrel_adjust
= 2;
4529 case TAB (PCINDEX
, LONG
):
4530 assert (fragP
->fr_fix
>= 2);
4531 buffer_address
[-2] |= 0x1;
4532 buffer_address
[-1] = 0x30;
4533 fixP
= fix_new (fragP
, (int) (fragP
->fr_fix
), 4, fragP
->fr_symbol
,
4534 fragP
->fr_offset
, 1, RELAX_RELOC_PC32
);
4535 fixP
->fx_pcrel_adjust
= 2;
4538 case TAB (ABSTOPCREL
, SHORT
):
4539 fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
, fragP
->fr_offset
,
4540 1, RELAX_RELOC_PC16
);
4543 case TAB (ABSTOPCREL
, LONG
):
4544 /* The thing to do here is force it to ABSOLUTE LONG, since
4545 ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway */
4546 if ((fragP
->fr_opcode
[1] & 0x3F) != 0x3A)
4548 fragP
->fr_opcode
[1] &= ~0x3F;
4549 fragP
->fr_opcode
[1] |= 0x39; /* Mode 7.1 */
4550 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
, fragP
->fr_offset
,
4551 0, RELAX_RELOC_ABS32
);
4557 #ifndef BFD_ASSEMBLER
4560 md_convert_frag (headers
, sec
, fragP
)
4561 object_headers
*headers ATTRIBUTE_UNUSED
;
4562 segT sec ATTRIBUTE_UNUSED
;
4565 md_convert_frag_1 (fragP
);
4571 md_convert_frag (abfd
, sec
, fragP
)
4572 bfd
*abfd ATTRIBUTE_UNUSED
;
4573 segT sec ATTRIBUTE_UNUSED
;
4576 md_convert_frag_1 (fragP
);
4580 /* Force truly undefined symbols to their maximum size, and generally set up
4581 the frag list to be relaxed
4584 md_estimate_size_before_relax (fragP
, segment
)
4585 register fragS
*fragP
;
4588 /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT. */
4589 switch (fragP
->fr_subtype
)
4591 case TAB (BRANCHBWL
, SZ_UNDEF
):
4592 case TAB (BRABSJUNC
, SZ_UNDEF
):
4593 case TAB (BRABSJCOND
, SZ_UNDEF
):
4595 if (S_GET_SEGMENT (fragP
->fr_symbol
) == segment
4596 && relaxable_symbol (fragP
->fr_symbol
))
4598 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), BYTE
);
4600 else if (flag_short_refs
)
4602 /* Symbol is undefined and we want short ref. */
4603 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), SHORT
);
4607 /* Symbol is still undefined. Make it LONG. */
4608 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), LONG
);
4613 case TAB (BRANCHBW
, SZ_UNDEF
):
4615 if (S_GET_SEGMENT (fragP
->fr_symbol
) == segment
4616 && relaxable_symbol (fragP
->fr_symbol
))
4618 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), BYTE
);
4622 /* Symbol is undefined and we don't have long branches. */
4623 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), SHORT
);
4628 case TAB (FBRANCH
, SZ_UNDEF
):
4629 case TAB (DBCCLBR
, SZ_UNDEF
):
4630 case TAB (DBCCABSJ
, SZ_UNDEF
):
4631 case TAB (PCREL1632
, SZ_UNDEF
):
4633 if ((S_GET_SEGMENT (fragP
->fr_symbol
) == segment
4634 && relaxable_symbol (fragP
->fr_symbol
))
4637 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), SHORT
);
4641 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), LONG
);
4646 case TAB (PCINDEX
, SZ_UNDEF
):
4647 if ((S_GET_SEGMENT (fragP
->fr_symbol
) == segment
4648 && relaxable_symbol (fragP
->fr_symbol
)))
4650 fragP
->fr_subtype
= TAB (PCINDEX
, BYTE
);
4654 fragP
->fr_subtype
= TAB (PCINDEX
, LONG
);
4658 case TAB (ABSTOPCREL
, SZ_UNDEF
):
4660 if ((S_GET_SEGMENT (fragP
->fr_symbol
) == segment
4661 && relaxable_symbol (fragP
->fr_symbol
)))
4663 fragP
->fr_subtype
= TAB (ABSTOPCREL
, SHORT
);
4667 fragP
->fr_subtype
= TAB (ABSTOPCREL
, LONG
);
4676 /* Now that SZ_UNDEF are taken care of, check others. */
4677 switch (fragP
->fr_subtype
)
4679 case TAB (BRANCHBWL
, BYTE
):
4680 case TAB (BRABSJUNC
, BYTE
):
4681 case TAB (BRABSJCOND
, BYTE
):
4682 case TAB (BRANCHBW
, BYTE
):
4683 /* We can't do a short jump to the next instruction, so in that
4684 case we force word mode. If the symbol is at the start of a
4685 frag, and it is the next frag with any data in it (usually
4686 this is just the next frag, but assembler listings may
4687 introduce empty frags), we must use word mode. */
4688 if (fragP
->fr_symbol
)
4692 sym_frag
= symbol_get_frag (fragP
->fr_symbol
);
4693 if (S_GET_VALUE (fragP
->fr_symbol
) == sym_frag
->fr_address
)
4697 for (l
= fragP
->fr_next
; l
!= sym_frag
; l
= l
->fr_next
)
4701 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), SHORT
);
4708 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
4711 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
4712 /* the bit-field entries in the relocation_info struct plays hell
4713 with the byte-order problems of cross-assembly. So as a hack,
4714 I added this mach. dependent ri twiddler. Ugly, but it gets
4716 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
4717 are symbolnum, most sig. byte first. Last byte is broken up with
4718 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
4719 nibble as nuthin. (on Sun 3 at least) */
4720 /* Translate the internal relocation information into target-specific
4724 md_ri_to_chars (the_bytes
, ri
)
4726 struct reloc_info_generic
*ri
;
4729 md_number_to_chars (the_bytes
, ri
->r_address
, 4);
4730 /* now the fun stuff */
4731 the_bytes
[4] = (ri
->r_symbolnum
>> 16) & 0x0ff;
4732 the_bytes
[5] = (ri
->r_symbolnum
>> 8) & 0x0ff;
4733 the_bytes
[6] = ri
->r_symbolnum
& 0x0ff;
4734 the_bytes
[7] = (((ri
->r_pcrel
<< 7) & 0x80) | ((ri
->r_length
<< 5) & 0x60) |
4735 ((ri
->r_extern
<< 4) & 0x10));
4738 #endif /* comment */
4740 #ifndef BFD_ASSEMBLER
4742 tc_aout_fix_to_chars (where
, fixP
, segment_address_in_file
)
4745 relax_addressT segment_address_in_file
;
4748 * In: length of relocation (or of address) in chars: 1, 2 or 4.
4749 * Out: GNU LD relocation length code: 0, 1, or 2.
4752 static CONST
unsigned char nbytes_r_length
[] = {42, 0, 1, 42, 2};
4755 know (fixP
->fx_addsy
!= NULL
);
4757 md_number_to_chars (where
,
4758 fixP
->fx_frag
->fr_address
+ fixP
->fx_where
- segment_address_in_file
,
4761 r_symbolnum
= (S_IS_DEFINED (fixP
->fx_addsy
)
4762 ? S_GET_TYPE (fixP
->fx_addsy
)
4763 : fixP
->fx_addsy
->sy_number
);
4765 where
[4] = (r_symbolnum
>> 16) & 0x0ff;
4766 where
[5] = (r_symbolnum
>> 8) & 0x0ff;
4767 where
[6] = r_symbolnum
& 0x0ff;
4768 where
[7] = (((fixP
->fx_pcrel
<< 7) & 0x80) | ((nbytes_r_length
[fixP
->fx_size
] << 5) & 0x60) |
4769 (((!S_IS_DEFINED (fixP
->fx_addsy
)) << 4) & 0x10));
4773 #endif /* OBJ_AOUT or OBJ_BOUT */
4775 #ifndef WORKING_DOT_WORD
4776 CONST
int md_short_jump_size
= 4;
4777 CONST
int md_long_jump_size
= 6;
4780 md_create_short_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
4782 addressT from_addr
, to_addr
;
4783 fragS
*frag ATTRIBUTE_UNUSED
;
4784 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
4788 offset
= to_addr
- (from_addr
+ 2);
4790 md_number_to_chars (ptr
, (valueT
) 0x6000, 2);
4791 md_number_to_chars (ptr
+ 2, (valueT
) offset
, 2);
4795 md_create_long_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
4797 addressT from_addr
, to_addr
;
4803 if (!HAVE_LONG_BRANCH(current_architecture
))
4805 offset
= to_addr
- S_GET_VALUE (to_symbol
);
4806 md_number_to_chars (ptr
, (valueT
) 0x4EF9, 2);
4807 md_number_to_chars (ptr
+ 2, (valueT
) offset
, 4);
4808 fix_new (frag
, (ptr
+ 2) - frag
->fr_literal
, 4, to_symbol
, (offsetT
) 0,
4813 offset
= to_addr
- (from_addr
+ 2);
4814 md_number_to_chars (ptr
, (valueT
) 0x60ff, 2);
4815 md_number_to_chars (ptr
+ 2, (valueT
) offset
, 4);
4821 /* Different values of OK tell what its OK to return. Things that
4822 aren't OK are an error (what a shock, no?)
4825 10: Absolute 1:8 only
4826 20: Absolute 0:7 only
4827 30: absolute 0:15 only
4828 40: Absolute 0:31 only
4829 50: absolute 0:127 only
4830 55: absolute -64:63 only
4831 60: absolute -128:127 only
4832 70: absolute 0:4095 only
4839 struct m68k_exp
*exp
;
4842 if (exp
->exp
.X_op
== O_absent
)
4844 /* Do the same thing the VAX asm does */
4845 op (exp
) = O_constant
;
4851 as_warn (_("expression out of range: defaulting to 1"));
4855 else if (exp
->exp
.X_op
== O_constant
)
4860 if (offs (exp
) < 1 || offs (exp
) > 8)
4862 as_warn (_("expression out of range: defaulting to 1"));
4867 if (offs (exp
) < 0 || offs (exp
) > 7)
4871 if (offs (exp
) < 0 || offs (exp
) > 15)
4875 if (offs (exp
) < 0 || offs (exp
) > 32)
4879 if (offs (exp
) < 0 || offs (exp
) > 127)
4883 if (offs (exp
) < -64 || offs (exp
) > 63)
4887 if (offs (exp
) < -128 || offs (exp
) > 127)
4891 if (offs (exp
) < 0 || offs (exp
) > 4095)
4894 as_warn (_("expression out of range: defaulting to 0"));
4902 else if (exp
->exp
.X_op
== O_big
)
4904 if (offs (exp
) <= 0 /* flonum */
4905 && (ok
== 80 /* no bignums */
4906 || (ok
> 10 /* small-int ranges including 0 ok */
4907 /* If we have a flonum zero, a zero integer should
4908 do as well (e.g., in moveq). */
4909 && generic_floating_point_number
.exponent
== 0
4910 && generic_floating_point_number
.low
[0] == 0)))
4912 /* HACK! Turn it into a long */
4913 LITTLENUM_TYPE words
[6];
4915 gen_to_words (words
, 2, 8L); /* These numbers are magic! */
4916 op (exp
) = O_constant
;
4919 offs (exp
) = words
[1] | (words
[0] << 16);
4923 op (exp
) = O_constant
;
4926 offs (exp
) = (ok
== 10) ? 1 : 0;
4927 as_warn (_("Can't deal with expression; defaulting to %ld"),
4933 if (ok
>= 10 && ok
<= 70)
4935 op (exp
) = O_constant
;
4938 offs (exp
) = (ok
== 10) ? 1 : 0;
4939 as_warn (_("Can't deal with expression; defaulting to %ld"),
4944 if (exp
->size
!= SIZE_UNSPEC
)
4952 if (!isbyte (offs (exp
)))
4953 as_warn (_("expression doesn't fit in BYTE"));
4956 if (!isword (offs (exp
)))
4957 as_warn (_("expression doesn't fit in WORD"));
4965 /* These are the back-ends for the various machine dependent pseudo-ops. */
4969 int ignore ATTRIBUTE_UNUSED
;
4971 subseg_set (data_section
, 1);
4972 demand_empty_rest_of_line ();
4977 int ignore ATTRIBUTE_UNUSED
;
4979 subseg_set (data_section
, 2);
4980 demand_empty_rest_of_line ();
4985 int ignore ATTRIBUTE_UNUSED
;
4987 /* We don't support putting frags in the BSS segment, we fake it
4988 by marking in_bss, then looking at s_skip for clues. */
4990 subseg_set (bss_section
, 0);
4991 demand_empty_rest_of_line ();
4996 int ignore ATTRIBUTE_UNUSED
;
4999 register long temp_fill
;
5001 temp
= 1; /* JF should be 2? */
5002 temp_fill
= get_absolute_expression ();
5003 if (!need_pass_2
) /* Never make frag if expect extra pass. */
5004 frag_align (temp
, (int) temp_fill
, 0);
5005 demand_empty_rest_of_line ();
5006 record_alignment (now_seg
, temp
);
5011 int ignore ATTRIBUTE_UNUSED
;
5013 demand_empty_rest_of_line ();
5016 /* Pseudo-ops handled for MRI compatibility. */
5018 /* This function returns non-zero if the argument is a conditional
5019 pseudo-op. This is called when checking whether a pending
5020 alignment is needed. */
5023 m68k_conditional_pseudoop (pop
)
5026 return (pop
->poc_handler
== s_mri_if
5027 || pop
->poc_handler
== s_mri_else
);
5030 /* Handle an MRI style chip specification. */
5039 s
= input_line_pointer
;
5040 /* We can't use get_symbol_end since the processor names are not proper
5042 while (is_part_of_name (c
= *input_line_pointer
++))
5044 *--input_line_pointer
= 0;
5045 for (i
= 0; i
< n_archs
; i
++)
5046 if (strcasecmp (s
, archs
[i
].name
) == 0)
5050 as_bad (_("%s: unrecognized processor name"), s
);
5051 *input_line_pointer
= c
;
5052 ignore_rest_of_line ();
5055 *input_line_pointer
= c
;
5057 if (*input_line_pointer
== '/')
5058 current_architecture
= 0;
5060 current_architecture
&= m68881
| m68851
;
5061 current_architecture
|= archs
[i
].arch
;
5063 while (*input_line_pointer
== '/')
5065 ++input_line_pointer
;
5066 s
= input_line_pointer
;
5067 /* We can't use get_symbol_end since the processor names are not
5069 while (is_part_of_name (c
= *input_line_pointer
++))
5071 *--input_line_pointer
= 0;
5072 if (strcmp (s
, "68881") == 0)
5073 current_architecture
|= m68881
;
5074 else if (strcmp (s
, "68851") == 0)
5075 current_architecture
|= m68851
;
5076 *input_line_pointer
= c
;
5079 /* Update info about available control registers. */
5080 select_control_regs ();
5083 /* The MRI CHIP pseudo-op. */
5087 int ignore ATTRIBUTE_UNUSED
;
5093 stop
= mri_comment_field (&stopc
);
5096 mri_comment_end (stop
, stopc
);
5097 demand_empty_rest_of_line ();
5100 /* The MRI FOPT pseudo-op. */
5104 int ignore ATTRIBUTE_UNUSED
;
5108 if (strncasecmp (input_line_pointer
, "ID=", 3) == 0)
5112 input_line_pointer
+= 3;
5113 temp
= get_absolute_expression ();
5114 if (temp
< 0 || temp
> 7)
5115 as_bad (_("bad coprocessor id"));
5117 m68k_float_copnum
= COP0
+ temp
;
5121 as_bad (_("unrecognized fopt option"));
5122 ignore_rest_of_line ();
5126 demand_empty_rest_of_line ();
5129 /* The structure used to handle the MRI OPT pseudo-op. */
5133 /* The name of the option. */
5136 /* If this is not NULL, just call this function. The first argument
5137 is the ARG field of this structure, the second argument is
5138 whether the option was negated. */
5139 void (*pfn
) PARAMS ((int arg
, int on
));
5141 /* If this is not NULL, and the PFN field is NULL, set the variable
5142 this points to. Set it to the ARG field if the option was not
5143 negated, and the NOTARG field otherwise. */
5146 /* The value to pass to PFN or to assign to *PVAR. */
5149 /* The value to assign to *PVAR if the option is negated. If PFN is
5150 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5151 the option may not be negated. */
5155 /* The table used to handle the MRI OPT pseudo-op. */
5157 static void skip_to_comma
PARAMS ((int, int));
5158 static void opt_nest
PARAMS ((int, int));
5159 static void opt_chip
PARAMS ((int, int));
5160 static void opt_list
PARAMS ((int, int));
5161 static void opt_list_symbols
PARAMS ((int, int));
5163 static const struct opt_action opt_table
[] =
5165 { "abspcadd", 0, &m68k_abspcadd
, 1, 0 },
5167 /* We do relaxing, so there is little use for these options. */
5168 { "b", 0, 0, 0, 0 },
5169 { "brs", 0, 0, 0, 0 },
5170 { "brb", 0, 0, 0, 0 },
5171 { "brl", 0, 0, 0, 0 },
5172 { "brw", 0, 0, 0, 0 },
5174 { "c", 0, 0, 0, 0 },
5175 { "cex", 0, 0, 0, 0 },
5176 { "case", 0, &symbols_case_sensitive
, 1, 0 },
5177 { "cl", 0, 0, 0, 0 },
5178 { "cre", 0, 0, 0, 0 },
5179 { "d", 0, &flag_keep_locals
, 1, 0 },
5180 { "e", 0, 0, 0, 0 },
5181 { "f", 0, &flag_short_refs
, 1, 0 },
5182 { "frs", 0, &flag_short_refs
, 1, 0 },
5183 { "frl", 0, &flag_short_refs
, 0, 1 },
5184 { "g", 0, 0, 0, 0 },
5185 { "i", 0, 0, 0, 0 },
5186 { "m", 0, 0, 0, 0 },
5187 { "mex", 0, 0, 0, 0 },
5188 { "mc", 0, 0, 0, 0 },
5189 { "md", 0, 0, 0, 0 },
5190 { "nest", opt_nest
, 0, 0, 0 },
5191 { "next", skip_to_comma
, 0, 0, 0 },
5192 { "o", 0, 0, 0, 0 },
5193 { "old", 0, 0, 0, 0 },
5194 { "op", skip_to_comma
, 0, 0, 0 },
5195 { "pco", 0, 0, 0, 0 },
5196 { "p", opt_chip
, 0, 0, 0 },
5197 { "pcr", 0, 0, 0, 0 },
5198 { "pcs", 0, 0, 0, 0 },
5199 { "r", 0, 0, 0, 0 },
5200 { "quick", 0, &m68k_quick
, 1, 0 },
5201 { "rel32", 0, &m68k_rel32
, 1, 0 },
5202 { "s", opt_list
, 0, 0, 0 },
5203 { "t", opt_list_symbols
, 0, 0, 0 },
5204 { "w", 0, &flag_no_warnings
, 0, 1 },
5208 #define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0]))
5210 /* The MRI OPT pseudo-op. */
5214 int ignore ATTRIBUTE_UNUSED
;
5222 const struct opt_action
*o
;
5227 if (*input_line_pointer
== '-')
5229 ++input_line_pointer
;
5232 else if (strncasecmp (input_line_pointer
, "NO", 2) == 0)
5234 input_line_pointer
+= 2;
5238 s
= input_line_pointer
;
5239 c
= get_symbol_end ();
5241 for (i
= 0, o
= opt_table
; i
< OPTCOUNT
; i
++, o
++)
5243 if (strcasecmp (s
, o
->name
) == 0)
5247 /* Restore input_line_pointer now in case the option
5249 *input_line_pointer
= c
;
5250 (*o
->pfn
) (o
->arg
, t
);
5252 else if (o
->pvar
!= NULL
)
5254 if (! t
&& o
->arg
== o
->notarg
)
5255 as_bad (_("option `%s' may not be negated"), s
);
5256 *input_line_pointer
= c
;
5257 *o
->pvar
= t
? o
->arg
: o
->notarg
;
5260 *input_line_pointer
= c
;
5266 as_bad (_("option `%s' not recognized"), s
);
5267 *input_line_pointer
= c
;
5270 while (*input_line_pointer
++ == ',');
5272 /* Move back to terminating character. */
5273 --input_line_pointer
;
5274 demand_empty_rest_of_line ();
5277 /* Skip ahead to a comma. This is used for OPT options which we do
5278 not suppor tand which take arguments. */
5281 skip_to_comma (arg
, on
)
5282 int arg ATTRIBUTE_UNUSED
;
5283 int on ATTRIBUTE_UNUSED
;
5285 while (*input_line_pointer
!= ','
5286 && ! is_end_of_line
[(unsigned char) *input_line_pointer
])
5287 ++input_line_pointer
;
5290 /* Handle the OPT NEST=depth option. */
5294 int arg ATTRIBUTE_UNUSED
;
5295 int on ATTRIBUTE_UNUSED
;
5297 if (*input_line_pointer
!= '=')
5299 as_bad (_("bad format of OPT NEST=depth"));
5303 ++input_line_pointer
;
5304 max_macro_nest
= get_absolute_expression ();
5307 /* Handle the OPT P=chip option. */
5311 int arg ATTRIBUTE_UNUSED
;
5312 int on ATTRIBUTE_UNUSED
;
5314 if (*input_line_pointer
!= '=')
5316 /* This is just OPT P, which we do not support. */
5320 ++input_line_pointer
;
5324 /* Handle the OPT S option. */
5328 int arg ATTRIBUTE_UNUSED
;
5334 /* Handle the OPT T option. */
5337 opt_list_symbols (arg
, on
)
5338 int arg ATTRIBUTE_UNUSED
;
5342 listing
|= LISTING_SYMBOLS
;
5344 listing
&=~ LISTING_SYMBOLS
;
5347 /* Handle the MRI REG pseudo-op. */
5351 int ignore ATTRIBUTE_UNUSED
;
5360 if (line_label
== NULL
)
5362 as_bad (_("missing label"));
5363 ignore_rest_of_line ();
5368 stop
= mri_comment_field (&stopc
);
5372 s
= input_line_pointer
;
5373 while (isalnum ((unsigned char) *input_line_pointer
)
5374 #ifdef REGISTER_PREFIX
5375 || *input_line_pointer
== REGISTER_PREFIX
5377 || *input_line_pointer
== '/'
5378 || *input_line_pointer
== '-')
5379 ++input_line_pointer
;
5380 c
= *input_line_pointer
;
5381 *input_line_pointer
= '\0';
5383 if (m68k_ip_op (s
, &rop
) != 0)
5385 if (rop
.error
== NULL
)
5386 as_bad (_("bad register list"));
5388 as_bad (_("bad register list: %s"), rop
.error
);
5389 *input_line_pointer
= c
;
5390 ignore_rest_of_line ();
5394 *input_line_pointer
= c
;
5396 if (rop
.mode
== REGLST
)
5398 else if (rop
.mode
== DREG
)
5399 mask
= 1 << (rop
.reg
- DATA0
);
5400 else if (rop
.mode
== AREG
)
5401 mask
= 1 << (rop
.reg
- ADDR0
+ 8);
5402 else if (rop
.mode
== FPREG
)
5403 mask
= 1 << (rop
.reg
- FP0
+ 16);
5404 else if (rop
.mode
== CONTROL
5407 else if (rop
.mode
== CONTROL
5410 else if (rop
.mode
== CONTROL
5415 as_bad (_("bad register list"));
5416 ignore_rest_of_line ();
5420 S_SET_SEGMENT (line_label
, reg_section
);
5421 S_SET_VALUE (line_label
, ~mask
);
5422 symbol_set_frag (line_label
, &zero_address_frag
);
5425 mri_comment_end (stop
, stopc
);
5427 demand_empty_rest_of_line ();
5430 /* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5434 struct save_opts
*next
;
5436 int symbols_case_sensitive
;
5444 /* FIXME: We don't save OPT S. */
5447 /* This variable holds the stack of saved options. */
5449 static struct save_opts
*save_stack
;
5451 /* The MRI SAVE pseudo-op. */
5455 int ignore ATTRIBUTE_UNUSED
;
5457 struct save_opts
*s
;
5459 s
= (struct save_opts
*) xmalloc (sizeof (struct save_opts
));
5460 s
->abspcadd
= m68k_abspcadd
;
5461 s
->symbols_case_sensitive
= symbols_case_sensitive
;
5462 s
->keep_locals
= flag_keep_locals
;
5463 s
->short_refs
= flag_short_refs
;
5464 s
->architecture
= current_architecture
;
5465 s
->quick
= m68k_quick
;
5466 s
->rel32
= m68k_rel32
;
5467 s
->listing
= listing
;
5468 s
->no_warnings
= flag_no_warnings
;
5470 s
->next
= save_stack
;
5473 demand_empty_rest_of_line ();
5476 /* The MRI RESTORE pseudo-op. */
5480 int ignore ATTRIBUTE_UNUSED
;
5482 struct save_opts
*s
;
5484 if (save_stack
== NULL
)
5486 as_bad (_("restore without save"));
5487 ignore_rest_of_line ();
5492 save_stack
= s
->next
;
5494 m68k_abspcadd
= s
->abspcadd
;
5495 symbols_case_sensitive
= s
->symbols_case_sensitive
;
5496 flag_keep_locals
= s
->keep_locals
;
5497 flag_short_refs
= s
->short_refs
;
5498 current_architecture
= s
->architecture
;
5499 m68k_quick
= s
->quick
;
5500 m68k_rel32
= s
->rel32
;
5501 listing
= s
->listing
;
5502 flag_no_warnings
= s
->no_warnings
;
5506 demand_empty_rest_of_line ();
5509 /* Types of MRI structured control directives. */
5511 enum mri_control_type
5519 /* This structure is used to stack the MRI structured control
5522 struct mri_control_info
5524 /* The directive within which this one is enclosed. */
5525 struct mri_control_info
*outer
;
5527 /* The type of directive. */
5528 enum mri_control_type type
;
5530 /* Whether an ELSE has been in an IF. */
5533 /* The add or sub statement at the end of a FOR. */
5536 /* The label of the top of a FOR or REPEAT loop. */
5539 /* The label to jump to for the next iteration, or the else
5540 expression of a conditional. */
5543 /* The label to jump to to break out of the loop, or the label past
5544 the end of a conditional. */
5548 /* The stack of MRI structured control directives. */
5550 static struct mri_control_info
*mri_control_stack
;
5552 /* The current MRI structured control directive index number, used to
5553 generate label names. */
5555 static int mri_control_index
;
5557 /* Some function prototypes. */
5559 static void mri_assemble
PARAMS ((char *));
5560 static char *mri_control_label
PARAMS ((void));
5561 static struct mri_control_info
*push_mri_control
5562 PARAMS ((enum mri_control_type
));
5563 static void pop_mri_control
PARAMS ((void));
5564 static int parse_mri_condition
PARAMS ((int *));
5565 static int parse_mri_control_operand
5566 PARAMS ((int *, char **, char **, char **, char **));
5567 static int swap_mri_condition
PARAMS ((int));
5568 static int reverse_mri_condition
PARAMS ((int));
5569 static void build_mri_control_operand
5570 PARAMS ((int, int, char *, char *, char *, char *, const char *,
5571 const char *, int));
5572 static void parse_mri_control_expression
5573 PARAMS ((char *, int, const char *, const char *, int));
5575 /* Assemble an instruction for an MRI structured control directive. */
5583 /* md_assemble expects the opcode to be in lower case. */
5584 for (s
= str
; *s
!= ' ' && *s
!= '\0'; s
++)
5586 if (isupper ((unsigned char) *s
))
5587 *s
= tolower ((unsigned char) *s
);
5593 /* Generate a new MRI label structured control directive label name. */
5596 mri_control_label ()
5600 n
= (char *) xmalloc (20);
5601 sprintf (n
, "%smc%d", FAKE_LABEL_NAME
, mri_control_index
);
5602 ++mri_control_index
;
5606 /* Create a new MRI structured control directive. */
5608 static struct mri_control_info
*
5609 push_mri_control (type
)
5610 enum mri_control_type type
;
5612 struct mri_control_info
*n
;
5614 n
= (struct mri_control_info
*) xmalloc (sizeof (struct mri_control_info
));
5618 if (type
== mri_if
|| type
== mri_while
)
5621 n
->top
= mri_control_label ();
5622 n
->next
= mri_control_label ();
5623 n
->bottom
= mri_control_label ();
5625 n
->outer
= mri_control_stack
;
5626 mri_control_stack
= n
;
5631 /* Pop off the stack of MRI structured control directives. */
5636 struct mri_control_info
*n
;
5638 n
= mri_control_stack
;
5639 mri_control_stack
= n
->outer
;
5647 /* Recognize a condition code in an MRI structured control expression. */
5650 parse_mri_condition (pcc
)
5655 know (*input_line_pointer
== '<');
5657 ++input_line_pointer
;
5658 c1
= *input_line_pointer
++;
5659 c2
= *input_line_pointer
++;
5661 if (*input_line_pointer
!= '>')
5663 as_bad (_("syntax error in structured control directive"));
5667 ++input_line_pointer
;
5675 *pcc
= (c1
<< 8) | c2
;
5680 /* Parse a single operand in an MRI structured control expression. */
5683 parse_mri_control_operand (pcc
, leftstart
, leftstop
, rightstart
, rightstop
)
5700 if (*input_line_pointer
== '<')
5702 /* It's just a condition code. */
5703 return parse_mri_condition (pcc
);
5706 /* Look ahead for the condition code. */
5707 for (s
= input_line_pointer
; *s
!= '\0'; ++s
)
5709 if (*s
== '<' && s
[1] != '\0' && s
[2] != '\0' && s
[3] == '>')
5714 as_bad (_("missing condition code in structured control directive"));
5718 *leftstart
= input_line_pointer
;
5720 if (*leftstop
> *leftstart
5721 && ((*leftstop
)[-1] == ' ' || (*leftstop
)[-1] == '\t'))
5724 input_line_pointer
= s
;
5725 if (! parse_mri_condition (pcc
))
5728 /* Look ahead for AND or OR or end of line. */
5729 for (s
= input_line_pointer
; *s
!= '\0'; ++s
)
5731 /* We must make sure we don't misinterpret AND/OR at the end of labels!
5732 if d0 <eq> #FOOAND and d1 <ne> #BAROR then
5734 if ( ( s
== input_line_pointer
5737 && ( ( strncasecmp (s
, "AND", 3) == 0
5738 && (s
[3] == '.' || ! is_part_of_name (s
[3])))
5739 || ( strncasecmp (s
, "OR", 2) == 0
5740 && (s
[2] == '.' || ! is_part_of_name (s
[2])))))
5744 *rightstart
= input_line_pointer
;
5746 if (*rightstop
> *rightstart
5747 && ((*rightstop
)[-1] == ' ' || (*rightstop
)[-1] == '\t'))
5750 input_line_pointer
= s
;
5755 #define MCC(b1, b2) (((b1) << 8) | (b2))
5757 /* Swap the sense of a condition. This changes the condition so that
5758 it generates the same result when the operands are swapped. */
5761 swap_mri_condition (cc
)
5766 case MCC ('h', 'i'): return MCC ('c', 's');
5767 case MCC ('l', 's'): return MCC ('c', 'c');
5768 /* <HS> is an alias for <CC> */
5769 case MCC ('h', 's'):
5770 case MCC ('c', 'c'): return MCC ('l', 's');
5771 /* <LO> is an alias for <CS> */
5772 case MCC ('l', 'o'):
5773 case MCC ('c', 's'): return MCC ('h', 'i');
5774 case MCC ('p', 'l'): return MCC ('m', 'i');
5775 case MCC ('m', 'i'): return MCC ('p', 'l');
5776 case MCC ('g', 'e'): return MCC ('l', 'e');
5777 case MCC ('l', 't'): return MCC ('g', 't');
5778 case MCC ('g', 't'): return MCC ('l', 't');
5779 case MCC ('l', 'e'): return MCC ('g', 'e');
5780 /* issue a warning for conditions we can not swap */
5781 case MCC ('n', 'e'): return MCC ('n', 'e'); // no problem here
5782 case MCC ('e', 'q'): return MCC ('e', 'q'); // also no problem
5783 case MCC ('v', 'c'):
5784 case MCC ('v', 's'):
5786 as_warn (_("Condition <%c%c> in structured control directive can not be encoded correctly"),
5787 (char) (cc
>> 8), (char) (cc
));
5793 /* Reverse the sense of a condition. */
5796 reverse_mri_condition (cc
)
5801 case MCC ('h', 'i'): return MCC ('l', 's');
5802 case MCC ('l', 's'): return MCC ('h', 'i');
5803 /* <HS> is an alias for <CC> */
5804 case MCC ('h', 's'): return MCC ('l', 'o');
5805 case MCC ('c', 'c'): return MCC ('c', 's');
5806 /* <LO> is an alias for <CS> */
5807 case MCC ('l', 'o'): return MCC ('h', 's');
5808 case MCC ('c', 's'): return MCC ('c', 'c');
5809 case MCC ('n', 'e'): return MCC ('e', 'q');
5810 case MCC ('e', 'q'): return MCC ('n', 'e');
5811 case MCC ('v', 'c'): return MCC ('v', 's');
5812 case MCC ('v', 's'): return MCC ('v', 'c');
5813 case MCC ('p', 'l'): return MCC ('m', 'i');
5814 case MCC ('m', 'i'): return MCC ('p', 'l');
5815 case MCC ('g', 'e'): return MCC ('l', 't');
5816 case MCC ('l', 't'): return MCC ('g', 'e');
5817 case MCC ('g', 't'): return MCC ('l', 'e');
5818 case MCC ('l', 'e'): return MCC ('g', 't');
5823 /* Build an MRI structured control expression. This generates test
5824 and branch instructions. It goes to TRUELAB if the condition is
5825 true, and to FALSELAB if the condition is false. Exactly one of
5826 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
5827 is the size qualifier for the expression. EXTENT is the size to
5828 use for the branch. */
5831 build_mri_control_operand (qual
, cc
, leftstart
, leftstop
, rightstart
,
5832 rightstop
, truelab
, falselab
, extent
)
5839 const char *truelab
;
5840 const char *falselab
;
5846 if (leftstart
!= NULL
)
5848 struct m68k_op leftop
, rightop
;
5851 /* Swap the compare operands, if necessary, to produce a legal
5852 m68k compare instruction. Comparing a register operand with
5853 a non-register operand requires the register to be on the
5854 right (cmp, cmpa). Comparing an immediate value with
5855 anything requires the immediate value to be on the left
5860 (void) m68k_ip_op (leftstart
, &leftop
);
5865 (void) m68k_ip_op (rightstart
, &rightop
);
5868 if (rightop
.mode
== IMMED
5869 || ((leftop
.mode
== DREG
|| leftop
.mode
== AREG
)
5870 && (rightop
.mode
!= DREG
&& rightop
.mode
!= AREG
)))
5874 /* Correct conditional handling:
5875 if #1 <lt> d0 then ;means if (1 < d0)
5881 cmp #1,d0 if we do *not* swap the operands
5882 bgt true we need the swapped condition!
5889 leftstart
= rightstart
;
5892 leftstop
= rightstop
;
5895 cc
= swap_mri_condition (cc
);
5899 if (truelab
== NULL
)
5901 cc
= reverse_mri_condition (cc
);
5905 if (leftstart
!= NULL
)
5907 buf
= (char *) xmalloc (20
5908 + (leftstop
- leftstart
)
5909 + (rightstop
- rightstart
));
5915 *s
++ = tolower (qual
);
5917 memcpy (s
, leftstart
, leftstop
- leftstart
);
5918 s
+= leftstop
- leftstart
;
5920 memcpy (s
, rightstart
, rightstop
- rightstart
);
5921 s
+= rightstop
- rightstart
;
5927 buf
= (char *) xmalloc (20 + strlen (truelab
));
5933 *s
++ = tolower (extent
);
5935 strcpy (s
, truelab
);
5940 /* Parse an MRI structured control expression. This generates test
5941 and branch instructions. STOP is where the expression ends. It
5942 goes to TRUELAB if the condition is true, and to FALSELAB if the
5943 condition is false. Exactly one of TRUELAB and FALSELAB will be
5944 NULL, meaning to fall through. QUAL is the size qualifier for the
5945 expression. EXTENT is the size to use for the branch. */
5948 parse_mri_control_expression (stop
, qual
, truelab
, falselab
, extent
)
5951 const char *truelab
;
5952 const char *falselab
;
5965 if (! parse_mri_control_operand (&cc
, &leftstart
, &leftstop
,
5966 &rightstart
, &rightstop
))
5972 if (strncasecmp (input_line_pointer
, "AND", 3) == 0)
5976 if (falselab
!= NULL
)
5979 flab
= mri_control_label ();
5981 build_mri_control_operand (qual
, cc
, leftstart
, leftstop
, rightstart
,
5982 rightstop
, (const char *) NULL
, flab
, extent
);
5984 input_line_pointer
+= 3;
5985 if (*input_line_pointer
!= '.'
5986 || input_line_pointer
[1] == '\0')
5990 qual
= input_line_pointer
[1];
5991 input_line_pointer
+= 2;
5994 if (! parse_mri_control_operand (&cc
, &leftstart
, &leftstop
,
5995 &rightstart
, &rightstop
))
6001 build_mri_control_operand (qual
, cc
, leftstart
, leftstop
, rightstart
,
6002 rightstop
, truelab
, falselab
, extent
);
6004 if (falselab
== NULL
)
6007 else if (strncasecmp (input_line_pointer
, "OR", 2) == 0)
6011 if (truelab
!= NULL
)
6014 tlab
= mri_control_label ();
6016 build_mri_control_operand (qual
, cc
, leftstart
, leftstop
, rightstart
,
6017 rightstop
, tlab
, (const char *) NULL
, extent
);
6019 input_line_pointer
+= 2;
6020 if (*input_line_pointer
!= '.'
6021 || input_line_pointer
[1] == '\0')
6025 qual
= input_line_pointer
[1];
6026 input_line_pointer
+= 2;
6029 if (! parse_mri_control_operand (&cc
, &leftstart
, &leftstop
,
6030 &rightstart
, &rightstop
))
6036 build_mri_control_operand (qual
, cc
, leftstart
, leftstop
, rightstart
,
6037 rightstop
, truelab
, falselab
, extent
);
6039 if (truelab
== NULL
)
6044 build_mri_control_operand (qual
, cc
, leftstart
, leftstop
, rightstart
,
6045 rightstop
, truelab
, falselab
, extent
);
6049 if (input_line_pointer
!= stop
)
6050 as_bad (_("syntax error in structured control directive"));
6053 /* Handle the MRI IF pseudo-op. This may be a structured control
6054 directive, or it may be a regular assembler conditional, depending
6063 struct mri_control_info
*n
;
6065 /* A structured control directive must end with THEN with an
6066 optional qualifier. */
6067 s
= input_line_pointer
;
6068 /* We only accept '*' as introduction of comments if preceded by white space
6069 or at first column of a line (I think this can't actually happen here?)
6070 This is important when assembling:
6071 if d0 <ne> 12(a0,d0*2) then
6072 if d0 <ne> #CONST*20 then */
6073 while ( ! ( is_end_of_line
[(unsigned char) *s
]
6076 && ( s
== input_line_pointer
6078 || *(s
-1) == '\t'))))
6081 while (s
> input_line_pointer
&& (*s
== ' ' || *s
== '\t'))
6084 if (s
- input_line_pointer
> 1
6088 if (s
- input_line_pointer
< 3
6089 || strncasecmp (s
- 3, "THEN", 4) != 0)
6093 as_bad (_("missing then"));
6094 ignore_rest_of_line ();
6098 /* It's a conditional. */
6103 /* Since this might be a conditional if, this pseudo-op will be
6104 called even if we are supported to be ignoring input. Double
6105 check now. Clobber *input_line_pointer so that ignore_input
6106 thinks that this is not a special pseudo-op. */
6107 c
= *input_line_pointer
;
6108 *input_line_pointer
= 0;
6109 if (ignore_input ())
6111 *input_line_pointer
= c
;
6112 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6113 ++input_line_pointer
;
6114 demand_empty_rest_of_line ();
6117 *input_line_pointer
= c
;
6119 n
= push_mri_control (mri_if
);
6121 parse_mri_control_expression (s
- 3, qual
, (const char *) NULL
,
6122 n
->next
, s
[1] == '.' ? s
[2] : '\0');
6125 input_line_pointer
= s
+ 3;
6127 input_line_pointer
= s
+ 1;
6131 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6132 ++input_line_pointer
;
6135 demand_empty_rest_of_line ();
6138 /* Handle the MRI else pseudo-op. If we are currently doing an MRI
6139 structured IF, associate the ELSE with the IF. Otherwise, assume
6140 it is a conditional else. */
6151 && (mri_control_stack
== NULL
6152 || mri_control_stack
->type
!= mri_if
6153 || mri_control_stack
->else_seen
))
6159 c
= *input_line_pointer
;
6160 *input_line_pointer
= 0;
6161 if (ignore_input ())
6163 *input_line_pointer
= c
;
6164 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6165 ++input_line_pointer
;
6166 demand_empty_rest_of_line ();
6169 *input_line_pointer
= c
;
6171 if (mri_control_stack
== NULL
6172 || mri_control_stack
->type
!= mri_if
6173 || mri_control_stack
->else_seen
)
6175 as_bad (_("else without matching if"));
6176 ignore_rest_of_line ();
6180 mri_control_stack
->else_seen
= 1;
6182 buf
= (char *) xmalloc (20 + strlen (mri_control_stack
->bottom
));
6183 q
[0] = tolower (qual
);
6185 sprintf (buf
, "bra%s %s", q
, mri_control_stack
->bottom
);
6189 colon (mri_control_stack
->next
);
6193 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6194 ++input_line_pointer
;
6197 demand_empty_rest_of_line ();
6200 /* Handle the MRI ENDI pseudo-op. */
6204 int ignore ATTRIBUTE_UNUSED
;
6206 if (mri_control_stack
== NULL
6207 || mri_control_stack
->type
!= mri_if
)
6209 as_bad (_("endi without matching if"));
6210 ignore_rest_of_line ();
6214 /* ignore_input will not return true for ENDI, so we don't need to
6215 worry about checking it again here. */
6217 if (! mri_control_stack
->else_seen
)
6218 colon (mri_control_stack
->next
);
6219 colon (mri_control_stack
->bottom
);
6225 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6226 ++input_line_pointer
;
6229 demand_empty_rest_of_line ();
6232 /* Handle the MRI BREAK pseudo-op. */
6235 s_mri_break (extent
)
6238 struct mri_control_info
*n
;
6242 n
= mri_control_stack
;
6244 && n
->type
!= mri_for
6245 && n
->type
!= mri_repeat
6246 && n
->type
!= mri_while
)
6250 as_bad (_("break outside of structured loop"));
6251 ignore_rest_of_line ();
6255 buf
= (char *) xmalloc (20 + strlen (n
->bottom
));
6256 ex
[0] = tolower (extent
);
6258 sprintf (buf
, "bra%s %s", ex
, n
->bottom
);
6264 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6265 ++input_line_pointer
;
6268 demand_empty_rest_of_line ();
6271 /* Handle the MRI NEXT pseudo-op. */
6277 struct mri_control_info
*n
;
6281 n
= mri_control_stack
;
6283 && n
->type
!= mri_for
6284 && n
->type
!= mri_repeat
6285 && n
->type
!= mri_while
)
6289 as_bad (_("next outside of structured loop"));
6290 ignore_rest_of_line ();
6294 buf
= (char *) xmalloc (20 + strlen (n
->next
));
6295 ex
[0] = tolower (extent
);
6297 sprintf (buf
, "bra%s %s", ex
, n
->next
);
6303 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6304 ++input_line_pointer
;
6307 demand_empty_rest_of_line ();
6310 /* Handle the MRI FOR pseudo-op. */
6316 const char *varstart
, *varstop
;
6317 const char *initstart
, *initstop
;
6318 const char *endstart
, *endstop
;
6319 const char *bystart
, *bystop
;
6323 struct mri_control_info
*n
;
6329 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6333 varstart
= input_line_pointer
;
6335 /* Look for the '='. */
6336 while (! is_end_of_line
[(unsigned char) *input_line_pointer
]
6337 && *input_line_pointer
!= '=')
6338 ++input_line_pointer
;
6339 if (*input_line_pointer
!= '=')
6341 as_bad (_("missing ="));
6342 ignore_rest_of_line ();
6346 varstop
= input_line_pointer
;
6347 if (varstop
> varstart
6348 && (varstop
[-1] == ' ' || varstop
[-1] == '\t'))
6351 ++input_line_pointer
;
6353 initstart
= input_line_pointer
;
6355 /* Look for TO or DOWNTO. */
6358 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6360 if (strncasecmp (input_line_pointer
, "TO", 2) == 0
6361 && ! is_part_of_name (input_line_pointer
[2]))
6363 initstop
= input_line_pointer
;
6364 input_line_pointer
+= 2;
6367 if (strncasecmp (input_line_pointer
, "DOWNTO", 6) == 0
6368 && ! is_part_of_name (input_line_pointer
[6]))
6370 initstop
= input_line_pointer
;
6372 input_line_pointer
+= 6;
6375 ++input_line_pointer
;
6377 if (initstop
== NULL
)
6379 as_bad (_("missing to or downto"));
6380 ignore_rest_of_line ();
6383 if (initstop
> initstart
6384 && (initstop
[-1] == ' ' || initstop
[-1] == '\t'))
6388 endstart
= input_line_pointer
;
6390 /* Look for BY or DO. */
6393 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6395 if (strncasecmp (input_line_pointer
, "BY", 2) == 0
6396 && ! is_part_of_name (input_line_pointer
[2]))
6398 endstop
= input_line_pointer
;
6400 input_line_pointer
+= 2;
6403 if (strncasecmp (input_line_pointer
, "DO", 2) == 0
6404 && (input_line_pointer
[2] == '.'
6405 || ! is_part_of_name (input_line_pointer
[2])))
6407 endstop
= input_line_pointer
;
6408 input_line_pointer
+= 2;
6411 ++input_line_pointer
;
6413 if (endstop
== NULL
)
6415 as_bad (_("missing do"));
6416 ignore_rest_of_line ();
6419 if (endstop
> endstart
6420 && (endstop
[-1] == ' ' || endstop
[-1] == '\t'))
6426 bystop
= bystart
+ 2;
6431 bystart
= input_line_pointer
;
6435 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6437 if (strncasecmp (input_line_pointer
, "DO", 2) == 0
6438 && (input_line_pointer
[2] == '.'
6439 || ! is_part_of_name (input_line_pointer
[2])))
6441 bystop
= input_line_pointer
;
6442 input_line_pointer
+= 2;
6445 ++input_line_pointer
;
6449 as_bad (_("missing do"));
6450 ignore_rest_of_line ();
6453 if (bystop
> bystart
6454 && (bystop
[-1] == ' ' || bystop
[-1] == '\t'))
6458 if (*input_line_pointer
!= '.')
6462 extent
= input_line_pointer
[1];
6463 input_line_pointer
+= 2;
6466 /* We have fully parsed the FOR operands. Now build the loop. */
6468 n
= push_mri_control (mri_for
);
6470 buf
= (char *) xmalloc (50 + (input_line_pointer
- varstart
));
6479 *s
++ = tolower (qual
);
6481 memcpy (s
, initstart
, initstop
- initstart
);
6482 s
+= initstop
- initstart
;
6484 memcpy (s
, varstart
, varstop
- varstart
);
6485 s
+= varstop
- varstart
;
6497 *s
++ = tolower (qual
);
6499 memcpy (s
, endstart
, endstop
- endstart
);
6500 s
+= endstop
- endstart
;
6502 memcpy (s
, varstart
, varstop
- varstart
);
6503 s
+= varstop
- varstart
;
6508 ex
[0] = tolower (extent
);
6511 sprintf (buf
, "blt%s %s", ex
, n
->bottom
);
6513 sprintf (buf
, "bgt%s %s", ex
, n
->bottom
);
6516 /* Put together the add or sub instruction used by ENDF. */
6524 *s
++ = tolower (qual
);
6526 memcpy (s
, bystart
, bystop
- bystart
);
6527 s
+= bystop
- bystart
;
6529 memcpy (s
, varstart
, varstop
- varstart
);
6530 s
+= varstop
- varstart
;
6536 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6537 ++input_line_pointer
;
6540 demand_empty_rest_of_line ();
6543 /* Handle the MRI ENDF pseudo-op. */
6547 int ignore ATTRIBUTE_UNUSED
;
6549 if (mri_control_stack
== NULL
6550 || mri_control_stack
->type
!= mri_for
)
6552 as_bad (_("endf without for"));
6553 ignore_rest_of_line ();
6557 colon (mri_control_stack
->next
);
6559 mri_assemble (mri_control_stack
->incr
);
6561 sprintf (mri_control_stack
->incr
, "bra %s", mri_control_stack
->top
);
6562 mri_assemble (mri_control_stack
->incr
);
6564 free (mri_control_stack
->incr
);
6566 colon (mri_control_stack
->bottom
);
6572 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6573 ++input_line_pointer
;
6576 demand_empty_rest_of_line ();
6579 /* Handle the MRI REPEAT pseudo-op. */
6582 s_mri_repeat (ignore
)
6583 int ignore ATTRIBUTE_UNUSED
;
6585 struct mri_control_info
*n
;
6587 n
= push_mri_control (mri_repeat
);
6591 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6592 ++input_line_pointer
;
6594 demand_empty_rest_of_line ();
6597 /* Handle the MRI UNTIL pseudo-op. */
6605 if (mri_control_stack
== NULL
6606 || mri_control_stack
->type
!= mri_repeat
)
6608 as_bad (_("until without repeat"));
6609 ignore_rest_of_line ();
6613 colon (mri_control_stack
->next
);
6615 for (s
= input_line_pointer
; ! is_end_of_line
[(unsigned char) *s
]; s
++)
6618 parse_mri_control_expression (s
, qual
, (const char *) NULL
,
6619 mri_control_stack
->top
, '\0');
6621 colon (mri_control_stack
->bottom
);
6623 input_line_pointer
= s
;
6629 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6630 ++input_line_pointer
;
6633 demand_empty_rest_of_line ();
6636 /* Handle the MRI WHILE pseudo-op. */
6644 struct mri_control_info
*n
;
6646 s
= input_line_pointer
;
6647 /* We only accept '*' as introduction of comments if preceded by white space
6648 or at first column of a line (I think this can't actually happen here?)
6649 This is important when assembling:
6650 while d0 <ne> 12(a0,d0*2) do
6651 while d0 <ne> #CONST*20 do */
6652 while ( ! ( is_end_of_line
[(unsigned char) *s
]
6655 && ( s
== input_line_pointer
6657 || *(s
-1) == '\t'))))
6660 while (*s
== ' ' || *s
== '\t')
6662 if (s
- input_line_pointer
> 1
6665 if (s
- input_line_pointer
< 2
6666 || strncasecmp (s
- 1, "DO", 2) != 0)
6668 as_bad (_("missing do"));
6669 ignore_rest_of_line ();
6673 n
= push_mri_control (mri_while
);
6677 parse_mri_control_expression (s
- 1, qual
, (const char *) NULL
, n
->bottom
,
6678 s
[1] == '.' ? s
[2] : '\0');
6680 input_line_pointer
= s
+ 1;
6681 if (*input_line_pointer
== '.')
6682 input_line_pointer
+= 2;
6686 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6687 ++input_line_pointer
;
6690 demand_empty_rest_of_line ();
6693 /* Handle the MRI ENDW pseudo-op. */
6697 int ignore ATTRIBUTE_UNUSED
;
6701 if (mri_control_stack
== NULL
6702 || mri_control_stack
->type
!= mri_while
)
6704 as_bad (_("endw without while"));
6705 ignore_rest_of_line ();
6709 buf
= (char *) xmalloc (20 + strlen (mri_control_stack
->next
));
6710 sprintf (buf
, "bra %s", mri_control_stack
->next
);
6714 colon (mri_control_stack
->bottom
);
6720 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6721 ++input_line_pointer
;
6724 demand_empty_rest_of_line ();
6729 * Invocation line includes a switch not recognized by the base assembler.
6730 * See if it's a processor-specific option. These are:
6732 * -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
6733 * -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
6734 * Select the architecture. Instructions or features not
6735 * supported by the selected architecture cause fatal
6736 * errors. More than one may be specified. The default is
6737 * -m68020 -m68851 -m68881. Note that -m68008 is a synonym
6738 * for -m68000, and -m68882 is a synonym for -m68881.
6739 * -[A]m[c]no-68851, -[A]m[c]no-68881
6740 * Don't accept 688?1 instructions. (The "c" is kind of silly,
6741 * so don't use or document it, but that's the way the parsing
6744 * -pic Indicates PIC.
6745 * -k Indicates PIC. (Sun 3 only.)
6746 * --pcrel Never turn PC-relative branches into absolute jumps.
6749 * Permit `|' to be used in expressions.
6754 CONST
char *md_shortopts
= "lSA:m:kQ:V";
6756 CONST
char *md_shortopts
= "lSA:m:k";
6759 struct option md_longopts
[] = {
6760 #define OPTION_PIC (OPTION_MD_BASE)
6761 {"pic", no_argument
, NULL
, OPTION_PIC
},
6762 #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
6763 {"register-prefix-optional", no_argument
, NULL
,
6764 OPTION_REGISTER_PREFIX_OPTIONAL
},
6765 #define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
6766 {"bitwise-or", no_argument
, NULL
, OPTION_BITWISE_OR
},
6767 #define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
6768 {"base-size-default-16", no_argument
, NULL
, OPTION_BASE_SIZE_DEFAULT_16
},
6769 #define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
6770 {"base-size-default-32", no_argument
, NULL
, OPTION_BASE_SIZE_DEFAULT_32
},
6771 #define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
6772 {"disp-size-default-16", no_argument
, NULL
, OPTION_DISP_SIZE_DEFAULT_16
},
6773 #define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
6774 {"disp-size-default-32", no_argument
, NULL
, OPTION_DISP_SIZE_DEFAULT_32
},
6775 #define OPTION_PCREL (OPTION_MD_BASE + 7)
6776 {"pcrel", no_argument
, NULL
, OPTION_PCREL
},
6777 {NULL
, no_argument
, NULL
, 0}
6779 size_t md_longopts_size
= sizeof (md_longopts
);
6782 md_parse_option (c
, arg
)
6788 case 'l': /* -l means keep external to 2 bit offset
6789 rather than 16 bit one */
6790 flag_short_refs
= 1;
6793 case 'S': /* -S means that jbsr's always turn into
6795 flag_long_jumps
= 1;
6798 case OPTION_PCREL
: /* --pcrel means never turn PC-relative
6799 branches into absolute jumps. */
6800 flag_keep_pcrel
= 1;
6806 /* intentional fall-through */
6809 if (arg
[0] == 'n' && arg
[1] == 'o' && arg
[2] == '-')
6813 const char *oarg
= arg
;
6819 if (arg
[0] == 'c' && arg
[1] == '6')
6822 for (i
= 0; i
< n_archs
; i
++)
6823 if (!strcmp (arg
, archs
[i
].name
))
6828 as_bad (_("unrecognized option `%s'"), oarg
);
6831 arch
= archs
[i
].arch
;
6834 else if (arch
== m68851
)
6843 if (arg
[0] == 'c' && arg
[1] == '6')
6846 for (i
= 0; i
< n_archs
; i
++)
6847 if (!strcmp (arg
, archs
[i
].name
))
6849 unsigned long arch
= archs
[i
].arch
;
6850 if (cpu_of_arch (arch
))
6851 /* It's a cpu spec. */
6853 current_architecture
&= ~m68000up
;
6854 current_architecture
|= arch
;
6856 else if (arch
== m68881
)
6858 current_architecture
|= m68881
;
6861 else if (arch
== m68851
)
6863 current_architecture
|= m68851
;
6873 as_bad (_("unrecognized architecture specification `%s'"), arg
);
6882 break; /* -pic, Position Independent Code */
6884 case OPTION_REGISTER_PREFIX_OPTIONAL
:
6885 flag_reg_prefix_optional
= 1;
6886 reg_prefix_optional_seen
= 1;
6889 /* -V: SVR4 argument to print version ID. */
6891 print_version_id ();
6894 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
6895 should be emitted or not. FIXME: Not implemented. */
6899 case OPTION_BITWISE_OR
:
6904 n
= (char *) xmalloc (strlen (m68k_comment_chars
) + 1);
6906 for (s
= m68k_comment_chars
; *s
!= '\0'; s
++)
6910 m68k_comment_chars
= n
;
6914 case OPTION_BASE_SIZE_DEFAULT_16
:
6915 m68k_index_width_default
= SIZE_WORD
;
6918 case OPTION_BASE_SIZE_DEFAULT_32
:
6919 m68k_index_width_default
= SIZE_LONG
;
6922 case OPTION_DISP_SIZE_DEFAULT_16
:
6924 m68k_rel32_from_cmdline
= 1;
6927 case OPTION_DISP_SIZE_DEFAULT_32
:
6929 m68k_rel32_from_cmdline
= 1;
6940 md_show_usage (stream
)
6943 fprintf (stream
, _("\
6945 -l use 1 word for refs to undefined symbols [default 2]\n\
6946 -m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060 |\n\
6947 -m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360 | -mcpu32 |\n\
6948 -m5200 | -m5202 | -m5204 | -m5206 | -m5206e | -m5307 | -m5407\n\
6949 specify variant of 680X0 architecture [default 68020]\n\
6950 -m68881 | -m68882 | -mno-68881 | -mno-68882\n\
6951 target has/lacks floating-point coprocessor\n\
6952 [default yes for 68020, 68030, and cpu32]\n"));
6953 fprintf (stream
, _("\
6954 -m68851 | -mno-68851\n\
6955 target has/lacks memory-management unit coprocessor\n\
6956 [default yes for 68020 and up]\n\
6957 -pic, -k generate position independent code\n\
6958 -S turn jbsr into jsr\n\
6959 --pcrel never turn PC-relative branches into absolute jumps\n\
6960 --register-prefix-optional\n\
6961 recognize register names without prefix character\n\
6962 --bitwise-or do not treat `|' as a comment character\n"));
6963 fprintf (stream
, _("\
6964 --base-size-default-16 base reg without size is 16 bits\n\
6965 --base-size-default-32 base reg without size is 32 bits (default)\n\
6966 --disp-size-default-16 displacement with unknown size is 16 bits\n\
6967 --disp-size-default-32 displacement with unknown size is 32 bits (default)\n"));
6972 /* TEST2: Test md_assemble() */
6973 /* Warning, this routine probably doesn't work anymore */
6977 struct m68k_it the_ins
;
6985 if (!gets (buf
) || !*buf
)
6987 if (buf
[0] == '|' || buf
[1] == '.')
6989 for (cp
= buf
; *cp
; cp
++)
6994 memset (&the_ins
, '\0', sizeof (the_ins
));
6995 m68k_ip (&the_ins
, buf
);
6998 printf (_("Error %s in %s\n"), the_ins
.error
, buf
);
7002 printf (_("Opcode(%d.%s): "), the_ins
.numo
, the_ins
.args
);
7003 for (n
= 0; n
< the_ins
.numo
; n
++)
7004 printf (" 0x%x", the_ins
.opcode
[n
] & 0xffff);
7006 print_the_insn (&the_ins
.opcode
[0], stdout
);
7007 (void) putchar ('\n');
7009 for (n
= 0; n
< strlen (the_ins
.args
) / 2; n
++)
7011 if (the_ins
.operands
[n
].error
)
7013 printf ("op%d Error %s in %s\n", n
, the_ins
.operands
[n
].error
, buf
);
7016 printf ("mode %d, reg %d, ", the_ins
.operands
[n
].mode
, the_ins
.operands
[n
].reg
);
7017 if (the_ins
.operands
[n
].b_const
)
7018 printf ("Constant: '%.*s', ", 1 + the_ins
.operands
[n
].e_const
- the_ins
.operands
[n
].b_const
, the_ins
.operands
[n
].b_const
);
7019 printf ("ireg %d, isiz %d, imul %d, ", the_ins
.operands
[n
].ireg
, the_ins
.operands
[n
].isiz
, the_ins
.operands
[n
].imul
);
7020 if (the_ins
.operands
[n
].b_iadd
)
7021 printf ("Iadd: '%.*s',", 1 + the_ins
.operands
[n
].e_iadd
- the_ins
.operands
[n
].b_iadd
, the_ins
.operands
[n
].b_iadd
);
7022 (void) putchar ('\n');
7034 while (*str
&& *str
!= ' ')
7036 if (str
[-1] == ':' || str
[1] == '=')
7043 /* Possible states for relaxation:
7045 0 0 branch offset byte (bra, etc)
7049 1 0 indexed offsets byte a0@(32,d4:w:1) etc
7053 2 0 two-offset index word-word a0@(32,d4)@(45) etc
7060 /* We have no need to default values of symbols. */
7063 md_undefined_symbol (name
)
7064 char *name ATTRIBUTE_UNUSED
;
7069 /* Round up a section size to the appropriate boundary. */
7071 md_section_align (segment
, size
)
7072 segT segment ATTRIBUTE_UNUSED
;
7076 #ifdef BFD_ASSEMBLER
7077 /* For a.out, force the section size to be aligned. If we don't do
7078 this, BFD will align it for us, but it will not write out the
7079 final bytes of the section. This may be a bug in BFD, but it is
7080 easier to fix it here since that is how the other a.out targets
7084 align
= bfd_get_section_alignment (stdoutput
, segment
);
7085 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
7092 /* Exactly what point is a PC-relative offset relative TO?
7093 On the 68k, it is relative to the address of the first extension
7094 word. The difference between the addresses of the offset and the
7095 first extension word is stored in fx_pcrel_adjust. */
7097 md_pcrel_from (fixP
)
7102 /* Because fx_pcrel_adjust is a char, and may be unsigned, we explicitly
7103 sign extend the value here. */
7104 adjust
= ((fixP
->fx_pcrel_adjust
& 0xff) ^ 0x80) - 0x80;
7107 return fixP
->fx_where
+ fixP
->fx_frag
->fr_address
- adjust
;
7110 #ifndef BFD_ASSEMBLER
7114 tc_coff_symbol_emit_hook (ignore
)
7115 symbolS
*ignore ATTRIBUTE_UNUSED
;
7120 tc_coff_sizemachdep (frag
)
7123 switch (frag
->fr_subtype
& 0x3)
7140 void m68k_elf_final_processing()
7142 /* Set file-specific flags if this is a cpu32 processor */
7143 if (cpu_of_arch (current_architecture
) & cpu32
)
7144 elf_elfheader (stdoutput
)->e_flags
|= EF_CPU32
;