1 /* tc-m32r.c -- Assembler for the Mitsubishi M32R.
2 Copyright 1996, 1997, 1998, 1999, 2000, 2001
3 Free Software Foundation, Inc.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
27 #include "opcodes/m32r-desc.h"
28 #include "opcodes/m32r-opc.h"
31 /* Linked list of symbols that are debugging symbols to be defined as the
32 beginning of the current instruction. */
33 typedef struct sym_link
35 struct sym_link
*next
;
39 static sym_linkS
*debug_sym_link
= (sym_linkS
*) 0;
41 /* Structure to hold all of the different components describing
42 an individual instruction. */
45 const CGEN_INSN
*insn
;
46 const CGEN_INSN
*orig_insn
;
49 CGEN_INSN_INT buffer
[1];
50 #define INSN_VALUE(buf) (*(buf))
52 unsigned char buffer
[CGEN_MAX_INSN_SIZE
];
53 #define INSN_VALUE(buf) (buf)
58 fixS
*fixups
[GAS_CGEN_MAX_FIXUPS
];
59 int indices
[MAX_OPERAND_INSTANCES
];
60 sym_linkS
*debug_sym_link
;
64 /* prev_insn.insn is non-null if last insn was a 16 bit insn on a 32 bit
65 boundary (i.e. was the first of two 16 bit insns). */
66 static m32r_insn prev_insn
;
68 /* Non-zero if we've seen a relaxable insn since the last 32 bit
70 static int seen_relaxable_p
= 0;
72 /* Non-zero if -relax specified, in which case sufficient relocs are output
73 for the linker to do relaxing.
74 We do simple forms of relaxing internally, but they are always done.
75 This flag does not apply to them. */
76 static int m32r_relax
;
79 /* Not supported yet. */
80 /* If non-NULL, pointer to cpu description file to read.
81 This allows runtime additions to the assembler. */
82 static const char *m32r_cpu_desc
;
85 /* Non-zero if warn when a high/shigh reloc has no matching low reloc.
86 Each high/shigh reloc must be paired with it's low cousin in order to
87 properly calculate the addend in a relocatable link (since there is a
88 potential carry from the low to the high/shigh).
89 This option is off by default though for user-written assembler code it
90 might make sense to make the default be on (i.e. have gcc pass a flag
91 to turn it off). This warning must not be on for GCC created code as
92 optimization may delete the low but not the high/shigh (at least we
93 shouldn't assume or require it to). */
94 static int warn_unmatched_high
= 0;
96 /* Non-zero if -m32rx has been specified, in which case support for the
97 extended M32RX instruction set should be enabled. */
98 static int enable_m32rx
= 0;
100 /* Non-zero if -m32rx -hidden has been specified, in which case support for
101 the special M32RX instruction set should be enabled. */
102 static int enable_special
= 0;
104 /* Non-zero if the programmer should be warned when an explicit parallel
105 instruction might have constraint violations. */
106 static int warn_explicit_parallel_conflicts
= 1;
108 /* Non-zero if insns can be made parallel. */
111 /* Stuff for .scomm symbols. */
112 static segT sbss_section
;
113 static asection scom_section
;
114 static asymbol scom_symbol
;
116 const char comment_chars
[] = ";";
117 const char line_comment_chars
[] = "#";
118 const char line_separator_chars
[] = "";
119 const char EXP_CHARS
[] = "eE";
120 const char FLT_CHARS
[] = "dD";
122 /* Relocations against symbols are done in two
123 parts, with a HI relocation and a LO relocation. Each relocation
124 has only 16 bits of space to store an addend. This means that in
125 order for the linker to handle carries correctly, it must be able
126 to locate both the HI and the LO relocation. This means that the
127 relocations must appear in order in the relocation table.
129 In order to implement this, we keep track of each unmatched HI
130 relocation. We then sort them so that they immediately precede the
131 corresponding LO relocation. */
136 struct m32r_hi_fixup
*next
;
141 /* The section this fixup is in. */
145 /* The list of unmatched HI relocs. */
147 static struct m32r_hi_fixup
*m32r_hi_fixup_list
;
155 if (stdoutput
!= NULL
)
156 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
,
157 enable_m32rx
? bfd_mach_m32rx
: bfd_mach_m32r
);
160 #define M32R_SHORTOPTS "O"
162 const char *md_shortopts
= M32R_SHORTOPTS
;
164 struct option md_longopts
[] =
166 #define OPTION_M32R (OPTION_MD_BASE)
167 #define OPTION_M32RX (OPTION_M32R + 1)
168 #define OPTION_WARN_PARALLEL (OPTION_M32RX + 1)
169 #define OPTION_NO_WARN_PARALLEL (OPTION_WARN_PARALLEL + 1)
170 #define OPTION_SPECIAL (OPTION_NO_WARN_PARALLEL + 1)
171 #define OPTION_WARN_UNMATCHED (OPTION_SPECIAL + 1)
172 #define OPTION_NO_WARN_UNMATCHED (OPTION_WARN_UNMATCHED + 1)
173 {"m32r", no_argument
, NULL
, OPTION_M32R
},
174 {"m32rx", no_argument
, NULL
, OPTION_M32RX
},
175 {"warn-explicit-parallel-conflicts", no_argument
, NULL
, OPTION_WARN_PARALLEL
},
176 {"Wp", no_argument
, NULL
, OPTION_WARN_PARALLEL
},
177 {"no-warn-explicit-parallel-conflicts", no_argument
, NULL
, OPTION_NO_WARN_PARALLEL
},
178 {"Wnp", no_argument
, NULL
, OPTION_NO_WARN_PARALLEL
},
179 {"hidden", no_argument
, NULL
, OPTION_SPECIAL
},
180 /* Sigh. I guess all warnings must now have both variants. */
181 {"warn-unmatched-high", no_argument
, NULL
, OPTION_WARN_UNMATCHED
},
182 {"Wuh", no_argument
, NULL
, OPTION_WARN_UNMATCHED
},
183 {"no-warn-unmatched-high", no_argument
, NULL
, OPTION_NO_WARN_UNMATCHED
},
184 {"Wnuh", no_argument
, NULL
, OPTION_NO_WARN_UNMATCHED
},
187 /* Not supported yet. */
188 #define OPTION_RELAX (OPTION_NO_WARN_UNMATCHED + 1)
189 #define OPTION_CPU_DESC (OPTION_RELAX + 1)
190 {"relax", no_argument
, NULL
, OPTION_RELAX
},
191 {"cpu-desc", required_argument
, NULL
, OPTION_CPU_DESC
},
193 {NULL
, no_argument
, NULL
, 0}
196 size_t md_longopts_size
= sizeof (md_longopts
);
199 md_parse_option (c
, arg
)
217 case OPTION_WARN_PARALLEL
:
218 warn_explicit_parallel_conflicts
= 1;
221 case OPTION_NO_WARN_PARALLEL
:
222 warn_explicit_parallel_conflicts
= 0;
230 /* Pretend that we do not recognise this option. */
231 as_bad (_("Unrecognised option: -hidden"));
236 case OPTION_WARN_UNMATCHED
:
237 warn_unmatched_high
= 1;
240 case OPTION_NO_WARN_UNMATCHED
:
241 warn_unmatched_high
= 0;
245 /* Not supported yet. */
249 case OPTION_CPU_DESC
:
262 md_show_usage (stream
)
265 fprintf (stream
, _(" M32R specific command line options:\n"));
267 fprintf (stream
, _("\
268 -m32r disable support for the m32rx instruction set\n"));
269 fprintf (stream
, _("\
270 -m32rx support the extended m32rx instruction set\n"));
271 fprintf (stream
, _("\
272 -O try to combine instructions in parallel\n"));
274 fprintf (stream
, _("\
275 -warn-explicit-parallel-conflicts warn when parallel instructions\n"));
276 fprintf (stream
, _("\
277 violate contraints\n"));
278 fprintf (stream
, _("\
279 -no-warn-explicit-parallel-conflicts do not warn when parallel\n"));
280 fprintf (stream
, _("\
281 instructions violate contraints\n"));
282 fprintf (stream
, _("\
283 -Wp synonym for -warn-explicit-parallel-conflicts\n"));
284 fprintf (stream
, _("\
285 -Wnp synonym for -no-warn-explicit-parallel-conflicts\n"));
287 fprintf (stream
, _("\
288 -warn-unmatched-high warn when an (s)high reloc has no matching low reloc\n"));
289 fprintf (stream
, _("\
290 -no-warn-unmatched-high do not warn about missing low relocs\n"));
291 fprintf (stream
, _("\
292 -Wuh synonym for -warn-unmatched-high\n"));
293 fprintf (stream
, _("\
294 -Wnuh synonym for -no-warn-unmatched-high\n"));
297 fprintf (stream
, _("\
298 -relax create linker relaxable code\n"));
299 fprintf (stream
, _("\
300 -cpu-desc provide runtime cpu description file\n"));
304 static void fill_insn
PARAMS ((int));
305 static void m32r_scomm
PARAMS ((int));
306 static void debug_sym
PARAMS ((int));
307 static void expand_debug_syms
PARAMS ((sym_linkS
*, int));
309 /* Set by md_assemble for use by m32r_fill_insn. */
310 static subsegT prev_subseg
;
311 static segT prev_seg
;
313 /* The target specific pseudo-ops which we support. */
314 const pseudo_typeS md_pseudo_table
[] =
317 { "fillinsn", fill_insn
, 0 },
318 { "scomm", m32r_scomm
, 0 },
319 { "debugsym", debug_sym
, 0 },
320 /* Not documented as so far there is no need for them.... */
321 { "m32r", allow_m32rx
, 0 },
322 { "m32rx", allow_m32rx
, 1 },
326 /* FIXME: Should be machine generated. */
327 #define NOP_INSN 0x7000
328 #define PAR_NOP_INSN 0xf000 /* Can only be used in 2nd slot. */
330 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
331 of an rs_align_code fragment. */
334 m32r_handle_align (fragp
)
337 static const unsigned char nop_pattern
[] = { 0xf0, 0x00 };
338 static const unsigned char multi_nop_pattern
[] = { 0x70, 0x00, 0xf0, 0x00 };
343 if (fragp
->fr_type
!= rs_align_code
)
346 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
347 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
359 memcpy (p
, nop_pattern
, 2);
365 memcpy (p
, multi_nop_pattern
, 4);
367 fragp
->fr_fix
+= fix
;
371 /* If the last instruction was the first of 2 16 bit insns,
372 output a nop to move the PC to a 32 bit boundary.
374 This is done via an alignment specification since branch relaxing
375 may make it unnecessary.
377 Internally, we need to output one of these each time a 32 bit insn is
378 seen after an insn that is relaxable. */
384 frag_align_code (2, 0);
385 prev_insn
.insn
= NULL
;
386 seen_relaxable_p
= 0;
389 /* Record the symbol so that when we output the insn, we can create
390 a symbol that is at the start of the instruction. This is used
391 to emit the label for the start of a breakpoint without causing
392 the assembler to emit a NOP if the previous instruction was a
393 16 bit instruction. */
401 register char *end_name
;
402 register symbolS
*symbolP
;
403 register sym_linkS
*link
;
405 name
= input_line_pointer
;
406 delim
= get_symbol_end ();
407 end_name
= input_line_pointer
;
409 if ((symbolP
= symbol_find (name
)) == NULL
410 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
412 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
415 symbol_table_insert (symbolP
);
416 if (S_IS_DEFINED (symbolP
) && S_GET_SEGMENT (symbolP
) != reg_section
)
417 /* xgettext:c-format */
418 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
422 link
= (sym_linkS
*) xmalloc (sizeof (sym_linkS
));
423 link
->symbol
= symbolP
;
424 link
->next
= debug_sym_link
;
425 debug_sym_link
= link
;
426 symbol_get_obj (symbolP
)->local
= 1;
430 demand_empty_rest_of_line ();
433 /* Second pass to expanding the debug symbols, go through linked
434 list of symbols and reassign the address. */
437 expand_debug_syms (syms
, align
)
441 char *save_input_line
= input_line_pointer
;
442 sym_linkS
*next_syms
;
447 (void) frag_align_code (align
, 0);
448 for (; syms
!= (sym_linkS
*) 0; syms
= next_syms
)
450 symbolS
*symbolP
= syms
->symbol
;
451 next_syms
= syms
->next
;
452 input_line_pointer
= ".\n";
453 pseudo_set (symbolP
);
454 free ((char *) syms
);
457 input_line_pointer
= save_input_line
;
460 /* Cover function to fill_insn called after a label and at end of assembly.
461 The result is always 1: we're called in a conditional to see if the
462 current line is a label. */
465 m32r_fill_insn (done
)
468 if (prev_seg
!= NULL
)
471 subsegT subseg
= now_subseg
;
473 subseg_set (prev_seg
, prev_subseg
);
477 subseg_set (seg
, subseg
);
480 if (done
&& debug_sym_link
)
482 expand_debug_syms (debug_sym_link
, 1);
483 debug_sym_link
= (sym_linkS
*) 0;
496 /* Initialize the `cgen' interface. */
498 /* Set the machine number and endian. */
499 gas_cgen_cpu_desc
= m32r_cgen_cpu_open (CGEN_CPU_OPEN_MACHS
, 0,
500 CGEN_CPU_OPEN_ENDIAN
,
503 m32r_cgen_init_asm (gas_cgen_cpu_desc
);
505 /* The operand instance table is used during optimization to determine
506 which insns can be executed in parallel. It is also used to give
507 warnings regarding operand interference in parallel insns. */
508 m32r_cgen_init_opinst_table (gas_cgen_cpu_desc
);
510 /* This is a callback from cgen to gas to parse operands. */
511 cgen_set_parse_operand_fn (gas_cgen_cpu_desc
, gas_cgen_parse_operand
);
514 /* Not supported yet. */
515 /* If a runtime cpu description file was provided, parse it. */
516 if (m32r_cpu_desc
!= NULL
)
520 errmsg
= cgen_read_cpu_file (gas_cgen_cpu_desc
, m32r_cpu_desc
);
522 as_bad ("%s: %s", m32r_cpu_desc
, errmsg
);
526 /* Save the current subseg so we can restore it [it's the default one and
527 we don't want the initial section to be .sbss]. */
531 /* The sbss section is for local .scomm symbols. */
532 sbss_section
= subseg_new (".sbss", 0);
534 /* This is copied from perform_an_assembly_pass. */
535 applicable
= bfd_applicable_section_flags (stdoutput
);
536 bfd_set_section_flags (stdoutput
, sbss_section
, applicable
& SEC_ALLOC
);
539 /* What does this do? [see perform_an_assembly_pass] */
540 seg_info (bss_section
)->bss
= 1;
543 subseg_set (seg
, subseg
);
545 /* We must construct a fake section similar to bfd_com_section
546 but with the name .scommon. */
547 scom_section
= bfd_com_section
;
548 scom_section
.name
= ".scommon";
549 scom_section
.output_section
= &scom_section
;
550 scom_section
.symbol
= &scom_symbol
;
551 scom_section
.symbol_ptr_ptr
= &scom_section
.symbol
;
552 scom_symbol
= *bfd_com_section
.symbol
;
553 scom_symbol
.name
= ".scommon";
554 scom_symbol
.section
= &scom_section
;
556 allow_m32rx (enable_m32rx
);
558 gas_cgen_initialize_saved_fixups_array ();
561 #define OPERAND_IS_COND_BIT(operand, indices, index) \
562 ((operand)->hw_type == HW_H_COND \
563 || ((operand)->hw_type == HW_H_PSW) \
564 || ((operand)->hw_type == HW_H_CR \
565 && (indices [index] == 0 || indices [index] == 1)))
567 /* Returns true if an output of instruction 'a' is referenced by an operand
568 of instruction 'b'. If 'check_outputs' is true then b's outputs are
569 checked, otherwise its inputs are examined. */
572 first_writes_to_seconds_operands (a
, b
, check_outputs
)
575 const int check_outputs
;
577 const CGEN_OPINST
*a_operands
= CGEN_INSN_OPERANDS (a
->insn
);
578 const CGEN_OPINST
*b_ops
= CGEN_INSN_OPERANDS (b
->insn
);
581 /* If at least one of the instructions takes no operands, then there is
582 nothing to check. There really are instructions without operands,
584 if (a_operands
== NULL
|| b_ops
== NULL
)
587 /* Scan the operand list of 'a' looking for an output operand. */
589 a_operands
->type
!= CGEN_OPINST_END
;
590 a_index
++, a_operands
++)
592 if (a_operands
->type
== CGEN_OPINST_OUTPUT
)
595 const CGEN_OPINST
*b_operands
= b_ops
;
598 The Condition bit 'C' is a shadow of the CBR register (control
599 register 1) and also a shadow of bit 31 of the program status
600 word (control register 0). For now this is handled here, rather
603 if (OPERAND_IS_COND_BIT (a_operands
, a
->indices
, a_index
))
605 /* Scan operand list of 'b' looking for another reference to the
606 condition bit, which goes in the right direction. */
608 b_operands
->type
!= CGEN_OPINST_END
;
609 b_index
++, b_operands
++)
611 if ((b_operands
->type
614 : CGEN_OPINST_INPUT
))
615 && OPERAND_IS_COND_BIT (b_operands
, b
->indices
, b_index
))
621 /* Scan operand list of 'b' looking for an operand that
622 references the same hardware element, and which goes in the
625 b_operands
->type
!= CGEN_OPINST_END
;
626 b_index
++, b_operands
++)
628 if ((b_operands
->type
631 : CGEN_OPINST_INPUT
))
632 && (b_operands
->hw_type
== a_operands
->hw_type
)
633 && (a
->indices
[a_index
] == b
->indices
[b_index
]))
643 /* Returns true if the insn can (potentially) alter the program counter. */
650 /* Once PC operands are working.... */
651 const CGEN_OPINST
*a_operands
== CGEN_INSN_OPERANDS (gas_cgen_cpu_desc
,
654 if (a_operands
== NULL
)
657 while (a_operands
->type
!= CGEN_OPINST_END
)
659 if (a_operands
->operand
!= NULL
660 && CGEN_OPERAND_INDEX (gas_cgen_cpu_desc
,
661 a_operands
->operand
) == M32R_OPERAND_PC
)
667 if (CGEN_INSN_ATTR_VALUE (a
->insn
, CGEN_INSN_UNCOND_CTI
)
668 || CGEN_INSN_ATTR_VALUE (a
->insn
, CGEN_INSN_COND_CTI
))
674 /* Return NULL if the two 16 bit insns can be executed in parallel.
675 Otherwise return a pointer to an error message explaining why not. */
678 can_make_parallel (a
, b
)
685 /* Make sure the instructions are the right length. */
686 if (CGEN_FIELDS_BITSIZE (&a
->fields
) != 16
687 || CGEN_FIELDS_BITSIZE (&b
->fields
) != 16)
690 if (first_writes_to_seconds_operands (a
, b
, true))
691 return _("Instructions write to the same destination register.");
693 a_pipe
= CGEN_INSN_ATTR_VALUE (a
->insn
, CGEN_INSN_PIPE
);
694 b_pipe
= CGEN_INSN_ATTR_VALUE (b
->insn
, CGEN_INSN_PIPE
);
696 /* Make sure that the instructions use the correct execution pipelines. */
697 if (a_pipe
== PIPE_NONE
698 || b_pipe
== PIPE_NONE
)
699 return _("Instructions do not use parallel execution pipelines.");
701 /* Leave this test for last, since it is the only test that can
702 go away if the instructions are swapped, and we want to make
703 sure that any other errors are detected before this happens. */
706 return _("Instructions share the same execution pipeline");
711 /* Force the top bit of the second 16-bit insn to be set. */
714 make_parallel (buffer
)
715 CGEN_INSN_BYTES_PTR buffer
;
720 buffer
[CGEN_CPU_ENDIAN (gas_cgen_cpu_desc
) == CGEN_ENDIAN_BIG
? 0 : 1]
725 /* Same as make_parallel except buffer contains the bytes in target order. */
728 target_make_parallel (buffer
)
731 buffer
[CGEN_CPU_ENDIAN (gas_cgen_cpu_desc
) == CGEN_ENDIAN_BIG
? 0 : 1]
735 /* Assemble two instructions with an explicit parallel operation (||) or
736 sequential operation (->). */
739 assemble_two_insns (str
, str2
, parallel_p
)
748 char save_str2
= *str2
;
750 /* Seperate the two instructions. */
753 /* Make sure the two insns begin on a 32 bit boundary.
754 This is also done for the serial case (foo -> bar), relaxing doesn't
755 affect insns written like this.
756 Note that we must always do this as we can't assume anything about
757 whether we're currently on a 32 bit boundary or not. Relaxing may
761 first
.debug_sym_link
= debug_sym_link
;
762 debug_sym_link
= (sym_linkS
*) 0;
764 /* Parse the first instruction. */
765 if (! (first
.insn
= m32r_cgen_assemble_insn
766 (gas_cgen_cpu_desc
, str
, & first
.fields
, first
.buffer
, & errmsg
)))
773 if (CGEN_FIELDS_BITSIZE (&first
.fields
) != 16)
775 /* xgettext:c-format */
776 as_bad (_("not a 16 bit instruction '%s'"), str
);
779 else if (! enable_special
780 && CGEN_INSN_ATTR_VALUE (first
.insn
, CGEN_INSN_SPECIAL
))
782 /* xgettext:c-format */
783 as_bad (_("unknown instruction '%s'"), str
);
786 else if (! enable_m32rx
787 /* FIXME: Need standard macro to perform this test. */
788 && (CGEN_INSN_ATTR_VALUE (first
.insn
, CGEN_INSN_MACH
)
789 == (1 << MACH_M32RX
)))
791 /* xgettext:c-format */
792 as_bad (_("instruction '%s' is for the M32RX only"), str
);
796 /* Check to see if this is an allowable parallel insn. */
798 && CGEN_INSN_ATTR_VALUE (first
.insn
, CGEN_INSN_PIPE
) == PIPE_NONE
)
800 /* xgettext:c-format */
801 as_bad (_("instruction '%s' cannot be executed in parallel."), str
);
805 /* Restore the original assembly text, just in case it is needed. */
808 /* Save the original string pointer. */
811 /* Advanced past the parsed string. */
814 /* Remember the entire string in case it is needed for error
818 /* Convert the opcode to lower case. */
822 while (isspace (*s2
++))
827 while (isalnum (*s2
))
829 if (isupper ((unsigned char) *s2
))
835 /* Preserve any fixups that have been generated and reset the list
837 gas_cgen_save_fixups (0);
839 /* Get the indices of the operands of the instruction. */
840 /* FIXME: CGEN_FIELDS is already recorded, but relying on that fact
841 doesn't seem right. Perhaps allow passing fields like we do insn. */
842 /* FIXME: ALIAS insns do not have operands, so we use this function
843 to find the equivalent insn and overwrite the value stored in our
844 structure. We still need the original insn, however, since this
845 may have certain attributes that are not present in the unaliased
846 version (eg relaxability). When aliases behave differently this
847 may have to change. */
848 first
.orig_insn
= first
.insn
;
850 CGEN_FIELDS tmp_fields
;
851 first
.insn
= cgen_lookup_get_insn_operands
852 (gas_cgen_cpu_desc
, NULL
, INSN_VALUE (first
.buffer
), NULL
, 16,
853 first
.indices
, &tmp_fields
);
856 if (first
.insn
== NULL
)
857 as_fatal (_("internal error: lookup/get operands failed"));
859 second
.debug_sym_link
= NULL
;
861 /* Parse the second instruction. */
862 if (! (second
.insn
= m32r_cgen_assemble_insn
863 (gas_cgen_cpu_desc
, str
, & second
.fields
, second
.buffer
, & errmsg
)))
870 if (CGEN_FIELDS_BITSIZE (&second
.fields
) != 16)
872 /* xgettext:c-format */
873 as_bad (_("not a 16 bit instruction '%s'"), str
);
876 else if (! enable_special
877 && CGEN_INSN_ATTR_VALUE (second
.insn
, CGEN_INSN_SPECIAL
))
879 /* xgettext:c-format */
880 as_bad (_("unknown instruction '%s'"), str
);
883 else if (! enable_m32rx
884 && CGEN_INSN_ATTR_VALUE (second
.insn
, CGEN_INSN_MACH
) == (1 << MACH_M32RX
))
886 /* xgettext:c-format */
887 as_bad (_("instruction '%s' is for the M32RX only"), str
);
891 /* Check to see if this is an allowable parallel insn. */
893 && CGEN_INSN_ATTR_VALUE (second
.insn
, CGEN_INSN_PIPE
) == PIPE_NONE
)
895 /* xgettext:c-format */
896 as_bad (_("instruction '%s' cannot be executed in parallel."), str
);
900 if (parallel_p
&& ! enable_m32rx
)
902 if (CGEN_INSN_NUM (first
.insn
) != M32R_INSN_NOP
903 && CGEN_INSN_NUM (second
.insn
) != M32R_INSN_NOP
)
905 /* xgettext:c-format */
906 as_bad (_("'%s': only the NOP instruction can be issued in parallel on the m32r"), str2
);
911 /* Get the indices of the operands of the instruction. */
912 second
.orig_insn
= second
.insn
;
914 CGEN_FIELDS tmp_fields
;
915 second
.insn
= cgen_lookup_get_insn_operands
916 (gas_cgen_cpu_desc
, NULL
, INSN_VALUE (second
.buffer
), NULL
, 16,
917 second
.indices
, &tmp_fields
);
920 if (second
.insn
== NULL
)
921 as_fatal (_("internal error: lookup/get operands failed"));
923 /* We assume that if the first instruction writes to a register that is
924 read by the second instruction it is because the programmer intended
925 this to happen, (after all they have explicitly requested that these
926 two instructions be executed in parallel). Although if the global
927 variable warn_explicit_parallel_conflicts is true then we do generate
928 a warning message. Similarly we assume that parallel branch and jump
929 instructions are deliberate and should not produce errors. */
931 if (parallel_p
&& warn_explicit_parallel_conflicts
)
933 if (first_writes_to_seconds_operands (&first
, &second
, false))
934 /* xgettext:c-format */
935 as_warn (_("%s: output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?"), str2
);
937 if (first_writes_to_seconds_operands (&second
, &first
, false))
938 /* xgettext:c-format */
939 as_warn (_("%s: output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?"), str2
);
943 || (errmsg
= (char *) can_make_parallel (&first
, &second
)) == NULL
)
945 /* Get the fixups for the first instruction. */
946 gas_cgen_swap_fixups (0);
949 expand_debug_syms (first
.debug_sym_link
, 1);
950 gas_cgen_finish_insn (first
.orig_insn
, first
.buffer
,
951 CGEN_FIELDS_BITSIZE (&first
.fields
), 0, NULL
);
953 /* Force the top bit of the second insn to be set. */
955 make_parallel (second
.buffer
);
957 /* Get its fixups. */
958 gas_cgen_restore_fixups (0);
961 expand_debug_syms (second
.debug_sym_link
, 1);
962 gas_cgen_finish_insn (second
.orig_insn
, second
.buffer
,
963 CGEN_FIELDS_BITSIZE (&second
.fields
), 0, NULL
);
965 /* Try swapping the instructions to see if they work that way. */
966 else if (can_make_parallel (&second
, &first
) == NULL
)
968 /* Write out the second instruction first. */
969 expand_debug_syms (second
.debug_sym_link
, 1);
970 gas_cgen_finish_insn (second
.orig_insn
, second
.buffer
,
971 CGEN_FIELDS_BITSIZE (&second
.fields
), 0, NULL
);
973 /* Force the top bit of the first instruction to be set. */
974 make_parallel (first
.buffer
);
976 /* Get the fixups for the first instruction. */
977 gas_cgen_restore_fixups (0);
979 /* Write out the first instruction. */
980 expand_debug_syms (first
.debug_sym_link
, 1);
981 gas_cgen_finish_insn (first
.orig_insn
, first
.buffer
,
982 CGEN_FIELDS_BITSIZE (&first
.fields
), 0, NULL
);
986 as_bad ("'%s': %s", str2
, errmsg
);
990 /* Set these so m32r_fill_insn can use them. */
992 prev_subseg
= now_subseg
;
1003 /* Initialize GAS's cgen interface for a new instruction. */
1004 gas_cgen_init_parse ();
1006 /* Look for a parallel instruction seperator. */
1007 if ((str2
= strstr (str
, "||")) != NULL
)
1009 assemble_two_insns (str
, str2
, 1);
1013 /* Also look for a sequential instruction seperator. */
1014 if ((str2
= strstr (str
, "->")) != NULL
)
1016 assemble_two_insns (str
, str2
, 0);
1020 insn
.debug_sym_link
= debug_sym_link
;
1021 debug_sym_link
= (sym_linkS
*) 0;
1023 insn
.insn
= m32r_cgen_assemble_insn
1024 (gas_cgen_cpu_desc
, str
, &insn
.fields
, insn
.buffer
, & errmsg
);
1032 if (! enable_special
1033 && CGEN_INSN_ATTR_VALUE (insn
.insn
, CGEN_INSN_SPECIAL
))
1035 /* xgettext:c-format */
1036 as_bad (_("unknown instruction '%s'"), str
);
1039 else if (! enable_m32rx
1040 && CGEN_INSN_ATTR_VALUE (insn
.insn
, CGEN_INSN_MACH
) == (1 << MACH_M32RX
))
1042 /* xgettext:c-format */
1043 as_bad (_("instruction '%s' is for the M32RX only"), str
);
1047 if (CGEN_INSN_BITSIZE (insn
.insn
) == 32)
1049 /* 32 bit insns must live on 32 bit boundaries. */
1050 if (prev_insn
.insn
|| seen_relaxable_p
)
1052 /* ??? If calling fill_insn too many times turns us into a memory
1053 pig, can we call a fn to assemble a nop instead of
1054 !seen_relaxable_p? */
1058 expand_debug_syms (insn
.debug_sym_link
, 2);
1060 /* Doesn't really matter what we pass for RELAX_P here. */
1061 gas_cgen_finish_insn (insn
.insn
, insn
.buffer
,
1062 CGEN_FIELDS_BITSIZE (&insn
.fields
), 1, NULL
);
1066 int on_32bit_boundary_p
;
1069 if (CGEN_INSN_BITSIZE (insn
.insn
) != 16)
1072 insn
.orig_insn
= insn
.insn
;
1074 /* If the previous insn was relaxable, then it may be expanded
1075 to fill the current 16 bit slot. Emit a NOP here to occupy
1076 this slot, so that we can start at optimizing at a 32 bit
1078 if (prev_insn
.insn
&& seen_relaxable_p
&& optimize
)
1083 /* Get the indices of the operands of the instruction.
1084 FIXME: See assemble_parallel for notes on orig_insn. */
1086 CGEN_FIELDS tmp_fields
;
1087 insn
.insn
= cgen_lookup_get_insn_operands
1088 (gas_cgen_cpu_desc
, NULL
, INSN_VALUE (insn
.buffer
), NULL
,
1089 16, insn
.indices
, &tmp_fields
);
1092 if (insn
.insn
== NULL
)
1093 as_fatal (_("internal error: lookup/get operands failed"));
1096 /* Compute whether we're on a 32 bit boundary or not.
1097 prev_insn.insn is NULL when we're on a 32 bit boundary. */
1098 on_32bit_boundary_p
= prev_insn
.insn
== NULL
;
1100 /* Look to see if this instruction can be combined with the
1101 previous instruction to make one, parallel, 32 bit instruction.
1102 If the previous instruction (potentially) changed the flow of
1103 program control, then it cannot be combined with the current
1104 instruction. If the current instruction is relaxable, then it
1105 might be replaced with a longer version, so we cannot combine it.
1106 Also if the output of the previous instruction is used as an
1107 input to the current instruction then it cannot be combined.
1108 Otherwise call can_make_parallel() with both orderings of the
1109 instructions to see if they can be combined. */
1110 if (! on_32bit_boundary_p
1113 && CGEN_INSN_ATTR_VALUE (insn
.orig_insn
, CGEN_INSN_RELAXABLE
) == 0
1114 && ! writes_to_pc (&prev_insn
)
1115 && ! first_writes_to_seconds_operands (&prev_insn
, &insn
, false))
1117 if (can_make_parallel (&prev_insn
, &insn
) == NULL
)
1118 make_parallel (insn
.buffer
);
1119 else if (can_make_parallel (&insn
, &prev_insn
) == NULL
)
1123 expand_debug_syms (insn
.debug_sym_link
, 1);
1129 /* Ensure each pair of 16 bit insns is in the same frag. */
1132 gas_cgen_finish_insn (insn
.orig_insn
, insn
.buffer
,
1133 CGEN_FIELDS_BITSIZE (&insn
.fields
),
1134 1 /* relax_p */, &fi
);
1135 insn
.addr
= fi
.addr
;
1136 insn
.frag
= fi
.frag
;
1137 insn
.num_fixups
= fi
.num_fixups
;
1138 for (i
= 0; i
< fi
.num_fixups
; ++i
)
1139 insn
.fixups
[i
] = fi
.fixups
[i
];
1146 #define SWAP_BYTES(a,b) tmp = a; a = b; b = tmp
1148 /* Swap the two insns */
1149 SWAP_BYTES (prev_insn
.addr
[0], insn
.addr
[0]);
1150 SWAP_BYTES (prev_insn
.addr
[1], insn
.addr
[1]);
1152 target_make_parallel (insn
.addr
);
1154 /* Swap any relaxable frags recorded for the two insns. */
1155 /* FIXME: Clarify. relaxation precludes parallel insns */
1156 if (prev_insn
.frag
->fr_opcode
== prev_insn
.addr
)
1157 prev_insn
.frag
->fr_opcode
= insn
.addr
;
1158 else if (insn
.frag
->fr_opcode
== insn
.addr
)
1159 insn
.frag
->fr_opcode
= prev_insn
.addr
;
1161 /* Update the addresses in any fixups.
1162 Note that we don't have to handle the case where each insn is in
1163 a different frag as we ensure they're in the same frag above. */
1164 for (i
= 0; i
< prev_insn
.num_fixups
; ++i
)
1165 prev_insn
.fixups
[i
]->fx_where
+= 2;
1166 for (i
= 0; i
< insn
.num_fixups
; ++i
)
1167 insn
.fixups
[i
]->fx_where
-= 2;
1170 /* Keep track of whether we've seen a pair of 16 bit insns.
1171 prev_insn.insn is NULL when we're on a 32 bit boundary. */
1172 if (on_32bit_boundary_p
)
1175 prev_insn
.insn
= NULL
;
1177 /* If the insn needs the following one to be on a 32 bit boundary
1178 (e.g. subroutine calls), fill this insn's slot. */
1179 if (on_32bit_boundary_p
1180 && CGEN_INSN_ATTR_VALUE (insn
.orig_insn
, CGEN_INSN_FILL_SLOT
) != 0)
1183 /* If this is a relaxable insn (can be replaced with a larger version)
1184 mark the fact so that we can emit an alignment directive for a
1185 following 32 bit insn if we see one. */
1186 if (CGEN_INSN_ATTR_VALUE (insn
.orig_insn
, CGEN_INSN_RELAXABLE
) != 0)
1187 seen_relaxable_p
= 1;
1190 /* Set these so m32r_fill_insn can use them. */
1192 prev_subseg
= now_subseg
;
1195 /* The syntax in the manual says constants begin with '#'.
1196 We just ignore it. */
1199 md_operand (expressionP
)
1200 expressionS
*expressionP
;
1202 if (*input_line_pointer
== '#')
1204 input_line_pointer
++;
1205 expression (expressionP
);
1210 md_section_align (segment
, size
)
1214 int align
= bfd_get_section_alignment (stdoutput
, segment
);
1215 return ((size
+ (1 << align
) - 1) & (-1 << align
));
1219 md_undefined_symbol (name
)
1225 /* .scomm pseudo-op handler.
1227 This is a new pseudo-op to handle putting objects in .scommon.
1228 By doing this the linker won't need to do any work,
1229 and more importantly it removes the implicit -G arg necessary to
1230 correctly link the object file. */
1236 register char *name
;
1240 register symbolS
*symbolP
;
1244 name
= input_line_pointer
;
1245 c
= get_symbol_end ();
1247 /* Just after name is now '\0'. */
1248 p
= input_line_pointer
;
1251 if (*input_line_pointer
!= ',')
1253 as_bad (_("Expected comma after symbol-name: rest of line ignored."));
1254 ignore_rest_of_line ();
1259 input_line_pointer
++;
1260 if ((size
= get_absolute_expression ()) < 0)
1262 /* xgettext:c-format */
1263 as_warn (_(".SCOMMon length (%ld.) <0! Ignored."), (long) size
);
1264 ignore_rest_of_line ();
1268 /* The third argument to .scomm is the alignment. */
1269 if (*input_line_pointer
!= ',')
1273 ++input_line_pointer
;
1274 align
= get_absolute_expression ();
1277 as_warn (_("ignoring bad alignment"));
1282 /* Convert to a power of 2 alignment. */
1285 for (align2
= 0; (align
& 1) == 0; align
>>= 1, ++align2
)
1289 as_bad (_("Common alignment not a power of 2"));
1290 ignore_rest_of_line ();
1298 symbolP
= symbol_find_or_make (name
);
1301 if (S_IS_DEFINED (symbolP
))
1303 /* xgettext:c-format */
1304 as_bad (_("Ignoring attempt to re-define symbol `%s'."),
1305 S_GET_NAME (symbolP
));
1306 ignore_rest_of_line ();
1310 if (S_GET_VALUE (symbolP
) && S_GET_VALUE (symbolP
) != (valueT
) size
)
1312 /* xgettext:c-format */
1313 as_bad (_("Length of .scomm \"%s\" is already %ld. Not changed to %ld."),
1314 S_GET_NAME (symbolP
),
1315 (long) S_GET_VALUE (symbolP
),
1318 ignore_rest_of_line ();
1322 if (symbol_get_obj (symbolP
)->local
)
1324 segT old_sec
= now_seg
;
1325 int old_subsec
= now_subseg
;
1328 record_alignment (sbss_section
, align2
);
1329 subseg_set (sbss_section
, 0);
1332 frag_align (align2
, 0, 0);
1334 if (S_GET_SEGMENT (symbolP
) == sbss_section
)
1335 symbol_get_frag (symbolP
)->fr_symbol
= 0;
1337 symbol_set_frag (symbolP
, frag_now
);
1339 pfrag
= frag_var (rs_org
, 1, 1, (relax_substateT
) 0, symbolP
, size
,
1342 S_SET_SIZE (symbolP
, size
);
1343 S_SET_SEGMENT (symbolP
, sbss_section
);
1344 S_CLEAR_EXTERNAL (symbolP
);
1345 subseg_set (old_sec
, old_subsec
);
1349 S_SET_VALUE (symbolP
, (valueT
) size
);
1350 S_SET_ALIGN (symbolP
, align2
);
1351 S_SET_EXTERNAL (symbolP
);
1352 S_SET_SEGMENT (symbolP
, &scom_section
);
1355 demand_empty_rest_of_line ();
1358 /* Interface to relax_segment. */
1360 /* FIXME: Build table by hand, get it working, then machine generate. */
1362 const relax_typeS md_relax_table
[] =
1365 1) most positive reach of this state,
1366 2) most negative reach of this state,
1367 3) how many bytes this mode will add to the size of the current frag
1368 4) which index into the table to try if we can't fit into this one. */
1370 /* The first entry must be unused because an `rlx_more' value of zero ends
1374 /* The displacement used by GAS is from the end of the 2 byte insn,
1375 so we subtract 2 from the following. */
1376 /* 16 bit insn, 8 bit disp -> 10 bit range.
1377 This doesn't handle a branch in the right slot at the border:
1378 the "& -4" isn't taken into account. It's not important enough to
1379 complicate things over it, so we subtract an extra 2 (or + 2 in -ve
1381 {511 - 2 - 2, -512 - 2 + 2, 0, 2 },
1382 /* 32 bit insn, 24 bit disp -> 26 bit range. */
1383 {0x2000000 - 1 - 2, -0x2000000 - 2, 2, 0 },
1384 /* Same thing, but with leading nop for alignment. */
1385 {0x2000000 - 1 - 2, -0x2000000 - 2, 4, 0 }
1389 m32r_relax_frag (segment
, fragP
, stretch
)
1394 /* Address of branch insn. */
1395 long address
= fragP
->fr_address
+ fragP
->fr_fix
- 2;
1398 /* Keep 32 bit insns aligned on 32 bit boundaries. */
1399 if (fragP
->fr_subtype
== 2)
1401 if ((address
& 3) != 0)
1403 fragP
->fr_subtype
= 3;
1407 else if (fragP
->fr_subtype
== 3)
1409 if ((address
& 3) == 0)
1411 fragP
->fr_subtype
= 2;
1417 growth
= relax_frag (segment
, fragP
, stretch
);
1419 /* Long jump on odd halfword boundary? */
1420 if (fragP
->fr_subtype
== 2 && (address
& 3) != 0)
1422 fragP
->fr_subtype
= 3;
1430 /* Return an initial guess of the length by which a fragment must grow to
1431 hold a branch to reach its destination.
1432 Also updates fr_type/fr_subtype as necessary.
1434 Called just before doing relaxation.
1435 Any symbol that is now undefined will not become defined.
1436 The guess for fr_var is ACTUALLY the growth beyond fr_fix.
1437 Whatever we do to grow fr_fix or fr_var contributes to our returned value.
1438 Although it may not be explicit in the frag, pretend fr_var starts
1442 md_estimate_size_before_relax (fragP
, segment
)
1446 /* The only thing we have to handle here are symbols outside of the
1447 current segment. They may be undefined or in a different segment in
1448 which case linker scripts may place them anywhere.
1449 However, we can't finish the fragment here and emit the reloc as insn
1450 alignment requirements may move the insn about. */
1452 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
)
1454 int old_fr_fix
= fragP
->fr_fix
;
1456 /* The symbol is undefined in this segment.
1457 Change the relaxation subtype to the max allowable and leave
1458 all further handling to md_convert_frag. */
1459 fragP
->fr_subtype
= 2;
1462 /* Can't use this, but leave in for illustration. */
1463 /* Change 16 bit insn to 32 bit insn. */
1464 fragP
->fr_opcode
[0] |= 0x80;
1466 /* Increase known (fixed) size of fragment. */
1469 /* Create a relocation for it. */
1470 fix_new (fragP
, old_fr_fix
, 4,
1472 fragP
->fr_offset
, 1 /* pcrel */,
1473 /* FIXME: Can't use a real BFD reloc here.
1474 gas_cgen_md_apply_fix3 can't handle it. */
1475 BFD_RELOC_M32R_26_PCREL
);
1477 /* Mark this fragment as finished. */
1479 return fragP
->fr_fix
- old_fr_fix
;
1482 const CGEN_INSN
*insn
;
1485 /* Update the recorded insn.
1486 Fortunately we don't have to look very far.
1487 FIXME: Change this to record in the instruction the next higher
1488 relaxable insn to use. */
1489 for (i
= 0, insn
= fragP
->fr_cgen
.insn
; i
< 4; i
++, insn
++)
1491 if ((strcmp (CGEN_INSN_MNEMONIC (insn
),
1492 CGEN_INSN_MNEMONIC (fragP
->fr_cgen
.insn
))
1494 && CGEN_INSN_ATTR_VALUE (insn
, CGEN_INSN_RELAX
))
1500 fragP
->fr_cgen
.insn
= insn
;
1506 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
1509 /* *FRAGP has been relaxed to its final size, and now needs to have
1510 the bytes inside it modified to conform to the new size.
1512 Called after relaxation is finished.
1513 fragP->fr_type == rs_machine_dependent.
1514 fragP->fr_subtype is the subtype of what the address relaxed to. */
1517 md_convert_frag (abfd
, sec
, fragP
)
1529 opcode
= fragP
->fr_opcode
;
1531 /* Address opcode resides at in file space. */
1532 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
- 2;
1534 switch (fragP
->fr_subtype
)
1538 displacement
= &opcode
[1];
1543 displacement
= &opcode
[1];
1546 opcode
[2] = opcode
[0] | 0x80;
1547 md_number_to_chars (opcode
, PAR_NOP_INSN
, 2);
1548 opcode_address
+= 2;
1550 displacement
= &opcode
[3];
1556 if (S_GET_SEGMENT (fragP
->fr_symbol
) != sec
)
1558 /* Symbol must be resolved by linker. */
1559 if (fragP
->fr_offset
& 3)
1560 as_warn (_("Addend to unresolved symbol not on word boundary."));
1561 addend
= fragP
->fr_offset
>> 2;
1565 /* Address we want to reach in file space. */
1566 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
1567 addend
= (target_address
- (opcode_address
& -4)) >> 2;
1570 /* Create a relocation for symbols that must be resolved by the linker.
1571 Otherwise output the completed insn. */
1573 if (S_GET_SEGMENT (fragP
->fr_symbol
) != sec
)
1575 assert (fragP
->fr_subtype
!= 1);
1576 assert (fragP
->fr_cgen
.insn
!= 0);
1577 gas_cgen_record_fixup (fragP
,
1578 /* Offset of branch insn in frag. */
1579 fragP
->fr_fix
+ extension
- 4,
1580 fragP
->fr_cgen
.insn
,
1582 /* FIXME: quick hack. */
1584 cgen_operand_lookup_by_num (gas_cgen_cpu_desc
,
1585 fragP
->fr_cgen
.opindex
),
1587 cgen_operand_lookup_by_num (gas_cgen_cpu_desc
,
1588 M32R_OPERAND_DISP24
),
1590 fragP
->fr_cgen
.opinfo
,
1591 fragP
->fr_symbol
, fragP
->fr_offset
);
1594 #define SIZE_FROM_RELAX_STATE(n) ((n) == 1 ? 1 : 3)
1596 md_number_to_chars (displacement
, (valueT
) addend
,
1597 SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
1599 fragP
->fr_fix
+= extension
;
1602 /* Functions concerning relocs. */
1604 /* The location from which a PC relative jump should be calculated,
1605 given a PC relative reloc. */
1608 md_pcrel_from_section (fixP
, sec
)
1612 if (fixP
->fx_addsy
!= (symbolS
*) NULL
1613 && (! S_IS_DEFINED (fixP
->fx_addsy
)
1614 || S_GET_SEGMENT (fixP
->fx_addsy
) != sec
))
1616 /* The symbol is undefined (or is defined but not in this section).
1617 Let the linker figure it out. */
1621 return (fixP
->fx_frag
->fr_address
+ fixP
->fx_where
) & -4L;
1624 /* Return the bfd reloc type for OPERAND of INSN at fixup FIXP.
1625 Returns BFD_RELOC_NONE if no reloc type can be found.
1626 *FIXP may be modified if desired. */
1628 bfd_reloc_code_real_type
1629 md_cgen_lookup_reloc (insn
, operand
, fixP
)
1630 const CGEN_INSN
*insn
;
1631 const CGEN_OPERAND
*operand
;
1634 switch (operand
->type
)
1636 case M32R_OPERAND_DISP8
: return BFD_RELOC_M32R_10_PCREL
;
1637 case M32R_OPERAND_DISP16
: return BFD_RELOC_M32R_18_PCREL
;
1638 case M32R_OPERAND_DISP24
: return BFD_RELOC_M32R_26_PCREL
;
1639 case M32R_OPERAND_UIMM24
: return BFD_RELOC_M32R_24
;
1640 case M32R_OPERAND_HI16
:
1641 case M32R_OPERAND_SLO16
:
1642 case M32R_OPERAND_ULO16
:
1643 /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */
1644 if (fixP
->fx_cgen
.opinfo
!= 0)
1645 return fixP
->fx_cgen
.opinfo
;
1648 /* Avoid -Wall warning. */
1651 return BFD_RELOC_NONE
;
1654 /* Record a HI16 reloc for later matching with its LO16 cousin. */
1657 m32r_record_hi16 (reloc_type
, fixP
, seg
)
1662 struct m32r_hi_fixup
*hi_fixup
;
1664 assert (reloc_type
== BFD_RELOC_M32R_HI16_SLO
1665 || reloc_type
== BFD_RELOC_M32R_HI16_ULO
);
1667 hi_fixup
= ((struct m32r_hi_fixup
*)
1668 xmalloc (sizeof (struct m32r_hi_fixup
)));
1669 hi_fixup
->fixp
= fixP
;
1670 hi_fixup
->seg
= now_seg
;
1671 hi_fixup
->next
= m32r_hi_fixup_list
;
1673 m32r_hi_fixup_list
= hi_fixup
;
1676 /* Called while parsing an instruction to create a fixup.
1677 We need to check for HI16 relocs and queue them up for later sorting. */
1680 m32r_cgen_record_fixup_exp (frag
, where
, insn
, length
, operand
, opinfo
, exp
)
1683 const CGEN_INSN
*insn
;
1685 const CGEN_OPERAND
*operand
;
1689 fixS
*fixP
= gas_cgen_record_fixup_exp (frag
, where
, insn
, length
,
1690 operand
, opinfo
, exp
);
1692 switch (operand
->type
)
1694 case M32R_OPERAND_HI16
:
1695 /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */
1696 if (fixP
->fx_cgen
.opinfo
== BFD_RELOC_M32R_HI16_SLO
1697 || fixP
->fx_cgen
.opinfo
== BFD_RELOC_M32R_HI16_ULO
)
1698 m32r_record_hi16 (fixP
->fx_cgen
.opinfo
, fixP
, now_seg
);
1701 /* Avoid -Wall warning */
1708 /* Return BFD reloc type from opinfo field in a fixS.
1709 It's tricky using fx_r_type in m32r_frob_file because the values
1710 are BFD_RELOC_UNUSED + operand number. */
1711 #define FX_OPINFO_R_TYPE(f) ((f)->fx_cgen.opinfo)
1713 /* Sort any unmatched HI16 relocs so that they immediately precede
1714 the corresponding LO16 reloc. This is called before md_apply_fix and
1720 struct m32r_hi_fixup
*l
;
1722 for (l
= m32r_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
1724 segment_info_type
*seginfo
;
1727 assert (FX_OPINFO_R_TYPE (l
->fixp
) == BFD_RELOC_M32R_HI16_SLO
1728 || FX_OPINFO_R_TYPE (l
->fixp
) == BFD_RELOC_M32R_HI16_ULO
);
1730 /* Check quickly whether the next fixup happens to be a matching low. */
1731 if (l
->fixp
->fx_next
!= NULL
1732 && FX_OPINFO_R_TYPE (l
->fixp
->fx_next
) == BFD_RELOC_M32R_LO16
1733 && l
->fixp
->fx_addsy
== l
->fixp
->fx_next
->fx_addsy
1734 && l
->fixp
->fx_offset
== l
->fixp
->fx_next
->fx_offset
)
1737 /* Look through the fixups for this segment for a matching `low'.
1738 When we find one, move the high/shigh just in front of it. We do
1739 this in two passes. In the first pass, we try to find a
1740 unique `low'. In the second pass, we permit multiple high's
1741 relocs for a single `low'. */
1742 seginfo
= seg_info (l
->seg
);
1743 for (pass
= 0; pass
< 2; pass
++)
1749 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
1751 /* Check whether this is a `low' fixup which matches l->fixp. */
1752 if (FX_OPINFO_R_TYPE (f
) == BFD_RELOC_M32R_LO16
1753 && f
->fx_addsy
== l
->fixp
->fx_addsy
1754 && f
->fx_offset
== l
->fixp
->fx_offset
1757 || (FX_OPINFO_R_TYPE (prev
) != BFD_RELOC_M32R_HI16_SLO
1758 && FX_OPINFO_R_TYPE (prev
) != BFD_RELOC_M32R_HI16_ULO
)
1759 || prev
->fx_addsy
!= f
->fx_addsy
1760 || prev
->fx_offset
!= f
->fx_offset
))
1764 /* Move l->fixp before f. */
1765 for (pf
= &seginfo
->fix_root
;
1767 pf
= & (*pf
)->fx_next
)
1768 assert (*pf
!= NULL
);
1770 *pf
= l
->fixp
->fx_next
;
1772 l
->fixp
->fx_next
= f
;
1774 seginfo
->fix_root
= l
->fixp
;
1776 prev
->fx_next
= l
->fixp
;
1788 && warn_unmatched_high
)
1789 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
1790 _("Unmatched high/shigh reloc"));
1795 /* See whether we need to force a relocation into the output file.
1796 This is used to force out switch and PC relative relocations when
1800 m32r_force_relocation (fix
)
1803 if (fix
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1804 || fix
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1810 return fix
->fx_pcrel
;
1813 /* Write a value out to the object file, using the appropriate endianness. */
1816 md_number_to_chars (buf
, val
, n
)
1821 if (target_big_endian
)
1822 number_to_chars_bigendian (buf
, val
, n
);
1824 number_to_chars_littleendian (buf
, val
, n
);
1827 /* Turn a string in input_line_pointer into a floating point constant
1828 of type TYPE, and store the appropriate bytes in *LITP. The number
1829 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1830 returned, or NULL on OK. */
1832 /* Equal to MAX_PRECISION in atof-ieee.c. */
1833 #define MAX_LITTLENUMS 6
1836 md_atof (type
, litP
, sizeP
)
1843 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1863 /* FIXME: Some targets allow other format chars for bigger sizes
1868 return _("Bad call to md_atof()");
1871 t
= atof_ieee (input_line_pointer
, type
, words
);
1873 input_line_pointer
= t
;
1874 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1876 if (target_big_endian
)
1878 for (i
= 0; i
< prec
; i
++)
1880 md_number_to_chars (litP
, (valueT
) words
[i
],
1881 sizeof (LITTLENUM_TYPE
));
1882 litP
+= sizeof (LITTLENUM_TYPE
);
1887 for (i
= prec
- 1; i
>= 0; i
--)
1889 md_number_to_chars (litP
, (valueT
) words
[i
],
1890 sizeof (LITTLENUM_TYPE
));
1891 litP
+= sizeof (LITTLENUM_TYPE
);
1899 m32r_elf_section_change_hook ()
1901 /* If we have reached the end of a section and we have just emitted a
1902 16 bit insn, then emit a nop to make sure that the section ends on
1903 a 32 bit boundary. */
1905 if (prev_insn
.insn
|| seen_relaxable_p
)
1906 (void) m32r_fill_insn (0);
1909 /* Return true if can adjust the reloc to be relative to its section
1910 (such as .data) instead of relative to some symbol. */
1913 m32r_fix_adjustable (fixP
)
1917 bfd_reloc_code_real_type reloc_type
;
1919 if ((int) fixP
->fx_r_type
>= (int) BFD_RELOC_UNUSED
)
1921 const CGEN_INSN
*insn
= NULL
;
1922 int opindex
= (int) fixP
->fx_r_type
- (int) BFD_RELOC_UNUSED
;
1923 const CGEN_OPERAND
*operand
=
1924 cgen_operand_lookup_by_num(gas_cgen_cpu_desc
, opindex
);
1925 reloc_type
= md_cgen_lookup_reloc (insn
, operand
, fixP
);
1928 reloc_type
= fixP
->fx_r_type
;
1930 if (fixP
->fx_addsy
== NULL
)
1933 /* Prevent all adjustments to global symbols. */
1934 if (S_IS_EXTERN (fixP
->fx_addsy
))
1936 if (S_IS_WEAK (fixP
->fx_addsy
))
1939 /* We need the symbol name for the VTABLE entries. */
1940 if (reloc_type
== BFD_RELOC_VTABLE_INHERIT
1941 || reloc_type
== BFD_RELOC_VTABLE_ENTRY
)