1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
5 Contributed by the OSF and Ralph Campbell.
6 Written by Keith Knowles and Ralph Campbell, working independently.
7 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
10 This file is part of GAS.
12 GAS is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GAS is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GAS; see the file COPYING. If not, write to the Free
24 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
32 #include "opcode/mips.h"
34 #include "dwarf2dbg.h"
35 #include "dw2gencfi.h"
38 #define DBG(x) printf x
44 /* Clean up namespace so we can include obj-elf.h too. */
45 static int mips_output_flavor (void);
46 static int mips_output_flavor (void) { return OUTPUT_FLAVOR
; }
47 #undef OBJ_PROCESS_STAB
54 #undef obj_frob_file_after_relocs
55 #undef obj_frob_symbol
57 #undef obj_sec_sym_ok_for_reloc
58 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
61 /* Fix any of them that we actually care about. */
63 #define OUTPUT_FLAVOR mips_output_flavor()
70 #ifndef ECOFF_DEBUGGING
71 #define NO_ECOFF_DEBUGGING
72 #define ECOFF_DEBUGGING 0
75 int mips_flag_mdebug
= -1;
77 /* Control generation of .pdr sections. Off by default on IRIX: the native
78 linker doesn't know about and discards them, but relocations against them
79 remain, leading to rld crashes. */
81 int mips_flag_pdr
= FALSE
;
83 int mips_flag_pdr
= TRUE
;
88 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
89 static char *mips_regmask_frag
;
95 #define PIC_CALL_REG 25
103 #define ILLEGAL_REG (32)
105 #define AT mips_opts.at
107 /* Allow override of standard little-endian ECOFF format. */
109 #ifndef ECOFF_LITTLE_FORMAT
110 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
113 extern int target_big_endian
;
115 /* The name of the readonly data section. */
116 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
118 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
120 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
124 /* Information about an instruction, including its format, operands
128 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
129 const struct mips_opcode
*insn_mo
;
131 /* True if this is a mips16 instruction and if we want the extended
133 bfd_boolean use_extend
;
135 /* The 16-bit extension instruction to use when USE_EXTEND is true. */
136 unsigned short extend
;
138 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
139 a copy of INSN_MO->match with the operands filled in. */
140 unsigned long insn_opcode
;
142 /* The frag that contains the instruction. */
145 /* The offset into FRAG of the first instruction byte. */
148 /* The relocs associated with the instruction, if any. */
151 /* True if this entry cannot be moved from its current position. */
152 unsigned int fixed_p
: 1;
154 /* True if this instruction occurred in a .set noreorder block. */
155 unsigned int noreorder_p
: 1;
157 /* True for mips16 instructions that jump to an absolute address. */
158 unsigned int mips16_absolute_jump_p
: 1;
160 /* True if this instruction is complete. */
161 unsigned int complete_p
: 1;
164 /* The ABI to use. */
175 /* MIPS ABI we are using for this output file. */
176 static enum mips_abi_level mips_abi
= NO_ABI
;
178 /* Whether or not we have code that can call pic code. */
179 int mips_abicalls
= FALSE
;
181 /* Whether or not we have code which can be put into a shared
183 static bfd_boolean mips_in_shared
= TRUE
;
185 /* This is the set of options which may be modified by the .set
186 pseudo-op. We use a struct so that .set push and .set pop are more
189 struct mips_set_options
191 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
192 if it has not been initialized. Changed by `.set mipsN', and the
193 -mipsN command line option, and the default CPU. */
195 /* Enabled Application Specific Extensions (ASEs). These are set to -1
196 if they have not been initialized. Changed by `.set <asename>', by
197 command line options, and based on the default architecture. */
204 /* Whether we are assembling for the mips16 processor. 0 if we are
205 not, 1 if we are, and -1 if the value has not been initialized.
206 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
207 -nomips16 command line options, and the default CPU. */
209 /* Non-zero if we should not reorder instructions. Changed by `.set
210 reorder' and `.set noreorder'. */
212 /* Non-zero if we should not permit the register designated "assembler
213 temporary" to be used in instructions. The value is the register
214 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
215 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
217 /* Non-zero if we should warn when a macro instruction expands into
218 more than one machine instruction. Changed by `.set nomacro' and
220 int warn_about_macros
;
221 /* Non-zero if we should not move instructions. Changed by `.set
222 move', `.set volatile', `.set nomove', and `.set novolatile'. */
224 /* Non-zero if we should not optimize branches by moving the target
225 of the branch into the delay slot. Actually, we don't perform
226 this optimization anyhow. Changed by `.set bopt' and `.set
229 /* Non-zero if we should not autoextend mips16 instructions.
230 Changed by `.set autoextend' and `.set noautoextend'. */
232 /* Restrict general purpose registers and floating point registers
233 to 32 bit. This is initially determined when -mgp32 or -mfp32
234 is passed but can changed if the assembler code uses .set mipsN. */
237 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
238 command line option, and the default CPU. */
240 /* True if ".set sym32" is in effect. */
242 /* True if floating-point operations are not allowed. Changed by .set
243 softfloat or .set hardfloat, by command line options -msoft-float or
244 -mhard-float. The default is false. */
245 bfd_boolean soft_float
;
247 /* True if only single-precision floating-point operations are allowed.
248 Changed by .set singlefloat or .set doublefloat, command-line options
249 -msingle-float or -mdouble-float. The default is false. */
250 bfd_boolean single_float
;
253 /* This is the struct we use to hold the current set of options. Note
254 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
255 -1 to indicate that they have not been initialized. */
257 /* True if -mgp32 was passed. */
258 static int file_mips_gp32
= -1;
260 /* True if -mfp32 was passed. */
261 static int file_mips_fp32
= -1;
263 /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */
264 static int file_mips_soft_float
= 0;
266 /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */
267 static int file_mips_single_float
= 0;
269 static struct mips_set_options mips_opts
=
271 /* isa */ ISA_UNKNOWN
, /* ase_mips3d */ -1, /* ase_mdmx */ -1,
272 /* ase_smartmips */ 0, /* ase_dsp */ -1, /* ase_dspr2 */ -1, /* ase_mt */ -1,
273 /* mips16 */ -1, /* noreorder */ 0, /* at */ ATREG
,
274 /* warn_about_macros */ 0, /* nomove */ 0, /* nobopt */ 0,
275 /* noautoextend */ 0, /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN
,
276 /* sym32 */ FALSE
, /* soft_float */ FALSE
, /* single_float */ FALSE
279 /* These variables are filled in with the masks of registers used.
280 The object format code reads them and puts them in the appropriate
282 unsigned long mips_gprmask
;
283 unsigned long mips_cprmask
[4];
285 /* MIPS ISA we are using for this output file. */
286 static int file_mips_isa
= ISA_UNKNOWN
;
288 /* True if any MIPS16 code was produced. */
289 static int file_ase_mips16
;
291 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
292 || mips_opts.isa == ISA_MIPS32R2 \
293 || mips_opts.isa == ISA_MIPS64 \
294 || mips_opts.isa == ISA_MIPS64R2)
296 /* True if we want to create R_MIPS_JALR for jalr $25. */
298 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
300 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
301 because there's no place for any addend, the only acceptable
302 expression is a bare symbol. */
303 #define MIPS_JALR_HINT_P(EXPR) \
304 (!HAVE_IN_PLACE_ADDENDS \
305 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
308 /* True if -mips3d was passed or implied by arguments passed on the
309 command line (e.g., by -march). */
310 static int file_ase_mips3d
;
312 /* True if -mdmx was passed or implied by arguments passed on the
313 command line (e.g., by -march). */
314 static int file_ase_mdmx
;
316 /* True if -msmartmips was passed or implied by arguments passed on the
317 command line (e.g., by -march). */
318 static int file_ase_smartmips
;
320 #define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \
321 || mips_opts.isa == ISA_MIPS32R2)
323 /* True if -mdsp was passed or implied by arguments passed on the
324 command line (e.g., by -march). */
325 static int file_ase_dsp
;
327 #define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2 \
328 || mips_opts.isa == ISA_MIPS64R2)
330 #define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2)
332 /* True if -mdspr2 was passed or implied by arguments passed on the
333 command line (e.g., by -march). */
334 static int file_ase_dspr2
;
336 #define ISA_SUPPORTS_DSPR2_ASE (mips_opts.isa == ISA_MIPS32R2 \
337 || mips_opts.isa == ISA_MIPS64R2)
339 /* True if -mmt was passed or implied by arguments passed on the
340 command line (e.g., by -march). */
341 static int file_ase_mt
;
343 #define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2 \
344 || mips_opts.isa == ISA_MIPS64R2)
346 /* The argument of the -march= flag. The architecture we are assembling. */
347 static int file_mips_arch
= CPU_UNKNOWN
;
348 static const char *mips_arch_string
;
350 /* The argument of the -mtune= flag. The architecture for which we
352 static int mips_tune
= CPU_UNKNOWN
;
353 static const char *mips_tune_string
;
355 /* True when generating 32-bit code for a 64-bit processor. */
356 static int mips_32bitmode
= 0;
358 /* True if the given ABI requires 32-bit registers. */
359 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
361 /* Likewise 64-bit registers. */
362 #define ABI_NEEDS_64BIT_REGS(ABI) \
364 || (ABI) == N64_ABI \
367 /* Return true if ISA supports 64 bit wide gp registers. */
368 #define ISA_HAS_64BIT_REGS(ISA) \
369 ((ISA) == ISA_MIPS3 \
370 || (ISA) == ISA_MIPS4 \
371 || (ISA) == ISA_MIPS5 \
372 || (ISA) == ISA_MIPS64 \
373 || (ISA) == ISA_MIPS64R2)
375 /* Return true if ISA supports 64 bit wide float registers. */
376 #define ISA_HAS_64BIT_FPRS(ISA) \
377 ((ISA) == ISA_MIPS3 \
378 || (ISA) == ISA_MIPS4 \
379 || (ISA) == ISA_MIPS5 \
380 || (ISA) == ISA_MIPS32R2 \
381 || (ISA) == ISA_MIPS64 \
382 || (ISA) == ISA_MIPS64R2)
384 /* Return true if ISA supports 64-bit right rotate (dror et al.)
386 #define ISA_HAS_DROR(ISA) \
387 ((ISA) == ISA_MIPS64R2)
389 /* Return true if ISA supports 32-bit right rotate (ror et al.)
391 #define ISA_HAS_ROR(ISA) \
392 ((ISA) == ISA_MIPS32R2 \
393 || (ISA) == ISA_MIPS64R2 \
394 || mips_opts.ase_smartmips)
396 /* Return true if ISA supports single-precision floats in odd registers. */
397 #define ISA_HAS_ODD_SINGLE_FPR(ISA) \
398 ((ISA) == ISA_MIPS32 \
399 || (ISA) == ISA_MIPS32R2 \
400 || (ISA) == ISA_MIPS64 \
401 || (ISA) == ISA_MIPS64R2)
403 /* Return true if ISA supports move to/from high part of a 64-bit
404 floating-point register. */
405 #define ISA_HAS_MXHC1(ISA) \
406 ((ISA) == ISA_MIPS32R2 \
407 || (ISA) == ISA_MIPS64R2)
409 #define HAVE_32BIT_GPRS \
410 (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
412 #define HAVE_32BIT_FPRS \
413 (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
415 #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
416 #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
418 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
420 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
422 /* True if relocations are stored in-place. */
423 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
425 /* The ABI-derived address size. */
426 #define HAVE_64BIT_ADDRESSES \
427 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
428 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
430 /* The size of symbolic constants (i.e., expressions of the form
431 "SYMBOL" or "SYMBOL + OFFSET"). */
432 #define HAVE_32BIT_SYMBOLS \
433 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
434 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
436 /* Addresses are loaded in different ways, depending on the address size
437 in use. The n32 ABI Documentation also mandates the use of additions
438 with overflow checking, but existing implementations don't follow it. */
439 #define ADDRESS_ADD_INSN \
440 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
442 #define ADDRESS_ADDI_INSN \
443 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
445 #define ADDRESS_LOAD_INSN \
446 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
448 #define ADDRESS_STORE_INSN \
449 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
451 /* Return true if the given CPU supports the MIPS16 ASE. */
452 #define CPU_HAS_MIPS16(cpu) \
453 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
454 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
456 /* True if CPU has a dror instruction. */
457 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
459 /* True if CPU has a ror instruction. */
460 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
462 /* True if CPU has seq/sne and seqi/snei instructions. */
463 #define CPU_HAS_SEQ(CPU) ((CPU) == CPU_OCTEON)
465 /* True if CPU does not implement the all the coprocessor insns. For these
466 CPUs only those COP insns are accepted that are explicitly marked to be
467 available on the CPU. ISA membership for COP insns is ignored. */
468 #define NO_ISA_COP(CPU) ((CPU) == CPU_OCTEON)
470 /* True if mflo and mfhi can be immediately followed by instructions
471 which write to the HI and LO registers.
473 According to MIPS specifications, MIPS ISAs I, II, and III need
474 (at least) two instructions between the reads of HI/LO and
475 instructions which write them, and later ISAs do not. Contradicting
476 the MIPS specifications, some MIPS IV processor user manuals (e.g.
477 the UM for the NEC Vr5000) document needing the instructions between
478 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
479 MIPS64 and later ISAs to have the interlocks, plus any specific
480 earlier-ISA CPUs for which CPU documentation declares that the
481 instructions are really interlocked. */
482 #define hilo_interlocks \
483 (mips_opts.isa == ISA_MIPS32 \
484 || mips_opts.isa == ISA_MIPS32R2 \
485 || mips_opts.isa == ISA_MIPS64 \
486 || mips_opts.isa == ISA_MIPS64R2 \
487 || mips_opts.arch == CPU_R4010 \
488 || mips_opts.arch == CPU_R10000 \
489 || mips_opts.arch == CPU_R12000 \
490 || mips_opts.arch == CPU_R14000 \
491 || mips_opts.arch == CPU_R16000 \
492 || mips_opts.arch == CPU_RM7000 \
493 || mips_opts.arch == CPU_VR5500 \
496 /* Whether the processor uses hardware interlocks to protect reads
497 from the GPRs after they are loaded from memory, and thus does not
498 require nops to be inserted. This applies to instructions marked
499 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
501 #define gpr_interlocks \
502 (mips_opts.isa != ISA_MIPS1 \
503 || mips_opts.arch == CPU_R3900)
505 /* Whether the processor uses hardware interlocks to avoid delays
506 required by coprocessor instructions, and thus does not require
507 nops to be inserted. This applies to instructions marked
508 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
509 between instructions marked INSN_WRITE_COND_CODE and ones marked
510 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
511 levels I, II, and III. */
512 /* Itbl support may require additional care here. */
513 #define cop_interlocks \
514 ((mips_opts.isa != ISA_MIPS1 \
515 && mips_opts.isa != ISA_MIPS2 \
516 && mips_opts.isa != ISA_MIPS3) \
517 || mips_opts.arch == CPU_R4300 \
520 /* Whether the processor uses hardware interlocks to protect reads
521 from coprocessor registers after they are loaded from memory, and
522 thus does not require nops to be inserted. This applies to
523 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
524 requires at MIPS ISA level I. */
525 #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1)
527 /* Is this a mfhi or mflo instruction? */
528 #define MF_HILO_INSN(PINFO) \
529 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
531 /* Returns true for a (non floating-point) coprocessor instruction. Reading
532 or writing the condition code is only possible on the coprocessors and
533 these insns are not marked with INSN_COP. Thus for these insns use the
534 condition-code flags. */
535 #define COP_INSN(PINFO) \
536 (PINFO != INSN_MACRO \
537 && ((PINFO) & (FP_S | FP_D)) == 0 \
538 && ((PINFO) & (INSN_COP | INSN_READ_COND_CODE | INSN_WRITE_COND_CODE)))
540 /* MIPS PIC level. */
542 enum mips_pic_level mips_pic
;
544 /* 1 if we should generate 32 bit offsets from the $gp register in
545 SVR4_PIC mode. Currently has no meaning in other modes. */
546 static int mips_big_got
= 0;
548 /* 1 if trap instructions should used for overflow rather than break
550 static int mips_trap
= 0;
552 /* 1 if double width floating point constants should not be constructed
553 by assembling two single width halves into two single width floating
554 point registers which just happen to alias the double width destination
555 register. On some architectures this aliasing can be disabled by a bit
556 in the status register, and the setting of this bit cannot be determined
557 automatically at assemble time. */
558 static int mips_disable_float_construction
;
560 /* Non-zero if any .set noreorder directives were used. */
562 static int mips_any_noreorder
;
564 /* Non-zero if nops should be inserted when the register referenced in
565 an mfhi/mflo instruction is read in the next two instructions. */
566 static int mips_7000_hilo_fix
;
568 /* The size of objects in the small data section. */
569 static unsigned int g_switch_value
= 8;
570 /* Whether the -G option was used. */
571 static int g_switch_seen
= 0;
576 /* If we can determine in advance that GP optimization won't be
577 possible, we can skip the relaxation stuff that tries to produce
578 GP-relative references. This makes delay slot optimization work
581 This function can only provide a guess, but it seems to work for
582 gcc output. It needs to guess right for gcc, otherwise gcc
583 will put what it thinks is a GP-relative instruction in a branch
586 I don't know if a fix is needed for the SVR4_PIC mode. I've only
587 fixed it for the non-PIC mode. KR 95/04/07 */
588 static int nopic_need_relax (symbolS
*, int);
590 /* handle of the OPCODE hash table */
591 static struct hash_control
*op_hash
= NULL
;
593 /* The opcode hash table we use for the mips16. */
594 static struct hash_control
*mips16_op_hash
= NULL
;
596 /* This array holds the chars that always start a comment. If the
597 pre-processor is disabled, these aren't very useful */
598 const char comment_chars
[] = "#";
600 /* This array holds the chars that only start a comment at the beginning of
601 a line. If the line seems to have the form '# 123 filename'
602 .line and .file directives will appear in the pre-processed output */
603 /* Note that input_file.c hand checks for '#' at the beginning of the
604 first line of the input file. This is because the compiler outputs
605 #NO_APP at the beginning of its output. */
606 /* Also note that C style comments are always supported. */
607 const char line_comment_chars
[] = "#";
609 /* This array holds machine specific line separator characters. */
610 const char line_separator_chars
[] = ";";
612 /* Chars that can be used to separate mant from exp in floating point nums */
613 const char EXP_CHARS
[] = "eE";
615 /* Chars that mean this number is a floating point constant */
618 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
620 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
621 changed in read.c . Ideally it shouldn't have to know about it at all,
622 but nothing is ideal around here.
625 static char *insn_error
;
627 static int auto_align
= 1;
629 /* When outputting SVR4 PIC code, the assembler needs to know the
630 offset in the stack frame from which to restore the $gp register.
631 This is set by the .cprestore pseudo-op, and saved in this
633 static offsetT mips_cprestore_offset
= -1;
635 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
636 more optimizations, it can use a register value instead of a memory-saved
637 offset and even an other register than $gp as global pointer. */
638 static offsetT mips_cpreturn_offset
= -1;
639 static int mips_cpreturn_register
= -1;
640 static int mips_gp_register
= GP
;
641 static int mips_gprel_offset
= 0;
643 /* Whether mips_cprestore_offset has been set in the current function
644 (or whether it has already been warned about, if not). */
645 static int mips_cprestore_valid
= 0;
647 /* This is the register which holds the stack frame, as set by the
648 .frame pseudo-op. This is needed to implement .cprestore. */
649 static int mips_frame_reg
= SP
;
651 /* Whether mips_frame_reg has been set in the current function
652 (or whether it has already been warned about, if not). */
653 static int mips_frame_reg_valid
= 0;
655 /* To output NOP instructions correctly, we need to keep information
656 about the previous two instructions. */
658 /* Whether we are optimizing. The default value of 2 means to remove
659 unneeded NOPs and swap branch instructions when possible. A value
660 of 1 means to not swap branches. A value of 0 means to always
662 static int mips_optimize
= 2;
664 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
665 equivalent to seeing no -g option at all. */
666 static int mips_debug
= 0;
668 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
669 #define MAX_VR4130_NOPS 4
671 /* The maximum number of NOPs needed to fill delay slots. */
672 #define MAX_DELAY_NOPS 2
674 /* The maximum number of NOPs needed for any purpose. */
677 /* A list of previous instructions, with index 0 being the most recent.
678 We need to look back MAX_NOPS instructions when filling delay slots
679 or working around processor errata. We need to look back one
680 instruction further if we're thinking about using history[0] to
681 fill a branch delay slot. */
682 static struct mips_cl_insn history
[1 + MAX_NOPS
];
684 /* Nop instructions used by emit_nop. */
685 static struct mips_cl_insn nop_insn
, mips16_nop_insn
;
687 /* The appropriate nop for the current mode. */
688 #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn : &nop_insn)
690 /* If this is set, it points to a frag holding nop instructions which
691 were inserted before the start of a noreorder section. If those
692 nops turn out to be unnecessary, the size of the frag can be
694 static fragS
*prev_nop_frag
;
696 /* The number of nop instructions we created in prev_nop_frag. */
697 static int prev_nop_frag_holds
;
699 /* The number of nop instructions that we know we need in
701 static int prev_nop_frag_required
;
703 /* The number of instructions we've seen since prev_nop_frag. */
704 static int prev_nop_frag_since
;
706 /* For ECOFF and ELF, relocations against symbols are done in two
707 parts, with a HI relocation and a LO relocation. Each relocation
708 has only 16 bits of space to store an addend. This means that in
709 order for the linker to handle carries correctly, it must be able
710 to locate both the HI and the LO relocation. This means that the
711 relocations must appear in order in the relocation table.
713 In order to implement this, we keep track of each unmatched HI
714 relocation. We then sort them so that they immediately precede the
715 corresponding LO relocation. */
720 struct mips_hi_fixup
*next
;
723 /* The section this fixup is in. */
727 /* The list of unmatched HI relocs. */
729 static struct mips_hi_fixup
*mips_hi_fixup_list
;
731 /* The frag containing the last explicit relocation operator.
732 Null if explicit relocations have not been used. */
734 static fragS
*prev_reloc_op_frag
;
736 /* Map normal MIPS register numbers to mips16 register numbers. */
738 #define X ILLEGAL_REG
739 static const int mips32_to_16_reg_map
[] =
741 X
, X
, 2, 3, 4, 5, 6, 7,
742 X
, X
, X
, X
, X
, X
, X
, X
,
743 0, 1, X
, X
, X
, X
, X
, X
,
744 X
, X
, X
, X
, X
, X
, X
, X
748 /* Map mips16 register numbers to normal MIPS register numbers. */
750 static const unsigned int mips16_to_32_reg_map
[] =
752 16, 17, 2, 3, 4, 5, 6, 7
755 /* Classifies the kind of instructions we're interested in when
756 implementing -mfix-vr4120. */
757 enum fix_vr4120_class
765 NUM_FIX_VR4120_CLASSES
768 /* ...likewise -mfix-loongson2f-jump. */
769 static bfd_boolean mips_fix_loongson2f_jump
;
771 /* ...likewise -mfix-loongson2f-nop. */
772 static bfd_boolean mips_fix_loongson2f_nop
;
774 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
775 static bfd_boolean mips_fix_loongson2f
;
777 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
778 there must be at least one other instruction between an instruction
779 of type X and an instruction of type Y. */
780 static unsigned int vr4120_conflicts
[NUM_FIX_VR4120_CLASSES
];
782 /* True if -mfix-vr4120 is in force. */
783 static int mips_fix_vr4120
;
785 /* ...likewise -mfix-vr4130. */
786 static int mips_fix_vr4130
;
788 /* ...likewise -mfix-24k. */
789 static int mips_fix_24k
;
791 /* ...likewise -mfix-cn63xxp1 */
792 static bfd_boolean mips_fix_cn63xxp1
;
794 /* We don't relax branches by default, since this causes us to expand
795 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
796 fail to compute the offset before expanding the macro to the most
797 efficient expansion. */
799 static int mips_relax_branch
;
801 /* The expansion of many macros depends on the type of symbol that
802 they refer to. For example, when generating position-dependent code,
803 a macro that refers to a symbol may have two different expansions,
804 one which uses GP-relative addresses and one which uses absolute
805 addresses. When generating SVR4-style PIC, a macro may have
806 different expansions for local and global symbols.
808 We handle these situations by generating both sequences and putting
809 them in variant frags. In position-dependent code, the first sequence
810 will be the GP-relative one and the second sequence will be the
811 absolute one. In SVR4 PIC, the first sequence will be for global
812 symbols and the second will be for local symbols.
814 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
815 SECOND are the lengths of the two sequences in bytes. These fields
816 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
817 the subtype has the following flags:
820 Set if it has been decided that we should use the second
821 sequence instead of the first.
824 Set in the first variant frag if the macro's second implementation
825 is longer than its first. This refers to the macro as a whole,
826 not an individual relaxation.
829 Set in the first variant frag if the macro appeared in a .set nomacro
830 block and if one alternative requires a warning but the other does not.
833 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
836 The frag's "opcode" points to the first fixup for relaxable code.
838 Relaxable macros are generated using a sequence such as:
840 relax_start (SYMBOL);
841 ... generate first expansion ...
843 ... generate second expansion ...
846 The code and fixups for the unwanted alternative are discarded
847 by md_convert_frag. */
848 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
850 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
851 #define RELAX_SECOND(X) ((X) & 0xff)
852 #define RELAX_USE_SECOND 0x10000
853 #define RELAX_SECOND_LONGER 0x20000
854 #define RELAX_NOMACRO 0x40000
855 #define RELAX_DELAY_SLOT 0x80000
857 /* Branch without likely bit. If label is out of range, we turn:
859 beq reg1, reg2, label
869 with the following opcode replacements:
876 bltzal <-> bgezal (with jal label instead of j label)
878 Even though keeping the delay slot instruction in the delay slot of
879 the branch would be more efficient, it would be very tricky to do
880 correctly, because we'd have to introduce a variable frag *after*
881 the delay slot instruction, and expand that instead. Let's do it
882 the easy way for now, even if the branch-not-taken case now costs
883 one additional instruction. Out-of-range branches are not supposed
884 to be common, anyway.
886 Branch likely. If label is out of range, we turn:
888 beql reg1, reg2, label
889 delay slot (annulled if branch not taken)
898 delay slot (executed only if branch taken)
901 It would be possible to generate a shorter sequence by losing the
902 likely bit, generating something like:
907 delay slot (executed only if branch taken)
919 bltzall -> bgezal (with jal label instead of j label)
920 bgezall -> bltzal (ditto)
923 but it's not clear that it would actually improve performance. */
924 #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \
928 | ((toofar) ? 0x20 : 0) \
929 | ((link) ? 0x40 : 0) \
930 | ((likely) ? 0x80 : 0) \
931 | ((uncond) ? 0x100 : 0)))
932 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
933 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0)
934 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0)
935 #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0)
936 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0)
937 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
939 /* For mips16 code, we use an entirely different form of relaxation.
940 mips16 supports two versions of most instructions which take
941 immediate values: a small one which takes some small value, and a
942 larger one which takes a 16 bit value. Since branches also follow
943 this pattern, relaxing these values is required.
945 We can assemble both mips16 and normal MIPS code in a single
946 object. Therefore, we need to support this type of relaxation at
947 the same time that we support the relaxation described above. We
948 use the high bit of the subtype field to distinguish these cases.
950 The information we store for this type of relaxation is the
951 argument code found in the opcode file for this relocation, whether
952 the user explicitly requested a small or extended form, and whether
953 the relocation is in a jump or jal delay slot. That tells us the
954 size of the value, and how it should be stored. We also store
955 whether the fragment is considered to be extended or not. We also
956 store whether this is known to be a branch to a different section,
957 whether we have tried to relax this frag yet, and whether we have
958 ever extended a PC relative fragment because of a shift count. */
959 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
962 | ((small) ? 0x100 : 0) \
963 | ((ext) ? 0x200 : 0) \
964 | ((dslot) ? 0x400 : 0) \
965 | ((jal_dslot) ? 0x800 : 0))
966 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
967 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
968 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
969 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
970 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
971 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
972 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
973 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
974 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
975 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
976 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
977 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
979 /* Is the given value a sign-extended 32-bit value? */
980 #define IS_SEXT_32BIT_NUM(x) \
981 (((x) &~ (offsetT) 0x7fffffff) == 0 \
982 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
984 /* Is the given value a sign-extended 16-bit value? */
985 #define IS_SEXT_16BIT_NUM(x) \
986 (((x) &~ (offsetT) 0x7fff) == 0 \
987 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
989 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
990 #define IS_ZEXT_32BIT_NUM(x) \
991 (((x) &~ (offsetT) 0xffffffff) == 0 \
992 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
994 /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
995 VALUE << SHIFT. VALUE is evaluated exactly once. */
996 #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
997 (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \
998 | (((VALUE) & (MASK)) << (SHIFT)))
1000 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1002 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1003 (((STRUCT) >> (SHIFT)) & (MASK))
1005 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
1006 INSN is a mips_cl_insn structure and VALUE is evaluated exactly once.
1008 include/opcode/mips.h specifies operand fields using the macros
1009 OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start
1010 with "MIPS16OP" instead of "OP". */
1011 #define INSERT_OPERAND(FIELD, INSN, VALUE) \
1012 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
1013 #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \
1014 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1015 MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD)
1017 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1018 #define EXTRACT_OPERAND(FIELD, INSN) \
1019 EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD)
1020 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1021 EXTRACT_BITS ((INSN).insn_opcode, \
1022 MIPS16OP_MASK_##FIELD, \
1023 MIPS16OP_SH_##FIELD)
1025 /* Global variables used when generating relaxable macros. See the
1026 comment above RELAX_ENCODE for more details about how relaxation
1029 /* 0 if we're not emitting a relaxable macro.
1030 1 if we're emitting the first of the two relaxation alternatives.
1031 2 if we're emitting the second alternative. */
1034 /* The first relaxable fixup in the current frag. (In other words,
1035 the first fixup that refers to relaxable code.) */
1038 /* sizes[0] says how many bytes of the first alternative are stored in
1039 the current frag. Likewise sizes[1] for the second alternative. */
1040 unsigned int sizes
[2];
1042 /* The symbol on which the choice of sequence depends. */
1046 /* Global variables used to decide whether a macro needs a warning. */
1048 /* True if the macro is in a branch delay slot. */
1049 bfd_boolean delay_slot_p
;
1051 /* For relaxable macros, sizes[0] is the length of the first alternative
1052 in bytes and sizes[1] is the length of the second alternative.
1053 For non-relaxable macros, both elements give the length of the
1055 unsigned int sizes
[2];
1057 /* The first variant frag for this macro. */
1059 } mips_macro_warning
;
1061 /* Prototypes for static functions. */
1063 #define internalError() \
1064 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
1066 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
1068 static void append_insn
1069 (struct mips_cl_insn
*, expressionS
*, bfd_reloc_code_real_type
*);
1070 static void mips_no_prev_insn (void);
1071 static void macro_build (expressionS
*, const char *, const char *, ...);
1072 static void mips16_macro_build
1073 (expressionS
*, const char *, const char *, va_list *);
1074 static void load_register (int, expressionS
*, int);
1075 static void macro_start (void);
1076 static void macro_end (void);
1077 static void macro (struct mips_cl_insn
* ip
);
1078 static void mips16_macro (struct mips_cl_insn
* ip
);
1079 static void mips_ip (char *str
, struct mips_cl_insn
* ip
);
1080 static void mips16_ip (char *str
, struct mips_cl_insn
* ip
);
1081 static void mips16_immed
1082 (char *, unsigned int, int, offsetT
, bfd_boolean
, bfd_boolean
, bfd_boolean
,
1083 unsigned long *, bfd_boolean
*, unsigned short *);
1084 static size_t my_getSmallExpression
1085 (expressionS
*, bfd_reloc_code_real_type
*, char *);
1086 static void my_getExpression (expressionS
*, char *);
1087 static void s_align (int);
1088 static void s_change_sec (int);
1089 static void s_change_section (int);
1090 static void s_cons (int);
1091 static void s_float_cons (int);
1092 static void s_mips_globl (int);
1093 static void s_option (int);
1094 static void s_mipsset (int);
1095 static void s_abicalls (int);
1096 static void s_cpload (int);
1097 static void s_cpsetup (int);
1098 static void s_cplocal (int);
1099 static void s_cprestore (int);
1100 static void s_cpreturn (int);
1101 static void s_dtprelword (int);
1102 static void s_dtpreldword (int);
1103 static void s_gpvalue (int);
1104 static void s_gpword (int);
1105 static void s_gpdword (int);
1106 static void s_cpadd (int);
1107 static void s_insn (int);
1108 static void md_obj_begin (void);
1109 static void md_obj_end (void);
1110 static void s_mips_ent (int);
1111 static void s_mips_end (int);
1112 static void s_mips_frame (int);
1113 static void s_mips_mask (int reg_type
);
1114 static void s_mips_stab (int);
1115 static void s_mips_weakext (int);
1116 static void s_mips_file (int);
1117 static void s_mips_loc (int);
1118 static bfd_boolean
pic_need_relax (symbolS
*, asection
*);
1119 static int relaxed_branch_length (fragS
*, asection
*, int);
1120 static int validate_mips_insn (const struct mips_opcode
*);
1122 /* Table and functions used to map between CPU/ISA names, and
1123 ISA levels, and CPU numbers. */
1125 struct mips_cpu_info
1127 const char *name
; /* CPU or ISA name. */
1128 int flags
; /* ASEs available, or ISA flag. */
1129 int isa
; /* ISA level. */
1130 int cpu
; /* CPU number (default CPU if ISA). */
1133 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1134 #define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */
1135 #define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */
1136 #define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */
1137 #define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */
1138 #define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */
1139 #define MIPS_CPU_ASE_DSPR2 0x0040 /* CPU implements DSP R2 ASE */
1141 static const struct mips_cpu_info
*mips_parse_cpu (const char *, const char *);
1142 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
1143 static const struct mips_cpu_info
*mips_cpu_info_from_arch (int);
1147 The following pseudo-ops from the Kane and Heinrich MIPS book
1148 should be defined here, but are currently unsupported: .alias,
1149 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1151 The following pseudo-ops from the Kane and Heinrich MIPS book are
1152 specific to the type of debugging information being generated, and
1153 should be defined by the object format: .aent, .begin, .bend,
1154 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1157 The following pseudo-ops from the Kane and Heinrich MIPS book are
1158 not MIPS CPU specific, but are also not specific to the object file
1159 format. This file is probably the best place to define them, but
1160 they are not currently supported: .asm0, .endr, .lab, .struct. */
1162 static const pseudo_typeS mips_pseudo_table
[] =
1164 /* MIPS specific pseudo-ops. */
1165 {"option", s_option
, 0},
1166 {"set", s_mipsset
, 0},
1167 {"rdata", s_change_sec
, 'r'},
1168 {"sdata", s_change_sec
, 's'},
1169 {"livereg", s_ignore
, 0},
1170 {"abicalls", s_abicalls
, 0},
1171 {"cpload", s_cpload
, 0},
1172 {"cpsetup", s_cpsetup
, 0},
1173 {"cplocal", s_cplocal
, 0},
1174 {"cprestore", s_cprestore
, 0},
1175 {"cpreturn", s_cpreturn
, 0},
1176 {"dtprelword", s_dtprelword
, 0},
1177 {"dtpreldword", s_dtpreldword
, 0},
1178 {"gpvalue", s_gpvalue
, 0},
1179 {"gpword", s_gpword
, 0},
1180 {"gpdword", s_gpdword
, 0},
1181 {"cpadd", s_cpadd
, 0},
1182 {"insn", s_insn
, 0},
1184 /* Relatively generic pseudo-ops that happen to be used on MIPS
1186 {"asciiz", stringer
, 8 + 1},
1187 {"bss", s_change_sec
, 'b'},
1189 {"half", s_cons
, 1},
1190 {"dword", s_cons
, 3},
1191 {"weakext", s_mips_weakext
, 0},
1192 {"origin", s_org
, 0},
1193 {"repeat", s_rept
, 0},
1195 /* For MIPS this is non-standard, but we define it for consistency. */
1196 {"sbss", s_change_sec
, 'B'},
1198 /* These pseudo-ops are defined in read.c, but must be overridden
1199 here for one reason or another. */
1200 {"align", s_align
, 0},
1201 {"byte", s_cons
, 0},
1202 {"data", s_change_sec
, 'd'},
1203 {"double", s_float_cons
, 'd'},
1204 {"float", s_float_cons
, 'f'},
1205 {"globl", s_mips_globl
, 0},
1206 {"global", s_mips_globl
, 0},
1207 {"hword", s_cons
, 1},
1209 {"long", s_cons
, 2},
1210 {"octa", s_cons
, 4},
1211 {"quad", s_cons
, 3},
1212 {"section", s_change_section
, 0},
1213 {"short", s_cons
, 1},
1214 {"single", s_float_cons
, 'f'},
1215 {"stabn", s_mips_stab
, 'n'},
1216 {"text", s_change_sec
, 't'},
1217 {"word", s_cons
, 2},
1219 { "extern", ecoff_directive_extern
, 0},
1224 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1226 /* These pseudo-ops should be defined by the object file format.
1227 However, a.out doesn't support them, so we have versions here. */
1228 {"aent", s_mips_ent
, 1},
1229 {"bgnb", s_ignore
, 0},
1230 {"end", s_mips_end
, 0},
1231 {"endb", s_ignore
, 0},
1232 {"ent", s_mips_ent
, 0},
1233 {"file", s_mips_file
, 0},
1234 {"fmask", s_mips_mask
, 'F'},
1235 {"frame", s_mips_frame
, 0},
1236 {"loc", s_mips_loc
, 0},
1237 {"mask", s_mips_mask
, 'R'},
1238 {"verstamp", s_ignore
, 0},
1242 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1243 purpose of the `.dc.a' internal pseudo-op. */
1246 mips_address_bytes (void)
1248 return HAVE_64BIT_ADDRESSES
? 8 : 4;
1251 extern void pop_insert (const pseudo_typeS
*);
1254 mips_pop_insert (void)
1256 pop_insert (mips_pseudo_table
);
1257 if (! ECOFF_DEBUGGING
)
1258 pop_insert (mips_nonecoff_pseudo_table
);
1261 /* Symbols labelling the current insn. */
1263 struct insn_label_list
1265 struct insn_label_list
*next
;
1269 static struct insn_label_list
*free_insn_labels
;
1270 #define label_list tc_segment_info_data.labels
1272 static void mips_clear_insn_labels (void);
1275 mips_clear_insn_labels (void)
1277 register struct insn_label_list
**pl
;
1278 segment_info_type
*si
;
1282 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1285 si
= seg_info (now_seg
);
1286 *pl
= si
->label_list
;
1287 si
->label_list
= NULL
;
1292 static char *expr_end
;
1294 /* Expressions which appear in instructions. These are set by
1297 static expressionS imm_expr
;
1298 static expressionS imm2_expr
;
1299 static expressionS offset_expr
;
1301 /* Relocs associated with imm_expr and offset_expr. */
1303 static bfd_reloc_code_real_type imm_reloc
[3]
1304 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1305 static bfd_reloc_code_real_type offset_reloc
[3]
1306 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1308 /* These are set by mips16_ip if an explicit extension is used. */
1310 static bfd_boolean mips16_small
, mips16_ext
;
1313 /* The pdr segment for per procedure frame/regmask info. Not used for
1316 static segT pdr_seg
;
1319 /* The default target format to use. */
1321 #if defined (TE_FreeBSD)
1322 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
1323 #elif defined (TE_TMIPS)
1324 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
1326 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
1330 mips_target_format (void)
1332 switch (OUTPUT_FLAVOR
)
1334 case bfd_target_ecoff_flavour
:
1335 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
1336 case bfd_target_coff_flavour
:
1338 case bfd_target_elf_flavour
:
1340 if (!HAVE_64BIT_OBJECTS
&& !HAVE_NEWABI
)
1341 return (target_big_endian
1342 ? "elf32-bigmips-vxworks"
1343 : "elf32-littlemips-vxworks");
1345 return (target_big_endian
1346 ? (HAVE_64BIT_OBJECTS
1347 ? ELF_TARGET ("elf64-", "big")
1349 ? ELF_TARGET ("elf32-n", "big")
1350 : ELF_TARGET ("elf32-", "big")))
1351 : (HAVE_64BIT_OBJECTS
1352 ? ELF_TARGET ("elf64-", "little")
1354 ? ELF_TARGET ("elf32-n", "little")
1355 : ELF_TARGET ("elf32-", "little"))));
1362 /* Return the length of instruction INSN. */
1364 static inline unsigned int
1365 insn_length (const struct mips_cl_insn
*insn
)
1367 if (!mips_opts
.mips16
)
1369 return insn
->mips16_absolute_jump_p
|| insn
->use_extend
? 4 : 2;
1372 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
1375 create_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*mo
)
1380 insn
->use_extend
= FALSE
;
1382 insn
->insn_opcode
= mo
->match
;
1385 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
1386 insn
->fixp
[i
] = NULL
;
1387 insn
->fixed_p
= (mips_opts
.noreorder
> 0);
1388 insn
->noreorder_p
= (mips_opts
.noreorder
> 0);
1389 insn
->mips16_absolute_jump_p
= 0;
1390 insn
->complete_p
= 0;
1393 /* Record the current MIPS16 mode in now_seg. */
1396 mips_record_mips16_mode (void)
1398 segment_info_type
*si
;
1400 si
= seg_info (now_seg
);
1401 if (si
->tc_segment_info_data
.mips16
!= mips_opts
.mips16
)
1402 si
->tc_segment_info_data
.mips16
= mips_opts
.mips16
;
1405 /* Install INSN at the location specified by its "frag" and "where" fields. */
1408 install_insn (const struct mips_cl_insn
*insn
)
1410 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
1411 if (!mips_opts
.mips16
)
1412 md_number_to_chars (f
, insn
->insn_opcode
, 4);
1413 else if (insn
->mips16_absolute_jump_p
)
1415 md_number_to_chars (f
, insn
->insn_opcode
>> 16, 2);
1416 md_number_to_chars (f
+ 2, insn
->insn_opcode
& 0xffff, 2);
1420 if (insn
->use_extend
)
1422 md_number_to_chars (f
, 0xf000 | insn
->extend
, 2);
1425 md_number_to_chars (f
, insn
->insn_opcode
, 2);
1427 mips_record_mips16_mode ();
1430 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
1431 and install the opcode in the new location. */
1434 move_insn (struct mips_cl_insn
*insn
, fragS
*frag
, long where
)
1439 insn
->where
= where
;
1440 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
1441 if (insn
->fixp
[i
] != NULL
)
1443 insn
->fixp
[i
]->fx_frag
= frag
;
1444 insn
->fixp
[i
]->fx_where
= where
;
1446 install_insn (insn
);
1449 /* Add INSN to the end of the output. */
1452 add_fixed_insn (struct mips_cl_insn
*insn
)
1454 char *f
= frag_more (insn_length (insn
));
1455 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
1458 /* Start a variant frag and move INSN to the start of the variant part,
1459 marking it as fixed. The other arguments are as for frag_var. */
1462 add_relaxed_insn (struct mips_cl_insn
*insn
, int max_chars
, int var
,
1463 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
1465 frag_grow (max_chars
);
1466 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
1468 frag_var (rs_machine_dependent
, max_chars
, var
,
1469 subtype
, symbol
, offset
, NULL
);
1472 /* Insert N copies of INSN into the history buffer, starting at
1473 position FIRST. Neither FIRST nor N need to be clipped. */
1476 insert_into_history (unsigned int first
, unsigned int n
,
1477 const struct mips_cl_insn
*insn
)
1479 if (mips_relax
.sequence
!= 2)
1483 for (i
= ARRAY_SIZE (history
); i
-- > first
;)
1485 history
[i
] = history
[i
- n
];
1491 /* Emit a nop instruction, recording it in the history buffer. */
1496 add_fixed_insn (NOP_INSN
);
1497 insert_into_history (0, 1, NOP_INSN
);
1500 /* Initialize vr4120_conflicts. There is a bit of duplication here:
1501 the idea is to make it obvious at a glance that each errata is
1505 init_vr4120_conflicts (void)
1507 #define CONFLICT(FIRST, SECOND) \
1508 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
1510 /* Errata 21 - [D]DIV[U] after [D]MACC */
1511 CONFLICT (MACC
, DIV
);
1512 CONFLICT (DMACC
, DIV
);
1514 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
1515 CONFLICT (DMULT
, DMULT
);
1516 CONFLICT (DMULT
, DMACC
);
1517 CONFLICT (DMACC
, DMULT
);
1518 CONFLICT (DMACC
, DMACC
);
1520 /* Errata 24 - MT{LO,HI} after [D]MACC */
1521 CONFLICT (MACC
, MTHILO
);
1522 CONFLICT (DMACC
, MTHILO
);
1524 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
1525 instruction is executed immediately after a MACC or DMACC
1526 instruction, the result of [either instruction] is incorrect." */
1527 CONFLICT (MACC
, MULT
);
1528 CONFLICT (MACC
, DMULT
);
1529 CONFLICT (DMACC
, MULT
);
1530 CONFLICT (DMACC
, DMULT
);
1532 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
1533 executed immediately after a DMULT, DMULTU, DIV, DIVU,
1534 DDIV or DDIVU instruction, the result of the MACC or
1535 DMACC instruction is incorrect.". */
1536 CONFLICT (DMULT
, MACC
);
1537 CONFLICT (DMULT
, DMACC
);
1538 CONFLICT (DIV
, MACC
);
1539 CONFLICT (DIV
, DMACC
);
1549 #define RTYPE_MASK 0x1ff00
1550 #define RTYPE_NUM 0x00100
1551 #define RTYPE_FPU 0x00200
1552 #define RTYPE_FCC 0x00400
1553 #define RTYPE_VEC 0x00800
1554 #define RTYPE_GP 0x01000
1555 #define RTYPE_CP0 0x02000
1556 #define RTYPE_PC 0x04000
1557 #define RTYPE_ACC 0x08000
1558 #define RTYPE_CCC 0x10000
1559 #define RNUM_MASK 0x000ff
1560 #define RWARN 0x80000
1562 #define GENERIC_REGISTER_NUMBERS \
1563 {"$0", RTYPE_NUM | 0}, \
1564 {"$1", RTYPE_NUM | 1}, \
1565 {"$2", RTYPE_NUM | 2}, \
1566 {"$3", RTYPE_NUM | 3}, \
1567 {"$4", RTYPE_NUM | 4}, \
1568 {"$5", RTYPE_NUM | 5}, \
1569 {"$6", RTYPE_NUM | 6}, \
1570 {"$7", RTYPE_NUM | 7}, \
1571 {"$8", RTYPE_NUM | 8}, \
1572 {"$9", RTYPE_NUM | 9}, \
1573 {"$10", RTYPE_NUM | 10}, \
1574 {"$11", RTYPE_NUM | 11}, \
1575 {"$12", RTYPE_NUM | 12}, \
1576 {"$13", RTYPE_NUM | 13}, \
1577 {"$14", RTYPE_NUM | 14}, \
1578 {"$15", RTYPE_NUM | 15}, \
1579 {"$16", RTYPE_NUM | 16}, \
1580 {"$17", RTYPE_NUM | 17}, \
1581 {"$18", RTYPE_NUM | 18}, \
1582 {"$19", RTYPE_NUM | 19}, \
1583 {"$20", RTYPE_NUM | 20}, \
1584 {"$21", RTYPE_NUM | 21}, \
1585 {"$22", RTYPE_NUM | 22}, \
1586 {"$23", RTYPE_NUM | 23}, \
1587 {"$24", RTYPE_NUM | 24}, \
1588 {"$25", RTYPE_NUM | 25}, \
1589 {"$26", RTYPE_NUM | 26}, \
1590 {"$27", RTYPE_NUM | 27}, \
1591 {"$28", RTYPE_NUM | 28}, \
1592 {"$29", RTYPE_NUM | 29}, \
1593 {"$30", RTYPE_NUM | 30}, \
1594 {"$31", RTYPE_NUM | 31}
1596 #define FPU_REGISTER_NAMES \
1597 {"$f0", RTYPE_FPU | 0}, \
1598 {"$f1", RTYPE_FPU | 1}, \
1599 {"$f2", RTYPE_FPU | 2}, \
1600 {"$f3", RTYPE_FPU | 3}, \
1601 {"$f4", RTYPE_FPU | 4}, \
1602 {"$f5", RTYPE_FPU | 5}, \
1603 {"$f6", RTYPE_FPU | 6}, \
1604 {"$f7", RTYPE_FPU | 7}, \
1605 {"$f8", RTYPE_FPU | 8}, \
1606 {"$f9", RTYPE_FPU | 9}, \
1607 {"$f10", RTYPE_FPU | 10}, \
1608 {"$f11", RTYPE_FPU | 11}, \
1609 {"$f12", RTYPE_FPU | 12}, \
1610 {"$f13", RTYPE_FPU | 13}, \
1611 {"$f14", RTYPE_FPU | 14}, \
1612 {"$f15", RTYPE_FPU | 15}, \
1613 {"$f16", RTYPE_FPU | 16}, \
1614 {"$f17", RTYPE_FPU | 17}, \
1615 {"$f18", RTYPE_FPU | 18}, \
1616 {"$f19", RTYPE_FPU | 19}, \
1617 {"$f20", RTYPE_FPU | 20}, \
1618 {"$f21", RTYPE_FPU | 21}, \
1619 {"$f22", RTYPE_FPU | 22}, \
1620 {"$f23", RTYPE_FPU | 23}, \
1621 {"$f24", RTYPE_FPU | 24}, \
1622 {"$f25", RTYPE_FPU | 25}, \
1623 {"$f26", RTYPE_FPU | 26}, \
1624 {"$f27", RTYPE_FPU | 27}, \
1625 {"$f28", RTYPE_FPU | 28}, \
1626 {"$f29", RTYPE_FPU | 29}, \
1627 {"$f30", RTYPE_FPU | 30}, \
1628 {"$f31", RTYPE_FPU | 31}
1630 #define FPU_CONDITION_CODE_NAMES \
1631 {"$fcc0", RTYPE_FCC | 0}, \
1632 {"$fcc1", RTYPE_FCC | 1}, \
1633 {"$fcc2", RTYPE_FCC | 2}, \
1634 {"$fcc3", RTYPE_FCC | 3}, \
1635 {"$fcc4", RTYPE_FCC | 4}, \
1636 {"$fcc5", RTYPE_FCC | 5}, \
1637 {"$fcc6", RTYPE_FCC | 6}, \
1638 {"$fcc7", RTYPE_FCC | 7}
1640 #define COPROC_CONDITION_CODE_NAMES \
1641 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
1642 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
1643 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
1644 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
1645 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
1646 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
1647 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
1648 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
1650 #define N32N64_SYMBOLIC_REGISTER_NAMES \
1651 {"$a4", RTYPE_GP | 8}, \
1652 {"$a5", RTYPE_GP | 9}, \
1653 {"$a6", RTYPE_GP | 10}, \
1654 {"$a7", RTYPE_GP | 11}, \
1655 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
1656 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
1657 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
1658 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
1659 {"$t0", RTYPE_GP | 12}, \
1660 {"$t1", RTYPE_GP | 13}, \
1661 {"$t2", RTYPE_GP | 14}, \
1662 {"$t3", RTYPE_GP | 15}
1664 #define O32_SYMBOLIC_REGISTER_NAMES \
1665 {"$t0", RTYPE_GP | 8}, \
1666 {"$t1", RTYPE_GP | 9}, \
1667 {"$t2", RTYPE_GP | 10}, \
1668 {"$t3", RTYPE_GP | 11}, \
1669 {"$t4", RTYPE_GP | 12}, \
1670 {"$t5", RTYPE_GP | 13}, \
1671 {"$t6", RTYPE_GP | 14}, \
1672 {"$t7", RTYPE_GP | 15}, \
1673 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
1674 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
1675 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
1676 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
1678 /* Remaining symbolic register names */
1679 #define SYMBOLIC_REGISTER_NAMES \
1680 {"$zero", RTYPE_GP | 0}, \
1681 {"$at", RTYPE_GP | 1}, \
1682 {"$AT", RTYPE_GP | 1}, \
1683 {"$v0", RTYPE_GP | 2}, \
1684 {"$v1", RTYPE_GP | 3}, \
1685 {"$a0", RTYPE_GP | 4}, \
1686 {"$a1", RTYPE_GP | 5}, \
1687 {"$a2", RTYPE_GP | 6}, \
1688 {"$a3", RTYPE_GP | 7}, \
1689 {"$s0", RTYPE_GP | 16}, \
1690 {"$s1", RTYPE_GP | 17}, \
1691 {"$s2", RTYPE_GP | 18}, \
1692 {"$s3", RTYPE_GP | 19}, \
1693 {"$s4", RTYPE_GP | 20}, \
1694 {"$s5", RTYPE_GP | 21}, \
1695 {"$s6", RTYPE_GP | 22}, \
1696 {"$s7", RTYPE_GP | 23}, \
1697 {"$t8", RTYPE_GP | 24}, \
1698 {"$t9", RTYPE_GP | 25}, \
1699 {"$k0", RTYPE_GP | 26}, \
1700 {"$kt0", RTYPE_GP | 26}, \
1701 {"$k1", RTYPE_GP | 27}, \
1702 {"$kt1", RTYPE_GP | 27}, \
1703 {"$gp", RTYPE_GP | 28}, \
1704 {"$sp", RTYPE_GP | 29}, \
1705 {"$s8", RTYPE_GP | 30}, \
1706 {"$fp", RTYPE_GP | 30}, \
1707 {"$ra", RTYPE_GP | 31}
1709 #define MIPS16_SPECIAL_REGISTER_NAMES \
1710 {"$pc", RTYPE_PC | 0}
1712 #define MDMX_VECTOR_REGISTER_NAMES \
1713 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
1714 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
1715 {"$v2", RTYPE_VEC | 2}, \
1716 {"$v3", RTYPE_VEC | 3}, \
1717 {"$v4", RTYPE_VEC | 4}, \
1718 {"$v5", RTYPE_VEC | 5}, \
1719 {"$v6", RTYPE_VEC | 6}, \
1720 {"$v7", RTYPE_VEC | 7}, \
1721 {"$v8", RTYPE_VEC | 8}, \
1722 {"$v9", RTYPE_VEC | 9}, \
1723 {"$v10", RTYPE_VEC | 10}, \
1724 {"$v11", RTYPE_VEC | 11}, \
1725 {"$v12", RTYPE_VEC | 12}, \
1726 {"$v13", RTYPE_VEC | 13}, \
1727 {"$v14", RTYPE_VEC | 14}, \
1728 {"$v15", RTYPE_VEC | 15}, \
1729 {"$v16", RTYPE_VEC | 16}, \
1730 {"$v17", RTYPE_VEC | 17}, \
1731 {"$v18", RTYPE_VEC | 18}, \
1732 {"$v19", RTYPE_VEC | 19}, \
1733 {"$v20", RTYPE_VEC | 20}, \
1734 {"$v21", RTYPE_VEC | 21}, \
1735 {"$v22", RTYPE_VEC | 22}, \
1736 {"$v23", RTYPE_VEC | 23}, \
1737 {"$v24", RTYPE_VEC | 24}, \
1738 {"$v25", RTYPE_VEC | 25}, \
1739 {"$v26", RTYPE_VEC | 26}, \
1740 {"$v27", RTYPE_VEC | 27}, \
1741 {"$v28", RTYPE_VEC | 28}, \
1742 {"$v29", RTYPE_VEC | 29}, \
1743 {"$v30", RTYPE_VEC | 30}, \
1744 {"$v31", RTYPE_VEC | 31}
1746 #define MIPS_DSP_ACCUMULATOR_NAMES \
1747 {"$ac0", RTYPE_ACC | 0}, \
1748 {"$ac1", RTYPE_ACC | 1}, \
1749 {"$ac2", RTYPE_ACC | 2}, \
1750 {"$ac3", RTYPE_ACC | 3}
1752 static const struct regname reg_names
[] = {
1753 GENERIC_REGISTER_NUMBERS
,
1755 FPU_CONDITION_CODE_NAMES
,
1756 COPROC_CONDITION_CODE_NAMES
,
1758 /* The $txx registers depends on the abi,
1759 these will be added later into the symbol table from
1760 one of the tables below once mips_abi is set after
1761 parsing of arguments from the command line. */
1762 SYMBOLIC_REGISTER_NAMES
,
1764 MIPS16_SPECIAL_REGISTER_NAMES
,
1765 MDMX_VECTOR_REGISTER_NAMES
,
1766 MIPS_DSP_ACCUMULATOR_NAMES
,
1770 static const struct regname reg_names_o32
[] = {
1771 O32_SYMBOLIC_REGISTER_NAMES
,
1775 static const struct regname reg_names_n32n64
[] = {
1776 N32N64_SYMBOLIC_REGISTER_NAMES
,
1781 reg_lookup (char **s
, unsigned int types
, unsigned int *regnop
)
1788 /* Find end of name. */
1790 if (is_name_beginner (*e
))
1792 while (is_part_of_name (*e
))
1795 /* Terminate name. */
1799 /* Look for a register symbol. */
1800 if ((symbolP
= symbol_find (*s
)) && S_GET_SEGMENT (symbolP
) == reg_section
)
1802 int r
= S_GET_VALUE (symbolP
);
1804 reg
= r
& RNUM_MASK
;
1805 else if ((types
& RTYPE_VEC
) && (r
& ~1) == (RTYPE_GP
| 2))
1806 /* Convert GP reg $v0/1 to MDMX reg $v0/1! */
1807 reg
= (r
& RNUM_MASK
) - 2;
1809 /* Else see if this is a register defined in an itbl entry. */
1810 else if ((types
& RTYPE_GP
) && itbl_have_entries
)
1817 if (itbl_get_reg_val (n
, &r
))
1818 reg
= r
& RNUM_MASK
;
1821 /* Advance to next token if a register was recognised. */
1824 else if (types
& RWARN
)
1825 as_warn (_("Unrecognized register name `%s'"), *s
);
1833 /* Return TRUE if opcode MO is valid on the currently selected ISA and
1834 architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
1837 is_opcode_valid (const struct mips_opcode
*mo
)
1839 int isa
= mips_opts
.isa
;
1842 if (mips_opts
.ase_mdmx
)
1844 if (mips_opts
.ase_dsp
)
1846 if (mips_opts
.ase_dsp
&& ISA_SUPPORTS_DSP64_ASE
)
1848 if (mips_opts
.ase_dspr2
)
1850 if (mips_opts
.ase_mt
)
1852 if (mips_opts
.ase_mips3d
)
1854 if (mips_opts
.ase_smartmips
)
1855 isa
|= INSN_SMARTMIPS
;
1857 /* Don't accept instructions based on the ISA if the CPU does not implement
1858 all the coprocessor insns. */
1859 if (NO_ISA_COP (mips_opts
.arch
)
1860 && COP_INSN (mo
->pinfo
))
1863 if (!OPCODE_IS_MEMBER (mo
, isa
, mips_opts
.arch
))
1866 /* Check whether the instruction or macro requires single-precision or
1867 double-precision floating-point support. Note that this information is
1868 stored differently in the opcode table for insns and macros. */
1869 if (mo
->pinfo
== INSN_MACRO
)
1871 fp_s
= mo
->pinfo2
& INSN2_M_FP_S
;
1872 fp_d
= mo
->pinfo2
& INSN2_M_FP_D
;
1876 fp_s
= mo
->pinfo
& FP_S
;
1877 fp_d
= mo
->pinfo
& FP_D
;
1880 if (fp_d
&& (mips_opts
.soft_float
|| mips_opts
.single_float
))
1883 if (fp_s
&& mips_opts
.soft_float
)
1889 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
1890 selected ISA and architecture. */
1893 is_opcode_valid_16 (const struct mips_opcode
*mo
)
1895 return OPCODE_IS_MEMBER (mo
, mips_opts
.isa
, mips_opts
.arch
) ? TRUE
: FALSE
;
1898 /* This function is called once, at assembler startup time. It should set up
1899 all the tables, etc. that the MD part of the assembler will need. */
1904 const char *retval
= NULL
;
1908 if (mips_pic
!= NO_PIC
)
1910 if (g_switch_seen
&& g_switch_value
!= 0)
1911 as_bad (_("-G may not be used in position-independent code"));
1915 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_arch
))
1916 as_warn (_("Could not set architecture and machine"));
1918 op_hash
= hash_new ();
1920 for (i
= 0; i
< NUMOPCODES
;)
1922 const char *name
= mips_opcodes
[i
].name
;
1924 retval
= hash_insert (op_hash
, name
, (void *) &mips_opcodes
[i
]);
1927 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
1928 mips_opcodes
[i
].name
, retval
);
1929 /* Probably a memory allocation problem? Give up now. */
1930 as_fatal (_("Broken assembler. No assembly attempted."));
1934 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
1936 if (!validate_mips_insn (&mips_opcodes
[i
]))
1938 if (nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
1940 create_insn (&nop_insn
, mips_opcodes
+ i
);
1941 if (mips_fix_loongson2f_nop
)
1942 nop_insn
.insn_opcode
= LOONGSON2F_NOP_INSN
;
1943 nop_insn
.fixed_p
= 1;
1948 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
1951 mips16_op_hash
= hash_new ();
1954 while (i
< bfd_mips16_num_opcodes
)
1956 const char *name
= mips16_opcodes
[i
].name
;
1958 retval
= hash_insert (mips16_op_hash
, name
, (void *) &mips16_opcodes
[i
]);
1960 as_fatal (_("internal: can't hash `%s': %s"),
1961 mips16_opcodes
[i
].name
, retval
);
1964 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
1965 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
1966 != mips16_opcodes
[i
].match
))
1968 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
1969 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
1972 if (mips16_nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
1974 create_insn (&mips16_nop_insn
, mips16_opcodes
+ i
);
1975 mips16_nop_insn
.fixed_p
= 1;
1979 while (i
< bfd_mips16_num_opcodes
1980 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
1984 as_fatal (_("Broken assembler. No assembly attempted."));
1986 /* We add all the general register names to the symbol table. This
1987 helps us detect invalid uses of them. */
1988 for (i
= 0; reg_names
[i
].name
; i
++)
1989 symbol_table_insert (symbol_new (reg_names
[i
].name
, reg_section
,
1990 reg_names
[i
].num
, /* & RNUM_MASK, */
1991 &zero_address_frag
));
1993 for (i
= 0; reg_names_n32n64
[i
].name
; i
++)
1994 symbol_table_insert (symbol_new (reg_names_n32n64
[i
].name
, reg_section
,
1995 reg_names_n32n64
[i
].num
, /* & RNUM_MASK, */
1996 &zero_address_frag
));
1998 for (i
= 0; reg_names_o32
[i
].name
; i
++)
1999 symbol_table_insert (symbol_new (reg_names_o32
[i
].name
, reg_section
,
2000 reg_names_o32
[i
].num
, /* & RNUM_MASK, */
2001 &zero_address_frag
));
2003 mips_no_prev_insn ();
2006 mips_cprmask
[0] = 0;
2007 mips_cprmask
[1] = 0;
2008 mips_cprmask
[2] = 0;
2009 mips_cprmask
[3] = 0;
2011 /* set the default alignment for the text section (2**2) */
2012 record_alignment (text_section
, 2);
2014 bfd_set_gp_size (stdoutput
, g_switch_value
);
2019 /* On a native system other than VxWorks, sections must be aligned
2020 to 16 byte boundaries. When configured for an embedded ELF
2021 target, we don't bother. */
2022 if (strncmp (TARGET_OS
, "elf", 3) != 0
2023 && strncmp (TARGET_OS
, "vxworks", 7) != 0)
2025 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
2026 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
2027 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
2030 /* Create a .reginfo section for register masks and a .mdebug
2031 section for debugging information. */
2039 subseg
= now_subseg
;
2041 /* The ABI says this section should be loaded so that the
2042 running program can access it. However, we don't load it
2043 if we are configured for an embedded target */
2044 flags
= SEC_READONLY
| SEC_DATA
;
2045 if (strncmp (TARGET_OS
, "elf", 3) != 0)
2046 flags
|= SEC_ALLOC
| SEC_LOAD
;
2048 if (mips_abi
!= N64_ABI
)
2050 sec
= subseg_new (".reginfo", (subsegT
) 0);
2052 bfd_set_section_flags (stdoutput
, sec
, flags
);
2053 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
2055 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
2059 /* The 64-bit ABI uses a .MIPS.options section rather than
2060 .reginfo section. */
2061 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
2062 bfd_set_section_flags (stdoutput
, sec
, flags
);
2063 bfd_set_section_alignment (stdoutput
, sec
, 3);
2065 /* Set up the option header. */
2067 Elf_Internal_Options opthdr
;
2070 opthdr
.kind
= ODK_REGINFO
;
2071 opthdr
.size
= (sizeof (Elf_External_Options
)
2072 + sizeof (Elf64_External_RegInfo
));
2075 f
= frag_more (sizeof (Elf_External_Options
));
2076 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
2077 (Elf_External_Options
*) f
);
2079 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
2083 if (ECOFF_DEBUGGING
)
2085 sec
= subseg_new (".mdebug", (subsegT
) 0);
2086 (void) bfd_set_section_flags (stdoutput
, sec
,
2087 SEC_HAS_CONTENTS
| SEC_READONLY
);
2088 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
2090 else if (mips_flag_pdr
)
2092 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
2093 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
2094 SEC_READONLY
| SEC_RELOC
2096 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
2099 subseg_set (seg
, subseg
);
2102 #endif /* OBJ_ELF */
2104 if (! ECOFF_DEBUGGING
)
2107 if (mips_fix_vr4120
)
2108 init_vr4120_conflicts ();
2114 mips_emit_delays ();
2115 if (! ECOFF_DEBUGGING
)
2120 md_assemble (char *str
)
2122 struct mips_cl_insn insn
;
2123 bfd_reloc_code_real_type unused_reloc
[3]
2124 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
2126 imm_expr
.X_op
= O_absent
;
2127 imm2_expr
.X_op
= O_absent
;
2128 offset_expr
.X_op
= O_absent
;
2129 imm_reloc
[0] = BFD_RELOC_UNUSED
;
2130 imm_reloc
[1] = BFD_RELOC_UNUSED
;
2131 imm_reloc
[2] = BFD_RELOC_UNUSED
;
2132 offset_reloc
[0] = BFD_RELOC_UNUSED
;
2133 offset_reloc
[1] = BFD_RELOC_UNUSED
;
2134 offset_reloc
[2] = BFD_RELOC_UNUSED
;
2136 if (mips_opts
.mips16
)
2137 mips16_ip (str
, &insn
);
2140 mips_ip (str
, &insn
);
2141 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
2142 str
, insn
.insn_opcode
));
2147 as_bad ("%s `%s'", insn_error
, str
);
2151 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
2154 if (mips_opts
.mips16
)
2155 mips16_macro (&insn
);
2162 if (imm_expr
.X_op
!= O_absent
)
2163 append_insn (&insn
, &imm_expr
, imm_reloc
);
2164 else if (offset_expr
.X_op
!= O_absent
)
2165 append_insn (&insn
, &offset_expr
, offset_reloc
);
2167 append_insn (&insn
, NULL
, unused_reloc
);
2171 /* Convenience functions for abstracting away the differences between
2172 MIPS16 and non-MIPS16 relocations. */
2174 static inline bfd_boolean
2175 mips16_reloc_p (bfd_reloc_code_real_type reloc
)
2179 case BFD_RELOC_MIPS16_JMP
:
2180 case BFD_RELOC_MIPS16_GPREL
:
2181 case BFD_RELOC_MIPS16_GOT16
:
2182 case BFD_RELOC_MIPS16_CALL16
:
2183 case BFD_RELOC_MIPS16_HI16_S
:
2184 case BFD_RELOC_MIPS16_HI16
:
2185 case BFD_RELOC_MIPS16_LO16
:
2193 static inline bfd_boolean
2194 got16_reloc_p (bfd_reloc_code_real_type reloc
)
2196 return reloc
== BFD_RELOC_MIPS_GOT16
|| reloc
== BFD_RELOC_MIPS16_GOT16
;
2199 static inline bfd_boolean
2200 hi16_reloc_p (bfd_reloc_code_real_type reloc
)
2202 return reloc
== BFD_RELOC_HI16_S
|| reloc
== BFD_RELOC_MIPS16_HI16_S
;
2205 static inline bfd_boolean
2206 lo16_reloc_p (bfd_reloc_code_real_type reloc
)
2208 return reloc
== BFD_RELOC_LO16
|| reloc
== BFD_RELOC_MIPS16_LO16
;
2211 /* Return true if the given relocation might need a matching %lo().
2212 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
2213 need a matching %lo() when applied to local symbols. */
2215 static inline bfd_boolean
2216 reloc_needs_lo_p (bfd_reloc_code_real_type reloc
)
2218 return (HAVE_IN_PLACE_ADDENDS
2219 && (hi16_reloc_p (reloc
)
2220 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
2221 all GOT16 relocations evaluate to "G". */
2222 || (got16_reloc_p (reloc
) && mips_pic
!= VXWORKS_PIC
)));
2225 /* Return the type of %lo() reloc needed by RELOC, given that
2226 reloc_needs_lo_p. */
2228 static inline bfd_reloc_code_real_type
2229 matching_lo_reloc (bfd_reloc_code_real_type reloc
)
2231 return mips16_reloc_p (reloc
) ? BFD_RELOC_MIPS16_LO16
: BFD_RELOC_LO16
;
2234 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
2237 static inline bfd_boolean
2238 fixup_has_matching_lo_p (fixS
*fixp
)
2240 return (fixp
->fx_next
!= NULL
2241 && fixp
->fx_next
->fx_r_type
== matching_lo_reloc (fixp
->fx_r_type
)
2242 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
2243 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
2246 /* This function returns true if modifying a register requires a
2250 reg_needs_delay (unsigned int reg
)
2252 unsigned long prev_pinfo
;
2254 prev_pinfo
= history
[0].insn_mo
->pinfo
;
2255 if (! mips_opts
.noreorder
2256 && (((prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)
2257 && ! gpr_interlocks
)
2258 || ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
2259 && ! cop_interlocks
)))
2261 /* A load from a coprocessor or from memory. All load delays
2262 delay the use of general register rt for one instruction. */
2263 /* Itbl support may require additional care here. */
2264 know (prev_pinfo
& INSN_WRITE_GPR_T
);
2265 if (reg
== EXTRACT_OPERAND (RT
, history
[0]))
2272 /* Move all labels in insn_labels to the current insertion point. */
2275 mips_move_labels (void)
2277 segment_info_type
*si
= seg_info (now_seg
);
2278 struct insn_label_list
*l
;
2281 for (l
= si
->label_list
; l
!= NULL
; l
= l
->next
)
2283 gas_assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2284 symbol_set_frag (l
->label
, frag_now
);
2285 val
= (valueT
) frag_now_fix ();
2286 /* mips16 text labels are stored as odd. */
2287 if (mips_opts
.mips16
)
2289 S_SET_VALUE (l
->label
, val
);
2294 s_is_linkonce (symbolS
*sym
, segT from_seg
)
2296 bfd_boolean linkonce
= FALSE
;
2297 segT symseg
= S_GET_SEGMENT (sym
);
2299 if (symseg
!= from_seg
&& !S_IS_LOCAL (sym
))
2301 if ((bfd_get_section_flags (stdoutput
, symseg
) & SEC_LINK_ONCE
))
2304 /* The GNU toolchain uses an extension for ELF: a section
2305 beginning with the magic string .gnu.linkonce is a
2306 linkonce section. */
2307 if (strncmp (segment_name (symseg
), ".gnu.linkonce",
2308 sizeof ".gnu.linkonce" - 1) == 0)
2315 /* Mark instruction labels in mips16 mode. This permits the linker to
2316 handle them specially, such as generating jalx instructions when
2317 needed. We also make them odd for the duration of the assembly, in
2318 order to generate the right sort of code. We will make them even
2319 in the adjust_symtab routine, while leaving them marked. This is
2320 convenient for the debugger and the disassembler. The linker knows
2321 to make them odd again. */
2324 mips16_mark_labels (void)
2326 segment_info_type
*si
= seg_info (now_seg
);
2327 struct insn_label_list
*l
;
2329 if (!mips_opts
.mips16
)
2332 for (l
= si
->label_list
; l
!= NULL
; l
= l
->next
)
2334 symbolS
*label
= l
->label
;
2336 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
2338 S_SET_OTHER (label
, ELF_ST_SET_MIPS16 (S_GET_OTHER (label
)));
2340 if ((S_GET_VALUE (label
) & 1) == 0
2341 /* Don't adjust the address if the label is global or weak, or
2342 in a link-once section, since we'll be emitting symbol reloc
2343 references to it which will be patched up by the linker, and
2344 the final value of the symbol may or may not be MIPS16. */
2345 && ! S_IS_WEAK (label
)
2346 && ! S_IS_EXTERNAL (label
)
2347 && ! s_is_linkonce (label
, now_seg
))
2348 S_SET_VALUE (label
, S_GET_VALUE (label
) | 1);
2352 /* End the current frag. Make it a variant frag and record the
2356 relax_close_frag (void)
2358 mips_macro_warning
.first_frag
= frag_now
;
2359 frag_var (rs_machine_dependent
, 0, 0,
2360 RELAX_ENCODE (mips_relax
.sizes
[0], mips_relax
.sizes
[1]),
2361 mips_relax
.symbol
, 0, (char *) mips_relax
.first_fixup
);
2363 memset (&mips_relax
.sizes
, 0, sizeof (mips_relax
.sizes
));
2364 mips_relax
.first_fixup
= 0;
2367 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
2368 See the comment above RELAX_ENCODE for more details. */
2371 relax_start (symbolS
*symbol
)
2373 gas_assert (mips_relax
.sequence
== 0);
2374 mips_relax
.sequence
= 1;
2375 mips_relax
.symbol
= symbol
;
2378 /* Start generating the second version of a relaxable sequence.
2379 See the comment above RELAX_ENCODE for more details. */
2384 gas_assert (mips_relax
.sequence
== 1);
2385 mips_relax
.sequence
= 2;
2388 /* End the current relaxable sequence. */
2393 gas_assert (mips_relax
.sequence
== 2);
2394 relax_close_frag ();
2395 mips_relax
.sequence
= 0;
2398 /* Return the mask of core registers that IP reads. */
2401 gpr_read_mask (const struct mips_cl_insn
*ip
)
2403 unsigned long pinfo
, pinfo2
;
2407 pinfo
= ip
->insn_mo
->pinfo
;
2408 pinfo2
= ip
->insn_mo
->pinfo2
;
2409 if (mips_opts
.mips16
)
2411 if (pinfo
& MIPS16_INSN_READ_X
)
2412 mask
|= 1 << mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RX
, *ip
)];
2413 if (pinfo
& MIPS16_INSN_READ_Y
)
2414 mask
|= 1 << mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RY
, *ip
)];
2415 if (pinfo
& MIPS16_INSN_READ_T
)
2417 if (pinfo
& MIPS16_INSN_READ_SP
)
2419 if (pinfo
& MIPS16_INSN_READ_31
)
2421 if (pinfo
& MIPS16_INSN_READ_Z
)
2422 mask
|= 1 << (mips16_to_32_reg_map
2423 [MIPS16_EXTRACT_OPERAND (MOVE32Z
, *ip
)]);
2424 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
2425 mask
|= 1 << MIPS16_EXTRACT_OPERAND (REGR32
, *ip
);
2429 if (pinfo2
& INSN2_READ_GPR_D
)
2430 mask
|= 1 << EXTRACT_OPERAND (RD
, *ip
);
2431 if (pinfo
& INSN_READ_GPR_T
)
2432 mask
|= 1 << EXTRACT_OPERAND (RT
, *ip
);
2433 if (pinfo
& INSN_READ_GPR_S
)
2434 mask
|= 1 << EXTRACT_OPERAND (RS
, *ip
);
2435 if (pinfo2
& INSN2_READ_GPR_Z
)
2436 mask
|= 1 << EXTRACT_OPERAND (RZ
, *ip
);
2441 /* Return the mask of core registers that IP writes. */
2444 gpr_write_mask (const struct mips_cl_insn
*ip
)
2446 unsigned long pinfo
, pinfo2
;
2450 pinfo
= ip
->insn_mo
->pinfo
;
2451 pinfo2
= ip
->insn_mo
->pinfo2
;
2452 if (mips_opts
.mips16
)
2454 if (pinfo
& MIPS16_INSN_WRITE_X
)
2455 mask
|= 1 << mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RX
, *ip
)];
2456 if (pinfo
& MIPS16_INSN_WRITE_Y
)
2457 mask
|= 1 << mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RY
, *ip
)];
2458 if (pinfo
& MIPS16_INSN_WRITE_Z
)
2459 mask
|= 1 << mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RZ
, *ip
)];
2460 if (pinfo
& MIPS16_INSN_WRITE_T
)
2462 if (pinfo
& MIPS16_INSN_WRITE_SP
)
2464 if (pinfo
& MIPS16_INSN_WRITE_31
)
2466 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2467 mask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
2471 if (pinfo
& INSN_WRITE_GPR_D
)
2472 mask
|= 1 << EXTRACT_OPERAND (RD
, *ip
);
2473 if (pinfo
& INSN_WRITE_GPR_T
)
2474 mask
|= 1 << EXTRACT_OPERAND (RT
, *ip
);
2475 if (pinfo
& INSN_WRITE_GPR_31
)
2477 if (pinfo2
& INSN2_WRITE_GPR_Z
)
2478 mask
|= 1 << EXTRACT_OPERAND (RZ
, *ip
);
2483 /* Return the mask of floating-point registers that IP reads. */
2486 fpr_read_mask (const struct mips_cl_insn
*ip
)
2488 unsigned long pinfo
, pinfo2
;
2492 pinfo
= ip
->insn_mo
->pinfo
;
2493 pinfo2
= ip
->insn_mo
->pinfo2
;
2494 if (!mips_opts
.mips16
)
2496 if (pinfo
& INSN_READ_FPR_S
)
2497 mask
|= 1 << EXTRACT_OPERAND (FS
, *ip
);
2498 if (pinfo
& INSN_READ_FPR_T
)
2499 mask
|= 1 << EXTRACT_OPERAND (FT
, *ip
);
2500 if (pinfo
& INSN_READ_FPR_R
)
2501 mask
|= 1 << EXTRACT_OPERAND (FR
, *ip
);
2502 if (pinfo2
& INSN2_READ_FPR_Z
)
2503 mask
|= 1 << EXTRACT_OPERAND (FZ
, *ip
);
2505 /* Conservatively treat all operands to an FP_D instruction are doubles.
2506 (This is overly pessimistic for things like cvt.d.s.) */
2507 if (HAVE_32BIT_FPRS
&& (pinfo
& FP_D
))
2512 /* Return the mask of floating-point registers that IP writes. */
2515 fpr_write_mask (const struct mips_cl_insn
*ip
)
2517 unsigned long pinfo
, pinfo2
;
2521 pinfo
= ip
->insn_mo
->pinfo
;
2522 pinfo2
= ip
->insn_mo
->pinfo2
;
2523 if (!mips_opts
.mips16
)
2525 if (pinfo
& INSN_WRITE_FPR_D
)
2526 mask
|= 1 << EXTRACT_OPERAND (FD
, *ip
);
2527 if (pinfo
& INSN_WRITE_FPR_S
)
2528 mask
|= 1 << EXTRACT_OPERAND (FS
, *ip
);
2529 if (pinfo
& INSN_WRITE_FPR_T
)
2530 mask
|= 1 << EXTRACT_OPERAND (FT
, *ip
);
2531 if (pinfo2
& INSN2_WRITE_FPR_Z
)
2532 mask
|= 1 << EXTRACT_OPERAND (FZ
, *ip
);
2534 /* Conservatively treat all operands to an FP_D instruction are doubles.
2535 (This is overly pessimistic for things like cvt.s.d.) */
2536 if (HAVE_32BIT_FPRS
&& (pinfo
& FP_D
))
2541 /* Classify an instruction according to the FIX_VR4120_* enumeration.
2542 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
2543 by VR4120 errata. */
2546 classify_vr4120_insn (const char *name
)
2548 if (strncmp (name
, "macc", 4) == 0)
2549 return FIX_VR4120_MACC
;
2550 if (strncmp (name
, "dmacc", 5) == 0)
2551 return FIX_VR4120_DMACC
;
2552 if (strncmp (name
, "mult", 4) == 0)
2553 return FIX_VR4120_MULT
;
2554 if (strncmp (name
, "dmult", 5) == 0)
2555 return FIX_VR4120_DMULT
;
2556 if (strstr (name
, "div"))
2557 return FIX_VR4120_DIV
;
2558 if (strcmp (name
, "mtlo") == 0 || strcmp (name
, "mthi") == 0)
2559 return FIX_VR4120_MTHILO
;
2560 return NUM_FIX_VR4120_CLASSES
;
2563 #define INSN_ERET 0x42000018
2564 #define INSN_DERET 0x4200001f
2566 /* Return the number of instructions that must separate INSN1 and INSN2,
2567 where INSN1 is the earlier instruction. Return the worst-case value
2568 for any INSN2 if INSN2 is null. */
2571 insns_between (const struct mips_cl_insn
*insn1
,
2572 const struct mips_cl_insn
*insn2
)
2574 unsigned long pinfo1
, pinfo2
;
2577 /* This function needs to know which pinfo flags are set for INSN2
2578 and which registers INSN2 uses. The former is stored in PINFO2 and
2579 the latter is tested via INSN2_USES_GPR. If INSN2 is null, PINFO2
2580 will have every flag set and INSN2_USES_GPR will always return true. */
2581 pinfo1
= insn1
->insn_mo
->pinfo
;
2582 pinfo2
= insn2
? insn2
->insn_mo
->pinfo
: ~0U;
2584 #define INSN2_USES_GPR(REG) \
2585 (insn2 == NULL || (gpr_read_mask (insn2) & (1U << (REG))) != 0)
2587 /* For most targets, write-after-read dependencies on the HI and LO
2588 registers must be separated by at least two instructions. */
2589 if (!hilo_interlocks
)
2591 if ((pinfo1
& INSN_READ_LO
) && (pinfo2
& INSN_WRITE_LO
))
2593 if ((pinfo1
& INSN_READ_HI
) && (pinfo2
& INSN_WRITE_HI
))
2597 /* If we're working around r7000 errata, there must be two instructions
2598 between an mfhi or mflo and any instruction that uses the result. */
2599 if (mips_7000_hilo_fix
2600 && MF_HILO_INSN (pinfo1
)
2601 && INSN2_USES_GPR (EXTRACT_OPERAND (RD
, *insn1
)))
2604 /* If we're working around 24K errata, one instruction is required
2605 if an ERET or DERET is followed by a branch instruction. */
2608 if (insn1
->insn_opcode
== INSN_ERET
2609 || insn1
->insn_opcode
== INSN_DERET
)
2612 || insn2
->insn_opcode
== INSN_ERET
2613 || insn2
->insn_opcode
== INSN_DERET
2614 || (insn2
->insn_mo
->pinfo
2615 & (INSN_UNCOND_BRANCH_DELAY
2616 | INSN_COND_BRANCH_DELAY
2617 | INSN_COND_BRANCH_LIKELY
)) != 0)
2622 /* If working around VR4120 errata, check for combinations that need
2623 a single intervening instruction. */
2624 if (mips_fix_vr4120
)
2626 unsigned int class1
, class2
;
2628 class1
= classify_vr4120_insn (insn1
->insn_mo
->name
);
2629 if (class1
!= NUM_FIX_VR4120_CLASSES
&& vr4120_conflicts
[class1
] != 0)
2633 class2
= classify_vr4120_insn (insn2
->insn_mo
->name
);
2634 if (vr4120_conflicts
[class1
] & (1 << class2
))
2639 if (!mips_opts
.mips16
)
2641 /* Check for GPR or coprocessor load delays. All such delays
2642 are on the RT register. */
2643 /* Itbl support may require additional care here. */
2644 if ((!gpr_interlocks
&& (pinfo1
& INSN_LOAD_MEMORY_DELAY
))
2645 || (!cop_interlocks
&& (pinfo1
& INSN_LOAD_COPROC_DELAY
)))
2647 know (pinfo1
& INSN_WRITE_GPR_T
);
2648 if (INSN2_USES_GPR (EXTRACT_OPERAND (RT
, *insn1
)))
2652 /* Check for generic coprocessor hazards.
2654 This case is not handled very well. There is no special
2655 knowledge of CP0 handling, and the coprocessors other than
2656 the floating point unit are not distinguished at all. */
2657 /* Itbl support may require additional care here. FIXME!
2658 Need to modify this to include knowledge about
2659 user specified delays! */
2660 else if ((!cop_interlocks
&& (pinfo1
& INSN_COPROC_MOVE_DELAY
))
2661 || (!cop_mem_interlocks
&& (pinfo1
& INSN_COPROC_MEMORY_DELAY
)))
2663 /* Handle cases where INSN1 writes to a known general coprocessor
2664 register. There must be a one instruction delay before INSN2
2665 if INSN2 reads that register, otherwise no delay is needed. */
2666 mask
= fpr_write_mask (insn1
);
2669 if (!insn2
|| (mask
& fpr_read_mask (insn2
)) != 0)
2674 /* Read-after-write dependencies on the control registers
2675 require a two-instruction gap. */
2676 if ((pinfo1
& INSN_WRITE_COND_CODE
)
2677 && (pinfo2
& INSN_READ_COND_CODE
))
2680 /* We don't know exactly what INSN1 does. If INSN2 is
2681 also a coprocessor instruction, assume there must be
2682 a one instruction gap. */
2683 if (pinfo2
& INSN_COP
)
2688 /* Check for read-after-write dependencies on the coprocessor
2689 control registers in cases where INSN1 does not need a general
2690 coprocessor delay. This means that INSN1 is a floating point
2691 comparison instruction. */
2692 /* Itbl support may require additional care here. */
2693 else if (!cop_interlocks
2694 && (pinfo1
& INSN_WRITE_COND_CODE
)
2695 && (pinfo2
& INSN_READ_COND_CODE
))
2699 #undef INSN2_USES_GPR
2704 /* Return the number of nops that would be needed to work around the
2705 VR4130 mflo/mfhi errata if instruction INSN immediately followed
2706 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
2707 that are contained within the first IGNORE instructions of HIST. */
2710 nops_for_vr4130 (int ignore
, const struct mips_cl_insn
*hist
,
2711 const struct mips_cl_insn
*insn
)
2716 /* Check if the instruction writes to HI or LO. MTHI and MTLO
2717 are not affected by the errata. */
2719 && ((insn
->insn_mo
->pinfo
& (INSN_WRITE_HI
| INSN_WRITE_LO
)) == 0
2720 || strcmp (insn
->insn_mo
->name
, "mtlo") == 0
2721 || strcmp (insn
->insn_mo
->name
, "mthi") == 0))
2724 /* Search for the first MFLO or MFHI. */
2725 for (i
= 0; i
< MAX_VR4130_NOPS
; i
++)
2726 if (MF_HILO_INSN (hist
[i
].insn_mo
->pinfo
))
2728 /* Extract the destination register. */
2729 mask
= gpr_write_mask (&hist
[i
]);
2731 /* No nops are needed if INSN reads that register. */
2732 if (insn
!= NULL
&& (gpr_read_mask (insn
) & mask
) != 0)
2735 /* ...or if any of the intervening instructions do. */
2736 for (j
= 0; j
< i
; j
++)
2737 if (gpr_read_mask (&hist
[j
]) & mask
)
2741 return MAX_VR4130_NOPS
- i
;
2746 #define BASE_REG_EQ(INSN1, INSN2) \
2747 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
2748 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
2750 /* Return the minimum alignment for this store instruction. */
2753 fix_24k_align_to (const struct mips_opcode
*mo
)
2755 if (strcmp (mo
->name
, "sh") == 0)
2758 if (strcmp (mo
->name
, "swc1") == 0
2759 || strcmp (mo
->name
, "swc2") == 0
2760 || strcmp (mo
->name
, "sw") == 0
2761 || strcmp (mo
->name
, "sc") == 0
2762 || strcmp (mo
->name
, "s.s") == 0)
2765 if (strcmp (mo
->name
, "sdc1") == 0
2766 || strcmp (mo
->name
, "sdc2") == 0
2767 || strcmp (mo
->name
, "s.d") == 0)
2774 struct fix_24k_store_info
2776 /* Immediate offset, if any, for this store instruction. */
2778 /* Alignment required by this store instruction. */
2780 /* True for register offsets. */
2781 int register_offset
;
2784 /* Comparison function used by qsort. */
2787 fix_24k_sort (const void *a
, const void *b
)
2789 const struct fix_24k_store_info
*pos1
= a
;
2790 const struct fix_24k_store_info
*pos2
= b
;
2792 return (pos1
->off
- pos2
->off
);
2795 /* INSN is a store instruction. Try to record the store information
2796 in STINFO. Return false if the information isn't known. */
2799 fix_24k_record_store_info (struct fix_24k_store_info
*stinfo
,
2800 const struct mips_cl_insn
*insn
)
2802 /* The instruction must have a known offset. */
2803 if (!insn
->complete_p
|| !strstr (insn
->insn_mo
->args
, "o("))
2806 stinfo
->off
= (insn
->insn_opcode
>> OP_SH_IMMEDIATE
) & OP_MASK_IMMEDIATE
;
2807 stinfo
->align_to
= fix_24k_align_to (insn
->insn_mo
);
2811 /* Return the number of nops that would be needed to work around the 24k
2812 "lost data on stores during refill" errata if instruction INSN
2813 immediately followed the 2 instructions described by HIST.
2814 Ignore hazards that are contained within the first IGNORE
2815 instructions of HIST.
2817 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
2818 for the data cache refills and store data. The following describes
2819 the scenario where the store data could be lost.
2821 * A data cache miss, due to either a load or a store, causing fill
2822 data to be supplied by the memory subsystem
2823 * The first three doublewords of fill data are returned and written
2825 * A sequence of four stores occurs in consecutive cycles around the
2826 final doubleword of the fill:
2830 * Zero, One or more instructions
2833 The four stores A-D must be to different doublewords of the line that
2834 is being filled. The fourth instruction in the sequence above permits
2835 the fill of the final doubleword to be transferred from the FSB into
2836 the cache. In the sequence above, the stores may be either integer
2837 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
2838 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
2839 different doublewords on the line. If the floating point unit is
2840 running in 1:2 mode, it is not possible to create the sequence above
2841 using only floating point store instructions.
2843 In this case, the cache line being filled is incorrectly marked
2844 invalid, thereby losing the data from any store to the line that
2845 occurs between the original miss and the completion of the five
2846 cycle sequence shown above.
2848 The workarounds are:
2850 * Run the data cache in write-through mode.
2851 * Insert a non-store instruction between
2852 Store A and Store B or Store B and Store C. */
2855 nops_for_24k (int ignore
, const struct mips_cl_insn
*hist
,
2856 const struct mips_cl_insn
*insn
)
2858 struct fix_24k_store_info pos
[3];
2859 int align
, i
, base_offset
;
2864 /* If the previous instruction wasn't a store, there's nothing to
2866 if ((hist
[0].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
2869 /* If the instructions after the previous one are unknown, we have
2870 to assume the worst. */
2874 /* Check whether we are dealing with three consecutive stores. */
2875 if ((insn
->insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0
2876 || (hist
[1].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
2879 /* If we don't know the relationship between the store addresses,
2880 assume the worst. */
2881 if (!BASE_REG_EQ (insn
->insn_opcode
, hist
[0].insn_opcode
)
2882 || !BASE_REG_EQ (insn
->insn_opcode
, hist
[1].insn_opcode
))
2885 if (!fix_24k_record_store_info (&pos
[0], insn
)
2886 || !fix_24k_record_store_info (&pos
[1], &hist
[0])
2887 || !fix_24k_record_store_info (&pos
[2], &hist
[1]))
2890 qsort (&pos
, 3, sizeof (struct fix_24k_store_info
), fix_24k_sort
);
2892 /* Pick a value of ALIGN and X such that all offsets are adjusted by
2893 X bytes and such that the base register + X is known to be aligned
2896 if (((insn
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == SP
)
2900 align
= pos
[0].align_to
;
2901 base_offset
= pos
[0].off
;
2902 for (i
= 1; i
< 3; i
++)
2903 if (align
< pos
[i
].align_to
)
2905 align
= pos
[i
].align_to
;
2906 base_offset
= pos
[i
].off
;
2908 for (i
= 0; i
< 3; i
++)
2909 pos
[i
].off
-= base_offset
;
2912 pos
[0].off
&= ~align
+ 1;
2913 pos
[1].off
&= ~align
+ 1;
2914 pos
[2].off
&= ~align
+ 1;
2916 /* If any two stores write to the same chunk, they also write to the
2917 same doubleword. The offsets are still sorted at this point. */
2918 if (pos
[0].off
== pos
[1].off
|| pos
[1].off
== pos
[2].off
)
2921 /* A range of at least 9 bytes is needed for the stores to be in
2922 non-overlapping doublewords. */
2923 if (pos
[2].off
- pos
[0].off
<= 8)
2926 if (pos
[2].off
- pos
[1].off
>= 24
2927 || pos
[1].off
- pos
[0].off
>= 24
2928 || pos
[2].off
- pos
[0].off
>= 32)
2934 /* Return the number of nops that would be needed if instruction INSN
2935 immediately followed the MAX_NOPS instructions given by HIST,
2936 where HIST[0] is the most recent instruction. Ignore hazards
2937 between INSN and the first IGNORE instructions in HIST.
2939 If INSN is null, return the worse-case number of nops for any
2943 nops_for_insn (int ignore
, const struct mips_cl_insn
*hist
,
2944 const struct mips_cl_insn
*insn
)
2946 int i
, nops
, tmp_nops
;
2949 for (i
= ignore
; i
< MAX_DELAY_NOPS
; i
++)
2951 tmp_nops
= insns_between (hist
+ i
, insn
) - i
;
2952 if (tmp_nops
> nops
)
2956 if (mips_fix_vr4130
)
2958 tmp_nops
= nops_for_vr4130 (ignore
, hist
, insn
);
2959 if (tmp_nops
> nops
)
2965 tmp_nops
= nops_for_24k (ignore
, hist
, insn
);
2966 if (tmp_nops
> nops
)
2973 /* The variable arguments provide NUM_INSNS extra instructions that
2974 might be added to HIST. Return the largest number of nops that
2975 would be needed after the extended sequence, ignoring hazards
2976 in the first IGNORE instructions. */
2979 nops_for_sequence (int num_insns
, int ignore
,
2980 const struct mips_cl_insn
*hist
, ...)
2983 struct mips_cl_insn buffer
[MAX_NOPS
];
2984 struct mips_cl_insn
*cursor
;
2987 va_start (args
, hist
);
2988 cursor
= buffer
+ num_insns
;
2989 memcpy (cursor
, hist
, (MAX_NOPS
- num_insns
) * sizeof (*cursor
));
2990 while (cursor
> buffer
)
2991 *--cursor
= *va_arg (args
, const struct mips_cl_insn
*);
2993 nops
= nops_for_insn (ignore
, buffer
, NULL
);
2998 /* Like nops_for_insn, but if INSN is a branch, take into account the
2999 worst-case delay for the branch target. */
3002 nops_for_insn_or_target (int ignore
, const struct mips_cl_insn
*hist
,
3003 const struct mips_cl_insn
*insn
)
3007 nops
= nops_for_insn (ignore
, hist
, insn
);
3008 if (insn
->insn_mo
->pinfo
& (INSN_UNCOND_BRANCH_DELAY
3009 | INSN_COND_BRANCH_DELAY
3010 | INSN_COND_BRANCH_LIKELY
))
3012 tmp_nops
= nops_for_sequence (2, ignore
? ignore
+ 2 : 0,
3013 hist
, insn
, NOP_INSN
);
3014 if (tmp_nops
> nops
)
3017 else if (mips_opts
.mips16
3018 && (insn
->insn_mo
->pinfo
& (MIPS16_INSN_UNCOND_BRANCH
3019 | MIPS16_INSN_COND_BRANCH
)))
3021 tmp_nops
= nops_for_sequence (1, ignore
? ignore
+ 1 : 0, hist
, insn
);
3022 if (tmp_nops
> nops
)
3028 /* Fix NOP issue: Replace nops by "or at,at,zero". */
3031 fix_loongson2f_nop (struct mips_cl_insn
* ip
)
3033 if (strcmp (ip
->insn_mo
->name
, "nop") == 0)
3034 ip
->insn_opcode
= LOONGSON2F_NOP_INSN
;
3037 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
3038 jr target pc &= 'hffff_ffff_cfff_ffff. */
3041 fix_loongson2f_jump (struct mips_cl_insn
* ip
)
3043 if (strcmp (ip
->insn_mo
->name
, "j") == 0
3044 || strcmp (ip
->insn_mo
->name
, "jr") == 0
3045 || strcmp (ip
->insn_mo
->name
, "jalr") == 0)
3053 sreg
= EXTRACT_OPERAND (RS
, *ip
);
3054 if (sreg
== ZERO
|| sreg
== KT0
|| sreg
== KT1
|| sreg
== ATREG
)
3057 ep
.X_op
= O_constant
;
3058 ep
.X_add_number
= 0xcfff0000;
3059 macro_build (&ep
, "lui", "t,u", ATREG
, BFD_RELOC_HI16
);
3060 ep
.X_add_number
= 0xffff;
3061 macro_build (&ep
, "ori", "t,r,i", ATREG
, ATREG
, BFD_RELOC_LO16
);
3062 macro_build (NULL
, "and", "d,v,t", sreg
, sreg
, ATREG
);
3067 fix_loongson2f (struct mips_cl_insn
* ip
)
3069 if (mips_fix_loongson2f_nop
)
3070 fix_loongson2f_nop (ip
);
3072 if (mips_fix_loongson2f_jump
)
3073 fix_loongson2f_jump (ip
);
3076 /* IP is a MIPS16 instruction whose opcode we have just changed.
3077 Point IP->insn_mo to the new opcode's definition. */
3080 find_altered_mips16_opcode (struct mips_cl_insn
*ip
)
3082 const struct mips_opcode
*mo
, *end
;
3084 end
= &mips16_opcodes
[bfd_mips16_num_opcodes
];
3085 for (mo
= ip
->insn_mo
; mo
< end
; mo
++)
3086 if ((ip
->insn_opcode
& mo
->mask
) == mo
->match
)
3094 /* Output an instruction. IP is the instruction information.
3095 ADDRESS_EXPR is an operand of the instruction to be used with
3099 append_insn (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
3100 bfd_reloc_code_real_type
*reloc_type
)
3102 unsigned long prev_pinfo
, pinfo
;
3103 unsigned long prev_pinfo2
, pinfo2
;
3104 relax_stateT prev_insn_frag_type
= 0;
3105 bfd_boolean relaxed_branch
= FALSE
;
3106 segment_info_type
*si
= seg_info (now_seg
);
3108 if (mips_fix_loongson2f
)
3109 fix_loongson2f (ip
);
3111 /* Mark instruction labels in mips16 mode. */
3112 mips16_mark_labels ();
3114 file_ase_mips16
|= mips_opts
.mips16
;
3116 prev_pinfo
= history
[0].insn_mo
->pinfo
;
3117 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
3118 pinfo
= ip
->insn_mo
->pinfo
;
3119 pinfo2
= ip
->insn_mo
->pinfo2
;
3121 if (address_expr
== NULL
)
3123 else if (*reloc_type
<= BFD_RELOC_UNUSED
3124 && address_expr
->X_op
== O_constant
)
3129 switch (*reloc_type
)
3132 ip
->insn_opcode
|= address_expr
->X_add_number
;
3135 case BFD_RELOC_MIPS_HIGHEST
:
3136 tmp
= (address_expr
->X_add_number
+ 0x800080008000ull
) >> 48;
3137 ip
->insn_opcode
|= tmp
& 0xffff;
3140 case BFD_RELOC_MIPS_HIGHER
:
3141 tmp
= (address_expr
->X_add_number
+ 0x80008000ull
) >> 32;
3142 ip
->insn_opcode
|= tmp
& 0xffff;
3145 case BFD_RELOC_HI16_S
:
3146 tmp
= (address_expr
->X_add_number
+ 0x8000) >> 16;
3147 ip
->insn_opcode
|= tmp
& 0xffff;
3150 case BFD_RELOC_HI16
:
3151 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 16) & 0xffff;
3154 case BFD_RELOC_UNUSED
:
3155 case BFD_RELOC_LO16
:
3156 case BFD_RELOC_MIPS_GOT_DISP
:
3157 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
3160 case BFD_RELOC_MIPS_JMP
:
3161 if ((address_expr
->X_add_number
& 3) != 0)
3162 as_bad (_("jump to misaligned address (0x%lx)"),
3163 (unsigned long) address_expr
->X_add_number
);
3164 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
3168 case BFD_RELOC_MIPS16_JMP
:
3169 if ((address_expr
->X_add_number
& 3) != 0)
3170 as_bad (_("jump to misaligned address (0x%lx)"),
3171 (unsigned long) address_expr
->X_add_number
);
3173 (((address_expr
->X_add_number
& 0x7c0000) << 3)
3174 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
3175 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
3179 case BFD_RELOC_16_PCREL_S2
:
3180 if ((address_expr
->X_add_number
& 3) != 0)
3181 as_bad (_("branch to misaligned address (0x%lx)"),
3182 (unsigned long) address_expr
->X_add_number
);
3183 if (mips_relax_branch
)
3185 if ((address_expr
->X_add_number
+ 0x20000) & ~0x3ffff)
3186 as_bad (_("branch address range overflow (0x%lx)"),
3187 (unsigned long) address_expr
->X_add_number
);
3188 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0xffff;
3197 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
3199 /* There are a lot of optimizations we could do that we don't.
3200 In particular, we do not, in general, reorder instructions.
3201 If you use gcc with optimization, it will reorder
3202 instructions and generally do much more optimization then we
3203 do here; repeating all that work in the assembler would only
3204 benefit hand written assembly code, and does not seem worth
3206 int nops
= (mips_optimize
== 0
3207 ? nops_for_insn (0, history
, NULL
)
3208 : nops_for_insn_or_target (0, history
, ip
));
3212 unsigned long old_frag_offset
;
3215 old_frag
= frag_now
;
3216 old_frag_offset
= frag_now_fix ();
3218 for (i
= 0; i
< nops
; i
++)
3223 listing_prev_line ();
3224 /* We may be at the start of a variant frag. In case we
3225 are, make sure there is enough space for the frag
3226 after the frags created by listing_prev_line. The
3227 argument to frag_grow here must be at least as large
3228 as the argument to all other calls to frag_grow in
3229 this file. We don't have to worry about being in the
3230 middle of a variant frag, because the variants insert
3231 all needed nop instructions themselves. */
3235 mips_move_labels ();
3237 #ifndef NO_ECOFF_DEBUGGING
3238 if (ECOFF_DEBUGGING
)
3239 ecoff_fix_loc (old_frag
, old_frag_offset
);
3243 else if (mips_relax
.sequence
!= 2 && prev_nop_frag
!= NULL
)
3247 /* Work out how many nops in prev_nop_frag are needed by IP,
3248 ignoring hazards generated by the first prev_nop_frag_since
3250 nops
= nops_for_insn_or_target (prev_nop_frag_since
, history
, ip
);
3251 gas_assert (nops
<= prev_nop_frag_holds
);
3253 /* Enforce NOPS as a minimum. */
3254 if (nops
> prev_nop_frag_required
)
3255 prev_nop_frag_required
= nops
;
3257 if (prev_nop_frag_holds
== prev_nop_frag_required
)
3259 /* Settle for the current number of nops. Update the history
3260 accordingly (for the benefit of any future .set reorder code). */
3261 prev_nop_frag
= NULL
;
3262 insert_into_history (prev_nop_frag_since
,
3263 prev_nop_frag_holds
, NOP_INSN
);
3267 /* Allow this instruction to replace one of the nops that was
3268 tentatively added to prev_nop_frag. */
3269 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
3270 prev_nop_frag_holds
--;
3271 prev_nop_frag_since
++;
3276 /* The value passed to dwarf2_emit_insn is the distance between
3277 the beginning of the current instruction and the address that
3278 should be recorded in the debug tables. For MIPS16 debug info
3279 we want to use ISA-encoded addresses, so we pass -1 for an
3280 address higher by one than the current. */
3281 dwarf2_emit_insn (mips_opts
.mips16
? -1 : 0);
3284 /* Record the frag type before frag_var. */
3285 if (history
[0].frag
)
3286 prev_insn_frag_type
= history
[0].frag
->fr_type
;
3289 && *reloc_type
== BFD_RELOC_16_PCREL_S2
3290 && (pinfo
& INSN_UNCOND_BRANCH_DELAY
|| pinfo
& INSN_COND_BRANCH_DELAY
3291 || pinfo
& INSN_COND_BRANCH_LIKELY
)
3292 && mips_relax_branch
3293 /* Don't try branch relaxation within .set nomacro, or within
3294 .set noat if we use $at for PIC computations. If it turns
3295 out that the branch was out-of-range, we'll get an error. */
3296 && !mips_opts
.warn_about_macros
3297 && (mips_opts
.at
|| mips_pic
== NO_PIC
)
3298 /* Don't relax BPOSGE32/64 as they have no complementing branches. */
3299 && !(ip
->insn_mo
->membership
& (INSN_DSP64
| INSN_DSP
))
3300 && !mips_opts
.mips16
)
3302 relaxed_branch
= TRUE
;
3303 add_relaxed_insn (ip
, (relaxed_branch_length
3305 (pinfo
& INSN_UNCOND_BRANCH_DELAY
) ? -1
3306 : (pinfo
& INSN_COND_BRANCH_LIKELY
) ? 1
3310 pinfo
& INSN_UNCOND_BRANCH_DELAY
,
3311 pinfo
& INSN_COND_BRANCH_LIKELY
,
3312 pinfo
& INSN_WRITE_GPR_31
,
3314 address_expr
->X_add_symbol
,
3315 address_expr
->X_add_number
);
3316 *reloc_type
= BFD_RELOC_UNUSED
;
3318 else if (*reloc_type
> BFD_RELOC_UNUSED
)
3320 /* We need to set up a variant frag. */
3321 gas_assert (mips_opts
.mips16
&& address_expr
!= NULL
);
3322 add_relaxed_insn (ip
, 4, 0,
3324 (*reloc_type
- BFD_RELOC_UNUSED
,
3325 mips16_small
, mips16_ext
,
3326 prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
,
3327 history
[0].mips16_absolute_jump_p
),
3328 make_expr_symbol (address_expr
), 0);
3330 else if (mips_opts
.mips16
3332 && *reloc_type
!= BFD_RELOC_MIPS16_JMP
)
3334 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
) == 0)
3335 /* Make sure there is enough room to swap this instruction with
3336 a following jump instruction. */
3338 add_fixed_insn (ip
);
3342 if (mips_opts
.mips16
3343 && mips_opts
.noreorder
3344 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
3345 as_warn (_("extended instruction in delay slot"));
3347 if (mips_relax
.sequence
)
3349 /* If we've reached the end of this frag, turn it into a variant
3350 frag and record the information for the instructions we've
3352 if (frag_room () < 4)
3353 relax_close_frag ();
3354 mips_relax
.sizes
[mips_relax
.sequence
- 1] += 4;
3357 if (mips_relax
.sequence
!= 2)
3358 mips_macro_warning
.sizes
[0] += 4;
3359 if (mips_relax
.sequence
!= 1)
3360 mips_macro_warning
.sizes
[1] += 4;
3362 if (mips_opts
.mips16
)
3365 ip
->mips16_absolute_jump_p
= (*reloc_type
== BFD_RELOC_MIPS16_JMP
);
3367 add_fixed_insn (ip
);
3370 if (address_expr
!= NULL
&& *reloc_type
<= BFD_RELOC_UNUSED
)
3373 && *reloc_type
< BFD_RELOC_UNUSED
)
3376 reloc_howto_type
*howto
;
3379 /* In a compound relocation, it is the final (outermost)
3380 operator that determines the relocated field. */
3381 for (i
= 1; i
< 3; i
++)
3382 if (reloc_type
[i
] == BFD_RELOC_UNUSED
)
3385 howto
= bfd_reloc_type_lookup (stdoutput
, reloc_type
[i
- 1]);
3388 /* To reproduce this failure try assembling gas/testsuites/
3389 gas/mips/mips16-intermix.s with a mips-ecoff targeted
3391 as_bad (_("Unsupported MIPS relocation number %d"), reloc_type
[i
- 1]);
3392 howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_16
);
3395 ip
->fixp
[0] = fix_new_exp (ip
->frag
, ip
->where
,
3396 bfd_get_reloc_size (howto
),
3398 reloc_type
[0] == BFD_RELOC_16_PCREL_S2
,
3401 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
3402 if (reloc_type
[0] == BFD_RELOC_MIPS16_JMP
3403 && ip
->fixp
[0]->fx_addsy
)
3404 *symbol_get_tc (ip
->fixp
[0]->fx_addsy
) = 1;
3406 /* These relocations can have an addend that won't fit in
3407 4 octets for 64bit assembly. */
3409 && ! howto
->partial_inplace
3410 && (reloc_type
[0] == BFD_RELOC_16
3411 || reloc_type
[0] == BFD_RELOC_32
3412 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
3413 || reloc_type
[0] == BFD_RELOC_GPREL16
3414 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
3415 || reloc_type
[0] == BFD_RELOC_GPREL32
3416 || reloc_type
[0] == BFD_RELOC_64
3417 || reloc_type
[0] == BFD_RELOC_CTOR
3418 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
3419 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
3420 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
3421 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
3422 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
3423 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
3424 || reloc_type
[0] == BFD_RELOC_MIPS16_GPREL
3425 || hi16_reloc_p (reloc_type
[0])
3426 || lo16_reloc_p (reloc_type
[0])))
3427 ip
->fixp
[0]->fx_no_overflow
= 1;
3429 if (mips_relax
.sequence
)
3431 if (mips_relax
.first_fixup
== 0)
3432 mips_relax
.first_fixup
= ip
->fixp
[0];
3434 else if (reloc_needs_lo_p (*reloc_type
))
3436 struct mips_hi_fixup
*hi_fixup
;
3438 /* Reuse the last entry if it already has a matching %lo. */
3439 hi_fixup
= mips_hi_fixup_list
;
3441 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
3443 hi_fixup
= ((struct mips_hi_fixup
*)
3444 xmalloc (sizeof (struct mips_hi_fixup
)));
3445 hi_fixup
->next
= mips_hi_fixup_list
;
3446 mips_hi_fixup_list
= hi_fixup
;
3448 hi_fixup
->fixp
= ip
->fixp
[0];
3449 hi_fixup
->seg
= now_seg
;
3452 /* Add fixups for the second and third relocations, if given.
3453 Note that the ABI allows the second relocation to be
3454 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
3455 moment we only use RSS_UNDEF, but we could add support
3456 for the others if it ever becomes necessary. */
3457 for (i
= 1; i
< 3; i
++)
3458 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
3460 ip
->fixp
[i
] = fix_new (ip
->frag
, ip
->where
,
3461 ip
->fixp
[0]->fx_size
, NULL
, 0,
3462 FALSE
, reloc_type
[i
]);
3464 /* Use fx_tcbit to mark compound relocs. */
3465 ip
->fixp
[0]->fx_tcbit
= 1;
3466 ip
->fixp
[i
]->fx_tcbit
= 1;
3472 /* Update the register mask information. */
3473 mips_gprmask
|= gpr_read_mask (ip
) | gpr_write_mask (ip
);
3474 mips_cprmask
[1] |= fpr_read_mask (ip
) | fpr_write_mask (ip
);
3476 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
3478 /* Filling the branch delay slot is more complex. We try to
3479 switch the branch with the previous instruction, which we can
3480 do if the previous instruction does not set up a condition
3481 that the branch tests and if the branch is not itself the
3482 target of any branch. */
3483 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
3484 || (pinfo
& INSN_COND_BRANCH_DELAY
))
3486 if (mips_optimize
< 2
3487 /* If we have seen .set volatile or .set nomove, don't
3489 || mips_opts
.nomove
!= 0
3490 /* We can't swap if the previous instruction's position
3492 || history
[0].fixed_p
3493 /* If the previous previous insn was in a .set
3494 noreorder, we can't swap. Actually, the MIPS
3495 assembler will swap in this situation. However, gcc
3496 configured -with-gnu-as will generate code like
3502 in which we can not swap the bne and INSN. If gcc is
3503 not configured -with-gnu-as, it does not output the
3505 || history
[1].noreorder_p
3506 /* If the branch is itself the target of a branch, we
3507 can not swap. We cheat on this; all we check for is
3508 whether there is a label on this instruction. If
3509 there are any branches to anything other than a
3510 label, users must use .set noreorder. */
3511 || si
->label_list
!= NULL
3512 /* If the previous instruction is in a variant frag
3513 other than this branch's one, we cannot do the swap.
3514 This does not apply to the mips16, which uses variant
3515 frags for different purposes. */
3516 || (! mips_opts
.mips16
3517 && prev_insn_frag_type
== rs_machine_dependent
)
3518 /* Check for conflicts between the branch and the instructions
3519 before the candidate delay slot. */
3520 || nops_for_insn (0, history
+ 1, ip
) > 0
3521 /* Check for conflicts between the swapped sequence and the
3522 target of the branch. */
3523 || nops_for_sequence (2, 0, history
+ 1, ip
, history
) > 0
3524 /* We do not swap with a trap instruction, since it
3525 complicates trap handlers to have the trap
3526 instruction be in a delay slot. */
3527 || (prev_pinfo
& INSN_TRAP
)
3528 /* If the branch reads a register that the previous
3529 instruction sets, we can not swap. */
3530 || (gpr_read_mask (ip
) & gpr_write_mask (&history
[0])) != 0
3531 /* If the branch writes a register that the previous
3532 instruction sets, we can not swap. */
3533 || (gpr_write_mask (ip
) & gpr_write_mask (&history
[0])) != 0
3534 /* If the branch writes a register that the previous
3535 instruction reads, we can not swap. */
3536 || (gpr_write_mask (ip
) & gpr_read_mask (&history
[0])) != 0
3537 /* If one instruction sets a condition code and the
3538 other one uses a condition code, we can not swap. */
3539 || ((pinfo
& INSN_READ_COND_CODE
)
3540 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
3541 || ((pinfo
& INSN_WRITE_COND_CODE
)
3542 && (prev_pinfo
& INSN_READ_COND_CODE
))
3543 /* If the previous instruction uses the PC, we can not
3545 || (mips_opts
.mips16
3546 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
3547 /* If the previous instruction had a fixup in mips16
3548 mode, we can not swap. This normally means that the
3549 previous instruction was a 4 byte branch anyhow. */
3550 || (mips_opts
.mips16
&& history
[0].fixp
[0])
3551 /* If the previous instruction is a sync, sync.l, or
3552 sync.p, we can not swap. */
3553 || (prev_pinfo
& INSN_SYNC
)
3554 /* If the previous instruction is an ERET or
3555 DERET, avoid the swap. */
3556 || (history
[0].insn_opcode
== INSN_ERET
)
3557 || (history
[0].insn_opcode
== INSN_DERET
))
3559 if (mips_opts
.mips16
3560 && (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
3561 && (pinfo
& (MIPS16_INSN_READ_X
| MIPS16_INSN_READ_31
))
3562 && ISA_SUPPORTS_MIPS16E
)
3564 /* Convert MIPS16 jr/jalr into a "compact" jump. */
3565 ip
->insn_opcode
|= 0x0080;
3566 find_altered_mips16_opcode (ip
);
3568 insert_into_history (0, 1, ip
);
3572 /* We could do even better for unconditional branches to
3573 portions of this object file; we could pick up the
3574 instruction at the destination, put it in the delay
3575 slot, and bump the destination address. */
3576 insert_into_history (0, 1, ip
);
3580 if (mips_relax
.sequence
)
3581 mips_relax
.sizes
[mips_relax
.sequence
- 1] += 4;
3585 /* It looks like we can actually do the swap. */
3586 struct mips_cl_insn delay
= history
[0];
3587 if (mips_opts
.mips16
)
3589 know (delay
.frag
== ip
->frag
);
3590 move_insn (ip
, delay
.frag
, delay
.where
);
3591 move_insn (&delay
, ip
->frag
, ip
->where
+ insn_length (ip
));
3593 else if (relaxed_branch
)
3595 /* Add the delay slot instruction to the end of the
3596 current frag and shrink the fixed part of the
3597 original frag. If the branch occupies the tail of
3598 the latter, move it backwards to cover the gap. */
3599 delay
.frag
->fr_fix
-= 4;
3600 if (delay
.frag
== ip
->frag
)
3601 move_insn (ip
, ip
->frag
, ip
->where
- 4);
3602 add_fixed_insn (&delay
);
3606 move_insn (&delay
, ip
->frag
, ip
->where
);
3607 move_insn (ip
, history
[0].frag
, history
[0].where
);
3611 insert_into_history (0, 1, &delay
);
3614 /* If that was an unconditional branch, forget the previous
3615 insn information. */
3616 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
3618 mips_no_prev_insn ();
3621 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
3623 /* We don't yet optimize a branch likely. What we should do
3624 is look at the target, copy the instruction found there
3625 into the delay slot, and increment the branch to jump to
3626 the next instruction. */
3627 insert_into_history (0, 1, ip
);
3631 insert_into_history (0, 1, ip
);
3634 insert_into_history (0, 1, ip
);
3636 /* We just output an insn, so the next one doesn't have a label. */
3637 mips_clear_insn_labels ();
3640 /* Forget that there was any previous instruction or label. */
3643 mips_no_prev_insn (void)
3645 prev_nop_frag
= NULL
;
3646 insert_into_history (0, ARRAY_SIZE (history
), NOP_INSN
);
3647 mips_clear_insn_labels ();
3650 /* This function must be called before we emit something other than
3651 instructions. It is like mips_no_prev_insn except that it inserts
3652 any NOPS that might be needed by previous instructions. */
3655 mips_emit_delays (void)
3657 if (! mips_opts
.noreorder
)
3659 int nops
= nops_for_insn (0, history
, NULL
);
3663 add_fixed_insn (NOP_INSN
);
3664 mips_move_labels ();
3667 mips_no_prev_insn ();
3670 /* Start a (possibly nested) noreorder block. */
3673 start_noreorder (void)
3675 if (mips_opts
.noreorder
== 0)
3680 /* None of the instructions before the .set noreorder can be moved. */
3681 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
3682 history
[i
].fixed_p
= 1;
3684 /* Insert any nops that might be needed between the .set noreorder
3685 block and the previous instructions. We will later remove any
3686 nops that turn out not to be needed. */
3687 nops
= nops_for_insn (0, history
, NULL
);
3690 if (mips_optimize
!= 0)
3692 /* Record the frag which holds the nop instructions, so
3693 that we can remove them if we don't need them. */
3694 frag_grow (mips_opts
.mips16
? nops
* 2 : nops
* 4);
3695 prev_nop_frag
= frag_now
;
3696 prev_nop_frag_holds
= nops
;
3697 prev_nop_frag_required
= 0;
3698 prev_nop_frag_since
= 0;
3701 for (; nops
> 0; --nops
)
3702 add_fixed_insn (NOP_INSN
);
3704 /* Move on to a new frag, so that it is safe to simply
3705 decrease the size of prev_nop_frag. */
3706 frag_wane (frag_now
);
3708 mips_move_labels ();
3710 mips16_mark_labels ();
3711 mips_clear_insn_labels ();
3713 mips_opts
.noreorder
++;
3714 mips_any_noreorder
= 1;
3717 /* End a nested noreorder block. */
3720 end_noreorder (void)
3723 mips_opts
.noreorder
--;
3724 if (mips_opts
.noreorder
== 0 && prev_nop_frag
!= NULL
)
3726 /* Commit to inserting prev_nop_frag_required nops and go back to
3727 handling nop insertion the .set reorder way. */
3728 prev_nop_frag
->fr_fix
-= ((prev_nop_frag_holds
- prev_nop_frag_required
)
3729 * (mips_opts
.mips16
? 2 : 4));
3730 insert_into_history (prev_nop_frag_since
,
3731 prev_nop_frag_required
, NOP_INSN
);
3732 prev_nop_frag
= NULL
;
3736 /* Set up global variables for the start of a new macro. */
3741 memset (&mips_macro_warning
.sizes
, 0, sizeof (mips_macro_warning
.sizes
));
3742 mips_macro_warning
.delay_slot_p
= (mips_opts
.noreorder
3743 && (history
[0].insn_mo
->pinfo
3744 & (INSN_UNCOND_BRANCH_DELAY
3745 | INSN_COND_BRANCH_DELAY
3746 | INSN_COND_BRANCH_LIKELY
)) != 0);
3749 /* Given that a macro is longer than 4 bytes, return the appropriate warning
3750 for it. Return null if no warning is needed. SUBTYPE is a bitmask of
3751 RELAX_DELAY_SLOT and RELAX_NOMACRO. */
3754 macro_warning (relax_substateT subtype
)
3756 if (subtype
& RELAX_DELAY_SLOT
)
3757 return _("Macro instruction expanded into multiple instructions"
3758 " in a branch delay slot");
3759 else if (subtype
& RELAX_NOMACRO
)
3760 return _("Macro instruction expanded into multiple instructions");
3765 /* Finish up a macro. Emit warnings as appropriate. */
3770 if (mips_macro_warning
.sizes
[0] > 4 || mips_macro_warning
.sizes
[1] > 4)
3772 relax_substateT subtype
;
3774 /* Set up the relaxation warning flags. */
3776 if (mips_macro_warning
.sizes
[1] > mips_macro_warning
.sizes
[0])
3777 subtype
|= RELAX_SECOND_LONGER
;
3778 if (mips_opts
.warn_about_macros
)
3779 subtype
|= RELAX_NOMACRO
;
3780 if (mips_macro_warning
.delay_slot_p
)
3781 subtype
|= RELAX_DELAY_SLOT
;
3783 if (mips_macro_warning
.sizes
[0] > 4 && mips_macro_warning
.sizes
[1] > 4)
3785 /* Either the macro has a single implementation or both
3786 implementations are longer than 4 bytes. Emit the
3788 const char *msg
= macro_warning (subtype
);
3790 as_warn ("%s", msg
);
3794 /* One implementation might need a warning but the other
3795 definitely doesn't. */
3796 mips_macro_warning
.first_frag
->fr_subtype
|= subtype
;
3801 /* Read a macro's relocation codes from *ARGS and store them in *R.
3802 The first argument in *ARGS will be either the code for a single
3803 relocation or -1 followed by the three codes that make up a
3804 composite relocation. */
3807 macro_read_relocs (va_list *args
, bfd_reloc_code_real_type
*r
)
3811 next
= va_arg (*args
, int);
3813 r
[0] = (bfd_reloc_code_real_type
) next
;
3815 for (i
= 0; i
< 3; i
++)
3816 r
[i
] = (bfd_reloc_code_real_type
) va_arg (*args
, int);
3819 /* Build an instruction created by a macro expansion. This is passed
3820 a pointer to the count of instructions created so far, an
3821 expression, the name of the instruction to build, an operand format
3822 string, and corresponding arguments. */
3825 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
3827 const struct mips_opcode
*mo
;
3828 struct mips_cl_insn insn
;
3829 bfd_reloc_code_real_type r
[3];
3832 va_start (args
, fmt
);
3834 if (mips_opts
.mips16
)
3836 mips16_macro_build (ep
, name
, fmt
, &args
);
3841 r
[0] = BFD_RELOC_UNUSED
;
3842 r
[1] = BFD_RELOC_UNUSED
;
3843 r
[2] = BFD_RELOC_UNUSED
;
3844 mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
3846 gas_assert (strcmp (name
, mo
->name
) == 0);
3850 /* Search until we get a match for NAME. It is assumed here that
3851 macros will never generate MDMX, MIPS-3D, or MT instructions. */
3852 if (strcmp (fmt
, mo
->args
) == 0
3853 && mo
->pinfo
!= INSN_MACRO
3854 && is_opcode_valid (mo
))
3858 gas_assert (mo
->name
);
3859 gas_assert (strcmp (name
, mo
->name
) == 0);
3862 create_insn (&insn
, mo
);
3880 INSERT_OPERAND (SHAMT
, insn
, va_arg (args
, int));
3885 /* Note that in the macro case, these arguments are already
3886 in MSB form. (When handling the instruction in the
3887 non-macro case, these arguments are sizes from which
3888 MSB values must be calculated.) */
3889 INSERT_OPERAND (INSMSB
, insn
, va_arg (args
, int));
3895 /* Note that in the macro case, these arguments are already
3896 in MSBD form. (When handling the instruction in the
3897 non-macro case, these arguments are sizes from which
3898 MSBD values must be calculated.) */
3899 INSERT_OPERAND (EXTMSBD
, insn
, va_arg (args
, int));
3903 INSERT_OPERAND (SEQI
, insn
, va_arg (args
, int));
3912 INSERT_OPERAND (BP
, insn
, va_arg (args
, int));
3918 INSERT_OPERAND (RT
, insn
, va_arg (args
, int));
3922 INSERT_OPERAND (CODE
, insn
, va_arg (args
, int));
3927 INSERT_OPERAND (FT
, insn
, va_arg (args
, int));
3933 INSERT_OPERAND (RD
, insn
, va_arg (args
, int));
3938 int tmp
= va_arg (args
, int);
3940 INSERT_OPERAND (RT
, insn
, tmp
);
3941 INSERT_OPERAND (RD
, insn
, tmp
);
3947 INSERT_OPERAND (FS
, insn
, va_arg (args
, int));
3954 INSERT_OPERAND (SHAMT
, insn
, va_arg (args
, int));
3958 INSERT_OPERAND (FD
, insn
, va_arg (args
, int));
3962 INSERT_OPERAND (CODE20
, insn
, va_arg (args
, int));
3966 INSERT_OPERAND (CODE19
, insn
, va_arg (args
, int));
3970 INSERT_OPERAND (CODE2
, insn
, va_arg (args
, int));
3977 INSERT_OPERAND (RS
, insn
, va_arg (args
, int));
3982 macro_read_relocs (&args
, r
);
3983 gas_assert (*r
== BFD_RELOC_GPREL16
3984 || *r
== BFD_RELOC_MIPS_HIGHER
3985 || *r
== BFD_RELOC_HI16_S
3986 || *r
== BFD_RELOC_LO16
3987 || *r
== BFD_RELOC_MIPS_GOT_OFST
);
3991 macro_read_relocs (&args
, r
);
3995 macro_read_relocs (&args
, r
);
3996 gas_assert (ep
!= NULL
3997 && (ep
->X_op
== O_constant
3998 || (ep
->X_op
== O_symbol
3999 && (*r
== BFD_RELOC_MIPS_HIGHEST
4000 || *r
== BFD_RELOC_HI16_S
4001 || *r
== BFD_RELOC_HI16
4002 || *r
== BFD_RELOC_GPREL16
4003 || *r
== BFD_RELOC_MIPS_GOT_HI16
4004 || *r
== BFD_RELOC_MIPS_CALL_HI16
))));
4008 gas_assert (ep
!= NULL
);
4011 * This allows macro() to pass an immediate expression for
4012 * creating short branches without creating a symbol.
4014 * We don't allow branch relaxation for these branches, as
4015 * they should only appear in ".set nomacro" anyway.
4017 if (ep
->X_op
== O_constant
)
4019 if ((ep
->X_add_number
& 3) != 0)
4020 as_bad (_("branch to misaligned address (0x%lx)"),
4021 (unsigned long) ep
->X_add_number
);
4022 if ((ep
->X_add_number
+ 0x20000) & ~0x3ffff)
4023 as_bad (_("branch address range overflow (0x%lx)"),
4024 (unsigned long) ep
->X_add_number
);
4025 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
4029 *r
= BFD_RELOC_16_PCREL_S2
;
4033 gas_assert (ep
!= NULL
);
4034 *r
= BFD_RELOC_MIPS_JMP
;
4038 INSERT_OPERAND (COPZ
, insn
, va_arg (args
, unsigned long));
4042 INSERT_OPERAND (CACHE
, insn
, va_arg (args
, unsigned long));
4051 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
4053 append_insn (&insn
, ep
, r
);
4057 mips16_macro_build (expressionS
*ep
, const char *name
, const char *fmt
,
4060 struct mips_opcode
*mo
;
4061 struct mips_cl_insn insn
;
4062 bfd_reloc_code_real_type r
[3]
4063 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
4065 mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
4067 gas_assert (strcmp (name
, mo
->name
) == 0);
4069 while (strcmp (fmt
, mo
->args
) != 0 || mo
->pinfo
== INSN_MACRO
)
4072 gas_assert (mo
->name
);
4073 gas_assert (strcmp (name
, mo
->name
) == 0);
4076 create_insn (&insn
, mo
);
4094 MIPS16_INSERT_OPERAND (RY
, insn
, va_arg (*args
, int));
4099 MIPS16_INSERT_OPERAND (RX
, insn
, va_arg (*args
, int));
4103 MIPS16_INSERT_OPERAND (RZ
, insn
, va_arg (*args
, int));
4107 MIPS16_INSERT_OPERAND (MOVE32Z
, insn
, va_arg (*args
, int));
4117 MIPS16_INSERT_OPERAND (REGR32
, insn
, va_arg (*args
, int));
4124 regno
= va_arg (*args
, int);
4125 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
4126 MIPS16_INSERT_OPERAND (REG32R
, insn
, regno
);
4147 gas_assert (ep
!= NULL
);
4149 if (ep
->X_op
!= O_constant
)
4150 *r
= (int) BFD_RELOC_UNUSED
+ c
;
4153 mips16_immed (NULL
, 0, c
, ep
->X_add_number
, FALSE
, FALSE
,
4154 FALSE
, &insn
.insn_opcode
, &insn
.use_extend
,
4157 *r
= BFD_RELOC_UNUSED
;
4163 MIPS16_INSERT_OPERAND (IMM6
, insn
, va_arg (*args
, int));
4170 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
4172 append_insn (&insn
, ep
, r
);
4176 * Sign-extend 32-bit mode constants that have bit 31 set and all
4177 * higher bits unset.
4180 normalize_constant_expr (expressionS
*ex
)
4182 if (ex
->X_op
== O_constant
4183 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
4184 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
4189 * Sign-extend 32-bit mode address offsets that have bit 31 set and
4190 * all higher bits unset.
4193 normalize_address_expr (expressionS
*ex
)
4195 if (((ex
->X_op
== O_constant
&& HAVE_32BIT_ADDRESSES
)
4196 || (ex
->X_op
== O_symbol
&& HAVE_32BIT_SYMBOLS
))
4197 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
4198 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
4203 * Generate a "jalr" instruction with a relocation hint to the called
4204 * function. This occurs in NewABI PIC code.
4207 macro_build_jalr (expressionS
*ep
)
4211 if (MIPS_JALR_HINT_P (ep
))
4216 macro_build (NULL
, "jalr", "d,s", RA
, PIC_CALL_REG
);
4217 if (MIPS_JALR_HINT_P (ep
))
4218 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
,
4219 4, ep
, FALSE
, BFD_RELOC_MIPS_JALR
);
4223 * Generate a "lui" instruction.
4226 macro_build_lui (expressionS
*ep
, int regnum
)
4228 expressionS high_expr
;
4229 const struct mips_opcode
*mo
;
4230 struct mips_cl_insn insn
;
4231 bfd_reloc_code_real_type r
[3]
4232 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
4233 const char *name
= "lui";
4234 const char *fmt
= "t,u";
4236 gas_assert (! mips_opts
.mips16
);
4240 if (high_expr
.X_op
== O_constant
)
4242 /* We can compute the instruction now without a relocation entry. */
4243 high_expr
.X_add_number
= ((high_expr
.X_add_number
+ 0x8000)
4245 *r
= BFD_RELOC_UNUSED
;
4249 gas_assert (ep
->X_op
== O_symbol
);
4250 /* _gp_disp is a special case, used from s_cpload.
4251 __gnu_local_gp is used if mips_no_shared. */
4252 gas_assert (mips_pic
== NO_PIC
4254 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0)
4255 || (! mips_in_shared
4256 && strcmp (S_GET_NAME (ep
->X_add_symbol
),
4257 "__gnu_local_gp") == 0));
4258 *r
= BFD_RELOC_HI16_S
;
4261 mo
= hash_find (op_hash
, name
);
4262 gas_assert (strcmp (name
, mo
->name
) == 0);
4263 gas_assert (strcmp (fmt
, mo
->args
) == 0);
4264 create_insn (&insn
, mo
);
4266 insn
.insn_opcode
= insn
.insn_mo
->match
;
4267 INSERT_OPERAND (RT
, insn
, regnum
);
4268 if (*r
== BFD_RELOC_UNUSED
)
4270 insn
.insn_opcode
|= high_expr
.X_add_number
;
4271 append_insn (&insn
, NULL
, r
);
4274 append_insn (&insn
, &high_expr
, r
);
4277 /* Generate a sequence of instructions to do a load or store from a constant
4278 offset off of a base register (breg) into/from a target register (treg),
4279 using AT if necessary. */
4281 macro_build_ldst_constoffset (expressionS
*ep
, const char *op
,
4282 int treg
, int breg
, int dbl
)
4284 gas_assert (ep
->X_op
== O_constant
);
4286 /* Sign-extending 32-bit constants makes their handling easier. */
4288 normalize_constant_expr (ep
);
4290 /* Right now, this routine can only handle signed 32-bit constants. */
4291 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
+ 0x8000))
4292 as_warn (_("operand overflow"));
4294 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
4296 /* Signed 16-bit offset will fit in the op. Easy! */
4297 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
4301 /* 32-bit offset, need multiple instructions and AT, like:
4302 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
4303 addu $tempreg,$tempreg,$breg
4304 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
4305 to handle the complete offset. */
4306 macro_build_lui (ep
, AT
);
4307 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
4308 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
4311 as_bad (_("Macro used $at after \".set noat\""));
4316 * Generates code to set the $at register to true (one)
4317 * if reg is less than the immediate expression.
4320 set_at (int reg
, int unsignedp
)
4322 if (imm_expr
.X_op
== O_constant
4323 && imm_expr
.X_add_number
>= -0x8000
4324 && imm_expr
.X_add_number
< 0x8000)
4325 macro_build (&imm_expr
, unsignedp
? "sltiu" : "slti", "t,r,j",
4326 AT
, reg
, BFD_RELOC_LO16
);
4329 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4330 macro_build (NULL
, unsignedp
? "sltu" : "slt", "d,v,t", AT
, reg
, AT
);
4334 /* Warn if an expression is not a constant. */
4337 check_absolute_expr (struct mips_cl_insn
*ip
, expressionS
*ex
)
4339 if (ex
->X_op
== O_big
)
4340 as_bad (_("unsupported large constant"));
4341 else if (ex
->X_op
!= O_constant
)
4342 as_bad (_("Instruction %s requires absolute expression"),
4345 if (HAVE_32BIT_GPRS
)
4346 normalize_constant_expr (ex
);
4349 /* Count the leading zeroes by performing a binary chop. This is a
4350 bulky bit of source, but performance is a LOT better for the
4351 majority of values than a simple loop to count the bits:
4352 for (lcnt = 0; (lcnt < 32); lcnt++)
4353 if ((v) & (1 << (31 - lcnt)))
4355 However it is not code size friendly, and the gain will drop a bit
4356 on certain cached systems.
4358 #define COUNT_TOP_ZEROES(v) \
4359 (((v) & ~0xffff) == 0 \
4360 ? ((v) & ~0xff) == 0 \
4361 ? ((v) & ~0xf) == 0 \
4362 ? ((v) & ~0x3) == 0 \
4363 ? ((v) & ~0x1) == 0 \
4368 : ((v) & ~0x7) == 0 \
4371 : ((v) & ~0x3f) == 0 \
4372 ? ((v) & ~0x1f) == 0 \
4375 : ((v) & ~0x7f) == 0 \
4378 : ((v) & ~0xfff) == 0 \
4379 ? ((v) & ~0x3ff) == 0 \
4380 ? ((v) & ~0x1ff) == 0 \
4383 : ((v) & ~0x7ff) == 0 \
4386 : ((v) & ~0x3fff) == 0 \
4387 ? ((v) & ~0x1fff) == 0 \
4390 : ((v) & ~0x7fff) == 0 \
4393 : ((v) & ~0xffffff) == 0 \
4394 ? ((v) & ~0xfffff) == 0 \
4395 ? ((v) & ~0x3ffff) == 0 \
4396 ? ((v) & ~0x1ffff) == 0 \
4399 : ((v) & ~0x7ffff) == 0 \
4402 : ((v) & ~0x3fffff) == 0 \
4403 ? ((v) & ~0x1fffff) == 0 \
4406 : ((v) & ~0x7fffff) == 0 \
4409 : ((v) & ~0xfffffff) == 0 \
4410 ? ((v) & ~0x3ffffff) == 0 \
4411 ? ((v) & ~0x1ffffff) == 0 \
4414 : ((v) & ~0x7ffffff) == 0 \
4417 : ((v) & ~0x3fffffff) == 0 \
4418 ? ((v) & ~0x1fffffff) == 0 \
4421 : ((v) & ~0x7fffffff) == 0 \
4426 * This routine generates the least number of instructions necessary to load
4427 * an absolute expression value into a register.
4430 load_register (int reg
, expressionS
*ep
, int dbl
)
4433 expressionS hi32
, lo32
;
4435 if (ep
->X_op
!= O_big
)
4437 gas_assert (ep
->X_op
== O_constant
);
4439 /* Sign-extending 32-bit constants makes their handling easier. */
4441 normalize_constant_expr (ep
);
4443 if (IS_SEXT_16BIT_NUM (ep
->X_add_number
))
4445 /* We can handle 16 bit signed values with an addiu to
4446 $zero. No need to ever use daddiu here, since $zero and
4447 the result are always correct in 32 bit mode. */
4448 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
4451 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
4453 /* We can handle 16 bit unsigned values with an ori to
4455 macro_build (ep
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
4458 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)))
4460 /* 32 bit values require an lui. */
4461 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
4462 if ((ep
->X_add_number
& 0xffff) != 0)
4463 macro_build (ep
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
4468 /* The value is larger than 32 bits. */
4470 if (!dbl
|| HAVE_32BIT_GPRS
)
4474 sprintf_vma (value
, ep
->X_add_number
);
4475 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
4476 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
4480 if (ep
->X_op
!= O_big
)
4483 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
4484 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
4485 hi32
.X_add_number
&= 0xffffffff;
4487 lo32
.X_add_number
&= 0xffffffff;
4491 gas_assert (ep
->X_add_number
> 2);
4492 if (ep
->X_add_number
== 3)
4493 generic_bignum
[3] = 0;
4494 else if (ep
->X_add_number
> 4)
4495 as_bad (_("Number larger than 64 bits"));
4496 lo32
.X_op
= O_constant
;
4497 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
4498 hi32
.X_op
= O_constant
;
4499 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
4502 if (hi32
.X_add_number
== 0)
4507 unsigned long hi
, lo
;
4509 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
4511 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
4513 macro_build (&lo32
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
4516 if (lo32
.X_add_number
& 0x80000000)
4518 macro_build (&lo32
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
4519 if (lo32
.X_add_number
& 0xffff)
4520 macro_build (&lo32
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
4525 /* Check for 16bit shifted constant. We know that hi32 is
4526 non-zero, so start the mask on the first bit of the hi32
4531 unsigned long himask
, lomask
;
4535 himask
= 0xffff >> (32 - shift
);
4536 lomask
= (0xffff << shift
) & 0xffffffff;
4540 himask
= 0xffff << (shift
- 32);
4543 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
4544 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
4548 tmp
.X_op
= O_constant
;
4550 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
4551 | (lo32
.X_add_number
>> shift
));
4553 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
4554 macro_build (&tmp
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
4555 macro_build (NULL
, (shift
>= 32) ? "dsll32" : "dsll", "d,w,<",
4556 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
4561 while (shift
<= (64 - 16));
4563 /* Find the bit number of the lowest one bit, and store the
4564 shifted value in hi/lo. */
4565 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
4566 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
4570 while ((lo
& 1) == 0)
4575 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
4581 while ((hi
& 1) == 0)
4590 /* Optimize if the shifted value is a (power of 2) - 1. */
4591 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
4592 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
4594 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
4599 /* This instruction will set the register to be all
4601 tmp
.X_op
= O_constant
;
4602 tmp
.X_add_number
= (offsetT
) -1;
4603 macro_build (&tmp
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
4607 macro_build (NULL
, (bit
>= 32) ? "dsll32" : "dsll", "d,w,<",
4608 reg
, reg
, (bit
>= 32) ? bit
- 32 : bit
);
4610 macro_build (NULL
, (shift
>= 32) ? "dsrl32" : "dsrl", "d,w,<",
4611 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
4616 /* Sign extend hi32 before calling load_register, because we can
4617 generally get better code when we load a sign extended value. */
4618 if ((hi32
.X_add_number
& 0x80000000) != 0)
4619 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
4620 load_register (reg
, &hi32
, 0);
4623 if ((lo32
.X_add_number
& 0xffff0000) == 0)
4627 macro_build (NULL
, "dsll32", "d,w,<", reg
, freg
, 0);
4635 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
4637 macro_build (&lo32
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
4638 macro_build (NULL
, "dsrl32", "d,w,<", reg
, reg
, 0);
4644 macro_build (NULL
, "dsll", "d,w,<", reg
, freg
, 16);
4648 mid16
.X_add_number
>>= 16;
4649 macro_build (&mid16
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
4650 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
4653 if ((lo32
.X_add_number
& 0xffff) != 0)
4654 macro_build (&lo32
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
4658 load_delay_nop (void)
4660 if (!gpr_interlocks
)
4661 macro_build (NULL
, "nop", "");
4664 /* Load an address into a register. */
4667 load_address (int reg
, expressionS
*ep
, int *used_at
)
4669 if (ep
->X_op
!= O_constant
4670 && ep
->X_op
!= O_symbol
)
4672 as_bad (_("expression too complex"));
4673 ep
->X_op
= O_constant
;
4676 if (ep
->X_op
== O_constant
)
4678 load_register (reg
, ep
, HAVE_64BIT_ADDRESSES
);
4682 if (mips_pic
== NO_PIC
)
4684 /* If this is a reference to a GP relative symbol, we want
4685 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
4687 lui $reg,<sym> (BFD_RELOC_HI16_S)
4688 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4689 If we have an addend, we always use the latter form.
4691 With 64bit address space and a usable $at we want
4692 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4693 lui $at,<sym> (BFD_RELOC_HI16_S)
4694 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
4695 daddiu $at,<sym> (BFD_RELOC_LO16)
4699 If $at is already in use, we use a path which is suboptimal
4700 on superscalar processors.
4701 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4702 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
4704 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
4706 daddiu $reg,<sym> (BFD_RELOC_LO16)
4708 For GP relative symbols in 64bit address space we can use
4709 the same sequence as in 32bit address space. */
4710 if (HAVE_64BIT_SYMBOLS
)
4712 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
4713 && !nopic_need_relax (ep
->X_add_symbol
, 1))
4715 relax_start (ep
->X_add_symbol
);
4716 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
4717 mips_gp_register
, BFD_RELOC_GPREL16
);
4721 if (*used_at
== 0 && mips_opts
.at
)
4723 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_HIGHEST
);
4724 macro_build (ep
, "lui", "t,u", AT
, BFD_RELOC_HI16_S
);
4725 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
4726 BFD_RELOC_MIPS_HIGHER
);
4727 macro_build (ep
, "daddiu", "t,r,j", AT
, AT
, BFD_RELOC_LO16
);
4728 macro_build (NULL
, "dsll32", "d,w,<", reg
, reg
, 0);
4729 macro_build (NULL
, "daddu", "d,v,t", reg
, reg
, AT
);
4734 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_HIGHEST
);
4735 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
4736 BFD_RELOC_MIPS_HIGHER
);
4737 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
4738 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_HI16_S
);
4739 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
4740 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_LO16
);
4743 if (mips_relax
.sequence
)
4748 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
4749 && !nopic_need_relax (ep
->X_add_symbol
, 1))
4751 relax_start (ep
->X_add_symbol
);
4752 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
4753 mips_gp_register
, BFD_RELOC_GPREL16
);
4756 macro_build_lui (ep
, reg
);
4757 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j",
4758 reg
, reg
, BFD_RELOC_LO16
);
4759 if (mips_relax
.sequence
)
4763 else if (!mips_big_got
)
4767 /* If this is a reference to an external symbol, we want
4768 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4770 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4772 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4773 If there is a constant, it must be added in after.
4775 If we have NewABI, we want
4776 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
4777 unless we're referencing a global symbol with a non-zero
4778 offset, in which case cst must be added separately. */
4781 if (ep
->X_add_number
)
4783 ex
.X_add_number
= ep
->X_add_number
;
4784 ep
->X_add_number
= 0;
4785 relax_start (ep
->X_add_symbol
);
4786 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4787 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
4788 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4789 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4790 ex
.X_op
= O_constant
;
4791 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
4792 reg
, reg
, BFD_RELOC_LO16
);
4793 ep
->X_add_number
= ex
.X_add_number
;
4796 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4797 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
4798 if (mips_relax
.sequence
)
4803 ex
.X_add_number
= ep
->X_add_number
;
4804 ep
->X_add_number
= 0;
4805 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4806 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4808 relax_start (ep
->X_add_symbol
);
4810 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4814 if (ex
.X_add_number
!= 0)
4816 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4817 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4818 ex
.X_op
= O_constant
;
4819 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
4820 reg
, reg
, BFD_RELOC_LO16
);
4824 else if (mips_big_got
)
4828 /* This is the large GOT case. If this is a reference to an
4829 external symbol, we want
4830 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4832 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
4834 Otherwise, for a reference to a local symbol in old ABI, we want
4835 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4837 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4838 If there is a constant, it must be added in after.
4840 In the NewABI, for local symbols, with or without offsets, we want:
4841 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
4842 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
4846 ex
.X_add_number
= ep
->X_add_number
;
4847 ep
->X_add_number
= 0;
4848 relax_start (ep
->X_add_symbol
);
4849 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_GOT_HI16
);
4850 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
4851 reg
, reg
, mips_gp_register
);
4852 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
4853 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
4854 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4855 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4856 else if (ex
.X_add_number
)
4858 ex
.X_op
= O_constant
;
4859 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4863 ep
->X_add_number
= ex
.X_add_number
;
4865 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4866 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
4867 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4868 BFD_RELOC_MIPS_GOT_OFST
);
4873 ex
.X_add_number
= ep
->X_add_number
;
4874 ep
->X_add_number
= 0;
4875 relax_start (ep
->X_add_symbol
);
4876 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_GOT_HI16
);
4877 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
4878 reg
, reg
, mips_gp_register
);
4879 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
4880 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
4882 if (reg_needs_delay (mips_gp_register
))
4884 /* We need a nop before loading from $gp. This special
4885 check is required because the lui which starts the main
4886 instruction stream does not refer to $gp, and so will not
4887 insert the nop which may be required. */
4888 macro_build (NULL
, "nop", "");
4890 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4891 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4893 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4897 if (ex
.X_add_number
!= 0)
4899 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4900 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4901 ex
.X_op
= O_constant
;
4902 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4910 if (!mips_opts
.at
&& *used_at
== 1)
4911 as_bad (_("Macro used $at after \".set noat\""));
4914 /* Move the contents of register SOURCE into register DEST. */
4917 move_register (int dest
, int source
)
4919 macro_build (NULL
, HAVE_32BIT_GPRS
? "addu" : "daddu", "d,v,t",
4923 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
4924 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
4925 The two alternatives are:
4927 Global symbol Local sybmol
4928 ------------- ------------
4929 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
4931 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
4933 load_got_offset emits the first instruction and add_got_offset
4934 emits the second for a 16-bit offset or add_got_offset_hilo emits
4935 a sequence to add a 32-bit offset using a scratch register. */
4938 load_got_offset (int dest
, expressionS
*local
)
4943 global
.X_add_number
= 0;
4945 relax_start (local
->X_add_symbol
);
4946 macro_build (&global
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
4947 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4949 macro_build (local
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
4950 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4955 add_got_offset (int dest
, expressionS
*local
)
4959 global
.X_op
= O_constant
;
4960 global
.X_op_symbol
= NULL
;
4961 global
.X_add_symbol
= NULL
;
4962 global
.X_add_number
= local
->X_add_number
;
4964 relax_start (local
->X_add_symbol
);
4965 macro_build (&global
, ADDRESS_ADDI_INSN
, "t,r,j",
4966 dest
, dest
, BFD_RELOC_LO16
);
4968 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", dest
, dest
, BFD_RELOC_LO16
);
4973 add_got_offset_hilo (int dest
, expressionS
*local
, int tmp
)
4976 int hold_mips_optimize
;
4978 global
.X_op
= O_constant
;
4979 global
.X_op_symbol
= NULL
;
4980 global
.X_add_symbol
= NULL
;
4981 global
.X_add_number
= local
->X_add_number
;
4983 relax_start (local
->X_add_symbol
);
4984 load_register (tmp
, &global
, HAVE_64BIT_ADDRESSES
);
4986 /* Set mips_optimize around the lui instruction to avoid
4987 inserting an unnecessary nop after the lw. */
4988 hold_mips_optimize
= mips_optimize
;
4990 macro_build_lui (&global
, tmp
);
4991 mips_optimize
= hold_mips_optimize
;
4992 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", tmp
, tmp
, BFD_RELOC_LO16
);
4995 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dest
, dest
, tmp
);
5000 * This routine implements the seemingly endless macro or synthesized
5001 * instructions and addressing modes in the mips assembly language. Many
5002 * of these macros are simple and are similar to each other. These could
5003 * probably be handled by some kind of table or grammar approach instead of
5004 * this verbose method. Others are not simple macros but are more like
5005 * optimizing code generation.
5006 * One interesting optimization is when several store macros appear
5007 * consecutively that would load AT with the upper half of the same address.
5008 * The ensuing load upper instructions are ommited. This implies some kind
5009 * of global optimization. We currently only optimize within a single macro.
5010 * For many of the load and store macros if the address is specified as a
5011 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
5012 * first load register 'at' with zero and use it as the base register. The
5013 * mips assembler simply uses register $zero. Just one tiny optimization
5017 macro (struct mips_cl_insn
*ip
)
5019 unsigned int treg
, sreg
, dreg
, breg
;
5020 unsigned int tempreg
;
5035 bfd_reloc_code_real_type r
;
5036 int hold_mips_optimize
;
5038 gas_assert (! mips_opts
.mips16
);
5040 treg
= EXTRACT_OPERAND (RT
, *ip
);
5041 dreg
= EXTRACT_OPERAND (RD
, *ip
);
5042 sreg
= breg
= EXTRACT_OPERAND (RS
, *ip
);
5043 mask
= ip
->insn_mo
->mask
;
5045 expr1
.X_op
= O_constant
;
5046 expr1
.X_op_symbol
= NULL
;
5047 expr1
.X_add_symbol
= NULL
;
5048 expr1
.X_add_number
= 1;
5062 expr1
.X_add_number
= 8;
5063 macro_build (&expr1
, "bgez", "s,p", sreg
);
5065 macro_build (NULL
, "nop", "");
5067 move_register (dreg
, sreg
);
5068 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, 0, sreg
);
5091 if (imm_expr
.X_op
== O_constant
5092 && imm_expr
.X_add_number
>= -0x8000
5093 && imm_expr
.X_add_number
< 0x8000)
5095 macro_build (&imm_expr
, s
, "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
5099 load_register (AT
, &imm_expr
, dbl
);
5100 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
5119 if (imm_expr
.X_op
== O_constant
5120 && imm_expr
.X_add_number
>= 0
5121 && imm_expr
.X_add_number
< 0x10000)
5123 if (mask
!= M_NOR_I
)
5124 macro_build (&imm_expr
, s
, "t,r,i", treg
, sreg
, BFD_RELOC_LO16
);
5127 macro_build (&imm_expr
, "ori", "t,r,i",
5128 treg
, sreg
, BFD_RELOC_LO16
);
5129 macro_build (NULL
, "nor", "d,v,t", treg
, treg
, 0);
5135 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
5136 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
5140 switch (imm_expr
.X_add_number
)
5143 macro_build (NULL
, "nop", "");
5146 macro_build (NULL
, "packrl.ph", "d,s,t", treg
, treg
, sreg
);
5149 macro_build (NULL
, "balign", "t,s,2", treg
, sreg
,
5150 (int) imm_expr
.X_add_number
);
5169 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
5171 macro_build (&offset_expr
, s
, "s,t,p", sreg
, ZERO
);
5175 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
5176 macro_build (&offset_expr
, s
, "s,t,p", sreg
, AT
);
5184 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", sreg
);
5189 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", treg
);
5193 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
5194 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, ZERO
);
5200 /* Check for > max integer. */
5201 maxnum
= 0x7fffffff;
5202 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
5209 if (imm_expr
.X_op
== O_constant
5210 && imm_expr
.X_add_number
>= maxnum
5211 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
5214 /* Result is always false. */
5216 macro_build (NULL
, "nop", "");
5218 macro_build (&offset_expr
, "bnel", "s,t,p", ZERO
, ZERO
);
5221 if (imm_expr
.X_op
!= O_constant
)
5222 as_bad (_("Unsupported large constant"));
5223 ++imm_expr
.X_add_number
;
5227 if (mask
== M_BGEL_I
)
5229 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
5231 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", sreg
);
5234 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
5236 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", sreg
);
5239 maxnum
= 0x7fffffff;
5240 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
5247 maxnum
= - maxnum
- 1;
5248 if (imm_expr
.X_op
== O_constant
5249 && imm_expr
.X_add_number
<= maxnum
5250 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
5253 /* result is always true */
5254 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
5255 macro_build (&offset_expr
, "b", "p");
5260 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, ZERO
);
5270 macro_build (&offset_expr
, likely
? "beql" : "beq",
5271 "s,t,p", ZERO
, treg
);
5275 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
5276 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, ZERO
);
5284 && imm_expr
.X_op
== O_constant
5285 && imm_expr
.X_add_number
== -1))
5287 if (imm_expr
.X_op
!= O_constant
)
5288 as_bad (_("Unsupported large constant"));
5289 ++imm_expr
.X_add_number
;
5293 if (mask
== M_BGEUL_I
)
5295 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
5297 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
5299 macro_build (&offset_expr
, likely
? "bnel" : "bne",
5300 "s,t,p", sreg
, ZERO
);
5305 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, ZERO
);
5313 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", sreg
);
5318 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", treg
);
5322 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
5323 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, ZERO
);
5331 macro_build (&offset_expr
, likely
? "bnel" : "bne",
5332 "s,t,p", sreg
, ZERO
);
5338 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
5339 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, ZERO
);
5347 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", sreg
);
5352 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", treg
);
5356 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
5357 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, ZERO
);
5363 maxnum
= 0x7fffffff;
5364 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
5371 if (imm_expr
.X_op
== O_constant
5372 && imm_expr
.X_add_number
>= maxnum
5373 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
5375 if (imm_expr
.X_op
!= O_constant
)
5376 as_bad (_("Unsupported large constant"));
5377 ++imm_expr
.X_add_number
;
5381 if (mask
== M_BLTL_I
)
5383 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
5385 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", sreg
);
5388 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
5390 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", sreg
);
5395 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, ZERO
);
5403 macro_build (&offset_expr
, likely
? "beql" : "beq",
5404 "s,t,p", sreg
, ZERO
);
5410 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
5411 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, ZERO
);
5419 && imm_expr
.X_op
== O_constant
5420 && imm_expr
.X_add_number
== -1))
5422 if (imm_expr
.X_op
!= O_constant
)
5423 as_bad (_("Unsupported large constant"));
5424 ++imm_expr
.X_add_number
;
5428 if (mask
== M_BLTUL_I
)
5430 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
5432 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
5434 macro_build (&offset_expr
, likely
? "beql" : "beq",
5435 "s,t,p", sreg
, ZERO
);
5440 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, ZERO
);
5448 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", sreg
);
5453 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", treg
);
5457 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
5458 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, ZERO
);
5468 macro_build (&offset_expr
, likely
? "bnel" : "bne",
5469 "s,t,p", ZERO
, treg
);
5473 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
5474 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, ZERO
);
5479 /* Use unsigned arithmetic. */
5483 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
5485 as_bad (_("Unsupported large constant"));
5490 pos
= imm_expr
.X_add_number
;
5491 size
= imm2_expr
.X_add_number
;
5496 as_bad (_("Improper position (%lu)"), (unsigned long) pos
);
5499 if (size
== 0 || size
> 64 || (pos
+ size
- 1) > 63)
5501 as_bad (_("Improper extract size (%lu, position %lu)"),
5502 (unsigned long) size
, (unsigned long) pos
);
5506 if (size
<= 32 && pos
< 32)
5511 else if (size
<= 32)
5521 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, (int) pos
,
5528 /* Use unsigned arithmetic. */
5532 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
5534 as_bad (_("Unsupported large constant"));
5539 pos
= imm_expr
.X_add_number
;
5540 size
= imm2_expr
.X_add_number
;
5545 as_bad (_("Improper position (%lu)"), (unsigned long) pos
);
5548 if (size
== 0 || size
> 64 || (pos
+ size
- 1) > 63)
5550 as_bad (_("Improper insert size (%lu, position %lu)"),
5551 (unsigned long) size
, (unsigned long) pos
);
5555 if (pos
< 32 && (pos
+ size
- 1) < 32)
5570 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, (int) pos
,
5571 (int) (pos
+ size
- 1));
5587 as_warn (_("Divide by zero."));
5589 macro_build (NULL
, "teq", "s,t,q", ZERO
, ZERO
, 7);
5591 macro_build (NULL
, "break", "c", 7);
5598 macro_build (NULL
, "teq", "s,t,q", treg
, ZERO
, 7);
5599 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
5603 expr1
.X_add_number
= 8;
5604 macro_build (&expr1
, "bne", "s,t,p", treg
, ZERO
);
5605 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
5606 macro_build (NULL
, "break", "c", 7);
5608 expr1
.X_add_number
= -1;
5610 load_register (AT
, &expr1
, dbl
);
5611 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
5612 macro_build (&expr1
, "bne", "s,t,p", treg
, AT
);
5615 expr1
.X_add_number
= 1;
5616 load_register (AT
, &expr1
, dbl
);
5617 macro_build (NULL
, "dsll32", "d,w,<", AT
, AT
, 31);
5621 expr1
.X_add_number
= 0x80000000;
5622 macro_build (&expr1
, "lui", "t,u", AT
, BFD_RELOC_HI16
);
5626 macro_build (NULL
, "teq", "s,t,q", sreg
, AT
, 6);
5627 /* We want to close the noreorder block as soon as possible, so
5628 that later insns are available for delay slot filling. */
5633 expr1
.X_add_number
= 8;
5634 macro_build (&expr1
, "bne", "s,t,p", sreg
, AT
);
5635 macro_build (NULL
, "nop", "");
5637 /* We want to close the noreorder block as soon as possible, so
5638 that later insns are available for delay slot filling. */
5641 macro_build (NULL
, "break", "c", 6);
5643 macro_build (NULL
, s
, "d", dreg
);
5682 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
5684 as_warn (_("Divide by zero."));
5686 macro_build (NULL
, "teq", "s,t,q", ZERO
, ZERO
, 7);
5688 macro_build (NULL
, "break", "c", 7);
5691 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
5693 if (strcmp (s2
, "mflo") == 0)
5694 move_register (dreg
, sreg
);
5696 move_register (dreg
, ZERO
);
5699 if (imm_expr
.X_op
== O_constant
5700 && imm_expr
.X_add_number
== -1
5701 && s
[strlen (s
) - 1] != 'u')
5703 if (strcmp (s2
, "mflo") == 0)
5705 macro_build (NULL
, dbl
? "dneg" : "neg", "d,w", dreg
, sreg
);
5708 move_register (dreg
, ZERO
);
5713 load_register (AT
, &imm_expr
, dbl
);
5714 macro_build (NULL
, s
, "z,s,t", sreg
, AT
);
5715 macro_build (NULL
, s2
, "d", dreg
);
5737 macro_build (NULL
, "teq", "s,t,q", treg
, ZERO
, 7);
5738 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
5739 /* We want to close the noreorder block as soon as possible, so
5740 that later insns are available for delay slot filling. */
5745 expr1
.X_add_number
= 8;
5746 macro_build (&expr1
, "bne", "s,t,p", treg
, ZERO
);
5747 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
5749 /* We want to close the noreorder block as soon as possible, so
5750 that later insns are available for delay slot filling. */
5752 macro_build (NULL
, "break", "c", 7);
5754 macro_build (NULL
, s2
, "d", dreg
);
5766 /* Load the address of a symbol into a register. If breg is not
5767 zero, we then add a base register to it. */
5769 if (dbl
&& HAVE_32BIT_GPRS
)
5770 as_warn (_("dla used to load 32-bit register"));
5772 if (!dbl
&& HAVE_64BIT_OBJECTS
)
5773 as_warn (_("la used to load 64-bit address"));
5775 if (offset_expr
.X_op
== O_constant
5776 && offset_expr
.X_add_number
>= -0x8000
5777 && offset_expr
.X_add_number
< 0x8000)
5779 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
5780 "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
5784 if (mips_opts
.at
&& (treg
== breg
))
5794 if (offset_expr
.X_op
!= O_symbol
5795 && offset_expr
.X_op
!= O_constant
)
5797 as_bad (_("Expression too complex"));
5798 offset_expr
.X_op
= O_constant
;
5801 if (offset_expr
.X_op
== O_constant
)
5802 load_register (tempreg
, &offset_expr
, HAVE_64BIT_ADDRESSES
);
5803 else if (mips_pic
== NO_PIC
)
5805 /* If this is a reference to a GP relative symbol, we want
5806 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
5808 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5809 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5810 If we have a constant, we need two instructions anyhow,
5811 so we may as well always use the latter form.
5813 With 64bit address space and a usable $at we want
5814 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5815 lui $at,<sym> (BFD_RELOC_HI16_S)
5816 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5817 daddiu $at,<sym> (BFD_RELOC_LO16)
5819 daddu $tempreg,$tempreg,$at
5821 If $at is already in use, we use a path which is suboptimal
5822 on superscalar processors.
5823 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5824 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5826 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5828 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
5830 For GP relative symbols in 64bit address space we can use
5831 the same sequence as in 32bit address space. */
5832 if (HAVE_64BIT_SYMBOLS
)
5834 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
5835 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5837 relax_start (offset_expr
.X_add_symbol
);
5838 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5839 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
5843 if (used_at
== 0 && mips_opts
.at
)
5845 macro_build (&offset_expr
, "lui", "t,u",
5846 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
5847 macro_build (&offset_expr
, "lui", "t,u",
5848 AT
, BFD_RELOC_HI16_S
);
5849 macro_build (&offset_expr
, "daddiu", "t,r,j",
5850 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
5851 macro_build (&offset_expr
, "daddiu", "t,r,j",
5852 AT
, AT
, BFD_RELOC_LO16
);
5853 macro_build (NULL
, "dsll32", "d,w,<", tempreg
, tempreg
, 0);
5854 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
5859 macro_build (&offset_expr
, "lui", "t,u",
5860 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
5861 macro_build (&offset_expr
, "daddiu", "t,r,j",
5862 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
5863 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
5864 macro_build (&offset_expr
, "daddiu", "t,r,j",
5865 tempreg
, tempreg
, BFD_RELOC_HI16_S
);
5866 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
5867 macro_build (&offset_expr
, "daddiu", "t,r,j",
5868 tempreg
, tempreg
, BFD_RELOC_LO16
);
5871 if (mips_relax
.sequence
)
5876 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
5877 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5879 relax_start (offset_expr
.X_add_symbol
);
5880 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5881 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
5884 if (!IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
5885 as_bad (_("Offset too large"));
5886 macro_build_lui (&offset_expr
, tempreg
);
5887 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5888 tempreg
, tempreg
, BFD_RELOC_LO16
);
5889 if (mips_relax
.sequence
)
5893 else if (!mips_big_got
&& !HAVE_NEWABI
)
5895 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5897 /* If this is a reference to an external symbol, and there
5898 is no constant, we want
5899 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5900 or for lca or if tempreg is PIC_CALL_REG
5901 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5902 For a local symbol, we want
5903 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5905 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5907 If we have a small constant, and this is a reference to
5908 an external symbol, we want
5909 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5911 addiu $tempreg,$tempreg,<constant>
5912 For a local symbol, we want the same instruction
5913 sequence, but we output a BFD_RELOC_LO16 reloc on the
5916 If we have a large constant, and this is a reference to
5917 an external symbol, we want
5918 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5919 lui $at,<hiconstant>
5920 addiu $at,$at,<loconstant>
5921 addu $tempreg,$tempreg,$at
5922 For a local symbol, we want the same instruction
5923 sequence, but we output a BFD_RELOC_LO16 reloc on the
5927 if (offset_expr
.X_add_number
== 0)
5929 if (mips_pic
== SVR4_PIC
5931 && (call
|| tempreg
== PIC_CALL_REG
))
5932 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
5934 relax_start (offset_expr
.X_add_symbol
);
5935 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5936 lw_reloc_type
, mips_gp_register
);
5939 /* We're going to put in an addu instruction using
5940 tempreg, so we may as well insert the nop right
5945 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5946 tempreg
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
5948 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5949 tempreg
, tempreg
, BFD_RELOC_LO16
);
5951 /* FIXME: If breg == 0, and the next instruction uses
5952 $tempreg, then if this variant case is used an extra
5953 nop will be generated. */
5955 else if (offset_expr
.X_add_number
>= -0x8000
5956 && offset_expr
.X_add_number
< 0x8000)
5958 load_got_offset (tempreg
, &offset_expr
);
5960 add_got_offset (tempreg
, &offset_expr
);
5964 expr1
.X_add_number
= offset_expr
.X_add_number
;
5965 offset_expr
.X_add_number
=
5966 ((offset_expr
.X_add_number
+ 0x8000) & 0xffff) - 0x8000;
5967 load_got_offset (tempreg
, &offset_expr
);
5968 offset_expr
.X_add_number
= expr1
.X_add_number
;
5969 /* If we are going to add in a base register, and the
5970 target register and the base register are the same,
5971 then we are using AT as a temporary register. Since
5972 we want to load the constant into AT, we add our
5973 current AT (from the global offset table) and the
5974 register into the register now, and pretend we were
5975 not using a base register. */
5979 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5984 add_got_offset_hilo (tempreg
, &offset_expr
, AT
);
5988 else if (!mips_big_got
&& HAVE_NEWABI
)
5990 int add_breg_early
= 0;
5992 /* If this is a reference to an external, and there is no
5993 constant, or local symbol (*), with or without a
5995 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5996 or for lca or if tempreg is PIC_CALL_REG
5997 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5999 If we have a small constant, and this is a reference to
6000 an external symbol, we want
6001 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
6002 addiu $tempreg,$tempreg,<constant>
6004 If we have a large constant, and this is a reference to
6005 an external symbol, we want
6006 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
6007 lui $at,<hiconstant>
6008 addiu $at,$at,<loconstant>
6009 addu $tempreg,$tempreg,$at
6011 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
6012 local symbols, even though it introduces an additional
6015 if (offset_expr
.X_add_number
)
6017 expr1
.X_add_number
= offset_expr
.X_add_number
;
6018 offset_expr
.X_add_number
= 0;
6020 relax_start (offset_expr
.X_add_symbol
);
6021 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6022 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
6024 if (expr1
.X_add_number
>= -0x8000
6025 && expr1
.X_add_number
< 0x8000)
6027 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
6028 tempreg
, tempreg
, BFD_RELOC_LO16
);
6030 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
6032 /* If we are going to add in a base register, and the
6033 target register and the base register are the same,
6034 then we are using AT as a temporary register. Since
6035 we want to load the constant into AT, we add our
6036 current AT (from the global offset table) and the
6037 register into the register now, and pretend we were
6038 not using a base register. */
6043 gas_assert (tempreg
== AT
);
6044 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6050 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
6051 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6057 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
6060 offset_expr
.X_add_number
= expr1
.X_add_number
;
6062 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6063 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
6066 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6067 treg
, tempreg
, breg
);
6073 else if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
6075 relax_start (offset_expr
.X_add_symbol
);
6076 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6077 BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
6079 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6080 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
6085 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6086 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
6089 else if (mips_big_got
&& !HAVE_NEWABI
)
6092 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
6093 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
6094 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
6096 /* This is the large GOT case. If this is a reference to an
6097 external symbol, and there is no constant, we want
6098 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6099 addu $tempreg,$tempreg,$gp
6100 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6101 or for lca or if tempreg is PIC_CALL_REG
6102 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
6103 addu $tempreg,$tempreg,$gp
6104 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
6105 For a local symbol, we want
6106 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6108 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6110 If we have a small constant, and this is a reference to
6111 an external symbol, we want
6112 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6113 addu $tempreg,$tempreg,$gp
6114 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6116 addiu $tempreg,$tempreg,<constant>
6117 For a local symbol, we want
6118 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6120 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
6122 If we have a large constant, and this is a reference to
6123 an external symbol, we want
6124 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6125 addu $tempreg,$tempreg,$gp
6126 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6127 lui $at,<hiconstant>
6128 addiu $at,$at,<loconstant>
6129 addu $tempreg,$tempreg,$at
6130 For a local symbol, we want
6131 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6132 lui $at,<hiconstant>
6133 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
6134 addu $tempreg,$tempreg,$at
6137 expr1
.X_add_number
= offset_expr
.X_add_number
;
6138 offset_expr
.X_add_number
= 0;
6139 relax_start (offset_expr
.X_add_symbol
);
6140 gpdelay
= reg_needs_delay (mips_gp_register
);
6141 if (expr1
.X_add_number
== 0 && breg
== 0
6142 && (call
|| tempreg
== PIC_CALL_REG
))
6144 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
6145 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
6147 macro_build (&offset_expr
, "lui", "t,u", tempreg
, lui_reloc_type
);
6148 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6149 tempreg
, tempreg
, mips_gp_register
);
6150 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6151 tempreg
, lw_reloc_type
, tempreg
);
6152 if (expr1
.X_add_number
== 0)
6156 /* We're going to put in an addu instruction using
6157 tempreg, so we may as well insert the nop right
6162 else if (expr1
.X_add_number
>= -0x8000
6163 && expr1
.X_add_number
< 0x8000)
6166 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
6167 tempreg
, tempreg
, BFD_RELOC_LO16
);
6171 /* If we are going to add in a base register, and the
6172 target register and the base register are the same,
6173 then we are using AT as a temporary register. Since
6174 we want to load the constant into AT, we add our
6175 current AT (from the global offset table) and the
6176 register into the register now, and pretend we were
6177 not using a base register. */
6182 gas_assert (tempreg
== AT
);
6184 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6189 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
6190 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
6194 offset_expr
.X_add_number
=
6195 ((expr1
.X_add_number
+ 0x8000) & 0xffff) - 0x8000;
6200 /* This is needed because this instruction uses $gp, but
6201 the first instruction on the main stream does not. */
6202 macro_build (NULL
, "nop", "");
6205 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6206 local_reloc_type
, mips_gp_register
);
6207 if (expr1
.X_add_number
>= -0x8000
6208 && expr1
.X_add_number
< 0x8000)
6211 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
6212 tempreg
, tempreg
, BFD_RELOC_LO16
);
6213 /* FIXME: If add_number is 0, and there was no base
6214 register, the external symbol case ended with a load,
6215 so if the symbol turns out to not be external, and
6216 the next instruction uses tempreg, an unnecessary nop
6217 will be inserted. */
6223 /* We must add in the base register now, as in the
6224 external symbol case. */
6225 gas_assert (tempreg
== AT
);
6227 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6230 /* We set breg to 0 because we have arranged to add
6231 it in in both cases. */
6235 macro_build_lui (&expr1
, AT
);
6236 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
6237 AT
, AT
, BFD_RELOC_LO16
);
6238 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6239 tempreg
, tempreg
, AT
);
6244 else if (mips_big_got
&& HAVE_NEWABI
)
6246 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
6247 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
6248 int add_breg_early
= 0;
6250 /* This is the large GOT case. If this is a reference to an
6251 external symbol, and there is no constant, we want
6252 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6253 add $tempreg,$tempreg,$gp
6254 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6255 or for lca or if tempreg is PIC_CALL_REG
6256 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
6257 add $tempreg,$tempreg,$gp
6258 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
6260 If we have a small constant, and this is a reference to
6261 an external symbol, we want
6262 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6263 add $tempreg,$tempreg,$gp
6264 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6265 addi $tempreg,$tempreg,<constant>
6267 If we have a large constant, and this is a reference to
6268 an external symbol, we want
6269 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6270 addu $tempreg,$tempreg,$gp
6271 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6272 lui $at,<hiconstant>
6273 addi $at,$at,<loconstant>
6274 add $tempreg,$tempreg,$at
6276 If we have NewABI, and we know it's a local symbol, we want
6277 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6278 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
6279 otherwise we have to resort to GOT_HI16/GOT_LO16. */
6281 relax_start (offset_expr
.X_add_symbol
);
6283 expr1
.X_add_number
= offset_expr
.X_add_number
;
6284 offset_expr
.X_add_number
= 0;
6286 if (expr1
.X_add_number
== 0 && breg
== 0
6287 && (call
|| tempreg
== PIC_CALL_REG
))
6289 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
6290 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
6292 macro_build (&offset_expr
, "lui", "t,u", tempreg
, lui_reloc_type
);
6293 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6294 tempreg
, tempreg
, mips_gp_register
);
6295 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6296 tempreg
, lw_reloc_type
, tempreg
);
6298 if (expr1
.X_add_number
== 0)
6300 else if (expr1
.X_add_number
>= -0x8000
6301 && expr1
.X_add_number
< 0x8000)
6303 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
6304 tempreg
, tempreg
, BFD_RELOC_LO16
);
6306 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
6308 /* If we are going to add in a base register, and the
6309 target register and the base register are the same,
6310 then we are using AT as a temporary register. Since
6311 we want to load the constant into AT, we add our
6312 current AT (from the global offset table) and the
6313 register into the register now, and pretend we were
6314 not using a base register. */
6319 gas_assert (tempreg
== AT
);
6320 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6326 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
6327 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
6332 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
6335 offset_expr
.X_add_number
= expr1
.X_add_number
;
6336 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6337 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
6338 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
6339 tempreg
, BFD_RELOC_MIPS_GOT_OFST
);
6342 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6343 treg
, tempreg
, breg
);
6353 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", treg
, tempreg
, breg
);
6358 unsigned long temp
= (treg
<< 16) | (0x01);
6359 macro_build (NULL
, "c2", "C", temp
);
6365 unsigned long temp
= (0x02);
6366 macro_build (NULL
, "c2", "C", temp
);
6372 unsigned long temp
= (treg
<< 16) | (0x02);
6373 macro_build (NULL
, "c2", "C", temp
);
6378 macro_build (NULL
, "c2", "C", 3);
6383 unsigned long temp
= (treg
<< 16) | 0x03;
6384 macro_build (NULL
, "c2", "C", temp
);
6389 /* The j instruction may not be used in PIC code, since it
6390 requires an absolute address. We convert it to a b
6392 if (mips_pic
== NO_PIC
)
6393 macro_build (&offset_expr
, "j", "a");
6395 macro_build (&offset_expr
, "b", "p");
6398 /* The jal instructions must be handled as macros because when
6399 generating PIC code they expand to multi-instruction
6400 sequences. Normally they are simple instructions. */
6405 if (mips_pic
== NO_PIC
)
6406 macro_build (NULL
, "jalr", "d,s", dreg
, sreg
);
6409 if (sreg
!= PIC_CALL_REG
)
6410 as_warn (_("MIPS PIC call to register other than $25"));
6412 macro_build (NULL
, "jalr", "d,s", dreg
, sreg
);
6413 if (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
)
6415 if (mips_cprestore_offset
< 0)
6416 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6419 if (!mips_frame_reg_valid
)
6421 as_warn (_("No .frame pseudo-op used in PIC code"));
6422 /* Quiet this warning. */
6423 mips_frame_reg_valid
= 1;
6425 if (!mips_cprestore_valid
)
6427 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6428 /* Quiet this warning. */
6429 mips_cprestore_valid
= 1;
6431 if (mips_opts
.noreorder
)
6432 macro_build (NULL
, "nop", "");
6433 expr1
.X_add_number
= mips_cprestore_offset
;
6434 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
6437 HAVE_64BIT_ADDRESSES
);
6445 if (mips_pic
== NO_PIC
)
6446 macro_build (&offset_expr
, "jal", "a");
6447 else if (mips_pic
== SVR4_PIC
)
6449 /* If this is a reference to an external symbol, and we are
6450 using a small GOT, we want
6451 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
6455 lw $gp,cprestore($sp)
6456 The cprestore value is set using the .cprestore
6457 pseudo-op. If we are using a big GOT, we want
6458 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
6460 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
6464 lw $gp,cprestore($sp)
6465 If the symbol is not external, we want
6466 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6468 addiu $25,$25,<sym> (BFD_RELOC_LO16)
6471 lw $gp,cprestore($sp)
6473 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
6474 sequences above, minus nops, unless the symbol is local,
6475 which enables us to use GOT_PAGE/GOT_OFST (big got) or
6481 relax_start (offset_expr
.X_add_symbol
);
6482 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6483 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
6486 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6487 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_DISP
,
6493 relax_start (offset_expr
.X_add_symbol
);
6494 macro_build (&offset_expr
, "lui", "t,u", PIC_CALL_REG
,
6495 BFD_RELOC_MIPS_CALL_HI16
);
6496 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
6497 PIC_CALL_REG
, mips_gp_register
);
6498 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6499 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
6502 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6503 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_PAGE
,
6505 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
6506 PIC_CALL_REG
, PIC_CALL_REG
,
6507 BFD_RELOC_MIPS_GOT_OFST
);
6511 macro_build_jalr (&offset_expr
);
6515 relax_start (offset_expr
.X_add_symbol
);
6518 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6519 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
6528 gpdelay
= reg_needs_delay (mips_gp_register
);
6529 macro_build (&offset_expr
, "lui", "t,u", PIC_CALL_REG
,
6530 BFD_RELOC_MIPS_CALL_HI16
);
6531 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
6532 PIC_CALL_REG
, mips_gp_register
);
6533 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6534 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
6539 macro_build (NULL
, "nop", "");
6541 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6542 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT16
,
6545 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
6546 PIC_CALL_REG
, PIC_CALL_REG
, BFD_RELOC_LO16
);
6548 macro_build_jalr (&offset_expr
);
6550 if (mips_cprestore_offset
< 0)
6551 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6554 if (!mips_frame_reg_valid
)
6556 as_warn (_("No .frame pseudo-op used in PIC code"));
6557 /* Quiet this warning. */
6558 mips_frame_reg_valid
= 1;
6560 if (!mips_cprestore_valid
)
6562 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6563 /* Quiet this warning. */
6564 mips_cprestore_valid
= 1;
6566 if (mips_opts
.noreorder
)
6567 macro_build (NULL
, "nop", "");
6568 expr1
.X_add_number
= mips_cprestore_offset
;
6569 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
6572 HAVE_64BIT_ADDRESSES
);
6576 else if (mips_pic
== VXWORKS_PIC
)
6577 as_bad (_("Non-PIC jump used in PIC library"));
6600 /* Itbl support may require additional care here. */
6605 /* Itbl support may require additional care here. */
6610 /* Itbl support may require additional care here. */
6615 /* Itbl support may require additional care here. */
6628 /* Itbl support may require additional care here. */
6633 /* Itbl support may require additional care here. */
6638 /* Itbl support may require additional care here. */
6658 if (breg
== treg
|| coproc
|| lr
)
6679 /* Itbl support may require additional care here. */
6684 /* Itbl support may require additional care here. */
6689 /* Itbl support may require additional care here. */
6694 /* Itbl support may require additional care here. */
6718 /* Itbl support may require additional care here. */
6722 /* Itbl support may require additional care here. */
6727 /* Itbl support may require additional care here. */
6740 && NO_ISA_COP (mips_opts
.arch
)
6741 && (ip
->insn_mo
->pinfo2
& (INSN2_M_FP_S
| INSN2_M_FP_D
)) == 0)
6743 as_bad (_("Opcode not supported on this processor: %s"),
6744 mips_cpu_info_from_arch (mips_opts
.arch
)->name
);
6748 /* Itbl support may require additional care here. */
6749 if (mask
== M_LWC1_AB
6750 || mask
== M_SWC1_AB
6751 || mask
== M_LDC1_AB
6752 || mask
== M_SDC1_AB
6756 else if (mask
== M_CACHE_AB
|| mask
== M_PREF_AB
)
6763 if (offset_expr
.X_op
!= O_constant
6764 && offset_expr
.X_op
!= O_symbol
)
6766 as_bad (_("Expression too complex"));
6767 offset_expr
.X_op
= O_constant
;
6770 if (HAVE_32BIT_ADDRESSES
6771 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
6775 sprintf_vma (value
, offset_expr
.X_add_number
);
6776 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
6779 /* A constant expression in PIC code can be handled just as it
6780 is in non PIC code. */
6781 if (offset_expr
.X_op
== O_constant
)
6783 expr1
.X_add_number
= offset_expr
.X_add_number
;
6784 normalize_address_expr (&expr1
);
6785 if (!IS_SEXT_16BIT_NUM (expr1
.X_add_number
))
6787 expr1
.X_add_number
= ((expr1
.X_add_number
+ 0x8000)
6788 & ~(bfd_vma
) 0xffff);
6789 load_register (tempreg
, &expr1
, HAVE_64BIT_ADDRESSES
);
6791 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6792 tempreg
, tempreg
, breg
);
6795 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
, breg
);
6797 else if (mips_pic
== NO_PIC
)
6799 /* If this is a reference to a GP relative symbol, and there
6800 is no base register, we want
6801 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6802 Otherwise, if there is no base register, we want
6803 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
6804 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6805 If we have a constant, we need two instructions anyhow,
6806 so we always use the latter form.
6808 If we have a base register, and this is a reference to a
6809 GP relative symbol, we want
6810 addu $tempreg,$breg,$gp
6811 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
6813 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
6814 addu $tempreg,$tempreg,$breg
6815 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6816 With a constant we always use the latter case.
6818 With 64bit address space and no base register and $at usable,
6820 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6821 lui $at,<sym> (BFD_RELOC_HI16_S)
6822 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6825 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6826 If we have a base register, we want
6827 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6828 lui $at,<sym> (BFD_RELOC_HI16_S)
6829 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6833 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6835 Without $at we can't generate the optimal path for superscalar
6836 processors here since this would require two temporary registers.
6837 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6838 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6840 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
6842 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6843 If we have a base register, we want
6844 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6845 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6847 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
6849 daddu $tempreg,$tempreg,$breg
6850 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6852 For GP relative symbols in 64bit address space we can use
6853 the same sequence as in 32bit address space. */
6854 if (HAVE_64BIT_SYMBOLS
)
6856 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6857 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6859 relax_start (offset_expr
.X_add_symbol
);
6862 macro_build (&offset_expr
, s
, fmt
, treg
,
6863 BFD_RELOC_GPREL16
, mips_gp_register
);
6867 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6868 tempreg
, breg
, mips_gp_register
);
6869 macro_build (&offset_expr
, s
, fmt
, treg
,
6870 BFD_RELOC_GPREL16
, tempreg
);
6875 if (used_at
== 0 && mips_opts
.at
)
6877 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6878 BFD_RELOC_MIPS_HIGHEST
);
6879 macro_build (&offset_expr
, "lui", "t,u", AT
,
6881 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
6882 tempreg
, BFD_RELOC_MIPS_HIGHER
);
6884 macro_build (NULL
, "daddu", "d,v,t", AT
, AT
, breg
);
6885 macro_build (NULL
, "dsll32", "d,w,<", tempreg
, tempreg
, 0);
6886 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
6887 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
,
6893 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6894 BFD_RELOC_MIPS_HIGHEST
);
6895 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
6896 tempreg
, BFD_RELOC_MIPS_HIGHER
);
6897 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
6898 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
6899 tempreg
, BFD_RELOC_HI16_S
);
6900 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
6902 macro_build (NULL
, "daddu", "d,v,t",
6903 tempreg
, tempreg
, breg
);
6904 macro_build (&offset_expr
, s
, fmt
, treg
,
6905 BFD_RELOC_LO16
, tempreg
);
6908 if (mips_relax
.sequence
)
6915 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6916 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6918 relax_start (offset_expr
.X_add_symbol
);
6919 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_GPREL16
,
6923 macro_build_lui (&offset_expr
, tempreg
);
6924 macro_build (&offset_expr
, s
, fmt
, treg
,
6925 BFD_RELOC_LO16
, tempreg
);
6926 if (mips_relax
.sequence
)
6931 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6932 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6934 relax_start (offset_expr
.X_add_symbol
);
6935 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6936 tempreg
, breg
, mips_gp_register
);
6937 macro_build (&offset_expr
, s
, fmt
, treg
,
6938 BFD_RELOC_GPREL16
, tempreg
);
6941 macro_build_lui (&offset_expr
, tempreg
);
6942 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6943 tempreg
, tempreg
, breg
);
6944 macro_build (&offset_expr
, s
, fmt
, treg
,
6945 BFD_RELOC_LO16
, tempreg
);
6946 if (mips_relax
.sequence
)
6950 else if (!mips_big_got
)
6952 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
6954 /* If this is a reference to an external symbol, we want
6955 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6957 <op> $treg,0($tempreg)
6959 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6961 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6962 <op> $treg,0($tempreg)
6965 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6966 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
6968 If there is a base register, we add it to $tempreg before
6969 the <op>. If there is a constant, we stick it in the
6970 <op> instruction. We don't handle constants larger than
6971 16 bits, because we have no way to load the upper 16 bits
6972 (actually, we could handle them for the subset of cases
6973 in which we are not using $at). */
6974 gas_assert (offset_expr
.X_op
== O_symbol
);
6977 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6978 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
6980 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6981 tempreg
, tempreg
, breg
);
6982 macro_build (&offset_expr
, s
, fmt
, treg
,
6983 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
6986 expr1
.X_add_number
= offset_expr
.X_add_number
;
6987 offset_expr
.X_add_number
= 0;
6988 if (expr1
.X_add_number
< -0x8000
6989 || expr1
.X_add_number
>= 0x8000)
6990 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6991 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6992 lw_reloc_type
, mips_gp_register
);
6994 relax_start (offset_expr
.X_add_symbol
);
6996 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
6997 tempreg
, BFD_RELOC_LO16
);
7000 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7001 tempreg
, tempreg
, breg
);
7002 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
7004 else if (mips_big_got
&& !HAVE_NEWABI
)
7008 /* If this is a reference to an external symbol, we want
7009 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7010 addu $tempreg,$tempreg,$gp
7011 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7012 <op> $treg,0($tempreg)
7014 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7016 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7017 <op> $treg,0($tempreg)
7018 If there is a base register, we add it to $tempreg before
7019 the <op>. If there is a constant, we stick it in the
7020 <op> instruction. We don't handle constants larger than
7021 16 bits, because we have no way to load the upper 16 bits
7022 (actually, we could handle them for the subset of cases
7023 in which we are not using $at). */
7024 gas_assert (offset_expr
.X_op
== O_symbol
);
7025 expr1
.X_add_number
= offset_expr
.X_add_number
;
7026 offset_expr
.X_add_number
= 0;
7027 if (expr1
.X_add_number
< -0x8000
7028 || expr1
.X_add_number
>= 0x8000)
7029 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7030 gpdelay
= reg_needs_delay (mips_gp_register
);
7031 relax_start (offset_expr
.X_add_symbol
);
7032 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
7033 BFD_RELOC_MIPS_GOT_HI16
);
7034 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
7036 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7037 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
7040 macro_build (NULL
, "nop", "");
7041 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7042 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
7044 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
7045 tempreg
, BFD_RELOC_LO16
);
7049 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7050 tempreg
, tempreg
, breg
);
7051 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
7053 else if (mips_big_got
&& HAVE_NEWABI
)
7055 /* If this is a reference to an external symbol, we want
7056 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7057 add $tempreg,$tempreg,$gp
7058 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7059 <op> $treg,<ofst>($tempreg)
7060 Otherwise, for local symbols, we want:
7061 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
7062 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
7063 gas_assert (offset_expr
.X_op
== O_symbol
);
7064 expr1
.X_add_number
= offset_expr
.X_add_number
;
7065 offset_expr
.X_add_number
= 0;
7066 if (expr1
.X_add_number
< -0x8000
7067 || expr1
.X_add_number
>= 0x8000)
7068 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7069 relax_start (offset_expr
.X_add_symbol
);
7070 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
7071 BFD_RELOC_MIPS_GOT_HI16
);
7072 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
7074 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7075 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
7077 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7078 tempreg
, tempreg
, breg
);
7079 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
7082 offset_expr
.X_add_number
= expr1
.X_add_number
;
7083 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7084 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
7086 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7087 tempreg
, tempreg
, breg
);
7088 macro_build (&offset_expr
, s
, fmt
, treg
,
7089 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
7099 load_register (treg
, &imm_expr
, 0);
7103 load_register (treg
, &imm_expr
, 1);
7107 if (imm_expr
.X_op
== O_constant
)
7110 load_register (AT
, &imm_expr
, 0);
7111 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
7116 gas_assert (offset_expr
.X_op
== O_symbol
7117 && strcmp (segment_name (S_GET_SEGMENT
7118 (offset_expr
.X_add_symbol
)),
7120 && offset_expr
.X_add_number
== 0);
7121 macro_build (&offset_expr
, "lwc1", "T,o(b)", treg
,
7122 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
7127 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
7128 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
7129 order 32 bits of the value and the low order 32 bits are either
7130 zero or in OFFSET_EXPR. */
7131 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
7133 if (HAVE_64BIT_GPRS
)
7134 load_register (treg
, &imm_expr
, 1);
7139 if (target_big_endian
)
7151 load_register (hreg
, &imm_expr
, 0);
7154 if (offset_expr
.X_op
== O_absent
)
7155 move_register (lreg
, 0);
7158 gas_assert (offset_expr
.X_op
== O_constant
);
7159 load_register (lreg
, &offset_expr
, 0);
7166 /* We know that sym is in the .rdata section. First we get the
7167 upper 16 bits of the address. */
7168 if (mips_pic
== NO_PIC
)
7170 macro_build_lui (&offset_expr
, AT
);
7175 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
7176 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
7180 /* Now we load the register(s). */
7181 if (HAVE_64BIT_GPRS
)
7184 macro_build (&offset_expr
, "ld", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7189 macro_build (&offset_expr
, "lw", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7192 /* FIXME: How in the world do we deal with the possible
7194 offset_expr
.X_add_number
+= 4;
7195 macro_build (&offset_expr
, "lw", "t,o(b)",
7196 treg
+ 1, BFD_RELOC_LO16
, AT
);
7202 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
7203 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
7204 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
7205 the value and the low order 32 bits are either zero or in
7207 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
7210 load_register (AT
, &imm_expr
, HAVE_64BIT_FPRS
);
7211 if (HAVE_64BIT_FPRS
)
7213 gas_assert (HAVE_64BIT_GPRS
);
7214 macro_build (NULL
, "dmtc1", "t,S", AT
, treg
);
7218 macro_build (NULL
, "mtc1", "t,G", AT
, treg
+ 1);
7219 if (offset_expr
.X_op
== O_absent
)
7220 macro_build (NULL
, "mtc1", "t,G", 0, treg
);
7223 gas_assert (offset_expr
.X_op
== O_constant
);
7224 load_register (AT
, &offset_expr
, 0);
7225 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
7231 gas_assert (offset_expr
.X_op
== O_symbol
7232 && offset_expr
.X_add_number
== 0);
7233 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
7234 if (strcmp (s
, ".lit8") == 0)
7236 if (mips_opts
.isa
!= ISA_MIPS1
)
7238 macro_build (&offset_expr
, "ldc1", "T,o(b)", treg
,
7239 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
7242 breg
= mips_gp_register
;
7243 r
= BFD_RELOC_MIPS_LITERAL
;
7248 gas_assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
7250 if (mips_pic
!= NO_PIC
)
7251 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
7252 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
7255 /* FIXME: This won't work for a 64 bit address. */
7256 macro_build_lui (&offset_expr
, AT
);
7259 if (mips_opts
.isa
!= ISA_MIPS1
)
7261 macro_build (&offset_expr
, "ldc1", "T,o(b)",
7262 treg
, BFD_RELOC_LO16
, AT
);
7271 /* Even on a big endian machine $fn comes before $fn+1. We have
7272 to adjust when loading from memory. */
7275 gas_assert (mips_opts
.isa
== ISA_MIPS1
);
7276 macro_build (&offset_expr
, "lwc1", "T,o(b)",
7277 target_big_endian
? treg
+ 1 : treg
, r
, breg
);
7278 /* FIXME: A possible overflow which I don't know how to deal
7280 offset_expr
.X_add_number
+= 4;
7281 macro_build (&offset_expr
, "lwc1", "T,o(b)",
7282 target_big_endian
? treg
: treg
+ 1, r
, breg
);
7286 gas_assert (mips_opts
.isa
== ISA_MIPS1
);
7287 /* Even on a big endian machine $fn comes before $fn+1. We have
7288 to adjust when storing to memory. */
7289 macro_build (&offset_expr
, "swc1", "T,o(b)",
7290 target_big_endian
? treg
+ 1 : treg
, BFD_RELOC_LO16
, breg
);
7291 offset_expr
.X_add_number
+= 4;
7292 macro_build (&offset_expr
, "swc1", "T,o(b)",
7293 target_big_endian
? treg
: treg
+ 1, BFD_RELOC_LO16
, breg
);
7298 * The MIPS assembler seems to check for X_add_number not
7299 * being double aligned and generating:
7302 * addiu at,at,%lo(foo+1)
7305 * But, the resulting address is the same after relocation so why
7306 * generate the extra instruction?
7308 /* Itbl support may require additional care here. */
7310 if (mips_opts
.isa
!= ISA_MIPS1
)
7321 if (mips_opts
.isa
!= ISA_MIPS1
)
7329 /* Itbl support may require additional care here. */
7334 if (HAVE_64BIT_GPRS
)
7345 if (HAVE_64BIT_GPRS
)
7355 if (offset_expr
.X_op
!= O_symbol
7356 && offset_expr
.X_op
!= O_constant
)
7358 as_bad (_("Expression too complex"));
7359 offset_expr
.X_op
= O_constant
;
7362 if (HAVE_32BIT_ADDRESSES
7363 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
7367 sprintf_vma (value
, offset_expr
.X_add_number
);
7368 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
7371 /* Even on a big endian machine $fn comes before $fn+1. We have
7372 to adjust when loading from memory. We set coproc if we must
7373 load $fn+1 first. */
7374 /* Itbl support may require additional care here. */
7375 if (!target_big_endian
)
7378 if (mips_pic
== NO_PIC
|| offset_expr
.X_op
== O_constant
)
7380 /* If this is a reference to a GP relative symbol, we want
7381 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
7382 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
7383 If we have a base register, we use this
7385 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
7386 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
7387 If this is not a GP relative symbol, we want
7388 lui $at,<sym> (BFD_RELOC_HI16_S)
7389 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
7390 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
7391 If there is a base register, we add it to $at after the
7392 lui instruction. If there is a constant, we always use
7394 if (offset_expr
.X_op
== O_symbol
7395 && (valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
7396 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
7398 relax_start (offset_expr
.X_add_symbol
);
7401 tempreg
= mips_gp_register
;
7405 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7406 AT
, breg
, mips_gp_register
);
7411 /* Itbl support may require additional care here. */
7412 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
7413 BFD_RELOC_GPREL16
, tempreg
);
7414 offset_expr
.X_add_number
+= 4;
7416 /* Set mips_optimize to 2 to avoid inserting an
7418 hold_mips_optimize
= mips_optimize
;
7420 /* Itbl support may require additional care here. */
7421 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
7422 BFD_RELOC_GPREL16
, tempreg
);
7423 mips_optimize
= hold_mips_optimize
;
7427 offset_expr
.X_add_number
-= 4;
7430 macro_build_lui (&offset_expr
, AT
);
7432 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
7433 /* Itbl support may require additional care here. */
7434 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
7435 BFD_RELOC_LO16
, AT
);
7436 /* FIXME: How do we handle overflow here? */
7437 offset_expr
.X_add_number
+= 4;
7438 /* Itbl support may require additional care here. */
7439 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
7440 BFD_RELOC_LO16
, AT
);
7441 if (mips_relax
.sequence
)
7444 else if (!mips_big_got
)
7446 /* If this is a reference to an external symbol, we want
7447 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7452 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7454 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
7455 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
7456 If there is a base register we add it to $at before the
7457 lwc1 instructions. If there is a constant we include it
7458 in the lwc1 instructions. */
7460 expr1
.X_add_number
= offset_expr
.X_add_number
;
7461 if (expr1
.X_add_number
< -0x8000
7462 || expr1
.X_add_number
>= 0x8000 - 4)
7463 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7464 load_got_offset (AT
, &offset_expr
);
7467 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
7469 /* Set mips_optimize to 2 to avoid inserting an undesired
7471 hold_mips_optimize
= mips_optimize
;
7474 /* Itbl support may require additional care here. */
7475 relax_start (offset_expr
.X_add_symbol
);
7476 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
7477 BFD_RELOC_LO16
, AT
);
7478 expr1
.X_add_number
+= 4;
7479 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
7480 BFD_RELOC_LO16
, AT
);
7482 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
7483 BFD_RELOC_LO16
, AT
);
7484 offset_expr
.X_add_number
+= 4;
7485 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
7486 BFD_RELOC_LO16
, AT
);
7489 mips_optimize
= hold_mips_optimize
;
7491 else if (mips_big_got
)
7495 /* If this is a reference to an external symbol, we want
7496 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7498 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
7503 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7505 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
7506 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
7507 If there is a base register we add it to $at before the
7508 lwc1 instructions. If there is a constant we include it
7509 in the lwc1 instructions. */
7511 expr1
.X_add_number
= offset_expr
.X_add_number
;
7512 offset_expr
.X_add_number
= 0;
7513 if (expr1
.X_add_number
< -0x8000
7514 || expr1
.X_add_number
>= 0x8000 - 4)
7515 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7516 gpdelay
= reg_needs_delay (mips_gp_register
);
7517 relax_start (offset_expr
.X_add_symbol
);
7518 macro_build (&offset_expr
, "lui", "t,u",
7519 AT
, BFD_RELOC_MIPS_GOT_HI16
);
7520 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7521 AT
, AT
, mips_gp_register
);
7522 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7523 AT
, BFD_RELOC_MIPS_GOT_LO16
, AT
);
7526 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
7527 /* Itbl support may require additional care here. */
7528 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
7529 BFD_RELOC_LO16
, AT
);
7530 expr1
.X_add_number
+= 4;
7532 /* Set mips_optimize to 2 to avoid inserting an undesired
7534 hold_mips_optimize
= mips_optimize
;
7536 /* Itbl support may require additional care here. */
7537 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
7538 BFD_RELOC_LO16
, AT
);
7539 mips_optimize
= hold_mips_optimize
;
7540 expr1
.X_add_number
-= 4;
7543 offset_expr
.X_add_number
= expr1
.X_add_number
;
7545 macro_build (NULL
, "nop", "");
7546 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
7547 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
7550 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
7551 /* Itbl support may require additional care here. */
7552 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
7553 BFD_RELOC_LO16
, AT
);
7554 offset_expr
.X_add_number
+= 4;
7556 /* Set mips_optimize to 2 to avoid inserting an undesired
7558 hold_mips_optimize
= mips_optimize
;
7560 /* Itbl support may require additional care here. */
7561 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
7562 BFD_RELOC_LO16
, AT
);
7563 mips_optimize
= hold_mips_optimize
;
7572 s
= HAVE_64BIT_GPRS
? "ld" : "lw";
7575 s
= HAVE_64BIT_GPRS
? "sd" : "sw";
7577 macro_build (&offset_expr
, s
, "t,o(b)", treg
,
7578 -1, offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
7580 if (!HAVE_64BIT_GPRS
)
7582 offset_expr
.X_add_number
+= 4;
7583 macro_build (&offset_expr
, s
, "t,o(b)", treg
+ 1,
7584 -1, offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
7589 /* New code added to support COPZ instructions.
7590 This code builds table entries out of the macros in mip_opcodes.
7591 R4000 uses interlocks to handle coproc delays.
7592 Other chips (like the R3000) require nops to be inserted for delays.
7594 FIXME: Currently, we require that the user handle delays.
7595 In order to fill delay slots for non-interlocked chips,
7596 we must have a way to specify delays based on the coprocessor.
7597 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
7598 What are the side-effects of the cop instruction?
7599 What cache support might we have and what are its effects?
7600 Both coprocessor & memory require delays. how long???
7601 What registers are read/set/modified?
7603 If an itbl is provided to interpret cop instructions,
7604 this knowledge can be encoded in the itbl spec. */
7618 if (NO_ISA_COP (mips_opts
.arch
)
7619 && (ip
->insn_mo
->pinfo2
& INSN2_M_FP_S
) == 0)
7621 as_bad (_("opcode not supported on this processor: %s"),
7622 mips_cpu_info_from_arch (mips_opts
.arch
)->name
);
7626 /* For now we just do C (same as Cz). The parameter will be
7627 stored in insn_opcode by mips_ip. */
7628 macro_build (NULL
, s
, "C", ip
->insn_opcode
);
7632 move_register (dreg
, sreg
);
7638 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t", sreg
, treg
);
7639 macro_build (NULL
, "mflo", "d", dreg
);
7645 /* The MIPS assembler some times generates shifts and adds. I'm
7646 not trying to be that fancy. GCC should do this for us
7649 load_register (AT
, &imm_expr
, dbl
);
7650 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, AT
);
7651 macro_build (NULL
, "mflo", "d", dreg
);
7667 load_register (AT
, &imm_expr
, dbl
);
7668 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, imm
? AT
: treg
);
7669 macro_build (NULL
, "mflo", "d", dreg
);
7670 macro_build (NULL
, dbl
? "dsra32" : "sra", "d,w,<", dreg
, dreg
, RA
);
7671 macro_build (NULL
, "mfhi", "d", AT
);
7673 macro_build (NULL
, "tne", "s,t,q", dreg
, AT
, 6);
7676 expr1
.X_add_number
= 8;
7677 macro_build (&expr1
, "beq", "s,t,p", dreg
, AT
);
7678 macro_build (NULL
, "nop", "");
7679 macro_build (NULL
, "break", "c", 6);
7682 macro_build (NULL
, "mflo", "d", dreg
);
7698 load_register (AT
, &imm_expr
, dbl
);
7699 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t",
7700 sreg
, imm
? AT
: treg
);
7701 macro_build (NULL
, "mfhi", "d", AT
);
7702 macro_build (NULL
, "mflo", "d", dreg
);
7704 macro_build (NULL
, "tne", "s,t,q", AT
, ZERO
, 6);
7707 expr1
.X_add_number
= 8;
7708 macro_build (&expr1
, "beq", "s,t,p", AT
, ZERO
);
7709 macro_build (NULL
, "nop", "");
7710 macro_build (NULL
, "break", "c", 6);
7716 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
7727 macro_build (NULL
, "dnegu", "d,w", tempreg
, treg
);
7728 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, tempreg
);
7732 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, treg
);
7733 macro_build (NULL
, "dsrlv", "d,t,s", AT
, sreg
, AT
);
7734 macro_build (NULL
, "dsllv", "d,t,s", dreg
, sreg
, treg
);
7735 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7739 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7750 macro_build (NULL
, "negu", "d,w", tempreg
, treg
);
7751 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, tempreg
);
7755 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, treg
);
7756 macro_build (NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
7757 macro_build (NULL
, "sllv", "d,t,s", dreg
, sreg
, treg
);
7758 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7767 if (imm_expr
.X_op
!= O_constant
)
7768 as_bad (_("Improper rotate count"));
7769 rot
= imm_expr
.X_add_number
& 0x3f;
7770 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
7772 rot
= (64 - rot
) & 0x3f;
7774 macro_build (NULL
, "dror32", "d,w,<", dreg
, sreg
, rot
- 32);
7776 macro_build (NULL
, "dror", "d,w,<", dreg
, sreg
, rot
);
7781 macro_build (NULL
, "dsrl", "d,w,<", dreg
, sreg
, 0);
7784 l
= (rot
< 0x20) ? "dsll" : "dsll32";
7785 rr
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
7788 macro_build (NULL
, l
, "d,w,<", AT
, sreg
, rot
);
7789 macro_build (NULL
, rr
, "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7790 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7798 if (imm_expr
.X_op
!= O_constant
)
7799 as_bad (_("Improper rotate count"));
7800 rot
= imm_expr
.X_add_number
& 0x1f;
7801 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7803 macro_build (NULL
, "ror", "d,w,<", dreg
, sreg
, (32 - rot
) & 0x1f);
7808 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, 0);
7812 macro_build (NULL
, "sll", "d,w,<", AT
, sreg
, rot
);
7813 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7814 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7819 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
7821 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, treg
);
7825 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, treg
);
7826 macro_build (NULL
, "dsllv", "d,t,s", AT
, sreg
, AT
);
7827 macro_build (NULL
, "dsrlv", "d,t,s", dreg
, sreg
, treg
);
7828 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7832 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7834 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, treg
);
7838 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, treg
);
7839 macro_build (NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
7840 macro_build (NULL
, "srlv", "d,t,s", dreg
, sreg
, treg
);
7841 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7850 if (imm_expr
.X_op
!= O_constant
)
7851 as_bad (_("Improper rotate count"));
7852 rot
= imm_expr
.X_add_number
& 0x3f;
7853 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
7856 macro_build (NULL
, "dror32", "d,w,<", dreg
, sreg
, rot
- 32);
7858 macro_build (NULL
, "dror", "d,w,<", dreg
, sreg
, rot
);
7863 macro_build (NULL
, "dsrl", "d,w,<", dreg
, sreg
, 0);
7866 rr
= (rot
< 0x20) ? "dsrl" : "dsrl32";
7867 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
7870 macro_build (NULL
, rr
, "d,w,<", AT
, sreg
, rot
);
7871 macro_build (NULL
, l
, "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7872 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7880 if (imm_expr
.X_op
!= O_constant
)
7881 as_bad (_("Improper rotate count"));
7882 rot
= imm_expr
.X_add_number
& 0x1f;
7883 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7885 macro_build (NULL
, "ror", "d,w,<", dreg
, sreg
, rot
);
7890 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, 0);
7894 macro_build (NULL
, "srl", "d,w,<", AT
, sreg
, rot
);
7895 macro_build (NULL
, "sll", "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7896 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7902 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, treg
, BFD_RELOC_LO16
);
7904 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7907 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
7908 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
7913 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7915 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7920 as_warn (_("Instruction %s: result is always false"),
7922 move_register (dreg
, 0);
7925 if (CPU_HAS_SEQ (mips_opts
.arch
)
7926 && -512 <= imm_expr
.X_add_number
7927 && imm_expr
.X_add_number
< 512)
7929 macro_build (NULL
, "seqi", "t,r,+Q", dreg
, sreg
,
7930 (int) imm_expr
.X_add_number
);
7933 if (imm_expr
.X_op
== O_constant
7934 && imm_expr
.X_add_number
>= 0
7935 && imm_expr
.X_add_number
< 0x10000)
7937 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
7939 else if (imm_expr
.X_op
== O_constant
7940 && imm_expr
.X_add_number
> -0x8000
7941 && imm_expr
.X_add_number
< 0)
7943 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7944 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7945 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7947 else if (CPU_HAS_SEQ (mips_opts
.arch
))
7950 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7951 macro_build (NULL
, "seq", "d,v,t", dreg
, sreg
, AT
);
7956 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7957 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
7960 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
7963 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
7969 macro_build (NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
7970 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7973 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
7975 if (imm_expr
.X_op
== O_constant
7976 && imm_expr
.X_add_number
>= -0x8000
7977 && imm_expr
.X_add_number
< 0x8000)
7979 macro_build (&imm_expr
, mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j",
7980 dreg
, sreg
, BFD_RELOC_LO16
);
7984 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7985 macro_build (NULL
, mask
== M_SGE_I
? "slt" : "sltu", "d,v,t",
7989 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7992 case M_SGT
: /* sreg > treg <==> treg < sreg */
7998 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
8001 case M_SGT_I
: /* sreg > I <==> I < sreg */
8008 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
8009 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
8012 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
8018 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
8019 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
8022 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
8029 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
8030 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
8031 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
8035 if (imm_expr
.X_op
== O_constant
8036 && imm_expr
.X_add_number
>= -0x8000
8037 && imm_expr
.X_add_number
< 0x8000)
8039 macro_build (&imm_expr
, "slti", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
8043 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
8044 macro_build (NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
8048 if (imm_expr
.X_op
== O_constant
8049 && imm_expr
.X_add_number
>= -0x8000
8050 && imm_expr
.X_add_number
< 0x8000)
8052 macro_build (&imm_expr
, "sltiu", "t,r,j", dreg
, sreg
,
8057 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
8058 macro_build (NULL
, "sltu", "d,v,t", dreg
, sreg
, AT
);
8063 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, treg
);
8065 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
8068 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
8069 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
8074 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
8076 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
8081 as_warn (_("Instruction %s: result is always true"),
8083 macro_build (&expr1
, HAVE_32BIT_GPRS
? "addiu" : "daddiu", "t,r,j",
8084 dreg
, 0, BFD_RELOC_LO16
);
8087 if (CPU_HAS_SEQ (mips_opts
.arch
)
8088 && -512 <= imm_expr
.X_add_number
8089 && imm_expr
.X_add_number
< 512)
8091 macro_build (NULL
, "snei", "t,r,+Q", dreg
, sreg
,
8092 (int) imm_expr
.X_add_number
);
8095 if (imm_expr
.X_op
== O_constant
8096 && imm_expr
.X_add_number
>= 0
8097 && imm_expr
.X_add_number
< 0x10000)
8099 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
8101 else if (imm_expr
.X_op
== O_constant
8102 && imm_expr
.X_add_number
> -0x8000
8103 && imm_expr
.X_add_number
< 0)
8105 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
8106 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
8107 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
8109 else if (CPU_HAS_SEQ (mips_opts
.arch
))
8112 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
8113 macro_build (NULL
, "sne", "d,v,t", dreg
, sreg
, AT
);
8118 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
8119 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
8122 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
8128 if (imm_expr
.X_op
== O_constant
8129 && imm_expr
.X_add_number
> -0x8000
8130 && imm_expr
.X_add_number
<= 0x8000)
8132 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
8133 macro_build (&imm_expr
, dbl
? "daddi" : "addi", "t,r,j",
8134 dreg
, sreg
, BFD_RELOC_LO16
);
8138 load_register (AT
, &imm_expr
, dbl
);
8139 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, sreg
, AT
);
8145 if (imm_expr
.X_op
== O_constant
8146 && imm_expr
.X_add_number
> -0x8000
8147 && imm_expr
.X_add_number
<= 0x8000)
8149 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
8150 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "t,r,j",
8151 dreg
, sreg
, BFD_RELOC_LO16
);
8155 load_register (AT
, &imm_expr
, dbl
);
8156 macro_build (NULL
, dbl
? "dsubu" : "subu", "d,v,t", dreg
, sreg
, AT
);
8178 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
8179 macro_build (NULL
, s
, "s,t", sreg
, AT
);
8184 gas_assert (mips_opts
.isa
== ISA_MIPS1
);
8186 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
8187 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
8190 * Is the double cfc1 instruction a bug in the mips assembler;
8191 * or is there a reason for it?
8194 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
8195 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
8196 macro_build (NULL
, "nop", "");
8197 expr1
.X_add_number
= 3;
8198 macro_build (&expr1
, "ori", "t,r,i", AT
, treg
, BFD_RELOC_LO16
);
8199 expr1
.X_add_number
= 2;
8200 macro_build (&expr1
, "xori", "t,r,i", AT
, AT
, BFD_RELOC_LO16
);
8201 macro_build (NULL
, "ctc1", "t,G", AT
, RA
);
8202 macro_build (NULL
, "nop", "");
8203 macro_build (NULL
, mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S",
8205 macro_build (NULL
, "ctc1", "t,G", treg
, RA
);
8206 macro_build (NULL
, "nop", "");
8217 if (offset_expr
.X_add_number
>= 0x7fff)
8218 as_bad (_("Operand overflow"));
8219 if (!target_big_endian
)
8220 ++offset_expr
.X_add_number
;
8221 macro_build (&offset_expr
, s
, "t,o(b)", AT
, BFD_RELOC_LO16
, breg
);
8222 if (!target_big_endian
)
8223 --offset_expr
.X_add_number
;
8225 ++offset_expr
.X_add_number
;
8226 macro_build (&offset_expr
, "lbu", "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
8227 macro_build (NULL
, "sll", "d,w,<", AT
, AT
, 8);
8228 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
8241 if (offset_expr
.X_add_number
>= 0x8000 - off
)
8242 as_bad (_("Operand overflow"));
8250 if (!target_big_endian
)
8251 offset_expr
.X_add_number
+= off
;
8252 macro_build (&offset_expr
, s
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
8253 if (!target_big_endian
)
8254 offset_expr
.X_add_number
-= off
;
8256 offset_expr
.X_add_number
+= off
;
8257 macro_build (&offset_expr
, s2
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
8259 /* If necessary, move the result in tempreg to the final destination. */
8260 if (treg
== tempreg
)
8262 /* Protect second load's delay slot. */
8264 move_register (treg
, tempreg
);
8278 load_address (AT
, &offset_expr
, &used_at
);
8280 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
8281 if (!target_big_endian
)
8282 expr1
.X_add_number
= off
;
8284 expr1
.X_add_number
= 0;
8285 macro_build (&expr1
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
8286 if (!target_big_endian
)
8287 expr1
.X_add_number
= 0;
8289 expr1
.X_add_number
= off
;
8290 macro_build (&expr1
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
8296 load_address (AT
, &offset_expr
, &used_at
);
8298 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
8299 if (target_big_endian
)
8300 expr1
.X_add_number
= 0;
8301 macro_build (&expr1
, mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)",
8302 treg
, BFD_RELOC_LO16
, AT
);
8303 if (target_big_endian
)
8304 expr1
.X_add_number
= 1;
8306 expr1
.X_add_number
= 0;
8307 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
8308 macro_build (NULL
, "sll", "d,w,<", treg
, treg
, 8);
8309 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
8314 if (offset_expr
.X_add_number
>= 0x7fff)
8315 as_bad (_("Operand overflow"));
8316 if (target_big_endian
)
8317 ++offset_expr
.X_add_number
;
8318 macro_build (&offset_expr
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
8319 macro_build (NULL
, "srl", "d,w,<", AT
, treg
, 8);
8320 if (target_big_endian
)
8321 --offset_expr
.X_add_number
;
8323 ++offset_expr
.X_add_number
;
8324 macro_build (&offset_expr
, "sb", "t,o(b)", AT
, BFD_RELOC_LO16
, breg
);
8337 if (offset_expr
.X_add_number
>= 0x8000 - off
)
8338 as_bad (_("Operand overflow"));
8339 if (!target_big_endian
)
8340 offset_expr
.X_add_number
+= off
;
8341 macro_build (&offset_expr
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
8342 if (!target_big_endian
)
8343 offset_expr
.X_add_number
-= off
;
8345 offset_expr
.X_add_number
+= off
;
8346 macro_build (&offset_expr
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
8360 load_address (AT
, &offset_expr
, &used_at
);
8362 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
8363 if (!target_big_endian
)
8364 expr1
.X_add_number
= off
;
8366 expr1
.X_add_number
= 0;
8367 macro_build (&expr1
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
8368 if (!target_big_endian
)
8369 expr1
.X_add_number
= 0;
8371 expr1
.X_add_number
= off
;
8372 macro_build (&expr1
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
8377 load_address (AT
, &offset_expr
, &used_at
);
8379 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
8380 if (!target_big_endian
)
8381 expr1
.X_add_number
= 0;
8382 macro_build (&expr1
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
8383 macro_build (NULL
, "srl", "d,w,<", treg
, treg
, 8);
8384 if (!target_big_endian
)
8385 expr1
.X_add_number
= 1;
8387 expr1
.X_add_number
= 0;
8388 macro_build (&expr1
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
8389 if (!target_big_endian
)
8390 expr1
.X_add_number
= 0;
8392 expr1
.X_add_number
= 1;
8393 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
8394 macro_build (NULL
, "sll", "d,w,<", treg
, treg
, 8);
8395 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
8399 /* FIXME: Check if this is one of the itbl macros, since they
8400 are added dynamically. */
8401 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
8404 if (!mips_opts
.at
&& used_at
)
8405 as_bad (_("Macro used $at after \".set noat\""));
8408 /* Implement macros in mips16 mode. */
8411 mips16_macro (struct mips_cl_insn
*ip
)
8414 int xreg
, yreg
, zreg
, tmp
;
8417 const char *s
, *s2
, *s3
;
8419 mask
= ip
->insn_mo
->mask
;
8421 xreg
= MIPS16_EXTRACT_OPERAND (RX
, *ip
);
8422 yreg
= MIPS16_EXTRACT_OPERAND (RY
, *ip
);
8423 zreg
= MIPS16_EXTRACT_OPERAND (RZ
, *ip
);
8425 expr1
.X_op
= O_constant
;
8426 expr1
.X_op_symbol
= NULL
;
8427 expr1
.X_add_symbol
= NULL
;
8428 expr1
.X_add_number
= 1;
8448 macro_build (NULL
, dbl
? "ddiv" : "div", "0,x,y", xreg
, yreg
);
8449 expr1
.X_add_number
= 2;
8450 macro_build (&expr1
, "bnez", "x,p", yreg
);
8451 macro_build (NULL
, "break", "6", 7);
8453 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
8454 since that causes an overflow. We should do that as well,
8455 but I don't see how to do the comparisons without a temporary
8458 macro_build (NULL
, s
, "x", zreg
);
8478 macro_build (NULL
, s
, "0,x,y", xreg
, yreg
);
8479 expr1
.X_add_number
= 2;
8480 macro_build (&expr1
, "bnez", "x,p", yreg
);
8481 macro_build (NULL
, "break", "6", 7);
8483 macro_build (NULL
, s2
, "x", zreg
);
8489 macro_build (NULL
, dbl
? "dmultu" : "multu", "x,y", xreg
, yreg
);
8490 macro_build (NULL
, "mflo", "x", zreg
);
8498 if (imm_expr
.X_op
!= O_constant
)
8499 as_bad (_("Unsupported large constant"));
8500 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
8501 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "y,x,4", yreg
, xreg
);
8505 if (imm_expr
.X_op
!= O_constant
)
8506 as_bad (_("Unsupported large constant"));
8507 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
8508 macro_build (&imm_expr
, "addiu", "x,k", xreg
);
8512 if (imm_expr
.X_op
!= O_constant
)
8513 as_bad (_("Unsupported large constant"));
8514 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
8515 macro_build (&imm_expr
, "daddiu", "y,j", yreg
);
8537 goto do_reverse_branch
;
8541 goto do_reverse_branch
;
8553 goto do_reverse_branch
;
8564 macro_build (NULL
, s
, "x,y", xreg
, yreg
);
8565 macro_build (&offset_expr
, s2
, "p");
8592 goto do_addone_branch_i
;
8597 goto do_addone_branch_i
;
8612 goto do_addone_branch_i
;
8619 if (imm_expr
.X_op
!= O_constant
)
8620 as_bad (_("Unsupported large constant"));
8621 ++imm_expr
.X_add_number
;
8624 macro_build (&imm_expr
, s
, s3
, xreg
);
8625 macro_build (&offset_expr
, s2
, "p");
8629 expr1
.X_add_number
= 0;
8630 macro_build (&expr1
, "slti", "x,8", yreg
);
8632 move_register (xreg
, yreg
);
8633 expr1
.X_add_number
= 2;
8634 macro_build (&expr1
, "bteqz", "p");
8635 macro_build (NULL
, "neg", "x,w", xreg
, xreg
);
8639 /* For consistency checking, verify that all bits are specified either
8640 by the match/mask part of the instruction definition, or by the
8643 validate_mips_insn (const struct mips_opcode
*opc
)
8645 const char *p
= opc
->args
;
8647 unsigned long used_bits
= opc
->mask
;
8649 if ((used_bits
& opc
->match
) != opc
->match
)
8651 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
8652 opc
->name
, opc
->args
);
8655 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
8665 case '1': USE_BITS (OP_MASK_UDI1
, OP_SH_UDI1
); break;
8666 case '2': USE_BITS (OP_MASK_UDI2
, OP_SH_UDI2
); break;
8667 case '3': USE_BITS (OP_MASK_UDI3
, OP_SH_UDI3
); break;
8668 case '4': USE_BITS (OP_MASK_UDI4
, OP_SH_UDI4
); break;
8669 case 'A': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
8670 case 'B': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
8671 case 'C': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
8672 case 'D': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
8673 USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
8674 case 'E': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
8675 case 'F': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
8676 case 'G': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
8677 case 'H': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
8679 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8680 case 'T': USE_BITS (OP_MASK_RT
, OP_SH_RT
);
8681 USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
8682 case 'x': USE_BITS (OP_MASK_BBITIND
, OP_SH_BBITIND
); break;
8683 case 'X': USE_BITS (OP_MASK_BBITIND
, OP_SH_BBITIND
); break;
8684 case 'p': USE_BITS (OP_MASK_CINSPOS
, OP_SH_CINSPOS
); break;
8685 case 'P': USE_BITS (OP_MASK_CINSPOS
, OP_SH_CINSPOS
); break;
8686 case 'Q': USE_BITS (OP_MASK_SEQI
, OP_SH_SEQI
); break;
8687 case 's': USE_BITS (OP_MASK_CINSLM1
, OP_SH_CINSLM1
); break;
8688 case 'S': USE_BITS (OP_MASK_CINSLM1
, OP_SH_CINSLM1
); break;
8689 case 'z': USE_BITS (OP_MASK_RZ
, OP_SH_RZ
); break;
8690 case 'Z': USE_BITS (OP_MASK_FZ
, OP_SH_FZ
); break;
8691 case 'a': USE_BITS (OP_MASK_OFFSET_A
, OP_SH_OFFSET_A
); break;
8692 case 'b': USE_BITS (OP_MASK_OFFSET_B
, OP_SH_OFFSET_B
); break;
8693 case 'c': USE_BITS (OP_MASK_OFFSET_C
, OP_SH_OFFSET_C
); break;
8696 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8697 c
, opc
->name
, opc
->args
);
8701 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
8702 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
8704 case 'B': USE_BITS (OP_MASK_CODE20
, OP_SH_CODE20
); break;
8705 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
8706 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
8707 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8709 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
8710 case 'H': USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
8712 case 'J': USE_BITS (OP_MASK_CODE19
, OP_SH_CODE19
); break;
8713 case 'K': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
8715 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
8716 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
8717 case 'O': USE_BITS (OP_MASK_ALN
, OP_SH_ALN
); break;
8718 case 'Q': USE_BITS (OP_MASK_VSEL
, OP_SH_VSEL
);
8719 USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
8720 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
8721 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
8722 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
8723 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
8724 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
8725 case 'X': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
8726 case 'Y': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
8727 case 'Z': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
8728 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
8729 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8730 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
8731 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
8733 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
8734 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
8735 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
8736 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
8738 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
8739 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
8740 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
8741 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8742 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8743 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8744 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
8745 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8746 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8749 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
8750 case 'U': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
8751 USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8752 case 'e': USE_BITS (OP_MASK_VECBYTE
, OP_SH_VECBYTE
); break;
8753 case '%': USE_BITS (OP_MASK_VECALIGN
, OP_SH_VECALIGN
); break;
8756 case '1': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
8757 case '2': USE_BITS (OP_MASK_BP
, OP_SH_BP
); break;
8758 case '3': USE_BITS (OP_MASK_SA3
, OP_SH_SA3
); break;
8759 case '4': USE_BITS (OP_MASK_SA4
, OP_SH_SA4
); break;
8760 case '5': USE_BITS (OP_MASK_IMM8
, OP_SH_IMM8
); break;
8761 case '6': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8762 case '7': USE_BITS (OP_MASK_DSPACC
, OP_SH_DSPACC
); break;
8763 case '8': USE_BITS (OP_MASK_WRDSP
, OP_SH_WRDSP
); break;
8764 case '9': USE_BITS (OP_MASK_DSPACC_S
, OP_SH_DSPACC_S
);break;
8765 case '0': USE_BITS (OP_MASK_DSPSFT
, OP_SH_DSPSFT
); break;
8766 case '\'': USE_BITS (OP_MASK_RDDSP
, OP_SH_RDDSP
); break;
8767 case ':': USE_BITS (OP_MASK_DSPSFT_7
, OP_SH_DSPSFT_7
);break;
8768 case '@': USE_BITS (OP_MASK_IMM10
, OP_SH_IMM10
); break;
8769 case '!': USE_BITS (OP_MASK_MT_U
, OP_SH_MT_U
); break;
8770 case '$': USE_BITS (OP_MASK_MT_H
, OP_SH_MT_H
); break;
8771 case '*': USE_BITS (OP_MASK_MTACC_T
, OP_SH_MTACC_T
); break;
8772 case '&': USE_BITS (OP_MASK_MTACC_D
, OP_SH_MTACC_D
); break;
8773 case 'g': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
8775 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
8776 c
, opc
->name
, opc
->args
);
8780 if (used_bits
!= 0xffffffff)
8782 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
8783 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
8789 /* UDI immediates. */
8797 static const struct mips_immed mips_immed
[] = {
8798 { '1', OP_SH_UDI1
, OP_MASK_UDI1
, 0},
8799 { '2', OP_SH_UDI2
, OP_MASK_UDI2
, 0},
8800 { '3', OP_SH_UDI3
, OP_MASK_UDI3
, 0},
8801 { '4', OP_SH_UDI4
, OP_MASK_UDI4
, 0},
8805 /* Check whether an odd floating-point register is allowed. */
8807 mips_oddfpreg_ok (const struct mips_opcode
*insn
, int argnum
)
8809 const char *s
= insn
->name
;
8811 if (insn
->pinfo
== INSN_MACRO
)
8812 /* Let a macro pass, we'll catch it later when it is expanded. */
8815 if (ISA_HAS_ODD_SINGLE_FPR (mips_opts
.isa
))
8817 /* Allow odd registers for single-precision ops. */
8818 switch (insn
->pinfo
& (FP_S
| FP_D
))
8822 return 1; /* both single precision - ok */
8824 return 0; /* both double precision - fail */
8829 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
8830 s
= strchr (insn
->name
, '.');
8832 s
= s
!= NULL
? strchr (s
+ 1, '.') : NULL
;
8833 return (s
!= NULL
&& (s
[1] == 'w' || s
[1] == 's'));
8836 /* Single-precision coprocessor loads and moves are OK too. */
8837 if ((insn
->pinfo
& FP_S
)
8838 && (insn
->pinfo
& (INSN_COPROC_MEMORY_DELAY
| INSN_STORE_MEMORY
8839 | INSN_LOAD_COPROC_DELAY
| INSN_COPROC_MOVE_DELAY
)))
8845 /* This routine assembles an instruction into its binary format. As a
8846 side effect, it sets one of the global variables imm_reloc or
8847 offset_reloc to the type of relocation to do if one of the operands
8848 is an address expression. */
8851 mips_ip (char *str
, struct mips_cl_insn
*ip
)
8856 struct mips_opcode
*insn
;
8859 unsigned int lastregno
;
8860 unsigned int lastpos
= 0;
8861 unsigned int limlo
, limhi
;
8864 offsetT min_range
, max_range
;
8870 /* If the instruction contains a '.', we first try to match an instruction
8871 including the '.'. Then we try again without the '.'. */
8873 for (s
= str
; *s
!= '\0' && !ISSPACE (*s
); ++s
)
8876 /* If we stopped on whitespace, then replace the whitespace with null for
8877 the call to hash_find. Save the character we replaced just in case we
8878 have to re-parse the instruction. */
8885 insn
= (struct mips_opcode
*) hash_find (op_hash
, str
);
8887 /* If we didn't find the instruction in the opcode table, try again, but
8888 this time with just the instruction up to, but not including the
8892 /* Restore the character we overwrite above (if any). */
8896 /* Scan up to the first '.' or whitespace. */
8898 *s
!= '\0' && *s
!= '.' && !ISSPACE (*s
);
8902 /* If we did not find a '.', then we can quit now. */
8905 insn_error
= _("Unrecognized opcode");
8909 /* Lookup the instruction in the hash table. */
8911 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
8913 insn_error
= _("Unrecognized opcode");
8923 gas_assert (strcmp (insn
->name
, str
) == 0);
8925 ok
= is_opcode_valid (insn
);
8928 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
8929 && strcmp (insn
->name
, insn
[1].name
) == 0)
8938 static char buf
[100];
8940 _("opcode not supported on this processor: %s (%s)"),
8941 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
8942 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
8951 create_insn (ip
, insn
);
8954 lastregno
= 0xffffffff;
8955 for (args
= insn
->args
;; ++args
)
8959 s
+= strspn (s
, " \t");
8963 case '\0': /* end of args */
8968 case '2': /* DSP 2-bit unsigned immediate in bit 11. */
8969 my_getExpression (&imm_expr
, s
);
8970 check_absolute_expr (ip
, &imm_expr
);
8971 if ((unsigned long) imm_expr
.X_add_number
!= 1
8972 && (unsigned long) imm_expr
.X_add_number
!= 3)
8974 as_bad (_("BALIGN immediate not 1 or 3 (%lu)"),
8975 (unsigned long) imm_expr
.X_add_number
);
8977 INSERT_OPERAND (BP
, *ip
, imm_expr
.X_add_number
);
8978 imm_expr
.X_op
= O_absent
;
8982 case '3': /* DSP 3-bit unsigned immediate in bit 21. */
8983 my_getExpression (&imm_expr
, s
);
8984 check_absolute_expr (ip
, &imm_expr
);
8985 if (imm_expr
.X_add_number
& ~OP_MASK_SA3
)
8987 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8988 OP_MASK_SA3
, (unsigned long) imm_expr
.X_add_number
);
8990 INSERT_OPERAND (SA3
, *ip
, imm_expr
.X_add_number
);
8991 imm_expr
.X_op
= O_absent
;
8995 case '4': /* DSP 4-bit unsigned immediate in bit 21. */
8996 my_getExpression (&imm_expr
, s
);
8997 check_absolute_expr (ip
, &imm_expr
);
8998 if (imm_expr
.X_add_number
& ~OP_MASK_SA4
)
9000 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
9001 OP_MASK_SA4
, (unsigned long) imm_expr
.X_add_number
);
9003 INSERT_OPERAND (SA4
, *ip
, imm_expr
.X_add_number
);
9004 imm_expr
.X_op
= O_absent
;
9008 case '5': /* DSP 8-bit unsigned immediate in bit 16. */
9009 my_getExpression (&imm_expr
, s
);
9010 check_absolute_expr (ip
, &imm_expr
);
9011 if (imm_expr
.X_add_number
& ~OP_MASK_IMM8
)
9013 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
9014 OP_MASK_IMM8
, (unsigned long) imm_expr
.X_add_number
);
9016 INSERT_OPERAND (IMM8
, *ip
, imm_expr
.X_add_number
);
9017 imm_expr
.X_op
= O_absent
;
9021 case '6': /* DSP 5-bit unsigned immediate in bit 21. */
9022 my_getExpression (&imm_expr
, s
);
9023 check_absolute_expr (ip
, &imm_expr
);
9024 if (imm_expr
.X_add_number
& ~OP_MASK_RS
)
9026 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
9027 OP_MASK_RS
, (unsigned long) imm_expr
.X_add_number
);
9029 INSERT_OPERAND (RS
, *ip
, imm_expr
.X_add_number
);
9030 imm_expr
.X_op
= O_absent
;
9034 case '7': /* Four DSP accumulators in bits 11,12. */
9035 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
9036 s
[3] >= '0' && s
[3] <= '3')
9040 INSERT_OPERAND (DSPACC
, *ip
, regno
);
9044 as_bad (_("Invalid dsp acc register"));
9047 case '8': /* DSP 6-bit unsigned immediate in bit 11. */
9048 my_getExpression (&imm_expr
, s
);
9049 check_absolute_expr (ip
, &imm_expr
);
9050 if (imm_expr
.X_add_number
& ~OP_MASK_WRDSP
)
9052 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
9054 (unsigned long) imm_expr
.X_add_number
);
9056 INSERT_OPERAND (WRDSP
, *ip
, imm_expr
.X_add_number
);
9057 imm_expr
.X_op
= O_absent
;
9061 case '9': /* Four DSP accumulators in bits 21,22. */
9062 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
9063 s
[3] >= '0' && s
[3] <= '3')
9067 INSERT_OPERAND (DSPACC_S
, *ip
, regno
);
9071 as_bad (_("Invalid dsp acc register"));
9074 case '0': /* DSP 6-bit signed immediate in bit 20. */
9075 my_getExpression (&imm_expr
, s
);
9076 check_absolute_expr (ip
, &imm_expr
);
9077 min_range
= -((OP_MASK_DSPSFT
+ 1) >> 1);
9078 max_range
= ((OP_MASK_DSPSFT
+ 1) >> 1) - 1;
9079 if (imm_expr
.X_add_number
< min_range
||
9080 imm_expr
.X_add_number
> max_range
)
9082 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
9083 (long) min_range
, (long) max_range
,
9084 (long) imm_expr
.X_add_number
);
9086 INSERT_OPERAND (DSPSFT
, *ip
, imm_expr
.X_add_number
);
9087 imm_expr
.X_op
= O_absent
;
9091 case '\'': /* DSP 6-bit unsigned immediate in bit 16. */
9092 my_getExpression (&imm_expr
, s
);
9093 check_absolute_expr (ip
, &imm_expr
);
9094 if (imm_expr
.X_add_number
& ~OP_MASK_RDDSP
)
9096 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
9098 (unsigned long) imm_expr
.X_add_number
);
9100 INSERT_OPERAND (RDDSP
, *ip
, imm_expr
.X_add_number
);
9101 imm_expr
.X_op
= O_absent
;
9105 case ':': /* DSP 7-bit signed immediate in bit 19. */
9106 my_getExpression (&imm_expr
, s
);
9107 check_absolute_expr (ip
, &imm_expr
);
9108 min_range
= -((OP_MASK_DSPSFT_7
+ 1) >> 1);
9109 max_range
= ((OP_MASK_DSPSFT_7
+ 1) >> 1) - 1;
9110 if (imm_expr
.X_add_number
< min_range
||
9111 imm_expr
.X_add_number
> max_range
)
9113 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
9114 (long) min_range
, (long) max_range
,
9115 (long) imm_expr
.X_add_number
);
9117 INSERT_OPERAND (DSPSFT_7
, *ip
, imm_expr
.X_add_number
);
9118 imm_expr
.X_op
= O_absent
;
9122 case '@': /* DSP 10-bit signed immediate in bit 16. */
9123 my_getExpression (&imm_expr
, s
);
9124 check_absolute_expr (ip
, &imm_expr
);
9125 min_range
= -((OP_MASK_IMM10
+ 1) >> 1);
9126 max_range
= ((OP_MASK_IMM10
+ 1) >> 1) - 1;
9127 if (imm_expr
.X_add_number
< min_range
||
9128 imm_expr
.X_add_number
> max_range
)
9130 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
9131 (long) min_range
, (long) max_range
,
9132 (long) imm_expr
.X_add_number
);
9134 INSERT_OPERAND (IMM10
, *ip
, imm_expr
.X_add_number
);
9135 imm_expr
.X_op
= O_absent
;
9139 case '!': /* MT usermode flag bit. */
9140 my_getExpression (&imm_expr
, s
);
9141 check_absolute_expr (ip
, &imm_expr
);
9142 if (imm_expr
.X_add_number
& ~OP_MASK_MT_U
)
9143 as_bad (_("MT usermode bit not 0 or 1 (%lu)"),
9144 (unsigned long) imm_expr
.X_add_number
);
9145 INSERT_OPERAND (MT_U
, *ip
, imm_expr
.X_add_number
);
9146 imm_expr
.X_op
= O_absent
;
9150 case '$': /* MT load high flag bit. */
9151 my_getExpression (&imm_expr
, s
);
9152 check_absolute_expr (ip
, &imm_expr
);
9153 if (imm_expr
.X_add_number
& ~OP_MASK_MT_H
)
9154 as_bad (_("MT load high bit not 0 or 1 (%lu)"),
9155 (unsigned long) imm_expr
.X_add_number
);
9156 INSERT_OPERAND (MT_H
, *ip
, imm_expr
.X_add_number
);
9157 imm_expr
.X_op
= O_absent
;
9161 case '*': /* Four DSP accumulators in bits 18,19. */
9162 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
9163 s
[3] >= '0' && s
[3] <= '3')
9167 INSERT_OPERAND (MTACC_T
, *ip
, regno
);
9171 as_bad (_("Invalid dsp/smartmips acc register"));
9174 case '&': /* Four DSP accumulators in bits 13,14. */
9175 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
9176 s
[3] >= '0' && s
[3] <= '3')
9180 INSERT_OPERAND (MTACC_D
, *ip
, regno
);
9184 as_bad (_("Invalid dsp/smartmips acc register"));
9196 INSERT_OPERAND (RS
, *ip
, lastregno
);
9200 INSERT_OPERAND (RT
, *ip
, lastregno
);
9204 INSERT_OPERAND (FT
, *ip
, lastregno
);
9208 INSERT_OPERAND (FS
, *ip
, lastregno
);
9214 /* Handle optional base register.
9215 Either the base register is omitted or
9216 we must have a left paren. */
9217 /* This is dependent on the next operand specifier
9218 is a base register specification. */
9219 gas_assert (args
[1] == 'b');
9223 case ')': /* These must match exactly. */
9230 case '+': /* Opcode extension character. */
9233 case '1': /* UDI immediates. */
9238 const struct mips_immed
*imm
= mips_immed
;
9240 while (imm
->type
&& imm
->type
!= *args
)
9244 my_getExpression (&imm_expr
, s
);
9245 check_absolute_expr (ip
, &imm_expr
);
9246 if ((unsigned long) imm_expr
.X_add_number
& ~imm
->mask
)
9248 as_warn (_("Illegal %s number (%lu, 0x%lx)"),
9249 imm
->desc
? imm
->desc
: ip
->insn_mo
->name
,
9250 (unsigned long) imm_expr
.X_add_number
,
9251 (unsigned long) imm_expr
.X_add_number
);
9252 imm_expr
.X_add_number
&= imm
->mask
;
9254 ip
->insn_opcode
|= ((unsigned long) imm_expr
.X_add_number
9256 imm_expr
.X_op
= O_absent
;
9261 case 'A': /* ins/ext position, becomes LSB. */
9270 my_getExpression (&imm_expr
, s
);
9271 check_absolute_expr (ip
, &imm_expr
);
9272 if ((unsigned long) imm_expr
.X_add_number
< limlo
9273 || (unsigned long) imm_expr
.X_add_number
> limhi
)
9275 as_bad (_("Improper position (%lu)"),
9276 (unsigned long) imm_expr
.X_add_number
);
9277 imm_expr
.X_add_number
= limlo
;
9279 lastpos
= imm_expr
.X_add_number
;
9280 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
.X_add_number
);
9281 imm_expr
.X_op
= O_absent
;
9285 case 'B': /* ins size, becomes MSB. */
9294 my_getExpression (&imm_expr
, s
);
9295 check_absolute_expr (ip
, &imm_expr
);
9296 /* Check for negative input so that small negative numbers
9297 will not succeed incorrectly. The checks against
9298 (pos+size) transitively check "size" itself,
9299 assuming that "pos" is reasonable. */
9300 if ((long) imm_expr
.X_add_number
< 0
9301 || ((unsigned long) imm_expr
.X_add_number
9303 || ((unsigned long) imm_expr
.X_add_number
9306 as_bad (_("Improper insert size (%lu, position %lu)"),
9307 (unsigned long) imm_expr
.X_add_number
,
9308 (unsigned long) lastpos
);
9309 imm_expr
.X_add_number
= limlo
- lastpos
;
9311 INSERT_OPERAND (INSMSB
, *ip
,
9312 lastpos
+ imm_expr
.X_add_number
- 1);
9313 imm_expr
.X_op
= O_absent
;
9317 case 'C': /* ext size, becomes MSBD. */
9330 my_getExpression (&imm_expr
, s
);
9331 check_absolute_expr (ip
, &imm_expr
);
9332 /* Check for negative input so that small negative numbers
9333 will not succeed incorrectly. The checks against
9334 (pos+size) transitively check "size" itself,
9335 assuming that "pos" is reasonable. */
9336 if ((long) imm_expr
.X_add_number
< 0
9337 || ((unsigned long) imm_expr
.X_add_number
9339 || ((unsigned long) imm_expr
.X_add_number
9342 as_bad (_("Improper extract size (%lu, position %lu)"),
9343 (unsigned long) imm_expr
.X_add_number
,
9344 (unsigned long) lastpos
);
9345 imm_expr
.X_add_number
= limlo
- lastpos
;
9347 INSERT_OPERAND (EXTMSBD
, *ip
, imm_expr
.X_add_number
- 1);
9348 imm_expr
.X_op
= O_absent
;
9353 /* +D is for disassembly only; never match. */
9357 /* "+I" is like "I", except that imm2_expr is used. */
9358 my_getExpression (&imm2_expr
, s
);
9359 if (imm2_expr
.X_op
!= O_big
9360 && imm2_expr
.X_op
!= O_constant
)
9361 insn_error
= _("absolute expression required");
9362 if (HAVE_32BIT_GPRS
)
9363 normalize_constant_expr (&imm2_expr
);
9367 case 'T': /* Coprocessor register. */
9368 /* +T is for disassembly only; never match. */
9371 case 't': /* Coprocessor register number. */
9372 if (s
[0] == '$' && ISDIGIT (s
[1]))
9382 while (ISDIGIT (*s
));
9384 as_bad (_("Invalid register number (%d)"), regno
);
9387 INSERT_OPERAND (RT
, *ip
, regno
);
9392 as_bad (_("Invalid coprocessor 0 register number"));
9396 /* bbit[01] and bbit[01]32 bit index. Give error if index
9397 is not in the valid range. */
9398 my_getExpression (&imm_expr
, s
);
9399 check_absolute_expr (ip
, &imm_expr
);
9400 if ((unsigned) imm_expr
.X_add_number
> 31)
9402 as_bad (_("Improper bit index (%lu)"),
9403 (unsigned long) imm_expr
.X_add_number
);
9404 imm_expr
.X_add_number
= 0;
9406 INSERT_OPERAND (BBITIND
, *ip
, imm_expr
.X_add_number
);
9407 imm_expr
.X_op
= O_absent
;
9412 /* bbit[01] bit index when bbit is used but we generate
9413 bbit[01]32 because the index is over 32. Move to the
9414 next candidate if index is not in the valid range. */
9415 my_getExpression (&imm_expr
, s
);
9416 check_absolute_expr (ip
, &imm_expr
);
9417 if ((unsigned) imm_expr
.X_add_number
< 32
9418 || (unsigned) imm_expr
.X_add_number
> 63)
9420 INSERT_OPERAND (BBITIND
, *ip
, imm_expr
.X_add_number
- 32);
9421 imm_expr
.X_op
= O_absent
;
9426 /* cins, cins32, exts and exts32 position field. Give error
9427 if it's not in the valid range. */
9428 my_getExpression (&imm_expr
, s
);
9429 check_absolute_expr (ip
, &imm_expr
);
9430 if ((unsigned) imm_expr
.X_add_number
> 31)
9432 as_bad (_("Improper position (%lu)"),
9433 (unsigned long) imm_expr
.X_add_number
);
9434 imm_expr
.X_add_number
= 0;
9436 /* Make the pos explicit to simplify +S. */
9437 lastpos
= imm_expr
.X_add_number
+ 32;
9438 INSERT_OPERAND (CINSPOS
, *ip
, imm_expr
.X_add_number
);
9439 imm_expr
.X_op
= O_absent
;
9444 /* cins, cins32, exts and exts32 position field. Move to
9445 the next candidate if it's not in the valid range. */
9446 my_getExpression (&imm_expr
, s
);
9447 check_absolute_expr (ip
, &imm_expr
);
9448 if ((unsigned) imm_expr
.X_add_number
< 32
9449 || (unsigned) imm_expr
.X_add_number
> 63)
9451 lastpos
= imm_expr
.X_add_number
;
9452 INSERT_OPERAND (CINSPOS
, *ip
, imm_expr
.X_add_number
- 32);
9453 imm_expr
.X_op
= O_absent
;
9458 /* cins and exts length-minus-one field. */
9459 my_getExpression (&imm_expr
, s
);
9460 check_absolute_expr (ip
, &imm_expr
);
9461 if ((unsigned long) imm_expr
.X_add_number
> 31)
9463 as_bad (_("Improper size (%lu)"),
9464 (unsigned long) imm_expr
.X_add_number
);
9465 imm_expr
.X_add_number
= 0;
9467 INSERT_OPERAND (CINSLM1
, *ip
, imm_expr
.X_add_number
);
9468 imm_expr
.X_op
= O_absent
;
9473 /* cins32/exts32 and cins/exts aliasing cint32/exts32
9474 length-minus-one field. */
9475 my_getExpression (&imm_expr
, s
);
9476 check_absolute_expr (ip
, &imm_expr
);
9477 if ((long) imm_expr
.X_add_number
< 0
9478 || (unsigned long) imm_expr
.X_add_number
+ lastpos
> 63)
9480 as_bad (_("Improper size (%lu)"),
9481 (unsigned long) imm_expr
.X_add_number
);
9482 imm_expr
.X_add_number
= 0;
9484 INSERT_OPERAND (CINSLM1
, *ip
, imm_expr
.X_add_number
);
9485 imm_expr
.X_op
= O_absent
;
9490 /* seqi/snei immediate field. */
9491 my_getExpression (&imm_expr
, s
);
9492 check_absolute_expr (ip
, &imm_expr
);
9493 if ((long) imm_expr
.X_add_number
< -512
9494 || (long) imm_expr
.X_add_number
>= 512)
9496 as_bad (_("Improper immediate (%ld)"),
9497 (long) imm_expr
.X_add_number
);
9498 imm_expr
.X_add_number
= 0;
9500 INSERT_OPERAND (SEQI
, *ip
, imm_expr
.X_add_number
);
9501 imm_expr
.X_op
= O_absent
;
9505 case 'a': /* 8-bit signed offset in bit 6 */
9506 my_getExpression (&imm_expr
, s
);
9507 check_absolute_expr (ip
, &imm_expr
);
9508 min_range
= -((OP_MASK_OFFSET_A
+ 1) >> 1);
9509 max_range
= ((OP_MASK_OFFSET_A
+ 1) >> 1) - 1;
9510 if (imm_expr
.X_add_number
< min_range
9511 || imm_expr
.X_add_number
> max_range
)
9513 as_bad (_("Offset not in range %ld..%ld (%ld)"),
9514 (long) min_range
, (long) max_range
,
9515 (long) imm_expr
.X_add_number
);
9517 INSERT_OPERAND (OFFSET_A
, *ip
, imm_expr
.X_add_number
);
9518 imm_expr
.X_op
= O_absent
;
9522 case 'b': /* 8-bit signed offset in bit 3 */
9523 my_getExpression (&imm_expr
, s
);
9524 check_absolute_expr (ip
, &imm_expr
);
9525 min_range
= -((OP_MASK_OFFSET_B
+ 1) >> 1);
9526 max_range
= ((OP_MASK_OFFSET_B
+ 1) >> 1) - 1;
9527 if (imm_expr
.X_add_number
< min_range
9528 || imm_expr
.X_add_number
> max_range
)
9530 as_bad (_("Offset not in range %ld..%ld (%ld)"),
9531 (long) min_range
, (long) max_range
,
9532 (long) imm_expr
.X_add_number
);
9534 INSERT_OPERAND (OFFSET_B
, *ip
, imm_expr
.X_add_number
);
9535 imm_expr
.X_op
= O_absent
;
9539 case 'c': /* 9-bit signed offset in bit 6 */
9540 my_getExpression (&imm_expr
, s
);
9541 check_absolute_expr (ip
, &imm_expr
);
9542 min_range
= -((OP_MASK_OFFSET_C
+ 1) >> 1);
9543 max_range
= ((OP_MASK_OFFSET_C
+ 1) >> 1) - 1;
9544 /* We check the offset range before adjusted. */
9547 if (imm_expr
.X_add_number
< min_range
9548 || imm_expr
.X_add_number
> max_range
)
9550 as_bad (_("Offset not in range %ld..%ld (%ld)"),
9551 (long) min_range
, (long) max_range
,
9552 (long) imm_expr
.X_add_number
);
9554 if (imm_expr
.X_add_number
& 0xf)
9556 as_bad (_("Offset not 16 bytes alignment (%ld)"),
9557 (long) imm_expr
.X_add_number
);
9559 /* Right shift 4 bits to adjust the offset operand. */
9560 INSERT_OPERAND (OFFSET_C
, *ip
, imm_expr
.X_add_number
>> 4);
9561 imm_expr
.X_op
= O_absent
;
9566 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
))
9568 if (regno
== AT
&& mips_opts
.at
)
9570 if (mips_opts
.at
== ATREG
)
9571 as_warn (_("used $at without \".set noat\""));
9573 as_warn (_("used $%u with \".set at=$%u\""),
9574 regno
, mips_opts
.at
);
9576 INSERT_OPERAND (RZ
, *ip
, regno
);
9580 if (!reg_lookup (&s
, RTYPE_FPU
, ®no
))
9582 INSERT_OPERAND (FZ
, *ip
, regno
);
9586 as_bad (_("Internal error: bad mips opcode "
9587 "(unknown extension operand type `+%c'): %s %s"),
9588 *args
, insn
->name
, insn
->args
);
9589 /* Further processing is fruitless. */
9594 case '<': /* must be at least one digit */
9596 * According to the manual, if the shift amount is greater
9597 * than 31 or less than 0, then the shift amount should be
9598 * mod 32. In reality the mips assembler issues an error.
9599 * We issue a warning and mask out all but the low 5 bits.
9601 my_getExpression (&imm_expr
, s
);
9602 check_absolute_expr (ip
, &imm_expr
);
9603 if ((unsigned long) imm_expr
.X_add_number
> 31)
9604 as_warn (_("Improper shift amount (%lu)"),
9605 (unsigned long) imm_expr
.X_add_number
);
9606 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
.X_add_number
);
9607 imm_expr
.X_op
= O_absent
;
9611 case '>': /* shift amount minus 32 */
9612 my_getExpression (&imm_expr
, s
);
9613 check_absolute_expr (ip
, &imm_expr
);
9614 if ((unsigned long) imm_expr
.X_add_number
< 32
9615 || (unsigned long) imm_expr
.X_add_number
> 63)
9617 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
.X_add_number
- 32);
9618 imm_expr
.X_op
= O_absent
;
9622 case 'k': /* CACHE code. */
9623 case 'h': /* PREFX code. */
9624 case '1': /* SYNC type. */
9625 my_getExpression (&imm_expr
, s
);
9626 check_absolute_expr (ip
, &imm_expr
);
9627 if ((unsigned long) imm_expr
.X_add_number
> 31)
9628 as_warn (_("Invalid value for `%s' (%lu)"),
9630 (unsigned long) imm_expr
.X_add_number
);
9633 if (mips_fix_cn63xxp1
&& strcmp ("pref", insn
->name
) == 0)
9634 switch (imm_expr
.X_add_number
)
9643 case 31: /* These are ok. */
9646 default: /* The rest must be changed to 28. */
9647 imm_expr
.X_add_number
= 28;
9650 INSERT_OPERAND (CACHE
, *ip
, imm_expr
.X_add_number
);
9652 else if (*args
== 'h')
9653 INSERT_OPERAND (PREFX
, *ip
, imm_expr
.X_add_number
);
9655 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
.X_add_number
);
9656 imm_expr
.X_op
= O_absent
;
9660 case 'c': /* BREAK code. */
9661 my_getExpression (&imm_expr
, s
);
9662 check_absolute_expr (ip
, &imm_expr
);
9663 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE
)
9664 as_warn (_("Code for %s not in range 0..1023 (%lu)"),
9666 (unsigned long) imm_expr
.X_add_number
);
9667 INSERT_OPERAND (CODE
, *ip
, imm_expr
.X_add_number
);
9668 imm_expr
.X_op
= O_absent
;
9672 case 'q': /* Lower BREAK code. */
9673 my_getExpression (&imm_expr
, s
);
9674 check_absolute_expr (ip
, &imm_expr
);
9675 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE2
)
9676 as_warn (_("Lower code for %s not in range 0..1023 (%lu)"),
9678 (unsigned long) imm_expr
.X_add_number
);
9679 INSERT_OPERAND (CODE2
, *ip
, imm_expr
.X_add_number
);
9680 imm_expr
.X_op
= O_absent
;
9684 case 'B': /* 20-bit SYSCALL/BREAK code. */
9685 my_getExpression (&imm_expr
, s
);
9686 check_absolute_expr (ip
, &imm_expr
);
9687 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE20
)
9688 as_warn (_("Code for %s not in range 0..1048575 (%lu)"),
9690 (unsigned long) imm_expr
.X_add_number
);
9691 INSERT_OPERAND (CODE20
, *ip
, imm_expr
.X_add_number
);
9692 imm_expr
.X_op
= O_absent
;
9696 case 'C': /* Coprocessor code. */
9697 my_getExpression (&imm_expr
, s
);
9698 check_absolute_expr (ip
, &imm_expr
);
9699 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_COPZ
)
9701 as_warn (_("Coproccesor code > 25 bits (%lu)"),
9702 (unsigned long) imm_expr
.X_add_number
);
9703 imm_expr
.X_add_number
&= OP_MASK_COPZ
;
9705 INSERT_OPERAND (COPZ
, *ip
, imm_expr
.X_add_number
);
9706 imm_expr
.X_op
= O_absent
;
9710 case 'J': /* 19-bit WAIT code. */
9711 my_getExpression (&imm_expr
, s
);
9712 check_absolute_expr (ip
, &imm_expr
);
9713 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE19
)
9715 as_warn (_("Illegal 19-bit code (%lu)"),
9716 (unsigned long) imm_expr
.X_add_number
);
9717 imm_expr
.X_add_number
&= OP_MASK_CODE19
;
9719 INSERT_OPERAND (CODE19
, *ip
, imm_expr
.X_add_number
);
9720 imm_expr
.X_op
= O_absent
;
9724 case 'P': /* Performance register. */
9725 my_getExpression (&imm_expr
, s
);
9726 check_absolute_expr (ip
, &imm_expr
);
9727 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
9728 as_warn (_("Invalid performance register (%lu)"),
9729 (unsigned long) imm_expr
.X_add_number
);
9730 INSERT_OPERAND (PERFREG
, *ip
, imm_expr
.X_add_number
);
9731 imm_expr
.X_op
= O_absent
;
9735 case 'G': /* Coprocessor destination register. */
9736 if (((ip
->insn_opcode
>> OP_SH_OP
) & OP_MASK_OP
) == OP_OP_COP0
)
9737 ok
= reg_lookup (&s
, RTYPE_NUM
| RTYPE_CP0
, ®no
);
9739 ok
= reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
);
9740 INSERT_OPERAND (RD
, *ip
, regno
);
9749 case 'b': /* Base register. */
9750 case 'd': /* Destination register. */
9751 case 's': /* Source register. */
9752 case 't': /* Target register. */
9753 case 'r': /* Both target and source. */
9754 case 'v': /* Both dest and source. */
9755 case 'w': /* Both dest and target. */
9756 case 'E': /* Coprocessor target register. */
9757 case 'K': /* RDHWR destination register. */
9758 case 'x': /* Ignore register name. */
9759 case 'z': /* Must be zero register. */
9760 case 'U': /* Destination register (CLO/CLZ). */
9761 case 'g': /* Coprocessor destination register. */
9763 if (*args
== 'E' || *args
== 'K')
9764 ok
= reg_lookup (&s
, RTYPE_NUM
, ®no
);
9767 ok
= reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
);
9768 if (regno
== AT
&& mips_opts
.at
)
9770 if (mips_opts
.at
== ATREG
)
9771 as_warn (_("Used $at without \".set noat\""));
9773 as_warn (_("Used $%u with \".set at=$%u\""),
9774 regno
, mips_opts
.at
);
9784 if (c
== 'r' || c
== 'v' || c
== 'w')
9791 /* 'z' only matches $0. */
9792 if (c
== 'z' && regno
!= 0)
9795 if (c
== 's' && !strncmp (ip
->insn_mo
->name
, "jalr", 4))
9797 if (regno
== lastregno
)
9800 = _("Source and destination must be different");
9803 if (regno
== 31 && lastregno
== 0xffffffff)
9806 = _("A destination register must be supplied");
9810 /* Now that we have assembled one operand, we use the args
9811 string to figure out where it goes in the instruction. */
9818 INSERT_OPERAND (RS
, *ip
, regno
);
9823 INSERT_OPERAND (RD
, *ip
, regno
);
9826 INSERT_OPERAND (RD
, *ip
, regno
);
9827 INSERT_OPERAND (RT
, *ip
, regno
);
9832 INSERT_OPERAND (RT
, *ip
, regno
);
9835 /* This case exists because on the r3000 trunc
9836 expands into a macro which requires a gp
9837 register. On the r6000 or r4000 it is
9838 assembled into a single instruction which
9839 ignores the register. Thus the insn version
9840 is MIPS_ISA2 and uses 'x', and the macro
9841 version is MIPS_ISA1 and uses 't'. */
9844 /* This case is for the div instruction, which
9845 acts differently if the destination argument
9846 is $0. This only matches $0, and is checked
9847 outside the switch. */
9857 INSERT_OPERAND (RS
, *ip
, lastregno
);
9860 INSERT_OPERAND (RT
, *ip
, lastregno
);
9865 case 'O': /* MDMX alignment immediate constant. */
9866 my_getExpression (&imm_expr
, s
);
9867 check_absolute_expr (ip
, &imm_expr
);
9868 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_ALN
)
9869 as_warn (_("Improper align amount (%ld), using low bits"),
9870 (long) imm_expr
.X_add_number
);
9871 INSERT_OPERAND (ALN
, *ip
, imm_expr
.X_add_number
);
9872 imm_expr
.X_op
= O_absent
;
9876 case 'Q': /* MDMX vector, element sel, or const. */
9879 /* MDMX Immediate. */
9880 my_getExpression (&imm_expr
, s
);
9881 check_absolute_expr (ip
, &imm_expr
);
9882 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_FT
)
9883 as_warn (_("Invalid MDMX Immediate (%ld)"),
9884 (long) imm_expr
.X_add_number
);
9885 INSERT_OPERAND (FT
, *ip
, imm_expr
.X_add_number
);
9886 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
9887 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_QH
<< OP_SH_VSEL
;
9889 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_OB
<< OP_SH_VSEL
;
9890 imm_expr
.X_op
= O_absent
;
9894 /* Not MDMX Immediate. Fall through. */
9895 case 'X': /* MDMX destination register. */
9896 case 'Y': /* MDMX source register. */
9897 case 'Z': /* MDMX target register. */
9899 case 'D': /* Floating point destination register. */
9900 case 'S': /* Floating point source register. */
9901 case 'T': /* Floating point target register. */
9902 case 'R': /* Floating point source register. */
9907 || (mips_opts
.ase_mdmx
9908 && (ip
->insn_mo
->pinfo
& FP_D
)
9909 && (ip
->insn_mo
->pinfo
& (INSN_COPROC_MOVE_DELAY
9910 | INSN_COPROC_MEMORY_DELAY
9911 | INSN_LOAD_COPROC_DELAY
9912 | INSN_LOAD_MEMORY_DELAY
9913 | INSN_STORE_MEMORY
))))
9916 if (reg_lookup (&s
, rtype
, ®no
))
9918 if ((regno
& 1) != 0
9920 && !mips_oddfpreg_ok (ip
->insn_mo
, argnum
))
9921 as_warn (_("Float register should be even, was %d"),
9929 if (c
== 'V' || c
== 'W')
9940 INSERT_OPERAND (FD
, *ip
, regno
);
9945 INSERT_OPERAND (FS
, *ip
, regno
);
9948 /* This is like 'Z', but also needs to fix the MDMX
9949 vector/scalar select bits. Note that the
9950 scalar immediate case is handled above. */
9953 int is_qh
= (ip
->insn_opcode
& (1 << OP_SH_VSEL
));
9954 int max_el
= (is_qh
? 3 : 7);
9956 my_getExpression(&imm_expr
, s
);
9957 check_absolute_expr (ip
, &imm_expr
);
9959 if (imm_expr
.X_add_number
> max_el
)
9960 as_bad (_("Bad element selector %ld"),
9961 (long) imm_expr
.X_add_number
);
9962 imm_expr
.X_add_number
&= max_el
;
9963 ip
->insn_opcode
|= (imm_expr
.X_add_number
9966 imm_expr
.X_op
= O_absent
;
9968 as_warn (_("Expecting ']' found '%s'"), s
);
9974 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
9975 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_QH
9978 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_OB
<<
9985 INSERT_OPERAND (FT
, *ip
, regno
);
9988 INSERT_OPERAND (FR
, *ip
, regno
);
9998 INSERT_OPERAND (FS
, *ip
, lastregno
);
10001 INSERT_OPERAND (FT
, *ip
, lastregno
);
10007 my_getExpression (&imm_expr
, s
);
10008 if (imm_expr
.X_op
!= O_big
10009 && imm_expr
.X_op
!= O_constant
)
10010 insn_error
= _("absolute expression required");
10011 if (HAVE_32BIT_GPRS
)
10012 normalize_constant_expr (&imm_expr
);
10017 my_getExpression (&offset_expr
, s
);
10018 normalize_address_expr (&offset_expr
);
10019 *imm_reloc
= BFD_RELOC_32
;
10032 unsigned char temp
[8];
10034 unsigned int length
;
10039 /* These only appear as the last operand in an
10040 instruction, and every instruction that accepts
10041 them in any variant accepts them in all variants.
10042 This means we don't have to worry about backing out
10043 any changes if the instruction does not match.
10045 The difference between them is the size of the
10046 floating point constant and where it goes. For 'F'
10047 and 'L' the constant is 64 bits; for 'f' and 'l' it
10048 is 32 bits. Where the constant is placed is based
10049 on how the MIPS assembler does things:
10052 f -- immediate value
10055 The .lit4 and .lit8 sections are only used if
10056 permitted by the -G argument.
10058 The code below needs to know whether the target register
10059 is 32 or 64 bits wide. It relies on the fact 'f' and
10060 'F' are used with GPR-based instructions and 'l' and
10061 'L' are used with FPR-based instructions. */
10063 f64
= *args
== 'F' || *args
== 'L';
10064 using_gprs
= *args
== 'F' || *args
== 'f';
10066 save_in
= input_line_pointer
;
10067 input_line_pointer
= s
;
10068 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
10070 s
= input_line_pointer
;
10071 input_line_pointer
= save_in
;
10072 if (err
!= NULL
&& *err
!= '\0')
10074 as_bad (_("Bad floating point constant: %s"), err
);
10075 memset (temp
, '\0', sizeof temp
);
10076 length
= f64
? 8 : 4;
10079 gas_assert (length
== (unsigned) (f64
? 8 : 4));
10083 && (g_switch_value
< 4
10084 || (temp
[0] == 0 && temp
[1] == 0)
10085 || (temp
[2] == 0 && temp
[3] == 0))))
10087 imm_expr
.X_op
= O_constant
;
10088 if (!target_big_endian
)
10089 imm_expr
.X_add_number
= bfd_getl32 (temp
);
10091 imm_expr
.X_add_number
= bfd_getb32 (temp
);
10093 else if (length
> 4
10094 && !mips_disable_float_construction
10095 /* Constants can only be constructed in GPRs and
10096 copied to FPRs if the GPRs are at least as wide
10097 as the FPRs. Force the constant into memory if
10098 we are using 64-bit FPRs but the GPRs are only
10101 || !(HAVE_64BIT_FPRS
&& HAVE_32BIT_GPRS
))
10102 && ((temp
[0] == 0 && temp
[1] == 0)
10103 || (temp
[2] == 0 && temp
[3] == 0))
10104 && ((temp
[4] == 0 && temp
[5] == 0)
10105 || (temp
[6] == 0 && temp
[7] == 0)))
10107 /* The value is simple enough to load with a couple of
10108 instructions. If using 32-bit registers, set
10109 imm_expr to the high order 32 bits and offset_expr to
10110 the low order 32 bits. Otherwise, set imm_expr to
10111 the entire 64 bit constant. */
10112 if (using_gprs
? HAVE_32BIT_GPRS
: HAVE_32BIT_FPRS
)
10114 imm_expr
.X_op
= O_constant
;
10115 offset_expr
.X_op
= O_constant
;
10116 if (!target_big_endian
)
10118 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
10119 offset_expr
.X_add_number
= bfd_getl32 (temp
);
10123 imm_expr
.X_add_number
= bfd_getb32 (temp
);
10124 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
10126 if (offset_expr
.X_add_number
== 0)
10127 offset_expr
.X_op
= O_absent
;
10129 else if (sizeof (imm_expr
.X_add_number
) > 4)
10131 imm_expr
.X_op
= O_constant
;
10132 if (!target_big_endian
)
10133 imm_expr
.X_add_number
= bfd_getl64 (temp
);
10135 imm_expr
.X_add_number
= bfd_getb64 (temp
);
10139 imm_expr
.X_op
= O_big
;
10140 imm_expr
.X_add_number
= 4;
10141 if (!target_big_endian
)
10143 generic_bignum
[0] = bfd_getl16 (temp
);
10144 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
10145 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
10146 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
10150 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
10151 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
10152 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
10153 generic_bignum
[3] = bfd_getb16 (temp
);
10159 const char *newname
;
10162 /* Switch to the right section. */
10164 subseg
= now_subseg
;
10167 default: /* unused default case avoids warnings. */
10169 newname
= RDATA_SECTION_NAME
;
10170 if (g_switch_value
>= 8)
10174 newname
= RDATA_SECTION_NAME
;
10177 gas_assert (g_switch_value
>= 4);
10181 new_seg
= subseg_new (newname
, (subsegT
) 0);
10183 bfd_set_section_flags (stdoutput
, new_seg
,
10188 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
10189 if (IS_ELF
&& strncmp (TARGET_OS
, "elf", 3) != 0)
10190 record_alignment (new_seg
, 4);
10192 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
10193 if (seg
== now_seg
)
10194 as_bad (_("Can't use floating point insn in this section"));
10196 /* Set the argument to the current address in the
10198 offset_expr
.X_op
= O_symbol
;
10199 offset_expr
.X_add_symbol
= symbol_temp_new_now ();
10200 offset_expr
.X_add_number
= 0;
10202 /* Put the floating point number into the section. */
10203 p
= frag_more ((int) length
);
10204 memcpy (p
, temp
, length
);
10206 /* Switch back to the original section. */
10207 subseg_set (seg
, subseg
);
10212 case 'i': /* 16-bit unsigned immediate. */
10213 case 'j': /* 16-bit signed immediate. */
10214 *imm_reloc
= BFD_RELOC_LO16
;
10215 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0)
10218 offsetT minval
, maxval
;
10220 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
10221 && strcmp (insn
->name
, insn
[1].name
) == 0);
10223 /* If the expression was written as an unsigned number,
10224 only treat it as signed if there are no more
10228 && sizeof (imm_expr
.X_add_number
) <= 4
10229 && imm_expr
.X_op
== O_constant
10230 && imm_expr
.X_add_number
< 0
10231 && imm_expr
.X_unsigned
10232 && HAVE_64BIT_GPRS
)
10235 /* For compatibility with older assemblers, we accept
10236 0x8000-0xffff as signed 16-bit numbers when only
10237 signed numbers are allowed. */
10239 minval
= 0, maxval
= 0xffff;
10241 minval
= -0x8000, maxval
= 0x7fff;
10243 minval
= -0x8000, maxval
= 0xffff;
10245 if (imm_expr
.X_op
!= O_constant
10246 || imm_expr
.X_add_number
< minval
10247 || imm_expr
.X_add_number
> maxval
)
10251 if (imm_expr
.X_op
== O_constant
10252 || imm_expr
.X_op
== O_big
)
10253 as_bad (_("Expression out of range"));
10259 case 'o': /* 16-bit offset. */
10260 offset_reloc
[0] = BFD_RELOC_LO16
;
10261 offset_reloc
[1] = BFD_RELOC_UNUSED
;
10262 offset_reloc
[2] = BFD_RELOC_UNUSED
;
10264 /* Check whether there is only a single bracketed expression
10265 left. If so, it must be the base register and the
10266 constant must be zero. */
10267 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
10269 offset_expr
.X_op
= O_constant
;
10270 offset_expr
.X_add_number
= 0;
10274 /* If this value won't fit into a 16 bit offset, then go
10275 find a macro that will generate the 32 bit offset
10277 if (my_getSmallExpression (&offset_expr
, offset_reloc
, s
) == 0
10278 && (offset_expr
.X_op
!= O_constant
10279 || offset_expr
.X_add_number
>= 0x8000
10280 || offset_expr
.X_add_number
< -0x8000))
10286 case 'p': /* PC-relative offset. */
10287 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
10288 my_getExpression (&offset_expr
, s
);
10292 case 'u': /* Upper 16 bits. */
10293 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0
10294 && imm_expr
.X_op
== O_constant
10295 && (imm_expr
.X_add_number
< 0
10296 || imm_expr
.X_add_number
>= 0x10000))
10297 as_bad (_("lui expression (%lu) not in range 0..65535"),
10298 (unsigned long) imm_expr
.X_add_number
);
10302 case 'a': /* 26-bit address. */
10303 my_getExpression (&offset_expr
, s
);
10305 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
10308 case 'N': /* 3-bit branch condition code. */
10309 case 'M': /* 3-bit compare condition code. */
10311 if (ip
->insn_mo
->pinfo
& (FP_D
| FP_S
))
10312 rtype
|= RTYPE_FCC
;
10313 if (!reg_lookup (&s
, rtype
, ®no
))
10315 if ((strcmp (str
+ strlen (str
) - 3, ".ps") == 0
10316 || strcmp (str
+ strlen (str
) - 5, "any2f") == 0
10317 || strcmp (str
+ strlen (str
) - 5, "any2t") == 0)
10318 && (regno
& 1) != 0)
10319 as_warn (_("Condition code register should be even for %s, "
10322 if ((strcmp (str
+ strlen (str
) - 5, "any4f") == 0
10323 || strcmp (str
+ strlen (str
) - 5, "any4t") == 0)
10324 && (regno
& 3) != 0)
10325 as_warn (_("Condition code register should be 0 or 4 for %s, "
10329 INSERT_OPERAND (BCC
, *ip
, regno
);
10331 INSERT_OPERAND (CCC
, *ip
, regno
);
10335 if (s
[0] == '0' && (s
[1] == 'x' || s
[1] == 'X'))
10346 while (ISDIGIT (*s
));
10349 c
= 8; /* Invalid sel value. */
10352 as_bad (_("Invalid coprocessor sub-selection value (0-7)"));
10353 ip
->insn_opcode
|= c
;
10357 /* Must be at least one digit. */
10358 my_getExpression (&imm_expr
, s
);
10359 check_absolute_expr (ip
, &imm_expr
);
10361 if ((unsigned long) imm_expr
.X_add_number
10362 > (unsigned long) OP_MASK_VECBYTE
)
10364 as_bad (_("bad byte vector index (%ld)"),
10365 (long) imm_expr
.X_add_number
);
10366 imm_expr
.X_add_number
= 0;
10369 INSERT_OPERAND (VECBYTE
, *ip
, imm_expr
.X_add_number
);
10370 imm_expr
.X_op
= O_absent
;
10375 my_getExpression (&imm_expr
, s
);
10376 check_absolute_expr (ip
, &imm_expr
);
10378 if ((unsigned long) imm_expr
.X_add_number
10379 > (unsigned long) OP_MASK_VECALIGN
)
10381 as_bad (_("bad byte vector index (%ld)"),
10382 (long) imm_expr
.X_add_number
);
10383 imm_expr
.X_add_number
= 0;
10386 INSERT_OPERAND (VECALIGN
, *ip
, imm_expr
.X_add_number
);
10387 imm_expr
.X_op
= O_absent
;
10392 as_bad (_("Bad char = '%c'\n"), *args
);
10397 /* Args don't match. */
10398 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
10399 !strcmp (insn
->name
, insn
[1].name
))
10403 insn_error
= _("Illegal operands");
10407 *(--argsStart
) = save_c
;
10408 insn_error
= _("Illegal operands");
10413 #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); }
10415 /* This routine assembles an instruction into its binary format when
10416 assembling for the mips16. As a side effect, it sets one of the
10417 global variables imm_reloc or offset_reloc to the type of
10418 relocation to do if one of the operands is an address expression.
10419 It also sets mips16_small and mips16_ext if the user explicitly
10420 requested a small or extended instruction. */
10423 mips16_ip (char *str
, struct mips_cl_insn
*ip
)
10427 struct mips_opcode
*insn
;
10429 unsigned int regno
;
10430 unsigned int lastregno
= 0;
10436 mips16_small
= FALSE
;
10437 mips16_ext
= FALSE
;
10439 for (s
= str
; ISLOWER (*s
); ++s
)
10451 if (s
[1] == 't' && s
[2] == ' ')
10454 mips16_small
= TRUE
;
10458 else if (s
[1] == 'e' && s
[2] == ' ')
10465 /* Fall through. */
10467 insn_error
= _("unknown opcode");
10471 if (mips_opts
.noautoextend
&& ! mips16_ext
)
10472 mips16_small
= TRUE
;
10474 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
10476 insn_error
= _("unrecognized opcode");
10485 gas_assert (strcmp (insn
->name
, str
) == 0);
10487 ok
= is_opcode_valid_16 (insn
);
10490 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
]
10491 && strcmp (insn
->name
, insn
[1].name
) == 0)
10500 static char buf
[100];
10502 _("opcode not supported on this processor: %s (%s)"),
10503 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
10504 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
10511 create_insn (ip
, insn
);
10512 imm_expr
.X_op
= O_absent
;
10513 imm_reloc
[0] = BFD_RELOC_UNUSED
;
10514 imm_reloc
[1] = BFD_RELOC_UNUSED
;
10515 imm_reloc
[2] = BFD_RELOC_UNUSED
;
10516 imm2_expr
.X_op
= O_absent
;
10517 offset_expr
.X_op
= O_absent
;
10518 offset_reloc
[0] = BFD_RELOC_UNUSED
;
10519 offset_reloc
[1] = BFD_RELOC_UNUSED
;
10520 offset_reloc
[2] = BFD_RELOC_UNUSED
;
10521 for (args
= insn
->args
; 1; ++args
)
10528 /* In this switch statement we call break if we did not find
10529 a match, continue if we did find a match, or return if we
10538 /* Stuff the immediate value in now, if we can. */
10539 if (imm_expr
.X_op
== O_constant
10540 && *imm_reloc
> BFD_RELOC_UNUSED
10541 && *imm_reloc
!= BFD_RELOC_MIPS16_GOT16
10542 && *imm_reloc
!= BFD_RELOC_MIPS16_CALL16
10543 && insn
->pinfo
!= INSN_MACRO
)
10547 switch (*offset_reloc
)
10549 case BFD_RELOC_MIPS16_HI16_S
:
10550 tmp
= (imm_expr
.X_add_number
+ 0x8000) >> 16;
10553 case BFD_RELOC_MIPS16_HI16
:
10554 tmp
= imm_expr
.X_add_number
>> 16;
10557 case BFD_RELOC_MIPS16_LO16
:
10558 tmp
= ((imm_expr
.X_add_number
+ 0x8000) & 0xffff)
10562 case BFD_RELOC_UNUSED
:
10563 tmp
= imm_expr
.X_add_number
;
10569 *offset_reloc
= BFD_RELOC_UNUSED
;
10571 mips16_immed (NULL
, 0, *imm_reloc
- BFD_RELOC_UNUSED
,
10572 tmp
, TRUE
, mips16_small
,
10573 mips16_ext
, &ip
->insn_opcode
,
10574 &ip
->use_extend
, &ip
->extend
);
10575 imm_expr
.X_op
= O_absent
;
10576 *imm_reloc
= BFD_RELOC_UNUSED
;
10590 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
10593 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
10609 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
10611 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
10615 /* Fall through. */
10626 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
))
10628 if (c
== 'v' || c
== 'w')
10631 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
10633 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
10644 if (c
== 'v' || c
== 'w')
10646 regno
= mips16_to_32_reg_map
[lastregno
];
10660 regno
= mips32_to_16_reg_map
[regno
];
10665 regno
= ILLEGAL_REG
;
10670 regno
= ILLEGAL_REG
;
10675 regno
= ILLEGAL_REG
;
10680 if (regno
== AT
&& mips_opts
.at
)
10682 if (mips_opts
.at
== ATREG
)
10683 as_warn (_("used $at without \".set noat\""));
10685 as_warn (_("used $%u with \".set at=$%u\""),
10686 regno
, mips_opts
.at
);
10694 if (regno
== ILLEGAL_REG
)
10701 MIPS16_INSERT_OPERAND (RX
, *ip
, regno
);
10705 MIPS16_INSERT_OPERAND (RY
, *ip
, regno
);
10708 MIPS16_INSERT_OPERAND (RZ
, *ip
, regno
);
10711 MIPS16_INSERT_OPERAND (MOVE32Z
, *ip
, regno
);
10717 MIPS16_INSERT_OPERAND (REGR32
, *ip
, regno
);
10720 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
10721 MIPS16_INSERT_OPERAND (REG32R
, *ip
, regno
);
10731 if (strncmp (s
, "$pc", 3) == 0)
10748 i
= my_getSmallExpression (&imm_expr
, imm_reloc
, s
);
10751 if (imm_expr
.X_op
!= O_constant
)
10754 ip
->use_extend
= TRUE
;
10759 /* We need to relax this instruction. */
10760 *offset_reloc
= *imm_reloc
;
10761 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
10766 *imm_reloc
= BFD_RELOC_UNUSED
;
10767 /* Fall through. */
10774 my_getExpression (&imm_expr
, s
);
10775 if (imm_expr
.X_op
== O_register
)
10777 /* What we thought was an expression turned out to
10780 if (s
[0] == '(' && args
[1] == '(')
10782 /* It looks like the expression was omitted
10783 before a register indirection, which means
10784 that the expression is implicitly zero. We
10785 still set up imm_expr, so that we handle
10786 explicit extensions correctly. */
10787 imm_expr
.X_op
= O_constant
;
10788 imm_expr
.X_add_number
= 0;
10789 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
10796 /* We need to relax this instruction. */
10797 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
10806 /* We use offset_reloc rather than imm_reloc for the PC
10807 relative operands. This lets macros with both
10808 immediate and address operands work correctly. */
10809 my_getExpression (&offset_expr
, s
);
10811 if (offset_expr
.X_op
== O_register
)
10814 /* We need to relax this instruction. */
10815 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
10819 case '6': /* break code */
10820 my_getExpression (&imm_expr
, s
);
10821 check_absolute_expr (ip
, &imm_expr
);
10822 if ((unsigned long) imm_expr
.X_add_number
> 63)
10823 as_warn (_("Invalid value for `%s' (%lu)"),
10825 (unsigned long) imm_expr
.X_add_number
);
10826 MIPS16_INSERT_OPERAND (IMM6
, *ip
, imm_expr
.X_add_number
);
10827 imm_expr
.X_op
= O_absent
;
10831 case 'a': /* 26 bit address */
10832 my_getExpression (&offset_expr
, s
);
10834 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
10835 ip
->insn_opcode
<<= 16;
10838 case 'l': /* register list for entry macro */
10839 case 'L': /* register list for exit macro */
10849 unsigned int freg
, reg1
, reg2
;
10851 while (*s
== ' ' || *s
== ',')
10853 if (reg_lookup (&s
, RTYPE_GP
| RTYPE_NUM
, ®1
))
10855 else if (reg_lookup (&s
, RTYPE_FPU
, ®1
))
10859 as_bad (_("can't parse register list"));
10869 if (!reg_lookup (&s
, freg
? RTYPE_FPU
10870 : (RTYPE_GP
| RTYPE_NUM
), ®2
))
10872 as_bad (_("invalid register list"));
10876 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
10878 mask
&= ~ (7 << 3);
10881 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
10883 mask
&= ~ (7 << 3);
10886 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
10887 mask
|= (reg2
- 3) << 3;
10888 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
10889 mask
|= (reg2
- 15) << 1;
10890 else if (reg1
== RA
&& reg2
== RA
)
10894 as_bad (_("invalid register list"));
10898 /* The mask is filled in in the opcode table for the
10899 benefit of the disassembler. We remove it before
10900 applying the actual mask. */
10901 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
10902 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
10906 case 'm': /* Register list for save insn. */
10907 case 'M': /* Register list for restore insn. */
10910 int framesz
= 0, seen_framesz
= 0;
10911 int nargs
= 0, statics
= 0, sregs
= 0;
10915 unsigned int reg1
, reg2
;
10917 SKIP_SPACE_TABS (s
);
10920 SKIP_SPACE_TABS (s
);
10922 my_getExpression (&imm_expr
, s
);
10923 if (imm_expr
.X_op
== O_constant
)
10925 /* Handle the frame size. */
10928 as_bad (_("more than one frame size in list"));
10932 framesz
= imm_expr
.X_add_number
;
10933 imm_expr
.X_op
= O_absent
;
10938 if (! reg_lookup (&s
, RTYPE_GP
| RTYPE_NUM
, ®1
))
10940 as_bad (_("can't parse register list"));
10952 if (! reg_lookup (&s
, RTYPE_GP
| RTYPE_NUM
, ®2
)
10955 as_bad (_("can't parse register list"));
10960 while (reg1
<= reg2
)
10962 if (reg1
>= 4 && reg1
<= 7)
10966 nargs
|= 1 << (reg1
- 4);
10968 /* statics $a0-$a3 */
10969 statics
|= 1 << (reg1
- 4);
10971 else if ((reg1
>= 16 && reg1
<= 23) || reg1
== 30)
10974 sregs
|= 1 << ((reg1
== 30) ? 8 : (reg1
- 16));
10976 else if (reg1
== 31)
10978 /* Add $ra to insn. */
10983 as_bad (_("unexpected register in list"));
10991 /* Encode args/statics combination. */
10992 if (nargs
& statics
)
10993 as_bad (_("arg/static registers overlap"));
10994 else if (nargs
== 0xf)
10995 /* All $a0-$a3 are args. */
10996 opcode
|= MIPS16_ALL_ARGS
<< 16;
10997 else if (statics
== 0xf)
10998 /* All $a0-$a3 are statics. */
10999 opcode
|= MIPS16_ALL_STATICS
<< 16;
11002 int narg
= 0, nstat
= 0;
11004 /* Count arg registers. */
11005 while (nargs
& 0x1)
11011 as_bad (_("invalid arg register list"));
11013 /* Count static registers. */
11014 while (statics
& 0x8)
11016 statics
= (statics
<< 1) & 0xf;
11020 as_bad (_("invalid static register list"));
11022 /* Encode args/statics. */
11023 opcode
|= ((narg
<< 2) | nstat
) << 16;
11026 /* Encode $s0/$s1. */
11027 if (sregs
& (1 << 0)) /* $s0 */
11029 if (sregs
& (1 << 1)) /* $s1 */
11035 /* Count regs $s2-$s8. */
11043 as_bad (_("invalid static register list"));
11044 /* Encode $s2-$s8. */
11045 opcode
|= nsreg
<< 24;
11048 /* Encode frame size. */
11050 as_bad (_("missing frame size"));
11051 else if ((framesz
& 7) != 0 || framesz
< 0
11052 || framesz
> 0xff * 8)
11053 as_bad (_("invalid frame size"));
11054 else if (framesz
!= 128 || (opcode
>> 16) != 0)
11057 opcode
|= (((framesz
& 0xf0) << 16)
11058 | (framesz
& 0x0f));
11061 /* Finally build the instruction. */
11062 if ((opcode
>> 16) != 0 || framesz
== 0)
11064 ip
->use_extend
= TRUE
;
11065 ip
->extend
= opcode
>> 16;
11067 ip
->insn_opcode
|= opcode
& 0x7f;
11071 case 'e': /* extend code */
11072 my_getExpression (&imm_expr
, s
);
11073 check_absolute_expr (ip
, &imm_expr
);
11074 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
11076 as_warn (_("Invalid value for `%s' (%lu)"),
11078 (unsigned long) imm_expr
.X_add_number
);
11079 imm_expr
.X_add_number
&= 0x7ff;
11081 ip
->insn_opcode
|= imm_expr
.X_add_number
;
11082 imm_expr
.X_op
= O_absent
;
11092 /* Args don't match. */
11093 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
11094 strcmp (insn
->name
, insn
[1].name
) == 0)
11101 insn_error
= _("illegal operands");
11107 /* This structure holds information we know about a mips16 immediate
11110 struct mips16_immed_operand
11112 /* The type code used in the argument string in the opcode table. */
11114 /* The number of bits in the short form of the opcode. */
11116 /* The number of bits in the extended form of the opcode. */
11118 /* The amount by which the short form is shifted when it is used;
11119 for example, the sw instruction has a shift count of 2. */
11121 /* The amount by which the short form is shifted when it is stored
11122 into the instruction code. */
11124 /* Non-zero if the short form is unsigned. */
11126 /* Non-zero if the extended form is unsigned. */
11128 /* Non-zero if the value is PC relative. */
11132 /* The mips16 immediate operand types. */
11134 static const struct mips16_immed_operand mips16_immed_operands
[] =
11136 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
11137 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
11138 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
11139 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
11140 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
11141 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
11142 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
11143 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
11144 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
11145 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
11146 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
11147 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
11148 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
11149 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
11150 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
11151 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
11152 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
11153 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
11154 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
11155 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
11156 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
11159 #define MIPS16_NUM_IMMED \
11160 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
11162 /* Handle a mips16 instruction with an immediate value. This or's the
11163 small immediate value into *INSN. It sets *USE_EXTEND to indicate
11164 whether an extended value is needed; if one is needed, it sets
11165 *EXTEND to the value. The argument type is TYPE. The value is VAL.
11166 If SMALL is true, an unextended opcode was explicitly requested.
11167 If EXT is true, an extended opcode was explicitly requested. If
11168 WARN is true, warn if EXT does not match reality. */
11171 mips16_immed (char *file
, unsigned int line
, int type
, offsetT val
,
11172 bfd_boolean warn
, bfd_boolean small
, bfd_boolean ext
,
11173 unsigned long *insn
, bfd_boolean
*use_extend
,
11174 unsigned short *extend
)
11176 const struct mips16_immed_operand
*op
;
11177 int mintiny
, maxtiny
;
11178 bfd_boolean needext
;
11180 op
= mips16_immed_operands
;
11181 while (op
->type
!= type
)
11184 gas_assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
11189 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
11192 maxtiny
= 1 << op
->nbits
;
11197 maxtiny
= (1 << op
->nbits
) - 1;
11202 mintiny
= - (1 << (op
->nbits
- 1));
11203 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
11206 /* Branch offsets have an implicit 0 in the lowest bit. */
11207 if (type
== 'p' || type
== 'q')
11210 if ((val
& ((1 << op
->shift
) - 1)) != 0
11211 || val
< (mintiny
<< op
->shift
)
11212 || val
> (maxtiny
<< op
->shift
))
11217 if (warn
&& ext
&& ! needext
)
11218 as_warn_where (file
, line
,
11219 _("extended operand requested but not required"));
11220 if (small
&& needext
)
11221 as_bad_where (file
, line
, _("invalid unextended operand value"));
11223 if (small
|| (! ext
&& ! needext
))
11227 *use_extend
= FALSE
;
11228 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
11229 insnval
<<= op
->op_shift
;
11234 long minext
, maxext
;
11240 maxext
= (1 << op
->extbits
) - 1;
11244 minext
= - (1 << (op
->extbits
- 1));
11245 maxext
= (1 << (op
->extbits
- 1)) - 1;
11247 if (val
< minext
|| val
> maxext
)
11248 as_bad_where (file
, line
,
11249 _("operand value out of range for instruction"));
11251 *use_extend
= TRUE
;
11252 if (op
->extbits
== 16)
11254 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
11257 else if (op
->extbits
== 15)
11259 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
11264 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
11268 *extend
= (unsigned short) extval
;
11273 struct percent_op_match
11276 bfd_reloc_code_real_type reloc
;
11279 static const struct percent_op_match mips_percent_op
[] =
11281 {"%lo", BFD_RELOC_LO16
},
11283 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
11284 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
11285 {"%call16", BFD_RELOC_MIPS_CALL16
},
11286 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
11287 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
11288 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
11289 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
11290 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
11291 {"%got", BFD_RELOC_MIPS_GOT16
},
11292 {"%gp_rel", BFD_RELOC_GPREL16
},
11293 {"%half", BFD_RELOC_16
},
11294 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
11295 {"%higher", BFD_RELOC_MIPS_HIGHER
},
11296 {"%neg", BFD_RELOC_MIPS_SUB
},
11297 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD
},
11298 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM
},
11299 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16
},
11300 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16
},
11301 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16
},
11302 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16
},
11303 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL
},
11305 {"%hi", BFD_RELOC_HI16_S
}
11308 static const struct percent_op_match mips16_percent_op
[] =
11310 {"%lo", BFD_RELOC_MIPS16_LO16
},
11311 {"%gprel", BFD_RELOC_MIPS16_GPREL
},
11312 {"%got", BFD_RELOC_MIPS16_GOT16
},
11313 {"%call16", BFD_RELOC_MIPS16_CALL16
},
11314 {"%hi", BFD_RELOC_MIPS16_HI16_S
}
11318 /* Return true if *STR points to a relocation operator. When returning true,
11319 move *STR over the operator and store its relocation code in *RELOC.
11320 Leave both *STR and *RELOC alone when returning false. */
11323 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
)
11325 const struct percent_op_match
*percent_op
;
11328 if (mips_opts
.mips16
)
11330 percent_op
= mips16_percent_op
;
11331 limit
= ARRAY_SIZE (mips16_percent_op
);
11335 percent_op
= mips_percent_op
;
11336 limit
= ARRAY_SIZE (mips_percent_op
);
11339 for (i
= 0; i
< limit
; i
++)
11340 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
11342 int len
= strlen (percent_op
[i
].str
);
11344 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
11347 *str
+= strlen (percent_op
[i
].str
);
11348 *reloc
= percent_op
[i
].reloc
;
11350 /* Check whether the output BFD supports this relocation.
11351 If not, issue an error and fall back on something safe. */
11352 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
11354 as_bad (_("relocation %s isn't supported by the current ABI"),
11355 percent_op
[i
].str
);
11356 *reloc
= BFD_RELOC_UNUSED
;
11364 /* Parse string STR as a 16-bit relocatable operand. Store the
11365 expression in *EP and the relocations in the array starting
11366 at RELOC. Return the number of relocation operators used.
11368 On exit, EXPR_END points to the first character after the expression. */
11371 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
11374 bfd_reloc_code_real_type reversed_reloc
[3];
11375 size_t reloc_index
, i
;
11376 int crux_depth
, str_depth
;
11379 /* Search for the start of the main expression, recoding relocations
11380 in REVERSED_RELOC. End the loop with CRUX pointing to the start
11381 of the main expression and with CRUX_DEPTH containing the number
11382 of open brackets at that point. */
11389 crux_depth
= str_depth
;
11391 /* Skip over whitespace and brackets, keeping count of the number
11393 while (*str
== ' ' || *str
== '\t' || *str
== '(')
11398 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
11399 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
11401 my_getExpression (ep
, crux
);
11404 /* Match every open bracket. */
11405 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
11409 if (crux_depth
> 0)
11410 as_bad (_("unclosed '('"));
11414 if (reloc_index
!= 0)
11416 prev_reloc_op_frag
= frag_now
;
11417 for (i
= 0; i
< reloc_index
; i
++)
11418 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
11421 return reloc_index
;
11425 my_getExpression (expressionS
*ep
, char *str
)
11429 save_in
= input_line_pointer
;
11430 input_line_pointer
= str
;
11432 expr_end
= input_line_pointer
;
11433 input_line_pointer
= save_in
;
11437 md_atof (int type
, char *litP
, int *sizeP
)
11439 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
11443 md_number_to_chars (char *buf
, valueT val
, int n
)
11445 if (target_big_endian
)
11446 number_to_chars_bigendian (buf
, val
, n
);
11448 number_to_chars_littleendian (buf
, val
, n
);
11452 static int support_64bit_objects(void)
11454 const char **list
, **l
;
11457 list
= bfd_target_list ();
11458 for (l
= list
; *l
!= NULL
; l
++)
11459 if (strcmp (*l
, ELF_TARGET ("elf64-", "big")) == 0
11460 || strcmp (*l
, ELF_TARGET ("elf64-", "little")) == 0)
11462 yes
= (*l
!= NULL
);
11466 #endif /* OBJ_ELF */
11468 const char *md_shortopts
= "O::g::G:";
11472 OPTION_MARCH
= OPTION_MD_BASE
,
11494 OPTION_NO_SMARTMIPS
,
11497 OPTION_COMPAT_ARCH_BASE
,
11506 OPTION_M7000_HILO_FIX
,
11507 OPTION_MNO_7000_HILO_FIX
,
11510 OPTION_FIX_LOONGSON2F_JUMP
,
11511 OPTION_NO_FIX_LOONGSON2F_JUMP
,
11512 OPTION_FIX_LOONGSON2F_NOP
,
11513 OPTION_NO_FIX_LOONGSON2F_NOP
,
11515 OPTION_NO_FIX_VR4120
,
11517 OPTION_NO_FIX_VR4130
,
11518 OPTION_FIX_CN63XXP1
,
11519 OPTION_NO_FIX_CN63XXP1
,
11526 OPTION_CONSTRUCT_FLOATS
,
11527 OPTION_NO_CONSTRUCT_FLOATS
,
11530 OPTION_RELAX_BRANCH
,
11531 OPTION_NO_RELAX_BRANCH
,
11538 OPTION_SINGLE_FLOAT
,
11539 OPTION_DOUBLE_FLOAT
,
11542 OPTION_CALL_SHARED
,
11543 OPTION_CALL_NONPIC
,
11553 OPTION_MVXWORKS_PIC
,
11554 #endif /* OBJ_ELF */
11558 struct option md_longopts
[] =
11560 /* Options which specify architecture. */
11561 {"march", required_argument
, NULL
, OPTION_MARCH
},
11562 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
11563 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
11564 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
11565 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
11566 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
11567 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
11568 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
11569 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
11570 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
11571 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
11572 {"mips64r2", no_argument
, NULL
, OPTION_MIPS64R2
},
11574 /* Options which specify Application Specific Extensions (ASEs). */
11575 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
11576 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
11577 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
11578 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
11579 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
11580 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
11581 {"mdsp", no_argument
, NULL
, OPTION_DSP
},
11582 {"mno-dsp", no_argument
, NULL
, OPTION_NO_DSP
},
11583 {"mmt", no_argument
, NULL
, OPTION_MT
},
11584 {"mno-mt", no_argument
, NULL
, OPTION_NO_MT
},
11585 {"msmartmips", no_argument
, NULL
, OPTION_SMARTMIPS
},
11586 {"mno-smartmips", no_argument
, NULL
, OPTION_NO_SMARTMIPS
},
11587 {"mdspr2", no_argument
, NULL
, OPTION_DSPR2
},
11588 {"mno-dspr2", no_argument
, NULL
, OPTION_NO_DSPR2
},
11590 /* Old-style architecture options. Don't add more of these. */
11591 {"m4650", no_argument
, NULL
, OPTION_M4650
},
11592 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
11593 {"m4010", no_argument
, NULL
, OPTION_M4010
},
11594 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
11595 {"m4100", no_argument
, NULL
, OPTION_M4100
},
11596 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
11597 {"m3900", no_argument
, NULL
, OPTION_M3900
},
11598 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
11600 /* Options which enable bug fixes. */
11601 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
11602 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
11603 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
11604 {"mfix-loongson2f-jump", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_JUMP
},
11605 {"mno-fix-loongson2f-jump", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_JUMP
},
11606 {"mfix-loongson2f-nop", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_NOP
},
11607 {"mno-fix-loongson2f-nop", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_NOP
},
11608 {"mfix-vr4120", no_argument
, NULL
, OPTION_FIX_VR4120
},
11609 {"mno-fix-vr4120", no_argument
, NULL
, OPTION_NO_FIX_VR4120
},
11610 {"mfix-vr4130", no_argument
, NULL
, OPTION_FIX_VR4130
},
11611 {"mno-fix-vr4130", no_argument
, NULL
, OPTION_NO_FIX_VR4130
},
11612 {"mfix-24k", no_argument
, NULL
, OPTION_FIX_24K
},
11613 {"mno-fix-24k", no_argument
, NULL
, OPTION_NO_FIX_24K
},
11614 {"mfix-cn63xxp1", no_argument
, NULL
, OPTION_FIX_CN63XXP1
},
11615 {"mno-fix-cn63xxp1", no_argument
, NULL
, OPTION_NO_FIX_CN63XXP1
},
11617 /* Miscellaneous options. */
11618 {"trap", no_argument
, NULL
, OPTION_TRAP
},
11619 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
11620 {"break", no_argument
, NULL
, OPTION_BREAK
},
11621 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
11622 {"EB", no_argument
, NULL
, OPTION_EB
},
11623 {"EL", no_argument
, NULL
, OPTION_EL
},
11624 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
11625 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
11626 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
11627 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
11628 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
11629 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
11630 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
11631 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
11632 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
11633 {"mno-shared", no_argument
, NULL
, OPTION_MNO_SHARED
},
11634 {"msym32", no_argument
, NULL
, OPTION_MSYM32
},
11635 {"mno-sym32", no_argument
, NULL
, OPTION_MNO_SYM32
},
11636 {"msoft-float", no_argument
, NULL
, OPTION_SOFT_FLOAT
},
11637 {"mhard-float", no_argument
, NULL
, OPTION_HARD_FLOAT
},
11638 {"msingle-float", no_argument
, NULL
, OPTION_SINGLE_FLOAT
},
11639 {"mdouble-float", no_argument
, NULL
, OPTION_DOUBLE_FLOAT
},
11641 /* Strictly speaking this next option is ELF specific,
11642 but we allow it for other ports as well in order to
11643 make testing easier. */
11644 {"32", no_argument
, NULL
, OPTION_32
},
11646 /* ELF-specific options. */
11648 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
11649 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
11650 {"call_nonpic", no_argument
, NULL
, OPTION_CALL_NONPIC
},
11651 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
11652 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
11653 {"mabi", required_argument
, NULL
, OPTION_MABI
},
11654 {"n32", no_argument
, NULL
, OPTION_N32
},
11655 {"64", no_argument
, NULL
, OPTION_64
},
11656 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
11657 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
11658 {"mpdr", no_argument
, NULL
, OPTION_PDR
},
11659 {"mno-pdr", no_argument
, NULL
, OPTION_NO_PDR
},
11660 {"mvxworks-pic", no_argument
, NULL
, OPTION_MVXWORKS_PIC
},
11661 #endif /* OBJ_ELF */
11663 {NULL
, no_argument
, NULL
, 0}
11665 size_t md_longopts_size
= sizeof (md_longopts
);
11667 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
11668 NEW_VALUE. Warn if another value was already specified. Note:
11669 we have to defer parsing the -march and -mtune arguments in order
11670 to handle 'from-abi' correctly, since the ABI might be specified
11671 in a later argument. */
11674 mips_set_option_string (const char **string_ptr
, const char *new_value
)
11676 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
11677 as_warn (_("A different %s was already specified, is now %s"),
11678 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
11681 *string_ptr
= new_value
;
11685 md_parse_option (int c
, char *arg
)
11689 case OPTION_CONSTRUCT_FLOATS
:
11690 mips_disable_float_construction
= 0;
11693 case OPTION_NO_CONSTRUCT_FLOATS
:
11694 mips_disable_float_construction
= 1;
11706 target_big_endian
= 1;
11710 target_big_endian
= 0;
11716 else if (arg
[0] == '0')
11718 else if (arg
[0] == '1')
11728 mips_debug
= atoi (arg
);
11732 file_mips_isa
= ISA_MIPS1
;
11736 file_mips_isa
= ISA_MIPS2
;
11740 file_mips_isa
= ISA_MIPS3
;
11744 file_mips_isa
= ISA_MIPS4
;
11748 file_mips_isa
= ISA_MIPS5
;
11751 case OPTION_MIPS32
:
11752 file_mips_isa
= ISA_MIPS32
;
11755 case OPTION_MIPS32R2
:
11756 file_mips_isa
= ISA_MIPS32R2
;
11759 case OPTION_MIPS64R2
:
11760 file_mips_isa
= ISA_MIPS64R2
;
11763 case OPTION_MIPS64
:
11764 file_mips_isa
= ISA_MIPS64
;
11768 mips_set_option_string (&mips_tune_string
, arg
);
11772 mips_set_option_string (&mips_arch_string
, arg
);
11776 mips_set_option_string (&mips_arch_string
, "4650");
11777 mips_set_option_string (&mips_tune_string
, "4650");
11780 case OPTION_NO_M4650
:
11784 mips_set_option_string (&mips_arch_string
, "4010");
11785 mips_set_option_string (&mips_tune_string
, "4010");
11788 case OPTION_NO_M4010
:
11792 mips_set_option_string (&mips_arch_string
, "4100");
11793 mips_set_option_string (&mips_tune_string
, "4100");
11796 case OPTION_NO_M4100
:
11800 mips_set_option_string (&mips_arch_string
, "3900");
11801 mips_set_option_string (&mips_tune_string
, "3900");
11804 case OPTION_NO_M3900
:
11808 mips_opts
.ase_mdmx
= 1;
11811 case OPTION_NO_MDMX
:
11812 mips_opts
.ase_mdmx
= 0;
11816 mips_opts
.ase_dsp
= 1;
11817 mips_opts
.ase_dspr2
= 0;
11820 case OPTION_NO_DSP
:
11821 mips_opts
.ase_dsp
= 0;
11822 mips_opts
.ase_dspr2
= 0;
11826 mips_opts
.ase_dspr2
= 1;
11827 mips_opts
.ase_dsp
= 1;
11830 case OPTION_NO_DSPR2
:
11831 mips_opts
.ase_dspr2
= 0;
11832 mips_opts
.ase_dsp
= 0;
11836 mips_opts
.ase_mt
= 1;
11840 mips_opts
.ase_mt
= 0;
11843 case OPTION_MIPS16
:
11844 mips_opts
.mips16
= 1;
11845 mips_no_prev_insn ();
11848 case OPTION_NO_MIPS16
:
11849 mips_opts
.mips16
= 0;
11850 mips_no_prev_insn ();
11853 case OPTION_MIPS3D
:
11854 mips_opts
.ase_mips3d
= 1;
11857 case OPTION_NO_MIPS3D
:
11858 mips_opts
.ase_mips3d
= 0;
11861 case OPTION_SMARTMIPS
:
11862 mips_opts
.ase_smartmips
= 1;
11865 case OPTION_NO_SMARTMIPS
:
11866 mips_opts
.ase_smartmips
= 0;
11869 case OPTION_FIX_24K
:
11873 case OPTION_NO_FIX_24K
:
11877 case OPTION_FIX_LOONGSON2F_JUMP
:
11878 mips_fix_loongson2f_jump
= TRUE
;
11881 case OPTION_NO_FIX_LOONGSON2F_JUMP
:
11882 mips_fix_loongson2f_jump
= FALSE
;
11885 case OPTION_FIX_LOONGSON2F_NOP
:
11886 mips_fix_loongson2f_nop
= TRUE
;
11889 case OPTION_NO_FIX_LOONGSON2F_NOP
:
11890 mips_fix_loongson2f_nop
= FALSE
;
11893 case OPTION_FIX_VR4120
:
11894 mips_fix_vr4120
= 1;
11897 case OPTION_NO_FIX_VR4120
:
11898 mips_fix_vr4120
= 0;
11901 case OPTION_FIX_VR4130
:
11902 mips_fix_vr4130
= 1;
11905 case OPTION_NO_FIX_VR4130
:
11906 mips_fix_vr4130
= 0;
11909 case OPTION_FIX_CN63XXP1
:
11910 mips_fix_cn63xxp1
= TRUE
;
11913 case OPTION_NO_FIX_CN63XXP1
:
11914 mips_fix_cn63xxp1
= FALSE
;
11917 case OPTION_RELAX_BRANCH
:
11918 mips_relax_branch
= 1;
11921 case OPTION_NO_RELAX_BRANCH
:
11922 mips_relax_branch
= 0;
11925 case OPTION_MSHARED
:
11926 mips_in_shared
= TRUE
;
11929 case OPTION_MNO_SHARED
:
11930 mips_in_shared
= FALSE
;
11933 case OPTION_MSYM32
:
11934 mips_opts
.sym32
= TRUE
;
11937 case OPTION_MNO_SYM32
:
11938 mips_opts
.sym32
= FALSE
;
11942 /* When generating ELF code, we permit -KPIC and -call_shared to
11943 select SVR4_PIC, and -non_shared to select no PIC. This is
11944 intended to be compatible with Irix 5. */
11945 case OPTION_CALL_SHARED
:
11948 as_bad (_("-call_shared is supported only for ELF format"));
11951 mips_pic
= SVR4_PIC
;
11952 mips_abicalls
= TRUE
;
11955 case OPTION_CALL_NONPIC
:
11958 as_bad (_("-call_nonpic is supported only for ELF format"));
11962 mips_abicalls
= TRUE
;
11965 case OPTION_NON_SHARED
:
11968 as_bad (_("-non_shared is supported only for ELF format"));
11972 mips_abicalls
= FALSE
;
11975 /* The -xgot option tells the assembler to use 32 bit offsets
11976 when accessing the got in SVR4_PIC mode. It is for Irix
11981 #endif /* OBJ_ELF */
11984 g_switch_value
= atoi (arg
);
11988 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
11992 mips_abi
= O32_ABI
;
11993 /* We silently ignore -32 for non-ELF targets. This greatly
11994 simplifies the construction of the MIPS GAS test cases. */
12001 as_bad (_("-n32 is supported for ELF format only"));
12004 mips_abi
= N32_ABI
;
12010 as_bad (_("-64 is supported for ELF format only"));
12013 mips_abi
= N64_ABI
;
12014 if (!support_64bit_objects())
12015 as_fatal (_("No compiled in support for 64 bit object file format"));
12017 #endif /* OBJ_ELF */
12020 file_mips_gp32
= 1;
12024 file_mips_gp32
= 0;
12028 file_mips_fp32
= 1;
12032 file_mips_fp32
= 0;
12035 case OPTION_SINGLE_FLOAT
:
12036 file_mips_single_float
= 1;
12039 case OPTION_DOUBLE_FLOAT
:
12040 file_mips_single_float
= 0;
12043 case OPTION_SOFT_FLOAT
:
12044 file_mips_soft_float
= 1;
12047 case OPTION_HARD_FLOAT
:
12048 file_mips_soft_float
= 0;
12055 as_bad (_("-mabi is supported for ELF format only"));
12058 if (strcmp (arg
, "32") == 0)
12059 mips_abi
= O32_ABI
;
12060 else if (strcmp (arg
, "o64") == 0)
12061 mips_abi
= O64_ABI
;
12062 else if (strcmp (arg
, "n32") == 0)
12063 mips_abi
= N32_ABI
;
12064 else if (strcmp (arg
, "64") == 0)
12066 mips_abi
= N64_ABI
;
12067 if (! support_64bit_objects())
12068 as_fatal (_("No compiled in support for 64 bit object file "
12071 else if (strcmp (arg
, "eabi") == 0)
12072 mips_abi
= EABI_ABI
;
12075 as_fatal (_("invalid abi -mabi=%s"), arg
);
12079 #endif /* OBJ_ELF */
12081 case OPTION_M7000_HILO_FIX
:
12082 mips_7000_hilo_fix
= TRUE
;
12085 case OPTION_MNO_7000_HILO_FIX
:
12086 mips_7000_hilo_fix
= FALSE
;
12090 case OPTION_MDEBUG
:
12091 mips_flag_mdebug
= TRUE
;
12094 case OPTION_NO_MDEBUG
:
12095 mips_flag_mdebug
= FALSE
;
12099 mips_flag_pdr
= TRUE
;
12102 case OPTION_NO_PDR
:
12103 mips_flag_pdr
= FALSE
;
12106 case OPTION_MVXWORKS_PIC
:
12107 mips_pic
= VXWORKS_PIC
;
12109 #endif /* OBJ_ELF */
12115 mips_fix_loongson2f
= mips_fix_loongson2f_nop
|| mips_fix_loongson2f_jump
;
12120 /* Set up globals to generate code for the ISA or processor
12121 described by INFO. */
12124 mips_set_architecture (const struct mips_cpu_info
*info
)
12128 file_mips_arch
= info
->cpu
;
12129 mips_opts
.arch
= info
->cpu
;
12130 mips_opts
.isa
= info
->isa
;
12135 /* Likewise for tuning. */
12138 mips_set_tune (const struct mips_cpu_info
*info
)
12141 mips_tune
= info
->cpu
;
12146 mips_after_parse_args (void)
12148 const struct mips_cpu_info
*arch_info
= 0;
12149 const struct mips_cpu_info
*tune_info
= 0;
12151 /* GP relative stuff not working for PE */
12152 if (strncmp (TARGET_OS
, "pe", 2) == 0)
12154 if (g_switch_seen
&& g_switch_value
!= 0)
12155 as_bad (_("-G not supported in this configuration."));
12156 g_switch_value
= 0;
12159 if (mips_abi
== NO_ABI
)
12160 mips_abi
= MIPS_DEFAULT_ABI
;
12162 /* The following code determines the architecture and register size.
12163 Similar code was added to GCC 3.3 (see override_options() in
12164 config/mips/mips.c). The GAS and GCC code should be kept in sync
12165 as much as possible. */
12167 if (mips_arch_string
!= 0)
12168 arch_info
= mips_parse_cpu ("-march", mips_arch_string
);
12170 if (file_mips_isa
!= ISA_UNKNOWN
)
12172 /* Handle -mipsN. At this point, file_mips_isa contains the
12173 ISA level specified by -mipsN, while arch_info->isa contains
12174 the -march selection (if any). */
12175 if (arch_info
!= 0)
12177 /* -march takes precedence over -mipsN, since it is more descriptive.
12178 There's no harm in specifying both as long as the ISA levels
12180 if (file_mips_isa
!= arch_info
->isa
)
12181 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
12182 mips_cpu_info_from_isa (file_mips_isa
)->name
,
12183 mips_cpu_info_from_isa (arch_info
->isa
)->name
);
12186 arch_info
= mips_cpu_info_from_isa (file_mips_isa
);
12189 if (arch_info
== 0)
12190 arch_info
= mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT
);
12192 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (arch_info
->isa
))
12193 as_bad (_("-march=%s is not compatible with the selected ABI"),
12196 mips_set_architecture (arch_info
);
12198 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
12199 if (mips_tune_string
!= 0)
12200 tune_info
= mips_parse_cpu ("-mtune", mips_tune_string
);
12202 if (tune_info
== 0)
12203 mips_set_tune (arch_info
);
12205 mips_set_tune (tune_info
);
12207 if (file_mips_gp32
>= 0)
12209 /* The user specified the size of the integer registers. Make sure
12210 it agrees with the ABI and ISA. */
12211 if (file_mips_gp32
== 0 && !ISA_HAS_64BIT_REGS (mips_opts
.isa
))
12212 as_bad (_("-mgp64 used with a 32-bit processor"));
12213 else if (file_mips_gp32
== 1 && ABI_NEEDS_64BIT_REGS (mips_abi
))
12214 as_bad (_("-mgp32 used with a 64-bit ABI"));
12215 else if (file_mips_gp32
== 0 && ABI_NEEDS_32BIT_REGS (mips_abi
))
12216 as_bad (_("-mgp64 used with a 32-bit ABI"));
12220 /* Infer the integer register size from the ABI and processor.
12221 Restrict ourselves to 32-bit registers if that's all the
12222 processor has, or if the ABI cannot handle 64-bit registers. */
12223 file_mips_gp32
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
12224 || !ISA_HAS_64BIT_REGS (mips_opts
.isa
));
12227 switch (file_mips_fp32
)
12231 /* No user specified float register size.
12232 ??? GAS treats single-float processors as though they had 64-bit
12233 float registers (although it complains when double-precision
12234 instructions are used). As things stand, saying they have 32-bit
12235 registers would lead to spurious "register must be even" messages.
12236 So here we assume float registers are never smaller than the
12238 if (file_mips_gp32
== 0)
12239 /* 64-bit integer registers implies 64-bit float registers. */
12240 file_mips_fp32
= 0;
12241 else if ((mips_opts
.ase_mips3d
> 0 || mips_opts
.ase_mdmx
> 0)
12242 && ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
12243 /* -mips3d and -mdmx imply 64-bit float registers, if possible. */
12244 file_mips_fp32
= 0;
12246 /* 32-bit float registers. */
12247 file_mips_fp32
= 1;
12250 /* The user specified the size of the float registers. Check if it
12251 agrees with the ABI and ISA. */
12253 if (!ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
12254 as_bad (_("-mfp64 used with a 32-bit fpu"));
12255 else if (ABI_NEEDS_32BIT_REGS (mips_abi
)
12256 && !ISA_HAS_MXHC1 (mips_opts
.isa
))
12257 as_warn (_("-mfp64 used with a 32-bit ABI"));
12260 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
12261 as_warn (_("-mfp32 used with a 64-bit ABI"));
12265 /* End of GCC-shared inference code. */
12267 /* This flag is set when we have a 64-bit capable CPU but use only
12268 32-bit wide registers. Note that EABI does not use it. */
12269 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
)
12270 && ((mips_abi
== NO_ABI
&& file_mips_gp32
== 1)
12271 || mips_abi
== O32_ABI
))
12272 mips_32bitmode
= 1;
12274 if (mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
12275 as_bad (_("trap exception not supported at ISA 1"));
12277 /* If the selected architecture includes support for ASEs, enable
12278 generation of code for them. */
12279 if (mips_opts
.mips16
== -1)
12280 mips_opts
.mips16
= (CPU_HAS_MIPS16 (file_mips_arch
)) ? 1 : 0;
12281 if (mips_opts
.ase_mips3d
== -1)
12282 mips_opts
.ase_mips3d
= ((arch_info
->flags
& MIPS_CPU_ASE_MIPS3D
)
12283 && file_mips_fp32
== 0) ? 1 : 0;
12284 if (mips_opts
.ase_mips3d
&& file_mips_fp32
== 1)
12285 as_bad (_("-mfp32 used with -mips3d"));
12287 if (mips_opts
.ase_mdmx
== -1)
12288 mips_opts
.ase_mdmx
= ((arch_info
->flags
& MIPS_CPU_ASE_MDMX
)
12289 && file_mips_fp32
== 0) ? 1 : 0;
12290 if (mips_opts
.ase_mdmx
&& file_mips_fp32
== 1)
12291 as_bad (_("-mfp32 used with -mdmx"));
12293 if (mips_opts
.ase_smartmips
== -1)
12294 mips_opts
.ase_smartmips
= (arch_info
->flags
& MIPS_CPU_ASE_SMARTMIPS
) ? 1 : 0;
12295 if (mips_opts
.ase_smartmips
&& !ISA_SUPPORTS_SMARTMIPS
)
12296 as_warn (_("%s ISA does not support SmartMIPS"),
12297 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
12299 if (mips_opts
.ase_dsp
== -1)
12300 mips_opts
.ase_dsp
= (arch_info
->flags
& MIPS_CPU_ASE_DSP
) ? 1 : 0;
12301 if (mips_opts
.ase_dsp
&& !ISA_SUPPORTS_DSP_ASE
)
12302 as_warn (_("%s ISA does not support DSP ASE"),
12303 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
12305 if (mips_opts
.ase_dspr2
== -1)
12307 mips_opts
.ase_dspr2
= (arch_info
->flags
& MIPS_CPU_ASE_DSPR2
) ? 1 : 0;
12308 mips_opts
.ase_dsp
= (arch_info
->flags
& MIPS_CPU_ASE_DSP
) ? 1 : 0;
12310 if (mips_opts
.ase_dspr2
&& !ISA_SUPPORTS_DSPR2_ASE
)
12311 as_warn (_("%s ISA does not support DSP R2 ASE"),
12312 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
12314 if (mips_opts
.ase_mt
== -1)
12315 mips_opts
.ase_mt
= (arch_info
->flags
& MIPS_CPU_ASE_MT
) ? 1 : 0;
12316 if (mips_opts
.ase_mt
&& !ISA_SUPPORTS_MT_ASE
)
12317 as_warn (_("%s ISA does not support MT ASE"),
12318 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
12320 file_mips_isa
= mips_opts
.isa
;
12321 file_ase_mips3d
= mips_opts
.ase_mips3d
;
12322 file_ase_mdmx
= mips_opts
.ase_mdmx
;
12323 file_ase_smartmips
= mips_opts
.ase_smartmips
;
12324 file_ase_dsp
= mips_opts
.ase_dsp
;
12325 file_ase_dspr2
= mips_opts
.ase_dspr2
;
12326 file_ase_mt
= mips_opts
.ase_mt
;
12327 mips_opts
.gp32
= file_mips_gp32
;
12328 mips_opts
.fp32
= file_mips_fp32
;
12329 mips_opts
.soft_float
= file_mips_soft_float
;
12330 mips_opts
.single_float
= file_mips_single_float
;
12332 if (mips_flag_mdebug
< 0)
12334 #ifdef OBJ_MAYBE_ECOFF
12335 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
)
12336 mips_flag_mdebug
= 1;
12338 #endif /* OBJ_MAYBE_ECOFF */
12339 mips_flag_mdebug
= 0;
12344 mips_init_after_args (void)
12346 /* initialize opcodes */
12347 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
12348 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
12352 md_pcrel_from (fixS
*fixP
)
12354 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
12355 switch (fixP
->fx_r_type
)
12357 case BFD_RELOC_16_PCREL_S2
:
12358 case BFD_RELOC_MIPS_JMP
:
12359 /* Return the address of the delay slot. */
12362 /* We have no relocation type for PC relative MIPS16 instructions. */
12363 if (fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != now_seg
)
12364 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
12365 _("PC relative MIPS16 instruction references a different section"));
12370 /* This is called before the symbol table is processed. In order to
12371 work with gcc when using mips-tfile, we must keep all local labels.
12372 However, in other cases, we want to discard them. If we were
12373 called with -g, but we didn't see any debugging information, it may
12374 mean that gcc is smuggling debugging information through to
12375 mips-tfile, in which case we must generate all local labels. */
12378 mips_frob_file_before_adjust (void)
12380 #ifndef NO_ECOFF_DEBUGGING
12381 if (ECOFF_DEBUGGING
12383 && ! ecoff_debugging_seen
)
12384 flag_keep_locals
= 1;
12388 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
12389 the corresponding LO16 reloc. This is called before md_apply_fix and
12390 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
12391 relocation operators.
12393 For our purposes, a %lo() expression matches a %got() or %hi()
12396 (a) it refers to the same symbol; and
12397 (b) the offset applied in the %lo() expression is no lower than
12398 the offset applied in the %got() or %hi().
12400 (b) allows us to cope with code like:
12403 lh $4,%lo(foo+2)($4)
12405 ...which is legal on RELA targets, and has a well-defined behaviour
12406 if the user knows that adding 2 to "foo" will not induce a carry to
12409 When several %lo()s match a particular %got() or %hi(), we use the
12410 following rules to distinguish them:
12412 (1) %lo()s with smaller offsets are a better match than %lo()s with
12415 (2) %lo()s with no matching %got() or %hi() are better than those
12416 that already have a matching %got() or %hi().
12418 (3) later %lo()s are better than earlier %lo()s.
12420 These rules are applied in order.
12422 (1) means, among other things, that %lo()s with identical offsets are
12423 chosen if they exist.
12425 (2) means that we won't associate several high-part relocations with
12426 the same low-part relocation unless there's no alternative. Having
12427 several high parts for the same low part is a GNU extension; this rule
12428 allows careful users to avoid it.
12430 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
12431 with the last high-part relocation being at the front of the list.
12432 It therefore makes sense to choose the last matching low-part
12433 relocation, all other things being equal. It's also easier
12434 to code that way. */
12437 mips_frob_file (void)
12439 struct mips_hi_fixup
*l
;
12440 bfd_reloc_code_real_type looking_for_rtype
= BFD_RELOC_UNUSED
;
12442 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
12444 segment_info_type
*seginfo
;
12445 bfd_boolean matched_lo_p
;
12446 fixS
**hi_pos
, **lo_pos
, **pos
;
12448 gas_assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
12450 /* If a GOT16 relocation turns out to be against a global symbol,
12451 there isn't supposed to be a matching LO. */
12452 if (got16_reloc_p (l
->fixp
->fx_r_type
)
12453 && !pic_need_relax (l
->fixp
->fx_addsy
, l
->seg
))
12456 /* Check quickly whether the next fixup happens to be a matching %lo. */
12457 if (fixup_has_matching_lo_p (l
->fixp
))
12460 seginfo
= seg_info (l
->seg
);
12462 /* Set HI_POS to the position of this relocation in the chain.
12463 Set LO_POS to the position of the chosen low-part relocation.
12464 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
12465 relocation that matches an immediately-preceding high-part
12469 matched_lo_p
= FALSE
;
12470 looking_for_rtype
= matching_lo_reloc (l
->fixp
->fx_r_type
);
12472 for (pos
= &seginfo
->fix_root
; *pos
!= NULL
; pos
= &(*pos
)->fx_next
)
12474 if (*pos
== l
->fixp
)
12477 if ((*pos
)->fx_r_type
== looking_for_rtype
12478 && symbol_same_p ((*pos
)->fx_addsy
, l
->fixp
->fx_addsy
)
12479 && (*pos
)->fx_offset
>= l
->fixp
->fx_offset
12481 || (*pos
)->fx_offset
< (*lo_pos
)->fx_offset
12483 && (*pos
)->fx_offset
== (*lo_pos
)->fx_offset
)))
12486 matched_lo_p
= (reloc_needs_lo_p ((*pos
)->fx_r_type
)
12487 && fixup_has_matching_lo_p (*pos
));
12490 /* If we found a match, remove the high-part relocation from its
12491 current position and insert it before the low-part relocation.
12492 Make the offsets match so that fixup_has_matching_lo_p()
12495 We don't warn about unmatched high-part relocations since some
12496 versions of gcc have been known to emit dead "lui ...%hi(...)"
12498 if (lo_pos
!= NULL
)
12500 l
->fixp
->fx_offset
= (*lo_pos
)->fx_offset
;
12501 if (l
->fixp
->fx_next
!= *lo_pos
)
12503 *hi_pos
= l
->fixp
->fx_next
;
12504 l
->fixp
->fx_next
= *lo_pos
;
12511 /* We may have combined relocations without symbols in the N32/N64 ABI.
12512 We have to prevent gas from dropping them. */
12515 mips_force_relocation (fixS
*fixp
)
12517 if (generic_force_reloc (fixp
))
12521 && S_GET_SEGMENT (fixp
->fx_addsy
) == bfd_abs_section_ptr
12522 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_SUB
12523 || hi16_reloc_p (fixp
->fx_r_type
)
12524 || lo16_reloc_p (fixp
->fx_r_type
)))
12530 /* Apply a fixup to the object file. */
12533 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
12537 reloc_howto_type
*howto
;
12539 /* We ignore generic BFD relocations we don't know about. */
12540 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
12544 gas_assert (fixP
->fx_size
== 4
12545 || fixP
->fx_r_type
== BFD_RELOC_16
12546 || fixP
->fx_r_type
== BFD_RELOC_64
12547 || fixP
->fx_r_type
== BFD_RELOC_CTOR
12548 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
12549 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
12550 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
12551 || fixP
->fx_r_type
== BFD_RELOC_MIPS_TLS_DTPREL64
);
12553 buf
= (bfd_byte
*) (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
);
12555 gas_assert (!fixP
->fx_pcrel
|| fixP
->fx_r_type
== BFD_RELOC_16_PCREL_S2
);
12557 /* Don't treat parts of a composite relocation as done. There are two
12560 (1) The second and third parts will be against 0 (RSS_UNDEF) but
12561 should nevertheless be emitted if the first part is.
12563 (2) In normal usage, composite relocations are never assembly-time
12564 constants. The easiest way of dealing with the pathological
12565 exceptions is to generate a relocation against STN_UNDEF and
12566 leave everything up to the linker. */
12567 if (fixP
->fx_addsy
== NULL
&& !fixP
->fx_pcrel
&& fixP
->fx_tcbit
== 0)
12570 switch (fixP
->fx_r_type
)
12572 case BFD_RELOC_MIPS_TLS_GD
:
12573 case BFD_RELOC_MIPS_TLS_LDM
:
12574 case BFD_RELOC_MIPS_TLS_DTPREL32
:
12575 case BFD_RELOC_MIPS_TLS_DTPREL64
:
12576 case BFD_RELOC_MIPS_TLS_DTPREL_HI16
:
12577 case BFD_RELOC_MIPS_TLS_DTPREL_LO16
:
12578 case BFD_RELOC_MIPS_TLS_GOTTPREL
:
12579 case BFD_RELOC_MIPS_TLS_TPREL_HI16
:
12580 case BFD_RELOC_MIPS_TLS_TPREL_LO16
:
12581 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
12584 case BFD_RELOC_MIPS_JMP
:
12585 case BFD_RELOC_MIPS_SHIFT5
:
12586 case BFD_RELOC_MIPS_SHIFT6
:
12587 case BFD_RELOC_MIPS_GOT_DISP
:
12588 case BFD_RELOC_MIPS_GOT_PAGE
:
12589 case BFD_RELOC_MIPS_GOT_OFST
:
12590 case BFD_RELOC_MIPS_SUB
:
12591 case BFD_RELOC_MIPS_INSERT_A
:
12592 case BFD_RELOC_MIPS_INSERT_B
:
12593 case BFD_RELOC_MIPS_DELETE
:
12594 case BFD_RELOC_MIPS_HIGHEST
:
12595 case BFD_RELOC_MIPS_HIGHER
:
12596 case BFD_RELOC_MIPS_SCN_DISP
:
12597 case BFD_RELOC_MIPS_REL16
:
12598 case BFD_RELOC_MIPS_RELGOT
:
12599 case BFD_RELOC_MIPS_JALR
:
12600 case BFD_RELOC_HI16
:
12601 case BFD_RELOC_HI16_S
:
12602 case BFD_RELOC_GPREL16
:
12603 case BFD_RELOC_MIPS_LITERAL
:
12604 case BFD_RELOC_MIPS_CALL16
:
12605 case BFD_RELOC_MIPS_GOT16
:
12606 case BFD_RELOC_GPREL32
:
12607 case BFD_RELOC_MIPS_GOT_HI16
:
12608 case BFD_RELOC_MIPS_GOT_LO16
:
12609 case BFD_RELOC_MIPS_CALL_HI16
:
12610 case BFD_RELOC_MIPS_CALL_LO16
:
12611 case BFD_RELOC_MIPS16_GPREL
:
12612 case BFD_RELOC_MIPS16_GOT16
:
12613 case BFD_RELOC_MIPS16_CALL16
:
12614 case BFD_RELOC_MIPS16_HI16
:
12615 case BFD_RELOC_MIPS16_HI16_S
:
12616 case BFD_RELOC_MIPS16_JMP
:
12617 /* Nothing needed to do. The value comes from the reloc entry. */
12621 /* This is handled like BFD_RELOC_32, but we output a sign
12622 extended value if we are only 32 bits. */
12625 if (8 <= sizeof (valueT
))
12626 md_number_to_chars ((char *) buf
, *valP
, 8);
12631 if ((*valP
& 0x80000000) != 0)
12635 md_number_to_chars ((char *)(buf
+ (target_big_endian
? 4 : 0)),
12637 md_number_to_chars ((char *)(buf
+ (target_big_endian
? 0 : 4)),
12643 case BFD_RELOC_RVA
:
12646 /* If we are deleting this reloc entry, we must fill in the
12647 value now. This can happen if we have a .word which is not
12648 resolved when it appears but is later defined. */
12650 md_number_to_chars ((char *) buf
, *valP
, fixP
->fx_size
);
12653 case BFD_RELOC_LO16
:
12654 case BFD_RELOC_MIPS16_LO16
:
12655 /* FIXME: Now that embedded-PIC is gone, some of this code/comment
12656 may be safe to remove, but if so it's not obvious. */
12657 /* When handling an embedded PIC switch statement, we can wind
12658 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
12661 if (*valP
+ 0x8000 > 0xffff)
12662 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
12663 _("relocation overflow"));
12664 if (target_big_endian
)
12666 md_number_to_chars ((char *) buf
, *valP
, 2);
12670 case BFD_RELOC_16_PCREL_S2
:
12671 if ((*valP
& 0x3) != 0)
12672 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
12673 _("Branch to misaligned address (%lx)"), (long) *valP
);
12675 /* We need to save the bits in the instruction since fixup_segment()
12676 might be deleting the relocation entry (i.e., a branch within
12677 the current segment). */
12678 if (! fixP
->fx_done
)
12681 /* Update old instruction data. */
12682 if (target_big_endian
)
12683 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
12685 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
12687 if (*valP
+ 0x20000 <= 0x3ffff)
12689 insn
|= (*valP
>> 2) & 0xffff;
12690 md_number_to_chars ((char *) buf
, insn
, 4);
12692 else if (mips_pic
== NO_PIC
12694 && fixP
->fx_frag
->fr_address
>= text_section
->vma
12695 && (fixP
->fx_frag
->fr_address
12696 < text_section
->vma
+ bfd_get_section_size (text_section
))
12697 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
12698 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
12699 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
12701 /* The branch offset is too large. If this is an
12702 unconditional branch, and we are not generating PIC code,
12703 we can convert it to an absolute jump instruction. */
12704 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
12705 insn
= 0x0c000000; /* jal */
12707 insn
= 0x08000000; /* j */
12708 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
12710 fixP
->fx_addsy
= section_symbol (text_section
);
12711 *valP
+= md_pcrel_from (fixP
);
12712 md_number_to_chars ((char *) buf
, insn
, 4);
12716 /* If we got here, we have branch-relaxation disabled,
12717 and there's nothing we can do to fix this instruction
12718 without turning it into a longer sequence. */
12719 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
12720 _("Branch out of range"));
12724 case BFD_RELOC_VTABLE_INHERIT
:
12727 && !S_IS_DEFINED (fixP
->fx_addsy
)
12728 && !S_IS_WEAK (fixP
->fx_addsy
))
12729 S_SET_WEAK (fixP
->fx_addsy
);
12732 case BFD_RELOC_VTABLE_ENTRY
:
12740 /* Remember value for tc_gen_reloc. */
12741 fixP
->fx_addnumber
= *valP
;
12751 name
= input_line_pointer
;
12752 c
= get_symbol_end ();
12753 p
= (symbolS
*) symbol_find_or_make (name
);
12754 *input_line_pointer
= c
;
12758 /* Align the current frag to a given power of two. If a particular
12759 fill byte should be used, FILL points to an integer that contains
12760 that byte, otherwise FILL is null.
12762 The MIPS assembler also automatically adjusts any preceding
12766 mips_align (int to
, int *fill
, symbolS
*label
)
12768 mips_emit_delays ();
12769 mips_record_mips16_mode ();
12770 if (fill
== NULL
&& subseg_text_p (now_seg
))
12771 frag_align_code (to
, 0);
12773 frag_align (to
, fill
? *fill
: 0, 0);
12774 record_alignment (now_seg
, to
);
12777 gas_assert (S_GET_SEGMENT (label
) == now_seg
);
12778 symbol_set_frag (label
, frag_now
);
12779 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
12783 /* Align to a given power of two. .align 0 turns off the automatic
12784 alignment used by the data creating pseudo-ops. */
12787 s_align (int x ATTRIBUTE_UNUSED
)
12789 int temp
, fill_value
, *fill_ptr
;
12790 long max_alignment
= 28;
12792 /* o Note that the assembler pulls down any immediately preceding label
12793 to the aligned address.
12794 o It's not documented but auto alignment is reinstated by
12795 a .align pseudo instruction.
12796 o Note also that after auto alignment is turned off the mips assembler
12797 issues an error on attempt to assemble an improperly aligned data item.
12800 temp
= get_absolute_expression ();
12801 if (temp
> max_alignment
)
12802 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
12805 as_warn (_("Alignment negative: 0 assumed."));
12808 if (*input_line_pointer
== ',')
12810 ++input_line_pointer
;
12811 fill_value
= get_absolute_expression ();
12812 fill_ptr
= &fill_value
;
12818 segment_info_type
*si
= seg_info (now_seg
);
12819 struct insn_label_list
*l
= si
->label_list
;
12820 /* Auto alignment should be switched on by next section change. */
12822 mips_align (temp
, fill_ptr
, l
!= NULL
? l
->label
: NULL
);
12829 demand_empty_rest_of_line ();
12833 s_change_sec (int sec
)
12838 /* The ELF backend needs to know that we are changing sections, so
12839 that .previous works correctly. We could do something like check
12840 for an obj_section_change_hook macro, but that might be confusing
12841 as it would not be appropriate to use it in the section changing
12842 functions in read.c, since obj-elf.c intercepts those. FIXME:
12843 This should be cleaner, somehow. */
12845 obj_elf_section_change_hook ();
12848 mips_emit_delays ();
12859 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
12860 demand_empty_rest_of_line ();
12864 seg
= subseg_new (RDATA_SECTION_NAME
,
12865 (subsegT
) get_absolute_expression ());
12868 bfd_set_section_flags (stdoutput
, seg
, (SEC_ALLOC
| SEC_LOAD
12869 | SEC_READONLY
| SEC_RELOC
12871 if (strncmp (TARGET_OS
, "elf", 3) != 0)
12872 record_alignment (seg
, 4);
12874 demand_empty_rest_of_line ();
12878 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
12881 bfd_set_section_flags (stdoutput
, seg
,
12882 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
12883 if (strncmp (TARGET_OS
, "elf", 3) != 0)
12884 record_alignment (seg
, 4);
12886 demand_empty_rest_of_line ();
12890 seg
= subseg_new (".sbss", (subsegT
) get_absolute_expression ());
12893 bfd_set_section_flags (stdoutput
, seg
, SEC_ALLOC
);
12894 if (strncmp (TARGET_OS
, "elf", 3) != 0)
12895 record_alignment (seg
, 4);
12897 demand_empty_rest_of_line ();
12905 s_change_section (int ignore ATTRIBUTE_UNUSED
)
12908 char *section_name
;
12913 int section_entry_size
;
12914 int section_alignment
;
12919 section_name
= input_line_pointer
;
12920 c
= get_symbol_end ();
12922 next_c
= *(input_line_pointer
+ 1);
12924 /* Do we have .section Name<,"flags">? */
12925 if (c
!= ',' || (c
== ',' && next_c
== '"'))
12927 /* just after name is now '\0'. */
12928 *input_line_pointer
= c
;
12929 input_line_pointer
= section_name
;
12930 obj_elf_section (ignore
);
12933 input_line_pointer
++;
12935 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
12937 section_type
= get_absolute_expression ();
12940 if (*input_line_pointer
++ == ',')
12941 section_flag
= get_absolute_expression ();
12944 if (*input_line_pointer
++ == ',')
12945 section_entry_size
= get_absolute_expression ();
12947 section_entry_size
= 0;
12948 if (*input_line_pointer
++ == ',')
12949 section_alignment
= get_absolute_expression ();
12951 section_alignment
= 0;
12952 /* FIXME: really ignore? */
12953 (void) section_alignment
;
12955 section_name
= xstrdup (section_name
);
12957 /* When using the generic form of .section (as implemented by obj-elf.c),
12958 there's no way to set the section type to SHT_MIPS_DWARF. Users have
12959 traditionally had to fall back on the more common @progbits instead.
12961 There's nothing really harmful in this, since bfd will correct
12962 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
12963 means that, for backwards compatibility, the special_section entries
12964 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
12966 Even so, we shouldn't force users of the MIPS .section syntax to
12967 incorrectly label the sections as SHT_PROGBITS. The best compromise
12968 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
12969 generic type-checking code. */
12970 if (section_type
== SHT_MIPS_DWARF
)
12971 section_type
= SHT_PROGBITS
;
12973 obj_elf_change_section (section_name
, section_type
, section_flag
,
12974 section_entry_size
, 0, 0, 0);
12976 if (now_seg
->name
!= section_name
)
12977 free (section_name
);
12978 #endif /* OBJ_ELF */
12982 mips_enable_auto_align (void)
12988 s_cons (int log_size
)
12990 segment_info_type
*si
= seg_info (now_seg
);
12991 struct insn_label_list
*l
= si
->label_list
;
12994 label
= l
!= NULL
? l
->label
: NULL
;
12995 mips_emit_delays ();
12996 if (log_size
> 0 && auto_align
)
12997 mips_align (log_size
, 0, label
);
12998 cons (1 << log_size
);
12999 mips_clear_insn_labels ();
13003 s_float_cons (int type
)
13005 segment_info_type
*si
= seg_info (now_seg
);
13006 struct insn_label_list
*l
= si
->label_list
;
13009 label
= l
!= NULL
? l
->label
: NULL
;
13011 mips_emit_delays ();
13016 mips_align (3, 0, label
);
13018 mips_align (2, 0, label
);
13022 mips_clear_insn_labels ();
13025 /* Handle .globl. We need to override it because on Irix 5 you are
13028 where foo is an undefined symbol, to mean that foo should be
13029 considered to be the address of a function. */
13032 s_mips_globl (int x ATTRIBUTE_UNUSED
)
13041 name
= input_line_pointer
;
13042 c
= get_symbol_end ();
13043 symbolP
= symbol_find_or_make (name
);
13044 S_SET_EXTERNAL (symbolP
);
13046 *input_line_pointer
= c
;
13047 SKIP_WHITESPACE ();
13049 /* On Irix 5, every global symbol that is not explicitly labelled as
13050 being a function is apparently labelled as being an object. */
13053 if (!is_end_of_line
[(unsigned char) *input_line_pointer
]
13054 && (*input_line_pointer
!= ','))
13059 secname
= input_line_pointer
;
13060 c
= get_symbol_end ();
13061 sec
= bfd_get_section_by_name (stdoutput
, secname
);
13063 as_bad (_("%s: no such section"), secname
);
13064 *input_line_pointer
= c
;
13066 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
13067 flag
= BSF_FUNCTION
;
13070 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
13072 c
= *input_line_pointer
;
13075 input_line_pointer
++;
13076 SKIP_WHITESPACE ();
13077 if (is_end_of_line
[(unsigned char) *input_line_pointer
])
13083 demand_empty_rest_of_line ();
13087 s_option (int x ATTRIBUTE_UNUSED
)
13092 opt
= input_line_pointer
;
13093 c
= get_symbol_end ();
13097 /* FIXME: What does this mean? */
13099 else if (strncmp (opt
, "pic", 3) == 0)
13103 i
= atoi (opt
+ 3);
13108 mips_pic
= SVR4_PIC
;
13109 mips_abicalls
= TRUE
;
13112 as_bad (_(".option pic%d not supported"), i
);
13114 if (mips_pic
== SVR4_PIC
)
13116 if (g_switch_seen
&& g_switch_value
!= 0)
13117 as_warn (_("-G may not be used with SVR4 PIC code"));
13118 g_switch_value
= 0;
13119 bfd_set_gp_size (stdoutput
, 0);
13123 as_warn (_("Unrecognized option \"%s\""), opt
);
13125 *input_line_pointer
= c
;
13126 demand_empty_rest_of_line ();
13129 /* This structure is used to hold a stack of .set values. */
13131 struct mips_option_stack
13133 struct mips_option_stack
*next
;
13134 struct mips_set_options options
;
13137 static struct mips_option_stack
*mips_opts_stack
;
13139 /* Handle the .set pseudo-op. */
13142 s_mipsset (int x ATTRIBUTE_UNUSED
)
13144 char *name
= input_line_pointer
, ch
;
13146 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
13147 ++input_line_pointer
;
13148 ch
= *input_line_pointer
;
13149 *input_line_pointer
= '\0';
13151 if (strcmp (name
, "reorder") == 0)
13153 if (mips_opts
.noreorder
)
13156 else if (strcmp (name
, "noreorder") == 0)
13158 if (!mips_opts
.noreorder
)
13159 start_noreorder ();
13161 else if (strncmp (name
, "at=", 3) == 0)
13163 char *s
= name
+ 3;
13165 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, &mips_opts
.at
))
13166 as_bad (_("Unrecognized register name `%s'"), s
);
13168 else if (strcmp (name
, "at") == 0)
13170 mips_opts
.at
= ATREG
;
13172 else if (strcmp (name
, "noat") == 0)
13174 mips_opts
.at
= ZERO
;
13176 else if (strcmp (name
, "macro") == 0)
13178 mips_opts
.warn_about_macros
= 0;
13180 else if (strcmp (name
, "nomacro") == 0)
13182 if (mips_opts
.noreorder
== 0)
13183 as_bad (_("`noreorder' must be set before `nomacro'"));
13184 mips_opts
.warn_about_macros
= 1;
13186 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
13188 mips_opts
.nomove
= 0;
13190 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
13192 mips_opts
.nomove
= 1;
13194 else if (strcmp (name
, "bopt") == 0)
13196 mips_opts
.nobopt
= 0;
13198 else if (strcmp (name
, "nobopt") == 0)
13200 mips_opts
.nobopt
= 1;
13202 else if (strcmp (name
, "gp=default") == 0)
13203 mips_opts
.gp32
= file_mips_gp32
;
13204 else if (strcmp (name
, "gp=32") == 0)
13205 mips_opts
.gp32
= 1;
13206 else if (strcmp (name
, "gp=64") == 0)
13208 if (!ISA_HAS_64BIT_REGS (mips_opts
.isa
))
13209 as_warn (_("%s isa does not support 64-bit registers"),
13210 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
13211 mips_opts
.gp32
= 0;
13213 else if (strcmp (name
, "fp=default") == 0)
13214 mips_opts
.fp32
= file_mips_fp32
;
13215 else if (strcmp (name
, "fp=32") == 0)
13216 mips_opts
.fp32
= 1;
13217 else if (strcmp (name
, "fp=64") == 0)
13219 if (!ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
13220 as_warn (_("%s isa does not support 64-bit floating point registers"),
13221 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
13222 mips_opts
.fp32
= 0;
13224 else if (strcmp (name
, "softfloat") == 0)
13225 mips_opts
.soft_float
= 1;
13226 else if (strcmp (name
, "hardfloat") == 0)
13227 mips_opts
.soft_float
= 0;
13228 else if (strcmp (name
, "singlefloat") == 0)
13229 mips_opts
.single_float
= 1;
13230 else if (strcmp (name
, "doublefloat") == 0)
13231 mips_opts
.single_float
= 0;
13232 else if (strcmp (name
, "mips16") == 0
13233 || strcmp (name
, "MIPS-16") == 0)
13234 mips_opts
.mips16
= 1;
13235 else if (strcmp (name
, "nomips16") == 0
13236 || strcmp (name
, "noMIPS-16") == 0)
13237 mips_opts
.mips16
= 0;
13238 else if (strcmp (name
, "smartmips") == 0)
13240 if (!ISA_SUPPORTS_SMARTMIPS
)
13241 as_warn (_("%s ISA does not support SmartMIPS ASE"),
13242 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
13243 mips_opts
.ase_smartmips
= 1;
13245 else if (strcmp (name
, "nosmartmips") == 0)
13246 mips_opts
.ase_smartmips
= 0;
13247 else if (strcmp (name
, "mips3d") == 0)
13248 mips_opts
.ase_mips3d
= 1;
13249 else if (strcmp (name
, "nomips3d") == 0)
13250 mips_opts
.ase_mips3d
= 0;
13251 else if (strcmp (name
, "mdmx") == 0)
13252 mips_opts
.ase_mdmx
= 1;
13253 else if (strcmp (name
, "nomdmx") == 0)
13254 mips_opts
.ase_mdmx
= 0;
13255 else if (strcmp (name
, "dsp") == 0)
13257 if (!ISA_SUPPORTS_DSP_ASE
)
13258 as_warn (_("%s ISA does not support DSP ASE"),
13259 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
13260 mips_opts
.ase_dsp
= 1;
13261 mips_opts
.ase_dspr2
= 0;
13263 else if (strcmp (name
, "nodsp") == 0)
13265 mips_opts
.ase_dsp
= 0;
13266 mips_opts
.ase_dspr2
= 0;
13268 else if (strcmp (name
, "dspr2") == 0)
13270 if (!ISA_SUPPORTS_DSPR2_ASE
)
13271 as_warn (_("%s ISA does not support DSP R2 ASE"),
13272 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
13273 mips_opts
.ase_dspr2
= 1;
13274 mips_opts
.ase_dsp
= 1;
13276 else if (strcmp (name
, "nodspr2") == 0)
13278 mips_opts
.ase_dspr2
= 0;
13279 mips_opts
.ase_dsp
= 0;
13281 else if (strcmp (name
, "mt") == 0)
13283 if (!ISA_SUPPORTS_MT_ASE
)
13284 as_warn (_("%s ISA does not support MT ASE"),
13285 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
13286 mips_opts
.ase_mt
= 1;
13288 else if (strcmp (name
, "nomt") == 0)
13289 mips_opts
.ase_mt
= 0;
13290 else if (strncmp (name
, "mips", 4) == 0 || strncmp (name
, "arch=", 5) == 0)
13294 /* Permit the user to change the ISA and architecture on the fly.
13295 Needless to say, misuse can cause serious problems. */
13296 if (strcmp (name
, "mips0") == 0 || strcmp (name
, "arch=default") == 0)
13299 mips_opts
.isa
= file_mips_isa
;
13300 mips_opts
.arch
= file_mips_arch
;
13302 else if (strncmp (name
, "arch=", 5) == 0)
13304 const struct mips_cpu_info
*p
;
13306 p
= mips_parse_cpu("internal use", name
+ 5);
13308 as_bad (_("unknown architecture %s"), name
+ 5);
13311 mips_opts
.arch
= p
->cpu
;
13312 mips_opts
.isa
= p
->isa
;
13315 else if (strncmp (name
, "mips", 4) == 0)
13317 const struct mips_cpu_info
*p
;
13319 p
= mips_parse_cpu("internal use", name
);
13321 as_bad (_("unknown ISA level %s"), name
+ 4);
13324 mips_opts
.arch
= p
->cpu
;
13325 mips_opts
.isa
= p
->isa
;
13329 as_bad (_("unknown ISA or architecture %s"), name
);
13331 switch (mips_opts
.isa
)
13339 mips_opts
.gp32
= 1;
13340 mips_opts
.fp32
= 1;
13347 mips_opts
.gp32
= 0;
13348 mips_opts
.fp32
= 0;
13351 as_bad (_("unknown ISA level %s"), name
+ 4);
13356 mips_opts
.gp32
= file_mips_gp32
;
13357 mips_opts
.fp32
= file_mips_fp32
;
13360 else if (strcmp (name
, "autoextend") == 0)
13361 mips_opts
.noautoextend
= 0;
13362 else if (strcmp (name
, "noautoextend") == 0)
13363 mips_opts
.noautoextend
= 1;
13364 else if (strcmp (name
, "push") == 0)
13366 struct mips_option_stack
*s
;
13368 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
13369 s
->next
= mips_opts_stack
;
13370 s
->options
= mips_opts
;
13371 mips_opts_stack
= s
;
13373 else if (strcmp (name
, "pop") == 0)
13375 struct mips_option_stack
*s
;
13377 s
= mips_opts_stack
;
13379 as_bad (_(".set pop with no .set push"));
13382 /* If we're changing the reorder mode we need to handle
13383 delay slots correctly. */
13384 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
13385 start_noreorder ();
13386 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
13389 mips_opts
= s
->options
;
13390 mips_opts_stack
= s
->next
;
13394 else if (strcmp (name
, "sym32") == 0)
13395 mips_opts
.sym32
= TRUE
;
13396 else if (strcmp (name
, "nosym32") == 0)
13397 mips_opts
.sym32
= FALSE
;
13398 else if (strchr (name
, ','))
13400 /* Generic ".set" directive; use the generic handler. */
13401 *input_line_pointer
= ch
;
13402 input_line_pointer
= name
;
13408 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
13410 *input_line_pointer
= ch
;
13411 demand_empty_rest_of_line ();
13414 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
13415 .option pic2. It means to generate SVR4 PIC calls. */
13418 s_abicalls (int ignore ATTRIBUTE_UNUSED
)
13420 mips_pic
= SVR4_PIC
;
13421 mips_abicalls
= TRUE
;
13423 if (g_switch_seen
&& g_switch_value
!= 0)
13424 as_warn (_("-G may not be used with SVR4 PIC code"));
13425 g_switch_value
= 0;
13427 bfd_set_gp_size (stdoutput
, 0);
13428 demand_empty_rest_of_line ();
13431 /* Handle the .cpload pseudo-op. This is used when generating SVR4
13432 PIC code. It sets the $gp register for the function based on the
13433 function address, which is in the register named in the argument.
13434 This uses a relocation against _gp_disp, which is handled specially
13435 by the linker. The result is:
13436 lui $gp,%hi(_gp_disp)
13437 addiu $gp,$gp,%lo(_gp_disp)
13438 addu $gp,$gp,.cpload argument
13439 The .cpload argument is normally $25 == $t9.
13441 The -mno-shared option changes this to:
13442 lui $gp,%hi(__gnu_local_gp)
13443 addiu $gp,$gp,%lo(__gnu_local_gp)
13444 and the argument is ignored. This saves an instruction, but the
13445 resulting code is not position independent; it uses an absolute
13446 address for __gnu_local_gp. Thus code assembled with -mno-shared
13447 can go into an ordinary executable, but not into a shared library. */
13450 s_cpload (int ignore ATTRIBUTE_UNUSED
)
13456 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
13457 .cpload is ignored. */
13458 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
13464 /* .cpload should be in a .set noreorder section. */
13465 if (mips_opts
.noreorder
== 0)
13466 as_warn (_(".cpload not in noreorder section"));
13468 reg
= tc_get_register (0);
13470 /* If we need to produce a 64-bit address, we are better off using
13471 the default instruction sequence. */
13472 in_shared
= mips_in_shared
|| HAVE_64BIT_SYMBOLS
;
13474 ex
.X_op
= O_symbol
;
13475 ex
.X_add_symbol
= symbol_find_or_make (in_shared
? "_gp_disp" :
13477 ex
.X_op_symbol
= NULL
;
13478 ex
.X_add_number
= 0;
13480 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
13481 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
13484 macro_build_lui (&ex
, mips_gp_register
);
13485 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
13486 mips_gp_register
, BFD_RELOC_LO16
);
13488 macro_build (NULL
, "addu", "d,v,t", mips_gp_register
,
13489 mips_gp_register
, reg
);
13492 demand_empty_rest_of_line ();
13495 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
13496 .cpsetup $reg1, offset|$reg2, label
13498 If offset is given, this results in:
13499 sd $gp, offset($sp)
13500 lui $gp, %hi(%neg(%gp_rel(label)))
13501 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
13502 daddu $gp, $gp, $reg1
13504 If $reg2 is given, this results in:
13505 daddu $reg2, $gp, $0
13506 lui $gp, %hi(%neg(%gp_rel(label)))
13507 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
13508 daddu $gp, $gp, $reg1
13509 $reg1 is normally $25 == $t9.
13511 The -mno-shared option replaces the last three instructions with
13513 addiu $gp,$gp,%lo(_gp) */
13516 s_cpsetup (int ignore ATTRIBUTE_UNUSED
)
13518 expressionS ex_off
;
13519 expressionS ex_sym
;
13522 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
13523 We also need NewABI support. */
13524 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
13530 reg1
= tc_get_register (0);
13531 SKIP_WHITESPACE ();
13532 if (*input_line_pointer
!= ',')
13534 as_bad (_("missing argument separator ',' for .cpsetup"));
13538 ++input_line_pointer
;
13539 SKIP_WHITESPACE ();
13540 if (*input_line_pointer
== '$')
13542 mips_cpreturn_register
= tc_get_register (0);
13543 mips_cpreturn_offset
= -1;
13547 mips_cpreturn_offset
= get_absolute_expression ();
13548 mips_cpreturn_register
= -1;
13550 SKIP_WHITESPACE ();
13551 if (*input_line_pointer
!= ',')
13553 as_bad (_("missing argument separator ',' for .cpsetup"));
13557 ++input_line_pointer
;
13558 SKIP_WHITESPACE ();
13559 expression (&ex_sym
);
13562 if (mips_cpreturn_register
== -1)
13564 ex_off
.X_op
= O_constant
;
13565 ex_off
.X_add_symbol
= NULL
;
13566 ex_off
.X_op_symbol
= NULL
;
13567 ex_off
.X_add_number
= mips_cpreturn_offset
;
13569 macro_build (&ex_off
, "sd", "t,o(b)", mips_gp_register
,
13570 BFD_RELOC_LO16
, SP
);
13573 macro_build (NULL
, "daddu", "d,v,t", mips_cpreturn_register
,
13574 mips_gp_register
, 0);
13576 if (mips_in_shared
|| HAVE_64BIT_SYMBOLS
)
13578 macro_build (&ex_sym
, "lui", "t,u", mips_gp_register
,
13579 -1, BFD_RELOC_GPREL16
, BFD_RELOC_MIPS_SUB
,
13582 macro_build (&ex_sym
, "addiu", "t,r,j", mips_gp_register
,
13583 mips_gp_register
, -1, BFD_RELOC_GPREL16
,
13584 BFD_RELOC_MIPS_SUB
, BFD_RELOC_LO16
);
13586 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", mips_gp_register
,
13587 mips_gp_register
, reg1
);
13593 ex
.X_op
= O_symbol
;
13594 ex
.X_add_symbol
= symbol_find_or_make ("__gnu_local_gp");
13595 ex
.X_op_symbol
= NULL
;
13596 ex
.X_add_number
= 0;
13598 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
13599 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
13601 macro_build_lui (&ex
, mips_gp_register
);
13602 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
13603 mips_gp_register
, BFD_RELOC_LO16
);
13608 demand_empty_rest_of_line ();
13612 s_cplocal (int ignore ATTRIBUTE_UNUSED
)
13614 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
13615 .cplocal is ignored. */
13616 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
13622 mips_gp_register
= tc_get_register (0);
13623 demand_empty_rest_of_line ();
13626 /* Handle the .cprestore pseudo-op. This stores $gp into a given
13627 offset from $sp. The offset is remembered, and after making a PIC
13628 call $gp is restored from that location. */
13631 s_cprestore (int ignore ATTRIBUTE_UNUSED
)
13635 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
13636 .cprestore is ignored. */
13637 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
13643 mips_cprestore_offset
= get_absolute_expression ();
13644 mips_cprestore_valid
= 1;
13646 ex
.X_op
= O_constant
;
13647 ex
.X_add_symbol
= NULL
;
13648 ex
.X_op_symbol
= NULL
;
13649 ex
.X_add_number
= mips_cprestore_offset
;
13652 macro_build_ldst_constoffset (&ex
, ADDRESS_STORE_INSN
, mips_gp_register
,
13653 SP
, HAVE_64BIT_ADDRESSES
);
13656 demand_empty_rest_of_line ();
13659 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
13660 was given in the preceding .cpsetup, it results in:
13661 ld $gp, offset($sp)
13663 If a register $reg2 was given there, it results in:
13664 daddu $gp, $reg2, $0 */
13667 s_cpreturn (int ignore ATTRIBUTE_UNUSED
)
13671 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
13672 We also need NewABI support. */
13673 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
13680 if (mips_cpreturn_register
== -1)
13682 ex
.X_op
= O_constant
;
13683 ex
.X_add_symbol
= NULL
;
13684 ex
.X_op_symbol
= NULL
;
13685 ex
.X_add_number
= mips_cpreturn_offset
;
13687 macro_build (&ex
, "ld", "t,o(b)", mips_gp_register
, BFD_RELOC_LO16
, SP
);
13690 macro_build (NULL
, "daddu", "d,v,t", mips_gp_register
,
13691 mips_cpreturn_register
, 0);
13694 demand_empty_rest_of_line ();
13697 /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate
13698 a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for
13699 use in DWARF debug information. */
13702 s_dtprel_internal (size_t bytes
)
13709 if (ex
.X_op
!= O_symbol
)
13711 as_bad (_("Unsupported use of %s"), (bytes
== 8
13714 ignore_rest_of_line ();
13717 p
= frag_more (bytes
);
13718 md_number_to_chars (p
, 0, bytes
);
13719 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, FALSE
,
13721 ? BFD_RELOC_MIPS_TLS_DTPREL64
13722 : BFD_RELOC_MIPS_TLS_DTPREL32
));
13724 demand_empty_rest_of_line ();
13727 /* Handle .dtprelword. */
13730 s_dtprelword (int ignore ATTRIBUTE_UNUSED
)
13732 s_dtprel_internal (4);
13735 /* Handle .dtpreldword. */
13738 s_dtpreldword (int ignore ATTRIBUTE_UNUSED
)
13740 s_dtprel_internal (8);
13743 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
13744 code. It sets the offset to use in gp_rel relocations. */
13747 s_gpvalue (int ignore ATTRIBUTE_UNUSED
)
13749 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
13750 We also need NewABI support. */
13751 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
13757 mips_gprel_offset
= get_absolute_expression ();
13759 demand_empty_rest_of_line ();
13762 /* Handle the .gpword pseudo-op. This is used when generating PIC
13763 code. It generates a 32 bit GP relative reloc. */
13766 s_gpword (int ignore ATTRIBUTE_UNUSED
)
13768 segment_info_type
*si
;
13769 struct insn_label_list
*l
;
13774 /* When not generating PIC code, this is treated as .word. */
13775 if (mips_pic
!= SVR4_PIC
)
13781 si
= seg_info (now_seg
);
13782 l
= si
->label_list
;
13783 label
= l
!= NULL
? l
->label
: NULL
;
13784 mips_emit_delays ();
13786 mips_align (2, 0, label
);
13789 mips_clear_insn_labels ();
13791 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
13793 as_bad (_("Unsupported use of .gpword"));
13794 ignore_rest_of_line ();
13798 md_number_to_chars (p
, 0, 4);
13799 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
13800 BFD_RELOC_GPREL32
);
13802 demand_empty_rest_of_line ();
13806 s_gpdword (int ignore ATTRIBUTE_UNUSED
)
13808 segment_info_type
*si
;
13809 struct insn_label_list
*l
;
13814 /* When not generating PIC code, this is treated as .dword. */
13815 if (mips_pic
!= SVR4_PIC
)
13821 si
= seg_info (now_seg
);
13822 l
= si
->label_list
;
13823 label
= l
!= NULL
? l
->label
: NULL
;
13824 mips_emit_delays ();
13826 mips_align (3, 0, label
);
13829 mips_clear_insn_labels ();
13831 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
13833 as_bad (_("Unsupported use of .gpdword"));
13834 ignore_rest_of_line ();
13838 md_number_to_chars (p
, 0, 8);
13839 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
13840 BFD_RELOC_GPREL32
)->fx_tcbit
= 1;
13842 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
13843 fix_new (frag_now
, p
- frag_now
->fr_literal
, 8, NULL
, 0,
13844 FALSE
, BFD_RELOC_64
)->fx_tcbit
= 1;
13846 demand_empty_rest_of_line ();
13849 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
13850 tables in SVR4 PIC code. */
13853 s_cpadd (int ignore ATTRIBUTE_UNUSED
)
13857 /* This is ignored when not generating SVR4 PIC code. */
13858 if (mips_pic
!= SVR4_PIC
)
13864 /* Add $gp to the register named as an argument. */
13866 reg
= tc_get_register (0);
13867 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", reg
, reg
, mips_gp_register
);
13870 demand_empty_rest_of_line ();
13873 /* Handle the .insn pseudo-op. This marks instruction labels in
13874 mips16 mode. This permits the linker to handle them specially,
13875 such as generating jalx instructions when needed. We also make
13876 them odd for the duration of the assembly, in order to generate the
13877 right sort of code. We will make them even in the adjust_symtab
13878 routine, while leaving them marked. This is convenient for the
13879 debugger and the disassembler. The linker knows to make them odd
13883 s_insn (int ignore ATTRIBUTE_UNUSED
)
13885 mips16_mark_labels ();
13887 demand_empty_rest_of_line ();
13890 /* Handle a .stabn directive. We need these in order to mark a label
13891 as being a mips16 text label correctly. Sometimes the compiler
13892 will emit a label, followed by a .stabn, and then switch sections.
13893 If the label and .stabn are in mips16 mode, then the label is
13894 really a mips16 text label. */
13897 s_mips_stab (int type
)
13900 mips16_mark_labels ();
13905 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
13908 s_mips_weakext (int ignore ATTRIBUTE_UNUSED
)
13915 name
= input_line_pointer
;
13916 c
= get_symbol_end ();
13917 symbolP
= symbol_find_or_make (name
);
13918 S_SET_WEAK (symbolP
);
13919 *input_line_pointer
= c
;
13921 SKIP_WHITESPACE ();
13923 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
13925 if (S_IS_DEFINED (symbolP
))
13927 as_bad (_("ignoring attempt to redefine symbol %s"),
13928 S_GET_NAME (symbolP
));
13929 ignore_rest_of_line ();
13933 if (*input_line_pointer
== ',')
13935 ++input_line_pointer
;
13936 SKIP_WHITESPACE ();
13940 if (exp
.X_op
!= O_symbol
)
13942 as_bad (_("bad .weakext directive"));
13943 ignore_rest_of_line ();
13946 symbol_set_value_expression (symbolP
, &exp
);
13949 demand_empty_rest_of_line ();
13952 /* Parse a register string into a number. Called from the ECOFF code
13953 to parse .frame. The argument is non-zero if this is the frame
13954 register, so that we can record it in mips_frame_reg. */
13957 tc_get_register (int frame
)
13961 SKIP_WHITESPACE ();
13962 if (! reg_lookup (&input_line_pointer
, RWARN
| RTYPE_NUM
| RTYPE_GP
, ®
))
13966 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
13967 mips_frame_reg_valid
= 1;
13968 mips_cprestore_valid
= 0;
13974 md_section_align (asection
*seg
, valueT addr
)
13976 int align
= bfd_get_section_alignment (stdoutput
, seg
);
13980 /* We don't need to align ELF sections to the full alignment.
13981 However, Irix 5 may prefer that we align them at least to a 16
13982 byte boundary. We don't bother to align the sections if we
13983 are targeted for an embedded system. */
13984 if (strncmp (TARGET_OS
, "elf", 3) == 0)
13990 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
13993 /* Utility routine, called from above as well. If called while the
13994 input file is still being read, it's only an approximation. (For
13995 example, a symbol may later become defined which appeared to be
13996 undefined earlier.) */
13999 nopic_need_relax (symbolS
*sym
, int before_relaxing
)
14004 if (g_switch_value
> 0)
14006 const char *symname
;
14009 /* Find out whether this symbol can be referenced off the $gp
14010 register. It can be if it is smaller than the -G size or if
14011 it is in the .sdata or .sbss section. Certain symbols can
14012 not be referenced off the $gp, although it appears as though
14014 symname
= S_GET_NAME (sym
);
14015 if (symname
!= (const char *) NULL
14016 && (strcmp (symname
, "eprol") == 0
14017 || strcmp (symname
, "etext") == 0
14018 || strcmp (symname
, "_gp") == 0
14019 || strcmp (symname
, "edata") == 0
14020 || strcmp (symname
, "_fbss") == 0
14021 || strcmp (symname
, "_fdata") == 0
14022 || strcmp (symname
, "_ftext") == 0
14023 || strcmp (symname
, "end") == 0
14024 || strcmp (symname
, "_gp_disp") == 0))
14026 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
14028 #ifndef NO_ECOFF_DEBUGGING
14029 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
14030 && (symbol_get_obj (sym
)->ecoff_extern_size
14031 <= g_switch_value
))
14033 /* We must defer this decision until after the whole
14034 file has been read, since there might be a .extern
14035 after the first use of this symbol. */
14036 || (before_relaxing
14037 #ifndef NO_ECOFF_DEBUGGING
14038 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
14040 && S_GET_VALUE (sym
) == 0)
14041 || (S_GET_VALUE (sym
) != 0
14042 && S_GET_VALUE (sym
) <= g_switch_value
)))
14046 const char *segname
;
14048 segname
= segment_name (S_GET_SEGMENT (sym
));
14049 gas_assert (strcmp (segname
, ".lit8") != 0
14050 && strcmp (segname
, ".lit4") != 0);
14051 change
= (strcmp (segname
, ".sdata") != 0
14052 && strcmp (segname
, ".sbss") != 0
14053 && strncmp (segname
, ".sdata.", 7) != 0
14054 && strncmp (segname
, ".sbss.", 6) != 0
14055 && strncmp (segname
, ".gnu.linkonce.sb.", 17) != 0
14056 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
14061 /* We are not optimizing for the $gp register. */
14066 /* Return true if the given symbol should be considered local for SVR4 PIC. */
14069 pic_need_relax (symbolS
*sym
, asection
*segtype
)
14073 /* Handle the case of a symbol equated to another symbol. */
14074 while (symbol_equated_reloc_p (sym
))
14078 /* It's possible to get a loop here in a badly written program. */
14079 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
14085 if (symbol_section_p (sym
))
14088 symsec
= S_GET_SEGMENT (sym
);
14090 /* This must duplicate the test in adjust_reloc_syms. */
14091 return (symsec
!= &bfd_und_section
14092 && symsec
!= &bfd_abs_section
14093 && !bfd_is_com_section (symsec
)
14094 && !s_is_linkonce (sym
, segtype
)
14096 /* A global or weak symbol is treated as external. */
14097 && (!IS_ELF
|| (! S_IS_WEAK (sym
) && ! S_IS_EXTERNAL (sym
)))
14103 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
14104 extended opcode. SEC is the section the frag is in. */
14107 mips16_extended_frag (fragS
*fragp
, asection
*sec
, long stretch
)
14110 const struct mips16_immed_operand
*op
;
14112 int mintiny
, maxtiny
;
14116 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
14118 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
14121 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
14122 op
= mips16_immed_operands
;
14123 while (op
->type
!= type
)
14126 gas_assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
14131 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
14134 maxtiny
= 1 << op
->nbits
;
14139 maxtiny
= (1 << op
->nbits
) - 1;
14144 mintiny
= - (1 << (op
->nbits
- 1));
14145 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
14148 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
14149 val
= S_GET_VALUE (fragp
->fr_symbol
);
14150 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
14156 /* We won't have the section when we are called from
14157 mips_relax_frag. However, we will always have been called
14158 from md_estimate_size_before_relax first. If this is a
14159 branch to a different section, we mark it as such. If SEC is
14160 NULL, and the frag is not marked, then it must be a branch to
14161 the same section. */
14164 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
14169 /* Must have been called from md_estimate_size_before_relax. */
14172 fragp
->fr_subtype
=
14173 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
14175 /* FIXME: We should support this, and let the linker
14176 catch branches and loads that are out of range. */
14177 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
14178 _("unsupported PC relative reference to different section"));
14182 if (fragp
!= sym_frag
&& sym_frag
->fr_address
== 0)
14183 /* Assume non-extended on the first relaxation pass.
14184 The address we have calculated will be bogus if this is
14185 a forward branch to another frag, as the forward frag
14186 will have fr_address == 0. */
14190 /* In this case, we know for sure that the symbol fragment is in
14191 the same section. If the relax_marker of the symbol fragment
14192 differs from the relax_marker of this fragment, we have not
14193 yet adjusted the symbol fragment fr_address. We want to add
14194 in STRETCH in order to get a better estimate of the address.
14195 This particularly matters because of the shift bits. */
14197 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
14201 /* Adjust stretch for any alignment frag. Note that if have
14202 been expanding the earlier code, the symbol may be
14203 defined in what appears to be an earlier frag. FIXME:
14204 This doesn't handle the fr_subtype field, which specifies
14205 a maximum number of bytes to skip when doing an
14207 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
14209 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
14212 stretch
= - ((- stretch
)
14213 & ~ ((1 << (int) f
->fr_offset
) - 1));
14215 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
14224 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
14226 /* The base address rules are complicated. The base address of
14227 a branch is the following instruction. The base address of a
14228 PC relative load or add is the instruction itself, but if it
14229 is in a delay slot (in which case it can not be extended) use
14230 the address of the instruction whose delay slot it is in. */
14231 if (type
== 'p' || type
== 'q')
14235 /* If we are currently assuming that this frag should be
14236 extended, then, the current address is two bytes
14238 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
14241 /* Ignore the low bit in the target, since it will be set
14242 for a text label. */
14243 if ((val
& 1) != 0)
14246 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
14248 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
14251 val
-= addr
& ~ ((1 << op
->shift
) - 1);
14253 /* Branch offsets have an implicit 0 in the lowest bit. */
14254 if (type
== 'p' || type
== 'q')
14257 /* If any of the shifted bits are set, we must use an extended
14258 opcode. If the address depends on the size of this
14259 instruction, this can lead to a loop, so we arrange to always
14260 use an extended opcode. We only check this when we are in
14261 the main relaxation loop, when SEC is NULL. */
14262 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
14264 fragp
->fr_subtype
=
14265 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
14269 /* If we are about to mark a frag as extended because the value
14270 is precisely maxtiny + 1, then there is a chance of an
14271 infinite loop as in the following code:
14276 In this case when the la is extended, foo is 0x3fc bytes
14277 away, so the la can be shrunk, but then foo is 0x400 away, so
14278 the la must be extended. To avoid this loop, we mark the
14279 frag as extended if it was small, and is about to become
14280 extended with a value of maxtiny + 1. */
14281 if (val
== ((maxtiny
+ 1) << op
->shift
)
14282 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
14285 fragp
->fr_subtype
=
14286 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
14290 else if (symsec
!= absolute_section
&& sec
!= NULL
)
14291 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
14293 if ((val
& ((1 << op
->shift
) - 1)) != 0
14294 || val
< (mintiny
<< op
->shift
)
14295 || val
> (maxtiny
<< op
->shift
))
14301 /* Compute the length of a branch sequence, and adjust the
14302 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
14303 worst-case length is computed, with UPDATE being used to indicate
14304 whether an unconditional (-1), branch-likely (+1) or regular (0)
14305 branch is to be computed. */
14307 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
14309 bfd_boolean toofar
;
14313 && S_IS_DEFINED (fragp
->fr_symbol
)
14314 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
14319 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
14321 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
14325 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
14328 /* If the symbol is not defined or it's in a different segment,
14329 assume the user knows what's going on and emit a short
14335 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
14337 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp
->fr_subtype
),
14338 RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
14339 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
14340 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
14346 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
14349 if (mips_pic
!= NO_PIC
)
14351 /* Additional space for PIC loading of target address. */
14353 if (mips_opts
.isa
== ISA_MIPS1
)
14354 /* Additional space for $at-stabilizing nop. */
14358 /* If branch is conditional. */
14359 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
14366 /* Estimate the size of a frag before relaxing. Unless this is the
14367 mips16, we are not really relaxing here, and the final size is
14368 encoded in the subtype information. For the mips16, we have to
14369 decide whether we are using an extended opcode or not. */
14372 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
14376 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
14379 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
14381 return fragp
->fr_var
;
14384 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
14385 /* We don't want to modify the EXTENDED bit here; it might get us
14386 into infinite loops. We change it only in mips_relax_frag(). */
14387 return (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2);
14389 if (mips_pic
== NO_PIC
)
14390 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
14391 else if (mips_pic
== SVR4_PIC
)
14392 change
= pic_need_relax (fragp
->fr_symbol
, segtype
);
14393 else if (mips_pic
== VXWORKS_PIC
)
14394 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
14401 fragp
->fr_subtype
|= RELAX_USE_SECOND
;
14402 return -RELAX_FIRST (fragp
->fr_subtype
);
14405 return -RELAX_SECOND (fragp
->fr_subtype
);
14408 /* This is called to see whether a reloc against a defined symbol
14409 should be converted into a reloc against a section. */
14412 mips_fix_adjustable (fixS
*fixp
)
14414 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
14415 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
14418 if (fixp
->fx_addsy
== NULL
)
14421 /* If symbol SYM is in a mergeable section, relocations of the form
14422 SYM + 0 can usually be made section-relative. The mergeable data
14423 is then identified by the section offset rather than by the symbol.
14425 However, if we're generating REL LO16 relocations, the offset is split
14426 between the LO16 and parterning high part relocation. The linker will
14427 need to recalculate the complete offset in order to correctly identify
14430 The linker has traditionally not looked for the parterning high part
14431 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
14432 placed anywhere. Rather than break backwards compatibility by changing
14433 this, it seems better not to force the issue, and instead keep the
14434 original symbol. This will work with either linker behavior. */
14435 if ((lo16_reloc_p (fixp
->fx_r_type
)
14436 || reloc_needs_lo_p (fixp
->fx_r_type
))
14437 && HAVE_IN_PLACE_ADDENDS
14438 && (S_GET_SEGMENT (fixp
->fx_addsy
)->flags
& SEC_MERGE
) != 0)
14441 /* There is no place to store an in-place offset for JALR relocations.
14442 Likewise an in-range offset of PC-relative relocations may overflow
14443 the in-place relocatable field if recalculated against the start
14444 address of the symbol's containing section. */
14445 if (HAVE_IN_PLACE_ADDENDS
14446 && (fixp
->fx_pcrel
|| fixp
->fx_r_type
== BFD_RELOC_MIPS_JALR
))
14450 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
14451 to a floating-point stub. The same is true for non-R_MIPS16_26
14452 relocations against MIPS16 functions; in this case, the stub becomes
14453 the function's canonical address.
14455 Floating-point stubs are stored in unique .mips16.call.* or
14456 .mips16.fn.* sections. If a stub T for function F is in section S,
14457 the first relocation in section S must be against F; this is how the
14458 linker determines the target function. All relocations that might
14459 resolve to T must also be against F. We therefore have the following
14460 restrictions, which are given in an intentionally-redundant way:
14462 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
14465 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
14466 if that stub might be used.
14468 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
14471 4. We cannot reduce a stub's relocations against MIPS16 symbols if
14472 that stub might be used.
14474 There is a further restriction:
14476 5. We cannot reduce R_MIPS16_26 relocations against MIPS16 symbols
14477 on targets with in-place addends; the relocation field cannot
14478 encode the low bit.
14480 For simplicity, we deal with (3)-(5) by not reducing _any_ relocation
14481 against a MIPS16 symbol.
14483 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
14484 relocation against some symbol R, no relocation against R may be
14485 reduced. (Note that this deals with (2) as well as (1) because
14486 relocations against global symbols will never be reduced on ELF
14487 targets.) This approach is a little simpler than trying to detect
14488 stub sections, and gives the "all or nothing" per-symbol consistency
14489 that we have for MIPS16 symbols. */
14491 && fixp
->fx_subsy
== NULL
14492 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp
->fx_addsy
))
14493 || *symbol_get_tc (fixp
->fx_addsy
)))
14500 /* Translate internal representation of relocation info to BFD target
14504 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
14506 static arelent
*retval
[4];
14508 bfd_reloc_code_real_type code
;
14510 memset (retval
, 0, sizeof(retval
));
14511 reloc
= retval
[0] = (arelent
*) xcalloc (1, sizeof (arelent
));
14512 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
14513 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
14514 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
14516 if (fixp
->fx_pcrel
)
14518 gas_assert (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
);
14520 /* At this point, fx_addnumber is "symbol offset - pcrel address".
14521 Relocations want only the symbol offset. */
14522 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
14525 /* A gruesome hack which is a result of the gruesome gas
14526 reloc handling. What's worse, for COFF (as opposed to
14527 ECOFF), we might need yet another copy of reloc->address.
14528 See bfd_install_relocation. */
14529 reloc
->addend
+= reloc
->address
;
14533 reloc
->addend
= fixp
->fx_addnumber
;
14535 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
14536 entry to be used in the relocation's section offset. */
14537 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
14539 reloc
->address
= reloc
->addend
;
14543 code
= fixp
->fx_r_type
;
14545 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
14546 if (reloc
->howto
== NULL
)
14548 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14549 _("Can not represent %s relocation in this object file format"),
14550 bfd_get_reloc_code_name (code
));
14557 /* Relax a machine dependent frag. This returns the amount by which
14558 the current size of the frag should change. */
14561 mips_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
14563 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
14565 offsetT old_var
= fragp
->fr_var
;
14567 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
14569 return fragp
->fr_var
- old_var
;
14572 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
14575 if (mips16_extended_frag (fragp
, NULL
, stretch
))
14577 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
14579 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
14584 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
14586 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
14593 /* Convert a machine dependent frag. */
14596 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec
, fragS
*fragp
)
14598 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
14601 unsigned long insn
;
14605 buf
= (bfd_byte
*)fragp
->fr_literal
+ fragp
->fr_fix
;
14607 if (target_big_endian
)
14608 insn
= bfd_getb32 (buf
);
14610 insn
= bfd_getl32 (buf
);
14612 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
14614 /* We generate a fixup instead of applying it right now
14615 because, if there are linker relaxations, we're going to
14616 need the relocations. */
14617 exp
.X_op
= O_symbol
;
14618 exp
.X_add_symbol
= fragp
->fr_symbol
;
14619 exp
.X_add_number
= fragp
->fr_offset
;
14621 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
14622 4, &exp
, TRUE
, BFD_RELOC_16_PCREL_S2
);
14623 fixp
->fx_file
= fragp
->fr_file
;
14624 fixp
->fx_line
= fragp
->fr_line
;
14626 md_number_to_chars ((char *) buf
, insn
, 4);
14633 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
14634 _("Relaxed out-of-range branch into a jump"));
14636 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
14639 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
14641 /* Reverse the branch. */
14642 switch ((insn
>> 28) & 0xf)
14645 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
14646 have the condition reversed by tweaking a single
14647 bit, and their opcodes all have 0x4???????. */
14648 gas_assert ((insn
& 0xf1000000) == 0x41000000);
14649 insn
^= 0x00010000;
14653 /* bltz 0x04000000 bgez 0x04010000
14654 bltzal 0x04100000 bgezal 0x04110000 */
14655 gas_assert ((insn
& 0xfc0e0000) == 0x04000000);
14656 insn
^= 0x00010000;
14660 /* beq 0x10000000 bne 0x14000000
14661 blez 0x18000000 bgtz 0x1c000000 */
14662 insn
^= 0x04000000;
14670 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
14672 /* Clear the and-link bit. */
14673 gas_assert ((insn
& 0xfc1c0000) == 0x04100000);
14675 /* bltzal 0x04100000 bgezal 0x04110000
14676 bltzall 0x04120000 bgezall 0x04130000 */
14677 insn
&= ~0x00100000;
14680 /* Branch over the branch (if the branch was likely) or the
14681 full jump (not likely case). Compute the offset from the
14682 current instruction to branch to. */
14683 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
14687 /* How many bytes in instructions we've already emitted? */
14688 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
14689 /* How many bytes in instructions from here to the end? */
14690 i
= fragp
->fr_var
- i
;
14692 /* Convert to instruction count. */
14694 /* Branch counts from the next instruction. */
14697 /* Branch over the jump. */
14698 md_number_to_chars ((char *) buf
, insn
, 4);
14702 md_number_to_chars ((char *) buf
, 0, 4);
14705 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
14707 /* beql $0, $0, 2f */
14709 /* Compute the PC offset from the current instruction to
14710 the end of the variable frag. */
14711 /* How many bytes in instructions we've already emitted? */
14712 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
14713 /* How many bytes in instructions from here to the end? */
14714 i
= fragp
->fr_var
- i
;
14715 /* Convert to instruction count. */
14717 /* Don't decrement i, because we want to branch over the
14721 md_number_to_chars ((char *) buf
, insn
, 4);
14724 md_number_to_chars ((char *) buf
, 0, 4);
14729 if (mips_pic
== NO_PIC
)
14732 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
14733 ? 0x0c000000 : 0x08000000);
14734 exp
.X_op
= O_symbol
;
14735 exp
.X_add_symbol
= fragp
->fr_symbol
;
14736 exp
.X_add_number
= fragp
->fr_offset
;
14738 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
14739 4, &exp
, FALSE
, BFD_RELOC_MIPS_JMP
);
14740 fixp
->fx_file
= fragp
->fr_file
;
14741 fixp
->fx_line
= fragp
->fr_line
;
14743 md_number_to_chars ((char *) buf
, insn
, 4);
14748 unsigned long at
= RELAX_BRANCH_AT (fragp
->fr_subtype
);
14750 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
14751 insn
= HAVE_64BIT_ADDRESSES
? 0xdf800000 : 0x8f800000;
14752 insn
|= at
<< OP_SH_RT
;
14753 exp
.X_op
= O_symbol
;
14754 exp
.X_add_symbol
= fragp
->fr_symbol
;
14755 exp
.X_add_number
= fragp
->fr_offset
;
14757 if (fragp
->fr_offset
)
14759 exp
.X_add_symbol
= make_expr_symbol (&exp
);
14760 exp
.X_add_number
= 0;
14763 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
14764 4, &exp
, FALSE
, BFD_RELOC_MIPS_GOT16
);
14765 fixp
->fx_file
= fragp
->fr_file
;
14766 fixp
->fx_line
= fragp
->fr_line
;
14768 md_number_to_chars ((char *) buf
, insn
, 4);
14771 if (mips_opts
.isa
== ISA_MIPS1
)
14774 md_number_to_chars ((char *) buf
, 0, 4);
14778 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
14779 insn
= HAVE_64BIT_ADDRESSES
? 0x64000000 : 0x24000000;
14780 insn
|= at
<< OP_SH_RS
| at
<< OP_SH_RT
;
14782 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
14783 4, &exp
, FALSE
, BFD_RELOC_LO16
);
14784 fixp
->fx_file
= fragp
->fr_file
;
14785 fixp
->fx_line
= fragp
->fr_line
;
14787 md_number_to_chars ((char *) buf
, insn
, 4);
14791 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
14795 insn
|= at
<< OP_SH_RS
;
14797 md_number_to_chars ((char *) buf
, insn
, 4);
14802 gas_assert (buf
== (bfd_byte
*)fragp
->fr_literal
14803 + fragp
->fr_fix
+ fragp
->fr_var
);
14805 fragp
->fr_fix
+= fragp
->fr_var
;
14810 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
14813 const struct mips16_immed_operand
*op
;
14814 bfd_boolean small
, ext
;
14817 unsigned long insn
;
14818 bfd_boolean use_extend
;
14819 unsigned short extend
;
14821 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
14822 op
= mips16_immed_operands
;
14823 while (op
->type
!= type
)
14826 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
14837 val
= resolve_symbol_value (fragp
->fr_symbol
);
14842 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
14844 /* The rules for the base address of a PC relative reloc are
14845 complicated; see mips16_extended_frag. */
14846 if (type
== 'p' || type
== 'q')
14851 /* Ignore the low bit in the target, since it will be
14852 set for a text label. */
14853 if ((val
& 1) != 0)
14856 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
14858 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
14861 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
14864 /* Make sure the section winds up with the alignment we have
14867 record_alignment (asec
, op
->shift
);
14871 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
14872 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
14873 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
14874 _("extended instruction in delay slot"));
14876 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
14878 if (target_big_endian
)
14879 insn
= bfd_getb16 (buf
);
14881 insn
= bfd_getl16 (buf
);
14883 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
14884 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
14885 small
, ext
, &insn
, &use_extend
, &extend
);
14889 md_number_to_chars ((char *) buf
, 0xf000 | extend
, 2);
14890 fragp
->fr_fix
+= 2;
14894 md_number_to_chars ((char *) buf
, insn
, 2);
14895 fragp
->fr_fix
+= 2;
14903 first
= RELAX_FIRST (fragp
->fr_subtype
);
14904 second
= RELAX_SECOND (fragp
->fr_subtype
);
14905 fixp
= (fixS
*) fragp
->fr_opcode
;
14907 /* Possibly emit a warning if we've chosen the longer option. */
14908 if (((fragp
->fr_subtype
& RELAX_USE_SECOND
) != 0)
14909 == ((fragp
->fr_subtype
& RELAX_SECOND_LONGER
) != 0))
14911 const char *msg
= macro_warning (fragp
->fr_subtype
);
14913 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
14916 /* Go through all the fixups for the first sequence. Disable them
14917 (by marking them as done) if we're going to use the second
14918 sequence instead. */
14920 && fixp
->fx_frag
== fragp
14921 && fixp
->fx_where
< fragp
->fr_fix
- second
)
14923 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
14925 fixp
= fixp
->fx_next
;
14928 /* Go through the fixups for the second sequence. Disable them if
14929 we're going to use the first sequence, otherwise adjust their
14930 addresses to account for the relaxation. */
14931 while (fixp
&& fixp
->fx_frag
== fragp
)
14933 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
14934 fixp
->fx_where
-= first
;
14937 fixp
= fixp
->fx_next
;
14940 /* Now modify the frag contents. */
14941 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
14945 start
= fragp
->fr_literal
+ fragp
->fr_fix
- first
- second
;
14946 memmove (start
, start
+ first
, second
);
14947 fragp
->fr_fix
-= first
;
14950 fragp
->fr_fix
-= second
;
14956 /* This function is called after the relocs have been generated.
14957 We've been storing mips16 text labels as odd. Here we convert them
14958 back to even for the convenience of the debugger. */
14961 mips_frob_file_after_relocs (void)
14964 unsigned int count
, i
;
14969 syms
= bfd_get_outsymbols (stdoutput
);
14970 count
= bfd_get_symcount (stdoutput
);
14971 for (i
= 0; i
< count
; i
++, syms
++)
14973 if (ELF_ST_IS_MIPS16 (elf_symbol (*syms
)->internal_elf_sym
.st_other
)
14974 && ((*syms
)->value
& 1) != 0)
14976 (*syms
)->value
&= ~1;
14977 /* If the symbol has an odd size, it was probably computed
14978 incorrectly, so adjust that as well. */
14979 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
14980 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
14987 /* This function is called whenever a label is defined, including fake
14988 labels instantiated off the dot special symbol. It is used when
14989 handling branch delays; if a branch has a label, we assume we cannot
14990 move it. This also bumps the value of the symbol by 1 in compressed
14994 mips_record_label (symbolS
*sym
)
14996 segment_info_type
*si
= seg_info (now_seg
);
14997 struct insn_label_list
*l
;
14999 if (free_insn_labels
== NULL
)
15000 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
15003 l
= free_insn_labels
;
15004 free_insn_labels
= l
->next
;
15008 l
->next
= si
->label_list
;
15009 si
->label_list
= l
;
15012 /* This function is called as tc_frob_label() whenever a label is defined
15013 and adds a DWARF-2 record we only want for true labels. */
15016 mips_define_label (symbolS
*sym
)
15018 mips_record_label (sym
);
15020 dwarf2_emit_label (sym
);
15024 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15026 /* Some special processing for a MIPS ELF file. */
15029 mips_elf_final_processing (void)
15031 /* Write out the register information. */
15032 if (mips_abi
!= N64_ABI
)
15036 s
.ri_gprmask
= mips_gprmask
;
15037 s
.ri_cprmask
[0] = mips_cprmask
[0];
15038 s
.ri_cprmask
[1] = mips_cprmask
[1];
15039 s
.ri_cprmask
[2] = mips_cprmask
[2];
15040 s
.ri_cprmask
[3] = mips_cprmask
[3];
15041 /* The gp_value field is set by the MIPS ELF backend. */
15043 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
15044 ((Elf32_External_RegInfo
*)
15045 mips_regmask_frag
));
15049 Elf64_Internal_RegInfo s
;
15051 s
.ri_gprmask
= mips_gprmask
;
15053 s
.ri_cprmask
[0] = mips_cprmask
[0];
15054 s
.ri_cprmask
[1] = mips_cprmask
[1];
15055 s
.ri_cprmask
[2] = mips_cprmask
[2];
15056 s
.ri_cprmask
[3] = mips_cprmask
[3];
15057 /* The gp_value field is set by the MIPS ELF backend. */
15059 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
15060 ((Elf64_External_RegInfo
*)
15061 mips_regmask_frag
));
15064 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
15065 sort of BFD interface for this. */
15066 if (mips_any_noreorder
)
15067 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
15068 if (mips_pic
!= NO_PIC
)
15070 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
15071 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
15074 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
15076 /* Set MIPS ELF flags for ASEs. */
15077 /* We may need to define a new flag for DSP ASE, and set this flag when
15078 file_ase_dsp is true. */
15079 /* Same for DSP R2. */
15080 /* We may need to define a new flag for MT ASE, and set this flag when
15081 file_ase_mt is true. */
15082 if (file_ase_mips16
)
15083 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
15084 #if 0 /* XXX FIXME */
15085 if (file_ase_mips3d
)
15086 elf_elfheader (stdoutput
)->e_flags
|= ???;
15089 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
15091 /* Set the MIPS ELF ABI flags. */
15092 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
15093 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
15094 else if (mips_abi
== O64_ABI
)
15095 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
15096 else if (mips_abi
== EABI_ABI
)
15098 if (!file_mips_gp32
)
15099 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
15101 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
15103 else if (mips_abi
== N32_ABI
)
15104 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
15106 /* Nothing to do for N64_ABI. */
15108 if (mips_32bitmode
)
15109 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
15111 #if 0 /* XXX FIXME */
15112 /* 32 bit code with 64 bit FP registers. */
15113 if (!file_mips_fp32
&& ABI_NEEDS_32BIT_REGS (mips_abi
))
15114 elf_elfheader (stdoutput
)->e_flags
|= ???;
15118 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
15120 typedef struct proc
{
15122 symbolS
*func_end_sym
;
15123 unsigned long reg_mask
;
15124 unsigned long reg_offset
;
15125 unsigned long fpreg_mask
;
15126 unsigned long fpreg_offset
;
15127 unsigned long frame_offset
;
15128 unsigned long frame_reg
;
15129 unsigned long pc_reg
;
15132 static procS cur_proc
;
15133 static procS
*cur_proc_ptr
;
15134 static int numprocs
;
15136 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1" and a normal
15140 mips_nop_opcode (void)
15142 return seg_info (now_seg
)->tc_segment_info_data
.mips16
;
15145 /* Fill in an rs_align_code fragment. This only needs to do something
15146 for MIPS16 code, where 0 is not a nop. */
15149 mips_handle_align (fragS
*fragp
)
15152 int bytes
, size
, excess
;
15155 if (fragp
->fr_type
!= rs_align_code
)
15158 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
15161 opcode
= mips16_nop_insn
.insn_opcode
;
15166 opcode
= nop_insn
.insn_opcode
;
15170 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
15171 excess
= bytes
% size
;
15174 /* If we're not inserting a whole number of instructions,
15175 pad the end of the fixed part of the frag with zeros. */
15176 memset (p
, 0, excess
);
15178 fragp
->fr_fix
+= excess
;
15181 md_number_to_chars (p
, opcode
, size
);
15182 fragp
->fr_var
= size
;
15186 md_obj_begin (void)
15193 /* Check for premature end, nesting errors, etc. */
15195 as_warn (_("missing .end at end of assembly"));
15204 if (*input_line_pointer
== '-')
15206 ++input_line_pointer
;
15209 if (!ISDIGIT (*input_line_pointer
))
15210 as_bad (_("expected simple number"));
15211 if (input_line_pointer
[0] == '0')
15213 if (input_line_pointer
[1] == 'x')
15215 input_line_pointer
+= 2;
15216 while (ISXDIGIT (*input_line_pointer
))
15219 val
|= hex_value (*input_line_pointer
++);
15221 return negative
? -val
: val
;
15225 ++input_line_pointer
;
15226 while (ISDIGIT (*input_line_pointer
))
15229 val
|= *input_line_pointer
++ - '0';
15231 return negative
? -val
: val
;
15234 if (!ISDIGIT (*input_line_pointer
))
15236 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
15237 *input_line_pointer
, *input_line_pointer
);
15238 as_warn (_("invalid number"));
15241 while (ISDIGIT (*input_line_pointer
))
15244 val
+= *input_line_pointer
++ - '0';
15246 return negative
? -val
: val
;
15249 /* The .file directive; just like the usual .file directive, but there
15250 is an initial number which is the ECOFF file index. In the non-ECOFF
15251 case .file implies DWARF-2. */
15254 s_mips_file (int x ATTRIBUTE_UNUSED
)
15256 static int first_file_directive
= 0;
15258 if (ECOFF_DEBUGGING
)
15267 filename
= dwarf2_directive_file (0);
15269 /* Versions of GCC up to 3.1 start files with a ".file"
15270 directive even for stabs output. Make sure that this
15271 ".file" is handled. Note that you need a version of GCC
15272 after 3.1 in order to support DWARF-2 on MIPS. */
15273 if (filename
!= NULL
&& ! first_file_directive
)
15275 (void) new_logical_line (filename
, -1);
15276 s_app_file_string (filename
, 0);
15278 first_file_directive
= 1;
15282 /* The .loc directive, implying DWARF-2. */
15285 s_mips_loc (int x ATTRIBUTE_UNUSED
)
15287 if (!ECOFF_DEBUGGING
)
15288 dwarf2_directive_loc (0);
15291 /* The .end directive. */
15294 s_mips_end (int x ATTRIBUTE_UNUSED
)
15298 /* Following functions need their own .frame and .cprestore directives. */
15299 mips_frame_reg_valid
= 0;
15300 mips_cprestore_valid
= 0;
15302 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
15305 demand_empty_rest_of_line ();
15310 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
15311 as_warn (_(".end not in text section"));
15315 as_warn (_(".end directive without a preceding .ent directive."));
15316 demand_empty_rest_of_line ();
15322 gas_assert (S_GET_NAME (p
));
15323 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->func_sym
)))
15324 as_warn (_(".end symbol does not match .ent symbol."));
15326 if (debug_type
== DEBUG_STABS
)
15327 stabs_generate_asm_endfunc (S_GET_NAME (p
),
15331 as_warn (_(".end directive missing or unknown symbol"));
15334 /* Create an expression to calculate the size of the function. */
15335 if (p
&& cur_proc_ptr
)
15337 OBJ_SYMFIELD_TYPE
*obj
= symbol_get_obj (p
);
15338 expressionS
*exp
= xmalloc (sizeof (expressionS
));
15341 exp
->X_op
= O_subtract
;
15342 exp
->X_add_symbol
= symbol_temp_new_now ();
15343 exp
->X_op_symbol
= p
;
15344 exp
->X_add_number
= 0;
15346 cur_proc_ptr
->func_end_sym
= exp
->X_add_symbol
;
15349 /* Generate a .pdr section. */
15350 if (IS_ELF
&& !ECOFF_DEBUGGING
&& mips_flag_pdr
)
15352 segT saved_seg
= now_seg
;
15353 subsegT saved_subseg
= now_subseg
;
15357 #ifdef md_flush_pending_output
15358 md_flush_pending_output ();
15361 gas_assert (pdr_seg
);
15362 subseg_set (pdr_seg
, 0);
15364 /* Write the symbol. */
15365 exp
.X_op
= O_symbol
;
15366 exp
.X_add_symbol
= p
;
15367 exp
.X_add_number
= 0;
15368 emit_expr (&exp
, 4);
15370 fragp
= frag_more (7 * 4);
15372 md_number_to_chars (fragp
, cur_proc_ptr
->reg_mask
, 4);
15373 md_number_to_chars (fragp
+ 4, cur_proc_ptr
->reg_offset
, 4);
15374 md_number_to_chars (fragp
+ 8, cur_proc_ptr
->fpreg_mask
, 4);
15375 md_number_to_chars (fragp
+ 12, cur_proc_ptr
->fpreg_offset
, 4);
15376 md_number_to_chars (fragp
+ 16, cur_proc_ptr
->frame_offset
, 4);
15377 md_number_to_chars (fragp
+ 20, cur_proc_ptr
->frame_reg
, 4);
15378 md_number_to_chars (fragp
+ 24, cur_proc_ptr
->pc_reg
, 4);
15380 subseg_set (saved_seg
, saved_subseg
);
15382 #endif /* OBJ_ELF */
15384 cur_proc_ptr
= NULL
;
15387 /* The .aent and .ent directives. */
15390 s_mips_ent (int aent
)
15394 symbolP
= get_symbol ();
15395 if (*input_line_pointer
== ',')
15396 ++input_line_pointer
;
15397 SKIP_WHITESPACE ();
15398 if (ISDIGIT (*input_line_pointer
)
15399 || *input_line_pointer
== '-')
15402 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
15403 as_warn (_(".ent or .aent not in text section."));
15405 if (!aent
&& cur_proc_ptr
)
15406 as_warn (_("missing .end"));
15410 /* This function needs its own .frame and .cprestore directives. */
15411 mips_frame_reg_valid
= 0;
15412 mips_cprestore_valid
= 0;
15414 cur_proc_ptr
= &cur_proc
;
15415 memset (cur_proc_ptr
, '\0', sizeof (procS
));
15417 cur_proc_ptr
->func_sym
= symbolP
;
15421 if (debug_type
== DEBUG_STABS
)
15422 stabs_generate_asm_func (S_GET_NAME (symbolP
),
15423 S_GET_NAME (symbolP
));
15426 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
15428 demand_empty_rest_of_line ();
15431 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
15432 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
15433 s_mips_frame is used so that we can set the PDR information correctly.
15434 We can't use the ecoff routines because they make reference to the ecoff
15435 symbol table (in the mdebug section). */
15438 s_mips_frame (int ignore ATTRIBUTE_UNUSED
)
15441 if (IS_ELF
&& !ECOFF_DEBUGGING
)
15445 if (cur_proc_ptr
== (procS
*) NULL
)
15447 as_warn (_(".frame outside of .ent"));
15448 demand_empty_rest_of_line ();
15452 cur_proc_ptr
->frame_reg
= tc_get_register (1);
15454 SKIP_WHITESPACE ();
15455 if (*input_line_pointer
++ != ','
15456 || get_absolute_expression_and_terminator (&val
) != ',')
15458 as_warn (_("Bad .frame directive"));
15459 --input_line_pointer
;
15460 demand_empty_rest_of_line ();
15464 cur_proc_ptr
->frame_offset
= val
;
15465 cur_proc_ptr
->pc_reg
= tc_get_register (0);
15467 demand_empty_rest_of_line ();
15470 #endif /* OBJ_ELF */
15474 /* The .fmask and .mask directives. If the mdebug section is present
15475 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
15476 embedded targets, s_mips_mask is used so that we can set the PDR
15477 information correctly. We can't use the ecoff routines because they
15478 make reference to the ecoff symbol table (in the mdebug section). */
15481 s_mips_mask (int reg_type
)
15484 if (IS_ELF
&& !ECOFF_DEBUGGING
)
15488 if (cur_proc_ptr
== (procS
*) NULL
)
15490 as_warn (_(".mask/.fmask outside of .ent"));
15491 demand_empty_rest_of_line ();
15495 if (get_absolute_expression_and_terminator (&mask
) != ',')
15497 as_warn (_("Bad .mask/.fmask directive"));
15498 --input_line_pointer
;
15499 demand_empty_rest_of_line ();
15503 off
= get_absolute_expression ();
15505 if (reg_type
== 'F')
15507 cur_proc_ptr
->fpreg_mask
= mask
;
15508 cur_proc_ptr
->fpreg_offset
= off
;
15512 cur_proc_ptr
->reg_mask
= mask
;
15513 cur_proc_ptr
->reg_offset
= off
;
15516 demand_empty_rest_of_line ();
15519 #endif /* OBJ_ELF */
15520 s_ignore (reg_type
);
15523 /* A table describing all the processors gas knows about. Names are
15524 matched in the order listed.
15526 To ease comparison, please keep this table in the same order as
15527 gcc's mips_cpu_info_table[]. */
15528 static const struct mips_cpu_info mips_cpu_info_table
[] =
15530 /* Entries for generic ISAs */
15531 { "mips1", MIPS_CPU_IS_ISA
, ISA_MIPS1
, CPU_R3000
},
15532 { "mips2", MIPS_CPU_IS_ISA
, ISA_MIPS2
, CPU_R6000
},
15533 { "mips3", MIPS_CPU_IS_ISA
, ISA_MIPS3
, CPU_R4000
},
15534 { "mips4", MIPS_CPU_IS_ISA
, ISA_MIPS4
, CPU_R8000
},
15535 { "mips5", MIPS_CPU_IS_ISA
, ISA_MIPS5
, CPU_MIPS5
},
15536 { "mips32", MIPS_CPU_IS_ISA
, ISA_MIPS32
, CPU_MIPS32
},
15537 { "mips32r2", MIPS_CPU_IS_ISA
, ISA_MIPS32R2
, CPU_MIPS32R2
},
15538 { "mips64", MIPS_CPU_IS_ISA
, ISA_MIPS64
, CPU_MIPS64
},
15539 { "mips64r2", MIPS_CPU_IS_ISA
, ISA_MIPS64R2
, CPU_MIPS64R2
},
15542 { "r3000", 0, ISA_MIPS1
, CPU_R3000
},
15543 { "r2000", 0, ISA_MIPS1
, CPU_R3000
},
15544 { "r3900", 0, ISA_MIPS1
, CPU_R3900
},
15547 { "r6000", 0, ISA_MIPS2
, CPU_R6000
},
15550 { "r4000", 0, ISA_MIPS3
, CPU_R4000
},
15551 { "r4010", 0, ISA_MIPS2
, CPU_R4010
},
15552 { "vr4100", 0, ISA_MIPS3
, CPU_VR4100
},
15553 { "vr4111", 0, ISA_MIPS3
, CPU_R4111
},
15554 { "vr4120", 0, ISA_MIPS3
, CPU_VR4120
},
15555 { "vr4130", 0, ISA_MIPS3
, CPU_VR4120
},
15556 { "vr4181", 0, ISA_MIPS3
, CPU_R4111
},
15557 { "vr4300", 0, ISA_MIPS3
, CPU_R4300
},
15558 { "r4400", 0, ISA_MIPS3
, CPU_R4400
},
15559 { "r4600", 0, ISA_MIPS3
, CPU_R4600
},
15560 { "orion", 0, ISA_MIPS3
, CPU_R4600
},
15561 { "r4650", 0, ISA_MIPS3
, CPU_R4650
},
15562 /* ST Microelectronics Loongson 2E and 2F cores */
15563 { "loongson2e", 0, ISA_MIPS3
, CPU_LOONGSON_2E
},
15564 { "loongson2f", 0, ISA_MIPS3
, CPU_LOONGSON_2F
},
15567 { "r8000", 0, ISA_MIPS4
, CPU_R8000
},
15568 { "r10000", 0, ISA_MIPS4
, CPU_R10000
},
15569 { "r12000", 0, ISA_MIPS4
, CPU_R12000
},
15570 { "r14000", 0, ISA_MIPS4
, CPU_R14000
},
15571 { "r16000", 0, ISA_MIPS4
, CPU_R16000
},
15572 { "vr5000", 0, ISA_MIPS4
, CPU_R5000
},
15573 { "vr5400", 0, ISA_MIPS4
, CPU_VR5400
},
15574 { "vr5500", 0, ISA_MIPS4
, CPU_VR5500
},
15575 { "rm5200", 0, ISA_MIPS4
, CPU_R5000
},
15576 { "rm5230", 0, ISA_MIPS4
, CPU_R5000
},
15577 { "rm5231", 0, ISA_MIPS4
, CPU_R5000
},
15578 { "rm5261", 0, ISA_MIPS4
, CPU_R5000
},
15579 { "rm5721", 0, ISA_MIPS4
, CPU_R5000
},
15580 { "rm7000", 0, ISA_MIPS4
, CPU_RM7000
},
15581 { "rm9000", 0, ISA_MIPS4
, CPU_RM9000
},
15584 { "4kc", 0, ISA_MIPS32
, CPU_MIPS32
},
15585 { "4km", 0, ISA_MIPS32
, CPU_MIPS32
},
15586 { "4kp", 0, ISA_MIPS32
, CPU_MIPS32
},
15587 { "4ksc", MIPS_CPU_ASE_SMARTMIPS
, ISA_MIPS32
, CPU_MIPS32
},
15589 /* MIPS 32 Release 2 */
15590 { "4kec", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15591 { "4kem", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15592 { "4kep", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15593 { "4ksd", MIPS_CPU_ASE_SMARTMIPS
, ISA_MIPS32R2
, CPU_MIPS32R2
},
15594 { "m4k", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15595 { "m4kp", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15596 { "24kc", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15597 { "24kf2_1", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15598 { "24kf", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15599 { "24kf1_1", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15600 /* Deprecated forms of the above. */
15601 { "24kfx", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15602 { "24kx", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15603 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
15604 { "24kec", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
15605 { "24kef2_1", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
15606 { "24kef", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
15607 { "24kef1_1", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
15608 /* Deprecated forms of the above. */
15609 { "24kefx", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
15610 { "24kex", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
15611 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
15612 { "34kc", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
15613 ISA_MIPS32R2
, CPU_MIPS32R2
},
15614 { "34kf2_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
15615 ISA_MIPS32R2
, CPU_MIPS32R2
},
15616 { "34kf", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
15617 ISA_MIPS32R2
, CPU_MIPS32R2
},
15618 { "34kf1_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
15619 ISA_MIPS32R2
, CPU_MIPS32R2
},
15620 /* Deprecated forms of the above. */
15621 { "34kfx", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
15622 ISA_MIPS32R2
, CPU_MIPS32R2
},
15623 { "34kx", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
15624 ISA_MIPS32R2
, CPU_MIPS32R2
},
15625 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
15626 { "74kc", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
15627 ISA_MIPS32R2
, CPU_MIPS32R2
},
15628 { "74kf2_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
15629 ISA_MIPS32R2
, CPU_MIPS32R2
},
15630 { "74kf", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
15631 ISA_MIPS32R2
, CPU_MIPS32R2
},
15632 { "74kf1_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
15633 ISA_MIPS32R2
, CPU_MIPS32R2
},
15634 { "74kf3_2", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
15635 ISA_MIPS32R2
, CPU_MIPS32R2
},
15636 /* Deprecated forms of the above. */
15637 { "74kfx", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
15638 ISA_MIPS32R2
, CPU_MIPS32R2
},
15639 { "74kx", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
15640 ISA_MIPS32R2
, CPU_MIPS32R2
},
15641 /* 1004K cores are multiprocessor versions of the 34K. */
15642 { "1004kc", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
15643 ISA_MIPS32R2
, CPU_MIPS32R2
},
15644 { "1004kf2_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
15645 ISA_MIPS32R2
, CPU_MIPS32R2
},
15646 { "1004kf", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
15647 ISA_MIPS32R2
, CPU_MIPS32R2
},
15648 { "1004kf1_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
15649 ISA_MIPS32R2
, CPU_MIPS32R2
},
15652 { "5kc", 0, ISA_MIPS64
, CPU_MIPS64
},
15653 { "5kf", 0, ISA_MIPS64
, CPU_MIPS64
},
15654 { "20kc", MIPS_CPU_ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
15655 { "25kf", MIPS_CPU_ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
15657 /* Broadcom SB-1 CPU core */
15658 { "sb1", MIPS_CPU_ASE_MIPS3D
| MIPS_CPU_ASE_MDMX
,
15659 ISA_MIPS64
, CPU_SB1
},
15660 /* Broadcom SB-1A CPU core */
15661 { "sb1a", MIPS_CPU_ASE_MIPS3D
| MIPS_CPU_ASE_MDMX
,
15662 ISA_MIPS64
, CPU_SB1
},
15664 { "loongson3a", 0, ISA_MIPS64
, CPU_LOONGSON_3A
},
15666 /* MIPS 64 Release 2 */
15668 /* Cavium Networks Octeon CPU core */
15669 { "octeon", 0, ISA_MIPS64R2
, CPU_OCTEON
},
15672 { "xlr", 0, ISA_MIPS64
, CPU_XLR
},
15679 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
15680 with a final "000" replaced by "k". Ignore case.
15682 Note: this function is shared between GCC and GAS. */
15685 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
15687 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
15688 given
++, canonical
++;
15690 return ((*given
== 0 && *canonical
== 0)
15691 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
15695 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
15696 CPU name. We've traditionally allowed a lot of variation here.
15698 Note: this function is shared between GCC and GAS. */
15701 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
15703 /* First see if the name matches exactly, or with a final "000"
15704 turned into "k". */
15705 if (mips_strict_matching_cpu_name_p (canonical
, given
))
15708 /* If not, try comparing based on numerical designation alone.
15709 See if GIVEN is an unadorned number, or 'r' followed by a number. */
15710 if (TOLOWER (*given
) == 'r')
15712 if (!ISDIGIT (*given
))
15715 /* Skip over some well-known prefixes in the canonical name,
15716 hoping to find a number there too. */
15717 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
15719 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
15721 else if (TOLOWER (canonical
[0]) == 'r')
15724 return mips_strict_matching_cpu_name_p (canonical
, given
);
15728 /* Parse an option that takes the name of a processor as its argument.
15729 OPTION is the name of the option and CPU_STRING is the argument.
15730 Return the corresponding processor enumeration if the CPU_STRING is
15731 recognized, otherwise report an error and return null.
15733 A similar function exists in GCC. */
15735 static const struct mips_cpu_info
*
15736 mips_parse_cpu (const char *option
, const char *cpu_string
)
15738 const struct mips_cpu_info
*p
;
15740 /* 'from-abi' selects the most compatible architecture for the given
15741 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
15742 EABIs, we have to decide whether we're using the 32-bit or 64-bit
15743 version. Look first at the -mgp options, if given, otherwise base
15744 the choice on MIPS_DEFAULT_64BIT.
15746 Treat NO_ABI like the EABIs. One reason to do this is that the
15747 plain 'mips' and 'mips64' configs have 'from-abi' as their default
15748 architecture. This code picks MIPS I for 'mips' and MIPS III for
15749 'mips64', just as we did in the days before 'from-abi'. */
15750 if (strcasecmp (cpu_string
, "from-abi") == 0)
15752 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
15753 return mips_cpu_info_from_isa (ISA_MIPS1
);
15755 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
15756 return mips_cpu_info_from_isa (ISA_MIPS3
);
15758 if (file_mips_gp32
>= 0)
15759 return mips_cpu_info_from_isa (file_mips_gp32
? ISA_MIPS1
: ISA_MIPS3
);
15761 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
15766 /* 'default' has traditionally been a no-op. Probably not very useful. */
15767 if (strcasecmp (cpu_string
, "default") == 0)
15770 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
15771 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
15774 as_bad (_("Bad value (%s) for %s"), cpu_string
, option
);
15778 /* Return the canonical processor information for ISA (a member of the
15779 ISA_MIPS* enumeration). */
15781 static const struct mips_cpu_info
*
15782 mips_cpu_info_from_isa (int isa
)
15786 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
15787 if ((mips_cpu_info_table
[i
].flags
& MIPS_CPU_IS_ISA
)
15788 && isa
== mips_cpu_info_table
[i
].isa
)
15789 return (&mips_cpu_info_table
[i
]);
15794 static const struct mips_cpu_info
*
15795 mips_cpu_info_from_arch (int arch
)
15799 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
15800 if (arch
== mips_cpu_info_table
[i
].cpu
)
15801 return (&mips_cpu_info_table
[i
]);
15807 show (FILE *stream
, const char *string
, int *col_p
, int *first_p
)
15811 fprintf (stream
, "%24s", "");
15816 fprintf (stream
, ", ");
15820 if (*col_p
+ strlen (string
) > 72)
15822 fprintf (stream
, "\n%24s", "");
15826 fprintf (stream
, "%s", string
);
15827 *col_p
+= strlen (string
);
15833 md_show_usage (FILE *stream
)
15838 fprintf (stream
, _("\
15840 -EB generate big endian output\n\
15841 -EL generate little endian output\n\
15842 -g, -g2 do not remove unneeded NOPs or swap branches\n\
15843 -G NUM allow referencing objects up to NUM bytes\n\
15844 implicitly with the gp register [default 8]\n"));
15845 fprintf (stream
, _("\
15846 -mips1 generate MIPS ISA I instructions\n\
15847 -mips2 generate MIPS ISA II instructions\n\
15848 -mips3 generate MIPS ISA III instructions\n\
15849 -mips4 generate MIPS ISA IV instructions\n\
15850 -mips5 generate MIPS ISA V instructions\n\
15851 -mips32 generate MIPS32 ISA instructions\n\
15852 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
15853 -mips64 generate MIPS64 ISA instructions\n\
15854 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
15855 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
15859 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
15860 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
15861 show (stream
, "from-abi", &column
, &first
);
15862 fputc ('\n', stream
);
15864 fprintf (stream
, _("\
15865 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
15866 -no-mCPU don't generate code specific to CPU.\n\
15867 For -mCPU and -no-mCPU, CPU must be one of:\n"));
15871 show (stream
, "3900", &column
, &first
);
15872 show (stream
, "4010", &column
, &first
);
15873 show (stream
, "4100", &column
, &first
);
15874 show (stream
, "4650", &column
, &first
);
15875 fputc ('\n', stream
);
15877 fprintf (stream
, _("\
15878 -mips16 generate mips16 instructions\n\
15879 -no-mips16 do not generate mips16 instructions\n"));
15880 fprintf (stream
, _("\
15881 -msmartmips generate smartmips instructions\n\
15882 -mno-smartmips do not generate smartmips instructions\n"));
15883 fprintf (stream
, _("\
15884 -mdsp generate DSP instructions\n\
15885 -mno-dsp do not generate DSP instructions\n"));
15886 fprintf (stream
, _("\
15887 -mdspr2 generate DSP R2 instructions\n\
15888 -mno-dspr2 do not generate DSP R2 instructions\n"));
15889 fprintf (stream
, _("\
15890 -mmt generate MT instructions\n\
15891 -mno-mt do not generate MT instructions\n"));
15892 fprintf (stream
, _("\
15893 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
15894 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
15895 -mfix-vr4120 work around certain VR4120 errata\n\
15896 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
15897 -mfix-24k insert a nop after ERET and DERET instructions\n\
15898 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
15899 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
15900 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
15901 -msym32 assume all symbols have 32-bit values\n\
15902 -O0 remove unneeded NOPs, do not swap branches\n\
15903 -O remove unneeded NOPs and swap branches\n\
15904 --trap, --no-break trap exception on div by 0 and mult overflow\n\
15905 --break, --no-trap break exception on div by 0 and mult overflow\n"));
15906 fprintf (stream
, _("\
15907 -mhard-float allow floating-point instructions\n\
15908 -msoft-float do not allow floating-point instructions\n\
15909 -msingle-float only allow 32-bit floating-point operations\n\
15910 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
15911 --[no-]construct-floats [dis]allow floating point values to be constructed\n"
15914 fprintf (stream
, _("\
15915 -KPIC, -call_shared generate SVR4 position independent code\n\
15916 -call_nonpic generate non-PIC code that can operate with DSOs\n\
15917 -mvxworks-pic generate VxWorks position independent code\n\
15918 -non_shared do not generate code that can operate with DSOs\n\
15919 -xgot assume a 32 bit GOT\n\
15920 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
15921 -mshared, -mno-shared disable/enable .cpload optimization for\n\
15922 position dependent (non shared) code\n\
15923 -mabi=ABI create ABI conformant object file for:\n"));
15927 show (stream
, "32", &column
, &first
);
15928 show (stream
, "o64", &column
, &first
);
15929 show (stream
, "n32", &column
, &first
);
15930 show (stream
, "64", &column
, &first
);
15931 show (stream
, "eabi", &column
, &first
);
15933 fputc ('\n', stream
);
15935 fprintf (stream
, _("\
15936 -32 create o32 ABI object file (default)\n\
15937 -n32 create n32 ABI object file\n\
15938 -64 create 64 ABI object file\n"));
15944 mips_dwarf2_format (asection
*sec ATTRIBUTE_UNUSED
)
15946 if (HAVE_64BIT_SYMBOLS
)
15947 return dwarf2_format_64bit_irix
;
15949 return dwarf2_format_32bit
;
15954 mips_dwarf2_addr_size (void)
15956 if (HAVE_64BIT_OBJECTS
)
15962 /* Standard calling conventions leave the CFA at SP on entry. */
15964 mips_cfi_frame_initial_instructions (void)
15966 cfi_add_CFA_def_cfa_register (SP
);
15970 tc_mips_regname_to_dw2regnum (char *regname
)
15972 unsigned int regnum
= -1;
15975 if (reg_lookup (®name
, RTYPE_GP
| RTYPE_NUM
, ®
))