opcodes/lm32-desc.h

   1 /* CPU data header for lm32.
   2
   3 THIS FILE IS MACHINE GENERATED WITH CGEN.
   4
   5 Copyright 1996-2010 Free Software Foundation, Inc.
   6
   7 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
   8
   9    This file is free software; you can redistribute it and/or modify
  10    it under the terms of the GNU General Public License as published by
  11    the Free Software Foundation; either version 3, or (at your option)
  12    any later version.
  13
  14    It is distributed in the hope that it will be useful, but WITHOUT
  15    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  16    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  17    License for more details.
  18
  19    You should have received a copy of the GNU General Public License along
  20    with this program; if not, write to the Free Software Foundation, Inc.,
  21    51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
  22
  23 */
  24
  25 #ifndef LM32_CPU_H
  26 #define LM32_CPU_H
  27
  28 #define CGEN_ARCH lm32
  29
  30 /* Given symbol S, return lm32_cgen_<S>.  */
  31 #define CGEN_SYM(s) lm32##_cgen_##s
  32
  33
  34 /* Selected cpu families.  */
  35 #define HAVE_CPU_LM32BF
  36
  37 #define CGEN_INSN_LSB0_P 1
  38
  39 /* Minimum size of any insn (in bytes).  */
  40 #define CGEN_MIN_INSN_SIZE 4
  41
  42 /* Maximum size of any insn (in bytes).  */
  43 #define CGEN_MAX_INSN_SIZE 4
  44
  45 #define CGEN_INT_INSN_P 1
  46
  47 /* Maximum number of syntax elements in an instruction.  */
  48 #define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 15
  49
  50 /* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
  51    e.g. In "b,a foo" the ",a" is an operand.  If mnemonics have operands
  52    we can't hash on everything up to the space.  */
  53 #define CGEN_MNEMONIC_OPERANDS
  54
  55 /* Maximum number of fields in an instruction.  */
  56 #define CGEN_ACTUAL_MAX_IFMT_OPERANDS 5
  57
  58 /* Enums.  */
  59
  60 /* Enum declaration for opcodes.  */
  61 typedef enum opcodes {
  62   OP_ADD = 45, OP_ADDI = 13, OP_AND = 40, OP_ANDI = 8
  63  , OP_ANDHI = 24, OP_B = 48, OP_BI = 56, OP_BE = 17
  64  , OP_BG = 18, OP_BGE = 19, OP_BGEU = 20, OP_BGU = 21
  65  , OP_BNE = 23, OP_CALL = 54, OP_CALLI = 62, OP_CMPE = 57
  66  , OP_CMPEI = 25, OP_CMPG = 58, OP_CMPGI = 26, OP_CMPGE = 59
  67  , OP_CMPGEI = 27, OP_CMPGEU = 60, OP_CMPGEUI = 28, OP_CMPGU = 61
  68  , OP_CMPGUI = 29, OP_CMPNE = 63, OP_CMPNEI = 31, OP_DIVU = 35
  69  , OP_LB = 4, OP_LBU = 16, OP_LH = 7, OP_LHU = 11
  70  , OP_LW = 10, OP_MODU = 49, OP_MUL = 34, OP_MULI = 2
  71  , OP_NOR = 33, OP_NORI = 1, OP_OR = 46, OP_ORI = 14
  72  , OP_ORHI = 30, OP_RAISE = 43, OP_RCSR = 36, OP_SB = 12
  73  , OP_SEXTB = 44, OP_SEXTH = 55, OP_SH = 3, OP_SL = 47
  74  , OP_SLI = 15, OP_SR = 37, OP_SRI = 5, OP_SRU = 32
  75  , OP_SRUI = 0, OP_SUB = 50, OP_SW = 22, OP_USER = 51
  76  , OP_WCSR = 52, OP_XNOR = 41, OP_XNORI = 9, OP_XOR = 38
  77  , OP_XORI = 6
  78 } OPCODES;
  79
  80 /* Attributes.  */
  81
  82 /* Enum declaration for machine type selection.  */
  83 typedef enum mach_attr {
  84   MACH_BASE, MACH_LM32, MACH_MAX
  85 } MACH_ATTR;
  86
  87 /* Enum declaration for instruction set selection.  */
  88 typedef enum isa_attr {
  89   ISA_LM32, ISA_MAX
  90 } ISA_ATTR;
  91
  92 /* Number of architecture variants.  */
  93 #define MAX_ISAS  1
  94 #define MAX_MACHS ((int) MACH_MAX)
  95
  96 /* Ifield support.  */
  97
  98 /* Ifield attribute indices.  */
  99
 100 /* Enum declaration for cgen_ifld attrs.  */
 101 typedef enum cgen_ifld_attr {
 102   CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED
 103  , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31
 104  , CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS
 105 } CGEN_IFLD_ATTR;
 106
 107 /* Number of non-boolean elements in cgen_ifld_attr.  */
 108 #define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1)
 109
 110 /* cgen_ifld attribute accessor macros.  */
 111 #define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset)
 112 #define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_VIRTUAL)) != 0)
 113 #define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_PCREL_ADDR)) != 0)
 114 #define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_ABS_ADDR)) != 0)
 115 #define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_RESERVED)) != 0)
 116 #define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_SIGN_OPT)) != 0)
 117 #define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_SIGNED)) != 0)
 118
 119 /* Enum declaration for lm32 ifield types.  */
 120 typedef enum ifield_type {
 121   LM32_F_NIL, LM32_F_ANYOF, LM32_F_OPCODE, LM32_F_R0
 122  , LM32_F_R1, LM32_F_R2, LM32_F_RESV0, LM32_F_SHIFT
 123  , LM32_F_IMM, LM32_F_UIMM, LM32_F_CSR, LM32_F_USER
 124  , LM32_F_EXCEPTION, LM32_F_BRANCH, LM32_F_CALL, LM32_F_MAX
 125 } IFIELD_TYPE;
 126
 127 #define MAX_IFLD ((int) LM32_F_MAX)
 128
 129 /* Hardware attribute indices.  */
 130
 131 /* Enum declaration for cgen_hw attrs.  */
 132 typedef enum cgen_hw_attr {
 133   CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE
 134  , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS
 135 } CGEN_HW_ATTR;
 136
 137 /* Number of non-boolean elements in cgen_hw_attr.  */
 138 #define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1)
 139
 140 /* cgen_hw attribute accessor macros.  */
 141 #define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset)
 142 #define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_VIRTUAL)) != 0)
 143 #define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_CACHE_ADDR)) != 0)
 144 #define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_PC)) != 0)
 145 #define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_PROFILE)) != 0)
 146
 147 /* Enum declaration for lm32 hardware types.  */
 148 typedef enum cgen_hw_type {
 149   HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR
 150  , HW_H_IADDR, HW_H_PC, HW_H_GR, HW_H_CSR
 151  , HW_MAX
 152 } CGEN_HW_TYPE;
 153
 154 #define MAX_HW ((int) HW_MAX)
 155
 156 /* Operand attribute indices.  */
 157
 158 /* Enum declaration for cgen_operand attrs.  */
 159 typedef enum cgen_operand_attr {
 160   CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT
 161  , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY
 162  , CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH, CGEN_OPERAND_END_NBOOLS
 163 } CGEN_OPERAND_ATTR;
 164
 165 /* Number of non-boolean elements in cgen_operand_attr.  */
 166 #define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1)
 167
 168 /* cgen_operand attribute accessor macros.  */
 169 #define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset)
 170 #define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_VIRTUAL)) != 0)
 171 #define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0)
 172 #define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_ABS_ADDR)) != 0)
 173 #define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SIGN_OPT)) != 0)
 174 #define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SIGNED)) != 0)
 175 #define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_NEGATIVE)) != 0)
 176 #define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_RELAX)) != 0)
 177 #define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SEM_ONLY)) != 0)
 178
 179 /* Enum declaration for lm32 operand types.  */
 180 typedef enum cgen_operand_type {
 181   LM32_OPERAND_PC, LM32_OPERAND_R0, LM32_OPERAND_R1, LM32_OPERAND_R2
 182  , LM32_OPERAND_SHIFT, LM32_OPERAND_IMM, LM32_OPERAND_UIMM, LM32_OPERAND_BRANCH
 183  , LM32_OPERAND_CALL, LM32_OPERAND_CSR, LM32_OPERAND_USER, LM32_OPERAND_EXCEPTION
 184  , LM32_OPERAND_HI16, LM32_OPERAND_LO16, LM32_OPERAND_GP16, LM32_OPERAND_GOT16
 185  , LM32_OPERAND_GOTOFFHI16, LM32_OPERAND_GOTOFFLO16, LM32_OPERAND_MAX
 186 } CGEN_OPERAND_TYPE;
 187
 188 /* Number of operands types.  */
 189 #define MAX_OPERANDS 18
 190
 191 /* Maximum number of operands referenced by any insn.  */
 192 #define MAX_OPERAND_INSTANCES 5
 193
 194 /* Insn attribute indices.  */
 195
 196 /* Enum declaration for cgen_insn attrs.  */
 197 typedef enum cgen_insn_attr {
 198   CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
 199  , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED
 200  , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31
 201  , CGEN_INSN_MACH, CGEN_INSN_END_NBOOLS
 202 } CGEN_INSN_ATTR;
 203
 204 /* Number of non-boolean elements in cgen_insn_attr.  */
 205 #define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1)
 206
 207 /* cgen_insn attribute accessor macros.  */
 208 #define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset)
 209 #define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_ALIAS)) != 0)
 210 #define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_VIRTUAL)) != 0)
 211 #define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_UNCOND_CTI)) != 0)
 212 #define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_COND_CTI)) != 0)
 213 #define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_SKIP_CTI)) != 0)
 214 #define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_DELAY_SLOT)) != 0)
 215 #define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_RELAXABLE)) != 0)
 216 #define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_RELAXED)) != 0)
 217 #define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_NO_DIS)) != 0)
 218 #define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_PBB)) != 0)
 219
 220 /* cgen.h uses things we just defined.  */
 221 #include "opcode/cgen.h"
 222
 223 extern const struct cgen_ifld lm32_cgen_ifld_table[];
 224
 225 /* Attributes.  */
 226 extern const CGEN_ATTR_TABLE lm32_cgen_hardware_attr_table[];
 227 extern const CGEN_ATTR_TABLE lm32_cgen_ifield_attr_table[];
 228 extern const CGEN_ATTR_TABLE lm32_cgen_operand_attr_table[];
 229 extern const CGEN_ATTR_TABLE lm32_cgen_insn_attr_table[];
 230
 231 /* Hardware decls.  */
 232
 233 extern CGEN_KEYWORD lm32_cgen_opval_h_gr;
 234 extern CGEN_KEYWORD lm32_cgen_opval_h_csr;
 235
 236 extern const CGEN_HW_ENTRY lm32_cgen_hw_table[];
 237
 238
 239
 240 #endif /* LM32_CPU_H */