* ld-sh/rd-sh.exp: New framework file.
[binutils.git] / opcodes / ppc-opc.c
blob4ff73cd5035549a9c9d7a8418322b189bbcb3762
1 /* ppc-opc.c -- PowerPC opcode list
2 Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001
3 Free Software Foundation, Inc.
4 Written by Ian Lance Taylor, Cygnus Support
6 This file is part of GDB, GAS, and the GNU binutils.
8 GDB, GAS, and the GNU binutils are free software; you can redistribute
9 them and/or modify them under the terms of the GNU General Public
10 License as published by the Free Software Foundation; either version
11 2, or (at your option) any later version.
13 GDB, GAS, and the GNU binutils are distributed in the hope that they
14 will be useful, but WITHOUT ANY WARRANTY; without even the implied
15 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
16 the GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this file; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
21 02111-1307, USA. */
23 #include <stdio.h>
24 #include "sysdep.h"
25 #include "opcode/ppc.h"
26 #include "opintl.h"
28 /* This file holds the PowerPC opcode table. The opcode table
29 includes almost all of the extended instruction mnemonics. This
30 permits the disassembler to use them, and simplifies the assembler
31 logic, at the cost of increasing the table size. The table is
32 strictly constant data, so the compiler should be able to put it in
33 the .text section.
35 This file also holds the operand table. All knowledge about
36 inserting operands into instructions and vice-versa is kept in this
37 file. */
39 /* Local insertion and extraction functions. */
41 static unsigned long insert_bat PARAMS ((unsigned long, long, const char **));
42 static long extract_bat PARAMS ((unsigned long, int *));
43 static unsigned long insert_bba PARAMS ((unsigned long, long, const char **));
44 static long extract_bba PARAMS ((unsigned long, int *));
45 static unsigned long insert_bd PARAMS ((unsigned long, long, const char **));
46 static long extract_bd PARAMS ((unsigned long, int *));
47 static unsigned long insert_bdm PARAMS ((unsigned long, long, const char **));
48 static long extract_bdm PARAMS ((unsigned long, int *));
49 static unsigned long insert_bdp PARAMS ((unsigned long, long, const char **));
50 static long extract_bdp PARAMS ((unsigned long, int *));
51 static int valid_bo PARAMS ((long));
52 static unsigned long insert_bo PARAMS ((unsigned long, long, const char **));
53 static long extract_bo PARAMS ((unsigned long, int *));
54 static unsigned long insert_boe PARAMS ((unsigned long, long, const char **));
55 static long extract_boe PARAMS ((unsigned long, int *));
56 static unsigned long insert_ds PARAMS ((unsigned long, long, const char **));
57 static long extract_ds PARAMS ((unsigned long, int *));
58 static unsigned long insert_de PARAMS ((unsigned long, long, const char **));
59 static long extract_de PARAMS ((unsigned long, int *));
60 static unsigned long insert_des PARAMS ((unsigned long, long, const char **));
61 static long extract_des PARAMS ((unsigned long, int *));
62 static unsigned long insert_li PARAMS ((unsigned long, long, const char **));
63 static long extract_li PARAMS ((unsigned long, int *));
64 static unsigned long insert_mbe PARAMS ((unsigned long, long, const char **));
65 static long extract_mbe PARAMS ((unsigned long, int *));
66 static unsigned long insert_mb6 PARAMS ((unsigned long, long, const char **));
67 static long extract_mb6 PARAMS ((unsigned long, int *));
68 static unsigned long insert_nb PARAMS ((unsigned long, long, const char **));
69 static long extract_nb PARAMS ((unsigned long, int *));
70 static unsigned long insert_nsi PARAMS ((unsigned long, long, const char **));
71 static long extract_nsi PARAMS ((unsigned long, int *));
72 static unsigned long insert_ral PARAMS ((unsigned long, long, const char **));
73 static unsigned long insert_ram PARAMS ((unsigned long, long, const char **));
74 static unsigned long insert_ras PARAMS ((unsigned long, long, const char **));
75 static unsigned long insert_rbs PARAMS ((unsigned long, long, const char **));
76 static long extract_rbs PARAMS ((unsigned long, int *));
77 static unsigned long insert_sh6 PARAMS ((unsigned long, long, const char **));
78 static long extract_sh6 PARAMS ((unsigned long, int *));
79 static unsigned long insert_spr PARAMS ((unsigned long, long, const char **));
80 static long extract_spr PARAMS ((unsigned long, int *));
81 static unsigned long insert_tbr PARAMS ((unsigned long, long, const char **));
82 static long extract_tbr PARAMS ((unsigned long, int *));
84 /* The operands table.
86 The fields are bits, shift, insert, extract, flags.
88 We used to put parens around the various additions, like the one
89 for BA just below. However, that caused trouble with feeble
90 compilers with a limit on depth of a parenthesized expression, like
91 (reportedly) the compiler in Microsoft Developer Studio 5. So we
92 omit the parens, since the macros are never used in a context where
93 the addition will be ambiguous. */
95 const struct powerpc_operand powerpc_operands[] =
97 /* The zero index is used to indicate the end of the list of
98 operands. */
99 #define UNUSED 0
100 { 0, 0, 0, 0, 0 },
102 /* The BA field in an XL form instruction. */
103 #define BA UNUSED + 1
104 #define BA_MASK (0x1f << 16)
105 { 5, 16, 0, 0, PPC_OPERAND_CR },
107 /* The BA field in an XL form instruction when it must be the same
108 as the BT field in the same instruction. */
109 #define BAT BA + 1
110 { 5, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
112 /* The BB field in an XL form instruction. */
113 #define BB BAT + 1
114 #define BB_MASK (0x1f << 11)
115 { 5, 11, 0, 0, PPC_OPERAND_CR },
117 /* The BB field in an XL form instruction when it must be the same
118 as the BA field in the same instruction. */
119 #define BBA BB + 1
120 { 5, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },
122 /* The BD field in a B form instruction. The lower two bits are
123 forced to zero. */
124 #define BD BBA + 1
125 { 16, 0, insert_bd, extract_bd, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
127 /* The BD field in a B form instruction when absolute addressing is
128 used. */
129 #define BDA BD + 1
130 { 16, 0, insert_bd, extract_bd, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
132 /* The BD field in a B form instruction when the - modifier is used.
133 This sets the y bit of the BO field appropriately. */
134 #define BDM BDA + 1
135 { 16, 0, insert_bdm, extract_bdm,
136 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
138 /* The BD field in a B form instruction when the - modifier is used
139 and absolute address is used. */
140 #define BDMA BDM + 1
141 { 16, 0, insert_bdm, extract_bdm,
142 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
144 /* The BD field in a B form instruction when the + modifier is used.
145 This sets the y bit of the BO field appropriately. */
146 #define BDP BDMA + 1
147 { 16, 0, insert_bdp, extract_bdp,
148 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
150 /* The BD field in a B form instruction when the + modifier is used
151 and absolute addressing is used. */
152 #define BDPA BDP + 1
153 { 16, 0, insert_bdp, extract_bdp,
154 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
156 /* The BF field in an X or XL form instruction. */
157 #define BF BDPA + 1
158 { 3, 23, 0, 0, PPC_OPERAND_CR },
160 /* An optional BF field. This is used for comparison instructions,
161 in which an omitted BF field is taken as zero. */
162 #define OBF BF + 1
163 { 3, 23, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
165 /* The BFA field in an X or XL form instruction. */
166 #define BFA OBF + 1
167 { 3, 18, 0, 0, PPC_OPERAND_CR },
169 /* The BI field in a B form or XL form instruction. */
170 #define BI BFA + 1
171 #define BI_MASK (0x1f << 16)
172 { 5, 16, 0, 0, PPC_OPERAND_CR },
174 /* The BO field in a B form instruction. Certain values are
175 illegal. */
176 #define BO BI + 1
177 #define BO_MASK (0x1f << 21)
178 { 5, 21, insert_bo, extract_bo, 0 },
180 /* The BO field in a B form instruction when the + or - modifier is
181 used. This is like the BO field, but it must be even. */
182 #define BOE BO + 1
183 { 5, 21, insert_boe, extract_boe, 0 },
185 /* The BT field in an X or XL form instruction. */
186 #define BT BOE + 1
187 { 5, 21, 0, 0, PPC_OPERAND_CR },
189 /* The condition register number portion of the BI field in a B form
190 or XL form instruction. This is used for the extended
191 conditional branch mnemonics, which set the lower two bits of the
192 BI field. This field is optional. */
193 #define CR BT + 1
194 { 3, 18, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
196 /* The CT field in an X form instruction. */
197 #define CT CR + 1
198 { 5, 21, 0, 0, 0 },
200 /* The D field in a D form instruction. This is a displacement off
201 a register, and implies that the next operand is a register in
202 parentheses. */
203 #define D CT + 1
204 { 16, 0, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
206 /* The DE field in a DE form instruction. This is like D, but is 12
207 bits only. */
208 #define DE D + 1
209 { 14, 0, insert_de, extract_de, PPC_OPERAND_PARENS },
211 /* The DES field in a DES form instruction. This is like DS, but is 14
212 bits only (12 stored.) */
213 #define DES DE + 1
214 { 14, 0, insert_des, extract_des, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
216 /* The DS field in a DS form instruction. This is like D, but the
217 lower two bits are forced to zero. */
218 #define DS DES + 1
219 { 16, 0, insert_ds, extract_ds,
220 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },
222 /* The E field in a wrteei instruction. */
223 #define E DS + 1
224 { 1, 15, 0, 0, 0 },
226 /* The FL1 field in a POWER SC form instruction. */
227 #define FL1 E + 1
228 { 4, 12, 0, 0, 0 },
230 /* The FL2 field in a POWER SC form instruction. */
231 #define FL2 FL1 + 1
232 { 3, 2, 0, 0, 0 },
234 /* The FLM field in an XFL form instruction. */
235 #define FLM FL2 + 1
236 { 8, 17, 0, 0, 0 },
238 /* The FRA field in an X or A form instruction. */
239 #define FRA FLM + 1
240 #define FRA_MASK (0x1f << 16)
241 { 5, 16, 0, 0, PPC_OPERAND_FPR },
243 /* The FRB field in an X or A form instruction. */
244 #define FRB FRA + 1
245 #define FRB_MASK (0x1f << 11)
246 { 5, 11, 0, 0, PPC_OPERAND_FPR },
248 /* The FRC field in an A form instruction. */
249 #define FRC FRB + 1
250 #define FRC_MASK (0x1f << 6)
251 { 5, 6, 0, 0, PPC_OPERAND_FPR },
253 /* The FRS field in an X form instruction or the FRT field in a D, X
254 or A form instruction. */
255 #define FRS FRC + 1
256 #define FRT FRS
257 { 5, 21, 0, 0, PPC_OPERAND_FPR },
259 /* The FXM field in an XFX instruction. */
260 #define FXM FRS + 1
261 #define FXM_MASK (0xff << 12)
262 { 8, 12, 0, 0, 0 },
264 /* The L field in a D or X form instruction. */
265 #define L FXM + 1
266 { 1, 21, 0, 0, PPC_OPERAND_OPTIONAL },
268 /* The LEV field in a POWER SC form instruction. */
269 #define LEV L + 1
270 { 7, 5, 0, 0, 0 },
272 /* The LI field in an I form instruction. The lower two bits are
273 forced to zero. */
274 #define LI LEV + 1
275 { 26, 0, insert_li, extract_li, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
277 /* The LI field in an I form instruction when used as an absolute
278 address. */
279 #define LIA LI + 1
280 { 26, 0, insert_li, extract_li, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
282 /* The LS field in an X (sync) form instruction. */
283 #define LS LIA + 1
284 { 2, 21, 0, 0, PPC_OPERAND_OPTIONAL },
286 /* The MB field in an M form instruction. */
287 #define MB LS + 1
288 #define MB_MASK (0x1f << 6)
289 { 5, 6, 0, 0, 0 },
291 /* The ME field in an M form instruction. */
292 #define ME MB + 1
293 #define ME_MASK (0x1f << 1)
294 { 5, 1, 0, 0, 0 },
296 /* The MB and ME fields in an M form instruction expressed a single
297 operand which is a bitmask indicating which bits to select. This
298 is a two operand form using PPC_OPERAND_NEXT. See the
299 description in opcode/ppc.h for what this means. */
300 #define MBE ME + 1
301 { 5, 6, 0, 0, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
302 { 32, 0, insert_mbe, extract_mbe, 0 },
304 /* The MB or ME field in an MD or MDS form instruction. The high
305 bit is wrapped to the low end. */
306 #define MB6 MBE + 2
307 #define ME6 MB6
308 #define MB6_MASK (0x3f << 5)
309 { 6, 5, insert_mb6, extract_mb6, 0 },
311 /* The MO field in an mbar instruction. */
312 #define MO MB6 + 1
313 { 5, 21, 0, 0, 0 },
315 /* The NB field in an X form instruction. The value 32 is stored as
316 0. */
317 #define NB MO + 1
318 { 6, 11, insert_nb, extract_nb, 0 },
320 /* The NSI field in a D form instruction. This is the same as the
321 SI field, only negated. */
322 #define NSI NB + 1
323 { 16, 0, insert_nsi, extract_nsi,
324 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
326 /* The RA field in an D, DS, X, XO, M, or MDS form instruction. */
327 #define RA NSI + 1
328 #define RA_MASK (0x1f << 16)
329 { 5, 16, 0, 0, PPC_OPERAND_GPR },
331 /* The RA field in a D or X form instruction which is an updating
332 load, which means that the RA field may not be zero and may not
333 equal the RT field. */
334 #define RAL RA + 1
335 { 5, 16, insert_ral, 0, PPC_OPERAND_GPR },
337 /* The RA field in an lmw instruction, which has special value
338 restrictions. */
339 #define RAM RAL + 1
340 { 5, 16, insert_ram, 0, PPC_OPERAND_GPR },
342 /* The RA field in a D or X form instruction which is an updating
343 store or an updating floating point load, which means that the RA
344 field may not be zero. */
345 #define RAS RAM + 1
346 { 5, 16, insert_ras, 0, PPC_OPERAND_GPR },
348 /* The RB field in an X, XO, M, or MDS form instruction. */
349 #define RB RAS + 1
350 #define RB_MASK (0x1f << 11)
351 { 5, 11, 0, 0, PPC_OPERAND_GPR },
353 /* The RB field in an X form instruction when it must be the same as
354 the RS field in the instruction. This is used for extended
355 mnemonics like mr. */
356 #define RBS RB + 1
357 { 5, 1, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },
359 /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
360 instruction or the RT field in a D, DS, X, XFX or XO form
361 instruction. */
362 #define RS RBS + 1
363 #define RT RS
364 #define RT_MASK (0x1f << 21)
365 { 5, 21, 0, 0, PPC_OPERAND_GPR },
367 /* The SH field in an X or M form instruction. */
368 #define SH RS + 1
369 #define SH_MASK (0x1f << 11)
370 { 5, 11, 0, 0, 0 },
372 /* The SH field in an MD form instruction. This is split. */
373 #define SH6 SH + 1
374 #define SH6_MASK ((0x1f << 11) | (1 << 1))
375 { 6, 1, insert_sh6, extract_sh6, 0 },
377 /* The SI field in a D form instruction. */
378 #define SI SH6 + 1
379 { 16, 0, 0, 0, PPC_OPERAND_SIGNED },
381 /* The SI field in a D form instruction when we accept a wide range
382 of positive values. */
383 #define SISIGNOPT SI + 1
384 { 16, 0, 0, 0, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
386 /* The SPR field in an XFX form instruction. This is flipped--the
387 lower 5 bits are stored in the upper 5 and vice- versa. */
388 #define SPR SISIGNOPT + 1
389 #define SPR_MASK (0x3ff << 11)
390 { 10, 11, insert_spr, extract_spr, 0 },
392 /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */
393 #define SPRBAT SPR + 1
394 #define SPRBAT_MASK (0x3 << 17)
395 { 2, 17, 0, 0, 0 },
397 /* The SPRG register number in an XFX form m[ft]sprg instruction. */
398 #define SPRG SPRBAT + 1
399 #define SPRG_MASK (0x3 << 16)
400 { 2, 16, 0, 0, 0 },
402 /* The SR field in an X form instruction. */
403 #define SR SPRG + 1
404 { 4, 16, 0, 0, 0 },
406 /* The SV field in a POWER SC form instruction. */
407 #define SV SR + 1
408 { 14, 2, 0, 0, 0 },
410 /* The TBR field in an XFX form instruction. This is like the SPR
411 field, but it is optional. */
412 #define TBR SV + 1
413 { 10, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL },
415 /* The TO field in a D or X form instruction. */
416 #define TO TBR + 1
417 #define TO_MASK (0x1f << 21)
418 { 5, 21, 0, 0, 0 },
420 /* The U field in an X form instruction. */
421 #define U TO + 1
422 { 4, 12, 0, 0, 0 },
424 /* The UI field in a D form instruction. */
425 #define UI U + 1
426 { 16, 0, 0, 0, 0 },
428 /* The VA field in a VA, VX or VXR form instruction. */
429 #define VA UI + 1
430 #define VA_MASK (0x1f << 16)
431 { 5, 16, 0, 0, PPC_OPERAND_VR },
433 /* The VB field in a VA, VX or VXR form instruction. */
434 #define VB VA + 1
435 #define VB_MASK (0x1f << 11)
436 { 5, 11, 0, 0, PPC_OPERAND_VR },
438 /* The VC field in a VA form instruction. */
439 #define VC VB + 1
440 #define VC_MASK (0x1f << 6)
441 { 5, 6, 0, 0, PPC_OPERAND_VR },
443 /* The VD or VS field in a VA, VX, VXR or X form instruction. */
444 #define VD VC + 1
445 #define VS VD
446 #define VD_MASK (0x1f << 21)
447 { 5, 21, 0, 0, PPC_OPERAND_VR },
449 /* The SIMM field in a VX form instruction. */
450 #define SIMM VD + 1
451 { 5, 16, 0, 0, PPC_OPERAND_SIGNED},
453 /* The UIMM field in a VX form instruction. */
454 #define UIMM SIMM + 1
455 { 5, 16, 0, 0, 0 },
457 /* The SHB field in a VA form instruction. */
458 #define SHB UIMM + 1
459 { 4, 6, 0, 0, 0 },
462 /* The functions used to insert and extract complicated operands. */
464 /* The BA field in an XL form instruction when it must be the same as
465 the BT field in the same instruction. This operand is marked FAKE.
466 The insertion function just copies the BT field into the BA field,
467 and the extraction function just checks that the fields are the
468 same. */
470 /*ARGSUSED*/
471 static unsigned long
472 insert_bat (insn, value, errmsg)
473 unsigned long insn;
474 long value ATTRIBUTE_UNUSED;
475 const char **errmsg ATTRIBUTE_UNUSED;
477 return insn | (((insn >> 21) & 0x1f) << 16);
480 static long
481 extract_bat (insn, invalid)
482 unsigned long insn;
483 int *invalid;
485 if (invalid != (int *) NULL
486 && ((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
487 *invalid = 1;
488 return 0;
491 /* The BB field in an XL form instruction when it must be the same as
492 the BA field in the same instruction. This operand is marked FAKE.
493 The insertion function just copies the BA field into the BB field,
494 and the extraction function just checks that the fields are the
495 same. */
497 /*ARGSUSED*/
498 static unsigned long
499 insert_bba (insn, value, errmsg)
500 unsigned long insn;
501 long value ATTRIBUTE_UNUSED;
502 const char **errmsg ATTRIBUTE_UNUSED;
504 return insn | (((insn >> 16) & 0x1f) << 11);
507 static long
508 extract_bba (insn, invalid)
509 unsigned long insn;
510 int *invalid;
512 if (invalid != (int *) NULL
513 && ((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
514 *invalid = 1;
515 return 0;
518 /* The BD field in a B form instruction. The lower two bits are
519 forced to zero. */
521 /*ARGSUSED*/
522 static unsigned long
523 insert_bd (insn, value, errmsg)
524 unsigned long insn;
525 long value;
526 const char **errmsg ATTRIBUTE_UNUSED;
528 return insn | (value & 0xfffc);
531 /*ARGSUSED*/
532 static long
533 extract_bd (insn, invalid)
534 unsigned long insn;
535 int *invalid ATTRIBUTE_UNUSED;
537 if ((insn & 0x8000) != 0)
538 return (insn & 0xfffc) - 0x10000;
539 else
540 return insn & 0xfffc;
543 /* The BD field in a B form instruction when the - modifier is used.
544 This modifier means that the branch is not expected to be taken.
545 We must set the y bit of the BO field to 1 if the offset is
546 negative. When extracting, we require that the y bit be 1 and that
547 the offset be positive, since if the y bit is 0 we just want to
548 print the normal form of the instruction. */
550 /*ARGSUSED*/
551 static unsigned long
552 insert_bdm (insn, value, errmsg)
553 unsigned long insn;
554 long value;
555 const char **errmsg ATTRIBUTE_UNUSED;
557 if ((value & 0x8000) != 0)
558 insn |= 1 << 21;
559 return insn | (value & 0xfffc);
562 static long
563 extract_bdm (insn, invalid)
564 unsigned long insn;
565 int *invalid;
567 if (invalid != (int *) NULL
568 && ((insn & (1 << 21)) == 0
569 || (insn & (1 << 15)) == 0))
570 *invalid = 1;
571 if ((insn & 0x8000) != 0)
572 return (insn & 0xfffc) - 0x10000;
573 else
574 return insn & 0xfffc;
577 /* The BD field in a B form instruction when the + modifier is used.
578 This is like BDM, above, except that the branch is expected to be
579 taken. */
581 /*ARGSUSED*/
582 static unsigned long
583 insert_bdp (insn, value, errmsg)
584 unsigned long insn;
585 long value;
586 const char **errmsg ATTRIBUTE_UNUSED;
588 if ((value & 0x8000) == 0)
589 insn |= 1 << 21;
590 return insn | (value & 0xfffc);
593 static long
594 extract_bdp (insn, invalid)
595 unsigned long insn;
596 int *invalid;
598 if (invalid != (int *) NULL
599 && ((insn & (1 << 21)) == 0
600 || (insn & (1 << 15)) != 0))
601 *invalid = 1;
602 if ((insn & 0x8000) != 0)
603 return (insn & 0xfffc) - 0x10000;
604 else
605 return insn & 0xfffc;
608 /* Check for legal values of a BO field. */
610 static int
611 valid_bo (value)
612 long value;
614 /* Certain encodings have bits that are required to be zero. These
615 are (z must be zero, y may be anything):
616 001zy
617 011zy
618 1z00y
619 1z01y
620 1z1zz
622 switch (value & 0x14)
624 default:
625 case 0:
626 return 1;
627 case 0x4:
628 return (value & 0x2) == 0;
629 case 0x10:
630 return (value & 0x8) == 0;
631 case 0x14:
632 return value == 0x14;
636 /* The BO field in a B form instruction. Warn about attempts to set
637 the field to an illegal value. */
639 static unsigned long
640 insert_bo (insn, value, errmsg)
641 unsigned long insn;
642 long value;
643 const char **errmsg;
645 if (errmsg != (const char **) NULL
646 && ! valid_bo (value))
647 *errmsg = _("invalid conditional option");
648 return insn | ((value & 0x1f) << 21);
651 static long
652 extract_bo (insn, invalid)
653 unsigned long insn;
654 int *invalid;
656 long value;
658 value = (insn >> 21) & 0x1f;
659 if (invalid != (int *) NULL
660 && ! valid_bo (value))
661 *invalid = 1;
662 return value;
665 /* The BO field in a B form instruction when the + or - modifier is
666 used. This is like the BO field, but it must be even. When
667 extracting it, we force it to be even. */
669 static unsigned long
670 insert_boe (insn, value, errmsg)
671 unsigned long insn;
672 long value;
673 const char **errmsg;
675 if (errmsg != (const char **) NULL)
677 if (! valid_bo (value))
678 *errmsg = _("invalid conditional option");
679 else if ((value & 1) != 0)
680 *errmsg = _("attempt to set y bit when using + or - modifier");
682 return insn | ((value & 0x1f) << 21);
685 static long
686 extract_boe (insn, invalid)
687 unsigned long insn;
688 int *invalid;
690 long value;
692 value = (insn >> 21) & 0x1f;
693 if (invalid != (int *) NULL
694 && ! valid_bo (value))
695 *invalid = 1;
696 return value & 0x1e;
699 /* The DS field in a DS form instruction. This is like D, but the
700 lower two bits are forced to zero. */
702 /*ARGSUSED*/
703 static unsigned long
704 insert_ds (insn, value, errmsg)
705 unsigned long insn;
706 long value;
707 const char **errmsg;
709 if ((value & 3) != 0 && errmsg != NULL)
710 *errmsg = _("offset not a multiple of 4");
711 return insn | (value & 0xfffc);
714 /*ARGSUSED*/
715 static long
716 extract_ds (insn, invalid)
717 unsigned long insn;
718 int *invalid ATTRIBUTE_UNUSED;
720 if ((insn & 0x8000) != 0)
721 return (insn & 0xfffc) - 0x10000;
722 else
723 return insn & 0xfffc;
726 /* The DE field in a DE form instruction. */
728 /*ARGSUSED*/
729 static unsigned long
730 insert_de (insn, value, errmsg)
731 unsigned long insn;
732 long value;
733 const char **errmsg;
735 if ((value > 2047 || value < -2048) && errmsg != NULL)
736 *errmsg = _("offset not between -2048 and 2047");
737 return insn | ((value << 4) & 0xfff0);
740 /*ARGSUSED*/
741 static long
742 extract_de (insn, invalid)
743 unsigned long insn;
744 int *invalid ATTRIBUTE_UNUSED;
746 return (insn & 0xfff0) >> 4;
749 /* The DES field in a DES form instruction. */
751 /*ARGSUSED*/
752 static unsigned long
753 insert_des (insn, value, errmsg)
754 unsigned long insn;
755 long value;
756 const char **errmsg;
758 if ((value > 8191 || value < -8192) && errmsg != NULL)
759 *errmsg = _("offset not between -8192 and 8191");
760 else if ((value & 3) != 0 && errmsg != NULL)
761 *errmsg = _("offset not a multiple of 4");
762 return insn | ((value << 2) & 0xfff0);
765 /*ARGSUSED*/
766 static long
767 extract_des (insn, invalid)
768 unsigned long insn;
769 int *invalid ATTRIBUTE_UNUSED;
771 if ((insn & 0x8000) != 0)
772 return ((insn & 0xfff0) >> 2) - 0x4000;
773 else
774 return (insn & 0xfff0) >> 2;
777 /* The LI field in an I form instruction. The lower two bits are
778 forced to zero. */
780 /*ARGSUSED*/
781 static unsigned long
782 insert_li (insn, value, errmsg)
783 unsigned long insn;
784 long value;
785 const char **errmsg;
787 if ((value & 3) != 0 && errmsg != (const char **) NULL)
788 *errmsg = _("ignoring least significant bits in branch offset");
789 return insn | (value & 0x3fffffc);
792 /*ARGSUSED*/
793 static long
794 extract_li (insn, invalid)
795 unsigned long insn;
796 int *invalid ATTRIBUTE_UNUSED;
798 if ((insn & 0x2000000) != 0)
799 return (insn & 0x3fffffc) - 0x4000000;
800 else
801 return insn & 0x3fffffc;
804 /* The MB and ME fields in an M form instruction expressed as a single
805 operand which is itself a bitmask. The extraction function always
806 marks it as invalid, since we never want to recognize an
807 instruction which uses a field of this type. */
809 static unsigned long
810 insert_mbe (insn, value, errmsg)
811 unsigned long insn;
812 long value;
813 const char **errmsg;
815 unsigned long uval, mask;
816 int mb, me, mx, count, last;
818 uval = value;
820 if (uval == 0)
822 if (errmsg != (const char **) NULL)
823 *errmsg = _("illegal bitmask");
824 return insn;
827 mb = 0;
828 me = 32;
829 if ((uval & 1) != 0)
830 last = 1;
831 else
832 last = 0;
833 count = 0;
835 /* mb: location of last 0->1 transition */
836 /* me: location of last 1->0 transition */
837 /* count: # transitions */
839 for (mx = 0, mask = (long) 1 << 31; mx < 32; ++mx, mask >>= 1)
841 if ((uval & mask) && !last)
843 ++count;
844 mb = mx;
845 last = 1;
847 else if (!(uval & mask) && last)
849 ++count;
850 me = mx;
851 last = 0;
854 if (me == 0)
855 me = 32;
857 if (count != 2 && (count != 0 || ! last))
859 if (errmsg != (const char **) NULL)
860 *errmsg = _("illegal bitmask");
863 return insn | (mb << 6) | ((me - 1) << 1);
866 static long
867 extract_mbe (insn, invalid)
868 unsigned long insn;
869 int *invalid;
871 long ret;
872 int mb, me;
873 int i;
875 if (invalid != (int *) NULL)
876 *invalid = 1;
878 mb = (insn >> 6) & 0x1f;
879 me = (insn >> 1) & 0x1f;
880 if (mb < me + 1)
882 ret = 0;
883 for (i = mb; i <= me; i++)
884 ret |= (long) 1 << (31 - i);
886 else if (mb == me + 1)
887 ret = ~0;
888 else /* (mb > me + 1) */
890 ret = ~ (long) 0;
891 for (i = me + 1; i < mb; i++)
892 ret &= ~ ((long) 1 << (31 - i));
894 return ret;
897 /* The MB or ME field in an MD or MDS form instruction. The high bit
898 is wrapped to the low end. */
900 /*ARGSUSED*/
901 static unsigned long
902 insert_mb6 (insn, value, errmsg)
903 unsigned long insn;
904 long value;
905 const char **errmsg ATTRIBUTE_UNUSED;
907 return insn | ((value & 0x1f) << 6) | (value & 0x20);
910 /*ARGSUSED*/
911 static long
912 extract_mb6 (insn, invalid)
913 unsigned long insn;
914 int *invalid ATTRIBUTE_UNUSED;
916 return ((insn >> 6) & 0x1f) | (insn & 0x20);
919 /* The NB field in an X form instruction. The value 32 is stored as
920 0. */
922 static unsigned long
923 insert_nb (insn, value, errmsg)
924 unsigned long insn;
925 long value;
926 const char **errmsg;
928 if (value < 0 || value > 32)
929 *errmsg = _("value out of range");
930 if (value == 32)
931 value = 0;
932 return insn | ((value & 0x1f) << 11);
935 /*ARGSUSED*/
936 static long
937 extract_nb (insn, invalid)
938 unsigned long insn;
939 int *invalid ATTRIBUTE_UNUSED;
941 long ret;
943 ret = (insn >> 11) & 0x1f;
944 if (ret == 0)
945 ret = 32;
946 return ret;
949 /* The NSI field in a D form instruction. This is the same as the SI
950 field, only negated. The extraction function always marks it as
951 invalid, since we never want to recognize an instruction which uses
952 a field of this type. */
954 /*ARGSUSED*/
955 static unsigned long
956 insert_nsi (insn, value, errmsg)
957 unsigned long insn;
958 long value;
959 const char **errmsg ATTRIBUTE_UNUSED;
961 return insn | ((- value) & 0xffff);
964 static long
965 extract_nsi (insn, invalid)
966 unsigned long insn;
967 int *invalid;
969 if (invalid != (int *) NULL)
970 *invalid = 1;
971 if ((insn & 0x8000) != 0)
972 return - ((long)(insn & 0xffff) - 0x10000);
973 else
974 return - (long)(insn & 0xffff);
977 /* The RA field in a D or X form instruction which is an updating
978 load, which means that the RA field may not be zero and may not
979 equal the RT field. */
981 static unsigned long
982 insert_ral (insn, value, errmsg)
983 unsigned long insn;
984 long value;
985 const char **errmsg;
987 if (value == 0
988 || (unsigned long) value == ((insn >> 21) & 0x1f))
989 *errmsg = "invalid register operand when updating";
990 return insn | ((value & 0x1f) << 16);
993 /* The RA field in an lmw instruction, which has special value
994 restrictions. */
996 static unsigned long
997 insert_ram (insn, value, errmsg)
998 unsigned long insn;
999 long value;
1000 const char **errmsg;
1002 if ((unsigned long) value >= ((insn >> 21) & 0x1f))
1003 *errmsg = _("index register in load range");
1004 return insn | ((value & 0x1f) << 16);
1007 /* The RA field in a D or X form instruction which is an updating
1008 store or an updating floating point load, which means that the RA
1009 field may not be zero. */
1011 static unsigned long
1012 insert_ras (insn, value, errmsg)
1013 unsigned long insn;
1014 long value;
1015 const char **errmsg;
1017 if (value == 0)
1018 *errmsg = _("invalid register operand when updating");
1019 return insn | ((value & 0x1f) << 16);
1022 /* The RB field in an X form instruction when it must be the same as
1023 the RS field in the instruction. This is used for extended
1024 mnemonics like mr. This operand is marked FAKE. The insertion
1025 function just copies the BT field into the BA field, and the
1026 extraction function just checks that the fields are the same. */
1028 /*ARGSUSED*/
1029 static unsigned long
1030 insert_rbs (insn, value, errmsg)
1031 unsigned long insn;
1032 long value ATTRIBUTE_UNUSED;
1033 const char **errmsg ATTRIBUTE_UNUSED;
1035 return insn | (((insn >> 21) & 0x1f) << 11);
1038 static long
1039 extract_rbs (insn, invalid)
1040 unsigned long insn;
1041 int *invalid;
1043 if (invalid != (int *) NULL
1044 && ((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f))
1045 *invalid = 1;
1046 return 0;
1049 /* The SH field in an MD form instruction. This is split. */
1051 /*ARGSUSED*/
1052 static unsigned long
1053 insert_sh6 (insn, value, errmsg)
1054 unsigned long insn;
1055 long value;
1056 const char **errmsg ATTRIBUTE_UNUSED;
1058 return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
1061 /*ARGSUSED*/
1062 static long
1063 extract_sh6 (insn, invalid)
1064 unsigned long insn;
1065 int *invalid ATTRIBUTE_UNUSED;
1067 return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
1070 /* The SPR field in an XFX form instruction. This is flipped--the
1071 lower 5 bits are stored in the upper 5 and vice- versa. */
1073 static unsigned long
1074 insert_spr (insn, value, errmsg)
1075 unsigned long insn;
1076 long value;
1077 const char **errmsg ATTRIBUTE_UNUSED;
1079 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1082 static long
1083 extract_spr (insn, invalid)
1084 unsigned long insn;
1085 int *invalid ATTRIBUTE_UNUSED;
1087 return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1090 /* The TBR field in an XFX instruction. This is just like SPR, but it
1091 is optional. When TBR is omitted, it must be inserted as 268 (the
1092 magic number of the TB register). These functions treat 0
1093 (indicating an omitted optional operand) as 268. This means that
1094 ``mftb 4,0'' is not handled correctly. This does not matter very
1095 much, since the architecture manual does not define mftb as
1096 accepting any values other than 268 or 269. */
1098 #define TB (268)
1100 static unsigned long
1101 insert_tbr (insn, value, errmsg)
1102 unsigned long insn;
1103 long value;
1104 const char **errmsg ATTRIBUTE_UNUSED;
1106 if (value == 0)
1107 value = TB;
1108 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1111 static long
1112 extract_tbr (insn, invalid)
1113 unsigned long insn;
1114 int *invalid ATTRIBUTE_UNUSED;
1116 long ret;
1118 ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1119 if (ret == TB)
1120 ret = 0;
1121 return ret;
1124 /* Macros used to form opcodes. */
1126 /* The main opcode. */
1127 #define OP(x) ((((unsigned long)(x)) & 0x3f) << 26)
1128 #define OP_MASK OP (0x3f)
1130 /* The main opcode combined with a trap code in the TO field of a D
1131 form instruction. Used for extended mnemonics for the trap
1132 instructions. */
1133 #define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21))
1134 #define OPTO_MASK (OP_MASK | TO_MASK)
1136 /* The main opcode combined with a comparison size bit in the L field
1137 of a D form or X form instruction. Used for extended mnemonics for
1138 the comparison instructions. */
1139 #define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21))
1140 #define OPL_MASK OPL (0x3f,1)
1142 /* An A form instruction. */
1143 #define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1))
1144 #define A_MASK A (0x3f, 0x1f, 1)
1146 /* An A_MASK with the FRB field fixed. */
1147 #define AFRB_MASK (A_MASK | FRB_MASK)
1149 /* An A_MASK with the FRC field fixed. */
1150 #define AFRC_MASK (A_MASK | FRC_MASK)
1152 /* An A_MASK with the FRA and FRC fields fixed. */
1153 #define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
1155 /* A B form instruction. */
1156 #define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1))
1157 #define B_MASK B (0x3f, 1, 1)
1159 /* A B form instruction setting the BO field. */
1160 #define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1161 #define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
1163 /* A BBO_MASK with the y bit of the BO field removed. This permits
1164 matching a conditional branch regardless of the setting of the y
1165 bit. */
1166 #define Y_MASK (((unsigned long)1) << 21)
1167 #define BBOY_MASK (BBO_MASK &~ Y_MASK)
1169 /* A B form instruction setting the BO field and the condition bits of
1170 the BI field. */
1171 #define BBOCB(op, bo, cb, aa, lk) \
1172 (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16))
1173 #define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
1175 /* A BBOCB_MASK with the y bit of the BO field removed. */
1176 #define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
1178 /* A BBOYCB_MASK in which the BI field is fixed. */
1179 #define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
1181 /* The main opcode mask with the RA field clear. */
1182 #define DRA_MASK (OP_MASK | RA_MASK)
1184 /* A DS form instruction. */
1185 #define DSO(op, xop) (OP (op) | ((xop) & 0x3))
1186 #define DS_MASK DSO (0x3f, 3)
1188 /* A DE form instruction. */
1189 #define DEO(op, xop) (OP (op) | ((xop) & 0xf))
1190 #define DE_MASK DEO (0x3e, 0xf)
1192 /* An M form instruction. */
1193 #define M(op, rc) (OP (op) | ((rc) & 1))
1194 #define M_MASK M (0x3f, 1)
1196 /* An M form instruction with the ME field specified. */
1197 #define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1))
1199 /* An M_MASK with the MB and ME fields fixed. */
1200 #define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
1202 /* An M_MASK with the SH and ME fields fixed. */
1203 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
1205 /* An MD form instruction. */
1206 #define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1))
1207 #define MD_MASK MD (0x3f, 0x7, 1)
1209 /* An MD_MASK with the MB field fixed. */
1210 #define MDMB_MASK (MD_MASK | MB6_MASK)
1212 /* An MD_MASK with the SH field fixed. */
1213 #define MDSH_MASK (MD_MASK | SH6_MASK)
1215 /* An MDS form instruction. */
1216 #define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1))
1217 #define MDS_MASK MDS (0x3f, 0xf, 1)
1219 /* An MDS_MASK with the MB field fixed. */
1220 #define MDSMB_MASK (MDS_MASK | MB6_MASK)
1222 /* An SC form instruction. */
1223 #define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
1224 #define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
1226 /* An VX form instruction. */
1227 #define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
1229 /* The mask for an VX form instruction. */
1230 #define VX_MASK VX(0x3f, 0x7ff)
1232 /* An VA form instruction. */
1233 #define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
1235 /* The mask for an VA form instruction. */
1236 #define VXA_MASK VXA(0x3f, 0x3f)
1238 /* An VXR form instruction. */
1239 #define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
1241 /* The mask for a VXR form instruction. */
1242 #define VXR_MASK VXR(0x3f, 0x3ff, 1)
1244 /* An X form instruction. */
1245 #define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1247 /* An X form instruction with the RC bit specified. */
1248 #define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
1250 /* The mask for an X form instruction. */
1251 #define X_MASK XRC (0x3f, 0x3ff, 1)
1253 /* An X_MASK with the RA field fixed. */
1254 #define XRA_MASK (X_MASK | RA_MASK)
1256 /* An X_MASK with the RB field fixed. */
1257 #define XRB_MASK (X_MASK | RB_MASK)
1259 /* An X_MASK with the RT field fixed. */
1260 #define XRT_MASK (X_MASK | RT_MASK)
1262 /* An X_MASK with the RA and RB fields fixed. */
1263 #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
1265 /* An X_MASK with the RT and RA fields fixed. */
1266 #define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
1268 /* An X form comparison instruction. */
1269 #define XCMPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
1271 /* The mask for an X form comparison instruction. */
1272 #define XCMP_MASK (X_MASK | (((unsigned long)1) << 22))
1274 /* The mask for an X form comparison instruction with the L field
1275 fixed. */
1276 #define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21))
1278 /* An X form trap instruction with the TO field specified. */
1279 #define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21))
1280 #define XTO_MASK (X_MASK | TO_MASK)
1282 /* An X form tlb instruction with the SH field specified. */
1283 #define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11))
1284 #define XTLB_MASK (X_MASK | SH_MASK)
1286 /* An X form sync instruction. */
1287 #define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
1289 /* An X form sync instruction with everything filled in except the LS field. */
1290 #define XSYNC_MASK (0xff9fffff)
1292 /* An XFL form instruction. */
1293 #define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
1294 #define XFL_MASK (XFL (0x3f, 0x3ff, 1) | (((unsigned long)1) << 25) | (((unsigned long)1) << 16))
1296 /* An XL form instruction with the LK field set to 0. */
1297 #define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1299 /* An XL form instruction which uses the LK field. */
1300 #define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
1302 /* The mask for an XL form instruction. */
1303 #define XL_MASK XLLK (0x3f, 0x3ff, 1)
1305 /* An XL form instruction which explicitly sets the BO field. */
1306 #define XLO(op, bo, xop, lk) \
1307 (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1308 #define XLO_MASK (XL_MASK | BO_MASK)
1310 /* An XL form instruction which explicitly sets the y bit of the BO
1311 field. */
1312 #define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21))
1313 #define XLYLK_MASK (XL_MASK | Y_MASK)
1315 /* An XL form instruction which sets the BO field and the condition
1316 bits of the BI field. */
1317 #define XLOCB(op, bo, cb, xop, lk) \
1318 (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16))
1319 #define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
1321 /* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed. */
1322 #define XLBB_MASK (XL_MASK | BB_MASK)
1323 #define XLYBB_MASK (XLYLK_MASK | BB_MASK)
1324 #define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
1326 /* An XL_MASK with the BO and BB fields fixed. */
1327 #define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
1329 /* An XL_MASK with the BO, BI and BB fields fixed. */
1330 #define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
1332 /* An XO form instruction. */
1333 #define XO(op, xop, oe, rc) \
1334 (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1))
1335 #define XO_MASK XO (0x3f, 0x1ff, 1, 1)
1337 /* An XO_MASK with the RB field fixed. */
1338 #define XORB_MASK (XO_MASK | RB_MASK)
1340 /* An XS form instruction. */
1341 #define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1))
1342 #define XS_MASK XS (0x3f, 0x1ff, 1)
1344 /* A mask for the FXM version of an XFX form instruction. */
1345 #define XFXFXM_MASK (X_MASK | (((unsigned long)1) << 20) | (((unsigned long)1) << 11))
1347 /* An XFX form instruction with the FXM field filled in. */
1348 #define XFXM(op, xop, fxm) \
1349 (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12))
1351 /* An XFX form instruction with the SPR field filled in. */
1352 #define XSPR(op, xop, spr) \
1353 (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6))
1354 #define XSPR_MASK (X_MASK | SPR_MASK)
1356 /* An XFX form instruction with the SPR field filled in except for the
1357 SPRBAT field. */
1358 #define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
1360 /* An XFX form instruction with the SPR field filled in except for the
1361 SPRG field. */
1362 #define XSPRG_MASK (XSPR_MASK &~ SPRG_MASK)
1364 /* An X form instruction with everything filled in except the E field. */
1365 #define XE_MASK (0xffff7fff)
1367 /* The BO encodings used in extended conditional branch mnemonics. */
1368 #define BODNZF (0x0)
1369 #define BODNZFP (0x1)
1370 #define BODZF (0x2)
1371 #define BODZFP (0x3)
1372 #define BOF (0x4)
1373 #define BOFP (0x5)
1374 #define BODNZT (0x8)
1375 #define BODNZTP (0x9)
1376 #define BODZT (0xa)
1377 #define BODZTP (0xb)
1378 #define BOT (0xc)
1379 #define BOTP (0xd)
1380 #define BODNZ (0x10)
1381 #define BODNZP (0x11)
1382 #define BODZ (0x12)
1383 #define BODZP (0x13)
1384 #define BOU (0x14)
1386 /* The BI condition bit encodings used in extended conditional branch
1387 mnemonics. */
1388 #define CBLT (0)
1389 #define CBGT (1)
1390 #define CBEQ (2)
1391 #define CBSO (3)
1393 /* The TO encodings used in extended trap mnemonics. */
1394 #define TOLGT (0x1)
1395 #define TOLLT (0x2)
1396 #define TOEQ (0x4)
1397 #define TOLGE (0x5)
1398 #define TOLNL (0x5)
1399 #define TOLLE (0x6)
1400 #define TOLNG (0x6)
1401 #define TOGT (0x8)
1402 #define TOGE (0xc)
1403 #define TONL (0xc)
1404 #define TOLT (0x10)
1405 #define TOLE (0x14)
1406 #define TONG (0x14)
1407 #define TONE (0x18)
1408 #define TOU (0x1f)
1410 /* Smaller names for the flags so each entry in the opcodes table will
1411 fit on a single line. */
1412 #undef PPC
1413 #define PPC PPC_OPCODE_PPC | PPC_OPCODE_ANY
1414 #define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_ANY
1415 #define PPC32 PPC_OPCODE_PPC | PPC_OPCODE_32 | PPC_OPCODE_ANY
1416 #define PPC64 PPC_OPCODE_64 | PPC_OPCODE_ANY
1417 #define PPCONLY PPC_OPCODE_PPC
1418 #define PPC403 PPC_OPCODE_403
1419 #define PPC405 PPC403
1420 #define PPC750 PPC
1421 #define PPC860 PPC
1422 #define PPCVEC PPC_OPCODE_ALTIVEC | PPC_OPCODE_ANY
1423 #define POWER PPC_OPCODE_POWER | PPC_OPCODE_ANY
1424 #define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_ANY
1425 #define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_ANY
1426 #define POWER32 PPC_OPCODE_POWER | PPC_OPCODE_ANY | PPC_OPCODE_32
1427 #define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_ANY
1428 #define COM32 PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_ANY | PPC_OPCODE_32
1429 #define M601 PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_ANY
1430 #define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON | PPC_OPCODE_ANY
1431 #define MFDEC1 PPC_OPCODE_POWER
1432 #define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601
1433 #define BOOKE PPC_OPCODE_BOOKE
1434 #define BOOKE64 PPC_OPCODE_BOOKE64
1436 /* The opcode table.
1438 The format of the opcode table is:
1440 NAME OPCODE MASK FLAGS { OPERANDS }
1442 NAME is the name of the instruction.
1443 OPCODE is the instruction opcode.
1444 MASK is the opcode mask; this is used to tell the disassembler
1445 which bits in the actual opcode must match OPCODE.
1446 FLAGS are flags indicated what processors support the instruction.
1447 OPERANDS is the list of operands.
1449 The disassembler reads the table in order and prints the first
1450 instruction which matches, so this table is sorted to put more
1451 specific instructions before more general instructions. It is also
1452 sorted by major opcode. */
1454 const struct powerpc_opcode powerpc_opcodes[] = {
1455 { "tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, { RA, SI } },
1456 { "tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, { RA, SI } },
1457 { "tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, { RA, SI } },
1458 { "tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC64, { RA, SI } },
1459 { "tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC64, { RA, SI } },
1460 { "tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, { RA, SI } },
1461 { "tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC64, { RA, SI } },
1462 { "tdgti", OPTO(2,TOGT), OPTO_MASK, PPC64, { RA, SI } },
1463 { "tdgei", OPTO(2,TOGE), OPTO_MASK, PPC64, { RA, SI } },
1464 { "tdnli", OPTO(2,TONL), OPTO_MASK, PPC64, { RA, SI } },
1465 { "tdlti", OPTO(2,TOLT), OPTO_MASK, PPC64, { RA, SI } },
1466 { "tdlei", OPTO(2,TOLE), OPTO_MASK, PPC64, { RA, SI } },
1467 { "tdngi", OPTO(2,TONG), OPTO_MASK, PPC64, { RA, SI } },
1468 { "tdnei", OPTO(2,TONE), OPTO_MASK, PPC64, { RA, SI } },
1469 { "tdi", OP(2), OP_MASK, PPC64, { TO, RA, SI } },
1471 { "twlgti", OPTO(3,TOLGT), OPTO_MASK, PPCCOM, { RA, SI } },
1472 { "tlgti", OPTO(3,TOLGT), OPTO_MASK, PWRCOM, { RA, SI } },
1473 { "twllti", OPTO(3,TOLLT), OPTO_MASK, PPCCOM, { RA, SI } },
1474 { "tllti", OPTO(3,TOLLT), OPTO_MASK, PWRCOM, { RA, SI } },
1475 { "tweqi", OPTO(3,TOEQ), OPTO_MASK, PPCCOM, { RA, SI } },
1476 { "teqi", OPTO(3,TOEQ), OPTO_MASK, PWRCOM, { RA, SI } },
1477 { "twlgei", OPTO(3,TOLGE), OPTO_MASK, PPCCOM, { RA, SI } },
1478 { "tlgei", OPTO(3,TOLGE), OPTO_MASK, PWRCOM, { RA, SI } },
1479 { "twlnli", OPTO(3,TOLNL), OPTO_MASK, PPCCOM, { RA, SI } },
1480 { "tlnli", OPTO(3,TOLNL), OPTO_MASK, PWRCOM, { RA, SI } },
1481 { "twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, { RA, SI } },
1482 { "tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, { RA, SI } },
1483 { "twlngi", OPTO(3,TOLNG), OPTO_MASK, PPCCOM, { RA, SI } },
1484 { "tlngi", OPTO(3,TOLNG), OPTO_MASK, PWRCOM, { RA, SI } },
1485 { "twgti", OPTO(3,TOGT), OPTO_MASK, PPCCOM, { RA, SI } },
1486 { "tgti", OPTO(3,TOGT), OPTO_MASK, PWRCOM, { RA, SI } },
1487 { "twgei", OPTO(3,TOGE), OPTO_MASK, PPCCOM, { RA, SI } },
1488 { "tgei", OPTO(3,TOGE), OPTO_MASK, PWRCOM, { RA, SI } },
1489 { "twnli", OPTO(3,TONL), OPTO_MASK, PPCCOM, { RA, SI } },
1490 { "tnli", OPTO(3,TONL), OPTO_MASK, PWRCOM, { RA, SI } },
1491 { "twlti", OPTO(3,TOLT), OPTO_MASK, PPCCOM, { RA, SI } },
1492 { "tlti", OPTO(3,TOLT), OPTO_MASK, PWRCOM, { RA, SI } },
1493 { "twlei", OPTO(3,TOLE), OPTO_MASK, PPCCOM, { RA, SI } },
1494 { "tlei", OPTO(3,TOLE), OPTO_MASK, PWRCOM, { RA, SI } },
1495 { "twngi", OPTO(3,TONG), OPTO_MASK, PPCCOM, { RA, SI } },
1496 { "tngi", OPTO(3,TONG), OPTO_MASK, PWRCOM, { RA, SI } },
1497 { "twnei", OPTO(3,TONE), OPTO_MASK, PPCCOM, { RA, SI } },
1498 { "tnei", OPTO(3,TONE), OPTO_MASK, PWRCOM, { RA, SI } },
1499 { "twi", OP(3), OP_MASK, PPCCOM, { TO, RA, SI } },
1500 { "ti", OP(3), OP_MASK, PWRCOM, { TO, RA, SI } },
1502 { "macchw", XO(4,172,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1503 { "macchw.", XO(4,172,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1504 { "macchwo", XO(4,172,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1505 { "macchwo.", XO(4,172,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1506 { "macchws", XO(4,236,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1507 { "macchws.", XO(4,236,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1508 { "macchwso", XO(4,236,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1509 { "macchwso.", XO(4,236,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1510 { "macchwsu", XO(4,204,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1511 { "macchwsu.", XO(4,204,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1512 { "macchwsuo", XO(4,204,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1513 { "macchwsuo.", XO(4,204,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1514 { "macchwu", XO(4,140,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1515 { "macchwu.", XO(4,140,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1516 { "macchwuo", XO(4,140,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1517 { "macchwuo.", XO(4,140,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1518 { "machhw", XO(4,44,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1519 { "machhw.", XO(4,44,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1520 { "machhwo", XO(4,44,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1521 { "machhwo.", XO(4,44,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1522 { "machhws", XO(4,108,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1523 { "machhws.", XO(4,108,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1524 { "machhwso", XO(4,108,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1525 { "machhwso.", XO(4,108,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1526 { "machhwsu", XO(4,76,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1527 { "machhwsu.", XO(4,76,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1528 { "machhwsuo", XO(4,76,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1529 { "machhwsuo.", XO(4,76,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1530 { "machhwu", XO(4,12,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1531 { "machhwu.", XO(4,12,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1532 { "machhwuo", XO(4,12,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1533 { "machhwuo.", XO(4,12,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1534 { "maclhw", XO(4,428,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1535 { "maclhw.", XO(4,428,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1536 { "maclhwo", XO(4,428,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1537 { "maclhwo.", XO(4,428,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1538 { "maclhws", XO(4,492,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1539 { "maclhws.", XO(4,492,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1540 { "maclhwso", XO(4,492,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1541 { "maclhwso.", XO(4,492,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1542 { "maclhwsu", XO(4,460,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1543 { "maclhwsu.", XO(4,460,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1544 { "maclhwsuo", XO(4,460,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1545 { "maclhwsuo.", XO(4,460,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1546 { "maclhwu", XO(4,396,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1547 { "maclhwu.", XO(4,396,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1548 { "maclhwuo", XO(4,396,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1549 { "maclhwuo.", XO(4,396,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1550 { "mulchw", XRC(4,168,0), X_MASK, PPC405, { RT, RA, RB } },
1551 { "mulchw.", XRC(4,168,1), X_MASK, PPC405, { RT, RA, RB } },
1552 { "mulchwu", XRC(4,136,0), X_MASK, PPC405, { RT, RA, RB } },
1553 { "mulchwu.", XRC(4,136,1), X_MASK, PPC405, { RT, RA, RB } },
1554 { "mulhhw", XRC(4,40,0), X_MASK, PPC405, { RT, RA, RB } },
1555 { "mulhhw.", XRC(4,40,1), X_MASK, PPC405, { RT, RA, RB } },
1556 { "mulhhwu", XRC(4,8,0), X_MASK, PPC405, { RT, RA, RB } },
1557 { "mulhhwu.", XRC(4,8,1), X_MASK, PPC405, { RT, RA, RB } },
1558 { "mullhw", XRC(4,424,0), X_MASK, PPC405, { RT, RA, RB } },
1559 { "mullhw.", XRC(4,424,1), X_MASK, PPC405, { RT, RA, RB } },
1560 { "mullhwu", XRC(4,392,0), X_MASK, PPC405, { RT, RA, RB } },
1561 { "mullhwu.", XRC(4,392,1), X_MASK, PPC405, { RT, RA, RB } },
1562 { "nmacchw", XO(4,174,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1563 { "nmacchw.", XO(4,174,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1564 { "nmacchwo", XO(4,174,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1565 { "nmacchwo.", XO(4,174,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1566 { "nmacchws", XO(4,238,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1567 { "nmacchws.", XO(4,238,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1568 { "nmacchwso", XO(4,238,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1569 { "nmacchwso.", XO(4,238,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1570 { "nmachhw", XO(4,46,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1571 { "nmachhw.", XO(4,46,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1572 { "nmachhwo", XO(4,46,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1573 { "nmachhwo.", XO(4,46,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1574 { "nmachhws", XO(4,110,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1575 { "nmachhws.", XO(4,110,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1576 { "nmachhwso", XO(4,110,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1577 { "nmachhwso.", XO(4,110,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1578 { "nmaclhw", XO(4,430,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1579 { "nmaclhw.", XO(4,430,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1580 { "nmaclhwo", XO(4,430,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1581 { "nmaclhwo.", XO(4,430,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1582 { "nmaclhws", XO(4,494,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1583 { "nmaclhws.", XO(4,494,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1584 { "nmaclhwso", XO(4,494,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1585 { "nmaclhwso.", XO(4,494,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1586 { "mfvscr", VX(4, 1540), VX_MASK, PPCVEC, { VD } },
1587 { "mtvscr", VX(4, 1604), VX_MASK, PPCVEC, { VD } },
1588 { "vaddcuw", VX(4, 384), VX_MASK, PPCVEC, { VD, VA, VB } },
1589 { "vaddfp", VX(4, 10), VX_MASK, PPCVEC, { VD, VA, VB } },
1590 { "vaddsbs", VX(4, 768), VX_MASK, PPCVEC, { VD, VA, VB } },
1591 { "vaddshs", VX(4, 832), VX_MASK, PPCVEC, { VD, VA, VB } },
1592 { "vaddsws", VX(4, 896), VX_MASK, PPCVEC, { VD, VA, VB } },
1593 { "vaddubm", VX(4, 0), VX_MASK, PPCVEC, { VD, VA, VB } },
1594 { "vaddubs", VX(4, 512), VX_MASK, PPCVEC, { VD, VA, VB } },
1595 { "vadduhm", VX(4, 64), VX_MASK, PPCVEC, { VD, VA, VB } },
1596 { "vadduhs", VX(4, 576), VX_MASK, PPCVEC, { VD, VA, VB } },
1597 { "vadduwm", VX(4, 128), VX_MASK, PPCVEC, { VD, VA, VB } },
1598 { "vadduws", VX(4, 640), VX_MASK, PPCVEC, { VD, VA, VB } },
1599 { "vand", VX(4, 1028), VX_MASK, PPCVEC, { VD, VA, VB } },
1600 { "vandc", VX(4, 1092), VX_MASK, PPCVEC, { VD, VA, VB } },
1601 { "vavgsb", VX(4, 1282), VX_MASK, PPCVEC, { VD, VA, VB } },
1602 { "vavgsh", VX(4, 1346), VX_MASK, PPCVEC, { VD, VA, VB } },
1603 { "vavgsw", VX(4, 1410), VX_MASK, PPCVEC, { VD, VA, VB } },
1604 { "vavgub", VX(4, 1026), VX_MASK, PPCVEC, { VD, VA, VB } },
1605 { "vavguh", VX(4, 1090), VX_MASK, PPCVEC, { VD, VA, VB } },
1606 { "vavguw", VX(4, 1154), VX_MASK, PPCVEC, { VD, VA, VB } },
1607 { "vcfsx", VX(4, 842), VX_MASK, PPCVEC, { VD, VB, UIMM } },
1608 { "vcfux", VX(4, 778), VX_MASK, PPCVEC, { VD, VB, UIMM } },
1609 { "vcmpbfp", VXR(4, 966, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1610 { "vcmpbfp.", VXR(4, 966, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1611 { "vcmpeqfp", VXR(4, 198, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1612 { "vcmpeqfp.", VXR(4, 198, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1613 { "vcmpequb", VXR(4, 6, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1614 { "vcmpequb.", VXR(4, 6, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1615 { "vcmpequh", VXR(4, 70, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1616 { "vcmpequh.", VXR(4, 70, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1617 { "vcmpequw", VXR(4, 134, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1618 { "vcmpequw.", VXR(4, 134, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1619 { "vcmpgefp", VXR(4, 454, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1620 { "vcmpgefp.", VXR(4, 454, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1621 { "vcmpgtfp", VXR(4, 710, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1622 { "vcmpgtfp.", VXR(4, 710, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1623 { "vcmpgtsb", VXR(4, 774, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1624 { "vcmpgtsb.", VXR(4, 774, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1625 { "vcmpgtsh", VXR(4, 838, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1626 { "vcmpgtsh.", VXR(4, 838, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1627 { "vcmpgtsw", VXR(4, 902, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1628 { "vcmpgtsw.", VXR(4, 902, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1629 { "vcmpgtub", VXR(4, 518, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1630 { "vcmpgtub.", VXR(4, 518, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1631 { "vcmpgtuh", VXR(4, 582, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1632 { "vcmpgtuh.", VXR(4, 582, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1633 { "vcmpgtuw", VXR(4, 646, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1634 { "vcmpgtuw.", VXR(4, 646, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1635 { "vctsxs", VX(4, 970), VX_MASK, PPCVEC, { VD, VB, UIMM } },
1636 { "vctuxs", VX(4, 906), VX_MASK, PPCVEC, { VD, VB, UIMM } },
1637 { "vexptefp", VX(4, 394), VX_MASK, PPCVEC, { VD, VB } },
1638 { "vlogefp", VX(4, 458), VX_MASK, PPCVEC, { VD, VB } },
1639 { "vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1640 { "vmaxfp", VX(4, 1034), VX_MASK, PPCVEC, { VD, VA, VB } },
1641 { "vmaxsb", VX(4, 258), VX_MASK, PPCVEC, { VD, VA, VB } },
1642 { "vmaxsh", VX(4, 322), VX_MASK, PPCVEC, { VD, VA, VB } },
1643 { "vmaxsw", VX(4, 386), VX_MASK, PPCVEC, { VD, VA, VB } },
1644 { "vmaxub", VX(4, 2), VX_MASK, PPCVEC, { VD, VA, VB } },
1645 { "vmaxuh", VX(4, 66), VX_MASK, PPCVEC, { VD, VA, VB } },
1646 { "vmaxuw", VX(4, 130), VX_MASK, PPCVEC, { VD, VA, VB } },
1647 { "vmhaddshs", VXA(4, 32), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1648 { "vmhraddshs", VXA(4, 33), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1649 { "vminfp", VX(4, 1098), VX_MASK, PPCVEC, { VD, VA, VB } },
1650 { "vminsb", VX(4, 770), VX_MASK, PPCVEC, { VD, VA, VB } },
1651 { "vminsh", VX(4, 834), VX_MASK, PPCVEC, { VD, VA, VB } },
1652 { "vminsw", VX(4, 898), VX_MASK, PPCVEC, { VD, VA, VB } },
1653 { "vminub", VX(4, 514), VX_MASK, PPCVEC, { VD, VA, VB } },
1654 { "vminuh", VX(4, 578), VX_MASK, PPCVEC, { VD, VA, VB } },
1655 { "vminuw", VX(4, 642), VX_MASK, PPCVEC, { VD, VA, VB } },
1656 { "vmladduhm", VXA(4, 34), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1657 { "vmrghb", VX(4, 12), VX_MASK, PPCVEC, { VD, VA, VB } },
1658 { "vmrghh", VX(4, 76), VX_MASK, PPCVEC, { VD, VA, VB } },
1659 { "vmrghw", VX(4, 140), VX_MASK, PPCVEC, { VD, VA, VB } },
1660 { "vmrglb", VX(4, 268), VX_MASK, PPCVEC, { VD, VA, VB } },
1661 { "vmrglh", VX(4, 332), VX_MASK, PPCVEC, { VD, VA, VB } },
1662 { "vmrglw", VX(4, 396), VX_MASK, PPCVEC, { VD, VA, VB } },
1663 { "vmsummbm", VXA(4, 37), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1664 { "vmsumshm", VXA(4, 40), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1665 { "vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1666 { "vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1667 { "vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1668 { "vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1669 { "vmulesb", VX(4, 776), VX_MASK, PPCVEC, { VD, VA, VB } },
1670 { "vmulesh", VX(4, 840), VX_MASK, PPCVEC, { VD, VA, VB } },
1671 { "vmuleub", VX(4, 520), VX_MASK, PPCVEC, { VD, VA, VB } },
1672 { "vmuleuh", VX(4, 584), VX_MASK, PPCVEC, { VD, VA, VB } },
1673 { "vmulosb", VX(4, 264), VX_MASK, PPCVEC, { VD, VA, VB } },
1674 { "vmulosh", VX(4, 328), VX_MASK, PPCVEC, { VD, VA, VB } },
1675 { "vmuloub", VX(4, 8), VX_MASK, PPCVEC, { VD, VA, VB } },
1676 { "vmulouh", VX(4, 72), VX_MASK, PPCVEC, { VD, VA, VB } },
1677 { "vnmsubfp", VXA(4, 47), VXA_MASK, PPCVEC, { VD, VA, VC, VB } },
1678 { "vnor", VX(4, 1284), VX_MASK, PPCVEC, { VD, VA, VB } },
1679 { "vor", VX(4, 1156), VX_MASK, PPCVEC, { VD, VA, VB } },
1680 { "vperm", VXA(4, 43), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1681 { "vpkpx", VX(4, 782), VX_MASK, PPCVEC, { VD, VA, VB } },
1682 { "vpkshss", VX(4, 398), VX_MASK, PPCVEC, { VD, VA, VB } },
1683 { "vpkshus", VX(4, 270), VX_MASK, PPCVEC, { VD, VA, VB } },
1684 { "vpkswss", VX(4, 462), VX_MASK, PPCVEC, { VD, VA, VB } },
1685 { "vpkswus", VX(4, 334), VX_MASK, PPCVEC, { VD, VA, VB } },
1686 { "vpkuhum", VX(4, 14), VX_MASK, PPCVEC, { VD, VA, VB } },
1687 { "vpkuhus", VX(4, 142), VX_MASK, PPCVEC, { VD, VA, VB } },
1688 { "vpkuwum", VX(4, 78), VX_MASK, PPCVEC, { VD, VA, VB } },
1689 { "vpkuwus", VX(4, 206), VX_MASK, PPCVEC, { VD, VA, VB } },
1690 { "vrefp", VX(4, 266), VX_MASK, PPCVEC, { VD, VB } },
1691 { "vrfim", VX(4, 714), VX_MASK, PPCVEC, { VD, VB } },
1692 { "vrfin", VX(4, 522), VX_MASK, PPCVEC, { VD, VB } },
1693 { "vrfip", VX(4, 650), VX_MASK, PPCVEC, { VD, VB } },
1694 { "vrfiz", VX(4, 586), VX_MASK, PPCVEC, { VD, VB } },
1695 { "vrlb", VX(4, 4), VX_MASK, PPCVEC, { VD, VA, VB } },
1696 { "vrlh", VX(4, 68), VX_MASK, PPCVEC, { VD, VA, VB } },
1697 { "vrlw", VX(4, 132), VX_MASK, PPCVEC, { VD, VA, VB } },
1698 { "vrsqrtefp", VX(4, 330), VX_MASK, PPCVEC, { VD, VB } },
1699 { "vsel", VXA(4, 42), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1700 { "vsl", VX(4, 452), VX_MASK, PPCVEC, { VD, VA, VB } },
1701 { "vslb", VX(4, 260), VX_MASK, PPCVEC, { VD, VA, VB } },
1702 { "vsldoi", VXA(4, 44), VXA_MASK, PPCVEC, { VD, VA, VB, SHB } },
1703 { "vslh", VX(4, 324), VX_MASK, PPCVEC, { VD, VA, VB } },
1704 { "vslo", VX(4, 1036), VX_MASK, PPCVEC, { VD, VA, VB } },
1705 { "vslw", VX(4, 388), VX_MASK, PPCVEC, { VD, VA, VB } },
1706 { "vspltb", VX(4, 524), VX_MASK, PPCVEC, { VD, VB, UIMM } },
1707 { "vsplth", VX(4, 588), VX_MASK, PPCVEC, { VD, VB, UIMM } },
1708 { "vspltisb", VX(4, 780), VX_MASK, PPCVEC, { VD, SIMM } },
1709 { "vspltish", VX(4, 844), VX_MASK, PPCVEC, { VD, SIMM } },
1710 { "vspltisw", VX(4, 908), VX_MASK, PPCVEC, { VD, SIMM } },
1711 { "vspltw", VX(4, 652), VX_MASK, PPCVEC, { VD, VB, UIMM } },
1712 { "vsr", VX(4, 708), VX_MASK, PPCVEC, { VD, VA, VB } },
1713 { "vsrab", VX(4, 772), VX_MASK, PPCVEC, { VD, VA, VB } },
1714 { "vsrah", VX(4, 836), VX_MASK, PPCVEC, { VD, VA, VB } },
1715 { "vsraw", VX(4, 900), VX_MASK, PPCVEC, { VD, VA, VB } },
1716 { "vsrb", VX(4, 516), VX_MASK, PPCVEC, { VD, VA, VB } },
1717 { "vsrh", VX(4, 580), VX_MASK, PPCVEC, { VD, VA, VB } },
1718 { "vsro", VX(4, 1100), VX_MASK, PPCVEC, { VD, VA, VB } },
1719 { "vsrw", VX(4, 644), VX_MASK, PPCVEC, { VD, VA, VB } },
1720 { "vsubcuw", VX(4, 1408), VX_MASK, PPCVEC, { VD, VA, VB } },
1721 { "vsubfp", VX(4, 74), VX_MASK, PPCVEC, { VD, VA, VB } },
1722 { "vsubsbs", VX(4, 1792), VX_MASK, PPCVEC, { VD, VA, VB } },
1723 { "vsubshs", VX(4, 1856), VX_MASK, PPCVEC, { VD, VA, VB } },
1724 { "vsubsws", VX(4, 1920), VX_MASK, PPCVEC, { VD, VA, VB } },
1725 { "vsububm", VX(4, 1024), VX_MASK, PPCVEC, { VD, VA, VB } },
1726 { "vsububs", VX(4, 1536), VX_MASK, PPCVEC, { VD, VA, VB } },
1727 { "vsubuhm", VX(4, 1088), VX_MASK, PPCVEC, { VD, VA, VB } },
1728 { "vsubuhs", VX(4, 1600), VX_MASK, PPCVEC, { VD, VA, VB } },
1729 { "vsubuwm", VX(4, 1152), VX_MASK, PPCVEC, { VD, VA, VB } },
1730 { "vsubuws", VX(4, 1664), VX_MASK, PPCVEC, { VD, VA, VB } },
1731 { "vsumsws", VX(4, 1928), VX_MASK, PPCVEC, { VD, VA, VB } },
1732 { "vsum2sws", VX(4, 1672), VX_MASK, PPCVEC, { VD, VA, VB } },
1733 { "vsum4sbs", VX(4, 1800), VX_MASK, PPCVEC, { VD, VA, VB } },
1734 { "vsum4shs", VX(4, 1608), VX_MASK, PPCVEC, { VD, VA, VB } },
1735 { "vsum4ubs", VX(4, 1544), VX_MASK, PPCVEC, { VD, VA, VB } },
1736 { "vupkhpx", VX(4, 846), VX_MASK, PPCVEC, { VD, VB } },
1737 { "vupkhsb", VX(4, 526), VX_MASK, PPCVEC, { VD, VB } },
1738 { "vupkhsh", VX(4, 590), VX_MASK, PPCVEC, { VD, VB } },
1739 { "vupklpx", VX(4, 974), VX_MASK, PPCVEC, { VD, VB } },
1740 { "vupklsb", VX(4, 654), VX_MASK, PPCVEC, { VD, VB } },
1741 { "vupklsh", VX(4, 718), VX_MASK, PPCVEC, { VD, VB } },
1742 { "vxor", VX(4, 1220), VX_MASK, PPCVEC, { VD, VA, VB } },
1744 { "mulli", OP(7), OP_MASK, PPCCOM, { RT, RA, SI } },
1745 { "muli", OP(7), OP_MASK, PWRCOM, { RT, RA, SI } },
1747 { "subfic", OP(8), OP_MASK, PPCCOM, { RT, RA, SI } },
1748 { "sfi", OP(8), OP_MASK, PWRCOM, { RT, RA, SI } },
1750 { "dozi", OP(9), OP_MASK, M601, { RT, RA, SI } },
1752 { "bce", B(9,0,0), B_MASK, BOOKE64, { BO, BI, BD } },
1753 { "bcel", B(9,0,1), B_MASK, BOOKE64, { BO, BI, BD } },
1754 { "bcea", B(9,1,0), B_MASK, BOOKE64, { BO, BI, BDA } },
1755 { "bcela", B(9,1,1), B_MASK, BOOKE64, { BO, BI, BDA } },
1757 { "cmplwi", OPL(10,0), OPL_MASK, PPCCOM, { OBF, RA, UI } },
1758 { "cmpldi", OPL(10,1), OPL_MASK, PPC64, { OBF, RA, UI } },
1759 { "cmpli", OP(10), OP_MASK, PPCONLY, { BF, L, RA, UI } },
1760 { "cmpli", OP(10), OP_MASK, PWRCOM, { BF, RA, UI } },
1762 { "cmpwi", OPL(11,0), OPL_MASK, PPCCOM, { OBF, RA, SI } },
1763 { "cmpdi", OPL(11,1), OPL_MASK, PPC64, { OBF, RA, SI } },
1764 { "cmpi", OP(11), OP_MASK, PPCONLY, { BF, L, RA, SI } },
1765 { "cmpi", OP(11), OP_MASK, PWRCOM, { BF, RA, SI } },
1767 { "addic", OP(12), OP_MASK, PPCCOM, { RT, RA, SI } },
1768 { "ai", OP(12), OP_MASK, PWRCOM, { RT, RA, SI } },
1769 { "subic", OP(12), OP_MASK, PPCCOM, { RT, RA, NSI } },
1771 { "addic.", OP(13), OP_MASK, PPCCOM, { RT, RA, SI } },
1772 { "ai.", OP(13), OP_MASK, PWRCOM, { RT, RA, SI } },
1773 { "subic.", OP(13), OP_MASK, PPCCOM, { RT, RA, NSI } },
1775 { "li", OP(14), DRA_MASK, PPCCOM, { RT, SI } },
1776 { "lil", OP(14), DRA_MASK, PWRCOM, { RT, SI } },
1777 { "addi", OP(14), OP_MASK, PPCCOM, { RT, RA, SI } },
1778 { "cal", OP(14), OP_MASK, PWRCOM, { RT, D, RA } },
1779 { "subi", OP(14), OP_MASK, PPCCOM, { RT, RA, NSI } },
1780 { "la", OP(14), OP_MASK, PPCCOM, { RT, D, RA } },
1782 { "lis", OP(15), DRA_MASK, PPCCOM, { RT, SISIGNOPT } },
1783 { "liu", OP(15), DRA_MASK, PWRCOM, { RT, SISIGNOPT } },
1784 { "addis", OP(15), OP_MASK, PPCCOM, { RT,RA,SISIGNOPT } },
1785 { "cau", OP(15), OP_MASK, PWRCOM, { RT,RA,SISIGNOPT } },
1786 { "subis", OP(15), OP_MASK, PPCCOM, { RT, RA, NSI } },
1788 { "bdnz-", BBO(16,BODNZ,0,0), BBOYBI_MASK, PPCCOM, { BDM } },
1789 { "bdnz+", BBO(16,BODNZ,0,0), BBOYBI_MASK, PPCCOM, { BDP } },
1790 { "bdnz", BBO(16,BODNZ,0,0), BBOYBI_MASK, PPCCOM, { BD } },
1791 { "bdn", BBO(16,BODNZ,0,0), BBOYBI_MASK, PWRCOM, { BD } },
1792 { "bdnzl-", BBO(16,BODNZ,0,1), BBOYBI_MASK, PPCCOM, { BDM } },
1793 { "bdnzl+", BBO(16,BODNZ,0,1), BBOYBI_MASK, PPCCOM, { BDP } },
1794 { "bdnzl", BBO(16,BODNZ,0,1), BBOYBI_MASK, PPCCOM, { BD } },
1795 { "bdnl", BBO(16,BODNZ,0,1), BBOYBI_MASK, PWRCOM, { BD } },
1796 { "bdnza-", BBO(16,BODNZ,1,0), BBOYBI_MASK, PPCCOM, { BDMA } },
1797 { "bdnza+", BBO(16,BODNZ,1,0), BBOYBI_MASK, PPCCOM, { BDPA } },
1798 { "bdnza", BBO(16,BODNZ,1,0), BBOYBI_MASK, PPCCOM, { BDA } },
1799 { "bdna", BBO(16,BODNZ,1,0), BBOYBI_MASK, PWRCOM, { BDA } },
1800 { "bdnzla-", BBO(16,BODNZ,1,1), BBOYBI_MASK, PPCCOM, { BDMA } },
1801 { "bdnzla+", BBO(16,BODNZ,1,1), BBOYBI_MASK, PPCCOM, { BDPA } },
1802 { "bdnzla", BBO(16,BODNZ,1,1), BBOYBI_MASK, PPCCOM, { BDA } },
1803 { "bdnla", BBO(16,BODNZ,1,1), BBOYBI_MASK, PWRCOM, { BDA } },
1804 { "bdz-", BBO(16,BODZ,0,0), BBOYBI_MASK, PPCCOM, { BDM } },
1805 { "bdz+", BBO(16,BODZ,0,0), BBOYBI_MASK, PPCCOM, { BDP } },
1806 { "bdz", BBO(16,BODZ,0,0), BBOYBI_MASK, COM, { BD } },
1807 { "bdzl-", BBO(16,BODZ,0,1), BBOYBI_MASK, PPCCOM, { BDM } },
1808 { "bdzl+", BBO(16,BODZ,0,1), BBOYBI_MASK, PPCCOM, { BDP } },
1809 { "bdzl", BBO(16,BODZ,0,1), BBOYBI_MASK, COM, { BD } },
1810 { "bdza-", BBO(16,BODZ,1,0), BBOYBI_MASK, PPCCOM, { BDMA } },
1811 { "bdza+", BBO(16,BODZ,1,0), BBOYBI_MASK, PPCCOM, { BDPA } },
1812 { "bdza", BBO(16,BODZ,1,0), BBOYBI_MASK, COM, { BDA } },
1813 { "bdzla-", BBO(16,BODZ,1,1), BBOYBI_MASK, PPCCOM, { BDMA } },
1814 { "bdzla+", BBO(16,BODZ,1,1), BBOYBI_MASK, PPCCOM, { BDPA } },
1815 { "bdzla", BBO(16,BODZ,1,1), BBOYBI_MASK, COM, { BDA } },
1816 { "blt-", BBOCB(16,BOT,CBLT,0,0), BBOYCB_MASK, PPCCOM, { CR, BDM } },
1817 { "blt+", BBOCB(16,BOT,CBLT,0,0), BBOYCB_MASK, PPCCOM, { CR, BDP } },
1818 { "blt", BBOCB(16,BOT,CBLT,0,0), BBOYCB_MASK, COM, { CR, BD } },
1819 { "bltl-", BBOCB(16,BOT,CBLT,0,1), BBOYCB_MASK, PPCCOM, { CR, BDM } },
1820 { "bltl+", BBOCB(16,BOT,CBLT,0,1), BBOYCB_MASK, PPCCOM, { CR, BDP } },
1821 { "bltl", BBOCB(16,BOT,CBLT,0,1), BBOYCB_MASK, COM, { CR, BD } },
1822 { "blta-", BBOCB(16,BOT,CBLT,1,0), BBOYCB_MASK, PPCCOM, { CR, BDMA } },
1823 { "blta+", BBOCB(16,BOT,CBLT,1,0), BBOYCB_MASK, PPCCOM, { CR, BDPA } },
1824 { "blta", BBOCB(16,BOT,CBLT,1,0), BBOYCB_MASK, COM, { CR, BDA } },
1825 { "bltla-", BBOCB(16,BOT,CBLT,1,1), BBOYCB_MASK, PPCCOM, { CR, BDMA } },
1826 { "bltla+", BBOCB(16,BOT,CBLT,1,1), BBOYCB_MASK, PPCCOM, { CR, BDPA } },
1827 { "bltla", BBOCB(16,BOT,CBLT,1,1), BBOYCB_MASK, COM, { CR, BDA } },
1828 { "bgt-", BBOCB(16,BOT,CBGT,0,0), BBOYCB_MASK, PPCCOM, { CR, BDM } },
1829 { "bgt+", BBOCB(16,BOT,CBGT,0,0), BBOYCB_MASK, PPCCOM, { CR, BDP } },
1830 { "bgt", BBOCB(16,BOT,CBGT,0,0), BBOYCB_MASK, COM, { CR, BD } },
1831 { "bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOYCB_MASK, PPCCOM, { CR, BDM } },
1832 { "bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOYCB_MASK, PPCCOM, { CR, BDP } },
1833 { "bgtl", BBOCB(16,BOT,CBGT,0,1), BBOYCB_MASK, COM, { CR, BD } },
1834 { "bgta-", BBOCB(16,BOT,CBGT,1,0), BBOYCB_MASK, PPCCOM, { CR, BDMA } },
1835 { "bgta+", BBOCB(16,BOT,CBGT,1,0), BBOYCB_MASK, PPCCOM, { CR, BDPA } },
1836 { "bgta", BBOCB(16,BOT,CBGT,1,0), BBOYCB_MASK, COM, { CR, BDA } },
1837 { "bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOYCB_MASK, PPCCOM, { CR, BDMA } },
1838 { "bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOYCB_MASK, PPCCOM, { CR, BDPA } },
1839 { "bgtla", BBOCB(16,BOT,CBGT,1,1), BBOYCB_MASK, COM, { CR, BDA } },
1840 { "beq-", BBOCB(16,BOT,CBEQ,0,0), BBOYCB_MASK, PPCCOM, { CR, BDM } },
1841 { "beq+", BBOCB(16,BOT,CBEQ,0,0), BBOYCB_MASK, PPCCOM, { CR, BDP } },
1842 { "beq", BBOCB(16,BOT,CBEQ,0,0), BBOYCB_MASK, COM, { CR, BD } },
1843 { "beql-", BBOCB(16,BOT,CBEQ,0,1), BBOYCB_MASK, PPCCOM, { CR, BDM } },
1844 { "beql+", BBOCB(16,BOT,CBEQ,0,1), BBOYCB_MASK, PPCCOM, { CR, BDP } },
1845 { "beql", BBOCB(16,BOT,CBEQ,0,1), BBOYCB_MASK, COM, { CR, BD } },
1846 { "beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOYCB_MASK, PPCCOM, { CR, BDMA } },
1847 { "beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOYCB_MASK, PPCCOM, { CR, BDPA } },
1848 { "beqa", BBOCB(16,BOT,CBEQ,1,0), BBOYCB_MASK, COM, { CR, BDA } },
1849 { "beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOYCB_MASK, PPCCOM, { CR, BDMA } },
1850 { "beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOYCB_MASK, PPCCOM, { CR, BDPA } },
1851 { "beqla", BBOCB(16,BOT,CBEQ,1,1), BBOYCB_MASK, COM, { CR, BDA } },
1852 { "bso-", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPCCOM, { CR, BDM } },
1853 { "bso+", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPCCOM, { CR, BDP } },
1854 { "bso", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, COM, { CR, BD } },
1855 { "bsol-", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPCCOM, { CR, BDM } },
1856 { "bsol+", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPCCOM, { CR, BDP } },
1857 { "bsol", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, COM, { CR, BD } },
1858 { "bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPCCOM, { CR, BDMA } },
1859 { "bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPCCOM, { CR, BDPA } },
1860 { "bsoa", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, COM, { CR, BDA } },
1861 { "bsola-", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPCCOM, { CR, BDMA } },
1862 { "bsola+", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPCCOM, { CR, BDPA } },
1863 { "bsola", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, COM, { CR, BDA } },
1864 { "bun-", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPCCOM, { CR, BDM } },
1865 { "bun+", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPCCOM, { CR, BDP } },
1866 { "bun", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPCCOM, { CR, BD } },
1867 { "bunl-", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPCCOM, { CR, BDM } },
1868 { "bunl+", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPCCOM, { CR, BDP } },
1869 { "bunl", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPCCOM, { CR, BD } },
1870 { "buna-", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPCCOM, { CR, BDMA } },
1871 { "buna+", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPCCOM, { CR, BDPA } },
1872 { "buna", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPCCOM, { CR, BDA } },
1873 { "bunla-", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPCCOM, { CR, BDMA } },
1874 { "bunla+", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPCCOM, { CR, BDPA } },
1875 { "bunla", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPCCOM, { CR, BDA } },
1876 { "bge-", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPCCOM, { CR, BDM } },
1877 { "bge+", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPCCOM, { CR, BDP } },
1878 { "bge", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, COM, { CR, BD } },
1879 { "bgel-", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPCCOM, { CR, BDM } },
1880 { "bgel+", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPCCOM, { CR, BDP } },
1881 { "bgel", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, COM, { CR, BD } },
1882 { "bgea-", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPCCOM, { CR, BDMA } },
1883 { "bgea+", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPCCOM, { CR, BDPA } },
1884 { "bgea", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, COM, { CR, BDA } },
1885 { "bgela-", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPCCOM, { CR, BDMA } },
1886 { "bgela+", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPCCOM, { CR, BDPA } },
1887 { "bgela", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, COM, { CR, BDA } },
1888 { "bnl-", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPCCOM, { CR, BDM } },
1889 { "bnl+", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPCCOM, { CR, BDP } },
1890 { "bnl", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, COM, { CR, BD } },
1891 { "bnll-", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPCCOM, { CR, BDM } },
1892 { "bnll+", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPCCOM, { CR, BDP } },
1893 { "bnll", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, COM, { CR, BD } },
1894 { "bnla-", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPCCOM, { CR, BDMA } },
1895 { "bnla+", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPCCOM, { CR, BDPA } },
1896 { "bnla", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, COM, { CR, BDA } },
1897 { "bnlla-", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPCCOM, { CR, BDMA } },
1898 { "bnlla+", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPCCOM, { CR, BDPA } },
1899 { "bnlla", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, COM, { CR, BDA } },
1900 { "ble-", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPCCOM, { CR, BDM } },
1901 { "ble+", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPCCOM, { CR, BDP } },
1902 { "ble", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, COM, { CR, BD } },
1903 { "blel-", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPCCOM, { CR, BDM } },
1904 { "blel+", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPCCOM, { CR, BDP } },
1905 { "blel", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, COM, { CR, BD } },
1906 { "blea-", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPCCOM, { CR, BDMA } },
1907 { "blea+", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPCCOM, { CR, BDPA } },
1908 { "blea", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, COM, { CR, BDA } },
1909 { "blela-", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPCCOM, { CR, BDMA } },
1910 { "blela+", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPCCOM, { CR, BDPA } },
1911 { "blela", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, COM, { CR, BDA } },
1912 { "bng-", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPCCOM, { CR, BDM } },
1913 { "bng+", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPCCOM, { CR, BDP } },
1914 { "bng", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, COM, { CR, BD } },
1915 { "bngl-", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPCCOM, { CR, BDM } },
1916 { "bngl+", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPCCOM, { CR, BDP } },
1917 { "bngl", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, COM, { CR, BD } },
1918 { "bnga-", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPCCOM, { CR, BDMA } },
1919 { "bnga+", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPCCOM, { CR, BDPA } },
1920 { "bnga", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, COM, { CR, BDA } },
1921 { "bngla-", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPCCOM, { CR, BDMA } },
1922 { "bngla+", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPCCOM, { CR, BDPA } },
1923 { "bngla", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, COM, { CR, BDA } },
1924 { "bne-", BBOCB(16,BOF,CBEQ,0,0), BBOYCB_MASK, PPCCOM, { CR, BDM } },
1925 { "bne+", BBOCB(16,BOF,CBEQ,0,0), BBOYCB_MASK, PPCCOM, { CR, BDP } },
1926 { "bne", BBOCB(16,BOF,CBEQ,0,0), BBOYCB_MASK, COM, { CR, BD } },
1927 { "bnel-", BBOCB(16,BOF,CBEQ,0,1), BBOYCB_MASK, PPCCOM, { CR, BDM } },
1928 { "bnel+", BBOCB(16,BOF,CBEQ,0,1), BBOYCB_MASK, PPCCOM, { CR, BDP } },
1929 { "bnel", BBOCB(16,BOF,CBEQ,0,1), BBOYCB_MASK, COM, { CR, BD } },
1930 { "bnea-", BBOCB(16,BOF,CBEQ,1,0), BBOYCB_MASK, PPCCOM, { CR, BDMA } },
1931 { "bnea+", BBOCB(16,BOF,CBEQ,1,0), BBOYCB_MASK, PPCCOM, { CR, BDPA } },
1932 { "bnea", BBOCB(16,BOF,CBEQ,1,0), BBOYCB_MASK, COM, { CR, BDA } },
1933 { "bnela-", BBOCB(16,BOF,CBEQ,1,1), BBOYCB_MASK, PPCCOM, { CR, BDMA } },
1934 { "bnela+", BBOCB(16,BOF,CBEQ,1,1), BBOYCB_MASK, PPCCOM, { CR, BDPA } },
1935 { "bnela", BBOCB(16,BOF,CBEQ,1,1), BBOYCB_MASK, COM, { CR, BDA } },
1936 { "bns-", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPCCOM, { CR, BDM } },
1937 { "bns+", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPCCOM, { CR, BDP } },
1938 { "bns", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, COM, { CR, BD } },
1939 { "bnsl-", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPCCOM, { CR, BDM } },
1940 { "bnsl+", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPCCOM, { CR, BDP } },
1941 { "bnsl", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, COM, { CR, BD } },
1942 { "bnsa-", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPCCOM, { CR, BDMA } },
1943 { "bnsa+", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPCCOM, { CR, BDPA } },
1944 { "bnsa", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, COM, { CR, BDA } },
1945 { "bnsla-", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPCCOM, { CR, BDMA } },
1946 { "bnsla+", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPCCOM, { CR, BDPA } },
1947 { "bnsla", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, COM, { CR, BDA } },
1948 { "bnu-", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPCCOM, { CR, BDM } },
1949 { "bnu+", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPCCOM, { CR, BDP } },
1950 { "bnu", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPCCOM, { CR, BD } },
1951 { "bnul-", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPCCOM, { CR, BDM } },
1952 { "bnul+", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPCCOM, { CR, BDP } },
1953 { "bnul", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPCCOM, { CR, BD } },
1954 { "bnua-", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPCCOM, { CR, BDMA } },
1955 { "bnua+", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPCCOM, { CR, BDPA } },
1956 { "bnua", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPCCOM, { CR, BDA } },
1957 { "bnula-", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPCCOM, { CR, BDMA } },
1958 { "bnula+", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPCCOM, { CR, BDPA } },
1959 { "bnula", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPCCOM, { CR, BDA } },
1960 { "bdnzt-", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, { BI, BDM } },
1961 { "bdnzt+", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, { BI, BDP } },
1962 { "bdnzt", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
1963 { "bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, { BI, BDM } },
1964 { "bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, { BI, BDP } },
1965 { "bdnztl", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
1966 { "bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, { BI, BDMA } },
1967 { "bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, { BI, BDPA } },
1968 { "bdnzta", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
1969 { "bdnztla-",BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, { BI, BDMA } },
1970 { "bdnztla+",BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, { BI, BDPA } },
1971 { "bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
1972 { "bdnzf-", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, { BI, BDM } },
1973 { "bdnzf+", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, { BI, BDP } },
1974 { "bdnzf", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
1975 { "bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, { BI, BDM } },
1976 { "bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, { BI, BDP } },
1977 { "bdnzfl", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
1978 { "bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, { BI, BDMA } },
1979 { "bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, { BI, BDPA } },
1980 { "bdnzfa", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
1981 { "bdnzfla-",BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, { BI, BDMA } },
1982 { "bdnzfla+",BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, { BI, BDPA } },
1983 { "bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
1984 { "bt-", BBO(16,BOT,0,0), BBOY_MASK, PPCCOM, { BI, BDM } },
1985 { "bt+", BBO(16,BOT,0,0), BBOY_MASK, PPCCOM, { BI, BDP } },
1986 { "bt", BBO(16,BOT,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
1987 { "bbt", BBO(16,BOT,0,0), BBOY_MASK, PWRCOM, { BI, BD } },
1988 { "btl-", BBO(16,BOT,0,1), BBOY_MASK, PPCCOM, { BI, BDM } },
1989 { "btl+", BBO(16,BOT,0,1), BBOY_MASK, PPCCOM, { BI, BDP } },
1990 { "btl", BBO(16,BOT,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
1991 { "bbtl", BBO(16,BOT,0,1), BBOY_MASK, PWRCOM, { BI, BD } },
1992 { "bta-", BBO(16,BOT,1,0), BBOY_MASK, PPCCOM, { BI, BDMA } },
1993 { "bta+", BBO(16,BOT,1,0), BBOY_MASK, PPCCOM, { BI, BDPA } },
1994 { "bta", BBO(16,BOT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
1995 { "bbta", BBO(16,BOT,1,0), BBOY_MASK, PWRCOM, { BI, BDA } },
1996 { "btla-", BBO(16,BOT,1,1), BBOY_MASK, PPCCOM, { BI, BDMA } },
1997 { "btla+", BBO(16,BOT,1,1), BBOY_MASK, PPCCOM, { BI, BDPA } },
1998 { "btla", BBO(16,BOT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
1999 { "bbtla", BBO(16,BOT,1,1), BBOY_MASK, PWRCOM, { BI, BDA } },
2000 { "bf-", BBO(16,BOF,0,0), BBOY_MASK, PPCCOM, { BI, BDM } },
2001 { "bf+", BBO(16,BOF,0,0), BBOY_MASK, PPCCOM, { BI, BDP } },
2002 { "bf", BBO(16,BOF,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
2003 { "bbf", BBO(16,BOF,0,0), BBOY_MASK, PWRCOM, { BI, BD } },
2004 { "bfl-", BBO(16,BOF,0,1), BBOY_MASK, PPCCOM, { BI, BDM } },
2005 { "bfl+", BBO(16,BOF,0,1), BBOY_MASK, PPCCOM, { BI, BDP } },
2006 { "bfl", BBO(16,BOF,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
2007 { "bbfl", BBO(16,BOF,0,1), BBOY_MASK, PWRCOM, { BI, BD } },
2008 { "bfa-", BBO(16,BOF,1,0), BBOY_MASK, PPCCOM, { BI, BDMA } },
2009 { "bfa+", BBO(16,BOF,1,0), BBOY_MASK, PPCCOM, { BI, BDPA } },
2010 { "bfa", BBO(16,BOF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
2011 { "bbfa", BBO(16,BOF,1,0), BBOY_MASK, PWRCOM, { BI, BDA } },
2012 { "bfla-", BBO(16,BOF,1,1), BBOY_MASK, PPCCOM, { BI, BDMA } },
2013 { "bfla+", BBO(16,BOF,1,1), BBOY_MASK, PPCCOM, { BI, BDPA } },
2014 { "bfla", BBO(16,BOF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
2015 { "bbfla", BBO(16,BOF,1,1), BBOY_MASK, PWRCOM, { BI, BDA } },
2016 { "bdzt-", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, { BI, BDM } },
2017 { "bdzt+", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, { BI, BDP } },
2018 { "bdzt", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
2019 { "bdztl-", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, { BI, BDM } },
2020 { "bdztl+", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, { BI, BDP } },
2021 { "bdztl", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
2022 { "bdzta-", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, { BI, BDMA } },
2023 { "bdzta+", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, { BI, BDPA } },
2024 { "bdzta", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
2025 { "bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, { BI, BDMA } },
2026 { "bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, { BI, BDPA } },
2027 { "bdztla", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
2028 { "bdzf-", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, { BI, BDM } },
2029 { "bdzf+", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, { BI, BDP } },
2030 { "bdzf", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
2031 { "bdzfl-", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, { BI, BDM } },
2032 { "bdzfl+", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, { BI, BDP } },
2033 { "bdzfl", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
2034 { "bdzfa-", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, { BI, BDMA } },
2035 { "bdzfa+", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, { BI, BDPA } },
2036 { "bdzfa", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
2037 { "bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, { BI, BDMA } },
2038 { "bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, { BI, BDPA } },
2039 { "bdzfla", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
2040 { "bc-", B(16,0,0), B_MASK, PPCCOM, { BOE, BI, BDM } },
2041 { "bc+", B(16,0,0), B_MASK, PPCCOM, { BOE, BI, BDP } },
2042 { "bc", B(16,0,0), B_MASK, COM, { BO, BI, BD } },
2043 { "bcl-", B(16,0,1), B_MASK, PPCCOM, { BOE, BI, BDM } },
2044 { "bcl+", B(16,0,1), B_MASK, PPCCOM, { BOE, BI, BDP } },
2045 { "bcl", B(16,0,1), B_MASK, COM, { BO, BI, BD } },
2046 { "bca-", B(16,1,0), B_MASK, PPCCOM, { BOE, BI, BDMA } },
2047 { "bca+", B(16,1,0), B_MASK, PPCCOM, { BOE, BI, BDPA } },
2048 { "bca", B(16,1,0), B_MASK, COM, { BO, BI, BDA } },
2049 { "bcla-", B(16,1,1), B_MASK, PPCCOM, { BOE, BI, BDMA } },
2050 { "bcla+", B(16,1,1), B_MASK, PPCCOM, { BOE, BI, BDPA } },
2051 { "bcla", B(16,1,1), B_MASK, COM, { BO, BI, BDA } },
2053 { "sc", SC(17,1,0), 0xffffffff, PPC, { 0 } },
2054 { "svc", SC(17,0,0), SC_MASK, POWER, { LEV, FL1, FL2 } },
2055 { "svcl", SC(17,0,1), SC_MASK, POWER, { LEV, FL1, FL2 } },
2056 { "svca", SC(17,1,0), SC_MASK, PWRCOM, { SV } },
2057 { "svcla", SC(17,1,1), SC_MASK, POWER, { SV } },
2059 { "b", B(18,0,0), B_MASK, COM, { LI } },
2060 { "bl", B(18,0,1), B_MASK, COM, { LI } },
2061 { "ba", B(18,1,0), B_MASK, COM, { LIA } },
2062 { "bla", B(18,1,1), B_MASK, COM, { LIA } },
2064 { "mcrf", XL(19,0), XLBB_MASK|(3<<21)|(3<<16), COM, { BF, BFA } },
2066 { "blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
2067 { "br", XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM, { 0 } },
2068 { "blrl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
2069 { "brl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM, { 0 } },
2070 { "bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
2071 { "bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
2072 { "bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
2073 { "bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
2074 { "bdnzlrl-",XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
2075 { "bdnzlrl+",XLO(19,BODNZP,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
2076 { "bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
2077 { "bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
2078 { "bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
2079 { "bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
2080 { "bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
2081 { "bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
2082 { "bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2083 { "bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2084 { "bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2085 { "bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2086 { "bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2087 { "bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2088 { "bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2089 { "bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2090 { "bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2091 { "bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2092 { "bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2093 { "bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2094 { "bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2095 { "bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2096 { "bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2097 { "bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2098 { "beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2099 { "beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2100 { "beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2101 { "beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2102 { "beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2103 { "beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2104 { "beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2105 { "beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2106 { "bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2107 { "bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2108 { "bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2109 { "bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2110 { "bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2111 { "bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2112 { "bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2113 { "bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2114 { "bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2115 { "bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2116 { "bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2117 { "bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2118 { "bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2119 { "bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2120 { "bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2121 { "bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2122 { "bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2123 { "bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2124 { "bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2125 { "bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2126 { "bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2127 { "bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2128 { "bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2129 { "bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2130 { "bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2131 { "bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2132 { "bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2133 { "bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2134 { "bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2135 { "bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2136 { "blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2137 { "blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2138 { "blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2139 { "bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2140 { "blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2141 { "blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2142 { "blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2143 { "blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2144 { "bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2145 { "bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2146 { "bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2147 { "bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2148 { "bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2149 { "bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2150 { "bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2151 { "bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2152 { "bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2153 { "bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2154 { "bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2155 { "bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2156 { "bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2157 { "bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2158 { "bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2159 { "bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2160 { "bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2161 { "bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2162 { "bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2163 { "bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2164 { "bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2165 { "bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2166 { "bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2167 { "bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2168 { "bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2169 { "bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2170 { "bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2171 { "bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2172 { "bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2173 { "bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2174 { "btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2175 { "btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2176 { "btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2177 { "bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM, { BI } },
2178 { "btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2179 { "btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2180 { "btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2181 { "bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM, { BI } },
2182 { "bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2183 { "bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2184 { "bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2185 { "bbfr", XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM, { BI } },
2186 { "bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2187 { "bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2188 { "bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2189 { "bbfrl", XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM, { BI } },
2190 { "bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2191 { "bdnztlr-",XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2192 { "bdnztlr+",XLO(19,BODNZTP,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2193 { "bdnztlrl",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2194 { "bdnztlrl-",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2195 { "bdnztlrl+",XLO(19,BODNZTP,16,1), XLBOBB_MASK, PPCCOM,{ BI } },
2196 { "bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2197 { "bdnzflr-",XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2198 { "bdnzflr+",XLO(19,BODNZFP,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2199 { "bdnzflrl",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2200 { "bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2201 { "bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, PPCCOM,{ BI } },
2202 { "bdztlr", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2203 { "bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2204 { "bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2205 { "bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2206 { "bdztlrl-",XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2207 { "bdztlrl+",XLO(19,BODZTP,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2208 { "bdzflr", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2209 { "bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2210 { "bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2211 { "bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2212 { "bdzflrl-",XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2213 { "bdzflrl+",XLO(19,BODZFP,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2214 { "bclr", XLLK(19,16,0), XLYBB_MASK, PPCCOM, { BO, BI } },
2215 { "bclrl", XLLK(19,16,1), XLYBB_MASK, PPCCOM, { BO, BI } },
2216 { "bclr+", XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
2217 { "bclrl+", XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
2218 { "bclr-", XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
2219 { "bclrl-", XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
2220 { "bcr", XLLK(19,16,0), XLBB_MASK, PWRCOM, { BO, BI } },
2221 { "bcrl", XLLK(19,16,1), XLBB_MASK, PWRCOM, { BO, BI } },
2222 { "bclre", XLLK(19,17,0), XLBB_MASK, BOOKE64, { BO, BI } },
2223 { "bclrel", XLLK(19,17,1), XLBB_MASK, BOOKE64, { BO, BI } },
2225 { "rfid", XL(19,18), 0xffffffff, PPC64, { 0 } },
2227 { "crnot", XL(19,33), XL_MASK, PPCCOM, { BT, BA, BBA } },
2228 { "crnor", XL(19,33), XL_MASK, COM, { BT, BA, BB } },
2230 { "rfi", XL(19,50), 0xffffffff, COM, { 0 } },
2231 { "rfci", XL(19,51), 0xffffffff, PPC403, { 0 } },
2232 { "rfci", XL(19,51), 0xffffffff, BOOKE, { 0 } },
2234 { "rfsvc", XL(19,82), 0xffffffff, POWER, { 0 } },
2236 { "crandc", XL(19,129), XL_MASK, COM, { BT, BA, BB } },
2238 { "isync", XL(19,150), 0xffffffff, PPCCOM, { 0 } },
2239 { "ics", XL(19,150), 0xffffffff, PWRCOM, { 0 } },
2241 { "crclr", XL(19,193), XL_MASK, PPCCOM, { BT, BAT, BBA } },
2242 { "crxor", XL(19,193), XL_MASK, COM, { BT, BA, BB } },
2244 { "crnand", XL(19,225), XL_MASK, COM, { BT, BA, BB } },
2246 { "crand", XL(19,257), XL_MASK, COM, { BT, BA, BB } },
2248 { "crset", XL(19,289), XL_MASK, PPCCOM, { BT, BAT, BBA } },
2249 { "creqv", XL(19,289), XL_MASK, COM, { BT, BA, BB } },
2251 { "crorc", XL(19,417), XL_MASK, COM, { BT, BA, BB } },
2253 { "crmove", XL(19,449), XL_MASK, PPCCOM, { BT, BA, BBA } },
2254 { "cror", XL(19,449), XL_MASK, COM, { BT, BA, BB } },
2256 { "bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, COM, { 0 } },
2257 { "bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, { 0 } },
2258 { "bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2259 { "bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2260 { "bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2261 { "bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2262 { "bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2263 { "bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2264 { "bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2265 { "bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2266 { "bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2267 { "bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2268 { "bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2269 { "bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2270 { "beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2271 { "beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2272 { "beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2273 { "beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2274 { "beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2275 { "beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2276 { "bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2277 { "bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2278 { "bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2279 { "bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2280 { "bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2281 { "bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2282 { "bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2283 { "bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2284 { "bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2285 { "bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2286 { "bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2287 { "bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2288 { "bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2289 { "bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2290 { "bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2291 { "bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2292 { "bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2293 { "bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2294 { "bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2295 { "bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2296 { "bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2297 { "bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2298 { "bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2299 { "bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2300 { "blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2301 { "blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2302 { "blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2303 { "blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2304 { "blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2305 { "blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2306 { "bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2307 { "bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2308 { "bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2309 { "bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2310 { "bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2311 { "bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2312 { "bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2313 { "bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2314 { "bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2315 { "bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2316 { "bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2317 { "bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2318 { "bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2319 { "bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2320 { "bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2321 { "bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2322 { "bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2323 { "bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2324 { "bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2325 { "bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2326 { "bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2327 { "bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2328 { "bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2329 { "bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2330 { "btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, { BI } },
2331 { "btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, { BI } },
2332 { "btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, PPCCOM, { BI } },
2333 { "btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, { BI } },
2334 { "btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, { BI } },
2335 { "btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, PPCCOM, { BI } },
2336 { "bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, { BI } },
2337 { "bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, { BI } },
2338 { "bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, PPCCOM, { BI } },
2339 { "bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, { BI } },
2340 { "bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, { BI } },
2341 { "bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, PPCCOM, { BI } },
2342 { "bcctr", XLLK(19,528,0), XLYBB_MASK, PPCCOM, { BO, BI } },
2343 { "bcctr-", XLYLK(19,528,0,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
2344 { "bcctr+", XLYLK(19,528,1,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
2345 { "bcctrl", XLLK(19,528,1), XLYBB_MASK, PPCCOM, { BO, BI } },
2346 { "bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
2347 { "bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
2348 { "bcc", XLLK(19,528,0), XLBB_MASK, PWRCOM, { BO, BI } },
2349 { "bccl", XLLK(19,528,1), XLBB_MASK, PWRCOM, { BO, BI } },
2350 { "bcctre", XLLK(19,529,0), XLYBB_MASK, BOOKE64, { BO, BI } },
2351 { "bcctrel", XLLK(19,529,1), XLYBB_MASK, BOOKE64, { BO, BI } },
2353 { "rlwimi", M(20,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
2354 { "rlimi", M(20,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
2356 { "rlwimi.", M(20,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
2357 { "rlimi.", M(20,1), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
2359 { "rotlwi", MME(21,31,0), MMBME_MASK, PPCCOM, { RA, RS, SH } },
2360 { "clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, { RA, RS, MB } },
2361 { "rlwinm", M(21,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
2362 { "rlinm", M(21,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
2363 { "rotlwi.", MME(21,31,1), MMBME_MASK, PPCCOM, { RA,RS,SH } },
2364 { "clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, { RA, RS, MB } },
2365 { "rlwinm.", M(21,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
2366 { "rlinm.", M(21,1), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
2368 { "rlmi", M(22,0), M_MASK, M601, { RA,RS,RB,MBE,ME } },
2369 { "rlmi.", M(22,1), M_MASK, M601, { RA,RS,RB,MBE,ME } },
2371 { "be", B(22,0,0), B_MASK, BOOKE64, { LI } },
2372 { "bel", B(22,0,1), B_MASK, BOOKE64, { LI } },
2373 { "bea", B(22,1,0), B_MASK, BOOKE64, { LIA } },
2374 { "bela", B(22,1,1), B_MASK, BOOKE64, { LIA } },
2376 { "rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, { RA, RS, RB } },
2377 { "rlwnm", M(23,0), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } },
2378 { "rlnm", M(23,0), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } },
2379 { "rotlw.", MME(23,31,1), MMBME_MASK, PPCCOM, { RA, RS, RB } },
2380 { "rlwnm.", M(23,1), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } },
2381 { "rlnm.", M(23,1), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } },
2383 { "nop", OP(24), 0xffffffff, PPCCOM, { 0 } },
2384 { "ori", OP(24), OP_MASK, PPCCOM, { RA, RS, UI } },
2385 { "oril", OP(24), OP_MASK, PWRCOM, { RA, RS, UI } },
2387 { "oris", OP(25), OP_MASK, PPCCOM, { RA, RS, UI } },
2388 { "oriu", OP(25), OP_MASK, PWRCOM, { RA, RS, UI } },
2390 { "xori", OP(26), OP_MASK, PPCCOM, { RA, RS, UI } },
2391 { "xoril", OP(26), OP_MASK, PWRCOM, { RA, RS, UI } },
2393 { "xoris", OP(27), OP_MASK, PPCCOM, { RA, RS, UI } },
2394 { "xoriu", OP(27), OP_MASK, PWRCOM, { RA, RS, UI } },
2396 { "andi.", OP(28), OP_MASK, PPCCOM, { RA, RS, UI } },
2397 { "andil.", OP(28), OP_MASK, PWRCOM, { RA, RS, UI } },
2399 { "andis.", OP(29), OP_MASK, PPCCOM, { RA, RS, UI } },
2400 { "andiu.", OP(29), OP_MASK, PWRCOM, { RA, RS, UI } },
2402 { "rotldi", MD(30,0,0), MDMB_MASK, PPC64, { RA, RS, SH6 } },
2403 { "clrldi", MD(30,0,0), MDSH_MASK, PPC64, { RA, RS, MB6 } },
2404 { "rldicl", MD(30,0,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
2405 { "rotldi.", MD(30,0,1), MDMB_MASK, PPC64, { RA, RS, SH6 } },
2406 { "clrldi.", MD(30,0,1), MDSH_MASK, PPC64, { RA, RS, MB6 } },
2407 { "rldicl.", MD(30,0,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
2409 { "rldicr", MD(30,1,0), MD_MASK, PPC64, { RA, RS, SH6, ME6 } },
2410 { "rldicr.", MD(30,1,1), MD_MASK, PPC64, { RA, RS, SH6, ME6 } },
2412 { "rldic", MD(30,2,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
2413 { "rldic.", MD(30,2,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
2415 { "rldimi", MD(30,3,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
2416 { "rldimi.", MD(30,3,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
2418 { "rotld", MDS(30,8,0), MDSMB_MASK, PPC64, { RA, RS, RB } },
2419 { "rldcl", MDS(30,8,0), MDS_MASK, PPC64, { RA, RS, RB, MB6 } },
2420 { "rotld.", MDS(30,8,1), MDSMB_MASK, PPC64, { RA, RS, RB } },
2421 { "rldcl.", MDS(30,8,1), MDS_MASK, PPC64, { RA, RS, RB, MB6 } },
2423 { "rldcr", MDS(30,9,0), MDS_MASK, PPC64, { RA, RS, RB, ME6 } },
2424 { "rldcr.", MDS(30,9,1), MDS_MASK, PPC64, { RA, RS, RB, ME6 } },
2426 { "cmpw", XCMPL(31,0,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } },
2427 { "cmpd", XCMPL(31,0,1), XCMPL_MASK, PPC64, { OBF, RA, RB } },
2428 { "cmp", X(31,0), XCMP_MASK, PPCONLY, { BF, L, RA, RB } },
2429 { "cmp", X(31,0), XCMPL_MASK, PWRCOM, { BF, RA, RB } },
2431 { "twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, { RA, RB } },
2432 { "tlgt", XTO(31,4,TOLGT), XTO_MASK, PWRCOM, { RA, RB } },
2433 { "twllt", XTO(31,4,TOLLT), XTO_MASK, PPCCOM, { RA, RB } },
2434 { "tllt", XTO(31,4,TOLLT), XTO_MASK, PWRCOM, { RA, RB } },
2435 { "tweq", XTO(31,4,TOEQ), XTO_MASK, PPCCOM, { RA, RB } },
2436 { "teq", XTO(31,4,TOEQ), XTO_MASK, PWRCOM, { RA, RB } },
2437 { "twlge", XTO(31,4,TOLGE), XTO_MASK, PPCCOM, { RA, RB } },
2438 { "tlge", XTO(31,4,TOLGE), XTO_MASK, PWRCOM, { RA, RB } },
2439 { "twlnl", XTO(31,4,TOLNL), XTO_MASK, PPCCOM, { RA, RB } },
2440 { "tlnl", XTO(31,4,TOLNL), XTO_MASK, PWRCOM, { RA, RB } },
2441 { "twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, { RA, RB } },
2442 { "tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, { RA, RB } },
2443 { "twlng", XTO(31,4,TOLNG), XTO_MASK, PPCCOM, { RA, RB } },
2444 { "tlng", XTO(31,4,TOLNG), XTO_MASK, PWRCOM, { RA, RB } },
2445 { "twgt", XTO(31,4,TOGT), XTO_MASK, PPCCOM, { RA, RB } },
2446 { "tgt", XTO(31,4,TOGT), XTO_MASK, PWRCOM, { RA, RB } },
2447 { "twge", XTO(31,4,TOGE), XTO_MASK, PPCCOM, { RA, RB } },
2448 { "tge", XTO(31,4,TOGE), XTO_MASK, PWRCOM, { RA, RB } },
2449 { "twnl", XTO(31,4,TONL), XTO_MASK, PPCCOM, { RA, RB } },
2450 { "tnl", XTO(31,4,TONL), XTO_MASK, PWRCOM, { RA, RB } },
2451 { "twlt", XTO(31,4,TOLT), XTO_MASK, PPCCOM, { RA, RB } },
2452 { "tlt", XTO(31,4,TOLT), XTO_MASK, PWRCOM, { RA, RB } },
2453 { "twle", XTO(31,4,TOLE), XTO_MASK, PPCCOM, { RA, RB } },
2454 { "tle", XTO(31,4,TOLE), XTO_MASK, PWRCOM, { RA, RB } },
2455 { "twng", XTO(31,4,TONG), XTO_MASK, PPCCOM, { RA, RB } },
2456 { "tng", XTO(31,4,TONG), XTO_MASK, PWRCOM, { RA, RB } },
2457 { "twne", XTO(31,4,TONE), XTO_MASK, PPCCOM, { RA, RB } },
2458 { "tne", XTO(31,4,TONE), XTO_MASK, PWRCOM, { RA, RB } },
2459 { "trap", XTO(31,4,TOU), 0xffffffff, PPCCOM, { 0 } },
2460 { "tw", X(31,4), X_MASK, PPCCOM, { TO, RA, RB } },
2461 { "t", X(31,4), X_MASK, PWRCOM, { TO, RA, RB } },
2463 { "subfc", XO(31,8,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
2464 { "sf", XO(31,8,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
2465 { "subc", XO(31,8,0,0), XO_MASK, PPC, { RT, RB, RA } },
2466 { "subfc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
2467 { "sf.", XO(31,8,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
2468 { "subc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RB, RA } },
2469 { "subfco", XO(31,8,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
2470 { "sfo", XO(31,8,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
2471 { "subco", XO(31,8,1,0), XO_MASK, PPC, { RT, RB, RA } },
2472 { "subfco.", XO(31,8,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
2473 { "sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
2474 { "subco.", XO(31,8,1,1), XO_MASK, PPC, { RT, RB, RA } },
2476 { "mulhdu", XO(31,9,0,0), XO_MASK, PPC64, { RT, RA, RB } },
2477 { "mulhdu.", XO(31,9,0,1), XO_MASK, PPC64, { RT, RA, RB } },
2479 { "addc", XO(31,10,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
2480 { "a", XO(31,10,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
2481 { "addc.", XO(31,10,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
2482 { "a.", XO(31,10,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
2483 { "addco", XO(31,10,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
2484 { "ao", XO(31,10,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
2485 { "addco.", XO(31,10,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
2486 { "ao.", XO(31,10,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
2488 { "mulhwu", XO(31,11,0,0), XO_MASK, PPC, { RT, RA, RB } },
2489 { "mulhwu.", XO(31,11,0,1), XO_MASK, PPC, { RT, RA, RB } },
2491 { "mfcr", X(31,19), XRARB_MASK, COM, { RT } },
2493 { "lwarx", X(31,20), X_MASK, PPC, { RT, RA, RB } },
2495 { "ldx", X(31,21), X_MASK, PPC64, { RT, RA, RB } },
2497 { "icbt", X(31,22), X_MASK, BOOKE, { CT, RA, RB } },
2499 { "lwzx", X(31,23), X_MASK, PPCCOM, { RT, RA, RB } },
2500 { "lx", X(31,23), X_MASK, PWRCOM, { RT, RA, RB } },
2502 { "slw", XRC(31,24,0), X_MASK, PPCCOM, { RA, RS, RB } },
2503 { "sl", XRC(31,24,0), X_MASK, PWRCOM, { RA, RS, RB } },
2504 { "slw.", XRC(31,24,1), X_MASK, PPCCOM, { RA, RS, RB } },
2505 { "sl.", XRC(31,24,1), X_MASK, PWRCOM, { RA, RS, RB } },
2507 { "cntlzw", XRC(31,26,0), XRB_MASK, PPCCOM, { RA, RS } },
2508 { "cntlz", XRC(31,26,0), XRB_MASK, PWRCOM, { RA, RS } },
2509 { "cntlzw.", XRC(31,26,1), XRB_MASK, PPCCOM, { RA, RS } },
2510 { "cntlz.", XRC(31,26,1), XRB_MASK, PWRCOM, { RA, RS } },
2512 { "sld", XRC(31,27,0), X_MASK, PPC64, { RA, RS, RB } },
2513 { "sld.", XRC(31,27,1), X_MASK, PPC64, { RA, RS, RB } },
2515 { "and", XRC(31,28,0), X_MASK, COM, { RA, RS, RB } },
2516 { "and.", XRC(31,28,1), X_MASK, COM, { RA, RS, RB } },
2518 { "maskg", XRC(31,29,0), X_MASK, M601, { RA, RS, RB } },
2519 { "maskg.", XRC(31,29,1), X_MASK, M601, { RA, RS, RB } },
2521 { "icbte", X(31,30), X_MASK, BOOKE64, { CT, RA, RB } },
2523 { "lwzxe", X(31,31), X_MASK, BOOKE64, { RT, RA, RB } },
2525 { "cmplw", XCMPL(31,32,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } },
2526 { "cmpld", XCMPL(31,32,1), XCMPL_MASK, PPC64, { OBF, RA, RB } },
2527 { "cmpl", X(31,32), XCMP_MASK, PPCONLY, { BF, L, RA, RB } },
2528 { "cmpl", X(31,32), XCMPL_MASK, PWRCOM, { BF, RA, RB } },
2530 { "subf", XO(31,40,0,0), XO_MASK, PPC, { RT, RA, RB } },
2531 { "sub", XO(31,40,0,0), XO_MASK, PPC, { RT, RB, RA } },
2532 { "subf.", XO(31,40,0,1), XO_MASK, PPC, { RT, RA, RB } },
2533 { "sub.", XO(31,40,0,1), XO_MASK, PPC, { RT, RB, RA } },
2534 { "subfo", XO(31,40,1,0), XO_MASK, PPC, { RT, RA, RB } },
2535 { "subo", XO(31,40,1,0), XO_MASK, PPC, { RT, RB, RA } },
2536 { "subfo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RA, RB } },
2537 { "subo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RB, RA } },
2539 { "ldux", X(31,53), X_MASK, PPC64, { RT, RAL, RB } },
2541 { "dcbst", X(31,54), XRT_MASK, PPC, { RA, RB } },
2543 { "lwzux", X(31,55), X_MASK, PPCCOM, { RT, RAL, RB } },
2544 { "lux", X(31,55), X_MASK, PWRCOM, { RT, RA, RB } },
2546 { "dcbste", X(31,62), XRT_MASK, BOOKE64, { RA, RB } },
2548 { "lwzuxe", X(31,63), X_MASK, BOOKE64, { RT, RAL, RB } },
2550 { "cntlzd", XRC(31,58,0), XRB_MASK, PPC64, { RA, RS } },
2551 { "cntlzd.", XRC(31,58,1), XRB_MASK, PPC64, { RA, RS } },
2553 { "andc", XRC(31,60,0), X_MASK, COM, { RA, RS, RB } },
2554 { "andc.", XRC(31,60,1), X_MASK, COM, { RA, RS, RB } },
2556 { "tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, { RA, RB } },
2557 { "tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC64, { RA, RB } },
2558 { "tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC64, { RA, RB } },
2559 { "tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC64, { RA, RB } },
2560 { "tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC64, { RA, RB } },
2561 { "tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, { RA, RB } },
2562 { "tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC64, { RA, RB } },
2563 { "tdgt", XTO(31,68,TOGT), XTO_MASK, PPC64, { RA, RB } },
2564 { "tdge", XTO(31,68,TOGE), XTO_MASK, PPC64, { RA, RB } },
2565 { "tdnl", XTO(31,68,TONL), XTO_MASK, PPC64, { RA, RB } },
2566 { "tdlt", XTO(31,68,TOLT), XTO_MASK, PPC64, { RA, RB } },
2567 { "tdle", XTO(31,68,TOLE), XTO_MASK, PPC64, { RA, RB } },
2568 { "tdng", XTO(31,68,TONG), XTO_MASK, PPC64, { RA, RB } },
2569 { "tdne", XTO(31,68,TONE), XTO_MASK, PPC64, { RA, RB } },
2570 { "td", X(31,68), X_MASK, PPC64, { TO, RA, RB } },
2572 { "mulhd", XO(31,73,0,0), XO_MASK, PPC64, { RT, RA, RB } },
2573 { "mulhd.", XO(31,73,0,1), XO_MASK, PPC64, { RT, RA, RB } },
2575 { "mulhw", XO(31,75,0,0), XO_MASK, PPC, { RT, RA, RB } },
2576 { "mulhw.", XO(31,75,0,1), XO_MASK, PPC, { RT, RA, RB } },
2578 { "mtsrd", X(31,82), XRB_MASK|(1<<20), PPC64, { SR, RS } },
2580 { "mfmsr", X(31,83), XRARB_MASK, COM, { RT } },
2582 { "ldarx", X(31,84), X_MASK, PPC64, { RT, RA, RB } },
2584 { "dcbf", X(31,86), XRT_MASK, PPC, { RA, RB } },
2586 { "lbzx", X(31,87), X_MASK, COM, { RT, RA, RB } },
2588 { "dcbfe", X(31,94), XRT_MASK, BOOKE64, { RA, RB } },
2590 { "lbzxe", X(31,95), X_MASK, BOOKE64, { RT, RA, RB } },
2592 { "neg", XO(31,104,0,0), XORB_MASK, COM, { RT, RA } },
2593 { "neg.", XO(31,104,0,1), XORB_MASK, COM, { RT, RA } },
2594 { "nego", XO(31,104,1,0), XORB_MASK, COM, { RT, RA } },
2595 { "nego.", XO(31,104,1,1), XORB_MASK, COM, { RT, RA } },
2597 { "mul", XO(31,107,0,0), XO_MASK, M601, { RT, RA, RB } },
2598 { "mul.", XO(31,107,0,1), XO_MASK, M601, { RT, RA, RB } },
2599 { "mulo", XO(31,107,1,0), XO_MASK, M601, { RT, RA, RB } },
2600 { "mulo.", XO(31,107,1,1), XO_MASK, M601, { RT, RA, RB } },
2602 { "mtsrdin", X(31,114), XRA_MASK, PPC64, { RS, RB } },
2604 { "clf", X(31,118), XTO_MASK, POWER, { RA, RB } },
2606 { "lbzux", X(31,119), X_MASK, COM, { RT, RAL, RB } },
2608 { "not", XRC(31,124,0), X_MASK, COM, { RA, RS, RBS } },
2609 { "nor", XRC(31,124,0), X_MASK, COM, { RA, RS, RB } },
2610 { "not.", XRC(31,124,1), X_MASK, COM, { RA, RS, RBS } },
2611 { "nor.", XRC(31,124,1), X_MASK, COM, { RA, RS, RB } },
2613 { "lwarxe", X(31,126), X_MASK, BOOKE64, { RT, RA, RB } },
2615 { "lbzuxe", X(31,127), X_MASK, BOOKE64, { RT, RAL, RB } },
2617 { "wrtee", X(31,131), XRARB_MASK, PPC403, { RS } },
2618 { "wrtee", X(31,131), XRARB_MASK, BOOKE, { RS } },
2620 { "subfe", XO(31,136,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
2621 { "sfe", XO(31,136,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
2622 { "subfe.", XO(31,136,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
2623 { "sfe.", XO(31,136,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
2624 { "subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
2625 { "sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
2626 { "subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
2627 { "sfeo.", XO(31,136,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
2629 { "adde", XO(31,138,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
2630 { "ae", XO(31,138,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
2631 { "adde.", XO(31,138,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
2632 { "ae.", XO(31,138,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
2633 { "addeo", XO(31,138,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
2634 { "aeo", XO(31,138,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
2635 { "addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
2636 { "aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
2638 { "mtcr", XFXM(31,144,0xff), XFXFXM_MASK|FXM_MASK, COM, { RS }},
2639 { "mtcrf", X(31,144), XFXFXM_MASK, COM, { FXM, RS } },
2641 { "mtmsr", X(31,146), XRARB_MASK, COM, { RS } },
2643 { "stdx", X(31,149), X_MASK, PPC64, { RS, RA, RB } },
2645 { "stwcx.", XRC(31,150,1), X_MASK, PPC, { RS, RA, RB } },
2647 { "stwx", X(31,151), X_MASK, PPCCOM, { RS, RA, RB } },
2648 { "stx", X(31,151), X_MASK, PWRCOM, { RS, RA, RB } },
2650 { "stwcxe.", XRC(31,158,1), X_MASK, BOOKE64, { RS, RA, RB } },
2652 { "stwxe", X(31,159), X_MASK, BOOKE64, { RS, RA, RB } },
2654 { "slq", XRC(31,152,0), X_MASK, M601, { RA, RS, RB } },
2655 { "slq.", XRC(31,152,1), X_MASK, M601, { RA, RS, RB } },
2657 { "sle", XRC(31,153,0), X_MASK, M601, { RA, RS, RB } },
2658 { "sle.", XRC(31,153,1), X_MASK, M601, { RA, RS, RB } },
2660 { "wrteei", X(31,163), XE_MASK, PPC403, { E } },
2661 { "wrteei", X(31,163), XE_MASK, BOOKE, { E } },
2663 { "mtmsrd", X(31,178), XRARB_MASK, PPC64, { RS } },
2665 { "stdux", X(31,181), X_MASK, PPC64, { RS, RAS, RB } },
2667 { "stwux", X(31,183), X_MASK, PPCCOM, { RS, RAS, RB } },
2668 { "stux", X(31,183), X_MASK, PWRCOM, { RS, RA, RB } },
2670 { "sliq", XRC(31,184,0), X_MASK, M601, { RA, RS, SH } },
2671 { "sliq.", XRC(31,184,1), X_MASK, M601, { RA, RS, SH } },
2673 { "stwuxe", X(31,191), X_MASK, BOOKE64, { RS, RAS, RB } },
2675 { "subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, { RT, RA } },
2676 { "sfze", XO(31,200,0,0), XORB_MASK, PWRCOM, { RT, RA } },
2677 { "subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM, { RT, RA } },
2678 { "sfze.", XO(31,200,0,1), XORB_MASK, PWRCOM, { RT, RA } },
2679 { "subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM, { RT, RA } },
2680 { "sfzeo", XO(31,200,1,0), XORB_MASK, PWRCOM, { RT, RA } },
2681 { "subfzeo.",XO(31,200,1,1), XORB_MASK, PPCCOM, { RT, RA } },
2682 { "sfzeo.", XO(31,200,1,1), XORB_MASK, PWRCOM, { RT, RA } },
2684 { "addze", XO(31,202,0,0), XORB_MASK, PPCCOM, { RT, RA } },
2685 { "aze", XO(31,202,0,0), XORB_MASK, PWRCOM, { RT, RA } },
2686 { "addze.", XO(31,202,0,1), XORB_MASK, PPCCOM, { RT, RA } },
2687 { "aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, { RT, RA } },
2688 { "addzeo", XO(31,202,1,0), XORB_MASK, PPCCOM, { RT, RA } },
2689 { "azeo", XO(31,202,1,0), XORB_MASK, PWRCOM, { RT, RA } },
2690 { "addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM, { RT, RA } },
2691 { "azeo.", XO(31,202,1,1), XORB_MASK, PWRCOM, { RT, RA } },
2693 { "mtsr", X(31,210), XRB_MASK|(1<<20), COM32, { SR, RS } },
2695 { "stdcx.", XRC(31,214,1), X_MASK, PPC64, { RS, RA, RB } },
2697 { "stbx", X(31,215), X_MASK, COM, { RS, RA, RB } },
2699 { "sllq", XRC(31,216,0), X_MASK, M601, { RA, RS, RB } },
2700 { "sllq.", XRC(31,216,1), X_MASK, M601, { RA, RS, RB } },
2702 { "sleq", XRC(31,217,0), X_MASK, M601, { RA, RS, RB } },
2703 { "sleq.", XRC(31,217,1), X_MASK, M601, { RA, RS, RB } },
2705 { "stbxe", X(31,223), X_MASK, BOOKE64, { RS, RA, RB } },
2707 { "subfme", XO(31,232,0,0), XORB_MASK, PPCCOM, { RT, RA } },
2708 { "sfme", XO(31,232,0,0), XORB_MASK, PWRCOM, { RT, RA } },
2709 { "subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM, { RT, RA } },
2710 { "sfme.", XO(31,232,0,1), XORB_MASK, PWRCOM, { RT, RA } },
2711 { "subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, { RT, RA } },
2712 { "sfmeo", XO(31,232,1,0), XORB_MASK, PWRCOM, { RT, RA } },
2713 { "subfmeo.",XO(31,232,1,1), XORB_MASK, PPCCOM, { RT, RA } },
2714 { "sfmeo.", XO(31,232,1,1), XORB_MASK, PWRCOM, { RT, RA } },
2716 { "mulld", XO(31,233,0,0), XO_MASK, PPC64, { RT, RA, RB } },
2717 { "mulld.", XO(31,233,0,1), XO_MASK, PPC64, { RT, RA, RB } },
2718 { "mulldo", XO(31,233,1,0), XO_MASK, PPC64, { RT, RA, RB } },
2719 { "mulldo.", XO(31,233,1,1), XO_MASK, PPC64, { RT, RA, RB } },
2721 { "addme", XO(31,234,0,0), XORB_MASK, PPCCOM, { RT, RA } },
2722 { "ame", XO(31,234,0,0), XORB_MASK, PWRCOM, { RT, RA } },
2723 { "addme.", XO(31,234,0,1), XORB_MASK, PPCCOM, { RT, RA } },
2724 { "ame.", XO(31,234,0,1), XORB_MASK, PWRCOM, { RT, RA } },
2725 { "addmeo", XO(31,234,1,0), XORB_MASK, PPCCOM, { RT, RA } },
2726 { "ameo", XO(31,234,1,0), XORB_MASK, PWRCOM, { RT, RA } },
2727 { "addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM, { RT, RA } },
2728 { "ameo.", XO(31,234,1,1), XORB_MASK, PWRCOM, { RT, RA } },
2730 { "mullw", XO(31,235,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
2731 { "muls", XO(31,235,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
2732 { "mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
2733 { "muls.", XO(31,235,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
2734 { "mullwo", XO(31,235,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
2735 { "mulso", XO(31,235,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
2736 { "mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
2737 { "mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
2739 { "mtsrin", X(31,242), XRA_MASK, PPC32, { RS, RB } },
2740 { "mtsri", X(31,242), XRA_MASK, POWER32, { RS, RB } },
2742 { "dcbtst", X(31,246), XRT_MASK, PPC, { CT, RA, RB } },
2744 { "stbux", X(31,247), X_MASK, COM, { RS, RAS, RB } },
2746 { "slliq", XRC(31,248,0), X_MASK, M601, { RA, RS, SH } },
2747 { "slliq.", XRC(31,248,1), X_MASK, M601, { RA, RS, SH } },
2749 { "dcbtste", X(31,253), X_MASK, BOOKE64, { CT, RA, RB } },
2751 { "stbuxe", X(31,255), X_MASK, BOOKE64, { RS, RAS, RB } },
2753 { "mfdcrx", X(31,259), X_MASK, BOOKE, { RS, RA } },
2755 { "icbt", X(31,262), XRT_MASK, PPC403, { RA, RB } },
2757 { "doz", XO(31,264,0,0), XO_MASK, M601, { RT, RA, RB } },
2758 { "doz.", XO(31,264,0,1), XO_MASK, M601, { RT, RA, RB } },
2759 { "dozo", XO(31,264,1,0), XO_MASK, M601, { RT, RA, RB } },
2760 { "dozo.", XO(31,264,1,1), XO_MASK, M601, { RT, RA, RB } },
2762 { "add", XO(31,266,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
2763 { "cax", XO(31,266,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
2764 { "add.", XO(31,266,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
2765 { "cax.", XO(31,266,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
2766 { "addo", XO(31,266,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
2767 { "caxo", XO(31,266,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
2768 { "addo.", XO(31,266,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
2769 { "caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
2771 { "mfapidi", X(31,275), X_MASK, BOOKE, { RT, RA } },
2773 { "lscbx", XRC(31,277,0), X_MASK, M601, { RT, RA, RB } },
2774 { "lscbx.", XRC(31,277,1), X_MASK, M601, { RT, RA, RB } },
2776 { "dcbt", X(31,278), XRT_MASK, PPC, { CT, RA, RB } },
2778 { "lhzx", X(31,279), X_MASK, COM, { RT, RA, RB } },
2780 { "eqv", XRC(31,284,0), X_MASK, COM, { RA, RS, RB } },
2781 { "eqv.", XRC(31,284,1), X_MASK, COM, { RA, RS, RB } },
2783 { "dcbte", X(31,286), X_MASK, BOOKE64, { CT, RA, RB } },
2785 { "lhzxe", X(31,287), X_MASK, BOOKE64, { RT, RA, RB } },
2787 { "tlbie", X(31,306), XRTRA_MASK, PPC, { RB } },
2788 { "tlbi", X(31,306), XRT_MASK, POWER, { RA, RB } },
2790 { "eciwx", X(31,310), X_MASK, PPC, { RT, RA, RB } },
2792 { "lhzux", X(31,311), X_MASK, COM, { RT, RAL, RB } },
2794 { "xor", XRC(31,316,0), X_MASK, COM, { RA, RS, RB } },
2795 { "xor.", XRC(31,316,1), X_MASK, COM, { RA, RS, RB } },
2797 { "lhzuxe", X(31,319), X_MASK, BOOKE64, { RT, RAL, RB } },
2799 { "mfexisr", XSPR(31,323,64), XSPR_MASK, PPC403, { RT } },
2800 { "mfexier", XSPR(31,323,66), XSPR_MASK, PPC403, { RT } },
2801 { "mfbr0", XSPR(31,323,128), XSPR_MASK, PPC403, { RT } },
2802 { "mfbr1", XSPR(31,323,129), XSPR_MASK, PPC403, { RT } },
2803 { "mfbr2", XSPR(31,323,130), XSPR_MASK, PPC403, { RT } },
2804 { "mfbr3", XSPR(31,323,131), XSPR_MASK, PPC403, { RT } },
2805 { "mfbr4", XSPR(31,323,132), XSPR_MASK, PPC403, { RT } },
2806 { "mfbr5", XSPR(31,323,133), XSPR_MASK, PPC403, { RT } },
2807 { "mfbr6", XSPR(31,323,134), XSPR_MASK, PPC403, { RT } },
2808 { "mfbr7", XSPR(31,323,135), XSPR_MASK, PPC403, { RT } },
2809 { "mfbear", XSPR(31,323,144), XSPR_MASK, PPC403, { RT } },
2810 { "mfbesr", XSPR(31,323,145), XSPR_MASK, PPC403, { RT } },
2811 { "mfiocr", XSPR(31,323,160), XSPR_MASK, PPC403, { RT } },
2812 { "mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403, { RT } },
2813 { "mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403, { RT } },
2814 { "mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403, { RT } },
2815 { "mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403, { RT } },
2816 { "mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403, { RT } },
2817 { "mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403, { RT } },
2818 { "mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403, { RT } },
2819 { "mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403, { RT } },
2820 { "mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403, { RT } },
2821 { "mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403, { RT } },
2822 { "mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403, { RT } },
2823 { "mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403, { RT } },
2824 { "mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403, { RT } },
2825 { "mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403, { RT } },
2826 { "mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403, { RT } },
2827 { "mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403, { RT } },
2828 { "mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403, { RT } },
2829 { "mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403, { RT } },
2830 { "mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403, { RT } },
2831 { "mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, { RT } },
2832 { "mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, { RT } },
2833 { "mfdcr", X(31,323), X_MASK, PPC403, { RT, SPR } },
2834 { "mfdcr", X(31,323), X_MASK, BOOKE, { RT, SPR } },
2836 { "div", XO(31,331,0,0), XO_MASK, M601, { RT, RA, RB } },
2837 { "div.", XO(31,331,0,1), XO_MASK, M601, { RT, RA, RB } },
2838 { "divo", XO(31,331,1,0), XO_MASK, M601, { RT, RA, RB } },
2839 { "divo.", XO(31,331,1,1), XO_MASK, M601, { RT, RA, RB } },
2841 { "mfmq", XSPR(31,339,0), XSPR_MASK, M601, { RT } },
2842 { "mfxer", XSPR(31,339,1), XSPR_MASK, COM, { RT } },
2843 { "mfrtcu", XSPR(31,339,4), XSPR_MASK, COM, { RT } },
2844 { "mfrtcl", XSPR(31,339,5), XSPR_MASK, COM, { RT } },
2845 { "mfdec", XSPR(31,339,6), XSPR_MASK, MFDEC1, { RT } },
2846 { "mflr", XSPR(31,339,8), XSPR_MASK, COM, { RT } },
2847 { "mfctr", XSPR(31,339,9), XSPR_MASK, COM, { RT } },
2848 { "mftid", XSPR(31,339,17), XSPR_MASK, POWER, { RT } },
2849 { "mfdsisr", XSPR(31,339,18), XSPR_MASK, COM, { RT } },
2850 { "mfdar", XSPR(31,339,19), XSPR_MASK, COM, { RT } },
2851 { "mfdec", XSPR(31,339,22), XSPR_MASK, MFDEC2, { RT } },
2852 { "mfsdr0", XSPR(31,339,24), XSPR_MASK, POWER, { RT } },
2853 { "mfsdr1", XSPR(31,339,25), XSPR_MASK, COM, { RT } },
2854 { "mfsrr0", XSPR(31,339,26), XSPR_MASK, COM, { RT } },
2855 { "mfsrr1", XSPR(31,339,27), XSPR_MASK, COM, { RT } },
2856 { "mfcmpa", XSPR(31,339,144), XSPR_MASK, PPC860, { RT } },
2857 { "mfcmpb", XSPR(31,339,145), XSPR_MASK, PPC860, { RT } },
2858 { "mfcmpc", XSPR(31,339,146), XSPR_MASK, PPC860, { RT } },
2859 { "mfcmpd", XSPR(31,339,147), XSPR_MASK, PPC860, { RT } },
2860 { "mficr", XSPR(31,339,148), XSPR_MASK, PPC860, { RT } },
2861 { "mfder", XSPR(31,339,149), XSPR_MASK, PPC860, { RT } },
2862 { "mfcounta", XSPR(31,339,150), XSPR_MASK, PPC860, { RT } },
2863 { "mfcountb", XSPR(31,339,151), XSPR_MASK, PPC860, { RT } },
2864 { "mfcmpe", XSPR(31,339,152), XSPR_MASK, PPC860, { RT } },
2865 { "mfcmpf", XSPR(31,339,153), XSPR_MASK, PPC860, { RT } },
2866 { "mfcmpg", XSPR(31,339,154), XSPR_MASK, PPC860, { RT } },
2867 { "mfcmph", XSPR(31,339,155), XSPR_MASK, PPC860, { RT } },
2868 { "mflctrl1", XSPR(31,339,156), XSPR_MASK, PPC860, { RT } },
2869 { "mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860, { RT } },
2870 { "mfictrl", XSPR(31,339,158), XSPR_MASK, PPC860, { RT } },
2871 { "mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, { RT } },
2872 { "mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405, { RT } },
2873 { "mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405, { RT } },
2874 { "mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405, { RT } },
2875 { "mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405, { RT } },
2876 { "mfsprg", XSPR(31,339,272), XSPRG_MASK, PPC, { RT, SPRG } },
2877 { "mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, { RT } },
2878 { "mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC, { RT } },
2879 { "mfsprg2", XSPR(31,339,274), XSPR_MASK, PPC, { RT } },
2880 { "mfsprg3", XSPR(31,339,275), XSPR_MASK, PPC, { RT } },
2881 { "mfasr", XSPR(31,339,280), XSPR_MASK, PPC64, { RT } },
2882 { "mfear", XSPR(31,339,282), XSPR_MASK, PPC, { RT } },
2883 { "mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, { RT } },
2884 { "mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
2885 { "mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
2886 { "mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
2887 { "mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
2888 { "mfic_cst", XSPR(31,339,560), XSPR_MASK, PPC860, { RT } },
2889 { "mfic_adr", XSPR(31,339,561), XSPR_MASK, PPC860, { RT } },
2890 { "mfic_dat", XSPR(31,339,562), XSPR_MASK, PPC860, { RT } },
2891 { "mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860, { RT } },
2892 { "mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860, { RT } },
2893 { "mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860, { RT } },
2894 { "mfdpdr", XSPR(31,339,630), XSPR_MASK, PPC860, { RT } },
2895 { "mfdpir", XSPR(31,339,631), XSPR_MASK, PPC860, { RT } },
2896 { "mfimmr", XSPR(31,339,638), XSPR_MASK, PPC860, { RT } },
2897 { "mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860, { RT } },
2898 { "mfmi_ap", XSPR(31,339,786), XSPR_MASK, PPC860, { RT } },
2899 { "mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860, { RT } },
2900 { "mfmi_twc", XSPR(31,339,789), XSPR_MASK, PPC860, { RT } },
2901 { "mfmi_rpn", XSPR(31,339,790), XSPR_MASK, PPC860, { RT } },
2902 { "mfmd_ctr", XSPR(31,339,792), XSPR_MASK, PPC860, { RT } },
2903 { "mfm_casid",XSPR(31,339,793), XSPR_MASK, PPC860, { RT } },
2904 { "mfmd_ap", XSPR(31,339,794), XSPR_MASK, PPC860, { RT } },
2905 { "mfmd_epn", XSPR(31,339,795), XSPR_MASK, PPC860, { RT } },
2906 { "mfmd_twb", XSPR(31,339,796), XSPR_MASK, PPC860, { RT } },
2907 { "mfmd_twc", XSPR(31,339,797), XSPR_MASK, PPC860, { RT } },
2908 { "mfmd_rpn", XSPR(31,339,798), XSPR_MASK, PPC860, { RT } },
2909 { "mfm_tw", XSPR(31,339,799), XSPR_MASK, PPC860, { RT } },
2910 { "mfmi_dbcam",XSPR(31,339,816), XSPR_MASK, PPC860, { RT } },
2911 { "mfmi_dbram0",XSPR(31,339,817), XSPR_MASK, PPC860, { RT } },
2912 { "mfmi_dbram1",XSPR(31,339,818), XSPR_MASK, PPC860, { RT } },
2913 { "mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860, { RT } },
2914 { "mfmd_dbram0",XSPR(31,339,825), XSPR_MASK, PPC860, { RT } },
2915 { "mfmd_dbram1",XSPR(31,339,826), XSPR_MASK, PPC860, { RT } },
2916 { "mfzpr", XSPR(31,339,944), XSPR_MASK, PPC403, { RT } },
2917 { "mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, { RT } },
2918 { "mfccr0", XSPR(31,339,947), XSPR_MASK, PPC405, { RT } },
2919 { "mficdbdr", XSPR(31,339,979), XSPR_MASK, PPC403, { RT } },
2920 { "mfummcr0", XSPR(31,339,936), XSPR_MASK, PPC750, { RT } },
2921 { "mfupmc1", XSPR(31,339,937), XSPR_MASK, PPC750, { RT } },
2922 { "mfupmc2", XSPR(31,339,938), XSPR_MASK, PPC750, { RT } },
2923 { "mfusia", XSPR(31,339,939), XSPR_MASK, PPC750, { RT } },
2924 { "mfummcr1", XSPR(31,339,940), XSPR_MASK, PPC750, { RT } },
2925 { "mfupmc3", XSPR(31,339,941), XSPR_MASK, PPC750, { RT } },
2926 { "mfupmc4", XSPR(31,339,942), XSPR_MASK, PPC750, { RT } },
2927 { "mfiac3", XSPR(31,339,948), XSPR_MASK, PPC405, { RT } },
2928 { "mfiac4", XSPR(31,339,949), XSPR_MASK, PPC405, { RT } },
2929 { "mfdvc1", XSPR(31,339,950), XSPR_MASK, PPC405, { RT } },
2930 { "mfdvc2", XSPR(31,339,951), XSPR_MASK, PPC405, { RT } },
2931 { "mfmmcr0", XSPR(31,339,952), XSPR_MASK, PPC750, { RT } },
2932 { "mfpmc1", XSPR(31,339,953), XSPR_MASK, PPC750, { RT } },
2933 { "mfsgr", XSPR(31,339,953), XSPR_MASK, PPC403, { RT } },
2934 { "mfpmc2", XSPR(31,339,954), XSPR_MASK, PPC750, { RT } },
2935 { "mfdcwr", XSPR(31,339,954), XSPR_MASK, PPC403, { RT } },
2936 { "mfsia", XSPR(31,339,955), XSPR_MASK, PPC750, { RT } },
2937 { "mfsler", XSPR(31,339,955), XSPR_MASK, PPC405, { RT } },
2938 { "mfmmcr1", XSPR(31,339,956), XSPR_MASK, PPC750, { RT } },
2939 { "mfsu0r", XSPR(31,339,956), XSPR_MASK, PPC405, { RT } },
2940 { "mfpmc3", XSPR(31,339,957), XSPR_MASK, PPC750, { RT } },
2941 { "mfdbcr1", XSPR(31,339,957), XSPR_MASK, PPC405, { RT } },
2942 { "mfpmc4", XSPR(31,339,958), XSPR_MASK, PPC750, { RT } },
2943 { "mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, { RT } },
2944 { "mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, { RT } },
2945 { "mfevpr", XSPR(31,339,982), XSPR_MASK, PPC403, { RT } },
2946 { "mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403, { RT } },
2947 { "mftsr", XSPR(31,339,984), XSPR_MASK, PPC403, { RT } },
2948 { "mftcr", XSPR(31,339,986), XSPR_MASK, PPC403, { RT } },
2949 { "mfpit", XSPR(31,339,987), XSPR_MASK, PPC403, { RT } },
2950 { "mftbhi", XSPR(31,339,988), XSPR_MASK, PPC403, { RT } },
2951 { "mftblo", XSPR(31,339,989), XSPR_MASK, PPC403, { RT } },
2952 { "mfsrr2", XSPR(31,339,990), XSPR_MASK, PPC403, { RT } },
2953 { "mfsrr3", XSPR(31,339,991), XSPR_MASK, PPC403, { RT } },
2954 { "mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, { RT } },
2955 { "mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405, { RT } },
2956 { "mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, { RT } },
2957 { "mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, { RT } },
2958 { "mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, { RT } },
2959 { "mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, { RT } },
2960 { "mfdccr", XSPR(31,339,1018), XSPR_MASK, PPC403, { RT } },
2961 { "mficcr", XSPR(31,339,1019), XSPR_MASK, PPC403, { RT } },
2962 { "mfpbl1", XSPR(31,339,1020), XSPR_MASK, PPC403, { RT } },
2963 { "mfpbu1", XSPR(31,339,1021), XSPR_MASK, PPC403, { RT } },
2964 { "mfpbl2", XSPR(31,339,1022), XSPR_MASK, PPC403, { RT } },
2965 { "mfpbu2", XSPR(31,339,1023), XSPR_MASK, PPC403, { RT } },
2966 { "mfl2cr", XSPR(31,339,1017), XSPR_MASK, PPC750, { RT } },
2967 { "mfictc", XSPR(31,339,1019), XSPR_MASK, PPC750, { RT } },
2968 { "mfthrm1", XSPR(31,339,1020), XSPR_MASK, PPC750, { RT } },
2969 { "mfthrm2", XSPR(31,339,1021), XSPR_MASK, PPC750, { RT } },
2970 { "mfthrm3", XSPR(31,339,1022), XSPR_MASK, PPC750, { RT } },
2971 { "mfspr", X(31,339), X_MASK, COM, { RT, SPR } },
2973 { "lwax", X(31,341), X_MASK, PPC64, { RT, RA, RB } },
2975 { "lhax", X(31,343), X_MASK, COM, { RT, RA, RB } },
2977 { "lhaxe", X(31,351), X_MASK, BOOKE64, { RT, RA, RB } },
2979 { "dccci", X(31,454), XRT_MASK, PPC403, { RA, RB } },
2981 { "abs", XO(31,360,0,0), XORB_MASK, M601, { RT, RA } },
2982 { "abs.", XO(31,360,0,1), XORB_MASK, M601, { RT, RA } },
2983 { "abso", XO(31,360,1,0), XORB_MASK, M601, { RT, RA } },
2984 { "abso.", XO(31,360,1,1), XORB_MASK, M601, { RT, RA } },
2986 { "divs", XO(31,363,0,0), XO_MASK, M601, { RT, RA, RB } },
2987 { "divs.", XO(31,363,0,1), XO_MASK, M601, { RT, RA, RB } },
2988 { "divso", XO(31,363,1,0), XO_MASK, M601, { RT, RA, RB } },
2989 { "divso.", XO(31,363,1,1), XO_MASK, M601, { RT, RA, RB } },
2991 { "tlbia", X(31,370), 0xffffffff, PPC, { 0 } },
2993 { "mftbl", XSPR(31,371,268), XSPR_MASK, PPC, { RT } },
2994 { "mftbu", XSPR(31,371,269), XSPR_MASK, PPC, { RT } },
2995 { "mftb", X(31,371), X_MASK, PPC, { RT, TBR } },
2997 { "lwaux", X(31,373), X_MASK, PPC64, { RT, RAL, RB } },
2999 { "lhaux", X(31,375), X_MASK, COM, { RT, RAL, RB } },
3001 { "lhauxe", X(31,383), X_MASK, BOOKE64, { RT, RAL, RB } },
3003 { "mtdcrx", X(31,387), X_MASK, BOOKE, { RA, RS } },
3005 { "subfe64", XO(31,392,0,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3006 { "subfe64o",XO(31,392,1,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3008 { "adde64", XO(31,394,0,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3009 { "adde64o", XO(31,394,1,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3011 { "slbmte", X(31,402), XRA_MASK, PPC64, { RS, RB } },
3013 { "sthx", X(31,407), X_MASK, COM, { RS, RA, RB } },
3015 { "lfqx", X(31,791), X_MASK, POWER2, { FRT, RA, RB } },
3017 { "lfqux", X(31,823), X_MASK, POWER2, { FRT, RA, RB } },
3019 { "stfqx", X(31,919), X_MASK, POWER2, { FRS, RA, RB } },
3021 { "stfqux", X(31,951), X_MASK, POWER2, { FRS, RA, RB } },
3023 { "orc", XRC(31,412,0), X_MASK, COM, { RA, RS, RB } },
3024 { "orc.", XRC(31,412,1), X_MASK, COM, { RA, RS, RB } },
3026 { "sradi", XS(31,413,0), XS_MASK, PPC64, { RA, RS, SH6 } },
3027 { "sradi.", XS(31,413,1), XS_MASK, PPC64, { RA, RS, SH6 } },
3029 { "sthxe", X(31,415), X_MASK, BOOKE64, { RS, RA, RB } },
3031 { "slbie", X(31,434), XRTRA_MASK, PPC64, { RB } },
3033 { "ecowx", X(31,438), X_MASK, PPC, { RT, RA, RB } },
3035 { "sthux", X(31,439), X_MASK, COM, { RS, RAS, RB } },
3037 { "sthuxe", X(31,447), X_MASK, BOOKE64, { RS, RAS, RB } },
3039 { "mr", XRC(31,444,0), X_MASK, COM, { RA, RS, RBS } },
3040 { "or", XRC(31,444,0), X_MASK, COM, { RA, RS, RB } },
3041 { "mr.", XRC(31,444,1), X_MASK, COM, { RA, RS, RBS } },
3042 { "or.", XRC(31,444,1), X_MASK, COM, { RA, RS, RB } },
3044 { "mtexisr", XSPR(31,451,64), XSPR_MASK, PPC403, { RT } },
3045 { "mtexier", XSPR(31,451,66), XSPR_MASK, PPC403, { RT } },
3046 { "mtbr0", XSPR(31,451,128), XSPR_MASK, PPC403, { RT } },
3047 { "mtbr1", XSPR(31,451,129), XSPR_MASK, PPC403, { RT } },
3048 { "mtbr2", XSPR(31,451,130), XSPR_MASK, PPC403, { RT } },
3049 { "mtbr3", XSPR(31,451,131), XSPR_MASK, PPC403, { RT } },
3050 { "mtbr4", XSPR(31,451,132), XSPR_MASK, PPC403, { RT } },
3051 { "mtbr5", XSPR(31,451,133), XSPR_MASK, PPC403, { RT } },
3052 { "mtbr6", XSPR(31,451,134), XSPR_MASK, PPC403, { RT } },
3053 { "mtbr7", XSPR(31,451,135), XSPR_MASK, PPC403, { RT } },
3054 { "mtbear", XSPR(31,451,144), XSPR_MASK, PPC403, { RT } },
3055 { "mtbesr", XSPR(31,451,145), XSPR_MASK, PPC403, { RT } },
3056 { "mtiocr", XSPR(31,451,160), XSPR_MASK, PPC403, { RT } },
3057 { "mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403, { RT } },
3058 { "mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403, { RT } },
3059 { "mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403, { RT } },
3060 { "mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403, { RT } },
3061 { "mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403, { RT } },
3062 { "mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403, { RT } },
3063 { "mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403, { RT } },
3064 { "mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403, { RT } },
3065 { "mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403, { RT } },
3066 { "mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403, { RT } },
3067 { "mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403, { RT } },
3068 { "mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403, { RT } },
3069 { "mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403, { RT } },
3070 { "mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403, { RT } },
3071 { "mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403, { RT } },
3072 { "mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403, { RT } },
3073 { "mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403, { RT } },
3074 { "mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403, { RT } },
3075 { "mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, { RT } },
3076 { "mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, { RT } },
3077 { "mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, { RT } },
3078 { "mtdcr", X(31,451), X_MASK, PPC403, { SPR, RS } },
3079 { "mtdcr", X(31,451), X_MASK, BOOKE, { SPR, RS } },
3081 { "subfze64",XO(31,456,0,0), XORB_MASK, BOOKE64, { RT, RA } },
3082 { "subfze64o",XO(31,456,1,0), XORB_MASK, BOOKE64, { RT, RA } },
3084 { "divdu", XO(31,457,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3085 { "divdu.", XO(31,457,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3086 { "divduo", XO(31,457,1,0), XO_MASK, PPC64, { RT, RA, RB } },
3087 { "divduo.", XO(31,457,1,1), XO_MASK, PPC64, { RT, RA, RB } },
3089 { "addze64", XO(31,458,0,0), XORB_MASK, BOOKE64, { RT, RA } },
3090 { "addze64o",XO(31,458,1,0), XORB_MASK, BOOKE64, { RT, RA } },
3092 { "divwu", XO(31,459,0,0), XO_MASK, PPC, { RT, RA, RB } },
3093 { "divwu.", XO(31,459,0,1), XO_MASK, PPC, { RT, RA, RB } },
3094 { "divwuo", XO(31,459,1,0), XO_MASK, PPC, { RT, RA, RB } },
3095 { "divwuo.", XO(31,459,1,1), XO_MASK, PPC, { RT, RA, RB } },
3097 { "mtmq", XSPR(31,467,0), XSPR_MASK, M601, { RS } },
3098 { "mtxer", XSPR(31,467,1), XSPR_MASK, COM, { RS } },
3099 { "mtlr", XSPR(31,467,8), XSPR_MASK, COM, { RS } },
3100 { "mtctr", XSPR(31,467,9), XSPR_MASK, COM, { RS } },
3101 { "mttid", XSPR(31,467,17), XSPR_MASK, POWER, { RS } },
3102 { "mtdsisr", XSPR(31,467,18), XSPR_MASK, COM, { RS } },
3103 { "mtdar", XSPR(31,467,19), XSPR_MASK, COM, { RS } },
3104 { "mtrtcu", XSPR(31,467,20), XSPR_MASK, COM, { RS } },
3105 { "mtrtcl", XSPR(31,467,21), XSPR_MASK, COM, { RS } },
3106 { "mtdec", XSPR(31,467,22), XSPR_MASK, COM, { RS } },
3107 { "mtsdr0", XSPR(31,467,24), XSPR_MASK, POWER, { RS } },
3108 { "mtsdr1", XSPR(31,467,25), XSPR_MASK, COM, { RS } },
3109 { "mtsrr0", XSPR(31,467,26), XSPR_MASK, COM, { RS } },
3110 { "mtsrr1", XSPR(31,467,27), XSPR_MASK, COM, { RS } },
3111 { "mtcmpa", XSPR(31,467,144), XSPR_MASK, PPC860, { RT } },
3112 { "mtcmpb", XSPR(31,467,145), XSPR_MASK, PPC860, { RT } },
3113 { "mtcmpc", XSPR(31,467,146), XSPR_MASK, PPC860, { RT } },
3114 { "mtcmpd", XSPR(31,467,147), XSPR_MASK, PPC860, { RT } },
3115 { "mticr", XSPR(31,467,148), XSPR_MASK, PPC860, { RT } },
3116 { "mtder", XSPR(31,467,149), XSPR_MASK, PPC860, { RT } },
3117 { "mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860, { RT } },
3118 { "mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860, { RT } },
3119 { "mtcmpe", XSPR(31,467,152), XSPR_MASK, PPC860, { RT } },
3120 { "mtcmpf", XSPR(31,467,153), XSPR_MASK, PPC860, { RT } },
3121 { "mtcmpg", XSPR(31,467,154), XSPR_MASK, PPC860, { RT } },
3122 { "mtcmph", XSPR(31,467,155), XSPR_MASK, PPC860, { RT } },
3123 { "mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860, { RT } },
3124 { "mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860, { RT } },
3125 { "mtictrl", XSPR(31,467,158), XSPR_MASK, PPC860, { RT } },
3126 { "mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, { RT } },
3127 { "mtsprg", XSPR(31,467,272), XSPRG_MASK, PPC, { SPRG, RS } },
3128 { "mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC, { RT } },
3129 { "mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, { RT } },
3130 { "mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC, { RT } },
3131 { "mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC, { RT } },
3132 { "mtsprg4", XSPR(31,467,276), XSPR_MASK, PPC405, { RT } },
3133 { "mtsprg5", XSPR(31,467,277), XSPR_MASK, PPC405, { RT } },
3134 { "mtsprg6", XSPR(31,467,278), XSPR_MASK, PPC405, { RT } },
3135 { "mtsprg7", XSPR(31,467,279), XSPR_MASK, PPC405, { RT } },
3136 { "mtasr", XSPR(31,467,280), XSPR_MASK, PPC64, { RS } },
3137 { "mtear", XSPR(31,467,282), XSPR_MASK, PPC, { RS } },
3138 { "mttbl", XSPR(31,467,284), XSPR_MASK, PPC, { RS } },
3139 { "mttbu", XSPR(31,467,285), XSPR_MASK, PPC, { RS } },
3140 { "mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
3141 { "mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
3142 { "mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
3143 { "mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
3144 { "mtzpr", XSPR(31,467,944), XSPR_MASK, PPC403, { RT } },
3145 { "mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, { RT } },
3146 { "mtccr0", XSPR(31,467,947), XSPR_MASK, PPC405, { RT } },
3147 { "mtiac3", XSPR(31,467,948), XSPR_MASK, PPC405, { RT } },
3148 { "mtiac4", XSPR(31,467,949), XSPR_MASK, PPC405, { RT } },
3149 { "mtdvc1", XSPR(31,467,950), XSPR_MASK, PPC405, { RT } },
3150 { "mtdvc2", XSPR(31,467,951), XSPR_MASK, PPC405, { RT } },
3151 { "mtsgr", XSPR(31,467,953), XSPR_MASK, PPC403, { RT } },
3152 { "mtdcwr", XSPR(31,467,954), XSPR_MASK, PPC403, { RT } },
3153 { "mtsler", XSPR(31,467,955), XSPR_MASK, PPC405, { RT } },
3154 { "mtsu0r", XSPR(31,467,956), XSPR_MASK, PPC405, { RT } },
3155 { "mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405, { RT } },
3156 { "mticdbdr",XSPR(31,467,979), XSPR_MASK, PPC403, { RT } },
3157 { "mtesr", XSPR(31,467,980), XSPR_MASK, PPC403, { RT } },
3158 { "mtdear", XSPR(31,467,981), XSPR_MASK, PPC403, { RT } },
3159 { "mtevpr", XSPR(31,467,982), XSPR_MASK, PPC403, { RT } },
3160 { "mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403, { RT } },
3161 { "mttsr", XSPR(31,467,984), XSPR_MASK, PPC403, { RT } },
3162 { "mttcr", XSPR(31,467,986), XSPR_MASK, PPC403, { RT } },
3163 { "mtpit", XSPR(31,467,987), XSPR_MASK, PPC403, { RT } },
3164 { "mttbhi", XSPR(31,467,988), XSPR_MASK, PPC403, { RT } },
3165 { "mttblo", XSPR(31,467,989), XSPR_MASK, PPC403, { RT } },
3166 { "mtsrr2", XSPR(31,467,990), XSPR_MASK, PPC403, { RT } },
3167 { "mtsrr3", XSPR(31,467,991), XSPR_MASK, PPC403, { RT } },
3168 { "mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, { RT } },
3169 { "mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405, { RT } },
3170 { "mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, { RT } },
3171 { "mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, { RT } },
3172 { "mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, { RT } },
3173 { "mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, { RT } },
3174 { "mtdccr", XSPR(31,467,1018), XSPR_MASK, PPC403, { RT } },
3175 { "mticcr", XSPR(31,467,1019), XSPR_MASK, PPC403, { RT } },
3176 { "mtpbl1", XSPR(31,467,1020), XSPR_MASK, PPC403, { RT } },
3177 { "mtpbu1", XSPR(31,467,1021), XSPR_MASK, PPC403, { RT } },
3178 { "mtpbl2", XSPR(31,467,1022), XSPR_MASK, PPC403, { RT } },
3179 { "mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, { RT } },
3180 { "mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, { RT } },
3181 { "mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, { RT } },
3182 { "mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, { RT } },
3183 { "mtusia", XSPR(31,467,939), XSPR_MASK, PPC750, { RT } },
3184 { "mtummcr1", XSPR(31,467,940), XSPR_MASK, PPC750, { RT } },
3185 { "mtupmc3", XSPR(31,467,941), XSPR_MASK, PPC750, { RT } },
3186 { "mtupmc4", XSPR(31,467,942), XSPR_MASK, PPC750, { RT } },
3187 { "mtmmcr0", XSPR(31,467,952), XSPR_MASK, PPC750, { RT } },
3188 { "mtpmc1", XSPR(31,467,953), XSPR_MASK, PPC750, { RT } },
3189 { "mtpmc2", XSPR(31,467,954), XSPR_MASK, PPC750, { RT } },
3190 { "mtsia", XSPR(31,467,955), XSPR_MASK, PPC750, { RT } },
3191 { "mtmmcr1", XSPR(31,467,956), XSPR_MASK, PPC750, { RT } },
3192 { "mtpmc3", XSPR(31,467,957), XSPR_MASK, PPC750, { RT } },
3193 { "mtpmc4", XSPR(31,467,958), XSPR_MASK, PPC750, { RT } },
3194 { "mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, { RT } },
3195 { "mtictc", XSPR(31,467,1019), XSPR_MASK, PPC750, { RT } },
3196 { "mtthrm1", XSPR(31,467,1020), XSPR_MASK, PPC750, { RT } },
3197 { "mtthrm2", XSPR(31,467,1021), XSPR_MASK, PPC750, { RT } },
3198 { "mtthrm3", XSPR(31,467,1022), XSPR_MASK, PPC750, { RT } },
3199 { "mtspr", X(31,467), X_MASK, COM, { SPR, RS } },
3201 { "dcbi", X(31,470), XRT_MASK, PPC, { RA, RB } },
3203 { "nand", XRC(31,476,0), X_MASK, COM, { RA, RS, RB } },
3204 { "nand.", XRC(31,476,1), X_MASK, COM, { RA, RS, RB } },
3206 { "dcbie", X(31,478), XRT_MASK, BOOKE64, { RA, RB } },
3208 { "dcread", X(31,486), X_MASK, PPC403, { RT, RA, RB }},
3210 { "nabs", XO(31,488,0,0), XORB_MASK, M601, { RT, RA } },
3211 { "subfme64",XO(31,488,0,0), XORB_MASK, BOOKE64, { RT, RA } },
3212 { "nabs.", XO(31,488,0,1), XORB_MASK, M601, { RT, RA } },
3213 { "nabso", XO(31,488,1,0), XORB_MASK, M601, { RT, RA } },
3214 { "subfme64o",XO(31,488,1,0), XORB_MASK, BOOKE64, { RT, RA } },
3215 { "nabso.", XO(31,488,1,1), XORB_MASK, M601, { RT, RA } },
3217 { "divd", XO(31,489,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3218 { "divd.", XO(31,489,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3219 { "divdo", XO(31,489,1,0), XO_MASK, PPC64, { RT, RA, RB } },
3220 { "divdo.", XO(31,489,1,1), XO_MASK, PPC64, { RT, RA, RB } },
3222 { "addme64", XO(31,490,0,0), XORB_MASK, BOOKE64, { RT, RA } },
3223 { "addme64o",XO(31,490,1,0), XORB_MASK, BOOKE64, { RT, RA } },
3225 { "divw", XO(31,491,0,0), XO_MASK, PPC, { RT, RA, RB } },
3226 { "divw.", XO(31,491,0,1), XO_MASK, PPC, { RT, RA, RB } },
3227 { "divwo", XO(31,491,1,0), XO_MASK, PPC, { RT, RA, RB } },
3228 { "divwo.", XO(31,491,1,1), XO_MASK, PPC, { RT, RA, RB } },
3230 { "slbia", X(31,498), 0xffffffff, PPC64, { 0 } },
3232 { "cli", X(31,502), XRB_MASK, POWER, { RT, RA } },
3234 { "stdcxe.", XRC(31,511,1), X_MASK, BOOKE64, { RS, RA, RB } },
3236 { "mcrxr", X(31,512), XRARB_MASK|(3<<21), COM, { BF } },
3238 { "mcrxr64", X(31,544), XRARB_MASK|(3<<21), BOOKE, { BF } },
3240 { "clcs", X(31,531), XRB_MASK, M601, { RT, RA } },
3242 { "lswx", X(31,533), X_MASK, PPCCOM, { RT, RA, RB } },
3243 { "lsx", X(31,533), X_MASK, PWRCOM, { RT, RA, RB } },
3245 { "lwbrx", X(31,534), X_MASK, PPCCOM, { RT, RA, RB } },
3246 { "lbrx", X(31,534), X_MASK, PWRCOM, { RT, RA, RB } },
3248 { "lfsx", X(31,535), X_MASK, COM, { FRT, RA, RB } },
3250 { "srw", XRC(31,536,0), X_MASK, PPCCOM, { RA, RS, RB } },
3251 { "sr", XRC(31,536,0), X_MASK, PWRCOM, { RA, RS, RB } },
3252 { "srw.", XRC(31,536,1), X_MASK, PPCCOM, { RA, RS, RB } },
3253 { "sr.", XRC(31,536,1), X_MASK, PWRCOM, { RA, RS, RB } },
3255 { "rrib", XRC(31,537,0), X_MASK, M601, { RA, RS, RB } },
3256 { "rrib.", XRC(31,537,1), X_MASK, M601, { RA, RS, RB } },
3258 { "srd", XRC(31,539,0), X_MASK, PPC64, { RA, RS, RB } },
3259 { "srd.", XRC(31,539,1), X_MASK, PPC64, { RA, RS, RB } },
3261 { "maskir", XRC(31,541,0), X_MASK, M601, { RA, RS, RB } },
3262 { "maskir.", XRC(31,541,1), X_MASK, M601, { RA, RS, RB } },
3264 { "lwbrxe", X(31,542), X_MASK, BOOKE64, { RT, RA, RB } },
3266 { "lfsxe", X(31,543), X_MASK, BOOKE64, { FRT, RA, RB } },
3268 { "tlbsync", X(31,566), 0xffffffff, PPC, { 0 } },
3270 { "lfsux", X(31,567), X_MASK, COM, { FRT, RAS, RB } },
3272 { "lfsuxe", X(31,575), X_MASK, BOOKE64, { FRT, RAS, RB } },
3274 { "mfsr", X(31,595), XRB_MASK|(1<<20), COM32, { RT, SR } },
3276 { "lswi", X(31,597), X_MASK, PPCCOM, { RT, RA, NB } },
3277 { "lsi", X(31,597), X_MASK, PWRCOM, { RT, RA, NB } },
3279 { "lwsync", XSYNC(31,598,1), 0xffffffff, PPCONLY, { 0 } },
3280 { "ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, { 0 } },
3281 { "sync", X(31,598), XSYNC_MASK, PPCCOM, { LS } },
3282 { "dcs", X(31,598), 0xffffffff, PWRCOM, { 0 } },
3283 { "msync", X(31,598), 0xf80007fe, BOOKE, { 0 } },
3285 { "lfdx", X(31,599), X_MASK, COM, { FRT, RA, RB } },
3287 { "lfdxe", X(31,607), X_MASK, BOOKE64, { FRT, RA, RB } },
3289 { "mfsri", X(31,627), X_MASK, PWRCOM, { RT, RA, RB } },
3291 { "dclst", X(31,630), XRB_MASK, PWRCOM, { RS, RA } },
3293 { "lfdux", X(31,631), X_MASK, COM, { FRT, RAS, RB } },
3295 { "lfduxe", X(31,639), X_MASK, BOOKE64, { FRT, RAS, RB } },
3297 { "mfsrin", X(31,659), XRA_MASK, PPC32, { RT, RB } },
3299 { "stswx", X(31,661), X_MASK, PPCCOM, { RS, RA, RB } },
3300 { "stsx", X(31,661), X_MASK, PWRCOM, { RS, RA, RB } },
3302 { "stwbrx", X(31,662), X_MASK, PPCCOM, { RS, RA, RB } },
3303 { "stbrx", X(31,662), X_MASK, PWRCOM, { RS, RA, RB } },
3305 { "stfsx", X(31,663), X_MASK, COM, { FRS, RA, RB } },
3307 { "srq", XRC(31,664,0), X_MASK, M601, { RA, RS, RB } },
3308 { "srq.", XRC(31,664,1), X_MASK, M601, { RA, RS, RB } },
3310 { "sre", XRC(31,665,0), X_MASK, M601, { RA, RS, RB } },
3311 { "sre.", XRC(31,665,1), X_MASK, M601, { RA, RS, RB } },
3313 { "stwbrxe", X(31,670), X_MASK, BOOKE64, { RS, RA, RB } },
3315 { "stfsxe", X(31,671), X_MASK, BOOKE64, { FRS, RA, RB } },
3317 { "stfsux", X(31,695), X_MASK, COM, { FRS, RAS, RB } },
3319 { "sriq", XRC(31,696,0), X_MASK, M601, { RA, RS, SH } },
3320 { "sriq.", XRC(31,696,1), X_MASK, M601, { RA, RS, SH } },
3322 { "stfsuxe", X(31,703), X_MASK, BOOKE64, { FRS, RAS, RB } },
3324 { "stswi", X(31,725), X_MASK, PPCCOM, { RS, RA, NB } },
3325 { "stsi", X(31,725), X_MASK, PWRCOM, { RS, RA, NB } },
3327 { "stfdx", X(31,727), X_MASK, COM, { FRS, RA, RB } },
3329 { "srlq", XRC(31,728,0), X_MASK, M601, { RA, RS, RB } },
3330 { "srlq.", XRC(31,728,1), X_MASK, M601, { RA, RS, RB } },
3332 { "sreq", XRC(31,729,0), X_MASK, M601, { RA, RS, RB } },
3333 { "sreq.", XRC(31,729,1), X_MASK, M601, { RA, RS, RB } },
3335 { "stfdxe", X(31,735), X_MASK, BOOKE64, { FRS, RA, RB } },
3337 { "dcba", X(31,758), XRT_MASK, PPC405, { RA, RB } },
3338 { "dcba", X(31,758), XRT_MASK, BOOKE, { RA, RB } },
3340 { "stfdux", X(31,759), X_MASK, COM, { FRS, RAS, RB } },
3342 { "srliq", XRC(31,760,0), X_MASK, M601, { RA, RS, SH } },
3343 { "srliq.", XRC(31,760,1), X_MASK, M601, { RA, RS, SH } },
3345 { "dcbae", X(31,766), XRT_MASK, BOOKE64, { RA, RB } },
3347 { "stfduxe", X(31,767), X_MASK, BOOKE64, { FRS, RAS, RB } },
3349 { "tlbivax", X(31,786), XRT_MASK, BOOKE, { RA, RB } },
3350 { "tlbivaxe",X(31,787), XRT_MASK, BOOKE, { RA, RB } },
3352 { "lhbrx", X(31,790), X_MASK, COM, { RT, RA, RB } },
3354 { "sraw", XRC(31,792,0), X_MASK, PPCCOM, { RA, RS, RB } },
3355 { "sra", XRC(31,792,0), X_MASK, PWRCOM, { RA, RS, RB } },
3356 { "sraw.", XRC(31,792,1), X_MASK, PPCCOM, { RA, RS, RB } },
3357 { "sra.", XRC(31,792,1), X_MASK, PWRCOM, { RA, RS, RB } },
3359 { "srad", XRC(31,794,0), X_MASK, PPC64, { RA, RS, RB } },
3360 { "srad.", XRC(31,794,1), X_MASK, PPC64, { RA, RS, RB } },
3362 { "lhbrxe", X(31,798), X_MASK, BOOKE64, { RT, RA, RB } },
3364 { "ldxe", X(31,799), X_MASK, BOOKE64, { RT, RA, RB } },
3365 { "lduxe", X(31,831), X_MASK, BOOKE64, { RT, RA, RB } },
3367 { "rac", X(31,818), X_MASK, PWRCOM, { RT, RA, RB } },
3369 { "srawi", XRC(31,824,0), X_MASK, PPCCOM, { RA, RS, SH } },
3370 { "srai", XRC(31,824,0), X_MASK, PWRCOM, { RA, RS, SH } },
3371 { "srawi.", XRC(31,824,1), X_MASK, PPCCOM, { RA, RS, SH } },
3372 { "srai.", XRC(31,824,1), X_MASK, PWRCOM, { RA, RS, SH } },
3374 { "slbmfev", X(31,851), XRA_MASK, PPC64, { RT, RB } },
3376 { "eieio", X(31,854), 0xffffffff, PPC, { 0 } },
3377 { "mbar", X(31,854), 0xffffffff, BOOKE, { MO } },
3379 { "tlbsx", XRC(31,914,0), X_MASK, PPC403, { RT, RA, RB } },
3380 { "tlbsx.", XRC(31,914,1), X_MASK, PPC403, { RT, RA, RB } },
3382 { "tlbsx", XRC(31,914,0), X_MASK, BOOKE, { RA, RB } },
3383 { "tlbsxe", XRC(31,915,0), X_MASK, BOOKE, { RA, RB } },
3385 { "slbmfee", X(31,915), XRA_MASK, PPC64, { RT, RB } },
3387 { "sthbrx", X(31,918), X_MASK, COM, { RS, RA, RB } },
3389 { "sraq", XRC(31,920,0), X_MASK, M601, { RA, RS, RB } },
3390 { "sraq.", XRC(31,920,1), X_MASK, M601, { RA, RS, RB } },
3392 { "srea", XRC(31,921,0), X_MASK, M601, { RA, RS, RB } },
3393 { "srea.", XRC(31,921,1), X_MASK, M601, { RA, RS, RB } },
3395 { "extsh", XRC(31,922,0), XRB_MASK, PPCCOM, { RA, RS } },
3396 { "exts", XRC(31,922,0), XRB_MASK, PWRCOM, { RA, RS } },
3397 { "extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, { RA, RS } },
3398 { "exts.", XRC(31,922,1), XRB_MASK, PWRCOM, { RA, RS } },
3400 { "sthbrxe", X(31,926), X_MASK, BOOKE64, { RS, RA, RB } },
3402 { "stdxe", X(31,927), X_MASK, BOOKE64, { RS, RA, RB } },
3404 { "tlbre", X(31,946), X_MASK, BOOKE, { RT, RA, SH } },
3406 { "tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, { RT, RA } },
3407 { "tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, { RT, RA } },
3409 { "sraiq", XRC(31,952,0), X_MASK, M601, { RA, RS, SH } },
3410 { "sraiq.", XRC(31,952,1), X_MASK, M601, { RA, RS, SH } },
3412 { "extsb", XRC(31,954,0), XRB_MASK, PPC, { RA, RS} },
3413 { "extsb.", XRC(31,954,1), XRB_MASK, PPC, { RA, RS} },
3415 { "stduxe", X(31,959), X_MASK, BOOKE64, { RS, RAS, RB } },
3417 { "iccci", X(31,966), XRT_MASK, PPC403, { RA, RB } },
3419 { "tlbld", X(31,978), XRTRA_MASK, PPC, { RB } },
3421 { "tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, { RT, RA } },
3422 { "tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, { RT, RA } },
3423 { "tlbwe", X(31,978), X_MASK, PPC403, { RS, RA, SH } },
3425 { "tlbwe", X(31,978), X_MASK, BOOKE, { RT, RA, SH } },
3427 { "icbi", X(31,982), XRT_MASK, PPC, { RA, RB } },
3429 { "stfiwx", X(31,983), X_MASK, PPC, { FRS, RA, RB } },
3431 { "extsw", XRC(31,986,0), XRB_MASK, PPC, { RA, RS } },
3432 { "extsw.", XRC(31,986,1), XRB_MASK, PPC, { RA, RS } },
3434 { "icread", X(31,998), XRT_MASK, PPC403, { RA, RB } },
3436 { "icbie", X(31,990), XRT_MASK, BOOKE64, { RA, RB } },
3437 { "stfiwxe", X(31,991), X_MASK, BOOKE64, { FRS, RA, RB } },
3439 { "tlbli", X(31,1010), XRTRA_MASK, PPC, { RB } },
3441 { "dcbz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
3442 { "dclz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
3444 { "dcbze", X(31,1022), XRT_MASK, BOOKE64, { RA, RB } },
3446 { "lvebx", X(31, 7), X_MASK, PPCVEC, { VD, RA, RB } },
3447 { "lvehx", X(31, 39), X_MASK, PPCVEC, { VD, RA, RB } },
3448 { "lvewx", X(31, 71), X_MASK, PPCVEC, { VD, RA, RB } },
3449 { "lvsl", X(31, 6), X_MASK, PPCVEC, { VD, RA, RB } },
3450 { "lvsr", X(31, 38), X_MASK, PPCVEC, { VD, RA, RB } },
3451 { "lvx", X(31, 103), X_MASK, PPCVEC, { VD, RA, RB } },
3452 { "lvxl", X(31, 359), X_MASK, PPCVEC, { VD, RA, RB } },
3453 { "stvebx", X(31, 135), X_MASK, PPCVEC, { VS, RA, RB } },
3454 { "stvehx", X(31, 167), X_MASK, PPCVEC, { VS, RA, RB } },
3455 { "stvewx", X(31, 199), X_MASK, PPCVEC, { VS, RA, RB } },
3456 { "stvx", X(31, 231), X_MASK, PPCVEC, { VS, RA, RB } },
3457 { "stvxl", X(31, 487), X_MASK, PPCVEC, { VS, RA, RB } },
3459 { "lwz", OP(32), OP_MASK, PPCCOM, { RT, D, RA } },
3460 { "l", OP(32), OP_MASK, PWRCOM, { RT, D, RA } },
3462 { "lwzu", OP(33), OP_MASK, PPCCOM, { RT, D, RAL } },
3463 { "lu", OP(33), OP_MASK, PWRCOM, { RT, D, RA } },
3465 { "lbz", OP(34), OP_MASK, COM, { RT, D, RA } },
3467 { "lbzu", OP(35), OP_MASK, COM, { RT, D, RAL } },
3469 { "stw", OP(36), OP_MASK, PPCCOM, { RS, D, RA } },
3470 { "st", OP(36), OP_MASK, PWRCOM, { RS, D, RA } },
3472 { "stwu", OP(37), OP_MASK, PPCCOM, { RS, D, RAS } },
3473 { "stu", OP(37), OP_MASK, PWRCOM, { RS, D, RA } },
3475 { "stb", OP(38), OP_MASK, COM, { RS, D, RA } },
3477 { "stbu", OP(39), OP_MASK, COM, { RS, D, RAS } },
3479 { "lhz", OP(40), OP_MASK, COM, { RT, D, RA } },
3481 { "lhzu", OP(41), OP_MASK, COM, { RT, D, RAL } },
3483 { "lha", OP(42), OP_MASK, COM, { RT, D, RA } },
3485 { "lhau", OP(43), OP_MASK, COM, { RT, D, RAL } },
3487 { "sth", OP(44), OP_MASK, COM, { RS, D, RA } },
3489 { "sthu", OP(45), OP_MASK, COM, { RS, D, RAS } },
3491 { "lmw", OP(46), OP_MASK, PPCCOM, { RT, D, RAM } },
3492 { "lm", OP(46), OP_MASK, PWRCOM, { RT, D, RA } },
3494 { "stmw", OP(47), OP_MASK, PPCCOM, { RS, D, RA } },
3495 { "stm", OP(47), OP_MASK, PWRCOM, { RS, D, RA } },
3497 { "lfs", OP(48), OP_MASK, COM, { FRT, D, RA } },
3499 { "lfsu", OP(49), OP_MASK, COM, { FRT, D, RAS } },
3501 { "lfd", OP(50), OP_MASK, COM, { FRT, D, RA } },
3503 { "lfdu", OP(51), OP_MASK, COM, { FRT, D, RAS } },
3505 { "stfs", OP(52), OP_MASK, COM, { FRS, D, RA } },
3507 { "stfsu", OP(53), OP_MASK, COM, { FRS, D, RAS } },
3509 { "stfd", OP(54), OP_MASK, COM, { FRS, D, RA } },
3511 { "stfdu", OP(55), OP_MASK, COM, { FRS, D, RAS } },
3513 { "lfq", OP(56), OP_MASK, POWER2, { FRT, D, RA } },
3515 { "lfqu", OP(57), OP_MASK, POWER2, { FRT, D, RA } },
3517 { "ld", DSO(58,0), DS_MASK, PPC64, { RT, DS, RA } },
3519 { "ldu", DSO(58,1), DS_MASK, PPC64, { RT, DS, RAL } },
3521 { "lwa", DSO(58,2), DS_MASK, PPC64, { RT, DS, RA } },
3523 { "lbze", DEO(58,0), DE_MASK, BOOKE64, { RT, DE, RA } },
3524 { "lbzue", DEO(58,1), DE_MASK, BOOKE64, { RT, DE, RAL } },
3525 { "lhze", DEO(58,2), DE_MASK, BOOKE64, { RT, DE, RA } },
3526 { "lhzue", DEO(58,3), DE_MASK, BOOKE64, { RT, DE, RAL } },
3527 { "lhae", DEO(58,4), DE_MASK, BOOKE64, { RT, DE, RA } },
3528 { "lhaue", DEO(58,5), DE_MASK, BOOKE64, { RT, DE, RAL } },
3529 { "lwze", DEO(58,6), DE_MASK, BOOKE64, { RT, DE, RA } },
3530 { "lwzue", DEO(58,7), DE_MASK, BOOKE64, { RT, DE, RAL } },
3531 { "stbe", DEO(58,8), DE_MASK, BOOKE64, { RS, DE, RA } },
3532 { "stbue", DEO(58,9), DE_MASK, BOOKE64, { RS, DE, RAS } },
3533 { "sthe", DEO(58,10), DE_MASK, BOOKE64, { RS, DE, RA } },
3534 { "sthue", DEO(58,11), DE_MASK, BOOKE64, { RS, DE, RAS } },
3535 { "stwe", DEO(58,14), DE_MASK, BOOKE64, { RS, DE, RA } },
3536 { "stwue", DEO(58,15), DE_MASK, BOOKE64, { RS, DE, RAS } },
3538 { "fdivs", A(59,18,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
3539 { "fdivs.", A(59,18,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
3541 { "fsubs", A(59,20,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
3542 { "fsubs.", A(59,20,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
3544 { "fadds", A(59,21,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
3545 { "fadds.", A(59,21,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
3547 { "fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
3548 { "fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
3550 { "fres", A(59,24,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
3551 { "fres.", A(59,24,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
3553 { "fmuls", A(59,25,0), AFRB_MASK, PPC, { FRT, FRA, FRC } },
3554 { "fmuls.", A(59,25,1), AFRB_MASK, PPC, { FRT, FRA, FRC } },
3556 { "fmsubs", A(59,28,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
3557 { "fmsubs.", A(59,28,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
3559 { "fmadds", A(59,29,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
3560 { "fmadds.", A(59,29,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
3562 { "fnmsubs", A(59,30,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
3563 { "fnmsubs.",A(59,30,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
3565 { "fnmadds", A(59,31,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
3566 { "fnmadds.",A(59,31,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
3568 { "stfq", OP(60), OP_MASK, POWER2, { FRS, D, RA } },
3570 { "stfqu", OP(61), OP_MASK, POWER2, { FRS, D, RA } },
3572 { "lde", DEO(62,0), DE_MASK, BOOKE64, { RT, DES, RA } },
3574 { "std", DSO(62,0), DS_MASK, PPC64, { RS, DS, RA } },
3576 { "ldue", DEO(62,1), DE_MASK, BOOKE64, { RT, DES, RA } },
3578 { "stdu", DSO(62,1), DS_MASK, PPC64, { RS, DS, RAS } },
3580 { "lfse", DEO(62,4), DE_MASK, BOOKE64, { FRT, DES, RA } },
3581 { "lfsue", DEO(62,5), DE_MASK, BOOKE64, { FRT, DES, RAS } },
3582 { "lfde", DEO(62,6), DE_MASK, BOOKE64, { FRT, DES, RA } },
3583 { "lfdue", DEO(62,7), DE_MASK, BOOKE64, { FRT, DES, RAS } },
3584 { "stde", DEO(62,8), DE_MASK, BOOKE64, { RS, DES, RA } },
3585 { "stdue", DEO(62,9), DE_MASK, BOOKE64, { RS, DES, RAS } },
3586 { "stfse", DEO(62,12), DE_MASK, BOOKE64, { FRS, DES, RA } },
3587 { "stfsue", DEO(62,13), DE_MASK, BOOKE64, { FRS, DES, RAS } },
3588 { "stfde", DEO(62,14), DE_MASK, BOOKE64, { FRS, DES, RA } },
3589 { "stfdue", DEO(62,15), DE_MASK, BOOKE64, { FRS, DES, RAS } },
3591 { "fcmpu", X(63,0), X_MASK|(3<<21), COM, { BF, FRA, FRB } },
3593 { "frsp", XRC(63,12,0), XRA_MASK, COM, { FRT, FRB } },
3594 { "frsp.", XRC(63,12,1), XRA_MASK, COM, { FRT, FRB } },
3596 { "fctiw", XRC(63,14,0), XRA_MASK, PPCCOM, { FRT, FRB } },
3597 { "fcir", XRC(63,14,0), XRA_MASK, POWER2, { FRT, FRB } },
3598 { "fctiw.", XRC(63,14,1), XRA_MASK, PPCCOM, { FRT, FRB } },
3599 { "fcir.", XRC(63,14,1), XRA_MASK, POWER2, { FRT, FRB } },
3601 { "fctiwz", XRC(63,15,0), XRA_MASK, PPCCOM, { FRT, FRB } },
3602 { "fcirz", XRC(63,15,0), XRA_MASK, POWER2, { FRT, FRB } },
3603 { "fctiwz.", XRC(63,15,1), XRA_MASK, PPCCOM, { FRT, FRB } },
3604 { "fcirz.", XRC(63,15,1), XRA_MASK, POWER2, { FRT, FRB } },
3606 { "fdiv", A(63,18,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
3607 { "fd", A(63,18,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
3608 { "fdiv.", A(63,18,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
3609 { "fd.", A(63,18,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
3611 { "fsub", A(63,20,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
3612 { "fs", A(63,20,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
3613 { "fsub.", A(63,20,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
3614 { "fs.", A(63,20,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
3616 { "fadd", A(63,21,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
3617 { "fa", A(63,21,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
3618 { "fadd.", A(63,21,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
3619 { "fa.", A(63,21,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
3621 { "fsqrt", A(63,22,0), AFRAFRC_MASK, PPCPWR2, { FRT, FRB } },
3622 { "fsqrt.", A(63,22,1), AFRAFRC_MASK, PPCPWR2, { FRT, FRB } },
3624 { "fsel", A(63,23,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
3625 { "fsel.", A(63,23,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
3627 { "fmul", A(63,25,0), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } },
3628 { "fm", A(63,25,0), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } },
3629 { "fmul.", A(63,25,1), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } },
3630 { "fm.", A(63,25,1), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } },
3632 { "frsqrte", A(63,26,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
3633 { "frsqrte.",A(63,26,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
3635 { "fmsub", A(63,28,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
3636 { "fms", A(63,28,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
3637 { "fmsub.", A(63,28,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
3638 { "fms.", A(63,28,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
3640 { "fmadd", A(63,29,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
3641 { "fma", A(63,29,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
3642 { "fmadd.", A(63,29,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
3643 { "fma.", A(63,29,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
3645 { "fnmsub", A(63,30,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
3646 { "fnms", A(63,30,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
3647 { "fnmsub.", A(63,30,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
3648 { "fnms.", A(63,30,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
3650 { "fnmadd", A(63,31,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
3651 { "fnma", A(63,31,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
3652 { "fnmadd.", A(63,31,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
3653 { "fnma.", A(63,31,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
3655 { "fcmpo", X(63,32), X_MASK|(3<<21), COM, { BF, FRA, FRB } },
3657 { "mtfsb1", XRC(63,38,0), XRARB_MASK, COM, { BT } },
3658 { "mtfsb1.", XRC(63,38,1), XRARB_MASK, COM, { BT } },
3660 { "fneg", XRC(63,40,0), XRA_MASK, COM, { FRT, FRB } },
3661 { "fneg.", XRC(63,40,1), XRA_MASK, COM, { FRT, FRB } },
3663 { "mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, { BF, BFA } },
3665 { "mtfsb0", XRC(63,70,0), XRARB_MASK, COM, { BT } },
3666 { "mtfsb0.", XRC(63,70,1), XRARB_MASK, COM, { BT } },
3668 { "fmr", XRC(63,72,0), XRA_MASK, COM, { FRT, FRB } },
3669 { "fmr.", XRC(63,72,1), XRA_MASK, COM, { FRT, FRB } },
3671 { "mtfsfi", XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } },
3672 { "mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } },
3674 { "fnabs", XRC(63,136,0), XRA_MASK, COM, { FRT, FRB } },
3675 { "fnabs.", XRC(63,136,1), XRA_MASK, COM, { FRT, FRB } },
3677 { "fabs", XRC(63,264,0), XRA_MASK, COM, { FRT, FRB } },
3678 { "fabs.", XRC(63,264,1), XRA_MASK, COM, { FRT, FRB } },
3680 { "mffs", XRC(63,583,0), XRARB_MASK, COM, { FRT } },
3681 { "mffs.", XRC(63,583,1), XRARB_MASK, COM, { FRT } },
3683 { "mtfsf", XFL(63,711,0), XFL_MASK, COM, { FLM, FRB } },
3684 { "mtfsf.", XFL(63,711,1), XFL_MASK, COM, { FLM, FRB } },
3686 { "fctid", XRC(63,814,0), XRA_MASK, PPC64, { FRT, FRB } },
3687 { "fctid.", XRC(63,814,1), XRA_MASK, PPC64, { FRT, FRB } },
3689 { "fctidz", XRC(63,815,0), XRA_MASK, PPC64, { FRT, FRB } },
3690 { "fctidz.", XRC(63,815,1), XRA_MASK, PPC64, { FRT, FRB } },
3692 { "fcfid", XRC(63,846,0), XRA_MASK, PPC64, { FRT, FRB } },
3693 { "fcfid.", XRC(63,846,1), XRA_MASK, PPC64, { FRT, FRB } },
3697 const int powerpc_num_opcodes =
3698 sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]);
3700 /* The macro table. This is only used by the assembler. */
3702 /* The expressions of the form (-x ! 31) & (x | 31) have the value 0
3703 when x=0; 32-x when x is between 1 and 31; are negative if x is
3704 negative; and are 32 or more otherwise. This is what you want
3705 when, for instance, you are emulating a right shift by a
3706 rotate-left-and-mask, because the underlying instructions support
3707 shifts of size 0 but not shifts of size 32. By comparison, when
3708 extracting x bits from some word you want to use just 32-x, because
3709 the underlying instructions don't support extracting 0 bits but do
3710 support extracting the whole word (32 bits in this case). */
3712 const struct powerpc_macro powerpc_macros[] = {
3713 { "extldi", 4, PPC64, "rldicr %0,%1,%3,(%2)-1" },
3714 { "extldi.", 4, PPC64, "rldicr. %0,%1,%3,(%2)-1" },
3715 { "extrdi", 4, PPC64, "rldicl %0,%1,(%2)+(%3),64-(%2)" },
3716 { "extrdi.", 4, PPC64, "rldicl. %0,%1,(%2)+(%3),64-(%2)" },
3717 { "insrdi", 4, PPC64, "rldimi %0,%1,64-((%2)+(%3)),%3" },
3718 { "insrdi.", 4, PPC64, "rldimi. %0,%1,64-((%2)+(%3)),%3" },
3719 { "rotrdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),0" },
3720 { "rotrdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0" },
3721 { "sldi", 3, PPC64, "rldicr %0,%1,%2,63-(%2)" },
3722 { "sldi.", 3, PPC64, "rldicr. %0,%1,%2,63-(%2)" },
3723 { "srdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2" },
3724 { "srdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2" },
3725 { "clrrdi", 3, PPC64, "rldicr %0,%1,0,63-(%2)" },
3726 { "clrrdi.", 3, PPC64, "rldicr. %0,%1,0,63-(%2)" },
3727 { "clrlsldi",4, PPC64, "rldic %0,%1,%3,(%2)-(%3)" },
3728 { "clrlsldi.",4, PPC64, "rldic. %0,%1,%3,(%2)-(%3)" },
3730 { "extlwi", 4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1" },
3731 { "extlwi.", 4, PPCCOM, "rlwinm. %0,%1,%3,0,(%2)-1" },
3732 { "extrwi", 4, PPCCOM, "rlwinm %0,%1,(%2)+(%3),32-(%2),31" },
3733 { "extrwi.", 4, PPCCOM, "rlwinm. %0,%1,(%2)+(%3),32-(%2),31" },
3734 { "inslwi", 4, PPCCOM, "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1" },
3735 { "inslwi.", 4, PPCCOM, "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
3736 { "insrwi", 4, PPCCOM, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1" },
3737 { "insrwi.", 4, PPCCOM, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
3738 { "rotrwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31" },
3739 { "rotrwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31" },
3740 { "slwi", 3, PPCCOM, "rlwinm %0,%1,%2,0,31-(%2)" },
3741 { "sli", 3, PWRCOM, "rlinm %0,%1,%2,0,31-(%2)" },
3742 { "slwi.", 3, PPCCOM, "rlwinm. %0,%1,%2,0,31-(%2)" },
3743 { "sli.", 3, PWRCOM, "rlinm. %0,%1,%2,0,31-(%2)" },
3744 { "srwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
3745 { "sri", 3, PWRCOM, "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
3746 { "srwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
3747 { "sri.", 3, PWRCOM, "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
3748 { "clrrwi", 3, PPCCOM, "rlwinm %0,%1,0,0,31-(%2)" },
3749 { "clrrwi.", 3, PPCCOM, "rlwinm. %0,%1,0,0,31-(%2)" },
3750 { "clrlslwi",4, PPCCOM, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)" },
3751 { "clrlslwi.",4, PPCCOM, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)" },
3755 const int powerpc_num_macros =
3756 sizeof (powerpc_macros) / sizeof (powerpc_macros[0]);