* ld-sh/rd-sh.exp: New framework file.
[binutils.git] / opcodes / openrisc-dis.c
blob6bbb0cbe7f2a7526562e8f4b9f9c7b357bc0497e
1 /* Disassembler interface for targets using CGEN. -*- C -*-
2 CGEN: Cpu tools GENerator
4 THIS FILE IS MACHINE GENERATED WITH CGEN.
5 - the resultant file is machine generated, cgen-dis.in isn't
7 Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
9 This file is part of the GNU Binutils and GDB, the GNU debugger.
11 This program is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
14 any later version.
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with this program; if not, write to the Free Software Foundation, Inc.,
23 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
25 /* ??? Eventually more and more of this stuff can go to cpu-independent files.
26 Keep that in mind. */
28 #include "sysdep.h"
29 #include <stdio.h>
30 #include "ansidecl.h"
31 #include "dis-asm.h"
32 #include "bfd.h"
33 #include "symcat.h"
34 #include "openrisc-desc.h"
35 #include "openrisc-opc.h"
36 #include "opintl.h"
38 /* Default text to print if an instruction isn't recognized. */
39 #define UNKNOWN_INSN_MSG _("*unknown*")
41 static void print_normal
42 PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned int, bfd_vma, int));
43 static void print_address
44 PARAMS ((CGEN_CPU_DESC, PTR, bfd_vma, unsigned int, bfd_vma, int));
45 static void print_keyword
46 PARAMS ((CGEN_CPU_DESC, PTR, CGEN_KEYWORD *, long, unsigned int));
47 static void print_insn_normal
48 PARAMS ((CGEN_CPU_DESC, PTR, const CGEN_INSN *, CGEN_FIELDS *,
49 bfd_vma, int));
50 static int print_insn
51 PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, unsigned));
52 static int default_print_insn
53 PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *));
54 static int read_insn
55 PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, int,
56 CGEN_EXTRACT_INFO *, unsigned long *));
58 /* -- disassembler routines inserted here */
61 void openrisc_cgen_print_operand
62 PARAMS ((CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *,
63 void const *, bfd_vma, int));
65 /* Main entry point for printing operands.
66 XINFO is a `void *' and not a `disassemble_info *' to not put a requirement
67 of dis-asm.h on cgen.h.
69 This function is basically just a big switch statement. Earlier versions
70 used tables to look up the function to use, but
71 - if the table contains both assembler and disassembler functions then
72 the disassembler contains much of the assembler and vice-versa,
73 - there's a lot of inlining possibilities as things grow,
74 - using a switch statement avoids the function call overhead.
76 This function could be moved into `print_insn_normal', but keeping it
77 separate makes clear the interface between `print_insn_normal' and each of
78 the handlers.
81 void
82 openrisc_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length)
83 CGEN_CPU_DESC cd;
84 int opindex;
85 PTR xinfo;
86 CGEN_FIELDS *fields;
87 void const *attrs ATTRIBUTE_UNUSED;
88 bfd_vma pc;
89 int length;
91 disassemble_info *info = (disassemble_info *) xinfo;
93 switch (opindex)
95 case OPENRISC_OPERAND_ABS_26 :
96 print_address (cd, info, fields->f_abs26, 0|(1<<CGEN_OPERAND_ABS_ADDR), pc, length);
97 break;
98 case OPENRISC_OPERAND_DISP_26 :
99 print_address (cd, info, fields->f_disp26, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
100 break;
101 case OPENRISC_OPERAND_HI16 :
102 print_normal (cd, info, fields->f_simm16, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_SIGN_OPT), pc, length);
103 break;
104 case OPENRISC_OPERAND_LO16 :
105 print_normal (cd, info, fields->f_lo16, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_SIGN_OPT), pc, length);
106 break;
107 case OPENRISC_OPERAND_OP_F_23 :
108 print_normal (cd, info, fields->f_op4, 0, pc, length);
109 break;
110 case OPENRISC_OPERAND_OP_F_3 :
111 print_normal (cd, info, fields->f_op5, 0, pc, length);
112 break;
113 case OPENRISC_OPERAND_RA :
114 print_keyword (cd, info, & openrisc_cgen_opval_h_gr, fields->f_r2, 0);
115 break;
116 case OPENRISC_OPERAND_RB :
117 print_keyword (cd, info, & openrisc_cgen_opval_h_gr, fields->f_r3, 0);
118 break;
119 case OPENRISC_OPERAND_RD :
120 print_keyword (cd, info, & openrisc_cgen_opval_h_gr, fields->f_r1, 0);
121 break;
122 case OPENRISC_OPERAND_SIMM_16 :
123 print_normal (cd, info, fields->f_simm16, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
124 break;
125 case OPENRISC_OPERAND_UI16NC :
126 print_normal (cd, info, fields->f_i16nc, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
127 break;
128 case OPENRISC_OPERAND_UIMM_16 :
129 print_normal (cd, info, fields->f_uimm16, 0, pc, length);
130 break;
131 case OPENRISC_OPERAND_UIMM_5 :
132 print_normal (cd, info, fields->f_uimm5, 0, pc, length);
133 break;
135 default :
136 /* xgettext:c-format */
137 fprintf (stderr, _("Unrecognized field %d while printing insn.\n"),
138 opindex);
139 abort ();
143 cgen_print_fn * const openrisc_cgen_print_handlers[] =
145 print_insn_normal,
149 void
150 openrisc_cgen_init_dis (cd)
151 CGEN_CPU_DESC cd;
153 openrisc_cgen_init_opcode_table (cd);
154 openrisc_cgen_init_ibld_table (cd);
155 cd->print_handlers = & openrisc_cgen_print_handlers[0];
156 cd->print_operand = openrisc_cgen_print_operand;
160 /* Default print handler. */
162 static void
163 print_normal (cd, dis_info, value, attrs, pc, length)
164 CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
165 PTR dis_info;
166 long value;
167 unsigned int attrs;
168 bfd_vma pc ATTRIBUTE_UNUSED;
169 int length ATTRIBUTE_UNUSED;
171 disassemble_info *info = (disassemble_info *) dis_info;
173 #ifdef CGEN_PRINT_NORMAL
174 CGEN_PRINT_NORMAL (cd, info, value, attrs, pc, length);
175 #endif
177 /* Print the operand as directed by the attributes. */
178 if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
179 ; /* nothing to do */
180 else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
181 (*info->fprintf_func) (info->stream, "%ld", value);
182 else
183 (*info->fprintf_func) (info->stream, "0x%lx", value);
186 /* Default address handler. */
188 static void
189 print_address (cd, dis_info, value, attrs, pc, length)
190 CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
191 PTR dis_info;
192 bfd_vma value;
193 unsigned int attrs;
194 bfd_vma pc ATTRIBUTE_UNUSED;
195 int length ATTRIBUTE_UNUSED;
197 disassemble_info *info = (disassemble_info *) dis_info;
199 #ifdef CGEN_PRINT_ADDRESS
200 CGEN_PRINT_ADDRESS (cd, info, value, attrs, pc, length);
201 #endif
203 /* Print the operand as directed by the attributes. */
204 if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
205 ; /* nothing to do */
206 else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR))
207 (*info->print_address_func) (value, info);
208 else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR))
209 (*info->print_address_func) (value, info);
210 else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
211 (*info->fprintf_func) (info->stream, "%ld", (long) value);
212 else
213 (*info->fprintf_func) (info->stream, "0x%lx", (long) value);
216 /* Keyword print handler. */
218 static void
219 print_keyword (cd, dis_info, keyword_table, value, attrs)
220 CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
221 PTR dis_info;
222 CGEN_KEYWORD *keyword_table;
223 long value;
224 unsigned int attrs ATTRIBUTE_UNUSED;
226 disassemble_info *info = (disassemble_info *) dis_info;
227 const CGEN_KEYWORD_ENTRY *ke;
229 ke = cgen_keyword_lookup_value (keyword_table, value);
230 if (ke != NULL)
231 (*info->fprintf_func) (info->stream, "%s", ke->name);
232 else
233 (*info->fprintf_func) (info->stream, "???");
236 /* Default insn printer.
238 DIS_INFO is defined as `PTR' so the disassembler needn't know anything
239 about disassemble_info. */
241 static void
242 print_insn_normal (cd, dis_info, insn, fields, pc, length)
243 CGEN_CPU_DESC cd;
244 PTR dis_info;
245 const CGEN_INSN *insn;
246 CGEN_FIELDS *fields;
247 bfd_vma pc;
248 int length;
250 const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
251 disassemble_info *info = (disassemble_info *) dis_info;
252 const CGEN_SYNTAX_CHAR_TYPE *syn;
254 CGEN_INIT_PRINT (cd);
256 for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
258 if (CGEN_SYNTAX_MNEMONIC_P (*syn))
260 (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn));
261 continue;
263 if (CGEN_SYNTAX_CHAR_P (*syn))
265 (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn));
266 continue;
269 /* We have an operand. */
270 openrisc_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info,
271 fields, CGEN_INSN_ATTRS (insn), pc, length);
275 /* Subroutine of print_insn. Reads an insn into the given buffers and updates
276 the extract info.
277 Returns 0 if all is well, non-zero otherwise. */
279 static int
280 read_insn (cd, pc, info, buf, buflen, ex_info, insn_value)
281 CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
282 bfd_vma pc;
283 disassemble_info *info;
284 char *buf;
285 int buflen;
286 CGEN_EXTRACT_INFO *ex_info;
287 unsigned long *insn_value;
289 int status = (*info->read_memory_func) (pc, buf, buflen, info);
290 if (status != 0)
292 (*info->memory_error_func) (status, pc, info);
293 return -1;
296 ex_info->dis_info = info;
297 ex_info->valid = (1 << buflen) - 1;
298 ex_info->insn_bytes = buf;
300 *insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG);
301 return 0;
304 /* Utility to print an insn.
305 BUF is the base part of the insn, target byte order, BUFLEN bytes long.
306 The result is the size of the insn in bytes or zero for an unknown insn
307 or -1 if an error occurs fetching data (memory_error_func will have
308 been called). */
310 static int
311 print_insn (cd, pc, info, buf, buflen)
312 CGEN_CPU_DESC cd;
313 bfd_vma pc;
314 disassemble_info *info;
315 char *buf;
316 unsigned int buflen;
318 CGEN_INSN_INT insn_value;
319 const CGEN_INSN_LIST *insn_list;
320 CGEN_EXTRACT_INFO ex_info;
322 /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */
323 insn_value = cgen_get_insn_value (cd, buf, buflen * 8);
325 /* Fill in ex_info fields like read_insn would. Don't actually call
326 read_insn, since the incoming buffer is already read (and possibly
327 modified a la m32r). */
328 ex_info.valid = (1 << buflen) - 1;
329 ex_info.dis_info = info;
330 ex_info.insn_bytes = buf;
332 /* The instructions are stored in hash lists.
333 Pick the first one and keep trying until we find the right one. */
335 insn_list = CGEN_DIS_LOOKUP_INSN (cd, buf, insn_value);
336 while (insn_list != NULL)
338 const CGEN_INSN *insn = insn_list->insn;
339 CGEN_FIELDS fields;
340 int length;
341 unsigned long insn_value_cropped;
343 #ifdef CGEN_VALIDATE_INSN_SUPPORTED
344 /* Not needed as insn shouldn't be in hash lists if not supported. */
345 /* Supported by this cpu? */
346 if (! openrisc_cgen_insn_supported (cd, insn))
348 insn_list = CGEN_DIS_NEXT_INSN (insn_list);
349 continue;
351 #endif
353 /* Basic bit mask must be correct. */
354 /* ??? May wish to allow target to defer this check until the extract
355 handler. */
357 /* Base size may exceed this instruction's size. Extract the
358 relevant part from the buffer. */
359 if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen &&
360 (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
361 insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
362 info->endian == BFD_ENDIAN_BIG);
363 else
364 insn_value_cropped = insn_value;
366 if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn))
367 == CGEN_INSN_BASE_VALUE (insn))
369 /* Printing is handled in two passes. The first pass parses the
370 machine insn and extracts the fields. The second pass prints
371 them. */
373 /* Make sure the entire insn is loaded into insn_value, if it
374 can fit. */
375 if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) &&
376 (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
378 unsigned long full_insn_value;
379 int rc = read_insn (cd, pc, info, buf,
380 CGEN_INSN_BITSIZE (insn) / 8,
381 & ex_info, & full_insn_value);
382 if (rc != 0)
383 return rc;
384 length = CGEN_EXTRACT_FN (cd, insn)
385 (cd, insn, &ex_info, full_insn_value, &fields, pc);
387 else
388 length = CGEN_EXTRACT_FN (cd, insn)
389 (cd, insn, &ex_info, insn_value_cropped, &fields, pc);
391 /* length < 0 -> error */
392 if (length < 0)
393 return length;
394 if (length > 0)
396 CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length);
397 /* length is in bits, result is in bytes */
398 return length / 8;
402 insn_list = CGEN_DIS_NEXT_INSN (insn_list);
405 return 0;
408 /* Default value for CGEN_PRINT_INSN.
409 The result is the size of the insn in bytes or zero for an unknown insn
410 or -1 if an error occured fetching bytes. */
412 #ifndef CGEN_PRINT_INSN
413 #define CGEN_PRINT_INSN default_print_insn
414 #endif
416 static int
417 default_print_insn (cd, pc, info)
418 CGEN_CPU_DESC cd;
419 bfd_vma pc;
420 disassemble_info *info;
422 char buf[CGEN_MAX_INSN_SIZE];
423 int buflen;
424 int status;
426 /* Attempt to read the base part of the insn. */
427 buflen = cd->base_insn_bitsize / 8;
428 status = (*info->read_memory_func) (pc, buf, buflen, info);
430 /* Try again with the minimum part, if min < base. */
431 if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize))
433 buflen = cd->min_insn_bitsize / 8;
434 status = (*info->read_memory_func) (pc, buf, buflen, info);
437 if (status != 0)
439 (*info->memory_error_func) (status, pc, info);
440 return -1;
443 return print_insn (cd, pc, info, buf, buflen);
446 /* Main entry point.
447 Print one instruction from PC on INFO->STREAM.
448 Return the size of the instruction (in bytes). */
451 print_insn_openrisc (pc, info)
452 bfd_vma pc;
453 disassemble_info *info;
455 static CGEN_CPU_DESC cd = 0;
456 static int prev_isa;
457 static int prev_mach;
458 static int prev_endian;
459 int length;
460 int isa,mach;
461 int endian = (info->endian == BFD_ENDIAN_BIG
462 ? CGEN_ENDIAN_BIG
463 : CGEN_ENDIAN_LITTLE);
464 enum bfd_architecture arch;
466 /* ??? gdb will set mach but leave the architecture as "unknown" */
467 #ifndef CGEN_BFD_ARCH
468 #define CGEN_BFD_ARCH bfd_arch_openrisc
469 #endif
470 arch = info->arch;
471 if (arch == bfd_arch_unknown)
472 arch = CGEN_BFD_ARCH;
474 /* There's no standard way to compute the machine or isa number
475 so we leave it to the target. */
476 #ifdef CGEN_COMPUTE_MACH
477 mach = CGEN_COMPUTE_MACH (info);
478 #else
479 mach = info->mach;
480 #endif
482 #ifdef CGEN_COMPUTE_ISA
483 isa = CGEN_COMPUTE_ISA (info);
484 #else
485 isa = 0;
486 #endif
488 /* If we've switched cpu's, close the current table and open a new one. */
489 if (cd
490 && (isa != prev_isa
491 || mach != prev_mach
492 || endian != prev_endian))
494 openrisc_cgen_cpu_close (cd);
495 cd = 0;
498 /* If we haven't initialized yet, initialize the opcode table. */
499 if (! cd)
501 const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach);
502 const char *mach_name;
504 if (!arch_type)
505 abort ();
506 mach_name = arch_type->printable_name;
508 prev_isa = isa;
509 prev_mach = mach;
510 prev_endian = endian;
511 cd = openrisc_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa,
512 CGEN_CPU_OPEN_BFDMACH, mach_name,
513 CGEN_CPU_OPEN_ENDIAN, prev_endian,
514 CGEN_CPU_OPEN_END);
515 if (!cd)
516 abort ();
517 openrisc_cgen_init_dis (cd);
520 /* We try to have as much common code as possible.
521 But at this point some targets need to take over. */
522 /* ??? Some targets may need a hook elsewhere. Try to avoid this,
523 but if not possible try to move this hook elsewhere rather than
524 have two hooks. */
525 length = CGEN_PRINT_INSN (cd, pc, info);
526 if (length > 0)
527 return length;
528 if (length < 0)
529 return -1;
531 (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
532 return cd->default_insn_bitsize / 8;