1 /* i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989, 91, 92, 93, 94, 95, 96, 97, 98, 99, 2000
3 Free Software Foundation, Inc.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
22 /* Intel 80386 machine specific gas.
23 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
24 x86_64 support by Jan Hubicka (jh@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
32 #include "dwarf2dbg.h"
33 #include "opcode/i386.h"
35 #ifndef REGISTER_WARNINGS
36 #define REGISTER_WARNINGS 1
39 #ifndef INFER_ADDR_PREFIX
40 #define INFER_ADDR_PREFIX 1
43 #ifndef SCALE1_WHEN_NO_INDEX
44 /* Specifying a scale factor besides 1 when there is no index is
45 futile. eg. `mov (%ebx,2),%al' does exactly the same as
46 `mov (%ebx),%al'. To slavishly follow what the programmer
47 specified, set SCALE1_WHEN_NO_INDEX to 0. */
48 #define SCALE1_WHEN_NO_INDEX 1
54 static unsigned int mode_from_disp_size
PARAMS ((unsigned int));
55 static int fits_in_signed_byte
PARAMS ((offsetT
));
56 static int fits_in_unsigned_byte
PARAMS ((offsetT
));
57 static int fits_in_unsigned_word
PARAMS ((offsetT
));
58 static int fits_in_signed_word
PARAMS ((offsetT
));
59 static int fits_in_unsigned_long
PARAMS ((offsetT
));
60 static int fits_in_signed_long
PARAMS ((offsetT
));
61 static int smallest_imm_type
PARAMS ((offsetT
));
62 static offsetT offset_in_range
PARAMS ((offsetT
, int));
63 static int add_prefix
PARAMS ((unsigned int));
64 static void set_code_flag
PARAMS ((int));
65 static void set_16bit_gcc_code_flag
PARAMS ((int));
66 static void set_intel_syntax
PARAMS ((int));
67 static void set_cpu_arch
PARAMS ((int));
70 static bfd_reloc_code_real_type reloc
71 PARAMS ((int, int, int, bfd_reloc_code_real_type
));
75 #define DEFAULT_ARCH "i386"
77 static char *default_arch
= DEFAULT_ARCH
;
79 /* 'md_assemble ()' gathers together information and puts it into a
86 const reg_entry
*regs
;
91 /* TM holds the template for the insn were currently assembling. */
94 /* SUFFIX holds the instruction mnemonic suffix if given.
95 (e.g. 'l' for 'movl') */
98 /* OPERANDS gives the number of given operands. */
99 unsigned int operands
;
101 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
102 of given register, displacement, memory operands and immediate
104 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
106 /* TYPES [i] is the type (see above #defines) which tells us how to
107 use OP[i] for the corresponding operand. */
108 unsigned int types
[MAX_OPERANDS
];
110 /* Displacement expression, immediate expression, or register for each
112 union i386_op op
[MAX_OPERANDS
];
114 /* Flags for operands. */
115 unsigned int flags
[MAX_OPERANDS
];
116 #define Operand_PCrel 1
118 /* Relocation type for operand */
120 enum bfd_reloc_code_real disp_reloc
[MAX_OPERANDS
];
122 int disp_reloc
[MAX_OPERANDS
];
125 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
126 the base index byte below. */
127 const reg_entry
*base_reg
;
128 const reg_entry
*index_reg
;
129 unsigned int log2_scale_factor
;
131 /* SEG gives the seg_entries of this insn. They are zero unless
132 explicit segment overrides are given. */
133 const seg_entry
*seg
[2];
135 /* PREFIX holds all the given prefix opcodes (usually null).
136 PREFIXES is the number of prefix opcodes. */
137 unsigned int prefixes
;
138 unsigned char prefix
[MAX_PREFIXES
];
140 /* RM and SIB are the modrm byte and the sib byte where the
141 addressing modes of this insn are encoded. */
148 typedef struct _i386_insn i386_insn
;
150 /* List of chars besides those in app.c:symbol_chars that can start an
151 operand. Used to prevent the scrubber eating vital white-space. */
153 const char extra_symbol_chars
[] = "*%-(@";
155 const char extra_symbol_chars
[] = "*%-(";
158 /* This array holds the chars that always start a comment. If the
159 pre-processor is disabled, these aren't very useful. */
160 #if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX) && !defined(TE_FreeBSD))
161 /* Putting '/' here makes it impossible to use the divide operator.
162 However, we need it for compatibility with SVR4 systems. */
163 const char comment_chars
[] = "#/";
164 #define PREFIX_SEPARATOR '\\'
166 const char comment_chars
[] = "#";
167 #define PREFIX_SEPARATOR '/'
170 /* This array holds the chars that only start a comment at the beginning of
171 a line. If the line seems to have the form '# 123 filename'
172 .line and .file directives will appear in the pre-processed output.
173 Note that input_file.c hand checks for '#' at the beginning of the
174 first line of the input file. This is because the compiler outputs
175 #NO_APP at the beginning of its output.
176 Also note that comments started like this one will always work if
177 '/' isn't otherwise defined. */
178 #if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX) && !defined(TE_FreeBSD))
179 const char line_comment_chars
[] = "";
181 const char line_comment_chars
[] = "/";
184 const char line_separator_chars
[] = ";";
186 /* Chars that can be used to separate mant from exp in floating point
188 const char EXP_CHARS
[] = "eE";
190 /* Chars that mean this number is a floating point constant
193 const char FLT_CHARS
[] = "fFdDxX";
195 /* Tables for lexical analysis. */
196 static char mnemonic_chars
[256];
197 static char register_chars
[256];
198 static char operand_chars
[256];
199 static char identifier_chars
[256];
200 static char digit_chars
[256];
202 /* Lexical macros. */
203 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
204 #define is_operand_char(x) (operand_chars[(unsigned char) x])
205 #define is_register_char(x) (register_chars[(unsigned char) x])
206 #define is_space_char(x) ((x) == ' ')
207 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
208 #define is_digit_char(x) (digit_chars[(unsigned char) x])
210 /* All non-digit non-letter charcters that may occur in an operand. */
211 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
213 /* md_assemble() always leaves the strings it's passed unaltered. To
214 effect this we maintain a stack of saved characters that we've smashed
215 with '\0's (indicating end of strings for various sub-fields of the
216 assembler instruction). */
217 static char save_stack
[32];
218 static char *save_stack_p
;
219 #define END_STRING_AND_SAVE(s) \
220 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
221 #define RESTORE_END_STRING(s) \
222 do { *(s) = *--save_stack_p; } while (0)
224 /* The instruction we're assembling. */
227 /* Possible templates for current insn. */
228 static const templates
*current_templates
;
230 /* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
231 static expressionS disp_expressions
[2], im_expressions
[2];
233 /* Current operand we are working on. */
234 static int this_operand
;
236 /* We support four different modes. FLAG_CODE variable is used to distinguish
244 static enum flag_code flag_code
;
245 static int use_rela_relocations
= 0;
247 /* The names used to print error messages. */
248 static const char *flag_code_names
[] =
255 /* 1 for intel syntax,
257 static int intel_syntax
= 0;
259 /* 1 if register prefix % not required. */
260 static int allow_naked_reg
= 0;
262 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
263 leave, push, and pop instructions so that gcc has the same stack
264 frame as in 32 bit mode. */
265 static char stackop_size
= '\0';
267 /* Non-zero to quieten some warnings. */
268 static int quiet_warnings
= 0;
271 static const char *cpu_arch_name
= NULL
;
273 /* CPU feature flags. */
274 static unsigned int cpu_arch_flags
= CpuUnknownFlags
|CpuNo64
;
276 /* Interface to relax_segment.
277 There are 2 relax states for 386 jump insns: one for conditional &
278 one for unconditional jumps. This is because these two types of
279 jumps add different sizes to frags when we're figuring out what
280 sort of jump to choose to reach a given label. */
284 #define UNCOND_JUMP 2
288 #define SMALL16 (SMALL|CODE16)
290 #define BIG16 (BIG|CODE16)
294 #define INLINE __inline__
300 #define ENCODE_RELAX_STATE(type,size) \
301 ((relax_substateT) ((type<<2) | (size)))
302 #define SIZE_FROM_RELAX_STATE(s) \
303 ( (((s) & 0x3) == BIG ? 4 : (((s) & 0x3) == BIG16 ? 2 : 1)) )
305 /* This table is used by relax_frag to promote short jumps to long
306 ones where necessary. SMALL (short) jumps may be promoted to BIG
307 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
308 don't allow a short jump in a 32 bit code segment to be promoted to
309 a 16 bit offset jump because it's slower (requires data size
310 prefix), and doesn't work, unless the destination is in the bottom
311 64k of the code segment (The top 16 bits of eip are zeroed). */
313 const relax_typeS md_relax_table
[] =
316 1) most positive reach of this state,
317 2) most negative reach of this state,
318 3) how many bytes this mode will add to the size of the current frag
319 4) which index into the table to try if we can't fit into this one. */
325 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
326 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
327 /* dword conditionals adds 4 bytes to frag:
328 1 extra opcode byte, 3 extra displacement bytes. */
330 /* word conditionals add 2 bytes to frag:
331 1 extra opcode byte, 1 extra displacement byte. */
334 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
335 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
336 /* dword jmp adds 3 bytes to frag:
337 0 extra opcode bytes, 3 extra displacement bytes. */
339 /* word jmp adds 1 byte to frag:
340 0 extra opcode bytes, 1 extra displacement byte. */
345 static const arch_entry cpu_arch
[] = {
347 {"i186", Cpu086
|Cpu186
},
348 {"i286", Cpu086
|Cpu186
|Cpu286
},
349 {"i386", Cpu086
|Cpu186
|Cpu286
|Cpu386
},
350 {"i486", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
},
351 {"i586", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuMMX
},
352 {"i686", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|CpuSSE
},
353 {"pentium", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuMMX
},
354 {"pentiumpro",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|CpuSSE
},
355 {"k6", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuK6
|CpuMMX
|Cpu3dnow
},
356 {"athlon", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuAthlon
|CpuMMX
|Cpu3dnow
},
357 {"sledgehammer",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuAthlon
|CpuSledgehammer
|CpuMMX
|Cpu3dnow
|CpuSSE
},
362 i386_align_code (fragP
, count
)
366 /* Various efficient no-op patterns for aligning code labels.
367 Note: Don't try to assemble the instructions in the comments.
368 0L and 0w are not legal. */
369 static const char f32_1
[] =
371 static const char f32_2
[] =
372 {0x89,0xf6}; /* movl %esi,%esi */
373 static const char f32_3
[] =
374 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
375 static const char f32_4
[] =
376 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
377 static const char f32_5
[] =
379 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
380 static const char f32_6
[] =
381 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
382 static const char f32_7
[] =
383 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
384 static const char f32_8
[] =
386 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
387 static const char f32_9
[] =
388 {0x89,0xf6, /* movl %esi,%esi */
389 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
390 static const char f32_10
[] =
391 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
392 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
393 static const char f32_11
[] =
394 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
395 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
396 static const char f32_12
[] =
397 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
398 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
399 static const char f32_13
[] =
400 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
401 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
402 static const char f32_14
[] =
403 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
404 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
405 static const char f32_15
[] =
406 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
407 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
408 static const char f16_3
[] =
409 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
410 static const char f16_4
[] =
411 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
412 static const char f16_5
[] =
414 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
415 static const char f16_6
[] =
416 {0x89,0xf6, /* mov %si,%si */
417 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
418 static const char f16_7
[] =
419 {0x8d,0x74,0x00, /* lea 0(%si),%si */
420 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
421 static const char f16_8
[] =
422 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
423 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
424 static const char *const f32_patt
[] = {
425 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
426 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
, f32_15
428 static const char *const f16_patt
[] = {
429 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
,
430 f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
433 /* ??? We can't use these fillers for x86_64, since they often kills the
434 upper halves. Solve later. */
435 if (flag_code
== CODE_64BIT
)
438 if (count
> 0 && count
<= 15)
440 if (flag_code
== CODE_16BIT
)
442 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
443 f16_patt
[count
- 1], count
);
445 /* Adjust jump offset. */
446 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
449 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
450 f32_patt
[count
- 1], count
);
451 fragP
->fr_var
= count
;
455 static char *output_invalid
PARAMS ((int c
));
456 static int i386_operand
PARAMS ((char *operand_string
));
457 static int i386_intel_operand
PARAMS ((char *operand_string
, int got_a_float
));
458 static const reg_entry
*parse_register
PARAMS ((char *reg_string
,
462 static void s_bss
PARAMS ((int));
465 symbolS
*GOT_symbol
; /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
467 static INLINE
unsigned int
468 mode_from_disp_size (t
)
471 return (t
& Disp8
) ? 1 : (t
& (Disp16
| Disp32
| Disp32S
)) ? 2 : 0;
475 fits_in_signed_byte (num
)
478 return (num
>= -128) && (num
<= 127);
482 fits_in_unsigned_byte (num
)
485 return (num
& 0xff) == num
;
489 fits_in_unsigned_word (num
)
492 return (num
& 0xffff) == num
;
496 fits_in_signed_word (num
)
499 return (-32768 <= num
) && (num
<= 32767);
502 fits_in_signed_long (num
)
503 offsetT num ATTRIBUTE_UNUSED
;
508 return (!(((offsetT
) -1 << 31) & num
)
509 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
511 } /* fits_in_signed_long() */
513 fits_in_unsigned_long (num
)
514 offsetT num ATTRIBUTE_UNUSED
;
519 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
521 } /* fits_in_unsigned_long() */
524 smallest_imm_type (num
)
527 if (cpu_arch_flags
!= (Cpu086
| Cpu186
| Cpu286
| Cpu386
| Cpu486
| CpuNo64
)
528 && !(cpu_arch_flags
& (CpuUnknown
)))
530 /* This code is disabled on the 486 because all the Imm1 forms
531 in the opcode table are slower on the i486. They're the
532 versions with the implicitly specified single-position
533 displacement, which has another syntax if you really want to
536 return Imm1
| Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
| Imm64
;
538 return (fits_in_signed_byte (num
)
539 ? (Imm8S
| Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
540 : fits_in_unsigned_byte (num
)
541 ? (Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
542 : (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
543 ? (Imm16
| Imm32
| Imm32S
| Imm64
)
544 : fits_in_signed_long (num
)
545 ? (Imm32
| Imm32S
| Imm64
)
546 : fits_in_unsigned_long (num
)
552 offset_in_range (val
, size
)
560 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
561 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
562 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
564 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
569 /* If BFD64, sign extend val. */
570 if (!use_rela_relocations
)
571 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
572 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
574 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
576 char buf1
[40], buf2
[40];
578 sprint_value (buf1
, val
);
579 sprint_value (buf2
, val
& mask
);
580 as_warn (_("%s shortened to %s"), buf1
, buf2
);
585 /* Returns 0 if attempting to add a prefix where one from the same
586 class already exists, 1 if non rep/repne added, 2 if rep/repne
595 if (prefix
>= 0x40 && prefix
< 0x50 && flag_code
== CODE_64BIT
)
603 case CS_PREFIX_OPCODE
:
604 case DS_PREFIX_OPCODE
:
605 case ES_PREFIX_OPCODE
:
606 case FS_PREFIX_OPCODE
:
607 case GS_PREFIX_OPCODE
:
608 case SS_PREFIX_OPCODE
:
612 case REPNE_PREFIX_OPCODE
:
613 case REPE_PREFIX_OPCODE
:
616 case LOCK_PREFIX_OPCODE
:
624 case ADDR_PREFIX_OPCODE
:
628 case DATA_PREFIX_OPCODE
:
635 as_bad (_("same type of prefix used twice"));
640 i
.prefix
[q
] = prefix
;
645 set_code_flag (value
)
649 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
650 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
651 if (value
== CODE_64BIT
&& !(cpu_arch_flags
& CpuSledgehammer
))
653 as_bad (_("64bit mode not supported on this CPU."));
655 if (value
== CODE_32BIT
&& !(cpu_arch_flags
& Cpu386
))
657 as_bad (_("32bit mode not supported on this CPU."));
663 set_16bit_gcc_code_flag (new_code_flag
)
666 flag_code
= new_code_flag
;
667 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
668 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
673 set_intel_syntax (syntax_flag
)
676 /* Find out if register prefixing is specified. */
677 int ask_naked_reg
= 0;
680 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
682 char *string
= input_line_pointer
;
683 int e
= get_symbol_end ();
685 if (strcmp (string
, "prefix") == 0)
687 else if (strcmp (string
, "noprefix") == 0)
690 as_bad (_("bad argument to syntax directive."));
691 *input_line_pointer
= e
;
693 demand_empty_rest_of_line ();
695 intel_syntax
= syntax_flag
;
697 if (ask_naked_reg
== 0)
700 allow_naked_reg
= (intel_syntax
701 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
703 /* Conservative default. */
708 allow_naked_reg
= (ask_naked_reg
< 0);
713 int dummy ATTRIBUTE_UNUSED
;
717 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
719 char *string
= input_line_pointer
;
720 int e
= get_symbol_end ();
723 for (i
= 0; cpu_arch
[i
].name
; i
++)
725 if (strcmp (string
, cpu_arch
[i
].name
) == 0)
727 cpu_arch_name
= cpu_arch
[i
].name
;
728 cpu_arch_flags
= cpu_arch
[i
].flags
| (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
732 if (!cpu_arch
[i
].name
)
733 as_bad (_("no such architecture: `%s'"), string
);
735 *input_line_pointer
= e
;
738 as_bad (_("missing cpu architecture"));
740 demand_empty_rest_of_line ();
743 const pseudo_typeS md_pseudo_table
[] =
745 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
746 {"align", s_align_bytes
, 0},
748 {"align", s_align_ptwo
, 0},
750 {"arch", set_cpu_arch
, 0},
754 {"ffloat", float_cons
, 'f'},
755 {"dfloat", float_cons
, 'd'},
756 {"tfloat", float_cons
, 'x'},
758 {"noopt", s_ignore
, 0},
759 {"optim", s_ignore
, 0},
760 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
761 {"code16", set_code_flag
, CODE_16BIT
},
762 {"code32", set_code_flag
, CODE_32BIT
},
763 {"code64", set_code_flag
, CODE_64BIT
},
764 {"intel_syntax", set_intel_syntax
, 1},
765 {"att_syntax", set_intel_syntax
, 0},
766 {"file", dwarf2_directive_file
, 0},
767 {"loc", dwarf2_directive_loc
, 0},
771 /* For interface with expression (). */
772 extern char *input_line_pointer
;
774 /* Hash table for instruction mnemonic lookup. */
775 static struct hash_control
*op_hash
;
777 /* Hash table for register lookup. */
778 static struct hash_control
*reg_hash
;
783 const char *hash_err
;
785 /* Initialize op_hash hash table. */
786 op_hash
= hash_new ();
789 register const template *optab
;
790 register templates
*core_optab
;
792 /* Setup for loop. */
794 core_optab
= (templates
*) xmalloc (sizeof (templates
));
795 core_optab
->start
= optab
;
800 if (optab
->name
== NULL
801 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
803 /* different name --> ship out current template list;
804 add to hash table; & begin anew. */
805 core_optab
->end
= optab
;
806 hash_err
= hash_insert (op_hash
,
811 as_fatal (_("Internal Error: Can't hash %s: %s"),
815 if (optab
->name
== NULL
)
817 core_optab
= (templates
*) xmalloc (sizeof (templates
));
818 core_optab
->start
= optab
;
823 /* Initialize reg_hash hash table. */
824 reg_hash
= hash_new ();
826 register const reg_entry
*regtab
;
828 for (regtab
= i386_regtab
;
829 regtab
< i386_regtab
+ sizeof (i386_regtab
) / sizeof (i386_regtab
[0]);
832 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (PTR
) regtab
);
834 as_fatal (_("Internal Error: Can't hash %s: %s"),
840 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
845 for (c
= 0; c
< 256; c
++)
850 mnemonic_chars
[c
] = c
;
851 register_chars
[c
] = c
;
852 operand_chars
[c
] = c
;
854 else if (islower (c
))
856 mnemonic_chars
[c
] = c
;
857 register_chars
[c
] = c
;
858 operand_chars
[c
] = c
;
860 else if (isupper (c
))
862 mnemonic_chars
[c
] = tolower (c
);
863 register_chars
[c
] = mnemonic_chars
[c
];
864 operand_chars
[c
] = c
;
867 if (isalpha (c
) || isdigit (c
))
868 identifier_chars
[c
] = c
;
871 identifier_chars
[c
] = c
;
872 operand_chars
[c
] = c
;
877 identifier_chars
['@'] = '@';
879 digit_chars
['-'] = '-';
880 identifier_chars
['_'] = '_';
881 identifier_chars
['.'] = '.';
883 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
884 operand_chars
[(unsigned char) *p
] = *p
;
887 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
888 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
890 record_alignment (text_section
, 2);
891 record_alignment (data_section
, 2);
892 record_alignment (bss_section
, 2);
898 i386_print_statistics (file
)
901 hash_print_statistics (file
, "i386 opcode", op_hash
);
902 hash_print_statistics (file
, "i386 register", reg_hash
);
907 /* Debugging routines for md_assemble. */
908 static void pi
PARAMS ((char *, i386_insn
*));
909 static void pte
PARAMS ((template *));
910 static void pt
PARAMS ((unsigned int));
911 static void pe
PARAMS ((expressionS
*));
912 static void ps
PARAMS ((symbolS
*));
921 fprintf (stdout
, "%s: template ", line
);
923 fprintf (stdout
, " address: base %s index %s scale %x\n",
924 x
->base_reg
? x
->base_reg
->reg_name
: "none",
925 x
->index_reg
? x
->index_reg
->reg_name
: "none",
926 x
->log2_scale_factor
);
927 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
928 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
929 fprintf (stdout
, " sib: base %x index %x scale %x\n",
930 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
931 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
932 x
->rex
.mode64
, x
->rex
.extX
, x
->rex
.extY
, x
->rex
.extZ
);
933 for (i
= 0; i
< x
->operands
; i
++)
935 fprintf (stdout
, " #%d: ", i
+ 1);
937 fprintf (stdout
, "\n");
939 & (Reg
| SReg2
| SReg3
| Control
| Debug
| Test
| RegMMX
| RegXMM
))
940 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
941 if (x
->types
[i
] & Imm
)
943 if (x
->types
[i
] & Disp
)
953 fprintf (stdout
, " %d operands ", t
->operands
);
954 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
955 if (t
->extension_opcode
!= None
)
956 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
957 if (t
->opcode_modifier
& D
)
958 fprintf (stdout
, "D");
959 if (t
->opcode_modifier
& W
)
960 fprintf (stdout
, "W");
961 fprintf (stdout
, "\n");
962 for (i
= 0; i
< t
->operands
; i
++)
964 fprintf (stdout
, " #%d type ", i
+ 1);
965 pt (t
->operand_types
[i
]);
966 fprintf (stdout
, "\n");
974 fprintf (stdout
, " operation %d\n", e
->X_op
);
975 fprintf (stdout
, " add_number %ld (%lx)\n",
976 (long) e
->X_add_number
, (long) e
->X_add_number
);
979 fprintf (stdout
, " add_symbol ");
980 ps (e
->X_add_symbol
);
981 fprintf (stdout
, "\n");
985 fprintf (stdout
, " op_symbol ");
987 fprintf (stdout
, "\n");
995 fprintf (stdout
, "%s type %s%s",
997 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
998 segment_name (S_GET_SEGMENT (s
)));
1020 { BaseIndex
, "BaseIndex" },
1024 { Disp32S
, "d32s" },
1026 { InOutPortReg
, "InOutPortReg" },
1027 { ShiftCount
, "ShiftCount" },
1028 { Control
, "control reg" },
1029 { Test
, "test reg" },
1030 { Debug
, "debug reg" },
1031 { FloatReg
, "FReg" },
1032 { FloatAcc
, "FAcc" },
1036 { JumpAbsolute
, "Jump Absolute" },
1047 register struct type_name
*ty
;
1049 for (ty
= type_names
; ty
->mask
; ty
++)
1051 fprintf (stdout
, "%s, ", ty
->tname
);
1055 #endif /* DEBUG386 */
1058 tc_i386_force_relocation (fixp
)
1061 #ifdef BFD_ASSEMBLER
1062 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1063 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1068 return fixp
->fx_r_type
== 7;
1072 #ifdef BFD_ASSEMBLER
1074 static bfd_reloc_code_real_type
1075 reloc (size
, pcrel
, sign
, other
)
1079 bfd_reloc_code_real_type other
;
1081 if (other
!= NO_RELOC
)
1087 as_bad(_("There are no unsigned pc-relative relocations"));
1090 case 1: return BFD_RELOC_8_PCREL
;
1091 case 2: return BFD_RELOC_16_PCREL
;
1092 case 4: return BFD_RELOC_32_PCREL
;
1094 as_bad (_("can not do %d byte pc-relative relocation"), size
);
1101 case 4: return BFD_RELOC_X86_64_32S
;
1106 case 1: return BFD_RELOC_8
;
1107 case 2: return BFD_RELOC_16
;
1108 case 4: return BFD_RELOC_32
;
1109 case 8: return BFD_RELOC_64
;
1111 as_bad (_("can not do %s %d byte relocation"),
1112 sign
? "signed" : "unsigned", size
);
1116 return BFD_RELOC_NONE
;
1119 /* Here we decide which fixups can be adjusted to make them relative to
1120 the beginning of the section instead of the symbol. Basically we need
1121 to make sure that the dynamic relocations are done correctly, so in
1122 some cases we force the original symbol to be used. */
1125 tc_i386_fix_adjustable (fixP
)
1128 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1129 /* Prevent all adjustments to global symbols, or else dynamic
1130 linking will not work correctly. */
1131 if (S_IS_EXTERNAL (fixP
->fx_addsy
)
1132 || S_IS_WEAK (fixP
->fx_addsy
))
1135 /* adjust_reloc_syms doesn't know about the GOT. */
1136 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
1137 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
1138 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
1139 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
1140 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
1141 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1142 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1147 #define reloc(SIZE,PCREL,SIGN,OTHER) 0
1148 #define BFD_RELOC_16 0
1149 #define BFD_RELOC_32 0
1150 #define BFD_RELOC_16_PCREL 0
1151 #define BFD_RELOC_32_PCREL 0
1152 #define BFD_RELOC_386_PLT32 0
1153 #define BFD_RELOC_386_GOT32 0
1154 #define BFD_RELOC_386_GOTOFF 0
1155 #define BFD_RELOC_X86_64_PLT32 0
1156 #define BFD_RELOC_X86_64_GOT32 0
1157 #define BFD_RELOC_X86_64_GOTPCREL 0
1160 static int intel_float_operand
PARAMS ((char *mnemonic
));
1163 intel_float_operand (mnemonic
)
1166 if (mnemonic
[0] == 'f' && mnemonic
[1] == 'i')
1169 if (mnemonic
[0] == 'f')
1175 /* This is the guts of the machine-dependent assembler. LINE points to a
1176 machine dependent instruction. This function is supposed to emit
1177 the frags/bytes it assembles to. */
1183 /* Points to template once we've found it. */
1186 /* Count the size of the instruction generated. */
1191 char mnemonic
[MAX_MNEM_SIZE
];
1193 /* Initialize globals. */
1194 memset (&i
, '\0', sizeof (i
));
1195 for (j
= 0; j
< MAX_OPERANDS
; j
++)
1196 i
.disp_reloc
[j
] = NO_RELOC
;
1197 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
1198 memset (im_expressions
, '\0', sizeof (im_expressions
));
1199 save_stack_p
= save_stack
;
1201 /* First parse an instruction mnemonic & call i386_operand for the operands.
1202 We assume that the scrubber has arranged it so that line[0] is the valid
1203 start of a (possibly prefixed) mnemonic. */
1206 char *token_start
= l
;
1209 /* Non-zero if we found a prefix only acceptable with string insns. */
1210 const char *expecting_string_instruction
= NULL
;
1215 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
1218 if (mnem_p
>= mnemonic
+ sizeof (mnemonic
))
1220 as_bad (_("no such instruction: `%s'"), token_start
);
1225 if (!is_space_char (*l
)
1226 && *l
!= END_OF_INSN
1227 && *l
!= PREFIX_SEPARATOR
)
1229 as_bad (_("invalid character %s in mnemonic"),
1230 output_invalid (*l
));
1233 if (token_start
== l
)
1235 if (*l
== PREFIX_SEPARATOR
)
1236 as_bad (_("expecting prefix; got nothing"));
1238 as_bad (_("expecting mnemonic; got nothing"));
1242 /* Look up instruction (or prefix) via hash table. */
1243 current_templates
= hash_find (op_hash
, mnemonic
);
1245 if (*l
!= END_OF_INSN
1246 && (! is_space_char (*l
) || l
[1] != END_OF_INSN
)
1247 && current_templates
1248 && (current_templates
->start
->opcode_modifier
& IsPrefix
))
1250 /* If we are in 16-bit mode, do not allow addr16 or data16.
1251 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1252 if ((current_templates
->start
->opcode_modifier
& (Size16
| Size32
))
1253 && (((current_templates
->start
->opcode_modifier
& Size32
) != 0)
1254 ^ (flag_code
== CODE_16BIT
)))
1256 as_bad (_("redundant %s prefix"),
1257 current_templates
->start
->name
);
1260 /* Add prefix, checking for repeated prefixes. */
1261 switch (add_prefix (current_templates
->start
->base_opcode
))
1266 expecting_string_instruction
= current_templates
->start
->name
;
1269 /* Skip past PREFIX_SEPARATOR and reset token_start. */
1276 if (!current_templates
)
1278 /* See if we can get a match by trimming off a suffix. */
1281 case WORD_MNEM_SUFFIX
:
1282 case BYTE_MNEM_SUFFIX
:
1283 case QWORD_MNEM_SUFFIX
:
1284 i
.suffix
= mnem_p
[-1];
1286 current_templates
= hash_find (op_hash
, mnemonic
);
1288 case SHORT_MNEM_SUFFIX
:
1289 case LONG_MNEM_SUFFIX
:
1292 i
.suffix
= mnem_p
[-1];
1294 current_templates
= hash_find (op_hash
, mnemonic
);
1302 if (intel_float_operand (mnemonic
))
1303 i
.suffix
= SHORT_MNEM_SUFFIX
;
1305 i
.suffix
= LONG_MNEM_SUFFIX
;
1307 current_templates
= hash_find (op_hash
, mnemonic
);
1311 if (!current_templates
)
1313 as_bad (_("no such instruction: `%s'"), token_start
);
1318 /* Check if instruction is supported on specified architecture. */
1319 if (cpu_arch_flags
!= 0)
1321 if ((current_templates
->start
->cpu_flags
& ~(Cpu64
| CpuNo64
))
1322 & ~(cpu_arch_flags
& ~(Cpu64
| CpuNo64
)))
1324 as_warn (_("`%s' is not supported on `%s'"),
1325 current_templates
->start
->name
, cpu_arch_name
);
1327 else if ((Cpu386
& ~cpu_arch_flags
) && (flag_code
!= CODE_16BIT
))
1329 as_warn (_("use .code16 to ensure correct addressing mode"));
1333 /* Check for rep/repne without a string instruction. */
1334 if (expecting_string_instruction
1335 && !(current_templates
->start
->opcode_modifier
& IsString
))
1337 as_bad (_("expecting string instruction after `%s'"),
1338 expecting_string_instruction
);
1342 /* There may be operands to parse. */
1343 if (*l
!= END_OF_INSN
)
1345 /* 1 if operand is pending after ','. */
1346 unsigned int expecting_operand
= 0;
1348 /* Non-zero if operand parens not balanced. */
1349 unsigned int paren_not_balanced
;
1353 /* Skip optional white space before operand. */
1354 if (is_space_char (*l
))
1356 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
1358 as_bad (_("invalid character %s before operand %d"),
1359 output_invalid (*l
),
1363 token_start
= l
; /* after white space */
1364 paren_not_balanced
= 0;
1365 while (paren_not_balanced
|| *l
!= ',')
1367 if (*l
== END_OF_INSN
)
1369 if (paren_not_balanced
)
1372 as_bad (_("unbalanced parenthesis in operand %d."),
1375 as_bad (_("unbalanced brackets in operand %d."),
1380 break; /* we are done */
1382 else if (!is_operand_char (*l
) && !is_space_char (*l
))
1384 as_bad (_("invalid character %s in operand %d"),
1385 output_invalid (*l
),
1392 ++paren_not_balanced
;
1394 --paren_not_balanced
;
1399 ++paren_not_balanced
;
1401 --paren_not_balanced
;
1405 if (l
!= token_start
)
1406 { /* Yes, we've read in another operand. */
1407 unsigned int operand_ok
;
1408 this_operand
= i
.operands
++;
1409 if (i
.operands
> MAX_OPERANDS
)
1411 as_bad (_("spurious operands; (%d operands/instruction max)"),
1415 /* Now parse operand adding info to 'i' as we go along. */
1416 END_STRING_AND_SAVE (l
);
1420 i386_intel_operand (token_start
,
1421 intel_float_operand (mnemonic
));
1423 operand_ok
= i386_operand (token_start
);
1425 RESTORE_END_STRING (l
);
1431 if (expecting_operand
)
1433 expecting_operand_after_comma
:
1434 as_bad (_("expecting operand after ','; got nothing"));
1439 as_bad (_("expecting operand before ','; got nothing"));
1444 /* Now *l must be either ',' or END_OF_INSN. */
1447 if (*++l
== END_OF_INSN
)
1449 /* Just skip it, if it's \n complain. */
1450 goto expecting_operand_after_comma
;
1452 expecting_operand
= 1;
1455 while (*l
!= END_OF_INSN
);
1459 /* Now we've parsed the mnemonic into a set of templates, and have the
1462 Next, we find a template that matches the given insn,
1463 making sure the overlap of the given operands types is consistent
1464 with the template operand types. */
1466 #define MATCH(overlap, given, template) \
1467 ((overlap & ~JumpAbsolute) \
1468 && ((given) & (BaseIndex|JumpAbsolute)) == ((overlap) & (BaseIndex|JumpAbsolute)))
1470 /* If given types r0 and r1 are registers they must be of the same type
1471 unless the expected operand type register overlap is null.
1472 Note that Acc in a template matches every size of reg. */
1473 #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
1474 ( ((g0) & Reg) == 0 || ((g1) & Reg) == 0 || \
1475 ((g0) & Reg) == ((g1) & Reg) || \
1476 ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
1479 register unsigned int overlap0
, overlap1
;
1480 unsigned int overlap2
;
1481 unsigned int found_reverse_match
;
1484 /* All intel opcodes have reversed operands except for "bound" and
1485 "enter". We also don't reverse intersegment "jmp" and "call"
1486 instructions with 2 immediate operands so that the immediate segment
1487 precedes the offset, as it does when in AT&T mode. "enter" and the
1488 intersegment "jmp" and "call" instructions are the only ones that
1489 have two immediate operands. */
1490 if (intel_syntax
&& i
.operands
> 1
1491 && (strcmp (mnemonic
, "bound") != 0)
1492 && !((i
.types
[0] & Imm
) && (i
.types
[1] & Imm
)))
1494 union i386_op temp_op
;
1495 unsigned int temp_type
;
1496 #ifdef BFD_ASSEMBLER
1497 enum bfd_reloc_code_real temp_reloc
;
1504 if (i
.operands
== 2)
1509 else if (i
.operands
== 3)
1514 temp_type
= i
.types
[xchg2
];
1515 i
.types
[xchg2
] = i
.types
[xchg1
];
1516 i
.types
[xchg1
] = temp_type
;
1517 temp_op
= i
.op
[xchg2
];
1518 i
.op
[xchg2
] = i
.op
[xchg1
];
1519 i
.op
[xchg1
] = temp_op
;
1520 temp_reloc
= i
.disp_reloc
[xchg2
];
1521 i
.disp_reloc
[xchg2
] = i
.disp_reloc
[xchg1
];
1522 i
.disp_reloc
[xchg1
] = temp_reloc
;
1524 if (i
.mem_operands
== 2)
1526 const seg_entry
*temp_seg
;
1527 temp_seg
= i
.seg
[0];
1528 i
.seg
[0] = i
.seg
[1];
1529 i
.seg
[1] = temp_seg
;
1535 /* Try to ensure constant immediates are represented in the smallest
1537 char guess_suffix
= 0;
1541 guess_suffix
= i
.suffix
;
1542 else if (i
.reg_operands
)
1544 /* Figure out a suffix from the last register operand specified.
1545 We can't do this properly yet, ie. excluding InOutPortReg,
1546 but the following works for instructions with immediates.
1547 In any case, we can't set i.suffix yet. */
1548 for (op
= i
.operands
; --op
>= 0;)
1549 if (i
.types
[op
] & Reg
)
1551 if (i
.types
[op
] & Reg8
)
1552 guess_suffix
= BYTE_MNEM_SUFFIX
;
1553 else if (i
.types
[op
] & Reg16
)
1554 guess_suffix
= WORD_MNEM_SUFFIX
;
1555 else if (i
.types
[op
] & Reg32
)
1556 guess_suffix
= LONG_MNEM_SUFFIX
;
1557 else if (i
.types
[op
] & Reg64
)
1558 guess_suffix
= QWORD_MNEM_SUFFIX
;
1562 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
1563 guess_suffix
= WORD_MNEM_SUFFIX
;
1565 for (op
= i
.operands
; --op
>= 0;)
1566 if (i
.types
[op
] & Imm
)
1568 switch (i
.op
[op
].imms
->X_op
)
1571 /* If a suffix is given, this operand may be shortened. */
1572 switch (guess_suffix
)
1574 case LONG_MNEM_SUFFIX
:
1575 i
.types
[op
] |= Imm32
| Imm64
;
1577 case WORD_MNEM_SUFFIX
:
1578 i
.types
[op
] |= Imm16
| Imm32S
| Imm32
| Imm64
;
1580 case BYTE_MNEM_SUFFIX
:
1581 i
.types
[op
] |= Imm16
| Imm8
| Imm8S
| Imm32S
| Imm32
| Imm64
;
1585 /* If this operand is at most 16 bits, convert it to a
1586 signed 16 bit number before trying to see whether it will
1587 fit in an even smaller size. This allows a 16-bit operand
1588 such as $0xffe0 to be recognised as within Imm8S range. */
1589 if ((i
.types
[op
] & Imm16
)
1590 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
)0xffff) == 0)
1592 i
.op
[op
].imms
->X_add_number
=
1593 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
1595 if ((i
.types
[op
] & Imm32
)
1596 && (i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1)) == 0)
1598 i
.op
[op
].imms
->X_add_number
=
1599 (i
.op
[op
].imms
->X_add_number
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
1601 i
.types
[op
] |= smallest_imm_type (i
.op
[op
].imms
->X_add_number
);
1602 /* We must avoid matching of Imm32 templates when 64bit only immediate is available. */
1603 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
1604 i
.types
[op
] &= ~Imm32
;
1609 /* Symbols and expressions. */
1611 /* Convert symbolic operand to proper sizes for matching. */
1612 switch (guess_suffix
)
1614 case QWORD_MNEM_SUFFIX
:
1615 i
.types
[op
] = Imm64
| Imm32S
;
1617 case LONG_MNEM_SUFFIX
:
1618 i
.types
[op
] = Imm32
| Imm64
;
1620 case WORD_MNEM_SUFFIX
:
1621 i
.types
[op
] = Imm16
| Imm32
| Imm64
;
1624 case BYTE_MNEM_SUFFIX
:
1625 i
.types
[op
] = Imm8
| Imm8S
| Imm16
| Imm32S
| Imm32
;
1634 if (i
.disp_operands
)
1636 /* Try to use the smallest displacement type too. */
1639 for (op
= i
.operands
; --op
>= 0;)
1640 if ((i
.types
[op
] & Disp
)
1641 && i
.op
[op
].imms
->X_op
== O_constant
)
1643 offsetT disp
= i
.op
[op
].disps
->X_add_number
;
1645 if (i
.types
[op
] & Disp16
)
1647 /* We know this operand is at most 16 bits, so
1648 convert to a signed 16 bit number before trying
1649 to see whether it will fit in an even smaller
1652 disp
= (((disp
& 0xffff) ^ 0x8000) - 0x8000);
1654 else if (i
.types
[op
] & Disp32
)
1656 /* We know this operand is at most 32 bits, so convert to a
1657 signed 32 bit number before trying to see whether it will
1658 fit in an even smaller size. */
1659 disp
&= (((offsetT
) 2 << 31) - 1);
1660 disp
= (disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
1662 if (flag_code
== CODE_64BIT
)
1664 if (fits_in_signed_long (disp
))
1665 i
.types
[op
] |= Disp32S
;
1666 if (fits_in_unsigned_long (disp
))
1667 i
.types
[op
] |= Disp32
;
1669 if ((i
.types
[op
] & (Disp32
| Disp32S
| Disp16
))
1670 && fits_in_signed_byte (disp
))
1671 i
.types
[op
] |= Disp8
;
1678 found_reverse_match
= 0;
1679 suffix_check
= (i
.suffix
== BYTE_MNEM_SUFFIX
1681 : (i
.suffix
== WORD_MNEM_SUFFIX
1683 : (i
.suffix
== SHORT_MNEM_SUFFIX
1685 : (i
.suffix
== LONG_MNEM_SUFFIX
1687 : (i
.suffix
== QWORD_MNEM_SUFFIX
1689 : (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
? No_xSuf
: 0))))));
1691 for (t
= current_templates
->start
;
1692 t
< current_templates
->end
;
1695 /* Must have right number of operands. */
1696 if (i
.operands
!= t
->operands
)
1699 /* Check the suffix, except for some instructions in intel mode. */
1700 if ((t
->opcode_modifier
& suffix_check
)
1702 && (t
->opcode_modifier
& IgnoreSize
))
1704 && t
->base_opcode
== 0xd9
1705 && (t
->extension_opcode
== 5 /* 0xd9,5 "fldcw" */
1706 || t
->extension_opcode
== 7))) /* 0xd9,7 "f{n}stcw" */
1709 else if (!t
->operands
)
1710 /* 0 operands always matches. */
1713 overlap0
= i
.types
[0] & t
->operand_types
[0];
1714 switch (t
->operands
)
1717 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0]))
1722 overlap1
= i
.types
[1] & t
->operand_types
[1];
1723 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0])
1724 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[1])
1725 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
1726 t
->operand_types
[0],
1727 overlap1
, i
.types
[1],
1728 t
->operand_types
[1]))
1730 /* Check if other direction is valid ... */
1731 if ((t
->opcode_modifier
& (D
|FloatD
)) == 0)
1734 /* Try reversing direction of operands. */
1735 overlap0
= i
.types
[0] & t
->operand_types
[1];
1736 overlap1
= i
.types
[1] & t
->operand_types
[0];
1737 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[1])
1738 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[0])
1739 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
1740 t
->operand_types
[1],
1741 overlap1
, i
.types
[1],
1742 t
->operand_types
[0]))
1744 /* Does not match either direction. */
1747 /* found_reverse_match holds which of D or FloatDR
1749 found_reverse_match
= t
->opcode_modifier
& (D
|FloatDR
);
1751 /* Found a forward 2 operand match here. */
1752 else if (t
->operands
== 3)
1754 /* Here we make use of the fact that there are no
1755 reverse match 3 operand instructions, and all 3
1756 operand instructions only need to be checked for
1757 register consistency between operands 2 and 3. */
1758 overlap2
= i
.types
[2] & t
->operand_types
[2];
1759 if (!MATCH (overlap2
, i
.types
[2], t
->operand_types
[2])
1760 || !CONSISTENT_REGISTER_MATCH (overlap1
, i
.types
[1],
1761 t
->operand_types
[1],
1762 overlap2
, i
.types
[2],
1763 t
->operand_types
[2]))
1767 /* Found either forward/reverse 2 or 3 operand match here:
1768 slip through to break. */
1770 if (t
->cpu_flags
& ~cpu_arch_flags
)
1772 found_reverse_match
= 0;
1775 /* We've found a match; break out of loop. */
1778 if (t
== current_templates
->end
)
1780 /* We found no match. */
1781 as_bad (_("suffix or operands invalid for `%s'"),
1782 current_templates
->start
->name
);
1786 if (!quiet_warnings
)
1789 && ((i
.types
[0] & JumpAbsolute
)
1790 != (t
->operand_types
[0] & JumpAbsolute
)))
1792 as_warn (_("indirect %s without `*'"), t
->name
);
1795 if ((t
->opcode_modifier
& (IsPrefix
|IgnoreSize
))
1796 == (IsPrefix
|IgnoreSize
))
1798 /* Warn them that a data or address size prefix doesn't
1799 affect assembly of the next line of code. */
1800 as_warn (_("stand-alone `%s' prefix"), t
->name
);
1804 /* Copy the template we found. */
1806 if (found_reverse_match
)
1808 /* If we found a reverse match we must alter the opcode
1809 direction bit. found_reverse_match holds bits to change
1810 (different for int & float insns). */
1812 i
.tm
.base_opcode
^= found_reverse_match
;
1814 i
.tm
.operand_types
[0] = t
->operand_types
[1];
1815 i
.tm
.operand_types
[1] = t
->operand_types
[0];
1818 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1821 && (i
.tm
.base_opcode
& 0xfffffde0) == 0xdce0)
1822 i
.tm
.base_opcode
^= FloatR
;
1824 if (i
.tm
.opcode_modifier
& FWait
)
1825 if (! add_prefix (FWAIT_OPCODE
))
1828 /* Check string instruction segment overrides. */
1829 if ((i
.tm
.opcode_modifier
& IsString
) != 0 && i
.mem_operands
!= 0)
1831 int mem_op
= (i
.types
[0] & AnyMem
) ? 0 : 1;
1832 if ((i
.tm
.operand_types
[mem_op
] & EsSeg
) != 0)
1834 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
1836 as_bad (_("`%s' operand %d must use `%%es' segment"),
1841 /* There's only ever one segment override allowed per instruction.
1842 This instruction possibly has a legal segment override on the
1843 second operand, so copy the segment to where non-string
1844 instructions store it, allowing common code. */
1845 i
.seg
[0] = i
.seg
[1];
1847 else if ((i
.tm
.operand_types
[mem_op
+ 1] & EsSeg
) != 0)
1849 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
1851 as_bad (_("`%s' operand %d must use `%%es' segment"),
1859 if (i
.reg_operands
&& flag_code
< CODE_64BIT
)
1862 for (op
= i
.operands
; --op
>= 0; )
1863 if ((i
.types
[op
] & Reg
)
1864 && (i
.op
[op
].regs
->reg_flags
& (RegRex64
|RegRex
)))
1865 as_bad (_("Extended register `%%%s' available only in 64bit mode."),
1866 i
.op
[op
].regs
->reg_name
);
1869 /* If matched instruction specifies an explicit instruction mnemonic
1871 if (i
.tm
.opcode_modifier
& (Size16
| Size32
| Size64
))
1873 if (i
.tm
.opcode_modifier
& Size16
)
1874 i
.suffix
= WORD_MNEM_SUFFIX
;
1875 else if (i
.tm
.opcode_modifier
& Size64
)
1876 i
.suffix
= QWORD_MNEM_SUFFIX
;
1878 i
.suffix
= LONG_MNEM_SUFFIX
;
1880 else if (i
.reg_operands
)
1882 /* If there's no instruction mnemonic suffix we try to invent one
1883 based on register operands. */
1886 /* We take i.suffix from the last register operand specified,
1887 Destination register type is more significant than source
1890 for (op
= i
.operands
; --op
>= 0;)
1891 if ((i
.types
[op
] & Reg
)
1892 && !(i
.tm
.operand_types
[op
] & InOutPortReg
))
1894 i
.suffix
= ((i
.types
[op
] & Reg8
) ? BYTE_MNEM_SUFFIX
:
1895 (i
.types
[op
] & Reg16
) ? WORD_MNEM_SUFFIX
:
1896 (i
.types
[op
] & Reg64
) ? QWORD_MNEM_SUFFIX
:
1901 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
1904 for (op
= i
.operands
; --op
>= 0;)
1906 /* If this is an eight bit register, it's OK. If it's
1907 the 16 or 32 bit version of an eight bit register,
1908 we will just use the low portion, and that's OK too. */
1909 if (i
.types
[op
] & Reg8
)
1912 /* movzx and movsx should not generate this warning. */
1914 && (i
.tm
.base_opcode
== 0xfb7
1915 || i
.tm
.base_opcode
== 0xfb6
1916 || i
.tm
.base_opcode
== 0x63
1917 || i
.tm
.base_opcode
== 0xfbe
1918 || i
.tm
.base_opcode
== 0xfbf))
1921 if ((i
.types
[op
] & WordReg
) && i
.op
[op
].regs
->reg_num
< 4
1923 /* Check that the template allows eight bit regs
1924 This kills insns such as `orb $1,%edx', which
1925 maybe should be allowed. */
1926 && (i
.tm
.operand_types
[op
] & (Reg8
|InOutPortReg
))
1930 /* Prohibit these changes in the 64bit mode, since
1931 the lowering is more complicated. */
1932 if (flag_code
== CODE_64BIT
1933 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
1934 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
1935 i
.op
[op
].regs
->reg_name
,
1937 #if REGISTER_WARNINGS
1939 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
1940 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
1941 (i
.op
[op
].regs
- (i
.types
[op
] & Reg16
? 8 : 16))->reg_name
,
1942 i
.op
[op
].regs
->reg_name
,
1947 /* Any other register is bad. */
1948 if (i
.types
[op
] & (Reg
| RegMMX
| RegXMM
1950 | Control
| Debug
| Test
1951 | FloatReg
| FloatAcc
))
1953 as_bad (_("`%%%s' not allowed with `%s%c'"),
1954 i
.op
[op
].regs
->reg_name
,
1961 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
1965 for (op
= i
.operands
; --op
>= 0;)
1966 /* Reject eight bit registers, except where the template
1967 requires them. (eg. movzb) */
1968 if ((i
.types
[op
] & Reg8
) != 0
1969 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
1971 as_bad (_("`%%%s' not allowed with `%s%c'"),
1972 i
.op
[op
].regs
->reg_name
,
1977 /* Warn if the e prefix on a general reg is missing. */
1978 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
1979 && (i
.types
[op
] & Reg16
) != 0
1980 && (i
.tm
.operand_types
[op
] & (Reg32
|Acc
)) != 0)
1982 /* Prohibit these changes in the 64bit mode, since
1983 the lowering is more complicated. */
1984 if (flag_code
== CODE_64BIT
)
1985 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
1986 i
.op
[op
].regs
->reg_name
,
1988 #if REGISTER_WARNINGS
1990 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
1991 (i
.op
[op
].regs
+ 8)->reg_name
,
1992 i
.op
[op
].regs
->reg_name
,
1996 /* Warn if the r prefix on a general reg is missing. */
1997 else if ((i
.types
[op
] & Reg64
) != 0
1998 && (i
.tm
.operand_types
[op
] & (Reg32
|Acc
)) != 0)
2000 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2001 i
.op
[op
].regs
->reg_name
,
2005 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
2008 if (flag_code
< CODE_64BIT
)
2009 as_bad (_("64bit operations available only in 64bit modes."));
2011 for (op
= i
.operands
; --op
>= 0; )
2012 /* Reject eight bit registers, except where the template
2013 requires them. (eg. movzb) */
2014 if ((i
.types
[op
] & Reg8
) != 0
2015 && (i
.tm
.operand_types
[op
] & (Reg16
|Reg32
|Acc
)) != 0)
2017 as_bad (_("`%%%s' not allowed with `%s%c'"),
2018 i
.op
[op
].regs
->reg_name
,
2023 /* Warn if the e prefix on a general reg is missing. */
2024 else if (((i
.types
[op
] & Reg16
) != 0
2025 || (i
.types
[op
] & Reg32
) != 0)
2026 && (i
.tm
.operand_types
[op
] & (Reg32
|Acc
)) != 0)
2028 /* Prohibit these changes in the 64bit mode, since
2029 the lowering is more complicated. */
2030 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2031 i
.op
[op
].regs
->reg_name
,
2035 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
2038 for (op
= i
.operands
; --op
>= 0;)
2039 /* Reject eight bit registers, except where the template
2040 requires them. (eg. movzb) */
2041 if ((i
.types
[op
] & Reg8
) != 0
2042 && (i
.tm
.operand_types
[op
] & (Reg16
|Reg32
|Acc
)) != 0)
2044 as_bad (_("`%%%s' not allowed with `%s%c'"),
2045 i
.op
[op
].regs
->reg_name
,
2050 /* Warn if the e prefix on a general reg is present. */
2051 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
2052 && (i
.types
[op
] & Reg32
) != 0
2053 && (i
.tm
.operand_types
[op
] & (Reg16
|Acc
)) != 0)
2055 /* Prohibit these changes in the 64bit mode, since
2056 the lowering is more complicated. */
2057 if (flag_code
== CODE_64BIT
)
2058 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2059 i
.op
[op
].regs
->reg_name
,
2062 #if REGISTER_WARNINGS
2063 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2064 (i
.op
[op
].regs
- 8)->reg_name
,
2065 i
.op
[op
].regs
->reg_name
,
2070 else if (intel_syntax
&& (i
.tm
.opcode_modifier
& IgnoreSize
))
2071 /* Do nothing if the instruction is going to ignore the prefix. */
2076 else if ((i
.tm
.opcode_modifier
& DefaultSize
) && !i
.suffix
)
2078 i
.suffix
= stackop_size
;
2080 /* Make still unresolved immediate matches conform to size of immediate
2081 given in i.suffix. Note: overlap2 cannot be an immediate! */
2082 if ((overlap0
& (Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
))
2083 && overlap0
!= Imm8
&& overlap0
!= Imm8S
2084 && overlap0
!= Imm16
&& overlap0
!= Imm32S
2085 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
2089 overlap0
&= (i
.suffix
== BYTE_MNEM_SUFFIX
? (Imm8
| Imm8S
) :
2090 (i
.suffix
== WORD_MNEM_SUFFIX
? Imm16
:
2091 (i
.suffix
== QWORD_MNEM_SUFFIX
? Imm64
| Imm32S
: Imm32
)));
2093 else if (overlap0
== (Imm16
| Imm32S
| Imm32
)
2094 || overlap0
== (Imm16
| Imm32
)
2095 || overlap0
== (Imm16
| Imm32S
))
2098 ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)) ? Imm16
: Imm32S
;
2100 if (overlap0
!= Imm8
&& overlap0
!= Imm8S
2101 && overlap0
!= Imm16
&& overlap0
!= Imm32S
2102 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
2104 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
2108 if ((overlap1
& (Imm8
| Imm8S
| Imm16
| Imm32S
| Imm32
))
2109 && overlap1
!= Imm8
&& overlap1
!= Imm8S
2110 && overlap1
!= Imm16
&& overlap1
!= Imm32S
2111 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
2115 overlap1
&= (i
.suffix
== BYTE_MNEM_SUFFIX
? (Imm8
| Imm8S
) :
2116 (i
.suffix
== WORD_MNEM_SUFFIX
? Imm16
:
2117 (i
.suffix
== QWORD_MNEM_SUFFIX
? Imm64
| Imm32S
: Imm32
)));
2119 else if (overlap1
== (Imm16
| Imm32
| Imm32S
)
2120 || overlap1
== (Imm16
| Imm32
)
2121 || overlap1
== (Imm16
| Imm32S
))
2124 ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)) ? Imm16
: Imm32S
;
2126 if (overlap1
!= Imm8
&& overlap1
!= Imm8S
2127 && overlap1
!= Imm16
&& overlap1
!= Imm32S
2128 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
2130 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1
, i
.suffix
);
2134 assert ((overlap2
& Imm
) == 0);
2136 i
.types
[0] = overlap0
;
2137 if (overlap0
& ImplicitRegister
)
2139 if (overlap0
& Imm1
)
2140 i
.imm_operands
= 0; /* kludge for shift insns. */
2142 i
.types
[1] = overlap1
;
2143 if (overlap1
& ImplicitRegister
)
2146 i
.types
[2] = overlap2
;
2147 if (overlap2
& ImplicitRegister
)
2150 /* Finalize opcode. First, we change the opcode based on the operand
2151 size given by i.suffix: We need not change things for byte insns. */
2153 if (!i
.suffix
&& (i
.tm
.opcode_modifier
& W
))
2155 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2159 /* For movzx and movsx, need to check the register type. */
2161 && (i
.tm
.base_opcode
== 0xfb6 || i
.tm
.base_opcode
== 0xfbe))
2162 if (i
.suffix
&& i
.suffix
== BYTE_MNEM_SUFFIX
)
2164 unsigned int prefix
= DATA_PREFIX_OPCODE
;
2166 if ((i
.op
[1].regs
->reg_type
& Reg16
) != 0)
2167 if (!add_prefix (prefix
))
2171 if (i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
2173 /* It's not a byte, select word/dword operation. */
2174 if (i
.tm
.opcode_modifier
& W
)
2176 if (i
.tm
.opcode_modifier
& ShortForm
)
2177 i
.tm
.base_opcode
|= 8;
2179 i
.tm
.base_opcode
|= 1;
2181 /* Now select between word & dword operations via the operand
2182 size prefix, except for instructions that will ignore this
2184 if (i
.suffix
!= QWORD_MNEM_SUFFIX
2185 && (i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
2186 && !(i
.tm
.opcode_modifier
& IgnoreSize
))
2188 unsigned int prefix
= DATA_PREFIX_OPCODE
;
2189 if (i
.tm
.opcode_modifier
& JumpByte
) /* jcxz, loop */
2190 prefix
= ADDR_PREFIX_OPCODE
;
2192 if (! add_prefix (prefix
))
2196 /* Set mode64 for an operand. */
2197 if (i
.suffix
== QWORD_MNEM_SUFFIX
2198 && !(i
.tm
.opcode_modifier
& NoRex64
))
2201 /* Size floating point instruction. */
2202 if (i
.suffix
== LONG_MNEM_SUFFIX
)
2204 if (i
.tm
.opcode_modifier
& FloatMF
)
2205 i
.tm
.base_opcode
^= 4;
2209 if (i
.tm
.opcode_modifier
& ImmExt
)
2211 /* These AMD 3DNow! and Intel Katmai New Instructions have an
2212 opcode suffix which is coded in the same place as an 8-bit
2213 immediate field would be. Here we fake an 8-bit immediate
2214 operand from the opcode suffix stored in tm.extension_opcode. */
2218 assert (i
.imm_operands
== 0 && i
.operands
<= 2 && 2 < MAX_OPERANDS
);
2220 exp
= &im_expressions
[i
.imm_operands
++];
2221 i
.op
[i
.operands
].imms
= exp
;
2222 i
.types
[i
.operands
++] = Imm8
;
2223 exp
->X_op
= O_constant
;
2224 exp
->X_add_number
= i
.tm
.extension_opcode
;
2225 i
.tm
.extension_opcode
= None
;
2228 /* For insns with operands there are more diddles to do to the opcode. */
2231 /* Default segment register this instruction will use
2232 for memory accesses. 0 means unknown.
2233 This is only for optimizing out unnecessary segment overrides. */
2234 const seg_entry
*default_seg
= 0;
2236 /* The imul $imm, %reg instruction is converted into
2237 imul $imm, %reg, %reg, and the clr %reg instruction
2238 is converted into xor %reg, %reg. */
2239 if (i
.tm
.opcode_modifier
& regKludge
)
2241 unsigned int first_reg_op
= (i
.types
[0] & Reg
) ? 0 : 1;
2242 /* Pretend we saw the extra register operand. */
2243 assert (i
.op
[first_reg_op
+ 1].regs
== 0);
2244 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
2245 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
2249 if (i
.tm
.opcode_modifier
& ShortForm
)
2251 /* The register or float register operand is in operand 0 or 1. */
2252 unsigned int op
= (i
.types
[0] & (Reg
| FloatReg
)) ? 0 : 1;
2253 /* Register goes in low 3 bits of opcode. */
2254 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
2255 if (i
.op
[op
].regs
->reg_flags
& RegRex
)
2257 if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
2259 /* Warn about some common errors, but press on regardless.
2260 The first case can be generated by gcc (<= 2.8.1). */
2261 if (i
.operands
== 2)
2263 /* Reversed arguments on faddp, fsubp, etc. */
2264 as_warn (_("translating to `%s %%%s,%%%s'"), i
.tm
.name
,
2265 i
.op
[1].regs
->reg_name
,
2266 i
.op
[0].regs
->reg_name
);
2270 /* Extraneous `l' suffix on fp insn. */
2271 as_warn (_("translating to `%s %%%s'"), i
.tm
.name
,
2272 i
.op
[0].regs
->reg_name
);
2276 else if (i
.tm
.opcode_modifier
& Modrm
)
2278 /* The opcode is completed (modulo i.tm.extension_opcode which
2279 must be put into the modrm byte).
2280 Now, we make the modrm & index base bytes based on all the
2281 info we've collected. */
2283 /* i.reg_operands MUST be the number of real register operands;
2284 implicit registers do not count. */
2285 if (i
.reg_operands
== 2)
2287 unsigned int source
, dest
;
2288 source
= ((i
.types
[0]
2289 & (Reg
| RegMMX
| RegXMM
2291 | Control
| Debug
| Test
))
2296 /* One of the register operands will be encoded in the
2297 i.tm.reg field, the other in the combined i.tm.mode
2298 and i.tm.regmem fields. If no form of this
2299 instruction supports a memory destination operand,
2300 then we assume the source operand may sometimes be
2301 a memory operand and so we need to store the
2302 destination in the i.rm.reg field. */
2303 if ((i
.tm
.operand_types
[dest
] & AnyMem
) == 0)
2305 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
2306 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
2307 if (i
.op
[dest
].regs
->reg_flags
& RegRex
)
2309 if (i
.op
[source
].regs
->reg_flags
& RegRex
)
2314 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
2315 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
2316 if (i
.op
[dest
].regs
->reg_flags
& RegRex
)
2318 if (i
.op
[source
].regs
->reg_flags
& RegRex
)
2323 { /* If it's not 2 reg operands... */
2326 unsigned int fake_zero_displacement
= 0;
2327 unsigned int op
= ((i
.types
[0] & AnyMem
)
2329 : (i
.types
[1] & AnyMem
) ? 1 : 2);
2336 if (! i
.disp_operands
)
2337 fake_zero_displacement
= 1;
2340 /* Operand is just <disp> */
2341 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
2343 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
2344 i
.types
[op
] &= ~Disp
;
2345 i
.types
[op
] |= Disp16
;
2347 else if (flag_code
!= CODE_64BIT
)
2349 i
.rm
.regmem
= NO_BASE_REGISTER
;
2350 i
.types
[op
] &= ~Disp
;
2351 i
.types
[op
] |= Disp32
;
2355 /* 64bit mode overwrites the 32bit absolute addressing
2356 by RIP relative addressing and absolute addressing
2357 is encoded by one of the redundant SIB forms. */
2359 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2360 i
.sib
.base
= NO_BASE_REGISTER
;
2361 i
.sib
.index
= NO_INDEX_REGISTER
;
2362 i
.types
[op
] &= ~Disp
;
2363 i
.types
[op
] |= Disp32S
;
2366 else /* ! i.base_reg && i.index_reg */
2368 i
.sib
.index
= i
.index_reg
->reg_num
;
2369 i
.sib
.base
= NO_BASE_REGISTER
;
2370 i
.sib
.scale
= i
.log2_scale_factor
;
2371 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2372 i
.types
[op
] &= ~Disp
;
2373 if (flag_code
!= CODE_64BIT
)
2374 i
.types
[op
] |= Disp32
; /* Must be 32 bit */
2376 i
.types
[op
] |= Disp32S
;
2377 if (i
.index_reg
->reg_flags
& RegRex
)
2381 /* RIP addressing for 64bit mode. */
2382 else if (i
.base_reg
->reg_type
== BaseIndex
)
2384 i
.rm
.regmem
= NO_BASE_REGISTER
;
2385 i
.types
[op
] &= ~Disp
;
2386 i
.types
[op
] |= Disp32S
;
2387 i
.flags
[op
] = Operand_PCrel
;
2389 else if (i
.base_reg
->reg_type
& Reg16
)
2391 switch (i
.base_reg
->reg_num
)
2396 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
2397 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
2404 if ((i
.types
[op
] & Disp
) == 0)
2406 /* fake (%bp) into 0(%bp) */
2407 i
.types
[op
] |= Disp8
;
2408 fake_zero_displacement
= 1;
2411 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
2412 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
2414 default: /* (%si) -> 4 or (%di) -> 5 */
2415 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
2417 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
2419 else /* i.base_reg and 32/64 bit mode */
2421 if (flag_code
== CODE_64BIT
2422 && (i
.types
[op
] & Disp
))
2424 if (i
.types
[op
] & Disp8
)
2425 i
.types
[op
] = Disp8
| Disp32S
;
2427 i
.types
[op
] = Disp32S
;
2429 i
.rm
.regmem
= i
.base_reg
->reg_num
;
2430 if (i
.base_reg
->reg_flags
& RegRex
)
2432 i
.sib
.base
= i
.base_reg
->reg_num
;
2433 /* x86-64 ignores REX prefix bit here to avoid
2434 decoder complications. */
2435 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
2438 if (i
.disp_operands
== 0)
2440 fake_zero_displacement
= 1;
2441 i
.types
[op
] |= Disp8
;
2444 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
2448 i
.sib
.scale
= i
.log2_scale_factor
;
2451 /* <disp>(%esp) becomes two byte modrm
2452 with no index register. We've already
2453 stored the code for esp in i.rm.regmem
2454 ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. Any
2455 base register besides %esp will not use
2456 the extra modrm byte. */
2457 i
.sib
.index
= NO_INDEX_REGISTER
;
2458 #if ! SCALE1_WHEN_NO_INDEX
2459 /* Another case where we force the second
2461 if (i
.log2_scale_factor
)
2462 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2467 i
.sib
.index
= i
.index_reg
->reg_num
;
2468 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2469 if (i
.index_reg
->reg_flags
& RegRex
)
2472 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
2475 if (fake_zero_displacement
)
2477 /* Fakes a zero displacement assuming that i.types[op]
2478 holds the correct displacement size. */
2481 assert (i
.op
[op
].disps
== 0);
2482 exp
= &disp_expressions
[i
.disp_operands
++];
2483 i
.op
[op
].disps
= exp
;
2484 exp
->X_op
= O_constant
;
2485 exp
->X_add_number
= 0;
2486 exp
->X_add_symbol
= (symbolS
*) 0;
2487 exp
->X_op_symbol
= (symbolS
*) 0;
2491 /* Fill in i.rm.reg or i.rm.regmem field with register
2492 operand (if any) based on i.tm.extension_opcode.
2493 Again, we must be careful to make sure that
2494 segment/control/debug/test/MMX registers are coded
2495 into the i.rm.reg field. */
2500 & (Reg
| RegMMX
| RegXMM
2502 | Control
| Debug
| Test
))
2505 & (Reg
| RegMMX
| RegXMM
2507 | Control
| Debug
| Test
))
2510 /* If there is an extension opcode to put here, the
2511 register number must be put into the regmem field. */
2512 if (i
.tm
.extension_opcode
!= None
)
2514 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
2515 if (i
.op
[op
].regs
->reg_flags
& RegRex
)
2520 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
2521 if (i
.op
[op
].regs
->reg_flags
& RegRex
)
2525 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2
2526 we must set it to 3 to indicate this is a register
2527 operand in the regmem field. */
2528 if (!i
.mem_operands
)
2532 /* Fill in i.rm.reg field with extension opcode (if any). */
2533 if (i
.tm
.extension_opcode
!= None
)
2534 i
.rm
.reg
= i
.tm
.extension_opcode
;
2537 else if (i
.tm
.opcode_modifier
& (Seg2ShortForm
| Seg3ShortForm
))
2539 if (i
.tm
.base_opcode
== POP_SEG_SHORT
2540 && i
.op
[0].regs
->reg_num
== 1)
2542 as_bad (_("you can't `pop %%cs'"));
2545 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
2546 if (i
.op
[0].regs
->reg_flags
& RegRex
)
2549 else if ((i
.tm
.base_opcode
& ~(D
|W
)) == MOV_AX_DISP32
)
2553 else if ((i
.tm
.opcode_modifier
& IsString
) != 0)
2555 /* For the string instructions that allow a segment override
2556 on one of their operands, the default segment is ds. */
2560 /* If a segment was explicitly specified,
2561 and the specified segment is not the default,
2562 use an opcode prefix to select it.
2563 If we never figured out what the default segment is,
2564 then default_seg will be zero at this point,
2565 and the specified segment prefix will always be used. */
2566 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
2568 if (! add_prefix (i
.seg
[0]->seg_prefix
))
2572 else if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
2574 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2575 as_warn (_("translating to `%sp'"), i
.tm
.name
);
2579 /* Handle conversion of 'int $3' --> special int3 insn. */
2580 if (i
.tm
.base_opcode
== INT_OPCODE
&& i
.op
[0].imms
->X_add_number
== 3)
2582 i
.tm
.base_opcode
= INT3_OPCODE
;
2586 if ((i
.tm
.opcode_modifier
& (Jump
| JumpByte
| JumpDword
))
2587 && i
.op
[0].disps
->X_op
== O_constant
)
2589 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2590 the absolute address given by the constant. Since ix86 jumps and
2591 calls are pc relative, we need to generate a reloc. */
2592 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
2593 i
.op
[0].disps
->X_op
= O_symbol
;
2596 if (i
.tm
.opcode_modifier
& Rex64
)
2599 /* For 8bit registers we would need an empty rex prefix.
2600 Also in the case instruction is already having prefix,
2601 we need to convert old registers to new ones. */
2603 if (((i
.types
[0] & Reg8
) && (i
.op
[0].regs
->reg_flags
& RegRex64
))
2604 || ((i
.types
[1] & Reg8
) && (i
.op
[1].regs
->reg_flags
& RegRex64
))
2605 || ((i
.rex
.mode64
|| i
.rex
.extX
|| i
.rex
.extY
|| i
.rex
.extZ
|| i
.rex
.empty
)
2606 && ((i
.types
[0] & Reg8
) || (i
.types
[1] & Reg8
))))
2610 for (x
= 0; x
< 2; x
++)
2612 /* Look for 8bit operand that does use old registers. */
2613 if (i
.types
[x
] & Reg8
2614 && !(i
.op
[x
].regs
->reg_flags
& RegRex64
))
2616 /* In case it is "hi" register, give up. */
2617 if (i
.op
[x
].regs
->reg_num
> 3)
2618 as_bad (_("Can't encode registers '%%%s' in the instruction requiring REX prefix.\n"),
2619 i
.op
[x
].regs
->reg_name
);
2621 /* Otherwise it is equivalent to the extended register.
2622 Since the encoding don't change this is merely cosmetical
2623 cleanup for debug output. */
2625 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
2630 if (i
.rex
.mode64
|| i
.rex
.extX
|| i
.rex
.extY
|| i
.rex
.extZ
|| i
.rex
.empty
)
2632 | (i
.rex
.mode64
? 8 : 0)
2633 | (i
.rex
.extX
? 4 : 0)
2634 | (i
.rex
.extY
? 2 : 0)
2635 | (i
.rex
.extZ
? 1 : 0));
2637 /* We are ready to output the insn. */
2642 if (i
.tm
.opcode_modifier
& Jump
)
2649 if (flag_code
== CODE_16BIT
)
2653 if (i
.prefix
[DATA_PREFIX
])
2659 if (i
.prefix
[REX_PREFIX
])
2669 if (i
.prefixes
!= 0 && !intel_syntax
)
2670 as_warn (_("skipping prefixes on this instruction"));
2672 /* It's always a symbol; End frag & setup for relax.
2673 Make sure there is enough room in this frag for the largest
2674 instruction we may generate in md_convert_frag. This is 2
2675 bytes for the opcode and room for the prefix and largest
2677 frag_grow (prefix
+ 2 + size
);
2678 insn_size
+= prefix
+ 1;
2679 /* Prefix and 1 opcode byte go in fr_fix. */
2680 p
= frag_more (prefix
+ 1);
2681 if (i
.prefix
[DATA_PREFIX
])
2682 *p
++ = DATA_PREFIX_OPCODE
;
2683 if (i
.prefix
[REX_PREFIX
])
2684 *p
++ = i
.prefix
[REX_PREFIX
];
2685 *p
= i
.tm
.base_opcode
;
2686 /* 1 possible extra opcode + displacement go in var part.
2687 Pass reloc in fr_var. */
2688 frag_var (rs_machine_dependent
,
2691 ((unsigned char) *p
== JUMP_PC_RELATIVE
2692 ? ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
) | code16
2693 : ENCODE_RELAX_STATE (COND_JUMP
, SMALL
) | code16
),
2694 i
.op
[0].disps
->X_add_symbol
,
2695 i
.op
[0].disps
->X_add_number
,
2698 else if (i
.tm
.opcode_modifier
& (JumpByte
| JumpDword
))
2702 if (i
.tm
.opcode_modifier
& JumpByte
)
2704 /* This is a loop or jecxz type instruction. */
2706 if (i
.prefix
[ADDR_PREFIX
])
2709 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
2718 if (flag_code
== CODE_16BIT
)
2721 if (i
.prefix
[DATA_PREFIX
])
2724 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
2734 if (i
.prefix
[REX_PREFIX
])
2736 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
2741 if (i
.prefixes
!= 0 && !intel_syntax
)
2742 as_warn (_("skipping prefixes on this instruction"));
2744 if (fits_in_unsigned_byte (i
.tm
.base_opcode
))
2746 insn_size
+= 1 + size
;
2747 p
= frag_more (1 + size
);
2751 /* Opcode can be at most two bytes. */
2752 insn_size
+= 2 + size
;
2753 p
= frag_more (2 + size
);
2754 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
2756 *p
++ = i
.tm
.base_opcode
& 0xff;
2758 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
2759 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.disp_reloc
[0]));
2761 else if (i
.tm
.opcode_modifier
& JumpInterSegment
)
2768 if (flag_code
== CODE_16BIT
)
2772 if (i
.prefix
[DATA_PREFIX
])
2778 if (i
.prefix
[REX_PREFIX
])
2788 if (i
.prefixes
!= 0 && !intel_syntax
)
2789 as_warn (_("skipping prefixes on this instruction"));
2791 /* 1 opcode; 2 segment; offset */
2792 insn_size
+= prefix
+ 1 + 2 + size
;
2793 p
= frag_more (prefix
+ 1 + 2 + size
);
2795 if (i
.prefix
[DATA_PREFIX
])
2796 *p
++ = DATA_PREFIX_OPCODE
;
2798 if (i
.prefix
[REX_PREFIX
])
2799 *p
++ = i
.prefix
[REX_PREFIX
];
2801 *p
++ = i
.tm
.base_opcode
;
2802 if (i
.op
[1].imms
->X_op
== O_constant
)
2804 offsetT n
= i
.op
[1].imms
->X_add_number
;
2807 && !fits_in_unsigned_word (n
)
2808 && !fits_in_signed_word (n
))
2810 as_bad (_("16-bit jump out of range"));
2813 md_number_to_chars (p
, n
, size
);
2816 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
2817 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.disp_reloc
[0]));
2818 if (i
.op
[0].imms
->X_op
!= O_constant
)
2819 as_bad (_("can't handle non absolute segment in `%s'"),
2821 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
2825 /* Output normal instructions here. */
2828 /* The prefix bytes. */
2830 q
< i
.prefix
+ sizeof (i
.prefix
) / sizeof (i
.prefix
[0]);
2837 md_number_to_chars (p
, (valueT
) *q
, 1);
2841 /* Now the opcode; be careful about word order here! */
2842 if (fits_in_unsigned_byte (i
.tm
.base_opcode
))
2845 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
2847 else if (fits_in_unsigned_word (i
.tm
.base_opcode
))
2851 /* Put out high byte first: can't use md_number_to_chars! */
2852 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
2853 *p
= i
.tm
.base_opcode
& 0xff;
2856 { /* Opcode is either 3 or 4 bytes. */
2857 if (i
.tm
.base_opcode
& 0xff000000)
2861 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
2868 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
2869 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
2870 *p
= (i
.tm
.base_opcode
) & 0xff;
2873 /* Now the modrm byte and sib byte (if present). */
2874 if (i
.tm
.opcode_modifier
& Modrm
)
2878 md_number_to_chars (p
,
2879 (valueT
) (i
.rm
.regmem
<< 0
2883 /* If i.rm.regmem == ESP (4)
2884 && i.rm.mode != (Register mode)
2886 ==> need second modrm byte. */
2887 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
2889 && !(i
.base_reg
&& (i
.base_reg
->reg_type
& Reg16
) != 0))
2893 md_number_to_chars (p
,
2894 (valueT
) (i
.sib
.base
<< 0
2896 | i
.sib
.scale
<< 6),
2901 if (i
.disp_operands
)
2903 register unsigned int n
;
2905 for (n
= 0; n
< i
.operands
; n
++)
2907 if (i
.types
[n
] & Disp
)
2909 if (i
.op
[n
].disps
->X_op
== O_constant
)
2915 if (i
.types
[n
] & (Disp8
| Disp16
| Disp64
))
2918 if (i
.types
[n
] & Disp8
)
2920 if (i
.types
[n
] & Disp64
)
2923 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
2926 p
= frag_more (size
);
2927 md_number_to_chars (p
, val
, size
);
2933 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
2935 /* The PC relative address is computed relative
2936 to the instruction boundary, so in case immediate
2937 fields follows, we need to adjust the value. */
2938 if (pcrel
&& i
.imm_operands
)
2941 register unsigned int n1
;
2943 for (n1
= 0; n1
< i
.operands
; n1
++)
2944 if (i
.types
[n1
] & Imm
)
2946 if (i
.types
[n1
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
2949 if (i
.types
[n1
] & (Imm8
| Imm8S
))
2951 if (i
.types
[n1
] & Imm64
)
2956 /* We should find the immediate. */
2957 if (n1
== i
.operands
)
2959 i
.op
[n
].disps
->X_add_number
-= imm_size
;
2962 if (i
.types
[n
] & Disp32S
)
2965 if (i
.types
[n
] & (Disp16
| Disp64
))
2968 if (i
.types
[n
] & Disp64
)
2973 p
= frag_more (size
);
2974 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
2975 i
.op
[n
].disps
, pcrel
,
2976 reloc (size
, pcrel
, sign
, i
.disp_reloc
[n
]));
2982 /* Output immediate. */
2985 register unsigned int n
;
2987 for (n
= 0; n
< i
.operands
; n
++)
2989 if (i
.types
[n
] & Imm
)
2991 if (i
.op
[n
].imms
->X_op
== O_constant
)
2997 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3000 if (i
.types
[n
] & (Imm8
| Imm8S
))
3002 else if (i
.types
[n
] & Imm64
)
3005 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
3008 p
= frag_more (size
);
3009 md_number_to_chars (p
, val
, size
);
3013 /* Not absolute_section.
3014 Need a 32-bit fixup (don't support 8bit
3015 non-absolute imms). Try to support other
3017 #ifdef BFD_ASSEMBLER
3018 enum bfd_reloc_code_real reloc_type
;
3025 if ((i
.types
[n
] & (Imm32S
))
3026 && i
.suffix
== QWORD_MNEM_SUFFIX
)
3028 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3031 if (i
.types
[n
] & (Imm8
| Imm8S
))
3033 if (i
.types
[n
] & Imm64
)
3038 p
= frag_more (size
);
3039 reloc_type
= reloc (size
, 0, sign
, i
.disp_reloc
[0]);
3040 #ifdef BFD_ASSEMBLER
3041 if (reloc_type
== BFD_RELOC_32
3043 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
3044 && (i
.op
[n
].imms
->X_op
== O_symbol
3045 || (i
.op
[n
].imms
->X_op
== O_add
3046 && ((symbol_get_value_expression
3047 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
3050 /* We don't support dynamic linking on x86-64 yet. */
3051 if (flag_code
== CODE_64BIT
)
3053 reloc_type
= BFD_RELOC_386_GOTPC
;
3054 i
.op
[n
].imms
->X_add_number
+= 3;
3057 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3058 i
.op
[n
].imms
, 0, reloc_type
);
3065 dwarf2_emit_insn (insn_size
);
3072 #endif /* DEBUG386 */
3076 static int i386_immediate
PARAMS ((char *));
3079 i386_immediate (imm_start
)
3082 char *save_input_line_pointer
;
3086 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
3088 as_bad (_("only 1 or 2 immediate operands are allowed"));
3092 exp
= &im_expressions
[i
.imm_operands
++];
3093 i
.op
[this_operand
].imms
= exp
;
3095 if (is_space_char (*imm_start
))
3098 save_input_line_pointer
= input_line_pointer
;
3099 input_line_pointer
= imm_start
;
3103 /* We can have operands of the form
3104 <symbol>@GOTOFF+<nnn>
3105 Take the easy way out here and copy everything
3106 into a temporary buffer... */
3109 cp
= strchr (input_line_pointer
, '@');
3116 /* GOT relocations are not supported in 16 bit mode. */
3117 if (flag_code
== CODE_16BIT
)
3118 as_bad (_("GOT relocations not supported in 16 bit mode"));
3120 if (GOT_symbol
== NULL
)
3121 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
3123 if (strncmp (cp
+ 1, "PLT", 3) == 0)
3125 if (flag_code
== CODE_64BIT
)
3126 i
.disp_reloc
[this_operand
] = BFD_RELOC_X86_64_PLT32
;
3128 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_PLT32
;
3131 else if (strncmp (cp
+ 1, "GOTOFF", 6) == 0)
3133 if (flag_code
== CODE_64BIT
)
3134 as_bad ("GOTOFF relocations are unsupported in 64bit mode.");
3135 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_GOTOFF
;
3138 else if (strncmp (cp
+ 1, "GOT", 3) == 0)
3140 if (flag_code
== CODE_64BIT
)
3141 i
.disp_reloc
[this_operand
] = BFD_RELOC_X86_64_GOT32
;
3143 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_GOT32
;
3146 else if (strncmp (cp
+ 1, "GOTPCREL", 3) == 0)
3148 if (flag_code
== CODE_64BIT
)
3149 i
.disp_reloc
[this_operand
] = BFD_RELOC_X86_64_GOTPCREL
;
3151 as_bad ("GOTPCREL relocations are supported only in 64bit mode.");
3155 as_bad (_("bad reloc specifier in expression"));
3157 /* Replace the relocation token with ' ', so that errors like
3158 foo@GOTOFF1 will be detected. */
3159 first
= cp
- input_line_pointer
;
3160 tmpbuf
= (char *) alloca (strlen (input_line_pointer
));
3161 memcpy (tmpbuf
, input_line_pointer
, first
);
3162 tmpbuf
[first
] = ' ';
3163 strcpy (tmpbuf
+ first
+ 1, cp
+ 1 + len
);
3164 input_line_pointer
= tmpbuf
;
3169 exp_seg
= expression (exp
);
3172 if (*input_line_pointer
)
3173 as_bad (_("ignoring junk `%s' after expression"), input_line_pointer
);
3175 input_line_pointer
= save_input_line_pointer
;
3177 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
3179 /* Missing or bad expr becomes absolute 0. */
3180 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
3182 exp
->X_op
= O_constant
;
3183 exp
->X_add_number
= 0;
3184 exp
->X_add_symbol
= (symbolS
*) 0;
3185 exp
->X_op_symbol
= (symbolS
*) 0;
3187 else if (exp
->X_op
== O_constant
)
3189 /* Size it properly later. */
3190 i
.types
[this_operand
] |= Imm64
;
3191 /* If BFD64, sign extend val. */
3192 if (!use_rela_relocations
)
3193 if ((exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
3194 exp
->X_add_number
= (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
3196 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3198 #ifdef BFD_ASSEMBLER
3199 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
3201 && exp_seg
!= text_section
3202 && exp_seg
!= data_section
3203 && exp_seg
!= bss_section
3204 && exp_seg
!= undefined_section
3205 #ifdef BFD_ASSEMBLER
3206 && !bfd_is_com_section (exp_seg
)
3210 #ifdef BFD_ASSEMBLER
3211 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
3213 as_bad (_("unimplemented segment type %d in operand"), exp_seg
);
3220 /* This is an address. The size of the address will be
3221 determined later, depending on destination register,
3222 suffix, or the default for the section. */
3223 i
.types
[this_operand
] |= Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
;
3229 static int i386_scale
PARAMS ((char *));
3235 if (!isdigit (*scale
))
3242 i
.log2_scale_factor
= 0;
3245 i
.log2_scale_factor
= 1;
3248 i
.log2_scale_factor
= 2;
3251 i
.log2_scale_factor
= 3;
3255 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
3259 if (i
.log2_scale_factor
!= 0 && ! i
.index_reg
)
3261 as_warn (_("scale factor of %d without an index register"),
3262 1 << i
.log2_scale_factor
);
3263 #if SCALE1_WHEN_NO_INDEX
3264 i
.log2_scale_factor
= 0;
3270 static int i386_displacement
PARAMS ((char *, char *));
3273 i386_displacement (disp_start
, disp_end
)
3277 register expressionS
*exp
;
3279 char *save_input_line_pointer
;
3280 int bigdisp
= Disp32
;
3282 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
3284 if (flag_code
== CODE_64BIT
)
3286 i
.types
[this_operand
] |= bigdisp
;
3288 exp
= &disp_expressions
[i
.disp_operands
];
3289 i
.op
[this_operand
].disps
= exp
;
3291 save_input_line_pointer
= input_line_pointer
;
3292 input_line_pointer
= disp_start
;
3293 END_STRING_AND_SAVE (disp_end
);
3295 #ifndef GCC_ASM_O_HACK
3296 #define GCC_ASM_O_HACK 0
3299 END_STRING_AND_SAVE (disp_end
+ 1);
3300 if ((i
.types
[this_operand
] & BaseIndex
) != 0
3301 && displacement_string_end
[-1] == '+')
3303 /* This hack is to avoid a warning when using the "o"
3304 constraint within gcc asm statements.
3307 #define _set_tssldt_desc(n,addr,limit,type) \
3308 __asm__ __volatile__ ( \
3310 "movw %w1,2+%0\n\t" \
3312 "movb %b1,4+%0\n\t" \
3313 "movb %4,5+%0\n\t" \
3314 "movb $0,6+%0\n\t" \
3315 "movb %h1,7+%0\n\t" \
3317 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
3319 This works great except that the output assembler ends
3320 up looking a bit weird if it turns out that there is
3321 no offset. You end up producing code that looks like:
3334 So here we provide the missing zero. */
3336 *displacement_string_end
= '0';
3341 /* We can have operands of the form
3342 <symbol>@GOTOFF+<nnn>
3343 Take the easy way out here and copy everything
3344 into a temporary buffer... */
3347 cp
= strchr (input_line_pointer
, '@');
3354 /* GOT relocations are not supported in 16 bit mode. */
3355 if (flag_code
== CODE_16BIT
)
3356 as_bad (_("GOT relocations not supported in 16 bit mode"));
3358 if (GOT_symbol
== NULL
)
3359 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
3361 if (strncmp (cp
+ 1, "PLT", 3) == 0)
3363 if (flag_code
== CODE_64BIT
)
3364 i
.disp_reloc
[this_operand
] = BFD_RELOC_X86_64_PLT32
;
3366 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_PLT32
;
3369 else if (strncmp (cp
+ 1, "GOTOFF", 6) == 0)
3371 if (flag_code
== CODE_64BIT
)
3372 as_bad ("GOTOFF relocation is not supported in 64bit mode.");
3373 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_GOTOFF
;
3376 else if (strncmp (cp
+ 1, "GOT", 3) == 0)
3378 if (flag_code
== CODE_64BIT
)
3379 i
.disp_reloc
[this_operand
] = BFD_RELOC_X86_64_GOT32
;
3381 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_GOT32
;
3384 else if (strncmp (cp
+ 1, "GOTPCREL", 3) == 0)
3386 if (flag_code
!= CODE_64BIT
)
3387 as_bad ("GOTPCREL relocation is supported only in 64bit mode.");
3388 i
.disp_reloc
[this_operand
] = BFD_RELOC_X86_64_GOTPCREL
;
3392 as_bad (_("bad reloc specifier in expression"));
3394 /* Replace the relocation token with ' ', so that errors like
3395 foo@GOTOFF1 will be detected. */
3396 first
= cp
- input_line_pointer
;
3397 tmpbuf
= (char *) alloca (strlen (input_line_pointer
));
3398 memcpy (tmpbuf
, input_line_pointer
, first
);
3399 tmpbuf
[first
] = ' ';
3400 strcpy (tmpbuf
+ first
+ 1, cp
+ 1 + len
);
3401 input_line_pointer
= tmpbuf
;
3406 exp_seg
= expression (exp
);
3408 #ifdef BFD_ASSEMBLER
3409 /* We do this to make sure that the section symbol is in
3410 the symbol table. We will ultimately change the relocation
3411 to be relative to the beginning of the section. */
3412 if (i
.disp_reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
3413 || i
.disp_reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
3415 if (S_IS_LOCAL(exp
->X_add_symbol
)
3416 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
3417 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
3418 assert (exp
->X_op
== O_symbol
);
3419 exp
->X_op
= O_subtract
;
3420 exp
->X_op_symbol
= GOT_symbol
;
3421 i
.disp_reloc
[this_operand
] = BFD_RELOC_32
;
3426 if (*input_line_pointer
)
3427 as_bad (_("ignoring junk `%s' after expression"),
3428 input_line_pointer
);
3430 RESTORE_END_STRING (disp_end
+ 1);
3432 RESTORE_END_STRING (disp_end
);
3433 input_line_pointer
= save_input_line_pointer
;
3435 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
3437 /* Missing or bad expr becomes absolute 0. */
3438 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
3440 exp
->X_op
= O_constant
;
3441 exp
->X_add_number
= 0;
3442 exp
->X_add_symbol
= (symbolS
*) 0;
3443 exp
->X_op_symbol
= (symbolS
*) 0;
3446 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3447 if (exp
->X_op
!= O_constant
3448 #ifdef BFD_ASSEMBLER
3449 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
3451 && exp_seg
!= text_section
3452 && exp_seg
!= data_section
3453 && exp_seg
!= bss_section
3454 && exp_seg
!= undefined_section
)
3456 #ifdef BFD_ASSEMBLER
3457 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
3459 as_bad (_("unimplemented segment type %d in operand"), exp_seg
);
3464 else if (flag_code
== CODE_64BIT
)
3465 i
.types
[this_operand
] |= Disp32S
| Disp32
;
3469 static int i386_index_check
PARAMS((const char *));
3471 /* Make sure the memory operand we've been dealt is valid.
3472 Return 1 on success, 0 on a failure. */
3475 i386_index_check (operand_string
)
3476 const char *operand_string
;
3479 #if INFER_ADDR_PREFIX
3485 if (flag_code
== CODE_64BIT
)
3489 && ((i
.base_reg
->reg_type
& Reg64
) == 0)
3490 && (i
.base_reg
->reg_type
!= BaseIndex
3493 && ((i
.index_reg
->reg_type
& (Reg64
|BaseIndex
))
3494 != (Reg64
|BaseIndex
))))
3499 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
3503 && ((i
.base_reg
->reg_type
& (Reg16
|BaseIndex
|RegRex
))
3504 != (Reg16
|BaseIndex
)))
3506 && (((i
.index_reg
->reg_type
& (Reg16
|BaseIndex
))
3507 != (Reg16
|BaseIndex
))
3509 && i
.base_reg
->reg_num
< 6
3510 && i
.index_reg
->reg_num
>= 6
3511 && i
.log2_scale_factor
== 0))))
3518 && (i
.base_reg
->reg_type
& (Reg32
| RegRex
)) != Reg32
)
3520 && ((i
.index_reg
->reg_type
& (Reg32
|BaseIndex
|RegRex
))
3521 != (Reg32
|BaseIndex
))))
3527 #if INFER_ADDR_PREFIX
3528 if (flag_code
!= CODE_64BIT
3529 && i
.prefix
[ADDR_PREFIX
] == 0 && stackop_size
!= '\0')
3531 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
3533 /* Change the size of any displacement too. At most one of
3534 Disp16 or Disp32 is set.
3535 FIXME. There doesn't seem to be any real need for separate
3536 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
3537 Removing them would probably clean up the code quite a lot. */
3538 if (i
.types
[this_operand
] & (Disp16
|Disp32
))
3539 i
.types
[this_operand
] ^= (Disp16
|Disp32
);
3544 as_bad (_("`%s' is not a valid base/index expression"),
3548 as_bad (_("`%s' is not a valid %s bit base/index expression"),
3550 flag_code_names
[flag_code
]);
3556 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
3560 i386_operand (operand_string
)
3561 char *operand_string
;
3565 char *op_string
= operand_string
;
3567 if (is_space_char (*op_string
))
3570 /* We check for an absolute prefix (differentiating,
3571 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
3572 if (*op_string
== ABSOLUTE_PREFIX
)
3575 if (is_space_char (*op_string
))
3577 i
.types
[this_operand
] |= JumpAbsolute
;
3580 /* Check if operand is a register. */
3581 if ((*op_string
== REGISTER_PREFIX
|| allow_naked_reg
)
3582 && (r
= parse_register (op_string
, &end_op
)) != NULL
)
3584 /* Check for a segment override by searching for ':' after a
3585 segment register. */
3587 if (is_space_char (*op_string
))
3589 if (*op_string
== ':' && (r
->reg_type
& (SReg2
| SReg3
)))
3594 i
.seg
[i
.mem_operands
] = &es
;
3597 i
.seg
[i
.mem_operands
] = &cs
;
3600 i
.seg
[i
.mem_operands
] = &ss
;
3603 i
.seg
[i
.mem_operands
] = &ds
;
3606 i
.seg
[i
.mem_operands
] = &fs
;
3609 i
.seg
[i
.mem_operands
] = &gs
;
3613 /* Skip the ':' and whitespace. */
3615 if (is_space_char (*op_string
))
3618 if (!is_digit_char (*op_string
)
3619 && !is_identifier_char (*op_string
)
3620 && *op_string
!= '('
3621 && *op_string
!= ABSOLUTE_PREFIX
)
3623 as_bad (_("bad memory operand `%s'"), op_string
);
3626 /* Handle case of %es:*foo. */
3627 if (*op_string
== ABSOLUTE_PREFIX
)
3630 if (is_space_char (*op_string
))
3632 i
.types
[this_operand
] |= JumpAbsolute
;
3634 goto do_memory_reference
;
3638 as_bad (_("junk `%s' after register"), op_string
);
3641 i
.types
[this_operand
] |= r
->reg_type
& ~BaseIndex
;
3642 i
.op
[this_operand
].regs
= r
;
3645 else if (*op_string
== REGISTER_PREFIX
)
3647 as_bad (_("bad register name `%s'"), op_string
);
3650 else if (*op_string
== IMMEDIATE_PREFIX
)
3653 if (i
.types
[this_operand
] & JumpAbsolute
)
3655 as_bad (_("immediate operand illegal with absolute jump"));
3658 if (!i386_immediate (op_string
))
3661 else if (is_digit_char (*op_string
)
3662 || is_identifier_char (*op_string
)
3663 || *op_string
== '(' )
3665 /* This is a memory reference of some sort. */
3668 /* Start and end of displacement string expression (if found). */
3669 char *displacement_string_start
;
3670 char *displacement_string_end
;
3672 do_memory_reference
:
3673 if ((i
.mem_operands
== 1
3674 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
3675 || i
.mem_operands
== 2)
3677 as_bad (_("too many memory references for `%s'"),
3678 current_templates
->start
->name
);
3682 /* Check for base index form. We detect the base index form by
3683 looking for an ')' at the end of the operand, searching
3684 for the '(' matching it, and finding a REGISTER_PREFIX or ','
3686 base_string
= op_string
+ strlen (op_string
);
3689 if (is_space_char (*base_string
))
3692 /* If we only have a displacement, set-up for it to be parsed later. */
3693 displacement_string_start
= op_string
;
3694 displacement_string_end
= base_string
+ 1;
3696 if (*base_string
== ')')
3699 unsigned int parens_balanced
= 1;
3700 /* We've already checked that the number of left & right ()'s are
3701 equal, so this loop will not be infinite. */
3705 if (*base_string
== ')')
3707 if (*base_string
== '(')
3710 while (parens_balanced
);
3712 temp_string
= base_string
;
3714 /* Skip past '(' and whitespace. */
3716 if (is_space_char (*base_string
))
3719 if (*base_string
== ','
3720 || ((*base_string
== REGISTER_PREFIX
|| allow_naked_reg
)
3721 && (i
.base_reg
= parse_register (base_string
, &end_op
)) != NULL
))
3723 displacement_string_end
= temp_string
;
3725 i
.types
[this_operand
] |= BaseIndex
;
3729 base_string
= end_op
;
3730 if (is_space_char (*base_string
))
3734 /* There may be an index reg or scale factor here. */
3735 if (*base_string
== ',')
3738 if (is_space_char (*base_string
))
3741 if ((*base_string
== REGISTER_PREFIX
|| allow_naked_reg
)
3742 && (i
.index_reg
= parse_register (base_string
, &end_op
)) != NULL
)
3744 base_string
= end_op
;
3745 if (is_space_char (*base_string
))
3747 if (*base_string
== ',')
3750 if (is_space_char (*base_string
))
3753 else if (*base_string
!= ')' )
3755 as_bad (_("expecting `,' or `)' after index register in `%s'"),
3760 else if (*base_string
== REGISTER_PREFIX
)
3762 as_bad (_("bad register name `%s'"), base_string
);
3766 /* Check for scale factor. */
3767 if (isdigit ((unsigned char) *base_string
))
3769 if (!i386_scale (base_string
))
3773 if (is_space_char (*base_string
))
3775 if (*base_string
!= ')')
3777 as_bad (_("expecting `)' after scale factor in `%s'"),
3782 else if (!i
.index_reg
)
3784 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
3789 else if (*base_string
!= ')')
3791 as_bad (_("expecting `,' or `)' after base register in `%s'"),
3796 else if (*base_string
== REGISTER_PREFIX
)
3798 as_bad (_("bad register name `%s'"), base_string
);
3803 /* If there's an expression beginning the operand, parse it,
3804 assuming displacement_string_start and
3805 displacement_string_end are meaningful. */
3806 if (displacement_string_start
!= displacement_string_end
)
3808 if (!i386_displacement (displacement_string_start
,
3809 displacement_string_end
))
3813 /* Special case for (%dx) while doing input/output op. */
3815 && i
.base_reg
->reg_type
== (Reg16
| InOutPortReg
)
3817 && i
.log2_scale_factor
== 0
3818 && i
.seg
[i
.mem_operands
] == 0
3819 && (i
.types
[this_operand
] & Disp
) == 0)
3821 i
.types
[this_operand
] = InOutPortReg
;
3825 if (i386_index_check (operand_string
) == 0)
3831 /* It's not a memory operand; argh! */
3832 as_bad (_("invalid char %s beginning operand %d `%s'"),
3833 output_invalid (*op_string
),
3838 return 1; /* Normal return. */
3841 /* md_estimate_size_before_relax()
3843 Called just before relax() for rs_machine_dependent frags. The x86
3844 assembler uses these frags to handle variable size jump
3847 Any symbol that is now undefined will not become defined.
3848 Return the correct fr_subtype in the frag.
3849 Return the initial "guess for variable size of frag" to caller.
3850 The guess is actually the growth beyond the fixed part. Whatever
3851 we do to grow the fixed or variable part contributes to our
3855 md_estimate_size_before_relax (fragP
, segment
)
3856 register fragS
*fragP
;
3857 register segT segment
;
3859 /* We've already got fragP->fr_subtype right; all we have to do is
3860 check for un-relaxable symbols. On an ELF system, we can't relax
3861 an externally visible symbol, because it may be overridden by a
3863 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
3864 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3865 || S_IS_EXTERNAL (fragP
->fr_symbol
)
3866 || S_IS_WEAK (fragP
->fr_symbol
)
3870 /* Symbol is undefined in this segment, or we need to keep a
3871 reloc so that weak symbols can be overridden. */
3872 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
3873 #ifdef BFD_ASSEMBLER
3874 enum bfd_reloc_code_real reloc_type
;
3878 unsigned char *opcode
;
3881 if (fragP
->fr_var
!= NO_RELOC
)
3882 reloc_type
= fragP
->fr_var
;
3884 reloc_type
= BFD_RELOC_16_PCREL
;
3886 reloc_type
= BFD_RELOC_32_PCREL
;
3888 old_fr_fix
= fragP
->fr_fix
;
3889 opcode
= (unsigned char *) fragP
->fr_opcode
;
3893 case JUMP_PC_RELATIVE
:
3894 /* Make jmp (0xeb) a dword displacement jump. */
3896 fragP
->fr_fix
+= size
;
3897 fix_new (fragP
, old_fr_fix
, size
,
3899 fragP
->fr_offset
, 1,
3904 /* This changes the byte-displacement jump 0x7N
3905 to the dword-displacement jump 0x0f,0x8N. */
3906 opcode
[1] = opcode
[0] + 0x10;
3907 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
3908 /* We've added an opcode byte. */
3909 fragP
->fr_fix
+= 1 + size
;
3910 fix_new (fragP
, old_fr_fix
+ 1, size
,
3912 fragP
->fr_offset
, 1,
3917 return fragP
->fr_fix
- old_fr_fix
;
3919 /* Guess a short jump. */
3923 /* Called after relax() is finished.
3925 In: Address of frag.
3926 fr_type == rs_machine_dependent.
3927 fr_subtype is what the address relaxed to.
3929 Out: Any fixSs and constants are set up.
3930 Caller will turn frag into a ".space 0". */
3932 #ifndef BFD_ASSEMBLER
3934 md_convert_frag (headers
, sec
, fragP
)
3935 object_headers
*headers ATTRIBUTE_UNUSED
;
3936 segT sec ATTRIBUTE_UNUSED
;
3937 register fragS
*fragP
;
3940 md_convert_frag (abfd
, sec
, fragP
)
3941 bfd
*abfd ATTRIBUTE_UNUSED
;
3942 segT sec ATTRIBUTE_UNUSED
;
3943 register fragS
*fragP
;
3946 register unsigned char *opcode
;
3947 unsigned char *where_to_put_displacement
= NULL
;
3948 offsetT target_address
;
3949 offsetT opcode_address
;
3950 unsigned int extension
= 0;
3951 offsetT displacement_from_opcode_start
;
3953 opcode
= (unsigned char *) fragP
->fr_opcode
;
3955 /* Address we want to reach in file space. */
3956 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
3957 #ifdef BFD_ASSEMBLER
3958 /* Not needed otherwise? */
3959 target_address
+= symbol_get_frag (fragP
->fr_symbol
)->fr_address
;
3962 /* Address opcode resides at in file space. */
3963 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
3965 /* Displacement from opcode start to fill into instruction. */
3966 displacement_from_opcode_start
= target_address
- opcode_address
;
3968 switch (fragP
->fr_subtype
)
3970 case ENCODE_RELAX_STATE (COND_JUMP
, SMALL
):
3971 case ENCODE_RELAX_STATE (COND_JUMP
, SMALL16
):
3972 case ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
):
3973 case ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL16
):
3974 /* Don't have to change opcode. */
3975 extension
= 1; /* 1 opcode + 1 displacement */
3976 where_to_put_displacement
= &opcode
[1];
3979 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
3980 extension
= 5; /* 2 opcode + 4 displacement */
3981 opcode
[1] = opcode
[0] + 0x10;
3982 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
3983 where_to_put_displacement
= &opcode
[2];
3986 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
3987 extension
= 4; /* 1 opcode + 4 displacement */
3989 where_to_put_displacement
= &opcode
[1];
3992 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
3993 extension
= 3; /* 2 opcode + 2 displacement */
3994 opcode
[1] = opcode
[0] + 0x10;
3995 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
3996 where_to_put_displacement
= &opcode
[2];
3999 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
4000 extension
= 2; /* 1 opcode + 2 displacement */
4002 where_to_put_displacement
= &opcode
[1];
4006 BAD_CASE (fragP
->fr_subtype
);
4009 /* Now put displacement after opcode. */
4010 md_number_to_chars ((char *) where_to_put_displacement
,
4011 (valueT
) (displacement_from_opcode_start
- extension
),
4012 SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
4013 fragP
->fr_fix
+= extension
;
4016 /* Size of byte displacement jmp. */
4017 int md_short_jump_size
= 2;
4019 /* Size of dword displacement jmp. */
4020 int md_long_jump_size
= 5;
4022 /* Size of relocation record. */
4023 const int md_reloc_size
= 8;
4026 md_create_short_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
4028 addressT from_addr
, to_addr
;
4029 fragS
*frag ATTRIBUTE_UNUSED
;
4030 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
4034 offset
= to_addr
- (from_addr
+ 2);
4035 /* Opcode for byte-disp jump. */
4036 md_number_to_chars (ptr
, (valueT
) 0xeb, 1);
4037 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 1);
4041 md_create_long_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
4043 addressT from_addr
, to_addr
;
4044 fragS
*frag ATTRIBUTE_UNUSED
;
4045 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
4049 offset
= to_addr
- (from_addr
+ 5);
4050 md_number_to_chars (ptr
, (valueT
) 0xe9, 1);
4051 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 4);
4054 /* Apply a fixup (fixS) to segment data, once it has been determined
4055 by our caller that we have all the info we need to fix it up.
4057 On the 386, immediates, displacements, and data pointers are all in
4058 the same (little-endian) format, so we don't need to care about which
4062 md_apply_fix3 (fixP
, valp
, seg
)
4063 /* The fix we're to put in. */
4066 /* Pointer to the value of the bits. */
4069 /* Segment fix is from. */
4070 segT seg ATTRIBUTE_UNUSED
;
4072 register char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
4073 valueT value
= *valp
;
4075 #if defined (BFD_ASSEMBLER) && !defined (TE_Mach)
4078 switch (fixP
->fx_r_type
)
4084 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
4087 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
4090 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
4095 /* This is a hack. There should be a better way to handle this.
4096 This covers for the fact that bfd_install_relocation will
4097 subtract the current location (for partial_inplace, PC relative
4098 relocations); see more below. */
4099 if ((fixP
->fx_r_type
== BFD_RELOC_32_PCREL
4100 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
4101 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
4105 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4107 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
4110 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4112 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4113 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
4115 segT fseg
= S_GET_SEGMENT (fixP
->fx_addsy
);
4118 || (symbol_section_p (fixP
->fx_addsy
)
4119 && fseg
!= absolute_section
))
4120 && ! S_IS_EXTERNAL (fixP
->fx_addsy
)
4121 && ! S_IS_WEAK (fixP
->fx_addsy
)
4122 && S_IS_DEFINED (fixP
->fx_addsy
)
4123 && ! S_IS_COMMON (fixP
->fx_addsy
))
4125 /* Yes, we add the values in twice. This is because
4126 bfd_perform_relocation subtracts them out again. I think
4127 bfd_perform_relocation is broken, but I don't dare change
4129 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4133 #if defined (OBJ_COFF) && defined (TE_PE)
4134 /* For some reason, the PE format does not store a section
4135 address offset for a PC relative symbol. */
4136 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
4137 value
+= md_pcrel_from (fixP
);
4141 /* Fix a few things - the dynamic linker expects certain values here,
4142 and we must not dissappoint it. */
4143 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4144 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4146 switch (fixP
->fx_r_type
)
4148 case BFD_RELOC_386_PLT32
:
4149 case BFD_RELOC_X86_64_PLT32
:
4150 /* Make the jump instruction point to the address of the operand. At
4151 runtime we merely add the offset to the actual PLT entry. */
4154 case BFD_RELOC_386_GOTPC
:
4156 /* This is tough to explain. We end up with this one if we have
4157 * operands that look like "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal
4158 * here is to obtain the absolute address of the GOT, and it is strongly
4159 * preferable from a performance point of view to avoid using a runtime
4160 * relocation for this. The actual sequence of instructions often look
4166 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
4168 * The call and pop essentially return the absolute address of
4169 * the label .L66 and store it in %ebx. The linker itself will
4170 * ultimately change the first operand of the addl so that %ebx points to
4171 * the GOT, but to keep things simple, the .o file must have this operand
4172 * set so that it generates not the absolute address of .L66, but the
4173 * absolute address of itself. This allows the linker itself simply
4174 * treat a GOTPC relocation as asking for a pcrel offset to the GOT to be
4175 * added in, and the addend of the relocation is stored in the operand
4176 * field for the instruction itself.
4178 * Our job here is to fix the operand so that it would add the correct
4179 * offset so that %ebx would point to itself. The thing that is tricky is
4180 * that .-.L66 will point to the beginning of the instruction, so we need
4181 * to further modify the operand so that it will point to itself.
4182 * There are other cases where you have something like:
4184 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
4186 * and here no correction would be required. Internally in the assembler
4187 * we treat operands of this form as not being pcrel since the '.' is
4188 * explicitly mentioned, and I wonder whether it would simplify matters
4189 * to do it this way. Who knows. In earlier versions of the PIC patches,
4190 * the pcrel_adjust field was used to store the correction, but since the
4191 * expression is not pcrel, I felt it would be confusing to do it this
4196 case BFD_RELOC_386_GOT32
:
4197 case BFD_RELOC_X86_64_GOT32
:
4198 value
= 0; /* Fully resolved at runtime. No addend. */
4200 case BFD_RELOC_386_GOTOFF
:
4201 case BFD_RELOC_X86_64_GOTPCREL
:
4204 case BFD_RELOC_VTABLE_INHERIT
:
4205 case BFD_RELOC_VTABLE_ENTRY
:
4212 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
4214 #endif /* defined (BFD_ASSEMBLER) && !defined (TE_Mach) */
4216 #ifndef BFD_ASSEMBLER
4217 md_number_to_chars (p
, value
, fixP
->fx_size
);
4219 /* Are we finished with this relocation now? */
4220 if (fixP
->fx_addsy
== 0 && fixP
->fx_pcrel
== 0)
4222 else if (use_rela_relocations
)
4224 fixP
->fx_no_overflow
= 1;
4227 md_number_to_chars (p
, value
, fixP
->fx_size
);
4233 #define MAX_LITTLENUMS 6
4235 /* Turn the string pointed to by litP into a floating point constant
4236 of type TYPE, and emit the appropriate bytes. The number of
4237 LITTLENUMS emitted is stored in *SIZEP. An error message is
4238 returned, or NULL on OK. */
4241 md_atof (type
, litP
, sizeP
)
4247 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4248 LITTLENUM_TYPE
*wordP
;
4270 return _("Bad call to md_atof ()");
4272 t
= atof_ieee (input_line_pointer
, type
, words
);
4274 input_line_pointer
= t
;
4276 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
4277 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
4278 the bigendian 386. */
4279 for (wordP
= words
+ prec
- 1; prec
--;)
4281 md_number_to_chars (litP
, (valueT
) (*wordP
--), sizeof (LITTLENUM_TYPE
));
4282 litP
+= sizeof (LITTLENUM_TYPE
);
4287 char output_invalid_buf
[8];
4294 sprintf (output_invalid_buf
, "'%c'", c
);
4296 sprintf (output_invalid_buf
, "(0x%x)", (unsigned) c
);
4297 return output_invalid_buf
;
4300 /* REG_STRING starts *before* REGISTER_PREFIX. */
4302 static const reg_entry
*
4303 parse_register (reg_string
, end_op
)
4307 char *s
= reg_string
;
4309 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
4312 /* Skip possible REGISTER_PREFIX and possible whitespace. */
4313 if (*s
== REGISTER_PREFIX
)
4316 if (is_space_char (*s
))
4320 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
4322 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
4323 return (const reg_entry
*) NULL
;
4327 /* For naked regs, make sure that we are not dealing with an identifier.
4328 This prevents confusing an identifier like `eax_var' with register
4330 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
4331 return (const reg_entry
*) NULL
;
4335 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
4337 /* Handle floating point regs, allowing spaces in the (i) part. */
4338 if (r
== i386_regtab
/* %st is first entry of table */)
4340 if (is_space_char (*s
))
4345 if (is_space_char (*s
))
4347 if (*s
>= '0' && *s
<= '7')
4349 r
= &i386_float_regtab
[*s
- '0'];
4351 if (is_space_char (*s
))
4359 /* We have "%st(" then garbage. */
4360 return (const reg_entry
*) NULL
;
4367 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4368 const char *md_shortopts
= "kVQ:sq";
4370 const char *md_shortopts
= "q";
4372 struct option md_longopts
[] = {
4373 #define OPTION_32 (OPTION_MD_BASE + 0)
4374 {"32", no_argument
, NULL
, OPTION_32
},
4375 #define OPTION_64 (OPTION_MD_BASE + 1)
4376 {"64", no_argument
, NULL
, OPTION_64
},
4377 {NULL
, no_argument
, NULL
, 0}
4379 size_t md_longopts_size
= sizeof (md_longopts
);
4382 md_parse_option (c
, arg
)
4384 char *arg ATTRIBUTE_UNUSED
;
4392 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4393 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
4394 should be emitted or not. FIXME: Not implemented. */
4398 /* -V: SVR4 argument to print version ID. */
4400 print_version_id ();
4403 /* -k: Ignore for FreeBSD compatibility. */
4408 /* -s: On i386 Solaris, this tells the native assembler to use
4409 .stab instead of .stab.excl. We always use .stab anyhow. */
4416 const char **list
, **l
;
4418 default_arch
= c
== OPTION_32
? "i386" : "x86_64";
4419 list
= bfd_target_list ();
4420 for (l
= list
; *l
!= NULL
; l
++)
4424 if (strcmp (*l
, "elf32-i386") == 0)
4429 if (strcmp (*l
, "elf64-x86-64") == 0)
4434 as_fatal (_("No compiled in support for %d bit object file format"),
4435 c
== OPTION_32
? 32 : 64);
4448 md_show_usage (stream
)
4451 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4452 fprintf (stream
, _("\
4454 -V print assembler version number\n\
4456 -q quieten some warnings\n\
4459 fprintf (stream
, _("\
4460 -q quieten some warnings\n"));
4464 #ifdef BFD_ASSEMBLER
4465 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
4466 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
4468 /* Pick the target format to use. */
4471 i386_target_format ()
4473 if (!strcmp (default_arch
, "x86_64"))
4474 set_code_flag (CODE_64BIT
);
4475 else if (!strcmp (default_arch
, "i386"))
4476 set_code_flag (CODE_32BIT
);
4478 as_fatal (_("Unknown architecture"));
4479 switch (OUTPUT_FLAVOR
)
4481 #ifdef OBJ_MAYBE_AOUT
4482 case bfd_target_aout_flavour
:
4483 return AOUT_TARGET_FORMAT
;
4485 #ifdef OBJ_MAYBE_COFF
4486 case bfd_target_coff_flavour
:
4489 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
4490 case bfd_target_elf_flavour
:
4492 if (flag_code
== CODE_64BIT
)
4493 use_rela_relocations
= 1;
4494 return flag_code
== CODE_64BIT
? "elf64-x86-64" : "elf32-i386";
4503 #endif /* OBJ_MAYBE_ more than one */
4504 #endif /* BFD_ASSEMBLER */
4507 md_undefined_symbol (name
)
4510 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
4511 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
4512 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
4513 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
4517 if (symbol_find (name
))
4518 as_bad (_("GOT already in symbol table"));
4519 GOT_symbol
= symbol_new (name
, undefined_section
,
4520 (valueT
) 0, &zero_address_frag
);
4527 /* Round up a section size to the appropriate boundary. */
4530 md_section_align (segment
, size
)
4531 segT segment ATTRIBUTE_UNUSED
;
4534 #ifdef BFD_ASSEMBLER
4535 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4536 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
4538 /* For a.out, force the section size to be aligned. If we don't do
4539 this, BFD will align it for us, but it will not write out the
4540 final bytes of the section. This may be a bug in BFD, but it is
4541 easier to fix it here since that is how the other a.out targets
4545 align
= bfd_get_section_alignment (stdoutput
, segment
);
4546 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
4554 /* On the i386, PC-relative offsets are relative to the start of the
4555 next instruction. That is, the address of the offset, plus its
4556 size, since the offset is always the last part of the insn. */
4559 md_pcrel_from (fixP
)
4562 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4569 int ignore ATTRIBUTE_UNUSED
;
4573 temp
= get_absolute_expression ();
4574 subseg_set (bss_section
, (subsegT
) temp
);
4575 demand_empty_rest_of_line ();
4580 #ifdef BFD_ASSEMBLER
4583 i386_validate_fix (fixp
)
4586 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
4588 /* GOTOFF relocation are nonsense in 64bit mode. */
4589 if (flag_code
== CODE_64BIT
)
4591 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
4597 tc_gen_reloc (section
, fixp
)
4598 asection
*section ATTRIBUTE_UNUSED
;
4602 bfd_reloc_code_real_type code
;
4604 switch (fixp
->fx_r_type
)
4606 case BFD_RELOC_X86_64_PLT32
:
4607 case BFD_RELOC_X86_64_GOT32
:
4608 case BFD_RELOC_X86_64_GOTPCREL
:
4609 case BFD_RELOC_386_PLT32
:
4610 case BFD_RELOC_386_GOT32
:
4611 case BFD_RELOC_386_GOTOFF
:
4612 case BFD_RELOC_386_GOTPC
:
4613 case BFD_RELOC_X86_64_32S
:
4615 case BFD_RELOC_VTABLE_ENTRY
:
4616 case BFD_RELOC_VTABLE_INHERIT
:
4617 code
= fixp
->fx_r_type
;
4622 switch (fixp
->fx_size
)
4625 as_bad (_("can not do %d byte pc-relative relocation"),
4627 code
= BFD_RELOC_32_PCREL
;
4629 case 1: code
= BFD_RELOC_8_PCREL
; break;
4630 case 2: code
= BFD_RELOC_16_PCREL
; break;
4631 case 4: code
= BFD_RELOC_32_PCREL
; break;
4636 switch (fixp
->fx_size
)
4639 as_bad (_("can not do %d byte relocation"), fixp
->fx_size
);
4640 code
= BFD_RELOC_32
;
4642 case 1: code
= BFD_RELOC_8
; break;
4643 case 2: code
= BFD_RELOC_16
; break;
4644 case 4: code
= BFD_RELOC_32
; break;
4645 case 8: code
= BFD_RELOC_64
; break;
4651 if (code
== BFD_RELOC_32
4653 && fixp
->fx_addsy
== GOT_symbol
)
4655 /* We don't support GOTPC on 64bit targets. */
4656 if (flag_code
== CODE_64BIT
)
4658 code
= BFD_RELOC_386_GOTPC
;
4661 rel
= (arelent
*) xmalloc (sizeof (arelent
));
4662 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
4663 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
4665 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
4666 if (!use_rela_relocations
)
4668 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
4669 vtable entry to be used in the relocation's section offset. */
4670 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
4671 rel
->address
= fixp
->fx_offset
;
4674 rel
->addend
= fixp
->fx_addnumber
;
4678 /* Use the rela in 64bit mode. */
4681 rel
->addend
= fixp
->fx_offset
;
4683 /* Ohhh, this is ugly. The problem is that if this is a local global
4684 symbol, the relocation will entirely be performed at link time, not
4685 at assembly time. bfd_perform_reloc doesn't know about this sort
4686 of thing, and as a result we need to fake it out here. */
4687 if ((S_IS_EXTERN (fixp
->fx_addsy
) || S_IS_WEAK (fixp
->fx_addsy
))
4688 && !S_IS_COMMON(fixp
->fx_addsy
))
4689 rel
->addend
-= symbol_get_bfdsym (fixp
->fx_addsy
)->value
;
4692 rel
->addend
-= fixp
->fx_size
;
4696 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
4697 if (rel
->howto
== NULL
)
4699 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
4700 _("cannot represent relocation type %s"),
4701 bfd_get_reloc_code_name (code
));
4702 /* Set howto to a garbage value so that we can keep going. */
4703 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
4704 assert (rel
->howto
!= NULL
);
4710 #else /* ! BFD_ASSEMBLER */
4712 #if (defined(OBJ_AOUT) | defined(OBJ_BOUT))
4714 tc_aout_fix_to_chars (where
, fixP
, segment_address_in_file
)
4717 relax_addressT segment_address_in_file
;
4719 /* In: length of relocation (or of address) in chars: 1, 2 or 4.
4720 Out: GNU LD relocation length code: 0, 1, or 2. */
4722 static const unsigned char nbytes_r_length
[] = { 42, 0, 1, 42, 2 };
4725 know (fixP
->fx_addsy
!= NULL
);
4727 md_number_to_chars (where
,
4728 (valueT
) (fixP
->fx_frag
->fr_address
4729 + fixP
->fx_where
- segment_address_in_file
),
4732 r_symbolnum
= (S_IS_DEFINED (fixP
->fx_addsy
)
4733 ? S_GET_TYPE (fixP
->fx_addsy
)
4734 : fixP
->fx_addsy
->sy_number
);
4736 where
[6] = (r_symbolnum
>> 16) & 0x0ff;
4737 where
[5] = (r_symbolnum
>> 8) & 0x0ff;
4738 where
[4] = r_symbolnum
& 0x0ff;
4739 where
[7] = ((((!S_IS_DEFINED (fixP
->fx_addsy
)) << 3) & 0x08)
4740 | ((nbytes_r_length
[fixP
->fx_size
] << 1) & 0x06)
4741 | (((fixP
->fx_pcrel
<< 0) & 0x01) & 0x0f));
4744 #endif /* OBJ_AOUT or OBJ_BOUT. */
4746 #if defined (I386COFF)
4749 tc_coff_fix2rtype (fixP
)
4752 if (fixP
->fx_r_type
== R_IMAGEBASE
)
4755 return (fixP
->fx_pcrel
?
4756 (fixP
->fx_size
== 1 ? R_PCRBYTE
:
4757 fixP
->fx_size
== 2 ? R_PCRWORD
:
4759 (fixP
->fx_size
== 1 ? R_RELBYTE
:
4760 fixP
->fx_size
== 2 ? R_RELWORD
:
4765 tc_coff_sizemachdep (frag
)
4769 return (frag
->fr_next
->fr_address
- frag
->fr_address
);
4774 #endif /* I386COFF */
4776 #endif /* ! BFD_ASSEMBLER */
4778 /* Parse operands using Intel syntax. This implements a recursive descent
4779 parser based on the BNF grammar published in Appendix B of the MASM 6.1
4782 FIXME: We do not recognize the full operand grammar defined in the MASM
4783 documentation. In particular, all the structure/union and
4784 high-level macro operands are missing.
4786 Uppercase words are terminals, lower case words are non-terminals.
4787 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
4788 bars '|' denote choices. Most grammar productions are implemented in
4789 functions called 'intel_<production>'.
4791 Initial production is 'expr'.
4797 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
4799 constant digits [[ radixOverride ]]
4801 dataType BYTE | WORD | DWORD | QWORD | XWORD
4834 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
4835 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
4837 hexdigit a | b | c | d | e | f
4838 | A | B | C | D | E | F
4848 register specialRegister
4852 segmentRegister CS | DS | ES | FS | GS | SS
4854 specialRegister CR0 | CR2 | CR3
4855 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
4856 | TR3 | TR4 | TR5 | TR6 | TR7
4858 We simplify the grammar in obvious places (e.g., register parsing is
4859 done by calling parse_register) and eliminate immediate left recursion
4860 to implement a recursive-descent parser.
4900 /* Parsing structure for the intel syntax parser. Used to implement the
4901 semantic actions for the operand grammar. */
4902 struct intel_parser_s
4904 char *op_string
; /* The string being parsed. */
4905 int got_a_float
; /* Whether the operand is a float. */
4906 int op_modifier
; /* Operand modifier. */
4907 int is_mem
; /* 1 if operand is memory reference. */
4908 const reg_entry
*reg
; /* Last register reference found. */
4909 char *disp
; /* Displacement string being built. */
4912 static struct intel_parser_s intel_parser
;
4914 /* Token structure for parsing intel syntax. */
4917 int code
; /* Token code. */
4918 const reg_entry
*reg
; /* Register entry for register tokens. */
4919 char *str
; /* String representation. */
4922 static struct intel_token cur_token
, prev_token
;
4925 /* Token codes for the intel parser. Since T_SHORT is already used
4926 by COFF, undefine it first to prevent a warning. */
4941 /* Prototypes for intel parser functions. */
4942 static int intel_match_token
PARAMS ((int code
));
4943 static void intel_get_token
PARAMS ((void));
4944 static void intel_putback_token
PARAMS ((void));
4945 static int intel_expr
PARAMS ((void));
4946 static int intel_e05
PARAMS ((void));
4947 static int intel_e05_1
PARAMS ((void));
4948 static int intel_e06
PARAMS ((void));
4949 static int intel_e06_1
PARAMS ((void));
4950 static int intel_e09
PARAMS ((void));
4951 static int intel_e09_1
PARAMS ((void));
4952 static int intel_e10
PARAMS ((void));
4953 static int intel_e10_1
PARAMS ((void));
4954 static int intel_e11
PARAMS ((void));
4957 i386_intel_operand (operand_string
, got_a_float
)
4958 char *operand_string
;
4964 /* Initialize token holders. */
4965 cur_token
.code
= prev_token
.code
= T_NIL
;
4966 cur_token
.reg
= prev_token
.reg
= NULL
;
4967 cur_token
.str
= prev_token
.str
= NULL
;
4969 /* Initialize parser structure. */
4970 p
= intel_parser
.op_string
= (char *)malloc (strlen (operand_string
) + 1);
4973 strcpy (intel_parser
.op_string
, operand_string
);
4974 intel_parser
.got_a_float
= got_a_float
;
4975 intel_parser
.op_modifier
= -1;
4976 intel_parser
.is_mem
= 0;
4977 intel_parser
.reg
= NULL
;
4978 intel_parser
.disp
= (char *)malloc (strlen (operand_string
) + 1);
4979 if (intel_parser
.disp
== NULL
)
4981 intel_parser
.disp
[0] = '\0';
4983 /* Read the first token and start the parser. */
4985 ret
= intel_expr ();
4989 /* If we found a memory reference, hand it over to i386_displacement
4990 to fill in the rest of the operand fields. */
4991 if (intel_parser
.is_mem
)
4993 if ((i
.mem_operands
== 1
4994 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
4995 || i
.mem_operands
== 2)
4997 as_bad (_("too many memory references for '%s'"),
4998 current_templates
->start
->name
);
5003 char *s
= intel_parser
.disp
;
5006 /* Add the displacement expression. */
5008 ret
= i386_displacement (s
, s
+ strlen (s
))
5009 && i386_index_check (s
);
5013 /* Constant and OFFSET expressions are handled by i386_immediate. */
5014 else if (intel_parser
.op_modifier
== OFFSET_FLAT
5015 || intel_parser
.reg
== NULL
)
5016 ret
= i386_immediate (intel_parser
.disp
);
5020 free (intel_parser
.disp
);
5030 /* expr SHORT e05 */
5031 if (cur_token
.code
== T_SHORT
)
5033 intel_parser
.op_modifier
= SHORT
;
5034 intel_match_token (T_SHORT
);
5036 return (intel_e05 ());
5041 return intel_e05 ();
5051 return (intel_e06 () && intel_e05_1 ());
5057 /* e05' addOp e06 e05' */
5058 if (cur_token
.code
== '+' || cur_token
.code
== '-')
5060 strcat (intel_parser
.disp
, cur_token
.str
);
5061 intel_match_token (cur_token
.code
);
5063 return (intel_e06 () && intel_e05_1 ());
5078 return (intel_e09 () && intel_e06_1 ());
5084 /* e06' mulOp e09 e06' */
5085 if (cur_token
.code
== '*' || cur_token
.code
== '/')
5087 strcat (intel_parser
.disp
, cur_token
.str
);
5088 intel_match_token (cur_token
.code
);
5090 return (intel_e09 () && intel_e06_1 ());
5098 /* e09 OFFSET e10 e09'
5107 /* e09 OFFSET e10 e09' */
5108 if (cur_token
.code
== T_OFFSET
)
5110 intel_parser
.is_mem
= 0;
5111 intel_parser
.op_modifier
= OFFSET_FLAT
;
5112 intel_match_token (T_OFFSET
);
5114 return (intel_e10 () && intel_e09_1 ());
5119 return (intel_e10 () && intel_e09_1 ());
5125 /* e09' PTR e10 e09' */
5126 if (cur_token
.code
== T_PTR
)
5128 if (prev_token
.code
== T_BYTE
)
5129 i
.suffix
= BYTE_MNEM_SUFFIX
;
5131 else if (prev_token
.code
== T_WORD
)
5133 if (intel_parser
.got_a_float
== 2) /* "fi..." */
5134 i
.suffix
= SHORT_MNEM_SUFFIX
;
5136 i
.suffix
= WORD_MNEM_SUFFIX
;
5139 else if (prev_token
.code
== T_DWORD
)
5141 if (intel_parser
.got_a_float
== 1) /* "f..." */
5142 i
.suffix
= SHORT_MNEM_SUFFIX
;
5144 i
.suffix
= LONG_MNEM_SUFFIX
;
5147 else if (prev_token
.code
== T_QWORD
)
5149 if (intel_parser
.got_a_float
== 1) /* "f..." */
5150 i
.suffix
= LONG_MNEM_SUFFIX
;
5152 i
.suffix
= QWORD_MNEM_SUFFIX
;
5155 else if (prev_token
.code
== T_XWORD
)
5156 i
.suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
5160 as_bad (_("Unknown operand modifier `%s'\n"), prev_token
.str
);
5164 intel_match_token (T_PTR
);
5166 return (intel_e10 () && intel_e09_1 ());
5169 /* e09 : e10 e09' */
5170 else if (cur_token
.code
== ':')
5172 /* Mark as a memory operand only if it's not already known to be an
5173 offset expression. */
5174 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5175 intel_parser
.is_mem
= 1;
5177 return (intel_match_token (':') && intel_e10 () && intel_e09_1 ());
5192 return (intel_e11 () && intel_e10_1 ());
5198 /* e10' [ expr ] e10' */
5199 if (cur_token
.code
== '[')
5201 intel_match_token ('[');
5203 /* Mark as a memory operand only if it's not already known to be an
5204 offset expression. If it's an offset expression, we need to keep
5206 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5207 intel_parser
.is_mem
= 1;
5209 strcat (intel_parser
.disp
, "[");
5211 /* Add a '+' to the displacement string if necessary. */
5212 if (*intel_parser
.disp
!= '\0'
5213 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
5214 strcat (intel_parser
.disp
, "+");
5216 if (intel_expr () && intel_match_token (']'))
5218 /* Preserve brackets when the operand is an offset expression. */
5219 if (intel_parser
.op_modifier
== OFFSET_FLAT
)
5220 strcat (intel_parser
.disp
, "]");
5222 return intel_e10_1 ();
5249 if (cur_token
.code
== '(')
5251 intel_match_token ('(');
5252 strcat (intel_parser
.disp
, "(");
5254 if (intel_expr () && intel_match_token (')'))
5256 strcat (intel_parser
.disp
, ")");
5264 else if (cur_token
.code
== '[')
5266 intel_match_token ('[');
5268 /* Mark as a memory operand only if it's not already known to be an
5269 offset expression. If it's an offset expression, we need to keep
5271 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5272 intel_parser
.is_mem
= 1;
5274 strcat (intel_parser
.disp
, "[");
5276 /* Operands for jump/call inside brackets denote absolute addresses. */
5277 if (current_templates
->start
->opcode_modifier
& Jump
5278 || current_templates
->start
->opcode_modifier
& JumpDword
5279 || current_templates
->start
->opcode_modifier
& JumpByte
5280 || current_templates
->start
->opcode_modifier
& JumpInterSegment
)
5281 i
.types
[this_operand
] |= JumpAbsolute
;
5283 /* Add a '+' to the displacement string if necessary. */
5284 if (*intel_parser
.disp
!= '\0'
5285 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
5286 strcat (intel_parser
.disp
, "+");
5288 if (intel_expr () && intel_match_token (']'))
5290 /* Preserve brackets when the operand is an offset expression. */
5291 if (intel_parser
.op_modifier
== OFFSET_FLAT
)
5292 strcat (intel_parser
.disp
, "]");
5305 else if (cur_token
.code
== T_BYTE
5306 || cur_token
.code
== T_WORD
5307 || cur_token
.code
== T_DWORD
5308 || cur_token
.code
== T_QWORD
5309 || cur_token
.code
== T_XWORD
)
5311 intel_match_token (cur_token
.code
);
5318 else if (cur_token
.code
== '$' || cur_token
.code
== '.')
5320 strcat (intel_parser
.disp
, cur_token
.str
);
5321 intel_match_token (cur_token
.code
);
5323 /* Mark as a memory operand only if it's not already known to be an
5324 offset expression. */
5325 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5326 intel_parser
.is_mem
= 1;
5332 else if (cur_token
.code
== T_REG
)
5334 const reg_entry
*reg
= intel_parser
.reg
= cur_token
.reg
;
5336 intel_match_token (T_REG
);
5338 /* Check for segment change. */
5339 if (cur_token
.code
== ':')
5341 if (reg
->reg_type
& (SReg2
| SReg3
))
5343 switch (reg
->reg_num
)
5346 i
.seg
[i
.mem_operands
] = &es
;
5349 i
.seg
[i
.mem_operands
] = &cs
;
5352 i
.seg
[i
.mem_operands
] = &ss
;
5355 i
.seg
[i
.mem_operands
] = &ds
;
5358 i
.seg
[i
.mem_operands
] = &fs
;
5361 i
.seg
[i
.mem_operands
] = &gs
;
5367 as_bad (_("`%s' is not a valid segment register"), reg
->reg_name
);
5372 /* Not a segment register. Check for register scaling. */
5373 else if (cur_token
.code
== '*')
5375 if (!intel_parser
.is_mem
)
5377 as_bad (_("Register scaling only allowed in memory operands."));
5381 /* What follows must be a valid scale. */
5382 if (intel_match_token ('*')
5383 && strchr ("01248", *cur_token
.str
))
5386 i
.types
[this_operand
] |= BaseIndex
;
5388 /* Set the scale after setting the register (otherwise,
5389 i386_scale will complain) */
5390 i386_scale (cur_token
.str
);
5391 intel_match_token (T_CONST
);
5395 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
5401 /* No scaling. If this is a memory operand, the register is either a
5402 base register (first occurrence) or an index register (second
5404 else if (intel_parser
.is_mem
&& !(reg
->reg_type
& (SReg2
| SReg3
)))
5406 if (i
.base_reg
&& i
.index_reg
)
5408 as_bad (_("Too many register references in memory operand.\n"));
5412 if (i
.base_reg
== NULL
)
5417 i
.types
[this_operand
] |= BaseIndex
;
5420 /* Offset modifier. Add the register to the displacement string to be
5421 parsed as an immediate expression after we're done. */
5422 else if (intel_parser
.op_modifier
== OFFSET_FLAT
)
5423 strcat (intel_parser
.disp
, reg
->reg_name
);
5425 /* It's neither base nor index nor offset. */
5428 i
.types
[this_operand
] |= reg
->reg_type
& ~BaseIndex
;
5429 i
.op
[this_operand
].regs
= reg
;
5433 /* Since registers are not part of the displacement string (except
5434 when we're parsing offset operands), we may need to remove any
5435 preceding '+' from the displacement string. */
5436 if (*intel_parser
.disp
!= '\0'
5437 && intel_parser
.op_modifier
!= OFFSET_FLAT
)
5439 char *s
= intel_parser
.disp
;
5440 s
+= strlen (s
) - 1;
5449 else if (cur_token
.code
== T_ID
)
5451 /* Add the identifier to the displacement string. */
5452 strcat (intel_parser
.disp
, cur_token
.str
);
5453 intel_match_token (T_ID
);
5455 /* The identifier represents a memory reference only if it's not
5456 preceded by an offset modifier. */
5457 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5458 intel_parser
.is_mem
= 1;
5464 else if (cur_token
.code
== T_CONST
5465 || cur_token
.code
== '-'
5466 || cur_token
.code
== '+')
5470 /* Allow constants that start with `+' or `-'. */
5471 if (cur_token
.code
== '-' || cur_token
.code
== '+')
5473 strcat (intel_parser
.disp
, cur_token
.str
);
5474 intel_match_token (cur_token
.code
);
5475 if (cur_token
.code
!= T_CONST
)
5477 as_bad (_("Syntax error. Expecting a constant. Got `%s'.\n"),
5483 save_str
= (char *)malloc (strlen (cur_token
.str
) + 1);
5484 if (save_str
== NULL
)
5486 strcpy (save_str
, cur_token
.str
);
5488 /* Get the next token to check for register scaling. */
5489 intel_match_token (cur_token
.code
);
5491 /* Check if this constant is a scaling factor for an index register. */
5492 if (cur_token
.code
== '*')
5494 if (intel_match_token ('*') && cur_token
.code
== T_REG
)
5496 if (!intel_parser
.is_mem
)
5498 as_bad (_("Register scaling only allowed in memory operands."));
5502 /* The constant is followed by `* reg', so it must be
5504 if (strchr ("01248", *save_str
))
5506 i
.index_reg
= cur_token
.reg
;
5507 i
.types
[this_operand
] |= BaseIndex
;
5509 /* Set the scale after setting the register (otherwise,
5510 i386_scale will complain) */
5511 i386_scale (save_str
);
5512 intel_match_token (T_REG
);
5514 /* Since registers are not part of the displacement
5515 string, we may need to remove any preceding '+' from
5516 the displacement string. */
5517 if (*intel_parser
.disp
!= '\0')
5519 char *s
= intel_parser
.disp
;
5520 s
+= strlen (s
) - 1;
5533 /* The constant was not used for register scaling. Since we have
5534 already consumed the token following `*' we now need to put it
5535 back in the stream. */
5537 intel_putback_token ();
5540 /* Add the constant to the displacement string. */
5541 strcat (intel_parser
.disp
, save_str
);
5547 as_bad (_("Unrecognized token '%s'"), cur_token
.str
);
5551 /* Match the given token against cur_token. If they match, read the next
5552 token from the operand string. */
5554 intel_match_token (code
)
5557 if (cur_token
.code
== code
)
5564 as_bad (_("Unexpected token `%s'\n"), cur_token
.str
);
5569 /* Read a new token from intel_parser.op_string and store it in cur_token. */
5574 const reg_entry
*reg
;
5575 struct intel_token new_token
;
5577 new_token
.code
= T_NIL
;
5578 new_token
.reg
= NULL
;
5579 new_token
.str
= NULL
;
5581 /* Free the memory allocated to the previous token and move
5582 cur_token to prev_token. */
5584 free (prev_token
.str
);
5586 prev_token
= cur_token
;
5588 /* Skip whitespace. */
5589 while (is_space_char (*intel_parser
.op_string
))
5590 intel_parser
.op_string
++;
5592 /* Return an empty token if we find nothing else on the line. */
5593 if (*intel_parser
.op_string
== '\0')
5595 cur_token
= new_token
;
5599 /* The new token cannot be larger than the remainder of the operand
5601 new_token
.str
= (char *)malloc (strlen (intel_parser
.op_string
) + 1);
5602 if (new_token
.str
== NULL
)
5604 new_token
.str
[0] = '\0';
5606 if (strchr ("0123456789", *intel_parser
.op_string
))
5608 char *p
= new_token
.str
;
5609 char *q
= intel_parser
.op_string
;
5610 new_token
.code
= T_CONST
;
5612 /* Allow any kind of identifier char to encompass floating point and
5613 hexadecimal numbers. */
5614 while (is_identifier_char (*q
))
5618 /* Recognize special symbol names [0-9][bf]. */
5619 if (strlen (intel_parser
.op_string
) == 2
5620 && (intel_parser
.op_string
[1] == 'b'
5621 || intel_parser
.op_string
[1] == 'f'))
5622 new_token
.code
= T_ID
;
5625 else if (strchr ("+-/*:[]()", *intel_parser
.op_string
))
5627 new_token
.code
= *intel_parser
.op_string
;
5628 new_token
.str
[0] = *intel_parser
.op_string
;
5629 new_token
.str
[1] = '\0';
5632 else if ((*intel_parser
.op_string
== REGISTER_PREFIX
|| allow_naked_reg
)
5633 && ((reg
= parse_register (intel_parser
.op_string
, &end_op
)) != NULL
))
5635 new_token
.code
= T_REG
;
5636 new_token
.reg
= reg
;
5638 if (*intel_parser
.op_string
== REGISTER_PREFIX
)
5640 new_token
.str
[0] = REGISTER_PREFIX
;
5641 new_token
.str
[1] = '\0';
5644 strcat (new_token
.str
, reg
->reg_name
);
5647 else if (is_identifier_char (*intel_parser
.op_string
))
5649 char *p
= new_token
.str
;
5650 char *q
= intel_parser
.op_string
;
5652 /* A '.' or '$' followed by an identifier char is an identifier.
5653 Otherwise, it's operator '.' followed by an expression. */
5654 if ((*q
== '.' || *q
== '$') && !is_identifier_char (*(q
+ 1)))
5656 new_token
.code
= *q
;
5657 new_token
.str
[0] = *q
;
5658 new_token
.str
[1] = '\0';
5662 while (is_identifier_char (*q
) || *q
== '@')
5666 if (strcasecmp (new_token
.str
, "BYTE") == 0)
5667 new_token
.code
= T_BYTE
;
5669 else if (strcasecmp (new_token
.str
, "WORD") == 0)
5670 new_token
.code
= T_WORD
;
5672 else if (strcasecmp (new_token
.str
, "DWORD") == 0)
5673 new_token
.code
= T_DWORD
;
5675 else if (strcasecmp (new_token
.str
, "QWORD") == 0)
5676 new_token
.code
= T_QWORD
;
5678 else if (strcasecmp (new_token
.str
, "XWORD") == 0)
5679 new_token
.code
= T_XWORD
;
5681 else if (strcasecmp (new_token
.str
, "PTR") == 0)
5682 new_token
.code
= T_PTR
;
5684 else if (strcasecmp (new_token
.str
, "SHORT") == 0)
5685 new_token
.code
= T_SHORT
;
5687 else if (strcasecmp (new_token
.str
, "OFFSET") == 0)
5689 new_token
.code
= T_OFFSET
;
5691 /* ??? This is not mentioned in the MASM grammar but gcc
5692 makes use of it with -mintel-syntax. OFFSET may be
5693 followed by FLAT: */
5694 if (strncasecmp (q
, " FLAT:", 6) == 0)
5695 strcat (new_token
.str
, " FLAT:");
5698 /* ??? This is not mentioned in the MASM grammar. */
5699 else if (strcasecmp (new_token
.str
, "FLAT") == 0)
5700 new_token
.code
= T_OFFSET
;
5703 new_token
.code
= T_ID
;
5708 as_bad (_("Unrecognized token `%s'\n"), intel_parser
.op_string
);
5710 intel_parser
.op_string
+= strlen (new_token
.str
);
5711 cur_token
= new_token
;
5714 /* Put cur_token back into the token stream and make cur_token point to
5717 intel_putback_token ()
5719 intel_parser
.op_string
-= strlen (cur_token
.str
);
5720 free (cur_token
.str
);
5721 cur_token
= prev_token
;
5723 /* Forget prev_token. */
5724 prev_token
.code
= T_NIL
;
5725 prev_token
.reg
= NULL
;
5726 prev_token
.str
= NULL
;