include/opcode/m88k.h

   1 /* Table of opcodes for the Motorola M88k family.
   2    Copyright 1989, 1990, 1991, 1993, 2001, 2002, 2010
   3    Free Software Foundation, Inc.
   4
   5    This file is part of GDB and GAS.
   6
   7    This program is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3 of the License, or
  10    (at your option) any later version.
  11
  12    This program is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15    GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this program; if not, write to the Free Software
  19    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  20    MA 02110-1301, USA.  */
  21
  22 /*
  23  *                      Disassembler Instruction Table
  24  *
  25  *      The first field of the table is the opcode field. If an opcode
  26  *      is specified which has any non-opcode bits on, a system error
  27  *      will occur when the system attempts the install it into the
  28  *      instruction table.  The second parameter is a pointer to the
  29  *      instruction mnemonic. Each operand is specified by offset, width,
  30  *      and type. The offset is the bit number of the least significant
  31  *      bit of the operand with bit 0 being the least significant bit of
  32  *      the instruction. The width is the number of bits used to specify
  33  *      the operand. The type specifies the output format to be used for
  34  *      the operand. The valid formats are: register, register indirect,
  35  *      hex constant, and bit field specification.  The last field is a
  36  *      pointer to the next instruction in the linked list.  These pointers
  37  *      are initialized by init_disasm().
  38  *
  39  *                              Revision History
  40  *
  41  *      Revision 1.0    11/08/85        Creation date
  42  *               1.1    02/05/86        Updated instruction mnemonic table MD
  43  *               1.2    06/16/86        Updated SIM_FLAGS for floating point
  44  *               1.3    09/20/86        Updated for new encoding
  45  *                      05/11/89        R. Trawick adapted from Motorola disassembler
  46  */
  47
  48 #include <stdio.h>
  49
  50 /* Define the number of bits in the primary opcode field of the instruction,
  51    the destination field, the source 1 and source 2 fields.  */
  52
  53 /* Size of opcode field.  */
  54 #define OP 8
  55
  56 /* Size of destination.  */
  57 #define DEST 6
  58
  59 /* Size of source1.  */
  60 #define SOURCE1 6
  61
  62 /* Size of source2.  */
  63 #define SOURCE2 6
  64
  65 /* Number of registers.  */
  66 #define REGs 32
  67
  68 /* Type definitions.  */
  69
  70 typedef unsigned int UINT;
  71 #define    WORD    long
  72 #define    FLAG    unsigned
  73 #define    STATE   short
  74
  75 /* The next four equates define the priorities that the various classes
  76  * of instructions have regarding writing results back into registers and
  77  * signalling exceptions.  */
  78
  79 /* PMEM is also defined in <sys/param.h> on Delta 88's.  Sigh!  */
  80 #undef PMEM
  81
  82 /* Integer priority.  */
  83 #define    PINT  0
  84
  85 /* Floating point priority.  */
  86 #define    PFLT  1
  87
  88 /* Memory priority.  */
  89 #define    PMEM  2
  90
  91 /* Not applicable, instruction doesn't write to regs.  */
  92 #define    NA    3
  93
  94 /* Highest of these priorities.  */
  95 #define    HIPRI 3
  96
  97 /* The instruction registers are an artificial mechanism to speed up
  98  * simulator execution.  In the real processor, an instruction register
  99  * is 32 bits wide.  In the simulator, the 32 bit instruction is kept in
 100  * a structure field called rawop, and the instruction is partially decoded,
 101  * and split into various fields and flags which make up the other fields
 102  * of the structure.
 103  * The partial decode is done when the instructions are initially loaded
 104  * into simulator memory.  The simulator code memory is not an array of
 105  * 32 bit words, but is an array of instruction register structures.
 106  * Yes this wastes memory, but it executes much quicker.
 107  */
 108
 109 struct IR_FIELDS
 110 {
 111   unsigned op:OP,
 112     dest: DEST,
 113     src1: SOURCE1,
 114     src2: SOURCE2;
 115   int ltncy,
 116     extime,
 117     /* Writeback priority.  */
 118     wb_pri;
 119   /* Immediate size.  */
 120   unsigned        imm_flags:2,
 121     /* Register source 1 used.  */
 122     rs1_used:1,
 123     /* Register source 2 used. */
 124     rs2_used:1,
 125     /* Register source/dest. used.  */
 126     rsd_used:1,
 127     /* Complement.  */
 128     c_flag:1,
 129     /* Upper half word.  */
 130     u_flag:1,
 131     /* Execute next.  */
 132     n_flag:1,
 133     /* Uses writeback slot.  */
 134     wb_flag:1,
 135     /* Dest size.  */
 136     dest_64:1,
 137     /* Source 1 size.  */
 138     s1_64:1,
 139     /* Source 2 size.  */
 140     s2_64:1,
 141     scale_flag:1,
 142     /* Scaled register.  */
 143     brk_flg:1;
 144 };
 145
 146 struct  mem_segs
 147 {
 148   /* Pointer (returned by calloc) to segment.  */
 149   struct mem_wrd *seg;
 150
 151   /* Base load address from file headers.  */
 152   unsigned long baseaddr;
 153
 154   /* Ending address of segment.  */
 155   unsigned long endaddr;
 156
 157   /* Segment control flags (none defined).  */
 158   int         flags;
 159 };
 160
 161 #define MAXSEGS         (10)                    /* max number of segment allowed */
 162 #define MEMSEGSIZE      (sizeof(struct mem_segs))/* size of mem_segs structure */
 163
 164 #if 0
 165 #define BRK_RD          (0x01)                  /* break on memory read */
 166 #define BRK_WR          (0x02)                  /* break on memory write */
 167 #define BRK_EXEC        (0x04)                  /* break on execution */
 168 #define BRK_CNT         (0x08)                  /* break on terminal count */
 169 #endif
 170
 171 struct mem_wrd
 172 {
 173   /* Simulator instruction break down.  */
 174   struct IR_FIELDS opcode;
 175   union {
 176     /* Memory element break down.  */
 177     unsigned long  l;
 178     unsigned short s[2];
 179     unsigned char  c[4];
 180   } mem;
 181 };
 182
 183 /* Size of each 32 bit memory model.  */
 184 #define MEMWRDSIZE      (sizeof (struct mem_wrd))
 185
 186 extern struct mem_segs memory[];
 187 extern struct PROCESSOR m78000;
 188
 189 struct PROCESSOR
 190 {
 191   unsigned WORD
 192   /* Execute instruction pointer.  */
 193   ip,
 194     /* Vector base register.  */
 195     vbr,
 196     /* Processor status register.  */
 197     psr;
 198
 199   /* Source 1.  */
 200   WORD    S1bus,
 201     /* Source 2.  */
 202     S2bus,
 203     /* Destination.  */
 204     Dbus,
 205     /* Data address bus.  */
 206     DAbus,
 207     ALU,
 208     /* Data registers.  */
 209     Regs[REGs],
 210     /* Max clocks before reg is available.  */
 211     time_left[REGs],
 212     /* Writeback priority of reg.  */
 213     wb_pri[REGs],
 214     /* Integer unit control regs.  */
 215     SFU0_regs[REGs],
 216     /* Floating point control regs.  */
 217     SFU1_regs[REGs],
 218     Scoreboard[REGs],
 219     Vbr;
 220   unsigned WORD   scoreboard,
 221     Psw,
 222     Tpsw;
 223   /* Waiting for a jump instruction.  */
 224   FLAG   jump_pending:1;
 225 };
 226
 227 /* Size of immediate field.  */
 228
 229 #define    i26bit      1
 230 #define    i16bit      2
 231 #define    i10bit      3
 232
 233 /* Definitions for fields in psr.  */
 234
 235 #define psr_mode  31
 236 #define psr_rbo   30
 237 #define psr_ser   29
 238 #define psr_carry 28
 239 #define psr_sf7m  11
 240 #define psr_sf6m  10
 241 #define psr_sf5m   9
 242 #define psr_sf4m   8
 243 #define psr_sf3m   7
 244 #define psr_sf2m   6
 245 #define psr_sf1m   5
 246 #define psr_mam    4
 247 #define psr_inm    3
 248 #define psr_exm    2
 249 #define psr_trm    1
 250 #define psr_ovfm   0
 251
 252 /* The 1 clock operations.  */
 253
 254 #define    ADDU        1
 255 #define    ADDC        2
 256 #define    ADDUC       3
 257 #define    ADD         4
 258
 259 #define    SUBU    ADD+1
 260 #define    SUBB    ADD+2
 261 #define    SUBUB   ADD+3
 262 #define    SUB     ADD+4
 263
 264 #define    AND_    ADD+5
 265 #define    OR      ADD+6
 266 #define    XOR     ADD+7
 267 #define    CMP     ADD+8
 268
 269 /* Loads.  */
 270
 271 #define    LDAB    CMP+1
 272 #define    LDAH    CMP+2
 273 #define    LDA     CMP+3
 274 #define    LDAD    CMP+4
 275
 276 #define    LDB   LDAD+1
 277 #define    LDH   LDAD+2
 278 #define    LD    LDAD+3
 279 #define    LDD   LDAD+4
 280 #define    LDBU  LDAD+5
 281 #define    LDHU  LDAD+6
 282
 283 /* Stores.  */
 284
 285 #define    STB    LDHU+1
 286 #define    STH    LDHU+2
 287 #define    ST     LDHU+3
 288 #define    STD    LDHU+4
 289
 290 /* Exchange.  */
 291
 292 #define    XMEMBU LDHU+5
 293 #define    XMEM   LDHU+6
 294
 295 /* Branches.  */
 296
 297 #define    JSR    STD+1
 298 #define    BSR    STD+2
 299 #define    BR     STD+3
 300 #define    JMP    STD+4
 301 #define    BB1    STD+5
 302 #define    BB0    STD+6
 303 #define    RTN    STD+7
 304 #define    BCND   STD+8
 305
 306 /* Traps.  */
 307
 308 #define    TB1    BCND+1
 309 #define    TB0    BCND+2
 310 #define    TCND   BCND+3
 311 #define    RTE    BCND+4
 312 #define    TBND   BCND+5
 313
 314 /* Misc.  */
 315
 316 #define    MUL     TBND + 1
 317 #define    DIV     MUL  +2
 318 #define    DIVU    MUL  +3
 319 #define    MASK    MUL  +4
 320 #define    FF0     MUL  +5
 321 #define    FF1     MUL  +6
 322 #define    CLR     MUL  +7
 323 #define    SET     MUL  +8
 324 #define    EXT     MUL  +9
 325 #define    EXTU    MUL  +10
 326 #define    MAK     MUL  +11
 327 #define    ROT     MUL  +12
 328
 329 /* Control register manipulations.  */
 330
 331 #define    LDCR    ROT  +1
 332 #define    STCR    ROT  +2
 333 #define    XCR     ROT  +3
 334
 335 #define    FLDCR    ROT  +4
 336 #define    FSTCR    ROT  +5
 337 #define    FXCR     ROT  +6
 338
 339 #define    NOP     XCR +1
 340
 341 /* Floating point instructions.  */
 342
 343 #define    FADD    NOP +1
 344 #define    FSUB    NOP +2
 345 #define    FMUL    NOP +3
 346 #define    FDIV    NOP +4
 347 #define    FSQRT   NOP +5
 348 #define    FCMP    NOP +6
 349 #define    FIP     NOP +7
 350 #define    FLT     NOP +8
 351 #define    INT     NOP +9
 352 #define    NINT    NOP +10
 353 #define    TRNC    NOP +11
 354 #define    FLDC   NOP +12
 355 #define    FSTC   NOP +13
 356 #define    FXC    NOP +14
 357
 358 #define UEXT(src,off,wid) \
 359   ((((unsigned int)(src)) >> (off)) & ((1 << (wid)) - 1))
 360
 361 #define SEXT(src,off,wid) \
 362   (((((int)(src))<<(32 - ((off) + (wid)))) >>(32 - (wid))) )
 363
 364 #define MAKE(src,off,wid) \
 365   ((((unsigned int)(src)) & ((1 << (wid)) - 1)) << (off))
 366
 367 #define opword(n) (unsigned long) (memaddr->mem.l)
 368
 369 /* Constants and masks.  */
 370
 371 #define SFU0       0x80000000
 372 #define SFU1       0x84000000
 373 #define SFU7       0x9c000000
 374 #define RRI10      0xf0000000
 375 #define RRR        0xf4000000
 376 #define SFUMASK    0xfc00ffe0
 377 #define RRRMASK    0xfc00ffe0
 378 #define RRI10MASK  0xfc00fc00
 379 #define DEFMASK    0xfc000000
 380 #define CTRL       0x0000f000
 381 #define CTRLMASK   0xfc00f800
 382
 383 /* Operands types.  */
 384
 385 enum operand_type
 386 {
 387   HEX = 1,
 388   REG = 2,
 389   CONT = 3,
 390   IND = 3,
 391   BF = 4,
 392   /* Scaled register.  */
 393   REGSC = 5,
 394   /* Control register.  */
 395   CRREG = 6,
 396   /* Floating point control register.  */
 397   FCRREG = 7,
 398   PCREL = 8,
 399   CONDMASK = 9,
 400   /* Extended register.  */
 401   XREG = 10,
 402   /* Decimal.  */
 403   DEC = 11
 404 };
 405
 406 /* Hashing specification.  */
 407
 408 #define HASHVAL     79
 409
 410 /* Structure templates.  */
 411
 412 typedef struct
 413 {
 414   unsigned int offset;
 415   unsigned int width;
 416   enum operand_type type;
 417 } OPSPEC;
 418
 419 struct SIM_FLAGS
 420 {
 421   int  ltncy,   /* latency (max number of clocks needed to execute).  */
 422     extime,   /* execution time (min number of clocks needed to execute).  */
 423     wb_pri;   /* writeback slot priority.  */
 424   unsigned         op:OP,   /* simulator version of opcode.  */
 425     imm_flags:2,   /* 10,16 or 26 bit immediate flags.  */
 426     rs1_used:1,   /* register source 1 used.  */
 427     rs2_used:1,   /* register source 2 used.  */
 428     rsd_used:1,   /* register source/dest used.  */
 429     c_flag:1,   /* complement.  */
 430     u_flag:1,   /* upper half word.  */
 431     n_flag:1,   /* execute next.  */
 432     wb_flag:1,   /* uses writeback slot.  */
 433     dest_64:1,   /* double precision dest.  */
 434     s1_64:1,   /* double precision source 1.  */
 435     s2_64:1,   /* double precision source 2.  */
 436     scale_flag:1;   /* register is scaled.  */
 437 };
 438
 439 typedef struct INSTRUCTAB {
 440   unsigned int  opcode;
 441   char          *mnemonic;
 442   OPSPEC        op1,op2,op3;
 443   struct SIM_FLAGS flgs;
 444 } INSTAB;
 445 \f
 446
 447 #define NO_OPERAND {0,0,0}
 448
 449 extern const INSTAB  instructions[];
 450
 451 /*
 452  * Local Variables:
 453  * fill-column: 131
 454  * End:
 455  */