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PR binutils/2768
[binutils.git] / opcodes / mips-dis.c
blobb0562ea25230caf0a76bc020e93a9d7a0ff41b3a
1 /* Print mips instructions for GDB, the GNU debugger, or for objdump.
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2005
4 Free Software Foundation, Inc.
5 Contributed by Nobuyuki Hikichi(hikichi@sra.co.jp).
6
7 This file is part of GDB, GAS, and the GNU binutils.
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
22 MA 02110-1301, USA. */
23
24 #include "sysdep.h"
25 #include "dis-asm.h"
26 #include "libiberty.h"
27 #include "opcode/mips.h"
28 #include "opintl.h"
29
30 /* FIXME: These are needed to figure out if the code is mips16 or
31 not. The low bit of the address is often a good indicator. No
32 symbol table is available when this code runs out in an embedded
33 system as when it is used for disassembler support in a monitor. */
34
35 #if !defined(EMBEDDED_ENV)
36 #define SYMTAB_AVAILABLE 1
37 #include "elf-bfd.h"
38 #include "elf/mips.h"
39 #endif
40
41 /* Mips instructions are at maximum this many bytes long. */
42 #define INSNLEN 4
43
44 \f
45 /* FIXME: These should be shared with gdb somehow. */
46
47 struct mips_cp0sel_name
48 {
49 unsigned int cp0reg;
50 unsigned int sel;
51 const char * const name;
52 };
53
54 /* The mips16 registers. */
55 static const unsigned int mips16_to_32_reg_map[] =
56 {
57 16, 17, 2, 3, 4, 5, 6, 7
58 };
59
60 #define mips16_reg_names(rn) mips_gpr_names[mips16_to_32_reg_map[rn]]
61
62
63 static const char * const mips_gpr_names_numeric[32] =
64 {
65 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
66 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
67 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
68 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
69 };
70
71 static const char * const mips_gpr_names_oldabi[32] =
72 {
73 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
74 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
75 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
76 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
77 };
78
79 static const char * const mips_gpr_names_newabi[32] =
80 {
81 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
82 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
83 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
84 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
85 };
86
87 static const char * const mips_fpr_names_numeric[32] =
88 {
89 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
90 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
91 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
92 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31"
93 };
94
95 static const char * const mips_fpr_names_32[32] =
96 {
97 "fv0", "fv0f", "fv1", "fv1f", "ft0", "ft0f", "ft1", "ft1f",
98 "ft2", "ft2f", "ft3", "ft3f", "fa0", "fa0f", "fa1", "fa1f",
99 "ft4", "ft4f", "ft5", "ft5f", "fs0", "fs0f", "fs1", "fs1f",
100 "fs2", "fs2f", "fs3", "fs3f", "fs4", "fs4f", "fs5", "fs5f"
101 };
102
103 static const char * const mips_fpr_names_n32[32] =
104 {
105 "fv0", "ft14", "fv1", "ft15", "ft0", "ft1", "ft2", "ft3",
106 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3",
107 "fa4", "fa5", "fa6", "fa7", "fs0", "ft8", "fs1", "ft9",
108 "fs2", "ft10", "fs3", "ft11", "fs4", "ft12", "fs5", "ft13"
109 };
110
111 static const char * const mips_fpr_names_64[32] =
112 {
113 "fv0", "ft12", "fv1", "ft13", "ft0", "ft1", "ft2", "ft3",
114 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3",
115 "fa4", "fa5", "fa6", "fa7", "ft8", "ft9", "ft10", "ft11",
116 "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7"
117 };
118
119 static const char * const mips_cp0_names_numeric[32] =
120 {
121 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
122 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
123 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
124 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
125 };
126
127 static const char * const mips_cp0_names_mips3264[32] =
128 {
129 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
130 "c0_context", "c0_pagemask", "c0_wired", "$7",
131 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
132 "c0_status", "c0_cause", "c0_epc", "c0_prid",
133 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
134 "c0_xcontext", "$21", "$22", "c0_debug",
135 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr",
136 "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave",
137 };
138
139 static const struct mips_cp0sel_name mips_cp0sel_names_mips3264[] =
140 {
141 { 16, 1, "c0_config1" },
142 { 16, 2, "c0_config2" },
143 { 16, 3, "c0_config3" },
144 { 18, 1, "c0_watchlo,1" },
145 { 18, 2, "c0_watchlo,2" },
146 { 18, 3, "c0_watchlo,3" },
147 { 18, 4, "c0_watchlo,4" },
148 { 18, 5, "c0_watchlo,5" },
149 { 18, 6, "c0_watchlo,6" },
150 { 18, 7, "c0_watchlo,7" },
151 { 19, 1, "c0_watchhi,1" },
152 { 19, 2, "c0_watchhi,2" },
153 { 19, 3, "c0_watchhi,3" },
154 { 19, 4, "c0_watchhi,4" },
155 { 19, 5, "c0_watchhi,5" },
156 { 19, 6, "c0_watchhi,6" },
157 { 19, 7, "c0_watchhi,7" },
158 { 25, 1, "c0_perfcnt,1" },
159 { 25, 2, "c0_perfcnt,2" },
160 { 25, 3, "c0_perfcnt,3" },
161 { 25, 4, "c0_perfcnt,4" },
162 { 25, 5, "c0_perfcnt,5" },
163 { 25, 6, "c0_perfcnt,6" },
164 { 25, 7, "c0_perfcnt,7" },
165 { 27, 1, "c0_cacheerr,1" },
166 { 27, 2, "c0_cacheerr,2" },
167 { 27, 3, "c0_cacheerr,3" },
168 { 28, 1, "c0_datalo" },
169 { 29, 1, "c0_datahi" }
170 };
171
172 static const char * const mips_cp0_names_mips3264r2[32] =
173 {
174 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
175 "c0_context", "c0_pagemask", "c0_wired", "c0_hwrena",
176 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
177 "c0_status", "c0_cause", "c0_epc", "c0_prid",
178 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
179 "c0_xcontext", "$21", "$22", "c0_debug",
180 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr",
181 "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave",
182 };
183
184 static const struct mips_cp0sel_name mips_cp0sel_names_mips3264r2[] =
185 {
186 { 4, 1, "c0_contextconfig" },
187 { 0, 1, "c0_mvpcontrol" },
188 { 0, 2, "c0_mvpconf0" },
189 { 0, 3, "c0_mvpconf1" },
190 { 1, 1, "c0_vpecontrol" },
191 { 1, 2, "c0_vpeconf0" },
192 { 1, 3, "c0_vpeconf1" },
193 { 1, 4, "c0_yqmask" },
194 { 1, 5, "c0_vpeschedule" },
195 { 1, 6, "c0_vpeschefback" },
196 { 2, 1, "c0_tcstatus" },
197 { 2, 2, "c0_tcbind" },
198 { 2, 3, "c0_tcrestart" },
199 { 2, 4, "c0_tchalt" },
200 { 2, 5, "c0_tccontext" },
201 { 2, 6, "c0_tcschedule" },
202 { 2, 7, "c0_tcschefback" },
203 { 5, 1, "c0_pagegrain" },
204 { 6, 1, "c0_srsconf0" },
205 { 6, 2, "c0_srsconf1" },
206 { 6, 3, "c0_srsconf2" },
207 { 6, 4, "c0_srsconf3" },
208 { 6, 5, "c0_srsconf4" },
209 { 12, 1, "c0_intctl" },
210 { 12, 2, "c0_srsctl" },
211 { 12, 3, "c0_srsmap" },
212 { 15, 1, "c0_ebase" },
213 { 16, 1, "c0_config1" },
214 { 16, 2, "c0_config2" },
215 { 16, 3, "c0_config3" },
216 { 18, 1, "c0_watchlo,1" },
217 { 18, 2, "c0_watchlo,2" },
218 { 18, 3, "c0_watchlo,3" },
219 { 18, 4, "c0_watchlo,4" },
220 { 18, 5, "c0_watchlo,5" },
221 { 18, 6, "c0_watchlo,6" },
222 { 18, 7, "c0_watchlo,7" },
223 { 19, 1, "c0_watchhi,1" },
224 { 19, 2, "c0_watchhi,2" },
225 { 19, 3, "c0_watchhi,3" },
226 { 19, 4, "c0_watchhi,4" },
227 { 19, 5, "c0_watchhi,5" },
228 { 19, 6, "c0_watchhi,6" },
229 { 19, 7, "c0_watchhi,7" },
230 { 23, 1, "c0_tracecontrol" },
231 { 23, 2, "c0_tracecontrol2" },
232 { 23, 3, "c0_usertracedata" },
233 { 23, 4, "c0_tracebpc" },
234 { 25, 1, "c0_perfcnt,1" },
235 { 25, 2, "c0_perfcnt,2" },
236 { 25, 3, "c0_perfcnt,3" },
237 { 25, 4, "c0_perfcnt,4" },
238 { 25, 5, "c0_perfcnt,5" },
239 { 25, 6, "c0_perfcnt,6" },
240 { 25, 7, "c0_perfcnt,7" },
241 { 27, 1, "c0_cacheerr,1" },
242 { 27, 2, "c0_cacheerr,2" },
243 { 27, 3, "c0_cacheerr,3" },
244 { 28, 1, "c0_datalo" },
245 { 28, 2, "c0_taglo1" },
246 { 28, 3, "c0_datalo1" },
247 { 28, 4, "c0_taglo2" },
248 { 28, 5, "c0_datalo2" },
249 { 28, 6, "c0_taglo3" },
250 { 28, 7, "c0_datalo3" },
251 { 29, 1, "c0_datahi" },
252 { 29, 2, "c0_taghi1" },
253 { 29, 3, "c0_datahi1" },
254 { 29, 4, "c0_taghi2" },
255 { 29, 5, "c0_datahi2" },
256 { 29, 6, "c0_taghi3" },
257 { 29, 7, "c0_datahi3" },
258 };
259
260 /* SB-1: MIPS64 (mips_cp0_names_mips3264) with minor mods. */
261 static const char * const mips_cp0_names_sb1[32] =
262 {
263 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
264 "c0_context", "c0_pagemask", "c0_wired", "$7",
265 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
266 "c0_status", "c0_cause", "c0_epc", "c0_prid",
267 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
268 "c0_xcontext", "$21", "$22", "c0_debug",
269 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr_i",
270 "c0_taglo_i", "c0_taghi_i", "c0_errorepc", "c0_desave",
271 };
272
273 static const struct mips_cp0sel_name mips_cp0sel_names_sb1[] =
274 {
275 { 16, 1, "c0_config1" },
276 { 18, 1, "c0_watchlo,1" },
277 { 19, 1, "c0_watchhi,1" },
278 { 22, 0, "c0_perftrace" },
279 { 23, 3, "c0_edebug" },
280 { 25, 1, "c0_perfcnt,1" },
281 { 25, 2, "c0_perfcnt,2" },
282 { 25, 3, "c0_perfcnt,3" },
283 { 25, 4, "c0_perfcnt,4" },
284 { 25, 5, "c0_perfcnt,5" },
285 { 25, 6, "c0_perfcnt,6" },
286 { 25, 7, "c0_perfcnt,7" },
287 { 26, 1, "c0_buserr_pa" },
288 { 27, 1, "c0_cacheerr_d" },
289 { 27, 3, "c0_cacheerr_d_pa" },
290 { 28, 1, "c0_datalo_i" },
291 { 28, 2, "c0_taglo_d" },
292 { 28, 3, "c0_datalo_d" },
293 { 29, 1, "c0_datahi_i" },
294 { 29, 2, "c0_taghi_d" },
295 { 29, 3, "c0_datahi_d" },
296 };
297
298 static const char * const mips_hwr_names_numeric[32] =
299 {
300 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
301 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
302 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
303 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
304 };
305
306 static const char * const mips_hwr_names_mips3264r2[32] =
307 {
308 "hwr_cpunum", "hwr_synci_step", "hwr_cc", "hwr_ccres",
309 "$4", "$5", "$6", "$7",
310 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
311 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
312 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
313 };
314
315 struct mips_abi_choice
316 {
317 const char * name;
318 const char * const *gpr_names;
319 const char * const *fpr_names;
320 };
321
322 struct mips_abi_choice mips_abi_choices[] =
323 {
324 { "numeric", mips_gpr_names_numeric, mips_fpr_names_numeric },
325 { "32", mips_gpr_names_oldabi, mips_fpr_names_32 },
326 { "n32", mips_gpr_names_newabi, mips_fpr_names_n32 },
327 { "64", mips_gpr_names_newabi, mips_fpr_names_64 },
328 };
329
330 struct mips_arch_choice
331 {
332 const char *name;
333 int bfd_mach_valid;
334 unsigned long bfd_mach;
335 int processor;
336 int isa;
337 const char * const *cp0_names;
338 const struct mips_cp0sel_name *cp0sel_names;
339 unsigned int cp0sel_names_len;
340 const char * const *hwr_names;
341 };
342
343 const struct mips_arch_choice mips_arch_choices[] =
344 {
345 { "numeric", 0, 0, 0, 0,
346 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
347
348 { "r3000", 1, bfd_mach_mips3000, CPU_R3000, ISA_MIPS1,
349 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
350 { "r3900", 1, bfd_mach_mips3900, CPU_R3900, ISA_MIPS1,
351 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
352 { "r4000", 1, bfd_mach_mips4000, CPU_R4000, ISA_MIPS3,
353 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
354 { "r4010", 1, bfd_mach_mips4010, CPU_R4010, ISA_MIPS2,
355 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
356 { "vr4100", 1, bfd_mach_mips4100, CPU_VR4100, ISA_MIPS3,
357 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
358 { "vr4111", 1, bfd_mach_mips4111, CPU_R4111, ISA_MIPS3,
359 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
360 { "vr4120", 1, bfd_mach_mips4120, CPU_VR4120, ISA_MIPS3,
361 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
362 { "r4300", 1, bfd_mach_mips4300, CPU_R4300, ISA_MIPS3,
363 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
364 { "r4400", 1, bfd_mach_mips4400, CPU_R4400, ISA_MIPS3,
365 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
366 { "r4600", 1, bfd_mach_mips4600, CPU_R4600, ISA_MIPS3,
367 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
368 { "r4650", 1, bfd_mach_mips4650, CPU_R4650, ISA_MIPS3,
369 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
370 { "r5000", 1, bfd_mach_mips5000, CPU_R5000, ISA_MIPS4,
371 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
372 { "vr5400", 1, bfd_mach_mips5400, CPU_VR5400, ISA_MIPS4,
373 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
374 { "vr5500", 1, bfd_mach_mips5500, CPU_VR5500, ISA_MIPS4,
375 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
376 { "r6000", 1, bfd_mach_mips6000, CPU_R6000, ISA_MIPS2,
377 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
378 { "rm7000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4,
379 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
380 { "rm9000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4,
381 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
382 { "r8000", 1, bfd_mach_mips8000, CPU_R8000, ISA_MIPS4,
383 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
384 { "r10000", 1, bfd_mach_mips10000, CPU_R10000, ISA_MIPS4,
385 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
386 { "r12000", 1, bfd_mach_mips12000, CPU_R12000, ISA_MIPS4,
387 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
388 { "mips5", 1, bfd_mach_mips5, CPU_MIPS5, ISA_MIPS5,
389 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
390
391 /* For stock MIPS32, disassemble all applicable MIPS-specified ASEs.
392 Note that MIPS-3D and MDMX are not applicable to MIPS32. (See
393 _MIPS32 Architecture For Programmers Volume I: Introduction to the
394 MIPS32 Architecture_ (MIPS Document Number MD00082, Revision 0.95),
395 page 1. */
396 { "mips32", 1, bfd_mach_mipsisa32, CPU_MIPS32,
397 ISA_MIPS32 | INSN_MIPS16 | INSN_SMARTMIPS,
398 mips_cp0_names_mips3264,
399 mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
400 mips_hwr_names_numeric },
401
402 { "mips32r2", 1, bfd_mach_mipsisa32r2, CPU_MIPS32R2,
403 (ISA_MIPS32R2 | INSN_MIPS16 | INSN_SMARTMIPS | INSN_DSP | INSN_MIPS3D
404 | INSN_MT),
405 mips_cp0_names_mips3264r2,
406 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
407 mips_hwr_names_mips3264r2 },
408
409 /* For stock MIPS64, disassemble all applicable MIPS-specified ASEs. */
410 { "mips64", 1, bfd_mach_mipsisa64, CPU_MIPS64,
411 ISA_MIPS64 | INSN_MIPS16 | INSN_MIPS3D | INSN_MDMX,
412 mips_cp0_names_mips3264,
413 mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
414 mips_hwr_names_numeric },
415
416 { "mips64r2", 1, bfd_mach_mipsisa64r2, CPU_MIPS64R2,
417 (ISA_MIPS64R2 | INSN_MIPS16 | INSN_MIPS3D | INSN_DSP | INSN_DSP64
418 | INSN_MT | INSN_MDMX),
419 mips_cp0_names_mips3264r2,
420 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
421 mips_hwr_names_mips3264r2 },
422
423 { "sb1", 1, bfd_mach_mips_sb1, CPU_SB1,
424 ISA_MIPS64 | INSN_MIPS3D | INSN_SB1,
425 mips_cp0_names_sb1,
426 mips_cp0sel_names_sb1, ARRAY_SIZE (mips_cp0sel_names_sb1),
427 mips_hwr_names_numeric },
428
429 /* This entry, mips16, is here only for ISA/processor selection; do
430 not print its name. */
431 { "", 1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS3 | INSN_MIPS16,
432 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
433 };
434
435 /* ISA and processor type to disassemble for, and register names to use.
436 set_default_mips_dis_options and parse_mips_dis_options fill in these
437 values. */
438 static int mips_processor;
439 static int mips_isa;
440 static const char * const *mips_gpr_names;
441 static const char * const *mips_fpr_names;
442 static const char * const *mips_cp0_names;
443 static const struct mips_cp0sel_name *mips_cp0sel_names;
444 static int mips_cp0sel_names_len;
445 static const char * const *mips_hwr_names;
446
447 /* Other options */
448 static int no_aliases; /* If set disassemble as most general inst. */
449 \f
450 static const struct mips_abi_choice *
451 choose_abi_by_name (const char *name, unsigned int namelen)
452 {
453 const struct mips_abi_choice *c;
454 unsigned int i;
455
456 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_abi_choices) && c == NULL; i++)
457 if (strncmp (mips_abi_choices[i].name, name, namelen) == 0
458 && strlen (mips_abi_choices[i].name) == namelen)
459 c = &mips_abi_choices[i];
460
461 return c;
462 }
463
464 static const struct mips_arch_choice *
465 choose_arch_by_name (const char *name, unsigned int namelen)
466 {
467 const struct mips_arch_choice *c = NULL;
468 unsigned int i;
469
470 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++)
471 if (strncmp (mips_arch_choices[i].name, name, namelen) == 0
472 && strlen (mips_arch_choices[i].name) == namelen)
473 c = &mips_arch_choices[i];
474
475 return c;
476 }
477
478 static const struct mips_arch_choice *
479 choose_arch_by_number (unsigned long mach)
480 {
481 static unsigned long hint_bfd_mach;
482 static const struct mips_arch_choice *hint_arch_choice;
483 const struct mips_arch_choice *c;
484 unsigned int i;
485
486 /* We optimize this because even if the user specifies no
487 flags, this will be done for every instruction! */
488 if (hint_bfd_mach == mach
489 && hint_arch_choice != NULL
490 && hint_arch_choice->bfd_mach == hint_bfd_mach)
491 return hint_arch_choice;
492
493 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++)
494 {
495 if (mips_arch_choices[i].bfd_mach_valid
496 && mips_arch_choices[i].bfd_mach == mach)
497 {
498 c = &mips_arch_choices[i];
499 hint_bfd_mach = mach;
500 hint_arch_choice = c;
501 }
502 }
503 return c;
504 }
505
506 /* Check if the object uses NewABI conventions. */
507
508 static int
509 is_newabi (Elf_Internal_Ehdr *header)
510 {
511 /* There are no old-style ABIs which use 64-bit ELF. */
512 if (header->e_ident[EI_CLASS] == ELFCLASS64)
513 return 1;
514
515 /* If a 32-bit ELF file, n32 is a new-style ABI. */
516 if ((header->e_flags & EF_MIPS_ABI2) != 0)
517 return 1;
518
519 return 0;
520 }
521
522 static void
523 set_default_mips_dis_options (struct disassemble_info *info)
524 {
525 const struct mips_arch_choice *chosen_arch;
526
527 /* Defaults: mipsIII/r3000 (?!), (o)32-style ("oldabi") GPR names,
528 and numeric FPR, CP0 register, and HWR names. */
529 mips_isa = ISA_MIPS3;
530 mips_processor = CPU_R3000;
531 mips_gpr_names = mips_gpr_names_oldabi;
532 mips_fpr_names = mips_fpr_names_numeric;
533 mips_cp0_names = mips_cp0_names_numeric;
534 mips_cp0sel_names = NULL;
535 mips_cp0sel_names_len = 0;
536 mips_hwr_names = mips_hwr_names_numeric;
537 no_aliases = 0;
538
539 /* If an ELF "newabi" binary, use the n32/(n)64 GPR names. */
540 if (info->flavour == bfd_target_elf_flavour && info->section != NULL)
541 {
542 Elf_Internal_Ehdr *header;
543
544 header = elf_elfheader (info->section->owner);
545 if (is_newabi (header))
546 mips_gpr_names = mips_gpr_names_newabi;
547 }
548
549 /* Set ISA, architecture, and cp0 register names as best we can. */
550 #if ! SYMTAB_AVAILABLE
551 /* This is running out on a target machine, not in a host tool.
552 FIXME: Where does mips_target_info come from? */
553 target_processor = mips_target_info.processor;
554 mips_isa = mips_target_info.isa;
555 #else
556 chosen_arch = choose_arch_by_number (info->mach);
557 if (chosen_arch != NULL)
558 {
559 mips_processor = chosen_arch->processor;
560 mips_isa = chosen_arch->isa;
561 mips_cp0_names = chosen_arch->cp0_names;
562 mips_cp0sel_names = chosen_arch->cp0sel_names;
563 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
564 mips_hwr_names = chosen_arch->hwr_names;
565 }
566 #endif
567 }
568
569 static void
570 parse_mips_dis_option (const char *option, unsigned int len)
571 {
572 unsigned int i, optionlen, vallen;
573 const char *val;
574 const struct mips_abi_choice *chosen_abi;
575 const struct mips_arch_choice *chosen_arch;
576
577 /* Try to match options that are simple flags */
578 if (strncmp (option, "no-aliases", 10) == 0)
579 {
580 no_aliases = 1;
581 return;
582 }
583
584 /* Look for the = that delimits the end of the option name. */
585 for (i = 0; i < len; i++)
586 if (option[i] == '=')
587 break;
588
589 if (i == 0) /* Invalid option: no name before '='. */
590 return;
591 if (i == len) /* Invalid option: no '='. */
592 return;
593 if (i == (len - 1)) /* Invalid option: no value after '='. */
594 return;
595
596 optionlen = i;
597 val = option + (optionlen + 1);
598 vallen = len - (optionlen + 1);
599
600 if (strncmp ("gpr-names", option, optionlen) == 0
601 && strlen ("gpr-names") == optionlen)
602 {
603 chosen_abi = choose_abi_by_name (val, vallen);
604 if (chosen_abi != NULL)
605 mips_gpr_names = chosen_abi->gpr_names;
606 return;
607 }
608
609 if (strncmp ("fpr-names", option, optionlen) == 0
610 && strlen ("fpr-names") == optionlen)
611 {
612 chosen_abi = choose_abi_by_name (val, vallen);
613 if (chosen_abi != NULL)
614 mips_fpr_names = chosen_abi->fpr_names;
615 return;
616 }
617
618 if (strncmp ("cp0-names", option, optionlen) == 0
619 && strlen ("cp0-names") == optionlen)
620 {
621 chosen_arch = choose_arch_by_name (val, vallen);
622 if (chosen_arch != NULL)
623 {
624 mips_cp0_names = chosen_arch->cp0_names;
625 mips_cp0sel_names = chosen_arch->cp0sel_names;
626 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
627 }
628 return;
629 }
630
631 if (strncmp ("hwr-names", option, optionlen) == 0
632 && strlen ("hwr-names") == optionlen)
633 {
634 chosen_arch = choose_arch_by_name (val, vallen);
635 if (chosen_arch != NULL)
636 mips_hwr_names = chosen_arch->hwr_names;
637 return;
638 }
639
640 if (strncmp ("reg-names", option, optionlen) == 0
641 && strlen ("reg-names") == optionlen)
642 {
643 /* We check both ABI and ARCH here unconditionally, so
644 that "numeric" will do the desirable thing: select
645 numeric register names for all registers. Other than
646 that, a given name probably won't match both. */
647 chosen_abi = choose_abi_by_name (val, vallen);
648 if (chosen_abi != NULL)
649 {
650 mips_gpr_names = chosen_abi->gpr_names;
651 mips_fpr_names = chosen_abi->fpr_names;
652 }
653 chosen_arch = choose_arch_by_name (val, vallen);
654 if (chosen_arch != NULL)
655 {
656 mips_cp0_names = chosen_arch->cp0_names;
657 mips_cp0sel_names = chosen_arch->cp0sel_names;
658 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
659 mips_hwr_names = chosen_arch->hwr_names;
660 }
661 return;
662 }
663
664 /* Invalid option. */
665 }
666
667 static void
668 parse_mips_dis_options (const char *options)
669 {
670 const char *option_end;
671
672 if (options == NULL)
673 return;
674
675 while (*options != '\0')
676 {
677 /* Skip empty options. */
678 if (*options == ',')
679 {
680 options++;
681 continue;
682 }
683
684 /* We know that *options is neither NUL or a comma. */
685 option_end = options + 1;
686 while (*option_end != ',' && *option_end != '\0')
687 option_end++;
688
689 parse_mips_dis_option (options, option_end - options);
690
691 /* Go on to the next one. If option_end points to a comma, it
692 will be skipped above. */
693 options = option_end;
694 }
695 }
696
697 static const struct mips_cp0sel_name *
698 lookup_mips_cp0sel_name (const struct mips_cp0sel_name *names,
699 unsigned int len,
700 unsigned int cp0reg,
701 unsigned int sel)
702 {
703 unsigned int i;
704
705 for (i = 0; i < len; i++)
706 if (names[i].cp0reg == cp0reg && names[i].sel == sel)
707 return &names[i];
708 return NULL;
709 }
710 \f
711 /* Print insn arguments for 32/64-bit code. */
712
713 static void
714 print_insn_args (const char *d,
715 register unsigned long int l,
716 bfd_vma pc,
717 struct disassemble_info *info,
718 const struct mips_opcode *opp)
719 {
720 int op, delta;
721 unsigned int lsb, msb, msbd;
722
723 lsb = 0;
724
725 for (; *d != '\0'; d++)
726 {
727 switch (*d)
728 {
729 case ',':
730 case '(':
731 case ')':
732 case '[':
733 case ']':
734 (*info->fprintf_func) (info->stream, "%c", *d);
735 break;
736
737 case '+':
738 /* Extension character; switch for second char. */
739 d++;
740 switch (*d)
741 {
742 case '\0':
743 /* xgettext:c-format */
744 (*info->fprintf_func) (info->stream,
745 _("# internal error, incomplete extension sequence (+)"));
746 return;
747
748 case 'A':
749 lsb = (l >> OP_SH_SHAMT) & OP_MASK_SHAMT;
750 (*info->fprintf_func) (info->stream, "0x%x", lsb);
751 break;
752
753 case 'B':
754 msb = (l >> OP_SH_INSMSB) & OP_MASK_INSMSB;
755 (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1);
756 break;
757
758 case '1':
759 (*info->fprintf_func) (info->stream, "0x%lx",
760 (l >> OP_SH_UDI1) & OP_MASK_UDI1);
761 break;
762
763 case '2':
764 (*info->fprintf_func) (info->stream, "0x%lx",
765 (l >> OP_SH_UDI2) & OP_MASK_UDI2);
766 break;
767
768 case '3':
769 (*info->fprintf_func) (info->stream, "0x%lx",
770 (l >> OP_SH_UDI3) & OP_MASK_UDI3);
771 break;
772
773 case '4':
774 (*info->fprintf_func) (info->stream, "0x%lx",
775 (l >> OP_SH_UDI4) & OP_MASK_UDI4);
776 break;
777
778 case 'C':
779 case 'H':
780 msbd = (l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD;
781 (*info->fprintf_func) (info->stream, "0x%x", msbd + 1);
782 break;
783
784 case 'D':
785 {
786 const struct mips_cp0sel_name *n;
787 unsigned int cp0reg, sel;
788
789 cp0reg = (l >> OP_SH_RD) & OP_MASK_RD;
790 sel = (l >> OP_SH_SEL) & OP_MASK_SEL;
791
792 /* CP0 register including 'sel' code for mtcN (et al.), to be
793 printed textually if known. If not known, print both
794 CP0 register name and sel numerically since CP0 register
795 with sel 0 may have a name unrelated to register being
796 printed. */
797 n = lookup_mips_cp0sel_name(mips_cp0sel_names,
798 mips_cp0sel_names_len, cp0reg, sel);
799 if (n != NULL)
800 (*info->fprintf_func) (info->stream, "%s", n->name);
801 else
802 (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel);
803 break;
804 }
805
806 case 'E':
807 lsb = ((l >> OP_SH_SHAMT) & OP_MASK_SHAMT) + 32;
808 (*info->fprintf_func) (info->stream, "0x%x", lsb);
809 break;
810
811 case 'F':
812 msb = ((l >> OP_SH_INSMSB) & OP_MASK_INSMSB) + 32;
813 (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1);
814 break;
815
816 case 'G':
817 msbd = ((l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD) + 32;
818 (*info->fprintf_func) (info->stream, "0x%x", msbd + 1);
819 break;
820
821 case 't': /* Coprocessor 0 reg name */
822 (*info->fprintf_func) (info->stream, "%s",
823 mips_cp0_names[(l >> OP_SH_RT) &
824 OP_MASK_RT]);
825 break;
826
827 case 'T': /* Coprocessor 0 reg name */
828 {
829 const struct mips_cp0sel_name *n;
830 unsigned int cp0reg, sel;
831
832 cp0reg = (l >> OP_SH_RT) & OP_MASK_RT;
833 sel = (l >> OP_SH_SEL) & OP_MASK_SEL;
834
835 /* CP0 register including 'sel' code for mftc0, to be
836 printed textually if known. If not known, print both
837 CP0 register name and sel numerically since CP0 register
838 with sel 0 may have a name unrelated to register being
839 printed. */
840 n = lookup_mips_cp0sel_name(mips_cp0sel_names,
841 mips_cp0sel_names_len, cp0reg, sel);
842 if (n != NULL)
843 (*info->fprintf_func) (info->stream, "%s", n->name);
844 else
845 (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel);
846 break;
847 }
848
849 default:
850 /* xgettext:c-format */
851 (*info->fprintf_func) (info->stream,
852 _("# internal error, undefined extension sequence (+%c)"),
853 *d);
854 return;
855 }
856 break;
857
858 case '3':
859 (*info->fprintf_func) (info->stream, "0x%lx",
860 (l >> OP_SH_SA3) & OP_MASK_SA3);
861 break;
862
863 case '4':
864 (*info->fprintf_func) (info->stream, "0x%lx",
865 (l >> OP_SH_SA4) & OP_MASK_SA4);
866 break;
867
868 case '5':
869 (*info->fprintf_func) (info->stream, "0x%lx",
870 (l >> OP_SH_IMM8) & OP_MASK_IMM8);
871 break;
872
873 case '6':
874 (*info->fprintf_func) (info->stream, "0x%lx",
875 (l >> OP_SH_RS) & OP_MASK_RS);
876 break;
877
878 case '7':
879 (*info->fprintf_func) (info->stream, "$ac%ld",
880 (l >> OP_SH_DSPACC) & OP_MASK_DSPACC);
881 break;
882
883 case '8':
884 (*info->fprintf_func) (info->stream, "0x%lx",
885 (l >> OP_SH_WRDSP) & OP_MASK_WRDSP);
886 break;
887
888 case '9':
889 (*info->fprintf_func) (info->stream, "$ac%ld",
890 (l >> OP_SH_DSPACC_S) & OP_MASK_DSPACC_S);
891 break;
892
893 case '0': /* dsp 6-bit signed immediate in bit 20 */
894 delta = ((l >> OP_SH_DSPSFT) & OP_MASK_DSPSFT);
895 if (delta & 0x20) /* test sign bit */
896 delta |= ~OP_MASK_DSPSFT;
897 (*info->fprintf_func) (info->stream, "%d", delta);
898 break;
899
900 case ':': /* dsp 7-bit signed immediate in bit 19 */
901 delta = ((l >> OP_SH_DSPSFT_7) & OP_MASK_DSPSFT_7);
902 if (delta & 0x40) /* test sign bit */
903 delta |= ~OP_MASK_DSPSFT_7;
904 (*info->fprintf_func) (info->stream, "%d", delta);
905 break;
906
907 case '\'':
908 (*info->fprintf_func) (info->stream, "0x%lx",
909 (l >> OP_SH_RDDSP) & OP_MASK_RDDSP);
910 break;
911
912 case '@': /* dsp 10-bit signed immediate in bit 16 */
913 delta = ((l >> OP_SH_IMM10) & OP_MASK_IMM10);
914 if (delta & 0x200) /* test sign bit */
915 delta |= ~OP_MASK_IMM10;
916 (*info->fprintf_func) (info->stream, "%d", delta);
917 break;
918
919 case '!':
920 (*info->fprintf_func) (info->stream, "%ld",
921 (l >> OP_SH_MT_U) & OP_MASK_MT_U);
922 break;
923
924 case '$':
925 (*info->fprintf_func) (info->stream, "%ld",
926 (l >> OP_SH_MT_H) & OP_MASK_MT_H);
927 break;
928
929 case '*':
930 (*info->fprintf_func) (info->stream, "$ac%ld",
931 (l >> OP_SH_MTACC_T) & OP_MASK_MTACC_T);
932 break;
933
934 case '&':
935 (*info->fprintf_func) (info->stream, "$ac%ld",
936 (l >> OP_SH_MTACC_D) & OP_MASK_MTACC_D);
937 break;
938
939 case 'g':
940 /* Coprocessor register for CTTC1, MTTC2, MTHC2, CTTC2. */
941 (*info->fprintf_func) (info->stream, "$%ld",
942 (l >> OP_SH_RD) & OP_MASK_RD);
943 break;
944
945 case 's':
946 case 'b':
947 case 'r':
948 case 'v':
949 (*info->fprintf_func) (info->stream, "%s",
950 mips_gpr_names[(l >> OP_SH_RS) & OP_MASK_RS]);
951 break;
952
953 case 't':
954 case 'w':
955 (*info->fprintf_func) (info->stream, "%s",
956 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
957 break;
958
959 case 'i':
960 case 'u':
961 (*info->fprintf_func) (info->stream, "0x%lx",
962 (l >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE);
963 break;
964
965 case 'j': /* Same as i, but sign-extended. */
966 case 'o':
967 delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA;
968 if (delta & 0x8000)
969 delta |= ~0xffff;
970 (*info->fprintf_func) (info->stream, "%d",
971 delta);
972 break;
973
974 case 'h':
975 (*info->fprintf_func) (info->stream, "0x%x",
976 (unsigned int) ((l >> OP_SH_PREFX)
977 & OP_MASK_PREFX));
978 break;
979
980 case 'k':
981 (*info->fprintf_func) (info->stream, "0x%x",
982 (unsigned int) ((l >> OP_SH_CACHE)
983 & OP_MASK_CACHE));
984 break;
985
986 case 'a':
987 info->target = (((pc + 4) & ~(bfd_vma) 0x0fffffff)
988 | (((l >> OP_SH_TARGET) & OP_MASK_TARGET) << 2));
989 /* For gdb disassembler, force odd address on jalx. */
990 if (info->flavour == bfd_target_unknown_flavour
991 && strcmp (opp->name, "jalx") == 0)
992 info->target |= 1;
993 (*info->print_address_func) (info->target, info);
994 break;
995
996 case 'p':
997 /* Sign extend the displacement. */
998 delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA;
999 if (delta & 0x8000)
1000 delta |= ~0xffff;
1001 info->target = (delta << 2) + pc + INSNLEN;
1002 (*info->print_address_func) (info->target, info);
1003 break;
1004
1005 case 'd':
1006 (*info->fprintf_func) (info->stream, "%s",
1007 mips_gpr_names[(l >> OP_SH_RD) & OP_MASK_RD]);
1008 break;
1009
1010 case 'U':
1011 {
1012 /* First check for both rd and rt being equal. */
1013 unsigned int reg = (l >> OP_SH_RD) & OP_MASK_RD;
1014 if (reg == ((l >> OP_SH_RT) & OP_MASK_RT))
1015 (*info->fprintf_func) (info->stream, "%s",
1016 mips_gpr_names[reg]);
1017 else
1018 {
1019 /* If one is zero use the other. */
1020 if (reg == 0)
1021 (*info->fprintf_func) (info->stream, "%s",
1022 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
1023 else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0)
1024 (*info->fprintf_func) (info->stream, "%s",
1025 mips_gpr_names[reg]);
1026 else /* Bogus, result depends on processor. */
1027 (*info->fprintf_func) (info->stream, "%s or %s",
1028 mips_gpr_names[reg],
1029 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
1030 }
1031 }
1032 break;
1033
1034 case 'z':
1035 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]);
1036 break;
1037
1038 case '<':
1039 (*info->fprintf_func) (info->stream, "0x%lx",
1040 (l >> OP_SH_SHAMT) & OP_MASK_SHAMT);
1041 break;
1042
1043 case 'c':
1044 (*info->fprintf_func) (info->stream, "0x%lx",
1045 (l >> OP_SH_CODE) & OP_MASK_CODE);
1046 break;
1047
1048 case 'q':
1049 (*info->fprintf_func) (info->stream, "0x%lx",
1050 (l >> OP_SH_CODE2) & OP_MASK_CODE2);
1051 break;
1052
1053 case 'C':
1054 (*info->fprintf_func) (info->stream, "0x%lx",
1055 (l >> OP_SH_COPZ) & OP_MASK_COPZ);
1056 break;
1057
1058 case 'B':
1059 (*info->fprintf_func) (info->stream, "0x%lx",
1060
1061 (l >> OP_SH_CODE20) & OP_MASK_CODE20);
1062 break;
1063
1064 case 'J':
1065 (*info->fprintf_func) (info->stream, "0x%lx",
1066 (l >> OP_SH_CODE19) & OP_MASK_CODE19);
1067 break;
1068
1069 case 'S':
1070 case 'V':
1071 (*info->fprintf_func) (info->stream, "%s",
1072 mips_fpr_names[(l >> OP_SH_FS) & OP_MASK_FS]);
1073 break;
1074
1075 case 'T':
1076 case 'W':
1077 (*info->fprintf_func) (info->stream, "%s",
1078 mips_fpr_names[(l >> OP_SH_FT) & OP_MASK_FT]);
1079 break;
1080
1081 case 'D':
1082 (*info->fprintf_func) (info->stream, "%s",
1083 mips_fpr_names[(l >> OP_SH_FD) & OP_MASK_FD]);
1084 break;
1085
1086 case 'R':
1087 (*info->fprintf_func) (info->stream, "%s",
1088 mips_fpr_names[(l >> OP_SH_FR) & OP_MASK_FR]);
1089 break;
1090
1091 case 'E':
1092 /* Coprocessor register for lwcN instructions, et al.
1093
1094 Note that there is no load/store cp0 instructions, and
1095 that FPU (cp1) instructions disassemble this field using
1096 'T' format. Therefore, until we gain understanding of
1097 cp2 register names, we can simply print the register
1098 numbers. */
1099 (*info->fprintf_func) (info->stream, "$%ld",
1100 (l >> OP_SH_RT) & OP_MASK_RT);
1101 break;
1102
1103 case 'G':
1104 /* Coprocessor register for mtcN instructions, et al. Note
1105 that FPU (cp1) instructions disassemble this field using
1106 'S' format. Therefore, we only need to worry about cp0,
1107 cp2, and cp3. */
1108 op = (l >> OP_SH_OP) & OP_MASK_OP;
1109 if (op == OP_OP_COP0)
1110 (*info->fprintf_func) (info->stream, "%s",
1111 mips_cp0_names[(l >> OP_SH_RD) & OP_MASK_RD]);
1112 else
1113 (*info->fprintf_func) (info->stream, "$%ld",
1114 (l >> OP_SH_RD) & OP_MASK_RD);
1115 break;
1116
1117 case 'K':
1118 (*info->fprintf_func) (info->stream, "%s",
1119 mips_hwr_names[(l >> OP_SH_RD) & OP_MASK_RD]);
1120 break;
1121
1122 case 'N':
1123 (*info->fprintf_func) (info->stream,
1124 ((opp->pinfo & (FP_D | FP_S)) != 0
1125 ? "$fcc%ld" : "$cc%ld"),
1126 (l >> OP_SH_BCC) & OP_MASK_BCC);
1127 break;
1128
1129 case 'M':
1130 (*info->fprintf_func) (info->stream, "$fcc%ld",
1131 (l >> OP_SH_CCC) & OP_MASK_CCC);
1132 break;
1133
1134 case 'P':
1135 (*info->fprintf_func) (info->stream, "%ld",
1136 (l >> OP_SH_PERFREG) & OP_MASK_PERFREG);
1137 break;
1138
1139 case 'e':
1140 (*info->fprintf_func) (info->stream, "%ld",
1141 (l >> OP_SH_VECBYTE) & OP_MASK_VECBYTE);
1142 break;
1143
1144 case '%':
1145 (*info->fprintf_func) (info->stream, "%ld",
1146 (l >> OP_SH_VECALIGN) & OP_MASK_VECALIGN);
1147 break;
1148
1149 case 'H':
1150 (*info->fprintf_func) (info->stream, "%ld",
1151 (l >> OP_SH_SEL) & OP_MASK_SEL);
1152 break;
1153
1154 case 'O':
1155 (*info->fprintf_func) (info->stream, "%ld",
1156 (l >> OP_SH_ALN) & OP_MASK_ALN);
1157 break;
1158
1159 case 'Q':
1160 {
1161 unsigned int vsel = (l >> OP_SH_VSEL) & OP_MASK_VSEL;
1162
1163 if ((vsel & 0x10) == 0)
1164 {
1165 int fmt;
1166
1167 vsel &= 0x0f;
1168 for (fmt = 0; fmt < 3; fmt++, vsel >>= 1)
1169 if ((vsel & 1) == 0)
1170 break;
1171 (*info->fprintf_func) (info->stream, "$v%ld[%d]",
1172 (l >> OP_SH_FT) & OP_MASK_FT,
1173 vsel >> 1);
1174 }
1175 else if ((vsel & 0x08) == 0)
1176 {
1177 (*info->fprintf_func) (info->stream, "$v%ld",
1178 (l >> OP_SH_FT) & OP_MASK_FT);
1179 }
1180 else
1181 {
1182 (*info->fprintf_func) (info->stream, "0x%lx",
1183 (l >> OP_SH_FT) & OP_MASK_FT);
1184 }
1185 }
1186 break;
1187
1188 case 'X':
1189 (*info->fprintf_func) (info->stream, "$v%ld",
1190 (l >> OP_SH_FD) & OP_MASK_FD);
1191 break;
1192
1193 case 'Y':
1194 (*info->fprintf_func) (info->stream, "$v%ld",
1195 (l >> OP_SH_FS) & OP_MASK_FS);
1196 break;
1197
1198 case 'Z':
1199 (*info->fprintf_func) (info->stream, "$v%ld",
1200 (l >> OP_SH_FT) & OP_MASK_FT);
1201 break;
1202
1203 default:
1204 /* xgettext:c-format */
1205 (*info->fprintf_func) (info->stream,
1206 _("# internal error, undefined modifier(%c)"),
1207 *d);
1208 return;
1209 }
1210 }
1211 }
1212 \f
1213 /* Print the mips instruction at address MEMADDR in debugged memory,
1214 on using INFO. Returns length of the instruction, in bytes, which is
1215 always INSNLEN. BIGENDIAN must be 1 if this is big-endian code, 0 if
1216 this is little-endian code. */
1217
1218 static int
1219 print_insn_mips (bfd_vma memaddr,
1220 unsigned long int word,
1221 struct disassemble_info *info)
1222 {
1223 const struct mips_opcode *op;
1224 static bfd_boolean init = 0;
1225 static const struct mips_opcode *mips_hash[OP_MASK_OP + 1];
1226
1227 /* Build a hash table to shorten the search time. */
1228 if (! init)
1229 {
1230 unsigned int i;
1231
1232 for (i = 0; i <= OP_MASK_OP; i++)
1233 {
1234 for (op = mips_opcodes; op < &mips_opcodes[NUMOPCODES]; op++)
1235 {
1236 if (op->pinfo == INSN_MACRO
1237 || (no_aliases && (op->pinfo2 & INSN2_ALIAS)))
1238 continue;
1239 if (i == ((op->match >> OP_SH_OP) & OP_MASK_OP))
1240 {
1241 mips_hash[i] = op;
1242 break;
1243 }
1244 }
1245 }
1246
1247 init = 1;
1248 }
1249
1250 info->bytes_per_chunk = INSNLEN;
1251 info->display_endian = info->endian;
1252 info->insn_info_valid = 1;
1253 info->branch_delay_insns = 0;
1254 info->data_size = 0;
1255 info->insn_type = dis_nonbranch;
1256 info->target = 0;
1257 info->target2 = 0;
1258
1259 op = mips_hash[(word >> OP_SH_OP) & OP_MASK_OP];
1260 if (op != NULL)
1261 {
1262 for (; op < &mips_opcodes[NUMOPCODES]; op++)
1263 {
1264 if (op->pinfo != INSN_MACRO
1265 && !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
1266 && (word & op->mask) == op->match)
1267 {
1268 const char *d;
1269
1270 /* We always allow to disassemble the jalx instruction. */
1271 if (! OPCODE_IS_MEMBER (op, mips_isa, mips_processor)
1272 && strcmp (op->name, "jalx"))
1273 continue;
1274
1275 /* Figure out instruction type and branch delay information. */
1276 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
1277 {
1278 if ((info->insn_type & INSN_WRITE_GPR_31) != 0)
1279 info->insn_type = dis_jsr;
1280 else
1281 info->insn_type = dis_branch;
1282 info->branch_delay_insns = 1;
1283 }
1284 else if ((op->pinfo & (INSN_COND_BRANCH_DELAY
1285 | INSN_COND_BRANCH_LIKELY)) != 0)
1286 {
1287 if ((info->insn_type & INSN_WRITE_GPR_31) != 0)
1288 info->insn_type = dis_condjsr;
1289 else
1290 info->insn_type = dis_condbranch;
1291 info->branch_delay_insns = 1;
1292 }
1293 else if ((op->pinfo & (INSN_STORE_MEMORY
1294 | INSN_LOAD_MEMORY_DELAY)) != 0)
1295 info->insn_type = dis_dref;
1296
1297 (*info->fprintf_func) (info->stream, "%s", op->name);
1298
1299 d = op->args;
1300 if (d != NULL && *d != '\0')
1301 {
1302 (*info->fprintf_func) (info->stream, "\t");
1303 print_insn_args (d, word, memaddr, info, op);
1304 }
1305
1306 return INSNLEN;
1307 }
1308 }
1309 }
1310
1311 /* Handle undefined instructions. */
1312 info->insn_type = dis_noninsn;
1313 (*info->fprintf_func) (info->stream, "0x%lx", word);
1314 return INSNLEN;
1315 }
1316 \f
1317 /* Disassemble an operand for a mips16 instruction. */
1318
1319 static void
1320 print_mips16_insn_arg (char type,
1321 const struct mips_opcode *op,
1322 int l,
1323 bfd_boolean use_extend,
1324 int extend,
1325 bfd_vma memaddr,
1326 struct disassemble_info *info)
1327 {
1328 switch (type)
1329 {
1330 case ',':
1331 case '(':
1332 case ')':
1333 (*info->fprintf_func) (info->stream, "%c", type);
1334 break;
1335
1336 case 'y':
1337 case 'w':
1338 (*info->fprintf_func) (info->stream, "%s",
1339 mips16_reg_names(((l >> MIPS16OP_SH_RY)
1340 & MIPS16OP_MASK_RY)));
1341 break;
1342
1343 case 'x':
1344 case 'v':
1345 (*info->fprintf_func) (info->stream, "%s",
1346 mips16_reg_names(((l >> MIPS16OP_SH_RX)
1347 & MIPS16OP_MASK_RX)));
1348 break;
1349
1350 case 'z':
1351 (*info->fprintf_func) (info->stream, "%s",
1352 mips16_reg_names(((l >> MIPS16OP_SH_RZ)
1353 & MIPS16OP_MASK_RZ)));
1354 break;
1355
1356 case 'Z':
1357 (*info->fprintf_func) (info->stream, "%s",
1358 mips16_reg_names(((l >> MIPS16OP_SH_MOVE32Z)
1359 & MIPS16OP_MASK_MOVE32Z)));
1360 break;
1361
1362 case '0':
1363 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]);
1364 break;
1365
1366 case 'S':
1367 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[29]);
1368 break;
1369
1370 case 'P':
1371 (*info->fprintf_func) (info->stream, "$pc");
1372 break;
1373
1374 case 'R':
1375 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[31]);
1376 break;
1377
1378 case 'X':
1379 (*info->fprintf_func) (info->stream, "%s",
1380 mips_gpr_names[((l >> MIPS16OP_SH_REGR32)
1381 & MIPS16OP_MASK_REGR32)]);
1382 break;
1383
1384 case 'Y':
1385 (*info->fprintf_func) (info->stream, "%s",
1386 mips_gpr_names[MIPS16OP_EXTRACT_REG32R (l)]);
1387 break;
1388
1389 case '<':
1390 case '>':
1391 case '[':
1392 case ']':
1393 case '4':
1394 case '5':
1395 case 'H':
1396 case 'W':
1397 case 'D':
1398 case 'j':
1399 case '6':
1400 case '8':
1401 case 'V':
1402 case 'C':
1403 case 'U':
1404 case 'k':
1405 case 'K':
1406 case 'p':
1407 case 'q':
1408 case 'A':
1409 case 'B':
1410 case 'E':
1411 {
1412 int immed, nbits, shift, signedp, extbits, pcrel, extu, branch;
1413
1414 shift = 0;
1415 signedp = 0;
1416 extbits = 16;
1417 pcrel = 0;
1418 extu = 0;
1419 branch = 0;
1420 switch (type)
1421 {
1422 case '<':
1423 nbits = 3;
1424 immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
1425 extbits = 5;
1426 extu = 1;
1427 break;
1428 case '>':
1429 nbits = 3;
1430 immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
1431 extbits = 5;
1432 extu = 1;
1433 break;
1434 case '[':
1435 nbits = 3;
1436 immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
1437 extbits = 6;
1438 extu = 1;
1439 break;
1440 case ']':
1441 nbits = 3;
1442 immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
1443 extbits = 6;
1444 extu = 1;
1445 break;
1446 case '4':
1447 nbits = 4;
1448 immed = (l >> MIPS16OP_SH_IMM4) & MIPS16OP_MASK_IMM4;
1449 signedp = 1;
1450 extbits = 15;
1451 break;
1452 case '5':
1453 nbits = 5;
1454 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1455 info->insn_type = dis_dref;
1456 info->data_size = 1;
1457 break;
1458 case 'H':
1459 nbits = 5;
1460 shift = 1;
1461 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1462 info->insn_type = dis_dref;
1463 info->data_size = 2;
1464 break;
1465 case 'W':
1466 nbits = 5;
1467 shift = 2;
1468 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1469 if ((op->pinfo & MIPS16_INSN_READ_PC) == 0
1470 && (op->pinfo & MIPS16_INSN_READ_SP) == 0)
1471 {
1472 info->insn_type = dis_dref;
1473 info->data_size = 4;
1474 }
1475 break;
1476 case 'D':
1477 nbits = 5;
1478 shift = 3;
1479 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1480 info->insn_type = dis_dref;
1481 info->data_size = 8;
1482 break;
1483 case 'j':
1484 nbits = 5;
1485 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1486 signedp = 1;
1487 break;
1488 case '6':
1489 nbits = 6;
1490 immed = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6;
1491 break;
1492 case '8':
1493 nbits = 8;
1494 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1495 break;
1496 case 'V':
1497 nbits = 8;
1498 shift = 2;
1499 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1500 /* FIXME: This might be lw, or it might be addiu to $sp or
1501 $pc. We assume it's load. */
1502 info->insn_type = dis_dref;
1503 info->data_size = 4;
1504 break;
1505 case 'C':
1506 nbits = 8;
1507 shift = 3;
1508 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1509 info->insn_type = dis_dref;
1510 info->data_size = 8;
1511 break;
1512 case 'U':
1513 nbits = 8;
1514 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1515 extu = 1;
1516 break;
1517 case 'k':
1518 nbits = 8;
1519 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1520 signedp = 1;
1521 break;
1522 case 'K':
1523 nbits = 8;
1524 shift = 3;
1525 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1526 signedp = 1;
1527 break;
1528 case 'p':
1529 nbits = 8;
1530 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1531 signedp = 1;
1532 pcrel = 1;
1533 branch = 1;
1534 info->insn_type = dis_condbranch;
1535 break;
1536 case 'q':
1537 nbits = 11;
1538 immed = (l >> MIPS16OP_SH_IMM11) & MIPS16OP_MASK_IMM11;
1539 signedp = 1;
1540 pcrel = 1;
1541 branch = 1;
1542 info->insn_type = dis_branch;
1543 break;
1544 case 'A':
1545 nbits = 8;
1546 shift = 2;
1547 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1548 pcrel = 1;
1549 /* FIXME: This can be lw or la. We assume it is lw. */
1550 info->insn_type = dis_dref;
1551 info->data_size = 4;
1552 break;
1553 case 'B':
1554 nbits = 5;
1555 shift = 3;
1556 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1557 pcrel = 1;
1558 info->insn_type = dis_dref;
1559 info->data_size = 8;
1560 break;
1561 case 'E':
1562 nbits = 5;
1563 shift = 2;
1564 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1565 pcrel = 1;
1566 break;
1567 default:
1568 abort ();
1569 }
1570
1571 if (! use_extend)
1572 {
1573 if (signedp && immed >= (1 << (nbits - 1)))
1574 immed -= 1 << nbits;
1575 immed <<= shift;
1576 if ((type == '<' || type == '>' || type == '[' || type == ']')
1577 && immed == 0)
1578 immed = 8;
1579 }
1580 else
1581 {
1582 if (extbits == 16)
1583 immed |= ((extend & 0x1f) << 11) | (extend & 0x7e0);
1584 else if (extbits == 15)
1585 immed |= ((extend & 0xf) << 11) | (extend & 0x7f0);
1586 else
1587 immed = ((extend >> 6) & 0x1f) | (extend & 0x20);
1588 immed &= (1 << extbits) - 1;
1589 if (! extu && immed >= (1 << (extbits - 1)))
1590 immed -= 1 << extbits;
1591 }
1592
1593 if (! pcrel)
1594 (*info->fprintf_func) (info->stream, "%d", immed);
1595 else
1596 {
1597 bfd_vma baseaddr;
1598
1599 if (branch)
1600 {
1601 immed *= 2;
1602 baseaddr = memaddr + 2;
1603 }
1604 else if (use_extend)
1605 baseaddr = memaddr - 2;
1606 else
1607 {
1608 int status;
1609 bfd_byte buffer[2];
1610
1611 baseaddr = memaddr;
1612
1613 /* If this instruction is in the delay slot of a jr
1614 instruction, the base address is the address of the
1615 jr instruction. If it is in the delay slot of jalr
1616 instruction, the base address is the address of the
1617 jalr instruction. This test is unreliable: we have
1618 no way of knowing whether the previous word is
1619 instruction or data. */
1620 status = (*info->read_memory_func) (memaddr - 4, buffer, 2,
1621 info);
1622 if (status == 0
1623 && (((info->endian == BFD_ENDIAN_BIG
1624 ? bfd_getb16 (buffer)
1625 : bfd_getl16 (buffer))
1626 & 0xf800) == 0x1800))
1627 baseaddr = memaddr - 4;
1628 else
1629 {
1630 status = (*info->read_memory_func) (memaddr - 2, buffer,
1631 2, info);
1632 if (status == 0
1633 && (((info->endian == BFD_ENDIAN_BIG
1634 ? bfd_getb16 (buffer)
1635 : bfd_getl16 (buffer))
1636 & 0xf81f) == 0xe800))
1637 baseaddr = memaddr - 2;
1638 }
1639 }
1640 info->target = (baseaddr & ~((1 << shift) - 1)) + immed;
1641 if (pcrel && branch
1642 && info->flavour == bfd_target_unknown_flavour)
1643 /* For gdb disassembler, maintain odd address. */
1644 info->target |= 1;
1645 (*info->print_address_func) (info->target, info);
1646 }
1647 }
1648 break;
1649
1650 case 'a':
1651 {
1652 int jalx = l & 0x400;
1653
1654 if (! use_extend)
1655 extend = 0;
1656 l = ((l & 0x1f) << 23) | ((l & 0x3e0) << 13) | (extend << 2);
1657 if (!jalx && info->flavour == bfd_target_unknown_flavour)
1658 /* For gdb disassembler, maintain odd address. */
1659 l |= 1;
1660 }
1661 info->target = ((memaddr + 4) & ~(bfd_vma) 0x0fffffff) | l;
1662 (*info->print_address_func) (info->target, info);
1663 info->insn_type = dis_jsr;
1664 info->branch_delay_insns = 1;
1665 break;
1666
1667 case 'l':
1668 case 'L':
1669 {
1670 int need_comma, amask, smask;
1671
1672 need_comma = 0;
1673
1674 l = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6;
1675
1676 amask = (l >> 3) & 7;
1677
1678 if (amask > 0 && amask < 5)
1679 {
1680 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]);
1681 if (amask > 1)
1682 (*info->fprintf_func) (info->stream, "-%s",
1683 mips_gpr_names[amask + 3]);
1684 need_comma = 1;
1685 }
1686
1687 smask = (l >> 1) & 3;
1688 if (smask == 3)
1689 {
1690 (*info->fprintf_func) (info->stream, "%s??",
1691 need_comma ? "," : "");
1692 need_comma = 1;
1693 }
1694 else if (smask > 0)
1695 {
1696 (*info->fprintf_func) (info->stream, "%s%s",
1697 need_comma ? "," : "",
1698 mips_gpr_names[16]);
1699 if (smask > 1)
1700 (*info->fprintf_func) (info->stream, "-%s",
1701 mips_gpr_names[smask + 15]);
1702 need_comma = 1;
1703 }
1704
1705 if (l & 1)
1706 {
1707 (*info->fprintf_func) (info->stream, "%s%s",
1708 need_comma ? "," : "",
1709 mips_gpr_names[31]);
1710 need_comma = 1;
1711 }
1712
1713 if (amask == 5 || amask == 6)
1714 {
1715 (*info->fprintf_func) (info->stream, "%s$f0",
1716 need_comma ? "," : "");
1717 if (amask == 6)
1718 (*info->fprintf_func) (info->stream, "-$f1");
1719 }
1720 }
1721 break;
1722
1723 case 'm':
1724 case 'M':
1725 /* MIPS16e save/restore. */
1726 {
1727 int need_comma = 0;
1728 int amask, args, statics;
1729 int nsreg, smask;
1730 int framesz;
1731 int i, j;
1732
1733 l = l & 0x7f;
1734 if (use_extend)
1735 l |= extend << 16;
1736
1737 amask = (l >> 16) & 0xf;
1738 if (amask == MIPS16_ALL_ARGS)
1739 {
1740 args = 4;
1741 statics = 0;
1742 }
1743 else if (amask == MIPS16_ALL_STATICS)
1744 {
1745 args = 0;
1746 statics = 4;
1747 }
1748 else
1749 {
1750 args = amask >> 2;
1751 statics = amask & 3;
1752 }
1753
1754 if (args > 0) {
1755 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]);
1756 if (args > 1)
1757 (*info->fprintf_func) (info->stream, "-%s",
1758 mips_gpr_names[4 + args - 1]);
1759 need_comma = 1;
1760 }
1761
1762 framesz = (((l >> 16) & 0xf0) | (l & 0x0f)) * 8;
1763 if (framesz == 0 && !use_extend)
1764 framesz = 128;
1765
1766 (*info->fprintf_func) (info->stream, "%s%d",
1767 need_comma ? "," : "",
1768 framesz);
1769
1770 if (l & 0x40) /* $ra */
1771 (*info->fprintf_func) (info->stream, ",%s", mips_gpr_names[31]);
1772
1773 nsreg = (l >> 24) & 0x7;
1774 smask = 0;
1775 if (l & 0x20) /* $s0 */
1776 smask |= 1 << 0;
1777 if (l & 0x10) /* $s1 */
1778 smask |= 1 << 1;
1779 if (nsreg > 0) /* $s2-$s8 */
1780 smask |= ((1 << nsreg) - 1) << 2;
1781
1782 /* Find first set static reg bit. */
1783 for (i = 0; i < 9; i++)
1784 {
1785 if (smask & (1 << i))
1786 {
1787 (*info->fprintf_func) (info->stream, ",%s",
1788 mips_gpr_names[i == 8 ? 30 : (16 + i)]);
1789 /* Skip over string of set bits. */
1790 for (j = i; smask & (2 << j); j++)
1791 continue;
1792 if (j > i)
1793 (*info->fprintf_func) (info->stream, "-%s",
1794 mips_gpr_names[j == 8 ? 30 : (16 + j)]);
1795 i = j + 1;
1796 }
1797 }
1798
1799 /* Statics $ax - $a3. */
1800 if (statics == 1)
1801 (*info->fprintf_func) (info->stream, ",%s", mips_gpr_names[7]);
1802 else if (statics > 0)
1803 (*info->fprintf_func) (info->stream, ",%s-%s",
1804 mips_gpr_names[7 - statics + 1],
1805 mips_gpr_names[7]);
1806 }
1807 break;
1808
1809 default:
1810 /* xgettext:c-format */
1811 (*info->fprintf_func)
1812 (info->stream,
1813 _("# internal disassembler error, unrecognised modifier (%c)"),
1814 type);
1815 abort ();
1816 }
1817 }
1818
1819 /* Disassemble mips16 instructions. */
1820
1821 static int
1822 print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info)
1823 {
1824 int status;
1825 bfd_byte buffer[2];
1826 int length;
1827 int insn;
1828 bfd_boolean use_extend;
1829 int extend = 0;
1830 const struct mips_opcode *op, *opend;
1831
1832 info->bytes_per_chunk = 2;
1833 info->display_endian = info->endian;
1834 info->insn_info_valid = 1;
1835 info->branch_delay_insns = 0;
1836 info->data_size = 0;
1837 info->insn_type = dis_nonbranch;
1838 info->target = 0;
1839 info->target2 = 0;
1840
1841 status = (*info->read_memory_func) (memaddr, buffer, 2, info);
1842 if (status != 0)
1843 {
1844 (*info->memory_error_func) (status, memaddr, info);
1845 return -1;
1846 }
1847
1848 length = 2;
1849
1850 if (info->endian == BFD_ENDIAN_BIG)
1851 insn = bfd_getb16 (buffer);
1852 else
1853 insn = bfd_getl16 (buffer);
1854
1855 /* Handle the extend opcode specially. */
1856 use_extend = FALSE;
1857 if ((insn & 0xf800) == 0xf000)
1858 {
1859 use_extend = TRUE;
1860 extend = insn & 0x7ff;
1861
1862 memaddr += 2;
1863
1864 status = (*info->read_memory_func) (memaddr, buffer, 2, info);
1865 if (status != 0)
1866 {
1867 (*info->fprintf_func) (info->stream, "extend 0x%x",
1868 (unsigned int) extend);
1869 (*info->memory_error_func) (status, memaddr, info);
1870 return -1;
1871 }
1872
1873 if (info->endian == BFD_ENDIAN_BIG)
1874 insn = bfd_getb16 (buffer);
1875 else
1876 insn = bfd_getl16 (buffer);
1877
1878 /* Check for an extend opcode followed by an extend opcode. */
1879 if ((insn & 0xf800) == 0xf000)
1880 {
1881 (*info->fprintf_func) (info->stream, "extend 0x%x",
1882 (unsigned int) extend);
1883 info->insn_type = dis_noninsn;
1884 return length;
1885 }
1886
1887 length += 2;
1888 }
1889
1890 /* FIXME: Should probably use a hash table on the major opcode here. */
1891
1892 opend = mips16_opcodes + bfd_mips16_num_opcodes;
1893 for (op = mips16_opcodes; op < opend; op++)
1894 {
1895 if (op->pinfo != INSN_MACRO
1896 && !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
1897 && (insn & op->mask) == op->match)
1898 {
1899 const char *s;
1900
1901 if (strchr (op->args, 'a') != NULL)
1902 {
1903 if (use_extend)
1904 {
1905 (*info->fprintf_func) (info->stream, "extend 0x%x",
1906 (unsigned int) extend);
1907 info->insn_type = dis_noninsn;
1908 return length - 2;
1909 }
1910
1911 use_extend = FALSE;
1912
1913 memaddr += 2;
1914
1915 status = (*info->read_memory_func) (memaddr, buffer, 2,
1916 info);
1917 if (status == 0)
1918 {
1919 use_extend = TRUE;
1920 if (info->endian == BFD_ENDIAN_BIG)
1921 extend = bfd_getb16 (buffer);
1922 else
1923 extend = bfd_getl16 (buffer);
1924 length += 2;
1925 }
1926 }
1927
1928 (*info->fprintf_func) (info->stream, "%s", op->name);
1929 if (op->args[0] != '\0')
1930 (*info->fprintf_func) (info->stream, "\t");
1931
1932 for (s = op->args; *s != '\0'; s++)
1933 {
1934 if (*s == ','
1935 && s[1] == 'w'
1936 && (((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX)
1937 == ((insn >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY)))
1938 {
1939 /* Skip the register and the comma. */
1940 ++s;
1941 continue;
1942 }
1943 if (*s == ','
1944 && s[1] == 'v'
1945 && (((insn >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ)
1946 == ((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX)))
1947 {
1948 /* Skip the register and the comma. */
1949 ++s;
1950 continue;
1951 }
1952 print_mips16_insn_arg (*s, op, insn, use_extend, extend, memaddr,
1953 info);
1954 }
1955
1956 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
1957 {
1958 info->branch_delay_insns = 1;
1959 if (info->insn_type != dis_jsr)
1960 info->insn_type = dis_branch;
1961 }
1962
1963 return length;
1964 }
1965 }
1966
1967 if (use_extend)
1968 (*info->fprintf_func) (info->stream, "0x%x", extend | 0xf000);
1969 (*info->fprintf_func) (info->stream, "0x%x", insn);
1970 info->insn_type = dis_noninsn;
1971
1972 return length;
1973 }
1974
1975 /* In an environment where we do not know the symbol type of the
1976 instruction we are forced to assume that the low order bit of the
1977 instructions' address may mark it as a mips16 instruction. If we
1978 are single stepping, or the pc is within the disassembled function,
1979 this works. Otherwise, we need a clue. Sometimes. */
1980
1981 static int
1982 _print_insn_mips (bfd_vma memaddr,
1983 struct disassemble_info *info,
1984 enum bfd_endian endianness)
1985 {
1986 bfd_byte buffer[INSNLEN];
1987 int status;
1988
1989 set_default_mips_dis_options (info);
1990 parse_mips_dis_options (info->disassembler_options);
1991
1992 #if 1
1993 /* FIXME: If odd address, this is CLEARLY a mips 16 instruction. */
1994 /* Only a few tools will work this way. */
1995 if (memaddr & 0x01)
1996 return print_insn_mips16 (memaddr, info);
1997 #endif
1998
1999 #if SYMTAB_AVAILABLE
2000 if (info->mach == bfd_mach_mips16
2001 || (info->flavour == bfd_target_elf_flavour
2002 && info->symbols != NULL
2003 && ((*(elf_symbol_type **) info->symbols)->internal_elf_sym.st_other
2004 == STO_MIPS16)))
2005 return print_insn_mips16 (memaddr, info);
2006 #endif
2007
2008 status = (*info->read_memory_func) (memaddr, buffer, INSNLEN, info);
2009 if (status == 0)
2010 {
2011 unsigned long insn;
2012
2013 if (endianness == BFD_ENDIAN_BIG)
2014 insn = (unsigned long) bfd_getb32 (buffer);
2015 else
2016 insn = (unsigned long) bfd_getl32 (buffer);
2017
2018 return print_insn_mips (memaddr, insn, info);
2019 }
2020 else
2021 {
2022 (*info->memory_error_func) (status, memaddr, info);
2023 return -1;
2024 }
2025 }
2026
2027 int
2028 print_insn_big_mips (bfd_vma memaddr, struct disassemble_info *info)
2029 {
2030 return _print_insn_mips (memaddr, info, BFD_ENDIAN_BIG);
2031 }
2032
2033 int
2034 print_insn_little_mips (bfd_vma memaddr, struct disassemble_info *info)
2035 {
2036 return _print_insn_mips (memaddr, info, BFD_ENDIAN_LITTLE);
2037 }
2038 \f
2039 void
2040 print_mips_disassembler_options (FILE *stream)
2041 {
2042 unsigned int i;
2043
2044 fprintf (stream, _("\n\
2045 The following MIPS specific disassembler options are supported for use\n\
2046 with the -M switch (multiple options should be separated by commas):\n"));
2047
2048 fprintf (stream, _("\n\
2049 gpr-names=ABI Print GPR names according to specified ABI.\n\
2050 Default: based on binary being disassembled.\n"));
2051
2052 fprintf (stream, _("\n\
2053 fpr-names=ABI Print FPR names according to specified ABI.\n\
2054 Default: numeric.\n"));
2055
2056 fprintf (stream, _("\n\
2057 cp0-names=ARCH Print CP0 register names according to\n\
2058 specified architecture.\n\
2059 Default: based on binary being disassembled.\n"));
2060
2061 fprintf (stream, _("\n\
2062 hwr-names=ARCH Print HWR names according to specified \n\
2063 architecture.\n\
2064 Default: based on binary being disassembled.\n"));
2065
2066 fprintf (stream, _("\n\
2067 reg-names=ABI Print GPR and FPR names according to\n\
2068 specified ABI.\n"));
2069
2070 fprintf (stream, _("\n\
2071 reg-names=ARCH Print CP0 register and HWR names according to\n\
2072 specified architecture.\n"));
2073
2074 fprintf (stream, _("\n\
2075 For the options above, the following values are supported for \"ABI\":\n\
2076 "));
2077 for (i = 0; i < ARRAY_SIZE (mips_abi_choices); i++)
2078 fprintf (stream, " %s", mips_abi_choices[i].name);
2079 fprintf (stream, _("\n"));
2080
2081 fprintf (stream, _("\n\
2082 For the options above, The following values are supported for \"ARCH\":\n\
2083 "));
2084 for (i = 0; i < ARRAY_SIZE (mips_arch_choices); i++)
2085 if (*mips_arch_choices[i].name != '\0')
2086 fprintf (stream, " %s", mips_arch_choices[i].name);
2087 fprintf (stream, _("\n"));
2088
2089 fprintf (stream, _("\n"));
2090 }
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