1 2010-10-25 Chao-ying Fu <fu@mips.com>
3 * mips-opc.c (madd, maddu, msub, msubu, mult, multu): Change D33 to D32.
5 2010-10-25 Nathan Sidwell <nathan@codesourcery.com>
7 * tic6x-dis.c: Add attribution.
9 2010-10-22 Alan Modra <amodra@gmail.com>
11 * Makefile.am (CLEANFILES): Add stamp-lm32. Sort.
12 * Makefile.in: Regenerate.
14 2010-10-18 Maciej W. Rozycki <macro@linux-mips.org>
16 * mips-opc.c (mips_builtin_opcodes): Move M_LD_OB and M_SD_OB
17 macros before their corresponding MIPS III hardware instructions.
19 2010-10-16 H.J. Lu <hongjiu.lu@intel.com>
21 * i386-gen.c (cpu_flag_init): Add CpuNop to CPU_GENERIC64_FLAGS.
23 * i386-init.h: Regenerated.
25 2010-10-15 Mike Frysinger <vapier@gentoo.org>
27 * bfin-dis.c (decode_dsp32alu_0): Call imm5d() for BYTEOP2M.
29 2010-10-14 H.J. Lu <hongjiu.lu@intel.com>
31 * i386-opc.tbl: Remove CheckRegSize from movq.
32 * i386-tbl.h: Regenerated.
34 2010-10-14 H.J. Lu <hongjiu.lu@intel.com>
36 * i386-opc.tbl: Remove CheckRegSize from instructions with
37 0, 1 or fixed operands.
38 * i386-tbl.h: Regenerated.
40 2010-10-14 H.J. Lu <hongjiu.lu@intel.com>
42 * i386-gen.c (opcode_modifiers): Add CheckRegSize.
44 * i386-opc.h (CheckRegSize): New.
45 (i386_opcode_modifier): Add checkregsize.
47 * i386-opc.tbl: Add CheckRegSize to instructions which
48 require register size check.
49 * i386-tbl.h: Regenerated.
51 2010-10-12 Andreas Schwab <schwab@linux-m68k.org>
53 * m68k-opc.c (m68k_opcodes): Move fnop before fbf.
55 2010-10-11 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
57 * s390-opc.c: Make the instruction masks for the load/store on
58 condition instructions to cover the condition code mask as well.
59 * s390-opc.txt: lgoc -> locg and stgoc -> stocg.
61 2010-10-11 Jan Kratochvil <jan.kratochvil@redhat.com>
62 Jiang Jilin <freephp@gmail.com>
64 * Makefile.am (libopcodes_a_SOURCES): New as empty.
65 * Makefile.in: Regenerate.
67 2010-10-09 Matt Rice <ratmice@gmail.com>
69 * fr30-desc.h: Regenerate.
70 * frv-desc.h: Regenerate.
71 * ip2k-desc.h: Regenerate.
72 * iq2000-desc.h: Regenerate.
73 * lm32-desc.h: Regenerate.
74 * m32c-desc.h: Regenerate.
75 * m32r-desc.h: Regenerate.
76 * mep-desc.h: Regenerate.
77 * mep-opc.c: Regenerate.
78 * mt-desc.h: Regenerate.
79 * openrisc-desc.h: Regenerate.
80 * xc16x-desc.h: Regenerate.
81 * xstormy16-desc.h: Regenerate.
83 2010-10-08 Pierre Muller <muller@ics.u-strasbg.fr>
85 Fix build with -DDEBUG=7
86 * frv-opc.c: Regenerate.
87 * or32-dis.c (DEBUG): Don't redefine.
88 (find_bytes_big, or32_extract, or32_opcode_match, or32_print_register):
89 Adapt DEBUG code to some type changes throughout.
90 * or32-opc.c (or32_extract): Likewise.
92 2010-10-07 Bernd Schmidt <bernds@codesourcery.com>
94 * tic6x-dis.c (print_insn_tic6x): Correct decoding of fstg field
95 in SPKERNEL instructions.
97 2010-10-02 H.J. Lu <hongjiu.lu@intel.com>
100 * i386-dis.c (RMAL): Remove duplicate.
102 2010-09-30 Pierre Muller <muller@ics.u-strasbg.fr>
104 * s390-mkopc.c (main): Exit with error 1 if sscanf fails
105 to parse all 6 parameters.
107 2010-09-28 Pierre Muller <muller@ics.u-strasbg.fr>
109 * s390-mkopc.c (main): Change description array size to 80.
110 Add maximum length of 79 to description parsing.
112 2010-09-27 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
114 * configure: Regenerate.
116 2010-09-27 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
118 * s390-mkopc.c (enum s390_opcde_cpu_val): Add S390_OPCODE_Z196.
119 (main): Recognize the new CPU string.
120 * s390-opc.c: Add new instruction formats and masks.
121 * s390-opc.txt: Add new z196 instructions.
123 2010-09-27 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
125 * s390-dis.c (print_insn_s390): Pick instruction with most
127 * s390-opc.c: Add unused bits to the insn mask.
128 * s390-opc.txt: Reorder some instructions to prefer more recent
131 2010-09-27 Tejas Belagod <tejas.belagod@arm.com>
133 * arm_dis.c (print_insn_coprocessor): Apply off-by-alignment
134 correction to unaligned PCs while printing comment.
136 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
138 * arm-dis.c (arm_opcodes): Add Virtualiztion Extensions support.
139 (thumb32_opcodes): Likewise.
140 (banked_regname): New function.
141 (print_insn_arm): Add Virtualization Extensions support.
142 (print_insn_thumb32): Likewise.
144 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
146 * arm-dis.c (arm_opcodes): Support disassembly of UDIV and SDIV in
149 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
151 * arm-dis.c (arm_opcodes): SMC implies Security Extensions.
152 (thumb32_opcodes): Likewise.
154 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
156 * arm-dis.c (arm_opcodes): Add support for pldw.
157 (thumb32_opcodes): Likewise.
159 2010-09-22 Robin Getz <robin.getz@analog.com>
161 * bfin-dis.c (fmtconst): Cast address to 32bits.
163 2010-09-22 Mike Frysinger <vapier@gentoo.org>
165 * bfin-dis.c (decode_REGMV_0): Rewrite valid combo checks.
167 2010-09-22 Robin Getz <robin.getz@analog.com>
169 * bfin-dis.c (decode_ProgCtrl_0): Check for parallel insns.
170 Reject P6/P7 to TESTSET.
171 (decode_PushPopReg_0): Check for parallel insns. Reject pushing
173 (decode_PushPopMultiple_0): Check for parallel insns. Make sure
174 P/D fields match all the time.
175 (decode_CCflag_0): Check for parallel insns. Verify x/y fields
176 are 0 for accumulator compares.
177 (decode_CC2stat_0): Check for parallel insns. Reject CC<op>CC.
178 (decode_CaCTRL_0, decode_ccMV_0, decode_CC2dreg_0, decode_BRCC_0,
179 decode_UJUMP_0, decode_LOGI2op_0, decode_COMPI2opD_0,
180 decode_COMPI2opP_0, decode_LoopSetup_0, decode_LDIMMhalf_0,
181 decode_CALLa_0, decode_linkage_0, decode_pseudoDEBUG_0,
182 decode_pseudoOChar_0, decode_pseudodbg_assert_0): Check for parallel
184 (decode_dagMODim_0): Verify br field for IREG ops.
185 (decode_LDST_0): Reject preg load into same preg.
186 (_print_insn_bfin): Handle returns for ILLEGAL decodes.
187 (print_insn_bfin): Likewise.
189 2010-09-22 Mike Frysinger <vapier@gentoo.org>
191 * bfin-dis.c (decode_PushPopMultiple_0): Return 0 when pr > 5.
193 2010-09-22 Robin Getz <robin.getz@analog.com>
195 * bfin-dis.c (decode_dsp32shiftimm_0): Add missing "S" flag.
197 2010-09-22 Mike Frysinger <vapier@gentoo.org>
199 * bfin-dis.c (decode_CC2stat_0): Decode all ASTAT bits.
201 2010-09-22 Robin Getz <robin.getz@analog.com>
203 * bfin-dis.c (IS_DREG, IS_PREG, IS_GENREG, IS_DAGREG): Reject
204 register values greater than 8.
205 (IS_RESERVEDREG, allreg, mostreg): New helpers.
206 (decode_ProgCtrl_0): Call IS_DREG/IS_PREG as appropriate.
207 (decode_PushPopReg_0): Call mostreg/allreg as appropriate.
208 (decode_CC2dreg_0): Check valid CC register number.
210 2010-09-22 Robin Getz <robin.getz@analog.com>
212 * bfin-dis.c (decode_pseudoDEBUG_0): Add space after DBG.
214 2010-09-22 Robin Getz <robin.getz@analog.com>
216 * bfin-dis.c (machine_registers): Add AC0_COPY, V_COPY, and RND_MOD.
217 (reg_names): Likewise.
218 (decode_statbits): Likewise; while reformatting to make manageable.
220 2010-09-22 Mike Frysinger <vapier@gentoo.org>
222 * bfin-dis.c (decode_pseudoDEBUG_0): Add space after OUTC.
223 (decode_pseudoOChar_0): New function.
224 (_print_insn_bfin): Remove #if 0 and call new decode_pseudoOChar_0.
226 2010-09-22 Robin Getz <robin.getz@analog.com>
228 * bfin-dis.c (decode_dsp32shift_0): Decode sub opcodes 2/2 as
229 LSHIFT instead of SHIFT.
231 2010-09-22 Mike Frysinger <vapier@gentoo.org>
233 * bfin-dis.c (constant_formats): Constify the whole structure.
234 (fmtconst): Add const to return value.
235 (reg_names): Mark const.
236 (decode_multfunc): Mark s0/s1 as const.
237 (decode_macfunc): Mark a/sop as const.
239 2010-09-17 Tejas Belagod <tejas.belagod@arm.com>
241 * arm_dis.c (coprocessor_opcodes): Add MRC entry for APSR_nzcv.
243 2010-09-14 Maciej W. Rozycki <macro@codesourcery.com>
245 * mips-opc.c (mips_builtin_opcodes): Add "sync_acquire",
246 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb".
248 2010-09-10 Pierre Muller <muller@ics.u-strasbg.fr>
250 * src/opcodes/dlx-dis.c (print_insn_dlx): Use dlx_insn type for
253 2010-08-31 H.J. Lu <hongjiu.lu@intel.com>
256 * i386-dis.c (sIv): New.
257 (dis386): Replace Iq with sIv on "pushT".
258 (reg_table): Replace T with {T|} on callT, JcallT, jmpT and JjmpT.
259 (x86_64_table): Replace {T|}/{P|} with P.
260 (putop): Add 'w' to 'T'/'P' if needed for Intel syntax.
261 (OP_sI): Update v_mode. Remove w_mode.
263 2010-08-27 Nathan Froyd <froydnj@codesourcery.com>
265 * ppc-opc.c (powerpc_opcodes) [lswx,lswi,stswx,stswi]: Deprecate
268 2010-08-17 H.J. Lu <hongjiu.lu@intel.com>
270 * i386-dis.c (reg_table): Replace Eb with Mb on prefetch and
273 2010-08-06 Quentin Neill <quentin.neill@amd.com>
275 * i386-gen.c (cpu_flag_init): Define CpuNop extension flag, add
276 to processor flags for PENTIUMPRO processors and later.
277 * i386-opc.h (enum): Add CpuNop.
278 (i386_cpu_flags): Add cpunop bit.
279 * i386-opc.tbl: Change nop cpu_flags.
280 * i386-init.h: Regenerated.
281 * i386-tbl.h: Likewise.
283 2010-08-06 Quentin Neill <quentin.neill@amd.com>
285 * i386-opc.h (enum): Fix typos in comments.
287 2010-08-06 Alan Modra <amodra@gmail.com>
289 * disassemble.c: Formatting.
290 (disassemble_init_for_target <ARCH_m32c>): Comment on endian.
292 2010-08-05 H.J. Lu <hongjiu.lu@intel.com>
294 * i386-opc.tbl: Add Cpu186 to ud1/ud2/ud2a/ud2b.
295 * i386-tbl.h: Regenerated.
297 2010-08-05 H.J. Lu <hongjiu.lu@intel.com>
299 * i386-dis.c (dis386_twobyte): Replace ud2a/ud2b with ud2/ud1.
301 * i386-opc.tbl: Add ud1. Remove Cpu686 from ud2/ud2a/ud2b.
302 * i386-tbl.h: Regenerated.
304 2010-07-29 DJ Delorie <dj@redhat.com>
306 * rx-decode.opc (SRR): New.
307 (rx_decode_opcode): Use it for movbi and movbir. Decode NOP2 (mov
308 r0,r0) and NOP3 (max r0,r0) special cases.
309 * rx-decode.c: Regenerate.
311 2010-07-28 H.J. Lu <hongjiu.lu@intel.com>
313 * i386-dis.c: Add 0F to VEX opcode enums.
315 2010-07-27 DJ Delorie <dj@redhat.com>
317 * rx-decode.opc (store_flags): Remove, replace with F_* macros.
318 (rx_decode_opcode): Likewise.
319 * rx-decode.c: Regenerate.
321 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
322 Ina Pandit <ina.pandit@kpitcummins.com>
324 * v850-dis.c (v850_sreg_names): Updated structure for system
326 (float_cc_names): new structure for condition codes.
327 (print_value): Update the function that prints value.
328 (get_operand_value): New function to get the operand value.
329 (disassemble): Updated to handle the disassembly of instructions.
330 (print_insn_v850): Updated function to print instruction for different
332 * opcodes/v850-opc.c (v850_msg_is_out_of_range, insert_i5div1,
333 extract_i5div1, insert_i5div2, extract_i5div2, insert_i5div3,
334 extract_i5div3, insert_d5_4, extract_d5_4, extract_d8_6,
335 insert_d8_7, extract_d8_7, insert_v8, extract_v8, insert_u16_loop,
336 extract_u16_loop, insert_d16_15, extract_d16_15, insert_d16_16,
337 extract_d16_16, nsert_d17_16, extract_d17_16, insert_d22,
338 extract_d22, insert_d23, extract_d23, insert_i9, extract_i9,
339 insert_u9, extract_u9, extract_spe, insert_r4, extract_r4): New.
340 (insert_d8_7, insert_d5_4, insert_i5div): Remove.
341 (v850_operands): Update with the relocation name. Also update
342 the instructions with specific set of processors.
344 2010-07-08 Tejas Belagod <tejas.belagod@arm.com>
346 * arm-dis.c (print_insn_arm): Add cases for printing more
348 (print_insn_thumb32): Likewise.
350 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
352 * mips-dis.c (print_insn_mips): Correct branch instruction type
355 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
357 * mips-dis.c (print_mips16_insn_arg): Remove branch instruction
358 type and delay slot determination.
359 (print_insn_mips16): Extend branch instruction type and delay
360 slot determination to cover all instructions.
361 * mips16-opc.c (BR): Remove macro.
362 (UBR, CBR): New macros.
363 (mips16_opcodes): Update branch annotation for "b", "beqz",
364 "bnez", "bteqz" and "btnez". Add branch annotation for "jalrc"
367 2010-07-05 H.J. Lu <hongjiu.lu@intel.com>
369 AVX Programming Reference (June, 2010)
370 * i386-dis.c (mod_table): Replace rdrnd with rdrand.
371 * i386-opc.tbl: Likewise.
372 * i386-tbl.h: Regenerated.
374 2010-07-05 H.J. Lu <hongjiu.lu@intel.com>
376 * i386-opc.h (CpuFSGSBase): Fix a typo in comments.
378 2010-07-03 Andreas Schwab <schwab@linux-m68k.org>
380 * ppc-dis.c (powerpc_init_dialect): Cast PPC_OPCODE_xxx to
381 ppc_cpu_t before inverting.
382 (ppc_parse_cpu): Likewise.
383 (print_insn_powerpc): Likewise.
385 2010-07-03 Alan Modra <amodra@gmail.com>
387 * ppc-dis.c (ppc_opts, powerpc_init_dialect): Remove old opcode flags.
388 * ppc-opc.c (PPC32, POWER32, COM32, CLASSIC): Delete.
389 (PPC64, MFDEC2): Update.
390 (NON32, NO371): Define.
391 (powerpc_opcode): Update to not use old opcode flags, and avoid
394 2010-07-03 DJ Delorie <dj@delorie.com>
396 * m32c-ibld.c: Regenerate.
398 2010-07-03 Alan Modra <amodra@gmail.com>
400 * ppc-opc.c (PWR2COM): Define.
401 (PPCPWR2): Add PPC_OPCODE_COMMON.
402 (powerpc_opcodes): Add "subc", "subco", "subco.", "fcir", "fcir.",
403 "fcirz", "fcirz." to -mcom opcodes. Remove "mfsri", "dclst",
406 2010-07-01 H.J. Lu <hongjiu.lu@intel.com>
408 AVX Programming Reference (June, 2010)
409 * i386-dis.c (PREFIX_0FAE_REG_0): New.
410 (PREFIX_0FAE_REG_1): Likewise.
411 (PREFIX_0FAE_REG_2): Likewise.
412 (PREFIX_0FAE_REG_3): Likewise.
413 (PREFIX_VEX_3813): Likewise.
414 (PREFIX_VEX_3A1D): Likewise.
415 (prefix_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1,
416 PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3, PREFIX_VEX_3813 and
418 (vex_table): Add PREFIX_VEX_3813 and PREFIX_VEX_3A1D.
419 (mod_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1,
420 PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3 xsaveopt and rdrnd.
422 * i386-gen.c (cpu_flag_init): Add CPU_XSAVEOPT_FLAGS,
423 CPU_FSGSBASE_FLAGS, CPU_RDRND_FLAGS and CPU_F16C_FLAGS.
424 (cpu_flags): Add CpuXsaveopt, CpuFSGSBase, CpuRdRnd and CpuF16C.
426 * i386-opc.h (CpuXsaveopt): New.
427 (CpuFSGSBase): Likewise.
428 (CpuRdRnd): Likewise.
430 (i386_cpu_flags): Add cpuxsaveopt, cpufsgsbase, cpurdrnd and
433 * i386-opc.tbl: Add xsaveopt, rdfsbase, rdgsbase, rdrnd,
434 wrfsbase, wrgsbase, vcvtph2ps and vcvtps2ph.
435 * i386-init.h: Regenerated.
436 * i386-tbl.h: Likewise.
438 2010-07-01 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
440 * ppc-opc.c (powerpc_opcodes): Revert deprecation of mfocrf, mtcrf
443 2010-06-29 Alan Modra <amodra@gmail.com>
445 * maxq-dis.c: Delete file.
446 * Makefile.am: Remove references to maxq.
447 * configure.in: Likewise.
448 * disassemble.c: Likewise.
449 * Makefile.in: Regenerate.
450 * configure: Regenerate.
451 * po/POTFILES.in: Regenerate.
453 2010-06-29 Alan Modra <amodra@gmail.com>
455 * mep-dis.c: Regenerate.
457 2010-06-28 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
459 * arm-disc.c (parse_insn_neon): Fix Neon alignment syntax.
461 2010-06-27 Alan Modra <amodra@gmail.com>
463 * arc-dis.c (arc_sprintf): Delete set but unused variables.
464 (decodeInstr): Likewise.
465 * dlx-dis.c (print_insn_dlx): Likewise.
466 * h8300-dis.c (bfd_h8_disassemble_init): Likewise.
467 * maxq-dis.c (check_move, print_insn): Likewise.
468 * mep-dis.c (mep_examine_ivc2_insns): Likewise.
469 * msp430-dis.c (msp430_branchinstr): Likewise.
470 * bfin-dis.c (_print_insn_bfin): Avoid set but unused warning.
471 * cgen-asm.in (parse_insn_normal, _cgen_assemble_insn): Likewise.
472 * sparc-dis.c (print_insn_sparc): Likewise.
473 * fr30-asm.c: Regenerate.
474 * frv-asm.c: Regenerate.
475 * ip2k-asm.c: Regenerate.
476 * iq2000-asm.c: Regenerate.
477 * lm32-asm.c: Regenerate.
478 * m32c-asm.c: Regenerate.
479 * m32r-asm.c: Regenerate.
480 * mep-asm.c: Regenerate.
481 * mt-asm.c: Regenerate.
482 * openrisc-asm.c: Regenerate.
483 * xc16x-asm.c: Regenerate.
484 * xstormy16-asm.c: Regenerate.
486 2010-06-16 Vincent Rivière <vincent.riviere@freesbee.fr>
489 * m68k-opc.c (m68k_opcodes): Remove move.l for isab and later.
491 2010-06-16 Vincent Rivière <vincent.riviere@freesbee.fr>
494 * m68k-dis.c (print_insn_arg): Prefix float constants with #0e.
496 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
498 * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_E500MC from e500 and
499 e500x2. Add PPC_OPCODE_E500 to e500 and e500x2
500 * ppc-opc.c (powerpc_opcodes): Deprecate all opcodes on EFS which
501 touch floating point regs and are enabled by COM, PPC or PPCCOM.
502 Treat sync as msync on e500. Treat eieio as mbar 1 on e500.
503 Treat lwsync as msync on e500.
505 2010-06-07 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
507 * arm-dis.c (thumb-opcodes): Add disassembly for movs.
509 2010-05-28 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
511 * arm-dis.c (print_insn_neon): Ensure disassembly of Neon
512 constants is the same on 32-bit and 64-bit hosts.
514 2010-05-27 Jason Duerstock <jason.duerstock+binutils@gmail.com>
516 * m68k-dis.c (print_insn_m68k): Emit undefined instructions as
517 .short directives so that they can be reassembled.
519 2010-05-26 Catherine Moore <clm@codesourcery.com>
520 David Ung <davidu@mips.com>
522 * mips-opc.c: Change membership to I1 for instructions ssnop and
525 2010-05-26 H.J. Lu <hongjiu.lu@intel.com>
527 * i386-dis.c (sib): New.
529 (print_insn): Call get_sib.
530 OP_E_memory): Use sib.
532 2010-05-26 Catherine Moore <clm@codesoourcery.com>
534 * mips-dis.c (mips_arch): Remove INSN_MIPS16.
535 * mips-opc.c (I16): Remove.
536 (mips_builtin_op): Reclassify jalx.
538 2010-05-19 Alan Modra <amodra@gmail.com>
540 * ppc-opc.c (powerpc_opcodes): Enable divdeu, devweu, divde,
541 divwe, divdeuo, divweuo, divdeo, divweo for A2. Add icswepx.
543 2010-05-13 Alan Modra <amodra@gmail.com>
545 * ppc-opc.c (powerpc_opcodes): Correct wclr encoding.
547 2010-05-11 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
549 * arm-dis.c (thumb_opcodes): Update ldmia entry to use new %W
551 (print_insn_thumb16): Add support for new %W format.
553 2010-05-07 Tristan Gingold <gingold@adacore.com>
555 * Makefile.in: Regenerate with automake 1.11.1.
558 2010-05-05 Nick Clifton <nickc@redhat.com>
560 * po/es.po: Updated Spanish translation.
562 2010-04-22 Nick Clifton <nickc@redhat.com>
564 * po/opcodes.pot: Updated by the Translation project.
565 * po/vi.po: Updated Vietnamese translation.
567 2010-04-16 H.J. Lu <hongjiu.lu@intel.com>
569 * i386-dis.c (get_valid_dis386): Return bad_opcode on unknown
572 2010-04-09 Nick Clifton <nickc@redhat.com>
574 * i386-dis.c (print_insn): Remove unused variable op.
575 (OP_sI): Remove unused variable mask.
577 2010-04-07 Alan Modra <amodra@gmail.com>
579 * configure: Regenerate.
581 2010-04-06 Peter Bergner <bergner@vnet.ibm.com>
583 * ppc-opc.c (RBOPT): New define.
584 ("dccci"): Enable for PPCA2. Make operands optional.
585 ("iccci"): Likewise. Do not deprecate for PPC476.
587 2010-04-02 Masaki Muranaka <monaka@monami-software.com>
589 * cr16-opc.c (cr16_instruction): Fix typo in comment.
591 2010-03-25 Joseph Myers <joseph@codesourcery.com>
593 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add tic6x-dis.c.
594 * Makefile.in: Regenerate.
595 * configure.in (bfd_tic6x_arch): New.
596 * configure: Regenerate.
597 * disassemble.c (ARCH_tic6x): Define if ARCH_all.
598 (disassembler): Handle TI C6X.
601 2010-03-24 Mike Frysinger <vapier@gentoo.org>
603 * bfin-dis.c (decode_regs_hi): Change REG_LH2 typo to REG_MH2.
605 2010-03-23 Joseph Myers <joseph@codesourcery.com>
607 * dis-buf.c (buffer_read_memory): Give error for reading just
608 before the start of memory.
610 2010-03-22 Sebastian Pop <sebastian.pop@amd.com>
611 Quentin Neill <quentin.neill@amd.com>
613 * i386-dis.c (OP_LWP_I): Removed.
614 (reg_table): Do not use OP_LWP_I, use Iq.
615 (OP_LWPCB_E): Remove use of names16.
617 * i386-opc.tbl: Removed 16bit LWP insns. 32bit LWP insns
618 should not set the Vex.length bit.
619 * i386-tbl.h: Regenerated.
621 2010-02-25 Edmar Wienskoski <edmar@freescale.com>
623 * ppc-dis.c (ppc_opts): Add PPC_OPCODE_E500MC for "e500mc64".
625 2010-02-24 Nick Clifton <nickc@redhat.com>
628 * arm-dis.c (arm_opcodes): Replace <prefix>addsubx with
629 <prefix>asx. Replace <prefix>subaddx with <prefix>sax.
630 (thumb32_opcodes): Likewise.
632 2010-02-15 Nick Clifton <nickc@redhat.com>
634 * po/vi.po: Updated Vietnamese translation.
636 2010-02-12 Doug Evans <dje@sebabeach.org>
638 * lm32-opinst.c: Regenerate.
640 2010-02-11 Doug Evans <dje@sebabeach.org>
642 * cgen-dis.in (print_normal): Delete CGEN_PRINT_NORMAL.
643 (print_address): Delete CGEN_PRINT_ADDRESS.
644 * fr30-dis.c, * frv-dis.c, * ip2k-dis.c, * iq2000-dis.c,
645 * lm32-dis.c, * m32c-dis.c, * m32r-desc.c, * m32r-desc.h,
646 * m32r-dis.c, * mep-dis.c, * mt-dis.c, * openrisc-dis.c,
647 * xc16x-dis.c, * xstormy16-dis.c: Regenerate.
649 * fr30-desc.c, * fr30-desc.h, * fr30-opc.c,
650 * frv-desc.c, * frv-desc.h, * frv-opc.c,
651 * ip2k-desc.c, * ip2k-desc.h, * ip2k-opc.c,
652 * iq2000-desc.c, * iq2000-desc.h, * iq2000-opc.c,
653 * lm32-desc.c, * lm32-desc.h, * lm32-opc.c, * lm32-opinst.c,
654 * m32c-desc.c, * m32c-desc.h, * m32c-opc.c,
655 * m32r-desc.c, * m32r-desc.h, * m32r-opc.c, * m32r-opinst.c,
656 * mep-desc.c, * mep-desc.h, * mep-opc.c,
657 * mt-desc.c, * mt-desc.h, * mt-opc.c,
658 * openrisc-desc.c, * openrisc-desc.h, * openrisc-opc.c,
659 * xc16x-desc.c, * xc16x-desc.h, * xc16x-opc.c,
660 * xstormy16-desc.c, * xstormy16-desc.h, * xstormy16-opc.c: Regenerate.
662 2010-02-11 H.J. Lu <hongjiu.lu@intel.com>
664 * i386-dis.c: Update copyright.
665 * i386-gen.c: Likewise.
666 * i386-opc.h: Likewise.
667 * i386-opc.tbl: Likewise.
669 2010-02-10 Quentin Neill <quentin.neill@amd.com>
670 Sebastian Pop <sebastian.pop@amd.com>
672 * i386-dis.c (OP_EX_VexImmW): Reintroduced
673 function to handle 5th imm8 operand.
674 (PREFIX_VEX_3A48): Added.
675 (PREFIX_VEX_3A49): Added.
676 (VEX_W_3A48_P_2): Added.
677 (VEX_W_3A49_P_2): Added.
678 (prefix table): Added entries for PREFIX_VEX_3A48
680 (vex table): Added entries for VEX_W_3A48_P_2 and
682 * i386-gen.c (operand_type_init): Added OPERAND_TYPE_VEC_IMM4
683 for Vec_Imm4 operands.
684 * i386-opc.h (enum): Added Vec_Imm4.
685 (i386_operand_type): Added vec_imm4.
686 * i386-opc.tbl: Add entries for vpermilp[ds].
687 * i386-init.h: Regenerated.
688 * i386-tbl.h: Regenerated.
690 2010-02-10 Richard Sandiford <r.sandiford@uk.ibm.com>
692 * ppc-dis.c (ppc_opts): Add "pwr4", "pwr5", "pwr5x", "pwr6"
693 and "pwr7". Move "a2" into alphabetical order.
695 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
697 * ppc-dis.c (ppc_opts): Add titan entry.
698 * ppc-opc.c (TITAN, MULHW): Define.
699 (powerpc_opcodes): Support AppliedMicro Titan core (APM83xxx).
701 2010-02-03 Quentin Neill <quentin.neill@amd.com>
703 * i386-gen.c (cpu_flag_init): Rename CPU_AMDFAM15_FLAGS
705 * i386-init.h: Regenerated.
707 2010-02-03 Anthony Green <green@moxielogic.com>
709 * moxie-opc.c (moxie_form1_opc_info): Move "nop" from 0x00 to
710 0x0f, and make 0x00 an illegal instruction.
712 2010-01-29 Daniel Jacobowitz <dan@codesourcery.com>
714 * opcodes/arm-dis.c (struct arm_private_data): New.
715 (print_insn_coprocessor, print_insn_arm): Update to use struct
717 (is_mapping_symbol, get_map_sym_type): New functions.
718 (get_sym_code_type): Check the symbol's section. Do not check
720 (print_insn): Default to disassembling ARM mode code. Check
721 for mapping symbols separately from other symbols. Use
722 struct arm_private_data.
724 2010-01-28 H.J. Lu <hongjiu.lu@intel.com>
726 * i386-dis.c (EXVexWdqScalar): New.
727 (vex_scalar_w_dq_mode): Likewise.
728 (prefix_table): Update entries for PREFIX_VEX_3899,
729 PREFIX_VEX_389B, PREFIX_VEX_389D, PREFIX_VEX_389F,
730 PREFIX_VEX_38A9, PREFIX_VEX_38AB, PREFIX_VEX_38AD,
731 PREFIX_VEX_38AF, PREFIX_VEX_38B9, PREFIX_VEX_38BB,
732 PREFIX_VEX_38BD and PREFIX_VEX_38BF.
733 (intel_operand_size): Handle vex_scalar_w_dq_mode.
736 2010-01-27 H.J. Lu <hongjiu.lu@intel.com>
738 * i386-dis.c (XMScalar): New.
739 (EXdScalar): Likewise.
740 (EXqScalar): Likewise.
741 (EXqScalarS): Likewise.
742 (VexScalar): Likewise.
743 (EXdVexScalarS): Likewise.
744 (EXqVexScalarS): Likewise.
745 (XMVexScalar): Likewise.
746 (scalar_mode): Likewise.
747 (d_scalar_mode): Likewise.
748 (d_scalar_swap_mode): Likewise.
749 (q_scalar_mode): Likewise.
750 (q_scalar_swap_mode): Likewise.
751 (vex_scalar_mode): Likewise.
752 (vex_len_table): Duplcate entries for VEX_LEN_10_P_1,
753 VEX_LEN_10_P_3, VEX_LEN_11_P_1, VEX_LEN_11_P_3, VEX_LEN_2A_P_1,
754 VEX_LEN_2A_P_3, VEX_LEN_2C_P_3, VEX_LEN_2D_P_1, VEX_LEN_2E_P_0,
755 VEX_LEN_2E_P_2, VEX_LEN_2F_P_2, VEX_LEN_51_P_1, VEX_LEN_51_P_3,
756 VEX_LEN_52_P_1, VEX_LEN_53_P_1, VEX_LEN_58_P_1, VEX_LEN_58_P_3,
757 VEX_LEN_59_P_1, VEX_LEN_5A_P_1, VEX_LEN_5A_P_3, VEX_LEN_5C_P_1,
758 VEX_LEN_5C_P_3, VEX_LEN_5D_P_1, VEX_LEN_5D_P_3, VEX_LEN_5E_P_1,
759 VEX_LEN_5E_P_3, VEX_LEN_5F_P_1, VEX_LEN_5F_P_3, VEX_LEN_6E_P_2,
760 VEX_LEN_7E_P_1, VEX_LEN_7E_P_2, VEX_LEN_D6_P_2, VEX_LEN_C2_P_1,
761 VEX_LEN_C2_P_3, VEX_LEN_3A0A_P_2 and VEX_LEN_3A0B_P_2.
762 (vex_w_table): Update entries for VEX_W_10_P_1, VEX_W_10_P_3,
763 VEX_W_11_P_1, VEX_W_11_P_3, VEX_W_2E_P_0, VEX_W_2E_P_2,
764 VEX_W_2F_P_0, VEX_W_2F_P_2, VEX_W_51_P_1, VEX_W_51_P_3,
765 VEX_W_52_P_1, VEX_W_53_P_1, VEX_W_58_P_1, VEX_W_58_P_3,
766 VEX_W_59_P_1, VEX_W_59_P_3, VEX_W_5A_P_1, VEX_W_5A_P_3,
767 VEX_W_5C_P_1, VEX_W_5C_P_3, VEX_W_5D_P_1, VEX_W_5D_P_3,
768 VEX_W_5E_P_1, VEX_W_5E_P_3, VEX_W_5F_P_1, VEX_W_5F_P_3,
769 VEX_W_7E_P_1, VEX_W_D6_P_2 VEX_W_C2_P_1, VEX_W_C2_P_3,
770 VEX_W_3A0A_P_2 and VEX_W_3A0B_P_2.
771 (intel_operand_size): Handle d_scalar_mode, d_scalar_swap_mode,
772 q_scalar_mode, q_scalar_swap_mode.
773 (OP_XMM): Handle scalar_mode.
774 (OP_EX): Handle d_scalar_mode, d_scalar_swap_mode, q_scalar_mode
775 and q_scalar_swap_mode.
776 (OP_VEX): Handle vex_scalar_mode.
778 2010-01-24 H.J. Lu <hongjiu.lu@intel.com>
780 * i386-dis.c (prefix_table): Remove trailing { Bad_Opcode }.
782 2010-01-24 H.J. Lu <hongjiu.lu@intel.com>
784 * i386-dis.c (vex_len_table): Remove trailing { Bad_Opcode }.
786 2010-01-24 H.J. Lu <hongjiu.lu@intel.com>
788 * i386-dis.c (prefix_table): Remove trailing { Bad_Opcode }.
790 2010-01-24 H.J. Lu <hongjiu.lu@intel.com>
792 * i386-dis.c (Bad_Opcode): New.
793 (bad_opcode): Likewise.
794 (dis386): Replace { "(bad)", { XX } } with { Bad_Opcode }.
795 (dis386_twobyte): Likewise.
796 (reg_table): Likewise.
797 (prefix_table): Likewise.
798 (x86_64_table): Likewise.
799 (vex_len_table): Likewise.
800 (vex_w_table): Likewise.
801 (mod_table): Likewise.
802 (rm_table): Likewise.
803 (float_reg): Likewise.
804 (reg_table): Remove trailing "(bad)" entries.
805 (prefix_table): Likewise.
806 (x86_64_table): Likewise.
807 (vex_len_table): Likewise.
808 (vex_w_table): Likewise.
809 (mod_table): Likewise.
810 (rm_table): Likewise.
811 (get_valid_dis386): Handle bytemode 0.
813 2010-01-23 H.J. Lu <hongjiu.lu@intel.com>
815 * i386-opc.h (VEXScalar): New.
817 * i386-opc.tbl: Replace "Vex" with "Vex=3" on AVX scalar
819 * i386-tbl.h: Regenerated.
821 2010-01-21 H.J. Lu <hongjiu.lu@intel.com>
823 * i386-dis.c (mod_table): Use FXSAVE on xsave and xrstor.
825 * i386-opc.tbl: Add xsave64 and xrstor64.
826 * i386-tbl.h: Regenerated.
828 2010-01-20 Nick Clifton <nickc@redhat.com>
831 * arm-dis.c (print_arm_address): Do not ignore negative bit in PC
832 based post-indexed addressing.
834 2010-01-15 Sebastian Pop <sebastian.pop@amd.com>
836 * i386-opc.tbl: Support all the possible aliases for VPCOM* insns.
837 * i386-tbl.h: Regenerated.
839 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
841 * i386-opc.h (VexVVVV): Replace VEX.DNS with VEX.NDS in
844 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
846 * i386-dis.c (names_mm): New.
847 (intel_names_mm): Likewise.
848 (att_names_mm): Likewise.
849 (names_xmm): Likewise.
850 (intel_names_xmm): Likewise.
851 (att_names_xmm): Likewise.
852 (names_ymm): Likewise.
853 (intel_names_ymm): Likewise.
854 (att_names_ymm): Likewise.
855 (print_insn): Set names_mm, names_xmm and names_ymm.
856 (OP_MMX): Use names_mm, names_xmm and names_ymm.
862 (XMM_Fixup): Likewise.
864 (OP_EX_VexReg): Likewise.
865 (OP_Vex_2src): Likewise.
866 (OP_Vex_2src_1): Likewise.
867 (OP_Vex_2src_2): Likewise.
868 (OP_REG_VexI4): Likewise.
870 2010-01-13 H.J. Lu <hongjiu.lu@intel.com>
872 * i386-dis.c (print_insn): Update comments.
874 2010-01-12 H.J. Lu <hongjiu.lu@intel.com>
876 * i386-dis.c (rex_original): Removed.
877 (ckprefix): Remove rex_original.
878 (print_insn): Update comments.
880 2010-01-09 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
882 * Makefile.in: Regenerate.
883 * configure: Regenerate.
885 2010-01-07 Doug Evans <dje@sebabeach.org>
887 * cgen-ibld.in (insert_normal, extract_normal): Minor cleanup.
888 * fr30-ibld.c, * frv-ibld.c, * ip2k-ibld.c, * iq2000-ibld.c,
889 * lm32-ibld.c, * m32c-ibld.c, * m32r-ibld.c, * mep-ibld.c,
890 * mt-ibld.c, * openrisc-ibld.c, * xc16x-ibld.c,
891 * xstormy16-ibld.c: Regenerate.
893 2010-01-06 Quentin Neill <quentin.neill@amd.com>
895 * i386-gen.c (cpu_flag_init): Add new CPU_AMDFAM15_FLAGS.
896 * i386-init.h: Regenerated.
898 2010-01-06 Daniel Gutson <dgutson@codesourcery.com>
900 * arm-dis.c (print_insn): Fixed search for next symbol and data
901 dumping condition, and the initial mapping symbol state.
903 2010-01-05 Doug Evans <dje@sebabeach.org>
905 * cgen-ibld.in: #include "cgen/basic-modes.h".
906 * fr30-ibld.c, * frv-ibld.c, * ip2k-ibld.c, * iq2000-ibld.c,
907 * lm32-ibld.c, * m32c-ibld.c, * m32r-ibld.c, * mep-ibld.c,
908 * mt-ibld.c, * openrisc-ibld.c, * xc16x-ibld.c,
909 * xstormy16-ibld.c: Regenerate.
911 2010-01-04 Nick Clifton <nickc@redhat.com>
914 * arm-dis.c (print_insn_coprocessor): Initialise value.
916 2010-01-04 Edmar Wienskoski <edmar@freescale.com>
918 * ppc-dis.c (ppc_opts): Add entry for "e500mc64".
920 2010-01-02 Doug Evans <dje@sebabeach.org>
922 * cgen-asm.in: Update copyright year.
923 * cgen-dis.in: Update copyright year.
924 * cgen-ibld.in: Update copyright year.
925 * fr30-asm.c, * fr30-desc.c, * fr30-desc.h, * fr30-dis.c,
926 * fr30-ibld.c, * fr30-opc.c, * fr30-opc.h, * frv-asm.c, * frv-desc.c,
927 * frv-desc.h, * frv-dis.c, * frv-ibld.c, * frv-opc.c, * frv-opc.h,
928 * ip2k-asm.c, * ip2k-desc.c, * ip2k-desc.h, * ip2k-dis.c,
929 * ip2k-ibld.c, * ip2k-opc.c, * ip2k-opc.h, * iq2000-asm.c,
930 * iq2000-desc.c, * iq2000-desc.h, * iq2000-dis.c, * iq2000-ibld.c,
931 * iq2000-opc.c, * iq2000-opc.h, * lm32-asm.c, * lm32-desc.c,
932 * lm32-desc.h, * lm32-dis.c, * lm32-ibld.c, * lm32-opc.c, * lm32-opc.h,
933 * lm32-opinst.c, * m32c-asm.c, * m32c-desc.c, * m32c-desc.h,
934 * m32c-dis.c, * m32c-ibld.c, * m32c-opc.c, * m32c-opc.h, * m32r-asm.c,
935 * m32r-desc.c, * m32r-desc.h, * m32r-dis.c, * m32r-ibld.c,
936 * m32r-opc.c, * m32r-opc.h, * m32r-opinst.c, * mep-asm.c, * mep-desc.c,
937 * mep-desc.h, * mep-dis.c, * mep-ibld.c, * mep-opc.c, * mep-opc.h,
938 * mt-asm.c, * mt-desc.c, * mt-desc.h, * mt-dis.c, * mt-ibld.c,
939 * mt-opc.c, * mt-opc.h, * openrisc-asm.c, * openrisc-desc.c,
940 * openrisc-desc.h, * openrisc-dis.c, * openrisc-ibld.c,
941 * openrisc-opc.c, * openrisc-opc.h, * xc16x-asm.c, * xc16x-desc.c,
942 * xc16x-desc.h, * xc16x-dis.c, * xc16x-ibld.c, * xc16x-opc.c,
943 * xc16x-opc.h, * xstormy16-asm.c, * xstormy16-desc.c,
944 * xstormy16-desc.h, * xstormy16-dis.c, * xstormy16-ibld.c,
945 * xstormy16-opc.c, * xstormy16-opc.h: Regenerate.
947 For older changes see ChangeLog-2009
953 version-control: never