opcodes/iq2000-dis.c

   1 /* Disassembler interface for targets using CGEN. -*- C -*-
   2    CGEN: Cpu tools GENerator
   3
   4 THIS FILE IS MACHINE GENERATED WITH CGEN.
   5 - the resultant file is machine generated, cgen-dis.in isn't
   6
   7 Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002
   8 Free Software Foundation, Inc.
   9
  10 This file is part of the GNU Binutils and GDB, the GNU debugger.
  11
  12 This program is free software; you can redistribute it and/or modify
  13 it under the terms of the GNU General Public License as published by
  14 the Free Software Foundation; either version 2, or (at your option)
  15 any later version.
  16
  17 This program is distributed in the hope that it will be useful,
  18 but WITHOUT ANY WARRANTY; without even the implied warranty of
  19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20 GNU General Public License for more details.
  21
  22 You should have received a copy of the GNU General Public License
  23 along with this program; if not, write to the Free Software Foundation, Inc.,
  24 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  25
  26 /* ??? Eventually more and more of this stuff can go to cpu-independent files.
  27    Keep that in mind.  */
  28
  29 #include "sysdep.h"
  30 #include <stdio.h>
  31 #include "ansidecl.h"
  32 #include "dis-asm.h"
  33 #include "bfd.h"
  34 #include "symcat.h"
  35 #include "libiberty.h"
  36 #include "iq2000-desc.h"
  37 #include "iq2000-opc.h"
  38 #include "opintl.h"
  39
  40 /* Default text to print if an instruction isn't recognized.  */
  41 #define UNKNOWN_INSN_MSG _("*unknown*")
  42
  43 static void print_normal
  44   (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int);
  45 static void print_address
  46   (CGEN_CPU_DESC, void *, bfd_vma, unsigned int, bfd_vma, int);
  47 static void print_keyword
  48   (CGEN_CPU_DESC, void *, CGEN_KEYWORD *, long, unsigned int);
  49 static void print_insn_normal
  50   (CGEN_CPU_DESC, void *, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int);
  51 static int print_insn
  52   (CGEN_CPU_DESC, bfd_vma,  disassemble_info *, char *, unsigned);
  53 static int default_print_insn
  54   (CGEN_CPU_DESC, bfd_vma, disassemble_info *);
  55 static int read_insn
  56   (CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, int, CGEN_EXTRACT_INFO *,
  57    unsigned long *);
  58 \f
  59 /* -- disassembler routines inserted here */
  60
  61
  62 void iq2000_cgen_print_operand
  63   PARAMS ((CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *,
  64            void const *, bfd_vma, int));
  65
  66 /* Main entry point for printing operands.
  67    XINFO is a `void *' and not a `disassemble_info *' to not put a requirement
  68    of dis-asm.h on cgen.h.
  69
  70    This function is basically just a big switch statement.  Earlier versions
  71    used tables to look up the function to use, but
  72    - if the table contains both assembler and disassembler functions then
  73      the disassembler contains much of the assembler and vice-versa,
  74    - there's a lot of inlining possibilities as things grow,
  75    - using a switch statement avoids the function call overhead.
  76
  77    This function could be moved into `print_insn_normal', but keeping it
  78    separate makes clear the interface between `print_insn_normal' and each of
  79    the handlers.  */
  80
  81 void
  82 iq2000_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length)
  83      CGEN_CPU_DESC cd;
  84      int opindex;
  85      PTR xinfo;
  86      CGEN_FIELDS *fields;
  87      void const *attrs ATTRIBUTE_UNUSED;
  88      bfd_vma pc;
  89      int length;
  90 {
  91  disassemble_info *info = (disassemble_info *) xinfo;
  92
  93   switch (opindex)
  94     {
  95     case IQ2000_OPERAND_BASE :
  96       print_keyword (cd, info, & iq2000_cgen_opval_gr_names, fields->f_rs, 0);
  97       break;
  98     case IQ2000_OPERAND_BASEOFF :
  99       print_address (cd, info, fields->f_imm, 0, pc, length);
 100       break;
 101     case IQ2000_OPERAND_BITNUM :
 102       print_normal (cd, info, fields->f_rt, 0, pc, length);
 103       break;
 104     case IQ2000_OPERAND_BYTECOUNT :
 105       print_normal (cd, info, fields->f_bytecount, 0, pc, length);
 106       break;
 107     case IQ2000_OPERAND_CAM_Y :
 108       print_normal (cd, info, fields->f_cam_y, 0, pc, length);
 109       break;
 110     case IQ2000_OPERAND_CAM_Z :
 111       print_normal (cd, info, fields->f_cam_z, 0, pc, length);
 112       break;
 113     case IQ2000_OPERAND_CM_3FUNC :
 114       print_normal (cd, info, fields->f_cm_3func, 0, pc, length);
 115       break;
 116     case IQ2000_OPERAND_CM_3Z :
 117       print_normal (cd, info, fields->f_cm_3z, 0, pc, length);
 118       break;
 119     case IQ2000_OPERAND_CM_4FUNC :
 120       print_normal (cd, info, fields->f_cm_4func, 0, pc, length);
 121       break;
 122     case IQ2000_OPERAND_CM_4Z :
 123       print_normal (cd, info, fields->f_cm_4z, 0, pc, length);
 124       break;
 125     case IQ2000_OPERAND_COUNT :
 126       print_normal (cd, info, fields->f_count, 0, pc, length);
 127       break;
 128     case IQ2000_OPERAND_EXECODE :
 129       print_normal (cd, info, fields->f_excode, 0, pc, length);
 130       break;
 131     case IQ2000_OPERAND_F_INDEX :
 132       print_normal (cd, info, fields->f_index, 0, pc, length);
 133       break;
 134     case IQ2000_OPERAND_HI16 :
 135       print_normal (cd, info, fields->f_imm, 0, pc, length);
 136       break;
 137     case IQ2000_OPERAND_IMM :
 138       print_normal (cd, info, fields->f_imm, 0, pc, length);
 139       break;
 140     case IQ2000_OPERAND_JMPTARG :
 141       print_address (cd, info, fields->f_jtarg, 0|(1<<CGEN_OPERAND_ABS_ADDR), pc, length);
 142       break;
 143     case IQ2000_OPERAND_JMPTARGQ10 :
 144       print_address (cd, info, fields->f_jtargq10, 0|(1<<CGEN_OPERAND_ABS_ADDR), pc, length);
 145       break;
 146     case IQ2000_OPERAND_LO16 :
 147       print_normal (cd, info, fields->f_imm, 0, pc, length);
 148       break;
 149     case IQ2000_OPERAND_MASK :
 150       print_normal (cd, info, fields->f_mask, 0, pc, length);
 151       break;
 152     case IQ2000_OPERAND_MASKL :
 153       print_normal (cd, info, fields->f_maskl, 0, pc, length);
 154       break;
 155     case IQ2000_OPERAND_MASKQ10 :
 156       print_normal (cd, info, fields->f_maskq10, 0, pc, length);
 157       break;
 158     case IQ2000_OPERAND_MASKR :
 159       print_normal (cd, info, fields->f_rs, 0, pc, length);
 160       break;
 161     case IQ2000_OPERAND_MLO16 :
 162       print_normal (cd, info, fields->f_imm, 0, pc, length);
 163       break;
 164     case IQ2000_OPERAND_OFFSET :
 165       print_address (cd, info, fields->f_offset, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
 166       break;
 167     case IQ2000_OPERAND_RD :
 168       print_keyword (cd, info, & iq2000_cgen_opval_gr_names, fields->f_rd, 0);
 169       break;
 170     case IQ2000_OPERAND_RD_RS :
 171       print_keyword (cd, info, & iq2000_cgen_opval_gr_names, fields->f_rd_rs, 0|(1<<CGEN_OPERAND_VIRTUAL));
 172       break;
 173     case IQ2000_OPERAND_RD_RT :
 174       print_keyword (cd, info, & iq2000_cgen_opval_gr_names, fields->f_rd_rt, 0|(1<<CGEN_OPERAND_VIRTUAL));
 175       break;
 176     case IQ2000_OPERAND_RS :
 177       print_keyword (cd, info, & iq2000_cgen_opval_gr_names, fields->f_rs, 0);
 178       break;
 179     case IQ2000_OPERAND_RT :
 180       print_keyword (cd, info, & iq2000_cgen_opval_gr_names, fields->f_rt, 0);
 181       break;
 182     case IQ2000_OPERAND_RT_RS :
 183       print_keyword (cd, info, & iq2000_cgen_opval_gr_names, fields->f_rt_rs, 0|(1<<CGEN_OPERAND_VIRTUAL));
 184       break;
 185     case IQ2000_OPERAND_SHAMT :
 186       print_normal (cd, info, fields->f_shamt, 0, pc, length);
 187       break;
 188
 189     default :
 190       /* xgettext:c-format */
 191       fprintf (stderr, _("Unrecognized field %d while printing insn.\n"),
 192                opindex);
 193     abort ();
 194   }
 195 }
 196
 197 cgen_print_fn * const iq2000_cgen_print_handlers[] =
 198 {
 199   print_insn_normal,
 200 };
 201
 202
 203 void
 204 iq2000_cgen_init_dis (cd)
 205      CGEN_CPU_DESC cd;
 206 {
 207   iq2000_cgen_init_opcode_table (cd);
 208   iq2000_cgen_init_ibld_table (cd);
 209   cd->print_handlers = & iq2000_cgen_print_handlers[0];
 210   cd->print_operand = iq2000_cgen_print_operand;
 211 }
 212
 213 \f
 214 /* Default print handler.  */
 215
 216 static void
 217 print_normal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
 218               void *dis_info,
 219               long value,
 220               unsigned int attrs,
 221               bfd_vma pc ATTRIBUTE_UNUSED,
 222               int length ATTRIBUTE_UNUSED)
 223 {
 224   disassemble_info *info = (disassemble_info *) dis_info;
 225
 226 #ifdef CGEN_PRINT_NORMAL
 227   CGEN_PRINT_NORMAL (cd, info, value, attrs, pc, length);
 228 #endif
 229
 230   /* Print the operand as directed by the attributes.  */
 231   if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
 232     ; /* nothing to do */
 233   else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
 234     (*info->fprintf_func) (info->stream, "%ld", value);
 235   else
 236     (*info->fprintf_func) (info->stream, "0x%lx", value);
 237 }
 238
 239 /* Default address handler.  */
 240
 241 static void
 242 print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
 243                void *dis_info,
 244                bfd_vma value,
 245                unsigned int attrs,
 246                bfd_vma pc ATTRIBUTE_UNUSED,
 247                int length ATTRIBUTE_UNUSED)
 248 {
 249   disassemble_info *info = (disassemble_info *) dis_info;
 250
 251 #ifdef CGEN_PRINT_ADDRESS
 252   CGEN_PRINT_ADDRESS (cd, info, value, attrs, pc, length);
 253 #endif
 254
 255   /* Print the operand as directed by the attributes.  */
 256   if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
 257     ; /* nothing to do */
 258   else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR))
 259     (*info->print_address_func) (value, info);
 260   else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR))
 261     (*info->print_address_func) (value, info);
 262   else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
 263     (*info->fprintf_func) (info->stream, "%ld", (long) value);
 264   else
 265     (*info->fprintf_func) (info->stream, "0x%lx", (long) value);
 266 }
 267
 268 /* Keyword print handler.  */
 269
 270 static void
 271 print_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
 272                void *dis_info,
 273                CGEN_KEYWORD *keyword_table,
 274                long value,
 275                unsigned int attrs ATTRIBUTE_UNUSED)
 276 {
 277   disassemble_info *info = (disassemble_info *) dis_info;
 278   const CGEN_KEYWORD_ENTRY *ke;
 279
 280   ke = cgen_keyword_lookup_value (keyword_table, value);
 281   if (ke != NULL)
 282     (*info->fprintf_func) (info->stream, "%s", ke->name);
 283   else
 284     (*info->fprintf_func) (info->stream, "???");
 285 }
 286 \f
 287 /* Default insn printer.
 288
 289    DIS_INFO is defined as `void *' so the disassembler needn't know anything
 290    about disassemble_info.  */
 291
 292 static void
 293 print_insn_normal (CGEN_CPU_DESC cd,
 294                    void *dis_info,
 295                    const CGEN_INSN *insn,
 296                    CGEN_FIELDS *fields,
 297                    bfd_vma pc,
 298                    int length)
 299 {
 300   const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
 301   disassemble_info *info = (disassemble_info *) dis_info;
 302   const CGEN_SYNTAX_CHAR_TYPE *syn;
 303
 304   CGEN_INIT_PRINT (cd);
 305
 306   for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
 307     {
 308       if (CGEN_SYNTAX_MNEMONIC_P (*syn))
 309         {
 310           (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn));
 311           continue;
 312         }
 313       if (CGEN_SYNTAX_CHAR_P (*syn))
 314         {
 315           (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn));
 316           continue;
 317         }
 318
 319       /* We have an operand.  */
 320       iq2000_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info,
 321                                  fields, CGEN_INSN_ATTRS (insn), pc, length);
 322     }
 323 }
 324 \f
 325 /* Subroutine of print_insn. Reads an insn into the given buffers and updates
 326    the extract info.
 327    Returns 0 if all is well, non-zero otherwise.  */
 328
 329 static int
 330 read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
 331            bfd_vma pc,
 332            disassemble_info *info,
 333            char *buf,
 334            int buflen,
 335            CGEN_EXTRACT_INFO *ex_info,
 336            unsigned long *insn_value)
 337 {
 338   int status = (*info->read_memory_func) (pc, buf, buflen, info);
 339   if (status != 0)
 340     {
 341       (*info->memory_error_func) (status, pc, info);
 342       return -1;
 343     }
 344
 345   ex_info->dis_info = info;
 346   ex_info->valid = (1 << buflen) - 1;
 347   ex_info->insn_bytes = buf;
 348
 349   *insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG);
 350   return 0;
 351 }
 352
 353 /* Utility to print an insn.
 354    BUF is the base part of the insn, target byte order, BUFLEN bytes long.
 355    The result is the size of the insn in bytes or zero for an unknown insn
 356    or -1 if an error occurs fetching data (memory_error_func will have
 357    been called).  */
 358
 359 static int
 360 print_insn (CGEN_CPU_DESC cd,
 361             bfd_vma pc,
 362             disassemble_info *info,
 363             char *buf,
 364             unsigned int buflen)
 365 {
 366   CGEN_INSN_INT insn_value;
 367   const CGEN_INSN_LIST *insn_list;
 368   CGEN_EXTRACT_INFO ex_info;
 369   int basesize;
 370
 371   /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */
 372   basesize = cd->base_insn_bitsize < buflen * 8 ?
 373                                      cd->base_insn_bitsize : buflen * 8;
 374   insn_value = cgen_get_insn_value (cd, buf, basesize);
 375
 376
 377   /* Fill in ex_info fields like read_insn would.  Don't actually call
 378      read_insn, since the incoming buffer is already read (and possibly
 379      modified a la m32r).  */
 380   ex_info.valid = (1 << buflen) - 1;
 381   ex_info.dis_info = info;
 382   ex_info.insn_bytes = buf;
 383
 384   /* The instructions are stored in hash lists.
 385      Pick the first one and keep trying until we find the right one.  */
 386
 387   insn_list = CGEN_DIS_LOOKUP_INSN (cd, buf, insn_value);
 388   while (insn_list != NULL)
 389     {
 390       const CGEN_INSN *insn = insn_list->insn;
 391       CGEN_FIELDS fields;
 392       int length;
 393       unsigned long insn_value_cropped;
 394
 395 #ifdef CGEN_VALIDATE_INSN_SUPPORTED
 396       /* Not needed as insn shouldn't be in hash lists if not supported.  */
 397       /* Supported by this cpu?  */
 398       if (! iq2000_cgen_insn_supported (cd, insn))
 399         {
 400           insn_list = CGEN_DIS_NEXT_INSN (insn_list);
 401           continue;
 402         }
 403 #endif
 404
 405       /* Basic bit mask must be correct.  */
 406       /* ??? May wish to allow target to defer this check until the extract
 407          handler.  */
 408
 409       /* Base size may exceed this instruction's size.  Extract the
 410          relevant part from the buffer. */
 411       if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen &&
 412           (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
 413         insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
 414                                            info->endian == BFD_ENDIAN_BIG);
 415       else
 416         insn_value_cropped = insn_value;
 417
 418       if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn))
 419           == CGEN_INSN_BASE_VALUE (insn))
 420         {
 421           /* Printing is handled in two passes.  The first pass parses the
 422              machine insn and extracts the fields.  The second pass prints
 423              them.  */
 424
 425           /* Make sure the entire insn is loaded into insn_value, if it
 426              can fit.  */
 427           if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) &&
 428               (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
 429             {
 430               unsigned long full_insn_value;
 431               int rc = read_insn (cd, pc, info, buf,
 432                                   CGEN_INSN_BITSIZE (insn) / 8,
 433                                   & ex_info, & full_insn_value);
 434               if (rc != 0)
 435                 return rc;
 436               length = CGEN_EXTRACT_FN (cd, insn)
 437                 (cd, insn, &ex_info, full_insn_value, &fields, pc);
 438             }
 439           else
 440             length = CGEN_EXTRACT_FN (cd, insn)
 441               (cd, insn, &ex_info, insn_value_cropped, &fields, pc);
 442
 443           /* length < 0 -> error */
 444           if (length < 0)
 445             return length;
 446           if (length > 0)
 447             {
 448               CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length);
 449               /* length is in bits, result is in bytes */
 450               return length / 8;
 451             }
 452         }
 453
 454       insn_list = CGEN_DIS_NEXT_INSN (insn_list);
 455     }
 456
 457   return 0;
 458 }
 459
 460 /* Default value for CGEN_PRINT_INSN.
 461    The result is the size of the insn in bytes or zero for an unknown insn
 462    or -1 if an error occured fetching bytes.  */
 463
 464 #ifndef CGEN_PRINT_INSN
 465 #define CGEN_PRINT_INSN default_print_insn
 466 #endif
 467
 468 static int
 469 default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
 470 {
 471   char buf[CGEN_MAX_INSN_SIZE];
 472   int buflen;
 473   int status;
 474
 475   /* Attempt to read the base part of the insn.  */
 476   buflen = cd->base_insn_bitsize / 8;
 477   status = (*info->read_memory_func) (pc, buf, buflen, info);
 478
 479   /* Try again with the minimum part, if min < base.  */
 480   if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize))
 481     {
 482       buflen = cd->min_insn_bitsize / 8;
 483       status = (*info->read_memory_func) (pc, buf, buflen, info);
 484     }
 485
 486   if (status != 0)
 487     {
 488       (*info->memory_error_func) (status, pc, info);
 489       return -1;
 490     }
 491
 492   return print_insn (cd, pc, info, buf, buflen);
 493 }
 494
 495 /* Main entry point.
 496    Print one instruction from PC on INFO->STREAM.
 497    Return the size of the instruction (in bytes).  */
 498
 499 typedef struct cpu_desc_list {
 500   struct cpu_desc_list *next;
 501   int isa;
 502   int mach;
 503   int endian;
 504   CGEN_CPU_DESC cd;
 505 } cpu_desc_list;
 506
 507 int
 508 print_insn_iq2000 (bfd_vma pc, disassemble_info *info)
 509 {
 510   static cpu_desc_list *cd_list = 0;
 511   cpu_desc_list *cl = 0;
 512   static CGEN_CPU_DESC cd = 0;
 513   static int prev_isa;
 514   static int prev_mach;
 515   static int prev_endian;
 516   int length;
 517   int isa,mach;
 518   int endian = (info->endian == BFD_ENDIAN_BIG
 519                 ? CGEN_ENDIAN_BIG
 520                 : CGEN_ENDIAN_LITTLE);
 521   enum bfd_architecture arch;
 522
 523   /* ??? gdb will set mach but leave the architecture as "unknown" */
 524 #ifndef CGEN_BFD_ARCH
 525 #define CGEN_BFD_ARCH bfd_arch_iq2000
 526 #endif
 527   arch = info->arch;
 528   if (arch == bfd_arch_unknown)
 529     arch = CGEN_BFD_ARCH;
 530
 531   /* There's no standard way to compute the machine or isa number
 532      so we leave it to the target.  */
 533 #ifdef CGEN_COMPUTE_MACH
 534   mach = CGEN_COMPUTE_MACH (info);
 535 #else
 536   mach = info->mach;
 537 #endif
 538
 539 #ifdef CGEN_COMPUTE_ISA
 540   isa = CGEN_COMPUTE_ISA (info);
 541 #else
 542   isa = info->insn_sets;
 543 #endif
 544
 545   /* If we've switched cpu's, try to find a handle we've used before */
 546   if (cd
 547       && (isa != prev_isa
 548           || mach != prev_mach
 549           || endian != prev_endian))
 550     {
 551       cd = 0;
 552       for (cl = cd_list; cl; cl = cl->next)
 553         {
 554           if (cl->isa == isa &&
 555               cl->mach == mach &&
 556               cl->endian == endian)
 557             {
 558               cd = cl->cd;
 559               break;
 560             }
 561         }
 562     }
 563
 564   /* If we haven't initialized yet, initialize the opcode table.  */
 565   if (! cd)
 566     {
 567       const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach);
 568       const char *mach_name;
 569
 570       if (!arch_type)
 571         abort ();
 572       mach_name = arch_type->printable_name;
 573
 574       prev_isa = isa;
 575       prev_mach = mach;
 576       prev_endian = endian;
 577       cd = iq2000_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa,
 578                                  CGEN_CPU_OPEN_BFDMACH, mach_name,
 579                                  CGEN_CPU_OPEN_ENDIAN, prev_endian,
 580                                  CGEN_CPU_OPEN_END);
 581       if (!cd)
 582         abort ();
 583
 584       /* save this away for future reference */
 585       cl = xmalloc (sizeof (struct cpu_desc_list));
 586       cl->cd = cd;
 587       cl->isa = isa;
 588       cl->mach = mach;
 589       cl->endian = endian;
 590       cl->next = cd_list;
 591       cd_list = cl;
 592
 593       iq2000_cgen_init_dis (cd);
 594     }
 595
 596   /* We try to have as much common code as possible.
 597      But at this point some targets need to take over.  */
 598   /* ??? Some targets may need a hook elsewhere.  Try to avoid this,
 599      but if not possible try to move this hook elsewhere rather than
 600      have two hooks.  */
 601   length = CGEN_PRINT_INSN (cd, pc, info);
 602   if (length > 0)
 603     return length;
 604   if (length < 0)
 605     return -1;
 606
 607   (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
 608   return cd->default_insn_bitsize / 8;
 609 }