1 /* Instruction building/extraction support for m32r. -*- C -*-
3 THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator.
4 - the resultant file is machine generated, cgen-ibld.in isn't
6 Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
8 This file is part of the GNU Binutils and GDB, the GNU debugger.
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software Foundation, Inc.,
22 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
24 /* ??? Eventually more and more of this stuff can go to cpu-independent files.
34 #include "m32r-desc.h"
39 #define min(a,b) ((a) < (b) ? (a) : (b))
41 #define max(a,b) ((a) > (b) ? (a) : (b))
43 /* Used by the ifield rtx function. */
44 #define FLD(f) (fields->f)
46 static const char * insert_normal
47 PARAMS ((CGEN_CPU_DESC
, long, unsigned int, unsigned int, unsigned int,
48 unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR
));
49 static const char * insert_insn_normal
50 PARAMS ((CGEN_CPU_DESC
, const CGEN_INSN
*,
51 CGEN_FIELDS
*, CGEN_INSN_BYTES_PTR
, bfd_vma
));
53 static int extract_normal
54 PARAMS ((CGEN_CPU_DESC
, CGEN_EXTRACT_INFO
*, CGEN_INSN_INT
,
55 unsigned int, unsigned int, unsigned int, unsigned int,
56 unsigned int, unsigned int, bfd_vma
, long *));
57 static int extract_insn_normal
58 PARAMS ((CGEN_CPU_DESC
, const CGEN_INSN
*, CGEN_EXTRACT_INFO
*,
59 CGEN_INSN_INT
, CGEN_FIELDS
*, bfd_vma
));
60 static void put_insn_int_value
61 PARAMS ((CGEN_CPU_DESC
, CGEN_INSN_BYTES_PTR
, int, int, CGEN_INSN_INT
));
64 /* Operand insertion. */
68 /* Subroutine of insert_normal. */
70 static CGEN_INLINE
void
71 insert_1 (cd
, value
, start
, length
, word_length
, bufp
)
74 int start
,length
,word_length
;
79 int big_p
= CGEN_CPU_INSN_ENDIAN (cd
) == CGEN_ENDIAN_BIG
;
88 x
= bfd_getb16 (bufp
);
90 x
= bfd_getl16 (bufp
);
93 /* ??? This may need reworking as these cases don't necessarily
94 want the first byte and the last two bytes handled like this. */
96 x
= (bufp
[0] << 16) | bfd_getb16 (bufp
+ 1);
98 x
= bfd_getl16 (bufp
) | (bufp
[2] << 16);
102 x
= bfd_getb32 (bufp
);
104 x
= bfd_getl32 (bufp
);
110 /* Written this way to avoid undefined behaviour. */
111 mask
= (((1L << (length
- 1)) - 1) << 1) | 1;
112 if (CGEN_INSN_LSB0_P
)
113 shift
= (start
+ 1) - length
;
115 shift
= (word_length
- (start
+ length
));
116 x
= (x
& ~(mask
<< shift
)) | ((value
& mask
) << shift
);
125 bfd_putb16 (x
, bufp
);
127 bfd_putl16 (x
, bufp
);
130 /* ??? This may need reworking as these cases don't necessarily
131 want the first byte and the last two bytes handled like this. */
135 bfd_putb16 (x
, bufp
+ 1);
139 bfd_putl16 (x
, bufp
);
145 bfd_putb32 (x
, bufp
);
147 bfd_putl32 (x
, bufp
);
154 #endif /* ! CGEN_INT_INSN_P */
156 /* Default insertion routine.
158 ATTRS is a mask of the boolean attributes.
159 WORD_OFFSET is the offset in bits from the start of the insn of the value.
160 WORD_LENGTH is the length of the word in bits in which the value resides.
161 START is the starting bit number in the word, architecture origin.
162 LENGTH is the length of VALUE in bits.
163 TOTAL_LENGTH is the total length of the insn in bits.
165 The result is an error message or NULL if success. */
167 /* ??? This duplicates functionality with bfd's howto table and
168 bfd_install_relocation. */
169 /* ??? This doesn't handle bfd_vma's. Create another function when
173 insert_normal (cd
, value
, attrs
, word_offset
, start
, length
, word_length
,
174 total_length
, buffer
)
178 unsigned int word_offset
, start
, length
, word_length
, total_length
;
179 CGEN_INSN_BYTES_PTR buffer
;
181 static char errbuf
[100];
182 /* Written this way to avoid undefined behaviour. */
183 unsigned long mask
= (((1L << (length
- 1)) - 1) << 1) | 1;
185 /* If LENGTH is zero, this operand doesn't contribute to the value. */
195 if (word_length
> 32)
198 /* For architectures with insns smaller than the base-insn-bitsize,
199 word_length may be too big. */
200 if (cd
->min_insn_bitsize
< cd
->base_insn_bitsize
)
203 && word_length
> total_length
)
204 word_length
= total_length
;
207 /* Ensure VALUE will fit. */
208 if (! CGEN_BOOL_ATTR (attrs
, CGEN_IFLD_SIGNED
))
210 unsigned long maxval
= mask
;
212 if ((unsigned long) value
> maxval
)
214 /* xgettext:c-format */
216 _("operand out of range (%lu not between 0 and %lu)"),
223 if (! cgen_signed_overflow_ok_p (cd
))
225 long minval
= - (1L << (length
- 1));
226 long maxval
= (1L << (length
- 1)) - 1;
228 if (value
< minval
|| value
> maxval
)
231 /* xgettext:c-format */
232 (errbuf
, _("operand out of range (%ld not between %ld and %ld)"),
233 value
, minval
, maxval
);
244 if (CGEN_INSN_LSB0_P
)
245 shift
= (word_offset
+ start
+ 1) - length
;
247 shift
= total_length
- (word_offset
+ start
+ length
);
248 *buffer
= (*buffer
& ~(mask
<< shift
)) | ((value
& mask
) << shift
);
251 #else /* ! CGEN_INT_INSN_P */
254 unsigned char *bufp
= (unsigned char *) buffer
+ word_offset
/ 8;
256 insert_1 (cd
, value
, start
, length
, word_length
, bufp
);
259 #endif /* ! CGEN_INT_INSN_P */
264 /* Default insn builder (insert handler).
265 The instruction is recorded in CGEN_INT_INSN_P byte order
266 (meaning that if CGEN_INT_INSN_P BUFFER is an int * and thus the value is
267 recorded in host byte order, otherwise BUFFER is an array of bytes and the
268 value is recorded in target byte order).
269 The result is an error message or NULL if success. */
272 insert_insn_normal (cd
, insn
, fields
, buffer
, pc
)
274 const CGEN_INSN
* insn
;
275 CGEN_FIELDS
* fields
;
276 CGEN_INSN_BYTES_PTR buffer
;
279 const CGEN_SYNTAX
*syntax
= CGEN_INSN_SYNTAX (insn
);
281 const unsigned char * syn
;
283 CGEN_INIT_INSERT (cd
);
284 value
= CGEN_INSN_BASE_VALUE (insn
);
286 /* If we're recording insns as numbers (rather than a string of bytes),
287 target byte order handling is deferred until later. */
291 put_insn_int_value (cd
, buffer
, cd
->base_insn_bitsize
,
292 CGEN_FIELDS_BITSIZE (fields
), value
);
296 cgen_put_insn_value (cd
, buffer
, min (cd
->base_insn_bitsize
,
297 CGEN_FIELDS_BITSIZE (fields
)),
300 #endif /* ! CGEN_INT_INSN_P */
302 /* ??? It would be better to scan the format's fields.
303 Still need to be able to insert a value based on the operand though;
304 e.g. storing a branch displacement that got resolved later.
305 Needs more thought first. */
307 for (syn
= CGEN_SYNTAX_STRING (syntax
); * syn
!= '\0'; ++ syn
)
311 if (CGEN_SYNTAX_CHAR_P (* syn
))
314 errmsg
= (* cd
->insert_operand
) (cd
, CGEN_SYNTAX_FIELD (*syn
),
323 /* Cover function to store an insn value into an integral insn. Must go here
324 because it needs <prefix>-desc.h for CGEN_INT_INSN_P. */
327 put_insn_int_value (cd
, buf
, length
, insn_length
, value
)
329 CGEN_INSN_BYTES_PTR buf
;
334 /* For architectures with insns smaller than the base-insn-bitsize,
335 length may be too big. */
336 if (length
> insn_length
)
340 int shift
= insn_length
- length
;
341 /* Written this way to avoid undefined behaviour. */
342 CGEN_INSN_INT mask
= (((1L << (length
- 1)) - 1) << 1) | 1;
343 *buf
= (*buf
& ~(mask
<< shift
)) | ((value
& mask
) << shift
);
347 /* Operand extraction. */
349 #if ! CGEN_INT_INSN_P
351 /* Subroutine of extract_normal.
352 Ensure sufficient bytes are cached in EX_INFO.
353 OFFSET is the offset in bytes from the start of the insn of the value.
354 BYTES is the length of the needed value.
355 Returns 1 for success, 0 for failure. */
357 static CGEN_INLINE
int
358 fill_cache (cd
, ex_info
, offset
, bytes
, pc
)
360 CGEN_EXTRACT_INFO
*ex_info
;
364 /* It's doubtful that the middle part has already been fetched so
365 we don't optimize that case. kiss. */
367 disassemble_info
*info
= (disassemble_info
*) ex_info
->dis_info
;
369 /* First do a quick check. */
370 mask
= (1 << bytes
) - 1;
371 if (((ex_info
->valid
>> offset
) & mask
) == mask
)
374 /* Search for the first byte we need to read. */
375 for (mask
= 1 << offset
; bytes
> 0; --bytes
, ++offset
, mask
<<= 1)
376 if (! (mask
& ex_info
->valid
))
384 status
= (*info
->read_memory_func
)
385 (pc
, ex_info
->insn_bytes
+ offset
, bytes
, info
);
389 (*info
->memory_error_func
) (status
, pc
, info
);
393 ex_info
->valid
|= ((1 << bytes
) - 1) << offset
;
399 /* Subroutine of extract_normal. */
401 static CGEN_INLINE
long
402 extract_1 (cd
, ex_info
, start
, length
, word_length
, bufp
, pc
)
404 CGEN_EXTRACT_INFO
*ex_info
;
405 int start
,length
,word_length
;
409 unsigned long x
,mask
;
411 int big_p
= CGEN_CPU_INSN_ENDIAN (cd
) == CGEN_ENDIAN_BIG
;
420 x
= bfd_getb16 (bufp
);
422 x
= bfd_getl16 (bufp
);
425 /* ??? This may need reworking as these cases don't necessarily
426 want the first byte and the last two bytes handled like this. */
428 x
= (bufp
[0] << 16) | bfd_getb16 (bufp
+ 1);
430 x
= bfd_getl16 (bufp
) | (bufp
[2] << 16);
434 x
= bfd_getb32 (bufp
);
436 x
= bfd_getl32 (bufp
);
442 /* Written this way to avoid undefined behaviour. */
443 mask
= (((1L << (length
- 1)) - 1) << 1) | 1;
444 if (CGEN_INSN_LSB0_P
)
445 shift
= (start
+ 1) - length
;
447 shift
= (word_length
- (start
+ length
));
448 return (x
>> shift
) & mask
;
451 #endif /* ! CGEN_INT_INSN_P */
453 /* Default extraction routine.
455 INSN_VALUE is the first base_insn_bitsize bits of the insn in host order,
456 or sometimes less for cases like the m32r where the base insn size is 32
457 but some insns are 16 bits.
458 ATTRS is a mask of the boolean attributes. We only need `SIGNED',
459 but for generality we take a bitmask of all of them.
460 WORD_OFFSET is the offset in bits from the start of the insn of the value.
461 WORD_LENGTH is the length of the word in bits in which the value resides.
462 START is the starting bit number in the word, architecture origin.
463 LENGTH is the length of VALUE in bits.
464 TOTAL_LENGTH is the total length of the insn in bits.
466 Returns 1 for success, 0 for failure. */
468 /* ??? The return code isn't properly used. wip. */
470 /* ??? This doesn't handle bfd_vma's. Create another function when
474 extract_normal (cd
, ex_info
, insn_value
, attrs
, word_offset
, start
, length
,
475 word_length
, total_length
, pc
, valuep
)
477 #if ! CGEN_INT_INSN_P
478 CGEN_EXTRACT_INFO
*ex_info
;
480 CGEN_EXTRACT_INFO
*ex_info ATTRIBUTE_UNUSED
;
482 CGEN_INSN_INT insn_value
;
484 unsigned int word_offset
, start
, length
, word_length
, total_length
;
485 #if ! CGEN_INT_INSN_P
488 bfd_vma pc ATTRIBUTE_UNUSED
;
494 /* If LENGTH is zero, this operand doesn't contribute to the value
495 so give it a standard value of zero. */
508 if (word_length
> 32)
511 /* For architectures with insns smaller than the insn-base-bitsize,
512 word_length may be too big. */
513 if (cd
->min_insn_bitsize
< cd
->base_insn_bitsize
)
516 && word_length
> total_length
)
517 word_length
= total_length
;
520 /* Does the value reside in INSN_VALUE? */
522 if (CGEN_INT_INSN_P
|| word_offset
== 0)
524 /* Written this way to avoid undefined behaviour. */
525 CGEN_INSN_INT mask
= (((1L << (length
- 1)) - 1) << 1) | 1;
527 if (CGEN_INSN_LSB0_P
)
528 value
= insn_value
>> ((word_offset
+ start
+ 1) - length
);
530 value
= insn_value
>> (total_length
- ( word_offset
+ start
+ length
));
533 if (CGEN_BOOL_ATTR (attrs
, CGEN_IFLD_SIGNED
)
534 && (value
& (1L << (length
- 1))))
538 #if ! CGEN_INT_INSN_P
542 unsigned char *bufp
= ex_info
->insn_bytes
+ word_offset
/ 8;
544 if (word_length
> 32)
547 if (fill_cache (cd
, ex_info
, word_offset
/ 8, word_length
/ 8, pc
) == 0)
550 value
= extract_1 (cd
, ex_info
, start
, length
, word_length
, bufp
, pc
);
553 #endif /* ! CGEN_INT_INSN_P */
560 /* Default insn extractor.
562 INSN_VALUE is the first base_insn_bitsize bits, translated to host order.
563 The extracted fields are stored in FIELDS.
564 EX_INFO is used to handle reading variable length insns.
565 Return the length of the insn in bits, or 0 if no match,
566 or -1 if an error occurs fetching data (memory_error_func will have
570 extract_insn_normal (cd
, insn
, ex_info
, insn_value
, fields
, pc
)
572 const CGEN_INSN
*insn
;
573 CGEN_EXTRACT_INFO
*ex_info
;
574 CGEN_INSN_INT insn_value
;
578 const CGEN_SYNTAX
*syntax
= CGEN_INSN_SYNTAX (insn
);
579 const unsigned char *syn
;
581 CGEN_FIELDS_BITSIZE (fields
) = CGEN_INSN_BITSIZE (insn
);
583 CGEN_INIT_EXTRACT (cd
);
585 for (syn
= CGEN_SYNTAX_STRING (syntax
); *syn
; ++syn
)
589 if (CGEN_SYNTAX_CHAR_P (*syn
))
592 length
= (* cd
->extract_operand
) (cd
, CGEN_SYNTAX_FIELD (*syn
),
593 ex_info
, insn_value
, fields
, pc
);
598 /* We recognized and successfully extracted this insn. */
599 return CGEN_INSN_BITSIZE (insn
);
602 /* machine generated code added here */
604 /* Main entry point for operand insertion.
606 This function is basically just a big switch statement. Earlier versions
607 used tables to look up the function to use, but
608 - if the table contains both assembler and disassembler functions then
609 the disassembler contains much of the assembler and vice-versa,
610 - there's a lot of inlining possibilities as things grow,
611 - using a switch statement avoids the function call overhead.
613 This function could be moved into `parse_insn_normal', but keeping it
614 separate makes clear the interface between `parse_insn_normal' and each of
615 the handlers. It's also needed by GAS to insert operands that couldn't be
616 resolved during parsing.
620 m32r_cgen_insert_operand (cd
, opindex
, fields
, buffer
, pc
)
623 CGEN_FIELDS
* fields
;
624 CGEN_INSN_BYTES_PTR buffer
;
627 const char * errmsg
= NULL
;
628 unsigned int total_length
= CGEN_FIELDS_BITSIZE (fields
);
632 case M32R_OPERAND_ACC
:
633 errmsg
= insert_normal (cd
, fields
->f_acc
, 0, 0, 8, 1, 32, total_length
, buffer
);
635 case M32R_OPERAND_ACCD
:
636 errmsg
= insert_normal (cd
, fields
->f_accd
, 0, 0, 4, 2, 32, total_length
, buffer
);
638 case M32R_OPERAND_ACCS
:
639 errmsg
= insert_normal (cd
, fields
->f_accs
, 0, 0, 12, 2, 32, total_length
, buffer
);
641 case M32R_OPERAND_DCR
:
642 errmsg
= insert_normal (cd
, fields
->f_r1
, 0, 0, 4, 4, 32, total_length
, buffer
);
644 case M32R_OPERAND_DISP16
:
646 long value
= fields
->f_disp16
;
647 value
= ((int) (((value
) - (pc
))) >> (2));
648 errmsg
= insert_normal (cd
, value
, 0|(1<<CGEN_IFLD_SIGNED
)|(1<<CGEN_IFLD_RELOC
)|(1<<CGEN_IFLD_PCREL_ADDR
), 0, 16, 16, 32, total_length
, buffer
);
651 case M32R_OPERAND_DISP24
:
653 long value
= fields
->f_disp24
;
654 value
= ((int) (((value
) - (pc
))) >> (2));
655 errmsg
= insert_normal (cd
, value
, 0|(1<<CGEN_IFLD_SIGNED
)|(1<<CGEN_IFLD_RELOC
)|(1<<CGEN_IFLD_PCREL_ADDR
), 0, 8, 24, 32, total_length
, buffer
);
658 case M32R_OPERAND_DISP8
:
660 long value
= fields
->f_disp8
;
661 value
= ((int) (((value
) - (((pc
) & (-4))))) >> (2));
662 errmsg
= insert_normal (cd
, value
, 0|(1<<CGEN_IFLD_SIGNED
)|(1<<CGEN_IFLD_RELOC
)|(1<<CGEN_IFLD_PCREL_ADDR
), 0, 8, 8, 32, total_length
, buffer
);
665 case M32R_OPERAND_DR
:
666 errmsg
= insert_normal (cd
, fields
->f_r1
, 0, 0, 4, 4, 32, total_length
, buffer
);
668 case M32R_OPERAND_HASH
:
670 case M32R_OPERAND_HI16
:
671 errmsg
= insert_normal (cd
, fields
->f_hi16
, 0|(1<<CGEN_IFLD_SIGN_OPT
), 0, 16, 16, 32, total_length
, buffer
);
673 case M32R_OPERAND_IMM1
:
675 long value
= fields
->f_imm1
;
676 value
= ((value
) - (1));
677 errmsg
= insert_normal (cd
, value
, 0, 0, 15, 1, 32, total_length
, buffer
);
680 case M32R_OPERAND_SCR
:
681 errmsg
= insert_normal (cd
, fields
->f_r2
, 0, 0, 12, 4, 32, total_length
, buffer
);
683 case M32R_OPERAND_SIMM16
:
684 errmsg
= insert_normal (cd
, fields
->f_simm16
, 0|(1<<CGEN_IFLD_SIGNED
), 0, 16, 16, 32, total_length
, buffer
);
686 case M32R_OPERAND_SIMM8
:
687 errmsg
= insert_normal (cd
, fields
->f_simm8
, 0|(1<<CGEN_IFLD_SIGNED
), 0, 8, 8, 32, total_length
, buffer
);
689 case M32R_OPERAND_SLO16
:
690 errmsg
= insert_normal (cd
, fields
->f_simm16
, 0|(1<<CGEN_IFLD_SIGNED
), 0, 16, 16, 32, total_length
, buffer
);
692 case M32R_OPERAND_SR
:
693 errmsg
= insert_normal (cd
, fields
->f_r2
, 0, 0, 12, 4, 32, total_length
, buffer
);
695 case M32R_OPERAND_SRC1
:
696 errmsg
= insert_normal (cd
, fields
->f_r1
, 0, 0, 4, 4, 32, total_length
, buffer
);
698 case M32R_OPERAND_SRC2
:
699 errmsg
= insert_normal (cd
, fields
->f_r2
, 0, 0, 12, 4, 32, total_length
, buffer
);
701 case M32R_OPERAND_UIMM16
:
702 errmsg
= insert_normal (cd
, fields
->f_uimm16
, 0, 0, 16, 16, 32, total_length
, buffer
);
704 case M32R_OPERAND_UIMM24
:
705 errmsg
= insert_normal (cd
, fields
->f_uimm24
, 0|(1<<CGEN_IFLD_RELOC
)|(1<<CGEN_IFLD_ABS_ADDR
), 0, 8, 24, 32, total_length
, buffer
);
707 case M32R_OPERAND_UIMM4
:
708 errmsg
= insert_normal (cd
, fields
->f_uimm4
, 0, 0, 12, 4, 32, total_length
, buffer
);
710 case M32R_OPERAND_UIMM5
:
711 errmsg
= insert_normal (cd
, fields
->f_uimm5
, 0, 0, 11, 5, 32, total_length
, buffer
);
713 case M32R_OPERAND_ULO16
:
714 errmsg
= insert_normal (cd
, fields
->f_uimm16
, 0, 0, 16, 16, 32, total_length
, buffer
);
718 /* xgettext:c-format */
719 fprintf (stderr
, _("Unrecognized field %d while building insn.\n"),
727 /* Main entry point for operand extraction.
728 The result is <= 0 for error, >0 for success.
729 ??? Actual values aren't well defined right now.
731 This function is basically just a big switch statement. Earlier versions
732 used tables to look up the function to use, but
733 - if the table contains both assembler and disassembler functions then
734 the disassembler contains much of the assembler and vice-versa,
735 - there's a lot of inlining possibilities as things grow,
736 - using a switch statement avoids the function call overhead.
738 This function could be moved into `print_insn_normal', but keeping it
739 separate makes clear the interface between `print_insn_normal' and each of
744 m32r_cgen_extract_operand (cd
, opindex
, ex_info
, insn_value
, fields
, pc
)
747 CGEN_EXTRACT_INFO
*ex_info
;
748 CGEN_INSN_INT insn_value
;
749 CGEN_FIELDS
* fields
;
752 /* Assume success (for those operands that are nops). */
754 unsigned int total_length
= CGEN_FIELDS_BITSIZE (fields
);
758 case M32R_OPERAND_ACC
:
759 length
= extract_normal (cd
, ex_info
, insn_value
, 0, 0, 8, 1, 32, total_length
, pc
, & fields
->f_acc
);
761 case M32R_OPERAND_ACCD
:
762 length
= extract_normal (cd
, ex_info
, insn_value
, 0, 0, 4, 2, 32, total_length
, pc
, & fields
->f_accd
);
764 case M32R_OPERAND_ACCS
:
765 length
= extract_normal (cd
, ex_info
, insn_value
, 0, 0, 12, 2, 32, total_length
, pc
, & fields
->f_accs
);
767 case M32R_OPERAND_DCR
:
768 length
= extract_normal (cd
, ex_info
, insn_value
, 0, 0, 4, 4, 32, total_length
, pc
, & fields
->f_r1
);
770 case M32R_OPERAND_DISP16
:
773 length
= extract_normal (cd
, ex_info
, insn_value
, 0|(1<<CGEN_IFLD_SIGNED
)|(1<<CGEN_IFLD_RELOC
)|(1<<CGEN_IFLD_PCREL_ADDR
), 0, 16, 16, 32, total_length
, pc
, & value
);
774 value
= ((((value
) << (2))) + (pc
));
775 fields
->f_disp16
= value
;
778 case M32R_OPERAND_DISP24
:
781 length
= extract_normal (cd
, ex_info
, insn_value
, 0|(1<<CGEN_IFLD_SIGNED
)|(1<<CGEN_IFLD_RELOC
)|(1<<CGEN_IFLD_PCREL_ADDR
), 0, 8, 24, 32, total_length
, pc
, & value
);
782 value
= ((((value
) << (2))) + (pc
));
783 fields
->f_disp24
= value
;
786 case M32R_OPERAND_DISP8
:
789 length
= extract_normal (cd
, ex_info
, insn_value
, 0|(1<<CGEN_IFLD_SIGNED
)|(1<<CGEN_IFLD_RELOC
)|(1<<CGEN_IFLD_PCREL_ADDR
), 0, 8, 8, 32, total_length
, pc
, & value
);
790 value
= ((((value
) << (2))) + (((pc
) & (-4))));
791 fields
->f_disp8
= value
;
794 case M32R_OPERAND_DR
:
795 length
= extract_normal (cd
, ex_info
, insn_value
, 0, 0, 4, 4, 32, total_length
, pc
, & fields
->f_r1
);
797 case M32R_OPERAND_HASH
:
799 case M32R_OPERAND_HI16
:
800 length
= extract_normal (cd
, ex_info
, insn_value
, 0|(1<<CGEN_IFLD_SIGN_OPT
), 0, 16, 16, 32, total_length
, pc
, & fields
->f_hi16
);
802 case M32R_OPERAND_IMM1
:
805 length
= extract_normal (cd
, ex_info
, insn_value
, 0, 0, 15, 1, 32, total_length
, pc
, & value
);
806 value
= ((value
) + (1));
807 fields
->f_imm1
= value
;
810 case M32R_OPERAND_SCR
:
811 length
= extract_normal (cd
, ex_info
, insn_value
, 0, 0, 12, 4, 32, total_length
, pc
, & fields
->f_r2
);
813 case M32R_OPERAND_SIMM16
:
814 length
= extract_normal (cd
, ex_info
, insn_value
, 0|(1<<CGEN_IFLD_SIGNED
), 0, 16, 16, 32, total_length
, pc
, & fields
->f_simm16
);
816 case M32R_OPERAND_SIMM8
:
817 length
= extract_normal (cd
, ex_info
, insn_value
, 0|(1<<CGEN_IFLD_SIGNED
), 0, 8, 8, 32, total_length
, pc
, & fields
->f_simm8
);
819 case M32R_OPERAND_SLO16
:
820 length
= extract_normal (cd
, ex_info
, insn_value
, 0|(1<<CGEN_IFLD_SIGNED
), 0, 16, 16, 32, total_length
, pc
, & fields
->f_simm16
);
822 case M32R_OPERAND_SR
:
823 length
= extract_normal (cd
, ex_info
, insn_value
, 0, 0, 12, 4, 32, total_length
, pc
, & fields
->f_r2
);
825 case M32R_OPERAND_SRC1
:
826 length
= extract_normal (cd
, ex_info
, insn_value
, 0, 0, 4, 4, 32, total_length
, pc
, & fields
->f_r1
);
828 case M32R_OPERAND_SRC2
:
829 length
= extract_normal (cd
, ex_info
, insn_value
, 0, 0, 12, 4, 32, total_length
, pc
, & fields
->f_r2
);
831 case M32R_OPERAND_UIMM16
:
832 length
= extract_normal (cd
, ex_info
, insn_value
, 0, 0, 16, 16, 32, total_length
, pc
, & fields
->f_uimm16
);
834 case M32R_OPERAND_UIMM24
:
835 length
= extract_normal (cd
, ex_info
, insn_value
, 0|(1<<CGEN_IFLD_RELOC
)|(1<<CGEN_IFLD_ABS_ADDR
), 0, 8, 24, 32, total_length
, pc
, & fields
->f_uimm24
);
837 case M32R_OPERAND_UIMM4
:
838 length
= extract_normal (cd
, ex_info
, insn_value
, 0, 0, 12, 4, 32, total_length
, pc
, & fields
->f_uimm4
);
840 case M32R_OPERAND_UIMM5
:
841 length
= extract_normal (cd
, ex_info
, insn_value
, 0, 0, 11, 5, 32, total_length
, pc
, & fields
->f_uimm5
);
843 case M32R_OPERAND_ULO16
:
844 length
= extract_normal (cd
, ex_info
, insn_value
, 0, 0, 16, 16, 32, total_length
, pc
, & fields
->f_uimm16
);
848 /* xgettext:c-format */
849 fprintf (stderr
, _("Unrecognized field %d while decoding insn.\n"),
857 cgen_insert_fn
* const m32r_cgen_insert_handlers
[] =
862 cgen_extract_fn
* const m32r_cgen_extract_handlers
[] =
867 /* Getting values from cgen_fields is handled by a collection of functions.
868 They are distinguished by the type of the VALUE argument they return.
869 TODO: floating point, inlining support, remove cases where result type
873 m32r_cgen_get_int_operand (cd
, opindex
, fields
)
876 const CGEN_FIELDS
* fields
;
882 case M32R_OPERAND_ACC
:
883 value
= fields
->f_acc
;
885 case M32R_OPERAND_ACCD
:
886 value
= fields
->f_accd
;
888 case M32R_OPERAND_ACCS
:
889 value
= fields
->f_accs
;
891 case M32R_OPERAND_DCR
:
892 value
= fields
->f_r1
;
894 case M32R_OPERAND_DISP16
:
895 value
= fields
->f_disp16
;
897 case M32R_OPERAND_DISP24
:
898 value
= fields
->f_disp24
;
900 case M32R_OPERAND_DISP8
:
901 value
= fields
->f_disp8
;
903 case M32R_OPERAND_DR
:
904 value
= fields
->f_r1
;
906 case M32R_OPERAND_HASH
:
909 case M32R_OPERAND_HI16
:
910 value
= fields
->f_hi16
;
912 case M32R_OPERAND_IMM1
:
913 value
= fields
->f_imm1
;
915 case M32R_OPERAND_SCR
:
916 value
= fields
->f_r2
;
918 case M32R_OPERAND_SIMM16
:
919 value
= fields
->f_simm16
;
921 case M32R_OPERAND_SIMM8
:
922 value
= fields
->f_simm8
;
924 case M32R_OPERAND_SLO16
:
925 value
= fields
->f_simm16
;
927 case M32R_OPERAND_SR
:
928 value
= fields
->f_r2
;
930 case M32R_OPERAND_SRC1
:
931 value
= fields
->f_r1
;
933 case M32R_OPERAND_SRC2
:
934 value
= fields
->f_r2
;
936 case M32R_OPERAND_UIMM16
:
937 value
= fields
->f_uimm16
;
939 case M32R_OPERAND_UIMM24
:
940 value
= fields
->f_uimm24
;
942 case M32R_OPERAND_UIMM4
:
943 value
= fields
->f_uimm4
;
945 case M32R_OPERAND_UIMM5
:
946 value
= fields
->f_uimm5
;
948 case M32R_OPERAND_ULO16
:
949 value
= fields
->f_uimm16
;
953 /* xgettext:c-format */
954 fprintf (stderr
, _("Unrecognized field %d while getting int operand.\n"),
963 m32r_cgen_get_vma_operand (cd
, opindex
, fields
)
966 const CGEN_FIELDS
* fields
;
972 case M32R_OPERAND_ACC
:
973 value
= fields
->f_acc
;
975 case M32R_OPERAND_ACCD
:
976 value
= fields
->f_accd
;
978 case M32R_OPERAND_ACCS
:
979 value
= fields
->f_accs
;
981 case M32R_OPERAND_DCR
:
982 value
= fields
->f_r1
;
984 case M32R_OPERAND_DISP16
:
985 value
= fields
->f_disp16
;
987 case M32R_OPERAND_DISP24
:
988 value
= fields
->f_disp24
;
990 case M32R_OPERAND_DISP8
:
991 value
= fields
->f_disp8
;
993 case M32R_OPERAND_DR
:
994 value
= fields
->f_r1
;
996 case M32R_OPERAND_HASH
:
999 case M32R_OPERAND_HI16
:
1000 value
= fields
->f_hi16
;
1002 case M32R_OPERAND_IMM1
:
1003 value
= fields
->f_imm1
;
1005 case M32R_OPERAND_SCR
:
1006 value
= fields
->f_r2
;
1008 case M32R_OPERAND_SIMM16
:
1009 value
= fields
->f_simm16
;
1011 case M32R_OPERAND_SIMM8
:
1012 value
= fields
->f_simm8
;
1014 case M32R_OPERAND_SLO16
:
1015 value
= fields
->f_simm16
;
1017 case M32R_OPERAND_SR
:
1018 value
= fields
->f_r2
;
1020 case M32R_OPERAND_SRC1
:
1021 value
= fields
->f_r1
;
1023 case M32R_OPERAND_SRC2
:
1024 value
= fields
->f_r2
;
1026 case M32R_OPERAND_UIMM16
:
1027 value
= fields
->f_uimm16
;
1029 case M32R_OPERAND_UIMM24
:
1030 value
= fields
->f_uimm24
;
1032 case M32R_OPERAND_UIMM4
:
1033 value
= fields
->f_uimm4
;
1035 case M32R_OPERAND_UIMM5
:
1036 value
= fields
->f_uimm5
;
1038 case M32R_OPERAND_ULO16
:
1039 value
= fields
->f_uimm16
;
1043 /* xgettext:c-format */
1044 fprintf (stderr
, _("Unrecognized field %d while getting vma operand.\n"),
1052 /* Stuffing values in cgen_fields is handled by a collection of functions.
1053 They are distinguished by the type of the VALUE argument they accept.
1054 TODO: floating point, inlining support, remove cases where argument type
1058 m32r_cgen_set_int_operand (cd
, opindex
, fields
, value
)
1061 CGEN_FIELDS
* fields
;
1066 case M32R_OPERAND_ACC
:
1067 fields
->f_acc
= value
;
1069 case M32R_OPERAND_ACCD
:
1070 fields
->f_accd
= value
;
1072 case M32R_OPERAND_ACCS
:
1073 fields
->f_accs
= value
;
1075 case M32R_OPERAND_DCR
:
1076 fields
->f_r1
= value
;
1078 case M32R_OPERAND_DISP16
:
1079 fields
->f_disp16
= value
;
1081 case M32R_OPERAND_DISP24
:
1082 fields
->f_disp24
= value
;
1084 case M32R_OPERAND_DISP8
:
1085 fields
->f_disp8
= value
;
1087 case M32R_OPERAND_DR
:
1088 fields
->f_r1
= value
;
1090 case M32R_OPERAND_HASH
:
1092 case M32R_OPERAND_HI16
:
1093 fields
->f_hi16
= value
;
1095 case M32R_OPERAND_IMM1
:
1096 fields
->f_imm1
= value
;
1098 case M32R_OPERAND_SCR
:
1099 fields
->f_r2
= value
;
1101 case M32R_OPERAND_SIMM16
:
1102 fields
->f_simm16
= value
;
1104 case M32R_OPERAND_SIMM8
:
1105 fields
->f_simm8
= value
;
1107 case M32R_OPERAND_SLO16
:
1108 fields
->f_simm16
= value
;
1110 case M32R_OPERAND_SR
:
1111 fields
->f_r2
= value
;
1113 case M32R_OPERAND_SRC1
:
1114 fields
->f_r1
= value
;
1116 case M32R_OPERAND_SRC2
:
1117 fields
->f_r2
= value
;
1119 case M32R_OPERAND_UIMM16
:
1120 fields
->f_uimm16
= value
;
1122 case M32R_OPERAND_UIMM24
:
1123 fields
->f_uimm24
= value
;
1125 case M32R_OPERAND_UIMM4
:
1126 fields
->f_uimm4
= value
;
1128 case M32R_OPERAND_UIMM5
:
1129 fields
->f_uimm5
= value
;
1131 case M32R_OPERAND_ULO16
:
1132 fields
->f_uimm16
= value
;
1136 /* xgettext:c-format */
1137 fprintf (stderr
, _("Unrecognized field %d while setting int operand.\n"),
1144 m32r_cgen_set_vma_operand (cd
, opindex
, fields
, value
)
1147 CGEN_FIELDS
* fields
;
1152 case M32R_OPERAND_ACC
:
1153 fields
->f_acc
= value
;
1155 case M32R_OPERAND_ACCD
:
1156 fields
->f_accd
= value
;
1158 case M32R_OPERAND_ACCS
:
1159 fields
->f_accs
= value
;
1161 case M32R_OPERAND_DCR
:
1162 fields
->f_r1
= value
;
1164 case M32R_OPERAND_DISP16
:
1165 fields
->f_disp16
= value
;
1167 case M32R_OPERAND_DISP24
:
1168 fields
->f_disp24
= value
;
1170 case M32R_OPERAND_DISP8
:
1171 fields
->f_disp8
= value
;
1173 case M32R_OPERAND_DR
:
1174 fields
->f_r1
= value
;
1176 case M32R_OPERAND_HASH
:
1178 case M32R_OPERAND_HI16
:
1179 fields
->f_hi16
= value
;
1181 case M32R_OPERAND_IMM1
:
1182 fields
->f_imm1
= value
;
1184 case M32R_OPERAND_SCR
:
1185 fields
->f_r2
= value
;
1187 case M32R_OPERAND_SIMM16
:
1188 fields
->f_simm16
= value
;
1190 case M32R_OPERAND_SIMM8
:
1191 fields
->f_simm8
= value
;
1193 case M32R_OPERAND_SLO16
:
1194 fields
->f_simm16
= value
;
1196 case M32R_OPERAND_SR
:
1197 fields
->f_r2
= value
;
1199 case M32R_OPERAND_SRC1
:
1200 fields
->f_r1
= value
;
1202 case M32R_OPERAND_SRC2
:
1203 fields
->f_r2
= value
;
1205 case M32R_OPERAND_UIMM16
:
1206 fields
->f_uimm16
= value
;
1208 case M32R_OPERAND_UIMM24
:
1209 fields
->f_uimm24
= value
;
1211 case M32R_OPERAND_UIMM4
:
1212 fields
->f_uimm4
= value
;
1214 case M32R_OPERAND_UIMM5
:
1215 fields
->f_uimm5
= value
;
1217 case M32R_OPERAND_ULO16
:
1218 fields
->f_uimm16
= value
;
1222 /* xgettext:c-format */
1223 fprintf (stderr
, _("Unrecognized field %d while setting vma operand.\n"),
1229 /* Function to call before using the instruction builder tables. */
1232 m32r_cgen_init_ibld_table (cd
)
1235 cd
->insert_handlers
= & m32r_cgen_insert_handlers
[0];
1236 cd
->extract_handlers
= & m32r_cgen_extract_handlers
[0];
1238 cd
->insert_operand
= m32r_cgen_insert_operand
;
1239 cd
->extract_operand
= m32r_cgen_extract_operand
;
1241 cd
->get_int_operand
= m32r_cgen_get_int_operand
;
1242 cd
->set_int_operand
= m32r_cgen_set_int_operand
;
1243 cd
->get_vma_operand
= m32r_cgen_get_vma_operand
;
1244 cd
->set_vma_operand
= m32r_cgen_set_vma_operand
;