opcodes/ppc-opc.c

   1 /* ppc-opc.c -- PowerPC opcode list
   2    Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002
   3    Free Software Foundation, Inc.
   4    Written by Ian Lance Taylor, Cygnus Support
   5
   6 This file is part of GDB, GAS, and the GNU binutils.
   7
   8 GDB, GAS, and the GNU binutils are free software; you can redistribute
   9 them and/or modify them under the terms of the GNU General Public
  10 License as published by the Free Software Foundation; either version
  11 2, or (at your option) any later version.
  12
  13 GDB, GAS, and the GNU binutils are distributed in the hope that they
  14 will be useful, but WITHOUT ANY WARRANTY; without even the implied
  15 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
  16 the GNU General Public License for more details.
  17
  18 You should have received a copy of the GNU General Public License
  19 along with this file; see the file COPYING.  If not, write to the Free
  20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
  21 02111-1307, USA.  */
  22
  23 #include <stdio.h>
  24 #include "sysdep.h"
  25 #include "opcode/ppc.h"
  26 #include "opintl.h"
  27
  28 /* This file holds the PowerPC opcode table.  The opcode table
  29    includes almost all of the extended instruction mnemonics.  This
  30    permits the disassembler to use them, and simplifies the assembler
  31    logic, at the cost of increasing the table size.  The table is
  32    strictly constant data, so the compiler should be able to put it in
  33    the .text section.
  34
  35    This file also holds the operand table.  All knowledge about
  36    inserting operands into instructions and vice-versa is kept in this
  37    file.  */
  38 \f
  39 /* Local insertion and extraction functions.  */
  40
  41 static unsigned long insert_bat
  42   PARAMS ((unsigned long, long, int, const char **));
  43 static long extract_bat
  44   PARAMS ((unsigned long, int, int *));
  45 static unsigned long insert_bba
  46   PARAMS ((unsigned long, long, int, const char **));
  47 static long extract_bba
  48   PARAMS ((unsigned long, int, int *));
  49 static unsigned long insert_bd
  50   PARAMS ((unsigned long, long, int, const char **));
  51 static long extract_bd
  52   PARAMS ((unsigned long, int, int *));
  53 static unsigned long insert_bdm
  54   PARAMS ((unsigned long, long, int, const char **));
  55 static long extract_bdm
  56   PARAMS ((unsigned long, int, int *));
  57 static unsigned long insert_bdp
  58   PARAMS ((unsigned long, long, int, const char **));
  59 static long extract_bdp
  60   PARAMS ((unsigned long, int, int *));
  61 static int valid_bo
  62   PARAMS ((long, int));
  63 static unsigned long insert_bo
  64   PARAMS ((unsigned long, long, int, const char **));
  65 static long extract_bo
  66   PARAMS ((unsigned long, int, int *));
  67 static unsigned long insert_boe
  68   PARAMS ((unsigned long, long, int, const char **));
  69 static long extract_boe
  70   PARAMS ((unsigned long, int, int *));
  71 static unsigned long insert_ds
  72   PARAMS ((unsigned long, long, int, const char **));
  73 static long extract_ds
  74   PARAMS ((unsigned long, int, int *));
  75 static unsigned long insert_de
  76   PARAMS ((unsigned long, long, int, const char **));
  77 static long extract_de
  78   PARAMS ((unsigned long, int, int *));
  79 static unsigned long insert_des
  80   PARAMS ((unsigned long, long, int, const char **));
  81 static long extract_des
  82   PARAMS ((unsigned long, int, int *));
  83 static unsigned long insert_li
  84   PARAMS ((unsigned long, long, int, const char **));
  85 static long extract_li
  86   PARAMS ((unsigned long, int, int *));
  87 static unsigned long insert_mbe
  88   PARAMS ((unsigned long, long, int, const char **));
  89 static long extract_mbe
  90   PARAMS ((unsigned long, int, int *));
  91 static unsigned long insert_mb6
  92   PARAMS ((unsigned long, long, int, const char **));
  93 static long extract_mb6
  94   PARAMS ((unsigned long, int, int *));
  95 static unsigned long insert_nb
  96   PARAMS ((unsigned long, long, int, const char **));
  97 static long extract_nb
  98   PARAMS ((unsigned long, int, int *));
  99 static unsigned long insert_nsi
 100   PARAMS ((unsigned long, long, int, const char **));
 101 static long extract_nsi
 102   PARAMS ((unsigned long, int, int *));
 103 static unsigned long insert_pmrn
 104   PARAMS ((unsigned long, long, int, const char **));
 105 static long extract_pmrn
 106   PARAMS ((unsigned long, int, int *));
 107 static unsigned long insert_ral
 108   PARAMS ((unsigned long, long, int, const char **));
 109 static unsigned long insert_ram
 110   PARAMS ((unsigned long, long, int, const char **));
 111 static unsigned long insert_ras
 112   PARAMS ((unsigned long, long, int, const char **));
 113 static unsigned long insert_rbs
 114   PARAMS ((unsigned long, long, int, const char **));
 115 static long extract_rbs
 116   PARAMS ((unsigned long, int, int *));
 117 static unsigned long insert_sh6
 118   PARAMS ((unsigned long, long, int, const char **));
 119 static long extract_sh6
 120   PARAMS ((unsigned long, int, int *));
 121 static unsigned long insert_spr
 122   PARAMS ((unsigned long, long, int, const char **));
 123 static long extract_spr
 124   PARAMS ((unsigned long, int, int *));
 125 static unsigned long insert_tbr
 126   PARAMS ((unsigned long, long, int, const char **));
 127 static long extract_tbr
 128   PARAMS ((unsigned long, int, int *));
 129 static unsigned long insert_ev2
 130   PARAMS ((unsigned long, long, int, const char **));
 131 static long extract_ev2
 132   PARAMS ((unsigned long, int, int *));
 133 static unsigned long insert_ev4
 134   PARAMS ((unsigned long, long, int, const char **));
 135 static long extract_ev4
 136   PARAMS ((unsigned long, int, int *));
 137 static unsigned long insert_ev8
 138   PARAMS ((unsigned long, long, int, const char **));
 139 static long extract_ev8
 140   PARAMS ((unsigned long, int, int *));
 141 \f
 142 /* The operands table.
 143
 144    The fields are bits, shift, insert, extract, flags.
 145
 146    We used to put parens around the various additions, like the one
 147    for BA just below.  However, that caused trouble with feeble
 148    compilers with a limit on depth of a parenthesized expression, like
 149    (reportedly) the compiler in Microsoft Developer Studio 5.  So we
 150    omit the parens, since the macros are never used in a context where
 151    the addition will be ambiguous.  */
 152
 153 const struct powerpc_operand powerpc_operands[] =
 154 {
 155   /* The zero index is used to indicate the end of the list of
 156      operands.  */
 157 #define UNUSED 0
 158   { 0, 0, 0, 0, 0 },
 159
 160   /* The BA field in an XL form instruction.  */
 161 #define BA UNUSED + 1
 162 #define BA_MASK (0x1f << 16)
 163   { 5, 16, 0, 0, PPC_OPERAND_CR },
 164
 165   /* The BA field in an XL form instruction when it must be the same
 166      as the BT field in the same instruction.  */
 167 #define BAT BA + 1
 168   { 5, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
 169
 170   /* The BB field in an XL form instruction.  */
 171 #define BB BAT + 1
 172 #define BB_MASK (0x1f << 11)
 173   { 5, 11, 0, 0, PPC_OPERAND_CR },
 174
 175   /* The BB field in an XL form instruction when it must be the same
 176      as the BA field in the same instruction.  */
 177 #define BBA BB + 1
 178   { 5, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },
 179
 180   /* The BD field in a B form instruction.  The lower two bits are
 181      forced to zero.  */
 182 #define BD BBA + 1
 183   { 16, 0, insert_bd, extract_bd, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 184
 185   /* The BD field in a B form instruction when absolute addressing is
 186      used.  */
 187 #define BDA BD + 1
 188   { 16, 0, insert_bd, extract_bd, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
 189
 190   /* The BD field in a B form instruction when the - modifier is used.
 191      This sets the y bit of the BO field appropriately.  */
 192 #define BDM BDA + 1
 193   { 16, 0, insert_bdm, extract_bdm,
 194       PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 195
 196   /* The BD field in a B form instruction when the - modifier is used
 197      and absolute address is used.  */
 198 #define BDMA BDM + 1
 199   { 16, 0, insert_bdm, extract_bdm,
 200       PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
 201
 202   /* The BD field in a B form instruction when the + modifier is used.
 203      This sets the y bit of the BO field appropriately.  */
 204 #define BDP BDMA + 1
 205   { 16, 0, insert_bdp, extract_bdp,
 206       PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 207
 208   /* The BD field in a B form instruction when the + modifier is used
 209      and absolute addressing is used.  */
 210 #define BDPA BDP + 1
 211   { 16, 0, insert_bdp, extract_bdp,
 212       PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
 213
 214   /* The BF field in an X or XL form instruction.  */
 215 #define BF BDPA + 1
 216   { 3, 23, 0, 0, PPC_OPERAND_CR },
 217
 218   /* An optional BF field.  This is used for comparison instructions,
 219      in which an omitted BF field is taken as zero.  */
 220 #define OBF BF + 1
 221   { 3, 23, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
 222
 223   /* The BFA field in an X or XL form instruction.  */
 224 #define BFA OBF + 1
 225   { 3, 18, 0, 0, PPC_OPERAND_CR },
 226
 227   /* The BI field in a B form or XL form instruction.  */
 228 #define BI BFA + 1
 229 #define BI_MASK (0x1f << 16)
 230   { 5, 16, 0, 0, PPC_OPERAND_CR },
 231
 232   /* The BO field in a B form instruction.  Certain values are
 233      illegal.  */
 234 #define BO BI + 1
 235 #define BO_MASK (0x1f << 21)
 236   { 5, 21, insert_bo, extract_bo, 0 },
 237
 238   /* The BO field in a B form instruction when the + or - modifier is
 239      used.  This is like the BO field, but it must be even.  */
 240 #define BOE BO + 1
 241   { 5, 21, insert_boe, extract_boe, 0 },
 242
 243   /* The BT field in an X or XL form instruction.  */
 244 #define BT BOE + 1
 245   { 5, 21, 0, 0, PPC_OPERAND_CR },
 246
 247   /* The condition register number portion of the BI field in a B form
 248      or XL form instruction.  This is used for the extended
 249      conditional branch mnemonics, which set the lower two bits of the
 250      BI field.  This field is optional.  */
 251 #define CR BT + 1
 252   { 3, 18, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
 253
 254   /* The CRB field in an X form instruction.  */
 255 #define CRB CR + 1
 256   { 5, 6, 0, 0, 0 },
 257
 258   /* The CRFD field in an X form instruction.  */
 259 #define CRFD CRB + 1
 260   { 3, 23, 0, 0, PPC_OPERAND_CR },
 261
 262   /* The CRFS field in an X form instruction.  */
 263 #define CRFS CRFD + 1
 264   { 3, 0, 0, 0, PPC_OPERAND_CR },
 265
 266   /* The CT field in an X form instruction.  */
 267 #define CT CRFS + 1
 268 #define RD CT
 269   { 5, 21, 0, 0, PPC_OPERAND_OPTIONAL },
 270
 271   /* The D field in a D form instruction.  This is a displacement off
 272      a register, and implies that the next operand is a register in
 273      parentheses.  */
 274 #define D CT + 1
 275   { 16, 0, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
 276
 277   /* The DE field in a DE form instruction.  This is like D, but is 12
 278      bits only.  */
 279 #define DE D + 1
 280   { 14, 0, insert_de, extract_de, PPC_OPERAND_PARENS },
 281
 282   /* The DES field in a DES form instruction.  This is like DS, but is 14
 283      bits only (12 stored.)  */
 284 #define DES DE + 1
 285   { 14, 0, insert_des, extract_des, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
 286
 287   /* The DS field in a DS form instruction.  This is like D, but the
 288      lower two bits are forced to zero.  */
 289 #define DS DES + 1
 290   { 16, 0, insert_ds, extract_ds,
 291       PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },
 292
 293   /* The E field in a wrteei instruction.  */
 294 #define E DS + 1
 295   { 1, 15, 0, 0, 0 },
 296
 297   /* The FL1 field in a POWER SC form instruction.  */
 298 #define FL1 E + 1
 299   { 4, 12, 0, 0, 0 },
 300
 301   /* The FL2 field in a POWER SC form instruction.  */
 302 #define FL2 FL1 + 1
 303   { 3, 2, 0, 0, 0 },
 304
 305   /* The FLM field in an XFL form instruction.  */
 306 #define FLM FL2 + 1
 307   { 8, 17, 0, 0, 0 },
 308
 309   /* The FRA field in an X or A form instruction.  */
 310 #define FRA FLM + 1
 311 #define FRA_MASK (0x1f << 16)
 312   { 5, 16, 0, 0, PPC_OPERAND_FPR },
 313
 314   /* The FRB field in an X or A form instruction.  */
 315 #define FRB FRA + 1
 316 #define FRB_MASK (0x1f << 11)
 317   { 5, 11, 0, 0, PPC_OPERAND_FPR },
 318
 319   /* The FRC field in an A form instruction.  */
 320 #define FRC FRB + 1
 321 #define FRC_MASK (0x1f << 6)
 322   { 5, 6, 0, 0, PPC_OPERAND_FPR },
 323
 324   /* The FRS field in an X form instruction or the FRT field in a D, X
 325      or A form instruction.  */
 326 #define FRS FRC + 1
 327 #define FRT FRS
 328   { 5, 21, 0, 0, PPC_OPERAND_FPR },
 329
 330   /* The FXM field in an XFX instruction.  */
 331 #define FXM FRS + 1
 332 #define FXM_MASK (0xff << 12)
 333   { 8, 12, 0, 0, 0 },
 334
 335   /* The L field in a D or X form instruction.  */
 336 #define L FXM + 1
 337   { 1, 21, 0, 0, PPC_OPERAND_OPTIONAL },
 338
 339   /* The LEV field in a POWER SC form instruction.  */
 340 #define LEV L + 1
 341   { 7, 5, 0, 0, 0 },
 342
 343   /* The LI field in an I form instruction.  The lower two bits are
 344      forced to zero.  */
 345 #define LI LEV + 1
 346   { 26, 0, insert_li, extract_li, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 347
 348   /* The LI field in an I form instruction when used as an absolute
 349      address.  */
 350 #define LIA LI + 1
 351   { 26, 0, insert_li, extract_li, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
 352
 353   /* The LS field in an X (sync) form instruction.  */
 354 #define LS LIA + 1
 355   { 2, 21, 0, 0, PPC_OPERAND_OPTIONAL },
 356
 357   /* The MB field in an M form instruction.  */
 358 #define MB LS + 1
 359 #define MB_MASK (0x1f << 6)
 360   { 5, 6, 0, 0, 0 },
 361
 362   /* The ME field in an M form instruction.  */
 363 #define ME MB + 1
 364 #define ME_MASK (0x1f << 1)
 365   { 5, 1, 0, 0, 0 },
 366
 367   /* The MB and ME fields in an M form instruction expressed a single
 368      operand which is a bitmask indicating which bits to select.  This
 369      is a two operand form using PPC_OPERAND_NEXT.  See the
 370      description in opcode/ppc.h for what this means.  */
 371 #define MBE ME + 1
 372   { 5, 6, 0, 0, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
 373   { 32, 0, insert_mbe, extract_mbe, 0 },
 374
 375   /* The MB or ME field in an MD or MDS form instruction.  The high
 376      bit is wrapped to the low end.  */
 377 #define MB6 MBE + 2
 378 #define ME6 MB6
 379 #define MB6_MASK (0x3f << 5)
 380   { 6, 5, insert_mb6, extract_mb6, 0 },
 381
 382   /* The MO field in an mbar instruction.  */
 383 #define MO MB6 + 1
 384   { 5, 21, 0, 0, 0 },
 385
 386   /* The NB field in an X form instruction.  The value 32 is stored as
 387      0.  */
 388 #define NB MO + 1
 389   { 6, 11, insert_nb, extract_nb, 0 },
 390
 391   /* The NSI field in a D form instruction.  This is the same as the
 392      SI field, only negated.  */
 393 #define NSI NB + 1
 394   { 16, 0, insert_nsi, extract_nsi,
 395       PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
 396
 397   /* The PMRN field in an X form instruction.  */
 398 #define PMRN NSI + 1
 399   { 16, 0, insert_pmrn, extract_pmrn, PPC_OPERAND_GPR },
 400
 401   /* The RA field in an D, DS, X, XO, M, or MDS form instruction.  */
 402 #define RA PMRN + 1
 403 #define RA_MASK (0x1f << 16)
 404   { 5, 16, 0, 0, PPC_OPERAND_GPR },
 405
 406   /* The RA field in a D or X form instruction which is an updating
 407      load, which means that the RA field may not be zero and may not
 408      equal the RT field.  */
 409 #define RAL RA + 1
 410   { 5, 16, insert_ral, 0, PPC_OPERAND_GPR },
 411
 412   /* The RA field in an lmw instruction, which has special value
 413      restrictions.  */
 414 #define RAM RAL + 1
 415   { 5, 16, insert_ram, 0, PPC_OPERAND_GPR },
 416
 417   /* The RA field in a D or X form instruction which is an updating
 418      store or an updating floating point load, which means that the RA
 419      field may not be zero.  */
 420 #define RAS RAM + 1
 421   { 5, 16, insert_ras, 0, PPC_OPERAND_GPR },
 422
 423   /* The RB field in an X, XO, M, or MDS form instruction.  */
 424 #define RB RAS + 1
 425 #define RB_MASK (0x1f << 11)
 426   { 5, 11, 0, 0, PPC_OPERAND_GPR },
 427
 428   /* The RB field in an X form instruction when it must be the same as
 429      the RS field in the instruction.  This is used for extended
 430      mnemonics like mr.  */
 431 #define RBS RB + 1
 432   { 5, 1, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },
 433
 434   /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
 435      instruction or the RT field in a D, DS, X, XFX or XO form
 436      instruction.  */
 437 #define RS RBS + 1
 438 #define RT RS
 439 #define RT_MASK (0x1f << 21)
 440   { 5, 21, 0, 0, PPC_OPERAND_GPR },
 441
 442   /* The SH field in an X or M form instruction.  */
 443 #define SH RS + 1
 444 #define SH_MASK (0x1f << 11)
 445   { 5, 11, 0, 0, 0 },
 446
 447   /* The SH field in an MD form instruction.  This is split.  */
 448 #define SH6 SH + 1
 449 #define SH6_MASK ((0x1f << 11) | (1 << 1))
 450   { 6, 1, insert_sh6, extract_sh6, 0 },
 451
 452   /* The SI field in a D form instruction.  */
 453 #define SI SH6 + 1
 454   { 16, 0, 0, 0, PPC_OPERAND_SIGNED },
 455
 456   /* The SI field in a D form instruction when we accept a wide range
 457      of positive values.  */
 458 #define SISIGNOPT SI + 1
 459   { 16, 0, 0, 0, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
 460
 461   /* The SPR field in an XFX form instruction.  This is flipped--the
 462      lower 5 bits are stored in the upper 5 and vice- versa.  */
 463 #define SPR SISIGNOPT + 1
 464 #define SPR_MASK (0x3ff << 11)
 465   { 10, 11, insert_spr, extract_spr, 0 },
 466
 467   /* The BAT index number in an XFX form m[ft]ibat[lu] instruction.  */
 468 #define SPRBAT SPR + 1
 469 #define SPRBAT_MASK (0x3 << 17)
 470   { 2, 17, 0, 0, 0 },
 471
 472   /* The SPRG register number in an XFX form m[ft]sprg instruction.  */
 473 #define SPRG SPRBAT + 1
 474 #define SPRG_MASK (0x3 << 16)
 475   { 2, 16, 0, 0, 0 },
 476
 477   /* The SR field in an X form instruction.  */
 478 #define SR SPRG + 1
 479   { 4, 16, 0, 0, 0 },
 480
 481   /* The STRM field in an X AltiVec form instruction.  */
 482 #define STRM SR + 1
 483 #define STRM_MASK (0x3 << 21)
 484   { 2, 21, 0, 0, 0 },
 485
 486   /* The SV field in a POWER SC form instruction.  */
 487 #define SV STRM + 1
 488   { 14, 2, 0, 0, 0 },
 489
 490   /* The TBR field in an XFX form instruction.  This is like the SPR
 491      field, but it is optional.  */
 492 #define TBR SV + 1
 493   { 10, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL },
 494
 495   /* The TO field in a D or X form instruction.  */
 496 #define TO TBR + 1
 497 #define TO_MASK (0x1f << 21)
 498   { 5, 21, 0, 0, 0 },
 499
 500   /* The U field in an X form instruction.  */
 501 #define U TO + 1
 502   { 4, 12, 0, 0, 0 },
 503
 504   /* The UI field in a D form instruction.  */
 505 #define UI U + 1
 506   { 16, 0, 0, 0, 0 },
 507
 508   /* The VA field in a VA, VX or VXR form instruction. */
 509 #define VA UI + 1
 510 #define VA_MASK (0x1f << 16)
 511   { 5, 16, 0, 0, PPC_OPERAND_VR },
 512
 513   /* The VB field in a VA, VX or VXR form instruction. */
 514 #define VB VA + 1
 515 #define VB_MASK (0x1f << 11)
 516   { 5, 11, 0, 0, PPC_OPERAND_VR },
 517
 518   /* The VC field in a VA form instruction. */
 519 #define VC VB + 1
 520 #define VC_MASK (0x1f << 6)
 521   { 5, 6, 0, 0, PPC_OPERAND_VR },
 522
 523   /* The VD or VS field in a VA, VX, VXR or X form instruction. */
 524 #define VD VC + 1
 525 #define VS VD
 526 #define VD_MASK (0x1f << 21)
 527   { 5, 21, 0, 0, PPC_OPERAND_VR },
 528
 529   /* The SIMM field in a VX form instruction. */
 530 #define SIMM VD + 1
 531   { 5, 16, 0, 0, PPC_OPERAND_SIGNED},
 532
 533   /* The UIMM field in a VX form instruction. */
 534 #define UIMM SIMM + 1
 535   { 5, 16, 0, 0, 0 },
 536
 537   /* The SHB field in a VA form instruction. */
 538 #define SHB UIMM + 1
 539   { 4, 6, 0, 0, 0 },
 540
 541   /* The other UIMM field in a EVX form instruction. */
 542 #define EVUIMM SHB + 1
 543   { 5, 11, 0, 0, 0 },
 544
 545   /* The other UIMM field in a half word EVX form instruction. */
 546 #define EVUIMM_2 EVUIMM + 1
 547   { 32, 11, insert_ev2, extract_ev2, PPC_OPERAND_PARENS },
 548
 549   /* The other UIMM field in a word EVX form instruction. */
 550 #define EVUIMM_4 EVUIMM_2 + 1
 551   { 32, 11, insert_ev4, extract_ev4, PPC_OPERAND_PARENS },
 552
 553   /* The other UIMM field in a double EVX form instruction. */
 554 #define EVUIMM_8 EVUIMM_4 + 1
 555   { 32, 11, insert_ev8, extract_ev8, PPC_OPERAND_PARENS },
 556
 557   /* The WS field.  */
 558 #define WS EVUIMM_8 + 1
 559 #define WS_MASK (0x7 << 11)
 560   { 3, 11, 0, 0, 0 },
 561
 562   /* The L field in an mtmsrd instruction */
 563 #define MTMSRD_L WS + 1
 564   { 1, 16, 0, 0, PPC_OPERAND_OPTIONAL },
 565
 566 };
 567
 568 /* The functions used to insert and extract complicated operands.  */
 569
 570 /* The BA field in an XL form instruction when it must be the same as
 571    the BT field in the same instruction.  This operand is marked FAKE.
 572    The insertion function just copies the BT field into the BA field,
 573    and the extraction function just checks that the fields are the
 574    same.  */
 575
 576 /*ARGSUSED*/
 577 static unsigned long
 578 insert_bat (insn, value, dialect, errmsg)
 579      unsigned long insn;
 580      long value ATTRIBUTE_UNUSED;
 581      int dialect ATTRIBUTE_UNUSED;
 582      const char **errmsg ATTRIBUTE_UNUSED;
 583 {
 584   return insn | (((insn >> 21) & 0x1f) << 16);
 585 }
 586
 587 static long
 588 extract_bat (insn, dialect, invalid)
 589      unsigned long insn;
 590      int dialect ATTRIBUTE_UNUSED;
 591      int *invalid;
 592 {
 593   if (invalid != (int *) NULL
 594       && ((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
 595     *invalid = 1;
 596   return 0;
 597 }
 598
 599 /* The BB field in an XL form instruction when it must be the same as
 600    the BA field in the same instruction.  This operand is marked FAKE.
 601    The insertion function just copies the BA field into the BB field,
 602    and the extraction function just checks that the fields are the
 603    same.  */
 604
 605 /*ARGSUSED*/
 606 static unsigned long
 607 insert_bba (insn, value, dialect, errmsg)
 608      unsigned long insn;
 609      long value ATTRIBUTE_UNUSED;
 610      int dialect ATTRIBUTE_UNUSED;
 611      const char **errmsg ATTRIBUTE_UNUSED;
 612 {
 613   return insn | (((insn >> 16) & 0x1f) << 11);
 614 }
 615
 616 static long
 617 extract_bba (insn, dialect, invalid)
 618      unsigned long insn;
 619      int dialect ATTRIBUTE_UNUSED;
 620      int *invalid;
 621 {
 622   if (invalid != (int *) NULL
 623       && ((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
 624     *invalid = 1;
 625   return 0;
 626 }
 627
 628 /* The BD field in a B form instruction.  The lower two bits are
 629    forced to zero.  */
 630
 631 /*ARGSUSED*/
 632 static unsigned long
 633 insert_bd (insn, value, dialect, errmsg)
 634      unsigned long insn;
 635      long value;
 636      int dialect ATTRIBUTE_UNUSED;
 637      const char **errmsg ATTRIBUTE_UNUSED;
 638 {
 639   return insn | (value & 0xfffc);
 640 }
 641
 642 /*ARGSUSED*/
 643 static long
 644 extract_bd (insn, dialect, invalid)
 645      unsigned long insn;
 646      int dialect ATTRIBUTE_UNUSED;
 647      int *invalid ATTRIBUTE_UNUSED;
 648 {
 649   return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
 650 }
 651
 652 /* The BD field in a B form instruction when the - modifier is used.
 653    This modifier means that the branch is not expected to be taken.
 654    For chips built to versions of the architecture prior to version 2
 655    (ie. not Power4 compatible), we set the y bit of the BO field to 1
 656    if the offset is negative.  When extracting, we require that the y
 657    bit be 1 and that the offset be positive, since if the y bit is 0
 658    we just want to print the normal form of the instruction.
 659    Power4 compatible targets use two bits, "a", and "t", instead of
 660    the "y" bit.  "at" == 00 => no hint, "at" == 01 => unpredictable,
 661    "at" == 10 => not taken, "at" == 11 => taken.  The "t" bit is 00001
 662    in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000
 663    for branch on CTR.  We only handle the taken/not-taken hint here.  */
 664
 665 /*ARGSUSED*/
 666 static unsigned long
 667 insert_bdm (insn, value, dialect, errmsg)
 668      unsigned long insn;
 669      long value;
 670      int dialect;
 671      const char **errmsg ATTRIBUTE_UNUSED;
 672 {
 673   if ((dialect & PPC_OPCODE_POWER4) == 0)
 674     {
 675       if ((value & 0x8000) != 0)
 676         insn |= 1 << 21;
 677     }
 678   else
 679     {
 680       if ((insn & (0x14 << 21)) == (0x04 << 21))
 681         insn |= 0x02 << 21;
 682       else if ((insn & (0x14 << 21)) == (0x10 << 21))
 683         insn |= 0x08 << 21;
 684     }
 685   return insn | (value & 0xfffc);
 686 }
 687
 688 static long
 689 extract_bdm (insn, dialect, invalid)
 690      unsigned long insn;
 691      int dialect;
 692      int *invalid;
 693 {
 694   if (invalid != (int *) NULL)
 695     {
 696       if ((dialect & PPC_OPCODE_POWER4) == 0)
 697         {
 698           if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0))
 699             *invalid = 1;
 700         }
 701       else
 702         {
 703           if ((insn & (0x17 << 21)) != (0x06 << 21)
 704               && (insn & (0x1d << 21)) != (0x18 << 21))
 705             *invalid = 1;
 706         }
 707     }
 708   return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
 709 }
 710
 711 /* The BD field in a B form instruction when the + modifier is used.
 712    This is like BDM, above, except that the branch is expected to be
 713    taken.  */
 714
 715 /*ARGSUSED*/
 716 static unsigned long
 717 insert_bdp (insn, value, dialect, errmsg)
 718      unsigned long insn;
 719      long value;
 720      int dialect;
 721      const char **errmsg ATTRIBUTE_UNUSED;
 722 {
 723   if ((dialect & PPC_OPCODE_POWER4) == 0)
 724     {
 725       if ((value & 0x8000) == 0)
 726         insn |= 1 << 21;
 727     }
 728   else
 729     {
 730       if ((insn & (0x14 << 21)) == (0x04 << 21))
 731         insn |= 0x03 << 21;
 732       else if ((insn & (0x14 << 21)) == (0x10 << 21))
 733         insn |= 0x09 << 21;
 734     }
 735   return insn | (value & 0xfffc);
 736 }
 737
 738 static long
 739 extract_bdp (insn, dialect, invalid)
 740      unsigned long insn;
 741      int dialect;
 742      int *invalid;
 743 {
 744   if (invalid != (int *) NULL)
 745     {
 746       if ((dialect & PPC_OPCODE_POWER4) == 0)
 747         {
 748           if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0))
 749             *invalid = 1;
 750         }
 751       else
 752         {
 753           if ((insn & (0x17 << 21)) != (0x07 << 21)
 754               && (insn & (0x1d << 21)) != (0x19 << 21))
 755             *invalid = 1;
 756         }
 757     }
 758   return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
 759 }
 760
 761 /* Check for legal values of a BO field.  */
 762
 763 static int
 764 valid_bo (value, dialect)
 765      long value;
 766      int dialect;
 767 {
 768   if ((dialect & PPC_OPCODE_POWER4) == 0)
 769     {
 770       /* Certain encodings have bits that are required to be zero.
 771          These are (z must be zero, y may be anything):
 772              001zy
 773              011zy
 774              1z00y
 775              1z01y
 776              1z1zz
 777       */
 778       switch (value & 0x14)
 779         {
 780         default:
 781         case 0:
 782           return 1;
 783         case 0x4:
 784           return (value & 0x2) == 0;
 785         case 0x10:
 786           return (value & 0x8) == 0;
 787         case 0x14:
 788           return value == 0x14;
 789         }
 790     }
 791   else
 792     {
 793       /* Certain encodings have bits that are required to be zero.
 794          These are (z must be zero, a & t may be anything):
 795              0000z
 796              0001z
 797              0100z
 798              0101z
 799              001at
 800              011at
 801              1a00t
 802              1a01t
 803              1z1zz
 804       */
 805       if ((value & 0x14) == 0)
 806         return (value & 0x1) == 0;
 807       else if ((value & 0x14) == 0x14)
 808         return value == 0x14;
 809       else
 810         return 1;
 811     }
 812 }
 813
 814 /* The BO field in a B form instruction.  Warn about attempts to set
 815    the field to an illegal value.  */
 816
 817 static unsigned long
 818 insert_bo (insn, value, dialect, errmsg)
 819      unsigned long insn;
 820      long value;
 821      int dialect;
 822      const char **errmsg;
 823 {
 824   if (errmsg != (const char **) NULL
 825       && ! valid_bo (value, dialect))
 826     *errmsg = _("invalid conditional option");
 827   return insn | ((value & 0x1f) << 21);
 828 }
 829
 830 static long
 831 extract_bo (insn, dialect, invalid)
 832      unsigned long insn;
 833      int dialect;
 834      int *invalid;
 835 {
 836   long value;
 837
 838   value = (insn >> 21) & 0x1f;
 839   if (invalid != (int *) NULL
 840       && ! valid_bo (value, dialect))
 841     *invalid = 1;
 842   return value;
 843 }
 844
 845 /* The BO field in a B form instruction when the + or - modifier is
 846    used.  This is like the BO field, but it must be even.  When
 847    extracting it, we force it to be even.  */
 848
 849 static unsigned long
 850 insert_boe (insn, value, dialect, errmsg)
 851      unsigned long insn;
 852      long value;
 853      int dialect;
 854      const char **errmsg;
 855 {
 856   if (errmsg != (const char **) NULL)
 857     {
 858       if (! valid_bo (value, dialect))
 859         *errmsg = _("invalid conditional option");
 860       else if ((value & 1) != 0)
 861         *errmsg = _("attempt to set y bit when using + or - modifier");
 862     }
 863   return insn | ((value & 0x1f) << 21);
 864 }
 865
 866 static long
 867 extract_boe (insn, dialect, invalid)
 868      unsigned long insn;
 869      int dialect;
 870      int *invalid;
 871 {
 872   long value;
 873
 874   value = (insn >> 21) & 0x1f;
 875   if (invalid != (int *) NULL
 876       && ! valid_bo (value, dialect))
 877     *invalid = 1;
 878   return value & 0x1e;
 879 }
 880
 881 static unsigned long
 882 insert_ev2 (insn, value, dialect, errmsg)
 883      unsigned long insn;
 884      long value;
 885      int dialect ATTRIBUTE_UNUSED;
 886      const char ** errmsg ATTRIBUTE_UNUSED;
 887 {
 888   if ((value & 1) != 0 && errmsg != NULL)
 889     *errmsg = _("offset not a multiple of 2");
 890   if ((value > 62) != 0 && errmsg != NULL)
 891     *errmsg = _("offset greater than 62");
 892   return insn | ((value & 0xf8) << 8);
 893 }
 894
 895 static long
 896 extract_ev2 (insn, dialect, invalid)
 897      unsigned long insn;
 898      int dialect ATTRIBUTE_UNUSED;
 899      int * invalid ATTRIBUTE_UNUSED;
 900 {
 901   return (insn >> 8) & 0xf8;
 902 }
 903
 904 static unsigned long
 905 insert_ev4 (insn, value, dialect, errmsg)
 906      unsigned long insn;
 907      long value;
 908      int dialect ATTRIBUTE_UNUSED;
 909      const char ** errmsg ATTRIBUTE_UNUSED;
 910 {
 911   if ((value & 3) != 0 && errmsg != NULL)
 912     *errmsg = _("offset not a multiple of 4");
 913   if ((value > 124) != 0 && errmsg != NULL)
 914     *errmsg = _("offset greater than 124");
 915   return insn | ((value & 0xf8) << 8);
 916 }
 917
 918 static long
 919 extract_ev4 (insn, dialect, invalid)
 920      unsigned long insn;
 921      int dialect ATTRIBUTE_UNUSED;
 922      int * invalid ATTRIBUTE_UNUSED;
 923 {
 924   return (insn >> 8) & 0xf8;
 925 }
 926
 927 static unsigned long
 928 insert_ev8 (insn, value, dialect, errmsg)
 929      unsigned long insn;
 930      long value;
 931      int dialect ATTRIBUTE_UNUSED;
 932      const char ** errmsg ATTRIBUTE_UNUSED;
 933 {
 934   if ((value & 7) != 0 && errmsg != NULL)
 935     *errmsg = _("offset not a multiple of 8");
 936   if ((value > 248) != 0 && errmsg != NULL)
 937     *errmsg = _("offset greater than 248");
 938   return insn | ((value & 0xf8) << 8);
 939 }
 940
 941 static long
 942 extract_ev8 (insn, dialect, invalid)
 943      unsigned long insn;
 944      int dialect ATTRIBUTE_UNUSED;
 945      int * invalid ATTRIBUTE_UNUSED;
 946 {
 947   return (insn >> 8) & 0xf8;
 948 }
 949
 950 /* The DS field in a DS form instruction.  This is like D, but the
 951    lower two bits are forced to zero.  */
 952
 953 /*ARGSUSED*/
 954 static unsigned long
 955 insert_ds (insn, value, dialect, errmsg)
 956      unsigned long insn;
 957      long value;
 958      int dialect ATTRIBUTE_UNUSED;
 959      const char **errmsg;
 960 {
 961   if ((value & 3) != 0 && errmsg != NULL)
 962     *errmsg = _("offset not a multiple of 4");
 963   return insn | (value & 0xfffc);
 964 }
 965
 966 /*ARGSUSED*/
 967 static long
 968 extract_ds (insn, dialect, invalid)
 969      unsigned long insn;
 970      int dialect ATTRIBUTE_UNUSED;
 971      int *invalid ATTRIBUTE_UNUSED;
 972 {
 973   return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
 974 }
 975
 976 /* The DE field in a DE form instruction.  */
 977
 978 /*ARGSUSED*/
 979 static unsigned long
 980 insert_de (insn, value, dialect, errmsg)
 981      unsigned long insn;
 982      long value;
 983      int dialect ATTRIBUTE_UNUSED;
 984      const char **errmsg;
 985 {
 986   if ((value > 2047 || value < -2048) && errmsg != NULL)
 987     *errmsg = _("offset not between -2048 and 2047");
 988   return insn | ((value << 4) & 0xfff0);
 989 }
 990
 991 /*ARGSUSED*/
 992 static long
 993 extract_de (insn, dialect, invalid)
 994      unsigned long insn;
 995      int dialect ATTRIBUTE_UNUSED;
 996      int *invalid ATTRIBUTE_UNUSED;
 997 {
 998   return (insn & 0xfff0) >> 4;
 999 }
1000
1001 /* The DES field in a DES form instruction.  */
1002
1003 /*ARGSUSED*/
1004 static unsigned long
1005 insert_des (insn, value, dialect, errmsg)
1006      unsigned long insn;
1007      long value;
1008      int dialect ATTRIBUTE_UNUSED;
1009      const char **errmsg;
1010 {
1011   if ((value > 8191 || value < -8192) && errmsg != NULL)
1012     *errmsg = _("offset not between -8192 and 8191");
1013   else if ((value & 3) != 0 && errmsg != NULL)
1014     *errmsg = _("offset not a multiple of 4");
1015   return insn | ((value << 2) & 0xfff0);
1016 }
1017
1018 /*ARGSUSED*/
1019 static long
1020 extract_des (insn, dialect, invalid)
1021      unsigned long insn;
1022      int dialect ATTRIBUTE_UNUSED;
1023      int *invalid ATTRIBUTE_UNUSED;
1024 {
1025   return (((insn >> 2) & 0x3ffc) ^ 0x2000) - 0x2000;
1026 }
1027
1028 /* The LI field in an I form instruction.  The lower two bits are
1029    forced to zero.  */
1030
1031 /*ARGSUSED*/
1032 static unsigned long
1033 insert_li (insn, value, dialect, errmsg)
1034      unsigned long insn;
1035      long value;
1036      int dialect ATTRIBUTE_UNUSED;
1037      const char **errmsg;
1038 {
1039   if ((value & 3) != 0 && errmsg != (const char **) NULL)
1040     *errmsg = _("ignoring least significant bits in branch offset");
1041   return insn | (value & 0x3fffffc);
1042 }
1043
1044 /*ARGSUSED*/
1045 static long
1046 extract_li (insn, dialect, invalid)
1047      unsigned long insn;
1048      int dialect ATTRIBUTE_UNUSED;
1049      int *invalid ATTRIBUTE_UNUSED;
1050 {
1051   return ((insn & 0x3fffffc) ^ 0x2000000) - 0x2000000;
1052 }
1053
1054 /* The MB and ME fields in an M form instruction expressed as a single
1055    operand which is itself a bitmask.  The extraction function always
1056    marks it as invalid, since we never want to recognize an
1057    instruction which uses a field of this type.  */
1058
1059 static unsigned long
1060 insert_mbe (insn, value, dialect, errmsg)
1061      unsigned long insn;
1062      long value;
1063      int dialect ATTRIBUTE_UNUSED;
1064      const char **errmsg;
1065 {
1066   unsigned long uval, mask;
1067   int mb, me, mx, count, last;
1068
1069   uval = value;
1070
1071   if (uval == 0)
1072     {
1073       if (errmsg != (const char **) NULL)
1074         *errmsg = _("illegal bitmask");
1075       return insn;
1076     }
1077
1078   mb = 0;
1079   me = 32;
1080   if ((uval & 1) != 0)
1081     last = 1;
1082   else
1083     last = 0;
1084   count = 0;
1085
1086   /* mb: location of last 0->1 transition */
1087   /* me: location of last 1->0 transition */
1088   /* count: # transitions */
1089
1090   for (mx = 0, mask = (long) 1 << 31; mx < 32; ++mx, mask >>= 1)
1091     {
1092       if ((uval & mask) && !last)
1093         {
1094           ++count;
1095           mb = mx;
1096           last = 1;
1097         }
1098       else if (!(uval & mask) && last)
1099         {
1100           ++count;
1101           me = mx;
1102           last = 0;
1103         }
1104     }
1105   if (me == 0)
1106     me = 32;
1107
1108   if (count != 2 && (count != 0 || ! last))
1109     {
1110       if (errmsg != (const char **) NULL)
1111         *errmsg = _("illegal bitmask");
1112     }
1113
1114   return insn | (mb << 6) | ((me - 1) << 1);
1115 }
1116
1117 static long
1118 extract_mbe (insn, dialect, invalid)
1119      unsigned long insn;
1120      int dialect ATTRIBUTE_UNUSED;
1121      int *invalid;
1122 {
1123   long ret;
1124   int mb, me;
1125   int i;
1126
1127   if (invalid != (int *) NULL)
1128     *invalid = 1;
1129
1130   mb = (insn >> 6) & 0x1f;
1131   me = (insn >> 1) & 0x1f;
1132   if (mb < me + 1)
1133     {
1134       ret = 0;
1135       for (i = mb; i <= me; i++)
1136         ret |= (long) 1 << (31 - i);
1137     }
1138   else if (mb == me + 1)
1139     ret = ~0;
1140   else /* (mb > me + 1) */
1141     {
1142       ret = ~ (long) 0;
1143       for (i = me + 1; i < mb; i++)
1144         ret &= ~ ((long) 1 << (31 - i));
1145     }
1146   return ret;
1147 }
1148
1149 /* The MB or ME field in an MD or MDS form instruction.  The high bit
1150    is wrapped to the low end.  */
1151
1152 /*ARGSUSED*/
1153 static unsigned long
1154 insert_mb6 (insn, value, dialect, errmsg)
1155      unsigned long insn;
1156      long value;
1157      int dialect ATTRIBUTE_UNUSED;
1158      const char **errmsg ATTRIBUTE_UNUSED;
1159 {
1160   return insn | ((value & 0x1f) << 6) | (value & 0x20);
1161 }
1162
1163 /*ARGSUSED*/
1164 static long
1165 extract_mb6 (insn, dialect, invalid)
1166      unsigned long insn;
1167      int dialect ATTRIBUTE_UNUSED;
1168      int *invalid ATTRIBUTE_UNUSED;
1169 {
1170   return ((insn >> 6) & 0x1f) | (insn & 0x20);
1171 }
1172
1173 /* The NB field in an X form instruction.  The value 32 is stored as
1174    0.  */
1175
1176 static unsigned long
1177 insert_nb (insn, value, dialect, errmsg)
1178      unsigned long insn;
1179      long value;
1180      int dialect ATTRIBUTE_UNUSED;
1181      const char **errmsg;
1182 {
1183   if (value < 0 || value > 32)
1184     *errmsg = _("value out of range");
1185   if (value == 32)
1186     value = 0;
1187   return insn | ((value & 0x1f) << 11);
1188 }
1189
1190 /*ARGSUSED*/
1191 static long
1192 extract_nb (insn, dialect, invalid)
1193      unsigned long insn;
1194      int dialect ATTRIBUTE_UNUSED;
1195      int *invalid ATTRIBUTE_UNUSED;
1196 {
1197   long ret;
1198
1199   ret = (insn >> 11) & 0x1f;
1200   if (ret == 0)
1201     ret = 32;
1202   return ret;
1203 }
1204
1205 /* The NSI field in a D form instruction.  This is the same as the SI
1206    field, only negated.  The extraction function always marks it as
1207    invalid, since we never want to recognize an instruction which uses
1208    a field of this type.  */
1209
1210 /*ARGSUSED*/
1211 static unsigned long
1212 insert_nsi (insn, value, dialect, errmsg)
1213      unsigned long insn;
1214      long value;
1215      int dialect ATTRIBUTE_UNUSED;
1216      const char **errmsg ATTRIBUTE_UNUSED;
1217 {
1218   return insn | ((- value) & 0xffff);
1219 }
1220
1221 static long
1222 extract_nsi (insn, dialect, invalid)
1223      unsigned long insn;
1224      int dialect ATTRIBUTE_UNUSED;
1225      int *invalid;
1226 {
1227   if (invalid != (int *) NULL)
1228     *invalid = 1;
1229   return - (((insn & 0xffff) ^ 0x8000) - 0x8000);
1230 }
1231
1232 /* The PMRN field in a X form instruction.
1233    This has 5+5 bits switched around.  */
1234
1235 static unsigned long
1236 insert_pmrn (insn, value, dialect, errmsg)
1237      unsigned long insn;
1238      long value;
1239      int dialect ATTRIBUTE_UNUSED;
1240      const char **errmsg ATTRIBUTE_UNUSED;
1241 {
1242   return insn | ((value & 0x1f) << 16) | ((value & 0x3e) << 11);
1243 }
1244
1245 static long
1246 extract_pmrn (insn, dialect, invalid)
1247      unsigned long insn;
1248      int dialect ATTRIBUTE_UNUSED;
1249      int *invalid ATTRIBUTE_UNUSED;
1250 {
1251   return ((insn >> 16) & 0x1f) | ((insn >> 11) & 0x3e);
1252 }
1253
1254 /* The RA field in a D or X form instruction which is an updating
1255    load, which means that the RA field may not be zero and may not
1256    equal the RT field.  */
1257
1258 static unsigned long
1259 insert_ral (insn, value, dialect, errmsg)
1260      unsigned long insn;
1261      long value;
1262      int dialect ATTRIBUTE_UNUSED;
1263      const char **errmsg;
1264 {
1265   if (value == 0
1266       || (unsigned long) value == ((insn >> 21) & 0x1f))
1267     *errmsg = "invalid register operand when updating";
1268   return insn | ((value & 0x1f) << 16);
1269 }
1270
1271 /* The RA field in an lmw instruction, which has special value
1272    restrictions.  */
1273
1274 static unsigned long
1275 insert_ram (insn, value, dialect, errmsg)
1276      unsigned long insn;
1277      long value;
1278      int dialect ATTRIBUTE_UNUSED;
1279      const char **errmsg;
1280 {
1281   if ((unsigned long) value >= ((insn >> 21) & 0x1f))
1282     *errmsg = _("index register in load range");
1283   return insn | ((value & 0x1f) << 16);
1284 }
1285
1286 /* The RA field in a D or X form instruction which is an updating
1287    store or an updating floating point load, which means that the RA
1288    field may not be zero.  */
1289
1290 static unsigned long
1291 insert_ras (insn, value, dialect, errmsg)
1292      unsigned long insn;
1293      long value;
1294      int dialect ATTRIBUTE_UNUSED;
1295      const char **errmsg;
1296 {
1297   if (value == 0)
1298     *errmsg = _("invalid register operand when updating");
1299   return insn | ((value & 0x1f) << 16);
1300 }
1301
1302 /* The RB field in an X form instruction when it must be the same as
1303    the RS field in the instruction.  This is used for extended
1304    mnemonics like mr.  This operand is marked FAKE.  The insertion
1305    function just copies the BT field into the BA field, and the
1306    extraction function just checks that the fields are the same.  */
1307
1308 /*ARGSUSED*/
1309 static unsigned long
1310 insert_rbs (insn, value, dialect, errmsg)
1311      unsigned long insn;
1312      long value ATTRIBUTE_UNUSED;
1313      int dialect ATTRIBUTE_UNUSED;
1314      const char **errmsg ATTRIBUTE_UNUSED;
1315 {
1316   return insn | (((insn >> 21) & 0x1f) << 11);
1317 }
1318
1319 static long
1320 extract_rbs (insn, dialect, invalid)
1321      unsigned long insn;
1322      int dialect ATTRIBUTE_UNUSED;
1323      int *invalid;
1324 {
1325   if (invalid != (int *) NULL
1326       && ((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f))
1327     *invalid = 1;
1328   return 0;
1329 }
1330
1331 /* The SH field in an MD form instruction.  This is split.  */
1332
1333 /*ARGSUSED*/
1334 static unsigned long
1335 insert_sh6 (insn, value, dialect, errmsg)
1336      unsigned long insn;
1337      long value;
1338      int dialect ATTRIBUTE_UNUSED;
1339      const char **errmsg ATTRIBUTE_UNUSED;
1340 {
1341   return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
1342 }
1343
1344 /*ARGSUSED*/
1345 static long
1346 extract_sh6 (insn, dialect, invalid)
1347      unsigned long insn;
1348      int dialect ATTRIBUTE_UNUSED;
1349      int *invalid ATTRIBUTE_UNUSED;
1350 {
1351   return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
1352 }
1353
1354 /* The SPR field in an XFX form instruction.  This is flipped--the
1355    lower 5 bits are stored in the upper 5 and vice- versa.  */
1356
1357 static unsigned long
1358 insert_spr (insn, value, dialect, errmsg)
1359      unsigned long insn;
1360      long value;
1361      int dialect ATTRIBUTE_UNUSED;
1362      const char **errmsg ATTRIBUTE_UNUSED;
1363 {
1364   return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1365 }
1366
1367 static long
1368 extract_spr (insn, dialect, invalid)
1369      unsigned long insn;
1370      int dialect ATTRIBUTE_UNUSED;
1371      int *invalid ATTRIBUTE_UNUSED;
1372 {
1373   return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1374 }
1375
1376 /* The TBR field in an XFX instruction.  This is just like SPR, but it
1377    is optional.  When TBR is omitted, it must be inserted as 268 (the
1378    magic number of the TB register).  These functions treat 0
1379    (indicating an omitted optional operand) as 268.  This means that
1380    ``mftb 4,0'' is not handled correctly.  This does not matter very
1381    much, since the architecture manual does not define mftb as
1382    accepting any values other than 268 or 269.  */
1383
1384 #define TB (268)
1385
1386 static unsigned long
1387 insert_tbr (insn, value, dialect, errmsg)
1388      unsigned long insn;
1389      long value;
1390      int dialect ATTRIBUTE_UNUSED;
1391      const char **errmsg ATTRIBUTE_UNUSED;
1392 {
1393   if (value == 0)
1394     value = TB;
1395   return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1396 }
1397
1398 static long
1399 extract_tbr (insn, dialect, invalid)
1400      unsigned long insn;
1401      int dialect ATTRIBUTE_UNUSED;
1402      int *invalid ATTRIBUTE_UNUSED;
1403 {
1404   long ret;
1405
1406   ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1407   if (ret == TB)
1408     ret = 0;
1409   return ret;
1410 }
1411 \f
1412 /* Macros used to form opcodes.  */
1413
1414 /* The main opcode.  */
1415 #define OP(x) ((((unsigned long)(x)) & 0x3f) << 26)
1416 #define OP_MASK OP (0x3f)
1417
1418 /* The main opcode combined with a trap code in the TO field of a D
1419    form instruction.  Used for extended mnemonics for the trap
1420    instructions.  */
1421 #define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21))
1422 #define OPTO_MASK (OP_MASK | TO_MASK)
1423
1424 /* The main opcode combined with a comparison size bit in the L field
1425    of a D form or X form instruction.  Used for extended mnemonics for
1426    the comparison instructions.  */
1427 #define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21))
1428 #define OPL_MASK OPL (0x3f,1)
1429
1430 /* An A form instruction.  */
1431 #define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1))
1432 #define A_MASK A (0x3f, 0x1f, 1)
1433
1434 /* An A_MASK with the FRB field fixed.  */
1435 #define AFRB_MASK (A_MASK | FRB_MASK)
1436
1437 /* An A_MASK with the FRC field fixed.  */
1438 #define AFRC_MASK (A_MASK | FRC_MASK)
1439
1440 /* An A_MASK with the FRA and FRC fields fixed.  */
1441 #define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
1442
1443 /* A B form instruction.  */
1444 #define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1))
1445 #define B_MASK B (0x3f, 1, 1)
1446
1447 /* A B form instruction setting the BO field.  */
1448 #define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1449 #define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
1450
1451 /* A BBO_MASK with the y bit of the BO field removed.  This permits
1452    matching a conditional branch regardless of the setting of the y
1453    bit.  Similarly for the 'at' bits used for power4 branch hints.  */
1454 #define Y_MASK   (((unsigned long) 1) << 21)
1455 #define AT1_MASK (((unsigned long) 3) << 21)
1456 #define AT2_MASK (((unsigned long) 9) << 21)
1457 #define BBOY_MASK  (BBO_MASK &~ Y_MASK)
1458 #define BBOAT_MASK (BBO_MASK &~ AT1_MASK)
1459
1460 /* A B form instruction setting the BO field and the condition bits of
1461    the BI field.  */
1462 #define BBOCB(op, bo, cb, aa, lk) \
1463   (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16))
1464 #define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
1465
1466 /* A BBOCB_MASK with the y bit of the BO field removed.  */
1467 #define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
1468 #define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK)
1469 #define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK)
1470
1471 /* A BBOYCB_MASK in which the BI field is fixed.  */
1472 #define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
1473 #define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK)
1474
1475 /* An Context form instruction.  */
1476 #define CTX(op, xop)   (OP (op) | (((unsigned long)(xop)) & 0x7))
1477 #define CTX_MASK       CTX(0x3f, 0x7)
1478
1479 /* An User Context form instruction.  */
1480 #define UCTX(op, xop)  (OP (op) | (((unsigned long)(xop)) & 0x1f))
1481 #define UCTX_MASK      UCTX(0x3f, 0x1f)
1482
1483 /* The main opcode mask with the RA field clear.  */
1484 #define DRA_MASK (OP_MASK | RA_MASK)
1485
1486 /* A DS form instruction.  */
1487 #define DSO(op, xop) (OP (op) | ((xop) & 0x3))
1488 #define DS_MASK DSO (0x3f, 3)
1489
1490 /* A DE form instruction.  */
1491 #define DEO(op, xop) (OP (op) | ((xop) & 0xf))
1492 #define DE_MASK DEO (0x3e, 0xf)
1493
1494 /* An EVSEL form instruction.  */
1495 #define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3)
1496 #define EVSEL_MASK EVSEL(0x3f, 0xff)
1497
1498 /* An M form instruction.  */
1499 #define M(op, rc) (OP (op) | ((rc) & 1))
1500 #define M_MASK M (0x3f, 1)
1501
1502 /* An M form instruction with the ME field specified.  */
1503 #define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1))
1504
1505 /* An M_MASK with the MB and ME fields fixed.  */
1506 #define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
1507
1508 /* An M_MASK with the SH and ME fields fixed.  */
1509 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
1510
1511 /* An MD form instruction.  */
1512 #define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1))
1513 #define MD_MASK MD (0x3f, 0x7, 1)
1514
1515 /* An MD_MASK with the MB field fixed.  */
1516 #define MDMB_MASK (MD_MASK | MB6_MASK)
1517
1518 /* An MD_MASK with the SH field fixed.  */
1519 #define MDSH_MASK (MD_MASK | SH6_MASK)
1520
1521 /* An MDS form instruction.  */
1522 #define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1))
1523 #define MDS_MASK MDS (0x3f, 0xf, 1)
1524
1525 /* An MDS_MASK with the MB field fixed.  */
1526 #define MDSMB_MASK (MDS_MASK | MB6_MASK)
1527
1528 /* An SC form instruction.  */
1529 #define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
1530 #define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
1531
1532 /* An VX form instruction. */
1533 #define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
1534
1535 /* The mask for an VX form instruction. */
1536 #define VX_MASK VX(0x3f, 0x7ff)
1537
1538 /* An VA form instruction. */
1539 #define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
1540
1541 /* The mask for an VA form instruction. */
1542 #define VXA_MASK VXA(0x3f, 0x3f)
1543
1544 /* An VXR form instruction. */
1545 #define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
1546
1547 /* The mask for a VXR form instruction. */
1548 #define VXR_MASK VXR(0x3f, 0x3ff, 1)
1549
1550 /* An X form instruction.  */
1551 #define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1552
1553 /* An X form instruction with the RC bit specified.  */
1554 #define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
1555
1556 /* The mask for an X form instruction.  */
1557 #define X_MASK XRC (0x3f, 0x3ff, 1)
1558
1559 /* An X_MASK with the RA field fixed.  */
1560 #define XRA_MASK (X_MASK | RA_MASK)
1561
1562 /* An X_MASK with the RB field fixed.  */
1563 #define XRB_MASK (X_MASK | RB_MASK)
1564
1565 /* An X_MASK with the RT field fixed.  */
1566 #define XRT_MASK (X_MASK | RT_MASK)
1567
1568 /* An X_MASK with the RA and RB fields fixed.  */
1569 #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
1570
1571 /* An XRARB_MASK, but with the L bit clear. */
1572 #define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16))
1573
1574 /* An X_MASK with the RT and RA fields fixed.  */
1575 #define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
1576
1577 /* An XRTRA_MASK, but with L bit clear.  */
1578 #define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21))
1579
1580 /* An X form comparison instruction.  */
1581 #define XCMPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
1582
1583 /* The mask for an X form comparison instruction.  */
1584 #define XCMP_MASK (X_MASK | (((unsigned long)1) << 22))
1585
1586 /* The mask for an X form comparison instruction with the L field
1587    fixed.  */
1588 #define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21))
1589
1590 /* An X form trap instruction with the TO field specified.  */
1591 #define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21))
1592 #define XTO_MASK (X_MASK | TO_MASK)
1593
1594 /* An X form tlb instruction with the SH field specified.  */
1595 #define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11))
1596 #define XTLB_MASK (X_MASK | SH_MASK)
1597
1598 /* An X form sync instruction.  */
1599 #define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
1600
1601 /* An X form sync instruction with everything filled in except the LS field.  */
1602 #define XSYNC_MASK (0xff9fffff)
1603
1604 /* An X form AltiVec dss instruction.  */
1605 #define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25))
1606 #define XDSS_MASK XDSS(0x3f, 0x3ff, 1)
1607
1608 /* An XFL form instruction.  */
1609 #define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
1610 #define XFL_MASK (XFL (0x3f, 0x3ff, 1) | (((unsigned long)1) << 25) | (((unsigned long)1) << 16))
1611
1612 /* An X form isel instruction.  */
1613 #define XISEL(op, xop)  (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
1614 #define XISEL_MASK      XISEL(0x3f, 0x1f)
1615
1616 /* An XL form instruction with the LK field set to 0.  */
1617 #define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1618
1619 /* An XL form instruction which uses the LK field.  */
1620 #define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
1621
1622 /* The mask for an XL form instruction.  */
1623 #define XL_MASK XLLK (0x3f, 0x3ff, 1)
1624
1625 /* An XL form instruction which explicitly sets the BO field.  */
1626 #define XLO(op, bo, xop, lk) \
1627   (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1628 #define XLO_MASK (XL_MASK | BO_MASK)
1629
1630 /* An XL form instruction which explicitly sets the y bit of the BO
1631    field.  */
1632 #define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21))
1633 #define XLYLK_MASK (XL_MASK | Y_MASK)
1634
1635 /* An XL form instruction which sets the BO field and the condition
1636    bits of the BI field.  */
1637 #define XLOCB(op, bo, cb, xop, lk) \
1638   (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16))
1639 #define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
1640
1641 /* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed.  */
1642 #define XLBB_MASK (XL_MASK | BB_MASK)
1643 #define XLYBB_MASK (XLYLK_MASK | BB_MASK)
1644 #define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
1645
1646 /* An XL_MASK with the BO and BB fields fixed.  */
1647 #define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
1648
1649 /* An XL_MASK with the BO, BI and BB fields fixed.  */
1650 #define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
1651
1652 /* An XO form instruction.  */
1653 #define XO(op, xop, oe, rc) \
1654   (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1))
1655 #define XO_MASK XO (0x3f, 0x1ff, 1, 1)
1656
1657 /* An XO_MASK with the RB field fixed.  */
1658 #define XORB_MASK (XO_MASK | RB_MASK)
1659
1660 /* An XS form instruction.  */
1661 #define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1))
1662 #define XS_MASK XS (0x3f, 0x1ff, 1)
1663
1664 /* A mask for the FXM version of an XFX form instruction.  */
1665 #define XFXFXM_MASK (X_MASK | (((unsigned long)1) << 20) | (((unsigned long)1) << 11))
1666
1667 /* An XFX form instruction with the FXM field filled in.  */
1668 #define XFXM(op, xop, fxm) \
1669   (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12))
1670
1671 /* An XFX form instruction with the SPR field filled in.  */
1672 #define XSPR(op, xop, spr) \
1673   (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6))
1674 #define XSPR_MASK (X_MASK | SPR_MASK)
1675
1676 /* An XFX form instruction with the SPR field filled in except for the
1677    SPRBAT field.  */
1678 #define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
1679
1680 /* An XFX form instruction with the SPR field filled in except for the
1681    SPRG field.  */
1682 #define XSPRG_MASK (XSPR_MASK &~ SPRG_MASK)
1683
1684 /* An X form instruction with everything filled in except the E field.  */
1685 #define XE_MASK (0xffff7fff)
1686
1687 /* An X form user context instruction.  */
1688 #define XUC(op, xop)  (OP (op) | (((unsigned long)(xop)) & 0x1f))
1689 #define XUC_MASK      XUC(0x3f, 0x1f)
1690
1691 /* The BO encodings used in extended conditional branch mnemonics.  */
1692 #define BODNZF  (0x0)
1693 #define BODNZFP (0x1)
1694 #define BODZF   (0x2)
1695 #define BODZFP  (0x3)
1696 #define BODNZT  (0x8)
1697 #define BODNZTP (0x9)
1698 #define BODZT   (0xa)
1699 #define BODZTP  (0xb)
1700
1701 #define BOF     (0x4)
1702 #define BOFP    (0x5)
1703 #define BOFM4   (0x6)
1704 #define BOFP4   (0x7)
1705 #define BOT     (0xc)
1706 #define BOTP    (0xd)
1707 #define BOTM4   (0xe)
1708 #define BOTP4   (0xf)
1709
1710 #define BODNZ   (0x10)
1711 #define BODNZP  (0x11)
1712 #define BODZ    (0x12)
1713 #define BODZP   (0x13)
1714 #define BODNZM4 (0x18)
1715 #define BODNZP4 (0x19)
1716 #define BODZM4  (0x1a)
1717 #define BODZP4  (0x1b)
1718
1719 #define BOU     (0x14)
1720
1721 /* The BI condition bit encodings used in extended conditional branch
1722    mnemonics.  */
1723 #define CBLT    (0)
1724 #define CBGT    (1)
1725 #define CBEQ    (2)
1726 #define CBSO    (3)
1727
1728 /* The TO encodings used in extended trap mnemonics.  */
1729 #define TOLGT   (0x1)
1730 #define TOLLT   (0x2)
1731 #define TOEQ    (0x4)
1732 #define TOLGE   (0x5)
1733 #define TOLNL   (0x5)
1734 #define TOLLE   (0x6)
1735 #define TOLNG   (0x6)
1736 #define TOGT    (0x8)
1737 #define TOGE    (0xc)
1738 #define TONL    (0xc)
1739 #define TOLT    (0x10)
1740 #define TOLE    (0x14)
1741 #define TONG    (0x14)
1742 #define TONE    (0x18)
1743 #define TOU     (0x1f)
1744 \f
1745 /* Smaller names for the flags so each entry in the opcodes table will
1746    fit on a single line.  */
1747 #undef  PPC
1748 #define PPC     PPC_OPCODE_PPC | PPC_OPCODE_ANY
1749 #define PPCCOM  PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_ANY
1750 #define NOPOWER4 PPC_OPCODE_NOPOWER4 | PPCCOM
1751 #define POWER4  PPC_OPCODE_POWER4 | PPCCOM
1752 #define PPC32   PPC_OPCODE_32 | PPC_OPCODE_PPC | PPC_OPCODE_ANY
1753 #define PPC64   PPC_OPCODE_64 | PPC_OPCODE_PPC | PPC_OPCODE_ANY
1754 #define PPCONLY PPC_OPCODE_PPC
1755 #define PPC403  PPC_OPCODE_403
1756 #define PPC405  PPC403
1757 #define PPC750  PPC
1758 #define PPC860  PPC
1759 #define PPCVEC  PPC_OPCODE_ALTIVEC | PPC_OPCODE_ANY | PPC_OPCODE_PPC
1760 #define POWER   PPC_OPCODE_POWER | PPC_OPCODE_ANY
1761 #define POWER2  PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_ANY
1762 #define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_ANY
1763 #define POWER32 PPC_OPCODE_POWER | PPC_OPCODE_ANY | PPC_OPCODE_32
1764 #define COM     PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_ANY
1765 #define COM32   PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_ANY | PPC_OPCODE_32
1766 #define M601    PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_ANY
1767 #define PWRCOM  PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON | PPC_OPCODE_ANY
1768 #define MFDEC1  PPC_OPCODE_POWER
1769 #define MFDEC2  PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE
1770 #define BOOKE   PPC_OPCODE_BOOKE
1771 #define BOOKE64 PPC_OPCODE_BOOKE64
1772 #define CLASSIC PPC_OPCODE_CLASSIC
1773 #define PPCSPE  PPC_OPCODE_SPE
1774 #define PPCISEL PPC_OPCODE_ISEL
1775 #define PPCEFS  PPC_OPCODE_EFS
1776 #define PPCBRLK PPC_OPCODE_BRLOCK
1777 #define PPCPMR  PPC_OPCODE_PMR
1778 #define PPCCHLK PPC_OPCODE_CACHELCK
1779 #define PPCCHLK64       PPC_OPCODE_CACHELCK | PPC_OPCODE_BOOKE64
1780 #define PPCRFMCI        PPC_OPCODE_RFMCI
1781 \f
1782 /* The opcode table.
1783
1784    The format of the opcode table is:
1785
1786    NAME      OPCODE     MASK            FLAGS           { OPERANDS }
1787
1788    NAME is the name of the instruction.
1789    OPCODE is the instruction opcode.
1790    MASK is the opcode mask; this is used to tell the disassembler
1791      which bits in the actual opcode must match OPCODE.
1792    FLAGS are flags indicated what processors support the instruction.
1793    OPERANDS is the list of operands.
1794
1795    The disassembler reads the table in order and prints the first
1796    instruction which matches, so this table is sorted to put more
1797    specific instructions before more general instructions.  It is also
1798    sorted by major opcode.  */
1799
1800 const struct powerpc_opcode powerpc_opcodes[] = {
1801 { "tdlgti",  OPTO(2,TOLGT), OPTO_MASK,  PPC64,          { RA, SI } },
1802 { "tdllti",  OPTO(2,TOLLT), OPTO_MASK,  PPC64,          { RA, SI } },
1803 { "tdeqi",   OPTO(2,TOEQ), OPTO_MASK,   PPC64,          { RA, SI } },
1804 { "tdlgei",  OPTO(2,TOLGE), OPTO_MASK,  PPC64,          { RA, SI } },
1805 { "tdlnli",  OPTO(2,TOLNL), OPTO_MASK,  PPC64,          { RA, SI } },
1806 { "tdllei",  OPTO(2,TOLLE), OPTO_MASK,  PPC64,          { RA, SI } },
1807 { "tdlngi",  OPTO(2,TOLNG), OPTO_MASK,  PPC64,          { RA, SI } },
1808 { "tdgti",   OPTO(2,TOGT), OPTO_MASK,   PPC64,          { RA, SI } },
1809 { "tdgei",   OPTO(2,TOGE), OPTO_MASK,   PPC64,          { RA, SI } },
1810 { "tdnli",   OPTO(2,TONL), OPTO_MASK,   PPC64,          { RA, SI } },
1811 { "tdlti",   OPTO(2,TOLT), OPTO_MASK,   PPC64,          { RA, SI } },
1812 { "tdlei",   OPTO(2,TOLE), OPTO_MASK,   PPC64,          { RA, SI } },
1813 { "tdngi",   OPTO(2,TONG), OPTO_MASK,   PPC64,          { RA, SI } },
1814 { "tdnei",   OPTO(2,TONE), OPTO_MASK,   PPC64,          { RA, SI } },
1815 { "tdi",     OP(2),     OP_MASK,        PPC64,          { TO, RA, SI } },
1816
1817 { "twlgti",  OPTO(3,TOLGT), OPTO_MASK,  PPCCOM,         { RA, SI } },
1818 { "tlgti",   OPTO(3,TOLGT), OPTO_MASK,  PWRCOM,         { RA, SI } },
1819 { "twllti",  OPTO(3,TOLLT), OPTO_MASK,  PPCCOM,         { RA, SI } },
1820 { "tllti",   OPTO(3,TOLLT), OPTO_MASK,  PWRCOM,         { RA, SI } },
1821 { "tweqi",   OPTO(3,TOEQ), OPTO_MASK,   PPCCOM,         { RA, SI } },
1822 { "teqi",    OPTO(3,TOEQ), OPTO_MASK,   PWRCOM,         { RA, SI } },
1823 { "twlgei",  OPTO(3,TOLGE), OPTO_MASK,  PPCCOM,         { RA, SI } },
1824 { "tlgei",   OPTO(3,TOLGE), OPTO_MASK,  PWRCOM,         { RA, SI } },
1825 { "twlnli",  OPTO(3,TOLNL), OPTO_MASK,  PPCCOM,         { RA, SI } },
1826 { "tlnli",   OPTO(3,TOLNL), OPTO_MASK,  PWRCOM,         { RA, SI } },
1827 { "twllei",  OPTO(3,TOLLE), OPTO_MASK,  PPCCOM,         { RA, SI } },
1828 { "tllei",   OPTO(3,TOLLE), OPTO_MASK,  PWRCOM,         { RA, SI } },
1829 { "twlngi",  OPTO(3,TOLNG), OPTO_MASK,  PPCCOM,         { RA, SI } },
1830 { "tlngi",   OPTO(3,TOLNG), OPTO_MASK,  PWRCOM,         { RA, SI } },
1831 { "twgti",   OPTO(3,TOGT), OPTO_MASK,   PPCCOM,         { RA, SI } },
1832 { "tgti",    OPTO(3,TOGT), OPTO_MASK,   PWRCOM,         { RA, SI } },
1833 { "twgei",   OPTO(3,TOGE), OPTO_MASK,   PPCCOM,         { RA, SI } },
1834 { "tgei",    OPTO(3,TOGE), OPTO_MASK,   PWRCOM,         { RA, SI } },
1835 { "twnli",   OPTO(3,TONL), OPTO_MASK,   PPCCOM,         { RA, SI } },
1836 { "tnli",    OPTO(3,TONL), OPTO_MASK,   PWRCOM,         { RA, SI } },
1837 { "twlti",   OPTO(3,TOLT), OPTO_MASK,   PPCCOM,         { RA, SI } },
1838 { "tlti",    OPTO(3,TOLT), OPTO_MASK,   PWRCOM,         { RA, SI } },
1839 { "twlei",   OPTO(3,TOLE), OPTO_MASK,   PPCCOM,         { RA, SI } },
1840 { "tlei",    OPTO(3,TOLE), OPTO_MASK,   PWRCOM,         { RA, SI } },
1841 { "twngi",   OPTO(3,TONG), OPTO_MASK,   PPCCOM,         { RA, SI } },
1842 { "tngi",    OPTO(3,TONG), OPTO_MASK,   PWRCOM,         { RA, SI } },
1843 { "twnei",   OPTO(3,TONE), OPTO_MASK,   PPCCOM,         { RA, SI } },
1844 { "tnei",    OPTO(3,TONE), OPTO_MASK,   PWRCOM,         { RA, SI } },
1845 { "twi",     OP(3),     OP_MASK,        PPCCOM,         { TO, RA, SI } },
1846 { "ti",      OP(3),     OP_MASK,        PWRCOM,         { TO, RA, SI } },
1847
1848 { "macchw",     XO(4,172,0,0), XO_MASK, PPC405,         { RT, RA, RB } },
1849 { "macchw.",    XO(4,172,0,1), XO_MASK, PPC405,         { RT, RA, RB } },
1850 { "macchwo",    XO(4,172,1,0), XO_MASK, PPC405,         { RT, RA, RB } },
1851 { "macchwo.",   XO(4,172,1,1), XO_MASK, PPC405,         { RT, RA, RB } },
1852 { "macchws",    XO(4,236,0,0), XO_MASK, PPC405,         { RT, RA, RB } },
1853 { "macchws.",   XO(4,236,0,1), XO_MASK, PPC405,         { RT, RA, RB } },
1854 { "macchwso",   XO(4,236,1,0), XO_MASK, PPC405,         { RT, RA, RB } },
1855 { "macchwso.",  XO(4,236,1,1), XO_MASK, PPC405,         { RT, RA, RB } },
1856 { "macchwsu",   XO(4,204,0,0), XO_MASK, PPC405,         { RT, RA, RB } },
1857 { "macchwsu.",  XO(4,204,0,1), XO_MASK, PPC405,         { RT, RA, RB } },
1858 { "macchwsuo",  XO(4,204,1,0), XO_MASK, PPC405,         { RT, RA, RB } },
1859 { "macchwsuo.", XO(4,204,1,1), XO_MASK, PPC405,         { RT, RA, RB } },
1860 { "macchwu",    XO(4,140,0,0), XO_MASK, PPC405,         { RT, RA, RB } },
1861 { "macchwu.",   XO(4,140,0,1), XO_MASK, PPC405,         { RT, RA, RB } },
1862 { "macchwuo",   XO(4,140,1,0), XO_MASK, PPC405,         { RT, RA, RB } },
1863 { "macchwuo.",  XO(4,140,1,1), XO_MASK, PPC405,         { RT, RA, RB } },
1864 { "machhw",     XO(4,44,0,0),  XO_MASK, PPC405,         { RT, RA, RB } },
1865 { "machhw.",    XO(4,44,0,1),  XO_MASK, PPC405,         { RT, RA, RB } },
1866 { "machhwo",    XO(4,44,1,0),  XO_MASK, PPC405,         { RT, RA, RB } },
1867 { "machhwo.",   XO(4,44,1,1),  XO_MASK, PPC405,         { RT, RA, RB } },
1868 { "machhws",    XO(4,108,0,0), XO_MASK, PPC405,         { RT, RA, RB } },
1869 { "machhws.",   XO(4,108,0,1), XO_MASK, PPC405,         { RT, RA, RB } },
1870 { "machhwso",   XO(4,108,1,0), XO_MASK, PPC405,         { RT, RA, RB } },
1871 { "machhwso.",  XO(4,108,1,1), XO_MASK, PPC405,         { RT, RA, RB } },
1872 { "machhwsu",   XO(4,76,0,0),  XO_MASK, PPC405,         { RT, RA, RB } },
1873 { "machhwsu.",  XO(4,76,0,1),  XO_MASK, PPC405,         { RT, RA, RB } },
1874 { "machhwsuo",  XO(4,76,1,0),  XO_MASK, PPC405,         { RT, RA, RB } },
1875 { "machhwsuo.", XO(4,76,1,1),  XO_MASK, PPC405,         { RT, RA, RB } },
1876 { "machhwu",    XO(4,12,0,0),  XO_MASK, PPC405,         { RT, RA, RB } },
1877 { "machhwu.",   XO(4,12,0,1),  XO_MASK, PPC405,         { RT, RA, RB } },
1878 { "machhwuo",   XO(4,12,1,0),  XO_MASK, PPC405,         { RT, RA, RB } },
1879 { "machhwuo.",  XO(4,12,1,1),  XO_MASK, PPC405,         { RT, RA, RB } },
1880 { "maclhw",     XO(4,428,0,0), XO_MASK, PPC405,         { RT, RA, RB } },
1881 { "maclhw.",    XO(4,428,0,1), XO_MASK, PPC405,         { RT, RA, RB } },
1882 { "maclhwo",    XO(4,428,1,0), XO_MASK, PPC405,         { RT, RA, RB } },
1883 { "maclhwo.",   XO(4,428,1,1), XO_MASK, PPC405,         { RT, RA, RB } },
1884 { "maclhws",    XO(4,492,0,0), XO_MASK, PPC405,         { RT, RA, RB } },
1885 { "maclhws.",   XO(4,492,0,1), XO_MASK, PPC405,         { RT, RA, RB } },
1886 { "maclhwso",   XO(4,492,1,0), XO_MASK, PPC405,         { RT, RA, RB } },
1887 { "maclhwso.",  XO(4,492,1,1), XO_MASK, PPC405,         { RT, RA, RB } },
1888 { "maclhwsu",   XO(4,460,0,0), XO_MASK, PPC405,         { RT, RA, RB } },
1889 { "maclhwsu.",  XO(4,460,0,1), XO_MASK, PPC405,         { RT, RA, RB } },
1890 { "maclhwsuo",  XO(4,460,1,0), XO_MASK, PPC405,         { RT, RA, RB } },
1891 { "maclhwsuo.", XO(4,460,1,1), XO_MASK, PPC405,         { RT, RA, RB } },
1892 { "maclhwu",    XO(4,396,0,0), XO_MASK, PPC405,         { RT, RA, RB } },
1893 { "maclhwu.",   XO(4,396,0,1), XO_MASK, PPC405,         { RT, RA, RB } },
1894 { "maclhwuo",   XO(4,396,1,0), XO_MASK, PPC405,         { RT, RA, RB } },
1895 { "maclhwuo.",  XO(4,396,1,1), XO_MASK, PPC405,         { RT, RA, RB } },
1896 { "mulchw",     XRC(4,168,0),  X_MASK,  PPC405,         { RT, RA, RB } },
1897 { "mulchw.",    XRC(4,168,1),  X_MASK,  PPC405,         { RT, RA, RB } },
1898 { "mulchwu",    XRC(4,136,0),  X_MASK,  PPC405,         { RT, RA, RB } },
1899 { "mulchwu.",   XRC(4,136,1),  X_MASK,  PPC405,         { RT, RA, RB } },
1900 { "mulhhw",     XRC(4,40,0),   X_MASK,  PPC405,         { RT, RA, RB } },
1901 { "mulhhw.",    XRC(4,40,1),   X_MASK,  PPC405,         { RT, RA, RB } },
1902 { "mulhhwu",    XRC(4,8,0),    X_MASK,  PPC405,         { RT, RA, RB } },
1903 { "mulhhwu.",   XRC(4,8,1),    X_MASK,  PPC405,         { RT, RA, RB } },
1904 { "mullhw",     XRC(4,424,0),  X_MASK,  PPC405,         { RT, RA, RB } },
1905 { "mullhw.",    XRC(4,424,1),  X_MASK,  PPC405,         { RT, RA, RB } },
1906 { "mullhwu",    XRC(4,392,0),  X_MASK,  PPC405,         { RT, RA, RB } },
1907 { "mullhwu.",   XRC(4,392,1),  X_MASK,  PPC405,         { RT, RA, RB } },
1908 { "nmacchw",    XO(4,174,0,0), XO_MASK, PPC405,         { RT, RA, RB } },
1909 { "nmacchw.",   XO(4,174,0,1), XO_MASK, PPC405,         { RT, RA, RB } },
1910 { "nmacchwo",   XO(4,174,1,0), XO_MASK, PPC405,         { RT, RA, RB } },
1911 { "nmacchwo.",  XO(4,174,1,1), XO_MASK, PPC405,         { RT, RA, RB } },
1912 { "nmacchws",   XO(4,238,0,0), XO_MASK, PPC405,         { RT, RA, RB } },
1913 { "nmacchws.",  XO(4,238,0,1), XO_MASK, PPC405,         { RT, RA, RB } },
1914 { "nmacchwso",  XO(4,238,1,0), XO_MASK, PPC405,         { RT, RA, RB } },
1915 { "nmacchwso.", XO(4,238,1,1), XO_MASK, PPC405,         { RT, RA, RB } },
1916 { "nmachhw",    XO(4,46,0,0),  XO_MASK, PPC405,         { RT, RA, RB } },
1917 { "nmachhw.",   XO(4,46,0,1),  XO_MASK, PPC405,         { RT, RA, RB } },
1918 { "nmachhwo",   XO(4,46,1,0),  XO_MASK, PPC405,         { RT, RA, RB } },
1919 { "nmachhwo.",  XO(4,46,1,1),  XO_MASK, PPC405,         { RT, RA, RB } },
1920 { "nmachhws",   XO(4,110,0,0), XO_MASK, PPC405,         { RT, RA, RB } },
1921 { "nmachhws.",  XO(4,110,0,1), XO_MASK, PPC405,         { RT, RA, RB } },
1922 { "nmachhwso",  XO(4,110,1,0), XO_MASK, PPC405,         { RT, RA, RB } },
1923 { "nmachhwso.", XO(4,110,1,1), XO_MASK, PPC405,         { RT, RA, RB } },
1924 { "nmaclhw",    XO(4,430,0,0), XO_MASK, PPC405,         { RT, RA, RB } },
1925 { "nmaclhw.",   XO(4,430,0,1), XO_MASK, PPC405,         { RT, RA, RB } },
1926 { "nmaclhwo",   XO(4,430,1,0), XO_MASK, PPC405,         { RT, RA, RB } },
1927 { "nmaclhwo.",  XO(4,430,1,1), XO_MASK, PPC405,         { RT, RA, RB } },
1928 { "nmaclhws",   XO(4,494,0,0), XO_MASK, PPC405,         { RT, RA, RB } },
1929 { "nmaclhws.",  XO(4,494,0,1), XO_MASK, PPC405,         { RT, RA, RB } },
1930 { "nmaclhwso",  XO(4,494,1,0), XO_MASK, PPC405,         { RT, RA, RB } },
1931 { "nmaclhwso.", XO(4,494,1,1), XO_MASK, PPC405,         { RT, RA, RB } },
1932 { "mfvscr",  VX(4, 1540), VX_MASK,      PPCVEC,         { VD } },
1933 { "mtvscr",  VX(4, 1604), VX_MASK,      PPCVEC,         { VB } },
1934 { "vaddcuw", VX(4,  384), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1935 { "vaddfp",  VX(4,   10), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1936 { "vaddsbs", VX(4,  768), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1937 { "vaddshs", VX(4,  832), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1938 { "vaddsws", VX(4,  896), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1939 { "vaddubm", VX(4,    0), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1940 { "vaddubs", VX(4,  512), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1941 { "vadduhm", VX(4,   64), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1942 { "vadduhs", VX(4,  576), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1943 { "vadduwm", VX(4,  128), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1944 { "vadduws", VX(4,  640), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1945 { "vand",    VX(4, 1028), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1946 { "vandc",   VX(4, 1092), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1947 { "vavgsb",  VX(4, 1282), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1948 { "vavgsh",  VX(4, 1346), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1949 { "vavgsw",  VX(4, 1410), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1950 { "vavgub",  VX(4, 1026), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1951 { "vavguh",  VX(4, 1090), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1952 { "vavguw",  VX(4, 1154), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1953 { "vcfsx",   VX(4,  842), VX_MASK,      PPCVEC,         { VD, VB, UIMM } },
1954 { "vcfux",   VX(4,  778), VX_MASK,      PPCVEC,         { VD, VB, UIMM } },
1955 { "vcmpbfp",   VXR(4, 966, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1956 { "vcmpbfp.",  VXR(4, 966, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1957 { "vcmpeqfp",  VXR(4, 198, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1958 { "vcmpeqfp.", VXR(4, 198, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1959 { "vcmpequb",  VXR(4,   6, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1960 { "vcmpequb.", VXR(4,   6, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1961 { "vcmpequh",  VXR(4,  70, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1962 { "vcmpequh.", VXR(4,  70, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1963 { "vcmpequw",  VXR(4, 134, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1964 { "vcmpequw.", VXR(4, 134, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1965 { "vcmpgefp",  VXR(4, 454, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1966 { "vcmpgefp.", VXR(4, 454, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1967 { "vcmpgtfp",  VXR(4, 710, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1968 { "vcmpgtfp.", VXR(4, 710, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1969 { "vcmpgtsb",  VXR(4, 774, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1970 { "vcmpgtsb.", VXR(4, 774, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1971 { "vcmpgtsh",  VXR(4, 838, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1972 { "vcmpgtsh.", VXR(4, 838, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1973 { "vcmpgtsw",  VXR(4, 902, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1974 { "vcmpgtsw.", VXR(4, 902, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1975 { "vcmpgtub",  VXR(4, 518, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1976 { "vcmpgtub.", VXR(4, 518, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1977 { "vcmpgtuh",  VXR(4, 582, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1978 { "vcmpgtuh.", VXR(4, 582, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1979 { "vcmpgtuw",  VXR(4, 646, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1980 { "vcmpgtuw.", VXR(4, 646, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1981 { "vctsxs",    VX(4,  970), VX_MASK,    PPCVEC,         { VD, VB, UIMM } },
1982 { "vctuxs",    VX(4,  906), VX_MASK,    PPCVEC,         { VD, VB, UIMM } },
1983 { "vexptefp",  VX(4,  394), VX_MASK,    PPCVEC,         { VD, VB } },
1984 { "vlogefp",   VX(4,  458), VX_MASK,    PPCVEC,         { VD, VB } },
1985 { "vmaddfp",   VXA(4,  46), VXA_MASK,   PPCVEC,         { VD, VA, VC, VB } },
1986 { "vmaxfp",    VX(4, 1034), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1987 { "vmaxsb",    VX(4,  258), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1988 { "vmaxsh",    VX(4,  322), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1989 { "vmaxsw",    VX(4,  386), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1990 { "vmaxub",    VX(4,    2), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1991 { "vmaxuh",    VX(4,   66), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1992 { "vmaxuw",    VX(4,  130), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1993 { "vmhaddshs", VXA(4,  32), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
1994 { "vmhraddshs", VXA(4, 33), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
1995 { "vminfp",    VX(4, 1098), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1996 { "vminsb",    VX(4,  770), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1997 { "vminsh",    VX(4,  834), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1998 { "vminsw",    VX(4,  898), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1999 { "vminub",    VX(4,  514), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2000 { "vminuh",    VX(4,  578), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2001 { "vminuw",    VX(4,  642), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2002 { "vmladduhm", VXA(4,  34), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
2003 { "vmrghb",    VX(4,   12), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2004 { "vmrghh",    VX(4,   76), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2005 { "vmrghw",    VX(4,  140), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2006 { "vmrglb",    VX(4,  268), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2007 { "vmrglh",    VX(4,  332), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2008 { "vmrglw",    VX(4,  396), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2009 { "vmsummbm",  VXA(4,  37), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
2010 { "vmsumshm",  VXA(4,  40), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
2011 { "vmsumshs",  VXA(4,  41), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
2012 { "vmsumubm",  VXA(4,  36), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
2013 { "vmsumuhm",  VXA(4,  38), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
2014 { "vmsumuhs",  VXA(4,  39), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
2015 { "vmulesb",   VX(4,  776), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2016 { "vmulesh",   VX(4,  840), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2017 { "vmuleub",   VX(4,  520), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2018 { "vmuleuh",   VX(4,  584), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2019 { "vmulosb",   VX(4,  264), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2020 { "vmulosh",   VX(4,  328), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2021 { "vmuloub",   VX(4,    8), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2022 { "vmulouh",   VX(4,   72), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2023 { "vnmsubfp",  VXA(4,  47), VXA_MASK,   PPCVEC,         { VD, VA, VC, VB } },
2024 { "vnor",      VX(4, 1284), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2025 { "vor",       VX(4, 1156), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2026 { "vperm",     VXA(4,  43), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
2027 { "vpkpx",     VX(4,  782), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2028 { "vpkshss",   VX(4,  398), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2029 { "vpkshus",   VX(4,  270), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2030 { "vpkswss",   VX(4,  462), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2031 { "vpkswus",   VX(4,  334), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2032 { "vpkuhum",   VX(4,   14), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2033 { "vpkuhus",   VX(4,  142), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2034 { "vpkuwum",   VX(4,   78), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2035 { "vpkuwus",   VX(4,  206), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2036 { "vrefp",     VX(4,  266), VX_MASK,    PPCVEC,         { VD, VB } },
2037 { "vrfim",     VX(4,  714), VX_MASK,    PPCVEC,         { VD, VB } },
2038 { "vrfin",     VX(4,  522), VX_MASK,    PPCVEC,         { VD, VB } },
2039 { "vrfip",     VX(4,  650), VX_MASK,    PPCVEC,         { VD, VB } },
2040 { "vrfiz",     VX(4,  586), VX_MASK,    PPCVEC,         { VD, VB } },
2041 { "vrlb",      VX(4,    4), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2042 { "vrlh",      VX(4,   68), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2043 { "vrlw",      VX(4,  132), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2044 { "vrsqrtefp", VX(4,  330), VX_MASK,    PPCVEC,         { VD, VB } },
2045 { "vsel",      VXA(4,  42), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
2046 { "vsl",       VX(4,  452), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2047 { "vslb",      VX(4,  260), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2048 { "vsldoi",    VXA(4,  44), VXA_MASK,   PPCVEC,         { VD, VA, VB, SHB } },
2049 { "vslh",      VX(4,  324), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2050 { "vslo",      VX(4, 1036), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2051 { "vslw",      VX(4,  388), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2052 { "vspltb",    VX(4,  524), VX_MASK,    PPCVEC,         { VD, VB, UIMM } },
2053 { "vsplth",    VX(4,  588), VX_MASK,    PPCVEC,         { VD, VB, UIMM } },
2054 { "vspltisb",  VX(4,  780), VX_MASK,    PPCVEC,         { VD, SIMM } },
2055 { "vspltish",  VX(4,  844), VX_MASK,    PPCVEC,         { VD, SIMM } },
2056 { "vspltisw",  VX(4,  908), VX_MASK,    PPCVEC,         { VD, SIMM } },
2057 { "vspltw",    VX(4,  652), VX_MASK,    PPCVEC,         { VD, VB, UIMM } },
2058 { "vsr",       VX(4,  708), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2059 { "vsrab",     VX(4,  772), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2060 { "vsrah",     VX(4,  836), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2061 { "vsraw",     VX(4,  900), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2062 { "vsrb",      VX(4,  516), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2063 { "vsrh",      VX(4,  580), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2064 { "vsro",      VX(4, 1100), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2065 { "vsrw",      VX(4,  644), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2066 { "vsubcuw",   VX(4, 1408), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2067 { "vsubfp",    VX(4,   74), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2068 { "vsubsbs",   VX(4, 1792), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2069 { "vsubshs",   VX(4, 1856), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2070 { "vsubsws",   VX(4, 1920), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2071 { "vsububm",   VX(4, 1024), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2072 { "vsububs",   VX(4, 1536), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2073 { "vsubuhm",   VX(4, 1088), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2074 { "vsubuhs",   VX(4, 1600), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2075 { "vsubuwm",   VX(4, 1152), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2076 { "vsubuws",   VX(4, 1664), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2077 { "vsumsws",   VX(4, 1928), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2078 { "vsum2sws",  VX(4, 1672), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2079 { "vsum4sbs",  VX(4, 1800), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2080 { "vsum4shs",  VX(4, 1608), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2081 { "vsum4ubs",  VX(4, 1544), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2082 { "vupkhpx",   VX(4,  846), VX_MASK,    PPCVEC,         { VD, VB } },
2083 { "vupkhsb",   VX(4,  526), VX_MASK,    PPCVEC,         { VD, VB } },
2084 { "vupkhsh",   VX(4,  590), VX_MASK,    PPCVEC,         { VD, VB } },
2085 { "vupklpx",   VX(4,  974), VX_MASK,    PPCVEC,         { VD, VB } },
2086 { "vupklsb",   VX(4,  654), VX_MASK,    PPCVEC,         { VD, VB } },
2087 { "vupklsh",   VX(4,  718), VX_MASK,    PPCVEC,         { VD, VB } },
2088 { "vxor",      VX(4, 1220), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2089
2090 { "evaddw",    VX(4, 512), VX_MASK,     PPCSPE,         { RD, RA, RB } },
2091 { "evaddiw",   VX(4, 514), VX_MASK,     PPCSPE,         { RD, RB, UIMM } },
2092 { "evsubfw",   VX(4, 516), VX_MASK,     PPCSPE,         { RD, RA, RB } },
2093 { "evsubw",    VX(4, 516), VX_MASK,     PPCSPE,         { RD, RB, RA } },
2094 { "evsubifw",  VX(4, 518), VX_MASK,     PPCSPE,         { RD, UIMM, RB } },
2095 { "evsubiw",   VX(4, 518), VX_MASK,     PPCSPE,         { RD, RB, UIMM } },
2096 { "evabs",     VX(4, 520), VX_MASK,     PPCSPE,         { RD, RA } },
2097 { "evneg",     VX(4, 521), VX_MASK,     PPCSPE,         { RD, RA } },
2098 { "evextsb",   VX(4, 522), VX_MASK,     PPCSPE,         { RD, RA } },
2099 { "evextsh",   VX(4, 523), VX_MASK,     PPCSPE,         { RD, RA } },
2100 { "evrndw",    VX(4, 524), VX_MASK,     PPCSPE,         { RD, RA } },
2101 { "evcntlzw",  VX(4, 525), VX_MASK,     PPCSPE,         { RD, RA } },
2102 { "evcntlsw",  VX(4, 526), VX_MASK,     PPCSPE,         { RD, RA } },
2103
2104 { "brinc",     VX(4, 527), VX_MASK,     PPCSPE,         { RD, RA, RB } },
2105
2106 { "evand",     VX(4, 529), VX_MASK,     PPCSPE,         { RD, RA, RB } },
2107 { "evandc",    VX(4, 530), VX_MASK,     PPCSPE,         { RD, RA, RB } },
2108 { "evmr",      VX(4, 535), VX_MASK,     PPCSPE,         { RS, RA, BBA } },
2109 { "evor",      VX(4, 535), VX_MASK,     PPCSPE,         { RD, RA, RB } },
2110 { "evorc",     VX(4, 539), VX_MASK,     PPCSPE,         { RD, RA, RB } },
2111 { "evxor",     VX(4, 534), VX_MASK,     PPCSPE,         { RD, RA, RB } },
2112 { "eveqv",     VX(4, 537), VX_MASK,     PPCSPE,         { RD, RA, RB } },
2113 { "evnand",    VX(4, 542), VX_MASK,     PPCSPE,         { RD, RA, RB } },
2114 { "evnot",     VX(4, 536), VX_MASK,     PPCSPE,         { RS, RA, BBA } },
2115 { "evnor",     VX(4, 536), VX_MASK,     PPCSPE,         { RD, RA, RB } },
2116
2117 { "evrlw",     VX(4, 552), VX_MASK,     PPCSPE,         { RD, RA, RB } },
2118 { "evrlwi",    VX(4, 554), VX_MASK,     PPCSPE,         { RD, RA, EVUIMM } },
2119 { "evslw",     VX(4, 548), VX_MASK,     PPCSPE,         { RD, RA, RB } },
2120 { "evslwi",    VX(4, 550), VX_MASK,     PPCSPE,         { RD, RA, EVUIMM } },
2121 { "evsrws",    VX(4, 545), VX_MASK,     PPCSPE,         { RD, RA, RB } },
2122 { "evsrwu",    VX(4, 544), VX_MASK,     PPCSPE,         { RD, RA, RB } },
2123 { "evsrwis",   VX(4, 547), VX_MASK,     PPCSPE,         { RD, RA, EVUIMM } },
2124 { "evsrwiu",   VX(4, 546), VX_MASK,     PPCSPE,         { RD, RA, EVUIMM } },
2125 { "evsplati",  VX(4, 553), VX_MASK,     PPCSPE,         { RD, SIMM } },
2126 { "evsplatfi", VX(4, 555), VX_MASK,     PPCSPE,         { RD, SIMM } },
2127 { "evmergehi", VX(4, 556), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2128 { "evmergelo", VX(4, 557), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2129 { "evmergehilo",VX(4,558), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2130 { "evmergelohi",VX(4,559), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2131
2132 { "evcmpgts",  VX(4, 561), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
2133 { "evcmpgtu",  VX(4, 560), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
2134 { "evcmplts",  VX(4, 563), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
2135 { "evcmpltu",  VX(4, 562), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
2136 { "evcmpeq",   VX(4, 564), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
2137 { "evsel",     EVSEL(4,79),EVSEL_MASK,  PPCSPE,         { RD, RA, RB, CRFS } },
2138
2139 { "evldd",     VX(4, 769), VX_MASK,     PPCSPE,         { RS, EVUIMM_8, RA } },
2140 { "evlddx",    VX(4, 768), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2141 { "evldw",     VX(4, 771), VX_MASK,     PPCSPE,         { RS, EVUIMM_8, RA } },
2142 { "evldwx",    VX(4, 770), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2143 { "evldh",     VX(4, 773), VX_MASK,     PPCSPE,         { RS, EVUIMM_8, RA } },
2144 { "evldhx",    VX(4, 772), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2145 { "evlwhe",    VX(4, 785), VX_MASK,     PPCSPE,         { RS, EVUIMM_4, RA } },
2146 { "evlwhex",   VX(4, 784), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2147 { "evlwhou",   VX(4, 789), VX_MASK,     PPCSPE,         { RS, EVUIMM_4, RA } },
2148 { "evlwhoux",  VX(4, 788), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2149 { "evlwhos",   VX(4, 791), VX_MASK,     PPCSPE,         { RS, EVUIMM_4, RA } },
2150 { "evlwhosx",  VX(4, 790), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2151 { "evlwwsplat",VX(4, 793), VX_MASK,     PPCSPE,         { RS, EVUIMM_4, RA } },
2152 { "evlwwsplatx",VX(4, 792), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2153 { "evlwhsplat",VX(4, 797), VX_MASK,     PPCSPE,         { RS, EVUIMM_4, RA } },
2154 { "evlwhsplatx",VX(4, 796), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2155 { "evlhhesplat",VX(4, 777), VX_MASK,    PPCSPE,         { RS, EVUIMM_2, RA } },
2156 { "evlhhesplatx",VX(4, 776), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2157 { "evlhhousplat",VX(4, 781), VX_MASK,   PPCSPE,         { RS, EVUIMM_2, RA } },
2158 { "evlhhousplatx",VX(4, 780), VX_MASK,  PPCSPE,         { RS, RA, RB } },
2159 { "evlhhossplat",VX(4, 783), VX_MASK,   PPCSPE,         { RS, EVUIMM_2, RA } },
2160 { "evlhhossplatx",VX(4, 782), VX_MASK,  PPCSPE,         { RS, RA, RB } },
2161
2162 { "evstdd",    VX(4, 801), VX_MASK,     PPCSPE,         { RS, EVUIMM_8, RA } },
2163 { "evstddx",   VX(4, 800), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2164 { "evstdw",    VX(4, 803), VX_MASK,     PPCSPE,         { RS, EVUIMM_8, RA } },
2165 { "evstdwx",   VX(4, 802), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2166 { "evstdh",    VX(4, 805), VX_MASK,     PPCSPE,         { RS, EVUIMM_8, RA } },
2167 { "evstdhx",   VX(4, 804), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2168 { "evstwwe",   VX(4, 825), VX_MASK,     PPCSPE,         { RS, EVUIMM_4, RA } },
2169 { "evstwwex",  VX(4, 824), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2170 { "evstwwo",   VX(4, 829), VX_MASK,     PPCSPE,         { RS, EVUIMM_4, RA } },
2171 { "evstwwox",  VX(4, 828), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2172 { "evstwhe",   VX(4, 817), VX_MASK,     PPCSPE,         { RS, EVUIMM_4, RA } },
2173 { "evstwhex",  VX(4, 816), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2174 { "evstwho",   VX(4, 821), VX_MASK,     PPCSPE,         { RS, EVUIMM_4, RA } },
2175 { "evstwhox",  VX(4, 820), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2176
2177 { "evfsabs",   VX(4, 644), VX_MASK,     PPCSPE,         { RD, RA } },
2178 { "evfsnabs",  VX(4, 645), VX_MASK,     PPCSPE,         { RD, RA } },
2179 { "evfsneg",   VX(4, 646), VX_MASK,     PPCSPE,         { RD, RA } },
2180 { "evfsadd",   VX(4, 640), VX_MASK,     PPCSPE,         { RD, RA, RB } },
2181 { "evfssub",   VX(4, 641), VX_MASK,     PPCSPE,         { RD, RA, RB } },
2182 { "evfsmul",   VX(4, 648), VX_MASK,     PPCSPE,         { RD, RA, RB } },
2183 { "evfsdiv",   VX(4, 649), VX_MASK,     PPCSPE,         { RD, RA, RB } },
2184 { "evfscmpgt", VX(4, 652), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
2185 { "evfscmplt", VX(4, 653), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
2186 { "evfscmpeq", VX(4, 654), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
2187 { "evfststgt", VX(4, 668), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
2188 { "evfststlt", VX(4, 669), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
2189 { "evfststeq", VX(4, 670), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
2190 { "evfscfui",  VX(4, 656), VX_MASK,     PPCSPE,         { RD, RB } },
2191 { "evfsctuiz", VX(4, 664), VX_MASK,     PPCSPE,         { RD, RB } },
2192 { "evfscfsi",  VX(4, 657), VX_MASK,     PPCSPE,         { RD, RB } },
2193 { "evfscfuf",  VX(4, 658), VX_MASK,     PPCSPE,         { RD, RB } },
2194 { "evfscfsf",  VX(4, 659), VX_MASK,     PPCSPE,         { RD, RB } },
2195 { "evfsctui",  VX(4, 660), VX_MASK,     PPCSPE,         { RD, RB } },
2196 { "evfsctsi",  VX(4, 661), VX_MASK,     PPCSPE,         { RD, RB } },
2197 { "evfsctsiz", VX(4, 666), VX_MASK,     PPCSPE,         { RD, RB } },
2198 { "evfsctuf",  VX(4, 662), VX_MASK,     PPCSPE,         { RD, RB } },
2199 { "evfsctsf",  VX(4, 663), VX_MASK,     PPCSPE,         { RD, RB } },
2200
2201 { "efsabs",   VX(4, 708), VX_MASK,      PPCEFS,         { RD, RA } },
2202 { "efsnabs",  VX(4, 709), VX_MASK,      PPCEFS,         { RD, RA } },
2203 { "efsneg",   VX(4, 710), VX_MASK,      PPCEFS,         { RD, RA } },
2204 { "efsadd",   VX(4, 704), VX_MASK,      PPCEFS,         { RD, RA, RB } },
2205 { "efssub",   VX(4, 705), VX_MASK,      PPCEFS,         { RD, RA, RB } },
2206 { "efsmul",   VX(4, 712), VX_MASK,      PPCEFS,         { RD, RA, RB } },
2207 { "efsdiv",   VX(4, 713), VX_MASK,      PPCEFS,         { RD, RA, RB } },
2208 { "efscmpgt", VX(4, 716), VX_MASK,      PPCEFS,         { CRFD, RA, RB } },
2209 { "efscmplt", VX(4, 717), VX_MASK,      PPCEFS,         { CRFD, RA, RB } },
2210 { "efscmpeq", VX(4, 718), VX_MASK,      PPCEFS,         { CRFD, RA, RB } },
2211 { "efststgt", VX(4, 732), VX_MASK,      PPCEFS,         { CRFD, RA, RB } },
2212 { "efststlt", VX(4, 733), VX_MASK,      PPCEFS,         { CRFD, RA, RB } },
2213 { "efststeq", VX(4, 734), VX_MASK,      PPCEFS,         { CRFD, RA, RB } },
2214 { "efscfui",  VX(4, 720), VX_MASK,      PPCEFS,         { RD, RB } },
2215 { "efsctuiz", VX(4, 728), VX_MASK,      PPCEFS,         { RD, RB } },
2216 { "efscfsi",  VX(4, 721), VX_MASK,      PPCEFS,         { RD, RB } },
2217 { "efscfuf",  VX(4, 722), VX_MASK,      PPCEFS,         { RD, RB } },
2218 { "efscfsf",  VX(4, 723), VX_MASK,      PPCEFS,         { RD, RB } },
2219 { "efsctui",  VX(4, 724), VX_MASK,      PPCEFS,         { RD, RB } },
2220 { "efsctsi",  VX(4, 725), VX_MASK,      PPCEFS,         { RD, RB } },
2221 { "efsctsiz", VX(4, 730), VX_MASK,      PPCEFS,         { RD, RB } },
2222 { "efsctuf",  VX(4, 726), VX_MASK,      PPCEFS,         { RD, RB } },
2223 { "efsctsf",  VX(4, 727), VX_MASK,      PPCEFS,         { RD, RB } },
2224
2225 { "evsabs",    VX(4, 708), VX_MASK,     PPCSPE,         { RD, RA } },
2226 { "evsnabs",   VX(4, 709), VX_MASK,     PPCSPE,         { RD, RA } },
2227 { "evsneg",    VX(4, 710), VX_MASK,     PPCSPE,         { RD, RA } },
2228 { "evsadd",    VX(4, 704), VX_MASK,     PPCSPE,         { RD, RA, RB } },
2229 { "evssub",    VX(4, 705), VX_MASK,     PPCSPE,         { RD, RA, RB } },
2230 { "evsmul",    VX(4, 712), VX_MASK,     PPCSPE,         { RD, RA, RB } },
2231 { "evsdiv",    VX(4, 713), VX_MASK,     PPCSPE,         { RD, RA, RB } },
2232 { "evscmpgt",  VX(4, 716), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
2233 { "evsgmplt",  VX(4, 717), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
2234 { "evsgmpeq",  VX(4, 718), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
2235 { "evststgt",  VX(4, 732), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
2236 { "evststlt",  VX(4, 733), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
2237 { "evststeq",  VX(4, 734), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
2238 { "evscfui",   VX(4, 720), VX_MASK,     PPCSPE,         { RD, RB } },
2239 { "evscfsi",   VX(4, 721), VX_MASK,     PPCSPE,         { RD, RB } },
2240 { "evscfuf",   VX(4, 722), VX_MASK,     PPCSPE,         { RD, RB } },
2241 { "evscfsf",   VX(4, 723), VX_MASK,     PPCSPE,         { RD, RB } },
2242 { "evsctui",   VX(4, 724), VX_MASK,     PPCSPE,         { RD, RB } },
2243 { "evsctuiz",  VX(4, 728), VX_MASK,     PPCSPE,         { RD, RB } },
2244 { "evsctsi",   VX(4, 725), VX_MASK,     PPCSPE,         { RD, RB } },
2245 { "evsctsiz",  VX(4, 730), VX_MASK,     PPCSPE,         { RD, RB } },
2246 { "evsctuf",   VX(4, 726), VX_MASK,     PPCSPE,         { RD, RB } },
2247 { "evsctsf",   VX(4, 727), VX_MASK,     PPCSPE,         { RD, RB } },
2248
2249 { "evmhossf",  VX(4, 1031), VX_MASK,    PPCSPE,         { RD, RA, RB } },
2250 { "evmhossfa", VX(4, 1063), VX_MASK,    PPCSPE,         { RD, RA, RB } },
2251 { "evmhosmf",  VX(4, 1039), VX_MASK,    PPCSPE,         { RD, RA, RB } },
2252 { "evmhosmfa", VX(4, 1071), VX_MASK,    PPCSPE,         { RD, RA, RB } },
2253 { "evmhosmi",  VX(4, 1037), VX_MASK,    PPCSPE,         { RD, RA, RB } },
2254 { "evmhosmia", VX(4, 1069), VX_MASK,    PPCSPE,         { RD, RA, RB } },
2255 { "evmhoumi",  VX(4, 1036), VX_MASK,    PPCSPE,         { RD, RA, RB } },
2256 { "evmhoumia", VX(4, 1068), VX_MASK,    PPCSPE,         { RD, RA, RB } },
2257 { "evmhessf",  VX(4, 1027), VX_MASK,    PPCSPE,         { RD, RA, RB } },
2258 { "evmhessfa", VX(4, 1059), VX_MASK,    PPCSPE,         { RD, RA, RB } },
2259 { "evmhesmf",  VX(4, 1035), VX_MASK,    PPCSPE,         { RD, RA, RB } },
2260 { "evmhesmfa", VX(4, 1067), VX_MASK,    PPCSPE,         { RD, RA, RB } },
2261 { "evmhesmi",  VX(4, 1033), VX_MASK,    PPCSPE,         { RD, RA, RB } },
2262 { "evmhesmia", VX(4, 1065), VX_MASK,    PPCSPE,         { RD, RA, RB } },
2263 { "evmheumi",  VX(4, 1032), VX_MASK,    PPCSPE,         { RD, RA, RB } },
2264 { "evmheumia", VX(4, 1064), VX_MASK,    PPCSPE,         { RD, RA, RB } },
2265
2266 { "evmhossfaaw",VX(4, 1287), VX_MASK,   PPCSPE,         { RD, RA, RB } },
2267 { "evmhossiaaw",VX(4, 1285), VX_MASK,   PPCSPE,         { RD, RA, RB } },
2268 { "evmhosmfaaw",VX(4, 1295), VX_MASK,   PPCSPE,         { RD, RA, RB } },
2269 { "evmhosmiaaw",VX(4, 1293), VX_MASK,   PPCSPE,         { RD, RA, RB } },
2270 { "evmhousiaaw",VX(4, 1284), VX_MASK,   PPCSPE,         { RD, RA, RB } },
2271 { "evmhoumiaaw",VX(4, 1292), VX_MASK,   PPCSPE,         { RD, RA, RB } },
2272 { "evmhessfaaw",VX(4, 1283), VX_MASK,   PPCSPE,         { RD, RA, RB } },
2273 { "evmhessiaaw",VX(4, 1281), VX_MASK,   PPCSPE,         { RD, RA, RB } },
2274 { "evmhesmfaaw",VX(4, 1291), VX_MASK,   PPCSPE,         { RD, RA, RB } },
2275 { "evmhesmiaaw",VX(4, 1289), VX_MASK,   PPCSPE,         { RD, RA, RB } },
2276 { "evmheusiaaw",VX(4, 1280), VX_MASK,   PPCSPE,         { RD, RA, RB } },
2277 { "evmheumiaaw",VX(4, 1288), VX_MASK,   PPCSPE,         { RD, RA, RB } },
2278
2279 { "evmhossfanw",VX(4, 1415), VX_MASK,   PPCSPE,         { RD, RA, RB } },
2280 { "evmhossianw",VX(4, 1413), VX_MASK,   PPCSPE,         { RD, RA, RB } },
2281 { "evmhosmfanw",VX(4, 1423), VX_MASK,   PPCSPE,         { RD, RA, RB } },
2282 { "evmhosmianw",VX(4, 1421), VX_MASK,   PPCSPE,         { RD, RA, RB } },
2283 { "evmhousianw",VX(4, 1412), VX_MASK,   PPCSPE,         { RD, RA, RB } },
2284 { "evmhoumianw",VX(4, 1420), VX_MASK,   PPCSPE,         { RD, RA, RB } },
2285 { "evmhessfanw",VX(4, 1411), VX_MASK,   PPCSPE,         { RD, RA, RB } },
2286 { "evmhessianw",VX(4, 1409), VX_MASK,   PPCSPE,         { RD, RA, RB } },
2287 { "evmhesmfanw",VX(4, 1419), VX_MASK,   PPCSPE,         { RD, RA, RB } },
2288 { "evmhesmianw",VX(4, 1417), VX_MASK,   PPCSPE,         { RD, RA, RB } },
2289 { "evmheusianw",VX(4, 1408), VX_MASK,   PPCSPE,         { RD, RA, RB } },
2290 { "evmheumianw",VX(4, 1416), VX_MASK,   PPCSPE,         { RD, RA, RB } },
2291
2292 { "evmhogsmfaa",VX(4, 1327), VX_MASK,   PPCSPE,         { RD, RA, RB } },
2293 { "evmhogsmiaa",VX(4, 1325), VX_MASK,   PPCSPE,         { RD, RA, RB } },
2294 { "evmhogumiaa",VX(4, 1324), VX_MASK,   PPCSPE,         { RD, RA, RB } },
2295 { "evmhegsmfaa",VX(4, 1323), VX_MASK,   PPCSPE,         { RD, RA, RB } },
2296 { "evmhegsmiaa",VX(4, 1321), VX_MASK,   PPCSPE,         { RD, RA, RB } },
2297 { "evmhegumiaa",VX(4, 1320), VX_MASK,   PPCSPE,         { RD, RA, RB } },
2298
2299 { "evmhogsmfan",VX(4, 1455), VX_MASK,   PPCSPE,         { RD, RA, RB } },
2300 { "evmhogsmian",VX(4, 1453), VX_MASK,   PPCSPE,         { RD, RA, RB } },
2301 { "evmhogumian",VX(4, 1452), VX_MASK,   PPCSPE,         { RD, RA, RB } },
2302 { "evmhegsmfan",VX(4, 1451), VX_MASK,   PPCSPE,         { RD, RA, RB } },
2303 { "evmhegsmian",VX(4, 1449), VX_MASK,   PPCSPE,         { RD, RA, RB } },
2304 { "evmhegumian",VX(4, 1448), VX_MASK,   PPCSPE,         { RD, RA, RB } },
2305
2306 { "evmwhssf",  VX(4, 1095), VX_MASK,    PPCSPE,         { RD, RA, RB } },
2307 { "evmwhssfa", VX(4, 1127), VX_MASK,    PPCSPE,         { RD, RA, RB } },
2308 { "evmwhsmf",  VX(4, 1103), VX_MASK,    PPCSPE,         { RD, RA, RB } },
2309 { "evmwhsmfa", VX(4, 1135), VX_MASK,    PPCSPE,         { RD, RA, RB } },
2310 { "evmwhsmi",  VX(4, 1101), VX_MASK,    PPCSPE,         { RD, RA, RB } },
2311 { "evmwhsmia", VX(4, 1133), VX_MASK,    PPCSPE,         { RD, RA, RB } },
2312 { "evmwhumi",  VX(4, 1100), VX_MASK,    PPCSPE,         { RD, RA, RB } },
2313 { "evmwhumia", VX(4, 1132), VX_MASK,    PPCSPE,         { RD, RA, RB } },
2314
2315 { "evmwlssf",  VX(4, 1091), VX_MASK,    PPCSPE,         { RD, RA, RB } },
2316 { "evmwlssfa", VX(4, 1123), VX_MASK,    PPCSPE,         { RD, RA, RB } },
2317 { "evmwlsmf",  VX(4, 1099), VX_MASK,    PPCSPE,         { RD, RA, RB } },
2318 { "evmwlsmfa", VX(4, 1131), VX_MASK,    PPCSPE,         { RD, RA, RB } },
2319 { "evmwlumi",  VX(4, 1096), VX_MASK,    PPCSPE,         { RD, RA, RB } },
2320 { "evmwlumia", VX(4, 1128), VX_MASK,    PPCSPE,         { RD, RA, RB } },
2321
2322 { "evmwhssfaa",VX(4, 1351), VX_MASK,    PPCSPE,         { RD, RA, RB } },
2323 { "evmwhssmaa",VX(4, 1349), VX_MASK,    PPCSPE,         { RD, RA, RB } },
2324 { "evmwhsmfaa",VX(4, 1359), VX_MASK,    PPCSPE,         { RD, RA, RB } },
2325 { "evmwhsmiaa",VX(4, 1357), VX_MASK,    PPCSPE,         { RD, RA, RB } },
2326 { "evmwhusiaa",VX(4, 1348), VX_MASK,    PPCSPE,         { RD, RA, RB } },
2327 { "evmwhumiaa",VX(4, 1356), VX_MASK,    PPCSPE,         { RD, RA, RB } },
2328
2329 { "evmwlssfaaw",VX(4, 1347), VX_MASK,   PPCSPE,         { RD, RA, RB } },
2330 { "evmwlssiaaw",VX(4, 1345), VX_MASK,   PPCSPE,         { RD, RA, RB } },
2331 { "evmwlsmfaaw",VX(4, 1355), VX_MASK,   PPCSPE,         { RD, RA, RB } },
2332 { "evmwlsmiaaw",VX(4, 1353), VX_MASK,   PPCSPE,         { RD, RA, RB } },
2333 { "evmwlusiaaw",VX(4, 1344), VX_MASK,   PPCSPE,         { RD, RA, RB } },
2334 { "evmwlumiaaw",VX(4, 1352), VX_MASK,   PPCSPE,         { RD, RA, RB } },
2335
2336 { "evmwhssfan",VX(4, 1479), VX_MASK,    PPCSPE,         { RD, RA, RB } },
2337 { "evmwhssian",VX(4, 1477), VX_MASK,    PPCSPE,         { RD, RA, RB } },
2338 { "evmwhsmfan",VX(4, 1487), VX_MASK,    PPCSPE,         { RD, RA, RB } },
2339 { "evmwhsmian",VX(4, 1485), VX_MASK,    PPCSPE,         { RD, RA, RB } },
2340 { "evmwhusian",VX(4, 1476), VX_MASK,    PPCSPE,         { RD, RA, RB } },
2341 { "evmwhumian",VX(4, 1484), VX_MASK,    PPCSPE,         { RD, RA, RB } },
2342
2343 { "evmwlssfanw",VX(4, 1475), VX_MASK,   PPCSPE,         { RD, RA, RB } },
2344 { "evmwlssianw",VX(4, 1473), VX_MASK,   PPCSPE,         { RD, RA, RB } },
2345 { "evmwlsmfanw",VX(4, 1483), VX_MASK,   PPCSPE,         { RD, RA, RB } },
2346 { "evmwlsmianw",VX(4, 1481), VX_MASK,   PPCSPE,         { RD, RA, RB } },
2347 { "evmwlusianw",VX(4, 1472), VX_MASK,   PPCSPE,         { RD, RA, RB } },
2348 { "evmwlumianw",VX(4, 1480), VX_MASK,   PPCSPE,         { RD, RA, RB } },
2349
2350 { "evmwhgssfaa",VX(4, 1383), VX_MASK,   PPCSPE,         { RD, RA, RB } },
2351 { "evmwhgsmfaa",VX(4, 1391), VX_MASK,   PPCSPE,         { RD, RA, RB } },
2352 { "evmwhgsmiaa",VX(4, 1381), VX_MASK,   PPCSPE,         { RD, RA, RB } },
2353 { "evmwhgumiaa",VX(4, 1380), VX_MASK,   PPCSPE,         { RD, RA, RB } },
2354
2355 { "evmwhgssfan",VX(4, 1511), VX_MASK,   PPCSPE,         { RD, RA, RB } },
2356 { "evmwhgsmfan",VX(4, 1519), VX_MASK,   PPCSPE,         { RD, RA, RB } },
2357 { "evmwhgsmian",VX(4, 1509), VX_MASK,   PPCSPE,         { RD, RA, RB } },
2358 { "evmwhgumian",VX(4, 1508), VX_MASK,   PPCSPE,         { RD, RA, RB } },
2359
2360 { "evmwssf",   VX(4, 1107), VX_MASK,    PPCSPE,         { RD, RA, RB } },
2361 { "evmwssfa",  VX(4, 1139), VX_MASK,    PPCSPE,         { RD, RA, RB } },
2362 { "evmwsmf",   VX(4, 1115), VX_MASK,    PPCSPE,         { RD, RA, RB } },
2363 { "evmwsmfa",  VX(4, 1147), VX_MASK,    PPCSPE,         { RD, RA, RB } },
2364 { "evmwsmi",   VX(4, 1113), VX_MASK,    PPCSPE,         { RD, RA, RB } },
2365 { "evmwsmia",  VX(4, 1145), VX_MASK,    PPCSPE,         { RD, RA, RB } },
2366 { "evmwumi",   VX(4, 1112), VX_MASK,    PPCSPE,         { RD, RA, RB } },
2367 { "evmwumia",  VX(4, 1144), VX_MASK,    PPCSPE,         { RD, RA, RB } },
2368
2369 { "evmwssfaa", VX(4, 1363), VX_MASK,    PPCSPE,         { RD, RA, RB } },
2370 { "evmwsmfaa", VX(4, 1371), VX_MASK,    PPCSPE,         { RD, RA, RB } },
2371 { "evmwsmiaa", VX(4, 1369), VX_MASK,    PPCSPE,         { RD, RA, RB } },
2372 { "evmwumiaa", VX(4, 1368), VX_MASK,    PPCSPE,         { RD, RA, RB } },
2373
2374 { "evmwssfan", VX(4, 1491), VX_MASK,    PPCSPE,         { RD, RA, RB } },
2375 { "evmwsmfan", VX(4, 1499), VX_MASK,    PPCSPE,         { RD, RA, RB } },
2376 { "evmwsmian", VX(4, 1497), VX_MASK,    PPCSPE,         { RD, RA, RB } },
2377 { "evmwumian", VX(4, 1496), VX_MASK,    PPCSPE,         { RD, RA, RB } },
2378
2379 { "evaddssiaaw",VX(4, 1217), VX_MASK,   PPCSPE,         { RD, RA } },
2380 { "evaddsmiaaw",VX(4, 1225), VX_MASK,   PPCSPE,         { RD, RA } },
2381 { "evaddusiaaw",VX(4, 1216), VX_MASK,   PPCSPE,         { RD, RA } },
2382 { "evaddumiaaw",VX(4, 1224), VX_MASK,   PPCSPE,         { RD, RA } },
2383
2384 { "evsubfssiaaw",VX(4, 1219), VX_MASK,  PPCSPE,         { RD, RA } },
2385 { "evsubfsmiaaw",VX(4, 1227), VX_MASK,  PPCSPE,         { RD, RA } },
2386 { "evsubfusiaaw",VX(4, 1218), VX_MASK,  PPCSPE,         { RD, RA } },
2387 { "evsubfumiaaw",VX(4, 1226), VX_MASK,  PPCSPE,         { RD, RA } },
2388
2389 { "evmra",    VX(4, 1220), VX_MASK,     PPCSPE,         { RD, RA } },
2390
2391 { "evdivws",  VX(4, 1222), VX_MASK,     PPCSPE,         { RD, RA, RB } },
2392 { "evdivwu",  VX(4, 1223), VX_MASK,     PPCSPE,         { RD, RA, RB } },
2393
2394 { "mulli",   OP(7),     OP_MASK,        PPCCOM,         { RT, RA, SI } },
2395 { "muli",    OP(7),     OP_MASK,        PWRCOM,         { RT, RA, SI } },
2396
2397 { "subfic",  OP(8),     OP_MASK,        PPCCOM,         { RT, RA, SI } },
2398 { "sfi",     OP(8),     OP_MASK,        PWRCOM,         { RT, RA, SI } },
2399
2400 { "dozi",    OP(9),     OP_MASK,        M601,           { RT, RA, SI } },
2401
2402 { "bce",     B(9,0,0),  B_MASK,         BOOKE64,        { BO, BI, BD } },
2403 { "bcel",    B(9,0,1),  B_MASK,         BOOKE64,        { BO, BI, BD } },
2404 { "bcea",    B(9,1,0),  B_MASK,         BOOKE64,        { BO, BI, BDA } },
2405 { "bcela",   B(9,1,1),  B_MASK,         BOOKE64,        { BO, BI, BDA } },
2406
2407 { "cmplwi",  OPL(10,0), OPL_MASK,       PPCCOM,         { OBF, RA, UI } },
2408 { "cmpldi",  OPL(10,1), OPL_MASK,       PPC64,          { OBF, RA, UI } },
2409 { "cmpli",   OP(10),    OP_MASK,        PPCONLY,        { BF, L, RA, UI } },
2410 { "cmpli",   OP(10),    OP_MASK,        PWRCOM,         { BF, RA, UI } },
2411
2412 { "cmpwi",   OPL(11,0), OPL_MASK,       PPCCOM,         { OBF, RA, SI } },
2413 { "cmpdi",   OPL(11,1), OPL_MASK,       PPC64,          { OBF, RA, SI } },
2414 { "cmpi",    OP(11),    OP_MASK,        PPCONLY,        { BF, L, RA, SI } },
2415 { "cmpi",    OP(11),    OP_MASK,        PWRCOM,         { BF, RA, SI } },
2416
2417 { "addic",   OP(12),    OP_MASK,        PPCCOM,         { RT, RA, SI } },
2418 { "ai",      OP(12),    OP_MASK,        PWRCOM,         { RT, RA, SI } },
2419 { "subic",   OP(12),    OP_MASK,        PPCCOM,         { RT, RA, NSI } },
2420
2421 { "addic.",  OP(13),    OP_MASK,        PPCCOM,         { RT, RA, SI } },
2422 { "ai.",     OP(13),    OP_MASK,        PWRCOM,         { RT, RA, SI } },
2423 { "subic.",  OP(13),    OP_MASK,        PPCCOM,         { RT, RA, NSI } },
2424
2425 { "li",      OP(14),    DRA_MASK,       PPCCOM,         { RT, SI } },
2426 { "lil",     OP(14),    DRA_MASK,       PWRCOM,         { RT, SI } },
2427 { "addi",    OP(14),    OP_MASK,        PPCCOM,         { RT, RA, SI } },
2428 { "cal",     OP(14),    OP_MASK,        PWRCOM,         { RT, D, RA } },
2429 { "subi",    OP(14),    OP_MASK,        PPCCOM,         { RT, RA, NSI } },
2430 { "la",      OP(14),    OP_MASK,        PPCCOM,         { RT, D, RA } },
2431
2432 { "lis",     OP(15),    DRA_MASK,       PPCCOM,         { RT, SISIGNOPT } },
2433 { "liu",     OP(15),    DRA_MASK,       PWRCOM,         { RT, SISIGNOPT } },
2434 { "addis",   OP(15),    OP_MASK,        PPCCOM,         { RT,RA,SISIGNOPT } },
2435 { "cau",     OP(15),    OP_MASK,        PWRCOM,         { RT,RA,SISIGNOPT } },
2436 { "subis",   OP(15),    OP_MASK,        PPCCOM,         { RT, RA, NSI } },
2437
2438 { "bdnz-",   BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM,   { BDM } },
2439 { "bdnz+",   BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM,   { BDP } },
2440 { "bdnz",    BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM,   { BD } },
2441 { "bdn",     BBO(16,BODNZ,0,0), BBOATBI_MASK, PWRCOM,   { BD } },
2442 { "bdnzl-",  BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM,   { BDM } },
2443 { "bdnzl+",  BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM,   { BDP } },
2444 { "bdnzl",   BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM,   { BD } },
2445 { "bdnl",    BBO(16,BODNZ,0,1), BBOATBI_MASK, PWRCOM,   { BD } },
2446 { "bdnza-",  BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM,   { BDMA } },
2447 { "bdnza+",  BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM,   { BDPA } },
2448 { "bdnza",   BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM,   { BDA } },
2449 { "bdna",    BBO(16,BODNZ,1,0), BBOATBI_MASK, PWRCOM,   { BDA } },
2450 { "bdnzla-", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM,   { BDMA } },
2451 { "bdnzla+", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM,   { BDPA } },
2452 { "bdnzla",  BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM,   { BDA } },
2453 { "bdnla",   BBO(16,BODNZ,1,1), BBOATBI_MASK, PWRCOM,   { BDA } },
2454 { "bdz-",    BBO(16,BODZ,0,0),  BBOATBI_MASK, PPCCOM,   { BDM } },
2455 { "bdz+",    BBO(16,BODZ,0,0),  BBOATBI_MASK, PPCCOM,   { BDP } },
2456 { "bdz",     BBO(16,BODZ,0,0),  BBOATBI_MASK, COM,      { BD } },
2457 { "bdzl-",   BBO(16,BODZ,0,1),  BBOATBI_MASK, PPCCOM,   { BDM } },
2458 { "bdzl+",   BBO(16,BODZ,0,1),  BBOATBI_MASK, PPCCOM,   { BDP } },
2459 { "bdzl",    BBO(16,BODZ,0,1),  BBOATBI_MASK, COM,      { BD } },
2460 { "bdza-",   BBO(16,BODZ,1,0),  BBOATBI_MASK, PPCCOM,   { BDMA } },
2461 { "bdza+",   BBO(16,BODZ,1,0),  BBOATBI_MASK, PPCCOM,   { BDPA } },
2462 { "bdza",    BBO(16,BODZ,1,0),  BBOATBI_MASK, COM,      { BDA } },
2463 { "bdzla-",  BBO(16,BODZ,1,1),  BBOATBI_MASK, PPCCOM,   { BDMA } },
2464 { "bdzla+",  BBO(16,BODZ,1,1),  BBOATBI_MASK, PPCCOM,   { BDPA } },
2465 { "bdzla",   BBO(16,BODZ,1,1),  BBOATBI_MASK, COM,      { BDA } },
2466 { "blt-",    BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2467 { "blt+",    BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2468 { "blt",     BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM,         { CR, BD } },
2469 { "bltl-",   BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2470 { "bltl+",   BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2471 { "bltl",    BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, COM,         { CR, BD } },
2472 { "blta-",   BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2473 { "blta+",   BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2474 { "blta",    BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
2475 { "bltla-",  BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2476 { "bltla+",  BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2477 { "bltla",   BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
2478 { "bgt-",    BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2479 { "bgt+",    BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2480 { "bgt",     BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, COM,         { CR, BD } },
2481 { "bgtl-",   BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2482 { "bgtl+",   BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2483 { "bgtl",    BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, COM,         { CR, BD } },
2484 { "bgta-",   BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2485 { "bgta+",   BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2486 { "bgta",    BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
2487 { "bgtla-",  BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2488 { "bgtla+",  BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2489 { "bgtla",   BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
2490 { "beq-",    BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2491 { "beq+",    BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2492 { "beq",     BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, COM,         { CR, BD } },
2493 { "beql-",   BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2494 { "beql+",   BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2495 { "beql",    BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, COM,         { CR, BD } },
2496 { "beqa-",   BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2497 { "beqa+",   BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2498 { "beqa",    BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
2499 { "beqla-",  BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2500 { "beqla+",  BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2501 { "beqla",   BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
2502 { "bso-",    BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2503 { "bso+",    BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2504 { "bso",     BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, COM,         { CR, BD } },
2505 { "bsol-",   BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2506 { "bsol+",   BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2507 { "bsol",    BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, COM,         { CR, BD } },
2508 { "bsoa-",   BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2509 { "bsoa+",   BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2510 { "bsoa",    BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
2511 { "bsola-",  BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2512 { "bsola+",  BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2513 { "bsola",   BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
2514 { "bun-",    BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2515 { "bun+",    BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2516 { "bun",     BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BD } },
2517 { "bunl-",   BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2518 { "bunl+",   BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2519 { "bunl",    BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BD } },
2520 { "buna-",   BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2521 { "buna+",   BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2522 { "buna",    BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDA } },
2523 { "bunla-",  BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2524 { "bunla+",  BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2525 { "bunla",   BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDA } },
2526 { "bge-",    BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2527 { "bge+",    BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2528 { "bge",     BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM,         { CR, BD } },
2529 { "bgel-",   BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2530 { "bgel+",   BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2531 { "bgel",    BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM,         { CR, BD } },
2532 { "bgea-",   BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2533 { "bgea+",   BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2534 { "bgea",    BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
2535 { "bgela-",  BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2536 { "bgela+",  BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2537 { "bgela",   BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
2538 { "bnl-",    BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2539 { "bnl+",    BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2540 { "bnl",     BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM,         { CR, BD } },
2541 { "bnll-",   BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2542 { "bnll+",   BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2543 { "bnll",    BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM,         { CR, BD } },
2544 { "bnla-",   BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2545 { "bnla+",   BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2546 { "bnla",    BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
2547 { "bnlla-",  BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2548 { "bnlla+",  BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2549 { "bnlla",   BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
2550 { "ble-",    BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2551 { "ble+",    BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2552 { "ble",     BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM,         { CR, BD } },
2553 { "blel-",   BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2554 { "blel+",   BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2555 { "blel",    BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM,         { CR, BD } },
2556 { "blea-",   BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2557 { "blea+",   BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2558 { "blea",    BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
2559 { "blela-",  BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2560 { "blela+",  BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2561 { "blela",   BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
2562 { "bng-",    BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2563 { "bng+",    BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2564 { "bng",     BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM,         { CR, BD } },
2565 { "bngl-",   BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2566 { "bngl+",   BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2567 { "bngl",    BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM,         { CR, BD } },
2568 { "bnga-",   BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2569 { "bnga+",   BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2570 { "bnga",    BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
2571 { "bngla-",  BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2572 { "bngla+",  BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2573 { "bngla",   BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
2574 { "bne-",    BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2575 { "bne+",    BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2576 { "bne",     BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, COM,         { CR, BD } },
2577 { "bnel-",   BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2578 { "bnel+",   BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2579 { "bnel",    BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, COM,         { CR, BD } },
2580 { "bnea-",   BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2581 { "bnea+",   BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2582 { "bnea",    BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
2583 { "bnela-",  BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2584 { "bnela+",  BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2585 { "bnela",   BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
2586 { "bns-",    BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2587 { "bns+",    BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2588 { "bns",     BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, COM,         { CR, BD } },
2589 { "bnsl-",   BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2590 { "bnsl+",   BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2591 { "bnsl",    BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, COM,         { CR, BD } },
2592 { "bnsa-",   BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2593 { "bnsa+",   BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2594 { "bnsa",    BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
2595 { "bnsla-",  BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2596 { "bnsla+",  BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2597 { "bnsla",   BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
2598 { "bnu-",    BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2599 { "bnu+",    BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2600 { "bnu",     BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BD } },
2601 { "bnul-",   BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2602 { "bnul+",   BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2603 { "bnul",    BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BD } },
2604 { "bnua-",   BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2605 { "bnua+",   BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2606 { "bnua",    BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDA } },
2607 { "bnula-",  BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2608 { "bnula+",  BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2609 { "bnula",   BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDA } },
2610 { "bdnzt-",  BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4,   { BI, BDM } },
2611 { "bdnzt+",  BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4,   { BI, BDP } },
2612 { "bdnzt",   BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM,     { BI, BD } },
2613 { "bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4,   { BI, BDM } },
2614 { "bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4,   { BI, BDP } },
2615 { "bdnztl",  BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM,     { BI, BD } },
2616 { "bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4,   { BI, BDMA } },
2617 { "bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4,   { BI, BDPA } },
2618 { "bdnzta",  BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM,     { BI, BDA } },
2619 { "bdnztla-",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4,   { BI, BDMA } },
2620 { "bdnztla+",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4,   { BI, BDPA } },
2621 { "bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM,     { BI, BDA } },
2622 { "bdnzf-",  BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4,   { BI, BDM } },
2623 { "bdnzf+",  BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4,   { BI, BDP } },
2624 { "bdnzf",   BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM,     { BI, BD } },
2625 { "bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4,   { BI, BDM } },
2626 { "bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4,   { BI, BDP } },
2627 { "bdnzfl",  BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM,     { BI, BD } },
2628 { "bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4,   { BI, BDMA } },
2629 { "bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4,   { BI, BDPA } },
2630 { "bdnzfa",  BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM,     { BI, BDA } },
2631 { "bdnzfla-",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4,   { BI, BDMA } },
2632 { "bdnzfla+",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4,   { BI, BDPA } },
2633 { "bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM,     { BI, BDA } },
2634 { "bt-",     BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM,       { BI, BDM } },
2635 { "bt+",     BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM,       { BI, BDP } },
2636 { "bt",      BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM,       { BI, BD } },
2637 { "bbt",     BBO(16,BOT,0,0), BBOAT_MASK, PWRCOM,       { BI, BD } },
2638 { "btl-",    BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM,       { BI, BDM } },
2639 { "btl+",    BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM,       { BI, BDP } },
2640 { "btl",     BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM,       { BI, BD } },
2641 { "bbtl",    BBO(16,BOT,0,1), BBOAT_MASK, PWRCOM,       { BI, BD } },
2642 { "bta-",    BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM,       { BI, BDMA } },
2643 { "bta+",    BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM,       { BI, BDPA } },
2644 { "bta",     BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM,       { BI, BDA } },
2645 { "bbta",    BBO(16,BOT,1,0), BBOAT_MASK, PWRCOM,       { BI, BDA } },
2646 { "btla-",   BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM,       { BI, BDMA } },
2647 { "btla+",   BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM,       { BI, BDPA } },
2648 { "btla",    BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM,       { BI, BDA } },
2649 { "bbtla",   BBO(16,BOT,1,1), BBOAT_MASK, PWRCOM,       { BI, BDA } },
2650 { "bf-",     BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM,       { BI, BDM } },
2651 { "bf+",     BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM,       { BI, BDP } },
2652 { "bf",      BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM,       { BI, BD } },
2653 { "bbf",     BBO(16,BOF,0,0), BBOAT_MASK, PWRCOM,       { BI, BD } },
2654 { "bfl-",    BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM,       { BI, BDM } },
2655 { "bfl+",    BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM,       { BI, BDP } },
2656 { "bfl",     BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM,       { BI, BD } },
2657 { "bbfl",    BBO(16,BOF,0,1), BBOAT_MASK, PWRCOM,       { BI, BD } },
2658 { "bfa-",    BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM,       { BI, BDMA } },
2659 { "bfa+",    BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM,       { BI, BDPA } },
2660 { "bfa",     BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM,       { BI, BDA } },
2661 { "bbfa",    BBO(16,BOF,1,0), BBOAT_MASK, PWRCOM,       { BI, BDA } },
2662 { "bfla-",   BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM,       { BI, BDMA } },
2663 { "bfla+",   BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM,       { BI, BDPA } },
2664 { "bfla",    BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM,       { BI, BDA } },
2665 { "bbfla",   BBO(16,BOF,1,1), BBOAT_MASK, PWRCOM,       { BI, BDA } },
2666 { "bdzt-",   BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4,    { BI, BDM } },
2667 { "bdzt+",   BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4,    { BI, BDP } },
2668 { "bdzt",    BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM,      { BI, BD } },
2669 { "bdztl-",  BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4,    { BI, BDM } },
2670 { "bdztl+",  BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4,    { BI, BDP } },
2671 { "bdztl",   BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM,      { BI, BD } },
2672 { "bdzta-",  BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4,    { BI, BDMA } },
2673 { "bdzta+",  BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4,    { BI, BDPA } },
2674 { "bdzta",   BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM,      { BI, BDA } },
2675 { "bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4,    { BI, BDMA } },
2676 { "bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4,    { BI, BDPA } },
2677 { "bdztla",  BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM,      { BI, BDA } },
2678 { "bdzf-",   BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4,    { BI, BDM } },
2679 { "bdzf+",   BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4,    { BI, BDP } },
2680 { "bdzf",    BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM,      { BI, BD } },
2681 { "bdzfl-",  BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4,    { BI, BDM } },
2682 { "bdzfl+",  BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4,    { BI, BDP } },
2683 { "bdzfl",   BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM,      { BI, BD } },
2684 { "bdzfa-",  BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4,    { BI, BDMA } },
2685 { "bdzfa+",  BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4,    { BI, BDPA } },
2686 { "bdzfa",   BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM,      { BI, BDA } },
2687 { "bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4,    { BI, BDMA } },
2688 { "bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4,    { BI, BDPA } },
2689 { "bdzfla",  BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM,      { BI, BDA } },
2690 { "bc-",     B(16,0,0), B_MASK,         PPCCOM,         { BOE, BI, BDM } },
2691 { "bc+",     B(16,0,0), B_MASK,         PPCCOM,         { BOE, BI, BDP } },
2692 { "bc",      B(16,0,0), B_MASK,         COM,            { BO, BI, BD } },
2693 { "bcl-",    B(16,0,1), B_MASK,         PPCCOM,         { BOE, BI, BDM } },
2694 { "bcl+",    B(16,0,1), B_MASK,         PPCCOM,         { BOE, BI, BDP } },
2695 { "bcl",     B(16,0,1), B_MASK,         COM,            { BO, BI, BD } },
2696 { "bca-",    B(16,1,0), B_MASK,         PPCCOM,         { BOE, BI, BDMA } },
2697 { "bca+",    B(16,1,0), B_MASK,         PPCCOM,         { BOE, BI, BDPA } },
2698 { "bca",     B(16,1,0), B_MASK,         COM,            { BO, BI, BDA } },
2699 { "bcla-",   B(16,1,1), B_MASK,         PPCCOM,         { BOE, BI, BDMA } },
2700 { "bcla+",   B(16,1,1), B_MASK,         PPCCOM,         { BOE, BI, BDPA } },
2701 { "bcla",    B(16,1,1), B_MASK,         COM,            { BO, BI, BDA } },
2702
2703 { "sc",      SC(17,1,0), 0xffffffff,    PPC,            { 0 } },
2704 { "svc",     SC(17,0,0), SC_MASK,       POWER,          { LEV, FL1, FL2 } },
2705 { "svcl",    SC(17,0,1), SC_MASK,       POWER,          { LEV, FL1, FL2 } },
2706 { "svca",    SC(17,1,0), SC_MASK,       PWRCOM,         { SV } },
2707 { "svcla",   SC(17,1,1), SC_MASK,       POWER,          { SV } },
2708
2709 { "b",       B(18,0,0), B_MASK,         COM,            { LI } },
2710 { "bl",      B(18,0,1), B_MASK,         COM,            { LI } },
2711 { "ba",      B(18,1,0), B_MASK,         COM,            { LIA } },
2712 { "bla",     B(18,1,1), B_MASK,         COM,            { LIA } },
2713
2714 { "mcrf",    XL(19,0),  XLBB_MASK|(3<<21)|(3<<16), COM, { BF, BFA } },
2715
2716 { "blr",     XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM,   { 0 } },
2717 { "br",      XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM,   { 0 } },
2718 { "blrl",    XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM,   { 0 } },
2719 { "brl",     XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM,   { 0 } },
2720 { "bdnzlr",  XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
2721 { "bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, NOPOWER4,       { 0 } },
2722 { "bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, NOPOWER4,      { 0 } },
2723 { "bdnzlr-", XLO(19,BODNZM4,16,0), XLBOBIBB_MASK, POWER4,       { 0 } },
2724 { "bdnzlr+", XLO(19,BODNZP4,16,0), XLBOBIBB_MASK, POWER4,       { 0 } },
2725 { "bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
2726 { "bdnzlrl-",XLO(19,BODNZ,16,1), XLBOBIBB_MASK, NOPOWER4,       { 0 } },
2727 { "bdnzlrl+",XLO(19,BODNZP,16,1), XLBOBIBB_MASK, NOPOWER4,      { 0 } },
2728 { "bdnzlrl-",XLO(19,BODNZM4,16,1), XLBOBIBB_MASK, POWER4,       { 0 } },
2729 { "bdnzlrl+",XLO(19,BODNZP4,16,1), XLBOBIBB_MASK, POWER4,       { 0 } },
2730 { "bdzlr",   XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM,  { 0 } },
2731 { "bdzlr-",  XLO(19,BODZ,16,0), XLBOBIBB_MASK, NOPOWER4,        { 0 } },
2732 { "bdzlr+",  XLO(19,BODZP,16,0), XLBOBIBB_MASK, NOPOWER4,       { 0 } },
2733 { "bdzlr-",  XLO(19,BODZM4,16,0), XLBOBIBB_MASK, POWER4,        { 0 } },
2734 { "bdzlr+",  XLO(19,BODZP4,16,0), XLBOBIBB_MASK, POWER4,        { 0 } },
2735 { "bdzlrl",  XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM,  { 0 } },
2736 { "bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, NOPOWER4,        { 0 } },
2737 { "bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, NOPOWER4,       { 0 } },
2738 { "bdzlrl-", XLO(19,BODZM4,16,1), XLBOBIBB_MASK, POWER4,        { 0 } },
2739 { "bdzlrl+", XLO(19,BODZP4,16,1), XLBOBIBB_MASK, POWER4,        { 0 } },
2740 { "bltlr",   XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2741 { "bltlr-",  XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2742 { "bltlr+",  XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2743 { "bltlr-",  XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2744 { "bltlr+",  XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2745 { "bltr",    XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2746 { "bltlrl",  XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2747 { "bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2748 { "bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2749 { "bltlrl-", XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2750 { "bltlrl+", XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2751 { "bltrl",   XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2752 { "bgtlr",   XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2753 { "bgtlr-",  XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2754 { "bgtlr+",  XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2755 { "bgtlr-",  XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2756 { "bgtlr+",  XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2757 { "bgtr",    XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2758 { "bgtlrl",  XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2759 { "bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2760 { "bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2761 { "bgtlrl-", XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2762 { "bgtlrl+", XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2763 { "bgtrl",   XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2764 { "beqlr",   XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2765 { "beqlr-",  XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2766 { "beqlr+",  XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2767 { "beqlr-",  XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2768 { "beqlr+",  XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2769 { "beqr",    XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2770 { "beqlrl",  XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2771 { "beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2772 { "beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2773 { "beqlrl-", XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2774 { "beqlrl+", XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2775 { "beqrl",   XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2776 { "bsolr",   XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2777 { "bsolr-",  XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2778 { "bsolr+",  XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2779 { "bsolr-",  XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2780 { "bsolr+",  XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2781 { "bsor",    XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2782 { "bsolrl",  XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2783 { "bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2784 { "bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2785 { "bsolrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2786 { "bsolrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2787 { "bsorl",   XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2788 { "bunlr",   XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2789 { "bunlr-",  XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2790 { "bunlr+",  XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2791 { "bunlr-",  XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2792 { "bunlr+",  XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2793 { "bunlrl",  XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2794 { "bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2795 { "bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2796 { "bunlrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2797 { "bunlrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2798 { "bgelr",   XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2799 { "bgelr-",  XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2800 { "bgelr+",  XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2801 { "bgelr-",  XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2802 { "bgelr+",  XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2803 { "bger",    XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2804 { "bgelrl",  XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2805 { "bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2806 { "bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2807 { "bgelrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2808 { "bgelrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2809 { "bgerl",   XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2810 { "bnllr",   XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2811 { "bnllr-",  XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2812 { "bnllr+",  XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2813 { "bnllr-",  XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2814 { "bnllr+",  XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2815 { "bnlr",    XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2816 { "bnllrl",  XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2817 { "bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2818 { "bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2819 { "bnllrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2820 { "bnllrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2821 { "bnlrl",   XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2822 { "blelr",   XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2823 { "blelr-",  XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2824 { "blelr+",  XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2825 { "blelr-",  XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2826 { "blelr+",  XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2827 { "bler",    XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2828 { "blelrl",  XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2829 { "blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2830 { "blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2831 { "blelrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2832 { "blelrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2833 { "blerl",   XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2834 { "bnglr",   XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2835 { "bnglr-",  XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2836 { "bnglr+",  XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2837 { "bnglr-",  XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2838 { "bnglr+",  XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2839 { "bngr",    XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2840 { "bnglrl",  XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2841 { "bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2842 { "bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2843 { "bnglrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2844 { "bnglrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2845 { "bngrl",   XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2846 { "bnelr",   XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2847 { "bnelr-",  XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2848 { "bnelr+",  XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2849 { "bnelr-",  XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2850 { "bnelr+",  XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2851 { "bner",    XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2852 { "bnelrl",  XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2853 { "bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2854 { "bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2855 { "bnelrl-", XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2856 { "bnelrl+", XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2857 { "bnerl",   XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2858 { "bnslr",   XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2859 { "bnslr-",  XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2860 { "bnslr+",  XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2861 { "bnslr-",  XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2862 { "bnslr+",  XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2863 { "bnsr",    XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2864 { "bnslrl",  XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2865 { "bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2866 { "bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2867 { "bnslrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2868 { "bnslrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2869 { "bnsrl",   XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2870 { "bnulr",   XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2871 { "bnulr-",  XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2872 { "bnulr+",  XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2873 { "bnulr-",  XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2874 { "bnulr+",  XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2875 { "bnulrl",  XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2876 { "bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2877 { "bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2878 { "bnulrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2879 { "bnulrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2880 { "btlr",    XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM,     { BI } },
2881 { "btlr-",   XLO(19,BOT,16,0), XLBOBB_MASK, NOPOWER4,   { BI } },
2882 { "btlr+",   XLO(19,BOTP,16,0), XLBOBB_MASK, NOPOWER4,  { BI } },
2883 { "btlr-",   XLO(19,BOTM4,16,0), XLBOBB_MASK, POWER4,   { BI } },
2884 { "btlr+",   XLO(19,BOTP4,16,0), XLBOBB_MASK, POWER4,   { BI } },
2885 { "bbtr",    XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM,     { BI } },
2886 { "btlrl",   XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM,     { BI } },
2887 { "btlrl-",  XLO(19,BOT,16,1), XLBOBB_MASK, NOPOWER4,   { BI } },
2888 { "btlrl+",  XLO(19,BOTP,16,1), XLBOBB_MASK, NOPOWER4,  { BI } },
2889 { "btlrl-",  XLO(19,BOTM4,16,1), XLBOBB_MASK, POWER4,   { BI } },
2890 { "btlrl+",  XLO(19,BOTP4,16,1), XLBOBB_MASK, POWER4,   { BI } },
2891 { "bbtrl",   XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM,     { BI } },
2892 { "bflr",    XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM,     { BI } },
2893 { "bflr-",   XLO(19,BOF,16,0), XLBOBB_MASK, NOPOWER4,   { BI } },
2894 { "bflr+",   XLO(19,BOFP,16,0), XLBOBB_MASK, NOPOWER4,  { BI } },
2895 { "bflr-",   XLO(19,BOFM4,16,0), XLBOBB_MASK, POWER4,   { BI } },
2896 { "bflr+",   XLO(19,BOFP4,16,0), XLBOBB_MASK, POWER4,   { BI } },
2897 { "bbfr",    XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM,     { BI } },
2898 { "bflrl",   XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM,     { BI } },
2899 { "bflrl-",  XLO(19,BOF,16,1), XLBOBB_MASK, NOPOWER4,   { BI } },
2900 { "bflrl+",  XLO(19,BOFP,16,1), XLBOBB_MASK, NOPOWER4,  { BI } },
2901 { "bflrl-",  XLO(19,BOFM4,16,1), XLBOBB_MASK, POWER4,   { BI } },
2902 { "bflrl+",  XLO(19,BOFP4,16,1), XLBOBB_MASK, POWER4,   { BI } },
2903 { "bbfrl",   XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM,     { BI } },
2904 { "bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM,  { BI } },
2905 { "bdnztlr-",XLO(19,BODNZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2906 { "bdnztlr+",XLO(19,BODNZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2907 { "bdnztlrl",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM,  { BI } },
2908 { "bdnztlrl-",XLO(19,BODNZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2909 { "bdnztlrl+",XLO(19,BODNZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2910 { "bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM,  { BI } },
2911 { "bdnzflr-",XLO(19,BODNZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2912 { "bdnzflr+",XLO(19,BODNZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2913 { "bdnzflrl",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM,  { BI } },
2914 { "bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2915 { "bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2916 { "bdztlr",  XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM,   { BI } },
2917 { "bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2918 { "bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2919 { "bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM,   { BI } },
2920 { "bdztlrl-",XLO(19,BODZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2921 { "bdztlrl+",XLO(19,BODZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2922 { "bdzflr",  XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM,   { BI } },
2923 { "bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2924 { "bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2925 { "bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM,   { BI } },
2926 { "bdzflrl-",XLO(19,BODZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2927 { "bdzflrl+",XLO(19,BODZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2928 { "bclr",    XLLK(19,16,0), XLYBB_MASK, PPCCOM,         { BO, BI } },
2929 { "bclrl",   XLLK(19,16,1), XLYBB_MASK, PPCCOM,         { BO, BI } },
2930 { "bclr+",   XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM,      { BOE, BI } },
2931 { "bclrl+",  XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM,      { BOE, BI } },
2932 { "bclr-",   XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM,      { BOE, BI } },
2933 { "bclrl-",  XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM,      { BOE, BI } },
2934 { "bcr",     XLLK(19,16,0), XLBB_MASK,  PWRCOM,         { BO, BI } },
2935 { "bcrl",    XLLK(19,16,1), XLBB_MASK,  PWRCOM,         { BO, BI } },
2936 { "bclre",   XLLK(19,17,0), XLBB_MASK,  BOOKE64,        { BO, BI } },
2937 { "bclrel",  XLLK(19,17,1), XLBB_MASK,  BOOKE64,        { BO, BI } },
2938
2939 { "rfid",    XL(19,18), 0xffffffff,     PPC64,          { 0 } },
2940
2941 { "crnot",   XL(19,33), XL_MASK,        PPCCOM,         { BT, BA, BBA } },
2942 { "crnor",   XL(19,33), XL_MASK,        COM,            { BT, BA, BB } },
2943 { "rfmci",    X(19,38),  0xffffffff,    PPCRFMCI,       { 0 } },
2944
2945
2946 { "rfi",     XL(19,50), 0xffffffff,     COM,            { 0 } },
2947 { "rfci",    XL(19,51), 0xffffffff,     PPC403,         { 0 } },
2948 { "rfci",    XL(19,51), 0xffffffff,     BOOKE,          { 0 } },
2949
2950 { "rfsvc",   XL(19,82), 0xffffffff,     POWER,          { 0 } },
2951
2952 { "crandc",  XL(19,129), XL_MASK,       COM,            { BT, BA, BB } },
2953
2954 { "isync",   XL(19,150), 0xffffffff,    PPCCOM,         { 0 } },
2955 { "ics",     XL(19,150), 0xffffffff,    PWRCOM,         { 0 } },
2956
2957 { "crclr",   XL(19,193), XL_MASK,       PPCCOM,         { BT, BAT, BBA } },
2958 { "crxor",   XL(19,193), XL_MASK,       COM,            { BT, BA, BB } },
2959
2960 { "crnand",  XL(19,225), XL_MASK,       COM,            { BT, BA, BB } },
2961
2962 { "crand",   XL(19,257), XL_MASK,       COM,            { BT, BA, BB } },
2963
2964 { "crset",   XL(19,289), XL_MASK,       PPCCOM,         { BT, BAT, BBA } },
2965 { "creqv",   XL(19,289), XL_MASK,       COM,            { BT, BA, BB } },
2966
2967 { "crorc",   XL(19,417), XL_MASK,       COM,            { BT, BA, BB } },
2968
2969 { "crmove",  XL(19,449), XL_MASK,       PPCCOM,         { BT, BA, BBA } },
2970 { "cror",    XL(19,449), XL_MASK,       COM,            { BT, BA, BB } },
2971
2972 { "bctr",    XLO(19,BOU,528,0), XLBOBIBB_MASK, COM,     { 0 } },
2973 { "bctrl",   XLO(19,BOU,528,1), XLBOBIBB_MASK, COM,     { 0 } },
2974 { "bltctr",  XLOCB(19,BOT,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2975 { "bltctr-", XLOCB(19,BOT,CBLT,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2976 { "bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2977 { "bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2978 { "bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2979 { "bltctrl", XLOCB(19,BOT,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2980 { "bltctrl-",XLOCB(19,BOT,CBLT,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2981 { "bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2982 { "bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2983 { "bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2984 { "bgtctr",  XLOCB(19,BOT,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2985 { "bgtctr-", XLOCB(19,BOT,CBGT,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2986 { "bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2987 { "bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2988 { "bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2989 { "bgtctrl", XLOCB(19,BOT,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2990 { "bgtctrl-",XLOCB(19,BOT,CBGT,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2991 { "bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2992 { "bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2993 { "bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2994 { "beqctr",  XLOCB(19,BOT,CBEQ,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2995 { "beqctr-", XLOCB(19,BOT,CBEQ,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2996 { "beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2997 { "beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2998 { "beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2999 { "beqctrl", XLOCB(19,BOT,CBEQ,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
3000 { "beqctrl-",XLOCB(19,BOT,CBEQ,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3001 { "beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3002 { "beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3003 { "beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3004 { "bsoctr",  XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
3005 { "bsoctr-", XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3006 { "bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3007 { "bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3008 { "bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3009 { "bsoctrl", XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
3010 { "bsoctrl-",XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3011 { "bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3012 { "bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3013 { "bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3014 { "bunctr",  XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
3015 { "bunctr-", XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3016 { "bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3017 { "bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3018 { "bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3019 { "bunctrl", XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
3020 { "bunctrl-",XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3021 { "bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3022 { "bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3023 { "bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3024 { "bgectr",  XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
3025 { "bgectr-", XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3026 { "bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3027 { "bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3028 { "bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3029 { "bgectrl", XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
3030 { "bgectrl-",XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3031 { "bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3032 { "bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3033 { "bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3034 { "bnlctr",  XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
3035 { "bnlctr-", XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3036 { "bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3037 { "bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3038 { "bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3039 { "bnlctrl", XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
3040 { "bnlctrl-",XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3041 { "bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3042 { "bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3043 { "bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3044 { "blectr",  XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
3045 { "blectr-", XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3046 { "blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3047 { "blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3048 { "blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3049 { "blectrl", XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
3050 { "blectrl-",XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3051 { "blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3052 { "blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3053 { "blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3054 { "bngctr",  XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
3055 { "bngctr-", XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3056 { "bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3057 { "bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3058 { "bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3059 { "bngctrl", XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
3060 { "bngctrl-",XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3061 { "bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3062 { "bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3063 { "bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3064 { "bnectr",  XLOCB(19,BOF,CBEQ,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
3065 { "bnectr-", XLOCB(19,BOF,CBEQ,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3066 { "bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3067 { "bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3068 { "bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3069 { "bnectrl", XLOCB(19,BOF,CBEQ,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
3070 { "bnectrl-",XLOCB(19,BOF,CBEQ,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3071 { "bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3072 { "bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3073 { "bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3074 { "bnsctr",  XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
3075 { "bnsctr-", XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3076 { "bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3077 { "bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3078 { "bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3079 { "bnsctrl", XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
3080 { "bnsctrl-",XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3081 { "bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3082 { "bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3083 { "bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3084 { "bnuctr",  XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
3085 { "bnuctr-", XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3086 { "bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3087 { "bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3088 { "bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3089 { "bnuctrl", XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
3090 { "bnuctrl-",XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3091 { "bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3092 { "bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3093 { "bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3094 { "btctr",   XLO(19,BOT,528,0),  XLBOBB_MASK, PPCCOM,   { BI } },
3095 { "btctr-",  XLO(19,BOT,528,0),  XLBOBB_MASK, NOPOWER4, { BI } },
3096 { "btctr+",  XLO(19,BOTP,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
3097 { "btctr-",  XLO(19,BOTM4,528,0), XLBOBB_MASK, POWER4, { BI } },
3098 { "btctr+",  XLO(19,BOTP4,528,0), XLBOBB_MASK, POWER4, { BI } },
3099 { "btctrl",  XLO(19,BOT,528,1),  XLBOBB_MASK, PPCCOM,   { BI } },
3100 { "btctrl-", XLO(19,BOT,528,1),  XLBOBB_MASK, NOPOWER4, { BI } },
3101 { "btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
3102 { "btctrl-", XLO(19,BOTM4,528,1), XLBOBB_MASK, POWER4, { BI } },
3103 { "btctrl+", XLO(19,BOTP4,528,1), XLBOBB_MASK, POWER4, { BI } },
3104 { "bfctr",   XLO(19,BOF,528,0),  XLBOBB_MASK, PPCCOM,   { BI } },
3105 { "bfctr-",  XLO(19,BOF,528,0),  XLBOBB_MASK, NOPOWER4, { BI } },
3106 { "bfctr+",  XLO(19,BOFP,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
3107 { "bfctr-",  XLO(19,BOFM4,528,0), XLBOBB_MASK, POWER4, { BI } },
3108 { "bfctr+",  XLO(19,BOFP4,528,0), XLBOBB_MASK, POWER4, { BI } },
3109 { "bfctrl",  XLO(19,BOF,528,1),  XLBOBB_MASK, PPCCOM,   { BI } },
3110 { "bfctrl-", XLO(19,BOF,528,1),  XLBOBB_MASK, NOPOWER4, { BI } },
3111 { "bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
3112 { "bfctrl-", XLO(19,BOFM4,528,1), XLBOBB_MASK, POWER4, { BI } },
3113 { "bfctrl+", XLO(19,BOFP4,528,1), XLBOBB_MASK, POWER4, { BI } },
3114 { "bcctr",   XLLK(19,528,0),     XLYBB_MASK,  PPCCOM,   { BO, BI } },
3115 { "bcctr-",  XLYLK(19,528,0,0),  XLYBB_MASK,  PPCCOM,   { BOE, BI } },
3116 { "bcctr+",  XLYLK(19,528,1,0),  XLYBB_MASK,  PPCCOM,   { BOE, BI } },
3117 { "bcctrl",  XLLK(19,528,1),     XLYBB_MASK,  PPCCOM,   { BO, BI } },
3118 { "bcctrl-", XLYLK(19,528,0,1),  XLYBB_MASK,  PPCCOM,   { BOE, BI } },
3119 { "bcctrl+", XLYLK(19,528,1,1),  XLYBB_MASK,  PPCCOM,   { BOE, BI } },
3120 { "bcc",     XLLK(19,528,0),     XLBB_MASK,   PWRCOM,   { BO, BI } },
3121 { "bccl",    XLLK(19,528,1),     XLBB_MASK,   PWRCOM,   { BO, BI } },
3122 { "bcctre",  XLLK(19,529,0),     XLYBB_MASK,  BOOKE64,  { BO, BI } },
3123 { "bcctrel", XLLK(19,529,1),     XLYBB_MASK,  BOOKE64,  { BO, BI } },
3124
3125 { "rlwimi",  M(20,0),   M_MASK,         PPCCOM,         { RA,RS,SH,MBE,ME } },
3126 { "rlimi",   M(20,0),   M_MASK,         PWRCOM,         { RA,RS,SH,MBE,ME } },
3127
3128 { "rlwimi.", M(20,1),   M_MASK,         PPCCOM,         { RA,RS,SH,MBE,ME } },
3129 { "rlimi.",  M(20,1),   M_MASK,         PWRCOM,         { RA,RS,SH,MBE,ME } },
3130
3131 { "rotlwi",  MME(21,31,0), MMBME_MASK,  PPCCOM,         { RA, RS, SH } },
3132 { "clrlwi",  MME(21,31,0), MSHME_MASK,  PPCCOM,         { RA, RS, MB } },
3133 { "rlwinm",  M(21,0),   M_MASK,         PPCCOM,         { RA,RS,SH,MBE,ME } },
3134 { "rlinm",   M(21,0),   M_MASK,         PWRCOM,         { RA,RS,SH,MBE,ME } },
3135 { "rotlwi.", MME(21,31,1), MMBME_MASK,  PPCCOM,         { RA,RS,SH } },
3136 { "clrlwi.", MME(21,31,1), MSHME_MASK,  PPCCOM,         { RA, RS, MB } },
3137 { "rlwinm.", M(21,1),   M_MASK,         PPCCOM,         { RA,RS,SH,MBE,ME } },
3138 { "rlinm.",  M(21,1),   M_MASK,         PWRCOM,         { RA,RS,SH,MBE,ME } },
3139
3140 { "rlmi",    M(22,0),   M_MASK,         M601,           { RA,RS,RB,MBE,ME } },
3141 { "rlmi.",   M(22,1),   M_MASK,         M601,           { RA,RS,RB,MBE,ME } },
3142
3143 { "be",      B(22,0,0), B_MASK,         BOOKE64,        { LI } },
3144 { "bel",     B(22,0,1), B_MASK,         BOOKE64,        { LI } },
3145 { "bea",     B(22,1,0), B_MASK,         BOOKE64,        { LIA } },
3146 { "bela",    B(22,1,1), B_MASK,         BOOKE64,        { LIA } },
3147
3148 { "rotlw",   MME(23,31,0), MMBME_MASK,  PPCCOM,         { RA, RS, RB } },
3149 { "rlwnm",   M(23,0),   M_MASK,         PPCCOM,         { RA,RS,RB,MBE,ME } },
3150 { "rlnm",    M(23,0),   M_MASK,         PWRCOM,         { RA,RS,RB,MBE,ME } },
3151 { "rotlw.",  MME(23,31,1), MMBME_MASK,  PPCCOM,         { RA, RS, RB } },
3152 { "rlwnm.",  M(23,1),   M_MASK,         PPCCOM,         { RA,RS,RB,MBE,ME } },
3153 { "rlnm.",   M(23,1),   M_MASK,         PWRCOM,         { RA,RS,RB,MBE,ME } },
3154
3155 { "nop",     OP(24),    0xffffffff,     PPCCOM,         { 0 } },
3156 { "ori",     OP(24),    OP_MASK,        PPCCOM,         { RA, RS, UI } },
3157 { "oril",    OP(24),    OP_MASK,        PWRCOM,         { RA, RS, UI } },
3158
3159 { "oris",    OP(25),    OP_MASK,        PPCCOM,         { RA, RS, UI } },
3160 { "oriu",    OP(25),    OP_MASK,        PWRCOM,         { RA, RS, UI } },
3161
3162 { "xori",    OP(26),    OP_MASK,        PPCCOM,         { RA, RS, UI } },
3163 { "xoril",   OP(26),    OP_MASK,        PWRCOM,         { RA, RS, UI } },
3164
3165 { "xoris",   OP(27),    OP_MASK,        PPCCOM,         { RA, RS, UI } },
3166 { "xoriu",   OP(27),    OP_MASK,        PWRCOM,         { RA, RS, UI } },
3167
3168 { "andi.",   OP(28),    OP_MASK,        PPCCOM,         { RA, RS, UI } },
3169 { "andil.",  OP(28),    OP_MASK,        PWRCOM,         { RA, RS, UI } },
3170
3171 { "andis.",  OP(29),    OP_MASK,        PPCCOM,         { RA, RS, UI } },
3172 { "andiu.",  OP(29),    OP_MASK,        PWRCOM,         { RA, RS, UI } },
3173
3174 { "rotldi",  MD(30,0,0), MDMB_MASK,     PPC64,          { RA, RS, SH6 } },
3175 { "clrldi",  MD(30,0,0), MDSH_MASK,     PPC64,          { RA, RS, MB6 } },
3176 { "rldicl",  MD(30,0,0), MD_MASK,       PPC64,          { RA, RS, SH6, MB6 } },
3177 { "rotldi.", MD(30,0,1), MDMB_MASK,     PPC64,          { RA, RS, SH6 } },
3178 { "clrldi.", MD(30,0,1), MDSH_MASK,     PPC64,          { RA, RS, MB6 } },
3179 { "rldicl.", MD(30,0,1), MD_MASK,       PPC64,          { RA, RS, SH6, MB6 } },
3180
3181 { "rldicr",  MD(30,1,0), MD_MASK,       PPC64,          { RA, RS, SH6, ME6 } },
3182 { "rldicr.", MD(30,1,1), MD_MASK,       PPC64,          { RA, RS, SH6, ME6 } },
3183
3184 { "rldic",   MD(30,2,0), MD_MASK,       PPC64,          { RA, RS, SH6, MB6 } },
3185 { "rldic.",  MD(30,2,1), MD_MASK,       PPC64,          { RA, RS, SH6, MB6 } },
3186
3187 { "rldimi",  MD(30,3,0), MD_MASK,       PPC64,          { RA, RS, SH6, MB6 } },
3188 { "rldimi.", MD(30,3,1), MD_MASK,       PPC64,          { RA, RS, SH6, MB6 } },
3189
3190 { "rotld",   MDS(30,8,0), MDSMB_MASK,   PPC64,          { RA, RS, RB } },
3191 { "rldcl",   MDS(30,8,0), MDS_MASK,     PPC64,          { RA, RS, RB, MB6 } },
3192 { "rotld.",  MDS(30,8,1), MDSMB_MASK,   PPC64,          { RA, RS, RB } },
3193 { "rldcl.",  MDS(30,8,1), MDS_MASK,     PPC64,          { RA, RS, RB, MB6 } },
3194
3195 { "rldcr",   MDS(30,9,0), MDS_MASK,     PPC64,          { RA, RS, RB, ME6 } },
3196 { "rldcr.",  MDS(30,9,1), MDS_MASK,     PPC64,          { RA, RS, RB, ME6 } },
3197
3198 { "cmpw",    XCMPL(31,0,0), XCMPL_MASK, PPCCOM,         { OBF, RA, RB } },
3199 { "cmpd",    XCMPL(31,0,1), XCMPL_MASK, PPC64,          { OBF, RA, RB } },
3200 { "cmp",     X(31,0),   XCMP_MASK,      PPCONLY,        { BF, L, RA, RB } },
3201 { "cmp",     X(31,0),   XCMPL_MASK,     PWRCOM,         { BF, RA, RB } },
3202
3203 { "twlgt",   XTO(31,4,TOLGT), XTO_MASK, PPCCOM,         { RA, RB } },
3204 { "tlgt",    XTO(31,4,TOLGT), XTO_MASK, PWRCOM,         { RA, RB } },
3205 { "twllt",   XTO(31,4,TOLLT), XTO_MASK, PPCCOM,         { RA, RB } },
3206 { "tllt",    XTO(31,4,TOLLT), XTO_MASK, PWRCOM,         { RA, RB } },
3207 { "tweq",    XTO(31,4,TOEQ), XTO_MASK,  PPCCOM,         { RA, RB } },
3208 { "teq",     XTO(31,4,TOEQ), XTO_MASK,  PWRCOM,         { RA, RB } },
3209 { "twlge",   XTO(31,4,TOLGE), XTO_MASK, PPCCOM,         { RA, RB } },
3210 { "tlge",    XTO(31,4,TOLGE), XTO_MASK, PWRCOM,         { RA, RB } },
3211 { "twlnl",   XTO(31,4,TOLNL), XTO_MASK, PPCCOM,         { RA, RB } },
3212 { "tlnl",    XTO(31,4,TOLNL), XTO_MASK, PWRCOM,         { RA, RB } },
3213 { "twlle",   XTO(31,4,TOLLE), XTO_MASK, PPCCOM,         { RA, RB } },
3214 { "tlle",    XTO(31,4,TOLLE), XTO_MASK, PWRCOM,         { RA, RB } },
3215 { "twlng",   XTO(31,4,TOLNG), XTO_MASK, PPCCOM,         { RA, RB } },
3216 { "tlng",    XTO(31,4,TOLNG), XTO_MASK, PWRCOM,         { RA, RB } },
3217 { "twgt",    XTO(31,4,TOGT), XTO_MASK,  PPCCOM,         { RA, RB } },
3218 { "tgt",     XTO(31,4,TOGT), XTO_MASK,  PWRCOM,         { RA, RB } },
3219 { "twge",    XTO(31,4,TOGE), XTO_MASK,  PPCCOM,         { RA, RB } },
3220 { "tge",     XTO(31,4,TOGE), XTO_MASK,  PWRCOM,         { RA, RB } },
3221 { "twnl",    XTO(31,4,TONL), XTO_MASK,  PPCCOM,         { RA, RB } },
3222 { "tnl",     XTO(31,4,TONL), XTO_MASK,  PWRCOM,         { RA, RB } },
3223 { "twlt",    XTO(31,4,TOLT), XTO_MASK,  PPCCOM,         { RA, RB } },
3224 { "tlt",     XTO(31,4,TOLT), XTO_MASK,  PWRCOM,         { RA, RB } },
3225 { "twle",    XTO(31,4,TOLE), XTO_MASK,  PPCCOM,         { RA, RB } },
3226 { "tle",     XTO(31,4,TOLE), XTO_MASK,  PWRCOM,         { RA, RB } },
3227 { "twng",    XTO(31,4,TONG), XTO_MASK,  PPCCOM,         { RA, RB } },
3228 { "tng",     XTO(31,4,TONG), XTO_MASK,  PWRCOM,         { RA, RB } },
3229 { "twne",    XTO(31,4,TONE), XTO_MASK,  PPCCOM,         { RA, RB } },
3230 { "tne",     XTO(31,4,TONE), XTO_MASK,  PWRCOM,         { RA, RB } },
3231 { "trap",    XTO(31,4,TOU), 0xffffffff, PPCCOM,         { 0 } },
3232 { "tw",      X(31,4),   X_MASK,         PPCCOM,         { TO, RA, RB } },
3233 { "t",       X(31,4),   X_MASK,         PWRCOM,         { TO, RA, RB } },
3234
3235 { "subfc",   XO(31,8,0,0), XO_MASK,     PPCCOM,         { RT, RA, RB } },
3236 { "sf",      XO(31,8,0,0), XO_MASK,     PWRCOM,         { RT, RA, RB } },
3237 { "subc",    XO(31,8,0,0), XO_MASK,     PPC,            { RT, RB, RA } },
3238 { "subfc.",  XO(31,8,0,1), XO_MASK,     PPCCOM,         { RT, RA, RB } },
3239 { "sf.",     XO(31,8,0,1), XO_MASK,     PWRCOM,         { RT, RA, RB } },
3240 { "subc.",   XO(31,8,0,1), XO_MASK,     PPCCOM,         { RT, RB, RA } },
3241 { "subfco",  XO(31,8,1,0), XO_MASK,     PPCCOM,         { RT, RA, RB } },
3242 { "sfo",     XO(31,8,1,0), XO_MASK,     PWRCOM,         { RT, RA, RB } },
3243 { "subco",   XO(31,8,1,0), XO_MASK,     PPC,            { RT, RB, RA } },
3244 { "subfco.", XO(31,8,1,1), XO_MASK,     PPCCOM,         { RT, RA, RB } },
3245 { "sfo.",    XO(31,8,1,1), XO_MASK,     PWRCOM,         { RT, RA, RB } },
3246 { "subco.",  XO(31,8,1,1), XO_MASK,     PPC,            { RT, RB, RA } },
3247
3248 { "mulhdu",  XO(31,9,0,0), XO_MASK,     PPC64,          { RT, RA, RB } },
3249 { "mulhdu.", XO(31,9,0,1), XO_MASK,     PPC64,          { RT, RA, RB } },
3250
3251 { "addc",    XO(31,10,0,0), XO_MASK,    PPCCOM,         { RT, RA, RB } },
3252 { "a",       XO(31,10,0,0), XO_MASK,    PWRCOM,         { RT, RA, RB } },
3253 { "addc.",   XO(31,10,0,1), XO_MASK,    PPCCOM,         { RT, RA, RB } },
3254 { "a.",      XO(31,10,0,1), XO_MASK,    PWRCOM,         { RT, RA, RB } },
3255 { "addco",   XO(31,10,1,0), XO_MASK,    PPCCOM,         { RT, RA, RB } },
3256 { "ao",      XO(31,10,1,0), XO_MASK,    PWRCOM,         { RT, RA, RB } },
3257 { "addco.",  XO(31,10,1,1), XO_MASK,    PPCCOM,         { RT, RA, RB } },
3258 { "ao.",     XO(31,10,1,1), XO_MASK,    PWRCOM,         { RT, RA, RB } },
3259
3260 { "mulhwu",  XO(31,11,0,0), XO_MASK,    PPC,            { RT, RA, RB } },
3261 { "mulhwu.", XO(31,11,0,1), XO_MASK,    PPC,            { RT, RA, RB } },
3262
3263 { "isellt",  X(31,15),      X_MASK,     PPCISEL,        { RT, RA, RB } },
3264 { "iselgt",  X(31,47),      X_MASK,     PPCISEL,        { RT, RA, RB } },
3265 { "iseleq",  X(31,79),      X_MASK,     PPCISEL,        { RT, RA, RB } },
3266 { "isel",    XISEL(31,15),  XISEL_MASK, PPCISEL,        { RT, RA, RB, CRB } },
3267
3268 { "mfcr",    X(31,19),  XRARB_MASK,     COM,            { RT } },
3269
3270 { "lwarx",   X(31,20),  X_MASK,         PPC,            { RT, RA, RB } },
3271
3272 { "ldx",     X(31,21),  X_MASK,         PPC64,          { RT, RA, RB } },
3273
3274 { "icbt",    X(31,22),  X_MASK,         BOOKE,          { CT, RA, RB } },
3275
3276 { "lwzx",    X(31,23),  X_MASK,         PPCCOM,         { RT, RA, RB } },
3277 { "lx",      X(31,23),  X_MASK,         PWRCOM,         { RT, RA, RB } },
3278
3279 { "slw",     XRC(31,24,0), X_MASK,      PPCCOM,         { RA, RS, RB } },
3280 { "sl",      XRC(31,24,0), X_MASK,      PWRCOM,         { RA, RS, RB } },
3281 { "slw.",    XRC(31,24,1), X_MASK,      PPCCOM,         { RA, RS, RB } },
3282 { "sl.",     XRC(31,24,1), X_MASK,      PWRCOM,         { RA, RS, RB } },
3283
3284 { "cntlzw",  XRC(31,26,0), XRB_MASK,    PPCCOM,         { RA, RS } },
3285 { "cntlz",   XRC(31,26,0), XRB_MASK,    PWRCOM,         { RA, RS } },
3286 { "cntlzw.", XRC(31,26,1), XRB_MASK,    PPCCOM,         { RA, RS } },
3287 { "cntlz.",  XRC(31,26,1), XRB_MASK,    PWRCOM,         { RA, RS } },
3288
3289 { "sld",     XRC(31,27,0), X_MASK,      PPC64,          { RA, RS, RB } },
3290 { "sld.",    XRC(31,27,1), X_MASK,      PPC64,          { RA, RS, RB } },
3291
3292 { "and",     XRC(31,28,0), X_MASK,      COM,            { RA, RS, RB } },
3293 { "and.",    XRC(31,28,1), X_MASK,      COM,            { RA, RS, RB } },
3294
3295 { "maskg",   XRC(31,29,0), X_MASK,      M601,           { RA, RS, RB } },
3296 { "maskg.",  XRC(31,29,1), X_MASK,      M601,           { RA, RS, RB } },
3297
3298 { "icbte",   X(31,30),  X_MASK,         BOOKE64,        { CT, RA, RB } },
3299
3300 { "lwzxe",   X(31,31),  X_MASK,         BOOKE64,        { RT, RA, RB } },
3301
3302 { "cmplw",   XCMPL(31,32,0), XCMPL_MASK, PPCCOM,        { OBF, RA, RB } },
3303 { "cmpld",   XCMPL(31,32,1), XCMPL_MASK, PPC64,         { OBF, RA, RB } },
3304 { "cmpl",    X(31,32),  XCMP_MASK,       PPCONLY,       { BF, L, RA, RB } },
3305 { "cmpl",    X(31,32),  XCMPL_MASK,      PWRCOM,        { BF, RA, RB } },
3306
3307 { "subf",    XO(31,40,0,0), XO_MASK,    PPC,            { RT, RA, RB } },
3308 { "sub",     XO(31,40,0,0), XO_MASK,    PPC,            { RT, RB, RA } },
3309 { "subf.",   XO(31,40,0,1), XO_MASK,    PPC,            { RT, RA, RB } },
3310 { "sub.",    XO(31,40,0,1), XO_MASK,    PPC,            { RT, RB, RA } },
3311 { "subfo",   XO(31,40,1,0), XO_MASK,    PPC,            { RT, RA, RB } },
3312 { "subo",    XO(31,40,1,0), XO_MASK,    PPC,            { RT, RB, RA } },
3313 { "subfo.",  XO(31,40,1,1), XO_MASK,    PPC,            { RT, RA, RB } },
3314 { "subo.",   XO(31,40,1,1), XO_MASK,    PPC,            { RT, RB, RA } },
3315
3316 { "ldux",    X(31,53),  X_MASK,         PPC64,          { RT, RAL, RB } },
3317
3318 { "dcbst",   X(31,54),  XRT_MASK,       PPC,            { RA, RB } },
3319
3320 { "lwzux",   X(31,55),  X_MASK,         PPCCOM,         { RT, RAL, RB } },
3321 { "lux",     X(31,55),  X_MASK,         PWRCOM,         { RT, RA, RB } },
3322
3323 { "dcbste",  X(31,62),  XRT_MASK,       BOOKE64,        { RA, RB } },
3324
3325 { "lwzuxe",  X(31,63),  X_MASK,         BOOKE64,        { RT, RAL, RB } },
3326
3327 { "cntlzd",  XRC(31,58,0), XRB_MASK,    PPC64,          { RA, RS } },
3328 { "cntlzd.", XRC(31,58,1), XRB_MASK,    PPC64,          { RA, RS } },
3329
3330 { "andc",    XRC(31,60,0), X_MASK,      COM,            { RA, RS, RB } },
3331 { "andc.",   XRC(31,60,1), X_MASK,      COM,            { RA, RS, RB } },
3332
3333 { "tdlgt",   XTO(31,68,TOLGT), XTO_MASK, PPC64,         { RA, RB } },
3334 { "tdllt",   XTO(31,68,TOLLT), XTO_MASK, PPC64,         { RA, RB } },
3335 { "tdeq",    XTO(31,68,TOEQ), XTO_MASK,  PPC64,         { RA, RB } },
3336 { "tdlge",   XTO(31,68,TOLGE), XTO_MASK, PPC64,         { RA, RB } },
3337 { "tdlnl",   XTO(31,68,TOLNL), XTO_MASK, PPC64,         { RA, RB } },
3338 { "tdlle",   XTO(31,68,TOLLE), XTO_MASK, PPC64,         { RA, RB } },
3339 { "tdlng",   XTO(31,68,TOLNG), XTO_MASK, PPC64,         { RA, RB } },
3340 { "tdgt",    XTO(31,68,TOGT), XTO_MASK,  PPC64,         { RA, RB } },
3341 { "tdge",    XTO(31,68,TOGE), XTO_MASK,  PPC64,         { RA, RB } },
3342 { "tdnl",    XTO(31,68,TONL), XTO_MASK,  PPC64,         { RA, RB } },
3343 { "tdlt",    XTO(31,68,TOLT), XTO_MASK,  PPC64,         { RA, RB } },
3344 { "tdle",    XTO(31,68,TOLE), XTO_MASK,  PPC64,         { RA, RB } },
3345 { "tdng",    XTO(31,68,TONG), XTO_MASK,  PPC64,         { RA, RB } },
3346 { "tdne",    XTO(31,68,TONE), XTO_MASK,  PPC64,         { RA, RB } },
3347 { "td",      X(31,68),  X_MASK,          PPC64,         { TO, RA, RB } },
3348
3349 { "mulhd",   XO(31,73,0,0), XO_MASK,     PPC64,         { RT, RA, RB } },
3350 { "mulhd.",  XO(31,73,0,1), XO_MASK,     PPC64,         { RT, RA, RB } },
3351
3352 { "mulhw",   XO(31,75,0,0), XO_MASK,    PPC,            { RT, RA, RB } },
3353 { "mulhw.",  XO(31,75,0,1), XO_MASK,    PPC,            { RT, RA, RB } },
3354
3355 { "mtsrd",   X(31,82),  XRB_MASK|(1<<20), PPC64,        { SR, RS } },
3356
3357 { "mfmsr",   X(31,83),  XRARB_MASK,     COM,            { RT } },
3358
3359 { "ldarx",   X(31,84),  X_MASK,         PPC64,          { RT, RA, RB } },
3360
3361 { "dcbf",    X(31,86),  XRT_MASK,       PPC,            { RA, RB } },
3362
3363 { "lbzx",    X(31,87),  X_MASK,         COM,            { RT, RA, RB } },
3364
3365 { "dcbfe",   X(31,94),  XRT_MASK,       BOOKE64,        { RA, RB } },
3366
3367 { "lbzxe",   X(31,95),  X_MASK,         BOOKE64,        { RT, RA, RB } },
3368
3369 { "neg",     XO(31,104,0,0), XORB_MASK, COM,            { RT, RA } },
3370 { "neg.",    XO(31,104,0,1), XORB_MASK, COM,            { RT, RA } },
3371 { "nego",    XO(31,104,1,0), XORB_MASK, COM,            { RT, RA } },
3372 { "nego.",   XO(31,104,1,1), XORB_MASK, COM,            { RT, RA } },
3373
3374 { "mul",     XO(31,107,0,0), XO_MASK,   M601,           { RT, RA, RB } },
3375 { "mul.",    XO(31,107,0,1), XO_MASK,   M601,           { RT, RA, RB } },
3376 { "mulo",    XO(31,107,1,0), XO_MASK,   M601,           { RT, RA, RB } },
3377 { "mulo.",   XO(31,107,1,1), XO_MASK,   M601,           { RT, RA, RB } },
3378
3379 { "mtsrdin", X(31,114), XRA_MASK,       PPC64,          { RS, RB } },
3380
3381 { "clf",     X(31,118), XTO_MASK,       POWER,          { RA, RB } },
3382
3383 { "lbzux",   X(31,119), X_MASK,         COM,            { RT, RAL, RB } },
3384
3385 { "not",     XRC(31,124,0), X_MASK,     COM,            { RA, RS, RBS } },
3386 { "nor",     XRC(31,124,0), X_MASK,     COM,            { RA, RS, RB } },
3387 { "not.",    XRC(31,124,1), X_MASK,     COM,            { RA, RS, RBS } },
3388 { "nor.",    XRC(31,124,1), X_MASK,     COM,            { RA, RS, RB } },
3389
3390 { "lwarxe",  X(31,126), X_MASK,         BOOKE64,        { RT, RA, RB } },
3391
3392 { "lbzuxe",  X(31,127), X_MASK,         BOOKE64,        { RT, RAL, RB } },
3393
3394 { "wrtee",   X(31,131), XRARB_MASK,     PPC403,         { RS } },
3395 { "wrtee",   X(31,131), XRARB_MASK,     BOOKE,          { RS } },
3396
3397 { "dcbtstls",X(31,134), X_MASK,         PPCCHLK,        { CT, RA, RB }},
3398
3399 { "subfe",   XO(31,136,0,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3400 { "sfe",     XO(31,136,0,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3401 { "subfe.",  XO(31,136,0,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3402 { "sfe.",    XO(31,136,0,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3403 { "subfeo",  XO(31,136,1,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3404 { "sfeo",    XO(31,136,1,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3405 { "subfeo.", XO(31,136,1,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3406 { "sfeo.",   XO(31,136,1,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3407
3408 { "adde",    XO(31,138,0,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3409 { "ae",      XO(31,138,0,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3410 { "adde.",   XO(31,138,0,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3411 { "ae.",     XO(31,138,0,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3412 { "addeo",   XO(31,138,1,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3413 { "aeo",     XO(31,138,1,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3414 { "addeo.",  XO(31,138,1,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3415 { "aeo.",    XO(31,138,1,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3416
3417 { "dcbtstlse",X(31,142),X_MASK,         PPCCHLK64,      { CT, RA, RB }},
3418
3419 { "mtcr",    XFXM(31,144,0xff), XFXFXM_MASK|FXM_MASK, COM,      { RS }},
3420 { "mtcrf",   X(31,144), XFXFXM_MASK,    COM,            { FXM, RS } },
3421
3422 { "mtmsr",   X(31,146), XRARB_MASK,     COM,            { RS } },
3423
3424 { "stdx",    X(31,149), X_MASK,         PPC64,          { RS, RA, RB } },
3425
3426 { "stwcx.",  XRC(31,150,1), X_MASK,     PPC,            { RS, RA, RB } },
3427
3428 { "stwx",    X(31,151), X_MASK,         PPCCOM,         { RS, RA, RB } },
3429 { "stx",     X(31,151), X_MASK,         PWRCOM,         { RS, RA, RB } },
3430
3431 { "stwcxe.", XRC(31,158,1), X_MASK,     BOOKE64,        { RS, RA, RB } },
3432
3433 { "stwxe",   X(31,159), X_MASK,         BOOKE64,        { RS, RA, RB } },
3434
3435 { "slq",     XRC(31,152,0), X_MASK,     M601,           { RA, RS, RB } },
3436 { "slq.",    XRC(31,152,1), X_MASK,     M601,           { RA, RS, RB } },
3437
3438 { "sle",     XRC(31,153,0), X_MASK,     M601,           { RA, RS, RB } },
3439 { "sle.",    XRC(31,153,1), X_MASK,     M601,           { RA, RS, RB } },
3440
3441 { "wrteei",  X(31,163), XE_MASK,        PPC403,         { E } },
3442 { "wrteei",  X(31,163), XE_MASK,        BOOKE,          { E } },
3443
3444 { "dcbtls",  X(31,166), X_MASK,         PPCCHLK,        { CT, RA, RB }},
3445 { "dcbtlse", X(31,174), X_MASK,         PPCCHLK64,      { CT, RA, RB }},
3446
3447 { "mtmsrd",  X(31,178), XRLARB_MASK,    PPC64,          { RS, MTMSRD_L } },
3448
3449 { "stdux",   X(31,181), X_MASK,         PPC64,          { RS, RAS, RB } },
3450
3451 { "stwux",   X(31,183), X_MASK,         PPCCOM,         { RS, RAS, RB } },
3452 { "stux",    X(31,183), X_MASK,         PWRCOM,         { RS, RA, RB } },
3453
3454 { "sliq",    XRC(31,184,0), X_MASK,     M601,           { RA, RS, SH } },
3455 { "sliq.",   XRC(31,184,1), X_MASK,     M601,           { RA, RS, SH } },
3456
3457 { "stwuxe",  X(31,191), X_MASK,         BOOKE64,        { RS, RAS, RB } },
3458
3459 { "subfze",  XO(31,200,0,0), XORB_MASK, PPCCOM,         { RT, RA } },
3460 { "sfze",    XO(31,200,0,0), XORB_MASK, PWRCOM,         { RT, RA } },
3461 { "subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM,         { RT, RA } },
3462 { "sfze.",   XO(31,200,0,1), XORB_MASK, PWRCOM,         { RT, RA } },
3463 { "subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM,         { RT, RA } },
3464 { "sfzeo",   XO(31,200,1,0), XORB_MASK, PWRCOM,         { RT, RA } },
3465 { "subfzeo.",XO(31,200,1,1), XORB_MASK, PPCCOM,         { RT, RA } },
3466 { "sfzeo.",  XO(31,200,1,1), XORB_MASK, PWRCOM,         { RT, RA } },
3467
3468 { "addze",   XO(31,202,0,0), XORB_MASK, PPCCOM,         { RT, RA } },
3469 { "aze",     XO(31,202,0,0), XORB_MASK, PWRCOM,         { RT, RA } },
3470 { "addze.",  XO(31,202,0,1), XORB_MASK, PPCCOM,         { RT, RA } },
3471 { "aze.",    XO(31,202,0,1), XORB_MASK, PWRCOM,         { RT, RA } },
3472 { "addzeo",  XO(31,202,1,0), XORB_MASK, PPCCOM,         { RT, RA } },
3473 { "azeo",    XO(31,202,1,0), XORB_MASK, PWRCOM,         { RT, RA } },
3474 { "addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM,         { RT, RA } },
3475 { "azeo.",   XO(31,202,1,1), XORB_MASK, PWRCOM,         { RT, RA } },
3476
3477 { "mtsr",    X(31,210), XRB_MASK|(1<<20), COM32,        { SR, RS } },
3478
3479 { "stdcx.",  XRC(31,214,1), X_MASK,     PPC64,          { RS, RA, RB } },
3480
3481 { "stbx",    X(31,215), X_MASK,         COM,            { RS, RA, RB } },
3482
3483 { "sllq",    XRC(31,216,0), X_MASK,     M601,           { RA, RS, RB } },
3484 { "sllq.",   XRC(31,216,1), X_MASK,     M601,           { RA, RS, RB } },
3485
3486 { "sleq",    XRC(31,217,0), X_MASK,     M601,           { RA, RS, RB } },
3487 { "sleq.",   XRC(31,217,1), X_MASK,     M601,           { RA, RS, RB } },
3488
3489 { "stbxe",   X(31,223), X_MASK,         BOOKE64,        { RS, RA, RB } },
3490
3491 { "icblc",   X(31,230), X_MASK,         PPCCHLK,        { CT, RA, RB }},
3492
3493 { "subfme",  XO(31,232,0,0), XORB_MASK, PPCCOM,         { RT, RA } },
3494 { "sfme",    XO(31,232,0,0), XORB_MASK, PWRCOM,         { RT, RA } },
3495 { "subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM,         { RT, RA } },
3496 { "sfme.",   XO(31,232,0,1), XORB_MASK, PWRCOM,         { RT, RA } },
3497 { "subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM,         { RT, RA } },
3498 { "sfmeo",   XO(31,232,1,0), XORB_MASK, PWRCOM,         { RT, RA } },
3499 { "subfmeo.",XO(31,232,1,1), XORB_MASK, PPCCOM,         { RT, RA } },
3500 { "sfmeo.",  XO(31,232,1,1), XORB_MASK, PWRCOM,         { RT, RA } },
3501
3502 { "mulld",   XO(31,233,0,0), XO_MASK,   PPC64,          { RT, RA, RB } },
3503 { "mulld.",  XO(31,233,0,1), XO_MASK,   PPC64,          { RT, RA, RB } },
3504 { "mulldo",  XO(31,233,1,0), XO_MASK,   PPC64,          { RT, RA, RB } },
3505 { "mulldo.", XO(31,233,1,1), XO_MASK,   PPC64,          { RT, RA, RB } },
3506
3507 { "addme",   XO(31,234,0,0), XORB_MASK, PPCCOM,         { RT, RA } },
3508 { "ame",     XO(31,234,0,0), XORB_MASK, PWRCOM,         { RT, RA } },
3509 { "addme.",  XO(31,234,0,1), XORB_MASK, PPCCOM,         { RT, RA } },
3510 { "ame.",    XO(31,234,0,1), XORB_MASK, PWRCOM,         { RT, RA } },
3511 { "addmeo",  XO(31,234,1,0), XORB_MASK, PPCCOM,         { RT, RA } },
3512 { "ameo",    XO(31,234,1,0), XORB_MASK, PWRCOM,         { RT, RA } },
3513 { "addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM,         { RT, RA } },
3514 { "ameo.",   XO(31,234,1,1), XORB_MASK, PWRCOM,         { RT, RA } },
3515
3516 { "mullw",   XO(31,235,0,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3517 { "muls",    XO(31,235,0,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3518 { "mullw.",  XO(31,235,0,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3519 { "muls.",   XO(31,235,0,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3520 { "mullwo",  XO(31,235,1,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3521 { "mulso",   XO(31,235,1,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3522 { "mullwo.", XO(31,235,1,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3523 { "mulso.",  XO(31,235,1,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3524
3525 { "icblce",  X(31,238), X_MASK,         PPCCHLK64,      { CT, RA, RB }},
3526 { "mtsrin",  X(31,242), XRA_MASK,       PPC32,          { RS, RB } },
3527 { "mtsri",   X(31,242), XRA_MASK,       POWER32,        { RS, RB } },
3528
3529 { "dcbtst",  X(31,246), XRT_MASK,       PPC,            { CT, RA, RB } },
3530
3531 { "stbux",   X(31,247), X_MASK,         COM,            { RS, RAS, RB } },
3532
3533 { "slliq",   XRC(31,248,0), X_MASK,     M601,           { RA, RS, SH } },
3534 { "slliq.",  XRC(31,248,1), X_MASK,     M601,           { RA, RS, SH } },
3535
3536 { "dcbtste", X(31,253), X_MASK,         BOOKE64,        { CT, RA, RB } },
3537
3538 { "stbuxe",  X(31,255), X_MASK,         BOOKE64,        { RS, RAS, RB } },
3539
3540 { "mfdcrx",  X(31,259), X_MASK,         BOOKE,          { RS, RA } },
3541
3542 { "icbt",    X(31,262), XRT_MASK,       PPC403,         { RA, RB } },
3543
3544 { "doz",     XO(31,264,0,0), XO_MASK,   M601,           { RT, RA, RB } },
3545 { "doz.",    XO(31,264,0,1), XO_MASK,   M601,           { RT, RA, RB } },
3546 { "dozo",    XO(31,264,1,0), XO_MASK,   M601,           { RT, RA, RB } },
3547 { "dozo.",   XO(31,264,1,1), XO_MASK,   M601,           { RT, RA, RB } },
3548
3549 { "add",     XO(31,266,0,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3550 { "cax",     XO(31,266,0,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3551 { "add.",    XO(31,266,0,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3552 { "cax.",    XO(31,266,0,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3553 { "addo",    XO(31,266,1,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3554 { "caxo",    XO(31,266,1,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3555 { "addo.",   XO(31,266,1,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3556 { "caxo.",   XO(31,266,1,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3557
3558 { "tlbiel",  X(31,274), XRTRA_MASK,     POWER4,         { RB } },
3559
3560 { "mfapidi", X(31,275), X_MASK,         BOOKE,          { RT, RA } },
3561
3562 { "lscbx",   XRC(31,277,0), X_MASK,     M601,           { RT, RA, RB } },
3563 { "lscbx.",  XRC(31,277,1), X_MASK,     M601,           { RT, RA, RB } },
3564
3565 { "dcbt",    X(31,278), XRT_MASK,       PPC,            { CT, RA, RB } },
3566
3567 { "lhzx",    X(31,279), X_MASK,         COM,            { RT, RA, RB } },
3568
3569 { "eqv",     XRC(31,284,0), X_MASK,     COM,            { RA, RS, RB } },
3570 { "eqv.",    XRC(31,284,1), X_MASK,     COM,            { RA, RS, RB } },
3571
3572 { "dcbte",   X(31,286), X_MASK,         BOOKE64,        { CT, RA, RB } },
3573
3574 { "lhzxe",   X(31,287), X_MASK,         BOOKE64,        { RT, RA, RB } },
3575
3576 { "tlbie",   X(31,306), XRTLRA_MASK,    PPC,            { RB, L } },
3577 { "tlbi",    X(31,306), XRT_MASK,       POWER,          { RA, RB } },
3578
3579 { "eciwx",   X(31,310), X_MASK,         PPC,            { RT, RA, RB } },
3580
3581 { "lhzux",   X(31,311), X_MASK,         COM,            { RT, RAL, RB } },
3582
3583 { "xor",     XRC(31,316,0), X_MASK,     COM,            { RA, RS, RB } },
3584 { "xor.",    XRC(31,316,1), X_MASK,     COM,            { RA, RS, RB } },
3585
3586 { "lhzuxe",  X(31,319), X_MASK,         BOOKE64,        { RT, RAL, RB } },
3587
3588 { "mfexisr",  XSPR(31,323,64),  XSPR_MASK, PPC403,      { RT } },
3589 { "mfexier",  XSPR(31,323,66),  XSPR_MASK, PPC403,      { RT } },
3590 { "mfbr0",    XSPR(31,323,128), XSPR_MASK, PPC403,      { RT } },
3591 { "mfbr1",    XSPR(31,323,129), XSPR_MASK, PPC403,      { RT } },
3592 { "mfbr2",    XSPR(31,323,130), XSPR_MASK, PPC403,      { RT } },
3593 { "mfbr3",    XSPR(31,323,131), XSPR_MASK, PPC403,      { RT } },
3594 { "mfbr4",    XSPR(31,323,132), XSPR_MASK, PPC403,      { RT } },
3595 { "mfbr5",    XSPR(31,323,133), XSPR_MASK, PPC403,      { RT } },
3596 { "mfbr6",    XSPR(31,323,134), XSPR_MASK, PPC403,      { RT } },
3597 { "mfbr7",    XSPR(31,323,135), XSPR_MASK, PPC403,      { RT } },
3598 { "mfbear",   XSPR(31,323,144), XSPR_MASK, PPC403,      { RT } },
3599 { "mfbesr",   XSPR(31,323,145), XSPR_MASK, PPC403,      { RT } },
3600 { "mfiocr",   XSPR(31,323,160), XSPR_MASK, PPC403,      { RT } },
3601 { "mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403,      { RT } },
3602 { "mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403,      { RT } },
3603 { "mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403,      { RT } },
3604 { "mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403,      { RT } },
3605 { "mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403,      { RT } },
3606 { "mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403,      { RT } },
3607 { "mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403,      { RT } },
3608 { "mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403,      { RT } },
3609 { "mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403,      { RT } },
3610 { "mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403,      { RT } },
3611 { "mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403,      { RT } },
3612 { "mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403,      { RT } },
3613 { "mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403,      { RT } },
3614 { "mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403,      { RT } },
3615 { "mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403,      { RT } },
3616 { "mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403,      { RT } },
3617 { "mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403,      { RT } },
3618 { "mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403,      { RT } },
3619 { "mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403,      { RT } },
3620 { "mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403,      { RT } },
3621 { "mfdmasr",  XSPR(31,323,224), XSPR_MASK, PPC403,      { RT } },
3622 { "mfdcr",    X(31,323),        X_MASK,         PPC403,         { RT, SPR } },
3623 { "mfdcr",    X(31,323),        X_MASK,         BOOKE,          { RT, SPR } },
3624
3625 { "div",     XO(31,331,0,0), XO_MASK,   M601,           { RT, RA, RB } },
3626 { "div.",    XO(31,331,0,1), XO_MASK,   M601,           { RT, RA, RB } },
3627 { "divo",    XO(31,331,1,0), XO_MASK,   M601,           { RT, RA, RB } },
3628 { "divo.",   XO(31,331,1,1), XO_MASK,   M601,           { RT, RA, RB } },
3629
3630 { "mfpmr",   X(31,334), X_MASK,         PPCPMR,         { RT, PMRN }},
3631
3632 { "mfmq",       XSPR(31,339,0),    XSPR_MASK, M601,     { RT } },
3633 { "mfxer",      XSPR(31,339,1),    XSPR_MASK, COM,      { RT } },
3634 { "mfrtcu",     XSPR(31,339,4),    XSPR_MASK, COM,      { RT } },
3635 { "mfrtcl",     XSPR(31,339,5),    XSPR_MASK, COM,      { RT } },
3636 { "mfdec",      XSPR(31,339,6),    XSPR_MASK, MFDEC1,   { RT } },
3637 { "mflr",       XSPR(31,339,8),    XSPR_MASK, COM,      { RT } },
3638 { "mfctr",      XSPR(31,339,9),    XSPR_MASK, COM,      { RT } },
3639 { "mftid",      XSPR(31,339,17),   XSPR_MASK, POWER,    { RT } },
3640 { "mfdsisr",    XSPR(31,339,18),   XSPR_MASK, COM,      { RT } },
3641 { "mfdar",      XSPR(31,339,19),   XSPR_MASK, COM,      { RT } },
3642 { "mfdec",      XSPR(31,339,22),   XSPR_MASK, MFDEC2,   { RT } },
3643 { "mfsdr0",     XSPR(31,339,24),   XSPR_MASK, POWER,    { RT } },
3644 { "mfsdr1",     XSPR(31,339,25),   XSPR_MASK, COM,      { RT } },
3645 { "mfsrr0",     XSPR(31,339,26),   XSPR_MASK, COM,      { RT } },
3646 { "mfsrr1",     XSPR(31,339,27),   XSPR_MASK, COM,      { RT } },
3647 { "mfpid",      XSPR(31,339,48),   XSPR_MASK, BOOKE,    { RT } },
3648 { "mfcsrr0",    XSPR(31,339,58),   XSPR_MASK, BOOKE,    { RT } },
3649 { "mfcsrr1",    XSPR(31,339,59),   XSPR_MASK, BOOKE,    { RT } },
3650 { "mfdear",     XSPR(31,339,61),   XSPR_MASK, BOOKE,    { RT } },
3651 { "mfesr",      XSPR(31,339,62),   XSPR_MASK, BOOKE,    { RT } },
3652 { "mfivpr",     XSPR(31,339,63),   XSPR_MASK, BOOKE,    { RT } },
3653 { "mfcmpa",     XSPR(31,339,144),  XSPR_MASK, PPC860,   { RT } },
3654 { "mfcmpb",     XSPR(31,339,145),  XSPR_MASK, PPC860,   { RT } },
3655 { "mfcmpc",     XSPR(31,339,146),  XSPR_MASK, PPC860,   { RT } },
3656 { "mfcmpd",     XSPR(31,339,147),  XSPR_MASK, PPC860,   { RT } },
3657 { "mficr",      XSPR(31,339,148),  XSPR_MASK, PPC860,   { RT } },
3658 { "mfder",      XSPR(31,339,149),  XSPR_MASK, PPC860,   { RT } },
3659 { "mfcounta",   XSPR(31,339,150),  XSPR_MASK, PPC860,   { RT } },
3660 { "mfcountb",   XSPR(31,339,151),  XSPR_MASK, PPC860,   { RT } },
3661 { "mfcmpe",     XSPR(31,339,152),  XSPR_MASK, PPC860,   { RT } },
3662 { "mfcmpf",     XSPR(31,339,153),  XSPR_MASK, PPC860,   { RT } },
3663 { "mfcmpg",     XSPR(31,339,154),  XSPR_MASK, PPC860,   { RT } },
3664 { "mfcmph",     XSPR(31,339,155),  XSPR_MASK, PPC860,   { RT } },
3665 { "mflctrl1",   XSPR(31,339,156),  XSPR_MASK, PPC860,   { RT } },
3666 { "mflctrl2",   XSPR(31,339,157),  XSPR_MASK, PPC860,   { RT } },
3667 { "mfictrl",    XSPR(31,339,158),  XSPR_MASK, PPC860,   { RT } },
3668 { "mfbar",      XSPR(31,339,159),  XSPR_MASK, PPC860,   { RT } },
3669 { "mfvrsave",   XSPR(31,339,256),  XSPR_MASK, PPCVEC,   { RT } },
3670 { "mfusprg0",   XSPR(31,339,256),  XSPR_MASK, BOOKE,    { RT } },
3671 { "mfsprg4",    XSPR(31,339,260),  XSPR_MASK, PPC405,   { RT } },
3672 { "mfsprg5",    XSPR(31,339,261),  XSPR_MASK, PPC405,   { RT } },
3673 { "mfsprg6",    XSPR(31,339,262),  XSPR_MASK, PPC405,   { RT } },
3674 { "mfsprg7",    XSPR(31,339,263),  XSPR_MASK, PPC405,   { RT } },
3675 { "mftbl",      XSPR(31,339,268),  XSPR_MASK, BOOKE,    { RT } },
3676 { "mftbu",      XSPR(31,339,269),  XSPR_MASK, BOOKE,    { RT } },
3677 { "mfsprg",     XSPR(31,339,272),  XSPRG_MASK, PPC,     { RT, SPRG } },
3678 { "mfsprg0",    XSPR(31,339,272),  XSPR_MASK, PPC,      { RT } },
3679 { "mfsprg1",    XSPR(31,339,273),  XSPR_MASK, PPC,      { RT } },
3680 { "mfsprg2",    XSPR(31,339,274),  XSPR_MASK, PPC,      { RT } },
3681 { "mfsprg3",    XSPR(31,339,275),  XSPR_MASK, PPC,      { RT } },
3682 { "mfasr",      XSPR(31,339,280),  XSPR_MASK, PPC64,    { RT } },
3683 { "mfear",      XSPR(31,339,282),  XSPR_MASK, PPC,      { RT } },
3684 { "mfpir",      XSPR(31,339,286),  XSPR_MASK, BOOKE,    { RT } },
3685 { "mfpvr",      XSPR(31,339,287),  XSPR_MASK, PPC,      { RT } },
3686 { "mfdbsr",     XSPR(31,339,304),  XSPR_MASK, BOOKE,    { RT } },
3687 { "mfdbcr0",    XSPR(31,339,308),  XSPR_MASK, BOOKE,    { RT } },
3688 { "mfdbcr1",    XSPR(31,339,309),  XSPR_MASK, BOOKE,    { RT } },
3689 { "mfdbcr2",    XSPR(31,339,310),  XSPR_MASK, BOOKE,    { RT } },
3690 { "mfiac1",     XSPR(31,339,312),  XSPR_MASK, BOOKE,    { RT } },
3691 { "mfiac2",     XSPR(31,339,313),  XSPR_MASK, BOOKE,    { RT } },
3692 { "mfiac3",     XSPR(31,339,314),  XSPR_MASK, BOOKE,    { RT } },
3693 { "mfiac4",     XSPR(31,339,315),  XSPR_MASK, BOOKE,    { RT } },
3694 { "mfdac1",     XSPR(31,339,316),  XSPR_MASK, BOOKE,    { RT } },
3695 { "mfdac2",     XSPR(31,339,317),  XSPR_MASK, BOOKE,    { RT } },
3696 { "mfdvc1",     XSPR(31,339,318),  XSPR_MASK, BOOKE,    { RT } },
3697 { "mfdvc2",     XSPR(31,339,319),  XSPR_MASK, BOOKE,    { RT } },
3698 { "mftsr",      XSPR(31,339,336),  XSPR_MASK, BOOKE,    { RT } },
3699 { "mftcr",      XSPR(31,339,340),  XSPR_MASK, BOOKE,    { RT } },
3700 { "mfivor0",    XSPR(31,339,400),  XSPR_MASK, BOOKE,    { RT } },
3701 { "mfivor1",    XSPR(31,339,401),  XSPR_MASK, BOOKE,    { RT } },
3702 { "mfivor2",    XSPR(31,339,402),  XSPR_MASK, BOOKE,    { RT } },
3703 { "mfivor3",    XSPR(31,339,403),  XSPR_MASK, BOOKE,    { RT } },
3704 { "mfivor4",    XSPR(31,339,404),  XSPR_MASK, BOOKE,    { RT } },
3705 { "mfivor5",    XSPR(31,339,405),  XSPR_MASK, BOOKE,    { RT } },
3706 { "mfivor6",    XSPR(31,339,406),  XSPR_MASK, BOOKE,    { RT } },
3707 { "mfivor7",    XSPR(31,339,407),  XSPR_MASK, BOOKE,    { RT } },
3708 { "mfivor8",    XSPR(31,339,408),  XSPR_MASK, BOOKE,    { RT } },
3709 { "mfivor9",    XSPR(31,339,409),  XSPR_MASK, BOOKE,    { RT } },
3710 { "mfivor10",   XSPR(31,339,410),  XSPR_MASK, BOOKE,    { RT } },
3711 { "mfivor11",   XSPR(31,339,411),  XSPR_MASK, BOOKE,    { RT } },
3712 { "mfivor12",   XSPR(31,339,412),  XSPR_MASK, BOOKE,    { RT } },
3713 { "mfivor13",   XSPR(31,339,413),  XSPR_MASK, BOOKE,    { RT } },
3714 { "mfivor14",   XSPR(31,339,414),  XSPR_MASK, BOOKE,    { RT } },
3715 { "mfivor15",   XSPR(31,339,415),  XSPR_MASK, BOOKE,    { RT } },
3716 { "mfspefscr",  XSPR(31,339,512),  XSPR_MASK, PPCSPE,   { RT } },
3717 { "mfbbear",    XSPR(31,339,513),  XSPR_MASK, PPCBRLK,  { RT } },
3718 { "mfibatu",    XSPR(31,339,528),  XSPRBAT_MASK, PPC,   { RT, SPRBAT } },
3719 { "mfibatl",    XSPR(31,339,529),  XSPRBAT_MASK, PPC,   { RT, SPRBAT } },
3720 { "mfdbatu",    XSPR(31,339,536),  XSPRBAT_MASK, PPC,   { RT, SPRBAT } },
3721 { "mfdbatl",    XSPR(31,339,537),  XSPRBAT_MASK, PPC,   { RT, SPRBAT } },
3722 { "mfic_cst",   XSPR(31,339,560),  XSPR_MASK, PPC860,   { RT } },
3723 { "mfic_adr",   XSPR(31,339,561),  XSPR_MASK, PPC860,   { RT } },
3724 { "mfic_dat",   XSPR(31,339,562),  XSPR_MASK, PPC860,   { RT } },
3725 { "mfdc_cst",   XSPR(31,339,568),  XSPR_MASK, PPC860,   { RT } },
3726 { "mfdc_adr",   XSPR(31,339,569),  XSPR_MASK, PPC860,   { RT } },
3727 { "mfdc_dat",   XSPR(31,339,570),  XSPR_MASK, PPC860,   { RT } },
3728 { "mfmcsrr0",   XSPR(31,339,570),  XSPR_MASK, PPCRFMCI, { RT } },
3729 { "mfmcsrr1",   XSPR(31,339,571),  XSPR_MASK, PPCRFMCI, { RT } },
3730 { "mfmcsr",     XSPR(31,339,572),  XSPR_MASK, PPCRFMCI, { RT } },
3731 { "mfdpdr",     XSPR(31,339,630),  XSPR_MASK, PPC860,   { RT } },
3732 { "mfdpir",     XSPR(31,339,631),  XSPR_MASK, PPC860,   { RT } },
3733 { "mfimmr",     XSPR(31,339,638),  XSPR_MASK, PPC860,   { RT } },
3734 { "mfmi_ctr",   XSPR(31,339,784),  XSPR_MASK, PPC860,   { RT } },
3735 { "mfmi_ap",    XSPR(31,339,786),  XSPR_MASK, PPC860,   { RT } },
3736 { "mfmi_epn",   XSPR(31,339,787),  XSPR_MASK, PPC860,   { RT } },
3737 { "mfmi_twc",   XSPR(31,339,789),  XSPR_MASK, PPC860,   { RT } },
3738 { "mfmi_rpn",   XSPR(31,339,790),  XSPR_MASK, PPC860,   { RT } },
3739 { "mfmd_ctr",   XSPR(31,339,792),  XSPR_MASK, PPC860,   { RT } },
3740 { "mfm_casid",  XSPR(31,339,793),  XSPR_MASK, PPC860,   { RT } },
3741 { "mfmd_ap",    XSPR(31,339,794),  XSPR_MASK, PPC860,   { RT } },
3742 { "mfmd_epn",   XSPR(31,339,795),  XSPR_MASK, PPC860,   { RT } },
3743 { "mfmd_twb",   XSPR(31,339,796),  XSPR_MASK, PPC860,   { RT } },
3744 { "mfmd_twc",   XSPR(31,339,797),  XSPR_MASK, PPC860,   { RT } },
3745 { "mfmd_rpn",   XSPR(31,339,798),  XSPR_MASK, PPC860,   { RT } },
3746 { "mfm_tw",     XSPR(31,339,799),  XSPR_MASK, PPC860,   { RT } },
3747 { "mfmi_dbcam", XSPR(31,339,816),  XSPR_MASK, PPC860,   { RT } },
3748 { "mfmi_dbram0",XSPR(31,339,817),  XSPR_MASK, PPC860,   { RT } },
3749 { "mfmi_dbram1",XSPR(31,339,818),  XSPR_MASK, PPC860,   { RT } },
3750 { "mfmd_dbcam", XSPR(31,339,824),  XSPR_MASK, PPC860,   { RT } },
3751 { "mfmd_dbram0",XSPR(31,339,825),  XSPR_MASK, PPC860,   { RT } },
3752 { "mfmd_dbram1",XSPR(31,339,826),  XSPR_MASK, PPC860,   { RT } },
3753 { "mfummcr0",   XSPR(31,339,936),  XSPR_MASK, PPC750,   { RT } },
3754 { "mfupmc1",    XSPR(31,339,937),  XSPR_MASK, PPC750,   { RT } },
3755 { "mfupmc2",    XSPR(31,339,938),  XSPR_MASK, PPC750,   { RT } },
3756 { "mfusia",     XSPR(31,339,939),  XSPR_MASK, PPC750,   { RT } },
3757 { "mfummcr1",   XSPR(31,339,940),  XSPR_MASK, PPC750,   { RT } },
3758 { "mfupmc3",    XSPR(31,339,941),  XSPR_MASK, PPC750,   { RT } },
3759 { "mfupmc4",    XSPR(31,339,942),  XSPR_MASK, PPC750,   { RT } },
3760 { "mfzpr",      XSPR(31,339,944),  XSPR_MASK, PPC403,   { RT } },
3761 { "mfpid",      XSPR(31,339,945),  XSPR_MASK, PPC403,   { RT } },
3762 { "mfccr0",     XSPR(31,339,947),  XSPR_MASK, PPC405,   { RT } },
3763 { "mfiac3",     XSPR(31,339,948),  XSPR_MASK, PPC405,   { RT } },
3764 { "mfiac4",     XSPR(31,339,949),  XSPR_MASK, PPC405,   { RT } },
3765 { "mfdvc1",     XSPR(31,339,950),  XSPR_MASK, PPC405,   { RT } },
3766 { "mfdvc2",     XSPR(31,339,951),  XSPR_MASK, PPC405,   { RT } },
3767 { "mfmmcr0",    XSPR(31,339,952),  XSPR_MASK, PPC750,   { RT } },
3768 { "mfpmc1",     XSPR(31,339,953),  XSPR_MASK, PPC750,   { RT } },
3769 { "mfsgr",      XSPR(31,339,953),  XSPR_MASK, PPC403,   { RT } },
3770 { "mfpmc2",     XSPR(31,339,954),  XSPR_MASK, PPC750,   { RT } },
3771 { "mfdcwr",     XSPR(31,339,954),  XSPR_MASK, PPC403,   { RT } },
3772 { "mfsia",      XSPR(31,339,955),  XSPR_MASK, PPC750,   { RT } },
3773 { "mfsler",     XSPR(31,339,955),  XSPR_MASK, PPC405,   { RT } },
3774 { "mfmmcr1",    XSPR(31,339,956),  XSPR_MASK, PPC750,   { RT } },
3775 { "mfsu0r",     XSPR(31,339,956),  XSPR_MASK, PPC405,   { RT } },
3776 { "mfpmc3",     XSPR(31,339,957),  XSPR_MASK, PPC750,   { RT } },
3777 { "mfdbcr1",    XSPR(31,339,957),  XSPR_MASK, PPC405,   { RT } },
3778 { "mfpmc4",     XSPR(31,339,958),  XSPR_MASK, PPC750,   { RT } },
3779 { "mficdbdr",   XSPR(31,339,979),  XSPR_MASK, PPC403,   { RT } },
3780 { "mfesr",      XSPR(31,339,980),  XSPR_MASK, PPC403,   { RT } },
3781 { "mfdear",     XSPR(31,339,981),  XSPR_MASK, PPC403,   { RT } },
3782 { "mfevpr",     XSPR(31,339,982),  XSPR_MASK, PPC403,   { RT } },
3783 { "mfcdbcr",    XSPR(31,339,983),  XSPR_MASK, PPC403,   { RT } },
3784 { "mftsr",      XSPR(31,339,984),  XSPR_MASK, PPC403,   { RT } },
3785 { "mftcr",      XSPR(31,339,986),  XSPR_MASK, PPC403,   { RT } },
3786 { "mfpit",      XSPR(31,339,987),  XSPR_MASK, PPC403,   { RT } },
3787 { "mftbhi",     XSPR(31,339,988),  XSPR_MASK, PPC403,   { RT } },
3788 { "mftblo",     XSPR(31,339,989),  XSPR_MASK, PPC403,   { RT } },
3789 { "mfsrr2",     XSPR(31,339,990),  XSPR_MASK, PPC403,   { RT } },
3790 { "mfsrr3",     XSPR(31,339,991),  XSPR_MASK, PPC403,   { RT } },
3791 { "mfdbsr",     XSPR(31,339,1008), XSPR_MASK, PPC403,   { RT } },
3792 { "mfdbcr0",    XSPR(31,339,1010), XSPR_MASK, PPC405,   { RT } },
3793 { "mfiac1",     XSPR(31,339,1012), XSPR_MASK, PPC403,   { RT } },
3794 { "mfiac2",     XSPR(31,339,1013), XSPR_MASK, PPC403,   { RT } },
3795 { "mfdac1",     XSPR(31,339,1014), XSPR_MASK, PPC403,   { RT } },
3796 { "mfdac2",     XSPR(31,339,1015), XSPR_MASK, PPC403,   { RT } },
3797 { "mfl2cr",     XSPR(31,339,1017), XSPR_MASK, PPC750,   { RT } },
3798 { "mfdccr",     XSPR(31,339,1018), XSPR_MASK, PPC403,   { RT } },
3799 { "mficcr",     XSPR(31,339,1019), XSPR_MASK, PPC403,   { RT } },
3800 { "mfictc",     XSPR(31,339,1019), XSPR_MASK, PPC750,   { RT } },
3801 { "mfpbl1",     XSPR(31,339,1020), XSPR_MASK, PPC403,   { RT } },
3802 { "mfthrm1",    XSPR(31,339,1020), XSPR_MASK, PPC750,   { RT } },
3803 { "mfpbu1",     XSPR(31,339,1021), XSPR_MASK, PPC403,   { RT } },
3804 { "mfthrm2",    XSPR(31,339,1021), XSPR_MASK, PPC750,   { RT } },
3805 { "mfpbl2",     XSPR(31,339,1022), XSPR_MASK, PPC403,   { RT } },
3806 { "mfthrm3",    XSPR(31,339,1022), XSPR_MASK, PPC750,   { RT } },
3807 { "mfpbu2",     XSPR(31,339,1023), XSPR_MASK, PPC403,   { RT } },
3808 { "mfspr",      X(31,339),         X_MASK,    COM,      { RT, SPR } },
3809
3810 { "lwax",    X(31,341), X_MASK,         PPC64,          { RT, RA, RB } },
3811
3812 { "dst",     XDSS(31,342,0), XDSS_MASK, PPCVEC,         { RA, RB, STRM } },
3813 { "dstt",    XDSS(31,342,1), XDSS_MASK, PPCVEC,         { RA, RB, STRM } },
3814
3815 { "lhax",    X(31,343), X_MASK,         COM,            { RT, RA, RB } },
3816
3817 { "lhaxe",   X(31,351), X_MASK,         BOOKE64,        { RT, RA, RB } },
3818
3819 { "dstst",   XDSS(31,374,0), XDSS_MASK, PPCVEC,         { RA, RB, STRM } },
3820 { "dststt",  XDSS(31,374,1), XDSS_MASK, PPCVEC,         { RA, RB, STRM } },
3821
3822 { "dccci",   X(31,454), XRT_MASK,       PPC403,         { RA, RB } },
3823
3824 { "abs",     XO(31,360,0,0), XORB_MASK, M601,           { RT, RA } },
3825 { "abs.",    XO(31,360,0,1), XORB_MASK, M601,           { RT, RA } },
3826 { "abso",    XO(31,360,1,0), XORB_MASK, M601,           { RT, RA } },
3827 { "abso.",   XO(31,360,1,1), XORB_MASK, M601,           { RT, RA } },
3828
3829 { "divs",    XO(31,363,0,0), XO_MASK,   M601,           { RT, RA, RB } },
3830 { "divs.",   XO(31,363,0,1), XO_MASK,   M601,           { RT, RA, RB } },
3831 { "divso",   XO(31,363,1,0), XO_MASK,   M601,           { RT, RA, RB } },
3832 { "divso.",  XO(31,363,1,1), XO_MASK,   M601,           { RT, RA, RB } },
3833
3834 { "tlbia",   X(31,370), 0xffffffff,     PPC,            { 0 } },
3835
3836 { "mftbl",   XSPR(31,371,268), XSPR_MASK, CLASSIC,      { RT } },
3837 { "mftbu",   XSPR(31,371,269), XSPR_MASK, CLASSIC,      { RT } },
3838 { "mftb",    X(31,371), X_MASK,         BOOKE,          { RT, TBR } },
3839 { "mftb",    X(31,371), X_MASK,         CLASSIC,        { RT, TBR } },
3840
3841 { "lwaux",   X(31,373), X_MASK,         PPC64,          { RT, RAL, RB } },
3842
3843 { "lhaux",   X(31,375), X_MASK,         COM,            { RT, RAL, RB } },
3844
3845 { "lhauxe",  X(31,383), X_MASK,         BOOKE64,        { RT, RAL, RB } },
3846
3847 { "mtdcrx",  X(31,387), X_MASK,         BOOKE,          { RA, RS } },
3848
3849 { "dcblc",   X(31,390), X_MASK,         PPCCHLK,        { CT, RA, RB }},
3850
3851 { "subfe64", XO(31,392,0,0), XO_MASK,   BOOKE64,        { RT, RA, RB } },
3852 { "subfe64o",XO(31,392,1,0), XO_MASK,   BOOKE64,        { RT, RA, RB } },
3853
3854 { "adde64",  XO(31,394,0,0), XO_MASK,   BOOKE64,        { RT, RA, RB } },
3855 { "adde64o", XO(31,394,1,0), XO_MASK,   BOOKE64,        { RT, RA, RB } },
3856
3857 { "dcblce",  X(31,398), X_MASK,         PPCCHLK64,      { CT, RA, RB }},
3858
3859 { "slbmte",  X(31,402), XRA_MASK,       PPC64,          { RS, RB } },
3860
3861 { "sthx",    X(31,407), X_MASK,         COM,            { RS, RA, RB } },
3862
3863 { "lfqx",    X(31,791), X_MASK,         POWER2,         { FRT, RA, RB } },
3864
3865 { "lfqux",   X(31,823), X_MASK,         POWER2,         { FRT, RA, RB } },
3866
3867 { "stfqx",   X(31,919), X_MASK,         POWER2,         { FRS, RA, RB } },
3868
3869 { "stfqux",  X(31,951), X_MASK,         POWER2,         { FRS, RA, RB } },
3870
3871 { "orc",     XRC(31,412,0), X_MASK,     COM,            { RA, RS, RB } },
3872 { "orc.",    XRC(31,412,1), X_MASK,     COM,            { RA, RS, RB } },
3873
3874 { "sradi",   XS(31,413,0), XS_MASK,     PPC64,          { RA, RS, SH6 } },
3875 { "sradi.",  XS(31,413,1), XS_MASK,     PPC64,          { RA, RS, SH6 } },
3876
3877 { "sthxe",   X(31,415), X_MASK,         BOOKE64,        { RS, RA, RB } },
3878
3879 { "slbie",   X(31,434), XRTRA_MASK,     PPC64,          { RB } },
3880
3881 { "ecowx",   X(31,438), X_MASK,         PPC,            { RT, RA, RB } },
3882
3883 { "sthux",   X(31,439), X_MASK,         COM,            { RS, RAS, RB } },
3884
3885 { "sthuxe",  X(31,447), X_MASK,         BOOKE64,        { RS, RAS, RB } },
3886
3887 { "mr",      XRC(31,444,0), X_MASK,     COM,            { RA, RS, RBS } },
3888 { "or",      XRC(31,444,0), X_MASK,     COM,            { RA, RS, RB } },
3889 { "mr.",     XRC(31,444,1), X_MASK,     COM,            { RA, RS, RBS } },
3890 { "or.",     XRC(31,444,1), X_MASK,     COM,            { RA, RS, RB } },
3891
3892 { "mtexisr",  XSPR(31,451,64),  XSPR_MASK, PPC403,      { RT } },
3893 { "mtexier",  XSPR(31,451,66),  XSPR_MASK, PPC403,      { RT } },
3894 { "mtbr0",    XSPR(31,451,128), XSPR_MASK, PPC403,      { RT } },
3895 { "mtbr1",    XSPR(31,451,129), XSPR_MASK, PPC403,      { RT } },
3896 { "mtbr2",    XSPR(31,451,130), XSPR_MASK, PPC403,      { RT } },
3897 { "mtbr3",    XSPR(31,451,131), XSPR_MASK, PPC403,      { RT } },
3898 { "mtbr4",    XSPR(31,451,132), XSPR_MASK, PPC403,      { RT } },
3899 { "mtbr5",    XSPR(31,451,133), XSPR_MASK, PPC403,      { RT } },
3900 { "mtbr6",    XSPR(31,451,134), XSPR_MASK, PPC403,      { RT } },
3901 { "mtbr7",    XSPR(31,451,135), XSPR_MASK, PPC403,      { RT } },
3902 { "mtbear",   XSPR(31,451,144), XSPR_MASK, PPC403,      { RT } },
3903 { "mtbesr",   XSPR(31,451,145), XSPR_MASK, PPC403,      { RT } },
3904 { "mtiocr",   XSPR(31,451,160), XSPR_MASK, PPC403,      { RT } },
3905 { "mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403,      { RT } },
3906 { "mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403,      { RT } },
3907 { "mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403,      { RT } },
3908 { "mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403,      { RT } },
3909 { "mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403,      { RT } },
3910 { "mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403,      { RT } },
3911 { "mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403,      { RT } },
3912 { "mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403,      { RT } },
3913 { "mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403,      { RT } },
3914 { "mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403,      { RT } },
3915 { "mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403,      { RT } },
3916 { "mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403,      { RT } },
3917 { "mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403,      { RT } },
3918 { "mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403,      { RT } },
3919 { "mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403,      { RT } },
3920 { "mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403,      { RT } },
3921 { "mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403,      { RT } },
3922 { "mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403,      { RT } },
3923 { "mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403,      { RT } },
3924 { "mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403,      { RT } },
3925 { "mtdmasr",  XSPR(31,451,224), XSPR_MASK, PPC403,      { RT } },
3926 { "mtdcr",    X(31,451),        X_MASK,         PPC403,         { SPR, RS } },
3927 { "mtdcr",    X(31,451),        X_MASK,         BOOKE,          { SPR, RS } },
3928
3929 { "subfze64",XO(31,456,0,0), XORB_MASK, BOOKE64,        { RT, RA } },
3930 { "subfze64o",XO(31,456,1,0), XORB_MASK, BOOKE64,       { RT, RA } },
3931
3932 { "divdu",   XO(31,457,0,0), XO_MASK,   PPC64,          { RT, RA, RB } },
3933 { "divdu.",  XO(31,457,0,1), XO_MASK,   PPC64,          { RT, RA, RB } },
3934 { "divduo",  XO(31,457,1,0), XO_MASK,   PPC64,          { RT, RA, RB } },
3935 { "divduo.", XO(31,457,1,1), XO_MASK,   PPC64,          { RT, RA, RB } },
3936
3937 { "addze64", XO(31,458,0,0), XORB_MASK, BOOKE64,        { RT, RA } },
3938 { "addze64o",XO(31,458,1,0), XORB_MASK, BOOKE64,        { RT, RA } },
3939
3940 { "divwu",   XO(31,459,0,0), XO_MASK,   PPC,            { RT, RA, RB } },
3941 { "divwu.",  XO(31,459,0,1), XO_MASK,   PPC,            { RT, RA, RB } },
3942 { "divwuo",  XO(31,459,1,0), XO_MASK,   PPC,            { RT, RA, RB } },
3943 { "divwuo.", XO(31,459,1,1), XO_MASK,   PPC,            { RT, RA, RB } },
3944
3945 { "mtmq",      XSPR(31,467,0),    XSPR_MASK, M601,      { RS } },
3946 { "mtxer",     XSPR(31,467,1),    XSPR_MASK, COM,       { RS } },
3947 { "mtlr",      XSPR(31,467,8),    XSPR_MASK, COM,       { RS } },
3948 { "mtctr",     XSPR(31,467,9),    XSPR_MASK, COM,       { RS } },
3949 { "mttid",     XSPR(31,467,17),   XSPR_MASK, POWER,     { RS } },
3950 { "mtdsisr",   XSPR(31,467,18),   XSPR_MASK, COM,       { RS } },
3951 { "mtdar",     XSPR(31,467,19),   XSPR_MASK, COM,       { RS } },
3952 { "mtrtcu",    XSPR(31,467,20),   XSPR_MASK, COM,       { RS } },
3953 { "mtrtcl",    XSPR(31,467,21),   XSPR_MASK, COM,       { RS } },
3954 { "mtdec",     XSPR(31,467,22),   XSPR_MASK, COM,       { RS } },
3955 { "mtsdr0",    XSPR(31,467,24),   XSPR_MASK, POWER,     { RS } },
3956 { "mtsdr1",    XSPR(31,467,25),   XSPR_MASK, COM,       { RS } },
3957 { "mtsrr0",    XSPR(31,467,26),   XSPR_MASK, COM,       { RS } },
3958 { "mtsrr1",    XSPR(31,467,27),   XSPR_MASK, COM,       { RS } },
3959 { "mtpid",     XSPR(31,467,48),   XSPR_MASK, BOOKE,     { RS } },
3960 { "mtdecar",   XSPR(31,467,54),   XSPR_MASK, BOOKE,     { RS } },
3961 { "mtcsrr0",   XSPR(31,467,58),   XSPR_MASK, BOOKE,     { RS } },
3962 { "mtcsrr1",   XSPR(31,467,59),   XSPR_MASK, BOOKE,     { RS } },
3963 { "mtdear",    XSPR(31,467,61),   XSPR_MASK, BOOKE,     { RS } },
3964 { "mtesr",     XSPR(31,467,62),   XSPR_MASK, BOOKE,     { RS } },
3965 { "mtivpr",    XSPR(31,467,63),   XSPR_MASK, BOOKE,     { RS } },
3966 { "mtcmpa",    XSPR(31,467,144),  XSPR_MASK, PPC860,    { RT } },
3967 { "mtcmpb",    XSPR(31,467,145),  XSPR_MASK, PPC860,    { RT } },
3968 { "mtcmpc",    XSPR(31,467,146),  XSPR_MASK, PPC860,    { RT } },
3969 { "mtcmpd",    XSPR(31,467,147),  XSPR_MASK, PPC860,    { RT } },
3970 { "mticr",     XSPR(31,467,148),  XSPR_MASK, PPC860,    { RT } },
3971 { "mtder",     XSPR(31,467,149),  XSPR_MASK, PPC860,    { RT } },
3972 { "mtcounta",  XSPR(31,467,150),  XSPR_MASK, PPC860,    { RT } },
3973 { "mtcountb",  XSPR(31,467,151),  XSPR_MASK, PPC860,    { RT } },
3974 { "mtcmpe",    XSPR(31,467,152),  XSPR_MASK, PPC860,    { RT } },
3975 { "mtcmpf",    XSPR(31,467,153),  XSPR_MASK, PPC860,    { RT } },
3976 { "mtcmpg",    XSPR(31,467,154),  XSPR_MASK, PPC860,    { RT } },
3977 { "mtcmph",    XSPR(31,467,155),  XSPR_MASK, PPC860,    { RT } },
3978 { "mtlctrl1",  XSPR(31,467,156),  XSPR_MASK, PPC860,    { RT } },
3979 { "mtlctrl2",  XSPR(31,467,157),  XSPR_MASK, PPC860,    { RT } },
3980 { "mtictrl",   XSPR(31,467,158),  XSPR_MASK, PPC860,    { RT } },
3981 { "mtbar",     XSPR(31,467,159),  XSPR_MASK, PPC860,    { RT } },
3982 { "mtvrsave",  XSPR(31,467,256),  XSPR_MASK, PPCVEC,    { RT } },
3983 { "mtusprg0",  XSPR(31,467,256),  XSPR_MASK, BOOKE,     { RS } },
3984 { "mtsprg",    XSPR(31,467,272),  XSPRG_MASK,PPC,       { SPRG, RS } },
3985 { "mtsprg0",   XSPR(31,467,272),  XSPR_MASK, PPC,       { RT } },
3986 { "mtsprg1",   XSPR(31,467,273),  XSPR_MASK, PPC,       { RT } },
3987 { "mtsprg2",   XSPR(31,467,274),  XSPR_MASK, PPC,       { RT } },
3988 { "mtsprg3",   XSPR(31,467,275),  XSPR_MASK, PPC,       { RT } },
3989 { "mtsprg4",   XSPR(31,467,276),  XSPR_MASK, PPC405,    { RT } },
3990 { "mtsprg4",   XSPR(31,467,276),  XSPR_MASK, BOOKE,     { RS } },
3991 { "mtsprg5",   XSPR(31,467,277),  XSPR_MASK, PPC405,    { RT } },
3992 { "mtsprg5",   XSPR(31,467,277),  XSPR_MASK, BOOKE,     { RS } },
3993 { "mtsprg6",   XSPR(31,467,278),  XSPR_MASK, PPC405,    { RT } },
3994 { "mtsprg6",   XSPR(31,467,278),  XSPR_MASK, BOOKE,     { RS } },
3995 { "mtsprg7",   XSPR(31,467,279),  XSPR_MASK, PPC405,    { RT } },
3996 { "mtsprg7",   XSPR(31,467,279),  XSPR_MASK, BOOKE,     { RS } },
3997 { "mtasr",     XSPR(31,467,280),  XSPR_MASK, PPC64,     { RS } },
3998 { "mtear",     XSPR(31,467,282),  XSPR_MASK, PPC,       { RS } },
3999 { "mttbl",     XSPR(31,467,284),  XSPR_MASK, PPC,       { RS } },
4000 { "mttbu",     XSPR(31,467,285),  XSPR_MASK, PPC,       { RS } },
4001 { "mtdbsr",    XSPR(31,467,304),  XSPR_MASK, BOOKE,     { RS } },
4002 { "mtdbcr0",   XSPR(31,467,308),  XSPR_MASK, BOOKE,     { RS } },
4003 { "mtdbcr1",   XSPR(31,467,309),  XSPR_MASK, BOOKE,     { RS } },
4004 { "mtdbcr2",   XSPR(31,467,310),  XSPR_MASK, BOOKE,     { RS } },
4005 { "mtiac1",    XSPR(31,467,312),  XSPR_MASK, BOOKE,     { RS } },
4006 { "mtiac2",    XSPR(31,467,313),  XSPR_MASK, BOOKE,     { RS } },
4007 { "mtiac3",    XSPR(31,467,314),  XSPR_MASK, BOOKE,     { RS } },
4008 { "mtiac4",    XSPR(31,467,315),  XSPR_MASK, BOOKE,     { RS } },
4009 { "mtdac1",    XSPR(31,467,316),  XSPR_MASK, BOOKE,     { RS } },
4010 { "mtdac2",    XSPR(31,467,317),  XSPR_MASK, BOOKE,     { RS } },
4011 { "mtdvc1",    XSPR(31,467,318),  XSPR_MASK, BOOKE,     { RS } },
4012 { "mtdvc2",    XSPR(31,467,319),  XSPR_MASK, BOOKE,     { RS } },
4013 { "mttsr",     XSPR(31,467,336),  XSPR_MASK, BOOKE,     { RS } },
4014 { "mttcr",     XSPR(31,467,340),  XSPR_MASK, BOOKE,     { RS } },
4015 { "mtivor0",   XSPR(31,467,400),  XSPR_MASK, BOOKE,     { RS } },
4016 { "mtivor1",   XSPR(31,467,401),  XSPR_MASK, BOOKE,     { RS } },
4017 { "mtivor2",   XSPR(31,467,402),  XSPR_MASK, BOOKE,     { RS } },
4018 { "mtivor3",   XSPR(31,467,403),  XSPR_MASK, BOOKE,     { RS } },
4019 { "mtivor4",   XSPR(31,467,404),  XSPR_MASK, BOOKE,     { RS } },
4020 { "mtivor5",   XSPR(31,467,405),  XSPR_MASK, BOOKE,     { RS } },
4021 { "mtivor6",   XSPR(31,467,406),  XSPR_MASK, BOOKE,     { RS } },
4022 { "mtivor7",   XSPR(31,467,407),  XSPR_MASK, BOOKE,     { RS } },
4023 { "mtivor8",   XSPR(31,467,408),  XSPR_MASK, BOOKE,     { RS } },
4024 { "mtivor9",   XSPR(31,467,409),  XSPR_MASK, BOOKE,     { RS } },
4025 { "mtivor10",  XSPR(31,467,410),  XSPR_MASK, BOOKE,     { RS } },
4026 { "mtivor11",  XSPR(31,467,411),  XSPR_MASK, BOOKE,     { RS } },
4027 { "mtivor12",  XSPR(31,467,412),  XSPR_MASK, BOOKE,     { RS } },
4028 { "mtivor13",  XSPR(31,467,413),  XSPR_MASK, BOOKE,     { RS } },
4029 { "mtivor14",  XSPR(31,467,414),  XSPR_MASK, BOOKE,     { RS } },
4030 { "mtivor15",  XSPR(31,467,415),  XSPR_MASK, BOOKE,     { RS } },
4031 { "mtspefscr", XSPR(31,467,512),  XSPR_MASK, PPCSPE,    { RT } },
4032 { "mtbbear",   XSPR(31,467,513),  XSPR_MASK, PPCBRLK,   { RS } },
4033 { "mtibatu",   XSPR(31,467,528),  XSPRBAT_MASK, PPC,    { SPRBAT, RS } },
4034 { "mtibatl",   XSPR(31,467,529),  XSPRBAT_MASK, PPC,    { SPRBAT, RS } },
4035 { "mtdbatu",   XSPR(31,467,536),  XSPRBAT_MASK, PPC,    { SPRBAT, RS } },
4036 { "mtdbatl",   XSPR(31,467,537),  XSPRBAT_MASK, PPC,    { SPRBAT, RS } },
4037 { "mtmcsrr0",  XSPR(31,467,570),  XSPR_MASK, PPCRFMCI,  { RS } },
4038 { "mtmcsrr1",  XSPR(31,467,571),  XSPR_MASK, PPCRFMCI,  { RS } },
4039 { "mtmcsr",    XSPR(31,467,572),  XSPR_MASK, PPCRFMCI,  { RS } },
4040 { "mtummcr0",  XSPR(31,467,936),  XSPR_MASK, PPC750,    { RT } },
4041 { "mtupmc1",   XSPR(31,467,937),  XSPR_MASK, PPC750,    { RT } },
4042 { "mtupmc2",   XSPR(31,467,938),  XSPR_MASK, PPC750,    { RT } },
4043 { "mtusia",    XSPR(31,467,939),  XSPR_MASK, PPC750,    { RT } },
4044 { "mtummcr1",  XSPR(31,467,940),  XSPR_MASK, PPC750,    { RT } },
4045 { "mtupmc3",   XSPR(31,467,941),  XSPR_MASK, PPC750,    { RT } },
4046 { "mtupmc4",   XSPR(31,467,942),  XSPR_MASK, PPC750,    { RT } },
4047 { "mtzpr",     XSPR(31,467,944),  XSPR_MASK, PPC403,    { RT } },
4048 { "mtpid",     XSPR(31,467,945),  XSPR_MASK, PPC403,    { RT } },
4049 { "mtccr0",    XSPR(31,467,947),  XSPR_MASK, PPC405,    { RT } },
4050 { "mtiac3",    XSPR(31,467,948),  XSPR_MASK, PPC405,    { RT } },
4051 { "mtiac4",    XSPR(31,467,949),  XSPR_MASK, PPC405,    { RT } },
4052 { "mtdvc1",    XSPR(31,467,950),  XSPR_MASK, PPC405,    { RT } },
4053 { "mtdvc2",    XSPR(31,467,951),  XSPR_MASK, PPC405,    { RT } },
4054 { "mtmmcr0",   XSPR(31,467,952),  XSPR_MASK, PPC750,    { RT } },
4055 { "mtsgr",     XSPR(31,467,953),  XSPR_MASK, PPC403,    { RT } },
4056 { "mtpmc1",    XSPR(31,467,953),  XSPR_MASK, PPC750,    { RT } },
4057 { "mtdcwr",    XSPR(31,467,954),  XSPR_MASK, PPC403,    { RT } },
4058 { "mtpmc2",    XSPR(31,467,954),  XSPR_MASK, PPC750,    { RT } },
4059 { "mtsler",    XSPR(31,467,955),  XSPR_MASK, PPC405,    { RT } },
4060 { "mtsia",     XSPR(31,467,955),  XSPR_MASK, PPC750,    { RT } },
4061 { "mtsu0r",    XSPR(31,467,956),  XSPR_MASK, PPC405,    { RT } },
4062 { "mtmmcr1",   XSPR(31,467,956),  XSPR_MASK, PPC750,    { RT } },
4063 { "mtdbcr1",   XSPR(31,467,957),  XSPR_MASK, PPC405,    { RT } },
4064 { "mtpmc3",    XSPR(31,467,957),  XSPR_MASK, PPC750,    { RT } },
4065 { "mtpmc4",    XSPR(31,467,958),  XSPR_MASK, PPC750,    { RT } },
4066 { "mticdbdr",  XSPR(31,467,979),  XSPR_MASK, PPC403,    { RT } },
4067 { "mtesr",     XSPR(31,467,980),  XSPR_MASK, PPC403,    { RT } },
4068 { "mtdear",    XSPR(31,467,981),  XSPR_MASK, PPC403,    { RT } },
4069 { "mtevpr",    XSPR(31,467,982),  XSPR_MASK, PPC403,    { RT } },
4070 { "mtcdbcr",   XSPR(31,467,983),  XSPR_MASK, PPC403,    { RT } },
4071 { "mttsr",     XSPR(31,467,984),  XSPR_MASK, PPC403,    { RT } },
4072 { "mttcr",     XSPR(31,467,986),  XSPR_MASK, PPC403,    { RT } },
4073 { "mtpit",     XSPR(31,467,987),  XSPR_MASK, PPC403,    { RT } },
4074 { "mttbhi",    XSPR(31,467,988),  XSPR_MASK, PPC403,    { RT } },
4075 { "mttblo",    XSPR(31,467,989),  XSPR_MASK, PPC403,    { RT } },
4076 { "mtsrr2",    XSPR(31,467,990),  XSPR_MASK, PPC403,    { RT } },
4077 { "mtsrr3",    XSPR(31,467,991),  XSPR_MASK, PPC403,    { RT } },
4078 { "mtdbsr",    XSPR(31,467,1008), XSPR_MASK, PPC403,    { RT } },
4079 { "mtdbcr0",   XSPR(31,467,1010), XSPR_MASK, PPC405,    { RT } },
4080 { "mtiac1",    XSPR(31,467,1012), XSPR_MASK, PPC403,    { RT } },
4081 { "mtiac2",    XSPR(31,467,1013), XSPR_MASK, PPC403,    { RT } },
4082 { "mtdac1",    XSPR(31,467,1014), XSPR_MASK, PPC403,    { RT } },
4083 { "mtdac2",    XSPR(31,467,1015), XSPR_MASK, PPC403,    { RT } },
4084 { "mtl2cr",    XSPR(31,467,1017), XSPR_MASK, PPC750,    { RT } },
4085 { "mtdccr",    XSPR(31,467,1018), XSPR_MASK, PPC403,    { RT } },
4086 { "mticcr",    XSPR(31,467,1019), XSPR_MASK, PPC403,    { RT } },
4087 { "mtictc",    XSPR(31,467,1019), XSPR_MASK, PPC750,    { RT } },
4088 { "mtpbl1",    XSPR(31,467,1020), XSPR_MASK, PPC403,    { RT } },
4089 { "mtthrm1",   XSPR(31,467,1020), XSPR_MASK, PPC750,    { RT } },
4090 { "mtpbu1",    XSPR(31,467,1021), XSPR_MASK, PPC403,    { RT } },
4091 { "mtthrm2",   XSPR(31,467,1021), XSPR_MASK, PPC750,    { RT } },
4092 { "mtpbl2",    XSPR(31,467,1022), XSPR_MASK, PPC403,    { RT } },
4093 { "mtthrm3",   XSPR(31,467,1022), XSPR_MASK, PPC750,    { RT } },
4094 { "mtpbu2",    XSPR(31,467,1023), XSPR_MASK, PPC403,    { RT } },
4095 { "mtspr",     X(31,467),         X_MASK,    COM,       { SPR, RS } },
4096
4097 { "dcbi",    X(31,470), XRT_MASK,       PPC,            { RA, RB } },
4098
4099 { "nand",    XRC(31,476,0), X_MASK,     COM,            { RA, RS, RB } },
4100 { "nand.",   XRC(31,476,1), X_MASK,     COM,            { RA, RS, RB } },
4101
4102 { "dcbie",   X(31,478), XRT_MASK,       BOOKE64,        { RA, RB } },
4103
4104 { "dcread",  X(31,486), X_MASK,         PPC403,         { RT, RA, RB }},
4105
4106 { "mtpmr",   X(31,462), X_MASK,         PPCPMR,         { PMRN, RS }},
4107
4108 { "icbtls",  X(31,486), X_MASK,         PPCCHLK,        { CT, RA, RB }},
4109
4110 { "nabs",    XO(31,488,0,0), XORB_MASK, M601,           { RT, RA } },
4111 { "subfme64",XO(31,488,0,0), XORB_MASK, BOOKE64,        { RT, RA } },
4112 { "nabs.",   XO(31,488,0,1), XORB_MASK, M601,           { RT, RA } },
4113 { "nabso",   XO(31,488,1,0), XORB_MASK, M601,           { RT, RA } },
4114 { "subfme64o",XO(31,488,1,0), XORB_MASK, BOOKE64,       { RT, RA } },
4115 { "nabso.",  XO(31,488,1,1), XORB_MASK, M601,           { RT, RA } },
4116
4117 { "divd",    XO(31,489,0,0), XO_MASK,   PPC64,          { RT, RA, RB } },
4118 { "divd.",   XO(31,489,0,1), XO_MASK,   PPC64,          { RT, RA, RB } },
4119 { "divdo",   XO(31,489,1,0), XO_MASK,   PPC64,          { RT, RA, RB } },
4120 { "divdo.",  XO(31,489,1,1), XO_MASK,   PPC64,          { RT, RA, RB } },
4121
4122 { "addme64", XO(31,490,0,0), XORB_MASK, BOOKE64,        { RT, RA } },
4123 { "addme64o",XO(31,490,1,0), XORB_MASK, BOOKE64,        { RT, RA } },
4124
4125 { "divw",    XO(31,491,0,0), XO_MASK,   PPC,            { RT, RA, RB } },
4126 { "divw.",   XO(31,491,0,1), XO_MASK,   PPC,            { RT, RA, RB } },
4127 { "divwo",   XO(31,491,1,0), XO_MASK,   PPC,            { RT, RA, RB } },
4128 { "divwo.",  XO(31,491,1,1), XO_MASK,   PPC,            { RT, RA, RB } },
4129
4130 { "icbtlse", X(31,494), X_MASK,         PPCCHLK64,      { CT, RA, RB }},
4131
4132 { "slbia",   X(31,498), 0xffffffff,     PPC64,          { 0 } },
4133
4134 { "cli",     X(31,502), XRB_MASK,       POWER,          { RT, RA } },
4135
4136 { "stdcxe.", XRC(31,511,1), X_MASK,     BOOKE64,        { RS, RA, RB } },
4137
4138 { "mcrxr",   X(31,512), XRARB_MASK|(3<<21), COM,        { BF } },
4139
4140 { "bblels",  X(31,518), X_MASK,         PPCBRLK,        { 0 }},
4141 { "mcrxr64", X(31,544), XRARB_MASK|(3<<21), BOOKE64,    { BF } },
4142
4143 { "clcs",    X(31,531), XRB_MASK,       M601,           { RT, RA } },
4144
4145 { "lswx",    X(31,533), X_MASK,         PPCCOM,         { RT, RA, RB } },
4146 { "lsx",     X(31,533), X_MASK,         PWRCOM,         { RT, RA, RB } },
4147
4148 { "lwbrx",   X(31,534), X_MASK,         PPCCOM,         { RT, RA, RB } },
4149 { "lbrx",    X(31,534), X_MASK,         PWRCOM,         { RT, RA, RB } },
4150
4151 { "lfsx",    X(31,535), X_MASK,         COM,            { FRT, RA, RB } },
4152
4153 { "srw",     XRC(31,536,0), X_MASK,     PPCCOM,         { RA, RS, RB } },
4154 { "sr",      XRC(31,536,0), X_MASK,     PWRCOM,         { RA, RS, RB } },
4155 { "srw.",    XRC(31,536,1), X_MASK,     PPCCOM,         { RA, RS, RB } },
4156 { "sr.",     XRC(31,536,1), X_MASK,     PWRCOM,         { RA, RS, RB } },
4157
4158 { "rrib",    XRC(31,537,0), X_MASK,     M601,           { RA, RS, RB } },
4159 { "rrib.",   XRC(31,537,1), X_MASK,     M601,           { RA, RS, RB } },
4160
4161 { "srd",     XRC(31,539,0), X_MASK,     PPC64,          { RA, RS, RB } },
4162 { "srd.",    XRC(31,539,1), X_MASK,     PPC64,          { RA, RS, RB } },
4163
4164 { "maskir",  XRC(31,541,0), X_MASK,     M601,           { RA, RS, RB } },
4165 { "maskir.", XRC(31,541,1), X_MASK,     M601,           { RA, RS, RB } },
4166
4167 { "lwbrxe",  X(31,542), X_MASK,         BOOKE64,        { RT, RA, RB } },
4168
4169 { "lfsxe",   X(31,543), X_MASK,         BOOKE64,        { FRT, RA, RB } },
4170
4171 { "bbelr",   X(31,550), X_MASK,         PPCBRLK,        { 0 }},
4172 { "tlbsync", X(31,566), 0xffffffff,     PPC,            { 0 } },
4173
4174 { "lfsux",   X(31,567), X_MASK,         COM,            { FRT, RAS, RB } },
4175
4176 { "lfsuxe",  X(31,575), X_MASK,         BOOKE64,        { FRT, RAS, RB } },
4177
4178 { "mfsr",    X(31,595), XRB_MASK|(1<<20), COM32,        { RT, SR } },
4179
4180 { "lswi",    X(31,597), X_MASK,         PPCCOM,         { RT, RA, NB } },
4181 { "lsi",     X(31,597), X_MASK,         PWRCOM,         { RT, RA, NB } },
4182
4183 { "lwsync",  XSYNC(31,598,1), 0xffffffff, PPCONLY,      { 0 } },
4184 { "ptesync", XSYNC(31,598,2), 0xffffffff, PPC64,        { 0 } },
4185 { "sync",    X(31,598), XSYNC_MASK,     PPCCOM,         { LS } },
4186 { "dcs",     X(31,598), 0xffffffff,     PWRCOM,         { 0 } },
4187 { "msync",   X(31,598), 0xf80007fe,     BOOKE,          { 0 } },
4188
4189 { "lfdx",    X(31,599), X_MASK,         COM,            { FRT, RA, RB } },
4190
4191 { "lfdxe",   X(31,607), X_MASK,         BOOKE64,        { FRT, RA, RB } },
4192
4193 { "mfsri",   X(31,627), X_MASK,         PWRCOM,         { RT, RA, RB } },
4194
4195 { "dclst",   X(31,630), XRB_MASK,       PWRCOM,         { RS, RA } },
4196
4197 { "lfdux",   X(31,631), X_MASK,         COM,            { FRT, RAS, RB } },
4198
4199 { "lfduxe",  X(31,639), X_MASK,         BOOKE64,        { FRT, RAS, RB } },
4200
4201 { "mfsrin",  X(31,659), XRA_MASK,       PPC32,          { RT, RB } },
4202
4203 { "stswx",   X(31,661), X_MASK,         PPCCOM,         { RS, RA, RB } },
4204 { "stsx",    X(31,661), X_MASK,         PWRCOM,         { RS, RA, RB } },
4205
4206 { "stwbrx",  X(31,662), X_MASK,         PPCCOM,         { RS, RA, RB } },
4207 { "stbrx",   X(31,662), X_MASK,         PWRCOM,         { RS, RA, RB } },
4208
4209 { "stfsx",   X(31,663), X_MASK,         COM,            { FRS, RA, RB } },
4210
4211 { "srq",     XRC(31,664,0), X_MASK,     M601,           { RA, RS, RB } },
4212 { "srq.",    XRC(31,664,1), X_MASK,     M601,           { RA, RS, RB } },
4213
4214 { "sre",     XRC(31,665,0), X_MASK,     M601,           { RA, RS, RB } },
4215 { "sre.",    XRC(31,665,1), X_MASK,     M601,           { RA, RS, RB } },
4216
4217 { "stwbrxe", X(31,670), X_MASK,         BOOKE64,        { RS, RA, RB } },
4218
4219 { "stfsxe",  X(31,671), X_MASK,         BOOKE64,        { FRS, RA, RB } },
4220
4221 { "stfsux",  X(31,695), X_MASK,         COM,            { FRS, RAS, RB } },
4222
4223 { "sriq",    XRC(31,696,0), X_MASK,     M601,           { RA, RS, SH } },
4224 { "sriq.",   XRC(31,696,1), X_MASK,     M601,           { RA, RS, SH } },
4225
4226 { "stfsuxe", X(31,703), X_MASK,         BOOKE64,        { FRS, RAS, RB } },
4227
4228 { "stswi",   X(31,725), X_MASK,         PPCCOM,         { RS, RA, NB } },
4229 { "stsi",    X(31,725), X_MASK,         PWRCOM,         { RS, RA, NB } },
4230
4231 { "stfdx",   X(31,727), X_MASK,         COM,            { FRS, RA, RB } },
4232
4233 { "srlq",    XRC(31,728,0), X_MASK,     M601,           { RA, RS, RB } },
4234 { "srlq.",   XRC(31,728,1), X_MASK,     M601,           { RA, RS, RB } },
4235
4236 { "sreq",    XRC(31,729,0), X_MASK,     M601,           { RA, RS, RB } },
4237 { "sreq.",   XRC(31,729,1), X_MASK,     M601,           { RA, RS, RB } },
4238
4239 { "stfdxe",  X(31,735), X_MASK,         BOOKE64,        { FRS, RA, RB } },
4240
4241 { "dcba",    X(31,758), XRT_MASK,       PPC405,         { RA, RB } },
4242 { "dcba",    X(31,758), XRT_MASK,       BOOKE,          { RA, RB } },
4243
4244 { "stfdux",  X(31,759), X_MASK,         COM,            { FRS, RAS, RB } },
4245
4246 { "srliq",   XRC(31,760,0), X_MASK,     M601,           { RA, RS, SH } },
4247 { "srliq.",  XRC(31,760,1), X_MASK,     M601,           { RA, RS, SH } },
4248
4249 { "dcbae",   X(31,766), XRT_MASK,       BOOKE64,        { RA, RB } },
4250
4251 { "stfduxe", X(31,767), X_MASK,         BOOKE64,        { FRS, RAS, RB } },
4252
4253 { "tlbivax", X(31,786), XRT_MASK,       BOOKE,          { RA, RB } },
4254 { "tlbivaxe",X(31,787), XRT_MASK,       BOOKE64,        { RA, RB } },
4255
4256 { "lhbrx",   X(31,790), X_MASK,         COM,            { RT, RA, RB } },
4257
4258 { "sraw",    XRC(31,792,0), X_MASK,     PPCCOM,         { RA, RS, RB } },
4259 { "sra",     XRC(31,792,0), X_MASK,     PWRCOM,         { RA, RS, RB } },
4260 { "sraw.",   XRC(31,792,1), X_MASK,     PPCCOM,         { RA, RS, RB } },
4261 { "sra.",    XRC(31,792,1), X_MASK,     PWRCOM,         { RA, RS, RB } },
4262
4263 { "srad",    XRC(31,794,0), X_MASK,     PPC64,          { RA, RS, RB } },
4264 { "srad.",   XRC(31,794,1), X_MASK,     PPC64,          { RA, RS, RB } },
4265
4266 { "lhbrxe",  X(31,798), X_MASK,         BOOKE64,        { RT, RA, RB } },
4267
4268 { "ldxe",    X(31,799), X_MASK,         BOOKE64,        { RT, RA, RB } },
4269 { "lduxe",   X(31,831), X_MASK,         BOOKE64,        { RT, RA, RB } },
4270
4271 { "rac",     X(31,818), X_MASK,         PWRCOM,         { RT, RA, RB } },
4272
4273 { "dss",     XDSS(31,822,0), XDSS_MASK, PPCVEC,         { STRM } },
4274 { "dssall",  XDSS(31,822,1), XDSS_MASK, PPCVEC,         { 0 } },
4275
4276 { "srawi",   XRC(31,824,0), X_MASK,     PPCCOM,         { RA, RS, SH } },
4277 { "srai",    XRC(31,824,0), X_MASK,     PWRCOM,         { RA, RS, SH } },
4278 { "srawi.",  XRC(31,824,1), X_MASK,     PPCCOM,         { RA, RS, SH } },
4279 { "srai.",   XRC(31,824,1), X_MASK,     PWRCOM,         { RA, RS, SH } },
4280
4281 { "slbmfev", X(31,851), XRA_MASK,       PPC64,          { RT, RB } },
4282
4283 { "eieio",   X(31,854), 0xffffffff,     PPC,            { 0 } },
4284 { "mbar",    X(31,854), 0xffffffff,     BOOKE,          { MO } },
4285
4286 { "tlbsx",   XRC(31,914,0), X_MASK,     PPC403,         { RT, RA, RB } },
4287 { "tlbsx.",  XRC(31,914,1), X_MASK,     PPC403,         { RT, RA, RB } },
4288
4289 { "tlbsx",   XRC(31,914,0), X_MASK,     BOOKE,          { RA, RB } },
4290 { "tlbsx.",  XRC(31,914,1), X_MASK,     BOOKE,          { RA, RB } },
4291 { "tlbsxe",  XRC(31,915,0), X_MASK,     BOOKE64,        { RA, RB } },
4292 { "tlbsxe.", XRC(31,915,1), X_MASK,     BOOKE64,        { RA, RB } },
4293
4294 { "slbmfee", X(31,915), XRA_MASK,       PPC64,          { RT, RB } },
4295
4296 { "sthbrx",  X(31,918), X_MASK,         COM,            { RS, RA, RB } },
4297
4298 { "sraq",    XRC(31,920,0), X_MASK,     M601,           { RA, RS, RB } },
4299 { "sraq.",   XRC(31,920,1), X_MASK,     M601,           { RA, RS, RB } },
4300
4301 { "srea",    XRC(31,921,0), X_MASK,     M601,           { RA, RS, RB } },
4302 { "srea.",   XRC(31,921,1), X_MASK,     M601,           { RA, RS, RB } },
4303
4304 { "extsh",   XRC(31,922,0), XRB_MASK,   PPCCOM,         { RA, RS } },
4305 { "exts",    XRC(31,922,0), XRB_MASK,   PWRCOM,         { RA, RS } },
4306 { "extsh.",  XRC(31,922,1), XRB_MASK,   PPCCOM,         { RA, RS } },
4307 { "exts.",   XRC(31,922,1), XRB_MASK,   PWRCOM,         { RA, RS } },
4308
4309 { "sthbrxe", X(31,926), X_MASK,         BOOKE64,        { RS, RA, RB } },
4310
4311 { "stdxe",   X(31,927), X_MASK,         BOOKE64,        { RS, RA, RB } },
4312
4313 { "tlbre",   X(31,946), X_MASK,         BOOKE,          { 0 } },
4314
4315 { "tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403,         { RT, RA } },
4316 { "tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403,         { RT, RA } },
4317
4318 { "sraiq",   XRC(31,952,0), X_MASK,     M601,           { RA, RS, SH } },
4319 { "sraiq.",  XRC(31,952,1), X_MASK,     M601,           { RA, RS, SH } },
4320
4321 { "extsb",   XRC(31,954,0), XRB_MASK,   PPC,            { RA, RS} },
4322 { "extsb.",  XRC(31,954,1), XRB_MASK,   PPC,            { RA, RS} },
4323
4324 { "stduxe",  X(31,959), X_MASK,         BOOKE64,        { RS, RAS, RB } },
4325
4326 { "iccci",   X(31,966), XRT_MASK,       PPC403,         { RA, RB } },
4327
4328 { "tlbwe",   X(31,978), X_MASK,         BOOKE,          { 0 } },
4329
4330 { "tlbld",   X(31,978), XRTRA_MASK,     PPC,            { RB } },
4331
4332 { "tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403,         { RT, RA } },
4333 { "tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403,         { RT, RA } },
4334 { "tlbwe",   X(31,978), X_MASK,         PPC403,         { RS, RA, SH } },
4335
4336 { "icbi",    X(31,982), XRT_MASK,       PPC,            { RA, RB } },
4337
4338 { "stfiwx",  X(31,983), X_MASK,         PPC,            { FRS, RA, RB } },
4339
4340 { "extsw",   XRC(31,986,0), XRB_MASK,   PPC64 | BOOKE64,{ RA, RS } },
4341 { "extsw.",  XRC(31,986,1), XRB_MASK,   PPC64,          { RA, RS } },
4342
4343 { "icread",  X(31,998), XRT_MASK,       PPC403,         { RA, RB } },
4344
4345 { "icbie",   X(31,990), XRT_MASK,       BOOKE64,        { RA, RB } },
4346 { "stfiwxe", X(31,991), X_MASK,         BOOKE64,        { FRS, RA, RB } },
4347
4348 { "tlbli",   X(31,1010), XRTRA_MASK,    PPC,            { RB } },
4349
4350 { "dcbz",    X(31,1014), XRT_MASK,      PPC,            { RA, RB } },
4351 { "dclz",    X(31,1014), XRT_MASK,      PPC,            { RA, RB } },
4352
4353 { "dcbze",   X(31,1022), XRT_MASK,      BOOKE64,        { RA, RB } },
4354
4355 { "lvebx",   X(31,   7), X_MASK,        PPCVEC,         { VD, RA, RB } },
4356 { "lvehx",   X(31,  39), X_MASK,        PPCVEC,         { VD, RA, RB } },
4357 { "lvewx",   X(31,  71), X_MASK,        PPCVEC,         { VD, RA, RB } },
4358 { "lvsl",    X(31,   6), X_MASK,        PPCVEC,         { VD, RA, RB } },
4359 { "lvsr",    X(31,  38), X_MASK,        PPCVEC,         { VD, RA, RB } },
4360 { "lvx",     X(31, 103), X_MASK,        PPCVEC,         { VD, RA, RB } },
4361 { "lvxl",    X(31, 359), X_MASK,        PPCVEC,         { VD, RA, RB } },
4362 { "stvebx",  X(31, 135), X_MASK,        PPCVEC,         { VS, RA, RB } },
4363 { "stvehx",  X(31, 167), X_MASK,        PPCVEC,         { VS, RA, RB } },
4364 { "stvewx",  X(31, 199), X_MASK,        PPCVEC,         { VS, RA, RB } },
4365 { "stvx",    X(31, 231), X_MASK,        PPCVEC,         { VS, RA, RB } },
4366 { "stvxl",   X(31, 487), X_MASK,        PPCVEC,         { VS, RA, RB } },
4367
4368 { "lwz",     OP(32),    OP_MASK,        PPCCOM,         { RT, D, RA } },
4369 { "l",       OP(32),    OP_MASK,        PWRCOM,         { RT, D, RA } },
4370
4371 { "lwzu",    OP(33),    OP_MASK,        PPCCOM,         { RT, D, RAL } },
4372 { "lu",      OP(33),    OP_MASK,        PWRCOM,         { RT, D, RA } },
4373
4374 { "lbz",     OP(34),    OP_MASK,        COM,            { RT, D, RA } },
4375
4376 { "lbzu",    OP(35),    OP_MASK,        COM,            { RT, D, RAL } },
4377
4378 { "stw",     OP(36),    OP_MASK,        PPCCOM,         { RS, D, RA } },
4379 { "st",      OP(36),    OP_MASK,        PWRCOM,         { RS, D, RA } },
4380
4381 { "stwu",    OP(37),    OP_MASK,        PPCCOM,         { RS, D, RAS } },
4382 { "stu",     OP(37),    OP_MASK,        PWRCOM,         { RS, D, RA } },
4383
4384 { "stb",     OP(38),    OP_MASK,        COM,            { RS, D, RA } },
4385
4386 { "stbu",    OP(39),    OP_MASK,        COM,            { RS, D, RAS } },
4387
4388 { "lhz",     OP(40),    OP_MASK,        COM,            { RT, D, RA } },
4389
4390 { "lhzu",    OP(41),    OP_MASK,        COM,            { RT, D, RAL } },
4391
4392 { "lha",     OP(42),    OP_MASK,        COM,            { RT, D, RA } },
4393
4394 { "lhau",    OP(43),    OP_MASK,        COM,            { RT, D, RAL } },
4395
4396 { "sth",     OP(44),    OP_MASK,        COM,            { RS, D, RA } },
4397
4398 { "sthu",    OP(45),    OP_MASK,        COM,            { RS, D, RAS } },
4399
4400 { "lmw",     OP(46),    OP_MASK,        PPCCOM,         { RT, D, RAM } },
4401 { "lm",      OP(46),    OP_MASK,        PWRCOM,         { RT, D, RA } },
4402
4403 { "stmw",    OP(47),    OP_MASK,        PPCCOM,         { RS, D, RA } },
4404 { "stm",     OP(47),    OP_MASK,        PWRCOM,         { RS, D, RA } },
4405
4406 { "lfs",     OP(48),    OP_MASK,        COM,            { FRT, D, RA } },
4407
4408 { "lfsu",    OP(49),    OP_MASK,        COM,            { FRT, D, RAS } },
4409
4410 { "lfd",     OP(50),    OP_MASK,        COM,            { FRT, D, RA } },
4411
4412 { "lfdu",    OP(51),    OP_MASK,        COM,            { FRT, D, RAS } },
4413
4414 { "stfs",    OP(52),    OP_MASK,        COM,            { FRS, D, RA } },
4415
4416 { "stfsu",   OP(53),    OP_MASK,        COM,            { FRS, D, RAS } },
4417
4418 { "stfd",    OP(54),    OP_MASK,        COM,            { FRS, D, RA } },
4419
4420 { "stfdu",   OP(55),    OP_MASK,        COM,            { FRS, D, RAS } },
4421
4422 { "lfq",     OP(56),    OP_MASK,        POWER2,         { FRT, D, RA } },
4423
4424 { "lfqu",    OP(57),    OP_MASK,        POWER2,         { FRT, D, RA } },
4425
4426 { "lbze",    DEO(58,0), DE_MASK,        BOOKE64,        { RT, DE, RA } },
4427 { "lbzue",   DEO(58,1), DE_MASK,        BOOKE64,        { RT, DE, RAL } },
4428 { "lhze",    DEO(58,2), DE_MASK,        BOOKE64,        { RT, DE, RA } },
4429 { "lhzue",   DEO(58,3), DE_MASK,        BOOKE64,        { RT, DE, RAL } },
4430 { "lhae",    DEO(58,4), DE_MASK,        BOOKE64,        { RT, DE, RA } },
4431 { "lhaue",   DEO(58,5), DE_MASK,        BOOKE64,        { RT, DE, RAL } },
4432 { "lwze",    DEO(58,6), DE_MASK,        BOOKE64,        { RT, DE, RA } },
4433 { "lwzue",   DEO(58,7), DE_MASK,        BOOKE64,        { RT, DE, RAL } },
4434 { "stbe",    DEO(58,8), DE_MASK,        BOOKE64,        { RS, DE, RA } },
4435 { "stbue",   DEO(58,9), DE_MASK,        BOOKE64,        { RS, DE, RAS } },
4436 { "sthe",    DEO(58,10), DE_MASK,       BOOKE64,        { RS, DE, RA } },
4437 { "sthue",   DEO(58,11), DE_MASK,       BOOKE64,        { RS, DE, RAS } },
4438 { "stwe",    DEO(58,14), DE_MASK,       BOOKE64,        { RS, DE, RA } },
4439 { "stwue",   DEO(58,15), DE_MASK,       BOOKE64,        { RS, DE, RAS } },
4440
4441 { "ld",      DSO(58,0), DS_MASK,        PPC64,          { RT, DS, RA } },
4442
4443 { "ldu",     DSO(58,1), DS_MASK,        PPC64,          { RT, DS, RAL } },
4444
4445 { "lwa",     DSO(58,2), DS_MASK,        PPC64,          { RT, DS, RA } },
4446
4447 { "fdivs",   A(59,18,0), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
4448 { "fdivs.",  A(59,18,1), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
4449
4450 { "fsubs",   A(59,20,0), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
4451 { "fsubs.",  A(59,20,1), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
4452
4453 { "fadds",   A(59,21,0), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
4454 { "fadds.",  A(59,21,1), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
4455
4456 { "fsqrts",  A(59,22,0), AFRAFRC_MASK,  PPC,            { FRT, FRB } },
4457 { "fsqrts.", A(59,22,1), AFRAFRC_MASK,  PPC,            { FRT, FRB } },
4458
4459 { "fres",    A(59,24,0), AFRAFRC_MASK,  PPC,            { FRT, FRB } },
4460 { "fres.",   A(59,24,1), AFRAFRC_MASK,  PPC,            { FRT, FRB } },
4461
4462 { "fmuls",   A(59,25,0), AFRB_MASK,     PPC,            { FRT, FRA, FRC } },
4463 { "fmuls.",  A(59,25,1), AFRB_MASK,     PPC,            { FRT, FRA, FRC } },
4464
4465 { "fmsubs",  A(59,28,0), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
4466 { "fmsubs.", A(59,28,1), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
4467
4468 { "fmadds",  A(59,29,0), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
4469 { "fmadds.", A(59,29,1), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
4470
4471 { "fnmsubs", A(59,30,0), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
4472 { "fnmsubs.",A(59,30,1), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
4473
4474 { "fnmadds", A(59,31,0), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
4475 { "fnmadds.",A(59,31,1), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
4476
4477 { "stfq",    OP(60),    OP_MASK,        POWER2,         { FRS, D, RA } },
4478
4479 { "stfqu",   OP(61),    OP_MASK,        POWER2,         { FRS, D, RA } },
4480
4481 { "lde",     DEO(62,0), DE_MASK,        BOOKE64,        { RT, DES, RA } },
4482 { "ldue",    DEO(62,1), DE_MASK,        BOOKE64,        { RT, DES, RA } },
4483 { "lfse",    DEO(62,4), DE_MASK,        BOOKE64,        { FRT, DES, RA } },
4484 { "lfsue",   DEO(62,5), DE_MASK,        BOOKE64,        { FRT, DES, RAS } },
4485 { "lfde",    DEO(62,6), DE_MASK,        BOOKE64,        { FRT, DES, RA } },
4486 { "lfdue",   DEO(62,7), DE_MASK,        BOOKE64,        { FRT, DES, RAS } },
4487 { "stde",    DEO(62,8), DE_MASK,        BOOKE64,        { RS, DES, RA } },
4488 { "stdue",   DEO(62,9), DE_MASK,        BOOKE64,        { RS, DES, RAS } },
4489 { "stfse",   DEO(62,12), DE_MASK,       BOOKE64,        { FRS, DES, RA } },
4490 { "stfsue",  DEO(62,13), DE_MASK,       BOOKE64,        { FRS, DES, RAS } },
4491 { "stfde",   DEO(62,14), DE_MASK,       BOOKE64,        { FRS, DES, RA } },
4492 { "stfdue",  DEO(62,15), DE_MASK,       BOOKE64,        { FRS, DES, RAS } },
4493
4494 { "std",     DSO(62,0), DS_MASK,        PPC64,          { RS, DS, RA } },
4495
4496 { "stdu",    DSO(62,1), DS_MASK,        PPC64,          { RS, DS, RAS } },
4497
4498 { "fcmpu",   X(63,0),   X_MASK|(3<<21), COM,            { BF, FRA, FRB } },
4499
4500 { "frsp",    XRC(63,12,0), XRA_MASK,    COM,            { FRT, FRB } },
4501 { "frsp.",   XRC(63,12,1), XRA_MASK,    COM,            { FRT, FRB } },
4502
4503 { "fctiw",   XRC(63,14,0), XRA_MASK,    PPCCOM,         { FRT, FRB } },
4504 { "fcir",    XRC(63,14,0), XRA_MASK,    POWER2,         { FRT, FRB } },
4505 { "fctiw.",  XRC(63,14,1), XRA_MASK,    PPCCOM,         { FRT, FRB } },
4506 { "fcir.",   XRC(63,14,1), XRA_MASK,    POWER2,         { FRT, FRB } },
4507
4508 { "fctiwz",  XRC(63,15,0), XRA_MASK,    PPCCOM,         { FRT, FRB } },
4509 { "fcirz",   XRC(63,15,0), XRA_MASK,    POWER2,         { FRT, FRB } },
4510 { "fctiwz.", XRC(63,15,1), XRA_MASK,    PPCCOM,         { FRT, FRB } },
4511 { "fcirz.",  XRC(63,15,1), XRA_MASK,    POWER2,         { FRT, FRB } },
4512
4513 { "fdiv",    A(63,18,0), AFRC_MASK,     PPCCOM,         { FRT, FRA, FRB } },
4514 { "fd",      A(63,18,0), AFRC_MASK,     PWRCOM,         { FRT, FRA, FRB } },
4515 { "fdiv.",   A(63,18,1), AFRC_MASK,     PPCCOM,         { FRT, FRA, FRB } },
4516 { "fd.",     A(63,18,1), AFRC_MASK,     PWRCOM,         { FRT, FRA, FRB } },
4517
4518 { "fsub",    A(63,20,0), AFRC_MASK,     PPCCOM,         { FRT, FRA, FRB } },
4519 { "fs",      A(63,20,0), AFRC_MASK,     PWRCOM,         { FRT, FRA, FRB } },
4520 { "fsub.",   A(63,20,1), AFRC_MASK,     PPCCOM,         { FRT, FRA, FRB } },
4521 { "fs.",     A(63,20,1), AFRC_MASK,     PWRCOM,         { FRT, FRA, FRB } },
4522
4523 { "fadd",    A(63,21,0), AFRC_MASK,     PPCCOM,         { FRT, FRA, FRB } },
4524 { "fa",      A(63,21,0), AFRC_MASK,     PWRCOM,         { FRT, FRA, FRB } },
4525 { "fadd.",   A(63,21,1), AFRC_MASK,     PPCCOM,         { FRT, FRA, FRB } },
4526 { "fa.",     A(63,21,1), AFRC_MASK,     PWRCOM,         { FRT, FRA, FRB } },
4527
4528 { "fsqrt",   A(63,22,0), AFRAFRC_MASK,  PPCPWR2,        { FRT, FRB } },
4529 { "fsqrt.",  A(63,22,1), AFRAFRC_MASK,  PPCPWR2,        { FRT, FRB } },
4530
4531 { "fsel",    A(63,23,0), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
4532 { "fsel.",   A(63,23,1), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
4533
4534 { "fmul",    A(63,25,0), AFRB_MASK,     PPCCOM,         { FRT, FRA, FRC } },
4535 { "fm",      A(63,25,0), AFRB_MASK,     PWRCOM,         { FRT, FRA, FRC } },
4536 { "fmul.",   A(63,25,1), AFRB_MASK,     PPCCOM,         { FRT, FRA, FRC } },
4537 { "fm.",     A(63,25,1), AFRB_MASK,     PWRCOM,         { FRT, FRA, FRC } },
4538
4539 { "frsqrte", A(63,26,0), AFRAFRC_MASK,  PPC,            { FRT, FRB } },
4540 { "frsqrte.",A(63,26,1), AFRAFRC_MASK,  PPC,            { FRT, FRB } },
4541
4542 { "fmsub",   A(63,28,0), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
4543 { "fms",     A(63,28,0), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
4544 { "fmsub.",  A(63,28,1), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
4545 { "fms.",    A(63,28,1), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
4546
4547 { "fmadd",   A(63,29,0), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
4548 { "fma",     A(63,29,0), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
4549 { "fmadd.",  A(63,29,1), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
4550 { "fma.",    A(63,29,1), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
4551
4552 { "fnmsub",  A(63,30,0), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
4553 { "fnms",    A(63,30,0), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
4554 { "fnmsub.", A(63,30,1), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
4555 { "fnms.",   A(63,30,1), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
4556
4557 { "fnmadd",  A(63,31,0), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
4558 { "fnma",    A(63,31,0), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
4559 { "fnmadd.", A(63,31,1), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
4560 { "fnma.",   A(63,31,1), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
4561
4562 { "fcmpo",   X(63,32),  X_MASK|(3<<21), COM,            { BF, FRA, FRB } },
4563
4564 { "mtfsb1",  XRC(63,38,0), XRARB_MASK,  COM,            { BT } },
4565 { "mtfsb1.", XRC(63,38,1), XRARB_MASK,  COM,            { BT } },
4566
4567 { "fneg",    XRC(63,40,0), XRA_MASK,    COM,            { FRT, FRB } },
4568 { "fneg.",   XRC(63,40,1), XRA_MASK,    COM,            { FRT, FRB } },
4569
4570 { "mcrfs",   X(63,64),  XRB_MASK|(3<<21)|(3<<16), COM,  { BF, BFA } },
4571
4572 { "mtfsb0",  XRC(63,70,0), XRARB_MASK,  COM,            { BT } },
4573 { "mtfsb0.", XRC(63,70,1), XRARB_MASK,  COM,            { BT } },
4574
4575 { "fmr",     XRC(63,72,0), XRA_MASK,    COM,            { FRT, FRB } },
4576 { "fmr.",    XRC(63,72,1), XRA_MASK,    COM,            { FRT, FRB } },
4577
4578 { "mtfsfi",  XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } },
4579 { "mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } },
4580
4581 { "fnabs",   XRC(63,136,0), XRA_MASK,   COM,            { FRT, FRB } },
4582 { "fnabs.",  XRC(63,136,1), XRA_MASK,   COM,            { FRT, FRB } },
4583
4584 { "fabs",    XRC(63,264,0), XRA_MASK,   COM,            { FRT, FRB } },
4585 { "fabs.",   XRC(63,264,1), XRA_MASK,   COM,            { FRT, FRB } },
4586
4587 { "mffs",    XRC(63,583,0), XRARB_MASK, COM,            { FRT } },
4588 { "mffs.",   XRC(63,583,1), XRARB_MASK, COM,            { FRT } },
4589
4590 { "mtfsf",   XFL(63,711,0), XFL_MASK,   COM,            { FLM, FRB } },
4591 { "mtfsf.",  XFL(63,711,1), XFL_MASK,   COM,            { FLM, FRB } },
4592
4593 { "fctid",   XRC(63,814,0), XRA_MASK,   PPC64,          { FRT, FRB } },
4594 { "fctid.",  XRC(63,814,1), XRA_MASK,   PPC64,          { FRT, FRB } },
4595
4596 { "fctidz",  XRC(63,815,0), XRA_MASK,   PPC64,          { FRT, FRB } },
4597 { "fctidz.", XRC(63,815,1), XRA_MASK,   PPC64,          { FRT, FRB } },
4598
4599 { "fcfid",   XRC(63,846,0), XRA_MASK,   PPC64,          { FRT, FRB } },
4600 { "fcfid.",  XRC(63,846,1), XRA_MASK,   PPC64,          { FRT, FRB } },
4601
4602 };
4603
4604 const int powerpc_num_opcodes =
4605   sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]);
4606 \f
4607 /* The macro table.  This is only used by the assembler.  */
4608
4609 /* The expressions of the form (-x ! 31) & (x | 31) have the value 0
4610    when x=0; 32-x when x is between 1 and 31; are negative if x is
4611    negative; and are 32 or more otherwise.  This is what you want
4612    when, for instance, you are emulating a right shift by a
4613    rotate-left-and-mask, because the underlying instructions support
4614    shifts of size 0 but not shifts of size 32.  By comparison, when
4615    extracting x bits from some word you want to use just 32-x, because
4616    the underlying instructions don't support extracting 0 bits but do
4617    support extracting the whole word (32 bits in this case).  */
4618
4619 const struct powerpc_macro powerpc_macros[] = {
4620 { "extldi",  4,   PPC64,        "rldicr %0,%1,%3,(%2)-1" },
4621 { "extldi.", 4,   PPC64,        "rldicr. %0,%1,%3,(%2)-1" },
4622 { "extrdi",  4,   PPC64,        "rldicl %0,%1,(%2)+(%3),64-(%2)" },
4623 { "extrdi.", 4,   PPC64,        "rldicl. %0,%1,(%2)+(%3),64-(%2)" },
4624 { "insrdi",  4,   PPC64,        "rldimi %0,%1,64-((%2)+(%3)),%3" },
4625 { "insrdi.", 4,   PPC64,        "rldimi. %0,%1,64-((%2)+(%3)),%3" },
4626 { "rotrdi",  3,   PPC64,        "rldicl %0,%1,(-(%2)!63)&((%2)|63),0" },
4627 { "rotrdi.", 3,   PPC64,        "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0" },
4628 { "sldi",    3,   PPC64,        "rldicr %0,%1,%2,63-(%2)" },
4629 { "sldi.",   3,   PPC64,        "rldicr. %0,%1,%2,63-(%2)" },
4630 { "srdi",    3,   PPC64,        "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2" },
4631 { "srdi.",   3,   PPC64,        "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2" },
4632 { "clrrdi",  3,   PPC64,        "rldicr %0,%1,0,63-(%2)" },
4633 { "clrrdi.", 3,   PPC64,        "rldicr. %0,%1,0,63-(%2)" },
4634 { "clrlsldi",4,   PPC64,        "rldic %0,%1,%3,(%2)-(%3)" },
4635 { "clrlsldi.",4,  PPC64,        "rldic. %0,%1,%3,(%2)-(%3)" },
4636
4637 { "extlwi",  4,   PPCCOM,       "rlwinm %0,%1,%3,0,(%2)-1" },
4638 { "extlwi.", 4,   PPCCOM,       "rlwinm. %0,%1,%3,0,(%2)-1" },
4639 { "extrwi",  4,   PPCCOM,       "rlwinm %0,%1,(%2)+(%3),32-(%2),31" },
4640 { "extrwi.", 4,   PPCCOM,       "rlwinm. %0,%1,(%2)+(%3),32-(%2),31" },
4641 { "inslwi",  4,   PPCCOM,       "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1" },
4642 { "inslwi.", 4,   PPCCOM,       "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
4643 { "insrwi",  4,   PPCCOM,       "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1" },
4644 { "insrwi.", 4,   PPCCOM,       "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
4645 { "rotrwi",  3,   PPCCOM,       "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31" },
4646 { "rotrwi.", 3,   PPCCOM,       "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31" },
4647 { "slwi",    3,   PPCCOM,       "rlwinm %0,%1,%2,0,31-(%2)" },
4648 { "sli",     3,   PWRCOM,       "rlinm %0,%1,%2,0,31-(%2)" },
4649 { "slwi.",   3,   PPCCOM,       "rlwinm. %0,%1,%2,0,31-(%2)" },
4650 { "sli.",    3,   PWRCOM,       "rlinm. %0,%1,%2,0,31-(%2)" },
4651 { "srwi",    3,   PPCCOM,       "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4652 { "sri",     3,   PWRCOM,       "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4653 { "srwi.",   3,   PPCCOM,       "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4654 { "sri.",    3,   PWRCOM,       "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4655 { "clrrwi",  3,   PPCCOM,       "rlwinm %0,%1,0,0,31-(%2)" },
4656 { "clrrwi.", 3,   PPCCOM,       "rlwinm. %0,%1,0,0,31-(%2)" },
4657 { "clrlslwi",4,   PPCCOM,       "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)" },
4658 { "clrlslwi.",4,  PPCCOM,       "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)" },
4659 };
4660
4661 const int powerpc_num_macros =
4662   sizeof (powerpc_macros) / sizeof (powerpc_macros[0]);