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[binutils.git] / opcodes / sh64-opc.c
blob206aeb30848e75438e089c699349df13c8222655
1 /* Definitions for SH64 opcodes.
2 Copyright (C) 2000, 2001, 2002 Free Software Foundation, Inc.
4 This program is free software; you can redistribute it and/or modify
5 it under the terms of the GNU General Public License as published by
6 the Free Software Foundation; either version 2 of the License, or
7 (at your option) any later version.
9 This program is distributed in the hope that it will be useful,
10 but WITHOUT ANY WARRANTY; without even the implied warranty of
11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 GNU General Public License for more details.
14 You should have received a copy of the GNU General Public License
15 along with this program; if not, write to the Free Software
16 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
18 #include "sh64-opc.h"
19 #include <stdio.h>
21 /* Users currently assume that no mnemonic appears twice. For
22 disassembly, the first complete match is displayed. */
23 const shmedia_opcode_info shmedia_table[] = {
25 /* 000000mmmmmm1001nnnnnndddddd0000 add <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
26 { "add", {A_GREG_M,A_GREG_N,A_GREG_D},
27 {OFFSET_20,OFFSET_10,OFFSET_4}, SHMEDIA_ADD_OPC
29 /* 000000mmmmmm1000nnnnnndddddd0000 add.l <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
30 { "add.l", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x00080000
32 /* 110100mmmmmmssssssssssdddddd0000 addi <A_GREG_M>,<A_IMMS10>,<A_GREG_D> */
33 { "addi", {A_GREG_M,A_IMMS10BY1,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4},
34 SHMEDIA_ADDI_OPC
36 /* 110101mmmmmmssssssssssdddddd0000 addi.l <A_GREG_M>,<A_IMMS10>,<A_GREG_D> */
37 { "addi.l", {A_GREG_M,A_IMMS10BY1,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xd4000000
39 /* 000000mmmmmm1100nnnnnndddddd0000 addz.l <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
40 { "addz.l", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x000c0000
42 /* 111000mmmmmm0100ssssss1111110000 alloco <A_GREG_M>,<A_IMMS6BY32> */
43 { "alloco", {A_GREG_M,A_IMMS6BY32}, {OFFSET_20,OFFSET_10}, 0xe00403f0
45 /* 000001mmmmmm1011nnnnnndddddd0000 and <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
46 { "and", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x040b0000
48 /* 000001mmmmmm1111nnnnnndddddd0000 andc <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
49 { "andc", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x040f0000
51 /* 110110mmmmmmssssssssssdddddd0000 andi <A_GREG_M>,<A_IMMS10>,<A_GREG_D> */
52 { "andi", {A_GREG_M,A_IMMS10,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xd8000000
54 /* 011001mmmmmm0001nnnnnnl00ccc0000 beq <A_GREG_M>,<A_GREG_N>,<A_TREG_A> */
55 { "beq/l", {A_GREG_M,A_GREG_N,A_TREG_A}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x64010200
57 /* 011001mmmmmm0001nnnnnnl00ccc0000 beq <A_GREG_M>,<A_GREG_N>,<A_TREG_A> */
58 { "beq", {A_GREG_M,A_GREG_N,A_TREG_A}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x64010200
60 /* 011001mmmmmm0001nnnnnn000ccc0000 beq/u <A_GREG_M>,<A_GREG_N>,<A_TREG_A> */
61 { "beq/u", {A_GREG_M,A_GREG_N,A_TREG_A}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x64010000
63 /* 111001mmmmmm0001ssssssl00ccc0000 beqi <A_GREG_M>,<A_IMMS6>,<A_TREG_A> */
64 { "beqi/l", {A_GREG_M,A_IMMS6,A_TREG_A}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xe4010200
66 /* 111001mmmmmm0001ssssssl00ccc0000 beqi <A_GREG_M>,<A_IMMS6>,<A_TREG_A> */
67 { "beqi", {A_GREG_M,A_IMMS6,A_TREG_A}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xe4010200
69 /* 111001mmmmmm0001ssssss000ccc0000 beqi/u <A_GREG_M>,<A_IMMS6>,<A_TREG_A> */
70 { "beqi/u", {A_GREG_M,A_IMMS6,A_TREG_A}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xe4010000
72 /* 011001mmmmmm0011nnnnnnl00ccc0000 bge <A_GREG_M>,<A_GREG_N>,<A_TREG_A> */
73 { "bge/l", {A_GREG_M,A_GREG_N,A_TREG_A}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x64030200
75 /* 011001mmmmmm0011nnnnnnl00ccc0000 bge <A_GREG_M>,<A_GREG_N>,<A_TREG_A> */
76 { "bge", {A_GREG_M,A_GREG_N,A_TREG_A}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x64030200
78 /* 011001mmmmmm0011nnnnnn000ccc0000 bge/u <A_GREG_M>,<A_GREG_N>,<A_TREG_A> */
79 { "bge/u", {A_GREG_M,A_GREG_N,A_TREG_A}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x64030000
81 /* 011001mmmmmm1011nnnnnnl00ccc0000 bgeu <A_GREG_M>,<A_GREG_N>,<A_TREG_A> */
82 { "bgeu/l", {A_GREG_M,A_GREG_N,A_TREG_A}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x640b0200
84 /* 011001mmmmmm1011nnnnnnl00ccc0000 bgeu <A_GREG_M>,<A_GREG_N>,<A_TREG_A> */
85 { "bgeu", {A_GREG_M,A_GREG_N,A_TREG_A}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x640b0200
87 /* 011001mmmmmm1011nnnnnn000ccc0000 bgeu/u <A_GREG_M>,<A_GREG_N>,<A_TREG_A> */
88 { "bgeu/u", {A_GREG_M,A_GREG_N,A_TREG_A}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x640b0000
90 /* 011001mmmmmm0111nnnnnnl00ccc0000 bgt <A_GREG_M>,<A_GREG_N>,<A_TREG_A> */
91 { "bgt/l", {A_GREG_M,A_GREG_N,A_TREG_A}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x64070200
93 /* 011001mmmmmm0111nnnnnnl00ccc0000 bgt <A_GREG_M>,<A_GREG_N>,<A_TREG_A> */
94 { "bgt", {A_GREG_M,A_GREG_N,A_TREG_A}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x64070200
96 /* 011001mmmmmm0111nnnnnn000ccc0000 bgt/u <A_GREG_M>,<A_GREG_N>,<A_TREG_A> */
97 { "bgt/u", {A_GREG_M,A_GREG_N,A_TREG_A}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x64070000
99 /* 011001mmmmmm1111nnnnnnl00ccc0000 bgtu <A_GREG_M>,<A_GREG_N>,<A_TREG_A> */
100 { "bgtu/l", {A_GREG_M,A_GREG_N,A_TREG_A}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x640f0200
102 /* 011001mmmmmm1111nnnnnnl00ccc0000 bgtu <A_GREG_M>,<A_GREG_N>,<A_TREG_A> */
103 { "bgtu", {A_GREG_M,A_GREG_N,A_TREG_A}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x640f0200
105 /* 011001mmmmmm1111nnnnnn000ccc0000 bgtu/u <A_GREG_M>,<A_GREG_N>,<A_TREG_A> */
106 { "bgtu/u", {A_GREG_M,A_GREG_N,A_TREG_A}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x640f0000
108 /* 010001000bbb0001111111dddddd0000 blink <A_TREG_B>,<A_GREG_D> */
109 { "blink", {A_TREG_B,A_GREG_D}, {OFFSET_20,OFFSET_4}, 0x4401fc00
111 /* 011001mmmmmm0101nnnnnnl00ccc0000 bne <A_GREG_M>,<A_GREG_N>,<A_TREG_A> */
112 { "bne/l", {A_GREG_M,A_GREG_N,A_TREG_A}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x64050200
114 /* 011001mmmmmm0101nnnnnnl00ccc0000 bne <A_GREG_M>,<A_GREG_N>,<A_TREG_A> */
115 { "bne", {A_GREG_M,A_GREG_N,A_TREG_A}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x64050200
117 /* 011001mmmmmm0101nnnnnn000ccc0000 bne/u <A_GREG_M>,<A_GREG_N>,<A_TREG_A> */
118 { "bne/u", {A_GREG_M,A_GREG_N,A_TREG_A}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x64050000
120 /* 111001mmmmmm0101ssssssl00ccc0000 bnei <A_GREG_M>,<A_IMMS6>,<A_TREG_A> */
121 { "bnei/l", {A_GREG_M,A_IMMS6,A_TREG_A}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xe4050200
123 /* 111001mmmmmm0101ssssssl00ccc0000 bnei <A_GREG_M>,<A_IMMS6>,<A_TREG_A> */
124 { "bnei", {A_GREG_M,A_IMMS6,A_TREG_A}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xe4050200
126 /* 111001mmmmmm0101ssssss000ccc0000 bnei/u <A_GREG_M>,<A_IMMS6>,<A_TREG_A> */
127 { "bnei/u", {A_GREG_M,A_IMMS6,A_TREG_A}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xe4050000
129 /* 01101111111101011111111111110000 brk */
130 { "brk", {A_NONE}, {OFFSET_NONE}, 0x6ff5fff0
132 /* 000000mmmmmm1111111111dddddd0000 byterev <A_GREG_M>,<A_GREG_D> */
133 { "byterev", {A_GREG_M,A_GREG_D}, {OFFSET_20,OFFSET_4}, 0x000ffc00
135 /* 000000mmmmmm0001nnnnnndddddd0000 cmpeq <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
136 { "cmpeq", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x00010000
138 /* 000000mmmmmm0011nnnnnndddddd0000 cmpgt <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
139 { "cmpgt", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x00030000
141 /* 000000mmmmmm0111nnnnnndddddd0000 cmpgtu <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
142 { "cmpgtu", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x00070000
144 /* 001000mmmmmm0001nnnnnnwwwwww0000 cmveq <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
145 { "cmveq", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x20010000
147 /* 001000mmmmmm0101nnnnnnwwwwww0000 cmvne <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
148 { "cmvne", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x20050000
150 /* 000110gggggg0001ggggggffffff0000 fabs.d <A_DREG_G>,<A_DREG_F> */
151 { "fabs.d", {A_DREG_G,A_REUSE_PREV,A_DREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x18010000
153 /* 000110gggggg0000ggggggffffff0000 fabs.s <A_FREG_G>,<A_FREG_F> */
154 { "fabs.s", {A_FREG_G,A_REUSE_PREV,A_FREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x18000000
156 /* 001101gggggg0001hhhhhhffffff0000 fadd.s <A_DREG_G>,<A_DREG_H>,<A_DREG_F> */
157 { "fadd.d", {A_DREG_G,A_DREG_H,A_DREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x34010000
159 /* 001101gggggg0000hhhhhhffffff0000 fadd.s <A_FREG_G>,<A_FREG_H>,<A_FREG_F> */
160 { "fadd.s", {A_FREG_G,A_FREG_H,A_FREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x34000000
162 /* 001100gggggg1001hhhhhhdddddd0000 fcmpeq.s <A_DREG_G>,<A_DREG_H>,<A_GREG_D> */
163 { "fcmpeq.d", {A_DREG_G,A_DREG_H,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x30090000
165 /* 001100gggggg1000hhhhhhdddddd0000 fcmpeq.s <A_FREG_G>,<A_FREG_H>,<A_GREG_D> */
166 { "fcmpeq.s", {A_FREG_G,A_FREG_H,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x30080000
168 /* 001100gggggg1111hhhhhhdddddd0000 fcmpge.d <A_DREG_G>,<A_DREG_H>,<A_GREG_D> */
169 { "fcmpge.d", {A_DREG_G,A_DREG_H,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x300f0000
171 /* 001100gggggg1110hhhhhhdddddd0000 fcmpge.s <A_FREG_G>,<A_FREG_H>,<A_GREG_D> */
172 { "fcmpge.s", {A_FREG_G,A_FREG_H,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x300e0000
174 /* 001100gggggg1101hhhhhhdddddd0000 fcmpgt.d <A_DREG_G>,<A_DREG_H>,<A_GREG_D> */
175 { "fcmpgt.d", {A_DREG_G,A_DREG_H,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x300d0000
177 /* 001100gggggg1100hhhhhhdddddd0000 fcmpgt.s <A_FREG_G>,<A_FREG_H>,<A_GREG_D> */
178 { "fcmpgt.s", {A_FREG_G,A_FREG_H,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x300c0000
180 /* 001100gggggg1011hhhhhhdddddd0000 fcmpun.d <A_DREG_G>,<A_DREG_H>,<A_GREG_D> */
181 { "fcmpun.d", {A_DREG_G,A_DREG_H,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x300b0000
183 /* 001100gggggg1010hhhhhhdddddd0000 fcmpun.s <A_FREG_G>,<A_FREG_H>,<A_GREG_D> */
184 { "fcmpun.s", {A_FREG_G,A_FREG_H,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x300a0000
186 /* 001110gggggg0111ggggggffffff0000 fcnv.ds <A_DREG_G>,<A_FREG_F> */
187 { "fcnv.ds", {A_DREG_G,A_REUSE_PREV,A_FREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x38070000
189 /* 001110gggggg0110ggggggffffff0000 fcnv.sd <A_FREG_G>,<A_DREG_F> */
190 { "fcnv.sd", {A_FREG_G,A_REUSE_PREV,A_DREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x38060000
192 /* 001101gggggg0101hhhhhhffffff0000 fdiv.d <A_DREG_G>,<A_DREG_H>,<A_DREG_F> */
193 { "fdiv.d", {A_DREG_G,A_DREG_H,A_DREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x34050000
195 /* 001101gggggg0100hhhhhhffffff0000 fdiv.s <A_FREG_G>,<A_FREG_H>,<A_FREG_F> */
196 { "fdiv.s", {A_FREG_G,A_FREG_H,A_FREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x34040000
198 /* 0001111111110010111111ffffff0000 fgetscr <A_FREG_F> */
199 { "fgetscr", {A_FREG_F}, {OFFSET_4}, 0x1ff2fc00
201 /* 000101gggggg0110hhhhhhffffff0000 fipr.s <A_FVREG_G>,<A_FVREG_H>,<A_FREG_F> */
202 { "fipr.s", {A_FVREG_G,A_FVREG_H,A_FREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x14060000
204 /* 100111mmmmmmssssssssssffffff0000 fld.d <A_GREG_M>,<A_IMMS10BY8>,<A_DREG_F> */
205 { "fld.d", {A_GREG_M,A_IMMS10BY8,A_DREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x9c000000
207 /* 100110mmmmmmssssssssssffffff0000 fld.p <A_GREG_M>,<A_IMMS10BY8>,<A_FPREG_F> */
208 { "fld.p", {A_GREG_M,A_IMMS10BY8,A_FPREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x98000000
210 /* 100101mmmmmmssssssssssffffff0000 fld.s <A_GREG_M>,<A_IMMS10BY4>,<A_FREG_F> */
211 { "fld.s", {A_GREG_M,A_IMMS10BY4,A_FREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x94000000
213 /* 000111mmmmmm1001nnnnnnffffff0000 fldx.d <A_GREG_M>,<A_GREG_N>,<A_DREG_F> */
214 { "fldx.d", {A_GREG_M,A_GREG_N,A_DREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x1c090000
216 /* 000111mmmmmm1101nnnnnnffffff0000 fldx.p <A_GREG_M>,<A_GREG_N>,<A_FPREG_F> */
217 { "fldx.p", {A_GREG_M,A_GREG_N,A_FPREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x1c0d0000
219 /* 000111mmmmmm1000nnnnnnffffff0000 fldx.s <A_GREG_M>,<A_GREG_N>,<A_FREG_F> */
220 { "fldx.s", {A_GREG_M,A_GREG_N,A_FREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x1c080000
222 /* 001110gggggg1110ggggggffffff0000 float.ld <A_FREG_G>,<A_DREG_F> */
223 { "float.ld", {A_FREG_G,A_REUSE_PREV,A_DREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x380e0000
225 /* 001110gggggg1100ggggggffffff0000 float.ls <A_FREG_G>,<A_FREG_F> */
226 { "float.ls", {A_FREG_G,A_REUSE_PREV,A_FREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x380c0000
228 /* 001110gggggg1101ggggggffffff0000 float.qd <A_DREG_G>,<A_DREG_F> */
229 { "float.qd", {A_DREG_G,A_REUSE_PREV,A_DREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x380d0000
231 /* 001110gggggg1111ggggggffffff0000 float.qs <A_DREG_G>,<A_FREG_F> */
232 { "float.qs", {A_DREG_G,A_REUSE_PREV,A_FREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x380f0000
234 /* 001101gggggg1110hhhhhhqqqqqq0000 fmac.s <A_FREG_G>,<A_FREG_H>,<A_FREG_F> */
235 { "fmac.s", {A_FREG_G,A_FREG_H,A_FREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x340e0000
237 /* 001110gggggg0001ggggggffffff0000 fmov.d <A_DREG_G>,<A_DREG_F> */
238 { "fmov.d", {A_DREG_G,A_REUSE_PREV,A_DREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x38010000
240 /* 001100gggggg0001ggggggdddddd0000 fmov.dq <A_DREG_G>,<A_GREG_D> */
241 { "fmov.dq", {A_DREG_G,A_REUSE_PREV,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x30010000
243 /* 000111mmmmmm0000111111ffffff0000 fmov.ls <A_GREG_M>,<A_FREG_F> */
244 { "fmov.ls", {A_GREG_M,A_FREG_F}, {OFFSET_20,OFFSET_4}, 0x1c00fc00
246 /* 000111mmmmmm0001111111ffffff0000 fmov.qd <A_GREG_M>,<A_DREG_F> */
247 { "fmov.qd", {A_GREG_M,A_DREG_F}, {OFFSET_20,OFFSET_4}, 0x1c01fc00
249 /* 001110gggggg0000ggggggffffff0000 fmov.s <A_FREG_G>,<A_FREG_F> */
250 { "fmov.s", {A_FREG_G,A_REUSE_PREV,A_FREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x38000000
252 /* 001100gggggg0000ggggggdddddd0000 fmov.sl <A_FREG_G>,<A_GREG_D> */
253 { "fmov.sl", {A_FREG_G,A_REUSE_PREV,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x30000000
255 /* 001101gggggg0111hhhhhhffffff0000 fmul.d <A_DREG_G>,<A_DREG_H>,<A_DREG_F> */
256 { "fmul.d", {A_DREG_G,A_DREG_H,A_DREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x34070000
258 /* 001101gggggg0110hhhhhhffffff0000 fmul.s <A_FREG_G>,<A_FREG_H>,<A_FREG_F> */
259 { "fmul.s", {A_FREG_G,A_FREG_H,A_FREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x34060000
261 /* 000110gggggg0011ggggggffffff0000 fneg.d <A_DREG_G>,<A_DREG_F> */
262 { "fneg.d", {A_DREG_G,A_REUSE_PREV,A_DREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x18030000
264 /* 000110gggggg0010ggggggffffff0000 fneg.s <A_FREG_G>,<A_FREG_F> */
265 { "fneg.s", {A_FREG_G,A_REUSE_PREV,A_FREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x18020000
267 /* 001100gggggg0010gggggg1111110000 fputscr <A_FREG_G> */
268 { "fputscr", {A_FREG_G,A_REUSE_PREV}, {OFFSET_20,OFFSET_10}, 0x300203f0
270 /* 001110gggggg0101ggggggffffff0000 fsqrt.d <A_DREG_G>,<A_DREG_F> */
271 { "fsqrt.d", {A_DREG_G,A_REUSE_PREV,A_DREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x38050000
273 /* 001110gggggg0100ggggggffffff0000 fsqrt.s <A_FREG_G>,<A_FREG_F> */
274 { "fsqrt.s", {A_FREG_G,A_REUSE_PREV,A_FREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x38040000
276 /* 101111mmmmmmsssssssssszzzzzz0000 fst.d <A_GREG_M>,<A_IMMS10BY8>,<A_DREG_F> */
277 { "fst.d", {A_GREG_M,A_IMMS10BY8,A_DREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xbc000000
279 /* 101110mmmmmmsssssssssszzzzzz0000 fst.p <A_GREG_M>,<A_IMMS10BY8>,<A_FPREG_F> */
280 { "fst.p", {A_GREG_M,A_IMMS10BY8,A_FPREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xb8000000
282 /* 101101mmmmmmsssssssssszzzzzz0000 fst.s <A_GREG_M>,<A_IMMS10BY4>,<A_FREG_F> */
283 { "fst.s", {A_GREG_M,A_IMMS10BY4,A_FREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xb4000000
285 /* 001111mmmmmm1001nnnnnnzzzzzz0000 fstx.d <A_GREG_M>,<A_GREG_N>,<A_DREG_F> */
286 { "fstx.d", {A_GREG_M,A_GREG_N,A_DREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x3c090000
288 /* 001111mmmmmm1101nnnnnnzzzzzz0000 fstx.p <A_GREG_M>,<A_GREG_N>,<A_FPREG_F> */
289 { "fstx.p", {A_GREG_M,A_GREG_N,A_FPREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x3c0d0000
291 /* 001111mmmmmm1000nnnnnnzzzzzz0000 fstx.s <A_GREG_M>,<A_GREG_N>,<A_FREG_F> */
292 { "fstx.s", {A_GREG_M,A_GREG_N,A_FREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x3c080000
294 /* 001101gggggg0011hhhhhhffffff0000 fsub.d <A_DREG_G>,<A_DREG_H>,<A_DREG_F> */
295 { "fsub.d", {A_DREG_G,A_DREG_H,A_DREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x34030000
297 /* 001101gggggg0010hhhhhhffffff0000 fsub.s <A_FREG_G>,<A_FREG_H>,<A_FREG_F> */
298 { "fsub.s", {A_FREG_G,A_FREG_H,A_FREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x34020000
300 /* 001110gggggg1011ggggggffffff0000 ftrc.dl <A_DREG_G>,<A_FREG_F> */
301 { "ftrc.dl", {A_DREG_G,A_REUSE_PREV,A_FREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x380b0000
303 /* 001110gggggg1001ggggggffffff0000 ftrc.dq <A_DREG_G>,<A_DREG_F> */
304 { "ftrc.dq", {A_DREG_G,A_REUSE_PREV,A_DREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x38090000
306 /* 001110gggggg1000ggggggffffff0000 ftrc.sl <A_FREG_G>,<A_FREG_F> */
307 { "ftrc.sl", {A_FREG_G,A_REUSE_PREV,A_FREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x38080000
309 /* 001110gggggg1010ggggggffffff0000 ftrc.sq <A_FREG_G>,<A_DREG_F> */
310 { "ftrc.sq", {A_FREG_G,A_REUSE_PREV,A_DREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x380a0000
312 /* 000101gggggg1110hhhhhhffffff0000 ftrv.s <A_FMREG_G>,<A_FVREG_H>,<A_FVREG_F> */
313 { "ftrv.s", {A_FMREG_G,A_FVREG_H,A_FVREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x140e0000
315 /* 110000mmmmmm1111ssssssdddddd0000 getcfg <A_GREG_M>,<A_IMMS6>,<A_GREG_D> */
316 { "getcfg", {A_GREG_M,A_IMMS6,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xc00f0000
318 /* 001001kkkkkk1111111111dddddd0000 getcon <A_CREG_K>,<A_GREG_M> */
319 { "getcon", {A_CREG_K,A_GREG_D}, {OFFSET_20,OFFSET_4}, 0x240ffc00
321 /* 010001rrrbbb0101111111dddddd0000 gettr <A_TREG_A>,<A_GREG_D> */
322 { "gettr", {A_TREG_B,A_GREG_D}, {OFFSET_20,OFFSET_4}, 0x4405fc00
324 /* 111000mmmmmm0101ssssss1111110000 icbi <A_GREG_M>,<A_IMMS6BY32> */
325 { "icbi", {A_GREG_M,A_IMMS6BY32}, {OFFSET_20,OFFSET_10}, 0xe00503f0
327 /* 100000mmmmmmssssssssssdddddd0000 ld.b <A_GREG_M>,<A_IMMS10BY1>,<A_GREG_D> */
328 { "ld.b", {A_GREG_M,A_IMMS10BY1,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x80000000
330 /* 100010mmmmmmssssssssssdddddd0000 ld.l <A_GREG_M>,<A_IMMS10BY4>,<A_GREG_D> */
331 { "ld.l", {A_GREG_M,A_IMMS10BY4,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x88000000
333 /* 100011mmmmmmssssssssssdddddd0000 ld.q <A_GREG_M>,<A_IMMS10BY8>,<A_GREG_D> */
334 { "ld.q", {A_GREG_M,A_IMMS10BY8,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x8c000000
336 /* 100100mmmmmmssssssssssdddddd0000 ld.ub <A_GREG_M>,<A_IMMS10BY1>,<A_GREG_D> */
337 { "ld.ub", {A_GREG_M,A_IMMS10BY1,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x90000000
339 /* 101100mmmmmmssssssssssdddddd0000 ld.uw <A_GREG_M>,<A_IMMS10BY2>,<A_GREG_D> */
340 { "ld.uw", {A_GREG_M,A_IMMS10BY2,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xb0000000
342 /* 100001mmmmmmssssssssssdddddd0000 ld.w <A_GREG_M>,<A_IMMS10BY2>,<A_GREG_D> */
343 { "ld.w", {A_GREG_M,A_IMMS10BY2,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x84000000
345 /* 110000mmmmmm0110ssssssdddddd0000 ldhi.l <A_GREG_M>,<A_IMMS6>,<A_GREG_D> */
346 { "ldhi.l", {A_GREG_M,A_IMMS6,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xc0060000
348 /* 110000mmmmmm0111ssssssdddddd0000 ldhi.q <A_GREG_M>,<A_IMMS6>,<A_GREG_D> */
349 { "ldhi.q", {A_GREG_M,A_IMMS6,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xc0070000
351 /* 110000mmmmmm0010ssssssdddddd0000 ldlo.l <A_GREG_M>,<A_IMMS6>,<A_GREG_D> */
352 { "ldlo.l", {A_GREG_M,A_IMMS6,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xc0020000
354 /* 110000mmmmmm0011ssssssdddddd0000 ldlo.q <A_GREG_M>,<A_IMMS6>,<A_GREG_D> */
355 { "ldlo.q", {A_GREG_M,A_IMMS6,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xc0030000
357 /* 010000mmmmmm0000nnnnnndddddd0000 ldx.b <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
358 { "ldx.b", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x40000000
360 /* 010000mmmmmm0010nnnnnndddddd0000 ldx.l <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
361 { "ldx.l", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x40020000
363 /* 010000mmmmmm0011nnnnnndddddd0000 ldx.q <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
364 { "ldx.q", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x40030000
366 /* 010000mmmmmm0100nnnnnndddddd0000 ldx.ub <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
367 { "ldx.ub", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x40040000
369 /* 010000mmmmmm0101nnnnnndddddd0000 ldx.uw <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
370 { "ldx.uw", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x40050000
372 /* 010000mmmmmm0001nnnnnndddddd0000 ldx.w <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
373 { "ldx.w", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x40010000
375 /* 001010mmmmmm1010111111dddddd0000 mabs.l <A_GREG_M>,<A_GREG_D> */
376 { "mabs.l", {A_GREG_M,A_GREG_D}, {OFFSET_20,OFFSET_4}, 0x280afc00
378 /* 001010mmmmmm1001111111dddddd0000 mabs.w <A_GREG_M>,<A_GREG_D> */
379 { "mabs.w", {A_GREG_M,A_GREG_D}, {OFFSET_20,OFFSET_4}, 0x2809fc00
381 /* 000010mmmmmm0010nnnnnndddddd0000 madd.l <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
382 { "madd.l", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x08020000
384 /* 000010mmmmmm0001nnnnnndddddd0000 madd.w <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
385 { "madd.w", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x08010000
387 /* 000010mmmmmm0110nnnnnndddddd0000 madds.l <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
388 { "madds.l", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x08060000
390 /* 000010mmmmmm0100nnnnnndddddd0000 madds.ub <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
391 { "madds.ub", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x08040000
393 /* 000010mmmmmm0101nnnnnndddddd0000 madds.w <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
394 { "madds.w", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x08050000
396 /* 001010mmmmmm0000nnnnnndddddd0000 mcmpeq.b <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
397 { "mcmpeq.b", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x28000000
399 /* 001010mmmmmm0010nnnnnndddddd0000 mcmpeq.l <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
400 { "mcmpeq.l", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x28020000
402 /* 001010mmmmmm0001nnnnnndddddd0000 mcmpeq.w <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
403 { "mcmpeq.w", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x28010000
405 /* 001010mmmmmm0110nnnnnndddddd0000 mcmpgt.l <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
406 { "mcmpgt.l", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x28060000
408 /* 001010mmmmmm0100nnnnnndddddd0000 mcmpgt.ub <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
409 { "mcmpgt.ub", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x28040000
411 /* 001010mmmmmm0101nnnnnndddddd0000 mcmpgt.w <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
412 { "mcmpgt.w", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x28050000
414 /* 010010mmmmmm0011nnnnnnwwwwww0000 mcmv <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
415 { "mcmv", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x48030000
417 /* 010011mmmmmm1101nnnnnndddddd0000 mcnvs.lw <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
418 { "mcnvs.lw", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x4c0d0000
420 /* 010011mmmmmm1000nnnnnndddddd0000 mcnvs.wb <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
421 { "mcnvs.wb", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x4c080000
423 /* 010011mmmmmm1100nnnnnndddddd0000 mcnvs.wub <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
424 { "mcnvs.wub", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x4c0c0000
426 /* 001010mmmmmm0111nnnnnndddddd0000 mextr1 <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
427 { "mextr1", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x28070000
429 /* 001010mmmmmm1011nnnnnndddddd0000 mextr2 <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
430 { "mextr2", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x280b0000
432 /* 001010mmmmmm1111nnnnnndddddd0000 mextr3 <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
433 { "mextr3", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x280f0000
435 /* 001011mmmmmm0011nnnnnndddddd0000 mextr4 <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
436 { "mextr4", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x2c030000
438 /* 001011mmmmmm0111nnnnnndddddd0000 mextr5 <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
439 { "mextr5", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x2c070000
441 /* 001011mmmmmm1011nnnnnndddddd0000 mextr6 <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
442 { "mextr6", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x2c0b0000
444 /* 001011mmmmmm1111nnnnnndddddd0000 mextr7 <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
445 { "mextr7", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x2c0f0000
447 /* 010010mmmmmm0001nnnnnnwwwwww0000 mmacfx.wl <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
448 { "mmacfx.wl", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x48010000
450 /* 010010mmmmmm0101nnnnnnwwwwww0000 mmacnfx.wl <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
451 { "mmacnfx.wl", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x48050000
453 /* 010011mmmmmm0010nnnnnndddddd0000 mmul.l <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
454 { "mmul.l", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x4c020000
456 /* 010011mmmmmm0001nnnnnndddddd0000 mmul.m <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
457 { "mmul.w", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x4c010000
459 /* 010011mmmmmm0110nnnnnndddddd0000 mmulfx.l <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
460 { "mmulfx.l", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x4c060000
462 /* 010011mmmmmm0101nnnnnndddddd0000 mmulfx.w <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
463 { "mmulfx.w", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x4c050000
465 /* 010011mmmmmm1001nnnnnndddddd0000 mmulfxrp.w <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
466 { "mmulfxrp.w", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x4c090000
468 /* 010011mmmmmm1110nnnnnndddddd0000 mmulhi.wl <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
469 { "mmulhi.wl", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x4c0e0000
471 /* 010011mmmmmm1010nnnnnndddddd0000 mmullo.wl <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
472 { "mmullo.wl", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x4c0a0000
474 /* 010010mmmmmm1001nnnnnnwwwwww0000 mmulsum.wq <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
475 { "mmulsum.wq", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x48090000
477 /* 110011ssssssssssssssssdddddd0000 movi <A_IMMS16>,<A_GREG_D> */
478 { "movi", {A_IMMS16,A_GREG_D}, {OFFSET_10,OFFSET_4}, SHMEDIA_MOVI_OPC
480 /* 001010mmmmmm1101nnnnnndddddd0000 mperm.w <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
481 { "mperm.w", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x280d0000
483 /* 010010mmmmmm0000nnnnnnwwwwww0000 msad.ubq <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
484 { "msad.ubq", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x48000000
486 /* 000011mmmmmm1010nnnnnndddddd0000 mshard.l <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
487 { "mshard.l", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x0c0a0000
489 /* 000011mmmmmm1001nnnnnndddddd0000 mshard.w <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
490 { "mshard.w", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x0c090000
492 /* 000011mmmmmm1011nnnnnndddddd0000 mshards.q <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
493 { "mshards.q", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x0c0b0000
495 /* 001011mmmmmm0100nnnnnndddddd0000 mshfhi.b <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
496 { "mshfhi.b", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x2c040000
498 /* 001011mmmmmm0110nnnnnndddddd0000 mshfhi.l <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
499 { "mshfhi.l", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x2c060000
501 /* 001011mmmmmm0101nnnnnndddddd0000 mshfhi.w <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
502 { "mshfhi.w", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x2c050000
504 /* 001011mmmmmm0000nnnnnndddddd0000 mshflo.b <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
505 { "mshflo.b", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x2c000000
507 /* 001011mmmmmm0010nnnnnndddddd0000 mshflo.l <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
508 { "mshflo.l", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x2c020000
510 /* 001011mmmmmm0001nnnnnndddddd0000 mshflo.w <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
511 { "mshflo.w", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x2c010000
513 /* 000011mmmmmm0010nnnnnndddddd0000 mshlld.l <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
514 { "mshlld.l", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x0c020000
516 /* 000011mmmmmm0001nnnnnndddddd0000 mshlld.w <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
517 { "mshlld.w", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x0c010000
519 /* 000011mmmmmm0110nnnnnndddddd0000 mshalds.l <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
520 { "mshalds.l", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x0c060000
522 /* 000011mmmmmm0101nnnnnndddddd0000 mshalds.w <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
523 { "mshalds.w", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x0c050000
525 /* 000011mmmmmm1110nnnnnndddddd0000 mshlrd.l <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
526 { "mshlrd.l", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x0c0e0000
528 /* 000011mmmmmm1101nnnnnndddddd0000 mshlrd.w <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
529 { "mshlrd.w", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x0c0d0000
531 /* 000010mmmmmm1010nnnnnndddddd0000 msub.l <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
532 { "msub.l", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x080a0000
534 /* 000010mmmmmm1001nnnnnndddddd0000 msub.w <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
535 { "msub.w", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x08090000
537 /* 000010mmmmmm1110nnnnnndddddd0000 msubs.l <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
538 { "msubs.l", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x080e0000
540 /* 000010mmmmmm1100nnnnnndddddd0000 msubs.ub <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
541 { "msubs.ub", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x080c0000
543 /* 000010mmmmmm1101nnnnnndddddd0000 msubs.w <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
544 { "msubs.w", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x080d0000
546 /* 000001mmmmmm1110nnnnnndddddd0000 muls.l <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
547 { "muls.l", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x040e0000
549 /* 000000mmmmmm1110nnnnnndddddd0000 mulu.l <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
550 { "mulu.l", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x000e0000
552 /* 01101111111100001111111111110000 nop */
553 { "nop", {A_NONE}, {OFFSET_NONE},
554 SHMEDIA_NOP_OPC
556 /* 000000mmmmmm1101111111dddddd0000 nsb <A_GREG_M>,<A_GREG_D> */
557 { "nsb", {A_GREG_M,A_GREG_D}, {OFFSET_20,OFFSET_4}, 0x000dfc00
559 /* 111000mmmmmm1001ssssss1111110000 ocbi <A_GREG_M>,<A_IMMS6BY32> */
560 { "ocbi", {A_GREG_M,A_IMMS6BY32}, {OFFSET_20,OFFSET_10}, 0xe00903f0
562 /* 111000mmmmmm1000ssssss1111110000 ocbp <A_GREG_M>,<A_IMMS6BY32> */
563 { "ocbp", {A_GREG_M,A_IMMS6BY32}, {OFFSET_20,OFFSET_10}, 0xe00803f0
565 /* 111000mmmmmm1100ssssss1111110000 ocbwb <A_GREG_M>,<A_IMMS6BY32> */
566 { "ocbwb", {A_GREG_M,A_IMMS6BY32}, {OFFSET_20,OFFSET_10}, 0xe00c03f0
568 /* 000001mmmmmm1001nnnnnndddddd0000 or <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
569 { "or", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x04090000
571 /* 110111mmmmmmssssssssssdddddd0000 ori <A_GREG_M>,<A_IMMS10>,<A_GREG_D> */
572 { "ori", {A_GREG_M,A_IMMS10,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xdc000000
574 /* 111000mmmmmm0001ssssss1111110000 prefi <A_GREG_M>,<A_IMMS6BY32> */
575 { "prefi", {A_GREG_M,A_IMMS6BY32}, {OFFSET_20,OFFSET_10}, 0xe00103f0
577 /* 111010sssssssssssssssslrraaa0000 pta <A_PCIMMS16BY4>,<A_TREG_A> */
578 { "pta/l", {A_PCIMMS16BY4,A_TREG_A}, {OFFSET_10,OFFSET_4},
579 SHMEDIA_PTA_OPC | SHMEDIA_LIKELY_BIT
581 /* 111010sssssssssssssssslrraaa0000 pta <A_PCIMMS16BY4>,<A_TREG_A> */
582 { "pta", {A_PCIMMS16BY4,A_TREG_A}, {OFFSET_10,OFFSET_4},
583 SHMEDIA_PTA_OPC | SHMEDIA_LIKELY_BIT
585 /* 111010ssssssssssssssss0rraaa0000 pta/u <A_PCIMMS16BY4>,<A_TREG_A> */
586 { "pta/u", {A_PCIMMS16BY4,A_TREG_A}, {OFFSET_10,OFFSET_4},
587 SHMEDIA_PTA_OPC
589 /* 0110101111110001nnnnnnl00aaa0000 ptabs <A_GREG_M>,<A_TREG_A> */
590 { "ptabs/l", {A_GREG_N,A_TREG_A}, {OFFSET_10,OFFSET_4}, 0x6bf10200
592 /* 0110101111110001nnnnnnl00aaa0000 ptabs <A_GREG_M>,<A_TREG_A> */
593 { "ptabs", {A_GREG_N,A_TREG_A}, {OFFSET_10,OFFSET_4}, 0x6bf10200
595 /* 0110101111110001nnnnnn000aaa0000 ptabs/u <A_GREG_M>,<A_TREG_A> */
596 { "ptabs/u", {A_GREG_N,A_TREG_A}, {OFFSET_10,OFFSET_4}, 0x6bf10000
598 /* 111011sssssssssssssssslrraaa0000 ptb <A_PCIMMS16BY4>,<A_TREG_A> */
599 { "ptb/l", {A_PCIMMS16BY4,A_TREG_A}, {OFFSET_10,OFFSET_4},
600 SHMEDIA_PTB_OPC | SHMEDIA_LIKELY_BIT
602 /* 111011sssssssssssssssslrraaa0000 ptb <A_PCIMMS16BY4>,<A_TREG_A> */
603 { "ptb", {A_PCIMMS16BY4,A_TREG_A}, {OFFSET_10,OFFSET_4},
604 SHMEDIA_PTB_OPC | SHMEDIA_LIKELY_BIT
606 /* 111011ssssssssssssssss0rraaa0000 ptb/u <A_PCIMMS16BY4>,<A_TREG_A> */
607 { "ptb/u", {A_PCIMMS16BY4,A_TREG_A}, {OFFSET_10,OFFSET_4},
608 SHMEDIA_PTB_OPC
610 /* 111010sssssssssssssssslrraaa0000 pt/l <A_PCIMMS16BY4>,<A_TREG_A> */
611 { "pt/l", {A_PCIMMS16BY4_PT,A_TREG_A},
612 {OFFSET_10,OFFSET_4}, SHMEDIA_PT_OPC | SHMEDIA_LIKELY_BIT
614 /* 111010sssssssssssssssslrraaa0000 pt <A_PCIMMS16BY4>,<A_TREG_A> */
615 { "pt", {A_PCIMMS16BY4_PT,A_TREG_A},
616 {OFFSET_10,OFFSET_4}, SHMEDIA_PT_OPC | SHMEDIA_LIKELY_BIT
618 /* 111010ssssssssssssssss0rraaa0000 pt/u <A_PCIMMS16BY4>,<A_TREG_A> */
619 { "pt/u", {A_PCIMMS16BY4_PT,A_TREG_A},
620 {OFFSET_10,OFFSET_4}, SHMEDIA_PT_OPC
622 /* 0110101111110101nnnnnnl00aaa0000 ptrel <A_GREG_M>,<A_TREG_A> */
623 { "ptrel/l", {A_GREG_N,A_TREG_A}, {OFFSET_10,OFFSET_4},
624 SHMEDIA_PTREL_OPC | SHMEDIA_LIKELY_BIT
626 /* 0110101111110101nnnnnnl00aaa0000 ptrel <A_GREG_M>,<A_TREG_A> */
627 { "ptrel", {A_GREG_N,A_TREG_A}, {OFFSET_10,OFFSET_4},
628 SHMEDIA_PTREL_OPC | SHMEDIA_LIKELY_BIT
630 /* 0110101111110101nnnnnn000aaa0000 ptrel/u <A_GREG_M>,<A_TREG_A> */
631 { "ptrel/u", {A_GREG_N,A_TREG_A}, {OFFSET_10,OFFSET_4},
632 SHMEDIA_PTREL_OPC
634 /* 111000mmmmmm1111ssssssyyyyyy0000 putcfg <A_GREG_M>,<A_IMMS6>,<A_GREG_D> */
635 { "putcfg", {A_GREG_M,A_IMMS6,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xe00f0000
637 /* 011011mmmmmm1111111111jjjjjj0000 putcon <A_GREG_M>,<A_CREG_J> */
638 { "putcon", {A_GREG_M,A_CREG_J}, {OFFSET_20,OFFSET_4}, 0x6c0ffc00
640 /* 01101111111100111111111111110000 rte */
641 { "rte", {A_NONE}, {OFFSET_NONE}, 0x6ff3fff0
643 /* 000001mmmmmm0111nnnnnndddddd0000 shard <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
644 { "shard", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x04070000
646 /* 000001mmmmmm0110nnnnnndddddd0000 shard.l <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
647 { "shard.l", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x04060000
649 /* 110001mmmmmm0111ssssssdddddd0000 shari <A_GREG_M>,<A_IMMU6>,<A_GREG_D> */
650 { "shari", {A_GREG_M,A_IMMU6,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xc4070000
652 /* 110001mmmmmm0110ssssssdddddd0000 shari <A_GREG_M>,<A_IMMU6>,<A_GREG_D> */
653 { "shari.l", {A_GREG_M,A_IMMU6,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xc4060000
655 /* 000001mmmmmm0001nnnnnndddddd0000 shlld <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
656 { "shlld", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x04010000
658 /* 000001mmmmmm0000nnnnnndddddd0000 shlld.l <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
659 { "shlld.l", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x04000000
661 /* 110001mmmmmm0001ssssssdddddd0000 shlli <A_GREG_M>,<A_IMMU6>,<A_GREG_D> */
662 { "shlli", {A_GREG_M,A_IMMU6,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xc4010000
664 /* 110001mmmmmm0000ssssssdddddd0000 shlli.l <A_GREG_M>,<A_IMMU5>,<A_GREG_D> */
665 { "shlli.l", {A_GREG_M,A_IMMU5,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xc4000000
667 /* 000001mmmmmm0011nnnnnndddddd0000 shlrd <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
668 { "shlrd", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x04030000
670 /* 000001mmmmmm0010nnnnnndddddd0000 shlrd.l <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
671 { "shlrd.l", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x04020000
673 /* 110001mmmmmm0011ssssssdddddd0000 shlri <A_GREG_M>,<A_IMMU6>,<A_GREG_D> */
674 { "shlri", {A_GREG_M,A_IMMU6,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xc4030000
676 /* 110001mmmmmm0010ssssssdddddd0000 shlri.l <A_GREG_M>,<A_IMMU5>,<A_GREG_D> */
677 { "shlri.l", {A_GREG_M,A_IMMU5,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xc4020000
679 /* 110010sssssssssssssssswwwwww0000 shori <A_IMMU16>,<A_GREG_D> */
680 { "shori", {A_IMMU16,A_GREG_D}, {OFFSET_10,OFFSET_4}, SHMEDIA_SHORI_OPC
682 /* 01101111111101111111111111110000 sleep */
683 { "sleep", {A_NONE}, {OFFSET_NONE}, 0x6ff7fff0
685 /* 101000mmmmmmssssssssssdddddd0000 st.b <A_GREG_M>,<A_IMMS10BY1>,<A_GREG_D> */
686 { "st.b", {A_GREG_M,A_IMMS10BY1,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xa0000000
688 /* 101010mmmmmmssssssssssdddddd0000 st.l <A_GREG_M>,<A_IMMS10BY4>,<A_GREG_D> */
689 { "st.l", {A_GREG_M,A_IMMS10BY4,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xa8000000
691 /* 101011mmmmmmssssssssssdddddd0000 st.q <A_GREG_M>,<A_IMMS10BY8>,<A_GREG_D> */
692 { "st.q", {A_GREG_M,A_IMMS10BY8,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xac000000
694 /* 101001mmmmmmssssssssssdddddd0000 st.w <A_GREG_M>,<A_IMMS10BY2>,<A_GREG_D> */
695 { "st.w", {A_GREG_M,A_IMMS10BY2,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xa4000000
697 /* 111000mmmmmm0110ssssssdddddd0000 sthi.l <A_GREG_M>,<A_IMMS6>,<A_GREG_D> */
698 { "sthi.l", {A_GREG_M,A_IMMS6,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xe0060000
700 /* 111000mmmmmm0111ssssssdddddd0000 sthi.q <A_GREG_M>,<A_IMMS6>,<A_GREG_D> */
701 { "sthi.q", {A_GREG_M,A_IMMS6,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xe0070000
703 /* 111000mmmmmm0010ssssssdddddd0000 stlo.l <A_GREG_M>,<A_IMMS6>,<A_GREG_D> */
704 { "stlo.l", {A_GREG_M,A_IMMS6,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xe0020000
706 /* 111000mmmmmm0011ssssssdddddd0000 stlo.q <A_GREG_M>,<A_IMMS6>,<A_GREG_D> */
707 { "stlo.q", {A_GREG_M,A_IMMS6,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xe0030000
709 /* 011000mmmmmm0000nnnnnndddddd0000 stx.b <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
710 { "stx.b", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x60000000
712 /* 011000mmmmmm0010nnnnnndddddd0000 stx.l <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
713 { "stx.l", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x60020000
715 /* 011000mmmmmm0011nnnnnndddddd0000 stx.q <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
716 { "stx.q", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x60030000
718 /* 011000mmmmmm0001nnnnnndddddd0000 stx.w <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
719 { "stx.w", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x60010000
721 /* 000000mmmmmm1011nnnnnndddddd0000 sub <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
722 { "sub", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x000b0000
724 /* 000000mmmmmm1010nnnnnndddddd0000 sub.l <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
725 { "sub.l", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x000a0000
727 /* 001000mmmmmm0011nnnnnnwwwwww0000 swap.q <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
728 { "swap.q", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x20030000
730 /* 01101111111100101111111111110000 synci */
731 { "synci", {A_NONE}, {OFFSET_NONE}, 0x6ff2fff0
733 /* 01101111111101101111111111110000 synco */
734 { "synco", {A_NONE}, {OFFSET_NONE}, 0x6ff6fff0
736 /* 011011mmmmmm00011111111111110000 trapa <A_GREG_M> */
737 { "trapa", {A_GREG_M}, {OFFSET_20}, 0x6c01fff0
739 /* 000001mmmmmm1101nnnnnndddddd0000 xor <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
740 { "xor", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x040d0000
742 /* 110001mmmmmm1101ssssssdddddd0000 xori <A_GREG_M>,<A_IMMS6>,<A_GREG_D> */
743 { "xori", {A_GREG_M,A_IMMS6,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xc40d0000
746 { NULL, {}, {}, 0 }
749 /* Predefined control register names as per SH-5/ST50-005-08. */
750 const shmedia_creg_info shmedia_creg_table[] = {
751 { 0, "sr" },
752 { 1, "ssr" },
753 { 2, "pssr" },
755 { 4, "intevt" },
756 { 5, "expevt" },
757 { 6, "pexpevt" },
758 { 7, "tra" },
759 { 8, "spc" },
760 { 9, "pspc" },
761 { 10, "resvec" },
762 { 11, "vbr" },
764 { 13, "tea" },
766 { 16, "dcr" },
767 { 17, "kcr0" },
768 { 18, "kcr1" },
770 { 62, "ctc" },
771 { 63, "usr" },
772 { -1, (char *) 0 }