1 2005-10-28 Dave Brolley <brolley@redhat.com>
3 Contribute the following changes:
4 2005-02-16 Dave Brolley <brolley@redhat.com>
6 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
7 cgen_isa_mask_* to cgen_bitset_*.
10 2005-09-30 Catherine Moore <clm@cm00re.com>
14 2005-10-24 Jan Beulich <jbeulich@novell.com>
16 * ia64.h (enum ia64_opnd): Move memory operand out of set of
19 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
21 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
22 Add FLAG_STRICT to pa10 ftest opcode.
24 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
26 * hppa.h (pa_opcodes): Remove lha entries.
28 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
30 * hppa.h (FLAG_STRICT): Revise comment.
31 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
32 before corresponding pa11 opcodes. Add strict pa10 register-immediate
35 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
37 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
39 2005-09-06 Chao-ying Fu <fu@mips.com>
41 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
42 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
44 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
45 (INSN_ASE_MASK): Update to include INSN_MT.
46 (INSN_MT): New define for MT ASE.
48 2005-08-25 Chao-ying Fu <fu@mips.com>
50 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
51 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
52 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
53 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
54 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
55 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
57 (INSN_DSP): New define for DSP ASE.
59 2005-08-18 Alan Modra <amodra@bigpond.net.au>
63 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
65 * ppc.h (PPC_OPCODE_E300): Define.
67 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
69 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
71 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
74 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
77 2005-07-27 Jan Beulich <jbeulich@novell.com>
79 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
80 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
81 Add movq-s as 64-bit variants of movd-s.
83 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
85 * hppa.h: Fix punctuation in comment.
87 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
88 implicit space-register addressing. Set space-register bits on opcodes
89 using implicit space-register addressing. Add various missing pa20
90 long-immediate opcodes. Remove various opcodes using implicit 3-bit
91 space-register addressing. Use "fE" instead of "fe" in various
94 2005-07-18 Jan Beulich <jbeulich@novell.com>
96 * i386.h (i386_optab): Operands of aam and aad are unsigned.
98 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
100 * i386.h (i386_optab): Support Intel VMX Instructions.
102 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
104 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
106 2005-07-05 Jan Beulich <jbeulich@novell.com>
108 * i386.h (i386_optab): Add new insns.
110 2005-07-01 Nick Clifton <nickc@redhat.com>
112 * sparc.h: Add typedefs to structure declarations.
114 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
117 * i386.h (i386_optab): Update comments for 64bit addressing on
118 mov. Allow 64bit addressing for mov and movq.
120 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
122 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
123 respectively, in various floating-point load and store patterns.
125 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
127 * hppa.h (FLAG_STRICT): Correct comment.
128 (pa_opcodes): Update load and store entries to allow both PA 1.X and
129 PA 2.0 mneumonics when equivalent. Entries with cache control
130 completers now require PA 1.1. Adjust whitespace.
132 2005-05-19 Anton Blanchard <anton@samba.org>
134 * ppc.h (PPC_OPCODE_POWER5): Define.
136 2005-05-10 Nick Clifton <nickc@redhat.com>
138 * Update the address and phone number of the FSF organization in
139 the GPL notices in the following files:
140 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
141 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
142 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
143 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
144 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
145 tic54x.h, tic80.h, v850.h, vax.h
147 2005-05-09 Jan Beulich <jbeulich@novell.com>
149 * i386.h (i386_optab): Add ht and hnt.
151 2005-04-18 Mark Kettenis <kettenis@gnu.org>
153 * i386.h: Insert hyphens into selected VIA PadLock extensions.
154 Add xcrypt-ctr. Provide aliases without hyphens.
156 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
158 Moved from ../ChangeLog
160 2005-04-12 Paul Brook <paul@codesourcery.com>
161 * m88k.h: Rename psr macros to avoid conflicts.
163 2005-03-12 Zack Weinberg <zack@codesourcery.com>
164 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
165 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
168 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
169 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
170 Remove redundant instruction types.
171 (struct argument): X_op - new field.
172 (struct cst4_entry): Remove.
173 (no_op_insn): Declare.
175 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
176 * crx.h (enum argtype): Rename types, remove unused types.
178 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
179 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
180 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
181 (enum operand_type): Rearrange operands, edit comments.
182 replace us<N> with ui<N> for unsigned immediate.
183 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
184 displacements (respectively).
185 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
186 (instruction type): Add NO_TYPE_INS.
187 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
188 (operand_entry): New field - 'flags'.
189 (operand flags): New.
191 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
192 * crx.h (operand_type): Remove redundant types i3, i4,
194 Add new unsigned immediate types us3, us4, us5, us16.
196 2005-04-12 Mark Kettenis <kettenis@gnu.org>
198 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
199 adjust them accordingly.
201 2005-04-01 Jan Beulich <jbeulich@novell.com>
203 * i386.h (i386_optab): Add rdtscp.
205 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
207 * i386.h (i386_optab): Don't allow the `l' suffix for moving
208 between memory and segment register. Allow movq for moving between
209 general-purpose register and segment register.
211 2005-02-09 Jan Beulich <jbeulich@novell.com>
214 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
215 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
218 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
220 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
221 * cgen.h (enum cgen_parse_operand_type): Add
222 CGEN_PARSE_OPERAND_SYMBOLIC.
224 2005-01-21 Fred Fish <fnf@specifixinc.com>
226 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
227 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
228 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
230 2005-01-19 Fred Fish <fnf@specifixinc.com>
232 * mips.h (struct mips_opcode): Add new pinfo2 member.
233 (INSN_ALIAS): New define for opcode table entries that are
234 specific instances of another entry, such as 'move' for an 'or'
236 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
237 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
239 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
241 * mips.h (CPU_RM9000): Define.
242 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
244 2004-11-25 Jan Beulich <jbeulich@novell.com>
246 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
247 to/from test registers are illegal in 64-bit mode. Add missing
248 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
249 (previously one had to explicitly encode a rex64 prefix). Re-enable
250 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
251 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
253 2004-11-23 Jan Beulich <jbeulich@novell.com>
255 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
256 available only with SSE2. Change the MMX additions introduced by SSE
257 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
258 instructions by their now designated identifier (since combining i686
259 and 3DNow! does not really imply 3DNow!A).
261 2004-11-19 Alan Modra <amodra@bigpond.net.au>
263 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
264 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
266 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
267 Vineet Sharma <vineets@noida.hcltech.com>
269 * maxq.h: New file: Disassembly information for the maxq port.
271 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
273 * i386.h (i386_optab): Put back "movzb".
275 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
277 * cris.h (enum cris_insn_version_usage): Tweak formatting and
278 comments. Remove member cris_ver_sim. Add members
279 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
280 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
281 (struct cris_support_reg, struct cris_cond15): New types.
282 (cris_conds15): Declare.
283 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
284 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
285 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
286 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
287 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
290 2004-11-04 Jan Beulich <jbeulich@novell.com>
292 * i386.h (sldx_Suf): Remove.
293 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
294 (q_FP): Define, implying no REX64.
295 (x_FP, sl_FP): Imply FloatMF.
296 (i386_optab): Split reg and mem forms of moving from segment registers
297 so that the memory forms can ignore the 16-/32-bit operand size
298 distinction. Adjust a few others for Intel mode. Remove *FP uses from
299 all non-floating-point instructions. Unite 32- and 64-bit forms of
300 movsx, movzx, and movd. Adjust floating point operations for the above
301 changes to the *FP macros. Add DefaultSize to floating point control
302 insns operating on larger memory ranges. Remove left over comments
303 hinting at certain insns being Intel-syntax ones where the ones
304 actually meant are already gone.
306 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
308 * crx.h: Add COPS_REG_INS - Coprocessor Special register
311 2004-09-30 Paul Brook <paul@codesourcery.com>
313 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
314 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
316 2004-09-11 Theodore A. Roth <troth@openavr.org>
318 * avr.h: Add support for
319 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
321 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
323 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
325 2004-08-24 Dmitry Diky <diwil@spec.ru>
327 * msp430.h (msp430_opc): Add new instructions.
328 (msp430_rcodes): Declare new instructions.
329 (msp430_hcodes): Likewise..
331 2004-08-13 Nick Clifton <nickc@redhat.com>
334 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
337 2004-08-30 Michal Ludvig <mludvig@suse.cz>
339 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
341 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
343 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
345 2004-07-21 Jan Beulich <jbeulich@novell.com>
347 * i386.h: Adjust instruction descriptions to better match the
350 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
352 * arm.h: Remove all old content. Replace with architecture defines
353 from gas/config/tc-arm.c.
355 2004-07-09 Andreas Schwab <schwab@suse.de>
357 * m68k.h: Fix comment.
359 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
363 2004-06-24 Alan Modra <amodra@bigpond.net.au>
365 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
367 2004-05-24 Peter Barada <peter@the-baradas.com>
369 * m68k.h: Add 'size' to m68k_opcode.
371 2004-05-05 Peter Barada <peter@the-baradas.com>
373 * m68k.h: Switch from ColdFire chip name to core variant.
375 2004-04-22 Peter Barada <peter@the-baradas.com>
377 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
378 descriptions for new EMAC cases.
379 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
380 handle Motorola MAC syntax.
381 Allow disassembly of ColdFire V4e object files.
383 2004-03-16 Alan Modra <amodra@bigpond.net.au>
385 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
387 2004-03-12 Jakub Jelinek <jakub@redhat.com>
389 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
391 2004-03-12 Michal Ludvig <mludvig@suse.cz>
393 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
395 2004-03-12 Michal Ludvig <mludvig@suse.cz>
397 * i386.h (i386_optab): Added xstore/xcrypt insns.
399 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
401 * h8300.h (32bit ldc/stc): Add relaxing support.
403 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
405 * h8300.h (BITOP): Pass MEMRELAX flag.
407 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
409 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
412 For older changes see ChangeLog-9103
418 version-control: never