1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "elf/x86-64.h"
36 #include "opcodes/i386-init.h"
38 #ifndef REGISTER_WARNINGS
39 #define REGISTER_WARNINGS 1
42 #ifndef INFER_ADDR_PREFIX
43 #define INFER_ADDR_PREFIX 1
47 #define DEFAULT_ARCH "i386"
52 #define INLINE __inline__
58 /* Prefixes will be emitted in the order defined below.
59 WAIT_PREFIX must be the first prefix since FWAIT is really is an
60 instruction, and so must come before any prefixes.
61 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
67 #define LOCKREP_PREFIX 4
68 #define REX_PREFIX 5 /* must come last. */
69 #define MAX_PREFIXES 6 /* max prefixes per opcode */
71 /* we define the syntax here (modulo base,index,scale syntax) */
72 #define REGISTER_PREFIX '%'
73 #define IMMEDIATE_PREFIX '$'
74 #define ABSOLUTE_PREFIX '*'
76 /* these are the instruction mnemonic suffixes in AT&T syntax or
77 memory operand size in Intel syntax. */
78 #define WORD_MNEM_SUFFIX 'w'
79 #define BYTE_MNEM_SUFFIX 'b'
80 #define SHORT_MNEM_SUFFIX 's'
81 #define LONG_MNEM_SUFFIX 'l'
82 #define QWORD_MNEM_SUFFIX 'q'
83 #define XMMWORD_MNEM_SUFFIX 'x'
84 #define YMMWORD_MNEM_SUFFIX 'y'
85 /* Intel Syntax. Use a non-ascii letter since since it never appears
87 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
89 #define END_OF_INSN '\0'
92 'templates' is for grouping together 'template' structures for opcodes
93 of the same name. This is only used for storing the insns in the grand
94 ole hash table of insns.
95 The templates themselves start at START and range up to (but not including)
100 const template *start
;
105 /* 386 operand encoding bytes: see 386 book for details of this. */
108 unsigned int regmem
; /* codes register or memory operand */
109 unsigned int reg
; /* codes register operand (or extended opcode) */
110 unsigned int mode
; /* how to interpret regmem & reg */
114 /* x86-64 extension prefix. */
115 typedef int rex_byte
;
117 /* The SSE5 instructions have a two bit instruction modifier (OC) that
118 is stored in two separate bytes in the instruction. Pick apart OC
119 into the 2 separate bits for instruction. */
120 #define DREX_OC0(x) (((x) & 1) != 0)
121 #define DREX_OC1(x) (((x) & 2) != 0)
123 #define DREX_OC0_MASK (1 << 3) /* set OC0 in byte 4 */
124 #define DREX_OC1_MASK (1 << 2) /* set OC1 in byte 3 */
127 #define DREX_XMEM_X1_X2_X2 0 /* 4 op insn, dest = src3, src1 = reg/mem */
128 #define DREX_X1_XMEM_X2_X2 1 /* 4 op insn, dest = src3, src2 = reg/mem */
129 #define DREX_X1_XMEM_X2_X1 2 /* 4 op insn, dest = src1, src2 = reg/mem */
130 #define DREX_X1_X2_XMEM_X1 3 /* 4 op insn, dest = src1, src3 = reg/mem */
132 #define DREX_XMEM_X1_X2 0 /* 3 op insn, src1 = reg/mem */
133 #define DREX_X1_XMEM_X2 1 /* 3 op insn, src1 = reg/mem */
135 /* Information needed to create the DREX byte in SSE5 instructions. */
138 unsigned int reg
; /* register */
139 unsigned int rex
; /* REX flags */
140 unsigned int modrm_reg
; /* which arg goes in the modrm.reg field */
141 unsigned int modrm_regmem
; /* which arg goes in the modrm.regmem field */
144 /* 386 opcode byte to code indirect addressing. */
159 PROCESSOR_PENTIUMPRO
,
172 /* x86 arch names, types and features */
175 const char *name
; /* arch name */
176 enum processor_type type
; /* arch type */
177 i386_cpu_flags flags
; /* cpu feature flags */
181 static void set_code_flag (int);
182 static void set_16bit_gcc_code_flag (int);
183 static void set_intel_syntax (int);
184 static void set_intel_mnemonic (int);
185 static void set_allow_index_reg (int);
186 static void set_cpu_arch (int);
188 static void pe_directive_secrel (int);
190 static void signed_cons (int);
191 static char *output_invalid (int c
);
192 static int i386_att_operand (char *);
193 static int i386_intel_operand (char *, int);
194 static const reg_entry
*parse_register (char *, char **);
195 static char *parse_insn (char *, char *);
196 static char *parse_operands (char *, const char *);
197 static void swap_operands (void);
198 static void swap_2_operands (int, int);
199 static void optimize_imm (void);
200 static void optimize_disp (void);
201 static int match_template (void);
202 static int check_string (void);
203 static int process_suffix (void);
204 static int check_byte_reg (void);
205 static int check_long_reg (void);
206 static int check_qword_reg (void);
207 static int check_word_reg (void);
208 static int finalize_imm (void);
209 static void process_drex (void);
210 static int process_operands (void);
211 static const seg_entry
*build_modrm_byte (void);
212 static void output_insn (void);
213 static void output_imm (fragS
*, offsetT
);
214 static void output_disp (fragS
*, offsetT
);
216 static void s_bss (int);
218 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
219 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
222 static const char *default_arch
= DEFAULT_ARCH
;
227 /* VEX prefix is either 2 byte or 3 byte. */
228 unsigned char bytes
[3];
230 /* Destination or source register specifier. */
231 const reg_entry
*register_specifier
;
234 /* 'md_assemble ()' gathers together information and puts it into a
241 const reg_entry
*regs
;
246 /* TM holds the template for the insn were currently assembling. */
249 /* SUFFIX holds the instruction size suffix for byte, word, dword
250 or qword, if given. */
253 /* OPERANDS gives the number of given operands. */
254 unsigned int operands
;
256 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
257 of given register, displacement, memory operands and immediate
259 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
261 /* TYPES [i] is the type (see above #defines) which tells us how to
262 use OP[i] for the corresponding operand. */
263 i386_operand_type types
[MAX_OPERANDS
];
265 /* Displacement expression, immediate expression, or register for each
267 union i386_op op
[MAX_OPERANDS
];
269 /* Flags for operands. */
270 unsigned int flags
[MAX_OPERANDS
];
271 #define Operand_PCrel 1
273 /* Relocation type for operand */
274 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
276 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
277 the base index byte below. */
278 const reg_entry
*base_reg
;
279 const reg_entry
*index_reg
;
280 unsigned int log2_scale_factor
;
282 /* SEG gives the seg_entries of this insn. They are zero unless
283 explicit segment overrides are given. */
284 const seg_entry
*seg
[2];
286 /* PREFIX holds all the given prefix opcodes (usually null).
287 PREFIXES is the number of prefix opcodes. */
288 unsigned int prefixes
;
289 unsigned char prefix
[MAX_PREFIXES
];
291 /* RM and SIB are the modrm byte and the sib byte where the
292 addressing modes of this insn are encoded. DREX is the byte
293 added by the SSE5 instructions. */
302 typedef struct _i386_insn i386_insn
;
304 /* List of chars besides those in app.c:symbol_chars that can start an
305 operand. Used to prevent the scrubber eating vital white-space. */
306 const char extra_symbol_chars
[] = "*%-(["
315 #if (defined (TE_I386AIX) \
316 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
317 && !defined (TE_GNU) \
318 && !defined (TE_LINUX) \
319 && !defined (TE_NETWARE) \
320 && !defined (TE_FreeBSD) \
321 && !defined (TE_NetBSD)))
322 /* This array holds the chars that always start a comment. If the
323 pre-processor is disabled, these aren't very useful. The option
324 --divide will remove '/' from this list. */
325 const char *i386_comment_chars
= "#/";
326 #define SVR4_COMMENT_CHARS 1
327 #define PREFIX_SEPARATOR '\\'
330 const char *i386_comment_chars
= "#";
331 #define PREFIX_SEPARATOR '/'
334 /* This array holds the chars that only start a comment at the beginning of
335 a line. If the line seems to have the form '# 123 filename'
336 .line and .file directives will appear in the pre-processed output.
337 Note that input_file.c hand checks for '#' at the beginning of the
338 first line of the input file. This is because the compiler outputs
339 #NO_APP at the beginning of its output.
340 Also note that comments started like this one will always work if
341 '/' isn't otherwise defined. */
342 const char line_comment_chars
[] = "#/";
344 const char line_separator_chars
[] = ";";
346 /* Chars that can be used to separate mant from exp in floating point
348 const char EXP_CHARS
[] = "eE";
350 /* Chars that mean this number is a floating point constant
353 const char FLT_CHARS
[] = "fFdDxX";
355 /* Tables for lexical analysis. */
356 static char mnemonic_chars
[256];
357 static char register_chars
[256];
358 static char operand_chars
[256];
359 static char identifier_chars
[256];
360 static char digit_chars
[256];
362 /* Lexical macros. */
363 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
364 #define is_operand_char(x) (operand_chars[(unsigned char) x])
365 #define is_register_char(x) (register_chars[(unsigned char) x])
366 #define is_space_char(x) ((x) == ' ')
367 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
368 #define is_digit_char(x) (digit_chars[(unsigned char) x])
370 /* All non-digit non-letter characters that may occur in an operand. */
371 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
373 /* md_assemble() always leaves the strings it's passed unaltered. To
374 effect this we maintain a stack of saved characters that we've smashed
375 with '\0's (indicating end of strings for various sub-fields of the
376 assembler instruction). */
377 static char save_stack
[32];
378 static char *save_stack_p
;
379 #define END_STRING_AND_SAVE(s) \
380 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
381 #define RESTORE_END_STRING(s) \
382 do { *(s) = *--save_stack_p; } while (0)
384 /* The instruction we're assembling. */
387 /* Possible templates for current insn. */
388 static const templates
*current_templates
;
390 /* Per instruction expressionS buffers: max displacements & immediates. */
391 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
392 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
394 /* Current operand we are working on. */
395 static int this_operand
;
397 /* We support four different modes. FLAG_CODE variable is used to distinguish
405 static enum flag_code flag_code
;
406 static unsigned int object_64bit
;
407 static int use_rela_relocations
= 0;
409 /* The names used to print error messages. */
410 static const char *flag_code_names
[] =
417 /* 1 for intel syntax,
419 static int intel_syntax
= 0;
421 /* 1 for intel mnemonic,
422 0 if att mnemonic. */
423 static int intel_mnemonic
= !SYSV386_COMPAT
;
425 /* 1 if support old (<= 2.8.1) versions of gcc. */
426 static int old_gcc
= OLDGCC_COMPAT
;
428 /* 1 if pseudo registers are permitted. */
429 static int allow_pseudo_reg
= 0;
431 /* 1 if register prefix % not required. */
432 static int allow_naked_reg
= 0;
434 /* 1 if pseudo index register, eiz/riz, is allowed . */
435 static int allow_index_reg
= 0;
445 /* Register prefix used for error message. */
446 static const char *register_prefix
= "%";
448 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
449 leave, push, and pop instructions so that gcc has the same stack
450 frame as in 32 bit mode. */
451 static char stackop_size
= '\0';
453 /* Non-zero to optimize code alignment. */
454 int optimize_align_code
= 1;
456 /* Non-zero to quieten some warnings. */
457 static int quiet_warnings
= 0;
460 static const char *cpu_arch_name
= NULL
;
461 static char *cpu_sub_arch_name
= NULL
;
463 /* CPU feature flags. */
464 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
466 /* If we have selected a cpu we are generating instructions for. */
467 static int cpu_arch_tune_set
= 0;
469 /* Cpu we are generating instructions for. */
470 static enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
472 /* CPU feature flags of cpu we are generating instructions for. */
473 static i386_cpu_flags cpu_arch_tune_flags
;
475 /* CPU instruction set architecture used. */
476 static enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
478 /* CPU feature flags of instruction set architecture used. */
479 static i386_cpu_flags cpu_arch_isa_flags
;
481 /* If set, conditional jumps are not automatically promoted to handle
482 larger than a byte offset. */
483 static unsigned int no_cond_jump_promotion
= 0;
485 /* Encode SSE instructions with VEX prefix. */
486 static unsigned int sse2avx
;
488 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
489 static symbolS
*GOT_symbol
;
491 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
492 unsigned int x86_dwarf2_return_column
;
494 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
495 int x86_cie_data_alignment
;
497 /* Interface to relax_segment.
498 There are 3 major relax states for 386 jump insns because the
499 different types of jumps add different sizes to frags when we're
500 figuring out what sort of jump to choose to reach a given label. */
503 #define UNCOND_JUMP 0
505 #define COND_JUMP86 2
510 #define SMALL16 (SMALL | CODE16)
512 #define BIG16 (BIG | CODE16)
516 #define INLINE __inline__
522 #define ENCODE_RELAX_STATE(type, size) \
523 ((relax_substateT) (((type) << 2) | (size)))
524 #define TYPE_FROM_RELAX_STATE(s) \
526 #define DISP_SIZE_FROM_RELAX_STATE(s) \
527 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
529 /* This table is used by relax_frag to promote short jumps to long
530 ones where necessary. SMALL (short) jumps may be promoted to BIG
531 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
532 don't allow a short jump in a 32 bit code segment to be promoted to
533 a 16 bit offset jump because it's slower (requires data size
534 prefix), and doesn't work, unless the destination is in the bottom
535 64k of the code segment (The top 16 bits of eip are zeroed). */
537 const relax_typeS md_relax_table
[] =
540 1) most positive reach of this state,
541 2) most negative reach of this state,
542 3) how many bytes this mode will have in the variable part of the frag
543 4) which index into the table to try if we can't fit into this one. */
545 /* UNCOND_JUMP states. */
546 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
547 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
548 /* dword jmp adds 4 bytes to frag:
549 0 extra opcode bytes, 4 displacement bytes. */
551 /* word jmp adds 2 byte2 to frag:
552 0 extra opcode bytes, 2 displacement bytes. */
555 /* COND_JUMP states. */
556 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
557 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
558 /* dword conditionals adds 5 bytes to frag:
559 1 extra opcode byte, 4 displacement bytes. */
561 /* word conditionals add 3 bytes to frag:
562 1 extra opcode byte, 2 displacement bytes. */
565 /* COND_JUMP86 states. */
566 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
567 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
568 /* dword conditionals adds 5 bytes to frag:
569 1 extra opcode byte, 4 displacement bytes. */
571 /* word conditionals add 4 bytes to frag:
572 1 displacement byte and a 3 byte long branch insn. */
576 static const arch_entry cpu_arch
[] =
578 { "generic32", PROCESSOR_GENERIC32
,
579 CPU_GENERIC32_FLAGS
},
580 { "generic64", PROCESSOR_GENERIC64
,
581 CPU_GENERIC64_FLAGS
},
582 { "i8086", PROCESSOR_UNKNOWN
,
584 { "i186", PROCESSOR_UNKNOWN
,
586 { "i286", PROCESSOR_UNKNOWN
,
588 { "i386", PROCESSOR_I386
,
590 { "i486", PROCESSOR_I486
,
592 { "i586", PROCESSOR_PENTIUM
,
594 { "i686", PROCESSOR_PENTIUMPRO
,
596 { "pentium", PROCESSOR_PENTIUM
,
598 { "pentiumpro", PROCESSOR_PENTIUMPRO
,
600 { "pentiumii", PROCESSOR_PENTIUMPRO
,
602 { "pentiumiii",PROCESSOR_PENTIUMPRO
,
604 { "pentium4", PROCESSOR_PENTIUM4
,
606 { "prescott", PROCESSOR_NOCONA
,
608 { "nocona", PROCESSOR_NOCONA
,
610 { "yonah", PROCESSOR_CORE
,
612 { "core", PROCESSOR_CORE
,
614 { "merom", PROCESSOR_CORE2
,
616 { "core2", PROCESSOR_CORE2
,
618 { "k6", PROCESSOR_K6
,
620 { "k6_2", PROCESSOR_K6
,
622 { "athlon", PROCESSOR_ATHLON
,
624 { "sledgehammer", PROCESSOR_K8
,
626 { "opteron", PROCESSOR_K8
,
628 { "k8", PROCESSOR_K8
,
630 { "amdfam10", PROCESSOR_AMDFAM10
,
631 CPU_AMDFAM10_FLAGS
},
632 { ".mmx", PROCESSOR_UNKNOWN
,
634 { ".sse", PROCESSOR_UNKNOWN
,
636 { ".sse2", PROCESSOR_UNKNOWN
,
638 { ".sse3", PROCESSOR_UNKNOWN
,
640 { ".ssse3", PROCESSOR_UNKNOWN
,
642 { ".sse4.1", PROCESSOR_UNKNOWN
,
644 { ".sse4.2", PROCESSOR_UNKNOWN
,
646 { ".sse4", PROCESSOR_UNKNOWN
,
648 { ".avx", PROCESSOR_UNKNOWN
,
650 { ".vmx", PROCESSOR_UNKNOWN
,
652 { ".smx", PROCESSOR_UNKNOWN
,
654 { ".xsave", PROCESSOR_UNKNOWN
,
656 { ".aes", PROCESSOR_UNKNOWN
,
658 { ".pclmul", PROCESSOR_UNKNOWN
,
660 { ".clmul", PROCESSOR_UNKNOWN
,
662 { ".fma", PROCESSOR_UNKNOWN
,
664 { ".3dnow", PROCESSOR_UNKNOWN
,
666 { ".3dnowa", PROCESSOR_UNKNOWN
,
668 { ".padlock", PROCESSOR_UNKNOWN
,
670 { ".pacifica", PROCESSOR_UNKNOWN
,
672 { ".svme", PROCESSOR_UNKNOWN
,
674 { ".sse4a", PROCESSOR_UNKNOWN
,
676 { ".abm", PROCESSOR_UNKNOWN
,
678 { ".sse5", PROCESSOR_UNKNOWN
,
682 const pseudo_typeS md_pseudo_table
[] =
684 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
685 {"align", s_align_bytes
, 0},
687 {"align", s_align_ptwo
, 0},
689 {"arch", set_cpu_arch
, 0},
693 {"ffloat", float_cons
, 'f'},
694 {"dfloat", float_cons
, 'd'},
695 {"tfloat", float_cons
, 'x'},
697 {"slong", signed_cons
, 4},
698 {"noopt", s_ignore
, 0},
699 {"optim", s_ignore
, 0},
700 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
701 {"code16", set_code_flag
, CODE_16BIT
},
702 {"code32", set_code_flag
, CODE_32BIT
},
703 {"code64", set_code_flag
, CODE_64BIT
},
704 {"intel_syntax", set_intel_syntax
, 1},
705 {"att_syntax", set_intel_syntax
, 0},
706 {"intel_mnemonic", set_intel_mnemonic
, 1},
707 {"att_mnemonic", set_intel_mnemonic
, 0},
708 {"allow_index_reg", set_allow_index_reg
, 1},
709 {"disallow_index_reg", set_allow_index_reg
, 0},
710 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
711 {"largecomm", handle_large_common
, 0},
713 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
714 {"loc", dwarf2_directive_loc
, 0},
715 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
718 {"secrel32", pe_directive_secrel
, 0},
723 /* For interface with expression (). */
724 extern char *input_line_pointer
;
726 /* Hash table for instruction mnemonic lookup. */
727 static struct hash_control
*op_hash
;
729 /* Hash table for register lookup. */
730 static struct hash_control
*reg_hash
;
733 i386_align_code (fragS
*fragP
, int count
)
735 /* Various efficient no-op patterns for aligning code labels.
736 Note: Don't try to assemble the instructions in the comments.
737 0L and 0w are not legal. */
738 static const char f32_1
[] =
740 static const char f32_2
[] =
741 {0x66,0x90}; /* xchg %ax,%ax */
742 static const char f32_3
[] =
743 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
744 static const char f32_4
[] =
745 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
746 static const char f32_5
[] =
748 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
749 static const char f32_6
[] =
750 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
751 static const char f32_7
[] =
752 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
753 static const char f32_8
[] =
755 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
756 static const char f32_9
[] =
757 {0x89,0xf6, /* movl %esi,%esi */
758 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
759 static const char f32_10
[] =
760 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
761 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
762 static const char f32_11
[] =
763 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
764 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
765 static const char f32_12
[] =
766 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
767 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
768 static const char f32_13
[] =
769 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
770 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
771 static const char f32_14
[] =
772 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
773 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
774 static const char f16_3
[] =
775 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
776 static const char f16_4
[] =
777 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
778 static const char f16_5
[] =
780 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
781 static const char f16_6
[] =
782 {0x89,0xf6, /* mov %si,%si */
783 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
784 static const char f16_7
[] =
785 {0x8d,0x74,0x00, /* lea 0(%si),%si */
786 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
787 static const char f16_8
[] =
788 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
789 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
790 static const char jump_31
[] =
791 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
792 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
793 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
794 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
795 static const char *const f32_patt
[] = {
796 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
797 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
799 static const char *const f16_patt
[] = {
800 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
803 static const char alt_3
[] =
805 /* nopl 0(%[re]ax) */
806 static const char alt_4
[] =
807 {0x0f,0x1f,0x40,0x00};
808 /* nopl 0(%[re]ax,%[re]ax,1) */
809 static const char alt_5
[] =
810 {0x0f,0x1f,0x44,0x00,0x00};
811 /* nopw 0(%[re]ax,%[re]ax,1) */
812 static const char alt_6
[] =
813 {0x66,0x0f,0x1f,0x44,0x00,0x00};
814 /* nopl 0L(%[re]ax) */
815 static const char alt_7
[] =
816 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
817 /* nopl 0L(%[re]ax,%[re]ax,1) */
818 static const char alt_8
[] =
819 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
820 /* nopw 0L(%[re]ax,%[re]ax,1) */
821 static const char alt_9
[] =
822 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
823 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
824 static const char alt_10
[] =
825 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
827 nopw %cs:0L(%[re]ax,%[re]ax,1) */
828 static const char alt_long_11
[] =
830 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
833 nopw %cs:0L(%[re]ax,%[re]ax,1) */
834 static const char alt_long_12
[] =
837 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
841 nopw %cs:0L(%[re]ax,%[re]ax,1) */
842 static const char alt_long_13
[] =
846 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
851 nopw %cs:0L(%[re]ax,%[re]ax,1) */
852 static const char alt_long_14
[] =
857 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
863 nopw %cs:0L(%[re]ax,%[re]ax,1) */
864 static const char alt_long_15
[] =
870 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
871 /* nopl 0(%[re]ax,%[re]ax,1)
872 nopw 0(%[re]ax,%[re]ax,1) */
873 static const char alt_short_11
[] =
874 {0x0f,0x1f,0x44,0x00,0x00,
875 0x66,0x0f,0x1f,0x44,0x00,0x00};
876 /* nopw 0(%[re]ax,%[re]ax,1)
877 nopw 0(%[re]ax,%[re]ax,1) */
878 static const char alt_short_12
[] =
879 {0x66,0x0f,0x1f,0x44,0x00,0x00,
880 0x66,0x0f,0x1f,0x44,0x00,0x00};
881 /* nopw 0(%[re]ax,%[re]ax,1)
883 static const char alt_short_13
[] =
884 {0x66,0x0f,0x1f,0x44,0x00,0x00,
885 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
888 static const char alt_short_14
[] =
889 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
890 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
892 nopl 0L(%[re]ax,%[re]ax,1) */
893 static const char alt_short_15
[] =
894 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
895 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
896 static const char *const alt_short_patt
[] = {
897 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
898 alt_9
, alt_10
, alt_short_11
, alt_short_12
, alt_short_13
,
899 alt_short_14
, alt_short_15
901 static const char *const alt_long_patt
[] = {
902 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
903 alt_9
, alt_10
, alt_long_11
, alt_long_12
, alt_long_13
,
904 alt_long_14
, alt_long_15
907 /* Only align for at least a positive non-zero boundary. */
908 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
911 /* We need to decide which NOP sequence to use for 32bit and
912 64bit. When -mtune= is used:
914 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
915 PROCESSOR_GENERIC32, f32_patt will be used.
916 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
917 PROCESSOR_CORE, PROCESSOR_CORE2, and PROCESSOR_GENERIC64,
918 alt_long_patt will be used.
919 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
920 PROCESSOR_AMDFAM10, alt_short_patt will be used.
922 When -mtune= isn't used, alt_long_patt will be used if
923 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
926 When -march= or .arch is used, we can't use anything beyond
927 cpu_arch_isa_flags. */
929 if (flag_code
== CODE_16BIT
)
933 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
935 /* Adjust jump offset. */
936 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
939 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
940 f16_patt
[count
- 1], count
);
944 const char *const *patt
= NULL
;
946 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
948 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
949 switch (cpu_arch_tune
)
951 case PROCESSOR_UNKNOWN
:
952 /* We use cpu_arch_isa_flags to check if we SHOULD
953 optimize for Cpu686. */
954 if (cpu_arch_isa_flags
.bitfield
.cpui686
)
955 patt
= alt_long_patt
;
959 case PROCESSOR_PENTIUMPRO
:
960 case PROCESSOR_PENTIUM4
:
961 case PROCESSOR_NOCONA
:
963 case PROCESSOR_CORE2
:
964 case PROCESSOR_GENERIC64
:
965 patt
= alt_long_patt
;
968 case PROCESSOR_ATHLON
:
970 case PROCESSOR_AMDFAM10
:
971 patt
= alt_short_patt
;
975 case PROCESSOR_PENTIUM
:
976 case PROCESSOR_GENERIC32
:
983 switch (cpu_arch_tune
)
985 case PROCESSOR_UNKNOWN
:
986 /* When cpu_arch_isa is net, cpu_arch_tune shouldn't be
987 PROCESSOR_UNKNOWN. */
993 case PROCESSOR_PENTIUM
:
995 case PROCESSOR_ATHLON
:
997 case PROCESSOR_AMDFAM10
:
998 case PROCESSOR_GENERIC32
:
999 /* We use cpu_arch_isa_flags to check if we CAN optimize
1001 if (cpu_arch_isa_flags
.bitfield
.cpui686
)
1002 patt
= alt_short_patt
;
1006 case PROCESSOR_PENTIUMPRO
:
1007 case PROCESSOR_PENTIUM4
:
1008 case PROCESSOR_NOCONA
:
1009 case PROCESSOR_CORE
:
1010 case PROCESSOR_CORE2
:
1011 if (cpu_arch_isa_flags
.bitfield
.cpui686
)
1012 patt
= alt_long_patt
;
1016 case PROCESSOR_GENERIC64
:
1017 patt
= alt_long_patt
;
1022 if (patt
== f32_patt
)
1024 /* If the padding is less than 15 bytes, we use the normal
1025 ones. Otherwise, we use a jump instruction and adjust
1028 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1029 patt
[count
- 1], count
);
1032 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1034 /* Adjust jump offset. */
1035 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1040 /* Maximum length of an instruction is 15 byte. If the
1041 padding is greater than 15 bytes and we don't use jump,
1042 we have to break it into smaller pieces. */
1043 int padding
= count
;
1044 while (padding
> 15)
1047 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1052 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1053 patt
[padding
- 1], padding
);
1056 fragP
->fr_var
= count
;
1060 operand_type_all_zero (const union i386_operand_type
*x
)
1062 switch (ARRAY_SIZE(x
->array
))
1071 return !x
->array
[0];
1078 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1080 switch (ARRAY_SIZE(x
->array
))
1095 operand_type_equal (const union i386_operand_type
*x
,
1096 const union i386_operand_type
*y
)
1098 switch (ARRAY_SIZE(x
->array
))
1101 if (x
->array
[2] != y
->array
[2])
1104 if (x
->array
[1] != y
->array
[1])
1107 return x
->array
[0] == y
->array
[0];
1115 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1117 switch (ARRAY_SIZE(x
->array
))
1126 return !x
->array
[0];
1133 cpu_flags_set (union i386_cpu_flags
*x
, unsigned int v
)
1135 switch (ARRAY_SIZE(x
->array
))
1150 cpu_flags_equal (const union i386_cpu_flags
*x
,
1151 const union i386_cpu_flags
*y
)
1153 switch (ARRAY_SIZE(x
->array
))
1156 if (x
->array
[2] != y
->array
[2])
1159 if (x
->array
[1] != y
->array
[1])
1162 return x
->array
[0] == y
->array
[0];
1170 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1172 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1173 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1176 static INLINE i386_cpu_flags
1177 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1179 switch (ARRAY_SIZE (x
.array
))
1182 x
.array
[2] &= y
.array
[2];
1184 x
.array
[1] &= y
.array
[1];
1186 x
.array
[0] &= y
.array
[0];
1194 static INLINE i386_cpu_flags
1195 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1197 switch (ARRAY_SIZE (x
.array
))
1200 x
.array
[2] |= y
.array
[2];
1202 x
.array
[1] |= y
.array
[1];
1204 x
.array
[0] |= y
.array
[0];
1212 #define CPU_FLAGS_ARCH_MATCH 0x1
1213 #define CPU_FLAGS_64BIT_MATCH 0x2
1215 #define CPU_FLAGS_32BIT_MATCH CPU_FLAGS_ARCH_MATCH
1216 #define CPU_FLAGS_PERFECT_MATCH \
1217 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1219 /* Return CPU flags match bits. */
1222 cpu_flags_match (const template *t
)
1224 i386_cpu_flags x
= t
->cpu_flags
;
1225 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1227 x
.bitfield
.cpu64
= 0;
1228 x
.bitfield
.cpuno64
= 0;
1230 if (cpu_flags_all_zero (&x
))
1232 /* This instruction is available on all archs. */
1233 match
|= CPU_FLAGS_32BIT_MATCH
;
1237 /* This instruction is available only on some archs. */
1238 i386_cpu_flags cpu
= cpu_arch_flags
;
1240 cpu
.bitfield
.cpu64
= 0;
1241 cpu
.bitfield
.cpuno64
= 0;
1242 cpu
= cpu_flags_and (x
, cpu
);
1243 if (!cpu_flags_all_zero (&cpu
))
1246 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1247 match
|= CPU_FLAGS_32BIT_MATCH
;
1253 static INLINE i386_operand_type
1254 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1256 switch (ARRAY_SIZE (x
.array
))
1259 x
.array
[2] &= y
.array
[2];
1261 x
.array
[1] &= y
.array
[1];
1263 x
.array
[0] &= y
.array
[0];
1271 static INLINE i386_operand_type
1272 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1274 switch (ARRAY_SIZE (x
.array
))
1277 x
.array
[2] |= y
.array
[2];
1279 x
.array
[1] |= y
.array
[1];
1281 x
.array
[0] |= y
.array
[0];
1289 static INLINE i386_operand_type
1290 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1292 switch (ARRAY_SIZE (x
.array
))
1295 x
.array
[2] ^= y
.array
[2];
1297 x
.array
[1] ^= y
.array
[1];
1299 x
.array
[0] ^= y
.array
[0];
1307 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1308 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1309 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1310 static const i386_operand_type inoutportreg
1311 = OPERAND_TYPE_INOUTPORTREG
;
1312 static const i386_operand_type reg16_inoutportreg
1313 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1314 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1315 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1316 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1317 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1318 static const i386_operand_type anydisp
1319 = OPERAND_TYPE_ANYDISP
;
1320 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1321 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1322 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1323 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1324 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1325 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1326 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1327 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1328 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1329 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1330 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1331 static const i386_operand_type vex_imm4
= OPERAND_TYPE_VEX_IMM4
;
1342 operand_type_check (i386_operand_type t
, enum operand_type c
)
1347 return (t
.bitfield
.reg8
1350 || t
.bitfield
.reg64
);
1353 return (t
.bitfield
.imm8
1357 || t
.bitfield
.imm32s
1358 || t
.bitfield
.imm64
);
1361 return (t
.bitfield
.disp8
1362 || t
.bitfield
.disp16
1363 || t
.bitfield
.disp32
1364 || t
.bitfield
.disp32s
1365 || t
.bitfield
.disp64
);
1368 return (t
.bitfield
.disp8
1369 || t
.bitfield
.disp16
1370 || t
.bitfield
.disp32
1371 || t
.bitfield
.disp32s
1372 || t
.bitfield
.disp64
1373 || t
.bitfield
.baseindex
);
1380 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1381 operand J for instruction template T. */
1384 match_reg_size (const template *t
, unsigned int j
)
1386 return !((i
.types
[j
].bitfield
.byte
1387 && !t
->operand_types
[j
].bitfield
.byte
)
1388 || (i
.types
[j
].bitfield
.word
1389 && !t
->operand_types
[j
].bitfield
.word
)
1390 || (i
.types
[j
].bitfield
.dword
1391 && !t
->operand_types
[j
].bitfield
.dword
)
1392 || (i
.types
[j
].bitfield
.qword
1393 && !t
->operand_types
[j
].bitfield
.qword
));
1396 /* Return 1 if there is no conflict in any size on operand J for
1397 instruction template T. */
1400 match_mem_size (const template *t
, unsigned int j
)
1402 return (match_reg_size (t
, j
)
1403 && !((i
.types
[j
].bitfield
.unspecified
1404 && !t
->operand_types
[j
].bitfield
.unspecified
)
1405 || (i
.types
[j
].bitfield
.fword
1406 && !t
->operand_types
[j
].bitfield
.fword
)
1407 || (i
.types
[j
].bitfield
.tbyte
1408 && !t
->operand_types
[j
].bitfield
.tbyte
)
1409 || (i
.types
[j
].bitfield
.xmmword
1410 && !t
->operand_types
[j
].bitfield
.xmmword
)
1411 || (i
.types
[j
].bitfield
.ymmword
1412 && !t
->operand_types
[j
].bitfield
.ymmword
)));
1415 /* Return 1 if there is no size conflict on any operands for
1416 instruction template T. */
1419 operand_size_match (const template *t
)
1424 /* Don't check jump instructions. */
1425 if (t
->opcode_modifier
.jump
1426 || t
->opcode_modifier
.jumpbyte
1427 || t
->opcode_modifier
.jumpdword
1428 || t
->opcode_modifier
.jumpintersegment
)
1431 /* Check memory and accumulator operand size. */
1432 for (j
= 0; j
< i
.operands
; j
++)
1434 if (t
->operand_types
[j
].bitfield
.anysize
)
1437 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1443 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1451 || (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
))
1454 /* Check reverse. */
1455 assert (i
.operands
== 2);
1458 for (j
= 0; j
< 2; j
++)
1460 if (t
->operand_types
[j
].bitfield
.acc
1461 && !match_reg_size (t
, j
? 0 : 1))
1467 if (i
.types
[j
].bitfield
.mem
1468 && !match_mem_size (t
, j
? 0 : 1))
1479 operand_type_match (i386_operand_type overlap
,
1480 i386_operand_type given
)
1482 i386_operand_type temp
= overlap
;
1484 temp
.bitfield
.jumpabsolute
= 0;
1485 temp
.bitfield
.unspecified
= 0;
1486 temp
.bitfield
.byte
= 0;
1487 temp
.bitfield
.word
= 0;
1488 temp
.bitfield
.dword
= 0;
1489 temp
.bitfield
.fword
= 0;
1490 temp
.bitfield
.qword
= 0;
1491 temp
.bitfield
.tbyte
= 0;
1492 temp
.bitfield
.xmmword
= 0;
1493 temp
.bitfield
.ymmword
= 0;
1494 if (operand_type_all_zero (&temp
))
1497 return (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1498 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
);
1501 /* If given types g0 and g1 are registers they must be of the same type
1502 unless the expected operand type register overlap is null.
1503 Note that Acc in a template matches every size of reg. */
1506 operand_type_register_match (i386_operand_type m0
,
1507 i386_operand_type g0
,
1508 i386_operand_type t0
,
1509 i386_operand_type m1
,
1510 i386_operand_type g1
,
1511 i386_operand_type t1
)
1513 if (!operand_type_check (g0
, reg
))
1516 if (!operand_type_check (g1
, reg
))
1519 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1520 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1521 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1522 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1525 if (m0
.bitfield
.acc
)
1527 t0
.bitfield
.reg8
= 1;
1528 t0
.bitfield
.reg16
= 1;
1529 t0
.bitfield
.reg32
= 1;
1530 t0
.bitfield
.reg64
= 1;
1533 if (m1
.bitfield
.acc
)
1535 t1
.bitfield
.reg8
= 1;
1536 t1
.bitfield
.reg16
= 1;
1537 t1
.bitfield
.reg32
= 1;
1538 t1
.bitfield
.reg64
= 1;
1541 return (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1542 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1543 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1544 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
));
1547 static INLINE
unsigned int
1548 mode_from_disp_size (i386_operand_type t
)
1550 if (t
.bitfield
.disp8
)
1552 else if (t
.bitfield
.disp16
1553 || t
.bitfield
.disp32
1554 || t
.bitfield
.disp32s
)
1561 fits_in_signed_byte (offsetT num
)
1563 return (num
>= -128) && (num
<= 127);
1567 fits_in_unsigned_byte (offsetT num
)
1569 return (num
& 0xff) == num
;
1573 fits_in_unsigned_word (offsetT num
)
1575 return (num
& 0xffff) == num
;
1579 fits_in_signed_word (offsetT num
)
1581 return (-32768 <= num
) && (num
<= 32767);
1585 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED
)
1590 return (!(((offsetT
) -1 << 31) & num
)
1591 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
1593 } /* fits_in_signed_long() */
1596 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED
)
1601 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
1603 } /* fits_in_unsigned_long() */
1606 fits_in_imm4 (offsetT num
)
1608 return (num
& 0xf) == num
;
1611 static i386_operand_type
1612 smallest_imm_type (offsetT num
)
1614 i386_operand_type t
;
1616 operand_type_set (&t
, 0);
1617 t
.bitfield
.imm64
= 1;
1619 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
1621 /* This code is disabled on the 486 because all the Imm1 forms
1622 in the opcode table are slower on the i486. They're the
1623 versions with the implicitly specified single-position
1624 displacement, which has another syntax if you really want to
1626 t
.bitfield
.imm1
= 1;
1627 t
.bitfield
.imm8
= 1;
1628 t
.bitfield
.imm8s
= 1;
1629 t
.bitfield
.imm16
= 1;
1630 t
.bitfield
.imm32
= 1;
1631 t
.bitfield
.imm32s
= 1;
1633 else if (fits_in_signed_byte (num
))
1635 t
.bitfield
.imm8
= 1;
1636 t
.bitfield
.imm8s
= 1;
1637 t
.bitfield
.imm16
= 1;
1638 t
.bitfield
.imm32
= 1;
1639 t
.bitfield
.imm32s
= 1;
1641 else if (fits_in_unsigned_byte (num
))
1643 t
.bitfield
.imm8
= 1;
1644 t
.bitfield
.imm16
= 1;
1645 t
.bitfield
.imm32
= 1;
1646 t
.bitfield
.imm32s
= 1;
1648 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
1650 t
.bitfield
.imm16
= 1;
1651 t
.bitfield
.imm32
= 1;
1652 t
.bitfield
.imm32s
= 1;
1654 else if (fits_in_signed_long (num
))
1656 t
.bitfield
.imm32
= 1;
1657 t
.bitfield
.imm32s
= 1;
1659 else if (fits_in_unsigned_long (num
))
1660 t
.bitfield
.imm32
= 1;
1666 offset_in_range (offsetT val
, int size
)
1672 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
1673 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
1674 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
1676 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
1681 /* If BFD64, sign extend val. */
1682 if (!use_rela_relocations
)
1683 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
1684 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
1686 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
1688 char buf1
[40], buf2
[40];
1690 sprint_value (buf1
, val
);
1691 sprint_value (buf2
, val
& mask
);
1692 as_warn (_("%s shortened to %s"), buf1
, buf2
);
1697 /* Returns 0 if attempting to add a prefix where one from the same
1698 class already exists, 1 if non rep/repne added, 2 if rep/repne
1701 add_prefix (unsigned int prefix
)
1706 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
1707 && flag_code
== CODE_64BIT
)
1709 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
1710 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
1711 && (prefix
& (REX_R
| REX_X
| REX_B
))))
1722 case CS_PREFIX_OPCODE
:
1723 case DS_PREFIX_OPCODE
:
1724 case ES_PREFIX_OPCODE
:
1725 case FS_PREFIX_OPCODE
:
1726 case GS_PREFIX_OPCODE
:
1727 case SS_PREFIX_OPCODE
:
1731 case REPNE_PREFIX_OPCODE
:
1732 case REPE_PREFIX_OPCODE
:
1735 case LOCK_PREFIX_OPCODE
:
1743 case ADDR_PREFIX_OPCODE
:
1747 case DATA_PREFIX_OPCODE
:
1751 if (i
.prefix
[q
] != 0)
1759 i
.prefix
[q
] |= prefix
;
1762 as_bad (_("same type of prefix used twice"));
1768 set_code_flag (int value
)
1771 if (flag_code
== CODE_64BIT
)
1773 cpu_arch_flags
.bitfield
.cpu64
= 1;
1774 cpu_arch_flags
.bitfield
.cpuno64
= 0;
1778 cpu_arch_flags
.bitfield
.cpu64
= 0;
1779 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1781 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
1783 as_bad (_("64bit mode not supported on this CPU."));
1785 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
1787 as_bad (_("32bit mode not supported on this CPU."));
1789 stackop_size
= '\0';
1793 set_16bit_gcc_code_flag (int new_code_flag
)
1795 flag_code
= new_code_flag
;
1796 if (flag_code
!= CODE_16BIT
)
1798 cpu_arch_flags
.bitfield
.cpu64
= 0;
1799 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1800 stackop_size
= LONG_MNEM_SUFFIX
;
1804 set_intel_syntax (int syntax_flag
)
1806 /* Find out if register prefixing is specified. */
1807 int ask_naked_reg
= 0;
1810 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1812 char *string
= input_line_pointer
;
1813 int e
= get_symbol_end ();
1815 if (strcmp (string
, "prefix") == 0)
1817 else if (strcmp (string
, "noprefix") == 0)
1820 as_bad (_("bad argument to syntax directive."));
1821 *input_line_pointer
= e
;
1823 demand_empty_rest_of_line ();
1825 intel_syntax
= syntax_flag
;
1827 if (ask_naked_reg
== 0)
1828 allow_naked_reg
= (intel_syntax
1829 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
1831 allow_naked_reg
= (ask_naked_reg
< 0);
1833 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
1834 identifier_chars
['$'] = intel_syntax
? '$' : 0;
1835 register_prefix
= allow_naked_reg
? "" : "%";
1839 set_intel_mnemonic (int mnemonic_flag
)
1841 intel_mnemonic
= mnemonic_flag
;
1845 set_allow_index_reg (int flag
)
1847 allow_index_reg
= flag
;
1851 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
1855 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1857 char *string
= input_line_pointer
;
1858 int e
= get_symbol_end ();
1860 i386_cpu_flags flags
;
1862 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
1864 if (strcmp (string
, cpu_arch
[i
].name
) == 0)
1868 cpu_arch_name
= cpu_arch
[i
].name
;
1869 cpu_sub_arch_name
= NULL
;
1870 cpu_arch_flags
= cpu_arch
[i
].flags
;
1871 if (flag_code
== CODE_64BIT
)
1873 cpu_arch_flags
.bitfield
.cpu64
= 1;
1874 cpu_arch_flags
.bitfield
.cpuno64
= 0;
1878 cpu_arch_flags
.bitfield
.cpu64
= 0;
1879 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1881 cpu_arch_isa
= cpu_arch
[i
].type
;
1882 cpu_arch_isa_flags
= cpu_arch
[i
].flags
;
1883 if (!cpu_arch_tune_set
)
1885 cpu_arch_tune
= cpu_arch_isa
;
1886 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
1891 flags
= cpu_flags_or (cpu_arch_flags
,
1893 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
1895 if (cpu_sub_arch_name
)
1897 char *name
= cpu_sub_arch_name
;
1898 cpu_sub_arch_name
= concat (name
,
1900 (const char *) NULL
);
1904 cpu_sub_arch_name
= xstrdup (cpu_arch
[i
].name
);
1905 cpu_arch_flags
= flags
;
1907 *input_line_pointer
= e
;
1908 demand_empty_rest_of_line ();
1912 if (i
>= ARRAY_SIZE (cpu_arch
))
1913 as_bad (_("no such architecture: `%s'"), string
);
1915 *input_line_pointer
= e
;
1918 as_bad (_("missing cpu architecture"));
1920 no_cond_jump_promotion
= 0;
1921 if (*input_line_pointer
== ','
1922 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
1924 char *string
= ++input_line_pointer
;
1925 int e
= get_symbol_end ();
1927 if (strcmp (string
, "nojumps") == 0)
1928 no_cond_jump_promotion
= 1;
1929 else if (strcmp (string
, "jumps") == 0)
1932 as_bad (_("no such architecture modifier: `%s'"), string
);
1934 *input_line_pointer
= e
;
1937 demand_empty_rest_of_line ();
1943 if (!strcmp (default_arch
, "x86_64"))
1944 return bfd_mach_x86_64
;
1945 else if (!strcmp (default_arch
, "i386"))
1946 return bfd_mach_i386_i386
;
1948 as_fatal (_("Unknown architecture"));
1954 const char *hash_err
;
1956 /* Initialize op_hash hash table. */
1957 op_hash
= hash_new ();
1960 const template *optab
;
1961 templates
*core_optab
;
1963 /* Setup for loop. */
1965 core_optab
= (templates
*) xmalloc (sizeof (templates
));
1966 core_optab
->start
= optab
;
1971 if (optab
->name
== NULL
1972 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
1974 /* different name --> ship out current template list;
1975 add to hash table; & begin anew. */
1976 core_optab
->end
= optab
;
1977 hash_err
= hash_insert (op_hash
,
1982 as_fatal (_("Internal Error: Can't hash %s: %s"),
1986 if (optab
->name
== NULL
)
1988 core_optab
= (templates
*) xmalloc (sizeof (templates
));
1989 core_optab
->start
= optab
;
1994 /* Initialize reg_hash hash table. */
1995 reg_hash
= hash_new ();
1997 const reg_entry
*regtab
;
1998 unsigned int regtab_size
= i386_regtab_size
;
2000 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2002 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (PTR
) regtab
);
2004 as_fatal (_("Internal Error: Can't hash %s: %s"),
2010 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2015 for (c
= 0; c
< 256; c
++)
2020 mnemonic_chars
[c
] = c
;
2021 register_chars
[c
] = c
;
2022 operand_chars
[c
] = c
;
2024 else if (ISLOWER (c
))
2026 mnemonic_chars
[c
] = c
;
2027 register_chars
[c
] = c
;
2028 operand_chars
[c
] = c
;
2030 else if (ISUPPER (c
))
2032 mnemonic_chars
[c
] = TOLOWER (c
);
2033 register_chars
[c
] = mnemonic_chars
[c
];
2034 operand_chars
[c
] = c
;
2037 if (ISALPHA (c
) || ISDIGIT (c
))
2038 identifier_chars
[c
] = c
;
2041 identifier_chars
[c
] = c
;
2042 operand_chars
[c
] = c
;
2047 identifier_chars
['@'] = '@';
2050 identifier_chars
['?'] = '?';
2051 operand_chars
['?'] = '?';
2053 digit_chars
['-'] = '-';
2054 mnemonic_chars
['_'] = '_';
2055 mnemonic_chars
['-'] = '-';
2056 mnemonic_chars
['.'] = '.';
2057 identifier_chars
['_'] = '_';
2058 identifier_chars
['.'] = '.';
2060 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2061 operand_chars
[(unsigned char) *p
] = *p
;
2064 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2067 record_alignment (text_section
, 2);
2068 record_alignment (data_section
, 2);
2069 record_alignment (bss_section
, 2);
2073 if (flag_code
== CODE_64BIT
)
2075 x86_dwarf2_return_column
= 16;
2076 x86_cie_data_alignment
= -8;
2080 x86_dwarf2_return_column
= 8;
2081 x86_cie_data_alignment
= -4;
2086 i386_print_statistics (FILE *file
)
2088 hash_print_statistics (file
, "i386 opcode", op_hash
);
2089 hash_print_statistics (file
, "i386 register", reg_hash
);
2094 /* Debugging routines for md_assemble. */
2095 static void pte (template *);
2096 static void pt (i386_operand_type
);
2097 static void pe (expressionS
*);
2098 static void ps (symbolS
*);
2101 pi (char *line
, i386_insn
*x
)
2105 fprintf (stdout
, "%s: template ", line
);
2107 fprintf (stdout
, " address: base %s index %s scale %x\n",
2108 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2109 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2110 x
->log2_scale_factor
);
2111 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2112 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2113 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2114 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2115 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2116 (x
->rex
& REX_W
) != 0,
2117 (x
->rex
& REX_R
) != 0,
2118 (x
->rex
& REX_X
) != 0,
2119 (x
->rex
& REX_B
) != 0);
2120 fprintf (stdout
, " drex: reg %d rex 0x%x\n",
2121 x
->drex
.reg
, x
->drex
.rex
);
2122 for (i
= 0; i
< x
->operands
; i
++)
2124 fprintf (stdout
, " #%d: ", i
+ 1);
2126 fprintf (stdout
, "\n");
2127 if (x
->types
[i
].bitfield
.reg8
2128 || x
->types
[i
].bitfield
.reg16
2129 || x
->types
[i
].bitfield
.reg32
2130 || x
->types
[i
].bitfield
.reg64
2131 || x
->types
[i
].bitfield
.regmmx
2132 || x
->types
[i
].bitfield
.regxmm
2133 || x
->types
[i
].bitfield
.regymm
2134 || x
->types
[i
].bitfield
.sreg2
2135 || x
->types
[i
].bitfield
.sreg3
2136 || x
->types
[i
].bitfield
.control
2137 || x
->types
[i
].bitfield
.debug
2138 || x
->types
[i
].bitfield
.test
)
2139 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
2140 if (operand_type_check (x
->types
[i
], imm
))
2142 if (operand_type_check (x
->types
[i
], disp
))
2143 pe (x
->op
[i
].disps
);
2151 fprintf (stdout
, " %d operands ", t
->operands
);
2152 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2153 if (t
->extension_opcode
!= None
)
2154 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2155 if (t
->opcode_modifier
.d
)
2156 fprintf (stdout
, "D");
2157 if (t
->opcode_modifier
.w
)
2158 fprintf (stdout
, "W");
2159 fprintf (stdout
, "\n");
2160 for (i
= 0; i
< t
->operands
; i
++)
2162 fprintf (stdout
, " #%d type ", i
+ 1);
2163 pt (t
->operand_types
[i
]);
2164 fprintf (stdout
, "\n");
2171 fprintf (stdout
, " operation %d\n", e
->X_op
);
2172 fprintf (stdout
, " add_number %ld (%lx)\n",
2173 (long) e
->X_add_number
, (long) e
->X_add_number
);
2174 if (e
->X_add_symbol
)
2176 fprintf (stdout
, " add_symbol ");
2177 ps (e
->X_add_symbol
);
2178 fprintf (stdout
, "\n");
2182 fprintf (stdout
, " op_symbol ");
2183 ps (e
->X_op_symbol
);
2184 fprintf (stdout
, "\n");
2191 fprintf (stdout
, "%s type %s%s",
2193 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2194 segment_name (S_GET_SEGMENT (s
)));
2197 static struct type_name
2199 i386_operand_type mask
;
2202 const type_names
[] =
2204 { OPERAND_TYPE_REG8
, "r8" },
2205 { OPERAND_TYPE_REG16
, "r16" },
2206 { OPERAND_TYPE_REG32
, "r32" },
2207 { OPERAND_TYPE_REG64
, "r64" },
2208 { OPERAND_TYPE_IMM8
, "i8" },
2209 { OPERAND_TYPE_IMM8
, "i8s" },
2210 { OPERAND_TYPE_IMM16
, "i16" },
2211 { OPERAND_TYPE_IMM32
, "i32" },
2212 { OPERAND_TYPE_IMM32S
, "i32s" },
2213 { OPERAND_TYPE_IMM64
, "i64" },
2214 { OPERAND_TYPE_IMM1
, "i1" },
2215 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2216 { OPERAND_TYPE_DISP8
, "d8" },
2217 { OPERAND_TYPE_DISP16
, "d16" },
2218 { OPERAND_TYPE_DISP32
, "d32" },
2219 { OPERAND_TYPE_DISP32S
, "d32s" },
2220 { OPERAND_TYPE_DISP64
, "d64" },
2221 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2222 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2223 { OPERAND_TYPE_CONTROL
, "control reg" },
2224 { OPERAND_TYPE_TEST
, "test reg" },
2225 { OPERAND_TYPE_DEBUG
, "debug reg" },
2226 { OPERAND_TYPE_FLOATREG
, "FReg" },
2227 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2228 { OPERAND_TYPE_SREG2
, "SReg2" },
2229 { OPERAND_TYPE_SREG3
, "SReg3" },
2230 { OPERAND_TYPE_ACC
, "Acc" },
2231 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2232 { OPERAND_TYPE_REGMMX
, "rMMX" },
2233 { OPERAND_TYPE_REGXMM
, "rXMM" },
2234 { OPERAND_TYPE_ESSEG
, "es" },
2235 { OPERAND_TYPE_VEX_IMM4
, "VEX i4" },
2239 pt (i386_operand_type t
)
2242 i386_operand_type a
;
2244 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2246 a
= operand_type_and (t
, type_names
[j
].mask
);
2247 if (!UINTS_ALL_ZERO (a
))
2248 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2253 #endif /* DEBUG386 */
2255 static bfd_reloc_code_real_type
2256 reloc (unsigned int size
,
2259 bfd_reloc_code_real_type other
)
2261 if (other
!= NO_RELOC
)
2263 reloc_howto_type
*reloc
;
2268 case BFD_RELOC_X86_64_GOT32
:
2269 return BFD_RELOC_X86_64_GOT64
;
2271 case BFD_RELOC_X86_64_PLTOFF64
:
2272 return BFD_RELOC_X86_64_PLTOFF64
;
2274 case BFD_RELOC_X86_64_GOTPC32
:
2275 other
= BFD_RELOC_X86_64_GOTPC64
;
2277 case BFD_RELOC_X86_64_GOTPCREL
:
2278 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2280 case BFD_RELOC_X86_64_TPOFF32
:
2281 other
= BFD_RELOC_X86_64_TPOFF64
;
2283 case BFD_RELOC_X86_64_DTPOFF32
:
2284 other
= BFD_RELOC_X86_64_DTPOFF64
;
2290 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2291 if (size
== 4 && flag_code
!= CODE_64BIT
)
2294 reloc
= bfd_reloc_type_lookup (stdoutput
, other
);
2296 as_bad (_("unknown relocation (%u)"), other
);
2297 else if (size
!= bfd_get_reloc_size (reloc
))
2298 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2299 bfd_get_reloc_size (reloc
),
2301 else if (pcrel
&& !reloc
->pc_relative
)
2302 as_bad (_("non-pc-relative relocation for pc-relative field"));
2303 else if ((reloc
->complain_on_overflow
== complain_overflow_signed
2305 || (reloc
->complain_on_overflow
== complain_overflow_unsigned
2307 as_bad (_("relocated field and relocation type differ in signedness"));
2316 as_bad (_("there are no unsigned pc-relative relocations"));
2319 case 1: return BFD_RELOC_8_PCREL
;
2320 case 2: return BFD_RELOC_16_PCREL
;
2321 case 4: return BFD_RELOC_32_PCREL
;
2322 case 8: return BFD_RELOC_64_PCREL
;
2324 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
2331 case 4: return BFD_RELOC_X86_64_32S
;
2336 case 1: return BFD_RELOC_8
;
2337 case 2: return BFD_RELOC_16
;
2338 case 4: return BFD_RELOC_32
;
2339 case 8: return BFD_RELOC_64
;
2341 as_bad (_("cannot do %s %u byte relocation"),
2342 sign
> 0 ? "signed" : "unsigned", size
);
2346 return BFD_RELOC_NONE
;
2349 /* Here we decide which fixups can be adjusted to make them relative to
2350 the beginning of the section instead of the symbol. Basically we need
2351 to make sure that the dynamic relocations are done correctly, so in
2352 some cases we force the original symbol to be used. */
2355 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
2357 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2361 /* Don't adjust pc-relative references to merge sections in 64-bit
2363 if (use_rela_relocations
2364 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
2368 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2369 and changed later by validate_fix. */
2370 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
2371 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
2374 /* adjust_reloc_syms doesn't know about the GOT. */
2375 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
2376 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
2377 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
2378 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
2379 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
2380 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
2381 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
2382 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
2383 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
2384 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
2385 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
2386 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
2387 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
2388 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
2389 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
2390 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
2391 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
2392 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
2393 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
2394 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
2395 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
2396 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
2397 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
2398 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
2399 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
2400 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
2401 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
2402 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
2409 intel_float_operand (const char *mnemonic
)
2411 /* Note that the value returned is meaningful only for opcodes with (memory)
2412 operands, hence the code here is free to improperly handle opcodes that
2413 have no operands (for better performance and smaller code). */
2415 if (mnemonic
[0] != 'f')
2416 return 0; /* non-math */
2418 switch (mnemonic
[1])
2420 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2421 the fs segment override prefix not currently handled because no
2422 call path can make opcodes without operands get here */
2424 return 2 /* integer op */;
2426 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
2427 return 3; /* fldcw/fldenv */
2430 if (mnemonic
[2] != 'o' /* fnop */)
2431 return 3; /* non-waiting control op */
2434 if (mnemonic
[2] == 's')
2435 return 3; /* frstor/frstpm */
2438 if (mnemonic
[2] == 'a')
2439 return 3; /* fsave */
2440 if (mnemonic
[2] == 't')
2442 switch (mnemonic
[3])
2444 case 'c': /* fstcw */
2445 case 'd': /* fstdw */
2446 case 'e': /* fstenv */
2447 case 's': /* fsts[gw] */
2453 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
2454 return 0; /* fxsave/fxrstor are not really math ops */
2461 /* Build the VEX prefix. */
2464 build_vex_prefix (void)
2466 unsigned int register_specifier
;
2467 unsigned int implied_prefix
;
2468 unsigned int vector_length
;
2470 /* Check register specifier. */
2471 if (i
.vex
.register_specifier
)
2473 register_specifier
= i
.vex
.register_specifier
->reg_num
;
2474 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
2475 register_specifier
+= 8;
2476 register_specifier
= ~register_specifier
& 0xf;
2479 register_specifier
= 0xf;
2481 vector_length
= i
.tm
.opcode_modifier
.vex256
? 1 : 0;
2483 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
2488 case DATA_PREFIX_OPCODE
:
2491 case REPE_PREFIX_OPCODE
:
2494 case REPNE_PREFIX_OPCODE
:
2501 /* Use 2-byte VEX prefix if possible. */
2502 if (i
.tm
.opcode_modifier
.vex0f
2503 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
2505 /* 2-byte VEX prefix. */
2509 i
.vex
.bytes
[0] = 0xc5;
2511 /* Check the REX.R bit. */
2512 r
= (i
.rex
& REX_R
) ? 0 : 1;
2513 i
.vex
.bytes
[1] = (r
<< 7
2514 | register_specifier
<< 3
2515 | vector_length
<< 2
2520 /* 3-byte VEX prefix. */
2523 if (i
.tm
.opcode_modifier
.vex0f
)
2525 else if (i
.tm
.opcode_modifier
.vex0f38
)
2527 else if (i
.tm
.opcode_modifier
.vex0f3a
)
2533 i
.vex
.bytes
[0] = 0xc4;
2535 /* The high 3 bits of the second VEX byte are 1's compliment
2536 of RXB bits from REX. */
2537 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
2539 /* Check the REX.W bit. */
2540 w
= (i
.rex
& REX_W
) ? 1 : 0;
2541 if (i
.tm
.opcode_modifier
.vexw0
|| i
.tm
.opcode_modifier
.vexw1
)
2546 if (i
.tm
.opcode_modifier
.vexw1
)
2550 i
.vex
.bytes
[2] = (w
<< 7
2551 | register_specifier
<< 3
2552 | vector_length
<< 2
2558 process_immext (void)
2562 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
&& i
.operands
> 0)
2564 /* SSE3 Instructions have the fixed operands with an opcode
2565 suffix which is coded in the same place as an 8-bit immediate
2566 field would be. Here we check those operands and remove them
2570 for (x
= 0; x
< i
.operands
; x
++)
2571 if (i
.op
[x
].regs
->reg_num
!= x
)
2572 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
2573 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
2579 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
2580 which is coded in the same place as an 8-bit immediate field
2581 would be. Here we fake an 8-bit immediate operand from the
2582 opcode suffix stored in tm.extension_opcode.
2584 SSE5 and AVX instructions also use this encoding, for some of
2585 3 argument instructions. */
2587 assert (i
.imm_operands
== 0
2589 || (i
.tm
.cpu_flags
.bitfield
.cpusse5
2591 || (i
.tm
.opcode_modifier
.vex
2592 && i
.operands
<= 4)));
2594 exp
= &im_expressions
[i
.imm_operands
++];
2595 i
.op
[i
.operands
].imms
= exp
;
2596 i
.types
[i
.operands
] = imm8
;
2598 exp
->X_op
= O_constant
;
2599 exp
->X_add_number
= i
.tm
.extension_opcode
;
2600 i
.tm
.extension_opcode
= None
;
2603 /* This is the guts of the machine-dependent assembler. LINE points to a
2604 machine dependent instruction. This function is supposed to emit
2605 the frags/bytes it assembles to. */
2608 md_assemble (char *line
)
2611 char mnemonic
[MAX_MNEM_SIZE
];
2613 /* Initialize globals. */
2614 memset (&i
, '\0', sizeof (i
));
2615 for (j
= 0; j
< MAX_OPERANDS
; j
++)
2616 i
.reloc
[j
] = NO_RELOC
;
2617 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
2618 memset (im_expressions
, '\0', sizeof (im_expressions
));
2619 save_stack_p
= save_stack
;
2621 /* First parse an instruction mnemonic & call i386_operand for the operands.
2622 We assume that the scrubber has arranged it so that line[0] is the valid
2623 start of a (possibly prefixed) mnemonic. */
2625 line
= parse_insn (line
, mnemonic
);
2629 line
= parse_operands (line
, mnemonic
);
2633 /* Now we've parsed the mnemonic into a set of templates, and have the
2634 operands at hand. */
2636 /* All intel opcodes have reversed operands except for "bound" and
2637 "enter". We also don't reverse intersegment "jmp" and "call"
2638 instructions with 2 immediate operands so that the immediate segment
2639 precedes the offset, as it does when in AT&T mode. */
2642 && (strcmp (mnemonic
, "bound") != 0)
2643 && (strcmp (mnemonic
, "invlpga") != 0)
2644 && !(operand_type_check (i
.types
[0], imm
)
2645 && operand_type_check (i
.types
[1], imm
)))
2648 /* The order of the immediates should be reversed
2649 for 2 immediates extrq and insertq instructions */
2650 if (i
.imm_operands
== 2
2651 && (strcmp (mnemonic
, "extrq") == 0
2652 || strcmp (mnemonic
, "insertq") == 0))
2653 swap_2_operands (0, 1);
2658 /* Don't optimize displacement for movabs since it only takes 64bit
2661 && (flag_code
!= CODE_64BIT
2662 || strcmp (mnemonic
, "movabs") != 0))
2665 /* Next, we find a template that matches the given insn,
2666 making sure the overlap of the given operands types is consistent
2667 with the template operand types. */
2669 if (!match_template ())
2672 if (sse_check
!= sse_check_none
2673 && (i
.tm
.cpu_flags
.bitfield
.cpusse
2674 || i
.tm
.cpu_flags
.bitfield
.cpusse2
2675 || i
.tm
.cpu_flags
.bitfield
.cpusse3
2676 || i
.tm
.cpu_flags
.bitfield
.cpussse3
2677 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
2678 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
2680 (sse_check
== sse_check_warning
2682 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
2685 /* Zap movzx and movsx suffix. The suffix has been set from
2686 "word ptr" or "byte ptr" on the source operand in Intel syntax
2687 or extracted from mnemonic in AT&T syntax. But we'll use
2688 the destination register to choose the suffix for encoding. */
2689 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
2691 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
2692 there is no suffix, the default will be byte extension. */
2693 if (i
.reg_operands
!= 2
2696 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
2701 if (i
.tm
.opcode_modifier
.fwait
)
2702 if (!add_prefix (FWAIT_OPCODE
))
2705 /* Check string instruction segment overrides. */
2706 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
2708 if (!check_string ())
2712 if (!process_suffix ())
2715 /* Make still unresolved immediate matches conform to size of immediate
2716 given in i.suffix. */
2717 if (!finalize_imm ())
2720 if (i
.types
[0].bitfield
.imm1
)
2721 i
.imm_operands
= 0; /* kludge for shift insns. */
2723 for (j
= 0; j
< 3; j
++)
2724 if (i
.types
[j
].bitfield
.inoutportreg
2725 || i
.types
[j
].bitfield
.shiftcount
2726 || i
.types
[j
].bitfield
.acc
2727 || i
.types
[j
].bitfield
.floatacc
)
2730 /* ImmExt should be processed after SSE2AVX. */
2731 if (!i
.tm
.opcode_modifier
.sse2avx
2732 && i
.tm
.opcode_modifier
.immext
)
2735 /* For insns with operands there are more diddles to do to the opcode. */
2738 if (!process_operands ())
2741 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
2743 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2744 as_warn (_("translating to `%sp'"), i
.tm
.name
);
2747 if (i
.tm
.opcode_modifier
.vex
)
2748 build_vex_prefix ();
2750 /* Handle conversion of 'int $3' --> special int3 insn. */
2751 if (i
.tm
.base_opcode
== INT_OPCODE
&& i
.op
[0].imms
->X_add_number
== 3)
2753 i
.tm
.base_opcode
= INT3_OPCODE
;
2757 if ((i
.tm
.opcode_modifier
.jump
2758 || i
.tm
.opcode_modifier
.jumpbyte
2759 || i
.tm
.opcode_modifier
.jumpdword
)
2760 && i
.op
[0].disps
->X_op
== O_constant
)
2762 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2763 the absolute address given by the constant. Since ix86 jumps and
2764 calls are pc relative, we need to generate a reloc. */
2765 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
2766 i
.op
[0].disps
->X_op
= O_symbol
;
2769 if (i
.tm
.opcode_modifier
.rex64
)
2772 /* For 8 bit registers we need an empty rex prefix. Also if the
2773 instruction already has a prefix, we need to convert old
2774 registers to new ones. */
2776 if ((i
.types
[0].bitfield
.reg8
2777 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
2778 || (i
.types
[1].bitfield
.reg8
2779 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
2780 || ((i
.types
[0].bitfield
.reg8
2781 || i
.types
[1].bitfield
.reg8
)
2786 i
.rex
|= REX_OPCODE
;
2787 for (x
= 0; x
< 2; x
++)
2789 /* Look for 8 bit operand that uses old registers. */
2790 if (i
.types
[x
].bitfield
.reg8
2791 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
2793 /* In case it is "hi" register, give up. */
2794 if (i
.op
[x
].regs
->reg_num
> 3)
2795 as_bad (_("can't encode register '%s%s' in an "
2796 "instruction requiring REX prefix."),
2797 register_prefix
, i
.op
[x
].regs
->reg_name
);
2799 /* Otherwise it is equivalent to the extended register.
2800 Since the encoding doesn't change this is merely
2801 cosmetic cleanup for debug output. */
2803 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
2808 /* If the instruction has the DREX attribute (aka SSE5), don't emit a
2810 if (i
.tm
.opcode_modifier
.drex
|| i
.tm
.opcode_modifier
.drexc
)
2815 else if (i
.rex
!= 0)
2816 add_prefix (REX_OPCODE
| i
.rex
);
2818 /* We are ready to output the insn. */
2823 parse_insn (char *line
, char *mnemonic
)
2826 char *token_start
= l
;
2831 /* Non-zero if we found a prefix only acceptable with string insns. */
2832 const char *expecting_string_instruction
= NULL
;
2837 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
2840 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
2842 as_bad (_("no such instruction: `%s'"), token_start
);
2847 if (!is_space_char (*l
)
2848 && *l
!= END_OF_INSN
2850 || (*l
!= PREFIX_SEPARATOR
2853 as_bad (_("invalid character %s in mnemonic"),
2854 output_invalid (*l
));
2857 if (token_start
== l
)
2859 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
2860 as_bad (_("expecting prefix; got nothing"));
2862 as_bad (_("expecting mnemonic; got nothing"));
2866 /* Look up instruction (or prefix) via hash table. */
2867 current_templates
= hash_find (op_hash
, mnemonic
);
2869 if (*l
!= END_OF_INSN
2870 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
2871 && current_templates
2872 && current_templates
->start
->opcode_modifier
.isprefix
)
2874 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
2876 as_bad ((flag_code
!= CODE_64BIT
2877 ? _("`%s' is only supported in 64-bit mode")
2878 : _("`%s' is not supported in 64-bit mode")),
2879 current_templates
->start
->name
);
2882 /* If we are in 16-bit mode, do not allow addr16 or data16.
2883 Similarly, in 32-bit mode, do not allow addr32 or data32. */
2884 if ((current_templates
->start
->opcode_modifier
.size16
2885 || current_templates
->start
->opcode_modifier
.size32
)
2886 && flag_code
!= CODE_64BIT
2887 && (current_templates
->start
->opcode_modifier
.size32
2888 ^ (flag_code
== CODE_16BIT
)))
2890 as_bad (_("redundant %s prefix"),
2891 current_templates
->start
->name
);
2894 /* Add prefix, checking for repeated prefixes. */
2895 switch (add_prefix (current_templates
->start
->base_opcode
))
2900 expecting_string_instruction
= current_templates
->start
->name
;
2903 /* Skip past PREFIX_SEPARATOR and reset token_start. */
2910 if (!current_templates
)
2912 /* See if we can get a match by trimming off a suffix. */
2915 case WORD_MNEM_SUFFIX
:
2916 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
2917 i
.suffix
= SHORT_MNEM_SUFFIX
;
2919 case BYTE_MNEM_SUFFIX
:
2920 case QWORD_MNEM_SUFFIX
:
2921 i
.suffix
= mnem_p
[-1];
2923 current_templates
= hash_find (op_hash
, mnemonic
);
2925 case SHORT_MNEM_SUFFIX
:
2926 case LONG_MNEM_SUFFIX
:
2929 i
.suffix
= mnem_p
[-1];
2931 current_templates
= hash_find (op_hash
, mnemonic
);
2939 if (intel_float_operand (mnemonic
) == 1)
2940 i
.suffix
= SHORT_MNEM_SUFFIX
;
2942 i
.suffix
= LONG_MNEM_SUFFIX
;
2944 current_templates
= hash_find (op_hash
, mnemonic
);
2948 if (!current_templates
)
2950 as_bad (_("no such instruction: `%s'"), token_start
);
2955 if (current_templates
->start
->opcode_modifier
.jump
2956 || current_templates
->start
->opcode_modifier
.jumpbyte
)
2958 /* Check for a branch hint. We allow ",pt" and ",pn" for
2959 predict taken and predict not taken respectively.
2960 I'm not sure that branch hints actually do anything on loop
2961 and jcxz insns (JumpByte) for current Pentium4 chips. They
2962 may work in the future and it doesn't hurt to accept them
2964 if (l
[0] == ',' && l
[1] == 'p')
2968 if (!add_prefix (DS_PREFIX_OPCODE
))
2972 else if (l
[2] == 'n')
2974 if (!add_prefix (CS_PREFIX_OPCODE
))
2980 /* Any other comma loses. */
2983 as_bad (_("invalid character %s in mnemonic"),
2984 output_invalid (*l
));
2988 /* Check if instruction is supported on specified architecture. */
2990 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
2992 supported
|= cpu_flags_match (t
);
2993 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
2997 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
2999 as_bad (flag_code
== CODE_64BIT
3000 ? _("`%s' is not supported in 64-bit mode")
3001 : _("`%s' is only supported in 64-bit mode"),
3002 current_templates
->start
->name
);
3005 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
3007 as_bad (_("`%s' is not supported on `%s%s'"),
3008 current_templates
->start
->name
, cpu_arch_name
,
3009 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
3014 if (!cpu_arch_flags
.bitfield
.cpui386
3015 && (flag_code
!= CODE_16BIT
))
3017 as_warn (_("use .code16 to ensure correct addressing mode"));
3020 /* Check for rep/repne without a string instruction. */
3021 if (expecting_string_instruction
)
3023 static templates override
;
3025 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3026 if (t
->opcode_modifier
.isstring
)
3028 if (t
>= current_templates
->end
)
3030 as_bad (_("expecting string instruction after `%s'"),
3031 expecting_string_instruction
);
3034 for (override
.start
= t
; t
< current_templates
->end
; ++t
)
3035 if (!t
->opcode_modifier
.isstring
)
3038 current_templates
= &override
;
3045 parse_operands (char *l
, const char *mnemonic
)
3049 /* 1 if operand is pending after ','. */
3050 unsigned int expecting_operand
= 0;
3052 /* Non-zero if operand parens not balanced. */
3053 unsigned int paren_not_balanced
;
3055 while (*l
!= END_OF_INSN
)
3057 /* Skip optional white space before operand. */
3058 if (is_space_char (*l
))
3060 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
3062 as_bad (_("invalid character %s before operand %d"),
3063 output_invalid (*l
),
3067 token_start
= l
; /* after white space */
3068 paren_not_balanced
= 0;
3069 while (paren_not_balanced
|| *l
!= ',')
3071 if (*l
== END_OF_INSN
)
3073 if (paren_not_balanced
)
3076 as_bad (_("unbalanced parenthesis in operand %d."),
3079 as_bad (_("unbalanced brackets in operand %d."),
3084 break; /* we are done */
3086 else if (!is_operand_char (*l
) && !is_space_char (*l
))
3088 as_bad (_("invalid character %s in operand %d"),
3089 output_invalid (*l
),
3096 ++paren_not_balanced
;
3098 --paren_not_balanced
;
3103 ++paren_not_balanced
;
3105 --paren_not_balanced
;
3109 if (l
!= token_start
)
3110 { /* Yes, we've read in another operand. */
3111 unsigned int operand_ok
;
3112 this_operand
= i
.operands
++;
3113 i
.types
[this_operand
].bitfield
.unspecified
= 1;
3114 if (i
.operands
> MAX_OPERANDS
)
3116 as_bad (_("spurious operands; (%d operands/instruction max)"),
3120 /* Now parse operand adding info to 'i' as we go along. */
3121 END_STRING_AND_SAVE (l
);
3125 i386_intel_operand (token_start
,
3126 intel_float_operand (mnemonic
));
3128 operand_ok
= i386_att_operand (token_start
);
3130 RESTORE_END_STRING (l
);
3136 if (expecting_operand
)
3138 expecting_operand_after_comma
:
3139 as_bad (_("expecting operand after ','; got nothing"));
3144 as_bad (_("expecting operand before ','; got nothing"));
3149 /* Now *l must be either ',' or END_OF_INSN. */
3152 if (*++l
== END_OF_INSN
)
3154 /* Just skip it, if it's \n complain. */
3155 goto expecting_operand_after_comma
;
3157 expecting_operand
= 1;
3164 swap_2_operands (int xchg1
, int xchg2
)
3166 union i386_op temp_op
;
3167 i386_operand_type temp_type
;
3168 enum bfd_reloc_code_real temp_reloc
;
3170 temp_type
= i
.types
[xchg2
];
3171 i
.types
[xchg2
] = i
.types
[xchg1
];
3172 i
.types
[xchg1
] = temp_type
;
3173 temp_op
= i
.op
[xchg2
];
3174 i
.op
[xchg2
] = i
.op
[xchg1
];
3175 i
.op
[xchg1
] = temp_op
;
3176 temp_reloc
= i
.reloc
[xchg2
];
3177 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
3178 i
.reloc
[xchg1
] = temp_reloc
;
3182 swap_operands (void)
3188 swap_2_operands (1, i
.operands
- 2);
3191 swap_2_operands (0, i
.operands
- 1);
3197 if (i
.mem_operands
== 2)
3199 const seg_entry
*temp_seg
;
3200 temp_seg
= i
.seg
[0];
3201 i
.seg
[0] = i
.seg
[1];
3202 i
.seg
[1] = temp_seg
;
3206 /* Try to ensure constant immediates are represented in the smallest
3211 char guess_suffix
= 0;
3215 guess_suffix
= i
.suffix
;
3216 else if (i
.reg_operands
)
3218 /* Figure out a suffix from the last register operand specified.
3219 We can't do this properly yet, ie. excluding InOutPortReg,
3220 but the following works for instructions with immediates.
3221 In any case, we can't set i.suffix yet. */
3222 for (op
= i
.operands
; --op
>= 0;)
3223 if (i
.types
[op
].bitfield
.reg8
)
3225 guess_suffix
= BYTE_MNEM_SUFFIX
;
3228 else if (i
.types
[op
].bitfield
.reg16
)
3230 guess_suffix
= WORD_MNEM_SUFFIX
;
3233 else if (i
.types
[op
].bitfield
.reg32
)
3235 guess_suffix
= LONG_MNEM_SUFFIX
;
3238 else if (i
.types
[op
].bitfield
.reg64
)
3240 guess_suffix
= QWORD_MNEM_SUFFIX
;
3244 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
3245 guess_suffix
= WORD_MNEM_SUFFIX
;
3247 for (op
= i
.operands
; --op
>= 0;)
3248 if (operand_type_check (i
.types
[op
], imm
))
3250 switch (i
.op
[op
].imms
->X_op
)
3253 /* If a suffix is given, this operand may be shortened. */
3254 switch (guess_suffix
)
3256 case LONG_MNEM_SUFFIX
:
3257 i
.types
[op
].bitfield
.imm32
= 1;
3258 i
.types
[op
].bitfield
.imm64
= 1;
3260 case WORD_MNEM_SUFFIX
:
3261 i
.types
[op
].bitfield
.imm16
= 1;
3262 i
.types
[op
].bitfield
.imm32
= 1;
3263 i
.types
[op
].bitfield
.imm32s
= 1;
3264 i
.types
[op
].bitfield
.imm64
= 1;
3266 case BYTE_MNEM_SUFFIX
:
3267 i
.types
[op
].bitfield
.imm8
= 1;
3268 i
.types
[op
].bitfield
.imm8s
= 1;
3269 i
.types
[op
].bitfield
.imm16
= 1;
3270 i
.types
[op
].bitfield
.imm32
= 1;
3271 i
.types
[op
].bitfield
.imm32s
= 1;
3272 i
.types
[op
].bitfield
.imm64
= 1;
3276 /* If this operand is at most 16 bits, convert it
3277 to a signed 16 bit number before trying to see
3278 whether it will fit in an even smaller size.
3279 This allows a 16-bit operand such as $0xffe0 to
3280 be recognised as within Imm8S range. */
3281 if ((i
.types
[op
].bitfield
.imm16
)
3282 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
3284 i
.op
[op
].imms
->X_add_number
=
3285 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
3287 if ((i
.types
[op
].bitfield
.imm32
)
3288 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
3291 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
3292 ^ ((offsetT
) 1 << 31))
3293 - ((offsetT
) 1 << 31));
3296 = operand_type_or (i
.types
[op
],
3297 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
3299 /* We must avoid matching of Imm32 templates when 64bit
3300 only immediate is available. */
3301 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
3302 i
.types
[op
].bitfield
.imm32
= 0;
3309 /* Symbols and expressions. */
3311 /* Convert symbolic operand to proper sizes for matching, but don't
3312 prevent matching a set of insns that only supports sizes other
3313 than those matching the insn suffix. */
3315 i386_operand_type mask
, allowed
;
3318 operand_type_set (&mask
, 0);
3319 operand_type_set (&allowed
, 0);
3321 for (t
= current_templates
->start
;
3322 t
< current_templates
->end
;
3324 allowed
= operand_type_or (allowed
,
3325 t
->operand_types
[op
]);
3326 switch (guess_suffix
)
3328 case QWORD_MNEM_SUFFIX
:
3329 mask
.bitfield
.imm64
= 1;
3330 mask
.bitfield
.imm32s
= 1;
3332 case LONG_MNEM_SUFFIX
:
3333 mask
.bitfield
.imm32
= 1;
3335 case WORD_MNEM_SUFFIX
:
3336 mask
.bitfield
.imm16
= 1;
3338 case BYTE_MNEM_SUFFIX
:
3339 mask
.bitfield
.imm8
= 1;
3344 allowed
= operand_type_and (mask
, allowed
);
3345 if (!operand_type_all_zero (&allowed
))
3346 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
3353 /* Try to use the smallest displacement type too. */
3355 optimize_disp (void)
3359 for (op
= i
.operands
; --op
>= 0;)
3360 if (operand_type_check (i
.types
[op
], disp
))
3362 if (i
.op
[op
].disps
->X_op
== O_constant
)
3364 offsetT disp
= i
.op
[op
].disps
->X_add_number
;
3366 if (i
.types
[op
].bitfield
.disp16
3367 && (disp
& ~(offsetT
) 0xffff) == 0)
3369 /* If this operand is at most 16 bits, convert
3370 to a signed 16 bit number and don't use 64bit
3372 disp
= (((disp
& 0xffff) ^ 0x8000) - 0x8000);
3373 i
.types
[op
].bitfield
.disp64
= 0;
3375 if (i
.types
[op
].bitfield
.disp32
3376 && (disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
3378 /* If this operand is at most 32 bits, convert
3379 to a signed 32 bit number and don't use 64bit
3381 disp
&= (((offsetT
) 2 << 31) - 1);
3382 disp
= (disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
3383 i
.types
[op
].bitfield
.disp64
= 0;
3385 if (!disp
&& i
.types
[op
].bitfield
.baseindex
)
3387 i
.types
[op
].bitfield
.disp8
= 0;
3388 i
.types
[op
].bitfield
.disp16
= 0;
3389 i
.types
[op
].bitfield
.disp32
= 0;
3390 i
.types
[op
].bitfield
.disp32s
= 0;
3391 i
.types
[op
].bitfield
.disp64
= 0;
3395 else if (flag_code
== CODE_64BIT
)
3397 if (fits_in_signed_long (disp
))
3399 i
.types
[op
].bitfield
.disp64
= 0;
3400 i
.types
[op
].bitfield
.disp32s
= 1;
3402 if (fits_in_unsigned_long (disp
))
3403 i
.types
[op
].bitfield
.disp32
= 1;
3405 if ((i
.types
[op
].bitfield
.disp32
3406 || i
.types
[op
].bitfield
.disp32s
3407 || i
.types
[op
].bitfield
.disp16
)
3408 && fits_in_signed_byte (disp
))
3409 i
.types
[op
].bitfield
.disp8
= 1;
3411 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
3412 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
3414 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
3415 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
3416 i
.types
[op
].bitfield
.disp8
= 0;
3417 i
.types
[op
].bitfield
.disp16
= 0;
3418 i
.types
[op
].bitfield
.disp32
= 0;
3419 i
.types
[op
].bitfield
.disp32s
= 0;
3420 i
.types
[op
].bitfield
.disp64
= 0;
3423 /* We only support 64bit displacement on constants. */
3424 i
.types
[op
].bitfield
.disp64
= 0;
3428 /* Check if operands are valid for the instrucrtion. Update VEX
3432 VEX_check_operands (const template *t
)
3434 if (!t
->opcode_modifier
.vex
)
3437 /* Only check VEX_Imm4, which must be the first operand. */
3438 if (t
->operand_types
[0].bitfield
.vex_imm4
)
3440 if (i
.op
[0].imms
->X_op
!= O_constant
3441 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
3444 /* Turn off Imm8 so that update_imm won't complain. */
3445 i
.types
[0] = vex_imm4
;
3452 match_template (void)
3454 /* Points to template once we've found it. */
3456 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
3457 i386_operand_type overlap4
;
3458 unsigned int found_reverse_match
;
3459 i386_opcode_modifier suffix_check
;
3460 i386_operand_type operand_types
[MAX_OPERANDS
];
3461 int addr_prefix_disp
;
3463 unsigned int found_cpu_match
;
3464 unsigned int check_register
;
3466 #if MAX_OPERANDS != 5
3467 # error "MAX_OPERANDS must be 5."
3470 found_reverse_match
= 0;
3471 addr_prefix_disp
= -1;
3473 memset (&suffix_check
, 0, sizeof (suffix_check
));
3474 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
3475 suffix_check
.no_bsuf
= 1;
3476 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
3477 suffix_check
.no_wsuf
= 1;
3478 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
3479 suffix_check
.no_ssuf
= 1;
3480 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
3481 suffix_check
.no_lsuf
= 1;
3482 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
3483 suffix_check
.no_qsuf
= 1;
3484 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
3485 suffix_check
.no_ldsuf
= 1;
3487 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
3489 addr_prefix_disp
= -1;
3491 /* Must have right number of operands. */
3492 if (i
.operands
!= t
->operands
)
3495 /* Check processor support. */
3496 found_cpu_match
= (cpu_flags_match (t
)
3497 == CPU_FLAGS_PERFECT_MATCH
);
3498 if (!found_cpu_match
)
3501 /* Check old gcc support. */
3502 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
3505 /* Check AT&T mnemonic. */
3506 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
3509 /* Check AT&T syntax Intel syntax. */
3510 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
3511 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
3514 /* Check the suffix, except for some instructions in intel mode. */
3515 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
3516 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
3517 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
3518 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
3519 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
3520 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
3521 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
3524 if (!operand_size_match (t
))
3527 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3528 operand_types
[j
] = t
->operand_types
[j
];
3530 /* In general, don't allow 64-bit operands in 32-bit mode. */
3531 if (i
.suffix
== QWORD_MNEM_SUFFIX
3532 && flag_code
!= CODE_64BIT
3534 ? (!t
->opcode_modifier
.ignoresize
3535 && !intel_float_operand (t
->name
))
3536 : intel_float_operand (t
->name
) != 2)
3537 && ((!operand_types
[0].bitfield
.regmmx
3538 && !operand_types
[0].bitfield
.regxmm
3539 && !operand_types
[0].bitfield
.regymm
)
3540 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
3541 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
3542 && !!operand_types
[t
->operands
> 1].bitfield
.regymm
))
3543 && (t
->base_opcode
!= 0x0fc7
3544 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
3547 /* In general, don't allow 32-bit operands on pre-386. */
3548 else if (i
.suffix
== LONG_MNEM_SUFFIX
3549 && !cpu_arch_flags
.bitfield
.cpui386
3551 ? (!t
->opcode_modifier
.ignoresize
3552 && !intel_float_operand (t
->name
))
3553 : intel_float_operand (t
->name
) != 2)
3554 && ((!operand_types
[0].bitfield
.regmmx
3555 && !operand_types
[0].bitfield
.regxmm
)
3556 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
3557 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
3560 /* Do not verify operands when there are none. */
3564 /* We've found a match; break out of loop. */
3568 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3569 into Disp32/Disp16/Disp32 operand. */
3570 if (i
.prefix
[ADDR_PREFIX
] != 0)
3572 /* There should be only one Disp operand. */
3576 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3578 if (operand_types
[j
].bitfield
.disp16
)
3580 addr_prefix_disp
= j
;
3581 operand_types
[j
].bitfield
.disp32
= 1;
3582 operand_types
[j
].bitfield
.disp16
= 0;
3588 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3590 if (operand_types
[j
].bitfield
.disp32
)
3592 addr_prefix_disp
= j
;
3593 operand_types
[j
].bitfield
.disp32
= 0;
3594 operand_types
[j
].bitfield
.disp16
= 1;
3600 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3602 if (operand_types
[j
].bitfield
.disp64
)
3604 addr_prefix_disp
= j
;
3605 operand_types
[j
].bitfield
.disp64
= 0;
3606 operand_types
[j
].bitfield
.disp32
= 1;
3614 /* We check register size only if size of operands can be
3615 encoded the canonical way. */
3616 check_register
= t
->opcode_modifier
.w
;
3617 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
3618 switch (t
->operands
)
3621 if (!operand_type_match (overlap0
, i
.types
[0]))
3625 /* xchg %eax, %eax is a special case. It is an aliase for nop
3626 only in 32bit mode and we can use opcode 0x90. In 64bit
3627 mode, we can't use 0x90 for xchg %eax, %eax since it should
3628 zero-extend %eax to %rax. */
3629 if (flag_code
== CODE_64BIT
3630 && t
->base_opcode
== 0x90
3631 && operand_type_equal (&i
.types
[0], &acc32
)
3632 && operand_type_equal (&i
.types
[1], &acc32
))
3637 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
3638 if (!operand_type_match (overlap0
, i
.types
[0])
3639 || !operand_type_match (overlap1
, i
.types
[1])
3641 && !operand_type_register_match (overlap0
, i
.types
[0],
3643 overlap1
, i
.types
[1],
3646 /* Check if other direction is valid ... */
3647 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
3650 /* Try reversing direction of operands. */
3651 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
3652 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
3653 if (!operand_type_match (overlap0
, i
.types
[0])
3654 || !operand_type_match (overlap1
, i
.types
[1])
3656 && !operand_type_register_match (overlap0
,
3663 /* Does not match either direction. */
3666 /* found_reverse_match holds which of D or FloatDR
3668 if (t
->opcode_modifier
.d
)
3669 found_reverse_match
= Opcode_D
;
3670 else if (t
->opcode_modifier
.floatd
)
3671 found_reverse_match
= Opcode_FloatD
;
3673 found_reverse_match
= 0;
3674 if (t
->opcode_modifier
.floatr
)
3675 found_reverse_match
|= Opcode_FloatR
;
3679 /* Found a forward 2 operand match here. */
3680 switch (t
->operands
)
3683 overlap4
= operand_type_and (i
.types
[4],
3686 overlap3
= operand_type_and (i
.types
[3],
3689 overlap2
= operand_type_and (i
.types
[2],
3694 switch (t
->operands
)
3697 if (!operand_type_match (overlap4
, i
.types
[4])
3698 || !operand_type_register_match (overlap3
,
3706 if (!operand_type_match (overlap3
, i
.types
[3])
3708 && !operand_type_register_match (overlap2
,
3716 /* Here we make use of the fact that there are no
3717 reverse match 3 operand instructions, and all 3
3718 operand instructions only need to be checked for
3719 register consistency between operands 2 and 3. */
3720 if (!operand_type_match (overlap2
, i
.types
[2])
3722 && !operand_type_register_match (overlap1
,
3732 /* Found either forward/reverse 2, 3 or 4 operand match here:
3733 slip through to break. */
3735 if (!found_cpu_match
)
3737 found_reverse_match
= 0;
3741 /* Check if VEX operands are valid. */
3742 if (VEX_check_operands (t
))
3745 /* We've found a match; break out of loop. */
3749 if (t
== current_templates
->end
)
3751 /* We found no match. */
3752 as_bad (_("suffix or operands invalid for `%s'"),
3753 current_templates
->start
->name
);
3757 if (!quiet_warnings
)
3760 && (i
.types
[0].bitfield
.jumpabsolute
3761 != operand_types
[0].bitfield
.jumpabsolute
))
3763 as_warn (_("indirect %s without `*'"), t
->name
);
3766 if (t
->opcode_modifier
.isprefix
3767 && t
->opcode_modifier
.ignoresize
)
3769 /* Warn them that a data or address size prefix doesn't
3770 affect assembly of the next line of code. */
3771 as_warn (_("stand-alone `%s' prefix"), t
->name
);
3775 /* Copy the template we found. */
3778 if (addr_prefix_disp
!= -1)
3779 i
.tm
.operand_types
[addr_prefix_disp
]
3780 = operand_types
[addr_prefix_disp
];
3782 if (found_reverse_match
)
3784 /* If we found a reverse match we must alter the opcode
3785 direction bit. found_reverse_match holds bits to change
3786 (different for int & float insns). */
3788 i
.tm
.base_opcode
^= found_reverse_match
;
3790 i
.tm
.operand_types
[0] = operand_types
[1];
3791 i
.tm
.operand_types
[1] = operand_types
[0];
3800 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
3801 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
3803 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
3805 as_bad (_("`%s' operand %d must use `%%es' segment"),
3810 /* There's only ever one segment override allowed per instruction.
3811 This instruction possibly has a legal segment override on the
3812 second operand, so copy the segment to where non-string
3813 instructions store it, allowing common code. */
3814 i
.seg
[0] = i
.seg
[1];
3816 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
3818 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
3820 as_bad (_("`%s' operand %d must use `%%es' segment"),
3830 process_suffix (void)
3832 /* If matched instruction specifies an explicit instruction mnemonic
3834 if (i
.tm
.opcode_modifier
.size16
)
3835 i
.suffix
= WORD_MNEM_SUFFIX
;
3836 else if (i
.tm
.opcode_modifier
.size32
)
3837 i
.suffix
= LONG_MNEM_SUFFIX
;
3838 else if (i
.tm
.opcode_modifier
.size64
)
3839 i
.suffix
= QWORD_MNEM_SUFFIX
;
3840 else if (i
.reg_operands
)
3842 /* If there's no instruction mnemonic suffix we try to invent one
3843 based on register operands. */
3846 /* We take i.suffix from the last register operand specified,
3847 Destination register type is more significant than source
3848 register type. crc32 in SSE4.2 prefers source register
3850 if (i
.tm
.base_opcode
== 0xf20f38f1)
3852 if (i
.types
[0].bitfield
.reg16
)
3853 i
.suffix
= WORD_MNEM_SUFFIX
;
3854 else if (i
.types
[0].bitfield
.reg32
)
3855 i
.suffix
= LONG_MNEM_SUFFIX
;
3856 else if (i
.types
[0].bitfield
.reg64
)
3857 i
.suffix
= QWORD_MNEM_SUFFIX
;
3859 else if (i
.tm
.base_opcode
== 0xf20f38f0)
3861 if (i
.types
[0].bitfield
.reg8
)
3862 i
.suffix
= BYTE_MNEM_SUFFIX
;
3869 if (i
.tm
.base_opcode
== 0xf20f38f1
3870 || i
.tm
.base_opcode
== 0xf20f38f0)
3872 /* We have to know the operand size for crc32. */
3873 as_bad (_("ambiguous memory operand size for `%s`"),
3878 for (op
= i
.operands
; --op
>= 0;)
3879 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
3881 if (i
.types
[op
].bitfield
.reg8
)
3883 i
.suffix
= BYTE_MNEM_SUFFIX
;
3886 else if (i
.types
[op
].bitfield
.reg16
)
3888 i
.suffix
= WORD_MNEM_SUFFIX
;
3891 else if (i
.types
[op
].bitfield
.reg32
)
3893 i
.suffix
= LONG_MNEM_SUFFIX
;
3896 else if (i
.types
[op
].bitfield
.reg64
)
3898 i
.suffix
= QWORD_MNEM_SUFFIX
;
3904 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
3906 if (!check_byte_reg ())
3909 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
3911 if (!check_long_reg ())
3914 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
3917 && i
.tm
.opcode_modifier
.ignoresize
3918 && i
.tm
.opcode_modifier
.no_qsuf
)
3920 else if (!check_qword_reg ())
3923 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
3925 if (!check_word_reg ())
3928 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
3929 || i
.suffix
== YMMWORD_MNEM_SUFFIX
)
3931 /* Skip if the instruction has x/y suffix. match_template
3932 should check if it is a valid suffix. */
3934 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
3935 /* Do nothing if the instruction is going to ignore the prefix. */
3940 else if (i
.tm
.opcode_modifier
.defaultsize
3942 /* exclude fldenv/frstor/fsave/fstenv */
3943 && i
.tm
.opcode_modifier
.no_ssuf
)
3945 i
.suffix
= stackop_size
;
3947 else if (intel_syntax
3949 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
3950 || i
.tm
.opcode_modifier
.jumpbyte
3951 || i
.tm
.opcode_modifier
.jumpintersegment
3952 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
3953 && i
.tm
.extension_opcode
<= 3)))
3958 if (!i
.tm
.opcode_modifier
.no_qsuf
)
3960 i
.suffix
= QWORD_MNEM_SUFFIX
;
3964 if (!i
.tm
.opcode_modifier
.no_lsuf
)
3965 i
.suffix
= LONG_MNEM_SUFFIX
;
3968 if (!i
.tm
.opcode_modifier
.no_wsuf
)
3969 i
.suffix
= WORD_MNEM_SUFFIX
;
3978 if (i
.tm
.opcode_modifier
.w
)
3980 as_bad (_("no instruction mnemonic suffix given and "
3981 "no register operands; can't size instruction"));
3987 unsigned int suffixes
;
3989 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
3990 if (!i
.tm
.opcode_modifier
.no_wsuf
)
3992 if (!i
.tm
.opcode_modifier
.no_lsuf
)
3994 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
3996 if (!i
.tm
.opcode_modifier
.no_ssuf
)
3998 if (!i
.tm
.opcode_modifier
.no_qsuf
)
4001 /* There are more than suffix matches. */
4002 if (i
.tm
.opcode_modifier
.w
4003 || ((suffixes
& (suffixes
- 1))
4004 && !i
.tm
.opcode_modifier
.defaultsize
4005 && !i
.tm
.opcode_modifier
.ignoresize
))
4007 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
4013 /* Change the opcode based on the operand size given by i.suffix;
4014 We don't need to change things for byte insns. */
4017 && i
.suffix
!= BYTE_MNEM_SUFFIX
4018 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
4019 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
)
4021 /* It's not a byte, select word/dword operation. */
4022 if (i
.tm
.opcode_modifier
.w
)
4024 if (i
.tm
.opcode_modifier
.shortform
)
4025 i
.tm
.base_opcode
|= 8;
4027 i
.tm
.base_opcode
|= 1;
4030 /* Now select between word & dword operations via the operand
4031 size prefix, except for instructions that will ignore this
4033 if (i
.tm
.opcode_modifier
.addrprefixop0
)
4035 /* The address size override prefix changes the size of the
4037 if ((flag_code
== CODE_32BIT
4038 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
4039 || (flag_code
!= CODE_32BIT
4040 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
4041 if (!add_prefix (ADDR_PREFIX_OPCODE
))
4044 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
4045 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
4046 && !i
.tm
.opcode_modifier
.ignoresize
4047 && !i
.tm
.opcode_modifier
.floatmf
4048 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
4049 || (flag_code
== CODE_64BIT
4050 && i
.tm
.opcode_modifier
.jumpbyte
)))
4052 unsigned int prefix
= DATA_PREFIX_OPCODE
;
4054 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
4055 prefix
= ADDR_PREFIX_OPCODE
;
4057 if (!add_prefix (prefix
))
4061 /* Set mode64 for an operand. */
4062 if (i
.suffix
== QWORD_MNEM_SUFFIX
4063 && flag_code
== CODE_64BIT
4064 && !i
.tm
.opcode_modifier
.norex64
)
4066 /* Special case for xchg %rax,%rax. It is NOP and doesn't
4067 need rex64. cmpxchg8b is also a special case. */
4068 if (! (i
.operands
== 2
4069 && i
.tm
.base_opcode
== 0x90
4070 && i
.tm
.extension_opcode
== None
4071 && operand_type_equal (&i
.types
[0], &acc64
)
4072 && operand_type_equal (&i
.types
[1], &acc64
))
4073 && ! (i
.operands
== 1
4074 && i
.tm
.base_opcode
== 0xfc7
4075 && i
.tm
.extension_opcode
== 1
4076 && !operand_type_check (i
.types
[0], reg
)
4077 && operand_type_check (i
.types
[0], anymem
)))
4081 /* Size floating point instruction. */
4082 if (i
.suffix
== LONG_MNEM_SUFFIX
)
4083 if (i
.tm
.opcode_modifier
.floatmf
)
4084 i
.tm
.base_opcode
^= 4;
4091 check_byte_reg (void)
4095 for (op
= i
.operands
; --op
>= 0;)
4097 /* If this is an eight bit register, it's OK. If it's the 16 or
4098 32 bit version of an eight bit register, we will just use the
4099 low portion, and that's OK too. */
4100 if (i
.types
[op
].bitfield
.reg8
)
4103 /* Don't generate this warning if not needed. */
4104 if (intel_syntax
&& i
.tm
.opcode_modifier
.byteokintel
)
4107 /* crc32 doesn't generate this warning. */
4108 if (i
.tm
.base_opcode
== 0xf20f38f0)
4111 if ((i
.types
[op
].bitfield
.reg16
4112 || i
.types
[op
].bitfield
.reg32
4113 || i
.types
[op
].bitfield
.reg64
)
4114 && i
.op
[op
].regs
->reg_num
< 4)
4116 /* Prohibit these changes in the 64bit mode, since the
4117 lowering is more complicated. */
4118 if (flag_code
== CODE_64BIT
4119 && !i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4121 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4122 register_prefix
, i
.op
[op
].regs
->reg_name
,
4126 #if REGISTER_WARNINGS
4128 && !i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4129 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4131 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
4132 ? REGNAM_AL
- REGNAM_AX
4133 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
4135 i
.op
[op
].regs
->reg_name
,
4140 /* Any other register is bad. */
4141 if (i
.types
[op
].bitfield
.reg16
4142 || i
.types
[op
].bitfield
.reg32
4143 || i
.types
[op
].bitfield
.reg64
4144 || i
.types
[op
].bitfield
.regmmx
4145 || i
.types
[op
].bitfield
.regxmm
4146 || i
.types
[op
].bitfield
.regymm
4147 || i
.types
[op
].bitfield
.sreg2
4148 || i
.types
[op
].bitfield
.sreg3
4149 || i
.types
[op
].bitfield
.control
4150 || i
.types
[op
].bitfield
.debug
4151 || i
.types
[op
].bitfield
.test
4152 || i
.types
[op
].bitfield
.floatreg
4153 || i
.types
[op
].bitfield
.floatacc
)
4155 as_bad (_("`%s%s' not allowed with `%s%c'"),
4157 i
.op
[op
].regs
->reg_name
,
4167 check_long_reg (void)
4171 for (op
= i
.operands
; --op
>= 0;)
4172 /* Reject eight bit registers, except where the template requires
4173 them. (eg. movzb) */
4174 if (i
.types
[op
].bitfield
.reg8
4175 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4176 || i
.tm
.operand_types
[op
].bitfield
.reg32
4177 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4179 as_bad (_("`%s%s' not allowed with `%s%c'"),
4181 i
.op
[op
].regs
->reg_name
,
4186 /* Warn if the e prefix on a general reg is missing. */
4187 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4188 && i
.types
[op
].bitfield
.reg16
4189 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4190 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4192 /* Prohibit these changes in the 64bit mode, since the
4193 lowering is more complicated. */
4194 if (flag_code
== CODE_64BIT
)
4196 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4197 register_prefix
, i
.op
[op
].regs
->reg_name
,
4201 #if REGISTER_WARNINGS
4203 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4205 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
4207 i
.op
[op
].regs
->reg_name
,
4211 /* Warn if the r prefix on a general reg is missing. */
4212 else if (i
.types
[op
].bitfield
.reg64
4213 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4214 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4217 && i
.tm
.opcode_modifier
.toqword
4218 && !i
.types
[0].bitfield
.regxmm
)
4220 /* Convert to QWORD. We want REX byte. */
4221 i
.suffix
= QWORD_MNEM_SUFFIX
;
4225 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4226 register_prefix
, i
.op
[op
].regs
->reg_name
,
4235 check_qword_reg (void)
4239 for (op
= i
.operands
; --op
>= 0; )
4240 /* Reject eight bit registers, except where the template requires
4241 them. (eg. movzb) */
4242 if (i
.types
[op
].bitfield
.reg8
4243 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4244 || i
.tm
.operand_types
[op
].bitfield
.reg32
4245 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4247 as_bad (_("`%s%s' not allowed with `%s%c'"),
4249 i
.op
[op
].regs
->reg_name
,
4254 /* Warn if the e prefix on a general reg is missing. */
4255 else if ((i
.types
[op
].bitfield
.reg16
4256 || i
.types
[op
].bitfield
.reg32
)
4257 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4258 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4260 /* Prohibit these changes in the 64bit mode, since the
4261 lowering is more complicated. */
4263 && i
.tm
.opcode_modifier
.todword
4264 && !i
.types
[0].bitfield
.regxmm
)
4266 /* Convert to DWORD. We don't want REX byte. */
4267 i
.suffix
= LONG_MNEM_SUFFIX
;
4271 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4272 register_prefix
, i
.op
[op
].regs
->reg_name
,
4281 check_word_reg (void)
4284 for (op
= i
.operands
; --op
>= 0;)
4285 /* Reject eight bit registers, except where the template requires
4286 them. (eg. movzb) */
4287 if (i
.types
[op
].bitfield
.reg8
4288 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4289 || i
.tm
.operand_types
[op
].bitfield
.reg32
4290 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4292 as_bad (_("`%s%s' not allowed with `%s%c'"),
4294 i
.op
[op
].regs
->reg_name
,
4299 /* Warn if the e prefix on a general reg is present. */
4300 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4301 && i
.types
[op
].bitfield
.reg32
4302 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4303 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4305 /* Prohibit these changes in the 64bit mode, since the
4306 lowering is more complicated. */
4307 if (flag_code
== CODE_64BIT
)
4309 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4310 register_prefix
, i
.op
[op
].regs
->reg_name
,
4315 #if REGISTER_WARNINGS
4316 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4318 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
4320 i
.op
[op
].regs
->reg_name
,
4328 update_imm (unsigned int j
)
4330 i386_operand_type overlap
;
4332 overlap
= operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
4333 if ((overlap
.bitfield
.imm8
4334 || overlap
.bitfield
.imm8s
4335 || overlap
.bitfield
.imm16
4336 || overlap
.bitfield
.imm32
4337 || overlap
.bitfield
.imm32s
4338 || overlap
.bitfield
.imm64
)
4339 && !operand_type_equal (&overlap
, &imm8
)
4340 && !operand_type_equal (&overlap
, &imm8s
)
4341 && !operand_type_equal (&overlap
, &imm16
)
4342 && !operand_type_equal (&overlap
, &imm32
)
4343 && !operand_type_equal (&overlap
, &imm32s
)
4344 && !operand_type_equal (&overlap
, &imm64
))
4348 i386_operand_type temp
;
4350 operand_type_set (&temp
, 0);
4351 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4353 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
4354 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
4356 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4357 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
4358 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4360 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
4361 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
4364 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
4367 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
4368 || operand_type_equal (&overlap
, &imm16_32
)
4369 || operand_type_equal (&overlap
, &imm16_32s
))
4371 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4376 if (!operand_type_equal (&overlap
, &imm8
)
4377 && !operand_type_equal (&overlap
, &imm8s
)
4378 && !operand_type_equal (&overlap
, &imm16
)
4379 && !operand_type_equal (&overlap
, &imm32
)
4380 && !operand_type_equal (&overlap
, &imm32s
)
4381 && !operand_type_equal (&overlap
, &imm64
))
4383 as_bad (_("no instruction mnemonic suffix given; "
4384 "can't determine immediate size"));
4388 i
.types
[j
] = overlap
;
4398 for (j
= 0; j
< 2; j
++)
4399 if (update_imm (j
) == 0)
4402 i
.types
[2] = operand_type_and (i
.types
[2], i
.tm
.operand_types
[2]);
4403 assert (operand_type_check (i
.types
[2], imm
) == 0);
4411 i
.drex
.modrm_reg
= 0;
4412 i
.drex
.modrm_regmem
= 0;
4414 /* SSE5 4 operand instructions must have the destination the same as
4415 one of the inputs. Figure out the destination register and cache
4416 it away in the drex field, and remember which fields to use for
4418 if (i
.tm
.opcode_modifier
.drex
4419 && i
.tm
.opcode_modifier
.drexv
4422 i
.tm
.extension_opcode
= None
;
4424 /* Case 1: 4 operand insn, dest = src1, src3 = register. */
4425 if (i
.types
[0].bitfield
.regxmm
!= 0
4426 && i
.types
[1].bitfield
.regxmm
!= 0
4427 && i
.types
[2].bitfield
.regxmm
!= 0
4428 && i
.types
[3].bitfield
.regxmm
!= 0
4429 && i
.op
[0].regs
->reg_num
== i
.op
[3].regs
->reg_num
4430 && i
.op
[0].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4432 /* Clear the arguments that are stored in drex. */
4433 operand_type_set (&i
.types
[0], 0);
4434 operand_type_set (&i
.types
[3], 0);
4435 i
.reg_operands
-= 2;
4437 /* There are two different ways to encode a 4 operand
4438 instruction with all registers that uses OC1 set to
4439 0 or 1. Favor setting OC1 to 0 since this mimics the
4440 actions of other SSE5 assemblers. Use modrm encoding 2
4441 for register/register. Include the high order bit that
4442 is normally stored in the REX byte in the register
4444 i
.tm
.extension_opcode
= DREX_X1_XMEM_X2_X1
;
4445 i
.drex
.modrm_reg
= 2;
4446 i
.drex
.modrm_regmem
= 1;
4447 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4448 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4451 /* Case 2: 4 operand insn, dest = src1, src3 = memory. */
4452 else if (i
.types
[0].bitfield
.regxmm
!= 0
4453 && i
.types
[1].bitfield
.regxmm
!= 0
4454 && (i
.types
[2].bitfield
.regxmm
4455 || operand_type_check (i
.types
[2], anymem
))
4456 && i
.types
[3].bitfield
.regxmm
!= 0
4457 && i
.op
[0].regs
->reg_num
== i
.op
[3].regs
->reg_num
4458 && i
.op
[0].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4460 /* clear the arguments that are stored in drex */
4461 operand_type_set (&i
.types
[0], 0);
4462 operand_type_set (&i
.types
[3], 0);
4463 i
.reg_operands
-= 2;
4465 /* Specify the modrm encoding for memory addressing. Include
4466 the high order bit that is normally stored in the REX byte
4467 in the register field. */
4468 i
.tm
.extension_opcode
= DREX_X1_X2_XMEM_X1
;
4469 i
.drex
.modrm_reg
= 1;
4470 i
.drex
.modrm_regmem
= 2;
4471 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4472 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4475 /* Case 3: 4 operand insn, dest = src1, src2 = memory. */
4476 else if (i
.types
[0].bitfield
.regxmm
!= 0
4477 && operand_type_check (i
.types
[1], anymem
) != 0
4478 && i
.types
[2].bitfield
.regxmm
!= 0
4479 && i
.types
[3].bitfield
.regxmm
!= 0
4480 && i
.op
[0].regs
->reg_num
== i
.op
[3].regs
->reg_num
4481 && i
.op
[0].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4483 /* Clear the arguments that are stored in drex. */
4484 operand_type_set (&i
.types
[0], 0);
4485 operand_type_set (&i
.types
[3], 0);
4486 i
.reg_operands
-= 2;
4488 /* Specify the modrm encoding for memory addressing. Include
4489 the high order bit that is normally stored in the REX byte
4490 in the register field. */
4491 i
.tm
.extension_opcode
= DREX_X1_XMEM_X2_X1
;
4492 i
.drex
.modrm_reg
= 2;
4493 i
.drex
.modrm_regmem
= 1;
4494 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4495 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4498 /* Case 4: 4 operand insn, dest = src3, src2 = register. */
4499 else if (i
.types
[0].bitfield
.regxmm
!= 0
4500 && i
.types
[1].bitfield
.regxmm
!= 0
4501 && i
.types
[2].bitfield
.regxmm
!= 0
4502 && i
.types
[3].bitfield
.regxmm
!= 0
4503 && i
.op
[2].regs
->reg_num
== i
.op
[3].regs
->reg_num
4504 && i
.op
[2].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4506 /* clear the arguments that are stored in drex */
4507 operand_type_set (&i
.types
[2], 0);
4508 operand_type_set (&i
.types
[3], 0);
4509 i
.reg_operands
-= 2;
4511 /* There are two different ways to encode a 4 operand
4512 instruction with all registers that uses OC1 set to
4513 0 or 1. Favor setting OC1 to 0 since this mimics the
4514 actions of other SSE5 assemblers. Use modrm encoding
4515 2 for register/register. Include the high order bit that
4516 is normally stored in the REX byte in the register
4518 i
.tm
.extension_opcode
= DREX_XMEM_X1_X2_X2
;
4519 i
.drex
.modrm_reg
= 1;
4520 i
.drex
.modrm_regmem
= 0;
4522 /* Remember the register, including the upper bits */
4523 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4524 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4527 /* Case 5: 4 operand insn, dest = src3, src2 = memory. */
4528 else if (i
.types
[0].bitfield
.regxmm
!= 0
4529 && (i
.types
[1].bitfield
.regxmm
4530 || operand_type_check (i
.types
[1], anymem
))
4531 && i
.types
[2].bitfield
.regxmm
!= 0
4532 && i
.types
[3].bitfield
.regxmm
!= 0
4533 && i
.op
[2].regs
->reg_num
== i
.op
[3].regs
->reg_num
4534 && i
.op
[2].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4536 /* Clear the arguments that are stored in drex. */
4537 operand_type_set (&i
.types
[2], 0);
4538 operand_type_set (&i
.types
[3], 0);
4539 i
.reg_operands
-= 2;
4541 /* Specify the modrm encoding and remember the register
4542 including the bits normally stored in the REX byte. */
4543 i
.tm
.extension_opcode
= DREX_X1_XMEM_X2_X2
;
4544 i
.drex
.modrm_reg
= 0;
4545 i
.drex
.modrm_regmem
= 1;
4546 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4547 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4550 /* Case 6: 4 operand insn, dest = src3, src1 = memory. */
4551 else if (operand_type_check (i
.types
[0], anymem
) != 0
4552 && i
.types
[1].bitfield
.regxmm
!= 0
4553 && i
.types
[2].bitfield
.regxmm
!= 0
4554 && i
.types
[3].bitfield
.regxmm
!= 0
4555 && i
.op
[2].regs
->reg_num
== i
.op
[3].regs
->reg_num
4556 && i
.op
[2].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4558 /* clear the arguments that are stored in drex */
4559 operand_type_set (&i
.types
[2], 0);
4560 operand_type_set (&i
.types
[3], 0);
4561 i
.reg_operands
-= 2;
4563 /* Specify the modrm encoding and remember the register
4564 including the bits normally stored in the REX byte. */
4565 i
.tm
.extension_opcode
= DREX_XMEM_X1_X2_X2
;
4566 i
.drex
.modrm_reg
= 1;
4567 i
.drex
.modrm_regmem
= 0;
4568 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4569 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4573 as_bad (_("Incorrect operands for the '%s' instruction"),
4577 /* SSE5 instructions with the DREX byte where the only memory operand
4578 is in the 2nd argument, and the first and last xmm register must
4579 match, and is encoded in the DREX byte. */
4580 else if (i
.tm
.opcode_modifier
.drex
4581 && !i
.tm
.opcode_modifier
.drexv
4584 /* Case 1: 4 operand insn, dest = src1, src3 = reg/mem. */
4585 if (i
.types
[0].bitfield
.regxmm
!= 0
4586 && (i
.types
[1].bitfield
.regxmm
4587 || operand_type_check(i
.types
[1], anymem
))
4588 && i
.types
[2].bitfield
.regxmm
!= 0
4589 && i
.types
[3].bitfield
.regxmm
!= 0
4590 && i
.op
[0].regs
->reg_num
== i
.op
[3].regs
->reg_num
4591 && i
.op
[0].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4593 /* clear the arguments that are stored in drex */
4594 operand_type_set (&i
.types
[0], 0);
4595 operand_type_set (&i
.types
[3], 0);
4596 i
.reg_operands
-= 2;
4598 /* Specify the modrm encoding and remember the register
4599 including the high bit normally stored in the REX
4601 i
.drex
.modrm_reg
= 2;
4602 i
.drex
.modrm_regmem
= 1;
4603 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4604 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4608 as_bad (_("Incorrect operands for the '%s' instruction"),
4612 /* SSE5 3 operand instructions that the result is a register, being
4613 either operand can be a memory operand, using OC0 to note which
4614 one is the memory. */
4615 else if (i
.tm
.opcode_modifier
.drex
4616 && i
.tm
.opcode_modifier
.drexv
4619 i
.tm
.extension_opcode
= None
;
4621 /* Case 1: 3 operand insn, src1 = register. */
4622 if (i
.types
[0].bitfield
.regxmm
!= 0
4623 && i
.types
[1].bitfield
.regxmm
!= 0
4624 && i
.types
[2].bitfield
.regxmm
!= 0)
4626 /* Clear the arguments that are stored in drex. */
4627 operand_type_set (&i
.types
[2], 0);
4630 /* Specify the modrm encoding and remember the register
4631 including the high bit normally stored in the REX byte. */
4632 i
.tm
.extension_opcode
= DREX_XMEM_X1_X2
;
4633 i
.drex
.modrm_reg
= 1;
4634 i
.drex
.modrm_regmem
= 0;
4635 i
.drex
.reg
= (i
.op
[2].regs
->reg_num
4636 + ((i
.op
[2].regs
->reg_flags
& RegRex
) ? 8 : 0));
4639 /* Case 2: 3 operand insn, src1 = memory. */
4640 else if (operand_type_check (i
.types
[0], anymem
) != 0
4641 && i
.types
[1].bitfield
.regxmm
!= 0
4642 && i
.types
[2].bitfield
.regxmm
!= 0)
4644 /* Clear the arguments that are stored in drex. */
4645 operand_type_set (&i
.types
[2], 0);
4648 /* Specify the modrm encoding and remember the register
4649 including the high bit normally stored in the REX
4651 i
.tm
.extension_opcode
= DREX_XMEM_X1_X2
;
4652 i
.drex
.modrm_reg
= 1;
4653 i
.drex
.modrm_regmem
= 0;
4654 i
.drex
.reg
= (i
.op
[2].regs
->reg_num
4655 + ((i
.op
[2].regs
->reg_flags
& RegRex
) ? 8 : 0));
4658 /* Case 3: 3 operand insn, src2 = memory. */
4659 else if (i
.types
[0].bitfield
.regxmm
!= 0
4660 && operand_type_check (i
.types
[1], anymem
) != 0
4661 && i
.types
[2].bitfield
.regxmm
!= 0)
4663 /* Clear the arguments that are stored in drex. */
4664 operand_type_set (&i
.types
[2], 0);
4667 /* Specify the modrm encoding and remember the register
4668 including the high bit normally stored in the REX byte. */
4669 i
.tm
.extension_opcode
= DREX_X1_XMEM_X2
;
4670 i
.drex
.modrm_reg
= 0;
4671 i
.drex
.modrm_regmem
= 1;
4672 i
.drex
.reg
= (i
.op
[2].regs
->reg_num
4673 + ((i
.op
[2].regs
->reg_flags
& RegRex
) ? 8 : 0));
4677 as_bad (_("Incorrect operands for the '%s' instruction"),
4681 /* SSE5 4 operand instructions that are the comparison instructions
4682 where the first operand is the immediate value of the comparison
4684 else if (i
.tm
.opcode_modifier
.drexc
!= 0 && i
.operands
== 4)
4686 /* Case 1: 4 operand insn, src1 = reg/memory. */
4687 if (operand_type_check (i
.types
[0], imm
) != 0
4688 && (i
.types
[1].bitfield
.regxmm
4689 || operand_type_check (i
.types
[1], anymem
))
4690 && i
.types
[2].bitfield
.regxmm
!= 0
4691 && i
.types
[3].bitfield
.regxmm
!= 0)
4693 /* clear the arguments that are stored in drex */
4694 operand_type_set (&i
.types
[3], 0);
4697 /* Specify the modrm encoding and remember the register
4698 including the high bit normally stored in the REX byte. */
4699 i
.drex
.modrm_reg
= 2;
4700 i
.drex
.modrm_regmem
= 1;
4701 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4702 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4705 /* Case 2: 3 operand insn with ImmExt that places the
4706 opcode_extension as an immediate argument. This is used for
4707 all of the varients of comparison that supplies the appropriate
4708 value as part of the instruction. */
4709 else if ((i
.types
[0].bitfield
.regxmm
4710 || operand_type_check (i
.types
[0], anymem
))
4711 && i
.types
[1].bitfield
.regxmm
!= 0
4712 && i
.types
[2].bitfield
.regxmm
!= 0
4713 && operand_type_check (i
.types
[3], imm
) != 0)
4715 /* clear the arguments that are stored in drex */
4716 operand_type_set (&i
.types
[2], 0);
4719 /* Specify the modrm encoding and remember the register
4720 including the high bit normally stored in the REX byte. */
4721 i
.drex
.modrm_reg
= 1;
4722 i
.drex
.modrm_regmem
= 0;
4723 i
.drex
.reg
= (i
.op
[2].regs
->reg_num
4724 + ((i
.op
[2].regs
->reg_flags
& RegRex
) ? 8 : 0));
4728 as_bad (_("Incorrect operands for the '%s' instruction"),
4732 else if (i
.tm
.opcode_modifier
.drex
4733 || i
.tm
.opcode_modifier
.drexv
4734 || i
.tm
.opcode_modifier
.drexc
)
4735 as_bad (_("Internal error for the '%s' instruction"), i
.tm
.name
);
4739 bad_implicit_operand (int xmm
)
4741 const char *reg
= xmm
? "xmm0" : "ymm0";
4743 as_bad (_("the last operand of `%s' must be `%s%s'"),
4744 i
.tm
.name
, register_prefix
, reg
);
4746 as_bad (_("the first operand of `%s' must be `%s%s'"),
4747 i
.tm
.name
, register_prefix
, reg
);
4752 process_operands (void)
4754 /* Default segment register this instruction will use for memory
4755 accesses. 0 means unknown. This is only for optimizing out
4756 unnecessary segment overrides. */
4757 const seg_entry
*default_seg
= 0;
4759 /* Handle all of the DREX munging that SSE5 needs. */
4760 if (i
.tm
.opcode_modifier
.drex
4761 || i
.tm
.opcode_modifier
.drexv
4762 || i
.tm
.opcode_modifier
.drexc
)
4765 if (i
.tm
.opcode_modifier
.sse2avx
4766 && (i
.tm
.opcode_modifier
.vexnds
4767 || i
.tm
.opcode_modifier
.vexndd
))
4769 unsigned int dup
= i
.operands
;
4770 unsigned int dest
= dup
- 1;
4773 /* The destination must be an xmm register. */
4774 assert (i
.reg_operands
4775 && MAX_OPERANDS
> dup
4776 && operand_type_equal (&i
.types
[dest
], ®xmm
));
4778 if (i
.tm
.opcode_modifier
.firstxmm0
)
4780 /* The first operand is implicit and must be xmm0. */
4781 assert (operand_type_equal (&i
.types
[0], ®xmm
));
4782 if (i
.op
[0].regs
->reg_num
!= 0)
4783 return bad_implicit_operand (1);
4785 if (i
.tm
.opcode_modifier
.vex3sources
)
4787 /* Keep xmm0 for instructions with VEX prefix and 3
4793 /* We remove the first xmm0 and keep the number of
4794 operands unchanged, which in fact duplicates the
4796 for (j
= 1; j
< i
.operands
; j
++)
4798 i
.op
[j
- 1] = i
.op
[j
];
4799 i
.types
[j
- 1] = i
.types
[j
];
4800 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
4804 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
4806 assert ((MAX_OPERANDS
- 1) > dup
4807 && i
.tm
.opcode_modifier
.vex3sources
);
4809 /* Add the implicit xmm0 for instructions with VEX prefix
4811 for (j
= i
.operands
; j
> 0; j
--)
4813 i
.op
[j
] = i
.op
[j
- 1];
4814 i
.types
[j
] = i
.types
[j
- 1];
4815 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
4818 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
4819 i
.types
[0] = regxmm
;
4820 i
.tm
.operand_types
[0] = regxmm
;
4823 i
.reg_operands
+= 2;
4828 i
.op
[dup
] = i
.op
[dest
];
4829 i
.types
[dup
] = i
.types
[dest
];
4830 i
.tm
.operand_types
[dup
] = i
.tm
.operand_types
[dest
];
4839 i
.op
[dup
] = i
.op
[dest
];
4840 i
.types
[dup
] = i
.types
[dest
];
4841 i
.tm
.operand_types
[dup
] = i
.tm
.operand_types
[dest
];
4844 if (i
.tm
.opcode_modifier
.immext
)
4847 else if (i
.tm
.opcode_modifier
.firstxmm0
)
4851 /* The first operand is implicit and must be xmm0/ymm0. */
4852 assert (i
.reg_operands
4853 && (operand_type_equal (&i
.types
[0], ®xmm
)
4854 || operand_type_equal (&i
.types
[0], ®ymm
)));
4855 if (i
.op
[0].regs
->reg_num
!= 0)
4856 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
4858 for (j
= 1; j
< i
.operands
; j
++)
4860 i
.op
[j
- 1] = i
.op
[j
];
4861 i
.types
[j
- 1] = i
.types
[j
];
4863 /* We need to adjust fields in i.tm since they are used by
4864 build_modrm_byte. */
4865 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
4872 else if (i
.tm
.opcode_modifier
.regkludge
)
4874 /* The imul $imm, %reg instruction is converted into
4875 imul $imm, %reg, %reg, and the clr %reg instruction
4876 is converted into xor %reg, %reg. */
4878 unsigned int first_reg_op
;
4880 if (operand_type_check (i
.types
[0], reg
))
4884 /* Pretend we saw the extra register operand. */
4885 assert (i
.reg_operands
== 1
4886 && i
.op
[first_reg_op
+ 1].regs
== 0);
4887 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
4888 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
4893 if (i
.tm
.opcode_modifier
.shortform
)
4895 if (i
.types
[0].bitfield
.sreg2
4896 || i
.types
[0].bitfield
.sreg3
)
4898 if (i
.tm
.base_opcode
== POP_SEG_SHORT
4899 && i
.op
[0].regs
->reg_num
== 1)
4901 as_bad (_("you can't `pop %%cs'"));
4904 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
4905 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
4910 /* The register or float register operand is in operand
4914 if (i
.types
[0].bitfield
.floatreg
4915 || operand_type_check (i
.types
[0], reg
))
4919 /* Register goes in low 3 bits of opcode. */
4920 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
4921 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
4923 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
4925 /* Warn about some common errors, but press on regardless.
4926 The first case can be generated by gcc (<= 2.8.1). */
4927 if (i
.operands
== 2)
4929 /* Reversed arguments on faddp, fsubp, etc. */
4930 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
4931 register_prefix
, i
.op
[1].regs
->reg_name
,
4932 register_prefix
, i
.op
[0].regs
->reg_name
);
4936 /* Extraneous `l' suffix on fp insn. */
4937 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
4938 register_prefix
, i
.op
[0].regs
->reg_name
);
4943 else if (i
.tm
.opcode_modifier
.modrm
)
4945 /* The opcode is completed (modulo i.tm.extension_opcode which
4946 must be put into the modrm byte). Now, we make the modrm and
4947 index base bytes based on all the info we've collected. */
4949 default_seg
= build_modrm_byte ();
4951 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
4955 else if (i
.tm
.opcode_modifier
.isstring
)
4957 /* For the string instructions that allow a segment override
4958 on one of their operands, the default segment is ds. */
4962 if (i
.tm
.base_opcode
== 0x8d /* lea */
4965 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
4967 /* If a segment was explicitly specified, and the specified segment
4968 is not the default, use an opcode prefix to select it. If we
4969 never figured out what the default segment is, then default_seg
4970 will be zero at this point, and the specified segment prefix will
4972 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
4974 if (!add_prefix (i
.seg
[0]->seg_prefix
))
4980 static const seg_entry
*
4981 build_modrm_byte (void)
4983 const seg_entry
*default_seg
= 0;
4984 unsigned int source
, dest
;
4987 /* The first operand of instructions with VEX prefix and 3 sources
4988 must be VEX_Imm4. */
4989 vex_3_sources
= i
.tm
.opcode_modifier
.vex3sources
;
4992 unsigned int nds
, reg
;
4994 if (i
.tm
.opcode_modifier
.veximmext
4995 && i
.tm
.opcode_modifier
.immext
)
4997 dest
= i
.operands
- 2;
5001 dest
= i
.operands
- 1;
5004 /* There are 2 kinds of instructions:
5005 1. 5 operands: one immediate operand and 4 register
5006 operands or 3 register operands plus 1 memory operand.
5007 It must have VexNDS and VexW0 or VexW1. The destination
5008 must be either XMM or YMM register.
5009 2. 4 operands: 4 register operands or 3 register operands
5010 plus 1 memory operand. It must have VexNDS and VexImmExt. */
5011 if (!((i
.reg_operands
== 4
5012 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
5013 && i
.tm
.opcode_modifier
.vexnds
5014 && (operand_type_equal (&i
.tm
.operand_types
[dest
], ®xmm
)
5015 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®ymm
))
5017 && i
.imm_operands
== 1
5018 && i
.types
[0].bitfield
.vex_imm4
5019 && (i
.tm
.opcode_modifier
.vexw0
5020 || i
.tm
.opcode_modifier
.vexw1
))
5022 && (i
.imm_operands
== 0
5023 || (i
.imm_operands
== 1
5024 && i
.tm
.opcode_modifier
.immext
))
5025 && i
.tm
.opcode_modifier
.veximmext
))))
5028 if (i
.imm_operands
== 0)
5030 /* When there is no immediate operand, generate an 8bit
5031 immediate operand to encode the first operand. */
5032 expressionS
*exp
= &im_expressions
[i
.imm_operands
++];
5033 i
.op
[i
.operands
].imms
= exp
;
5034 i
.types
[i
.operands
] = imm8
;
5036 /* If VexW1 is set, the first operand is the source and
5037 the second operand is encoded in the immediate operand. */
5038 if (i
.tm
.opcode_modifier
.vexw1
)
5049 /* FMA swaps REG and NDS. */
5050 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
5058 assert (operand_type_equal (&i
.tm
.operand_types
[reg
], ®xmm
)
5059 || operand_type_equal (&i
.tm
.operand_types
[reg
],
5061 exp
->X_op
= O_constant
;
5063 = ((i
.op
[reg
].regs
->reg_num
5064 + ((i
.op
[reg
].regs
->reg_flags
& RegRex
) ? 8 : 0)) << 4);
5070 if (i
.tm
.opcode_modifier
.vexw0
)
5072 /* If VexW0 is set, the third operand is the source and
5073 the second operand is encoded in the immediate
5080 /* VexW1 is set, the second operand is the source and
5081 the third operand is encoded in the immediate
5087 if (i
.tm
.opcode_modifier
.immext
)
5089 /* When ImmExt is set, the immdiate byte is the last
5091 imm
= i
.operands
- 1;
5099 /* Turn on Imm8 so that output_imm will generate it. */
5100 i
.types
[imm
].bitfield
.imm8
= 1;
5103 assert (operand_type_equal (&i
.tm
.operand_types
[reg
], ®xmm
)
5104 || operand_type_equal (&i
.tm
.operand_types
[reg
],
5106 i
.op
[imm
].imms
->X_add_number
5107 |= ((i
.op
[reg
].regs
->reg_num
5108 + ((i
.op
[reg
].regs
->reg_flags
& RegRex
) ? 8 : 0)) << 4);
5111 assert (operand_type_equal (&i
.tm
.operand_types
[nds
], ®xmm
)
5112 || operand_type_equal (&i
.tm
.operand_types
[nds
], ®ymm
));
5113 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
5119 /* SSE5 4 operand instructions are encoded in such a way that one of
5120 the inputs must match the destination register. Process_drex hides
5121 the 3rd argument in the drex field, so that by the time we get
5122 here, it looks to GAS as if this is a 2 operand instruction. */
5123 if ((i
.tm
.opcode_modifier
.drex
5124 || i
.tm
.opcode_modifier
.drexv
5125 || i
.tm
.opcode_modifier
.drexc
)
5126 && i
.reg_operands
== 2)
5128 const reg_entry
*reg
= i
.op
[i
.drex
.modrm_reg
].regs
;
5129 const reg_entry
*regmem
= i
.op
[i
.drex
.modrm_regmem
].regs
;
5131 i
.rm
.reg
= reg
->reg_num
;
5132 i
.rm
.regmem
= regmem
->reg_num
;
5134 if ((reg
->reg_flags
& RegRex
) != 0)
5136 if ((regmem
->reg_flags
& RegRex
) != 0)
5140 /* i.reg_operands MUST be the number of real register operands;
5141 implicit registers do not count. If there are 3 register
5142 operands, it must be a instruction with VexNDS. For a
5143 instruction with VexNDD, the destination register is encoded
5144 in VEX prefix. If there are 4 register operands, it must be
5145 a instruction with VEX prefix and 3 sources. */
5146 else if (i
.mem_operands
== 0
5147 && ((i
.reg_operands
== 2
5148 && !i
.tm
.opcode_modifier
.vexndd
)
5149 || (i
.reg_operands
== 3
5150 && i
.tm
.opcode_modifier
.vexnds
)
5151 || (i
.reg_operands
== 4 && vex_3_sources
)))
5159 /* When there are 3 operands, one of them may be immediate,
5160 which may be the first or the last operand. Otherwise,
5161 the first operand must be shift count register (cl) or it
5162 is an instruction with VexNDS. */
5163 assert (i
.imm_operands
== 1
5164 || (i
.imm_operands
== 0
5165 && (i
.tm
.opcode_modifier
.vexnds
5166 || i
.types
[0].bitfield
.shiftcount
)));
5167 if (operand_type_check (i
.types
[0], imm
)
5168 || i
.types
[0].bitfield
.shiftcount
)
5174 /* When there are 4 operands, the first two must be 8bit
5175 immediate operands. The source operand will be the 3rd
5178 For instructions with VexNDS, if the first operand
5179 an imm8, the source operand is the 2nd one. If the last
5180 operand is imm8, the source operand is the first one. */
5181 assert ((i
.imm_operands
== 2
5182 && i
.types
[0].bitfield
.imm8
5183 && i
.types
[1].bitfield
.imm8
)
5184 || (i
.tm
.opcode_modifier
.vexnds
5185 && i
.imm_operands
== 1
5186 && (i
.types
[0].bitfield
.imm8
5187 || i
.types
[i
.operands
- 1].bitfield
.imm8
)));
5188 if (i
.tm
.opcode_modifier
.vexnds
)
5190 if (i
.types
[0].bitfield
.imm8
)
5208 if (i
.tm
.opcode_modifier
.vexnds
)
5210 /* For instructions with VexNDS, the register-only
5211 source operand must be XMM or YMM register. It is
5212 encoded in VEX prefix. */
5213 if ((dest
+ 1) >= i
.operands
5214 || (!operand_type_equal (&i
.tm
.operand_types
[dest
],
5216 && !operand_type_equal (&i
.tm
.operand_types
[dest
],
5219 i
.vex
.register_specifier
= i
.op
[dest
].regs
;
5225 /* One of the register operands will be encoded in the i.tm.reg
5226 field, the other in the combined i.tm.mode and i.tm.regmem
5227 fields. If no form of this instruction supports a memory
5228 destination operand, then we assume the source operand may
5229 sometimes be a memory operand and so we need to store the
5230 destination in the i.rm.reg field. */
5231 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
5232 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
5234 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
5235 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
5236 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
5238 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
5243 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
5244 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
5245 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
5247 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
5250 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
5252 if (!i
.types
[0].bitfield
.control
5253 && !i
.types
[1].bitfield
.control
)
5255 i
.rex
&= ~(REX_R
| REX_B
);
5256 add_prefix (LOCK_PREFIX_OPCODE
);
5260 { /* If it's not 2 reg operands... */
5265 unsigned int fake_zero_displacement
= 0;
5268 /* This has been precalculated for SSE5 instructions
5269 that have a DREX field earlier in process_drex. */
5270 if (i
.tm
.opcode_modifier
.drex
5271 || i
.tm
.opcode_modifier
.drexv
5272 || i
.tm
.opcode_modifier
.drexc
)
5273 op
= i
.drex
.modrm_regmem
;
5276 for (op
= 0; op
< i
.operands
; op
++)
5277 if (operand_type_check (i
.types
[op
], anymem
))
5279 assert (op
< i
.operands
);
5284 if (i
.base_reg
== 0)
5287 if (!i
.disp_operands
)
5288 fake_zero_displacement
= 1;
5289 if (i
.index_reg
== 0)
5291 /* Operand is just <disp> */
5292 if (flag_code
== CODE_64BIT
)
5294 /* 64bit mode overwrites the 32bit absolute
5295 addressing by RIP relative addressing and
5296 absolute addressing is encoded by one of the
5297 redundant SIB forms. */
5298 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5299 i
.sib
.base
= NO_BASE_REGISTER
;
5300 i
.sib
.index
= NO_INDEX_REGISTER
;
5301 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
5302 ? disp32s
: disp32
);
5304 else if ((flag_code
== CODE_16BIT
)
5305 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
5307 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
5308 i
.types
[op
] = disp16
;
5312 i
.rm
.regmem
= NO_BASE_REGISTER
;
5313 i
.types
[op
] = disp32
;
5316 else /* !i.base_reg && i.index_reg */
5318 if (i
.index_reg
->reg_num
== RegEiz
5319 || i
.index_reg
->reg_num
== RegRiz
)
5320 i
.sib
.index
= NO_INDEX_REGISTER
;
5322 i
.sib
.index
= i
.index_reg
->reg_num
;
5323 i
.sib
.base
= NO_BASE_REGISTER
;
5324 i
.sib
.scale
= i
.log2_scale_factor
;
5325 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5326 i
.types
[op
].bitfield
.disp8
= 0;
5327 i
.types
[op
].bitfield
.disp16
= 0;
5328 i
.types
[op
].bitfield
.disp64
= 0;
5329 if (flag_code
!= CODE_64BIT
)
5331 /* Must be 32 bit */
5332 i
.types
[op
].bitfield
.disp32
= 1;
5333 i
.types
[op
].bitfield
.disp32s
= 0;
5337 i
.types
[op
].bitfield
.disp32
= 0;
5338 i
.types
[op
].bitfield
.disp32s
= 1;
5340 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5344 /* RIP addressing for 64bit mode. */
5345 else if (i
.base_reg
->reg_num
== RegRip
||
5346 i
.base_reg
->reg_num
== RegEip
)
5348 i
.rm
.regmem
= NO_BASE_REGISTER
;
5349 i
.types
[op
].bitfield
.disp8
= 0;
5350 i
.types
[op
].bitfield
.disp16
= 0;
5351 i
.types
[op
].bitfield
.disp32
= 0;
5352 i
.types
[op
].bitfield
.disp32s
= 1;
5353 i
.types
[op
].bitfield
.disp64
= 0;
5354 i
.flags
[op
] |= Operand_PCrel
;
5355 if (! i
.disp_operands
)
5356 fake_zero_displacement
= 1;
5358 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
5360 switch (i
.base_reg
->reg_num
)
5363 if (i
.index_reg
== 0)
5365 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
5366 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
5370 if (i
.index_reg
== 0)
5373 if (operand_type_check (i
.types
[op
], disp
) == 0)
5375 /* fake (%bp) into 0(%bp) */
5376 i
.types
[op
].bitfield
.disp8
= 1;
5377 fake_zero_displacement
= 1;
5380 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
5381 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
5383 default: /* (%si) -> 4 or (%di) -> 5 */
5384 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
5386 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5388 else /* i.base_reg and 32/64 bit mode */
5390 if (flag_code
== CODE_64BIT
5391 && operand_type_check (i
.types
[op
], disp
))
5393 i386_operand_type temp
;
5394 operand_type_set (&temp
, 0);
5395 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
5397 if (i
.prefix
[ADDR_PREFIX
] == 0)
5398 i
.types
[op
].bitfield
.disp32s
= 1;
5400 i
.types
[op
].bitfield
.disp32
= 1;
5403 i
.rm
.regmem
= i
.base_reg
->reg_num
;
5404 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
5406 i
.sib
.base
= i
.base_reg
->reg_num
;
5407 /* x86-64 ignores REX prefix bit here to avoid decoder
5409 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
5412 if (i
.disp_operands
== 0)
5414 fake_zero_displacement
= 1;
5415 i
.types
[op
].bitfield
.disp8
= 1;
5418 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
5422 i
.sib
.scale
= i
.log2_scale_factor
;
5423 if (i
.index_reg
== 0)
5425 /* <disp>(%esp) becomes two byte modrm with no index
5426 register. We've already stored the code for esp
5427 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5428 Any base register besides %esp will not use the
5429 extra modrm byte. */
5430 i
.sib
.index
= NO_INDEX_REGISTER
;
5434 if (i
.index_reg
->reg_num
== RegEiz
5435 || i
.index_reg
->reg_num
== RegRiz
)
5436 i
.sib
.index
= NO_INDEX_REGISTER
;
5438 i
.sib
.index
= i
.index_reg
->reg_num
;
5439 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5440 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5445 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5446 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
5449 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5452 if (fake_zero_displacement
)
5454 /* Fakes a zero displacement assuming that i.types[op]
5455 holds the correct displacement size. */
5458 assert (i
.op
[op
].disps
== 0);
5459 exp
= &disp_expressions
[i
.disp_operands
++];
5460 i
.op
[op
].disps
= exp
;
5461 exp
->X_op
= O_constant
;
5462 exp
->X_add_number
= 0;
5463 exp
->X_add_symbol
= (symbolS
*) 0;
5464 exp
->X_op_symbol
= (symbolS
*) 0;
5472 /* Fill in i.rm.reg or i.rm.regmem field with register operand
5473 (if any) based on i.tm.extension_opcode. Again, we must be
5474 careful to make sure that segment/control/debug/test/MMX
5475 registers are coded into the i.rm.reg field. */
5480 /* This has been precalculated for SSE5 instructions
5481 that have a DREX field earlier in process_drex. */
5482 if (i
.tm
.opcode_modifier
.drex
5483 || i
.tm
.opcode_modifier
.drexv
5484 || i
.tm
.opcode_modifier
.drexc
)
5486 op
= i
.drex
.modrm_reg
;
5487 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
5488 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5493 unsigned int vex_reg
= ~0;
5495 for (op
= 0; op
< i
.operands
; op
++)
5496 if (i
.types
[op
].bitfield
.reg8
5497 || i
.types
[op
].bitfield
.reg16
5498 || i
.types
[op
].bitfield
.reg32
5499 || i
.types
[op
].bitfield
.reg64
5500 || i
.types
[op
].bitfield
.regmmx
5501 || i
.types
[op
].bitfield
.regxmm
5502 || i
.types
[op
].bitfield
.regymm
5503 || i
.types
[op
].bitfield
.sreg2
5504 || i
.types
[op
].bitfield
.sreg3
5505 || i
.types
[op
].bitfield
.control
5506 || i
.types
[op
].bitfield
.debug
5507 || i
.types
[op
].bitfield
.test
)
5512 else if (i
.tm
.opcode_modifier
.vexnds
)
5514 /* For instructions with VexNDS, the register-only
5515 source operand is encoded in VEX prefix. */
5516 assert (mem
!= (unsigned int) ~0);
5521 assert (op
< i
.operands
);
5526 assert (vex_reg
< i
.operands
);
5529 else if (i
.tm
.opcode_modifier
.vexndd
)
5531 /* For instructions with VexNDD, there should be
5532 no memory operand and the register destination
5533 is encoded in VEX prefix. */
5534 assert (i
.mem_operands
== 0
5535 && (op
+ 2) == i
.operands
);
5539 assert (op
< i
.operands
);
5541 if (vex_reg
!= (unsigned int) ~0)
5543 assert (i
.reg_operands
== 2);
5545 if (!operand_type_equal (&i
.tm
.operand_types
[vex_reg
],
5547 && !operand_type_equal (&i
.tm
.operand_types
[vex_reg
],
5550 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
5553 /* If there is an extension opcode to put here, the
5554 register number must be put into the regmem field. */
5555 if (i
.tm
.extension_opcode
!= None
)
5557 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
5558 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5563 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
5564 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5569 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
5570 must set it to 3 to indicate this is a register operand
5571 in the regmem field. */
5572 if (!i
.mem_operands
)
5576 /* Fill in i.rm.reg field with extension opcode (if any). */
5577 if (i
.tm
.extension_opcode
!= None
5578 && !(i
.tm
.opcode_modifier
.drex
5579 || i
.tm
.opcode_modifier
.drexv
5580 || i
.tm
.opcode_modifier
.drexc
))
5581 i
.rm
.reg
= i
.tm
.extension_opcode
;
5587 output_branch (void)
5592 relax_substateT subtype
;
5597 if (flag_code
== CODE_16BIT
)
5601 if (i
.prefix
[DATA_PREFIX
] != 0)
5607 /* Pentium4 branch hints. */
5608 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
5609 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
5614 if (i
.prefix
[REX_PREFIX
] != 0)
5620 if (i
.prefixes
!= 0 && !intel_syntax
)
5621 as_warn (_("skipping prefixes on this instruction"));
5623 /* It's always a symbol; End frag & setup for relax.
5624 Make sure there is enough room in this frag for the largest
5625 instruction we may generate in md_convert_frag. This is 2
5626 bytes for the opcode and room for the prefix and largest
5628 frag_grow (prefix
+ 2 + 4);
5629 /* Prefix and 1 opcode byte go in fr_fix. */
5630 p
= frag_more (prefix
+ 1);
5631 if (i
.prefix
[DATA_PREFIX
] != 0)
5632 *p
++ = DATA_PREFIX_OPCODE
;
5633 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
5634 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
5635 *p
++ = i
.prefix
[SEG_PREFIX
];
5636 if (i
.prefix
[REX_PREFIX
] != 0)
5637 *p
++ = i
.prefix
[REX_PREFIX
];
5638 *p
= i
.tm
.base_opcode
;
5640 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
5641 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
);
5642 else if (cpu_arch_flags
.bitfield
.cpui386
)
5643 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, SMALL
);
5645 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, SMALL
);
5648 sym
= i
.op
[0].disps
->X_add_symbol
;
5649 off
= i
.op
[0].disps
->X_add_number
;
5651 if (i
.op
[0].disps
->X_op
!= O_constant
5652 && i
.op
[0].disps
->X_op
!= O_symbol
)
5654 /* Handle complex expressions. */
5655 sym
= make_expr_symbol (i
.op
[0].disps
);
5659 /* 1 possible extra opcode + 4 byte displacement go in var part.
5660 Pass reloc in fr_var. */
5661 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
5671 if (i
.tm
.opcode_modifier
.jumpbyte
)
5673 /* This is a loop or jecxz type instruction. */
5675 if (i
.prefix
[ADDR_PREFIX
] != 0)
5677 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
5680 /* Pentium4 branch hints. */
5681 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
5682 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
5684 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
5693 if (flag_code
== CODE_16BIT
)
5696 if (i
.prefix
[DATA_PREFIX
] != 0)
5698 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
5708 if (i
.prefix
[REX_PREFIX
] != 0)
5710 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
5714 if (i
.prefixes
!= 0 && !intel_syntax
)
5715 as_warn (_("skipping prefixes on this instruction"));
5717 p
= frag_more (1 + size
);
5718 *p
++ = i
.tm
.base_opcode
;
5720 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5721 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
5723 /* All jumps handled here are signed, but don't use a signed limit
5724 check for 32 and 16 bit jumps as we want to allow wrap around at
5725 4G and 64k respectively. */
5727 fixP
->fx_signed
= 1;
5731 output_interseg_jump (void)
5739 if (flag_code
== CODE_16BIT
)
5743 if (i
.prefix
[DATA_PREFIX
] != 0)
5749 if (i
.prefix
[REX_PREFIX
] != 0)
5759 if (i
.prefixes
!= 0 && !intel_syntax
)
5760 as_warn (_("skipping prefixes on this instruction"));
5762 /* 1 opcode; 2 segment; offset */
5763 p
= frag_more (prefix
+ 1 + 2 + size
);
5765 if (i
.prefix
[DATA_PREFIX
] != 0)
5766 *p
++ = DATA_PREFIX_OPCODE
;
5768 if (i
.prefix
[REX_PREFIX
] != 0)
5769 *p
++ = i
.prefix
[REX_PREFIX
];
5771 *p
++ = i
.tm
.base_opcode
;
5772 if (i
.op
[1].imms
->X_op
== O_constant
)
5774 offsetT n
= i
.op
[1].imms
->X_add_number
;
5777 && !fits_in_unsigned_word (n
)
5778 && !fits_in_signed_word (n
))
5780 as_bad (_("16-bit jump out of range"));
5783 md_number_to_chars (p
, n
, size
);
5786 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5787 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
5788 if (i
.op
[0].imms
->X_op
!= O_constant
)
5789 as_bad (_("can't handle non absolute segment in `%s'"),
5791 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
5797 fragS
*insn_start_frag
;
5798 offsetT insn_start_off
;
5800 /* Tie dwarf2 debug info to the address at the start of the insn.
5801 We can't do this after the insn has been output as the current
5802 frag may have been closed off. eg. by frag_var. */
5803 dwarf2_emit_insn (0);
5805 insn_start_frag
= frag_now
;
5806 insn_start_off
= frag_now_fix ();
5809 if (i
.tm
.opcode_modifier
.jump
)
5811 else if (i
.tm
.opcode_modifier
.jumpbyte
5812 || i
.tm
.opcode_modifier
.jumpdword
)
5814 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
5815 output_interseg_jump ();
5818 /* Output normal instructions here. */
5822 unsigned int prefix
;
5824 /* Since the VEX prefix contains the implicit prefix, we don't
5825 need the explicit prefix. */
5826 if (!i
.tm
.opcode_modifier
.vex
)
5828 switch (i
.tm
.opcode_length
)
5831 if (i
.tm
.base_opcode
& 0xff000000)
5833 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
5838 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
5840 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
5841 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
5844 if (prefix
!= REPE_PREFIX_OPCODE
5845 || (i
.prefix
[LOCKREP_PREFIX
]
5846 != REPE_PREFIX_OPCODE
))
5847 add_prefix (prefix
);
5850 add_prefix (prefix
);
5859 /* The prefix bytes. */
5860 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
5862 FRAG_APPEND_1_CHAR (*q
);
5865 if (i
.tm
.opcode_modifier
.vex
)
5867 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
5872 /* REX byte is encoded in VEX prefix. */
5876 FRAG_APPEND_1_CHAR (*q
);
5879 /* There should be no other prefixes for instructions
5884 /* Now the VEX prefix. */
5885 p
= frag_more (i
.vex
.length
);
5886 for (j
= 0; j
< i
.vex
.length
; j
++)
5887 p
[j
] = i
.vex
.bytes
[j
];
5890 /* Now the opcode; be careful about word order here! */
5891 if (i
.tm
.opcode_length
== 1)
5893 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
5897 switch (i
.tm
.opcode_length
)
5901 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
5911 /* Put out high byte first: can't use md_number_to_chars! */
5912 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
5913 *p
= i
.tm
.base_opcode
& 0xff;
5915 /* On SSE5, encode the OC1 bit in the DREX field if this
5916 encoding has multiple formats. */
5917 if (i
.tm
.opcode_modifier
.drex
5918 && i
.tm
.opcode_modifier
.drexv
5919 && DREX_OC1 (i
.tm
.extension_opcode
))
5920 *p
|= DREX_OC1_MASK
;
5923 /* Now the modrm byte and sib byte (if present). */
5924 if (i
.tm
.opcode_modifier
.modrm
)
5926 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
5929 /* If i.rm.regmem == ESP (4)
5930 && i.rm.mode != (Register mode)
5932 ==> need second modrm byte. */
5933 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
5935 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
5936 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
5938 | i
.sib
.scale
<< 6));
5941 /* Write the DREX byte if needed. */
5942 if (i
.tm
.opcode_modifier
.drex
|| i
.tm
.opcode_modifier
.drexc
)
5945 *p
= (((i
.drex
.reg
& 0xf) << 4) | (i
.drex
.rex
& 0x7));
5947 /* Encode the OC0 bit if this encoding has multiple
5949 if ((i
.tm
.opcode_modifier
.drex
5950 || i
.tm
.opcode_modifier
.drexv
)
5951 && DREX_OC0 (i
.tm
.extension_opcode
))
5952 *p
|= DREX_OC0_MASK
;
5955 if (i
.disp_operands
)
5956 output_disp (insn_start_frag
, insn_start_off
);
5959 output_imm (insn_start_frag
, insn_start_off
);
5965 pi ("" /*line*/, &i
);
5967 #endif /* DEBUG386 */
5970 /* Return the size of the displacement operand N. */
5973 disp_size (unsigned int n
)
5976 if (i
.types
[n
].bitfield
.disp64
)
5978 else if (i
.types
[n
].bitfield
.disp8
)
5980 else if (i
.types
[n
].bitfield
.disp16
)
5985 /* Return the size of the immediate operand N. */
5988 imm_size (unsigned int n
)
5991 if (i
.types
[n
].bitfield
.imm64
)
5993 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
5995 else if (i
.types
[n
].bitfield
.imm16
)
6001 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
6006 for (n
= 0; n
< i
.operands
; n
++)
6008 if (operand_type_check (i
.types
[n
], disp
))
6010 if (i
.op
[n
].disps
->X_op
== O_constant
)
6012 int size
= disp_size (n
);
6015 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
6017 p
= frag_more (size
);
6018 md_number_to_chars (p
, val
, size
);
6022 enum bfd_reloc_code_real reloc_type
;
6023 int size
= disp_size (n
);
6024 int sign
= i
.types
[n
].bitfield
.disp32s
;
6025 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
6027 /* We can't have 8 bit displacement here. */
6028 assert (!i
.types
[n
].bitfield
.disp8
);
6030 /* The PC relative address is computed relative
6031 to the instruction boundary, so in case immediate
6032 fields follows, we need to adjust the value. */
6033 if (pcrel
&& i
.imm_operands
)
6038 for (n1
= 0; n1
< i
.operands
; n1
++)
6039 if (operand_type_check (i
.types
[n1
], imm
))
6041 /* Only one immediate is allowed for PC
6042 relative address. */
6045 i
.op
[n
].disps
->X_add_number
-= sz
;
6047 /* We should find the immediate. */
6051 p
= frag_more (size
);
6052 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
6054 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
6055 && (((reloc_type
== BFD_RELOC_32
6056 || reloc_type
== BFD_RELOC_X86_64_32S
6057 || (reloc_type
== BFD_RELOC_64
6059 && (i
.op
[n
].disps
->X_op
== O_symbol
6060 || (i
.op
[n
].disps
->X_op
== O_add
6061 && ((symbol_get_value_expression
6062 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
6064 || reloc_type
== BFD_RELOC_32_PCREL
))
6068 if (insn_start_frag
== frag_now
)
6069 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
6074 add
= insn_start_frag
->fr_fix
- insn_start_off
;
6075 for (fr
= insn_start_frag
->fr_next
;
6076 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
6078 add
+= p
- frag_now
->fr_literal
;
6083 reloc_type
= BFD_RELOC_386_GOTPC
;
6084 i
.op
[n
].imms
->X_add_number
+= add
;
6086 else if (reloc_type
== BFD_RELOC_64
)
6087 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
6089 /* Don't do the adjustment for x86-64, as there
6090 the pcrel addressing is relative to the _next_
6091 insn, and that is taken care of in other code. */
6092 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
6094 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6095 i
.op
[n
].disps
, pcrel
, reloc_type
);
6102 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
6107 for (n
= 0; n
< i
.operands
; n
++)
6109 if (operand_type_check (i
.types
[n
], imm
))
6111 if (i
.op
[n
].imms
->X_op
== O_constant
)
6113 int size
= imm_size (n
);
6116 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
6118 p
= frag_more (size
);
6119 md_number_to_chars (p
, val
, size
);
6123 /* Not absolute_section.
6124 Need a 32-bit fixup (don't support 8bit
6125 non-absolute imms). Try to support other
6127 enum bfd_reloc_code_real reloc_type
;
6128 int size
= imm_size (n
);
6131 if (i
.types
[n
].bitfield
.imm32s
6132 && (i
.suffix
== QWORD_MNEM_SUFFIX
6133 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
6138 p
= frag_more (size
);
6139 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
6141 /* This is tough to explain. We end up with this one if we
6142 * have operands that look like
6143 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
6144 * obtain the absolute address of the GOT, and it is strongly
6145 * preferable from a performance point of view to avoid using
6146 * a runtime relocation for this. The actual sequence of
6147 * instructions often look something like:
6152 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
6154 * The call and pop essentially return the absolute address
6155 * of the label .L66 and store it in %ebx. The linker itself
6156 * will ultimately change the first operand of the addl so
6157 * that %ebx points to the GOT, but to keep things simple, the
6158 * .o file must have this operand set so that it generates not
6159 * the absolute address of .L66, but the absolute address of
6160 * itself. This allows the linker itself simply treat a GOTPC
6161 * relocation as asking for a pcrel offset to the GOT to be
6162 * added in, and the addend of the relocation is stored in the
6163 * operand field for the instruction itself.
6165 * Our job here is to fix the operand so that it would add
6166 * the correct offset so that %ebx would point to itself. The
6167 * thing that is tricky is that .-.L66 will point to the
6168 * beginning of the instruction, so we need to further modify
6169 * the operand so that it will point to itself. There are
6170 * other cases where you have something like:
6172 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
6174 * and here no correction would be required. Internally in
6175 * the assembler we treat operands of this form as not being
6176 * pcrel since the '.' is explicitly mentioned, and I wonder
6177 * whether it would simplify matters to do it this way. Who
6178 * knows. In earlier versions of the PIC patches, the
6179 * pcrel_adjust field was used to store the correction, but
6180 * since the expression is not pcrel, I felt it would be
6181 * confusing to do it this way. */
6183 if ((reloc_type
== BFD_RELOC_32
6184 || reloc_type
== BFD_RELOC_X86_64_32S
6185 || reloc_type
== BFD_RELOC_64
)
6187 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
6188 && (i
.op
[n
].imms
->X_op
== O_symbol
6189 || (i
.op
[n
].imms
->X_op
== O_add
6190 && ((symbol_get_value_expression
6191 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
6196 if (insn_start_frag
== frag_now
)
6197 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
6202 add
= insn_start_frag
->fr_fix
- insn_start_off
;
6203 for (fr
= insn_start_frag
->fr_next
;
6204 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
6206 add
+= p
- frag_now
->fr_literal
;
6210 reloc_type
= BFD_RELOC_386_GOTPC
;
6212 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
6214 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
6215 i
.op
[n
].imms
->X_add_number
+= add
;
6217 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6218 i
.op
[n
].imms
, 0, reloc_type
);
6224 /* x86_cons_fix_new is called via the expression parsing code when a
6225 reloc is needed. We use this hook to get the correct .got reloc. */
6226 static enum bfd_reloc_code_real got_reloc
= NO_RELOC
;
6227 static int cons_sign
= -1;
6230 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
6233 enum bfd_reloc_code_real r
= reloc (len
, 0, cons_sign
, got_reloc
);
6235 got_reloc
= NO_RELOC
;
6238 if (exp
->X_op
== O_secrel
)
6240 exp
->X_op
= O_symbol
;
6241 r
= BFD_RELOC_32_SECREL
;
6245 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
6248 #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
6249 # define lex_got(reloc, adjust, types) NULL
6251 /* Parse operands of the form
6252 <symbol>@GOTOFF+<nnn>
6253 and similar .plt or .got references.
6255 If we find one, set up the correct relocation in RELOC and copy the
6256 input string, minus the `@GOTOFF' into a malloc'd buffer for
6257 parsing by the calling routine. Return this buffer, and if ADJUST
6258 is non-null set it to the length of the string we removed from the
6259 input line. Otherwise return NULL. */
6261 lex_got (enum bfd_reloc_code_real
*reloc
,
6263 i386_operand_type
*types
)
6265 /* Some of the relocations depend on the size of what field is to
6266 be relocated. But in our callers i386_immediate and i386_displacement
6267 we don't yet know the operand size (this will be set by insn
6268 matching). Hence we record the word32 relocation here,
6269 and adjust the reloc according to the real size in reloc(). */
6270 static const struct {
6272 const enum bfd_reloc_code_real rel
[2];
6273 const i386_operand_type types64
;
6276 BFD_RELOC_X86_64_PLTOFF64
},
6277 OPERAND_TYPE_IMM64
},
6278 { "PLT", { BFD_RELOC_386_PLT32
,
6279 BFD_RELOC_X86_64_PLT32
},
6280 OPERAND_TYPE_IMM32_32S_DISP32
},
6282 BFD_RELOC_X86_64_GOTPLT64
},
6283 OPERAND_TYPE_IMM64_DISP64
},
6284 { "GOTOFF", { BFD_RELOC_386_GOTOFF
,
6285 BFD_RELOC_X86_64_GOTOFF64
},
6286 OPERAND_TYPE_IMM64_DISP64
},
6288 BFD_RELOC_X86_64_GOTPCREL
},
6289 OPERAND_TYPE_IMM32_32S_DISP32
},
6290 { "TLSGD", { BFD_RELOC_386_TLS_GD
,
6291 BFD_RELOC_X86_64_TLSGD
},
6292 OPERAND_TYPE_IMM32_32S_DISP32
},
6293 { "TLSLDM", { BFD_RELOC_386_TLS_LDM
,
6295 OPERAND_TYPE_NONE
},
6297 BFD_RELOC_X86_64_TLSLD
},
6298 OPERAND_TYPE_IMM32_32S_DISP32
},
6299 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32
,
6300 BFD_RELOC_X86_64_GOTTPOFF
},
6301 OPERAND_TYPE_IMM32_32S_DISP32
},
6302 { "TPOFF", { BFD_RELOC_386_TLS_LE_32
,
6303 BFD_RELOC_X86_64_TPOFF32
},
6304 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6305 { "NTPOFF", { BFD_RELOC_386_TLS_LE
,
6307 OPERAND_TYPE_NONE
},
6308 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32
,
6309 BFD_RELOC_X86_64_DTPOFF32
},
6311 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6312 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE
,
6314 OPERAND_TYPE_NONE
},
6315 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE
,
6317 OPERAND_TYPE_NONE
},
6318 { "GOT", { BFD_RELOC_386_GOT32
,
6319 BFD_RELOC_X86_64_GOT32
},
6320 OPERAND_TYPE_IMM32_32S_64_DISP32
},
6321 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC
,
6322 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
6323 OPERAND_TYPE_IMM32_32S_DISP32
},
6324 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL
,
6325 BFD_RELOC_X86_64_TLSDESC_CALL
},
6326 OPERAND_TYPE_IMM32_32S_DISP32
},
6334 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
6335 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
6338 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
6342 len
= strlen (gotrel
[j
].str
);
6343 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
6345 if (gotrel
[j
].rel
[object_64bit
] != 0)
6348 char *tmpbuf
, *past_reloc
;
6350 *reloc
= gotrel
[j
].rel
[object_64bit
];
6356 if (flag_code
!= CODE_64BIT
)
6358 types
->bitfield
.imm32
= 1;
6359 types
->bitfield
.disp32
= 1;
6362 *types
= gotrel
[j
].types64
;
6365 if (GOT_symbol
== NULL
)
6366 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
6368 /* The length of the first part of our input line. */
6369 first
= cp
- input_line_pointer
;
6371 /* The second part goes from after the reloc token until
6372 (and including) an end_of_line char or comma. */
6373 past_reloc
= cp
+ 1 + len
;
6375 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
6377 second
= cp
+ 1 - past_reloc
;
6379 /* Allocate and copy string. The trailing NUL shouldn't
6380 be necessary, but be safe. */
6381 tmpbuf
= xmalloc (first
+ second
+ 2);
6382 memcpy (tmpbuf
, input_line_pointer
, first
);
6383 if (second
!= 0 && *past_reloc
!= ' ')
6384 /* Replace the relocation token with ' ', so that
6385 errors like foo@GOTOFF1 will be detected. */
6386 tmpbuf
[first
++] = ' ';
6387 memcpy (tmpbuf
+ first
, past_reloc
, second
);
6388 tmpbuf
[first
+ second
] = '\0';
6392 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6393 gotrel
[j
].str
, 1 << (5 + object_64bit
));
6398 /* Might be a symbol version string. Don't as_bad here. */
6403 x86_cons (expressionS
*exp
, int size
)
6405 if (size
== 4 || (object_64bit
&& size
== 8))
6407 /* Handle @GOTOFF and the like in an expression. */
6409 char *gotfree_input_line
;
6412 save
= input_line_pointer
;
6413 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
6414 if (gotfree_input_line
)
6415 input_line_pointer
= gotfree_input_line
;
6419 if (gotfree_input_line
)
6421 /* expression () has merrily parsed up to the end of line,
6422 or a comma - in the wrong buffer. Transfer how far
6423 input_line_pointer has moved to the right buffer. */
6424 input_line_pointer
= (save
6425 + (input_line_pointer
- gotfree_input_line
)
6427 free (gotfree_input_line
);
6428 if (exp
->X_op
== O_constant
6429 || exp
->X_op
== O_absent
6430 || exp
->X_op
== O_illegal
6431 || exp
->X_op
== O_register
6432 || exp
->X_op
== O_big
)
6434 char c
= *input_line_pointer
;
6435 *input_line_pointer
= 0;
6436 as_bad (_("missing or invalid expression `%s'"), save
);
6437 *input_line_pointer
= c
;
6446 static void signed_cons (int size
)
6448 if (flag_code
== CODE_64BIT
)
6456 pe_directive_secrel (dummy
)
6457 int dummy ATTRIBUTE_UNUSED
;
6464 if (exp
.X_op
== O_symbol
)
6465 exp
.X_op
= O_secrel
;
6467 emit_expr (&exp
, 4);
6469 while (*input_line_pointer
++ == ',');
6471 input_line_pointer
--;
6472 demand_empty_rest_of_line ();
6477 i386_immediate (char *imm_start
)
6479 char *save_input_line_pointer
;
6480 char *gotfree_input_line
;
6483 i386_operand_type types
;
6485 operand_type_set (&types
, ~0);
6487 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
6489 as_bad (_("at most %d immediate operands are allowed"),
6490 MAX_IMMEDIATE_OPERANDS
);
6494 exp
= &im_expressions
[i
.imm_operands
++];
6495 i
.op
[this_operand
].imms
= exp
;
6497 if (is_space_char (*imm_start
))
6500 save_input_line_pointer
= input_line_pointer
;
6501 input_line_pointer
= imm_start
;
6503 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
6504 if (gotfree_input_line
)
6505 input_line_pointer
= gotfree_input_line
;
6507 exp_seg
= expression (exp
);
6510 if (*input_line_pointer
)
6511 as_bad (_("junk `%s' after expression"), input_line_pointer
);
6513 input_line_pointer
= save_input_line_pointer
;
6514 if (gotfree_input_line
)
6515 free (gotfree_input_line
);
6517 if (exp
->X_op
== O_absent
6518 || exp
->X_op
== O_illegal
6519 || exp
->X_op
== O_big
6520 || (gotfree_input_line
6521 && (exp
->X_op
== O_constant
6522 || exp
->X_op
== O_register
)))
6524 as_bad (_("missing or invalid immediate expression `%s'"),
6528 else if (exp
->X_op
== O_constant
)
6530 /* Size it properly later. */
6531 i
.types
[this_operand
].bitfield
.imm64
= 1;
6532 /* If BFD64, sign extend val. */
6533 if (!use_rela_relocations
6534 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
6536 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
6538 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6539 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
6540 && exp_seg
!= absolute_section
6541 && exp_seg
!= text_section
6542 && exp_seg
!= data_section
6543 && exp_seg
!= bss_section
6544 && exp_seg
!= undefined_section
6545 && !bfd_is_com_section (exp_seg
))
6547 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
6551 else if (!intel_syntax
&& exp
->X_op
== O_register
)
6553 as_bad (_("illegal immediate register operand %s"), imm_start
);
6558 /* This is an address. The size of the address will be
6559 determined later, depending on destination register,
6560 suffix, or the default for the section. */
6561 i
.types
[this_operand
].bitfield
.imm8
= 1;
6562 i
.types
[this_operand
].bitfield
.imm16
= 1;
6563 i
.types
[this_operand
].bitfield
.imm32
= 1;
6564 i
.types
[this_operand
].bitfield
.imm32s
= 1;
6565 i
.types
[this_operand
].bitfield
.imm64
= 1;
6566 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
6574 i386_scale (char *scale
)
6577 char *save
= input_line_pointer
;
6579 input_line_pointer
= scale
;
6580 val
= get_absolute_expression ();
6585 i
.log2_scale_factor
= 0;
6588 i
.log2_scale_factor
= 1;
6591 i
.log2_scale_factor
= 2;
6594 i
.log2_scale_factor
= 3;
6598 char sep
= *input_line_pointer
;
6600 *input_line_pointer
= '\0';
6601 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
6603 *input_line_pointer
= sep
;
6604 input_line_pointer
= save
;
6608 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
6610 as_warn (_("scale factor of %d without an index register"),
6611 1 << i
.log2_scale_factor
);
6612 i
.log2_scale_factor
= 0;
6614 scale
= input_line_pointer
;
6615 input_line_pointer
= save
;
6620 i386_displacement (char *disp_start
, char *disp_end
)
6624 char *save_input_line_pointer
;
6625 char *gotfree_input_line
;
6627 i386_operand_type bigdisp
, types
= anydisp
;
6630 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
6632 as_bad (_("at most %d displacement operands are allowed"),
6633 MAX_MEMORY_OPERANDS
);
6637 operand_type_set (&bigdisp
, 0);
6638 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
6639 || (!current_templates
->start
->opcode_modifier
.jump
6640 && !current_templates
->start
->opcode_modifier
.jumpdword
))
6642 bigdisp
.bitfield
.disp32
= 1;
6643 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
6644 if (flag_code
== CODE_64BIT
)
6648 bigdisp
.bitfield
.disp32s
= 1;
6649 bigdisp
.bitfield
.disp64
= 1;
6652 else if ((flag_code
== CODE_16BIT
) ^ override
)
6654 bigdisp
.bitfield
.disp32
= 0;
6655 bigdisp
.bitfield
.disp16
= 1;
6660 /* For PC-relative branches, the width of the displacement
6661 is dependent upon data size, not address size. */
6662 override
= (i
.prefix
[DATA_PREFIX
] != 0);
6663 if (flag_code
== CODE_64BIT
)
6665 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
6666 bigdisp
.bitfield
.disp16
= 1;
6669 bigdisp
.bitfield
.disp32
= 1;
6670 bigdisp
.bitfield
.disp32s
= 1;
6676 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
6678 : LONG_MNEM_SUFFIX
));
6679 bigdisp
.bitfield
.disp32
= 1;
6680 if ((flag_code
== CODE_16BIT
) ^ override
)
6682 bigdisp
.bitfield
.disp32
= 0;
6683 bigdisp
.bitfield
.disp16
= 1;
6687 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
6690 exp
= &disp_expressions
[i
.disp_operands
];
6691 i
.op
[this_operand
].disps
= exp
;
6693 save_input_line_pointer
= input_line_pointer
;
6694 input_line_pointer
= disp_start
;
6695 END_STRING_AND_SAVE (disp_end
);
6697 #ifndef GCC_ASM_O_HACK
6698 #define GCC_ASM_O_HACK 0
6701 END_STRING_AND_SAVE (disp_end
+ 1);
6702 if (i
.types
[this_operand
].bitfield
.baseIndex
6703 && displacement_string_end
[-1] == '+')
6705 /* This hack is to avoid a warning when using the "o"
6706 constraint within gcc asm statements.
6709 #define _set_tssldt_desc(n,addr,limit,type) \
6710 __asm__ __volatile__ ( \
6712 "movw %w1,2+%0\n\t" \
6714 "movb %b1,4+%0\n\t" \
6715 "movb %4,5+%0\n\t" \
6716 "movb $0,6+%0\n\t" \
6717 "movb %h1,7+%0\n\t" \
6719 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
6721 This works great except that the output assembler ends
6722 up looking a bit weird if it turns out that there is
6723 no offset. You end up producing code that looks like:
6736 So here we provide the missing zero. */
6738 *displacement_string_end
= '0';
6741 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
6742 if (gotfree_input_line
)
6743 input_line_pointer
= gotfree_input_line
;
6745 exp_seg
= expression (exp
);
6748 if (*input_line_pointer
)
6749 as_bad (_("junk `%s' after expression"), input_line_pointer
);
6751 RESTORE_END_STRING (disp_end
+ 1);
6753 input_line_pointer
= save_input_line_pointer
;
6754 if (gotfree_input_line
)
6755 free (gotfree_input_line
);
6758 /* We do this to make sure that the section symbol is in
6759 the symbol table. We will ultimately change the relocation
6760 to be relative to the beginning of the section. */
6761 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
6762 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
6763 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
6765 if (exp
->X_op
!= O_symbol
)
6768 if (S_IS_LOCAL (exp
->X_add_symbol
)
6769 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
6770 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
6771 exp
->X_op
= O_subtract
;
6772 exp
->X_op_symbol
= GOT_symbol
;
6773 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
6774 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
6775 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
6776 i
.reloc
[this_operand
] = BFD_RELOC_64
;
6778 i
.reloc
[this_operand
] = BFD_RELOC_32
;
6781 else if (exp
->X_op
== O_absent
6782 || exp
->X_op
== O_illegal
6783 || exp
->X_op
== O_big
6784 || (gotfree_input_line
6785 && (exp
->X_op
== O_constant
6786 || exp
->X_op
== O_register
)))
6789 as_bad (_("missing or invalid displacement expression `%s'"),
6794 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6795 else if (exp
->X_op
!= O_constant
6796 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
6797 && exp_seg
!= absolute_section
6798 && exp_seg
!= text_section
6799 && exp_seg
!= data_section
6800 && exp_seg
!= bss_section
6801 && exp_seg
!= undefined_section
6802 && !bfd_is_com_section (exp_seg
))
6804 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
6809 RESTORE_END_STRING (disp_end
);
6811 /* Check if this is a displacement only operand. */
6812 bigdisp
= i
.types
[this_operand
];
6813 bigdisp
.bitfield
.disp8
= 0;
6814 bigdisp
.bitfield
.disp16
= 0;
6815 bigdisp
.bitfield
.disp32
= 0;
6816 bigdisp
.bitfield
.disp32s
= 0;
6817 bigdisp
.bitfield
.disp64
= 0;
6818 if (operand_type_all_zero (&bigdisp
))
6819 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
6825 /* Make sure the memory operand we've been dealt is valid.
6826 Return 1 on success, 0 on a failure. */
6829 i386_index_check (const char *operand_string
)
6832 #if INFER_ADDR_PREFIX
6838 if (flag_code
== CODE_64BIT
)
6841 && ((i
.prefix
[ADDR_PREFIX
] == 0
6842 && !i
.base_reg
->reg_type
.bitfield
.reg64
)
6843 || (i
.prefix
[ADDR_PREFIX
]
6844 && !i
.base_reg
->reg_type
.bitfield
.reg32
))
6846 || i
.base_reg
->reg_num
!=
6847 (i
.prefix
[ADDR_PREFIX
] == 0 ? RegRip
: RegEip
)))
6849 && (!i
.index_reg
->reg_type
.bitfield
.baseindex
6850 || (i
.prefix
[ADDR_PREFIX
] == 0
6851 && i
.index_reg
->reg_num
!= RegRiz
6852 && !i
.index_reg
->reg_type
.bitfield
.reg64
6854 || (i
.prefix
[ADDR_PREFIX
]
6855 && i
.index_reg
->reg_num
!= RegEiz
6856 && !i
.index_reg
->reg_type
.bitfield
.reg32
))))
6861 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
6865 && (!i
.base_reg
->reg_type
.bitfield
.reg16
6866 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
6868 && (!i
.index_reg
->reg_type
.bitfield
.reg16
6869 || !i
.index_reg
->reg_type
.bitfield
.baseindex
6871 && i
.base_reg
->reg_num
< 6
6872 && i
.index_reg
->reg_num
>= 6
6873 && i
.log2_scale_factor
== 0))))
6880 && !i
.base_reg
->reg_type
.bitfield
.reg32
)
6882 && ((!i
.index_reg
->reg_type
.bitfield
.reg32
6883 && i
.index_reg
->reg_num
!= RegEiz
)
6884 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
6890 #if INFER_ADDR_PREFIX
6891 if (i
.prefix
[ADDR_PREFIX
] == 0)
6893 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
6895 /* Change the size of any displacement too. At most one of
6896 Disp16 or Disp32 is set.
6897 FIXME. There doesn't seem to be any real need for separate
6898 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
6899 Removing them would probably clean up the code quite a lot. */
6900 if (flag_code
!= CODE_64BIT
6901 && (i
.types
[this_operand
].bitfield
.disp16
6902 || i
.types
[this_operand
].bitfield
.disp32
))
6903 i
.types
[this_operand
]
6904 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
6909 as_bad (_("`%s' is not a valid base/index expression"),
6913 as_bad (_("`%s' is not a valid %s bit base/index expression"),
6915 flag_code_names
[flag_code
]);
6920 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
6924 i386_att_operand (char *operand_string
)
6928 char *op_string
= operand_string
;
6930 if (is_space_char (*op_string
))
6933 /* We check for an absolute prefix (differentiating,
6934 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
6935 if (*op_string
== ABSOLUTE_PREFIX
)
6938 if (is_space_char (*op_string
))
6940 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
6943 /* Check if operand is a register. */
6944 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
6946 i386_operand_type temp
;
6948 /* Check for a segment override by searching for ':' after a
6949 segment register. */
6951 if (is_space_char (*op_string
))
6953 if (*op_string
== ':'
6954 && (r
->reg_type
.bitfield
.sreg2
6955 || r
->reg_type
.bitfield
.sreg3
))
6960 i
.seg
[i
.mem_operands
] = &es
;
6963 i
.seg
[i
.mem_operands
] = &cs
;
6966 i
.seg
[i
.mem_operands
] = &ss
;
6969 i
.seg
[i
.mem_operands
] = &ds
;
6972 i
.seg
[i
.mem_operands
] = &fs
;
6975 i
.seg
[i
.mem_operands
] = &gs
;
6979 /* Skip the ':' and whitespace. */
6981 if (is_space_char (*op_string
))
6984 if (!is_digit_char (*op_string
)
6985 && !is_identifier_char (*op_string
)
6986 && *op_string
!= '('
6987 && *op_string
!= ABSOLUTE_PREFIX
)
6989 as_bad (_("bad memory operand `%s'"), op_string
);
6992 /* Handle case of %es:*foo. */
6993 if (*op_string
== ABSOLUTE_PREFIX
)
6996 if (is_space_char (*op_string
))
6998 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
7000 goto do_memory_reference
;
7004 as_bad (_("junk `%s' after register"), op_string
);
7008 temp
.bitfield
.baseindex
= 0;
7009 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
7011 i
.types
[this_operand
].bitfield
.unspecified
= 0;
7012 i
.op
[this_operand
].regs
= r
;
7015 else if (*op_string
== REGISTER_PREFIX
)
7017 as_bad (_("bad register name `%s'"), op_string
);
7020 else if (*op_string
== IMMEDIATE_PREFIX
)
7023 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
7025 as_bad (_("immediate operand illegal with absolute jump"));
7028 if (!i386_immediate (op_string
))
7031 else if (is_digit_char (*op_string
)
7032 || is_identifier_char (*op_string
)
7033 || *op_string
== '(')
7035 /* This is a memory reference of some sort. */
7038 /* Start and end of displacement string expression (if found). */
7039 char *displacement_string_start
;
7040 char *displacement_string_end
;
7042 do_memory_reference
:
7043 if ((i
.mem_operands
== 1
7044 && !current_templates
->start
->opcode_modifier
.isstring
)
7045 || i
.mem_operands
== 2)
7047 as_bad (_("too many memory references for `%s'"),
7048 current_templates
->start
->name
);
7052 /* Check for base index form. We detect the base index form by
7053 looking for an ')' at the end of the operand, searching
7054 for the '(' matching it, and finding a REGISTER_PREFIX or ','
7056 base_string
= op_string
+ strlen (op_string
);
7059 if (is_space_char (*base_string
))
7062 /* If we only have a displacement, set-up for it to be parsed later. */
7063 displacement_string_start
= op_string
;
7064 displacement_string_end
= base_string
+ 1;
7066 if (*base_string
== ')')
7069 unsigned int parens_balanced
= 1;
7070 /* We've already checked that the number of left & right ()'s are
7071 equal, so this loop will not be infinite. */
7075 if (*base_string
== ')')
7077 if (*base_string
== '(')
7080 while (parens_balanced
);
7082 temp_string
= base_string
;
7084 /* Skip past '(' and whitespace. */
7086 if (is_space_char (*base_string
))
7089 if (*base_string
== ','
7090 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
7093 displacement_string_end
= temp_string
;
7095 i
.types
[this_operand
].bitfield
.baseindex
= 1;
7099 base_string
= end_op
;
7100 if (is_space_char (*base_string
))
7104 /* There may be an index reg or scale factor here. */
7105 if (*base_string
== ',')
7108 if (is_space_char (*base_string
))
7111 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
7114 base_string
= end_op
;
7115 if (is_space_char (*base_string
))
7117 if (*base_string
== ',')
7120 if (is_space_char (*base_string
))
7123 else if (*base_string
!= ')')
7125 as_bad (_("expecting `,' or `)' "
7126 "after index register in `%s'"),
7131 else if (*base_string
== REGISTER_PREFIX
)
7133 as_bad (_("bad register name `%s'"), base_string
);
7137 /* Check for scale factor. */
7138 if (*base_string
!= ')')
7140 char *end_scale
= i386_scale (base_string
);
7145 base_string
= end_scale
;
7146 if (is_space_char (*base_string
))
7148 if (*base_string
!= ')')
7150 as_bad (_("expecting `)' "
7151 "after scale factor in `%s'"),
7156 else if (!i
.index_reg
)
7158 as_bad (_("expecting index register or scale factor "
7159 "after `,'; got '%c'"),
7164 else if (*base_string
!= ')')
7166 as_bad (_("expecting `,' or `)' "
7167 "after base register in `%s'"),
7172 else if (*base_string
== REGISTER_PREFIX
)
7174 as_bad (_("bad register name `%s'"), base_string
);
7179 /* If there's an expression beginning the operand, parse it,
7180 assuming displacement_string_start and
7181 displacement_string_end are meaningful. */
7182 if (displacement_string_start
!= displacement_string_end
)
7184 if (!i386_displacement (displacement_string_start
,
7185 displacement_string_end
))
7189 /* Special case for (%dx) while doing input/output op. */
7191 && operand_type_equal (&i
.base_reg
->reg_type
,
7192 ®16_inoutportreg
)
7194 && i
.log2_scale_factor
== 0
7195 && i
.seg
[i
.mem_operands
] == 0
7196 && !operand_type_check (i
.types
[this_operand
], disp
))
7198 i
.types
[this_operand
] = inoutportreg
;
7202 if (i386_index_check (operand_string
) == 0)
7204 i
.types
[this_operand
].bitfield
.mem
= 1;
7209 /* It's not a memory operand; argh! */
7210 as_bad (_("invalid char %s beginning operand %d `%s'"),
7211 output_invalid (*op_string
),
7216 return 1; /* Normal return. */
7219 /* md_estimate_size_before_relax()
7221 Called just before relax() for rs_machine_dependent frags. The x86
7222 assembler uses these frags to handle variable size jump
7225 Any symbol that is now undefined will not become defined.
7226 Return the correct fr_subtype in the frag.
7227 Return the initial "guess for variable size of frag" to caller.
7228 The guess is actually the growth beyond the fixed part. Whatever
7229 we do to grow the fixed or variable part contributes to our
7233 md_estimate_size_before_relax (fragP
, segment
)
7237 /* We've already got fragP->fr_subtype right; all we have to do is
7238 check for un-relaxable symbols. On an ELF system, we can't relax
7239 an externally visible symbol, because it may be overridden by a
7241 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
7242 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7244 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
7245 || S_IS_WEAK (fragP
->fr_symbol
)))
7249 /* Symbol is undefined in this segment, or we need to keep a
7250 reloc so that weak symbols can be overridden. */
7251 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
7252 enum bfd_reloc_code_real reloc_type
;
7253 unsigned char *opcode
;
7256 if (fragP
->fr_var
!= NO_RELOC
)
7257 reloc_type
= fragP
->fr_var
;
7259 reloc_type
= BFD_RELOC_16_PCREL
;
7261 reloc_type
= BFD_RELOC_32_PCREL
;
7263 old_fr_fix
= fragP
->fr_fix
;
7264 opcode
= (unsigned char *) fragP
->fr_opcode
;
7266 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
7269 /* Make jmp (0xeb) a (d)word displacement jump. */
7271 fragP
->fr_fix
+= size
;
7272 fix_new (fragP
, old_fr_fix
, size
,
7274 fragP
->fr_offset
, 1,
7280 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
7282 /* Negate the condition, and branch past an
7283 unconditional jump. */
7286 /* Insert an unconditional jump. */
7288 /* We added two extra opcode bytes, and have a two byte
7290 fragP
->fr_fix
+= 2 + 2;
7291 fix_new (fragP
, old_fr_fix
+ 2, 2,
7293 fragP
->fr_offset
, 1,
7300 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
7305 fixP
= fix_new (fragP
, old_fr_fix
, 1,
7307 fragP
->fr_offset
, 1,
7309 fixP
->fx_signed
= 1;
7313 /* This changes the byte-displacement jump 0x7N
7314 to the (d)word-displacement jump 0x0f,0x8N. */
7315 opcode
[1] = opcode
[0] + 0x10;
7316 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7317 /* We've added an opcode byte. */
7318 fragP
->fr_fix
+= 1 + size
;
7319 fix_new (fragP
, old_fr_fix
+ 1, size
,
7321 fragP
->fr_offset
, 1,
7326 BAD_CASE (fragP
->fr_subtype
);
7330 return fragP
->fr_fix
- old_fr_fix
;
7333 /* Guess size depending on current relax state. Initially the relax
7334 state will correspond to a short jump and we return 1, because
7335 the variable part of the frag (the branch offset) is one byte
7336 long. However, we can relax a section more than once and in that
7337 case we must either set fr_subtype back to the unrelaxed state,
7338 or return the value for the appropriate branch. */
7339 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
7342 /* Called after relax() is finished.
7344 In: Address of frag.
7345 fr_type == rs_machine_dependent.
7346 fr_subtype is what the address relaxed to.
7348 Out: Any fixSs and constants are set up.
7349 Caller will turn frag into a ".space 0". */
7352 md_convert_frag (abfd
, sec
, fragP
)
7353 bfd
*abfd ATTRIBUTE_UNUSED
;
7354 segT sec ATTRIBUTE_UNUSED
;
7357 unsigned char *opcode
;
7358 unsigned char *where_to_put_displacement
= NULL
;
7359 offsetT target_address
;
7360 offsetT opcode_address
;
7361 unsigned int extension
= 0;
7362 offsetT displacement_from_opcode_start
;
7364 opcode
= (unsigned char *) fragP
->fr_opcode
;
7366 /* Address we want to reach in file space. */
7367 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
7369 /* Address opcode resides at in file space. */
7370 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
7372 /* Displacement from opcode start to fill into instruction. */
7373 displacement_from_opcode_start
= target_address
- opcode_address
;
7375 if ((fragP
->fr_subtype
& BIG
) == 0)
7377 /* Don't have to change opcode. */
7378 extension
= 1; /* 1 opcode + 1 displacement */
7379 where_to_put_displacement
= &opcode
[1];
7383 if (no_cond_jump_promotion
7384 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
7385 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
7386 _("long jump required"));
7388 switch (fragP
->fr_subtype
)
7390 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
7391 extension
= 4; /* 1 opcode + 4 displacement */
7393 where_to_put_displacement
= &opcode
[1];
7396 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
7397 extension
= 2; /* 1 opcode + 2 displacement */
7399 where_to_put_displacement
= &opcode
[1];
7402 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
7403 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
7404 extension
= 5; /* 2 opcode + 4 displacement */
7405 opcode
[1] = opcode
[0] + 0x10;
7406 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7407 where_to_put_displacement
= &opcode
[2];
7410 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
7411 extension
= 3; /* 2 opcode + 2 displacement */
7412 opcode
[1] = opcode
[0] + 0x10;
7413 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7414 where_to_put_displacement
= &opcode
[2];
7417 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
7422 where_to_put_displacement
= &opcode
[3];
7426 BAD_CASE (fragP
->fr_subtype
);
7431 /* If size if less then four we are sure that the operand fits,
7432 but if it's 4, then it could be that the displacement is larger
7434 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
7436 && ((addressT
) (displacement_from_opcode_start
- extension
7437 + ((addressT
) 1 << 31))
7438 > (((addressT
) 2 << 31) - 1)))
7440 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
7441 _("jump target out of range"));
7442 /* Make us emit 0. */
7443 displacement_from_opcode_start
= extension
;
7445 /* Now put displacement after opcode. */
7446 md_number_to_chars ((char *) where_to_put_displacement
,
7447 (valueT
) (displacement_from_opcode_start
- extension
),
7448 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
7449 fragP
->fr_fix
+= extension
;
7452 /* Apply a fixup (fixS) to segment data, once it has been determined
7453 by our caller that we have all the info we need to fix it up.
7455 On the 386, immediates, displacements, and data pointers are all in
7456 the same (little-endian) format, so we don't need to care about which
7460 md_apply_fix (fixP
, valP
, seg
)
7461 /* The fix we're to put in. */
7463 /* Pointer to the value of the bits. */
7465 /* Segment fix is from. */
7466 segT seg ATTRIBUTE_UNUSED
;
7468 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
7469 valueT value
= *valP
;
7471 #if !defined (TE_Mach)
7474 switch (fixP
->fx_r_type
)
7480 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
7483 case BFD_RELOC_X86_64_32S
:
7484 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
7487 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
7490 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
7495 if (fixP
->fx_addsy
!= NULL
7496 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
7497 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
7498 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
7499 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
7500 && !use_rela_relocations
)
7502 /* This is a hack. There should be a better way to handle this.
7503 This covers for the fact that bfd_install_relocation will
7504 subtract the current location (for partial_inplace, PC relative
7505 relocations); see more below. */
7509 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
7512 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7514 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7517 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
7520 || (symbol_section_p (fixP
->fx_addsy
)
7521 && sym_seg
!= absolute_section
))
7522 && !generic_force_reloc (fixP
))
7524 /* Yes, we add the values in twice. This is because
7525 bfd_install_relocation subtracts them out again. I think
7526 bfd_install_relocation is broken, but I don't dare change
7528 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7532 #if defined (OBJ_COFF) && defined (TE_PE)
7533 /* For some reason, the PE format does not store a
7534 section address offset for a PC relative symbol. */
7535 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
7536 || S_IS_WEAK (fixP
->fx_addsy
))
7537 value
+= md_pcrel_from (fixP
);
7541 /* Fix a few things - the dynamic linker expects certain values here,
7542 and we must not disappoint it. */
7543 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7544 if (IS_ELF
&& fixP
->fx_addsy
)
7545 switch (fixP
->fx_r_type
)
7547 case BFD_RELOC_386_PLT32
:
7548 case BFD_RELOC_X86_64_PLT32
:
7549 /* Make the jump instruction point to the address of the operand. At
7550 runtime we merely add the offset to the actual PLT entry. */
7554 case BFD_RELOC_386_TLS_GD
:
7555 case BFD_RELOC_386_TLS_LDM
:
7556 case BFD_RELOC_386_TLS_IE_32
:
7557 case BFD_RELOC_386_TLS_IE
:
7558 case BFD_RELOC_386_TLS_GOTIE
:
7559 case BFD_RELOC_386_TLS_GOTDESC
:
7560 case BFD_RELOC_X86_64_TLSGD
:
7561 case BFD_RELOC_X86_64_TLSLD
:
7562 case BFD_RELOC_X86_64_GOTTPOFF
:
7563 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
7564 value
= 0; /* Fully resolved at runtime. No addend. */
7566 case BFD_RELOC_386_TLS_LE
:
7567 case BFD_RELOC_386_TLS_LDO_32
:
7568 case BFD_RELOC_386_TLS_LE_32
:
7569 case BFD_RELOC_X86_64_DTPOFF32
:
7570 case BFD_RELOC_X86_64_DTPOFF64
:
7571 case BFD_RELOC_X86_64_TPOFF32
:
7572 case BFD_RELOC_X86_64_TPOFF64
:
7573 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7576 case BFD_RELOC_386_TLS_DESC_CALL
:
7577 case BFD_RELOC_X86_64_TLSDESC_CALL
:
7578 value
= 0; /* Fully resolved at runtime. No addend. */
7579 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7583 case BFD_RELOC_386_GOT32
:
7584 case BFD_RELOC_X86_64_GOT32
:
7585 value
= 0; /* Fully resolved at runtime. No addend. */
7588 case BFD_RELOC_VTABLE_INHERIT
:
7589 case BFD_RELOC_VTABLE_ENTRY
:
7596 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
7598 #endif /* !defined (TE_Mach) */
7600 /* Are we finished with this relocation now? */
7601 if (fixP
->fx_addsy
== NULL
)
7603 else if (use_rela_relocations
)
7605 fixP
->fx_no_overflow
= 1;
7606 /* Remember value for tc_gen_reloc. */
7607 fixP
->fx_addnumber
= value
;
7611 md_number_to_chars (p
, value
, fixP
->fx_size
);
7615 md_atof (int type
, char *litP
, int *sizeP
)
7617 /* This outputs the LITTLENUMs in REVERSE order;
7618 in accord with the bigendian 386. */
7619 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
7622 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
7625 output_invalid (int c
)
7628 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
7631 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
7632 "(0x%x)", (unsigned char) c
);
7633 return output_invalid_buf
;
7636 /* REG_STRING starts *before* REGISTER_PREFIX. */
7638 static const reg_entry
*
7639 parse_real_register (char *reg_string
, char **end_op
)
7641 char *s
= reg_string
;
7643 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
7646 /* Skip possible REGISTER_PREFIX and possible whitespace. */
7647 if (*s
== REGISTER_PREFIX
)
7650 if (is_space_char (*s
))
7654 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
7656 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
7657 return (const reg_entry
*) NULL
;
7661 /* For naked regs, make sure that we are not dealing with an identifier.
7662 This prevents confusing an identifier like `eax_var' with register
7664 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
7665 return (const reg_entry
*) NULL
;
7669 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
7671 /* Handle floating point regs, allowing spaces in the (i) part. */
7672 if (r
== i386_regtab
/* %st is first entry of table */)
7674 if (is_space_char (*s
))
7679 if (is_space_char (*s
))
7681 if (*s
>= '0' && *s
<= '7')
7685 if (is_space_char (*s
))
7690 r
= hash_find (reg_hash
, "st(0)");
7695 /* We have "%st(" then garbage. */
7696 return (const reg_entry
*) NULL
;
7700 if (r
== NULL
|| allow_pseudo_reg
)
7703 if (operand_type_all_zero (&r
->reg_type
))
7704 return (const reg_entry
*) NULL
;
7706 if ((r
->reg_type
.bitfield
.reg32
7707 || r
->reg_type
.bitfield
.sreg3
7708 || r
->reg_type
.bitfield
.control
7709 || r
->reg_type
.bitfield
.debug
7710 || r
->reg_type
.bitfield
.test
)
7711 && !cpu_arch_flags
.bitfield
.cpui386
)
7712 return (const reg_entry
*) NULL
;
7714 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
7715 return (const reg_entry
*) NULL
;
7717 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpusse
)
7718 return (const reg_entry
*) NULL
;
7720 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuavx
)
7721 return (const reg_entry
*) NULL
;
7723 /* Don't allow fake index register unless allow_index_reg isn't 0. */
7724 if (!allow_index_reg
7725 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
7726 return (const reg_entry
*) NULL
;
7728 if (((r
->reg_flags
& (RegRex64
| RegRex
))
7729 || r
->reg_type
.bitfield
.reg64
)
7730 && (!cpu_arch_flags
.bitfield
.cpulm
7731 || !operand_type_equal (&r
->reg_type
, &control
))
7732 && flag_code
!= CODE_64BIT
)
7733 return (const reg_entry
*) NULL
;
7735 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
7736 return (const reg_entry
*) NULL
;
7741 /* REG_STRING starts *before* REGISTER_PREFIX. */
7743 static const reg_entry
*
7744 parse_register (char *reg_string
, char **end_op
)
7748 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
7749 r
= parse_real_register (reg_string
, end_op
);
7754 char *save
= input_line_pointer
;
7758 input_line_pointer
= reg_string
;
7759 c
= get_symbol_end ();
7760 symbolP
= symbol_find (reg_string
);
7761 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
7763 const expressionS
*e
= symbol_get_value_expression (symbolP
);
7765 know (e
->X_op
== O_register
);
7766 know (e
->X_add_number
>= 0
7767 && (valueT
) e
->X_add_number
< i386_regtab_size
);
7768 r
= i386_regtab
+ e
->X_add_number
;
7769 *end_op
= input_line_pointer
;
7771 *input_line_pointer
= c
;
7772 input_line_pointer
= save
;
7778 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
7781 char *end
= input_line_pointer
;
7784 r
= parse_register (name
, &input_line_pointer
);
7785 if (r
&& end
<= input_line_pointer
)
7787 *nextcharP
= *input_line_pointer
;
7788 *input_line_pointer
= 0;
7789 e
->X_op
= O_register
;
7790 e
->X_add_number
= r
- i386_regtab
;
7793 input_line_pointer
= end
;
7799 md_operand (expressionS
*e
)
7801 if (*input_line_pointer
== REGISTER_PREFIX
)
7804 const reg_entry
*r
= parse_real_register (input_line_pointer
, &end
);
7808 e
->X_op
= O_register
;
7809 e
->X_add_number
= r
- i386_regtab
;
7810 input_line_pointer
= end
;
7816 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7817 const char *md_shortopts
= "kVQ:sqn";
7819 const char *md_shortopts
= "qn";
7822 #define OPTION_32 (OPTION_MD_BASE + 0)
7823 #define OPTION_64 (OPTION_MD_BASE + 1)
7824 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
7825 #define OPTION_MARCH (OPTION_MD_BASE + 3)
7826 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
7827 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
7828 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
7829 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
7830 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
7831 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
7832 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
7833 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
7835 struct option md_longopts
[] =
7837 {"32", no_argument
, NULL
, OPTION_32
},
7838 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
7839 {"64", no_argument
, NULL
, OPTION_64
},
7841 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
7842 {"march", required_argument
, NULL
, OPTION_MARCH
},
7843 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
7844 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
7845 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
7846 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
7847 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
7848 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
7849 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
7850 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
7851 {NULL
, no_argument
, NULL
, 0}
7853 size_t md_longopts_size
= sizeof (md_longopts
);
7856 md_parse_option (int c
, char *arg
)
7864 optimize_align_code
= 0;
7871 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7872 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7873 should be emitted or not. FIXME: Not implemented. */
7877 /* -V: SVR4 argument to print version ID. */
7879 print_version_id ();
7882 /* -k: Ignore for FreeBSD compatibility. */
7887 /* -s: On i386 Solaris, this tells the native assembler to use
7888 .stab instead of .stab.excl. We always use .stab anyhow. */
7891 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
7894 const char **list
, **l
;
7896 list
= bfd_target_list ();
7897 for (l
= list
; *l
!= NULL
; l
++)
7898 if (CONST_STRNEQ (*l
, "elf64-x86-64")
7899 || strcmp (*l
, "coff-x86-64") == 0
7900 || strcmp (*l
, "pe-x86-64") == 0
7901 || strcmp (*l
, "pei-x86-64") == 0)
7903 default_arch
= "x86_64";
7907 as_fatal (_("No compiled in support for x86_64"));
7914 default_arch
= "i386";
7918 #ifdef SVR4_COMMENT_CHARS
7923 n
= (char *) xmalloc (strlen (i386_comment_chars
) + 1);
7925 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
7929 i386_comment_chars
= n
;
7935 arch
= xstrdup (arg
);
7939 as_fatal (_("Invalid -march= option: `%s'"), arg
);
7940 next
= strchr (arch
, '+');
7943 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
7945 if (strcmp (arch
, cpu_arch
[i
].name
) == 0)
7948 cpu_arch_name
= cpu_arch
[i
].name
;
7949 cpu_sub_arch_name
= NULL
;
7950 cpu_arch_flags
= cpu_arch
[i
].flags
;
7951 cpu_arch_isa
= cpu_arch
[i
].type
;
7952 cpu_arch_isa_flags
= cpu_arch
[i
].flags
;
7953 if (!cpu_arch_tune_set
)
7955 cpu_arch_tune
= cpu_arch_isa
;
7956 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
7960 else if (*cpu_arch
[i
].name
== '.'
7961 && strcmp (arch
, cpu_arch
[i
].name
+ 1) == 0)
7963 /* ISA entension. */
7964 i386_cpu_flags flags
;
7965 flags
= cpu_flags_or (cpu_arch_flags
,
7967 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
7969 if (cpu_sub_arch_name
)
7971 char *name
= cpu_sub_arch_name
;
7972 cpu_sub_arch_name
= concat (name
,
7974 (const char *) NULL
);
7978 cpu_sub_arch_name
= xstrdup (cpu_arch
[i
].name
);
7979 cpu_arch_flags
= flags
;
7985 if (i
>= ARRAY_SIZE (cpu_arch
))
7986 as_fatal (_("Invalid -march= option: `%s'"), arg
);
7990 while (next
!= NULL
);
7995 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
7996 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
7998 if (strcmp (arg
, cpu_arch
[i
].name
) == 0)
8000 cpu_arch_tune_set
= 1;
8001 cpu_arch_tune
= cpu_arch
[i
].type
;
8002 cpu_arch_tune_flags
= cpu_arch
[i
].flags
;
8006 if (i
>= ARRAY_SIZE (cpu_arch
))
8007 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
8010 case OPTION_MMNEMONIC
:
8011 if (strcasecmp (arg
, "att") == 0)
8013 else if (strcasecmp (arg
, "intel") == 0)
8016 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg
);
8019 case OPTION_MSYNTAX
:
8020 if (strcasecmp (arg
, "att") == 0)
8022 else if (strcasecmp (arg
, "intel") == 0)
8025 as_fatal (_("Invalid -msyntax= option: `%s'"), arg
);
8028 case OPTION_MINDEX_REG
:
8029 allow_index_reg
= 1;
8032 case OPTION_MNAKED_REG
:
8033 allow_naked_reg
= 1;
8036 case OPTION_MOLD_GCC
:
8040 case OPTION_MSSE2AVX
:
8044 case OPTION_MSSE_CHECK
:
8045 if (strcasecmp (arg
, "error") == 0)
8046 sse_check
= sse_check_error
;
8047 else if (strcasecmp (arg
, "warning") == 0)
8048 sse_check
= sse_check_warning
;
8049 else if (strcasecmp (arg
, "none") == 0)
8050 sse_check
= sse_check_none
;
8052 as_fatal (_("Invalid -msse-check= option: `%s'"), arg
);
8062 md_show_usage (stream
)
8065 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8066 fprintf (stream
, _("\
8068 -V print assembler version number\n\
8071 fprintf (stream
, _("\
8072 -n Do not optimize code alignment\n\
8073 -q quieten some warnings\n"));
8074 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8075 fprintf (stream
, _("\
8078 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
8079 fprintf (stream
, _("\
8080 --32/--64 generate 32bit/64bit code\n"));
8082 #ifdef SVR4_COMMENT_CHARS
8083 fprintf (stream
, _("\
8084 --divide do not treat `/' as a comment character\n"));
8086 fprintf (stream
, _("\
8087 --divide ignored\n"));
8089 fprintf (stream
, _("\
8090 -march=CPU[,+EXTENSION...]\n\
8091 generate code for CPU and EXTENSION, CPU is one of:\n\
8092 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
8093 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
8094 core, core2, k6, k6_2, athlon, k8, amdfam10,\n\
8095 generic32, generic64\n\
8096 EXTENSION is combination of:\n\
8097 mmx, sse, sse2, sse3, ssse3, sse4.1, sse4.2, sse4,\n\
8098 avx, vmx, smx, xsave, aes, pclmul, fma, 3dnow,\n\
8099 3dnowa, sse4a, sse5, svme, abm, padlock\n"));
8100 fprintf (stream
, _("\
8101 -mtune=CPU optimize for CPU, CPU is one of:\n\
8102 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
8103 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
8104 core, core2, k6, k6_2, athlon, k8, amdfam10,\n\
8105 generic32, generic64\n"));
8106 fprintf (stream
, _("\
8107 -msse2avx encode SSE instructions with VEX prefix\n"));
8108 fprintf (stream
, _("\
8109 -msse-check=[none|error|warning]\n\
8110 check SSE instructions\n"));
8111 fprintf (stream
, _("\
8112 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
8113 fprintf (stream
, _("\
8114 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
8115 fprintf (stream
, _("\
8116 -mindex-reg support pseudo index registers\n"));
8117 fprintf (stream
, _("\
8118 -mnaked-reg don't require `%%' prefix for registers\n"));
8119 fprintf (stream
, _("\
8120 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
8123 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
8124 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (TE_PEP))
8126 /* Pick the target format to use. */
8129 i386_target_format (void)
8131 if (!strcmp (default_arch
, "x86_64"))
8133 set_code_flag (CODE_64BIT
);
8134 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
8136 cpu_arch_isa_flags
.bitfield
.cpui186
= 1;
8137 cpu_arch_isa_flags
.bitfield
.cpui286
= 1;
8138 cpu_arch_isa_flags
.bitfield
.cpui386
= 1;
8139 cpu_arch_isa_flags
.bitfield
.cpui486
= 1;
8140 cpu_arch_isa_flags
.bitfield
.cpui586
= 1;
8141 cpu_arch_isa_flags
.bitfield
.cpui686
= 1;
8142 cpu_arch_isa_flags
.bitfield
.cpup4
= 1;
8143 cpu_arch_isa_flags
.bitfield
.cpummx
= 1;
8144 cpu_arch_isa_flags
.bitfield
.cpusse
= 1;
8145 cpu_arch_isa_flags
.bitfield
.cpusse2
= 1;
8147 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
8149 cpu_arch_tune_flags
.bitfield
.cpui186
= 1;
8150 cpu_arch_tune_flags
.bitfield
.cpui286
= 1;
8151 cpu_arch_tune_flags
.bitfield
.cpui386
= 1;
8152 cpu_arch_tune_flags
.bitfield
.cpui486
= 1;
8153 cpu_arch_tune_flags
.bitfield
.cpui586
= 1;
8154 cpu_arch_tune_flags
.bitfield
.cpui686
= 1;
8155 cpu_arch_tune_flags
.bitfield
.cpup4
= 1;
8156 cpu_arch_tune_flags
.bitfield
.cpummx
= 1;
8157 cpu_arch_tune_flags
.bitfield
.cpusse
= 1;
8158 cpu_arch_tune_flags
.bitfield
.cpusse2
= 1;
8161 else if (!strcmp (default_arch
, "i386"))
8163 set_code_flag (CODE_32BIT
);
8164 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
8166 cpu_arch_isa_flags
.bitfield
.cpui186
= 1;
8167 cpu_arch_isa_flags
.bitfield
.cpui286
= 1;
8168 cpu_arch_isa_flags
.bitfield
.cpui386
= 1;
8170 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
8172 cpu_arch_tune_flags
.bitfield
.cpui186
= 1;
8173 cpu_arch_tune_flags
.bitfield
.cpui286
= 1;
8174 cpu_arch_tune_flags
.bitfield
.cpui386
= 1;
8178 as_fatal (_("Unknown architecture"));
8179 switch (OUTPUT_FLAVOR
)
8182 case bfd_target_coff_flavour
:
8183 return flag_code
== CODE_64BIT
? COFF_TARGET_FORMAT
: "coff-i386";
8186 #ifdef OBJ_MAYBE_AOUT
8187 case bfd_target_aout_flavour
:
8188 return AOUT_TARGET_FORMAT
;
8190 #ifdef OBJ_MAYBE_COFF
8191 case bfd_target_coff_flavour
:
8194 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8195 case bfd_target_elf_flavour
:
8197 if (flag_code
== CODE_64BIT
)
8200 use_rela_relocations
= 1;
8202 return flag_code
== CODE_64BIT
? ELF_TARGET_FORMAT64
: ELF_TARGET_FORMAT
;
8211 #endif /* OBJ_MAYBE_ more than one */
8213 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
8215 i386_elf_emit_arch_note (void)
8217 if (IS_ELF
&& cpu_arch_name
!= NULL
)
8220 asection
*seg
= now_seg
;
8221 subsegT subseg
= now_subseg
;
8222 Elf_Internal_Note i_note
;
8223 Elf_External_Note e_note
;
8224 asection
*note_secp
;
8227 /* Create the .note section. */
8228 note_secp
= subseg_new (".note", 0);
8229 bfd_set_section_flags (stdoutput
,
8231 SEC_HAS_CONTENTS
| SEC_READONLY
);
8233 /* Process the arch string. */
8234 len
= strlen (cpu_arch_name
);
8236 i_note
.namesz
= len
+ 1;
8238 i_note
.type
= NT_ARCH
;
8239 p
= frag_more (sizeof (e_note
.namesz
));
8240 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
8241 p
= frag_more (sizeof (e_note
.descsz
));
8242 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
8243 p
= frag_more (sizeof (e_note
.type
));
8244 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
8245 p
= frag_more (len
+ 1);
8246 strcpy (p
, cpu_arch_name
);
8248 frag_align (2, 0, 0);
8250 subseg_set (seg
, subseg
);
8256 md_undefined_symbol (name
)
8259 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
8260 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
8261 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
8262 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
8266 if (symbol_find (name
))
8267 as_bad (_("GOT already in symbol table"));
8268 GOT_symbol
= symbol_new (name
, undefined_section
,
8269 (valueT
) 0, &zero_address_frag
);
8276 /* Round up a section size to the appropriate boundary. */
8279 md_section_align (segment
, size
)
8280 segT segment ATTRIBUTE_UNUSED
;
8283 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8284 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
8286 /* For a.out, force the section size to be aligned. If we don't do
8287 this, BFD will align it for us, but it will not write out the
8288 final bytes of the section. This may be a bug in BFD, but it is
8289 easier to fix it here since that is how the other a.out targets
8293 align
= bfd_get_section_alignment (stdoutput
, segment
);
8294 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
8301 /* On the i386, PC-relative offsets are relative to the start of the
8302 next instruction. That is, the address of the offset, plus its
8303 size, since the offset is always the last part of the insn. */
8306 md_pcrel_from (fixS
*fixP
)
8308 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
8314 s_bss (int ignore ATTRIBUTE_UNUSED
)
8318 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8320 obj_elf_section_change_hook ();
8322 temp
= get_absolute_expression ();
8323 subseg_set (bss_section
, (subsegT
) temp
);
8324 demand_empty_rest_of_line ();
8330 i386_validate_fix (fixS
*fixp
)
8332 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
8334 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
8338 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
8343 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
8345 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
8352 tc_gen_reloc (section
, fixp
)
8353 asection
*section ATTRIBUTE_UNUSED
;
8357 bfd_reloc_code_real_type code
;
8359 switch (fixp
->fx_r_type
)
8361 case BFD_RELOC_X86_64_PLT32
:
8362 case BFD_RELOC_X86_64_GOT32
:
8363 case BFD_RELOC_X86_64_GOTPCREL
:
8364 case BFD_RELOC_386_PLT32
:
8365 case BFD_RELOC_386_GOT32
:
8366 case BFD_RELOC_386_GOTOFF
:
8367 case BFD_RELOC_386_GOTPC
:
8368 case BFD_RELOC_386_TLS_GD
:
8369 case BFD_RELOC_386_TLS_LDM
:
8370 case BFD_RELOC_386_TLS_LDO_32
:
8371 case BFD_RELOC_386_TLS_IE_32
:
8372 case BFD_RELOC_386_TLS_IE
:
8373 case BFD_RELOC_386_TLS_GOTIE
:
8374 case BFD_RELOC_386_TLS_LE_32
:
8375 case BFD_RELOC_386_TLS_LE
:
8376 case BFD_RELOC_386_TLS_GOTDESC
:
8377 case BFD_RELOC_386_TLS_DESC_CALL
:
8378 case BFD_RELOC_X86_64_TLSGD
:
8379 case BFD_RELOC_X86_64_TLSLD
:
8380 case BFD_RELOC_X86_64_DTPOFF32
:
8381 case BFD_RELOC_X86_64_DTPOFF64
:
8382 case BFD_RELOC_X86_64_GOTTPOFF
:
8383 case BFD_RELOC_X86_64_TPOFF32
:
8384 case BFD_RELOC_X86_64_TPOFF64
:
8385 case BFD_RELOC_X86_64_GOTOFF64
:
8386 case BFD_RELOC_X86_64_GOTPC32
:
8387 case BFD_RELOC_X86_64_GOT64
:
8388 case BFD_RELOC_X86_64_GOTPCREL64
:
8389 case BFD_RELOC_X86_64_GOTPC64
:
8390 case BFD_RELOC_X86_64_GOTPLT64
:
8391 case BFD_RELOC_X86_64_PLTOFF64
:
8392 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
8393 case BFD_RELOC_X86_64_TLSDESC_CALL
:
8395 case BFD_RELOC_VTABLE_ENTRY
:
8396 case BFD_RELOC_VTABLE_INHERIT
:
8398 case BFD_RELOC_32_SECREL
:
8400 code
= fixp
->fx_r_type
;
8402 case BFD_RELOC_X86_64_32S
:
8403 if (!fixp
->fx_pcrel
)
8405 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
8406 code
= fixp
->fx_r_type
;
8412 switch (fixp
->fx_size
)
8415 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8416 _("can not do %d byte pc-relative relocation"),
8418 code
= BFD_RELOC_32_PCREL
;
8420 case 1: code
= BFD_RELOC_8_PCREL
; break;
8421 case 2: code
= BFD_RELOC_16_PCREL
; break;
8422 case 4: code
= BFD_RELOC_32_PCREL
; break;
8424 case 8: code
= BFD_RELOC_64_PCREL
; break;
8430 switch (fixp
->fx_size
)
8433 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8434 _("can not do %d byte relocation"),
8436 code
= BFD_RELOC_32
;
8438 case 1: code
= BFD_RELOC_8
; break;
8439 case 2: code
= BFD_RELOC_16
; break;
8440 case 4: code
= BFD_RELOC_32
; break;
8442 case 8: code
= BFD_RELOC_64
; break;
8449 if ((code
== BFD_RELOC_32
8450 || code
== BFD_RELOC_32_PCREL
8451 || code
== BFD_RELOC_X86_64_32S
)
8453 && fixp
->fx_addsy
== GOT_symbol
)
8456 code
= BFD_RELOC_386_GOTPC
;
8458 code
= BFD_RELOC_X86_64_GOTPC32
;
8460 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
8462 && fixp
->fx_addsy
== GOT_symbol
)
8464 code
= BFD_RELOC_X86_64_GOTPC64
;
8467 rel
= (arelent
*) xmalloc (sizeof (arelent
));
8468 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
8469 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
8471 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
8473 if (!use_rela_relocations
)
8475 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
8476 vtable entry to be used in the relocation's section offset. */
8477 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
8478 rel
->address
= fixp
->fx_offset
;
8482 /* Use the rela in 64bit mode. */
8485 if (!fixp
->fx_pcrel
)
8486 rel
->addend
= fixp
->fx_offset
;
8490 case BFD_RELOC_X86_64_PLT32
:
8491 case BFD_RELOC_X86_64_GOT32
:
8492 case BFD_RELOC_X86_64_GOTPCREL
:
8493 case BFD_RELOC_X86_64_TLSGD
:
8494 case BFD_RELOC_X86_64_TLSLD
:
8495 case BFD_RELOC_X86_64_GOTTPOFF
:
8496 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
8497 case BFD_RELOC_X86_64_TLSDESC_CALL
:
8498 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
8501 rel
->addend
= (section
->vma
8503 + fixp
->fx_addnumber
8504 + md_pcrel_from (fixp
));
8509 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
8510 if (rel
->howto
== NULL
)
8512 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8513 _("cannot represent relocation type %s"),
8514 bfd_get_reloc_code_name (code
));
8515 /* Set howto to a garbage value so that we can keep going. */
8516 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
8517 assert (rel
->howto
!= NULL
);
8524 /* Parse operands using Intel syntax. This implements a recursive descent
8525 parser based on the BNF grammar published in Appendix B of the MASM 6.1
8528 FIXME: We do not recognize the full operand grammar defined in the MASM
8529 documentation. In particular, all the structure/union and
8530 high-level macro operands are missing.
8532 Uppercase words are terminals, lower case words are non-terminals.
8533 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
8534 bars '|' denote choices. Most grammar productions are implemented in
8535 functions called 'intel_<production>'.
8537 Initial production is 'expr'.
8543 binOp & | AND | \| | OR | ^ | XOR
8545 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
8547 constant digits [[ radixOverride ]]
8549 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD | YMMWORD
8587 => expr expr cmpOp e04
8590 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
8591 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
8593 hexdigit a | b | c | d | e | f
8594 | A | B | C | D | E | F
8600 mulOp * | / | % | MOD | << | SHL | >> | SHR
8604 register specialRegister
8608 segmentRegister CS | DS | ES | FS | GS | SS
8610 specialRegister CR0 | CR2 | CR3 | CR4
8611 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
8612 | TR3 | TR4 | TR5 | TR6 | TR7
8614 We simplify the grammar in obvious places (e.g., register parsing is
8615 done by calling parse_register) and eliminate immediate left recursion
8616 to implement a recursive-descent parser.
8620 expr' cmpOp e04 expr'
8672 /* Parsing structure for the intel syntax parser. Used to implement the
8673 semantic actions for the operand grammar. */
8674 struct intel_parser_s
8676 char *op_string
; /* The string being parsed. */
8677 int got_a_float
; /* Whether the operand is a float. */
8678 int op_modifier
; /* Operand modifier. */
8679 int is_mem
; /* 1 if operand is memory reference. */
8680 int in_offset
; /* >=1 if parsing operand of offset. */
8681 int in_bracket
; /* >=1 if parsing operand in brackets. */
8682 const reg_entry
*reg
; /* Last register reference found. */
8683 char *disp
; /* Displacement string being built. */
8684 char *next_operand
; /* Resume point when splitting operands. */
8687 static struct intel_parser_s intel_parser
;
8689 /* Token structure for parsing intel syntax. */
8692 int code
; /* Token code. */
8693 const reg_entry
*reg
; /* Register entry for register tokens. */
8694 char *str
; /* String representation. */
8697 static struct intel_token cur_token
, prev_token
;
8699 /* Token codes for the intel parser. Since T_SHORT is already used
8700 by COFF, undefine it first to prevent a warning. */
8718 #define T_YMMWORD 16
8720 /* Prototypes for intel parser functions. */
8721 static int intel_match_token (int);
8722 static void intel_putback_token (void);
8723 static void intel_get_token (void);
8724 static int intel_expr (void);
8725 static int intel_e04 (void);
8726 static int intel_e05 (void);
8727 static int intel_e06 (void);
8728 static int intel_e09 (void);
8729 static int intel_e10 (void);
8730 static int intel_e11 (void);
8733 i386_intel_operand (char *operand_string
, int got_a_float
)
8738 p
= intel_parser
.op_string
= xstrdup (operand_string
);
8739 intel_parser
.disp
= (char *) xmalloc (strlen (operand_string
) + 1);
8743 /* Initialize token holders. */
8744 cur_token
.code
= prev_token
.code
= T_NIL
;
8745 cur_token
.reg
= prev_token
.reg
= NULL
;
8746 cur_token
.str
= prev_token
.str
= NULL
;
8748 /* Initialize parser structure. */
8749 intel_parser
.got_a_float
= got_a_float
;
8750 intel_parser
.op_modifier
= 0;
8751 intel_parser
.is_mem
= 0;
8752 intel_parser
.in_offset
= 0;
8753 intel_parser
.in_bracket
= 0;
8754 intel_parser
.reg
= NULL
;
8755 intel_parser
.disp
[0] = '\0';
8756 intel_parser
.next_operand
= NULL
;
8758 /* Read the first token and start the parser. */
8760 ret
= intel_expr ();
8765 if (cur_token
.code
!= T_NIL
)
8767 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
8768 current_templates
->start
->name
, cur_token
.str
);
8771 /* If we found a memory reference, hand it over to i386_displacement
8772 to fill in the rest of the operand fields. */
8773 else if (intel_parser
.is_mem
)
8775 if ((i
.mem_operands
== 1
8776 && !current_templates
->start
->opcode_modifier
.isstring
)
8777 || i
.mem_operands
== 2)
8779 as_bad (_("too many memory references for '%s'"),
8780 current_templates
->start
->name
);
8785 char *s
= intel_parser
.disp
;
8786 i
.types
[this_operand
].bitfield
.mem
= 1;
8789 if (!quiet_warnings
&& intel_parser
.is_mem
< 0)
8790 /* See the comments in intel_bracket_expr. */
8791 as_warn (_("Treating `%s' as memory reference"), operand_string
);
8793 /* Add the displacement expression. */
8795 ret
= i386_displacement (s
, s
+ strlen (s
));
8798 /* Swap base and index in 16-bit memory operands like
8799 [si+bx]. Since i386_index_check is also used in AT&T
8800 mode we have to do that here. */
8803 && i
.base_reg
->reg_type
.bitfield
.reg16
8804 && i
.index_reg
->reg_type
.bitfield
.reg16
8805 && i
.base_reg
->reg_num
>= 6
8806 && i
.index_reg
->reg_num
< 6)
8808 const reg_entry
*base
= i
.index_reg
;
8810 i
.index_reg
= i
.base_reg
;
8813 ret
= i386_index_check (operand_string
);
8818 /* Constant and OFFSET expressions are handled by i386_immediate. */
8819 else if ((intel_parser
.op_modifier
& (1 << T_OFFSET
))
8820 || intel_parser
.reg
== NULL
)
8822 if (i
.mem_operands
< 2 && i
.seg
[i
.mem_operands
])
8824 if (!(intel_parser
.op_modifier
& (1 << T_OFFSET
)))
8825 as_warn (_("Segment override ignored"));
8826 i
.seg
[i
.mem_operands
] = NULL
;
8828 ret
= i386_immediate (intel_parser
.disp
);
8831 if (intel_parser
.next_operand
&& this_operand
>= MAX_OPERANDS
- 1)
8833 if (!ret
|| !intel_parser
.next_operand
)
8835 intel_parser
.op_string
= intel_parser
.next_operand
;
8836 this_operand
= i
.operands
++;
8837 i
.types
[this_operand
].bitfield
.unspecified
= 1;
8841 free (intel_parser
.disp
);
8846 #define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
8850 expr' cmpOp e04 expr'
8855 /* XXX Implement the comparison operators. */
8856 return intel_e04 ();
8873 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
8874 i
.base_reg
= i386_regtab
+ REGNAM_AL
; /* al is invalid as base */
8876 if (cur_token
.code
== '+')
8878 else if (cur_token
.code
== '-')
8879 nregs
= NUM_ADDRESS_REGS
;
8883 strcat (intel_parser
.disp
, cur_token
.str
);
8884 intel_match_token (cur_token
.code
);
8895 int nregs
= ~NUM_ADDRESS_REGS
;
8902 if (cur_token
.code
== '&'
8903 || cur_token
.code
== '|'
8904 || cur_token
.code
== '^')
8908 str
[0] = cur_token
.code
;
8910 strcat (intel_parser
.disp
, str
);
8915 intel_match_token (cur_token
.code
);
8920 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
8921 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 1; /* cl is invalid as base */
8932 int nregs
= ~NUM_ADDRESS_REGS
;
8939 if (cur_token
.code
== '*'
8940 || cur_token
.code
== '/'
8941 || cur_token
.code
== '%')
8945 str
[0] = cur_token
.code
;
8947 strcat (intel_parser
.disp
, str
);
8949 else if (cur_token
.code
== T_SHL
)
8950 strcat (intel_parser
.disp
, "<<");
8951 else if (cur_token
.code
== T_SHR
)
8952 strcat (intel_parser
.disp
, ">>");
8956 intel_match_token (cur_token
.code
);
8961 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
8962 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 2; /* dl is invalid as base */
8980 int nregs
= ~NUM_ADDRESS_REGS
;
8985 /* Don't consume constants here. */
8986 if (cur_token
.code
== '+' || cur_token
.code
== '-')
8988 /* Need to look one token ahead - if the next token
8989 is a constant, the current token is its sign. */
8992 intel_match_token (cur_token
.code
);
8993 next_code
= cur_token
.code
;
8994 intel_putback_token ();
8995 if (next_code
== T_CONST
)
8999 /* e09 OFFSET e09 */
9000 if (cur_token
.code
== T_OFFSET
)
9003 ++intel_parser
.in_offset
;
9007 else if (cur_token
.code
== T_SHORT
)
9008 intel_parser
.op_modifier
|= 1 << T_SHORT
;
9011 else if (cur_token
.code
== '+')
9012 strcat (intel_parser
.disp
, "+");
9017 else if (cur_token
.code
== '-' || cur_token
.code
== '~')
9023 str
[0] = cur_token
.code
;
9025 strcat (intel_parser
.disp
, str
);
9032 intel_match_token (cur_token
.code
);
9040 /* e09' PTR e10 e09' */
9041 if (cur_token
.code
== T_PTR
)
9045 if (prev_token
.code
== T_BYTE
)
9047 suffix
= BYTE_MNEM_SUFFIX
;
9048 i
.types
[this_operand
].bitfield
.byte
= 1;
9051 else if (prev_token
.code
== T_WORD
)
9053 if ((current_templates
->start
->name
[0] == 'l'
9054 && current_templates
->start
->name
[2] == 's'
9055 && current_templates
->start
->name
[3] == 0)
9056 || current_templates
->start
->base_opcode
== 0x62 /* bound */)
9057 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
9058 else if (intel_parser
.got_a_float
== 2) /* "fi..." */
9059 suffix
= SHORT_MNEM_SUFFIX
;
9061 suffix
= WORD_MNEM_SUFFIX
;
9062 i
.types
[this_operand
].bitfield
.word
= 1;
9065 else if (prev_token
.code
== T_DWORD
)
9067 if ((current_templates
->start
->name
[0] == 'l'
9068 && current_templates
->start
->name
[2] == 's'
9069 && current_templates
->start
->name
[3] == 0)
9070 || current_templates
->start
->base_opcode
== 0x62 /* bound */)
9071 suffix
= WORD_MNEM_SUFFIX
;
9072 else if (flag_code
== CODE_16BIT
9073 && (current_templates
->start
->opcode_modifier
.jump
9074 || current_templates
->start
->opcode_modifier
.jumpdword
))
9075 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
9076 else if (intel_parser
.got_a_float
== 1) /* "f..." */
9077 suffix
= SHORT_MNEM_SUFFIX
;
9079 suffix
= LONG_MNEM_SUFFIX
;
9080 i
.types
[this_operand
].bitfield
.dword
= 1;
9083 else if (prev_token
.code
== T_FWORD
)
9085 if (current_templates
->start
->name
[0] == 'l'
9086 && current_templates
->start
->name
[2] == 's'
9087 && current_templates
->start
->name
[3] == 0)
9088 suffix
= LONG_MNEM_SUFFIX
;
9089 else if (!intel_parser
.got_a_float
)
9091 if (flag_code
== CODE_16BIT
)
9092 add_prefix (DATA_PREFIX_OPCODE
);
9093 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
9096 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
9097 i
.types
[this_operand
].bitfield
.fword
= 1;
9100 else if (prev_token
.code
== T_QWORD
)
9102 if (current_templates
->start
->base_opcode
== 0x62 /* bound */
9103 || intel_parser
.got_a_float
== 1) /* "f..." */
9104 suffix
= LONG_MNEM_SUFFIX
;
9106 suffix
= QWORD_MNEM_SUFFIX
;
9107 i
.types
[this_operand
].bitfield
.qword
= 1;
9110 else if (prev_token
.code
== T_TBYTE
)
9112 if (intel_parser
.got_a_float
== 1)
9113 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
9115 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
9118 else if (prev_token
.code
== T_XMMWORD
)
9120 suffix
= XMMWORD_MNEM_SUFFIX
;
9121 i
.types
[this_operand
].bitfield
.xmmword
= 1;
9124 else if (prev_token
.code
== T_YMMWORD
)
9126 suffix
= YMMWORD_MNEM_SUFFIX
;
9127 i
.types
[this_operand
].bitfield
.ymmword
= 1;
9132 as_bad (_("Unknown operand modifier `%s'"), prev_token
.str
);
9136 i
.types
[this_operand
].bitfield
.unspecified
= 0;
9138 /* Operands for jump/call using 'ptr' notation denote absolute
9140 if (current_templates
->start
->opcode_modifier
.jump
9141 || current_templates
->start
->opcode_modifier
.jumpdword
)
9142 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
9144 if (current_templates
->start
->base_opcode
== 0x8d /* lea */)
9148 else if (i
.suffix
!= suffix
)
9150 as_bad (_("Conflicting operand modifiers"));
9156 /* e09' : e10 e09' */
9157 else if (cur_token
.code
== ':')
9159 if (prev_token
.code
!= T_REG
)
9161 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
9162 segment/group identifier (which we don't have), using comma
9163 as the operand separator there is even less consistent, since
9164 there all branches only have a single operand. */
9165 if (this_operand
!= 0
9166 || intel_parser
.in_offset
9167 || intel_parser
.in_bracket
9168 || (!current_templates
->start
->opcode_modifier
.jump
9169 && !current_templates
->start
->opcode_modifier
.jumpdword
9170 && !current_templates
->start
->opcode_modifier
.jumpintersegment
9171 && !current_templates
->start
->operand_types
[0].bitfield
.jumpabsolute
))
9172 return intel_match_token (T_NIL
);
9173 /* Remember the start of the 2nd operand and terminate 1st
9175 XXX This isn't right, yet (when SSSS:OOOO is right operand of
9176 another expression), but it gets at least the simplest case
9177 (a plain number or symbol on the left side) right. */
9178 intel_parser
.next_operand
= intel_parser
.op_string
;
9179 *--intel_parser
.op_string
= '\0';
9180 return intel_match_token (':');
9188 intel_match_token (cur_token
.code
);
9194 --intel_parser
.in_offset
;
9197 if (NUM_ADDRESS_REGS
> nregs
)
9199 as_bad (_("Invalid operand to `OFFSET'"));
9202 intel_parser
.op_modifier
|= 1 << T_OFFSET
;
9205 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
9206 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 3; /* bl is invalid as base */
9211 intel_bracket_expr (void)
9213 int was_offset
= intel_parser
.op_modifier
& (1 << T_OFFSET
);
9214 const char *start
= intel_parser
.op_string
;
9217 if (i
.op
[this_operand
].regs
)
9218 return intel_match_token (T_NIL
);
9220 intel_match_token ('[');
9222 /* Mark as a memory operand only if it's not already known to be an
9223 offset expression. If it's an offset expression, we need to keep
9225 if (!intel_parser
.in_offset
)
9227 ++intel_parser
.in_bracket
;
9229 /* Operands for jump/call inside brackets denote absolute addresses. */
9230 if (current_templates
->start
->opcode_modifier
.jump
9231 || current_templates
->start
->opcode_modifier
.jumpdword
)
9232 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
9234 /* Unfortunately gas always diverged from MASM in a respect that can't
9235 be easily fixed without risking to break code sequences likely to be
9236 encountered (the testsuite even check for this): MASM doesn't consider
9237 an expression inside brackets unconditionally as a memory reference.
9238 When that is e.g. a constant, an offset expression, or the sum of the
9239 two, this is still taken as a constant load. gas, however, always
9240 treated these as memory references. As a compromise, we'll try to make
9241 offset expressions inside brackets work the MASM way (since that's
9242 less likely to be found in real world code), but make constants alone
9243 continue to work the traditional gas way. In either case, issue a
9245 intel_parser
.op_modifier
&= ~was_offset
;
9248 strcat (intel_parser
.disp
, "[");
9250 /* Add a '+' to the displacement string if necessary. */
9251 if (*intel_parser
.disp
!= '\0'
9252 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
9253 strcat (intel_parser
.disp
, "+");
9256 && (len
= intel_parser
.op_string
- start
- 1,
9257 intel_match_token (']')))
9259 /* Preserve brackets when the operand is an offset expression. */
9260 if (intel_parser
.in_offset
)
9261 strcat (intel_parser
.disp
, "]");
9264 --intel_parser
.in_bracket
;
9265 if (i
.base_reg
|| i
.index_reg
)
9266 intel_parser
.is_mem
= 1;
9267 if (!intel_parser
.is_mem
)
9269 if (!(intel_parser
.op_modifier
& (1 << T_OFFSET
)))
9270 /* Defer the warning until all of the operand was parsed. */
9271 intel_parser
.is_mem
= -1;
9272 else if (!quiet_warnings
)
9273 as_warn (_("`[%.*s]' taken to mean just `%.*s'"),
9274 len
, start
, len
, start
);
9277 intel_parser
.op_modifier
|= was_offset
;
9294 while (cur_token
.code
== '[')
9296 if (!intel_bracket_expr ())
9322 switch (cur_token
.code
)
9326 intel_match_token ('(');
9327 strcat (intel_parser
.disp
, "(");
9329 if (intel_expr () && intel_match_token (')'))
9331 strcat (intel_parser
.disp
, ")");
9338 return intel_bracket_expr ();
9343 strcat (intel_parser
.disp
, cur_token
.str
);
9344 intel_match_token (cur_token
.code
);
9346 /* Mark as a memory operand only if it's not already known to be an
9347 offset expression. */
9348 if (!intel_parser
.in_offset
)
9349 intel_parser
.is_mem
= 1;
9356 const reg_entry
*reg
= intel_parser
.reg
= cur_token
.reg
;
9358 intel_match_token (T_REG
);
9360 /* Check for segment change. */
9361 if (cur_token
.code
== ':')
9363 if (!reg
->reg_type
.bitfield
.sreg2
9364 && !reg
->reg_type
.bitfield
.sreg3
)
9366 as_bad (_("`%s' is not a valid segment register"),
9370 else if (i
.mem_operands
>= 2)
9371 as_warn (_("Segment override ignored"));
9372 else if (i
.seg
[i
.mem_operands
])
9373 as_warn (_("Extra segment override ignored"));
9376 if (!intel_parser
.in_offset
)
9377 intel_parser
.is_mem
= 1;
9378 switch (reg
->reg_num
)
9381 i
.seg
[i
.mem_operands
] = &es
;
9384 i
.seg
[i
.mem_operands
] = &cs
;
9387 i
.seg
[i
.mem_operands
] = &ss
;
9390 i
.seg
[i
.mem_operands
] = &ds
;
9393 i
.seg
[i
.mem_operands
] = &fs
;
9396 i
.seg
[i
.mem_operands
] = &gs
;
9402 else if (reg
->reg_type
.bitfield
.sreg3
&& reg
->reg_num
== RegFlat
)
9404 as_bad (_("cannot use `FLAT' here"));
9408 /* Not a segment register. Check for register scaling. */
9409 else if (cur_token
.code
== '*')
9411 if (!intel_parser
.in_bracket
)
9413 as_bad (_("Register scaling only allowed in memory operands"));
9417 if (reg
->reg_type
.bitfield
.reg16
) /* Disallow things like [si*1]. */
9418 reg
= i386_regtab
+ REGNAM_AX
+ 4; /* sp is invalid as index */
9419 else if (i
.index_reg
)
9420 reg
= i386_regtab
+ REGNAM_EAX
+ 4; /* esp is invalid as index */
9422 /* What follows must be a valid scale. */
9423 intel_match_token ('*');
9425 i
.types
[this_operand
].bitfield
.baseindex
= 1;
9427 /* Set the scale after setting the register (otherwise,
9428 i386_scale will complain) */
9429 if (cur_token
.code
== '+' || cur_token
.code
== '-')
9431 char *str
, sign
= cur_token
.code
;
9432 intel_match_token (cur_token
.code
);
9433 if (cur_token
.code
!= T_CONST
)
9435 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
9439 str
= (char *) xmalloc (strlen (cur_token
.str
) + 2);
9440 strcpy (str
+ 1, cur_token
.str
);
9442 if (!i386_scale (str
))
9446 else if (!i386_scale (cur_token
.str
))
9448 intel_match_token (cur_token
.code
);
9451 /* No scaling. If this is a memory operand, the register is either a
9452 base register (first occurrence) or an index register (second
9454 else if (intel_parser
.in_bracket
)
9459 else if (!i
.index_reg
)
9463 as_bad (_("Too many register references in memory operand"));
9467 i
.types
[this_operand
].bitfield
.baseindex
= 1;
9470 /* It's neither base nor index. */
9471 else if (!intel_parser
.in_offset
&& !intel_parser
.is_mem
)
9473 i386_operand_type temp
= reg
->reg_type
;
9474 temp
.bitfield
.baseindex
= 0;
9475 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
9477 i
.types
[this_operand
].bitfield
.unspecified
= 0;
9478 i
.op
[this_operand
].regs
= reg
;
9483 as_bad (_("Invalid use of register"));
9487 /* Since registers are not part of the displacement string (except
9488 when we're parsing offset operands), we may need to remove any
9489 preceding '+' from the displacement string. */
9490 if (*intel_parser
.disp
!= '\0'
9491 && !intel_parser
.in_offset
)
9493 char *s
= intel_parser
.disp
;
9494 s
+= strlen (s
) - 1;
9519 intel_match_token (cur_token
.code
);
9521 if (cur_token
.code
== T_PTR
)
9524 /* It must have been an identifier. */
9525 intel_putback_token ();
9526 cur_token
.code
= T_ID
;
9532 if (!intel_parser
.in_offset
&& intel_parser
.is_mem
<= 0)
9536 /* The identifier represents a memory reference only if it's not
9537 preceded by an offset modifier and if it's not an equate. */
9538 symbolP
= symbol_find(cur_token
.str
);
9539 if (!symbolP
|| S_GET_SEGMENT(symbolP
) != absolute_section
)
9540 intel_parser
.is_mem
= 1;
9548 char *save_str
, sign
= 0;
9550 /* Allow constants that start with `+' or `-'. */
9551 if (cur_token
.code
== '-' || cur_token
.code
== '+')
9553 sign
= cur_token
.code
;
9554 intel_match_token (cur_token
.code
);
9555 if (cur_token
.code
!= T_CONST
)
9557 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
9563 save_str
= (char *) xmalloc (strlen (cur_token
.str
) + 2);
9564 strcpy (save_str
+ !!sign
, cur_token
.str
);
9568 /* Get the next token to check for register scaling. */
9569 intel_match_token (cur_token
.code
);
9571 /* Check if this constant is a scaling factor for an
9573 if (cur_token
.code
== '*')
9575 if (intel_match_token ('*') && cur_token
.code
== T_REG
)
9577 const reg_entry
*reg
= cur_token
.reg
;
9579 if (!intel_parser
.in_bracket
)
9581 as_bad (_("Register scaling only allowed "
9582 "in memory operands"));
9586 /* Disallow things like [1*si].
9587 sp and esp are invalid as index. */
9588 if (reg
->reg_type
.bitfield
.reg16
)
9589 reg
= i386_regtab
+ REGNAM_AX
+ 4;
9590 else if (i
.index_reg
)
9591 reg
= i386_regtab
+ REGNAM_EAX
+ 4;
9593 /* The constant is followed by `* reg', so it must be
9596 i
.types
[this_operand
].bitfield
.baseindex
= 1;
9598 /* Set the scale after setting the register (otherwise,
9599 i386_scale will complain) */
9600 if (!i386_scale (save_str
))
9602 intel_match_token (T_REG
);
9604 /* Since registers are not part of the displacement
9605 string, we may need to remove any preceding '+' from
9606 the displacement string. */
9607 if (*intel_parser
.disp
!= '\0')
9609 char *s
= intel_parser
.disp
;
9610 s
+= strlen (s
) - 1;
9620 /* The constant was not used for register scaling. Since we have
9621 already consumed the token following `*' we now need to put it
9622 back in the stream. */
9623 intel_putback_token ();
9626 /* Add the constant to the displacement string. */
9627 strcat (intel_parser
.disp
, save_str
);
9634 as_bad (_("Unrecognized token '%s'"), cur_token
.str
);
9638 /* Match the given token against cur_token. If they match, read the next
9639 token from the operand string. */
9641 intel_match_token (int code
)
9643 if (cur_token
.code
== code
)
9650 as_bad (_("Unexpected token `%s'"), cur_token
.str
);
9655 /* Read a new token from intel_parser.op_string and store it in cur_token. */
9657 intel_get_token (void)
9660 const reg_entry
*reg
;
9661 struct intel_token new_token
;
9663 new_token
.code
= T_NIL
;
9664 new_token
.reg
= NULL
;
9665 new_token
.str
= NULL
;
9667 /* Free the memory allocated to the previous token and move
9668 cur_token to prev_token. */
9670 free (prev_token
.str
);
9672 prev_token
= cur_token
;
9674 /* Skip whitespace. */
9675 while (is_space_char (*intel_parser
.op_string
))
9676 intel_parser
.op_string
++;
9678 /* Return an empty token if we find nothing else on the line. */
9679 if (*intel_parser
.op_string
== '\0')
9681 cur_token
= new_token
;
9685 /* The new token cannot be larger than the remainder of the operand
9687 new_token
.str
= (char *) xmalloc (strlen (intel_parser
.op_string
) + 1);
9688 new_token
.str
[0] = '\0';
9690 if (strchr ("0123456789", *intel_parser
.op_string
))
9692 char *p
= new_token
.str
;
9693 char *q
= intel_parser
.op_string
;
9694 new_token
.code
= T_CONST
;
9696 /* Allow any kind of identifier char to encompass floating point and
9697 hexadecimal numbers. */
9698 while (is_identifier_char (*q
))
9702 /* Recognize special symbol names [0-9][bf]. */
9703 if (strlen (intel_parser
.op_string
) == 2
9704 && (intel_parser
.op_string
[1] == 'b'
9705 || intel_parser
.op_string
[1] == 'f'))
9706 new_token
.code
= T_ID
;
9709 else if ((reg
= parse_register (intel_parser
.op_string
, &end_op
)) != NULL
)
9711 size_t len
= end_op
- intel_parser
.op_string
;
9713 new_token
.code
= T_REG
;
9714 new_token
.reg
= reg
;
9716 memcpy (new_token
.str
, intel_parser
.op_string
, len
);
9717 new_token
.str
[len
] = '\0';
9720 else if (is_identifier_char (*intel_parser
.op_string
))
9722 char *p
= new_token
.str
;
9723 char *q
= intel_parser
.op_string
;
9725 /* A '.' or '$' followed by an identifier char is an identifier.
9726 Otherwise, it's operator '.' followed by an expression. */
9727 if ((*q
== '.' || *q
== '$') && !is_identifier_char (*(q
+ 1)))
9729 new_token
.code
= '.';
9730 new_token
.str
[0] = '.';
9731 new_token
.str
[1] = '\0';
9735 while (is_identifier_char (*q
) || *q
== '@')
9739 if (strcasecmp (new_token
.str
, "NOT") == 0)
9740 new_token
.code
= '~';
9742 else if (strcasecmp (new_token
.str
, "MOD") == 0)
9743 new_token
.code
= '%';
9745 else if (strcasecmp (new_token
.str
, "AND") == 0)
9746 new_token
.code
= '&';
9748 else if (strcasecmp (new_token
.str
, "OR") == 0)
9749 new_token
.code
= '|';
9751 else if (strcasecmp (new_token
.str
, "XOR") == 0)
9752 new_token
.code
= '^';
9754 else if (strcasecmp (new_token
.str
, "SHL") == 0)
9755 new_token
.code
= T_SHL
;
9757 else if (strcasecmp (new_token
.str
, "SHR") == 0)
9758 new_token
.code
= T_SHR
;
9760 else if (strcasecmp (new_token
.str
, "BYTE") == 0)
9761 new_token
.code
= T_BYTE
;
9763 else if (strcasecmp (new_token
.str
, "WORD") == 0)
9764 new_token
.code
= T_WORD
;
9766 else if (strcasecmp (new_token
.str
, "DWORD") == 0)
9767 new_token
.code
= T_DWORD
;
9769 else if (strcasecmp (new_token
.str
, "FWORD") == 0)
9770 new_token
.code
= T_FWORD
;
9772 else if (strcasecmp (new_token
.str
, "QWORD") == 0)
9773 new_token
.code
= T_QWORD
;
9775 else if (strcasecmp (new_token
.str
, "TBYTE") == 0
9776 /* XXX remove (gcc still uses it) */
9777 || strcasecmp (new_token
.str
, "XWORD") == 0)
9778 new_token
.code
= T_TBYTE
;
9780 else if (strcasecmp (new_token
.str
, "XMMWORD") == 0
9781 || strcasecmp (new_token
.str
, "OWORD") == 0)
9782 new_token
.code
= T_XMMWORD
;
9784 else if (strcasecmp (new_token
.str
, "YMMWORD") == 0)
9785 new_token
.code
= T_YMMWORD
;
9787 else if (strcasecmp (new_token
.str
, "PTR") == 0)
9788 new_token
.code
= T_PTR
;
9790 else if (strcasecmp (new_token
.str
, "SHORT") == 0)
9791 new_token
.code
= T_SHORT
;
9793 else if (strcasecmp (new_token
.str
, "OFFSET") == 0)
9795 new_token
.code
= T_OFFSET
;
9797 /* ??? This is not mentioned in the MASM grammar but gcc
9798 makes use of it with -mintel-syntax. OFFSET may be
9799 followed by FLAT: */
9800 if (strncasecmp (q
, " FLAT:", 6) == 0)
9801 strcat (new_token
.str
, " FLAT:");
9805 new_token
.code
= T_ID
;
9809 else if (strchr ("+-/*%|&^:[]()~", *intel_parser
.op_string
))
9811 new_token
.code
= *intel_parser
.op_string
;
9812 new_token
.str
[0] = *intel_parser
.op_string
;
9813 new_token
.str
[1] = '\0';
9816 else if (strchr ("<>", *intel_parser
.op_string
)
9817 && *intel_parser
.op_string
== *(intel_parser
.op_string
+ 1))
9819 new_token
.code
= *intel_parser
.op_string
== '<' ? T_SHL
: T_SHR
;
9820 new_token
.str
[0] = *intel_parser
.op_string
;
9821 new_token
.str
[1] = *intel_parser
.op_string
;
9822 new_token
.str
[2] = '\0';
9826 as_bad (_("Unrecognized token `%s'"), intel_parser
.op_string
);
9828 intel_parser
.op_string
+= strlen (new_token
.str
);
9829 cur_token
= new_token
;
9832 /* Put cur_token back into the token stream and make cur_token point to
9835 intel_putback_token (void)
9837 if (cur_token
.code
!= T_NIL
)
9839 intel_parser
.op_string
-= strlen (cur_token
.str
);
9840 free (cur_token
.str
);
9842 cur_token
= prev_token
;
9844 /* Forget prev_token. */
9845 prev_token
.code
= T_NIL
;
9846 prev_token
.reg
= NULL
;
9847 prev_token
.str
= NULL
;
9851 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
9853 int saved_naked_reg
;
9854 char saved_register_dot
;
9856 saved_naked_reg
= allow_naked_reg
;
9857 allow_naked_reg
= 1;
9858 saved_register_dot
= register_chars
['.'];
9859 register_chars
['.'] = '.';
9860 allow_pseudo_reg
= 1;
9861 expression_and_evaluate (exp
);
9862 allow_pseudo_reg
= 0;
9863 register_chars
['.'] = saved_register_dot
;
9864 allow_naked_reg
= saved_naked_reg
;
9866 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
9868 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
9870 exp
->X_op
= O_constant
;
9871 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
9872 .dw2_regnum
[flag_code
>> 1];
9875 exp
->X_op
= O_illegal
;
9880 tc_x86_frame_initial_instructions (void)
9882 static unsigned int sp_regno
[2];
9884 if (!sp_regno
[flag_code
>> 1])
9886 char *saved_input
= input_line_pointer
;
9887 char sp
[][4] = {"esp", "rsp"};
9890 input_line_pointer
= sp
[flag_code
>> 1];
9891 tc_x86_parse_to_dw2regnum (&exp
);
9892 assert (exp
.X_op
== O_constant
);
9893 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
9894 input_line_pointer
= saved_input
;
9897 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
9898 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
9902 i386_elf_section_type (const char *str
, size_t len
)
9904 if (flag_code
== CODE_64BIT
9905 && len
== sizeof ("unwind") - 1
9906 && strncmp (str
, "unwind", 6) == 0)
9907 return SHT_X86_64_UNWIND
;
9914 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
9918 expr
.X_op
= O_secrel
;
9919 expr
.X_add_symbol
= symbol
;
9920 expr
.X_add_number
= 0;
9921 emit_expr (&expr
, size
);
9925 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9926 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
9929 x86_64_section_letter (int letter
, char **ptr_msg
)
9931 if (flag_code
== CODE_64BIT
)
9934 return SHF_X86_64_LARGE
;
9936 *ptr_msg
= _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
9939 *ptr_msg
= _("Bad .section directive: want a,w,x,M,S,G,T in string");
9944 x86_64_section_word (char *str
, size_t len
)
9946 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
9947 return SHF_X86_64_LARGE
;
9953 handle_large_common (int small ATTRIBUTE_UNUSED
)
9955 if (flag_code
!= CODE_64BIT
)
9957 s_comm_internal (0, elf_common_parse
);
9958 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
9962 static segT lbss_section
;
9963 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
9964 asection
*saved_bss_section
= bss_section
;
9966 if (lbss_section
== NULL
)
9968 flagword applicable
;
9970 subsegT subseg
= now_subseg
;
9972 /* The .lbss section is for local .largecomm symbols. */
9973 lbss_section
= subseg_new (".lbss", 0);
9974 applicable
= bfd_applicable_section_flags (stdoutput
);
9975 bfd_set_section_flags (stdoutput
, lbss_section
,
9976 applicable
& SEC_ALLOC
);
9977 seg_info (lbss_section
)->bss
= 1;
9979 subseg_set (seg
, subseg
);
9982 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
9983 bss_section
= lbss_section
;
9985 s_comm_internal (0, elf_common_parse
);
9987 elf_com_section_ptr
= saved_com_section_ptr
;
9988 bss_section
= saved_bss_section
;
9991 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */