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* gas/elf/elf.exp (run_list_test): Undo $readelf change in 2001-06-07.
[binutils.git] / opcodes / i960-dis.c
blob90b170a3bb86046d99a10697a8ad81b4d150f855
1 /* Disassemble i80960 instructions.
2 Copyright 1990, 1991, 1993, 1994, 1995, 1996, 1998, 1999, 2000
3 Free Software Foundation, Inc.
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2, or (at your option)
8 any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; see the file COPYING. If not, write to the
17 Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA
18 02111-1307, USA. */
19
20 #include "sysdep.h"
21 #include "dis-asm.h"
22
23 static const char *const reg_names[] = {
24 /* 0 */ "pfp", "sp", "rip", "r3", "r4", "r5", "r6", "r7",
25 /* 8 */ "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
26 /* 16 */ "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
27 /* 24 */ "g8", "g9", "g10", "g11", "g12", "g13", "g14", "fp",
28 /* 32 */ "pc", "ac", "ip", "tc", "fp0", "fp1", "fp2", "fp3"
29 };
30
31
32 static FILE *stream; /* Output goes here */
33 static struct disassemble_info *info;
34 static void print_addr();
35 static void ctrl();
36 static void cobr();
37 static void reg();
38 static int mem();
39 static void ea();
40 static void dstop();
41 static void regop();
42 static void invalid();
43 static int pinsn();
44 static void put_abs();
45
46
47 /* Print the i960 instruction at address 'memaddr' in debugged memory,
48 on INFO->STREAM. Returns length of the instruction, in bytes. */
49
50 int
51 print_insn_i960 (memaddr, info_arg)
52 bfd_vma memaddr;
53 struct disassemble_info *info_arg;
54 {
55 unsigned int word1, word2 = 0xdeadbeef;
56 bfd_byte buffer[8];
57 int status;
58
59 info = info_arg;
60 stream = info->stream;
61
62 /* Read word1. Only read word2 if the instruction
63 needs it, to prevent reading past the end of a section. */
64
65 status = (*info->read_memory_func) (memaddr, (bfd_byte *) buffer, 4, info);
66 if (status != 0)
67 {
68 (*info->memory_error_func) (status, memaddr, info);
69 return -1;
70 }
71
72 word1 = bfd_getl32 (buffer);
73
74 /* Divide instruction set into classes based on high 4 bits of opcode. */
75 switch ( (word1 >> 28) & 0xf )
76 {
77 default:
78 break;
79 case 0x8:
80 case 0x9:
81 case 0xa:
82 case 0xb:
83 case 0xc:
84 /* Read word2. */
85 status = (*info->read_memory_func)
86 (memaddr + 4, (bfd_byte *) (buffer + 4), 4, info);
87 if (status != 0)
88 {
89 (*info->memory_error_func) (status, memaddr, info);
90 return -1;
91 }
92 word2 = bfd_getl32 (buffer + 4);
93 break;
94 }
95
96 return pinsn( memaddr, word1, word2 );
97 }
98 \f
99 #define IN_GDB
100
101 /*****************************************************************************
102 * All code below this point should be identical with that of
103 * the disassembler in gdmp960.
104
105 A noble sentiment, but at least in cosmetic ways (info->fprintf_func), it
106 just ain't so. -kingdon, 31 Mar 93
107 *****************************************************************************/
108
109 struct tabent {
110 char *name;
111 short numops;
112 };
113
114 struct sparse_tabent {
115 int opcode;
116 char *name;
117 short numops;
118 };
119
120 static int
121 pinsn( memaddr, word1, word2 )
122 bfd_vma memaddr;
123 unsigned long word1, word2;
124 {
125 int instr_len;
126
127 instr_len = 4;
128 put_abs( word1, word2 );
129
130 /* Divide instruction set into classes based on high 4 bits of opcode*/
131 switch ( (word1 >> 28) & 0xf ){
132 case 0x0:
133 case 0x1:
134 ctrl( memaddr, word1, word2 );
135 break;
136 case 0x2:
137 case 0x3:
138 cobr( memaddr, word1, word2 );
139 break;
140 case 0x5:
141 case 0x6:
142 case 0x7:
143 reg( word1 );
144 break;
145 case 0x8:
146 case 0x9:
147 case 0xa:
148 case 0xb:
149 case 0xc:
150 instr_len = mem( memaddr, word1, word2, 0 );
151 break;
152 default:
153 /* invalid instruction, print as data word */
154 invalid( word1 );
155 break;
156 }
157 return instr_len;
158 }
159
160 /****************************************/
161 /* CTRL format */
162 /****************************************/
163 static void
164 ctrl( memaddr, word1, word2 )
165 bfd_vma memaddr;
166 unsigned long word1, word2;
167 {
168 int i;
169 static const struct tabent ctrl_tab[] = {
170 { NULL, 0, }, /* 0x00 */
171 { NULL, 0, }, /* 0x01 */
172 { NULL, 0, }, /* 0x02 */
173 { NULL, 0, }, /* 0x03 */
174 { NULL, 0, }, /* 0x04 */
175 { NULL, 0, }, /* 0x05 */
176 { NULL, 0, }, /* 0x06 */
177 { NULL, 0, }, /* 0x07 */
178 { "b", 1, }, /* 0x08 */
179 { "call", 1, }, /* 0x09 */
180 { "ret", 0, }, /* 0x0a */
181 { "bal", 1, }, /* 0x0b */
182 { NULL, 0, }, /* 0x0c */
183 { NULL, 0, }, /* 0x0d */
184 { NULL, 0, }, /* 0x0e */
185 { NULL, 0, }, /* 0x0f */
186 { "bno", 1, }, /* 0x10 */
187 { "bg", 1, }, /* 0x11 */
188 { "be", 1, }, /* 0x12 */
189 { "bge", 1, }, /* 0x13 */
190 { "bl", 1, }, /* 0x14 */
191 { "bne", 1, }, /* 0x15 */
192 { "ble", 1, }, /* 0x16 */
193 { "bo", 1, }, /* 0x17 */
194 { "faultno", 0, }, /* 0x18 */
195 { "faultg", 0, }, /* 0x19 */
196 { "faulte", 0, }, /* 0x1a */
197 { "faultge", 0, }, /* 0x1b */
198 { "faultl", 0, }, /* 0x1c */
199 { "faultne", 0, }, /* 0x1d */
200 { "faultle", 0, }, /* 0x1e */
201 { "faulto", 0, }, /* 0x1f */
202 };
203
204 i = (word1 >> 24) & 0xff;
205 if ( (ctrl_tab[i].name == NULL) || ((word1 & 1) != 0) ){
206 invalid( word1 );
207 return;
208 }
209
210 (*info->fprintf_func) ( stream, ctrl_tab[i].name );
211 if ( word1 & 2 ){ /* Predicts branch not taken */
212 (*info->fprintf_func) ( stream, ".f" );
213 }
214
215 if ( ctrl_tab[i].numops == 1 ){
216 /* EXTRACT DISPLACEMENT AND CONVERT TO ADDRESS */
217 word1 &= 0x00ffffff;
218 if ( word1 & 0x00800000 ){ /* Sign bit is set */
219 word1 |= (-1 & ~0xffffff); /* Sign extend */
220 }
221 (*info->fprintf_func)( stream, "\t" );
222 print_addr( word1 + memaddr );
223 }
224 }
225
226 /****************************************/
227 /* COBR format */
228 /****************************************/
229 static void
230 cobr( memaddr, word1, word2 )
231 bfd_vma memaddr;
232 unsigned long word1, word2;
233 {
234 int src1;
235 int src2;
236 int i;
237
238 static const struct tabent cobr_tab[] = {
239 { "testno", 1, }, /* 0x20 */
240 { "testg", 1, }, /* 0x21 */
241 { "teste", 1, }, /* 0x22 */
242 { "testge", 1, }, /* 0x23 */
243 { "testl", 1, }, /* 0x24 */
244 { "testne", 1, }, /* 0x25 */
245 { "testle", 1, }, /* 0x26 */
246 { "testo", 1, }, /* 0x27 */
247 { NULL, 0, }, /* 0x28 */
248 { NULL, 0, }, /* 0x29 */
249 { NULL, 0, }, /* 0x2a */
250 { NULL, 0, }, /* 0x2b */
251 { NULL, 0, }, /* 0x2c */
252 { NULL, 0, }, /* 0x2d */
253 { NULL, 0, }, /* 0x2e */
254 { NULL, 0, }, /* 0x2f */
255 { "bbc", 3, }, /* 0x30 */
256 { "cmpobg", 3, }, /* 0x31 */
257 { "cmpobe", 3, }, /* 0x32 */
258 { "cmpobge", 3, }, /* 0x33 */
259 { "cmpobl", 3, }, /* 0x34 */
260 { "cmpobne", 3, }, /* 0x35 */
261 { "cmpoble", 3, }, /* 0x36 */
262 { "bbs", 3, }, /* 0x37 */
263 { "cmpibno", 3, }, /* 0x38 */
264 { "cmpibg", 3, }, /* 0x39 */
265 { "cmpibe", 3, }, /* 0x3a */
266 { "cmpibge", 3, }, /* 0x3b */
267 { "cmpibl", 3, }, /* 0x3c */
268 { "cmpibne", 3, }, /* 0x3d */
269 { "cmpible", 3, }, /* 0x3e */
270 { "cmpibo", 3, }, /* 0x3f */
271 };
272
273 i = ((word1 >> 24) & 0xff) - 0x20;
274 if ( cobr_tab[i].name == NULL ){
275 invalid( word1 );
276 return;
277 }
278
279 (*info->fprintf_func) ( stream, cobr_tab[i].name );
280 if ( word1 & 2 ){ /* Predicts branch not taken */
281 (*info->fprintf_func) ( stream, ".f" );
282 }
283 (*info->fprintf_func)( stream, "\t" );
284
285 src1 = (word1 >> 19) & 0x1f;
286 src2 = (word1 >> 14) & 0x1f;
287
288 if ( word1 & 0x02000 ){ /* M1 is 1 */
289 (*info->fprintf_func)( stream, "%d", src1 );
290 } else { /* M1 is 0 */
291 (*info->fprintf_func)( stream, reg_names[src1] );
292 }
293
294 if ( cobr_tab[i].numops > 1 ){
295 if ( word1 & 1 ){ /* S2 is 1 */
296 (*info->fprintf_func)( stream, ",sf%d,", src2 );
297 } else { /* S1 is 0 */
298 (*info->fprintf_func)( stream, ",%s,", reg_names[src2] );
299 }
300
301 /* Extract displacement and convert to address
302 */
303 word1 &= 0x00001ffc;
304 if ( word1 & 0x00001000 ){ /* Negative displacement */
305 word1 |= (-1 & ~0x1fff); /* Sign extend */
306 }
307 print_addr( memaddr + word1 );
308 }
309 }
310
311 /****************************************/
312 /* MEM format */
313 /****************************************/
314 static int /* returns instruction length: 4 or 8 */
315 mem( memaddr, word1, word2, noprint )
316 bfd_vma memaddr;
317 unsigned long word1, word2;
318 int noprint; /* If TRUE, return instruction length, but
319 * don't output any text.
320 */
321 {
322 int i, j;
323 int len;
324 int mode;
325 int offset;
326 const char *reg1, *reg2, *reg3;
327
328 /* This lookup table is too sparse to make it worth typing in, but not
329 so large as to make a sparse array necessary. We create the table
330 at runtime. */
331
332 /*
333 * NOTE: In this table, the meaning of 'numops' is:
334 * 1: single operand
335 * 2: 2 operands, load instruction
336 * -2: 2 operands, store instruction
337 */
338 static struct tabent *mem_tab;
339 /* Opcodes of 0x8X, 9X, aX, bX, and cX must be in the table. */
340 #define MEM_MIN 0x80
341 #define MEM_MAX 0xcf
342 #define MEM_SIZ ( * sizeof(struct tabent))
343
344 static const struct sparse_tabent mem_init[] = {
345 { 0x80, "ldob", 2 },
346 { 0x82, "stob", -2 },
347 { 0x84, "bx", 1 },
348 { 0x85, "balx", 2 },
349 { 0x86, "callx", 1 },
350 { 0x88, "ldos", 2 },
351 { 0x8a, "stos", -2 },
352 { 0x8c, "lda", 2 },
353 { 0x90, "ld", 2 },
354 { 0x92, "st", -2 },
355 { 0x98, "ldl", 2 },
356 { 0x9a, "stl", -2 },
357 { 0xa0, "ldt", 2 },
358 { 0xa2, "stt", -2 },
359 { 0xac, "dcinva", 1 },
360 { 0xb0, "ldq", 2 },
361 { 0xb2, "stq", -2 },
362 { 0xc0, "ldib", 2 },
363 { 0xc2, "stib", -2 },
364 { 0xc8, "ldis", 2 },
365 { 0xca, "stis", -2 },
366 { 0, NULL, 0 }
367 };
368 static struct tabent mem_tab_buf[MEM_MAX - MEM_MIN + 1];
369
370 if ( mem_tab == NULL ){
371 mem_tab = mem_tab_buf;
372 for ( i = 0; mem_init[i].opcode != 0; i++ ){
373 j = mem_init[i].opcode - MEM_MIN;
374 mem_tab[j].name = mem_init[i].name;
375 mem_tab[j].numops = mem_init[i].numops;
376 }
377 }
378
379 i = ((word1 >> 24) & 0xff) - MEM_MIN;
380 mode = (word1 >> 10) & 0xf;
381
382 if ( (mem_tab[i].name != NULL) /* Valid instruction */
383 && ((mode == 5) || (mode >=12)) ){ /* With 32-bit displacement */
384 len = 8;
385 } else {
386 len = 4;
387 }
388
389 if ( noprint ){
390 return len;
391 }
392
393 if ( (mem_tab[i].name == NULL) || (mode == 6) ){
394 invalid( word1 );
395 return len;
396 }
397
398 (*info->fprintf_func)( stream, "%s\t", mem_tab[i].name );
399
400 reg1 = reg_names[ (word1 >> 19) & 0x1f ]; /* MEMB only */
401 reg2 = reg_names[ (word1 >> 14) & 0x1f ];
402 reg3 = reg_names[ word1 & 0x1f ]; /* MEMB only */
403 offset = word1 & 0xfff; /* MEMA only */
404
405 switch ( mem_tab[i].numops ){
406
407 case 2: /* LOAD INSTRUCTION */
408 if ( mode & 4 ){ /* MEMB FORMAT */
409 ea( memaddr, mode, reg2, reg3, word1, word2 );
410 (*info->fprintf_func)( stream, ",%s", reg1 );
411 } else { /* MEMA FORMAT */
412 (*info->fprintf_func)( stream, "0x%x", (unsigned) offset );
413 if (mode & 8) {
414 (*info->fprintf_func)( stream, "(%s)", reg2 );
415 }
416 (*info->fprintf_func)( stream, ",%s", reg1 );
417 }
418 break;
419
420 case -2: /* STORE INSTRUCTION */
421 if ( mode & 4 ){ /* MEMB FORMAT */
422 (*info->fprintf_func)( stream, "%s,", reg1 );
423 ea( memaddr, mode, reg2, reg3, word1, word2 );
424 } else { /* MEMA FORMAT */
425 (*info->fprintf_func)( stream, "%s,0x%x", reg1, (unsigned) offset );
426 if (mode & 8) {
427 (*info->fprintf_func)( stream, "(%s)", reg2 );
428 }
429 }
430 break;
431
432 case 1: /* BX/CALLX INSTRUCTION */
433 if ( mode & 4 ){ /* MEMB FORMAT */
434 ea( memaddr, mode, reg2, reg3, word1, word2 );
435 } else { /* MEMA FORMAT */
436 (*info->fprintf_func)( stream, "0x%x", (unsigned) offset );
437 if (mode & 8) {
438 (*info->fprintf_func)( stream, "(%s)", reg2 );
439 }
440 }
441 break;
442 }
443
444 return len;
445 }
446
447 /****************************************/
448 /* REG format */
449 /****************************************/
450 static void
451 reg( word1 )
452 unsigned long word1;
453 {
454 int i, j;
455 int opcode;
456 int fp;
457 int m1, m2, m3;
458 int s1, s2;
459 int src, src2, dst;
460 char *mnemp;
461
462 /* This lookup table is too sparse to make it worth typing in, but not
463 so large as to make a sparse array necessary. We create the table
464 at runtime. */
465
466 /*
467 * NOTE: In this table, the meaning of 'numops' is:
468 * 1: single operand, which is NOT a destination.
469 * -1: single operand, which IS a destination.
470 * 2: 2 operands, the 2nd of which is NOT a destination.
471 * -2: 2 operands, the 2nd of which IS a destination.
472 * 3: 3 operands
473 *
474 * If an opcode mnemonic begins with "F", it is a floating-point
475 * opcode (the "F" is not printed).
476 */
477
478 static struct tabent *reg_tab;
479 static const struct sparse_tabent reg_init[] = {
480 #define REG_MIN 0x580
481 { 0x580, "notbit", 3 },
482 { 0x581, "and", 3 },
483 { 0x582, "andnot", 3 },
484 { 0x583, "setbit", 3 },
485 { 0x584, "notand", 3 },
486 { 0x586, "xor", 3 },
487 { 0x587, "or", 3 },
488 { 0x588, "nor", 3 },
489 { 0x589, "xnor", 3 },
490 { 0x58a, "not", -2 },
491 { 0x58b, "ornot", 3 },
492 { 0x58c, "clrbit", 3 },
493 { 0x58d, "notor", 3 },
494 { 0x58e, "nand", 3 },
495 { 0x58f, "alterbit", 3 },
496 { 0x590, "addo", 3 },
497 { 0x591, "addi", 3 },
498 { 0x592, "subo", 3 },
499 { 0x593, "subi", 3 },
500 { 0x594, "cmpob", 2 },
501 { 0x595, "cmpib", 2 },
502 { 0x596, "cmpos", 2 },
503 { 0x597, "cmpis", 2 },
504 { 0x598, "shro", 3 },
505 { 0x59a, "shrdi", 3 },
506 { 0x59b, "shri", 3 },
507 { 0x59c, "shlo", 3 },
508 { 0x59d, "rotate", 3 },
509 { 0x59e, "shli", 3 },
510 { 0x5a0, "cmpo", 2 },
511 { 0x5a1, "cmpi", 2 },
512 { 0x5a2, "concmpo", 2 },
513 { 0x5a3, "concmpi", 2 },
514 { 0x5a4, "cmpinco", 3 },
515 { 0x5a5, "cmpinci", 3 },
516 { 0x5a6, "cmpdeco", 3 },
517 { 0x5a7, "cmpdeci", 3 },
518 { 0x5ac, "scanbyte", 2 },
519 { 0x5ad, "bswap", -2 },
520 { 0x5ae, "chkbit", 2 },
521 { 0x5b0, "addc", 3 },
522 { 0x5b2, "subc", 3 },
523 { 0x5b4, "intdis", 0 },
524 { 0x5b5, "inten", 0 },
525 { 0x5cc, "mov", -2 },
526 { 0x5d8, "eshro", 3 },
527 { 0x5dc, "movl", -2 },
528 { 0x5ec, "movt", -2 },
529 { 0x5fc, "movq", -2 },
530 { 0x600, "synmov", 2 },
531 { 0x601, "synmovl", 2 },
532 { 0x602, "synmovq", 2 },
533 { 0x603, "cmpstr", 3 },
534 { 0x604, "movqstr", 3 },
535 { 0x605, "movstr", 3 },
536 { 0x610, "atmod", 3 },
537 { 0x612, "atadd", 3 },
538 { 0x613, "inspacc", -2 },
539 { 0x614, "ldphy", -2 },
540 { 0x615, "synld", -2 },
541 { 0x617, "fill", 3 },
542 { 0x630, "sdma", 3 },
543 { 0x631, "udma", 0 },
544 { 0x640, "spanbit", -2 },
545 { 0x641, "scanbit", -2 },
546 { 0x642, "daddc", 3 },
547 { 0x643, "dsubc", 3 },
548 { 0x644, "dmovt", -2 },
549 { 0x645, "modac", 3 },
550 { 0x646, "condrec", -2 },
551 { 0x650, "modify", 3 },
552 { 0x651, "extract", 3 },
553 { 0x654, "modtc", 3 },
554 { 0x655, "modpc", 3 },
555 { 0x656, "receive", -2 },
556 { 0x658, "intctl", -2 },
557 { 0x659, "sysctl", 3 },
558 { 0x65b, "icctl", 3 },
559 { 0x65c, "dcctl", 3 },
560 { 0x65d, "halt", 0 },
561 { 0x660, "calls", 1 },
562 { 0x662, "send", 3 },
563 { 0x663, "sendserv", 1 },
564 { 0x664, "resumprcs", 1 },
565 { 0x665, "schedprcs", 1 },
566 { 0x666, "saveprcs", 0 },
567 { 0x668, "condwait", 1 },
568 { 0x669, "wait", 1 },
569 { 0x66a, "signal", 1 },
570 { 0x66b, "mark", 0 },
571 { 0x66c, "fmark", 0 },
572 { 0x66d, "flushreg", 0 },
573 { 0x66f, "syncf", 0 },
574 { 0x670, "emul", 3 },
575 { 0x671, "ediv", 3 },
576 { 0x673, "ldtime", -1 },
577 { 0x674, "Fcvtir", -2 },
578 { 0x675, "Fcvtilr", -2 },
579 { 0x676, "Fscalerl", 3 },
580 { 0x677, "Fscaler", 3 },
581 { 0x680, "Fatanr", 3 },
582 { 0x681, "Flogepr", 3 },
583 { 0x682, "Flogr", 3 },
584 { 0x683, "Fremr", 3 },
585 { 0x684, "Fcmpor", 2 },
586 { 0x685, "Fcmpr", 2 },
587 { 0x688, "Fsqrtr", -2 },
588 { 0x689, "Fexpr", -2 },
589 { 0x68a, "Flogbnr", -2 },
590 { 0x68b, "Froundr", -2 },
591 { 0x68c, "Fsinr", -2 },
592 { 0x68d, "Fcosr", -2 },
593 { 0x68e, "Ftanr", -2 },
594 { 0x68f, "Fclassr", 1 },
595 { 0x690, "Fatanrl", 3 },
596 { 0x691, "Flogeprl", 3 },
597 { 0x692, "Flogrl", 3 },
598 { 0x693, "Fremrl", 3 },
599 { 0x694, "Fcmporl", 2 },
600 { 0x695, "Fcmprl", 2 },
601 { 0x698, "Fsqrtrl", -2 },
602 { 0x699, "Fexprl", -2 },
603 { 0x69a, "Flogbnrl", -2 },
604 { 0x69b, "Froundrl", -2 },
605 { 0x69c, "Fsinrl", -2 },
606 { 0x69d, "Fcosrl", -2 },
607 { 0x69e, "Ftanrl", -2 },
608 { 0x69f, "Fclassrl", 1 },
609 { 0x6c0, "Fcvtri", -2 },
610 { 0x6c1, "Fcvtril", -2 },
611 { 0x6c2, "Fcvtzri", -2 },
612 { 0x6c3, "Fcvtzril", -2 },
613 { 0x6c9, "Fmovr", -2 },
614 { 0x6d9, "Fmovrl", -2 },
615 { 0x6e1, "Fmovre", -2 },
616 { 0x6e2, "Fcpysre", 3 },
617 { 0x6e3, "Fcpyrsre", 3 },
618 { 0x701, "mulo", 3 },
619 { 0x708, "remo", 3 },
620 { 0x70b, "divo", 3 },
621 { 0x741, "muli", 3 },
622 { 0x748, "remi", 3 },
623 { 0x749, "modi", 3 },
624 { 0x74b, "divi", 3 },
625 { 0x780, "addono", 3 },
626 { 0x781, "addino", 3 },
627 { 0x782, "subono", 3 },
628 { 0x783, "subino", 3 },
629 { 0x784, "selno", 3 },
630 { 0x78b, "Fdivr", 3 },
631 { 0x78c, "Fmulr", 3 },
632 { 0x78d, "Fsubr", 3 },
633 { 0x78f, "Faddr", 3 },
634 { 0x790, "addog", 3 },
635 { 0x791, "addig", 3 },
636 { 0x792, "subog", 3 },
637 { 0x793, "subig", 3 },
638 { 0x794, "selg", 3 },
639 { 0x79b, "Fdivrl", 3 },
640 { 0x79c, "Fmulrl", 3 },
641 { 0x79d, "Fsubrl", 3 },
642 { 0x79f, "Faddrl", 3 },
643 { 0x7a0, "addoe", 3 },
644 { 0x7a1, "addie", 3 },
645 { 0x7a2, "suboe", 3 },
646 { 0x7a3, "subie", 3 },
647 { 0x7a4, "sele", 3 },
648 { 0x7b0, "addoge", 3 },
649 { 0x7b1, "addige", 3 },
650 { 0x7b2, "suboge", 3 },
651 { 0x7b3, "subige", 3 },
652 { 0x7b4, "selge", 3 },
653 { 0x7c0, "addol", 3 },
654 { 0x7c1, "addil", 3 },
655 { 0x7c2, "subol", 3 },
656 { 0x7c3, "subil", 3 },
657 { 0x7c4, "sell", 3 },
658 { 0x7d0, "addone", 3 },
659 { 0x7d1, "addine", 3 },
660 { 0x7d2, "subone", 3 },
661 { 0x7d3, "subine", 3 },
662 { 0x7d4, "selne", 3 },
663 { 0x7e0, "addole", 3 },
664 { 0x7e1, "addile", 3 },
665 { 0x7e2, "subole", 3 },
666 { 0x7e3, "subile", 3 },
667 { 0x7e4, "selle", 3 },
668 { 0x7f0, "addoo", 3 },
669 { 0x7f1, "addio", 3 },
670 { 0x7f2, "suboo", 3 },
671 { 0x7f3, "subio", 3 },
672 { 0x7f4, "selo", 3 },
673 #define REG_MAX 0x7f4
674 { 0, NULL, 0 }
675 };
676 static struct tabent reg_tab_buf[REG_MAX - REG_MIN + 1];
677
678 if ( reg_tab == NULL ){
679 reg_tab = reg_tab_buf;
680 for ( i = 0; reg_init[i].opcode != 0; i++ ){
681 j = reg_init[i].opcode - REG_MIN;
682 reg_tab[j].name = reg_init[i].name;
683 reg_tab[j].numops = reg_init[i].numops;
684 }
685 }
686
687 opcode = ((word1 >> 20) & 0xff0) | ((word1 >> 7) & 0xf);
688 i = opcode - REG_MIN;
689
690 if ( (opcode<REG_MIN) || (opcode>REG_MAX) || (reg_tab[i].name==NULL) ){
691 invalid( word1 );
692 return;
693 }
694
695 mnemp = reg_tab[i].name;
696 if ( *mnemp == 'F' ){
697 fp = 1;
698 mnemp++;
699 } else {
700 fp = 0;
701 }
702
703 (*info->fprintf_func)( stream, mnemp );
704
705 s1 = (word1 >> 5) & 1;
706 s2 = (word1 >> 6) & 1;
707 m1 = (word1 >> 11) & 1;
708 m2 = (word1 >> 12) & 1;
709 m3 = (word1 >> 13) & 1;
710 src = word1 & 0x1f;
711 src2 = (word1 >> 14) & 0x1f;
712 dst = (word1 >> 19) & 0x1f;
713
714 if ( reg_tab[i].numops != 0 ){
715 (*info->fprintf_func)( stream, "\t" );
716
717 switch ( reg_tab[i].numops ){
718 case 1:
719 regop( m1, s1, src, fp );
720 break;
721 case -1:
722 dstop( m3, dst, fp );
723 break;
724 case 2:
725 regop( m1, s1, src, fp );
726 (*info->fprintf_func)( stream, "," );
727 regop( m2, s2, src2, fp );
728 break;
729 case -2:
730 regop( m1, s1, src, fp );
731 (*info->fprintf_func)( stream, "," );
732 dstop( m3, dst, fp );
733 break;
734 case 3:
735 regop( m1, s1, src, fp );
736 (*info->fprintf_func)( stream, "," );
737 regop( m2, s2, src2, fp );
738 (*info->fprintf_func)( stream, "," );
739 dstop( m3, dst, fp );
740 break;
741 }
742 }
743 }
744
745
746 /*
747 * Print out effective address for memb instructions.
748 */
749 static void
750 ea( memaddr, mode, reg2, reg3, word1, word2 )
751 bfd_vma memaddr;
752 int mode;
753 char *reg2, *reg3;
754 int word1;
755 unsigned int word2;
756 {
757 int scale;
758 static const int scale_tab[] = { 1, 2, 4, 8, 16 };
759
760 scale = (word1 >> 7) & 0x07;
761 if ( (scale > 4) || (((word1 >> 5) & 0x03) != 0) ){
762 invalid( word1 );
763 return;
764 }
765 scale = scale_tab[scale];
766
767 switch (mode) {
768 case 4: /* (reg) */
769 (*info->fprintf_func)( stream, "(%s)", reg2 );
770 break;
771 case 5: /* displ+8(ip) */
772 print_addr( word2+8+memaddr );
773 break;
774 case 7: /* (reg)[index*scale] */
775 if (scale == 1) {
776 (*info->fprintf_func)( stream, "(%s)[%s]", reg2, reg3 );
777 } else {
778 (*info->fprintf_func)( stream, "(%s)[%s*%d]",reg2,reg3,scale);
779 }
780 break;
781 case 12: /* displacement */
782 print_addr( (bfd_vma)word2 );
783 break;
784 case 13: /* displ(reg) */
785 print_addr( (bfd_vma)word2 );
786 (*info->fprintf_func)( stream, "(%s)", reg2 );
787 break;
788 case 14: /* displ[index*scale] */
789 print_addr( (bfd_vma)word2 );
790 if (scale == 1) {
791 (*info->fprintf_func)( stream, "[%s]", reg3 );
792 } else {
793 (*info->fprintf_func)( stream, "[%s*%d]", reg3, scale );
794 }
795 break;
796 case 15: /* displ(reg)[index*scale] */
797 print_addr( (bfd_vma)word2 );
798 if (scale == 1) {
799 (*info->fprintf_func)( stream, "(%s)[%s]", reg2, reg3 );
800 } else {
801 (*info->fprintf_func)( stream, "(%s)[%s*%d]",reg2,reg3,scale );
802 }
803 break;
804 default:
805 invalid( word1 );
806 return;
807 }
808 }
809
810
811 /************************************************/
812 /* Register Instruction Operand */
813 /************************************************/
814 static void
815 regop( mode, spec, reg, fp )
816 int mode, spec, reg, fp;
817 {
818 if ( fp ){ /* FLOATING POINT INSTRUCTION */
819 if ( mode == 1 ){ /* FP operand */
820 switch ( reg ){
821 case 0: (*info->fprintf_func)( stream, "fp0" );
822 break;
823 case 1: (*info->fprintf_func)( stream, "fp1" );
824 break;
825 case 2: (*info->fprintf_func)( stream, "fp2" );
826 break;
827 case 3: (*info->fprintf_func)( stream, "fp3" );
828 break;
829 case 16: (*info->fprintf_func)( stream, "0f0.0" );
830 break;
831 case 22: (*info->fprintf_func)( stream, "0f1.0" );
832 break;
833 default: (*info->fprintf_func)( stream, "?" );
834 break;
835 }
836 } else { /* Non-FP register */
837 (*info->fprintf_func)( stream, reg_names[reg] );
838 }
839 } else { /* NOT FLOATING POINT */
840 if ( mode == 1 ){ /* Literal */
841 (*info->fprintf_func)( stream, "%d", reg );
842 } else { /* Register */
843 if ( spec == 0 ){
844 (*info->fprintf_func)( stream, reg_names[reg] );
845 } else {
846 (*info->fprintf_func)( stream, "sf%d", reg );
847 }
848 }
849 }
850 }
851
852 /************************************************/
853 /* Register Instruction Destination Operand */
854 /************************************************/
855 static void
856 dstop( mode, reg, fp )
857 int mode, reg, fp;
858 {
859 /* 'dst' operand can't be a literal. On non-FP instructions, register
860 * mode is assumed and "m3" acts as if were "s3"; on FP-instructions,
861 * sf registers are not allowed so m3 acts normally.
862 */
863 if ( fp ){
864 regop( mode, 0, reg, fp );
865 } else {
866 regop( 0, mode, reg, fp );
867 }
868 }
869
870
871 static void
872 invalid( word1 )
873 int word1;
874 {
875 (*info->fprintf_func)( stream, ".word\t0x%08x", (unsigned) word1 );
876 }
877
878 static void
879 print_addr(a)
880 bfd_vma a;
881 {
882 (*info->print_address_func) (a, info);
883 }
884
885 static void
886 put_abs( word1, word2 )
887 unsigned long word1, word2;
888 {
889 #ifdef IN_GDB
890 return;
891 #else
892 int len;
893
894 switch ( (word1 >> 28) & 0xf ){
895 case 0x8:
896 case 0x9:
897 case 0xa:
898 case 0xb:
899 case 0xc:
900 /* MEM format instruction */
901 len = mem( 0, word1, word2, 1 );
902 break;
903 default:
904 len = 4;
905 break;
906 }
907
908 if ( len == 8 ){
909 (*info->fprintf_func)( stream, "%08x %08x\t", word1, word2 );
910 } else {
911 (*info->fprintf_func)( stream, "%08x \t", word1 );
912 }
913 ;
914
915 #endif
916 }
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