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Fix unwind section bug found by linux kernel.
[binutils.git] / gas / config / tc-ia64.c
blob517b6d3a38343b26817f074a1bfb7d256c397d49
1 /* tc-ia64.c -- Assembler for the HP/Intel IA-64 architecture.
2 Copyright (C) 1998, 1999, 2000 Free Software Foundation.
3 Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
4
5 This file is part of GAS, the GNU Assembler.
6
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
21
22 /*
23 TODO:
24
25 - optional operands
26 - directives:
27 .alias
28 .eb
29 .estate
30 .lb
31 .popsection
32 .previous
33 .psr
34 .pushsection
35 - labels are wrong if automatic alignment is introduced
36 (e.g., checkout the second real10 definition in test-data.s)
37 - DV-related stuff:
38 <reg>.safe_across_calls and any other DV-related directives I don't
39 have documentation for.
40 verify mod-sched-brs reads/writes are checked/marked (and other
41 notes)
42
43 */
44
45 #include "as.h"
46 #include "dwarf2dbg.h"
47 #include "subsegs.h"
48
49 #include "opcode/ia64.h"
50
51 #include "elf/ia64.h"
52
53 #define NELEMS(a) ((int) (sizeof (a)/sizeof ((a)[0])))
54 #define MIN(a,b) ((a) < (b) ? (a) : (b))
55
56 #define NUM_SLOTS 4
57 #define PREV_SLOT md.slot[(md.curr_slot + NUM_SLOTS - 1) % NUM_SLOTS]
58 #define CURR_SLOT md.slot[md.curr_slot]
59
60 #define O_pseudo_fixup (O_max + 1)
61
62 enum special_section
63 {
64 SPECIAL_SECTION_BSS = 0,
65 SPECIAL_SECTION_SBSS,
66 SPECIAL_SECTION_SDATA,
67 SPECIAL_SECTION_RODATA,
68 SPECIAL_SECTION_COMMENT,
69 SPECIAL_SECTION_UNWIND,
70 SPECIAL_SECTION_UNWIND_INFO
71 };
72
73 enum reloc_func
74 {
75 FUNC_FPTR_RELATIVE,
76 FUNC_GP_RELATIVE,
77 FUNC_LT_RELATIVE,
78 FUNC_PC_RELATIVE,
79 FUNC_PLT_RELATIVE,
80 FUNC_SEC_RELATIVE,
81 FUNC_SEG_RELATIVE,
82 FUNC_LTV_RELATIVE,
83 FUNC_LT_FPTR_RELATIVE,
84 };
85
86 enum reg_symbol
87 {
88 REG_GR = 0,
89 REG_FR = (REG_GR + 128),
90 REG_AR = (REG_FR + 128),
91 REG_CR = (REG_AR + 128),
92 REG_P = (REG_CR + 128),
93 REG_BR = (REG_P + 64),
94 REG_IP = (REG_BR + 8),
95 REG_CFM,
96 REG_PR,
97 REG_PR_ROT,
98 REG_PSR,
99 REG_PSR_L,
100 REG_PSR_UM,
101 /* The following are pseudo-registers for use by gas only. */
102 IND_CPUID,
103 IND_DBR,
104 IND_DTR,
105 IND_ITR,
106 IND_IBR,
107 IND_MEM,
108 IND_MSR,
109 IND_PKR,
110 IND_PMC,
111 IND_PMD,
112 IND_RR,
113 /* The following pseudo-registers are used for unwind directives only: */
114 REG_PSP,
115 REG_PRIUNAT,
116 REG_NUM
117 };
118
119 enum dynreg_type
120 {
121 DYNREG_GR = 0, /* dynamic general purpose register */
122 DYNREG_FR, /* dynamic floating point register */
123 DYNREG_PR, /* dynamic predicate register */
124 DYNREG_NUM_TYPES
125 };
126
127 /* On the ia64, we can't know the address of a text label until the
128 instructions are packed into a bundle. To handle this, we keep
129 track of the list of labels that appear in front of each
130 instruction. */
131 struct label_fix
132 {
133 struct label_fix *next;
134 struct symbol *sym;
135 };
136
137 extern int target_big_endian;
138
139 /* Characters which always start a comment. */
140 const char comment_chars[] = "";
141
142 /* Characters which start a comment at the beginning of a line. */
143 const char line_comment_chars[] = "#";
144
145 /* Characters which may be used to separate multiple commands on a
146 single line. */
147 const char line_separator_chars[] = ";";
148
149 /* Characters which are used to indicate an exponent in a floating
150 point number. */
151 const char EXP_CHARS[] = "eE";
152
153 /* Characters which mean that a number is a floating point constant,
154 as in 0d1.0. */
155 const char FLT_CHARS[] = "rRsSfFdDxXpP";
156
157 /* ia64-specific option processing: */
158
159 const char *md_shortopts = "M:N:x::";
160
161 struct option md_longopts[] =
162 {
163 #define OPTION_MCONSTANT_GP (OPTION_MD_BASE + 1)
164 {"mconstant-gp", no_argument, NULL, OPTION_MCONSTANT_GP},
165 #define OPTION_MAUTO_PIC (OPTION_MD_BASE + 2)
166 {"mauto-pic", no_argument, NULL, OPTION_MAUTO_PIC}
167 };
168
169 size_t md_longopts_size = sizeof (md_longopts);
170
171 static struct
172 {
173 struct hash_control *pseudo_hash; /* pseudo opcode hash table */
174 struct hash_control *reg_hash; /* register name hash table */
175 struct hash_control *dynreg_hash; /* dynamic register hash table */
176 struct hash_control *const_hash; /* constant hash table */
177 struct hash_control *entry_hash; /* code entry hint hash table */
178
179 symbolS *regsym[REG_NUM];
180
181 /* If X_op is != O_absent, the registername for the instruction's
182 qualifying predicate. If NULL, p0 is assumed for instructions
183 that are predicatable. */
184 expressionS qp;
185
186 unsigned int
187 manual_bundling : 1,
188 debug_dv: 1,
189 detect_dv: 1,
190 explicit_mode : 1, /* which mode we're in */
191 default_explicit_mode : 1, /* which mode is the default */
192 mode_explicitly_set : 1, /* was the current mode explicitly set? */
193 auto_align : 1;
194
195 /* Each bundle consists of up to three instructions. We keep
196 track of four most recent instructions so we can correctly set
197 the end_of_insn_group for the last instruction in a bundle. */
198 int curr_slot;
199 int num_slots_in_use;
200 struct slot
201 {
202 unsigned int
203 end_of_insn_group : 1,
204 manual_bundling_on : 1,
205 manual_bundling_off : 1;
206 signed char user_template; /* user-selected template, if any */
207 unsigned char qp_regno; /* qualifying predicate */
208 /* This duplicates a good fraction of "struct fix" but we
209 can't use a "struct fix" instead since we can't call
210 fix_new_exp() until we know the address of the instruction. */
211 int num_fixups;
212 struct insn_fix
213 {
214 bfd_reloc_code_real_type code;
215 enum ia64_opnd opnd; /* type of operand in need of fix */
216 unsigned int is_pcrel : 1; /* is operand pc-relative? */
217 expressionS expr; /* the value to be inserted */
218 }
219 fixup[2]; /* at most two fixups per insn */
220 struct ia64_opcode *idesc;
221 struct label_fix *label_fixups;
222 struct unw_rec_list *unwind_record; /* Unwind directive. */
223 expressionS opnd[6];
224 char *src_file;
225 unsigned int src_line;
226 struct dwarf2_line_info debug_line;
227 }
228 slot[NUM_SLOTS];
229
230 segT last_text_seg;
231
232 struct dynreg
233 {
234 struct dynreg *next; /* next dynamic register */
235 const char *name;
236 unsigned short base; /* the base register number */
237 unsigned short num_regs; /* # of registers in this set */
238 }
239 *dynreg[DYNREG_NUM_TYPES], in, loc, out, rot;
240
241 flagword flags; /* ELF-header flags */
242
243 struct mem_offset {
244 unsigned hint:1; /* is this hint currently valid? */
245 bfd_vma offset; /* mem.offset offset */
246 bfd_vma base; /* mem.offset base */
247 } mem_offset;
248
249 int path; /* number of alt. entry points seen */
250 const char **entry_labels; /* labels of all alternate paths in
251 the current DV-checking block. */
252 int maxpaths; /* size currently allocated for
253 entry_labels */
254 }
255 md;
256
257 /* application registers: */
258
259 #define AR_K0 0
260 #define AR_K7 7
261 #define AR_RSC 16
262 #define AR_BSP 17
263 #define AR_BSPSTORE 18
264 #define AR_RNAT 19
265 #define AR_UNAT 36
266 #define AR_FPSR 40
267 #define AR_ITC 44
268 #define AR_PFS 64
269 #define AR_LC 65
270
271 static const struct
272 {
273 const char *name;
274 int regnum;
275 }
276 ar[] =
277 {
278 {"ar.k0", 0}, {"ar.k1", 1}, {"ar.k2", 2}, {"ar.k3", 3},
279 {"ar.k4", 4}, {"ar.k5", 5}, {"ar.k6", 6}, {"ar.k7", 7},
280 {"ar.rsc", 16}, {"ar.bsp", 17},
281 {"ar.bspstore", 18}, {"ar.rnat", 19},
282 {"ar.fcr", 21}, {"ar.eflag", 24},
283 {"ar.csd", 25}, {"ar.ssd", 26},
284 {"ar.cflg", 27}, {"ar.fsr", 28},
285 {"ar.fir", 29}, {"ar.fdr", 30},
286 {"ar.ccv", 32}, {"ar.unat", 36},
287 {"ar.fpsr", 40}, {"ar.itc", 44},
288 {"ar.pfs", 64}, {"ar.lc", 65},
289 {"ar.ec", 66},
290 };
291
292 #define CR_IPSR 16
293 #define CR_ISR 17
294 #define CR_IIP 19
295 #define CR_IFA 20
296 #define CR_ITIR 21
297 #define CR_IIPA 22
298 #define CR_IFS 23
299 #define CR_IIM 24
300 #define CR_IHA 25
301 #define CR_IVR 65
302 #define CR_TPR 66
303 #define CR_EOI 67
304 #define CR_IRR0 68
305 #define CR_IRR3 71
306 #define CR_LRR0 80
307 #define CR_LRR1 81
308
309 /* control registers: */
310 static const struct
311 {
312 const char *name;
313 int regnum;
314 }
315 cr[] =
316 {
317 {"cr.dcr", 0},
318 {"cr.itm", 1},
319 {"cr.iva", 2},
320 {"cr.pta", 8},
321 {"cr.gpta", 9},
322 {"cr.ipsr", 16},
323 {"cr.isr", 17},
324 {"cr.iip", 19},
325 {"cr.ifa", 20},
326 {"cr.itir", 21},
327 {"cr.iipa", 22},
328 {"cr.ifs", 23},
329 {"cr.iim", 24},
330 {"cr.iha", 25},
331 {"cr.lid", 64},
332 {"cr.ivr", 65},
333 {"cr.tpr", 66},
334 {"cr.eoi", 67},
335 {"cr.irr0", 68},
336 {"cr.irr1", 69},
337 {"cr.irr2", 70},
338 {"cr.irr3", 71},
339 {"cr.itv", 72},
340 {"cr.pmv", 73},
341 {"cr.cmcv", 74},
342 {"cr.lrr0", 80},
343 {"cr.lrr1", 81}
344 };
345
346 #define PSR_MFL 4
347 #define PSR_IC 13
348 #define PSR_DFL 18
349 #define PSR_CPL 32
350
351 static const struct const_desc
352 {
353 const char *name;
354 valueT value;
355 }
356 const_bits[] =
357 {
358 /* PSR constant masks: */
359
360 /* 0: reserved */
361 {"psr.be", ((valueT) 1) << 1},
362 {"psr.up", ((valueT) 1) << 2},
363 {"psr.ac", ((valueT) 1) << 3},
364 {"psr.mfl", ((valueT) 1) << 4},
365 {"psr.mfh", ((valueT) 1) << 5},
366 /* 6-12: reserved */
367 {"psr.ic", ((valueT) 1) << 13},
368 {"psr.i", ((valueT) 1) << 14},
369 {"psr.pk", ((valueT) 1) << 15},
370 /* 16: reserved */
371 {"psr.dt", ((valueT) 1) << 17},
372 {"psr.dfl", ((valueT) 1) << 18},
373 {"psr.dfh", ((valueT) 1) << 19},
374 {"psr.sp", ((valueT) 1) << 20},
375 {"psr.pp", ((valueT) 1) << 21},
376 {"psr.di", ((valueT) 1) << 22},
377 {"psr.si", ((valueT) 1) << 23},
378 {"psr.db", ((valueT) 1) << 24},
379 {"psr.lp", ((valueT) 1) << 25},
380 {"psr.tb", ((valueT) 1) << 26},
381 {"psr.rt", ((valueT) 1) << 27},
382 /* 28-31: reserved */
383 /* 32-33: cpl (current privilege level) */
384 {"psr.is", ((valueT) 1) << 34},
385 {"psr.mc", ((valueT) 1) << 35},
386 {"psr.it", ((valueT) 1) << 36},
387 {"psr.id", ((valueT) 1) << 37},
388 {"psr.da", ((valueT) 1) << 38},
389 {"psr.dd", ((valueT) 1) << 39},
390 {"psr.ss", ((valueT) 1) << 40},
391 /* 41-42: ri (restart instruction) */
392 {"psr.ed", ((valueT) 1) << 43},
393 {"psr.bn", ((valueT) 1) << 44},
394 };
395
396 /* indirect register-sets/memory: */
397
398 static const struct
399 {
400 const char *name;
401 int regnum;
402 }
403 indirect_reg[] =
404 {
405 { "CPUID", IND_CPUID },
406 { "cpuid", IND_CPUID },
407 { "dbr", IND_DBR },
408 { "dtr", IND_DTR },
409 { "itr", IND_ITR },
410 { "ibr", IND_IBR },
411 { "msr", IND_MSR },
412 { "pkr", IND_PKR },
413 { "pmc", IND_PMC },
414 { "pmd", IND_PMD },
415 { "rr", IND_RR },
416 };
417
418 /* Pseudo functions used to indicate relocation types (these functions
419 start with an at sign (@). */
420 static struct
421 {
422 const char *name;
423 enum pseudo_type
424 {
425 PSEUDO_FUNC_NONE,
426 PSEUDO_FUNC_RELOC,
427 PSEUDO_FUNC_CONST,
428 PSEUDO_FUNC_REG,
429 PSEUDO_FUNC_FLOAT
430 }
431 type;
432 union
433 {
434 unsigned long ival;
435 symbolS *sym;
436 }
437 u;
438 }
439 pseudo_func[] =
440 {
441 /* reloc pseudo functions (these must come first!): */
442 { "fptr", PSEUDO_FUNC_RELOC },
443 { "gprel", PSEUDO_FUNC_RELOC },
444 { "ltoff", PSEUDO_FUNC_RELOC },
445 { "pcrel", PSEUDO_FUNC_RELOC },
446 { "pltoff", PSEUDO_FUNC_RELOC },
447 { "secrel", PSEUDO_FUNC_RELOC },
448 { "segrel", PSEUDO_FUNC_RELOC },
449 { "ltv", PSEUDO_FUNC_RELOC },
450 { 0, }, /* placeholder for FUNC_LT_FPTR_RELATIVE */
451
452 /* mbtype4 constants: */
453 { "alt", PSEUDO_FUNC_CONST, { 0xa } },
454 { "brcst", PSEUDO_FUNC_CONST, { 0x0 } },
455 { "mix", PSEUDO_FUNC_CONST, { 0x8 } },
456 { "rev", PSEUDO_FUNC_CONST, { 0xb } },
457 { "shuf", PSEUDO_FUNC_CONST, { 0x9 } },
458
459 /* fclass constants: */
460 { "nat", PSEUDO_FUNC_CONST, { 0x100 } },
461 { "qnan", PSEUDO_FUNC_CONST, { 0x080 } },
462 { "snan", PSEUDO_FUNC_CONST, { 0x040 } },
463 { "pos", PSEUDO_FUNC_CONST, { 0x001 } },
464 { "neg", PSEUDO_FUNC_CONST, { 0x002 } },
465 { "zero", PSEUDO_FUNC_CONST, { 0x004 } },
466 { "unorm", PSEUDO_FUNC_CONST, { 0x008 } },
467 { "norm", PSEUDO_FUNC_CONST, { 0x010 } },
468 { "inf", PSEUDO_FUNC_CONST, { 0x020 } },
469
470 { "natval", PSEUDO_FUNC_CONST, { 0x100 } }, /* old usage */
471
472 /* unwind-related constants: */
473 { "svr4", PSEUDO_FUNC_CONST, { 0 } },
474 { "hpux", PSEUDO_FUNC_CONST, { 1 } },
475 { "nt", PSEUDO_FUNC_CONST, { 2 } },
476
477 /* unwind-related registers: */
478 { "priunat",PSEUDO_FUNC_REG, { REG_PRIUNAT } }
479 };
480
481 /* 41-bit nop opcodes (one per unit): */
482 static const bfd_vma nop[IA64_NUM_UNITS] =
483 {
484 0x0000000000LL, /* NIL => break 0 */
485 0x0008000000LL, /* I-unit nop */
486 0x0008000000LL, /* M-unit nop */
487 0x4000000000LL, /* B-unit nop */
488 0x0008000000LL, /* F-unit nop */
489 0x0008000000LL, /* L-"unit" nop */
490 0x0008000000LL, /* X-unit nop */
491 };
492
493 /* Can't be `const' as it's passed to input routines (which have the
494 habit of setting temporary sentinels. */
495 static char special_section_name[][20] =
496 {
497 {".bss"}, {".sbss"}, {".sdata"}, {".rodata"}, {".comment"},
498 {".IA_64.unwind"}, {".IA_64.unwind_info"}
499 };
500
501 /* The best template for a particular sequence of up to three
502 instructions: */
503 #define N IA64_NUM_TYPES
504 static unsigned char best_template[N][N][N];
505 #undef N
506
507 /* Resource dependencies currently in effect */
508 static struct rsrc {
509 int depind; /* dependency index */
510 const struct ia64_dependency *dependency; /* actual dependency */
511 unsigned specific:1, /* is this a specific bit/regno? */
512 link_to_qp_branch:1; /* will a branch on the same QP clear it?*/
513 int index; /* specific regno/bit within dependency */
514 int note; /* optional qualifying note (0 if none) */
515 #define STATE_NONE 0
516 #define STATE_STOP 1
517 #define STATE_SRLZ 2
518 int insn_srlz; /* current insn serialization state */
519 int data_srlz; /* current data serialization state */
520 int qp_regno; /* qualifying predicate for this usage */
521 char *file; /* what file marked this dependency */
522 int line; /* what line marked this dependency */
523 struct mem_offset mem_offset; /* optional memory offset hint */
524 int path; /* corresponding code entry index */
525 } *regdeps = NULL;
526 static int regdepslen = 0;
527 static int regdepstotlen = 0;
528 static const char *dv_mode[] = { "RAW", "WAW", "WAR" };
529 static const char *dv_sem[] = { "none", "implied", "impliedf",
530 "data", "instr", "specific", "other" };
531
532 /* Current state of PR mutexation */
533 static struct qpmutex {
534 valueT prmask;
535 int path;
536 } *qp_mutexes = NULL; /* QP mutex bitmasks */
537 static int qp_mutexeslen = 0;
538 static int qp_mutexestotlen = 0;
539 static valueT qp_safe_across_calls = 0;
540
541 /* Current state of PR implications */
542 static struct qp_imply {
543 unsigned p1:6;
544 unsigned p2:6;
545 unsigned p2_branched:1;
546 int path;
547 } *qp_implies = NULL;
548 static int qp_implieslen = 0;
549 static int qp_impliestotlen = 0;
550
551 /* Keep track of static GR values so that indirect register usage can
552 sometimes be tracked. */
553 static struct gr {
554 unsigned known:1;
555 int path;
556 valueT value;
557 } gr_values[128] = {{ 1, 0 }};
558
559 /* These are the routines required to output the various types of
560 unwind records. */
561
562 typedef struct unw_rec_list {
563 unwind_record r;
564 unsigned long slot_number;
565 struct unw_rec_list *next;
566 } unw_rec_list;
567
568 #define SLOT_NUM_NOT_SET -1
569
570 static struct
571 {
572 unsigned long next_slot_number;
573
574 /* Maintain a list of unwind entries for the current function. */
575 unw_rec_list *list;
576 unw_rec_list *tail;
577
578 /* Any unwind entires that should be attached to the current slot
579 that an insn is being constructed for. */
580 unw_rec_list *current_entry;
581
582 /* These are used to create the unwind table entry for this function. */
583 symbolS *proc_start;
584 symbolS *proc_end;
585 symbolS *info; /* pointer to unwind info */
586 symbolS *personality_routine;
587
588 /* TRUE if processing unwind directives in a prologue region. */
589 int prologue;
590 int prologue_mask;
591 } unwind;
592
593 typedef void (*vbyte_func) PARAMS ((int, char *, char *));
594
595 /* Forward delarations: */
596 static int ar_is_in_integer_unit PARAMS ((int regnum));
597 static void set_section PARAMS ((char *name));
598 static unsigned int set_regstack PARAMS ((unsigned int, unsigned int,
599 unsigned int, unsigned int));
600 static void dot_radix PARAMS ((int));
601 static void dot_special_section PARAMS ((int));
602 static void dot_proc PARAMS ((int));
603 static void dot_fframe PARAMS ((int));
604 static void dot_vframe PARAMS ((int));
605 static void dot_vframesp PARAMS ((int));
606 static void dot_vframepsp PARAMS ((int));
607 static void dot_save PARAMS ((int));
608 static void dot_restore PARAMS ((int));
609 static void dot_restorereg PARAMS ((int));
610 static void dot_restorereg_p PARAMS ((int));
611 static void dot_handlerdata PARAMS ((int));
612 static void dot_unwentry PARAMS ((int));
613 static void dot_altrp PARAMS ((int));
614 static void dot_savemem PARAMS ((int));
615 static void dot_saveg PARAMS ((int));
616 static void dot_savef PARAMS ((int));
617 static void dot_saveb PARAMS ((int));
618 static void dot_savegf PARAMS ((int));
619 static void dot_spill PARAMS ((int));
620 static void dot_spillreg PARAMS ((int));
621 static void dot_spillmem PARAMS ((int));
622 static void dot_spillreg_p PARAMS ((int));
623 static void dot_spillmem_p PARAMS ((int));
624 static void dot_label_state PARAMS ((int));
625 static void dot_copy_state PARAMS ((int));
626 static void dot_unwabi PARAMS ((int));
627 static void dot_personality PARAMS ((int));
628 static void dot_body PARAMS ((int));
629 static void dot_prologue PARAMS ((int));
630 static void dot_endp PARAMS ((int));
631 static void dot_template PARAMS ((int));
632 static void dot_regstk PARAMS ((int));
633 static void dot_rot PARAMS ((int));
634 static void dot_byteorder PARAMS ((int));
635 static void dot_psr PARAMS ((int));
636 static void dot_alias PARAMS ((int));
637 static void dot_ln PARAMS ((int));
638 static char *parse_section_name PARAMS ((void));
639 static void dot_xdata PARAMS ((int));
640 static void stmt_float_cons PARAMS ((int));
641 static void stmt_cons_ua PARAMS ((int));
642 static void dot_xfloat_cons PARAMS ((int));
643 static void dot_xstringer PARAMS ((int));
644 static void dot_xdata_ua PARAMS ((int));
645 static void dot_xfloat_cons_ua PARAMS ((int));
646 static void print_prmask PARAMS ((valueT mask));
647 static void dot_pred_rel PARAMS ((int));
648 static void dot_reg_val PARAMS ((int));
649 static void dot_dv_mode PARAMS ((int));
650 static void dot_entry PARAMS ((int));
651 static void dot_mem_offset PARAMS ((int));
652 static void add_unwind_entry PARAMS((unw_rec_list *ptr));
653 static symbolS* declare_register PARAMS ((const char *name, int regnum));
654 static void declare_register_set PARAMS ((const char *, int, int));
655 static unsigned int operand_width PARAMS ((enum ia64_opnd));
656 static int operand_match PARAMS ((const struct ia64_opcode *idesc,
657 int index, expressionS *e));
658 static int parse_operand PARAMS ((expressionS *e));
659 static struct ia64_opcode * parse_operands PARAMS ((struct ia64_opcode *));
660 static void build_insn PARAMS ((struct slot *, bfd_vma *));
661 static void emit_one_bundle PARAMS ((void));
662 static void fix_insn PARAMS ((fixS *, const struct ia64_operand *, valueT));
663 static bfd_reloc_code_real_type ia64_gen_real_reloc_type PARAMS ((struct symbol *sym,
664 bfd_reloc_code_real_type r_type));
665 static void insn_group_break PARAMS ((int, int, int));
666 static void mark_resource PARAMS ((struct ia64_opcode *, const struct ia64_dependency *,
667 struct rsrc *, int depind, int path));
668 static void add_qp_mutex PARAMS((valueT mask));
669 static void add_qp_imply PARAMS((int p1, int p2));
670 static void clear_qp_branch_flag PARAMS((valueT mask));
671 static void clear_qp_mutex PARAMS((valueT mask));
672 static void clear_qp_implies PARAMS((valueT p1_mask, valueT p2_mask));
673 static void clear_register_values PARAMS ((void));
674 static void print_dependency PARAMS ((const char *action, int depind));
675 static void instruction_serialization PARAMS ((void));
676 static void data_serialization PARAMS ((void));
677 static void remove_marked_resource PARAMS ((struct rsrc *));
678 static int is_conditional_branch PARAMS ((struct ia64_opcode *));
679 static int is_taken_branch PARAMS ((struct ia64_opcode *));
680 static int is_interruption_or_rfi PARAMS ((struct ia64_opcode *));
681 static int depends_on PARAMS ((int, struct ia64_opcode *));
682 static int specify_resource PARAMS ((const struct ia64_dependency *,
683 struct ia64_opcode *, int, struct rsrc [], int, int));
684 static int check_dv PARAMS((struct ia64_opcode *idesc));
685 static void check_dependencies PARAMS((struct ia64_opcode *));
686 static void mark_resources PARAMS((struct ia64_opcode *));
687 static void update_dependencies PARAMS((struct ia64_opcode *));
688 static void note_register_values PARAMS((struct ia64_opcode *));
689 static int qp_mutex PARAMS ((int, int, int));
690 static int resources_match PARAMS ((struct rsrc *, struct ia64_opcode *, int, int, int));
691 static void output_vbyte_mem PARAMS ((int, char *, char *));
692 static void count_output PARAMS ((int, char *, char *));
693 static void output_R1_format PARAMS ((vbyte_func, unw_record_type, int));
694 static void output_R2_format PARAMS ((vbyte_func, int, int, unsigned long));
695 static void output_R3_format PARAMS ((vbyte_func, unw_record_type, unsigned long));
696 static void output_P1_format PARAMS ((vbyte_func, int));
697 static void output_P2_format PARAMS ((vbyte_func, int, int));
698 static void output_P3_format PARAMS ((vbyte_func, unw_record_type, int));
699 static void output_P4_format PARAMS ((vbyte_func, unsigned char *, unsigned long));
700 static void output_P5_format PARAMS ((vbyte_func, int, unsigned long));
701 static void output_P6_format PARAMS ((vbyte_func, unw_record_type, int));
702 static void output_P7_format PARAMS ((vbyte_func, unw_record_type, unsigned long, unsigned long));
703 static void output_P8_format PARAMS ((vbyte_func, unw_record_type, unsigned long));
704 static void output_P9_format PARAMS ((vbyte_func, int, int));
705 static void output_P10_format PARAMS ((vbyte_func, int, int));
706 static void output_B1_format PARAMS ((vbyte_func, unw_record_type, unsigned long));
707 static void output_B2_format PARAMS ((vbyte_func, unsigned long, unsigned long));
708 static void output_B3_format PARAMS ((vbyte_func, unsigned long, unsigned long));
709 static void output_B4_format PARAMS ((vbyte_func, unw_record_type, unsigned long));
710 static char format_ab_reg PARAMS ((int, int));
711 static void output_X1_format PARAMS ((vbyte_func, unw_record_type, int, int, unsigned long,
712 unsigned long));
713 static void output_X2_format PARAMS ((vbyte_func, int, int, int, int, int, unsigned long));
714 static void output_X3_format PARAMS ((vbyte_func, unw_record_type, int, int, int, unsigned long,
715 unsigned long));
716 static void output_X4_format PARAMS ((vbyte_func, int, int, int, int, int, int, unsigned long));
717 static void free_list_records PARAMS ((unw_rec_list *));
718 static unw_rec_list *output_prologue PARAMS ((void));
719 static unw_rec_list *output_prologue_gr PARAMS ((unsigned int, unsigned int));
720 static unw_rec_list *output_body PARAMS ((void));
721 static unw_rec_list *output_mem_stack_f PARAMS ((unsigned int));
722 static unw_rec_list *output_mem_stack_v PARAMS ((void));
723 static unw_rec_list *output_psp_gr PARAMS ((unsigned int));
724 static unw_rec_list *output_psp_sprel PARAMS ((unsigned int));
725 static unw_rec_list *output_rp_when PARAMS ((void));
726 static unw_rec_list *output_rp_gr PARAMS ((unsigned int));
727 static unw_rec_list *output_rp_br PARAMS ((unsigned int));
728 static unw_rec_list *output_rp_psprel PARAMS ((unsigned int));
729 static unw_rec_list *output_rp_sprel PARAMS ((unsigned int));
730 static unw_rec_list *output_pfs_when PARAMS ((void));
731 static unw_rec_list *output_pfs_gr PARAMS ((unsigned int));
732 static unw_rec_list *output_pfs_psprel PARAMS ((unsigned int));
733 static unw_rec_list *output_pfs_sprel PARAMS ((unsigned int));
734 static unw_rec_list *output_preds_when PARAMS ((void));
735 static unw_rec_list *output_preds_gr PARAMS ((unsigned int));
736 static unw_rec_list *output_preds_psprel PARAMS ((unsigned int));
737 static unw_rec_list *output_preds_sprel PARAMS ((unsigned int));
738 static unw_rec_list *output_fr_mem PARAMS ((unsigned int));
739 static unw_rec_list *output_frgr_mem PARAMS ((unsigned int, unsigned int));
740 static unw_rec_list *output_gr_gr PARAMS ((unsigned int, unsigned int));
741 static unw_rec_list *output_gr_mem PARAMS ((unsigned int));
742 static unw_rec_list *output_br_mem PARAMS ((unsigned int));
743 static unw_rec_list *output_br_gr PARAMS ((unsigned int, unsigned int));
744 static unw_rec_list *output_spill_base PARAMS ((unsigned int));
745 static unw_rec_list *output_unat_when PARAMS ((void));
746 static unw_rec_list *output_unat_gr PARAMS ((unsigned int));
747 static unw_rec_list *output_unat_psprel PARAMS ((unsigned int));
748 static unw_rec_list *output_unat_sprel PARAMS ((unsigned int));
749 static unw_rec_list *output_lc_when PARAMS ((void));
750 static unw_rec_list *output_lc_gr PARAMS ((unsigned int));
751 static unw_rec_list *output_lc_psprel PARAMS ((unsigned int));
752 static unw_rec_list *output_lc_sprel PARAMS ((unsigned int));
753 static unw_rec_list *output_fpsr_when PARAMS ((void));
754 static unw_rec_list *output_fpsr_gr PARAMS ((unsigned int));
755 static unw_rec_list *output_fpsr_psprel PARAMS ((unsigned int));
756 static unw_rec_list *output_fpsr_sprel PARAMS ((unsigned int));
757 static unw_rec_list *output_priunat_when_gr PARAMS ((void));
758 static unw_rec_list *output_priunat_when_mem PARAMS ((void));
759 static unw_rec_list *output_priunat_gr PARAMS ((unsigned int));
760 static unw_rec_list *output_priunat_psprel PARAMS ((unsigned int));
761 static unw_rec_list *output_priunat_sprel PARAMS ((unsigned int));
762 static unw_rec_list *output_bsp_when PARAMS ((void));
763 static unw_rec_list *output_bsp_gr PARAMS ((unsigned int));
764 static unw_rec_list *output_bsp_psprel PARAMS ((unsigned int));
765 static unw_rec_list *output_bsp_sprel PARAMS ((unsigned int));
766 static unw_rec_list *output_bspstore_when PARAMS ((void));
767 static unw_rec_list *output_bspstore_gr PARAMS ((unsigned int));
768 static unw_rec_list *output_bspstore_psprel PARAMS ((unsigned int));
769 static unw_rec_list *output_bspstore_sprel PARAMS ((unsigned int));
770 static unw_rec_list *output_rnat_when PARAMS ((void));
771 static unw_rec_list *output_rnat_gr PARAMS ((unsigned int));
772 static unw_rec_list *output_rnat_psprel PARAMS ((unsigned int));
773 static unw_rec_list *output_rnat_sprel PARAMS ((unsigned int));
774 static unw_rec_list *output_unwabi PARAMS ((unsigned long, unsigned long));
775 static unw_rec_list *output_epilogue PARAMS ((unsigned long));
776 static unw_rec_list *output_label_state PARAMS ((unsigned long));
777 static unw_rec_list *output_copy_state PARAMS ((unsigned long));
778 static unw_rec_list *output_spill_psprel PARAMS ((unsigned int, unsigned int, unsigned int));
779 static unw_rec_list *output_spill_sprel PARAMS ((unsigned int, unsigned int, unsigned int));
780 static unw_rec_list *output_spill_psprel_p PARAMS ((unsigned int, unsigned int, unsigned int,
781 unsigned int));
782 static unw_rec_list *output_spill_sprel_p PARAMS ((unsigned int, unsigned int, unsigned int,
783 unsigned int));
784 static unw_rec_list *output_spill_reg PARAMS ((unsigned int, unsigned int, unsigned int,
785 unsigned int));
786 static unw_rec_list *output_spill_reg_p PARAMS ((unsigned int, unsigned int, unsigned int,
787 unsigned int, unsigned int));
788 static void process_one_record PARAMS ((unw_rec_list *, vbyte_func));
789 static void process_unw_records PARAMS ((unw_rec_list *, vbyte_func));
790 static int calc_record_size PARAMS ((unw_rec_list *));
791 static void set_imask PARAMS ((unw_rec_list *, unsigned long, unsigned long, unsigned int));
792 static int count_bits PARAMS ((unsigned long));
793 static unsigned long slot_index PARAMS ((unsigned long, unsigned long));
794 static void fixup_unw_records PARAMS ((unw_rec_list *));
795 static int output_unw_records PARAMS ((unw_rec_list *, void **));
796 static int convert_expr_to_ab_reg PARAMS ((expressionS *, unsigned int *, unsigned int *));
797 static int convert_expr_to_xy_reg PARAMS ((expressionS *, unsigned int *, unsigned int *));
798 static int generate_unwind_image PARAMS ((void));
799
800 /* Determine if application register REGNUM resides in the integer
801 unit (as opposed to the memory unit). */
802 static int
803 ar_is_in_integer_unit (reg)
804 int reg;
805 {
806 reg -= REG_AR;
807
808 return (reg == 64 /* pfs */
809 || reg == 65 /* lc */
810 || reg == 66 /* ec */
811 /* ??? ias accepts and puts these in the integer unit. */
812 || (reg >= 112 && reg <= 127));
813 }
814
815 /* Switch to section NAME and create section if necessary. It's
816 rather ugly that we have to manipulate input_line_pointer but I
817 don't see any other way to accomplish the same thing without
818 changing obj-elf.c (which may be the Right Thing, in the end). */
819 static void
820 set_section (name)
821 char *name;
822 {
823 char *saved_input_line_pointer;
824
825 saved_input_line_pointer = input_line_pointer;
826 input_line_pointer = name;
827 obj_elf_section (0);
828 input_line_pointer = saved_input_line_pointer;
829 }
830
831 /* Map SHF_IA_64_SHORT to SEC_SMALL_DATA. */
832
833 flagword
834 ia64_elf_section_flags (flags, attr, type)
835 flagword flags;
836 int attr, type;
837 {
838 if (attr & SHF_IA_64_SHORT)
839 flags |= SEC_SMALL_DATA;
840 return flags;
841 }
842
843 static unsigned int
844 set_regstack (ins, locs, outs, rots)
845 unsigned int ins, locs, outs, rots;
846 {
847 unsigned int sof; /* size of frame */
848
849 sof = ins + locs + outs;
850 if (sof > 96)
851 {
852 as_bad ("Size of frame exceeds maximum of 96 registers");
853 return 0;
854 }
855 if (rots > sof)
856 {
857 as_warn ("Size of rotating registers exceeds frame size");
858 return 0;
859 }
860 md.in.base = REG_GR + 32;
861 md.loc.base = md.in.base + ins;
862 md.out.base = md.loc.base + locs;
863
864 md.in.num_regs = ins;
865 md.loc.num_regs = locs;
866 md.out.num_regs = outs;
867 md.rot.num_regs = rots;
868 return sof;
869 }
870
871 void
872 ia64_flush_insns ()
873 {
874 struct label_fix *lfix;
875 segT saved_seg;
876 subsegT saved_subseg;
877
878 if (!md.last_text_seg)
879 return;
880
881 saved_seg = now_seg;
882 saved_subseg = now_subseg;
883
884 subseg_set (md.last_text_seg, 0);
885
886 while (md.num_slots_in_use > 0)
887 emit_one_bundle (); /* force out queued instructions */
888
889 /* In case there are labels following the last instruction, resolve
890 those now: */
891 for (lfix = CURR_SLOT.label_fixups; lfix; lfix = lfix->next)
892 {
893 S_SET_VALUE (lfix->sym, frag_now_fix ());
894 symbol_set_frag (lfix->sym, frag_now);
895 }
896 CURR_SLOT.label_fixups = 0;
897
898 subseg_set (saved_seg, saved_subseg);
899 }
900
901 void
902 ia64_do_align (nbytes)
903 int nbytes;
904 {
905 char *saved_input_line_pointer = input_line_pointer;
906
907 input_line_pointer = "";
908 s_align_bytes (nbytes);
909 input_line_pointer = saved_input_line_pointer;
910 }
911
912 void
913 ia64_cons_align (nbytes)
914 int nbytes;
915 {
916 if (md.auto_align)
917 {
918 char *saved_input_line_pointer = input_line_pointer;
919 input_line_pointer = "";
920 s_align_bytes (nbytes);
921 input_line_pointer = saved_input_line_pointer;
922 }
923 }
924
925 /* Output COUNT bytes to a memory location. */
926 static unsigned char *vbyte_mem_ptr = NULL;
927
928 void
929 output_vbyte_mem (count, ptr, comment)
930 int count;
931 char *ptr;
932 char *comment;
933 {
934 int x;
935 if (vbyte_mem_ptr == NULL)
936 abort ();
937
938 if (count == 0)
939 return;
940 for (x = 0; x < count; x++)
941 *(vbyte_mem_ptr++) = ptr[x];
942 }
943
944 /* Count the number of bytes required for records. */
945 static int vbyte_count = 0;
946 void
947 count_output (count, ptr, comment)
948 int count;
949 char *ptr;
950 char *comment;
951 {
952 vbyte_count += count;
953 }
954
955 static void
956 output_R1_format (f, rtype, rlen)
957 vbyte_func f;
958 unw_record_type rtype;
959 int rlen;
960 {
961 int r = 0;
962 char byte;
963 if (rlen > 0x1f)
964 {
965 output_R3_format (f, rtype, rlen);
966 return;
967 }
968
969 if (rtype == body)
970 r = 1;
971 else if (rtype != prologue)
972 as_bad ("record type is not valid");
973
974 byte = UNW_R1 | (r << 5) | (rlen & 0x1f);
975 (*f) (1, &byte, NULL);
976 }
977
978 static void
979 output_R2_format (f, mask, grsave, rlen)
980 vbyte_func f;
981 int mask, grsave;
982 unsigned long rlen;
983 {
984 char bytes[20];
985 int count = 2;
986 mask = (mask & 0x0f);
987 grsave = (grsave & 0x7f);
988
989 bytes[0] = (UNW_R2 | (mask >> 1));
990 bytes[1] = (((mask & 0x01) << 7) | grsave);
991 count += output_leb128 (bytes + 2, rlen, 0);
992 (*f) (count, bytes, NULL);
993 }
994
995 static void
996 output_R3_format (f, rtype, rlen)
997 vbyte_func f;
998 unw_record_type rtype;
999 unsigned long rlen;
1000 {
1001 int r = 0, count;
1002 char bytes[20];
1003 if (rlen <= 0x1f)
1004 {
1005 output_R1_format (f, rtype, rlen);
1006 return;
1007 }
1008
1009 if (rtype == body)
1010 r = 1;
1011 else if (rtype != prologue)
1012 as_bad ("record type is not valid");
1013 bytes[0] = (UNW_R3 | r);
1014 count = output_leb128 (bytes + 1, rlen, 0);
1015 (*f) (count + 1, bytes, NULL);
1016 }
1017
1018 static void
1019 output_P1_format (f, brmask)
1020 vbyte_func f;
1021 int brmask;
1022 {
1023 char byte;
1024 byte = UNW_P1 | (brmask & 0x1f);
1025 (*f) (1, &byte, NULL);
1026 }
1027
1028 static void
1029 output_P2_format (f, brmask, gr)
1030 vbyte_func f;
1031 int brmask;
1032 int gr;
1033 {
1034 char bytes[2];
1035 brmask = (brmask & 0x1f);
1036 bytes[0] = UNW_P2 | (brmask >> 1);
1037 bytes[1] = (((brmask & 1) << 7) | gr);
1038 (*f) (2, bytes, NULL);
1039 }
1040
1041 static void
1042 output_P3_format (f, rtype, reg)
1043 vbyte_func f;
1044 unw_record_type rtype;
1045 int reg;
1046 {
1047 char bytes[2];
1048 int r = 0;
1049 reg = (reg & 0x7f);
1050 switch (rtype)
1051 {
1052 case psp_gr:
1053 r = 0;
1054 break;
1055 case rp_gr:
1056 r = 1;
1057 break;
1058 case pfs_gr:
1059 r = 2;
1060 break;
1061 case preds_gr:
1062 r = 3;
1063 break;
1064 case unat_gr:
1065 r = 4;
1066 break;
1067 case lc_gr:
1068 r = 5;
1069 break;
1070 case rp_br:
1071 r = 6;
1072 break;
1073 case rnat_gr:
1074 r = 7;
1075 break;
1076 case bsp_gr:
1077 r = 8;
1078 break;
1079 case bspstore_gr:
1080 r = 9;
1081 break;
1082 case fpsr_gr:
1083 r = 10;
1084 break;
1085 case priunat_gr:
1086 r = 11;
1087 break;
1088 default:
1089 as_bad ("Invalid record type for P3 format.");
1090 }
1091 bytes[0] = (UNW_P3 | (r >> 1));
1092 bytes[1] = (((r & 1) << 7) | reg);
1093 (*f) (2, bytes, NULL);
1094 }
1095
1096
1097 static void
1098 output_P4_format (f, imask, imask_size)
1099 vbyte_func f;
1100 unsigned char *imask;
1101 unsigned long imask_size;
1102 {
1103 imask[0] = UNW_P4;
1104 (*f) (imask_size, imask, NULL);
1105 }
1106
1107 static void
1108 output_P5_format (f, grmask, frmask)
1109 vbyte_func f;
1110 int grmask;
1111 unsigned long frmask;
1112 {
1113 char bytes[4];
1114 grmask = (grmask & 0x0f);
1115
1116 bytes[0] = UNW_P5;
1117 bytes[1] = ((grmask << 4) | ((frmask & 0x000f0000) >> 16));
1118 bytes[2] = ((frmask & 0x0000ff00) >> 8);
1119 bytes[3] = (frmask & 0x000000ff);
1120 (*f) (4, bytes, NULL);
1121 }
1122
1123 static void
1124 output_P6_format (f, rtype, rmask)
1125 vbyte_func f;
1126 unw_record_type rtype;
1127 int rmask;
1128 {
1129 char byte;
1130 int r = 0;
1131
1132 if (rtype == gr_mem)
1133 r = 1;
1134 else if (rtype != fr_mem)
1135 as_bad ("Invalid record type for format P6");
1136 byte = (UNW_P6 | (r << 4) | (rmask & 0x0f));
1137 (*f) (1, &byte, NULL);
1138 }
1139
1140 static void
1141 output_P7_format (f, rtype, w1, w2)
1142 vbyte_func f;
1143 unw_record_type rtype;
1144 unsigned long w1;
1145 unsigned long w2;
1146 {
1147 char bytes[20];
1148 int count = 1;
1149 int r = 0;
1150 count += output_leb128 (bytes + 1, w1, 0);
1151 switch (rtype)
1152 {
1153 case mem_stack_f:
1154 r = 0;
1155 count += output_leb128 (bytes + count, w2 >> 4, 0);
1156 break;
1157 case mem_stack_v:
1158 r = 1;
1159 break;
1160 case spill_base:
1161 r = 2;
1162 break;
1163 case psp_sprel:
1164 r = 3;
1165 break;
1166 case rp_when:
1167 r = 4;
1168 break;
1169 case rp_psprel:
1170 r = 5;
1171 break;
1172 case pfs_when:
1173 r = 6;
1174 break;
1175 case pfs_psprel:
1176 r = 7;
1177 break;
1178 case preds_when:
1179 r = 8;
1180 break;
1181 case preds_psprel:
1182 r = 9;
1183 break;
1184 case lc_when:
1185 r = 10;
1186 break;
1187 case lc_psprel:
1188 r = 11;
1189 break;
1190 case unat_when:
1191 r = 12;
1192 break;
1193 case unat_psprel:
1194 r = 13;
1195 break;
1196 case fpsr_when:
1197 r = 14;
1198 break;
1199 case fpsr_psprel:
1200 r = 15;
1201 break;
1202 default:
1203 break;
1204 }
1205 bytes[0] = (UNW_P7 | r);
1206 (*f) (count, bytes, NULL);
1207 }
1208
1209 static void
1210 output_P8_format (f, rtype, t)
1211 vbyte_func f;
1212 unw_record_type rtype;
1213 unsigned long t;
1214 {
1215 char bytes[20];
1216 int r = 0;
1217 int count = 2;
1218 bytes[0] = UNW_P8;
1219 switch (rtype)
1220 {
1221 case rp_sprel:
1222 r = 1;
1223 break;
1224 case pfs_sprel:
1225 r = 2;
1226 break;
1227 case preds_sprel:
1228 r = 3;
1229 break;
1230 case lc_sprel:
1231 r = 4;
1232 break;
1233 case unat_sprel:
1234 r = 5;
1235 break;
1236 case fpsr_sprel:
1237 r = 6;
1238 break;
1239 case bsp_when:
1240 r = 7;
1241 break;
1242 case bsp_psprel:
1243 r = 8;
1244 break;
1245 case bsp_sprel:
1246 r = 9;
1247 break;
1248 case bspstore_when:
1249 r = 10;
1250 break;
1251 case bspstore_psprel:
1252 r = 11;
1253 break;
1254 case bspstore_sprel:
1255 r = 12;
1256 break;
1257 case rnat_when:
1258 r = 13;
1259 break;
1260 case rnat_psprel:
1261 r = 14;
1262 break;
1263 case rnat_sprel:
1264 r = 15;
1265 break;
1266 case priunat_when_gr:
1267 r = 16;
1268 break;
1269 case priunat_psprel:
1270 r = 17;
1271 break;
1272 case priunat_sprel:
1273 r = 18;
1274 break;
1275 case priunat_when_mem:
1276 r = 19;
1277 break;
1278 default:
1279 break;
1280 }
1281 bytes[1] = r;
1282 count += output_leb128 (bytes + 2, t, 0);
1283 (*f) (count, bytes, NULL);
1284 }
1285
1286 static void
1287 output_P9_format (f, grmask, gr)
1288 vbyte_func f;
1289 int grmask;
1290 int gr;
1291 {
1292 char bytes[3];
1293 bytes[0] = UNW_P9;
1294 bytes[1] = (grmask & 0x0f);
1295 bytes[2] = (gr & 0x7f);
1296 (*f) (3, bytes, NULL);
1297 }
1298
1299 static void
1300 output_P10_format (f, abi, context)
1301 vbyte_func f;
1302 int abi;
1303 int context;
1304 {
1305 char bytes[3];
1306 bytes[0] = UNW_P10;
1307 bytes[1] = (abi & 0xff);
1308 bytes[2] = (context & 0xff);
1309 (*f) (3, bytes, NULL);
1310 }
1311
1312 static void
1313 output_B1_format (f, rtype, label)
1314 vbyte_func f;
1315 unw_record_type rtype;
1316 unsigned long label;
1317 {
1318 char byte;
1319 int r = 0;
1320 if (label > 0x1f)
1321 {
1322 output_B4_format (f, rtype, label);
1323 return;
1324 }
1325 if (rtype == copy_state)
1326 r = 1;
1327 else if (rtype != label_state)
1328 as_bad ("Invalid record type for format B1");
1329
1330 byte = (UNW_B1 | (r << 5) | (label & 0x1f));
1331 (*f) (1, &byte, NULL);
1332 }
1333
1334 static void
1335 output_B2_format (f, ecount, t)
1336 vbyte_func f;
1337 unsigned long ecount;
1338 unsigned long t;
1339 {
1340 char bytes[20];
1341 int count = 1;
1342 if (ecount > 0x1f)
1343 {
1344 output_B3_format (f, ecount, t);
1345 return;
1346 }
1347 bytes[0] = (UNW_B2 | (ecount & 0x1f));
1348 count += output_leb128 (bytes + 1, t, 0);
1349 (*f) (count, bytes, NULL);
1350 }
1351
1352 static void
1353 output_B3_format (f, ecount, t)
1354 vbyte_func f;
1355 unsigned long ecount;
1356 unsigned long t;
1357 {
1358 char bytes[20];
1359 int count = 1;
1360 if (ecount <= 0x1f)
1361 {
1362 output_B2_format (f, ecount, t);
1363 return;
1364 }
1365 bytes[0] = UNW_B3;
1366 count += output_leb128 (bytes + 1, t, 0);
1367 count += output_leb128 (bytes + count, ecount, 0);
1368 (*f) (count, bytes, NULL);
1369 }
1370
1371 static void
1372 output_B4_format (f, rtype, label)
1373 vbyte_func f;
1374 unw_record_type rtype;
1375 unsigned long label;
1376 {
1377 char bytes[20];
1378 int r = 0;
1379 int count = 1;
1380 if (label <= 0x1f)
1381 {
1382 output_B1_format (f, rtype, label);
1383 return;
1384 }
1385
1386 if (rtype == copy_state)
1387 r = 1;
1388 else if (rtype != label_state)
1389 as_bad ("Invalid record type for format B1");
1390
1391 bytes[0] = (UNW_B4 | (r << 3));
1392 count += output_leb128 (bytes + 1, label, 0);
1393 (*f) (count, bytes, NULL);
1394 }
1395
1396 static char
1397 format_ab_reg (ab, reg)
1398 int ab;
1399 int reg;
1400 {
1401 int ret;
1402 ab = (ab & 3);
1403 reg = (reg & 0x1f);
1404 ret = (ab << 5) | reg;
1405 return ret;
1406 }
1407
1408 static void
1409 output_X1_format (f, rtype, ab, reg, t, w1)
1410 vbyte_func f;
1411 unw_record_type rtype;
1412 int ab, reg;
1413 unsigned long t;
1414 unsigned long w1;
1415 {
1416 char bytes[20];
1417 int r = 0;
1418 int count = 2;
1419 bytes[0] = UNW_X1;
1420
1421 if (rtype == spill_sprel)
1422 r = 1;
1423 else if (rtype != spill_psprel)
1424 as_bad ("Invalid record type for format X1");
1425 bytes[1] = ((r << 7) | format_ab_reg (ab, reg));
1426 count += output_leb128 (bytes + 2, t, 0);
1427 count += output_leb128 (bytes + count, w1, 0);
1428 (*f) (count, bytes, NULL);
1429 }
1430
1431 static void
1432 output_X2_format (f, ab, reg, x, y, treg, t)
1433 vbyte_func f;
1434 int ab, reg;
1435 int x, y, treg;
1436 unsigned long t;
1437 {
1438 char bytes[20];
1439 int count = 3;
1440 bytes[0] = UNW_X2;
1441 bytes[1] = (((x & 1) << 7) | format_ab_reg (ab, reg));
1442 bytes[2] = (((y & 1) << 7) | (treg & 0x7f));
1443 count += output_leb128 (bytes + 3, t, 0);
1444 (*f) (count, bytes, NULL);
1445 }
1446
1447 static void
1448 output_X3_format (f, rtype, qp, ab, reg, t, w1)
1449 vbyte_func f;
1450 unw_record_type rtype;
1451 int qp;
1452 int ab, reg;
1453 unsigned long t;
1454 unsigned long w1;
1455 {
1456 char bytes[20];
1457 int r = 0;
1458 int count = 3;
1459 bytes[0] = UNW_X3;
1460
1461 if (rtype == spill_sprel_p)
1462 r = 1;
1463 else if (rtype != spill_psprel_p)
1464 as_bad ("Invalid record type for format X3");
1465 bytes[1] = ((r << 7) | (qp & 0x3f));
1466 bytes[2] = format_ab_reg (ab, reg);
1467 count += output_leb128 (bytes + 3, t, 0);
1468 count += output_leb128 (bytes + count, w1, 0);
1469 (*f) (count, bytes, NULL);
1470 }
1471
1472 static void
1473 output_X4_format (f, qp, ab, reg, x, y, treg, t)
1474 vbyte_func f;
1475 int qp;
1476 int ab, reg;
1477 int x, y, treg;
1478 unsigned long t;
1479 {
1480 char bytes[20];
1481 int count = 4;
1482 bytes[0] = UNW_X4;
1483 bytes[1] = (qp & 0x3f);
1484 bytes[2] = (((x & 1) << 7) | format_ab_reg (ab, reg));
1485 bytes[3] = (((y & 1) << 7) | (treg & 0x7f));
1486 count += output_leb128 (bytes + 4, t, 0);
1487 (*f) (count, bytes, NULL);
1488 }
1489
1490 /* This function allocates a record list structure, and initializes fields. */
1491 static unw_rec_list *
1492 alloc_record (unw_record_type t)
1493 {
1494 unw_rec_list *ptr;
1495 ptr = xmalloc (sizeof (*ptr));
1496 ptr->next = NULL;
1497 ptr->slot_number = SLOT_NUM_NOT_SET;
1498 ptr->r.type = t;
1499 return ptr;
1500 }
1501
1502 /* This function frees an entire list of record structures. */
1503 void
1504 free_list_records (unw_rec_list *first)
1505 {
1506 unw_rec_list *ptr;
1507 for (ptr = first; ptr != NULL; )
1508 {
1509 unw_rec_list *tmp = ptr;
1510
1511 if ((tmp->r.type == prologue || tmp->r.type == prologue_gr)
1512 && tmp->r.record.r.mask.i)
1513 free (tmp->r.record.r.mask.i);
1514
1515 ptr = ptr->next;
1516 free (tmp);
1517 }
1518 }
1519
1520 static unw_rec_list *
1521 output_prologue ()
1522 {
1523 unw_rec_list *ptr = alloc_record (prologue);
1524 memset (&ptr->r.record.r.mask, 0, sizeof (ptr->r.record.r.mask));
1525 return ptr;
1526 }
1527
1528 static unw_rec_list *
1529 output_prologue_gr (saved_mask, reg)
1530 unsigned int saved_mask;
1531 unsigned int reg;
1532 {
1533 unw_rec_list *ptr = alloc_record (prologue_gr);
1534 memset (&ptr->r.record.r.mask, 0, sizeof (ptr->r.record.r.mask));
1535 ptr->r.record.r.grmask = saved_mask;
1536 ptr->r.record.r.grsave = reg;
1537 return ptr;
1538 }
1539
1540 static unw_rec_list *
1541 output_body ()
1542 {
1543 unw_rec_list *ptr = alloc_record (body);
1544 return ptr;
1545 }
1546
1547 static unw_rec_list *
1548 output_mem_stack_f (size)
1549 unsigned int size;
1550 {
1551 unw_rec_list *ptr = alloc_record (mem_stack_f);
1552 ptr->r.record.p.size = size;
1553 return ptr;
1554 }
1555
1556 static unw_rec_list *
1557 output_mem_stack_v ()
1558 {
1559 unw_rec_list *ptr = alloc_record (mem_stack_v);
1560 return ptr;
1561 }
1562
1563 static unw_rec_list *
1564 output_psp_gr (gr)
1565 unsigned int gr;
1566 {
1567 unw_rec_list *ptr = alloc_record (psp_gr);
1568 ptr->r.record.p.gr = gr;
1569 return ptr;
1570 }
1571
1572 static unw_rec_list *
1573 output_psp_sprel (offset)
1574 unsigned int offset;
1575 {
1576 unw_rec_list *ptr = alloc_record (psp_sprel);
1577 ptr->r.record.p.spoff = offset/4;
1578 return ptr;
1579 }
1580
1581 static unw_rec_list *
1582 output_rp_when ()
1583 {
1584 unw_rec_list *ptr = alloc_record (rp_when);
1585 return ptr;
1586 }
1587
1588 static unw_rec_list *
1589 output_rp_gr (gr)
1590 unsigned int gr;
1591 {
1592 unw_rec_list *ptr = alloc_record (rp_gr);
1593 ptr->r.record.p.gr = gr;
1594 return ptr;
1595 }
1596
1597 static unw_rec_list *
1598 output_rp_br (br)
1599 unsigned int br;
1600 {
1601 unw_rec_list *ptr = alloc_record (rp_br);
1602 ptr->r.record.p.br = br;
1603 return ptr;
1604 }
1605
1606 static unw_rec_list *
1607 output_rp_psprel (offset)
1608 unsigned int offset;
1609 {
1610 unw_rec_list *ptr = alloc_record (rp_psprel);
1611 ptr->r.record.p.pspoff = offset/4;
1612 return ptr;
1613 }
1614
1615 static unw_rec_list *
1616 output_rp_sprel (offset)
1617 unsigned int offset;
1618 {
1619 unw_rec_list *ptr = alloc_record (rp_sprel);
1620 ptr->r.record.p.spoff = offset/4;
1621 return ptr;
1622 }
1623
1624 static unw_rec_list *
1625 output_pfs_when ()
1626 {
1627 unw_rec_list *ptr = alloc_record (pfs_when);
1628 return ptr;
1629 }
1630
1631 static unw_rec_list *
1632 output_pfs_gr (gr)
1633 unsigned int gr;
1634 {
1635 unw_rec_list *ptr = alloc_record (pfs_gr);
1636 ptr->r.record.p.gr = gr;
1637 return ptr;
1638 }
1639
1640 static unw_rec_list *
1641 output_pfs_psprel (offset)
1642 unsigned int offset;
1643 {
1644 unw_rec_list *ptr = alloc_record (pfs_psprel);
1645 ptr->r.record.p.pspoff = offset/4;
1646 return ptr;
1647 }
1648
1649 static unw_rec_list *
1650 output_pfs_sprel (offset)
1651 unsigned int offset;
1652 {
1653 unw_rec_list *ptr = alloc_record (pfs_sprel);
1654 ptr->r.record.p.spoff = offset/4;
1655 return ptr;
1656 }
1657
1658 static unw_rec_list *
1659 output_preds_when ()
1660 {
1661 unw_rec_list *ptr = alloc_record (preds_when);
1662 return ptr;
1663 }
1664
1665 static unw_rec_list *
1666 output_preds_gr (gr)
1667 unsigned int gr;
1668 {
1669 unw_rec_list *ptr = alloc_record (preds_gr);
1670 ptr->r.record.p.gr = gr;
1671 return ptr;
1672 }
1673
1674 static unw_rec_list *
1675 output_preds_psprel (offset)
1676 unsigned int offset;
1677 {
1678 unw_rec_list *ptr = alloc_record (preds_psprel);
1679 ptr->r.record.p.pspoff = offset/4;
1680 return ptr;
1681 }
1682
1683 static unw_rec_list *
1684 output_preds_sprel (offset)
1685 unsigned int offset;
1686 {
1687 unw_rec_list *ptr = alloc_record (preds_sprel);
1688 ptr->r.record.p.spoff = offset/4;
1689 return ptr;
1690 }
1691
1692 static unw_rec_list *
1693 output_fr_mem (mask)
1694 unsigned int mask;
1695 {
1696 unw_rec_list *ptr = alloc_record (fr_mem);
1697 ptr->r.record.p.rmask = mask;
1698 return ptr;
1699 }
1700
1701 static unw_rec_list *
1702 output_frgr_mem (gr_mask, fr_mask)
1703 unsigned int gr_mask;
1704 unsigned int fr_mask;
1705 {
1706 unw_rec_list *ptr = alloc_record (frgr_mem);
1707 ptr->r.record.p.grmask = gr_mask;
1708 ptr->r.record.p.frmask = fr_mask;
1709 return ptr;
1710 }
1711
1712 static unw_rec_list *
1713 output_gr_gr (mask, reg)
1714 unsigned int mask;
1715 unsigned int reg;
1716 {
1717 unw_rec_list *ptr = alloc_record (gr_gr);
1718 ptr->r.record.p.grmask = mask;
1719 ptr->r.record.p.gr = reg;
1720 return ptr;
1721 }
1722
1723 static unw_rec_list *
1724 output_gr_mem (mask)
1725 unsigned int mask;
1726 {
1727 unw_rec_list *ptr = alloc_record (gr_mem);
1728 ptr->r.record.p.rmask = mask;
1729 return ptr;
1730 }
1731
1732 static unw_rec_list *
1733 output_br_mem (unsigned int mask)
1734 {
1735 unw_rec_list *ptr = alloc_record (br_mem);
1736 ptr->r.record.p.brmask = mask;
1737 return ptr;
1738 }
1739
1740 static unw_rec_list *
1741 output_br_gr (save_mask, reg)
1742 unsigned int save_mask;
1743 unsigned int reg;
1744 {
1745 unw_rec_list *ptr = alloc_record (br_gr);
1746 ptr->r.record.p.brmask = save_mask;
1747 ptr->r.record.p.gr = reg;
1748 return ptr;
1749 }
1750
1751 static unw_rec_list *
1752 output_spill_base (offset)
1753 unsigned int offset;
1754 {
1755 unw_rec_list *ptr = alloc_record (spill_base);
1756 ptr->r.record.p.pspoff = offset/4;
1757 return ptr;
1758 }
1759
1760 static unw_rec_list *
1761 output_unat_when ()
1762 {
1763 unw_rec_list *ptr = alloc_record (unat_when);
1764 return ptr;
1765 }
1766
1767 static unw_rec_list *
1768 output_unat_gr (gr)
1769 unsigned int gr;
1770 {
1771 unw_rec_list *ptr = alloc_record (unat_gr);
1772 ptr->r.record.p.gr = gr;
1773 return ptr;
1774 }
1775
1776 static unw_rec_list *
1777 output_unat_psprel (offset)
1778 unsigned int offset;
1779 {
1780 unw_rec_list *ptr = alloc_record (unat_psprel);
1781 ptr->r.record.p.pspoff = offset/4;
1782 return ptr;
1783 }
1784
1785 static unw_rec_list *
1786 output_unat_sprel (offset)
1787 unsigned int offset;
1788 {
1789 unw_rec_list *ptr = alloc_record (unat_sprel);
1790 ptr->r.record.p.spoff = offset/4;
1791 return ptr;
1792 }
1793
1794 static unw_rec_list *
1795 output_lc_when ()
1796 {
1797 unw_rec_list *ptr = alloc_record (lc_when);
1798 return ptr;
1799 }
1800
1801 static unw_rec_list *
1802 output_lc_gr (gr)
1803 unsigned int gr;
1804 {
1805 unw_rec_list *ptr = alloc_record (lc_gr);
1806 ptr->r.record.p.gr = gr;
1807 return ptr;
1808 }
1809
1810 static unw_rec_list *
1811 output_lc_psprel (offset)
1812 unsigned int offset;
1813 {
1814 unw_rec_list *ptr = alloc_record (lc_psprel);
1815 ptr->r.record.p.pspoff = offset/4;
1816 return ptr;
1817 }
1818
1819 static unw_rec_list *
1820 output_lc_sprel (offset)
1821 unsigned int offset;
1822 {
1823 unw_rec_list *ptr = alloc_record (lc_sprel);
1824 ptr->r.record.p.spoff = offset/4;
1825 return ptr;
1826 }
1827
1828 static unw_rec_list *
1829 output_fpsr_when ()
1830 {
1831 unw_rec_list *ptr = alloc_record (fpsr_when);
1832 return ptr;
1833 }
1834
1835 static unw_rec_list *
1836 output_fpsr_gr (gr)
1837 unsigned int gr;
1838 {
1839 unw_rec_list *ptr = alloc_record (fpsr_gr);
1840 ptr->r.record.p.gr = gr;
1841 return ptr;
1842 }
1843
1844 static unw_rec_list *
1845 output_fpsr_psprel (offset)
1846 unsigned int offset;
1847 {
1848 unw_rec_list *ptr = alloc_record (fpsr_psprel);
1849 ptr->r.record.p.pspoff = offset/4;
1850 return ptr;
1851 }
1852
1853 static unw_rec_list *
1854 output_fpsr_sprel (offset)
1855 unsigned int offset;
1856 {
1857 unw_rec_list *ptr = alloc_record (fpsr_sprel);
1858 ptr->r.record.p.spoff = offset/4;
1859 return ptr;
1860 }
1861
1862 static unw_rec_list *
1863 output_priunat_when_gr ()
1864 {
1865 unw_rec_list *ptr = alloc_record (priunat_when_gr);
1866 return ptr;
1867 }
1868
1869 static unw_rec_list *
1870 output_priunat_when_mem ()
1871 {
1872 unw_rec_list *ptr = alloc_record (priunat_when_mem);
1873 return ptr;
1874 }
1875
1876 static unw_rec_list *
1877 output_priunat_gr (gr)
1878 unsigned int gr;
1879 {
1880 unw_rec_list *ptr = alloc_record (priunat_gr);
1881 ptr->r.record.p.gr = gr;
1882 return ptr;
1883 }
1884
1885 static unw_rec_list *
1886 output_priunat_psprel (offset)
1887 unsigned int offset;
1888 {
1889 unw_rec_list *ptr = alloc_record (priunat_psprel);
1890 ptr->r.record.p.pspoff = offset/4;
1891 return ptr;
1892 }
1893
1894 static unw_rec_list *
1895 output_priunat_sprel (offset)
1896 unsigned int offset;
1897 {
1898 unw_rec_list *ptr = alloc_record (priunat_sprel);
1899 ptr->r.record.p.spoff = offset/4;
1900 return ptr;
1901 }
1902
1903 static unw_rec_list *
1904 output_bsp_when ()
1905 {
1906 unw_rec_list *ptr = alloc_record (bsp_when);
1907 return ptr;
1908 }
1909
1910 static unw_rec_list *
1911 output_bsp_gr (gr)
1912 unsigned int gr;
1913 {
1914 unw_rec_list *ptr = alloc_record (bsp_gr);
1915 ptr->r.record.p.gr = gr;
1916 return ptr;
1917 }
1918
1919 static unw_rec_list *
1920 output_bsp_psprel (offset)
1921 unsigned int offset;
1922 {
1923 unw_rec_list *ptr = alloc_record (bsp_psprel);
1924 ptr->r.record.p.pspoff = offset/4;
1925 return ptr;
1926 }
1927
1928 static unw_rec_list *
1929 output_bsp_sprel (offset)
1930 unsigned int offset;
1931 {
1932 unw_rec_list *ptr = alloc_record (bsp_sprel);
1933 ptr->r.record.p.spoff = offset/4;
1934 return ptr;
1935 }
1936
1937 static unw_rec_list *
1938 output_bspstore_when ()
1939 {
1940 unw_rec_list *ptr = alloc_record (bspstore_when);
1941 return ptr;
1942 }
1943
1944 static unw_rec_list *
1945 output_bspstore_gr (gr)
1946 unsigned int gr;
1947 {
1948 unw_rec_list *ptr = alloc_record (bspstore_gr);
1949 ptr->r.record.p.gr = gr;
1950 return ptr;
1951 }
1952
1953 static unw_rec_list *
1954 output_bspstore_psprel (offset)
1955 unsigned int offset;
1956 {
1957 unw_rec_list *ptr = alloc_record (bspstore_psprel);
1958 ptr->r.record.p.pspoff = offset/4;
1959 return ptr;
1960 }
1961
1962 static unw_rec_list *
1963 output_bspstore_sprel (offset)
1964 unsigned int offset;
1965 {
1966 unw_rec_list *ptr = alloc_record (bspstore_sprel);
1967 ptr->r.record.p.spoff = offset/4;
1968 return ptr;
1969 }
1970
1971 static unw_rec_list *
1972 output_rnat_when ()
1973 {
1974 unw_rec_list *ptr = alloc_record (rnat_when);
1975 return ptr;
1976 }
1977
1978 static unw_rec_list *
1979 output_rnat_gr (gr)
1980 unsigned int gr;
1981 {
1982 unw_rec_list *ptr = alloc_record (rnat_gr);
1983 ptr->r.record.p.gr = gr;
1984 return ptr;
1985 }
1986
1987 static unw_rec_list *
1988 output_rnat_psprel (offset)
1989 unsigned int offset;
1990 {
1991 unw_rec_list *ptr = alloc_record (rnat_psprel);
1992 ptr->r.record.p.pspoff = offset/4;
1993 return ptr;
1994 }
1995
1996 static unw_rec_list *
1997 output_rnat_sprel (offset)
1998 unsigned int offset;
1999 {
2000 unw_rec_list *ptr = alloc_record (rnat_sprel);
2001 ptr->r.record.p.spoff = offset/4;
2002 return ptr;
2003 }
2004
2005 static unw_rec_list *
2006 output_unwabi (abi, context)
2007 unsigned long abi;
2008 unsigned long context;
2009 {
2010 unw_rec_list *ptr = alloc_record (unwabi);
2011 ptr->r.record.p.abi = abi;
2012 ptr->r.record.p.context = context;
2013 return ptr;
2014 }
2015
2016 static unw_rec_list *
2017 output_epilogue (unsigned long ecount)
2018 {
2019 unw_rec_list *ptr = alloc_record (epilogue);
2020 ptr->r.record.b.ecount = ecount;
2021 return ptr;
2022 }
2023
2024 static unw_rec_list *
2025 output_label_state (unsigned long label)
2026 {
2027 unw_rec_list *ptr = alloc_record (label_state);
2028 ptr->r.record.b.label = label;
2029 return ptr;
2030 }
2031
2032 static unw_rec_list *
2033 output_copy_state (unsigned long label)
2034 {
2035 unw_rec_list *ptr = alloc_record (copy_state);
2036 ptr->r.record.b.label = label;
2037 return ptr;
2038 }
2039
2040 static unw_rec_list *
2041 output_spill_psprel (ab, reg, offset)
2042 unsigned int ab;
2043 unsigned int reg;
2044 unsigned int offset;
2045 {
2046 unw_rec_list *ptr = alloc_record (spill_psprel);
2047 ptr->r.record.x.ab = ab;
2048 ptr->r.record.x.reg = reg;
2049 ptr->r.record.x.pspoff = offset/4;
2050 return ptr;
2051 }
2052
2053 static unw_rec_list *
2054 output_spill_sprel (ab, reg, offset)
2055 unsigned int ab;
2056 unsigned int reg;
2057 unsigned int offset;
2058 {
2059 unw_rec_list *ptr = alloc_record (spill_sprel);
2060 ptr->r.record.x.ab = ab;
2061 ptr->r.record.x.reg = reg;
2062 ptr->r.record.x.spoff = offset/4;
2063 return ptr;
2064 }
2065
2066 static unw_rec_list *
2067 output_spill_psprel_p (ab, reg, offset, predicate)
2068 unsigned int ab;
2069 unsigned int reg;
2070 unsigned int offset;
2071 unsigned int predicate;
2072 {
2073 unw_rec_list *ptr = alloc_record (spill_psprel_p);
2074 ptr->r.record.x.ab = ab;
2075 ptr->r.record.x.reg = reg;
2076 ptr->r.record.x.pspoff = offset/4;
2077 ptr->r.record.x.qp = predicate;
2078 return ptr;
2079 }
2080
2081 static unw_rec_list *
2082 output_spill_sprel_p (ab, reg, offset, predicate)
2083 unsigned int ab;
2084 unsigned int reg;
2085 unsigned int offset;
2086 unsigned int predicate;
2087 {
2088 unw_rec_list *ptr = alloc_record (spill_sprel_p);
2089 ptr->r.record.x.ab = ab;
2090 ptr->r.record.x.reg = reg;
2091 ptr->r.record.x.spoff = offset/4;
2092 ptr->r.record.x.qp = predicate;
2093 return ptr;
2094 }
2095
2096 static unw_rec_list *
2097 output_spill_reg (ab, reg, targ_reg, xy)
2098 unsigned int ab;
2099 unsigned int reg;
2100 unsigned int targ_reg;
2101 unsigned int xy;
2102 {
2103 unw_rec_list *ptr = alloc_record (spill_reg);
2104 ptr->r.record.x.ab = ab;
2105 ptr->r.record.x.reg = reg;
2106 ptr->r.record.x.treg = targ_reg;
2107 ptr->r.record.x.xy = xy;
2108 return ptr;
2109 }
2110
2111 static unw_rec_list *
2112 output_spill_reg_p (ab, reg, targ_reg, xy, predicate)
2113 unsigned int ab;
2114 unsigned int reg;
2115 unsigned int targ_reg;
2116 unsigned int xy;
2117 unsigned int predicate;
2118 {
2119 unw_rec_list *ptr = alloc_record (spill_reg_p);
2120 ptr->r.record.x.ab = ab;
2121 ptr->r.record.x.reg = reg;
2122 ptr->r.record.x.treg = targ_reg;
2123 ptr->r.record.x.xy = xy;
2124 ptr->r.record.x.qp = predicate;
2125 return ptr;
2126 }
2127
2128 /* Given a unw_rec_list process the correct format with the
2129 specified function. */
2130 static void
2131 process_one_record (ptr, f)
2132 unw_rec_list *ptr;
2133 vbyte_func f;
2134 {
2135 unsigned long fr_mask, gr_mask;
2136
2137 switch (ptr->r.type)
2138 {
2139 case gr_mem:
2140 case fr_mem:
2141 case br_mem:
2142 case frgr_mem:
2143 /* these are taken care of by prologue/prologue_gr */
2144 break;
2145
2146 case prologue_gr:
2147 case prologue:
2148 if (ptr->r.type == prologue_gr)
2149 output_R2_format (f, ptr->r.record.r.grmask,
2150 ptr->r.record.r.grsave, ptr->r.record.r.rlen);
2151 else
2152 output_R1_format (f, ptr->r.type, ptr->r.record.r.rlen);
2153
2154 /* output descriptor(s) for union of register spills (if any): */
2155 gr_mask = ptr->r.record.r.mask.gr_mem;
2156 fr_mask = ptr->r.record.r.mask.fr_mem;
2157 if (fr_mask)
2158 {
2159 if ((fr_mask & ~0xfUL) == 0)
2160 output_P6_format (f, fr_mem, fr_mask);
2161 else
2162 {
2163 output_P5_format (f, gr_mask, fr_mask);
2164 gr_mask = 0;
2165 }
2166 }
2167 if (gr_mask)
2168 output_P6_format (f, gr_mem, gr_mask);
2169 if (ptr->r.record.r.mask.br_mem)
2170 output_P1_format (f, ptr->r.record.r.mask.br_mem);
2171
2172 /* output imask descriptor if necessary: */
2173 if (ptr->r.record.r.mask.i)
2174 output_P4_format (f, ptr->r.record.r.mask.i,
2175 ptr->r.record.r.imask_size);
2176 break;
2177
2178 case body:
2179 output_R1_format (f, ptr->r.type, ptr->r.record.r.rlen);
2180 break;
2181 case mem_stack_f:
2182 case mem_stack_v:
2183 output_P7_format (f, ptr->r.type, ptr->r.record.p.t,
2184 ptr->r.record.p.size);
2185 break;
2186 case psp_gr:
2187 case rp_gr:
2188 case pfs_gr:
2189 case preds_gr:
2190 case unat_gr:
2191 case lc_gr:
2192 case fpsr_gr:
2193 case priunat_gr:
2194 case bsp_gr:
2195 case bspstore_gr:
2196 case rnat_gr:
2197 output_P3_format (f, ptr->r.type, ptr->r.record.p.gr);
2198 break;
2199 case rp_br:
2200 output_P3_format (f, rp_br, ptr->r.record.p.br);
2201 break;
2202 case psp_sprel:
2203 output_P7_format (f, psp_sprel, ptr->r.record.p.spoff, 0);
2204 break;
2205 case rp_when:
2206 case pfs_when:
2207 case preds_when:
2208 case unat_when:
2209 case lc_when:
2210 case fpsr_when:
2211 output_P7_format (f, ptr->r.type, ptr->r.record.p.t, 0);
2212 break;
2213 case rp_psprel:
2214 case pfs_psprel:
2215 case preds_psprel:
2216 case unat_psprel:
2217 case lc_psprel:
2218 case fpsr_psprel:
2219 case spill_base:
2220 output_P7_format (f, ptr->r.type, ptr->r.record.p.pspoff, 0);
2221 break;
2222 case rp_sprel:
2223 case pfs_sprel:
2224 case preds_sprel:
2225 case unat_sprel:
2226 case lc_sprel:
2227 case fpsr_sprel:
2228 case priunat_sprel:
2229 case bsp_sprel:
2230 case bspstore_sprel:
2231 case rnat_sprel:
2232 output_P8_format (f, ptr->r.type, ptr->r.record.p.spoff);
2233 break;
2234 case gr_gr:
2235 output_P9_format (f, ptr->r.record.p.grmask, ptr->r.record.p.gr);
2236 break;
2237 case br_gr:
2238 output_P2_format (f, ptr->r.record.p.brmask, ptr->r.record.p.gr);
2239 break;
2240 case spill_mask:
2241 as_bad ("spill_mask record unimplemented.");
2242 break;
2243 case priunat_when_gr:
2244 case priunat_when_mem:
2245 case bsp_when:
2246 case bspstore_when:
2247 case rnat_when:
2248 output_P8_format (f, ptr->r.type, ptr->r.record.p.t);
2249 break;
2250 case priunat_psprel:
2251 case bsp_psprel:
2252 case bspstore_psprel:
2253 case rnat_psprel:
2254 output_P8_format (f, ptr->r.type, ptr->r.record.p.pspoff);
2255 break;
2256 case unwabi:
2257 output_P10_format (f, ptr->r.record.p.abi, ptr->r.record.p.context);
2258 break;
2259 case epilogue:
2260 output_B3_format (f, ptr->r.record.b.ecount, ptr->r.record.b.t);
2261 break;
2262 case label_state:
2263 case copy_state:
2264 output_B4_format (f, ptr->r.type, ptr->r.record.b.label);
2265 break;
2266 case spill_psprel:
2267 output_X1_format (f, ptr->r.type, ptr->r.record.x.ab,
2268 ptr->r.record.x.reg, ptr->r.record.x.t,
2269 ptr->r.record.x.pspoff);
2270 break;
2271 case spill_sprel:
2272 output_X1_format (f, ptr->r.type, ptr->r.record.x.ab,
2273 ptr->r.record.x.reg, ptr->r.record.x.t,
2274 ptr->r.record.x.spoff);
2275 break;
2276 case spill_reg:
2277 output_X2_format (f, ptr->r.record.x.ab, ptr->r.record.x.reg,
2278 ptr->r.record.x.xy >> 1, ptr->r.record.x.xy,
2279 ptr->r.record.x.treg, ptr->r.record.x.t);
2280 break;
2281 case spill_psprel_p:
2282 output_X3_format (f, ptr->r.type, ptr->r.record.x.qp,
2283 ptr->r.record.x.ab, ptr->r.record.x.reg,
2284 ptr->r.record.x.t, ptr->r.record.x.pspoff);
2285 break;
2286 case spill_sprel_p:
2287 output_X3_format (f, ptr->r.type, ptr->r.record.x.qp,
2288 ptr->r.record.x.ab, ptr->r.record.x.reg,
2289 ptr->r.record.x.t, ptr->r.record.x.spoff);
2290 break;
2291 case spill_reg_p:
2292 output_X4_format (f, ptr->r.record.x.qp, ptr->r.record.x.ab,
2293 ptr->r.record.x.reg, ptr->r.record.x.xy >> 1,
2294 ptr->r.record.x.xy, ptr->r.record.x.treg,
2295 ptr->r.record.x.t);
2296 break;
2297 default:
2298 as_bad ("record_type_not_valid");
2299 break;
2300 }
2301 }
2302
2303 /* Given a unw_rec_list list, process all the records with
2304 the specified function. */
2305 static void
2306 process_unw_records (list, f)
2307 unw_rec_list *list;
2308 vbyte_func f;
2309 {
2310 unw_rec_list *ptr;
2311 for (ptr = list; ptr; ptr = ptr->next)
2312 process_one_record (ptr, f);
2313 }
2314
2315 /* Determine the size of a record list in bytes. */
2316 static int
2317 calc_record_size (list)
2318 unw_rec_list *list;
2319 {
2320 vbyte_count = 0;
2321 process_unw_records (list, count_output);
2322 return vbyte_count;
2323 }
2324
2325 /* Update IMASK bitmask to reflect the fact that one or more registers
2326 of type TYPE are saved starting at instruction with index T. If N
2327 bits are set in REGMASK, it is assumed that instructions T through
2328 T+N-1 save these registers.
2329
2330 TYPE values:
2331 0: no save
2332 1: instruction saves next fp reg
2333 2: instruction saves next general reg
2334 3: instruction saves next branch reg */
2335 static void
2336 set_imask (region, regmask, t, type)
2337 unw_rec_list *region;
2338 unsigned long regmask;
2339 unsigned long t;
2340 unsigned int type;
2341 {
2342 unsigned char *imask;
2343 unsigned long imask_size;
2344 unsigned int i;
2345 int pos;
2346
2347 imask = region->r.record.r.mask.i;
2348 imask_size = region->r.record.r.imask_size;
2349 if (!imask)
2350 {
2351 imask_size = (region->r.record.r.rlen*2 + 7)/8 + 1;
2352 imask = xmalloc (imask_size);
2353 memset (imask, 0, imask_size);
2354
2355 region->r.record.r.imask_size = imask_size;
2356 region->r.record.r.mask.i = imask;
2357 }
2358
2359 i = (t/4) + 1;
2360 pos = 2*(3 - t%4);
2361 while (regmask)
2362 {
2363 if (i >= imask_size)
2364 {
2365 as_bad ("Ignoring attempt to spill beyond end of region");
2366 return;
2367 }
2368
2369 imask[i] |= (type & 0x3) << pos;
2370
2371 regmask &= (regmask - 1);
2372 pos -= 2;
2373 if (pos < 0)
2374 {
2375 pos = 0;
2376 ++i;
2377 }
2378 }
2379 }
2380
2381 static int
2382 count_bits (unsigned long mask)
2383 {
2384 int n = 0;
2385
2386 while (mask)
2387 {
2388 mask &= mask - 1;
2389 ++n;
2390 }
2391 return n;
2392 }
2393
2394 unsigned long
2395 slot_index (unsigned long slot_addr, unsigned long first_addr)
2396 {
2397 return (3*((slot_addr >> 4) - (first_addr >> 4))
2398 + ((slot_addr & 0x3) - (first_addr & 0x3)));
2399 }
2400
2401 /* Given a complete record list, process any records which have
2402 unresolved fields, (ie length counts for a prologue). After
2403 this has been run, all neccessary information should be available
2404 within each record to generate an image. */
2405 static void
2406 fixup_unw_records (list)
2407 unw_rec_list *list;
2408 {
2409 unw_rec_list *ptr, *region = 0;
2410 unsigned long first_addr = 0, rlen = 0, t;
2411
2412 for (ptr = list; ptr; ptr = ptr->next)
2413 {
2414 if (ptr->slot_number == SLOT_NUM_NOT_SET)
2415 as_bad (" Insn slot not set in unwind record.");
2416 t = slot_index (ptr->slot_number, first_addr);
2417 switch (ptr->r.type)
2418 {
2419 case prologue:
2420 case prologue_gr:
2421 case body:
2422 {
2423 unw_rec_list *last;
2424 int size, dir_len = 0;
2425 unsigned long last_addr;
2426
2427 first_addr = ptr->slot_number;
2428 ptr->slot_number = 0;
2429 /* Find either the next body/prologue start, or the end of
2430 the list, and determine the size of the region. */
2431 last_addr = unwind.next_slot_number;
2432 for (last = ptr->next; last != NULL; last = last->next)
2433 if (last->r.type == prologue || last->r.type == prologue_gr
2434 || last->r.type == body)
2435 {
2436 last_addr = last->slot_number;
2437 break;
2438 }
2439 else if (!last->next)
2440 {
2441 /* In the absence of an explicit .body directive,
2442 the prologue ends after the last instruction
2443 covered by an unwind directive. */
2444 if (ptr->r.type != body)
2445 {
2446 last_addr = last->slot_number;
2447 switch (last->r.type)
2448 {
2449 case frgr_mem:
2450 dir_len = (count_bits (last->r.record.p.frmask)
2451 + count_bits (last->r.record.p.grmask));
2452 break;
2453 case fr_mem:
2454 case gr_mem:
2455 dir_len += count_bits (last->r.record.p.rmask);
2456 break;
2457 case br_mem:
2458 case br_gr:
2459 dir_len += count_bits (last->r.record.p.brmask);
2460 break;
2461 case gr_gr:
2462 dir_len += count_bits (last->r.record.p.grmask);
2463 break;
2464 default:
2465 dir_len = 1;
2466 break;
2467 }
2468 }
2469 break;
2470 }
2471 size = slot_index (last_addr, first_addr) + dir_len;
2472 rlen = ptr->r.record.r.rlen = size;
2473 region = ptr;
2474 break;
2475 }
2476 case epilogue:
2477 ptr->r.record.b.t = rlen - 1 - t;
2478 break;
2479
2480 case mem_stack_f:
2481 case mem_stack_v:
2482 case rp_when:
2483 case pfs_when:
2484 case preds_when:
2485 case unat_when:
2486 case lc_when:
2487 case fpsr_when:
2488 case priunat_when_gr:
2489 case priunat_when_mem:
2490 case bsp_when:
2491 case bspstore_when:
2492 case rnat_when:
2493 ptr->r.record.p.t = t;
2494 break;
2495
2496 case spill_reg:
2497 case spill_sprel:
2498 case spill_psprel:
2499 case spill_reg_p:
2500 case spill_sprel_p:
2501 case spill_psprel_p:
2502 ptr->r.record.x.t = t;
2503 break;
2504
2505 case frgr_mem:
2506 if (!region)
2507 {
2508 as_bad ("frgr_mem record before region record!\n");
2509 return;
2510 }
2511 region->r.record.r.mask.fr_mem |= ptr->r.record.p.frmask;
2512 region->r.record.r.mask.gr_mem |= ptr->r.record.p.grmask;
2513 set_imask (region, ptr->r.record.p.frmask, t, 1);
2514 set_imask (region, ptr->r.record.p.grmask, t, 2);
2515 break;
2516 case fr_mem:
2517 if (!region)
2518 {
2519 as_bad ("fr_mem record before region record!\n");
2520 return;
2521 }
2522 region->r.record.r.mask.fr_mem |= ptr->r.record.p.rmask;
2523 set_imask (region, ptr->r.record.p.rmask, t, 1);
2524 break;
2525 case gr_mem:
2526 if (!region)
2527 {
2528 as_bad ("gr_mem record before region record!\n");
2529 return;
2530 }
2531 region->r.record.r.mask.gr_mem |= ptr->r.record.p.rmask;
2532 set_imask (region, ptr->r.record.p.rmask, t, 2);
2533 break;
2534 case br_mem:
2535 if (!region)
2536 {
2537 as_bad ("br_mem record before region record!\n");
2538 return;
2539 }
2540 region->r.record.r.mask.br_mem |= ptr->r.record.p.brmask;
2541 set_imask (region, ptr->r.record.p.brmask, t, 3);
2542 break;
2543
2544 case gr_gr:
2545 if (!region)
2546 {
2547 as_bad ("gr_gr record before region record!\n");
2548 return;
2549 }
2550 set_imask (region, ptr->r.record.p.grmask, t, 2);
2551 break;
2552 case br_gr:
2553 if (!region)
2554 {
2555 as_bad ("br_gr record before region record!\n");
2556 return;
2557 }
2558 set_imask (region, ptr->r.record.p.brmask, t, 3);
2559 break;
2560
2561 default:
2562 break;
2563 }
2564 }
2565 }
2566
2567 /* Generate an unwind image from a record list. Returns the number of
2568 bytes in the resulting image. The memory image itselof is returned
2569 in the 'ptr' parameter. */
2570 static int
2571 output_unw_records (list, ptr)
2572 unw_rec_list *list;
2573 void **ptr;
2574 {
2575 int size, x, extra = 0;
2576 unsigned char *mem;
2577
2578 fixup_unw_records (list);
2579 size = calc_record_size (list);
2580
2581 /* pad to 8 byte boundry. */
2582 x = size % 8;
2583 if (x != 0)
2584 extra = 8 - x;
2585 /* Add 8 for the header + 8 more bytes for the personality offset. */
2586 mem = xmalloc (size + extra + 16);
2587
2588 vbyte_mem_ptr = mem + 8;
2589 /* Clear the padding area and personality. */
2590 memset (mem + 8 + size, 0 , extra + 8);
2591 /* Initialize the header area. */
2592 md_number_to_chars (mem, (((bfd_vma) 1 << 48) /* version */
2593 | (unwind.personality_routine
2594 ? ((bfd_vma) 3 << 32) /* U & E handler flags */
2595 : 0)
2596 | ((size + extra) / 8)), /* length (dwords) */
2597 8);
2598
2599 process_unw_records (list, output_vbyte_mem);
2600
2601 *ptr = mem;
2602 return size + extra + 16;
2603 }
2604
2605 static int
2606 convert_expr_to_ab_reg (e, ab, regp)
2607 expressionS *e;
2608 unsigned int *ab;
2609 unsigned int *regp;
2610 {
2611 unsigned int reg;
2612
2613 if (e->X_op != O_register)
2614 return 0;
2615
2616 reg = e->X_add_number;
2617 if (reg >= REG_GR + 4 && reg <= REG_GR + 7)
2618 {
2619 *ab = 0;
2620 *regp = reg - REG_GR;
2621 }
2622 else if ((reg >= REG_FR + 2 && reg <= REG_FR + 5)
2623 || (reg >= REG_FR + 16 && reg <= REG_FR + 31))
2624 {
2625 *ab = 1;
2626 *regp = reg - REG_FR;
2627 }
2628 else if (reg >= REG_BR + 1 && reg <= REG_BR + 5)
2629 {
2630 *ab = 2;
2631 *regp = reg - REG_BR;
2632 }
2633 else
2634 {
2635 *ab = 3;
2636 switch (reg)
2637 {
2638 case REG_PR: *regp = 0; break;
2639 case REG_PSP: *regp = 1; break;
2640 case REG_PRIUNAT: *regp = 2; break;
2641 case REG_BR + 0: *regp = 3; break;
2642 case REG_AR + AR_BSP: *regp = 4; break;
2643 case REG_AR + AR_BSPSTORE: *regp = 5; break;
2644 case REG_AR + AR_RNAT: *regp = 6; break;
2645 case REG_AR + AR_UNAT: *regp = 7; break;
2646 case REG_AR + AR_FPSR: *regp = 8; break;
2647 case REG_AR + AR_PFS: *regp = 9; break;
2648 case REG_AR + AR_LC: *regp = 10; break;
2649
2650 default:
2651 return 0;
2652 }
2653 }
2654 return 1;
2655 }
2656
2657 static int
2658 convert_expr_to_xy_reg (e, xy, regp)
2659 expressionS *e;
2660 unsigned int *xy;
2661 unsigned int *regp;
2662 {
2663 unsigned int reg;
2664
2665 if (e->X_op != O_register)
2666 return 0;
2667
2668 reg = e->X_add_number;
2669
2670 if (reg >= REG_GR && reg <= REG_GR + 127)
2671 {
2672 *xy = 0;
2673 *regp = reg - REG_GR;
2674 }
2675 else if (reg >= REG_FR && reg <= REG_FR + 127)
2676 {
2677 *xy = 1;
2678 *regp = reg - REG_FR;
2679 }
2680 else if (reg >= REG_BR && reg <= REG_BR + 7)
2681 {
2682 *xy = 2;
2683 *regp = reg - REG_BR;
2684 }
2685 else
2686 return -1;
2687 return 1;
2688 }
2689
2690 static void
2691 dot_radix (dummy)
2692 int dummy;
2693 {
2694 int radix;
2695
2696 SKIP_WHITESPACE ();
2697 radix = *input_line_pointer++;
2698
2699 if (radix != 'C' && !is_end_of_line[(unsigned char) radix])
2700 {
2701 as_bad ("Radix `%c' unsupported", *input_line_pointer);
2702 ignore_rest_of_line ();
2703 return;
2704 }
2705 }
2706
2707 /* .sbss, .bss etc. are macros that expand into ".section SECNAME". */
2708 static void
2709 dot_special_section (which)
2710 int which;
2711 {
2712 set_section ((char *) special_section_name[which]);
2713 }
2714
2715 static void
2716 add_unwind_entry (ptr)
2717 unw_rec_list *ptr;
2718 {
2719 if (unwind.tail)
2720 unwind.tail->next = ptr;
2721 else
2722 unwind.list = ptr;
2723 unwind.tail = ptr;
2724
2725 /* The current entry can in fact be a chain of unwind entries. */
2726 if (unwind.current_entry == NULL)
2727 unwind.current_entry = ptr;
2728 }
2729
2730 static void
2731 dot_fframe (dummy)
2732 int dummy;
2733 {
2734 expressionS e;
2735
2736 parse_operand (&e);
2737
2738 if (e.X_op != O_constant)
2739 as_bad ("Operand to .fframe must be a constant");
2740 else
2741 add_unwind_entry (output_mem_stack_f (e.X_add_number));
2742 }
2743
2744 static void
2745 dot_vframe (dummy)
2746 int dummy;
2747 {
2748 expressionS e;
2749 unsigned reg;
2750
2751 parse_operand (&e);
2752 reg = e.X_add_number - REG_GR;
2753 if (e.X_op == O_register && reg < 128)
2754 {
2755 add_unwind_entry (output_mem_stack_v ());
2756 if (! (unwind.prologue_mask & 2))
2757 add_unwind_entry (output_psp_gr (reg));
2758 }
2759 else
2760 as_bad ("First operand to .vframe must be a general register");
2761 }
2762
2763 static void
2764 dot_vframesp (dummy)
2765 int dummy;
2766 {
2767 expressionS e;
2768
2769 parse_operand (&e);
2770 if (e.X_op == O_constant)
2771 {
2772 add_unwind_entry (output_mem_stack_v ());
2773 add_unwind_entry (output_psp_sprel (e.X_add_number));
2774 }
2775 else
2776 as_bad ("First operand to .vframesp must be a general register");
2777 }
2778
2779 static void
2780 dot_vframepsp (dummy)
2781 int dummy;
2782 {
2783 expressionS e;
2784
2785 parse_operand (&e);
2786 if (e.X_op == O_constant)
2787 {
2788 add_unwind_entry (output_mem_stack_v ());
2789 add_unwind_entry (output_psp_sprel (e.X_add_number));
2790 }
2791 else
2792 as_bad ("First operand to .vframepsp must be a general register");
2793 }
2794
2795 static void
2796 dot_save (dummy)
2797 int dummy;
2798 {
2799 expressionS e1, e2;
2800 int sep;
2801 int reg1, reg2;
2802
2803 sep = parse_operand (&e1);
2804 if (sep != ',')
2805 as_bad ("No second operand to .save");
2806 sep = parse_operand (&e2);
2807
2808 reg1 = e1.X_add_number;
2809 reg2 = e2.X_add_number - REG_GR;
2810
2811 /* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'. */
2812 if (e1.X_op == O_register)
2813 {
2814 if (e2.X_op == O_register && reg2 >=0 && reg2 < 128)
2815 {
2816 switch (reg1)
2817 {
2818 case REG_AR + AR_BSP:
2819 add_unwind_entry (output_bsp_when ());
2820 add_unwind_entry (output_bsp_gr (reg2));
2821 break;
2822 case REG_AR + AR_BSPSTORE:
2823 add_unwind_entry (output_bspstore_when ());
2824 add_unwind_entry (output_bspstore_gr (reg2));
2825 break;
2826 case REG_AR + AR_RNAT:
2827 add_unwind_entry (output_rnat_when ());
2828 add_unwind_entry (output_rnat_gr (reg2));
2829 break;
2830 case REG_AR+AR_UNAT:
2831 add_unwind_entry (output_unat_when ());
2832 add_unwind_entry (output_unat_gr (reg2));
2833 break;
2834 case REG_AR+AR_FPSR:
2835 add_unwind_entry (output_fpsr_when ());
2836 add_unwind_entry (output_fpsr_gr (reg2));
2837 break;
2838 case REG_AR+AR_PFS:
2839 add_unwind_entry (output_pfs_when ());
2840 if (! (unwind.prologue_mask & 4))
2841 add_unwind_entry (output_pfs_gr (reg2));
2842 break;
2843 case REG_AR+AR_LC:
2844 add_unwind_entry (output_lc_when ());
2845 add_unwind_entry (output_lc_gr (reg2));
2846 break;
2847 case REG_BR:
2848 add_unwind_entry (output_rp_when ());
2849 if (! (unwind.prologue_mask & 8))
2850 add_unwind_entry (output_rp_gr (reg2));
2851 break;
2852 case REG_PR:
2853 add_unwind_entry (output_preds_when ());
2854 if (! (unwind.prologue_mask & 1))
2855 add_unwind_entry (output_preds_gr (reg2));
2856 break;
2857 case REG_PRIUNAT:
2858 add_unwind_entry (output_priunat_when_gr ());
2859 add_unwind_entry (output_priunat_gr (reg2));
2860 break;
2861 default:
2862 as_bad ("First operand not a valid register");
2863 }
2864 }
2865 else
2866 as_bad (" Second operand not a valid register");
2867 }
2868 else
2869 as_bad ("First operand not a register");
2870 }
2871
2872 static void
2873 dot_restore (dummy)
2874 int dummy;
2875 {
2876 expressionS e1, e2;
2877 unsigned long ecount = 0;
2878 int sep;
2879
2880 sep = parse_operand (&e1);
2881 if (e1.X_op != O_register || e1.X_add_number != REG_GR + 12)
2882 {
2883 as_bad ("First operand to .restore must be stack pointer (sp)");
2884 return;
2885 }
2886
2887 if (sep == ',')
2888 {
2889 parse_operand (&e2);
2890 if (e1.X_op != O_constant)
2891 {
2892 as_bad ("Second operand to .restore must be constant");
2893 return;
2894 }
2895 ecount = e1.X_op;
2896 }
2897 add_unwind_entry (output_epilogue (ecount));
2898 }
2899
2900 static void
2901 dot_restorereg (dummy)
2902 int dummy;
2903 {
2904 unsigned int ab, reg;
2905 expressionS e;
2906
2907 parse_operand (&e);
2908
2909 if (!convert_expr_to_ab_reg (&e, &ab, &reg))
2910 {
2911 as_bad ("First operand to .restorereg must be a preserved register");
2912 return;
2913 }
2914 add_unwind_entry (output_spill_reg (ab, reg, 0, 0));
2915 }
2916
2917 static void
2918 dot_restorereg_p (dummy)
2919 int dummy;
2920 {
2921 unsigned int qp, ab, reg;
2922 expressionS e1, e2;
2923 int sep;
2924
2925 sep = parse_operand (&e1);
2926 if (sep != ',')
2927 {
2928 as_bad ("No second operand to .restorereg.p");
2929 return;
2930 }
2931
2932 parse_operand (&e2);
2933
2934 qp = e1.X_add_number - REG_P;
2935 if (e1.X_op != O_register || qp > 63)
2936 {
2937 as_bad ("First operand to .restorereg.p must be a predicate");
2938 return;
2939 }
2940
2941 if (!convert_expr_to_ab_reg (&e2, &ab, &reg))
2942 {
2943 as_bad ("Second operand to .restorereg.p must be a preserved register");
2944 return;
2945 }
2946 add_unwind_entry (output_spill_reg_p (ab, reg, 0, 0, qp));
2947 }
2948
2949 static int
2950 generate_unwind_image ()
2951 {
2952 int size;
2953 unsigned char *unw_rec;
2954
2955 /* Force out pending instructions, to make sure all unwind records have
2956 a valid slot_number field. */
2957 ia64_flush_insns ();
2958
2959 /* Generate the unwind record. */
2960 size = output_unw_records (unwind.list, (void **) &unw_rec);
2961 if (size % 8 != 0)
2962 as_bad ("Unwind record is not a multiple of 8 bytes.");
2963
2964 /* If there are unwind records, switch sections, and output the info. */
2965 if (size != 0)
2966 {
2967 unsigned char *where;
2968 expressionS exp;
2969 set_section ((char *) special_section_name[SPECIAL_SECTION_UNWIND_INFO]);
2970
2971 /* Set expression which points to start of unwind descriptor area. */
2972 unwind.info = expr_build_dot ();
2973
2974 where = (unsigned char *)frag_more (size);
2975
2976 /* Issue a label for this address, and keep track of it to put it
2977 in the unwind section. */
2978
2979 /* Copy the information from the unwind record into this section. The
2980 data is already in the correct byte order. */
2981 memcpy (where, unw_rec, size);
2982 /* Add the personality address to the image. */
2983 if (unwind.personality_routine != 0)
2984 {
2985 exp.X_op = O_symbol;
2986 exp.X_add_symbol = unwind.personality_routine;
2987 exp.X_add_number = 0;
2988 fix_new_exp (frag_now, frag_now_fix () - 8, 8,
2989 &exp, 0, BFD_RELOC_IA64_LTOFF_FPTR64LSB);
2990 unwind.personality_routine = 0;
2991 }
2992 obj_elf_previous (0);
2993 }
2994
2995 free_list_records (unwind.list);
2996 unwind.list = unwind.tail = unwind.current_entry = NULL;
2997
2998 return size;
2999 }
3000
3001 static void
3002 dot_handlerdata (dummy)
3003 int dummy;
3004 {
3005 generate_unwind_image ();
3006 demand_empty_rest_of_line ();
3007 }
3008
3009 static void
3010 dot_unwentry (dummy)
3011 int dummy;
3012 {
3013 demand_empty_rest_of_line ();
3014 }
3015
3016 static void
3017 dot_altrp (dummy)
3018 int dummy;
3019 {
3020 expressionS e;
3021 unsigned reg;
3022
3023 parse_operand (&e);
3024 reg = e.X_add_number - REG_BR;
3025 if (e.X_op == O_register && reg < 8)
3026 add_unwind_entry (output_rp_br (reg));
3027 else
3028 as_bad ("First operand not a valid branch register");
3029 }
3030
3031 static void
3032 dot_savemem (psprel)
3033 int psprel;
3034 {
3035 expressionS e1, e2;
3036 int sep;
3037 int reg1, val;
3038
3039 sep = parse_operand (&e1);
3040 if (sep != ',')
3041 as_bad ("No second operand to .save%ssp", psprel ? "p" : "");
3042 sep = parse_operand (&e2);
3043
3044 reg1 = e1.X_add_number;
3045 val = e2.X_add_number;
3046
3047 /* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'. */
3048 if (e1.X_op == O_register)
3049 {
3050 if (e2.X_op == O_constant)
3051 {
3052 switch (reg1)
3053 {
3054 case REG_AR + AR_BSP:
3055 add_unwind_entry (output_bsp_when ());
3056 add_unwind_entry ((psprel
3057 ? output_bsp_psprel
3058 : output_bsp_sprel) (val));
3059 break;
3060 case REG_AR + AR_BSPSTORE:
3061 add_unwind_entry (output_bspstore_when ());
3062 add_unwind_entry ((psprel
3063 ? output_bspstore_psprel
3064 : output_bspstore_sprel) (val));
3065 break;
3066 case REG_AR + AR_RNAT:
3067 add_unwind_entry (output_rnat_when ());
3068 add_unwind_entry ((psprel
3069 ? output_rnat_psprel
3070 : output_rnat_sprel) (val));
3071 break;
3072 case REG_AR + AR_UNAT:
3073 add_unwind_entry (output_unat_when ());
3074 add_unwind_entry ((psprel
3075 ? output_unat_psprel
3076 : output_unat_sprel) (val));
3077 break;
3078 case REG_AR + AR_FPSR:
3079 add_unwind_entry (output_fpsr_when ());
3080 add_unwind_entry ((psprel
3081 ? output_fpsr_psprel
3082 : output_fpsr_sprel) (val));
3083 break;
3084 case REG_AR + AR_PFS:
3085 add_unwind_entry (output_pfs_when ());
3086 add_unwind_entry ((psprel
3087 ? output_pfs_psprel
3088 : output_pfs_sprel) (val));
3089 break;
3090 case REG_AR + AR_LC:
3091 add_unwind_entry (output_lc_when ());
3092 add_unwind_entry ((psprel
3093 ? output_lc_psprel
3094 : output_lc_sprel) (val));
3095 break;
3096 case REG_BR:
3097 add_unwind_entry (output_rp_when ());
3098 add_unwind_entry ((psprel
3099 ? output_rp_psprel
3100 : output_rp_sprel) (val));
3101 break;
3102 case REG_PR:
3103 add_unwind_entry (output_preds_when ());
3104 add_unwind_entry ((psprel
3105 ? output_preds_psprel
3106 : output_preds_sprel) (val));
3107 break;
3108 case REG_PRIUNAT:
3109 add_unwind_entry (output_priunat_when_mem ());
3110 add_unwind_entry ((psprel
3111 ? output_priunat_psprel
3112 : output_priunat_sprel) (val));
3113 break;
3114 default:
3115 as_bad ("First operand not a valid register");
3116 }
3117 }
3118 else
3119 as_bad (" Second operand not a valid constant");
3120 }
3121 else
3122 as_bad ("First operand not a register");
3123 }
3124
3125 static void
3126 dot_saveg (dummy)
3127 int dummy;
3128 {
3129 expressionS e1, e2;
3130 int sep;
3131 sep = parse_operand (&e1);
3132 if (sep == ',')
3133 parse_operand (&e2);
3134
3135 if (e1.X_op != O_constant)
3136 as_bad ("First operand to .save.g must be a constant.");
3137 else
3138 {
3139 int grmask = e1.X_add_number;
3140 if (sep != ',')
3141 add_unwind_entry (output_gr_mem (grmask));
3142 else
3143 {
3144 int reg = e2.X_add_number - REG_GR;
3145 if (e2.X_op == O_register && reg >=0 && reg < 128)
3146 add_unwind_entry (output_gr_gr (grmask, reg));
3147 else
3148 as_bad ("Second operand is an invalid register.");
3149 }
3150 }
3151 }
3152
3153 static void
3154 dot_savef (dummy)
3155 int dummy;
3156 {
3157 expressionS e1;
3158 int sep;
3159 sep = parse_operand (&e1);
3160
3161 if (e1.X_op != O_constant)
3162 as_bad ("Operand to .save.f must be a constant.");
3163 else
3164 add_unwind_entry (output_fr_mem (e1.X_add_number));
3165 }
3166
3167 static void
3168 dot_saveb (dummy)
3169 int dummy;
3170 {
3171 expressionS e1, e2;
3172 unsigned int reg;
3173 unsigned char sep;
3174 int brmask;
3175
3176 sep = parse_operand (&e1);
3177 if (e1.X_op != O_constant)
3178 {
3179 as_bad ("First operand to .save.b must be a constant.");
3180 return;
3181 }
3182 brmask = e1.X_add_number;
3183
3184 if (sep == ',')
3185 {
3186 sep = parse_operand (&e2);
3187 reg = e2.X_add_number - REG_GR;
3188 if (e2.X_op != O_register || reg > 127)
3189 {
3190 as_bad ("Second operand to .save.b must be a general register.");
3191 return;
3192 }
3193 add_unwind_entry (output_br_gr (brmask, e2.X_add_number));
3194 }
3195 else
3196 add_unwind_entry (output_br_mem (brmask));
3197
3198 if (!is_end_of_line[sep] && !is_it_end_of_statement ())
3199 ignore_rest_of_line ();
3200 }
3201
3202 static void
3203 dot_savegf (dummy)
3204 int dummy;
3205 {
3206 expressionS e1, e2;
3207 int sep;
3208 sep = parse_operand (&e1);
3209 if (sep == ',')
3210 parse_operand (&e2);
3211
3212 if (e1.X_op != O_constant || sep != ',' || e2.X_op != O_constant)
3213 as_bad ("Both operands of .save.gf must be constants.");
3214 else
3215 {
3216 int grmask = e1.X_add_number;
3217 int frmask = e2.X_add_number;
3218 add_unwind_entry (output_frgr_mem (grmask, frmask));
3219 }
3220 }
3221
3222 static void
3223 dot_spill (dummy)
3224 int dummy;
3225 {
3226 expressionS e;
3227 unsigned char sep;
3228
3229 sep = parse_operand (&e);
3230 if (!is_end_of_line[sep] && !is_it_end_of_statement ())
3231 ignore_rest_of_line ();
3232
3233 if (e.X_op != O_constant)
3234 as_bad ("Operand to .spill must be a constant");
3235 else
3236 add_unwind_entry (output_spill_base (e.X_add_number));
3237 }
3238
3239 static void
3240 dot_spillreg (dummy)
3241 int dummy;
3242 {
3243 int sep, ab, xy, reg, treg;
3244 expressionS e1, e2;
3245
3246 sep = parse_operand (&e1);
3247 if (sep != ',')
3248 {
3249 as_bad ("No second operand to .spillreg");
3250 return;
3251 }
3252
3253 parse_operand (&e2);
3254
3255 if (!convert_expr_to_ab_reg (&e1, &ab, &reg))
3256 {
3257 as_bad ("First operand to .spillreg must be a preserved register");
3258 return;
3259 }
3260
3261 if (!convert_expr_to_xy_reg (&e2, &xy, &treg))
3262 {
3263 as_bad ("Second operand to .spillreg must be a register");
3264 return;
3265 }
3266
3267 add_unwind_entry (output_spill_reg (ab, reg, treg, xy));
3268 }
3269
3270 static void
3271 dot_spillmem (psprel)
3272 int psprel;
3273 {
3274 expressionS e1, e2;
3275 int sep, ab, reg;
3276
3277 sep = parse_operand (&e1);
3278 if (sep != ',')
3279 {
3280 as_bad ("Second operand missing");
3281 return;
3282 }
3283
3284 parse_operand (&e2);
3285
3286 if (!convert_expr_to_ab_reg (&e1, &ab, &reg))
3287 {
3288 as_bad ("First operand to .spill%s must be a preserved register",
3289 psprel ? "psp" : "sp");
3290 return;
3291 }
3292
3293 if (e2.X_op != O_constant)
3294 {
3295 as_bad ("Second operand to .spill%s must be a constant",
3296 psprel ? "psp" : "sp");
3297 return;
3298 }
3299
3300 if (psprel)
3301 add_unwind_entry (output_spill_psprel (ab, reg, e2.X_add_number));
3302 else
3303 add_unwind_entry (output_spill_sprel (ab, reg, e2.X_add_number));
3304 }
3305
3306 static void
3307 dot_spillreg_p (dummy)
3308 int dummy;
3309 {
3310 int sep, ab, xy, reg, treg;
3311 expressionS e1, e2, e3;
3312 unsigned int qp;
3313
3314 sep = parse_operand (&e1);
3315 if (sep != ',')
3316 {
3317 as_bad ("No second and third operand to .spillreg.p");
3318 return;
3319 }
3320
3321 sep = parse_operand (&e2);
3322 if (sep != ',')
3323 {
3324 as_bad ("No third operand to .spillreg.p");
3325 return;
3326 }
3327
3328 parse_operand (&e3);
3329
3330 qp = e1.X_add_number - REG_P;
3331
3332 if (e1.X_op != O_register || qp > 63)
3333 {
3334 as_bad ("First operand to .spillreg.p must be a predicate");
3335 return;
3336 }
3337
3338 if (!convert_expr_to_ab_reg (&e2, &ab, &reg))
3339 {
3340 as_bad ("Second operand to .spillreg.p must be a preserved register");
3341 return;
3342 }
3343
3344 if (!convert_expr_to_xy_reg (&e3, &xy, &treg))
3345 {
3346 as_bad ("Third operand to .spillreg.p must be a register");
3347 return;
3348 }
3349
3350 add_unwind_entry (output_spill_reg_p (ab, reg, treg, xy, qp));
3351 }
3352
3353 static void
3354 dot_spillmem_p (psprel)
3355 int psprel;
3356 {
3357 expressionS e1, e2, e3;
3358 int sep, ab, reg;
3359 unsigned int qp;
3360
3361 sep = parse_operand (&e1);
3362 if (sep != ',')
3363 {
3364 as_bad ("Second operand missing");
3365 return;
3366 }
3367
3368 parse_operand (&e2);
3369 if (sep != ',')
3370 {
3371 as_bad ("Second operand missing");
3372 return;
3373 }
3374
3375 parse_operand (&e3);
3376
3377 qp = e1.X_add_number - REG_P;
3378 if (e1.X_op != O_register || qp > 63)
3379 {
3380 as_bad ("First operand to .spill%s_p must be a predicate",
3381 psprel ? "psp" : "sp");
3382 return;
3383 }
3384
3385 if (!convert_expr_to_ab_reg (&e2, &ab, &reg))
3386 {
3387 as_bad ("Second operand to .spill%s_p must be a preserved register",
3388 psprel ? "psp" : "sp");
3389 return;
3390 }
3391
3392 if (e3.X_op != O_constant)
3393 {
3394 as_bad ("Third operand to .spill%s_p must be a constant",
3395 psprel ? "psp" : "sp");
3396 return;
3397 }
3398
3399 if (psprel)
3400 add_unwind_entry (output_spill_psprel_p (qp, ab, reg, e3.X_add_number));
3401 else
3402 add_unwind_entry (output_spill_sprel_p (qp, ab, reg, e3.X_add_number));
3403 }
3404
3405 static void
3406 dot_label_state (dummy)
3407 int dummy;
3408 {
3409 expressionS e;
3410
3411 parse_operand (&e);
3412 if (e.X_op != O_constant)
3413 {
3414 as_bad ("Operand to .label_state must be a constant");
3415 return;
3416 }
3417 add_unwind_entry (output_label_state (e.X_add_number));
3418 }
3419
3420 static void
3421 dot_copy_state (dummy)
3422 int dummy;
3423 {
3424 expressionS e;
3425
3426 parse_operand (&e);
3427 if (e.X_op != O_constant)
3428 {
3429 as_bad ("Operand to .copy_state must be a constant");
3430 return;
3431 }
3432 add_unwind_entry (output_copy_state (e.X_add_number));
3433 }
3434
3435 static void
3436 dot_unwabi (dummy)
3437 int dummy;
3438 {
3439 expressionS e1, e2;
3440 unsigned char sep;
3441
3442 sep = parse_operand (&e1);
3443 if (sep != ',')
3444 {
3445 as_bad ("Second operand to .unwabi missing");
3446 return;
3447 }
3448 sep = parse_operand (&e2);
3449 if (!is_end_of_line[sep] && !is_it_end_of_statement ())
3450 ignore_rest_of_line ();
3451
3452 if (e1.X_op != O_constant)
3453 {
3454 as_bad ("First operand to .unwabi must be a constant");
3455 return;
3456 }
3457
3458 if (e2.X_op != O_constant)
3459 {
3460 as_bad ("Second operand to .unwabi must be a constant");
3461 return;
3462 }
3463
3464 add_unwind_entry (output_unwabi (e1.X_add_number, e2.X_add_number));
3465 }
3466
3467 static void
3468 dot_personality (dummy)
3469 int dummy;
3470 {
3471 char *name, *p, c;
3472 SKIP_WHITESPACE ();
3473 name = input_line_pointer;
3474 c = get_symbol_end ();
3475 p = input_line_pointer;
3476 unwind.personality_routine = symbol_find_or_make (name);
3477 *p = c;
3478 SKIP_WHITESPACE ();
3479 demand_empty_rest_of_line ();
3480 }
3481
3482 static void
3483 dot_proc (dummy)
3484 int dummy;
3485 {
3486 char *name, *p, c;
3487 symbolS *sym;
3488
3489 unwind.proc_start = expr_build_dot ();
3490 /* Parse names of main and alternate entry points and mark them as
3491 function symbols: */
3492 while (1)
3493 {
3494 SKIP_WHITESPACE ();
3495 name = input_line_pointer;
3496 c = get_symbol_end ();
3497 p = input_line_pointer;
3498 sym = symbol_find_or_make (name);
3499 if (unwind.proc_start == 0)
3500 {
3501 unwind.proc_start = sym;
3502 }
3503 symbol_get_bfdsym (sym)->flags |= BSF_FUNCTION;
3504 *p = c;
3505 SKIP_WHITESPACE ();
3506 if (*input_line_pointer != ',')
3507 break;
3508 ++input_line_pointer;
3509 }
3510 demand_empty_rest_of_line ();
3511 ia64_do_align (16);
3512
3513 unwind.list = unwind.tail = unwind.current_entry = NULL;
3514 unwind.personality_routine = 0;
3515 }
3516
3517 static void
3518 dot_body (dummy)
3519 int dummy;
3520 {
3521 unwind.prologue = 0;
3522 unwind.prologue_mask = 0;
3523
3524 add_unwind_entry (output_body ());
3525 demand_empty_rest_of_line ();
3526 }
3527
3528 static void
3529 dot_prologue (dummy)
3530 int dummy;
3531 {
3532 unsigned char sep;
3533 int mask = 0, grsave;
3534
3535 if (!is_it_end_of_statement ())
3536 {
3537 expressionS e1, e2;
3538 sep = parse_operand (&e1);
3539 if (sep != ',')
3540 as_bad ("No second operand to .prologue");
3541 sep = parse_operand (&e2);
3542 if (!is_end_of_line[sep] && !is_it_end_of_statement ())
3543 ignore_rest_of_line ();
3544
3545 if (e1.X_op == O_constant)
3546 {
3547 mask = e1.X_add_number;
3548
3549 if (e2.X_op == O_constant)
3550 grsave = e2.X_add_number;
3551 else if (e2.X_op == O_register
3552 && (grsave = e2.X_add_number - REG_GR) < 128)
3553 ;
3554 else
3555 as_bad ("Second operand not a constant or general register");
3556
3557 add_unwind_entry (output_prologue_gr (mask, grsave));
3558 }
3559 else
3560 as_bad ("First operand not a constant");
3561 }
3562 else
3563 add_unwind_entry (output_prologue ());
3564
3565 unwind.prologue = 1;
3566 unwind.prologue_mask = mask;
3567 }
3568
3569 static void
3570 dot_endp (dummy)
3571 int dummy;
3572 {
3573 expressionS e;
3574 unsigned char *ptr;
3575 long where;
3576 segT saved_seg;
3577 subsegT saved_subseg;
3578
3579 saved_seg = now_seg;
3580 saved_subseg = now_subseg;
3581
3582 expression (&e);
3583 demand_empty_rest_of_line ();
3584
3585 insn_group_break (1, 0, 0);
3586
3587 /* If there was a .handlerdata, we haven't generated an image yet. */
3588 if (unwind.info == 0)
3589 {
3590 generate_unwind_image ();
3591 }
3592
3593 subseg_set (md.last_text_seg, 0);
3594 unwind.proc_end = expr_build_dot ();
3595
3596 set_section ((char *) special_section_name[SPECIAL_SECTION_UNWIND]);
3597 ptr = frag_more (24);
3598 where = frag_now_fix () - 24;
3599
3600 /* Issue the values of a) Proc Begin, b) Proc End, c) Unwind Record. */
3601 e.X_op = O_pseudo_fixup;
3602 e.X_op_symbol = pseudo_func[FUNC_SEG_RELATIVE].u.sym;
3603 e.X_add_number = 0;
3604 e.X_add_symbol = unwind.proc_start;
3605 ia64_cons_fix_new (frag_now, where, 8, &e);
3606
3607 e.X_op = O_pseudo_fixup;
3608 e.X_op_symbol = pseudo_func[FUNC_SEG_RELATIVE].u.sym;
3609 e.X_add_number = 0;
3610 e.X_add_symbol = unwind.proc_end;
3611 ia64_cons_fix_new (frag_now, where + 8, 8, &e);
3612
3613 if (unwind.info != 0)
3614 {
3615 e.X_op = O_pseudo_fixup;
3616 e.X_op_symbol = pseudo_func[FUNC_SEG_RELATIVE].u.sym;
3617 e.X_add_number = 0;
3618 e.X_add_symbol = unwind.info;
3619 ia64_cons_fix_new (frag_now, where + 16, 8, &e);
3620 }
3621 else
3622 md_number_to_chars (ptr + 16, 0, 8);
3623
3624 subseg_set (saved_seg, saved_subseg);
3625 unwind.proc_start = unwind.proc_end = unwind.info = 0;
3626 }
3627
3628 static void
3629 dot_template (template)
3630 int template;
3631 {
3632 CURR_SLOT.user_template = template;
3633 }
3634
3635 static void
3636 dot_regstk (dummy)
3637 int dummy;
3638 {
3639 int ins, locs, outs, rots;
3640
3641 if (is_it_end_of_statement ())
3642 ins = locs = outs = rots = 0;
3643 else
3644 {
3645 ins = get_absolute_expression ();
3646 if (*input_line_pointer++ != ',')
3647 goto err;
3648 locs = get_absolute_expression ();
3649 if (*input_line_pointer++ != ',')
3650 goto err;
3651 outs = get_absolute_expression ();
3652 if (*input_line_pointer++ != ',')
3653 goto err;
3654 rots = get_absolute_expression ();
3655 }
3656 set_regstack (ins, locs, outs, rots);
3657 return;
3658
3659 err:
3660 as_bad ("Comma expected");
3661 ignore_rest_of_line ();
3662 }
3663
3664 static void
3665 dot_rot (type)
3666 int type;
3667 {
3668 unsigned num_regs, num_alloced = 0;
3669 struct dynreg **drpp, *dr;
3670 int ch, base_reg = 0;
3671 char *name, *start;
3672 size_t len;
3673
3674 switch (type)
3675 {
3676 case DYNREG_GR: base_reg = REG_GR + 32; break;
3677 case DYNREG_FR: base_reg = REG_FR + 32; break;
3678 case DYNREG_PR: base_reg = REG_P + 16; break;
3679 default: break;
3680 }
3681
3682 /* first, remove existing names from hash table: */
3683 for (dr = md.dynreg[type]; dr && dr->num_regs; dr = dr->next)
3684 {
3685 hash_delete (md.dynreg_hash, dr->name);
3686 dr->num_regs = 0;
3687 }
3688
3689 drpp = &md.dynreg[type];
3690 while (1)
3691 {
3692 start = input_line_pointer;
3693 ch = get_symbol_end ();
3694 *input_line_pointer = ch;
3695 len = (input_line_pointer - start);
3696
3697 SKIP_WHITESPACE ();
3698 if (*input_line_pointer != '[')
3699 {
3700 as_bad ("Expected '['");
3701 goto err;
3702 }
3703 ++input_line_pointer; /* skip '[' */
3704
3705 num_regs = get_absolute_expression ();
3706
3707 if (*input_line_pointer++ != ']')
3708 {
3709 as_bad ("Expected ']'");
3710 goto err;
3711 }
3712 SKIP_WHITESPACE ();
3713
3714 num_alloced += num_regs;
3715 switch (type)
3716 {
3717 case DYNREG_GR:
3718 if (num_alloced > md.rot.num_regs)
3719 {
3720 as_bad ("Used more than the declared %d rotating registers",
3721 md.rot.num_regs);
3722 goto err;
3723 }
3724 break;
3725 case DYNREG_FR:
3726 if (num_alloced > 96)
3727 {
3728 as_bad ("Used more than the available 96 rotating registers");
3729 goto err;
3730 }
3731 break;
3732 case DYNREG_PR:
3733 if (num_alloced > 48)
3734 {
3735 as_bad ("Used more than the available 48 rotating registers");
3736 goto err;
3737 }
3738 break;
3739
3740 default:
3741 break;
3742 }
3743
3744 name = obstack_alloc (&notes, len + 1);
3745 memcpy (name, start, len);
3746 name[len] = '\0';
3747
3748 if (!*drpp)
3749 {
3750 *drpp = obstack_alloc (&notes, sizeof (*dr));
3751 memset (*drpp, 0, sizeof (*dr));
3752 }
3753
3754 dr = *drpp;
3755 dr->name = name;
3756 dr->num_regs = num_regs;
3757 dr->base = base_reg;
3758 drpp = &dr->next;
3759 base_reg += num_regs;
3760
3761 if (hash_insert (md.dynreg_hash, name, dr))
3762 {
3763 as_bad ("Attempt to redefine register set `%s'", name);
3764 goto err;
3765 }
3766
3767 if (*input_line_pointer != ',')
3768 break;
3769 ++input_line_pointer; /* skip comma */
3770 SKIP_WHITESPACE ();
3771 }
3772 demand_empty_rest_of_line ();
3773 return;
3774
3775 err:
3776 ignore_rest_of_line ();
3777 }
3778
3779 static void
3780 dot_byteorder (byteorder)
3781 int byteorder;
3782 {
3783 target_big_endian = byteorder;
3784 }
3785
3786 static void
3787 dot_psr (dummy)
3788 int dummy;
3789 {
3790 char *option;
3791 int ch;
3792
3793 while (1)
3794 {
3795 option = input_line_pointer;
3796 ch = get_symbol_end ();
3797 if (strcmp (option, "lsb") == 0)
3798 md.flags &= ~EF_IA_64_BE;
3799 else if (strcmp (option, "msb") == 0)
3800 md.flags |= EF_IA_64_BE;
3801 else if (strcmp (option, "abi32") == 0)
3802 md.flags &= ~EF_IA_64_ABI64;
3803 else if (strcmp (option, "abi64") == 0)
3804 md.flags |= EF_IA_64_ABI64;
3805 else
3806 as_bad ("Unknown psr option `%s'", option);
3807 *input_line_pointer = ch;
3808
3809 SKIP_WHITESPACE ();
3810 if (*input_line_pointer != ',')
3811 break;
3812
3813 ++input_line_pointer;
3814 SKIP_WHITESPACE ();
3815 }
3816 demand_empty_rest_of_line ();
3817 }
3818
3819 static void
3820 dot_alias (dummy)
3821 int dummy;
3822 {
3823 as_bad (".alias not implemented yet");
3824 }
3825
3826 static void
3827 dot_ln (dummy)
3828 int dummy;
3829 {
3830 new_logical_line (0, get_absolute_expression ());
3831 demand_empty_rest_of_line ();
3832 }
3833
3834 static char*
3835 parse_section_name ()
3836 {
3837 char *name;
3838 int len;
3839
3840 SKIP_WHITESPACE ();
3841 if (*input_line_pointer != '"')
3842 {
3843 as_bad ("Missing section name");
3844 ignore_rest_of_line ();
3845 return 0;
3846 }
3847 name = demand_copy_C_string (&len);
3848 if (!name)
3849 {
3850 ignore_rest_of_line ();
3851 return 0;
3852 }
3853 SKIP_WHITESPACE ();
3854 if (*input_line_pointer != ',')
3855 {
3856 as_bad ("Comma expected after section name");
3857 ignore_rest_of_line ();
3858 return 0;
3859 }
3860 ++input_line_pointer; /* skip comma */
3861 return name;
3862 }
3863
3864 static void
3865 dot_xdata (size)
3866 int size;
3867 {
3868 char *name = parse_section_name ();
3869 if (!name)
3870 return;
3871
3872 set_section (name);
3873 cons (size);
3874 obj_elf_previous (0);
3875 }
3876
3877 /* Why doesn't float_cons() call md_cons_align() the way cons() does? */
3878 static void
3879 stmt_float_cons (kind)
3880 int kind;
3881 {
3882 size_t size;
3883
3884 switch (kind)
3885 {
3886 case 'd': size = 8; break;
3887 case 'x': size = 10; break;
3888
3889 case 'f':
3890 default:
3891 size = 4;
3892 break;
3893 }
3894 ia64_do_align (size);
3895 float_cons (kind);
3896 }
3897
3898 static void
3899 stmt_cons_ua (size)
3900 int size;
3901 {
3902 int saved_auto_align = md.auto_align;
3903
3904 md.auto_align = 0;
3905 cons (size);
3906 md.auto_align = saved_auto_align;
3907 }
3908
3909 static void
3910 dot_xfloat_cons (kind)
3911 int kind;
3912 {
3913 char *name = parse_section_name ();
3914 if (!name)
3915 return;
3916
3917 set_section (name);
3918 stmt_float_cons (kind);
3919 obj_elf_previous (0);
3920 }
3921
3922 static void
3923 dot_xstringer (zero)
3924 int zero;
3925 {
3926 char *name = parse_section_name ();
3927 if (!name)
3928 return;
3929
3930 set_section (name);
3931 stringer (zero);
3932 obj_elf_previous (0);
3933 }
3934
3935 static void
3936 dot_xdata_ua (size)
3937 int size;
3938 {
3939 int saved_auto_align = md.auto_align;
3940 char *name = parse_section_name ();
3941 if (!name)
3942 return;
3943
3944 set_section (name);
3945 md.auto_align = 0;
3946 cons (size);
3947 md.auto_align = saved_auto_align;
3948 obj_elf_previous (0);
3949 }
3950
3951 static void
3952 dot_xfloat_cons_ua (kind)
3953 int kind;
3954 {
3955 int saved_auto_align = md.auto_align;
3956 char *name = parse_section_name ();
3957 if (!name)
3958 return;
3959
3960 set_section (name);
3961 md.auto_align = 0;
3962 stmt_float_cons (kind);
3963 md.auto_align = saved_auto_align;
3964 obj_elf_previous (0);
3965 }
3966
3967 /* .reg.val <regname>,value */
3968 static void
3969 dot_reg_val (dummy)
3970 int dummy;
3971 {
3972 expressionS reg;
3973
3974 expression (&reg);
3975 if (reg.X_op != O_register)
3976 {
3977 as_bad (_("Register name expected"));
3978 ignore_rest_of_line ();
3979 }
3980 else if (*input_line_pointer++ != ',')
3981 {
3982 as_bad (_("Comma expected"));
3983 ignore_rest_of_line ();
3984 }
3985 else
3986 {
3987 valueT value = get_absolute_expression ();
3988 int regno = reg.X_add_number;
3989 if (regno < REG_GR || regno > REG_GR+128)
3990 as_warn (_("Register value annotation ignored"));
3991 else
3992 {
3993 gr_values[regno-REG_GR].known = 1;
3994 gr_values[regno-REG_GR].value = value;
3995 gr_values[regno-REG_GR].path = md.path;
3996 }
3997 }
3998 demand_empty_rest_of_line ();
3999 }
4000
4001 /* select dv checking mode
4002 .auto
4003 .explicit
4004 .default
4005
4006 A stop is inserted when changing modes
4007 */
4008 static void
4009 dot_dv_mode (type)
4010 int type;
4011 {
4012 if (md.manual_bundling)
4013 as_warn (_("Directive invalid within a bundle"));
4014
4015 if (type == 'E' || type == 'A')
4016 md.mode_explicitly_set = 0;
4017 else
4018 md.mode_explicitly_set = 1;
4019
4020 md.detect_dv = 1;
4021 switch (type)
4022 {
4023 case 'A':
4024 case 'a':
4025 if (md.explicit_mode)
4026 insn_group_break (1, 0, 0);
4027 md.explicit_mode = 0;
4028 break;
4029 case 'E':
4030 case 'e':
4031 if (!md.explicit_mode)
4032 insn_group_break (1, 0, 0);
4033 md.explicit_mode = 1;
4034 break;
4035 default:
4036 case 'd':
4037 if (md.explicit_mode != md.default_explicit_mode)
4038 insn_group_break (1, 0, 0);
4039 md.explicit_mode = md.default_explicit_mode;
4040 md.mode_explicitly_set = 0;
4041 break;
4042 }
4043 }
4044
4045 static void
4046 print_prmask (mask)
4047 valueT mask;
4048 {
4049 int regno;
4050 char *comma = "";
4051 for (regno = 0;regno < 64;regno++)
4052 {
4053 if (mask & ((valueT)1<<regno))
4054 {
4055 fprintf (stderr, "%s p%d", comma, regno);
4056 comma = ",";
4057 }
4058 }
4059 }
4060
4061 /*
4062 .pred.rel.clear [p1 [,p2 [,...]]] (also .pred.rel "clear")
4063 .pred.rel.imply p1, p2 (also .pred.rel "imply")
4064 .pred.rel.mutex p1, p2 [,...] (also .pred.rel "mutex")
4065 .pred.safe_across_calls p1 [, p2 [,...]]
4066 */
4067 static void
4068 dot_pred_rel (type)
4069 int type;
4070 {
4071 valueT mask = 0;
4072 int count = 0;
4073 int p1 = -1, p2 = -1;
4074
4075 if (type == 0)
4076 {
4077 if (*input_line_pointer != '"')
4078 {
4079 as_bad (_("Missing predicate relation type"));
4080 ignore_rest_of_line ();
4081 return;
4082 }
4083 else
4084 {
4085 int len;
4086 char *form = demand_copy_C_string (&len);
4087 if (strcmp (form, "mutex") == 0)
4088 type = 'm';
4089 else if (strcmp (form, "clear") == 0)
4090 type = 'c';
4091 else if (strcmp (form, "imply") == 0)
4092 type = 'i';
4093 else
4094 {
4095 as_bad (_("Unrecognized predicate relation type"));
4096 ignore_rest_of_line ();
4097 return;
4098 }
4099 }
4100 if (*input_line_pointer == ',')
4101 ++input_line_pointer;
4102 SKIP_WHITESPACE ();
4103 }
4104
4105 SKIP_WHITESPACE ();
4106 while (1)
4107 {
4108 valueT bit = 1;
4109 int regno;
4110
4111 if (toupper (*input_line_pointer) != 'P'
4112 || (regno = atoi (++input_line_pointer)) < 0
4113 || regno > 63)
4114 {
4115 as_bad (_("Predicate register expected"));
4116 ignore_rest_of_line ();
4117 return;
4118 }
4119 while (isdigit (*input_line_pointer))
4120 ++input_line_pointer;
4121 if (p1 == -1)
4122 p1 = regno;
4123 else if (p2 == -1)
4124 p2 = regno;
4125 bit <<= regno;
4126 if (mask & bit)
4127 as_warn (_("Duplicate predicate register ignored"));
4128 mask |= bit; count++;
4129 /* see if it's a range */
4130 if (*input_line_pointer == '-')
4131 {
4132 valueT stop = 1;
4133 ++input_line_pointer;
4134
4135 if (toupper (*input_line_pointer) != 'P'
4136 || (regno = atoi (++input_line_pointer)) < 0
4137 || regno > 63)
4138 {
4139 as_bad (_("Predicate register expected"));
4140 ignore_rest_of_line ();
4141 return;
4142 }
4143 while (isdigit (*input_line_pointer))
4144 ++input_line_pointer;
4145 stop <<= regno;
4146 if (bit >= stop)
4147 {
4148 as_bad (_("Bad register range"));
4149 ignore_rest_of_line ();
4150 return;
4151 }
4152 while (bit < stop)
4153 {
4154 bit <<= 1;
4155 mask |= bit; count++;
4156 }
4157 SKIP_WHITESPACE ();
4158 }
4159 if (*input_line_pointer != ',')
4160 break;
4161 ++input_line_pointer;
4162 SKIP_WHITESPACE ();
4163 }
4164
4165 switch (type)
4166 {
4167 case 'c':
4168 if (count == 0)
4169 mask = ~(valueT)0;
4170 clear_qp_mutex (mask);
4171 clear_qp_implies (mask, (valueT)0);
4172 break;
4173 case 'i':
4174 if (count != 2 || p1 == -1 || p2 == -1)
4175 as_bad (_("Predicate source and target required"));
4176 else if (p1 == 0 || p2 == 0)
4177 as_bad (_("Use of p0 is not valid in this context"));
4178 else
4179 add_qp_imply (p1, p2);
4180 break;
4181 case 'm':
4182 if (count < 2)
4183 {
4184 as_bad (_("At least two PR arguments expected"));
4185 break;
4186 }
4187 else if (mask & 1)
4188 {
4189 as_bad (_("Use of p0 is not valid in this context"));
4190 break;
4191 }
4192 add_qp_mutex (mask);
4193 break;
4194 case 's':
4195 /* note that we don't override any existing relations */
4196 if (count == 0)
4197 {
4198 as_bad (_("At least one PR argument expected"));
4199 break;
4200 }
4201 if (md.debug_dv)
4202 {
4203 fprintf (stderr, "Safe across calls: ");
4204 print_prmask (mask);
4205 fprintf (stderr, "\n");
4206 }
4207 qp_safe_across_calls = mask;
4208 break;
4209 }
4210 demand_empty_rest_of_line ();
4211 }
4212
4213 /* .entry label [, label [, ...]]
4214 Hint to DV code that the given labels are to be considered entry points.
4215 Otherwise, only global labels are considered entry points.
4216 */
4217 static void
4218 dot_entry (dummy)
4219 int dummy;
4220 {
4221 const char *err;
4222 char *name;
4223 int c;
4224 symbolS *symbolP;
4225
4226 do
4227 {
4228 name = input_line_pointer;
4229 c = get_symbol_end ();
4230 symbolP = symbol_find_or_make (name);
4231
4232 err = hash_insert (md.entry_hash, S_GET_NAME (symbolP), (PTR) symbolP);
4233 if (err)
4234 as_fatal (_("Inserting \"%s\" into entry hint table failed: %s"),
4235 name, err);
4236
4237 *input_line_pointer = c;
4238 SKIP_WHITESPACE ();
4239 c = *input_line_pointer;
4240 if (c == ',')
4241 {
4242 input_line_pointer++;
4243 SKIP_WHITESPACE ();
4244 if (*input_line_pointer == '\n')
4245 c = '\n';
4246 }
4247 }
4248 while (c == ',');
4249
4250 demand_empty_rest_of_line ();
4251 }
4252
4253 /* .mem.offset offset, base
4254 "base" is used to distinguish between offsets from a different base.
4255 */
4256 static void
4257 dot_mem_offset (dummy)
4258 int dummy;
4259 {
4260 md.mem_offset.hint = 1;
4261 md.mem_offset.offset = get_absolute_expression ();
4262 if (*input_line_pointer != ',')
4263 {
4264 as_bad (_("Comma expected"));
4265 ignore_rest_of_line ();
4266 return;
4267 }
4268 ++input_line_pointer;
4269 md.mem_offset.base = get_absolute_expression ();
4270 demand_empty_rest_of_line ();
4271 }
4272
4273 /* ia64-specific pseudo-ops: */
4274 const pseudo_typeS md_pseudo_table[] =
4275 {
4276 { "radix", dot_radix, 0 },
4277 { "lcomm", s_lcomm_bytes, 1 },
4278 { "bss", dot_special_section, SPECIAL_SECTION_BSS },
4279 { "sbss", dot_special_section, SPECIAL_SECTION_SBSS },
4280 { "sdata", dot_special_section, SPECIAL_SECTION_SDATA },
4281 { "rodata", dot_special_section, SPECIAL_SECTION_RODATA },
4282 { "comment", dot_special_section, SPECIAL_SECTION_COMMENT },
4283 { "ia_64.unwind", dot_special_section, SPECIAL_SECTION_UNWIND },
4284 { "ia_64.unwind_info", dot_special_section, SPECIAL_SECTION_UNWIND_INFO },
4285 { "proc", dot_proc, 0 },
4286 { "body", dot_body, 0 },
4287 { "prologue", dot_prologue, 0 },
4288 { "endp", dot_endp },
4289 { "file", dwarf2_directive_file },
4290 { "loc", dwarf2_directive_loc },
4291
4292 { "fframe", dot_fframe },
4293 { "vframe", dot_vframe },
4294 { "vframesp", dot_vframesp },
4295 { "vframepsp", dot_vframepsp },
4296 { "save", dot_save },
4297 { "restore", dot_restore },
4298 { "restorereg", dot_restorereg },
4299 { "restorereg.p", dot_restorereg_p },
4300 { "handlerdata", dot_handlerdata },
4301 { "unwentry", dot_unwentry },
4302 { "altrp", dot_altrp },
4303 { "savesp", dot_savemem, 0 },
4304 { "savepsp", dot_savemem, 1 },
4305 { "save.g", dot_saveg },
4306 { "save.f", dot_savef },
4307 { "save.b", dot_saveb },
4308 { "save.gf", dot_savegf },
4309 { "spill", dot_spill },
4310 { "spillreg", dot_spillreg },
4311 { "spillsp", dot_spillmem, 0 },
4312 { "spillpsp", dot_spillmem, 1 },
4313 { "spillreg.p", dot_spillreg_p },
4314 { "spillsp.p", dot_spillmem_p, 0 },
4315 { "spillpsp.p", dot_spillmem_p, 1 },
4316 { "label_state", dot_label_state },
4317 { "copy_state", dot_copy_state },
4318 { "unwabi", dot_unwabi },
4319 { "personality", dot_personality },
4320 #if 0
4321 { "estate", dot_estate },
4322 #endif
4323 { "mii", dot_template, 0x0 },
4324 { "mli", dot_template, 0x2 }, /* old format, for compatibility */
4325 { "mlx", dot_template, 0x2 },
4326 { "mmi", dot_template, 0x4 },
4327 { "mfi", dot_template, 0x6 },
4328 { "mmf", dot_template, 0x7 },
4329 { "mib", dot_template, 0x8 },
4330 { "mbb", dot_template, 0x9 },
4331 { "bbb", dot_template, 0xb },
4332 { "mmb", dot_template, 0xc },
4333 { "mfb", dot_template, 0xe },
4334 #if 0
4335 { "lb", dot_scope, 0 },
4336 { "le", dot_scope, 1 },
4337 #endif
4338 { "align", s_align_bytes, 0 },
4339 { "regstk", dot_regstk, 0 },
4340 { "rotr", dot_rot, DYNREG_GR },
4341 { "rotf", dot_rot, DYNREG_FR },
4342 { "rotp", dot_rot, DYNREG_PR },
4343 { "lsb", dot_byteorder, 0 },
4344 { "msb", dot_byteorder, 1 },
4345 { "psr", dot_psr, 0 },
4346 { "alias", dot_alias, 0 },
4347 { "ln", dot_ln, 0 }, /* source line info (for debugging) */
4348
4349 { "xdata1", dot_xdata, 1 },
4350 { "xdata2", dot_xdata, 2 },
4351 { "xdata4", dot_xdata, 4 },
4352 { "xdata8", dot_xdata, 8 },
4353 { "xreal4", dot_xfloat_cons, 'f' },
4354 { "xreal8", dot_xfloat_cons, 'd' },
4355 { "xreal10", dot_xfloat_cons, 'x' },
4356 { "xstring", dot_xstringer, 0 },
4357 { "xstringz", dot_xstringer, 1 },
4358
4359 /* unaligned versions: */
4360 { "xdata2.ua", dot_xdata_ua, 2 },
4361 { "xdata4.ua", dot_xdata_ua, 4 },
4362 { "xdata8.ua", dot_xdata_ua, 8 },
4363 { "xreal4.ua", dot_xfloat_cons_ua, 'f' },
4364 { "xreal8.ua", dot_xfloat_cons_ua, 'd' },
4365 { "xreal10.ua", dot_xfloat_cons_ua, 'x' },
4366
4367 /* annotations/DV checking support */
4368 { "entry", dot_entry, 0 },
4369 { "mem.offset", dot_mem_offset },
4370 { "pred.rel", dot_pred_rel, 0 },
4371 { "pred.rel.clear", dot_pred_rel, 'c' },
4372 { "pred.rel.imply", dot_pred_rel, 'i' },
4373 { "pred.rel.mutex", dot_pred_rel, 'm' },
4374 { "pred.safe_across_calls", dot_pred_rel, 's' },
4375 { "reg.val", dot_reg_val },
4376 { "auto", dot_dv_mode, 'a' },
4377 { "explicit", dot_dv_mode, 'e' },
4378 { "default", dot_dv_mode, 'd' },
4379
4380 { NULL, 0, 0 }
4381 };
4382
4383 static const struct pseudo_opcode
4384 {
4385 const char *name;
4386 void (*handler) (int);
4387 int arg;
4388 }
4389 pseudo_opcode[] =
4390 {
4391 /* these are more like pseudo-ops, but don't start with a dot */
4392 { "data1", cons, 1 },
4393 { "data2", cons, 2 },
4394 { "data4", cons, 4 },
4395 { "data8", cons, 8 },
4396 { "real4", stmt_float_cons, 'f' },
4397 { "real8", stmt_float_cons, 'd' },
4398 { "real10", stmt_float_cons, 'x' },
4399 { "string", stringer, 0 },
4400 { "stringz", stringer, 1 },
4401
4402 /* unaligned versions: */
4403 { "data2.ua", stmt_cons_ua, 2 },
4404 { "data4.ua", stmt_cons_ua, 4 },
4405 { "data8.ua", stmt_cons_ua, 8 },
4406 { "real4.ua", float_cons, 'f' },
4407 { "real8.ua", float_cons, 'd' },
4408 { "real10.ua", float_cons, 'x' },
4409 };
4410
4411 /* Declare a register by creating a symbol for it and entering it in
4412 the symbol table. */
4413 static symbolS*
4414 declare_register (name, regnum)
4415 const char *name;
4416 int regnum;
4417 {
4418 const char *err;
4419 symbolS *sym;
4420
4421 sym = symbol_new (name, reg_section, regnum, &zero_address_frag);
4422
4423 err = hash_insert (md.reg_hash, S_GET_NAME (sym), (PTR) sym);
4424 if (err)
4425 as_fatal ("Inserting \"%s\" into register table failed: %s",
4426 name, err);
4427
4428 return sym;
4429 }
4430
4431 static void
4432 declare_register_set (prefix, num_regs, base_regnum)
4433 const char *prefix;
4434 int num_regs;
4435 int base_regnum;
4436 {
4437 char name[8];
4438 int i;
4439
4440 for (i = 0; i < num_regs; ++i)
4441 {
4442 sprintf (name, "%s%u", prefix, i);
4443 declare_register (name, base_regnum + i);
4444 }
4445 }
4446
4447 static unsigned int
4448 operand_width (opnd)
4449 enum ia64_opnd opnd;
4450 {
4451 const struct ia64_operand *odesc = &elf64_ia64_operands[opnd];
4452 unsigned int bits = 0;
4453 int i;
4454
4455 bits = 0;
4456 for (i = 0; i < NELEMS (odesc->field) && odesc->field[i].bits; ++i)
4457 bits += odesc->field[i].bits;
4458
4459 return bits;
4460 }
4461
4462 static int
4463 operand_match (idesc, index, e)
4464 const struct ia64_opcode *idesc;
4465 int index;
4466 expressionS *e;
4467 {
4468 enum ia64_opnd opnd = idesc->operands[index];
4469 int bits, relocatable = 0;
4470 struct insn_fix *fix;
4471 bfd_signed_vma val;
4472
4473 switch (opnd)
4474 {
4475 /* constants: */
4476
4477 case IA64_OPND_AR_CCV:
4478 if (e->X_op == O_register && e->X_add_number == REG_AR + 32)
4479 return 1;
4480 break;
4481
4482 case IA64_OPND_AR_PFS:
4483 if (e->X_op == O_register && e->X_add_number == REG_AR + 64)
4484 return 1;
4485 break;
4486
4487 case IA64_OPND_GR0:
4488 if (e->X_op == O_register && e->X_add_number == REG_GR + 0)
4489 return 1;
4490 break;
4491
4492 case IA64_OPND_IP:
4493 if (e->X_op == O_register && e->X_add_number == REG_IP)
4494 return 1;
4495 break;
4496
4497 case IA64_OPND_PR:
4498 if (e->X_op == O_register && e->X_add_number == REG_PR)
4499 return 1;
4500 break;
4501
4502 case IA64_OPND_PR_ROT:
4503 if (e->X_op == O_register && e->X_add_number == REG_PR_ROT)
4504 return 1;
4505 break;
4506
4507 case IA64_OPND_PSR:
4508 if (e->X_op == O_register && e->X_add_number == REG_PSR)
4509 return 1;
4510 break;
4511
4512 case IA64_OPND_PSR_L:
4513 if (e->X_op == O_register && e->X_add_number == REG_PSR_L)
4514 return 1;
4515 break;
4516
4517 case IA64_OPND_PSR_UM:
4518 if (e->X_op == O_register && e->X_add_number == REG_PSR_UM)
4519 return 1;
4520 break;
4521
4522 case IA64_OPND_C1:
4523 if (e->X_op == O_constant && e->X_add_number == 1)
4524 return 1;
4525 break;
4526
4527 case IA64_OPND_C8:
4528 if (e->X_op == O_constant && e->X_add_number == 8)
4529 return 1;
4530 break;
4531
4532 case IA64_OPND_C16:
4533 if (e->X_op == O_constant && e->X_add_number == 16)
4534 return 1;
4535 break;
4536
4537 /* register operands: */
4538
4539 case IA64_OPND_AR3:
4540 if (e->X_op == O_register && e->X_add_number >= REG_AR
4541 && e->X_add_number < REG_AR + 128)
4542 return 1;
4543 break;
4544
4545 case IA64_OPND_B1:
4546 case IA64_OPND_B2:
4547 if (e->X_op == O_register && e->X_add_number >= REG_BR
4548 && e->X_add_number < REG_BR + 8)
4549 return 1;
4550 break;
4551
4552 case IA64_OPND_CR3:
4553 if (e->X_op == O_register && e->X_add_number >= REG_CR
4554 && e->X_add_number < REG_CR + 128)
4555 return 1;
4556 break;
4557
4558 case IA64_OPND_F1:
4559 case IA64_OPND_F2:
4560 case IA64_OPND_F3:
4561 case IA64_OPND_F4:
4562 if (e->X_op == O_register && e->X_add_number >= REG_FR
4563 && e->X_add_number < REG_FR + 128)
4564 return 1;
4565 break;
4566
4567 case IA64_OPND_P1:
4568 case IA64_OPND_P2:
4569 if (e->X_op == O_register && e->X_add_number >= REG_P
4570 && e->X_add_number < REG_P + 64)
4571 return 1;
4572 break;
4573
4574 case IA64_OPND_R1:
4575 case IA64_OPND_R2:
4576 case IA64_OPND_R3:
4577 if (e->X_op == O_register && e->X_add_number >= REG_GR
4578 && e->X_add_number < REG_GR + 128)
4579 return 1;
4580 break;
4581
4582 case IA64_OPND_R3_2:
4583 if (e->X_op == O_register && e->X_add_number >= REG_GR
4584 && e->X_add_number < REG_GR + 4)
4585 return 1;
4586 break;
4587
4588 /* indirect operands: */
4589 case IA64_OPND_CPUID_R3:
4590 case IA64_OPND_DBR_R3:
4591 case IA64_OPND_DTR_R3:
4592 case IA64_OPND_ITR_R3:
4593 case IA64_OPND_IBR_R3:
4594 case IA64_OPND_MSR_R3:
4595 case IA64_OPND_PKR_R3:
4596 case IA64_OPND_PMC_R3:
4597 case IA64_OPND_PMD_R3:
4598 case IA64_OPND_RR_R3:
4599 if (e->X_op == O_index && e->X_op_symbol
4600 && (S_GET_VALUE (e->X_op_symbol) - IND_CPUID
4601 == opnd - IA64_OPND_CPUID_R3))
4602 return 1;
4603 break;
4604
4605 case IA64_OPND_MR3:
4606 if (e->X_op == O_index && !e->X_op_symbol)
4607 return 1;
4608 break;
4609
4610 /* immediate operands: */
4611 case IA64_OPND_CNT2a:
4612 case IA64_OPND_LEN4:
4613 case IA64_OPND_LEN6:
4614 bits = operand_width (idesc->operands[index]);
4615 if (e->X_op == O_constant
4616 && (bfd_vma) (e->X_add_number - 1) < ((bfd_vma) 1 << bits))
4617 return 1;
4618 break;
4619
4620 case IA64_OPND_CNT2b:
4621 if (e->X_op == O_constant
4622 && (bfd_vma) (e->X_add_number - 1) < 3)
4623 return 1;
4624 break;
4625
4626 case IA64_OPND_CNT2c:
4627 val = e->X_add_number;
4628 if (e->X_op == O_constant
4629 && (val == 0 || val == 7 || val == 15 || val == 16))
4630 return 1;
4631 break;
4632
4633 case IA64_OPND_SOR:
4634 /* SOR must be an integer multiple of 8 */
4635 if (e->X_add_number & 0x7)
4636 break;
4637 case IA64_OPND_SOF:
4638 case IA64_OPND_SOL:
4639 if (e->X_op == O_constant &&
4640 (bfd_vma) e->X_add_number <= 96)
4641 return 1;
4642 break;
4643
4644 case IA64_OPND_IMMU62:
4645 if (e->X_op == O_constant)
4646 {
4647 if ((bfd_vma) e->X_add_number < ((bfd_vma) 1 << 62))
4648 return 1;
4649 }
4650 else
4651 {
4652 /* FIXME -- need 62-bit relocation type */
4653 as_bad (_("62-bit relocation not yet implemented"));
4654 }
4655 break;
4656
4657 case IA64_OPND_IMMU64:
4658 if (e->X_op == O_symbol || e->X_op == O_pseudo_fixup
4659 || e->X_op == O_subtract)
4660 {
4661 fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups;
4662 fix->code = BFD_RELOC_IA64_IMM64;
4663 if (e->X_op != O_subtract)
4664 {
4665 fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code);
4666 if (e->X_op == O_pseudo_fixup)
4667 e->X_op = O_symbol;
4668 }
4669
4670 fix->opnd = idesc->operands[index];
4671 fix->expr = *e;
4672 fix->is_pcrel = 0;
4673 ++CURR_SLOT.num_fixups;
4674 return 1;
4675 }
4676 else if (e->X_op == O_constant)
4677 return 1;
4678 break;
4679
4680 case IA64_OPND_CCNT5:
4681 case IA64_OPND_CNT5:
4682 case IA64_OPND_CNT6:
4683 case IA64_OPND_CPOS6a:
4684 case IA64_OPND_CPOS6b:
4685 case IA64_OPND_CPOS6c:
4686 case IA64_OPND_IMMU2:
4687 case IA64_OPND_IMMU7a:
4688 case IA64_OPND_IMMU7b:
4689 case IA64_OPND_IMMU21:
4690 case IA64_OPND_IMMU24:
4691 case IA64_OPND_MBTYPE4:
4692 case IA64_OPND_MHTYPE8:
4693 case IA64_OPND_POS6:
4694 bits = operand_width (idesc->operands[index]);
4695 if (e->X_op == O_constant
4696 && (bfd_vma) e->X_add_number < ((bfd_vma) 1 << bits))
4697 return 1;
4698 break;
4699
4700 case IA64_OPND_IMMU9:
4701 bits = operand_width (idesc->operands[index]);
4702 if (e->X_op == O_constant
4703 && (bfd_vma) e->X_add_number < ((bfd_vma) 1 << bits))
4704 {
4705 int lobits = e->X_add_number & 0x3;
4706 if (((bfd_vma) e->X_add_number & 0x3C) != 0 && lobits == 0)
4707 e->X_add_number |= (bfd_vma)0x3;
4708 return 1;
4709 }
4710 break;
4711
4712 case IA64_OPND_IMM44:
4713 /* least 16 bits must be zero */
4714 if ((e->X_add_number & 0xffff) != 0)
4715 as_warn (_("lower 16 bits of mask ignored"));
4716
4717 if (e->X_op == O_constant
4718 && ((e->X_add_number >= 0
4719 && e->X_add_number < ((bfd_vma) 1 << 44))
4720 || (e->X_add_number < 0
4721 && -e->X_add_number <= ((bfd_vma) 1 << 44))))
4722 {
4723 /* sign-extend */
4724 if (e->X_add_number >= 0
4725 && (e->X_add_number & ((bfd_vma) 1 << 43)) != 0)
4726 {
4727 e->X_add_number |= ~(((bfd_vma) 1 << 44) - 1);
4728 }
4729 return 1;
4730 }
4731 break;
4732
4733 case IA64_OPND_IMM17:
4734 /* bit 0 is a don't care (pr0 is hardwired to 1) */
4735 if (e->X_op == O_constant
4736 && ((e->X_add_number >= 0
4737 && e->X_add_number < ((bfd_vma) 1 << 17))
4738 || (e->X_add_number < 0
4739 && -e->X_add_number <= ((bfd_vma) 1 << 17))))
4740 {
4741 /* sign-extend */
4742 if (e->X_add_number >= 0
4743 && (e->X_add_number & ((bfd_vma) 1 << 16)) != 0)
4744 {
4745 e->X_add_number |= ~(((bfd_vma)1 << 17) - 1);
4746 }
4747 return 1;
4748 }
4749 break;
4750
4751 case IA64_OPND_IMM14:
4752 case IA64_OPND_IMM22:
4753 relocatable = 1;
4754 case IA64_OPND_IMM1:
4755 case IA64_OPND_IMM8:
4756 case IA64_OPND_IMM8U4:
4757 case IA64_OPND_IMM8M1:
4758 case IA64_OPND_IMM8M1U4:
4759 case IA64_OPND_IMM8M1U8:
4760 case IA64_OPND_IMM9a:
4761 case IA64_OPND_IMM9b:
4762 bits = operand_width (idesc->operands[index]);
4763 if (relocatable && (e->X_op == O_symbol
4764 || e->X_op == O_subtract
4765 || e->X_op == O_pseudo_fixup))
4766 {
4767 fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups;
4768
4769 if (idesc->operands[index] == IA64_OPND_IMM14)
4770 fix->code = BFD_RELOC_IA64_IMM14;
4771 else
4772 fix->code = BFD_RELOC_IA64_IMM22;
4773
4774 if (e->X_op != O_subtract)
4775 {
4776 fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code);
4777 if (e->X_op == O_pseudo_fixup)
4778 e->X_op = O_symbol;
4779 }
4780
4781 fix->opnd = idesc->operands[index];
4782 fix->expr = *e;
4783 fix->is_pcrel = 0;
4784 ++CURR_SLOT.num_fixups;
4785 return 1;
4786 }
4787 else if (e->X_op != O_constant
4788 && ! (e->X_op == O_big && opnd == IA64_OPND_IMM8M1U8))
4789 return 0;
4790
4791 if (opnd == IA64_OPND_IMM8M1U4)
4792 {
4793 /* Zero is not valid for unsigned compares that take an adjusted
4794 constant immediate range. */
4795 if (e->X_add_number == 0)
4796 return 0;
4797
4798 /* Sign-extend 32-bit unsigned numbers, so that the following range
4799 checks will work. */
4800 val = e->X_add_number;
4801 if (((val & (~(bfd_vma)0 << 32)) == 0)
4802 && ((val & ((bfd_vma)1 << 31)) != 0))
4803 val = ((val << 32) >> 32);
4804
4805 /* Check for 0x100000000. This is valid because
4806 0x100000000-1 is the same as ((uint32_t) -1). */
4807 if (val == ((bfd_signed_vma) 1 << 32))
4808 return 1;
4809
4810 val = val - 1;
4811 }
4812 else if (opnd == IA64_OPND_IMM8M1U8)
4813 {
4814 /* Zero is not valid for unsigned compares that take an adjusted
4815 constant immediate range. */
4816 if (e->X_add_number == 0)
4817 return 0;
4818
4819 /* Check for 0x10000000000000000. */
4820 if (e->X_op == O_big)
4821 {
4822 if (generic_bignum[0] == 0
4823 && generic_bignum[1] == 0
4824 && generic_bignum[2] == 0
4825 && generic_bignum[3] == 0
4826 && generic_bignum[4] == 1)
4827 return 1;
4828 else
4829 return 0;
4830 }
4831 else
4832 val = e->X_add_number - 1;
4833 }
4834 else if (opnd == IA64_OPND_IMM8M1)
4835 val = e->X_add_number - 1;
4836 else if (opnd == IA64_OPND_IMM8U4)
4837 {
4838 /* Sign-extend 32-bit unsigned numbers, so that the following range
4839 checks will work. */
4840 val = e->X_add_number;
4841 if (((val & (~(bfd_vma)0 << 32)) == 0)
4842 && ((val & ((bfd_vma)1 << 31)) != 0))
4843 val = ((val << 32) >> 32);
4844 }
4845 else
4846 val = e->X_add_number;
4847
4848 if ((val >= 0 && val < ((bfd_vma) 1 << (bits - 1)))
4849 || (val < 0 && -val <= ((bfd_vma) 1 << (bits - 1))))
4850 return 1;
4851 break;
4852
4853 case IA64_OPND_INC3:
4854 /* +/- 1, 4, 8, 16 */
4855 val = e->X_add_number;
4856 if (val < 0)
4857 val = -val;
4858 if (e->X_op == O_constant
4859 && (val == 1 || val == 4 || val == 8 || val == 16))
4860 return 1;
4861 break;
4862
4863 case IA64_OPND_TGT25:
4864 case IA64_OPND_TGT25b:
4865 case IA64_OPND_TGT25c:
4866 case IA64_OPND_TGT64:
4867 if (e->X_op == O_symbol)
4868 {
4869 fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups;
4870 if (opnd == IA64_OPND_TGT25)
4871 fix->code = BFD_RELOC_IA64_PCREL21F;
4872 else if (opnd == IA64_OPND_TGT25b)
4873 fix->code = BFD_RELOC_IA64_PCREL21M;
4874 else if (opnd == IA64_OPND_TGT25c)
4875 fix->code = BFD_RELOC_IA64_PCREL21B;
4876 else if (opnd == IA64_OPND_TGT64)
4877 fix->code = BFD_RELOC_IA64_PCREL60B;
4878 else
4879 abort ();
4880
4881 fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code);
4882 fix->opnd = idesc->operands[index];
4883 fix->expr = *e;
4884 fix->is_pcrel = 1;
4885 ++CURR_SLOT.num_fixups;
4886 return 1;
4887 }
4888 case IA64_OPND_TAG13:
4889 case IA64_OPND_TAG13b:
4890 switch (e->X_op)
4891 {
4892 case O_constant:
4893 return 1;
4894
4895 case O_symbol:
4896 fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups;
4897 fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, 0);
4898 fix->opnd = idesc->operands[index];
4899 fix->expr = *e;
4900 fix->is_pcrel = 1;
4901 ++CURR_SLOT.num_fixups;
4902 return 1;
4903
4904 default:
4905 break;
4906 }
4907 break;
4908
4909 default:
4910 break;
4911 }
4912 return 0;
4913 }
4914
4915 static int
4916 parse_operand (e)
4917 expressionS *e;
4918 {
4919 int sep = '\0';
4920
4921 memset (e, 0, sizeof (*e));
4922 e->X_op = O_absent;
4923 SKIP_WHITESPACE ();
4924 if (*input_line_pointer != '}')
4925 expression (e);
4926 sep = *input_line_pointer++;
4927
4928 if (sep == '}')
4929 {
4930 if (!md.manual_bundling)
4931 as_warn ("Found '}' when manual bundling is off");
4932 else
4933 CURR_SLOT.manual_bundling_off = 1;
4934 md.manual_bundling = 0;
4935 sep = '\0';
4936 }
4937 return sep;
4938 }
4939
4940 /* Returns the next entry in the opcode table that matches the one in
4941 IDESC, and frees the entry in IDESC. If no matching entry is
4942 found, NULL is returned instead. */
4943
4944 static struct ia64_opcode *
4945 get_next_opcode (struct ia64_opcode *idesc)
4946 {
4947 struct ia64_opcode *next = ia64_find_next_opcode (idesc);
4948 ia64_free_opcode (idesc);
4949 return next;
4950 }
4951
4952 /* Parse the operands for the opcode and find the opcode variant that
4953 matches the specified operands, or NULL if no match is possible. */
4954 static struct ia64_opcode*
4955 parse_operands (idesc)
4956 struct ia64_opcode *idesc;
4957 {
4958 int i = 0, highest_unmatched_operand, num_operands = 0, num_outputs = 0;
4959 int sep = 0;
4960 enum ia64_opnd expected_operand = IA64_OPND_NIL;
4961 char mnemonic[129];
4962 char *first_arg = 0, *end, *saved_input_pointer;
4963 unsigned int sof;
4964
4965 assert (strlen (idesc->name) <= 128);
4966
4967 strcpy (mnemonic, idesc->name);
4968 if (idesc->operands[2] == IA64_OPND_SOF)
4969 {
4970 /* To make the common idiom "alloc loc?=ar.pfs,0,1,0,0" work, we
4971 can't parse the first operand until we have parsed the
4972 remaining operands of the "alloc" instruction. */
4973 SKIP_WHITESPACE ();
4974 first_arg = input_line_pointer;
4975 end = strchr (input_line_pointer, '=');
4976 if (!end)
4977 {
4978 as_bad ("Expected separator `='");
4979 return 0;
4980 }
4981 input_line_pointer = end + 1;
4982 ++i;
4983 ++num_outputs;
4984 }
4985
4986 for (; i < NELEMS (CURR_SLOT.opnd); ++i)
4987 {
4988 sep = parse_operand (CURR_SLOT.opnd + i);
4989 if (CURR_SLOT.opnd[i].X_op == O_absent)
4990 break;
4991
4992 ++num_operands;
4993
4994 if (sep != '=' && sep != ',')
4995 break;
4996
4997 if (sep == '=')
4998 {
4999 if (num_outputs > 0)
5000 as_bad ("Duplicate equal sign (=) in instruction");
5001 else
5002 num_outputs = i + 1;
5003 }
5004 }
5005 if (sep != '\0')
5006 {
5007 as_bad ("Illegal operand separator `%c'", sep);
5008 return 0;
5009 }
5010
5011 if (idesc->operands[2] == IA64_OPND_SOF)
5012 {
5013 /* map alloc r1=ar.pfs,i,l,o,r to alloc r1=ar.pfs,(i+l+o),(i+l),r */
5014 know (strcmp (idesc->name, "alloc") == 0);
5015 if (num_operands == 5 /* first_arg not included in this count! */
5016 && CURR_SLOT.opnd[2].X_op == O_constant
5017 && CURR_SLOT.opnd[3].X_op == O_constant
5018 && CURR_SLOT.opnd[4].X_op == O_constant
5019 && CURR_SLOT.opnd[5].X_op == O_constant)
5020 {
5021 sof = set_regstack (CURR_SLOT.opnd[2].X_add_number,
5022 CURR_SLOT.opnd[3].X_add_number,
5023 CURR_SLOT.opnd[4].X_add_number,
5024 CURR_SLOT.opnd[5].X_add_number);
5025
5026 /* now we can parse the first arg: */
5027 saved_input_pointer = input_line_pointer;
5028 input_line_pointer = first_arg;
5029 sep = parse_operand (CURR_SLOT.opnd + 0);
5030 if (sep != '=')
5031 --num_outputs; /* force error */
5032 input_line_pointer = saved_input_pointer;
5033
5034 CURR_SLOT.opnd[2].X_add_number = sof;
5035 CURR_SLOT.opnd[3].X_add_number
5036 = sof - CURR_SLOT.opnd[4].X_add_number;
5037 CURR_SLOT.opnd[4] = CURR_SLOT.opnd[5];
5038 }
5039 }
5040
5041 highest_unmatched_operand = 0;
5042 expected_operand = idesc->operands[0];
5043 for (; idesc; idesc = get_next_opcode (idesc))
5044 {
5045 if (num_outputs != idesc->num_outputs)
5046 continue; /* mismatch in # of outputs */
5047
5048 CURR_SLOT.num_fixups = 0;
5049 for (i = 0; i < num_operands && idesc->operands[i]; ++i)
5050 if (!operand_match (idesc, i, CURR_SLOT.opnd + i))
5051 break;
5052
5053 if (i != num_operands)
5054 {
5055 if (i > highest_unmatched_operand)
5056 {
5057 highest_unmatched_operand = i;
5058 expected_operand = idesc->operands[i];
5059 }
5060 continue;
5061 }
5062
5063 if (num_operands < NELEMS (idesc->operands)
5064 && idesc->operands[num_operands])
5065 continue; /* mismatch in number of arguments */
5066
5067 break;
5068 }
5069 if (!idesc)
5070 {
5071 if (expected_operand)
5072 as_bad ("Operand %u of `%s' should be %s",
5073 highest_unmatched_operand + 1, mnemonic,
5074 elf64_ia64_operands[expected_operand].desc);
5075 else
5076 as_bad ("Operand mismatch");
5077 return 0;
5078 }
5079 return idesc;
5080 }
5081
5082 static void
5083 build_insn (slot, insnp)
5084 struct slot *slot;
5085 bfd_vma *insnp;
5086 {
5087 const struct ia64_operand *odesc, *o2desc;
5088 struct ia64_opcode *idesc = slot->idesc;
5089 bfd_signed_vma insn, val;
5090 const char *err;
5091 int i;
5092
5093 insn = idesc->opcode | slot->qp_regno;
5094
5095 for (i = 0; i < NELEMS (idesc->operands) && idesc->operands[i]; ++i)
5096 {
5097 if (slot->opnd[i].X_op == O_register
5098 || slot->opnd[i].X_op == O_constant
5099 || slot->opnd[i].X_op == O_index)
5100 val = slot->opnd[i].X_add_number;
5101 else if (slot->opnd[i].X_op == O_big)
5102 {
5103 /* This must be the value 0x10000000000000000. */
5104 assert (idesc->operands[i] == IA64_OPND_IMM8M1U8);
5105 val = 0;
5106 }
5107 else
5108 val = 0;
5109
5110 switch (idesc->operands[i])
5111 {
5112 case IA64_OPND_IMMU64:
5113 *insnp++ = (val >> 22) & 0x1ffffffffffLL;
5114 insn |= (((val & 0x7f) << 13) | (((val >> 7) & 0x1ff) << 27)
5115 | (((val >> 16) & 0x1f) << 22) | (((val >> 21) & 0x1) << 21)
5116 | (((val >> 63) & 0x1) << 36));
5117 continue;
5118
5119 case IA64_OPND_IMMU62:
5120 val &= 0x3fffffffffffffffULL;
5121 if (val != slot->opnd[i].X_add_number)
5122 as_warn (_("Value truncated to 62 bits"));
5123 *insnp++ = (val >> 21) & 0x1ffffffffffLL;
5124 insn |= (((val & 0xfffff) << 6) | (((val >> 20) & 0x1) << 36));
5125 continue;
5126
5127 case IA64_OPND_TGT64:
5128 val >>= 4;
5129 *insnp++ = ((val >> 20) & 0x7fffffffffLL) << 2;
5130 insn |= ((((val >> 59) & 0x1) << 36)
5131 | (((val >> 0) & 0xfffff) << 13));
5132 continue;
5133
5134 case IA64_OPND_AR3:
5135 val -= REG_AR;
5136 break;
5137
5138 case IA64_OPND_B1:
5139 case IA64_OPND_B2:
5140 val -= REG_BR;
5141 break;
5142
5143 case IA64_OPND_CR3:
5144 val -= REG_CR;
5145 break;
5146
5147 case IA64_OPND_F1:
5148 case IA64_OPND_F2:
5149 case IA64_OPND_F3:
5150 case IA64_OPND_F4:
5151 val -= REG_FR;
5152 break;
5153
5154 case IA64_OPND_P1:
5155 case IA64_OPND_P2:
5156 val -= REG_P;
5157 break;
5158
5159 case IA64_OPND_R1:
5160 case IA64_OPND_R2:
5161 case IA64_OPND_R3:
5162 case IA64_OPND_R3_2:
5163 case IA64_OPND_CPUID_R3:
5164 case IA64_OPND_DBR_R3:
5165 case IA64_OPND_DTR_R3:
5166 case IA64_OPND_ITR_R3:
5167 case IA64_OPND_IBR_R3:
5168 case IA64_OPND_MR3:
5169 case IA64_OPND_MSR_R3:
5170 case IA64_OPND_PKR_R3:
5171 case IA64_OPND_PMC_R3:
5172 case IA64_OPND_PMD_R3:
5173 case IA64_OPND_RR_R3:
5174 val -= REG_GR;
5175 break;
5176
5177 default:
5178 break;
5179 }
5180
5181 odesc = elf64_ia64_operands + idesc->operands[i];
5182 err = (*odesc->insert) (odesc, val, &insn);
5183 if (err)
5184 as_bad_where (slot->src_file, slot->src_line,
5185 "Bad operand value: %s", err);
5186 if (idesc->flags & IA64_OPCODE_PSEUDO)
5187 {
5188 if ((idesc->flags & IA64_OPCODE_F2_EQ_F3)
5189 && odesc == elf64_ia64_operands + IA64_OPND_F3)
5190 {
5191 o2desc = elf64_ia64_operands + IA64_OPND_F2;
5192 (*o2desc->insert) (o2desc, val, &insn);
5193 }
5194 if ((idesc->flags & IA64_OPCODE_LEN_EQ_64MCNT)
5195 && (odesc == elf64_ia64_operands + IA64_OPND_CPOS6a
5196 || odesc == elf64_ia64_operands + IA64_OPND_POS6))
5197 {
5198 o2desc = elf64_ia64_operands + IA64_OPND_LEN6;
5199 (*o2desc->insert) (o2desc, 64 - val, &insn);
5200 }
5201 }
5202 }
5203 *insnp = insn;
5204 }
5205
5206 static void
5207 emit_one_bundle ()
5208 {
5209 unsigned int manual_bundling_on = 0, manual_bundling_off = 0;
5210 unsigned int manual_bundling = 0;
5211 enum ia64_unit required_unit, insn_unit = 0;
5212 enum ia64_insn_type type[3], insn_type;
5213 unsigned int template, orig_template;
5214 bfd_vma insn[3] = {-1, -1, -1};
5215 struct ia64_opcode *idesc;
5216 int end_of_insn_group = 0, user_template = -1;
5217 int n, i, j, first, curr;
5218 unw_rec_list *ptr, *prev;
5219 bfd_vma t0 = 0, t1 = 0;
5220 struct label_fix *lfix;
5221 struct insn_fix *ifix;
5222 char mnemonic[16];
5223 fixS *fix;
5224 char *f;
5225
5226 first = (md.curr_slot + NUM_SLOTS - md.num_slots_in_use) % NUM_SLOTS;
5227 know (first >= 0 & first < NUM_SLOTS);
5228 n = MIN (3, md.num_slots_in_use);
5229
5230 /* Determine template: user user_template if specified, best match
5231 otherwise: */
5232
5233 if (md.slot[first].user_template >= 0)
5234 user_template = template = md.slot[first].user_template;
5235 else
5236 {
5237 /* auto select appropriate template */
5238 memset (type, 0, sizeof (type));
5239 curr = first;
5240 for (i = 0; i < n; ++i)
5241 {
5242 type[i] = md.slot[curr].idesc->type;
5243 curr = (curr + 1) % NUM_SLOTS;
5244 }
5245 template = best_template[type[0]][type[1]][type[2]];
5246 }
5247
5248 /* initialize instructions with appropriate nops: */
5249 for (i = 0; i < 3; ++i)
5250 insn[i] = nop[ia64_templ_desc[template].exec_unit[i]];
5251
5252 f = frag_more (16);
5253
5254 /* now fill in slots with as many insns as possible: */
5255 curr = first;
5256 idesc = md.slot[curr].idesc;
5257 end_of_insn_group = 0;
5258 for (i = 0; i < 3 && md.num_slots_in_use > 0; ++i)
5259 {
5260 /* Set the slot number for prologue/body records now as those
5261 refer to the current point, not the point after the
5262 instruction has been issued: */
5263 /* Don't try to delete prologue/body records here, as that will cause
5264 them to also be deleted from the master list of unwind records. */
5265 for (ptr = md.slot[curr].unwind_record; ptr; ptr = ptr->next)
5266 if (ptr->r.type == prologue || ptr->r.type == prologue_gr
5267 || ptr->r.type == body)
5268 ptr->slot_number = (unsigned long) f + i;
5269
5270 if (idesc->flags & IA64_OPCODE_SLOT2)
5271 {
5272 if (manual_bundling && i != 2)
5273 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
5274 "`%s' must be last in bundle", idesc->name);
5275 else
5276 i = 2;
5277 }
5278 if (idesc->flags & IA64_OPCODE_LAST)
5279 {
5280 int required_slot, required_template;
5281
5282 /* If we need a stop bit after an M slot, our only choice is
5283 template 5 (M;;MI). If we need a stop bit after a B
5284 slot, our only choice is to place it at the end of the
5285 bundle, because the only available templates are MIB,
5286 MBB, BBB, MMB, and MFB. We don't handle anything other
5287 than M and B slots because these are the only kind of
5288 instructions that can have the IA64_OPCODE_LAST bit set. */
5289 required_template = template;
5290 switch (idesc->type)
5291 {
5292 case IA64_TYPE_M:
5293 required_slot = 0;
5294 required_template = 5;
5295 break;
5296
5297 case IA64_TYPE_B:
5298 required_slot = 2;
5299 break;
5300
5301 default:
5302 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
5303 "Internal error: don't know how to force %s to end"
5304 "of instruction group", idesc->name);
5305 required_slot = i;
5306 break;
5307 }
5308 if (manual_bundling && i != required_slot)
5309 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
5310 "`%s' must be last in instruction group",
5311 idesc->name);
5312 if (required_slot < i)
5313 /* Can't fit this instruction. */
5314 break;
5315
5316 i = required_slot;
5317 if (required_template != template)
5318 {
5319 /* If we switch the template, we need to reset the NOPs
5320 after slot i. The slot-types of the instructions ahead
5321 of i never change, so we don't need to worry about
5322 changing NOPs in front of this slot. */
5323 for (j = i; j < 3; ++j)
5324 insn[j] = nop[ia64_templ_desc[required_template].exec_unit[j]];
5325 }
5326 template = required_template;
5327 }
5328 if (curr != first && md.slot[curr].label_fixups)
5329 {
5330 if (manual_bundling_on)
5331 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
5332 "Label must be first in a bundle");
5333 /* This insn must go into the first slot of a bundle. */
5334 break;
5335 }
5336
5337 manual_bundling_on = md.slot[curr].manual_bundling_on;
5338 manual_bundling_off = md.slot[curr].manual_bundling_off;
5339
5340 if (manual_bundling_on)
5341 {
5342 if (curr == first)
5343 manual_bundling = 1;
5344 else
5345 break; /* need to start a new bundle */
5346 }
5347
5348 if (end_of_insn_group && md.num_slots_in_use >= 1)
5349 {
5350 /* We need an instruction group boundary in the middle of a
5351 bundle. See if we can switch to an other template with
5352 an appropriate boundary. */
5353
5354 orig_template = template;
5355 if (i == 1 && (user_template == 4
5356 || (user_template < 0
5357 && (ia64_templ_desc[template].exec_unit[0]
5358 == IA64_UNIT_M))))
5359 {
5360 template = 5;
5361 end_of_insn_group = 0;
5362 }
5363 else if (i == 2 && (user_template == 0
5364 || (user_template < 0
5365 && (ia64_templ_desc[template].exec_unit[1]
5366 == IA64_UNIT_I)))
5367 /* This test makes sure we don't switch the template if
5368 the next instruction is one that needs to be first in
5369 an instruction group. Since all those instructions are
5370 in the M group, there is no way such an instruction can
5371 fit in this bundle even if we switch the template. The
5372 reason we have to check for this is that otherwise we
5373 may end up generating "MI;;I M.." which has the deadly
5374 effect that the second M instruction is no longer the
5375 first in the bundle! --davidm 99/12/16 */
5376 && (idesc->flags & IA64_OPCODE_FIRST) == 0)
5377 {
5378 template = 1;
5379 end_of_insn_group = 0;
5380 }
5381 else if (curr != first)
5382 /* can't fit this insn */
5383 break;
5384
5385 if (template != orig_template)
5386 /* if we switch the template, we need to reset the NOPs
5387 after slot i. The slot-types of the instructions ahead
5388 of i never change, so we don't need to worry about
5389 changing NOPs in front of this slot. */
5390 for (j = i; j < 3; ++j)
5391 insn[j] = nop[ia64_templ_desc[template].exec_unit[j]];
5392 }
5393 required_unit = ia64_templ_desc[template].exec_unit[i];
5394
5395 /* resolve dynamic opcodes such as "break" and "nop": */
5396 if (idesc->type == IA64_TYPE_DYN)
5397 {
5398 if ((strcmp (idesc->name, "nop") == 0)
5399 || (strcmp (idesc->name, "break") == 0))
5400 insn_unit = required_unit;
5401 else if (strcmp (idesc->name, "chk.s") == 0)
5402 {
5403 insn_unit = IA64_UNIT_M;
5404 if (required_unit == IA64_UNIT_I)
5405 insn_unit = IA64_UNIT_I;
5406 }
5407 else
5408 as_fatal ("emit_one_bundle: unexpected dynamic op");
5409
5410 sprintf (mnemonic, "%s.%c", idesc->name, "?imbf??"[insn_unit]);
5411 ia64_free_opcode (idesc);
5412 md.slot[curr].idesc = idesc = ia64_find_opcode (mnemonic);
5413 #if 0
5414 know (!idesc->next); /* no resolved dynamic ops have collisions */
5415 #endif
5416 }
5417 else
5418 {
5419 insn_type = idesc->type;
5420 insn_unit = IA64_UNIT_NIL;
5421 switch (insn_type)
5422 {
5423 case IA64_TYPE_A:
5424 if (required_unit == IA64_UNIT_I || required_unit == IA64_UNIT_M)
5425 insn_unit = required_unit;
5426 break;
5427 case IA64_TYPE_X: insn_unit = IA64_UNIT_L; break;
5428 case IA64_TYPE_I: insn_unit = IA64_UNIT_I; break;
5429 case IA64_TYPE_M: insn_unit = IA64_UNIT_M; break;
5430 case IA64_TYPE_B: insn_unit = IA64_UNIT_B; break;
5431 case IA64_TYPE_F: insn_unit = IA64_UNIT_F; break;
5432 default: break;
5433 }
5434 }
5435
5436 if (insn_unit != required_unit)
5437 {
5438 if (required_unit == IA64_UNIT_L
5439 && insn_unit == IA64_UNIT_I
5440 && !(idesc->flags & IA64_OPCODE_X_IN_MLX))
5441 {
5442 /* we got ourselves an MLX template but the current
5443 instruction isn't an X-unit, or an I-unit instruction
5444 that can go into the X slot of an MLX template. Duh. */
5445 if (md.num_slots_in_use >= NUM_SLOTS)
5446 {
5447 as_bad_where (md.slot[curr].src_file,
5448 md.slot[curr].src_line,
5449 "`%s' can't go in X slot of "
5450 "MLX template", idesc->name);
5451 /* drop this insn so we don't livelock: */
5452 --md.num_slots_in_use;
5453 }
5454 break;
5455 }
5456 continue; /* try next slot */
5457 }
5458
5459 if (debug_type == DEBUG_DWARF2)
5460 {
5461 bfd_vma addr;
5462
5463 addr = frag_now->fr_address + frag_now_fix () - 16 + 1*i;
5464 dwarf2_gen_line_info (addr, &md.slot[curr].debug_line);
5465 }
5466
5467 build_insn (md.slot + curr, insn + i);
5468
5469 /* Set slot counts for non prologue/body unwind records. */
5470 for (ptr = md.slot[curr].unwind_record; ptr; ptr = ptr->next)
5471 if (ptr->r.type != prologue && ptr->r.type != prologue_gr
5472 && ptr->r.type != body)
5473 ptr->slot_number = (unsigned long) f + i;
5474 md.slot[curr].unwind_record = NULL;
5475 unwind.next_slot_number = (unsigned long) f + i + ((i == 2)?(0x10-2):1);
5476
5477 if (required_unit == IA64_UNIT_L)
5478 {
5479 know (i == 1);
5480 /* skip one slot for long/X-unit instructions */
5481 ++i;
5482 }
5483 --md.num_slots_in_use;
5484
5485 /* now is a good time to fix up the labels for this insn: */
5486 for (lfix = md.slot[curr].label_fixups; lfix; lfix = lfix->next)
5487 {
5488 S_SET_VALUE (lfix->sym, frag_now_fix () - 16);
5489 symbol_set_frag (lfix->sym, frag_now);
5490 }
5491
5492 for (j = 0; j < md.slot[curr].num_fixups; ++j)
5493 {
5494 ifix = md.slot[curr].fixup + j;
5495 fix = fix_new_exp (frag_now, frag_now_fix () - 16 + i, 4,
5496 &ifix->expr, ifix->is_pcrel, ifix->code);
5497 fix->tc_fix_data.opnd = ifix->opnd;
5498 fix->fx_plt = (fix->fx_r_type == BFD_RELOC_IA64_PLTOFF22);
5499 fix->fx_file = md.slot[curr].src_file;
5500 fix->fx_line = md.slot[curr].src_line;
5501 }
5502
5503 end_of_insn_group = md.slot[curr].end_of_insn_group;
5504
5505 /* clear slot: */
5506 ia64_free_opcode (md.slot[curr].idesc);
5507 memset (md.slot + curr, 0, sizeof (md.slot[curr]));
5508 md.slot[curr].user_template = -1;
5509
5510 if (manual_bundling_off)
5511 {
5512 manual_bundling = 0;
5513 break;
5514 }
5515 curr = (curr + 1) % NUM_SLOTS;
5516 idesc = md.slot[curr].idesc;
5517 }
5518 if (manual_bundling)
5519 {
5520 if (md.num_slots_in_use > 0)
5521 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
5522 "`%s' does not fit into %s template",
5523 idesc->name, ia64_templ_desc[template].name);
5524 else
5525 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
5526 "Missing '}' at end of file");
5527 }
5528 know (md.num_slots_in_use < NUM_SLOTS);
5529
5530 t0 = end_of_insn_group | (template << 1) | (insn[0] << 5) | (insn[1] << 46);
5531 t1 = ((insn[1] >> 18) & 0x7fffff) | (insn[2] << 23);
5532
5533 md_number_to_chars (f + 0, t0, 8);
5534 md_number_to_chars (f + 8, t1, 8);
5535 }
5536
5537 int
5538 md_parse_option (c, arg)
5539 int c;
5540 char *arg;
5541 {
5542 switch (c)
5543 {
5544 /* Switches from the Intel assembler. */
5545 case 'M':
5546 if (strcmp (arg, "ilp64") == 0
5547 || strcmp (arg, "lp64") == 0
5548 || strcmp (arg, "p64") == 0)
5549 {
5550 md.flags |= EF_IA_64_ABI64;
5551 }
5552 else if (strcmp (arg, "ilp32") == 0)
5553 {
5554 md.flags &= ~EF_IA_64_ABI64;
5555 }
5556 else if (strcmp (arg, "le") == 0)
5557 {
5558 md.flags &= ~EF_IA_64_BE;
5559 }
5560 else if (strcmp (arg, "be") == 0)
5561 {
5562 md.flags |= EF_IA_64_BE;
5563 }
5564 else
5565 return 0;
5566 break;
5567
5568 case 'N':
5569 if (strcmp (arg, "so") == 0)
5570 {
5571 /* Suppress signon message. */
5572 }
5573 else if (strcmp (arg, "pi") == 0)
5574 {
5575 /* Reject privileged instructions. FIXME */
5576 }
5577 else if (strcmp (arg, "us") == 0)
5578 {
5579 /* Allow union of signed and unsigned range. FIXME */
5580 }
5581 else if (strcmp (arg, "close_fcalls") == 0)
5582 {
5583 /* Do not resolve global function calls. */
5584 }
5585 else
5586 return 0;
5587 break;
5588
5589 case 'C':
5590 /* temp[="prefix"] Insert temporary labels into the object file
5591 symbol table prefixed by "prefix".
5592 Default prefix is ":temp:".
5593 */
5594 break;
5595
5596 case 'a':
5597 /* ??? Conflicts with gas' listing option. */
5598 /* indirect=<tgt> Assume unannotated indirect branches behavior
5599 according to <tgt> --
5600 exit: branch out from the current context (default)
5601 labels: all labels in context may be branch targets
5602 */
5603 break;
5604
5605 case 'x':
5606 /* -X conflicts with an ignored option, use -x instead */
5607 md.detect_dv = 1;
5608 if (!arg || strcmp (arg, "explicit") == 0)
5609 {
5610 /* set default mode to explicit */
5611 md.default_explicit_mode = 1;
5612 break;
5613 }
5614 else if (strcmp (arg, "auto") == 0)
5615 {
5616 md.default_explicit_mode = 0;
5617 }
5618 else if (strcmp (arg, "debug") == 0)
5619 {
5620 md.debug_dv = 1;
5621 }
5622 else if (strcmp (arg, "debugx") == 0)
5623 {
5624 md.default_explicit_mode = 1;
5625 md.debug_dv = 1;
5626 }
5627 else
5628 {
5629 as_bad (_("Unrecognized option '-x%s'"), arg);
5630 }
5631 break;
5632
5633 case 'S':
5634 /* nops Print nops statistics. */
5635 break;
5636
5637 /* GNU specific switches for gcc. */
5638 case OPTION_MCONSTANT_GP:
5639 md.flags |= EF_IA_64_CONS_GP;
5640 break;
5641
5642 case OPTION_MAUTO_PIC:
5643 md.flags |= EF_IA_64_NOFUNCDESC_CONS_GP;
5644 break;
5645
5646 default:
5647 return 0;
5648 }
5649
5650 return 1;
5651 }
5652
5653 void
5654 md_show_usage (stream)
5655 FILE *stream;
5656 {
5657 fputs(_("\
5658 IA-64 options:\n\
5659 -Milp32|-Milp64|-Mlp64|-Mp64 select data model (default -Mlp64)\n\
5660 -Mle | -Mbe select little- or big-endian byte order (default -Mle)\n\
5661 -x | -xexplicit turn on dependency violation checking (default)\n\
5662 -xauto automagically remove dependency violations\n\
5663 -xdebug debug dependency violation checker\n"),
5664 stream);
5665 }
5666
5667 static inline int
5668 match (int templ, int type, int slot)
5669 {
5670 enum ia64_unit unit;
5671 int result;
5672
5673 unit = ia64_templ_desc[templ].exec_unit[slot];
5674 switch (type)
5675 {
5676 case IA64_TYPE_DYN: result = 1; break; /* for nop and break */
5677 case IA64_TYPE_A:
5678 result = (unit == IA64_UNIT_I || unit == IA64_UNIT_M);
5679 break;
5680 case IA64_TYPE_X: result = (unit == IA64_UNIT_L); break;
5681 case IA64_TYPE_I: result = (unit == IA64_UNIT_I); break;
5682 case IA64_TYPE_M: result = (unit == IA64_UNIT_M); break;
5683 case IA64_TYPE_B: result = (unit == IA64_UNIT_B); break;
5684 case IA64_TYPE_F: result = (unit == IA64_UNIT_F); break;
5685 default: result = 0; break;
5686 }
5687 return result;
5688 }
5689
5690 /* This function is called once, at assembler startup time. It sets
5691 up all the tables, etc. that the MD part of the assembler will need
5692 that can be determined before arguments are parsed. */
5693 void
5694 md_begin ()
5695 {
5696 int i, j, k, t, total, ar_base, cr_base, goodness, best, regnum;
5697 const char *err;
5698 char name[8];
5699
5700 md.auto_align = 1;
5701 md.explicit_mode = md.default_explicit_mode;
5702
5703 bfd_set_section_alignment (stdoutput, text_section, 4);
5704
5705 target_big_endian = 0;
5706 pseudo_func[FUNC_FPTR_RELATIVE].u.sym =
5707 symbol_new (".<fptr>", undefined_section, FUNC_FPTR_RELATIVE,
5708 &zero_address_frag);
5709
5710 pseudo_func[FUNC_GP_RELATIVE].u.sym =
5711 symbol_new (".<gprel>", undefined_section, FUNC_GP_RELATIVE,
5712 &zero_address_frag);
5713
5714 pseudo_func[FUNC_LT_RELATIVE].u.sym =
5715 symbol_new (".<ltoff>", undefined_section, FUNC_LT_RELATIVE,
5716 &zero_address_frag);
5717
5718 pseudo_func[FUNC_PC_RELATIVE].u.sym =
5719 symbol_new (".<pcrel>", undefined_section, FUNC_PC_RELATIVE,
5720 &zero_address_frag);
5721
5722 pseudo_func[FUNC_PLT_RELATIVE].u.sym =
5723 symbol_new (".<pltoff>", undefined_section, FUNC_PLT_RELATIVE,
5724 &zero_address_frag);
5725
5726 pseudo_func[FUNC_SEC_RELATIVE].u.sym =
5727 symbol_new (".<secrel>", undefined_section, FUNC_SEC_RELATIVE,
5728 &zero_address_frag);
5729
5730 pseudo_func[FUNC_SEG_RELATIVE].u.sym =
5731 symbol_new (".<segrel>", undefined_section, FUNC_SEG_RELATIVE,
5732 &zero_address_frag);
5733
5734 pseudo_func[FUNC_LTV_RELATIVE].u.sym =
5735 symbol_new (".<ltv>", undefined_section, FUNC_LTV_RELATIVE,
5736 &zero_address_frag);
5737
5738 pseudo_func[FUNC_LT_FPTR_RELATIVE].u.sym =
5739 symbol_new (".<ltoff.fptr>", undefined_section, FUNC_LT_FPTR_RELATIVE,
5740 &zero_address_frag);
5741
5742 /* compute the table of best templates: */
5743 for (i = 0; i < IA64_NUM_TYPES; ++i)
5744 for (j = 0; j < IA64_NUM_TYPES; ++j)
5745 for (k = 0; k < IA64_NUM_TYPES; ++k)
5746 {
5747 best = 0;
5748 for (t = 0; t < NELEMS (ia64_templ_desc); ++t)
5749 {
5750 goodness = 0;
5751 if (match (t, i, 0))
5752 {
5753 if (match (t, j, 1))
5754 {
5755 if (match (t, k, 2))
5756 goodness = 3;
5757 else
5758 goodness = 2;
5759 }
5760 else if (match (t, j, 2))
5761 goodness = 2;
5762 else
5763 goodness = 1;
5764 }
5765 else if (match (t, i, 1))
5766 {
5767 if (match (t, j, 2))
5768 goodness = 2;
5769 else
5770 goodness = 1;
5771 }
5772 else if (match (t, i, 2))
5773 goodness = 1;
5774
5775 if (goodness > best)
5776 {
5777 best = goodness;
5778 best_template[i][j][k] = t;
5779 }
5780 }
5781 }
5782
5783 for (i = 0; i < NUM_SLOTS; ++i)
5784 md.slot[i].user_template = -1;
5785
5786 md.pseudo_hash = hash_new ();
5787 for (i = 0; i < NELEMS (pseudo_opcode); ++i)
5788 {
5789 err = hash_insert (md.pseudo_hash, pseudo_opcode[i].name,
5790 (void *) (pseudo_opcode + i));
5791 if (err)
5792 as_fatal ("ia64.md_begin: can't hash `%s': %s",
5793 pseudo_opcode[i].name, err);
5794 }
5795
5796 md.reg_hash = hash_new ();
5797 md.dynreg_hash = hash_new ();
5798 md.const_hash = hash_new ();
5799 md.entry_hash = hash_new ();
5800
5801 /* general registers: */
5802
5803 total = 128;
5804 for (i = 0; i < total; ++i)
5805 {
5806 sprintf (name, "r%d", i - REG_GR);
5807 md.regsym[i] = declare_register (name, i);
5808 }
5809
5810 /* floating point registers: */
5811 total += 128;
5812 for (; i < total; ++i)
5813 {
5814 sprintf (name, "f%d", i - REG_FR);
5815 md.regsym[i] = declare_register (name, i);
5816 }
5817
5818 /* application registers: */
5819 total += 128;
5820 ar_base = i;
5821 for (; i < total; ++i)
5822 {
5823 sprintf (name, "ar%d", i - REG_AR);
5824 md.regsym[i] = declare_register (name, i);
5825 }
5826
5827 /* control registers: */
5828 total += 128;
5829 cr_base = i;
5830 for (; i < total; ++i)
5831 {
5832 sprintf (name, "cr%d", i - REG_CR);
5833 md.regsym[i] = declare_register (name, i);
5834 }
5835
5836 /* predicate registers: */
5837 total += 64;
5838 for (; i < total; ++i)
5839 {
5840 sprintf (name, "p%d", i - REG_P);
5841 md.regsym[i] = declare_register (name, i);
5842 }
5843
5844 /* branch registers: */
5845 total += 8;
5846 for (; i < total; ++i)
5847 {
5848 sprintf (name, "b%d", i - REG_BR);
5849 md.regsym[i] = declare_register (name, i);
5850 }
5851
5852 md.regsym[REG_IP] = declare_register ("ip", REG_IP);
5853 md.regsym[REG_CFM] = declare_register ("cfm", REG_CFM);
5854 md.regsym[REG_PR] = declare_register ("pr", REG_PR);
5855 md.regsym[REG_PR_ROT] = declare_register ("pr.rot", REG_PR_ROT);
5856 md.regsym[REG_PSR] = declare_register ("psr", REG_PSR);
5857 md.regsym[REG_PSR_L] = declare_register ("psr.l", REG_PSR_L);
5858 md.regsym[REG_PSR_UM] = declare_register ("psr.um", REG_PSR_UM);
5859
5860 for (i = 0; i < NELEMS (indirect_reg); ++i)
5861 {
5862 regnum = indirect_reg[i].regnum;
5863 md.regsym[regnum] = declare_register (indirect_reg[i].name, regnum);
5864 }
5865
5866 /* define synonyms for application registers: */
5867 for (i = REG_AR; i < REG_AR + NELEMS (ar); ++i)
5868 md.regsym[i] = declare_register (ar[i - REG_AR].name,
5869 REG_AR + ar[i - REG_AR].regnum);
5870
5871 /* define synonyms for control registers: */
5872 for (i = REG_CR; i < REG_CR + NELEMS (cr); ++i)
5873 md.regsym[i] = declare_register (cr[i - REG_CR].name,
5874 REG_CR + cr[i - REG_CR].regnum);
5875
5876 declare_register ("gp", REG_GR + 1);
5877 declare_register ("sp", REG_GR + 12);
5878 declare_register ("rp", REG_BR + 0);
5879
5880 /* pseudo-registers used to specify unwind info: */
5881 declare_register ("psp", REG_PSP);
5882
5883 declare_register_set ("ret", 4, REG_GR + 8);
5884 declare_register_set ("farg", 8, REG_FR + 8);
5885 declare_register_set ("fret", 8, REG_FR + 8);
5886
5887 for (i = 0; i < NELEMS (const_bits); ++i)
5888 {
5889 err = hash_insert (md.const_hash, const_bits[i].name,
5890 (PTR) (const_bits + i));
5891 if (err)
5892 as_fatal ("Inserting \"%s\" into constant hash table failed: %s",
5893 name, err);
5894 }
5895
5896 /* Default to 64-bit mode. */
5897 /* ??? This overrides the -M options, but they aren't working anyways. */
5898 md.flags |= EF_IA_64_ABI64;
5899
5900 md.mem_offset.hint = 0;
5901 md.path = 0;
5902 md.maxpaths = 0;
5903 md.entry_labels = NULL;
5904 }
5905
5906 void
5907 ia64_end_of_source ()
5908 {
5909 /* terminate insn group upon reaching end of file: */
5910 insn_group_break (1, 0, 0);
5911
5912 /* emits slots we haven't written yet: */
5913 ia64_flush_insns ();
5914
5915 bfd_set_private_flags (stdoutput, md.flags);
5916
5917 if (debug_type == DEBUG_DWARF2)
5918 dwarf2_finish ();
5919
5920 md.mem_offset.hint = 0;
5921 }
5922
5923 void
5924 ia64_start_line ()
5925 {
5926 md.qp.X_op = O_absent;
5927
5928 if (ignore_input ())
5929 return;
5930
5931 if (input_line_pointer[0] == ';' && input_line_pointer[-1] == ';')
5932 {
5933 if (md.detect_dv && !md.explicit_mode)
5934 as_warn (_("Explicit stops are ignored in auto mode"));
5935 else
5936 insn_group_break (1, 0, 0);
5937 }
5938 }
5939
5940 int
5941 ia64_unrecognized_line (ch)
5942 int ch;
5943 {
5944 switch (ch)
5945 {
5946 case '(':
5947 expression (&md.qp);
5948 if (*input_line_pointer++ != ')')
5949 {
5950 as_bad ("Expected ')'");
5951 return 0;
5952 }
5953 if (md.qp.X_op != O_register)
5954 {
5955 as_bad ("Qualifying predicate expected");
5956 return 0;
5957 }
5958 if (md.qp.X_add_number < REG_P || md.qp.X_add_number >= REG_P + 64)
5959 {
5960 as_bad ("Predicate register expected");
5961 return 0;
5962 }
5963 return 1;
5964
5965 case '{':
5966 if (md.manual_bundling)
5967 as_warn ("Found '{' when manual bundling is already turned on");
5968 else
5969 CURR_SLOT.manual_bundling_on = 1;
5970 md.manual_bundling = 1;
5971
5972 /* bundling is only acceptable in explicit mode
5973 or when in default automatic mode */
5974 if (md.detect_dv && !md.explicit_mode)
5975 {
5976 if (!md.mode_explicitly_set
5977 && !md.default_explicit_mode)
5978 dot_dv_mode ('E');
5979 else
5980 as_warn (_("Found '{' after explicit switch to automatic mode"));
5981 }
5982 return 1;
5983
5984 case '}':
5985 if (!md.manual_bundling)
5986 as_warn ("Found '}' when manual bundling is off");
5987 else
5988 PREV_SLOT.manual_bundling_off = 1;
5989 md.manual_bundling = 0;
5990
5991 /* switch back to automatic mode, if applicable */
5992 if (md.detect_dv
5993 && md.explicit_mode
5994 && !md.mode_explicitly_set
5995 && !md.default_explicit_mode)
5996 dot_dv_mode ('A');
5997
5998 /* Allow '{' to follow on the same line. We also allow ";;", but that
5999 happens automatically because ';' is an end of line marker. */
6000 SKIP_WHITESPACE ();
6001 if (input_line_pointer[0] == '{')
6002 {
6003 input_line_pointer++;
6004 return ia64_unrecognized_line ('{');
6005 }
6006
6007 demand_empty_rest_of_line ();
6008 return 1;
6009
6010 default:
6011 break;
6012 }
6013 return 0; /* not a valid line */
6014 }
6015
6016 void
6017 ia64_frob_label (sym)
6018 struct symbol *sym;
6019 {
6020 struct label_fix *fix;
6021
6022 if (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE)
6023 {
6024 md.last_text_seg = now_seg;
6025 fix = obstack_alloc (&notes, sizeof (*fix));
6026 fix->sym = sym;
6027 fix->next = CURR_SLOT.label_fixups;
6028 CURR_SLOT.label_fixups = fix;
6029
6030 /* keep track of how many code entry points we've seen */
6031 if (md.path == md.maxpaths)
6032 {
6033 md.maxpaths += 20;
6034 md.entry_labels = (const char **)
6035 xrealloc ((void *)md.entry_labels, md.maxpaths * sizeof (char *));
6036 }
6037 md.entry_labels[md.path++] = S_GET_NAME (sym);
6038 }
6039 }
6040
6041 void
6042 ia64_flush_pending_output ()
6043 {
6044 if (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE)
6045 {
6046 /* ??? This causes many unnecessary stop bits to be emitted.
6047 Unfortunately, it isn't clear if it is safe to remove this. */
6048 insn_group_break (1, 0, 0);
6049 ia64_flush_insns ();
6050 }
6051 }
6052
6053 /* Do ia64-specific expression optimization. All that's done here is
6054 to transform index expressions that are either due to the indexing
6055 of rotating registers or due to the indexing of indirect register
6056 sets. */
6057 int
6058 ia64_optimize_expr (l, op, r)
6059 expressionS *l;
6060 operatorT op;
6061 expressionS *r;
6062 {
6063 unsigned num_regs;
6064
6065 if (op == O_index)
6066 {
6067 if (l->X_op == O_register && r->X_op == O_constant)
6068 {
6069 num_regs = (l->X_add_number >> 16);
6070 if ((unsigned) r->X_add_number >= num_regs)
6071 {
6072 if (!num_regs)
6073 as_bad ("No current frame");
6074 else
6075 as_bad ("Index out of range 0..%u", num_regs - 1);
6076 r->X_add_number = 0;
6077 }
6078 l->X_add_number = (l->X_add_number & 0xffff) + r->X_add_number;
6079 return 1;
6080 }
6081 else if (l->X_op == O_register && r->X_op == O_register)
6082 {
6083 if (l->X_add_number < IND_CPUID || l->X_add_number > IND_RR
6084 || l->X_add_number == IND_MEM)
6085 {
6086 as_bad ("Indirect register set name expected");
6087 l->X_add_number = IND_CPUID;
6088 }
6089 l->X_op = O_index;
6090 l->X_op_symbol = md.regsym[l->X_add_number];
6091 l->X_add_number = r->X_add_number;
6092 return 1;
6093 }
6094 }
6095 return 0;
6096 }
6097
6098 int
6099 ia64_parse_name (name, e)
6100 char *name;
6101 expressionS *e;
6102 {
6103 struct const_desc *cdesc;
6104 struct dynreg *dr = 0;
6105 unsigned int regnum;
6106 struct symbol *sym;
6107 char *end;
6108
6109 /* first see if NAME is a known register name: */
6110 sym = hash_find (md.reg_hash, name);
6111 if (sym)
6112 {
6113 e->X_op = O_register;
6114 e->X_add_number = S_GET_VALUE (sym);
6115 return 1;
6116 }
6117
6118 cdesc = hash_find (md.const_hash, name);
6119 if (cdesc)
6120 {
6121 e->X_op = O_constant;
6122 e->X_add_number = cdesc->value;
6123 return 1;
6124 }
6125
6126 /* check for inN, locN, or outN: */
6127 switch (name[0])
6128 {
6129 case 'i':
6130 if (name[1] == 'n' && isdigit (name[2]))
6131 {
6132 dr = &md.in;
6133 name += 2;
6134 }
6135 break;
6136
6137 case 'l':
6138 if (name[1] == 'o' && name[2] == 'c' && isdigit (name[3]))
6139 {
6140 dr = &md.loc;
6141 name += 3;
6142 }
6143 break;
6144
6145 case 'o':
6146 if (name[1] == 'u' && name[2] == 't' && isdigit (name[3]))
6147 {
6148 dr = &md.out;
6149 name += 3;
6150 }
6151 break;
6152
6153 default:
6154 break;
6155 }
6156
6157 if (dr)
6158 {
6159 /* the name is inN, locN, or outN; parse the register number: */
6160 regnum = strtoul (name, &end, 10);
6161 if (end > name && *end == '\0')
6162 {
6163 if ((unsigned) regnum >= dr->num_regs)
6164 {
6165 if (!dr->num_regs)
6166 as_bad ("No current frame");
6167 else
6168 as_bad ("Register number out of range 0..%u", dr->num_regs-1);
6169 regnum = 0;
6170 }
6171 e->X_op = O_register;
6172 e->X_add_number = dr->base + regnum;
6173 return 1;
6174 }
6175 }
6176
6177 if ((dr = hash_find (md.dynreg_hash, name)))
6178 {
6179 /* We've got ourselves the name of a rotating register set.
6180 Store the base register number in the low 16 bits of
6181 X_add_number and the size of the register set in the top 16
6182 bits. */
6183 e->X_op = O_register;
6184 e->X_add_number = dr->base | (dr->num_regs << 16);
6185 return 1;
6186 }
6187 return 0;
6188 }
6189
6190 /* Remove the '#' suffix that indicates a symbol as opposed to a register. */
6191
6192 char *
6193 ia64_canonicalize_symbol_name (name)
6194 char *name;
6195 {
6196 size_t len = strlen(name);
6197 if (len > 1 && name[len-1] == '#')
6198 name[len-1] = '\0';
6199 return name;
6200 }
6201
6202 static int
6203 is_conditional_branch (idesc)
6204 struct ia64_opcode *idesc;
6205 {
6206 return (strncmp (idesc->name, "br", 2) == 0
6207 && (strcmp (idesc->name, "br") == 0
6208 || strncmp (idesc->name, "br.cond", 7) == 0
6209 || strncmp (idesc->name, "br.call", 7) == 0
6210 || strncmp (idesc->name, "br.ret", 6) == 0
6211 || strcmp (idesc->name, "brl") == 0
6212 || strncmp (idesc->name, "brl.cond", 7) == 0
6213 || strncmp (idesc->name, "brl.call", 7) == 0
6214 || strncmp (idesc->name, "brl.ret", 6) == 0));
6215 }
6216
6217 /* Return whether the given opcode is a taken branch. If there's any doubt,
6218 returns zero */
6219 static int
6220 is_taken_branch (idesc)
6221 struct ia64_opcode *idesc;
6222 {
6223 return ((is_conditional_branch (idesc) && CURR_SLOT.qp_regno == 0)
6224 || strncmp (idesc->name, "br.ia", 5) == 0);
6225 }
6226
6227 /* Return whether the given opcode is an interruption or rfi. If there's any
6228 doubt, returns zero */
6229 static int
6230 is_interruption_or_rfi (idesc)
6231 struct ia64_opcode *idesc;
6232 {
6233 if (strcmp (idesc->name, "rfi") == 0)
6234 return 1;
6235 return 0;
6236 }
6237
6238 /* Returns the index of the given dependency in the opcode's list of chks, or
6239 -1 if there is no dependency. */
6240 static int
6241 depends_on (depind, idesc)
6242 int depind;
6243 struct ia64_opcode *idesc;
6244 {
6245 int i;
6246 const struct ia64_opcode_dependency *dep = idesc->dependencies;
6247 for (i = 0;i < dep->nchks; i++)
6248 {
6249 if (depind == DEP(dep->chks[i]))
6250 return i;
6251 }
6252 return -1;
6253 }
6254
6255 /* Determine a set of specific resources used for a particular resource
6256 class. Returns the number of specific resources identified For those
6257 cases which are not determinable statically, the resource returned is
6258 marked nonspecific.
6259
6260 Meanings of value in 'NOTE':
6261 1) only read/write when the register number is explicitly encoded in the
6262 insn.
6263 2) only read CFM when accessing a rotating GR, FR, or PR. mov pr only
6264 accesses CFM when qualifying predicate is in the rotating region.
6265 3) general register value is used to specify an indirect register; not
6266 determinable statically.
6267 4) only read the given resource when bits 7:0 of the indirect index
6268 register value does not match the register number of the resource; not
6269 determinable statically.
6270 5) all rules are implementation specific.
6271 6) only when both the index specified by the reader and the index specified
6272 by the writer have the same value in bits 63:61; not determinable
6273 statically.
6274 7) only access the specified resource when the corresponding mask bit is
6275 set
6276 8) PSR.dfh is only read when these insns reference FR32-127. PSR.dfl is
6277 only read when these insns reference FR2-31
6278 9) PSR.mfl is only written when these insns write FR2-31. PSR.mfh is only
6279 written when these insns write FR32-127
6280 10) The PSR.bn bit is only accessed when one of GR16-31 is specified in the
6281 instruction
6282 11) The target predicates are written independently of PR[qp], but source
6283 registers are only read if PR[qp] is true. Since the state of PR[qp]
6284 cannot statically be determined, all source registers are marked used.
6285 12) This insn only reads the specified predicate register when that
6286 register is the PR[qp].
6287 13) This reference to ld-c only applies to teh GR whose value is loaded
6288 with data returned from memory, not the post-incremented address register.
6289 14) The RSE resource includes the implementation-specific RSE internal
6290 state resources. At least one (and possibly more) of these resources are
6291 read by each instruction listed in IC:rse-readers. At least one (and
6292 possibly more) of these resources are written by each insn listed in
6293 IC:rse-writers.
6294 15+16) Represents reserved instructions, which the assembler does not
6295 generate.
6296
6297 Memory resources (i.e. locations in memory) are *not* marked or tracked by
6298 this code; there are no dependency violations based on memory access.
6299
6300 */
6301
6302 #define MAX_SPECS 256
6303 #define DV_CHK 1
6304 #define DV_REG 0
6305
6306 static int
6307 specify_resource (dep, idesc, type, specs, note, path)
6308 const struct ia64_dependency *dep;
6309 struct ia64_opcode *idesc;
6310 int type; /* is this a DV chk or a DV reg? */
6311 struct rsrc specs[MAX_SPECS]; /* returned specific resources */
6312 int note; /* resource note for this insn's usage */
6313 int path; /* which execution path to examine */
6314 {
6315 int count = 0;
6316 int i;
6317 int rsrc_write = 0;
6318 struct rsrc tmpl;
6319
6320 if (dep->mode == IA64_DV_WAW
6321 || (dep->mode == IA64_DV_RAW && type == DV_REG)
6322 || (dep->mode == IA64_DV_WAR && type == DV_CHK))
6323 rsrc_write = 1;
6324
6325 /* template for any resources we identify */
6326 tmpl.dependency = dep;
6327 tmpl.note = note;
6328 tmpl.insn_srlz = tmpl.data_srlz = 0;
6329 tmpl.qp_regno = CURR_SLOT.qp_regno;
6330 tmpl.link_to_qp_branch = 1;
6331 tmpl.mem_offset.hint = 0;
6332 tmpl.specific = 1;
6333 tmpl.index = 0;
6334
6335 #define UNHANDLED \
6336 as_warn (_("Unhandled dependency %s for %s (%s), note %d"), \
6337 dep->name, idesc->name, (rsrc_write?"write":"read"), note)
6338 #define KNOWN(REG) (gr_values[REG].known && gr_values[REG].path >= path)
6339
6340 /* we don't need to track these */
6341 if (dep->semantics == IA64_DVS_NONE)
6342 return 0;
6343
6344 switch (dep->specifier)
6345 {
6346 case IA64_RS_AR_K:
6347 if (note == 1)
6348 {
6349 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3)
6350 {
6351 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
6352 if (regno >= 0 && regno <= 7)
6353 {
6354 specs[count] = tmpl;
6355 specs[count++].index = regno;
6356 }
6357 }
6358 }
6359 else if (note == 0)
6360 {
6361 for(i=0;i < 8;i++)
6362 {
6363 specs[count] = tmpl;
6364 specs[count++].index = i;
6365 }
6366 }
6367 else
6368 {
6369 UNHANDLED;
6370 }
6371 break;
6372
6373 case IA64_RS_AR_UNAT:
6374 /* This is a mov =AR or mov AR= instruction. */
6375 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3)
6376 {
6377 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
6378 if (regno == AR_UNAT)
6379 {
6380 specs[count++] = tmpl;
6381 }
6382 }
6383 else
6384 {
6385 /* This is a spill/fill, or other instruction that modifies the
6386 unat register. */
6387
6388 /* Unless we can determine the specific bits used, mark the whole
6389 thing; bits 8:3 of the memory address indicate the bit used in
6390 UNAT. The .mem.offset hint may be used to eliminate a small
6391 subset of conflicts. */
6392 specs[count] = tmpl;
6393 if (md.mem_offset.hint)
6394 {
6395 if (md.debug_dv)
6396 fprintf (stderr, " Using hint for spill/fill\n");
6397 /* the index isn't actually used, just set it to something
6398 approximating the bit index */
6399 specs[count].index = (md.mem_offset.offset >> 3) & 0x3F;
6400 specs[count].mem_offset.hint = 1;
6401 specs[count].mem_offset.offset = md.mem_offset.offset;
6402 specs[count++].mem_offset.base = md.mem_offset.base;
6403 }
6404 else
6405 {
6406 specs[count++].specific = 0;
6407 }
6408 }
6409 break;
6410
6411 case IA64_RS_AR:
6412 if (note == 1)
6413 {
6414 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3)
6415 {
6416 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
6417 if ((regno >= 8 && regno <= 15)
6418 || (regno >= 20 && regno <= 23)
6419 || (regno >= 31 && regno <= 39)
6420 || (regno >= 41 && regno <= 47)
6421 || (regno >= 67 && regno <= 111))
6422 {
6423 specs[count] = tmpl;
6424 specs[count++].index = regno;
6425 }
6426 }
6427 }
6428 else
6429 {
6430 UNHANDLED;
6431 }
6432 break;
6433
6434 case IA64_RS_ARb:
6435 if (note == 1)
6436 {
6437 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3)
6438 {
6439 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
6440 if ((regno >= 48 && regno <= 63)
6441 || (regno >= 112 && regno <= 127))
6442 {
6443 specs[count] = tmpl;
6444 specs[count++].index = regno;
6445 }
6446 }
6447 }
6448 else if (note == 0)
6449 {
6450 for (i=48;i < 64;i++)
6451 {
6452 specs[count] = tmpl;
6453 specs[count++].index = i;
6454 }
6455 for (i=112;i < 128;i++)
6456 {
6457 specs[count] = tmpl;
6458 specs[count++].index = i;
6459 }
6460 }
6461 else
6462 {
6463 UNHANDLED;
6464 }
6465 break;
6466
6467 case IA64_RS_BR:
6468 if (note != 1)
6469 {
6470 UNHANDLED;
6471 }
6472 else
6473 {
6474 if (rsrc_write)
6475 {
6476 for (i=0;i < idesc->num_outputs;i++)
6477 if (idesc->operands[i] == IA64_OPND_B1
6478 || idesc->operands[i] == IA64_OPND_B2)
6479 {
6480 specs[count] = tmpl;
6481 specs[count++].index =
6482 CURR_SLOT.opnd[i].X_add_number - REG_BR;
6483 }
6484 }
6485 else
6486 {
6487 for (i = idesc->num_outputs;i < NELEMS(idesc->operands);i++)
6488 if (idesc->operands[i] == IA64_OPND_B1
6489 || idesc->operands[i] == IA64_OPND_B2)
6490 {
6491 specs[count] = tmpl;
6492 specs[count++].index =
6493 CURR_SLOT.opnd[i].X_add_number - REG_BR;
6494 }
6495 }
6496 }
6497 break;
6498
6499 case IA64_RS_CPUID: /* four or more registers */
6500 if (note == 3)
6501 {
6502 if (idesc->operands[!rsrc_write] == IA64_OPND_CPUID_R3)
6503 {
6504 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
6505 if (regno >= 0 && regno < NELEMS(gr_values)
6506 && KNOWN(regno))
6507 {
6508 specs[count] = tmpl;
6509 specs[count++].index = gr_values[regno].value & 0xFF;
6510 }
6511 else
6512 {
6513 specs[count] = tmpl;
6514 specs[count++].specific = 0;
6515 }
6516 }
6517 }
6518 else
6519 {
6520 UNHANDLED;
6521 }
6522 break;
6523
6524 case IA64_RS_DBR: /* four or more registers */
6525 if (note == 3)
6526 {
6527 if (idesc->operands[!rsrc_write] == IA64_OPND_DBR_R3)
6528 {
6529 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
6530 if (regno >= 0 && regno < NELEMS(gr_values)
6531 && KNOWN(regno))
6532 {
6533 specs[count] = tmpl;
6534 specs[count++].index = gr_values[regno].value & 0xFF;
6535 }
6536 else
6537 {
6538 specs[count] = tmpl;
6539 specs[count++].specific = 0;
6540 }
6541 }
6542 }
6543 else if (note == 0 && !rsrc_write)
6544 {
6545 specs[count] = tmpl;
6546 specs[count++].specific = 0;
6547 }
6548 else
6549 {
6550 UNHANDLED;
6551 }
6552 break;
6553
6554 case IA64_RS_IBR: /* four or more registers */
6555 if (note == 3)
6556 {
6557 if (idesc->operands[!rsrc_write] == IA64_OPND_IBR_R3)
6558 {
6559 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
6560 if (regno >= 0 && regno < NELEMS(gr_values)
6561 && KNOWN(regno))
6562 {
6563 specs[count] = tmpl;
6564 specs[count++].index = gr_values[regno].value & 0xFF;
6565 }
6566 else
6567 {
6568 specs[count] = tmpl;
6569 specs[count++].specific = 0;
6570 }
6571 }
6572 }
6573 else
6574 {
6575 UNHANDLED;
6576 }
6577 break;
6578
6579 case IA64_RS_MSR:
6580 if (note == 5)
6581 {
6582 /* These are implementation specific. Force all references to
6583 conflict with all other references. */
6584 specs[count] = tmpl;
6585 specs[count++].specific = 0;
6586 }
6587 else
6588 {
6589 UNHANDLED;
6590 }
6591 break;
6592
6593 case IA64_RS_PKR: /* 16 or more registers */
6594 if (note == 3 || note == 4)
6595 {
6596 if (idesc->operands[!rsrc_write] == IA64_OPND_PKR_R3)
6597 {
6598 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
6599 if (regno >= 0 && regno < NELEMS(gr_values)
6600 && KNOWN(regno))
6601 {
6602 if (note == 3)
6603 {
6604 specs[count] = tmpl;
6605 specs[count++].index = gr_values[regno].value & 0xFF;
6606 }
6607 else for (i=0;i < NELEMS(gr_values);i++)
6608 {
6609 /* uses all registers *except* the one in R3 */
6610 if (i != (gr_values[regno].value & 0xFF))
6611 {
6612 specs[count] = tmpl;
6613 specs[count++].index = i;
6614 }
6615 }
6616 }
6617 else
6618 {
6619 specs[count] = tmpl;
6620 specs[count++].specific = 0;
6621 }
6622 }
6623 }
6624 else if (note == 0)
6625 {
6626 /* probe et al. */
6627 specs[count] = tmpl;
6628 specs[count++].specific = 0;
6629 }
6630 break;
6631
6632 case IA64_RS_PMC: /* four or more registers */
6633 if (note == 3)
6634 {
6635 if (idesc->operands[!rsrc_write] == IA64_OPND_PMC_R3
6636 || (!rsrc_write && idesc->operands[1] == IA64_OPND_PMD_R3))
6637
6638 {
6639 int index = ((idesc->operands[1] == IA64_OPND_R3 && !rsrc_write)
6640 ? 1 : !rsrc_write);
6641 int regno = CURR_SLOT.opnd[index].X_add_number - REG_GR;
6642 if (regno >= 0 && regno < NELEMS(gr_values)
6643 && KNOWN(regno))
6644 {
6645 specs[count] = tmpl;
6646 specs[count++].index = gr_values[regno].value & 0xFF;
6647 }
6648 else
6649 {
6650 specs[count] = tmpl;
6651 specs[count++].specific = 0;
6652 }
6653 }
6654 }
6655 else
6656 {
6657 UNHANDLED;
6658 }
6659 break;
6660
6661 case IA64_RS_PMD: /* four or more registers */
6662 if (note == 3)
6663 {
6664 if (idesc->operands[!rsrc_write] == IA64_OPND_PMD_R3)
6665 {
6666 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
6667 if (regno >= 0 && regno < NELEMS(gr_values)
6668 && KNOWN(regno))
6669 {
6670 specs[count] = tmpl;
6671 specs[count++].index = gr_values[regno].value & 0xFF;
6672 }
6673 else
6674 {
6675 specs[count] = tmpl;
6676 specs[count++].specific = 0;
6677 }
6678 }
6679 }
6680 else
6681 {
6682 UNHANDLED;
6683 }
6684 break;
6685
6686 case IA64_RS_RR: /* eight registers */
6687 if (note == 6)
6688 {
6689 if (idesc->operands[!rsrc_write] == IA64_OPND_RR_R3)
6690 {
6691 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
6692 if (regno >= 0 && regno < NELEMS(gr_values)
6693 && KNOWN(regno))
6694 {
6695 specs[count] = tmpl;
6696 specs[count++].index = (gr_values[regno].value >> 61) & 0x7;
6697 }
6698 else
6699 {
6700 specs[count] = tmpl;
6701 specs[count++].specific = 0;
6702 }
6703 }
6704 }
6705 else if (note == 0 && !rsrc_write)
6706 {
6707 specs[count] = tmpl;
6708 specs[count++].specific = 0;
6709 }
6710 else
6711 {
6712 UNHANDLED;
6713 }
6714 break;
6715
6716 case IA64_RS_CR_IRR:
6717 if (note == 0)
6718 {
6719 /* handle mov-from-CR-IVR; it's a read that writes CR[IRR] */
6720 int regno = CURR_SLOT.opnd[1].X_add_number - REG_CR;
6721 if (rsrc_write
6722 && idesc->operands[1] == IA64_OPND_CR3
6723 && regno == CR_IVR)
6724 {
6725 for(i=0;i < 4;i++)
6726 {
6727 specs[count] = tmpl;
6728 specs[count++].index = CR_IRR0 + i;
6729 }
6730 }
6731 }
6732 else if (note == 1)
6733 {
6734 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR;
6735 if (idesc->operands[!rsrc_write] == IA64_OPND_CR3
6736 && regno >= CR_IRR0
6737 && regno <= CR_IRR3)
6738 {
6739 specs[count] = tmpl;
6740 specs[count++].index = regno;
6741 }
6742 }
6743 else
6744 {
6745 UNHANDLED;
6746 }
6747 break;
6748
6749 case IA64_RS_CR_LRR:
6750 if (note != 1)
6751 {
6752 UNHANDLED;
6753 }
6754 else
6755 {
6756 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR;
6757 if (idesc->operands[!rsrc_write] == IA64_OPND_CR3
6758 && (regno == CR_LRR0 || regno == CR_LRR1))
6759 {
6760 specs[count] = tmpl;
6761 specs[count++].index = regno;
6762 }
6763 }
6764 break;
6765
6766 case IA64_RS_CR:
6767 if (note == 1)
6768 {
6769 if (idesc->operands[!rsrc_write] == IA64_OPND_CR3)
6770 {
6771 specs[count] = tmpl;
6772 specs[count++].index =
6773 CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR;
6774 }
6775 }
6776 else
6777 {
6778 UNHANDLED;
6779 }
6780 break;
6781
6782 case IA64_RS_FR:
6783 case IA64_RS_FRb:
6784 if (note != 1)
6785 {
6786 UNHANDLED;
6787 }
6788 else if (rsrc_write)
6789 {
6790 if (dep->specifier == IA64_RS_FRb
6791 && idesc->operands[0] == IA64_OPND_F1)
6792 {
6793 specs[count] = tmpl;
6794 specs[count++].index = CURR_SLOT.opnd[0].X_add_number - REG_FR;
6795 }
6796 }
6797 else
6798 {
6799 for (i=idesc->num_outputs;i < NELEMS(idesc->operands);i++)
6800 {
6801 if (idesc->operands[i] == IA64_OPND_F2
6802 || idesc->operands[i] == IA64_OPND_F3
6803 || idesc->operands[i] == IA64_OPND_F4)
6804 {
6805 specs[count] = tmpl;
6806 specs[count++].index =
6807 CURR_SLOT.opnd[i].X_add_number - REG_FR;
6808 }
6809 }
6810 }
6811 break;
6812
6813 case IA64_RS_GR:
6814 if (note == 13)
6815 {
6816 /* This reference applies only to the GR whose value is loaded with
6817 data returned from memory */
6818 specs[count] = tmpl;
6819 specs[count++].index = CURR_SLOT.opnd[0].X_add_number - REG_GR;
6820 }
6821 else if (note == 1)
6822 {
6823 if (rsrc_write)
6824 {
6825 for (i= 0; i < idesc->num_outputs; i++)
6826 if (idesc->operands[i] == IA64_OPND_R1
6827 || idesc->operands[i] == IA64_OPND_R2
6828 || idesc->operands[i] == IA64_OPND_R3)
6829 {
6830 specs[count] = tmpl;
6831 specs[count++].index =
6832 CURR_SLOT.opnd[i].X_add_number - REG_GR;
6833 }
6834 if (idesc->flags & IA64_OPCODE_POSTINC)
6835 for (i = 0; i < NELEMS (idesc->operands); i++)
6836 if (idesc->operands[i] == IA64_OPND_MR3)
6837 {
6838 specs[count] = tmpl;
6839 specs[count++].index =
6840 CURR_SLOT.opnd[i].X_add_number - REG_GR;
6841 }
6842 }
6843 else
6844 {
6845 /* Look for anything that reads a GR */
6846 for (i=0;i < NELEMS(idesc->operands);i++)
6847 {
6848 if (idesc->operands[i] == IA64_OPND_MR3
6849 || idesc->operands[i] == IA64_OPND_CPUID_R3
6850 || idesc->operands[i] == IA64_OPND_DBR_R3
6851 || idesc->operands[i] == IA64_OPND_IBR_R3
6852 || idesc->operands[i] == IA64_OPND_MSR_R3
6853 || idesc->operands[i] == IA64_OPND_PKR_R3
6854 || idesc->operands[i] == IA64_OPND_PMC_R3
6855 || idesc->operands[i] == IA64_OPND_PMD_R3
6856 || idesc->operands[i] == IA64_OPND_RR_R3
6857 || ((i >= idesc->num_outputs)
6858 && (idesc->operands[i] == IA64_OPND_R1
6859 || idesc->operands[i] == IA64_OPND_R2
6860 || idesc->operands[i] == IA64_OPND_R3
6861 /* addl source register. */
6862 || idesc->operands[i] == IA64_OPND_R3_2)))
6863 {
6864 specs[count] = tmpl;
6865 specs[count++].index =
6866 CURR_SLOT.opnd[i].X_add_number - REG_GR;
6867 }
6868 }
6869 }
6870 }
6871 else
6872 {
6873 UNHANDLED;
6874 }
6875 break;
6876
6877 case IA64_RS_PR:
6878 if (note == 0)
6879 {
6880 if (idesc->operands[0] == IA64_OPND_PR_ROT)
6881 {
6882 for (i=16;i < 63;i++)
6883 {
6884 specs[count] = tmpl;
6885 specs[count++].index = i;
6886 }
6887 }
6888 else
6889 {
6890 for (i=1;i < 63;i++)
6891 {
6892 specs[count] = tmpl;
6893 specs[count++].index = i;
6894 }
6895 }
6896 }
6897 else if (note == 7)
6898 {
6899 valueT mask = 0;
6900 /* mark only those registers indicated by the mask */
6901 if (rsrc_write
6902 && idesc->operands[0] == IA64_OPND_PR)
6903 {
6904 mask = CURR_SLOT.opnd[2].X_add_number;
6905 if (mask & ((valueT)1<<16))
6906 mask |= ~(valueT)0xffff;
6907 for (i=1;i < 63;i++)
6908 {
6909 if (mask & ((valueT)1<<i))
6910 {
6911 specs[count] = tmpl;
6912 specs[count++].index = i;
6913 }
6914 }
6915 }
6916 else if (rsrc_write
6917 && idesc->operands[0] == IA64_OPND_PR_ROT)
6918 {
6919 for (i=16;i < 63;i++)
6920 {
6921 specs[count] = tmpl;
6922 specs[count++].index = i;
6923 }
6924 }
6925 else
6926 {
6927 UNHANDLED;
6928 }
6929 }
6930 else if (note == 11) /* note 11 implies note 1 as well */
6931 {
6932 if (rsrc_write)
6933 {
6934 for (i=0;i < idesc->num_outputs;i++)
6935 {
6936 if (idesc->operands[i] == IA64_OPND_P1
6937 || idesc->operands[i] == IA64_OPND_P2)
6938 {
6939 int regno = CURR_SLOT.opnd[i].X_add_number - REG_P;
6940 if (regno != 0)
6941 {
6942 specs[count] = tmpl;
6943 specs[count++].index = regno;
6944 }
6945 }
6946 }
6947 }
6948 else
6949 {
6950 UNHANDLED;
6951 }
6952 }
6953 else if (note == 12)
6954 {
6955 if (CURR_SLOT.qp_regno != 0)
6956 {
6957 specs[count] = tmpl;
6958 specs[count++].index = CURR_SLOT.qp_regno;
6959 }
6960 }
6961 else if (note == 1)
6962 {
6963 if (rsrc_write)
6964 {
6965 int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P;
6966 int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P;
6967 if ((idesc->operands[0] == IA64_OPND_P1
6968 || idesc->operands[0] == IA64_OPND_P2)
6969 && p1 != 0 && p1 != 63)
6970 {
6971 specs[count] = tmpl;
6972 specs[count++].index = p1;
6973 }
6974 if ((idesc->operands[1] == IA64_OPND_P1
6975 || idesc->operands[1] == IA64_OPND_P2)
6976 && p2 != 0 && p2 != 63)
6977 {
6978 specs[count] = tmpl;
6979 specs[count++].index = p2;
6980 }
6981 }
6982 else
6983 {
6984 if (CURR_SLOT.qp_regno != 0)
6985 {
6986 specs[count] = tmpl;
6987 specs[count++].index = CURR_SLOT.qp_regno;
6988 }
6989 if (idesc->operands[1] == IA64_OPND_PR)
6990 {
6991 for (i=1;i < 63;i++)
6992 {
6993 specs[count] = tmpl;
6994 specs[count++].index = i;
6995 }
6996 }
6997 }
6998 }
6999 else
7000 {
7001 UNHANDLED;
7002 }
7003 break;
7004
7005 case IA64_RS_PSR:
7006 /* Verify that the instruction is using the PSR bit indicated in
7007 dep->regindex */
7008 if (note == 0)
7009 {
7010 if (idesc->operands[!rsrc_write] == IA64_OPND_PSR_UM)
7011 {
7012 if (dep->regindex < 6)
7013 {
7014 specs[count++] = tmpl;
7015 }
7016 }
7017 else if (idesc->operands[!rsrc_write] == IA64_OPND_PSR)
7018 {
7019 if (dep->regindex < 32
7020 || dep->regindex == 35
7021 || dep->regindex == 36
7022 || (!rsrc_write && dep->regindex == PSR_CPL))
7023 {
7024 specs[count++] = tmpl;
7025 }
7026 }
7027 else if (idesc->operands[!rsrc_write] == IA64_OPND_PSR_L)
7028 {
7029 if (dep->regindex < 32
7030 || dep->regindex == 35
7031 || dep->regindex == 36
7032 || (rsrc_write && dep->regindex == PSR_CPL))
7033 {
7034 specs[count++] = tmpl;
7035 }
7036 }
7037 else
7038 {
7039 /* Several PSR bits have very specific dependencies. */
7040 switch (dep->regindex)
7041 {
7042 default:
7043 specs[count++] = tmpl;
7044 break;
7045 case PSR_IC:
7046 if (rsrc_write)
7047 {
7048 specs[count++] = tmpl;
7049 }
7050 else
7051 {
7052 /* Only certain CR accesses use PSR.ic */
7053 if (idesc->operands[0] == IA64_OPND_CR3
7054 || idesc->operands[1] == IA64_OPND_CR3)
7055 {
7056 int index =
7057 ((idesc->operands[0] == IA64_OPND_CR3)
7058 ? 0 : 1);
7059 int regno =
7060 CURR_SLOT.opnd[index].X_add_number - REG_CR;
7061
7062 switch (regno)
7063 {
7064 default:
7065 break;
7066 case CR_ITIR:
7067 case CR_IFS:
7068 case CR_IIM:
7069 case CR_IIP:
7070 case CR_IPSR:
7071 case CR_ISR:
7072 case CR_IFA:
7073 case CR_IHA:
7074 case CR_IIPA:
7075 specs[count++] = tmpl;
7076 break;
7077 }
7078 }
7079 }
7080 break;
7081 case PSR_CPL:
7082 if (rsrc_write)
7083 {
7084 specs[count++] = tmpl;
7085 }
7086 else
7087 {
7088 /* Only some AR accesses use cpl */
7089 if (idesc->operands[0] == IA64_OPND_AR3
7090 || idesc->operands[1] == IA64_OPND_AR3)
7091 {
7092 int index =
7093 ((idesc->operands[0] == IA64_OPND_AR3)
7094 ? 0 : 1);
7095 int regno =
7096 CURR_SLOT.opnd[index].X_add_number - REG_AR;
7097
7098 if (regno == AR_ITC
7099 || (index == 0
7100 && (regno == AR_ITC
7101 || regno == AR_RSC
7102 || (regno >= AR_K0
7103 && regno <= AR_K7))))
7104 {
7105 specs[count++] = tmpl;
7106 }
7107 }
7108 else
7109 {
7110 specs[count++] = tmpl;
7111 }
7112 break;
7113 }
7114 }
7115 }
7116 }
7117 else if (note == 7)
7118 {
7119 valueT mask = 0;
7120 if (idesc->operands[0] == IA64_OPND_IMMU24)
7121 {
7122 mask = CURR_SLOT.opnd[0].X_add_number;
7123 }
7124 else
7125 {
7126 UNHANDLED;
7127 }
7128 if (mask & ((valueT)1<<dep->regindex))
7129 {
7130 specs[count++] = tmpl;
7131 }
7132 }
7133 else if (note == 8)
7134 {
7135 int min = dep->regindex == PSR_DFL ? 2 : 32;
7136 int max = dep->regindex == PSR_DFL ? 31 : 127;
7137 /* dfh is read on FR32-127; dfl is read on FR2-31 */
7138 for (i=0;i < NELEMS(idesc->operands);i++)
7139 {
7140 if (idesc->operands[i] == IA64_OPND_F1
7141 || idesc->operands[i] == IA64_OPND_F2
7142 || idesc->operands[i] == IA64_OPND_F3
7143 || idesc->operands[i] == IA64_OPND_F4)
7144 {
7145 int reg = CURR_SLOT.opnd[i].X_add_number - REG_FR;
7146 if (reg >= min && reg <= max)
7147 {
7148 specs[count++] = tmpl;
7149 }
7150 }
7151 }
7152 }
7153 else if (note == 9)
7154 {
7155 int min = dep->regindex == PSR_MFL ? 2 : 32;
7156 int max = dep->regindex == PSR_MFL ? 31 : 127;
7157 /* mfh is read on writes to FR32-127; mfl is read on writes to
7158 FR2-31 */
7159 for (i=0;i < idesc->num_outputs;i++)
7160 {
7161 if (idesc->operands[i] == IA64_OPND_F1)
7162 {
7163 int reg = CURR_SLOT.opnd[i].X_add_number - REG_FR;
7164 if (reg >= min && reg <= max)
7165 {
7166 specs[count++] = tmpl;
7167 }
7168 }
7169 }
7170 }
7171 else if (note == 10)
7172 {
7173 for (i=0;i < NELEMS(idesc->operands);i++)
7174 {
7175 if (idesc->operands[i] == IA64_OPND_R1
7176 || idesc->operands[i] == IA64_OPND_R2
7177 || idesc->operands[i] == IA64_OPND_R3)
7178 {
7179 int regno = CURR_SLOT.opnd[i].X_add_number - REG_GR;
7180 if (regno >= 16 && regno <= 31)
7181 {
7182 specs[count++] = tmpl;
7183 }
7184 }
7185 }
7186 }
7187 else
7188 {
7189 UNHANDLED;
7190 }
7191 break;
7192
7193 case IA64_RS_AR_FPSR:
7194 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3)
7195 {
7196 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
7197 if (regno == AR_FPSR)
7198 {
7199 specs[count++] = tmpl;
7200 }
7201 }
7202 else
7203 {
7204 specs[count++] = tmpl;
7205 }
7206 break;
7207
7208 case IA64_RS_ARX:
7209 /* Handle all AR[REG] resources */
7210 if (note == 0 || note == 1)
7211 {
7212 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
7213 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3
7214 && regno == dep->regindex)
7215 {
7216 specs[count++] = tmpl;
7217 }
7218 /* other AR[REG] resources may be affected by AR accesses */
7219 else if (idesc->operands[0] == IA64_OPND_AR3)
7220 {
7221 /* AR[] writes */
7222 regno = CURR_SLOT.opnd[0].X_add_number - REG_AR;
7223 switch (dep->regindex)
7224 {
7225 default:
7226 break;
7227 case AR_BSP:
7228 case AR_RNAT:
7229 if (regno == AR_BSPSTORE)
7230 {
7231 specs[count++] = tmpl;
7232 }
7233 case AR_RSC:
7234 if (!rsrc_write &&
7235 (regno == AR_BSPSTORE
7236 || regno == AR_RNAT))
7237 {
7238 specs[count++] = tmpl;
7239 }
7240 break;
7241 }
7242 }
7243 else if (idesc->operands[1] == IA64_OPND_AR3)
7244 {
7245 /* AR[] reads */
7246 regno = CURR_SLOT.opnd[1].X_add_number - REG_AR;
7247 switch (dep->regindex)
7248 {
7249 default:
7250 break;
7251 case AR_RSC:
7252 if (regno == AR_BSPSTORE || regno == AR_RNAT)
7253 {
7254 specs[count++] = tmpl;
7255 }
7256 break;
7257 }
7258 }
7259 else
7260 {
7261 specs[count++] = tmpl;
7262 }
7263 }
7264 else
7265 {
7266 UNHANDLED;
7267 }
7268 break;
7269
7270 case IA64_RS_CRX:
7271 /* Handle all CR[REG] resources */
7272 if (note == 0 || note == 1)
7273 {
7274 if (idesc->operands[!rsrc_write] == IA64_OPND_CR3)
7275 {
7276 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR;
7277 if (regno == dep->regindex)
7278 {
7279 specs[count++] = tmpl;
7280 }
7281 else if (!rsrc_write)
7282 {
7283 /* Reads from CR[IVR] affect other resources. */
7284 if (regno == CR_IVR)
7285 {
7286 if ((dep->regindex >= CR_IRR0
7287 && dep->regindex <= CR_IRR3)
7288 || dep->regindex == CR_TPR)
7289 {
7290 specs[count++] = tmpl;
7291 }
7292 }
7293 }
7294 }
7295 else
7296 {
7297 specs[count++] = tmpl;
7298 }
7299 }
7300 else
7301 {
7302 UNHANDLED;
7303 }
7304 break;
7305
7306 case IA64_RS_INSERVICE:
7307 /* look for write of EOI (67) or read of IVR (65) */
7308 if ((idesc->operands[0] == IA64_OPND_CR3
7309 && CURR_SLOT.opnd[0].X_add_number - REG_CR == CR_EOI)
7310 || (idesc->operands[1] == IA64_OPND_CR3
7311 && CURR_SLOT.opnd[1].X_add_number - REG_CR == CR_IVR))
7312 {
7313 specs[count++] = tmpl;
7314 }
7315 break;
7316
7317 case IA64_RS_GR0:
7318 if (note == 1)
7319 {
7320 specs[count++] = tmpl;
7321 }
7322 else
7323 {
7324 UNHANDLED;
7325 }
7326 break;
7327
7328 case IA64_RS_CFM:
7329 if (note != 2)
7330 {
7331 specs[count++] = tmpl;
7332 }
7333 else
7334 {
7335 /* Check if any of the registers accessed are in the rotating region.
7336 mov to/from pr accesses CFM only when qp_regno is in the rotating
7337 region */
7338 for (i=0;i < NELEMS(idesc->operands);i++)
7339 {
7340 if (idesc->operands[i] == IA64_OPND_R1
7341 || idesc->operands[i] == IA64_OPND_R2
7342 || idesc->operands[i] == IA64_OPND_R3)
7343 {
7344 int num = CURR_SLOT.opnd[i].X_add_number - REG_GR;
7345 /* Assumes that md.rot.num_regs is always valid */
7346 if (md.rot.num_regs > 0
7347 && num > 31
7348 && num < 31 + md.rot.num_regs)
7349 {
7350 specs[count] = tmpl;
7351 specs[count++].specific = 0;
7352 }
7353 }
7354 else if (idesc->operands[i] == IA64_OPND_F1
7355 || idesc->operands[i] == IA64_OPND_F2
7356 || idesc->operands[i] == IA64_OPND_F3
7357 || idesc->operands[i] == IA64_OPND_F4)
7358 {
7359 int num = CURR_SLOT.opnd[i].X_add_number - REG_FR;
7360 if (num > 31)
7361 {
7362 specs[count] = tmpl;
7363 specs[count++].specific = 0;
7364 }
7365 }
7366 else if (idesc->operands[i] == IA64_OPND_P1
7367 || idesc->operands[i] == IA64_OPND_P2)
7368 {
7369 int num = CURR_SLOT.opnd[i].X_add_number - REG_P;
7370 if (num > 15)
7371 {
7372 specs[count] = tmpl;
7373 specs[count++].specific = 0;
7374 }
7375 }
7376 }
7377 if (CURR_SLOT.qp_regno > 15)
7378 {
7379 specs[count] = tmpl;
7380 specs[count++].specific = 0;
7381 }
7382 }
7383 break;
7384
7385 case IA64_RS_PR63:
7386 if (note == 0)
7387 {
7388 specs[count++] = tmpl;
7389 }
7390 else if (note == 11)
7391 {
7392 if ((idesc->operands[0] == IA64_OPND_P1
7393 && CURR_SLOT.opnd[0].X_add_number - REG_P == 63)
7394 || (idesc->operands[1] == IA64_OPND_P2
7395 && CURR_SLOT.opnd[1].X_add_number - REG_P == 63))
7396 {
7397 specs[count++] = tmpl;
7398 }
7399 }
7400 else if (note == 12)
7401 {
7402 if (CURR_SLOT.qp_regno == 63)
7403 {
7404 specs[count++] = tmpl;
7405 }
7406 }
7407 else if (note == 7)
7408 {
7409 valueT mask = 0;
7410 if (idesc->operands[2] == IA64_OPND_IMM17)
7411 mask = CURR_SLOT.opnd[2].X_add_number;
7412 if (mask & ((valueT)1<<63))
7413 {
7414 specs[count++] = tmpl;
7415 }
7416 }
7417 else if (note == 1)
7418 {
7419 if (rsrc_write)
7420 {
7421 for (i=0;i < idesc->num_outputs;i++)
7422 if ((idesc->operands[i] == IA64_OPND_P1
7423 || idesc->operands[i] == IA64_OPND_P2)
7424 && CURR_SLOT.opnd[i].X_add_number - REG_P == 63)
7425 {
7426 specs[count++] = tmpl;
7427 }
7428 }
7429 else
7430 {
7431 if (CURR_SLOT.qp_regno == 63)
7432 {
7433 specs[count++] = tmpl;
7434 }
7435 }
7436 }
7437 else
7438 {
7439 UNHANDLED;
7440 }
7441 break;
7442
7443 case IA64_RS_RSE:
7444 /* FIXME we can identify some individual RSE written resources, but RSE
7445 read resources have not yet been completely identified, so for now
7446 treat RSE as a single resource */
7447 if (strncmp (idesc->name, "mov", 3) == 0)
7448 {
7449 if (rsrc_write)
7450 {
7451 if (idesc->operands[0] == IA64_OPND_AR3
7452 && CURR_SLOT.opnd[0].X_add_number - REG_AR == AR_BSPSTORE)
7453 {
7454 specs[count] = tmpl;
7455 specs[count++].index = 0; /* IA64_RSE_BSPLOAD/RNATBITINDEX */
7456 }
7457 }
7458 else
7459 {
7460 if (idesc->operands[0] == IA64_OPND_AR3)
7461 {
7462 if (CURR_SLOT.opnd[0].X_add_number - REG_AR == AR_BSPSTORE
7463 || CURR_SLOT.opnd[0].X_add_number - REG_AR == AR_RNAT)
7464 {
7465 specs[count++] = tmpl;
7466 }
7467 }
7468 else if (idesc->operands[1] == IA64_OPND_AR3)
7469 {
7470 if (CURR_SLOT.opnd[1].X_add_number - REG_AR == AR_BSP
7471 || CURR_SLOT.opnd[1].X_add_number - REG_AR == AR_BSPSTORE
7472 || CURR_SLOT.opnd[1].X_add_number - REG_AR == AR_RNAT)
7473 {
7474 specs[count++] = tmpl;
7475 }
7476 }
7477 }
7478 }
7479 else
7480 {
7481 specs[count++] = tmpl;
7482 }
7483 break;
7484
7485 case IA64_RS_ANY:
7486 /* FIXME -- do any of these need to be non-specific? */
7487 specs[count++] = tmpl;
7488 break;
7489
7490 default:
7491 as_bad (_("Unrecognized dependency specifier %d\n"), dep->specifier);
7492 break;
7493 }
7494
7495 return count;
7496 }
7497
7498 /* Clear branch flags on marked resources. This breaks the link between the
7499 QP of the marking instruction and a subsequent branch on the same QP.
7500 */
7501 static void
7502 clear_qp_branch_flag (mask)
7503 valueT mask;
7504 {
7505 int i;
7506 for (i = 0;i < regdepslen;i++)
7507 {
7508 valueT bit = ((valueT)1 << regdeps[i].qp_regno);
7509 if ((bit & mask) != 0)
7510 {
7511 regdeps[i].link_to_qp_branch = 0;
7512 }
7513 }
7514 }
7515
7516 /* Remove any mutexes which contain any of the PRs indicated in the mask.
7517
7518 Any changes to a PR clears the mutex relations which include that PR.
7519 */
7520 static void
7521 clear_qp_mutex (mask)
7522 valueT mask;
7523 {
7524 int i;
7525
7526 i = 0;
7527 while (i < qp_mutexeslen)
7528 {
7529 if ((qp_mutexes[i].prmask & mask) != 0)
7530 {
7531 if (md.debug_dv)
7532 {
7533 fprintf (stderr, " Clearing mutex relation");
7534 print_prmask (qp_mutexes[i].prmask);
7535 fprintf (stderr, "\n");
7536 }
7537 qp_mutexes[i] = qp_mutexes[--qp_mutexeslen];
7538 }
7539 else
7540 ++i;
7541 }
7542 }
7543
7544 /* Clear implies relations which contain PRs in the given masks.
7545 P1_MASK indicates the source of the implies relation, while P2_MASK
7546 indicates the implied PR.
7547 */
7548 static void
7549 clear_qp_implies (p1_mask, p2_mask)
7550 valueT p1_mask;
7551 valueT p2_mask;
7552 {
7553 int i;
7554
7555 i = 0;
7556 while (i < qp_implieslen)
7557 {
7558 if ((((valueT)1 << qp_implies[i].p1) & p1_mask) != 0
7559 || (((valueT)1 << qp_implies[i].p2) & p2_mask) != 0)
7560 {
7561 if (md.debug_dv)
7562 fprintf (stderr, "Clearing implied relation PR%d->PR%d\n",
7563 qp_implies[i].p1, qp_implies[i].p2);
7564 qp_implies[i] = qp_implies[--qp_implieslen];
7565 }
7566 else
7567 ++i;
7568 }
7569 }
7570
7571 /* add the PRs specified to the list of implied relations */
7572 static void
7573 add_qp_imply (p1, p2)
7574 int p1, p2;
7575 {
7576 valueT mask;
7577 valueT bit;
7578 int i;
7579
7580 /* p0 is not meaningful here */
7581 if (p1 == 0 || p2 == 0)
7582 abort ();
7583
7584 if (p1 == p2)
7585 return;
7586
7587 /* if it exists already, ignore it */
7588 for (i=0;i < qp_implieslen;i++)
7589 {
7590 if (qp_implies[i].p1 == p1
7591 && qp_implies[i].p2 == p2
7592 && qp_implies[i].path == md.path
7593 && !qp_implies[i].p2_branched)
7594 return;
7595 }
7596
7597 if (qp_implieslen == qp_impliestotlen)
7598 {
7599 qp_impliestotlen += 20;
7600 qp_implies = (struct qp_imply *)
7601 xrealloc ((void *)qp_implies,
7602 qp_impliestotlen * sizeof (struct qp_imply));
7603 }
7604 if (md.debug_dv)
7605 fprintf (stderr, " Registering PR%d implies PR%d\n", p1, p2);
7606 qp_implies[qp_implieslen].p1 = p1;
7607 qp_implies[qp_implieslen].p2 = p2;
7608 qp_implies[qp_implieslen].path = md.path;
7609 qp_implies[qp_implieslen++].p2_branched = 0;
7610
7611 /* Add in the implied transitive relations; for everything that p2 implies,
7612 make p1 imply that, too; for everything that implies p1, make it imply p2
7613 as well. */
7614 for (i=0;i < qp_implieslen;i++)
7615 {
7616 if (qp_implies[i].p1 == p2)
7617 add_qp_imply (p1, qp_implies[i].p2);
7618 if (qp_implies[i].p2 == p1)
7619 add_qp_imply (qp_implies[i].p1, p2);
7620 }
7621 /* Add in mutex relations implied by this implies relation; for each mutex
7622 relation containing p2, duplicate it and replace p2 with p1. */
7623 bit = (valueT)1 << p1;
7624 mask = (valueT)1 << p2;
7625 for (i=0;i < qp_mutexeslen;i++)
7626 {
7627 if (qp_mutexes[i].prmask & mask)
7628 add_qp_mutex ((qp_mutexes[i].prmask & ~mask) | bit);
7629 }
7630 }
7631
7632
7633 /* Add the PRs specified in the mask to the mutex list; this means that only
7634 one of the PRs can be true at any time. PR0 should never be included in
7635 the mask. */
7636 static void
7637 add_qp_mutex (mask)
7638 valueT mask;
7639 {
7640 if (mask & 0x1)
7641 abort ();
7642
7643 if (qp_mutexeslen == qp_mutexestotlen)
7644 {
7645 qp_mutexestotlen += 20;
7646 qp_mutexes = (struct qpmutex *)
7647 xrealloc ((void *)qp_mutexes,
7648 qp_mutexestotlen * sizeof (struct qpmutex));
7649 }
7650 if (md.debug_dv)
7651 {
7652 fprintf (stderr, " Registering mutex on");
7653 print_prmask (mask);
7654 fprintf (stderr, "\n");
7655 }
7656 qp_mutexes[qp_mutexeslen].path = md.path;
7657 qp_mutexes[qp_mutexeslen++].prmask = mask;
7658 }
7659
7660 static void
7661 clear_register_values ()
7662 {
7663 int i;
7664 if (md.debug_dv)
7665 fprintf (stderr, " Clearing register values\n");
7666 for (i=1;i < NELEMS(gr_values);i++)
7667 gr_values[i].known = 0;
7668 }
7669
7670 /* Keep track of register values/changes which affect DV tracking.
7671
7672 optimization note: should add a flag to classes of insns where otherwise we
7673 have to examine a group of strings to identify them.
7674
7675 */
7676 static void
7677 note_register_values (idesc)
7678 struct ia64_opcode *idesc;
7679 {
7680 valueT qp_changemask = 0;
7681 int i;
7682
7683 /* invalidate values for registers being written to */
7684 for (i=0;i < idesc->num_outputs;i++)
7685 {
7686 if (idesc->operands[i] == IA64_OPND_R1
7687 || idesc->operands[i] == IA64_OPND_R2
7688 || idesc->operands[i] == IA64_OPND_R3)
7689 {
7690 int regno = CURR_SLOT.opnd[i].X_add_number - REG_GR;
7691 if (regno > 0 && regno < NELEMS(gr_values))
7692 gr_values[regno].known = 0;
7693 }
7694 else if (idesc->operands[i] == IA64_OPND_R3_2)
7695 {
7696 int regno = CURR_SLOT.opnd[i].X_add_number - REG_GR;
7697 if (regno > 0 && regno < 4)
7698 gr_values[regno].known = 0;
7699 }
7700 else if (idesc->operands[i] == IA64_OPND_P1
7701 || idesc->operands[i] == IA64_OPND_P2)
7702 {
7703 int regno = CURR_SLOT.opnd[i].X_add_number - REG_P;
7704 qp_changemask |= (valueT)1 << regno;
7705 }
7706 else if (idesc->operands[i] == IA64_OPND_PR)
7707 {
7708 if (idesc->operands[2] & (valueT)0x10000)
7709 qp_changemask = ~(valueT)0x1FFFF | idesc->operands[2];
7710 else
7711 qp_changemask = idesc->operands[2];
7712 break;
7713 }
7714 else if (idesc->operands[i] == IA64_OPND_PR_ROT)
7715 {
7716 if (idesc->operands[1] & ((valueT)1 << 43))
7717 qp_changemask = ~(valueT)0xFFFFFFFFFFF | idesc->operands[1];
7718 else
7719 qp_changemask = idesc->operands[1];
7720 qp_changemask &= ~(valueT)0xFFFF;
7721 break;
7722 }
7723 }
7724
7725 /* Always clear qp branch flags on any PR change */
7726 /* FIXME there may be exceptions for certain compares */
7727 clear_qp_branch_flag (qp_changemask);
7728
7729 /* invalidate rotating registers on insns which affect RRBs in CFM */
7730 if (idesc->flags & IA64_OPCODE_MOD_RRBS)
7731 {
7732 qp_changemask |= ~(valueT)0xFFFF;
7733 if (strcmp (idesc->name, "clrrrb.pr") != 0)
7734 {
7735 for (i=32;i < 32+md.rot.num_regs;i++)
7736 gr_values[i].known = 0;
7737 }
7738 clear_qp_mutex (qp_changemask);
7739 clear_qp_implies (qp_changemask, qp_changemask);
7740 }
7741 /* after a call, all register values are undefined, except those marked
7742 as "safe" */
7743 else if (strncmp (idesc->name, "br.call", 6) == 0
7744 || strncmp (idesc->name, "brl.call", 7) == 0)
7745 {
7746 // FIXME keep GR values which are marked as "safe_across_calls"
7747 clear_register_values ();
7748 clear_qp_mutex (~qp_safe_across_calls);
7749 clear_qp_implies (~qp_safe_across_calls, ~qp_safe_across_calls);
7750 clear_qp_branch_flag (~qp_safe_across_calls);
7751 }
7752 else if (is_interruption_or_rfi (idesc)
7753 || is_taken_branch (idesc))
7754 {
7755 clear_register_values ();
7756 clear_qp_mutex (~(valueT)0);
7757 clear_qp_implies (~(valueT)0, ~(valueT)0);
7758 }
7759 /* Look for mutex and implies relations */
7760 else if ((idesc->operands[0] == IA64_OPND_P1
7761 || idesc->operands[0] == IA64_OPND_P2)
7762 && (idesc->operands[1] == IA64_OPND_P1
7763 || idesc->operands[1] == IA64_OPND_P2))
7764 {
7765 int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P;
7766 int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P;
7767 valueT p1mask = (valueT)1 << p1;
7768 valueT p2mask = (valueT)1 << p2;
7769
7770 /* if one of the PRs is PR0, we can't really do anything */
7771 if (p1 == 0 || p2 == 0)
7772 {
7773 if (md.debug_dv)
7774 fprintf (stderr, " Ignoring PRs due to inclusion of p0\n");
7775 }
7776 /* In general, clear mutexes and implies which include P1 or P2,
7777 with the following exceptions */
7778 else if (strstr (idesc->name, ".or.andcm") != NULL)
7779 {
7780 add_qp_mutex (p1mask | p2mask);
7781 clear_qp_implies (p2mask, p1mask);
7782 }
7783 else if (strstr (idesc->name, ".and.orcm") != NULL)
7784 {
7785 add_qp_mutex (p1mask | p2mask);
7786 clear_qp_implies (p1mask, p2mask);
7787 }
7788 else if (strstr (idesc->name, ".and") != NULL)
7789 {
7790 clear_qp_implies (0, p1mask | p2mask);
7791 }
7792 else if (strstr (idesc->name, ".or") != NULL)
7793 {
7794 clear_qp_mutex (p1mask | p2mask);
7795 clear_qp_implies (p1mask | p2mask, 0);
7796 }
7797 else
7798 {
7799 clear_qp_implies (p1mask | p2mask, p1mask | p2mask);
7800 if (strstr (idesc->name, ".unc") != NULL)
7801 {
7802 add_qp_mutex (p1mask | p2mask);
7803 if (CURR_SLOT.qp_regno != 0)
7804 {
7805 add_qp_imply (CURR_SLOT.opnd[0].X_add_number - REG_P,
7806 CURR_SLOT.qp_regno);
7807 add_qp_imply (CURR_SLOT.opnd[1].X_add_number - REG_P,
7808 CURR_SLOT.qp_regno);
7809 }
7810 }
7811 else if (CURR_SLOT.qp_regno == 0)
7812 {
7813 add_qp_mutex (p1mask | p2mask);
7814 }
7815 else
7816 {
7817 clear_qp_mutex (p1mask | p2mask);
7818 }
7819 }
7820 }
7821 /* Look for mov imm insns into GRs */
7822 else if (idesc->operands[0] == IA64_OPND_R1
7823 && (idesc->operands[1] == IA64_OPND_IMM22
7824 || idesc->operands[1] == IA64_OPND_IMMU64)
7825 && (strcmp(idesc->name, "mov") == 0
7826 || strcmp(idesc->name, "movl") == 0))
7827 {
7828 int regno = CURR_SLOT.opnd[0].X_add_number - REG_GR;
7829 if (regno > 0 && regno < NELEMS(gr_values))
7830 {
7831 gr_values[regno].known = 1;
7832 gr_values[regno].value = CURR_SLOT.opnd[1].X_add_number;
7833 gr_values[regno].path = md.path;
7834 if (md.debug_dv)
7835 fprintf (stderr, " Know gr%d = 0x%llx\n",
7836 regno, gr_values[regno].value);
7837 }
7838 }
7839 else
7840 {
7841 clear_qp_mutex (qp_changemask);
7842 clear_qp_implies (qp_changemask, qp_changemask);
7843 }
7844 }
7845
7846 /* Return whether the given predicate registers are currently mutex */
7847 static int
7848 qp_mutex (p1, p2, path)
7849 int p1;
7850 int p2;
7851 int path;
7852 {
7853 int i;
7854 valueT mask;
7855
7856 if (p1 != p2)
7857 {
7858 mask = ((valueT)1<<p1) | (valueT)1<<p2;
7859 for (i=0;i < qp_mutexeslen;i++)
7860 {
7861 if (qp_mutexes[i].path >= path
7862 && (qp_mutexes[i].prmask & mask) == mask)
7863 return 1;
7864 }
7865 }
7866 return 0;
7867 }
7868
7869 /* Return whether the given resource is in the given insn's list of chks
7870 Return 1 if the conflict is absolutely determined, 2 if it's a potential
7871 conflict.
7872 */
7873 static int
7874 resources_match (rs, idesc, note, qp_regno, path)
7875 struct rsrc *rs;
7876 struct ia64_opcode *idesc;
7877 int note;
7878 int qp_regno;
7879 int path;
7880 {
7881 struct rsrc specs[MAX_SPECS];
7882 int count;
7883
7884 /* If the marked resource's qp_regno and the given qp_regno are mutex,
7885 we don't need to check. One exception is note 11, which indicates that
7886 target predicates are written regardless of PR[qp]. */
7887 if (qp_mutex (rs->qp_regno, qp_regno, path)
7888 && note != 11)
7889 return 0;
7890
7891 count = specify_resource (rs->dependency, idesc, DV_CHK, specs, note, path);
7892 while (count-- > 0)
7893 {
7894 /* UNAT checking is a bit more specific than other resources */
7895 if (rs->dependency->specifier == IA64_RS_AR_UNAT
7896 && specs[count].mem_offset.hint
7897 && rs->mem_offset.hint)
7898 {
7899 if (rs->mem_offset.base == specs[count].mem_offset.base)
7900 {
7901 if (((rs->mem_offset.offset >> 3) & 0x3F) ==
7902 ((specs[count].mem_offset.offset >> 3) & 0x3F))
7903 return 1;
7904 else
7905 continue;
7906 }
7907 }
7908
7909 /* If either resource is not specific, conservatively assume a conflict
7910 */
7911 if (!specs[count].specific || !rs->specific)
7912 return 2;
7913 else if (specs[count].index == rs->index)
7914 return 1;
7915 }
7916 #if 0
7917 if (md.debug_dv)
7918 fprintf (stderr, " No %s conflicts\n", rs->dependency->name);
7919 #endif
7920
7921 return 0;
7922 }
7923
7924 /* Indicate an instruction group break; if INSERT_STOP is non-zero, then
7925 insert a stop to create the break. Update all resource dependencies
7926 appropriately. If QP_REGNO is non-zero, only apply the break to resources
7927 which use the same QP_REGNO and have the link_to_qp_branch flag set.
7928 If SAVE_CURRENT is non-zero, don't affect resources marked by the current
7929 instruction.
7930 */
7931
7932 static void
7933 insn_group_break (insert_stop, qp_regno, save_current)
7934 int insert_stop;
7935 int qp_regno;
7936 int save_current;
7937 {
7938 int i;
7939
7940 if (insert_stop && md.num_slots_in_use > 0)
7941 PREV_SLOT.end_of_insn_group = 1;
7942
7943 if (md.debug_dv)
7944 {
7945 fprintf (stderr, " Insn group break%s",
7946 (insert_stop ? " (w/stop)" : ""));
7947 if (qp_regno != 0)
7948 fprintf (stderr, " effective for QP=%d", qp_regno);
7949 fprintf (stderr, "\n");
7950 }
7951
7952 i = 0;
7953 while (i < regdepslen)
7954 {
7955 const struct ia64_dependency *dep = regdeps[i].dependency;
7956
7957 if (qp_regno != 0
7958 && regdeps[i].qp_regno != qp_regno)
7959 {
7960 ++i;
7961 continue;
7962 }
7963
7964 if (save_current
7965 && CURR_SLOT.src_file == regdeps[i].file
7966 && CURR_SLOT.src_line == regdeps[i].line)
7967 {
7968 ++i;
7969 continue;
7970 }
7971
7972 /* clear dependencies which are automatically cleared by a stop, or
7973 those that have reached the appropriate state of insn serialization */
7974 if (dep->semantics == IA64_DVS_IMPLIED
7975 || dep->semantics == IA64_DVS_IMPLIEDF
7976 || regdeps[i].insn_srlz == STATE_SRLZ)
7977 {
7978 print_dependency ("Removing", i);
7979 regdeps[i] = regdeps[--regdepslen];
7980 }
7981 else
7982 {
7983 if (dep->semantics == IA64_DVS_DATA
7984 || dep->semantics == IA64_DVS_INSTR
7985 || dep->semantics == IA64_DVS_SPECIFIC)
7986 {
7987 if (regdeps[i].insn_srlz == STATE_NONE)
7988 regdeps[i].insn_srlz = STATE_STOP;
7989 if (regdeps[i].data_srlz == STATE_NONE)
7990 regdeps[i].data_srlz = STATE_STOP;
7991 }
7992 ++i;
7993 }
7994 }
7995 }
7996
7997 /* Add the given resource usage spec to the list of active dependencies */
7998 static void
7999 mark_resource (idesc, dep, spec, depind, path)
8000 struct ia64_opcode *idesc;
8001 const struct ia64_dependency *dep;
8002 struct rsrc *spec;
8003 int depind;
8004 int path;
8005 {
8006 if (regdepslen == regdepstotlen)
8007 {
8008 regdepstotlen += 20;
8009 regdeps = (struct rsrc *)
8010 xrealloc ((void *)regdeps,
8011 regdepstotlen * sizeof(struct rsrc));
8012 }
8013
8014 regdeps[regdepslen] = *spec;
8015 regdeps[regdepslen].depind = depind;
8016 regdeps[regdepslen].path = path;
8017 regdeps[regdepslen].file = CURR_SLOT.src_file;
8018 regdeps[regdepslen].line = CURR_SLOT.src_line;
8019
8020 print_dependency ("Adding", regdepslen);
8021
8022 ++regdepslen;
8023 }
8024
8025 static void
8026 print_dependency (action, depind)
8027 const char *action;
8028 int depind;
8029 {
8030 if (md.debug_dv)
8031 {
8032 fprintf (stderr, " %s %s '%s'",
8033 action, dv_mode[(regdeps[depind].dependency)->mode],
8034 (regdeps[depind].dependency)->name);
8035 if (regdeps[depind].specific && regdeps[depind].index != 0)
8036 fprintf (stderr, " (%d)", regdeps[depind].index);
8037 if (regdeps[depind].mem_offset.hint)
8038 fprintf (stderr, " 0x%llx+0x%llx",
8039 regdeps[depind].mem_offset.base,
8040 regdeps[depind].mem_offset.offset);
8041 fprintf (stderr, "\n");
8042 }
8043 }
8044
8045 static void
8046 instruction_serialization ()
8047 {
8048 int i;
8049 if (md.debug_dv)
8050 fprintf (stderr, " Instruction serialization\n");
8051 for (i=0;i < regdepslen;i++)
8052 if (regdeps[i].insn_srlz == STATE_STOP)
8053 regdeps[i].insn_srlz = STATE_SRLZ;
8054 }
8055
8056 static void
8057 data_serialization ()
8058 {
8059 int i = 0;
8060 if (md.debug_dv)
8061 fprintf (stderr, " Data serialization\n");
8062 while (i < regdepslen)
8063 {
8064 if (regdeps[i].data_srlz == STATE_STOP
8065 /* Note: as of 991210, all "other" dependencies are cleared by a
8066 data serialization. This might change with new tables */
8067 || (regdeps[i].dependency)->semantics == IA64_DVS_OTHER)
8068 {
8069 print_dependency ("Removing", i);
8070 regdeps[i] = regdeps[--regdepslen];
8071 }
8072 else
8073 ++i;
8074 }
8075 }
8076
8077 /* Insert stops and serializations as needed to avoid DVs */
8078 static void
8079 remove_marked_resource (rs)
8080 struct rsrc *rs;
8081 {
8082 switch (rs->dependency->semantics)
8083 {
8084 case IA64_DVS_SPECIFIC:
8085 if (md.debug_dv)
8086 fprintf (stderr, "Implementation-specific, assume worst case...\n");
8087 /* ...fall through... */
8088 case IA64_DVS_INSTR:
8089 if (md.debug_dv)
8090 fprintf (stderr, "Inserting instr serialization\n");
8091 if (rs->insn_srlz < STATE_STOP)
8092 insn_group_break (1, 0, 0);
8093 if (rs->insn_srlz < STATE_SRLZ)
8094 {
8095 int oldqp = CURR_SLOT.qp_regno;
8096 struct ia64_opcode *oldidesc = CURR_SLOT.idesc;
8097 /* Manually jam a srlz.i insn into the stream */
8098 CURR_SLOT.qp_regno = 0;
8099 CURR_SLOT.idesc = ia64_find_opcode ("srlz.i");
8100 instruction_serialization ();
8101 md.curr_slot = (md.curr_slot + 1) % NUM_SLOTS;
8102 if (++md.num_slots_in_use >= NUM_SLOTS)
8103 emit_one_bundle ();
8104 CURR_SLOT.qp_regno = oldqp;
8105 CURR_SLOT.idesc = oldidesc;
8106 }
8107 insn_group_break (1, 0, 0);
8108 break;
8109 case IA64_DVS_OTHER: /* as of rev2 (991220) of the DV tables, all
8110 "other" types of DV are eliminated
8111 by a data serialization */
8112 case IA64_DVS_DATA:
8113 if (md.debug_dv)
8114 fprintf (stderr, "Inserting data serialization\n");
8115 if (rs->data_srlz < STATE_STOP)
8116 insn_group_break (1, 0, 0);
8117 {
8118 int oldqp = CURR_SLOT.qp_regno;
8119 struct ia64_opcode *oldidesc = CURR_SLOT.idesc;
8120 /* Manually jam a srlz.d insn into the stream */
8121 CURR_SLOT.qp_regno = 0;
8122 CURR_SLOT.idesc = ia64_find_opcode ("srlz.d");
8123 data_serialization ();
8124 md.curr_slot = (md.curr_slot + 1) % NUM_SLOTS;
8125 if (++md.num_slots_in_use >= NUM_SLOTS)
8126 emit_one_bundle ();
8127 CURR_SLOT.qp_regno = oldqp;
8128 CURR_SLOT.idesc = oldidesc;
8129 }
8130 break;
8131 case IA64_DVS_IMPLIED:
8132 case IA64_DVS_IMPLIEDF:
8133 if (md.debug_dv)
8134 fprintf (stderr, "Inserting stop\n");
8135 insn_group_break (1, 0, 0);
8136 break;
8137 default:
8138 break;
8139 }
8140 }
8141
8142 /* Check the resources used by the given opcode against the current dependency
8143 list.
8144
8145 The check is run once for each execution path encountered. In this case,
8146 a unique execution path is the sequence of instructions following a code
8147 entry point, e.g. the following has three execution paths, one starting
8148 at L0, one at L1, and one at L2.
8149
8150 L0: nop
8151 L1: add
8152 L2: add
8153 br.ret
8154 */
8155 static void
8156 check_dependencies (idesc)
8157 struct ia64_opcode *idesc;
8158 {
8159 const struct ia64_opcode_dependency *opdeps = idesc->dependencies;
8160 int path;
8161 int i;
8162
8163 /* Note that the number of marked resources may change within the
8164 loop if in auto mode. */
8165 i = 0;
8166 while (i < regdepslen)
8167 {
8168 struct rsrc *rs = &regdeps[i];
8169 const struct ia64_dependency *dep = rs->dependency;
8170 int chkind;
8171 int note;
8172 int start_over = 0;
8173
8174 if (dep->semantics == IA64_DVS_NONE
8175 || (chkind = depends_on (rs->depind, idesc)) == -1)
8176 {
8177 ++i; continue;
8178 }
8179
8180 note = NOTE(opdeps->chks[chkind]);
8181
8182 /* Check this resource against each execution path seen thus far */
8183 for (path=0;path <= md.path;path++)
8184 {
8185 int matchtype;
8186
8187 /* If the dependency wasn't on the path being checked, ignore it */
8188 if (rs->path < path)
8189 continue;
8190
8191 /* If the QP for this insn implies a QP which has branched, don't
8192 bother checking. Ed. NOTE: I don't think this check is terribly
8193 useful; what's the point of generating code which will only be
8194 reached if its QP is zero?
8195 This code was specifically inserted to handle the following code,
8196 based on notes from Intel's DV checking code, where p1 implies p2.
8197
8198 mov r4 = 2
8199 (p2) br.cond L
8200 (p1) mov r4 = 7
8201
8202 */
8203 if (CURR_SLOT.qp_regno != 0)
8204 {
8205 int skip = 0;
8206 int implies;
8207 for (implies=0;implies < qp_implieslen;implies++)
8208 {
8209 if (qp_implies[implies].path >= path
8210 && qp_implies[implies].p1 == CURR_SLOT.qp_regno
8211 && qp_implies[implies].p2_branched)
8212 {
8213 skip = 1;
8214 break;
8215 }
8216 }
8217 if (skip)
8218 continue;
8219 }
8220
8221 if ((matchtype = resources_match (rs, idesc, note,
8222 CURR_SLOT.qp_regno, path)) != 0)
8223 {
8224 char msg[1024];
8225 char pathmsg[256] = "";
8226 char indexmsg[256] = "";
8227 int certain = (matchtype == 1 && CURR_SLOT.qp_regno == 0);
8228
8229 if (path != 0)
8230 sprintf (pathmsg, " when entry is at label '%s'",
8231 md.entry_labels[path-1]);
8232 if (rs->specific && rs->index != 0)
8233 sprintf (indexmsg, ", specific resource number is %d",
8234 rs->index);
8235 sprintf (msg, "Use of '%s' %s %s dependency '%s' (%s)%s%s",
8236 idesc->name,
8237 (certain ? "violates" : "may violate"),
8238 dv_mode[dep->mode], dep->name,
8239 dv_sem[dep->semantics],
8240 pathmsg, indexmsg);
8241
8242 if (md.explicit_mode)
8243 {
8244 as_warn ("%s", msg);
8245 if (path < md.path)
8246 as_warn (_("Only the first path encountering the conflict "
8247 "is reported"));
8248 as_warn_where (rs->file, rs->line,
8249 _("This is the location of the "
8250 "conflicting usage"));
8251 /* Don't bother checking other paths, to avoid duplicating
8252 the same warning */
8253 break;
8254 }
8255 else
8256 {
8257 if (md.debug_dv)
8258 fprintf(stderr, "%s @ %s:%d\n", msg, rs->file, rs->line);
8259
8260 remove_marked_resource (rs);
8261
8262 /* since the set of dependencies has changed, start over */
8263 /* FIXME -- since we're removing dvs as we go, we
8264 probably don't really need to start over... */
8265 start_over = 1;
8266 break;
8267 }
8268 }
8269 }
8270 if (start_over)
8271 i = 0;
8272 else
8273 ++i;
8274 }
8275 }
8276
8277 /* register new dependencies based on the given opcode */
8278 static void
8279 mark_resources (idesc)
8280 struct ia64_opcode *idesc;
8281 {
8282 int i;
8283 const struct ia64_opcode_dependency *opdeps = idesc->dependencies;
8284 int add_only_qp_reads = 0;
8285
8286 /* A conditional branch only uses its resources if it is taken; if it is
8287 taken, we stop following that path. The other branch types effectively
8288 *always* write their resources. If it's not taken, register only QP
8289 reads. */
8290 if (is_conditional_branch (idesc) || is_interruption_or_rfi (idesc))
8291 {
8292 add_only_qp_reads = 1;
8293 }
8294
8295 if (md.debug_dv)
8296 fprintf (stderr, "Registering '%s' resource usage\n", idesc->name);
8297
8298 for (i=0;i < opdeps->nregs;i++)
8299 {
8300 const struct ia64_dependency *dep;
8301 struct rsrc specs[MAX_SPECS];
8302 int note;
8303 int path;
8304 int count;
8305
8306 dep = ia64_find_dependency (opdeps->regs[i]);
8307 note = NOTE(opdeps->regs[i]);
8308
8309 if (add_only_qp_reads
8310 && !(dep->mode == IA64_DV_WAR
8311 && (dep->specifier == IA64_RS_PR
8312 || dep->specifier == IA64_RS_PR63)))
8313 continue;
8314
8315 count = specify_resource (dep, idesc, DV_REG, specs, note, md.path);
8316
8317 #if 0
8318 if (md.debug_dv && !count)
8319 fprintf (stderr, " No %s %s usage found (path %d)\n",
8320 dv_mode[dep->mode], dep->name, md.path);
8321 #endif
8322
8323 while (count-- > 0)
8324 {
8325 mark_resource (idesc, dep, &specs[count],
8326 DEP(opdeps->regs[i]), md.path);
8327 }
8328
8329 /* The execution path may affect register values, which may in turn
8330 affect which indirect-access resources are accessed. */
8331 switch (dep->specifier)
8332 {
8333 default:
8334 break;
8335 case IA64_RS_CPUID:
8336 case IA64_RS_DBR:
8337 case IA64_RS_IBR:
8338 case IA64_RS_MSR:
8339 case IA64_RS_PKR:
8340 case IA64_RS_PMC:
8341 case IA64_RS_PMD:
8342 case IA64_RS_RR:
8343 for (path=0;path < md.path;path++)
8344 {
8345 count = specify_resource (dep, idesc, DV_REG, specs, note, path);
8346 while (count-- > 0)
8347 mark_resource (idesc, dep, &specs[count],
8348 DEP(opdeps->regs[i]), path);
8349 }
8350 break;
8351 }
8352 }
8353 }
8354
8355 /* remove dependencies when they no longer apply */
8356 static void
8357 update_dependencies (idesc)
8358 struct ia64_opcode *idesc;
8359 {
8360 int i;
8361
8362 if (strcmp (idesc->name, "srlz.i") == 0)
8363 {
8364 instruction_serialization ();
8365 }
8366 else if (strcmp (idesc->name, "srlz.d") == 0)
8367 {
8368 data_serialization ();
8369 }
8370 else if (is_interruption_or_rfi (idesc)
8371 || is_taken_branch (idesc))
8372 {
8373 /* although technically the taken branch doesn't clear dependencies
8374 which require a srlz.[id], we don't follow the branch; the next
8375 instruction is assumed to start with a clean slate */
8376 regdepslen = 0;
8377 md.path = 0;
8378 }
8379 else if (is_conditional_branch (idesc)
8380 && CURR_SLOT.qp_regno != 0)
8381 {
8382 int is_call = strstr (idesc->name, ".call") != NULL;
8383
8384 for (i=0;i < qp_implieslen;i++)
8385 {
8386 /* if the conditional branch's predicate is implied by the predicate
8387 in an existing dependency, remove that dependency */
8388 if (qp_implies[i].p2 == CURR_SLOT.qp_regno)
8389 {
8390 int depind = 0;
8391 /* note that this implied predicate takes a branch so that if
8392 a later insn generates a DV but its predicate implies this
8393 one, we can avoid the false DV warning */
8394 qp_implies[i].p2_branched = 1;
8395 while (depind < regdepslen)
8396 {
8397 if (regdeps[depind].qp_regno == qp_implies[i].p1)
8398 {
8399 print_dependency ("Removing", depind);
8400 regdeps[depind] = regdeps[--regdepslen];
8401 }
8402 else
8403 ++depind;
8404 }
8405 }
8406 }
8407 /* Any marked resources which have this same predicate should be
8408 cleared, provided that the QP hasn't been modified between the
8409 marking instruction and the branch.
8410 */
8411 if (is_call)
8412 {
8413 insn_group_break (0, CURR_SLOT.qp_regno, 1);
8414 }
8415 else
8416 {
8417 i = 0;
8418 while (i < regdepslen)
8419 {
8420 if (regdeps[i].qp_regno == CURR_SLOT.qp_regno
8421 && regdeps[i].link_to_qp_branch
8422 && (regdeps[i].file != CURR_SLOT.src_file
8423 || regdeps[i].line != CURR_SLOT.src_line))
8424 {
8425 /* Treat like a taken branch */
8426 print_dependency ("Removing", i);
8427 regdeps[i] = regdeps[--regdepslen];
8428 }
8429 else
8430 ++i;
8431 }
8432 }
8433 }
8434 }
8435
8436 /* Examine the current instruction for dependency violations. */
8437 static int
8438 check_dv (idesc)
8439 struct ia64_opcode *idesc;
8440 {
8441 if (md.debug_dv)
8442 {
8443 fprintf (stderr, "Checking %s for violations (line %d, %d/%d)\n",
8444 idesc->name, CURR_SLOT.src_line,
8445 idesc->dependencies->nchks,
8446 idesc->dependencies->nregs);
8447 }
8448
8449 /* Look through the list of currently marked resources; if the current
8450 instruction has the dependency in its chks list which uses that resource,
8451 check against the specific resources used.
8452 */
8453 check_dependencies (idesc);
8454
8455 /*
8456 Look up the instruction's regdeps (RAW writes, WAW writes, and WAR reads),
8457 then add them to the list of marked resources.
8458 */
8459 mark_resources (idesc);
8460
8461 /* There are several types of dependency semantics, and each has its own
8462 requirements for being cleared
8463
8464 Instruction serialization (insns separated by interruption, rfi, or
8465 writer + srlz.i + reader, all in separate groups) clears DVS_INSTR.
8466
8467 Data serialization (instruction serialization, or writer + srlz.d +
8468 reader, where writer and srlz.d are in separate groups) clears
8469 DVS_DATA. (This also clears DVS_OTHER, but that is not guaranteed to
8470 always be the case).
8471
8472 Instruction group break (groups separated by stop, taken branch,
8473 interruption or rfi) clears DVS_IMPLIED and DVS_IMPLIEDF.
8474 */
8475 update_dependencies (idesc);
8476
8477 /* Sometimes, knowing a register value allows us to avoid giving a false DV
8478 warning. Keep track of as many as possible that are useful. */
8479 note_register_values (idesc);
8480
8481 /* We don't need or want this anymore. */
8482 md.mem_offset.hint = 0;
8483
8484 return 0;
8485 }
8486
8487 /* Translate one line of assembly. Pseudo ops and labels do not show
8488 here. */
8489 void
8490 md_assemble (str)
8491 char *str;
8492 {
8493 char *saved_input_line_pointer, *mnemonic;
8494 const struct pseudo_opcode *pdesc;
8495 struct ia64_opcode *idesc;
8496 unsigned char qp_regno;
8497 unsigned int flags;
8498 int ch;
8499
8500 saved_input_line_pointer = input_line_pointer;
8501 input_line_pointer = str;
8502
8503 /* extract the opcode (mnemonic): */
8504
8505 mnemonic = input_line_pointer;
8506 ch = get_symbol_end ();
8507 pdesc = (struct pseudo_opcode *) hash_find (md.pseudo_hash, mnemonic);
8508 if (pdesc)
8509 {
8510 *input_line_pointer = ch;
8511 (*pdesc->handler) (pdesc->arg);
8512 goto done;
8513 }
8514
8515 /* find the instruction descriptor matching the arguments: */
8516
8517 idesc = ia64_find_opcode (mnemonic);
8518 *input_line_pointer = ch;
8519 if (!idesc)
8520 {
8521 as_bad ("Unknown opcode `%s'", mnemonic);
8522 goto done;
8523 }
8524
8525 idesc = parse_operands (idesc);
8526 if (!idesc)
8527 goto done;
8528
8529 /* Handle the dynamic ops we can handle now: */
8530 if (idesc->type == IA64_TYPE_DYN)
8531 {
8532 if (strcmp (idesc->name, "add") == 0)
8533 {
8534 if (CURR_SLOT.opnd[2].X_op == O_register
8535 && CURR_SLOT.opnd[2].X_add_number < 4)
8536 mnemonic = "addl";
8537 else
8538 mnemonic = "adds";
8539 ia64_free_opcode (idesc);
8540 idesc = ia64_find_opcode (mnemonic);
8541 #if 0
8542 know (!idesc->next);
8543 #endif
8544 }
8545 else if (strcmp (idesc->name, "mov") == 0)
8546 {
8547 enum ia64_opnd opnd1, opnd2;
8548 int rop;
8549
8550 opnd1 = idesc->operands[0];
8551 opnd2 = idesc->operands[1];
8552 if (opnd1 == IA64_OPND_AR3)
8553 rop = 0;
8554 else if (opnd2 == IA64_OPND_AR3)
8555 rop = 1;
8556 else
8557 abort ();
8558 if (CURR_SLOT.opnd[rop].X_op == O_register
8559 && ar_is_in_integer_unit (CURR_SLOT.opnd[rop].X_add_number))
8560 mnemonic = "mov.i";
8561 else
8562 mnemonic = "mov.m";
8563 ia64_free_opcode (idesc);
8564 idesc = ia64_find_opcode (mnemonic);
8565 while (idesc != NULL
8566 && (idesc->operands[0] != opnd1
8567 || idesc->operands[1] != opnd2))
8568 idesc = get_next_opcode (idesc);
8569 }
8570 }
8571
8572 qp_regno = 0;
8573 if (md.qp.X_op == O_register)
8574 qp_regno = md.qp.X_add_number - REG_P;
8575
8576 flags = idesc->flags;
8577
8578 if ((flags & IA64_OPCODE_FIRST) != 0)
8579 insn_group_break (1, 0, 0);
8580
8581 if ((flags & IA64_OPCODE_NO_PRED) != 0 && qp_regno != 0)
8582 {
8583 as_bad ("`%s' cannot be predicated", idesc->name);
8584 goto done;
8585 }
8586
8587 /* build the instruction: */
8588 CURR_SLOT.qp_regno = qp_regno;
8589 CURR_SLOT.idesc = idesc;
8590 as_where (&CURR_SLOT.src_file, &CURR_SLOT.src_line);
8591 if (debug_type == DEBUG_DWARF2)
8592 dwarf2_where (&CURR_SLOT.debug_line);
8593
8594 /* Add unwind entry, if there is one. */
8595 if (unwind.current_entry)
8596 {
8597 CURR_SLOT.unwind_record = unwind.current_entry;
8598 unwind.current_entry = NULL;
8599 }
8600
8601 /* check for dependency violations */
8602 if (md.detect_dv)
8603 check_dv(idesc);
8604
8605 md.curr_slot = (md.curr_slot + 1) % NUM_SLOTS;
8606 if (++md.num_slots_in_use >= NUM_SLOTS)
8607 emit_one_bundle ();
8608
8609 if ((flags & IA64_OPCODE_LAST) != 0)
8610 insn_group_break (1, 0, 0);
8611
8612 md.last_text_seg = now_seg;
8613
8614 done:
8615 input_line_pointer = saved_input_line_pointer;
8616 }
8617
8618 /* Called when symbol NAME cannot be found in the symbol table.
8619 Should be used for dynamic valued symbols only. */
8620 symbolS*
8621 md_undefined_symbol (name)
8622 char *name;
8623 {
8624 return 0;
8625 }
8626
8627 /* Called for any expression that can not be recognized. When the
8628 function is called, `input_line_pointer' will point to the start of
8629 the expression. */
8630 void
8631 md_operand (e)
8632 expressionS *e;
8633 {
8634 enum pseudo_type pseudo_type;
8635 const char *name;
8636 size_t len;
8637 int ch, i;
8638
8639 switch (*input_line_pointer)
8640 {
8641 case '@':
8642 /* find what relocation pseudo-function we're dealing with: */
8643 pseudo_type = 0;
8644 ch = *++input_line_pointer;
8645 for (i = 0; i < NELEMS (pseudo_func); ++i)
8646 if (pseudo_func[i].name && pseudo_func[i].name[0] == ch)
8647 {
8648 len = strlen (pseudo_func[i].name);
8649 if (strncmp (pseudo_func[i].name + 1,
8650 input_line_pointer + 1, len - 1) == 0
8651 && !is_part_of_name (input_line_pointer[len]))
8652 {
8653 input_line_pointer += len;
8654 pseudo_type = pseudo_func[i].type;
8655 break;
8656 }
8657 }
8658 switch (pseudo_type)
8659 {
8660 case PSEUDO_FUNC_RELOC:
8661 SKIP_WHITESPACE ();
8662 if (*input_line_pointer != '(')
8663 {
8664 as_bad ("Expected '('");
8665 goto err;
8666 }
8667 ++input_line_pointer; /* skip '(' */
8668 expression (e);
8669 if (*input_line_pointer++ != ')')
8670 {
8671 as_bad ("Missing ')'");
8672 goto err;
8673 }
8674 if (e->X_op != O_symbol)
8675 {
8676 if (e->X_op != O_pseudo_fixup)
8677 {
8678 as_bad ("Not a symbolic expression");
8679 goto err;
8680 }
8681 if (S_GET_VALUE (e->X_op_symbol) == FUNC_FPTR_RELATIVE
8682 && i == FUNC_LT_RELATIVE)
8683 i = FUNC_LT_FPTR_RELATIVE;
8684 else
8685 {
8686 as_bad ("Illegal combination of relocation functions");
8687 goto err;
8688 }
8689 }
8690 /* make sure gas doesn't get rid of local symbols that are used
8691 in relocs: */
8692 e->X_op = O_pseudo_fixup;
8693 e->X_op_symbol = pseudo_func[i].u.sym;
8694 break;
8695
8696 case PSEUDO_FUNC_CONST:
8697 e->X_op = O_constant;
8698 e->X_add_number = pseudo_func[i].u.ival;
8699 break;
8700
8701 case PSEUDO_FUNC_REG:
8702 e->X_op = O_register;
8703 e->X_add_number = pseudo_func[i].u.ival;
8704 break;
8705
8706 default:
8707 name = input_line_pointer - 1;
8708 get_symbol_end ();
8709 as_bad ("Unknown pseudo function `%s'", name);
8710 goto err;
8711 }
8712 break;
8713
8714 case '[':
8715 ++input_line_pointer;
8716 expression (e);
8717 if (*input_line_pointer != ']')
8718 {
8719 as_bad ("Closing bracket misssing");
8720 goto err;
8721 }
8722 else
8723 {
8724 if (e->X_op != O_register)
8725 as_bad ("Register expected as index");
8726
8727 ++input_line_pointer;
8728 e->X_op = O_index;
8729 }
8730 break;
8731
8732 default:
8733 break;
8734 }
8735 return;
8736
8737 err:
8738 ignore_rest_of_line ();
8739 }
8740
8741 /* Return 1 if it's OK to adjust a reloc by replacing the symbol with
8742 a section symbol plus some offset. For relocs involving @fptr(),
8743 directives we don't want such adjustments since we need to have the
8744 original symbol's name in the reloc. */
8745 int
8746 ia64_fix_adjustable (fix)
8747 fixS *fix;
8748 {
8749 /* Prevent all adjustments to global symbols */
8750 if (S_IS_EXTERN (fix->fx_addsy) || S_IS_WEAK (fix->fx_addsy))
8751 return 0;
8752
8753 switch (fix->fx_r_type)
8754 {
8755 case BFD_RELOC_IA64_FPTR64I:
8756 case BFD_RELOC_IA64_FPTR32MSB:
8757 case BFD_RELOC_IA64_FPTR32LSB:
8758 case BFD_RELOC_IA64_FPTR64MSB:
8759 case BFD_RELOC_IA64_FPTR64LSB:
8760 case BFD_RELOC_IA64_LTOFF_FPTR22:
8761 case BFD_RELOC_IA64_LTOFF_FPTR64I:
8762 return 0;
8763 default:
8764 break;
8765 }
8766
8767 return 1;
8768 }
8769
8770 int
8771 ia64_force_relocation (fix)
8772 fixS *fix;
8773 {
8774 switch (fix->fx_r_type)
8775 {
8776 case BFD_RELOC_IA64_FPTR64I:
8777 case BFD_RELOC_IA64_FPTR32MSB:
8778 case BFD_RELOC_IA64_FPTR32LSB:
8779 case BFD_RELOC_IA64_FPTR64MSB:
8780 case BFD_RELOC_IA64_FPTR64LSB:
8781
8782 case BFD_RELOC_IA64_LTOFF22:
8783 case BFD_RELOC_IA64_LTOFF64I:
8784 case BFD_RELOC_IA64_LTOFF_FPTR22:
8785 case BFD_RELOC_IA64_LTOFF_FPTR64I:
8786 case BFD_RELOC_IA64_PLTOFF22:
8787 case BFD_RELOC_IA64_PLTOFF64I:
8788 case BFD_RELOC_IA64_PLTOFF64MSB:
8789 case BFD_RELOC_IA64_PLTOFF64LSB:
8790 return 1;
8791
8792 default:
8793 return 0;
8794 }
8795 return 0;
8796 }
8797
8798 /* Decide from what point a pc-relative relocation is relative to,
8799 relative to the pc-relative fixup. Er, relatively speaking. */
8800 long
8801 ia64_pcrel_from_section (fix, sec)
8802 fixS *fix;
8803 segT sec;
8804 {
8805 unsigned long off = fix->fx_frag->fr_address + fix->fx_where;
8806
8807 if (bfd_get_section_flags (stdoutput, sec) & SEC_CODE)
8808 off &= ~0xfUL;
8809
8810 return off;
8811 }
8812
8813 /* This is called whenever some data item (not an instruction) needs a
8814 fixup. We pick the right reloc code depending on the byteorder
8815 currently in effect. */
8816 void
8817 ia64_cons_fix_new (f, where, nbytes, exp)
8818 fragS *f;
8819 int where;
8820 int nbytes;
8821 expressionS *exp;
8822 {
8823 bfd_reloc_code_real_type code;
8824 fixS *fix;
8825
8826 switch (nbytes)
8827 {
8828 /* There are no reloc for 8 and 16 bit quantities, but we allow
8829 them here since they will work fine as long as the expression
8830 is fully defined at the end of the pass over the source file. */
8831 case 1: code = BFD_RELOC_8; break;
8832 case 2: code = BFD_RELOC_16; break;
8833 case 4:
8834 if (target_big_endian)
8835 code = BFD_RELOC_IA64_DIR32MSB;
8836 else
8837 code = BFD_RELOC_IA64_DIR32LSB;
8838 break;
8839
8840 case 8:
8841 if (target_big_endian)
8842 code = BFD_RELOC_IA64_DIR64MSB;
8843 else
8844 code = BFD_RELOC_IA64_DIR64LSB;
8845 break;
8846
8847 default:
8848 as_bad ("Unsupported fixup size %d", nbytes);
8849 ignore_rest_of_line ();
8850 return;
8851 }
8852 if (exp->X_op == O_pseudo_fixup)
8853 {
8854 /* ??? */
8855 exp->X_op = O_symbol;
8856 code = ia64_gen_real_reloc_type (exp->X_op_symbol, code);
8857 }
8858 fix = fix_new_exp (f, where, nbytes, exp, 0, code);
8859 /* We need to store the byte order in effect in case we're going
8860 to fix an 8 or 16 bit relocation (for which there no real
8861 relocs available). See md_apply_fix(). */
8862 fix->tc_fix_data.bigendian = target_big_endian;
8863 }
8864
8865 /* Return the actual relocation we wish to associate with the pseudo
8866 reloc described by SYM and R_TYPE. SYM should be one of the
8867 symbols in the pseudo_func array, or NULL. */
8868
8869 static bfd_reloc_code_real_type
8870 ia64_gen_real_reloc_type (sym, r_type)
8871 struct symbol *sym;
8872 bfd_reloc_code_real_type r_type;
8873 {
8874 bfd_reloc_code_real_type new = 0;
8875
8876 if (sym == NULL)
8877 {
8878 return r_type;
8879 }
8880
8881 switch (S_GET_VALUE (sym))
8882 {
8883 case FUNC_FPTR_RELATIVE:
8884 switch (r_type)
8885 {
8886 case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_FPTR64I; break;
8887 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_FPTR32MSB; break;
8888 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_FPTR32LSB; break;
8889 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_FPTR64MSB; break;
8890 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_FPTR64LSB; break;
8891 default: break;
8892 }
8893 break;
8894
8895 case FUNC_GP_RELATIVE:
8896 switch (r_type)
8897 {
8898 case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_GPREL22; break;
8899 case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_GPREL64I; break;
8900 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_GPREL32MSB; break;
8901 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_GPREL32LSB; break;
8902 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_GPREL64MSB; break;
8903 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_GPREL64LSB; break;
8904 default: break;
8905 }
8906 break;
8907
8908 case FUNC_LT_RELATIVE:
8909 switch (r_type)
8910 {
8911 case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_LTOFF22; break;
8912 case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_LTOFF64I; break;
8913 default: break;
8914 }
8915 break;
8916
8917 case FUNC_PC_RELATIVE:
8918 switch (r_type)
8919 {
8920 case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_PCREL22; break;
8921 case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_PCREL64I; break;
8922 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_PCREL32MSB; break;
8923 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_PCREL32LSB; break;
8924 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_PCREL64MSB; break;
8925 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_PCREL64LSB; break;
8926 default: break;
8927 }
8928 break;
8929
8930 case FUNC_PLT_RELATIVE:
8931 switch (r_type)
8932 {
8933 case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_PLTOFF22; break;
8934 case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_PLTOFF64I; break;
8935 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_PLTOFF64MSB;break;
8936 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_PLTOFF64LSB;break;
8937 default: break;
8938 }
8939 break;
8940
8941 case FUNC_SEC_RELATIVE:
8942 switch (r_type)
8943 {
8944 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_SECREL32MSB;break;
8945 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_SECREL32LSB;break;
8946 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_SECREL64MSB;break;
8947 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_SECREL64LSB;break;
8948 default: break;
8949 }
8950 break;
8951
8952 case FUNC_SEG_RELATIVE:
8953 switch (r_type)
8954 {
8955 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_SEGREL32MSB;break;
8956 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_SEGREL32LSB;break;
8957 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_SEGREL64MSB;break;
8958 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_SEGREL64LSB;break;
8959 default: break;
8960 }
8961 break;
8962
8963 case FUNC_LTV_RELATIVE:
8964 switch (r_type)
8965 {
8966 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_LTV32MSB; break;
8967 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_LTV32LSB; break;
8968 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_LTV64MSB; break;
8969 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_LTV64LSB; break;
8970 default: break;
8971 }
8972 break;
8973
8974 case FUNC_LT_FPTR_RELATIVE:
8975 switch (r_type)
8976 {
8977 case BFD_RELOC_IA64_IMM22:
8978 new = BFD_RELOC_IA64_LTOFF_FPTR22; break;
8979 case BFD_RELOC_IA64_IMM64:
8980 new = BFD_RELOC_IA64_LTOFF_FPTR64I; break;
8981 default:
8982 break;
8983 }
8984 break;
8985 default:
8986 abort ();
8987 }
8988 /* Hmmmm. Should this ever occur? */
8989 if (new)
8990 return new;
8991 else
8992 return r_type;
8993 }
8994
8995 /* Here is where generate the appropriate reloc for pseudo relocation
8996 functions. */
8997 void
8998 ia64_validate_fix (fix)
8999 fixS *fix;
9000 {
9001 switch (fix->fx_r_type)
9002 {
9003 case BFD_RELOC_IA64_FPTR64I:
9004 case BFD_RELOC_IA64_FPTR32MSB:
9005 case BFD_RELOC_IA64_FPTR64LSB:
9006 case BFD_RELOC_IA64_LTOFF_FPTR22:
9007 case BFD_RELOC_IA64_LTOFF_FPTR64I:
9008 if (fix->fx_offset != 0)
9009 as_bad_where (fix->fx_file, fix->fx_line,
9010 "No addend allowed in @fptr() relocation");
9011 break;
9012 default:
9013 break;
9014 }
9015
9016 return;
9017 }
9018
9019 static void
9020 fix_insn (fix, odesc, value)
9021 fixS *fix;
9022 const struct ia64_operand *odesc;
9023 valueT value;
9024 {
9025 bfd_vma insn[3], t0, t1, control_bits;
9026 const char *err;
9027 char *fixpos;
9028 long slot;
9029
9030 slot = fix->fx_where & 0x3;
9031 fixpos = fix->fx_frag->fr_literal + (fix->fx_where - slot);
9032
9033 /* Bundles are always in little-endian byte order */
9034 t0 = bfd_getl64 (fixpos);
9035 t1 = bfd_getl64 (fixpos + 8);
9036 control_bits = t0 & 0x1f;
9037 insn[0] = (t0 >> 5) & 0x1ffffffffffLL;
9038 insn[1] = ((t0 >> 46) & 0x3ffff) | ((t1 & 0x7fffff) << 18);
9039 insn[2] = (t1 >> 23) & 0x1ffffffffffLL;
9040
9041 err = NULL;
9042 if (odesc - elf64_ia64_operands == IA64_OPND_IMMU64)
9043 {
9044 insn[1] = (value >> 22) & 0x1ffffffffffLL;
9045 insn[2] |= (((value & 0x7f) << 13)
9046 | (((value >> 7) & 0x1ff) << 27)
9047 | (((value >> 16) & 0x1f) << 22)
9048 | (((value >> 21) & 0x1) << 21)
9049 | (((value >> 63) & 0x1) << 36));
9050 }
9051 else if (odesc - elf64_ia64_operands == IA64_OPND_IMMU62)
9052 {
9053 if (value & ~0x3fffffffffffffffULL)
9054 err = "integer operand out of range";
9055 insn[1] = (value >> 21) & 0x1ffffffffffLL;
9056 insn[2] |= (((value & 0xfffff) << 6) | (((value >> 20) & 0x1) << 36));
9057 }
9058 else if (odesc - elf64_ia64_operands == IA64_OPND_TGT64)
9059 {
9060 value >>= 4;
9061 insn[1] = ((value >> 20) & 0x7fffffffffLL) << 2;
9062 insn[2] |= ((((value >> 59) & 0x1) << 36)
9063 | (((value >> 0) & 0xfffff) << 13));
9064 }
9065 else
9066 err = (*odesc->insert) (odesc, value, insn + slot);
9067
9068 if (err)
9069 as_bad_where (fix->fx_file, fix->fx_line, err);
9070
9071 t0 = control_bits | (insn[0] << 5) | (insn[1] << 46);
9072 t1 = ((insn[1] >> 18) & 0x7fffff) | (insn[2] << 23);
9073 md_number_to_chars (fixpos + 0, t0, 8);
9074 md_number_to_chars (fixpos + 8, t1, 8);
9075 }
9076
9077 /* Attempt to simplify or even eliminate a fixup. The return value is
9078 ignored; perhaps it was once meaningful, but now it is historical.
9079 To indicate that a fixup has been eliminated, set FIXP->FX_DONE.
9080
9081 If fixp->fx_addsy is non-NULL, we'll have to generate a reloc entry
9082 (if possible). */
9083 int
9084 md_apply_fix3 (fix, valuep, seg)
9085 fixS *fix;
9086 valueT *valuep;
9087 segT seg;
9088 {
9089 char *fixpos;
9090 valueT value = *valuep;
9091 int adjust = 0;
9092
9093 fixpos = fix->fx_frag->fr_literal + fix->fx_where;
9094
9095 if (fix->fx_pcrel)
9096 {
9097 switch (fix->fx_r_type)
9098 {
9099 case BFD_RELOC_IA64_DIR32MSB:
9100 fix->fx_r_type = BFD_RELOC_IA64_PCREL32MSB;
9101 adjust = 1;
9102 break;
9103
9104 case BFD_RELOC_IA64_DIR32LSB:
9105 fix->fx_r_type = BFD_RELOC_IA64_PCREL32LSB;
9106 adjust = 1;
9107 break;
9108
9109 case BFD_RELOC_IA64_DIR64MSB:
9110 fix->fx_r_type = BFD_RELOC_IA64_PCREL64MSB;
9111 adjust = 1;
9112 break;
9113
9114 case BFD_RELOC_IA64_DIR64LSB:
9115 fix->fx_r_type = BFD_RELOC_IA64_PCREL64LSB;
9116 adjust = 1;
9117 break;
9118
9119 default:
9120 break;
9121 }
9122 }
9123 if (fix->fx_addsy)
9124 {
9125 switch (fix->fx_r_type)
9126 {
9127 case 0:
9128 as_bad_where (fix->fx_file, fix->fx_line,
9129 "%s must have a constant value",
9130 elf64_ia64_operands[fix->tc_fix_data.opnd].desc);
9131 break;
9132
9133 default:
9134 break;
9135 }
9136
9137 /* ??? This is a hack copied from tc-i386.c to make PCREL relocs
9138 work. There should be a better way to handle this. */
9139 if (adjust)
9140 fix->fx_offset += fix->fx_where + fix->fx_frag->fr_address;
9141 }
9142 else if (fix->tc_fix_data.opnd == IA64_OPND_NIL)
9143 {
9144 if (fix->tc_fix_data.bigendian)
9145 number_to_chars_bigendian (fixpos, value, fix->fx_size);
9146 else
9147 number_to_chars_littleendian (fixpos, value, fix->fx_size);
9148 fix->fx_done = 1;
9149 return 1;
9150 }
9151 else
9152 {
9153 fix_insn (fix, elf64_ia64_operands + fix->tc_fix_data.opnd, value);
9154 fix->fx_done = 1;
9155 return 1;
9156 }
9157 return 1;
9158 }
9159
9160 /* Generate the BFD reloc to be stuck in the object file from the
9161 fixup used internally in the assembler. */
9162 arelent*
9163 tc_gen_reloc (sec, fixp)
9164 asection *sec;
9165 fixS *fixp;
9166 {
9167 arelent *reloc;
9168
9169 reloc = xmalloc (sizeof (*reloc));
9170 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
9171 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
9172 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
9173 reloc->addend = fixp->fx_offset;
9174 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
9175
9176 if (!reloc->howto)
9177 {
9178 as_bad_where (fixp->fx_file, fixp->fx_line,
9179 "Cannot represent %s relocation in object file",
9180 bfd_get_reloc_code_name (fixp->fx_r_type));
9181 }
9182 return reloc;
9183 }
9184
9185 /* Turn a string in input_line_pointer into a floating point constant
9186 of type TYPE, and store the appropriate bytes in *LIT. The number
9187 of LITTLENUMS emitted is stored in *SIZE. An error message is
9188 returned, or NULL on OK. */
9189
9190 #define MAX_LITTLENUMS 5
9191
9192 char*
9193 md_atof (type, lit, size)
9194 int type;
9195 char *lit;
9196 int *size;
9197 {
9198 LITTLENUM_TYPE words[MAX_LITTLENUMS];
9199 LITTLENUM_TYPE *word;
9200 char *t;
9201 int prec;
9202
9203 switch (type)
9204 {
9205 /* IEEE floats */
9206 case 'f':
9207 case 'F':
9208 case 's':
9209 case 'S':
9210 prec = 2;
9211 break;
9212
9213 case 'd':
9214 case 'D':
9215 case 'r':
9216 case 'R':
9217 prec = 4;
9218 break;
9219
9220 case 'x':
9221 case 'X':
9222 case 'p':
9223 case 'P':
9224 prec = 5;
9225 break;
9226
9227 default:
9228 *size = 0;
9229 return "Bad call to MD_ATOF()";
9230 }
9231 t = atof_ieee (input_line_pointer, type, words);
9232 if (t)
9233 input_line_pointer = t;
9234 *size = prec * sizeof (LITTLENUM_TYPE);
9235
9236 for (word = words + prec - 1; prec--;)
9237 {
9238 md_number_to_chars (lit, (long) (*word--), sizeof (LITTLENUM_TYPE));
9239 lit += sizeof (LITTLENUM_TYPE);
9240 }
9241 return 0;
9242 }
9243
9244 /* Round up a section's size to the appropriate boundary. */
9245 valueT
9246 md_section_align (seg, size)
9247 segT seg;
9248 valueT size;
9249 {
9250 int align = bfd_get_section_alignment (stdoutput, seg);
9251 valueT mask = ((valueT)1 << align) - 1;
9252
9253 return (size + mask) & ~mask;
9254 }
9255
9256 /* Handle ia64 specific semantics of the align directive. */
9257
9258 int
9259 ia64_md_do_align (n, fill, len, max)
9260 int n;
9261 const char *fill;
9262 int len;
9263 int max;
9264 {
9265 /* Fill any pending bundle with nops. */
9266 if (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE)
9267 ia64_flush_insns ();
9268
9269 /* When we align code in a text section, emit a bundle of 3 nops instead of
9270 zero bytes. We can only do this if a multiple of 16 bytes was requested.
9271 N is log base 2 of the requested alignment. */
9272 if (fill == NULL
9273 && bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE
9274 && n > 4)
9275 {
9276 /* Use mfi bundle of nops with no stop bits. */
9277 static const unsigned char be_nop[]
9278 = { 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00,
9279 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x0c};
9280 static const unsigned char le_nop[]
9281 = { 0x0c, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
9282 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00};
9283
9284 /* Make sure we are on a 16-byte boundary, in case someone has been
9285 putting data into a text section. */
9286 frag_align (4, 0, 0);
9287
9288 if (target_big_endian)
9289 frag_align_pattern (n, be_nop, 16, max);
9290 else
9291 frag_align_pattern (n, le_nop, 16, max);
9292 return 1;
9293 }
9294
9295 return 0;
9296 }
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