include/opcode/tic80.h

   1 /* tic80.h -- Header file for TI TMS320C80 (MV) opcode table
   2    Copyright 1996, 1997, 2003 Free Software Foundation, Inc.
   3    Written by Fred Fish (fnf@cygnus.com), Cygnus Support
   4
   5 This file is part of GDB, GAS, and the GNU binutils.
   6
   7 GDB, GAS, and the GNU binutils are free software; you can redistribute
   8 them and/or modify them under the terms of the GNU General Public
   9 License as published by the Free Software Foundation; either version
  10 1, or (at your option) any later version.
  11
  12 GDB, GAS, and the GNU binutils are distributed in the hope that they
  13 will be useful, but WITHOUT ANY WARRANTY; without even the implied
  14 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
  15 the GNU General Public License for more details.
  16
  17 You should have received a copy of the GNU General Public License
  18 along with this file; see the file COPYING.  If not, write to the Free
  19 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
  20
  21 #ifndef TIC80_H
  22 #define TIC80_H
  23
  24 /* The opcode table is an array of struct tic80_opcode.  */
  25
  26 struct tic80_opcode
  27 {
  28   /* The opcode name.  */
  29
  30   const char *name;
  31
  32   /* The opcode itself.  Those bits which will be filled in with operands
  33      are zeroes.  */
  34
  35   unsigned long opcode;
  36
  37   /* The opcode mask.  This is used by the disassembler.  This is a mask
  38      containing ones indicating those bits which must match the opcode
  39      field, and zeroes indicating those bits which need not match (and are
  40      presumably filled in by operands).  */
  41
  42   unsigned long mask;
  43
  44   /* Special purpose flags for this opcode. */
  45
  46   unsigned char flags;
  47
  48   /* An array of operand codes.  Each code is an index into the operand
  49      table.  They appear in the order which the operands must appear in
  50      assembly code, and are terminated by a zero.  FIXME: Adjust size to
  51      match actual requirements when TIc80 support is complete */
  52
  53   unsigned char operands[8];
  54 };
  55
  56 /* The table itself is sorted by major opcode number, and is otherwise in
  57    the order in which the disassembler should consider instructions.
  58    FIXME: This isn't currently true. */
  59
  60 extern const struct tic80_opcode tic80_opcodes[];
  61 extern const int tic80_num_opcodes;
  62
  63 \f
  64 /* The operands table is an array of struct tic80_operand.  */
  65
  66 struct tic80_operand
  67 {
  68   /* The number of bits in the operand.  */
  69
  70   int bits;
  71
  72   /* How far the operand is left shifted in the instruction.  */
  73
  74   int shift;
  75
  76   /* Insertion function.  This is used by the assembler.  To insert an
  77      operand value into an instruction, check this field.
  78
  79      If it is NULL, execute
  80          i |= (op & ((1 << o->bits) - 1)) << o->shift;
  81      (i is the instruction which we are filling in, o is a pointer to
  82      this structure, and op is the opcode value; this assumes twos
  83      complement arithmetic).
  84
  85      If this field is not NULL, then simply call it with the
  86      instruction and the operand value.  It will return the new value
  87      of the instruction.  If the ERRMSG argument is not NULL, then if
  88      the operand value is illegal, *ERRMSG will be set to a warning
  89      string (the operand will be inserted in any case).  If the
  90      operand value is legal, *ERRMSG will be unchanged (most operands
  91      can accept any value).  */
  92
  93   unsigned long (*insert)
  94     (unsigned long instruction, long op, const char **errmsg);
  95
  96   /* Extraction function.  This is used by the disassembler.  To
  97      extract this operand type from an instruction, check this field.
  98
  99      If it is NULL, compute
 100          op = ((i) >> o->shift) & ((1 << o->bits) - 1);
 101          if ((o->flags & TIC80_OPERAND_SIGNED) != 0
 102              && (op & (1 << (o->bits - 1))) != 0)
 103            op -= 1 << o->bits;
 104      (i is the instruction, o is a pointer to this structure, and op
 105      is the result; this assumes twos complement arithmetic).
 106
 107      If this field is not NULL, then simply call it with the
 108      instruction value.  It will return the value of the operand.  If
 109      the INVALID argument is not NULL, *INVALID will be set to
 110      non-zero if this operand type can not actually be extracted from
 111      this operand (i.e., the instruction does not match).  If the
 112      operand is valid, *INVALID will not be changed.  */
 113
 114   long (*extract) (unsigned long instruction, int *invalid);
 115
 116   /* One bit syntax flags.  */
 117
 118   unsigned long flags;
 119 };
 120
 121 /* Elements in the table are retrieved by indexing with values from
 122    the operands field of the tic80_opcodes table.  */
 123
 124 extern const struct tic80_operand tic80_operands[];
 125
 126 \f
 127 /* Values defined for the flags field of a struct tic80_operand.
 128
 129    Note that flags for all predefined symbols, such as the general purpose
 130    registers (ex: r10), control registers (ex: FPST), condition codes (ex:
 131    eq0.b), bit numbers (ex: gt.b), etc are large enough that they can be
 132    or'd into an int where the lower bits contain the actual numeric value
 133    that correponds to this predefined symbol.  This way a single int can
 134    contain both the value of the symbol and it's type.
 135  */
 136
 137 /* This operand must be an even register number.  Floating point numbers
 138    for example are stored in even/odd register pairs. */
 139
 140 #define TIC80_OPERAND_EVEN      (1 << 0)
 141
 142 /* This operand must be an odd register number and must be one greater than
 143    the register number of the previous operand.  I.E. the second register in
 144    an even/odd register pair. */
 145
 146 #define TIC80_OPERAND_ODD       (1 << 1)
 147
 148 /* This operand takes signed values.  */
 149
 150 #define TIC80_OPERAND_SIGNED    (1 << 2)
 151
 152 /* This operand may be either a predefined constant name or a numeric value.
 153    An example would be a condition code like "eq0.b" which has the numeric
 154    value 0x2. */
 155
 156 #define TIC80_OPERAND_NUM       (1 << 3)
 157
 158 /* This operand should be wrapped in parentheses rather than separated
 159    from the previous one by a comma.  This is used for various
 160    instructions, like the load and store instructions, which want
 161    their operands to look like "displacement(reg)" */
 162
 163 #define TIC80_OPERAND_PARENS    (1 << 4)
 164
 165 /* This operand is a PC relative branch offset.  The disassembler prints
 166    these symbolically if possible.  Note that the offsets are taken as word
 167    offsets. */
 168
 169 #define TIC80_OPERAND_PCREL     (1 << 5)
 170
 171 /* This flag is a hint to the disassembler for using hex as the prefered
 172    printing format, even for small positive or negative immediate values.
 173    Normally values in the range -999 to 999 are printed as signed decimal
 174    values and other values are printed in hex. */
 175
 176 #define TIC80_OPERAND_BITFIELD  (1 << 6)
 177
 178 /* This operand may have a ":m" modifier specified by bit 17 in a short
 179    immediate form instruction. */
 180
 181 #define TIC80_OPERAND_M_SI      (1 << 7)
 182
 183 /* This operand may have a ":m" modifier specified by bit 15 in a long
 184    immediate or register form instruction. */
 185
 186 #define TIC80_OPERAND_M_LI      (1 << 8)
 187
 188 /* This operand may have a ":s" modifier specified in bit 11 in a long
 189    immediate or register form instruction. */
 190
 191 #define TIC80_OPERAND_SCALED    (1 << 9)
 192
 193 /* This operand is a floating point value */
 194
 195 #define TIC80_OPERAND_FLOAT     (1 << 10)
 196
 197 /* This operand is an byte offset from a base relocation. The lower
 198  two bits of the final relocated address are ignored when the value is
 199  written to the program counter. */
 200
 201 #define TIC80_OPERAND_BASEREL   (1 << 11)
 202
 203 /* This operand is an "endmask" field for a shift instruction.
 204    It is treated special in that it can have values of 0-32,
 205    where 0 and 32 result in the same instruction.  The assembler
 206    must be able to accept both endmask values.  This disassembler
 207    has no way of knowing from the instruction which value was
 208    given at assembly time, so it just uses '0'. */
 209
 210 #define TIC80_OPERAND_ENDMASK   (1 << 12)
 211
 212 /* This operand is one of the 32 general purpose registers.
 213    The disassembler prints these with a leading 'r'. */
 214
 215 #define TIC80_OPERAND_GPR       (1 << 27)
 216
 217 /* This operand is a floating point accumulator register.
 218    The disassembler prints these with a leading 'a'. */
 219
 220 #define TIC80_OPERAND_FPA       ( 1 << 28)
 221
 222 /* This operand is a control register number, either numeric or
 223    symbolic (like "EIF", "EPC", etc).
 224    The disassembler prints these symbolically. */
 225
 226 #define TIC80_OPERAND_CR        (1 << 29)
 227
 228 /* This operand is a condition code, either numeric or
 229    symbolic (like "eq0.b", "ne0.w", etc).
 230    The disassembler prints these symbolically. */
 231
 232 #define TIC80_OPERAND_CC        (1 << 30)
 233
 234 /* This operand is a bit number, either numeric or
 235    symbolic (like "eq.b", "or.f", etc).
 236    The disassembler prints these symbolically.
 237    Note that they appear in the instruction in 1's complement relative
 238    to the values given in the manual. */
 239
 240 #define TIC80_OPERAND_BITNUM    (1 << 31)
 241
 242 /* This mask is used to strip operand bits from an int that contains
 243    both operand bits and a numeric value in the lsbs. */
 244
 245 #define TIC80_OPERAND_MASK      (TIC80_OPERAND_GPR | TIC80_OPERAND_FPA | TIC80_OPERAND_CR | TIC80_OPERAND_CC | TIC80_OPERAND_BITNUM)
 246
 247 \f
 248 /* Flag bits for the struct tic80_opcode flags field. */
 249
 250 #define TIC80_VECTOR            01      /* Is a vector instruction */
 251 #define TIC80_NO_R0_DEST        02      /* Register r0 cannot be a destination register */
 252
 253 \f
 254 /* The opcodes library contains a table that allows translation from predefined
 255    symbol names to numeric values, and vice versa. */
 256
 257 /* Structure to hold information about predefined symbols.  */
 258
 259 struct predefined_symbol
 260 {
 261   char *name;           /* name to recognize */
 262   int value;
 263 };
 264
 265 #define PDS_NAME(pdsp) ((pdsp) -> name)
 266 #define PDS_VALUE(pdsp) ((pdsp) -> value)
 267
 268 /* Translation array.  */
 269 extern const struct predefined_symbol tic80_predefined_symbols[];
 270 /* How many members in the array.  */
 271 extern const int tic80_num_predefined_symbols;
 272
 273 /* Translate value to symbolic name.  */
 274 const char *tic80_value_to_symbol (int val, int class);
 275
 276 /* Translate symbolic name to value.  */
 277 int tic80_symbol_to_value (char *name, int class);
 278
 279 const struct predefined_symbol *tic80_next_predefined_symbol
 280   (const struct predefined_symbol *);
 281
 282 #endif /* TIC80_H */