opcodes/m32r-dis.c

   1 /* Disassembler interface for targets using CGEN. -*- C -*-
   2    CGEN: Cpu tools GENerator
   3
   4 THIS FILE IS MACHINE GENERATED WITH CGEN.
   5 - the resultant file is machine generated, cgen-dis.in isn't
   6
   7 Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002
   8 Free Software Foundation, Inc.
   9
  10 This file is part of the GNU Binutils and GDB, the GNU debugger.
  11
  12 This program is free software; you can redistribute it and/or modify
  13 it under the terms of the GNU General Public License as published by
  14 the Free Software Foundation; either version 2, or (at your option)
  15 any later version.
  16
  17 This program is distributed in the hope that it will be useful,
  18 but WITHOUT ANY WARRANTY; without even the implied warranty of
  19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20 GNU General Public License for more details.
  21
  22 You should have received a copy of the GNU General Public License
  23 along with this program; if not, write to the Free Software Foundation, Inc.,
  24 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  25
  26 /* ??? Eventually more and more of this stuff can go to cpu-independent files.
  27    Keep that in mind.  */
  28
  29 #include "sysdep.h"
  30 #include <stdio.h>
  31 #include "ansidecl.h"
  32 #include "dis-asm.h"
  33 #include "bfd.h"
  34 #include "symcat.h"
  35 #include "libiberty.h"
  36 #include "m32r-desc.h"
  37 #include "m32r-opc.h"
  38 #include "opintl.h"
  39
  40 /* Default text to print if an instruction isn't recognized.  */
  41 #define UNKNOWN_INSN_MSG _("*unknown*")
  42
  43 static void print_normal
  44      PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned int, bfd_vma, int));
  45 static void print_address
  46      PARAMS ((CGEN_CPU_DESC, PTR, bfd_vma, unsigned int, bfd_vma, int));
  47 static void print_keyword
  48      PARAMS ((CGEN_CPU_DESC, PTR, CGEN_KEYWORD *, long, unsigned int));
  49 static void print_insn_normal
  50      PARAMS ((CGEN_CPU_DESC, PTR, const CGEN_INSN *, CGEN_FIELDS *,
  51               bfd_vma, int));
  52 static int print_insn
  53      PARAMS ((CGEN_CPU_DESC, bfd_vma,  disassemble_info *, char *, unsigned));
  54 static int default_print_insn
  55      PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *));
  56 static int read_insn
  57      PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, int,
  58               CGEN_EXTRACT_INFO *, unsigned long *));
  59 \f
  60 /* -- disassembler routines inserted here */
  61
  62 /* -- dis.c */
  63 static void print_hash PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int));
  64 static int my_print_insn PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *));
  65
  66 /* Immediate values are prefixed with '#'.  */
  67
  68 #define CGEN_PRINT_NORMAL(cd, info, value, attrs, pc, length)   \
  69   do                                                            \
  70     {                                                           \
  71       if (CGEN_BOOL_ATTR ((attrs), CGEN_OPERAND_HASH_PREFIX))   \
  72         (*info->fprintf_func) (info->stream, "#");              \
  73     }                                                           \
  74   while (0)
  75
  76 /* Handle '#' prefixes as operands.  */
  77
  78 static void
  79 print_hash (cd, dis_info, value, attrs, pc, length)
  80      CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
  81      PTR dis_info;
  82      long value ATTRIBUTE_UNUSED;
  83      unsigned int attrs ATTRIBUTE_UNUSED;
  84      bfd_vma pc ATTRIBUTE_UNUSED;
  85      int length ATTRIBUTE_UNUSED;
  86 {
  87   disassemble_info *info = (disassemble_info *) dis_info;
  88   (*info->fprintf_func) (info->stream, "#");
  89 }
  90
  91 #undef  CGEN_PRINT_INSN
  92 #define CGEN_PRINT_INSN my_print_insn
  93
  94 static int
  95 my_print_insn (cd, pc, info)
  96      CGEN_CPU_DESC cd;
  97      bfd_vma pc;
  98      disassemble_info *info;
  99 {
 100   char buffer[CGEN_MAX_INSN_SIZE];
 101   char *buf = buffer;
 102   int status;
 103   int buflen = (pc & 3) == 0 ? 4 : 2;
 104
 105   /* Read the base part of the insn.  */
 106
 107   status = (*info->read_memory_func) (pc, buf, buflen, info);
 108   if (status != 0)
 109     {
 110       (*info->memory_error_func) (status, pc, info);
 111       return -1;
 112     }
 113
 114   /* 32 bit insn?  */
 115   if ((pc & 3) == 0 && (buf[0] & 0x80) != 0)
 116     return print_insn (cd, pc, info, buf, buflen);
 117
 118   /* Print the first insn.  */
 119   if ((pc & 3) == 0)
 120     {
 121       if (print_insn (cd, pc, info, buf, 2) == 0)
 122         (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
 123       buf += 2;
 124     }
 125
 126   if (buf[0] & 0x80)
 127     {
 128       /* Parallel.  */
 129       (*info->fprintf_func) (info->stream, " || ");
 130       buf[0] &= 0x7f;
 131     }
 132   else
 133     (*info->fprintf_func) (info->stream, " -> ");
 134
 135   /* The "& 3" is to pass a consistent address.
 136      Parallel insns arguably both begin on the word boundary.
 137      Also, branch insns are calculated relative to the word boundary.  */
 138   if (print_insn (cd, pc & ~ (bfd_vma) 3, info, buf, 2) == 0)
 139     (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
 140
 141   return (pc & 3) ? 2 : 4;
 142 }
 143
 144 /* -- */
 145
 146 void m32r_cgen_print_operand
 147   PARAMS ((CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *,
 148            void const *, bfd_vma, int));
 149
 150 /* Main entry point for printing operands.
 151    XINFO is a `void *' and not a `disassemble_info *' to not put a requirement
 152    of dis-asm.h on cgen.h.
 153
 154    This function is basically just a big switch statement.  Earlier versions
 155    used tables to look up the function to use, but
 156    - if the table contains both assembler and disassembler functions then
 157      the disassembler contains much of the assembler and vice-versa,
 158    - there's a lot of inlining possibilities as things grow,
 159    - using a switch statement avoids the function call overhead.
 160
 161    This function could be moved into `print_insn_normal', but keeping it
 162    separate makes clear the interface between `print_insn_normal' and each of
 163    the handlers.  */
 164
 165 void
 166 m32r_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length)
 167      CGEN_CPU_DESC cd;
 168      int opindex;
 169      PTR xinfo;
 170      CGEN_FIELDS *fields;
 171      void const *attrs ATTRIBUTE_UNUSED;
 172      bfd_vma pc;
 173      int length;
 174 {
 175  disassemble_info *info = (disassemble_info *) xinfo;
 176
 177   switch (opindex)
 178     {
 179     case M32R_OPERAND_ACC :
 180       print_keyword (cd, info, & m32r_cgen_opval_h_accums, fields->f_acc, 0);
 181       break;
 182     case M32R_OPERAND_ACCD :
 183       print_keyword (cd, info, & m32r_cgen_opval_h_accums, fields->f_accd, 0);
 184       break;
 185     case M32R_OPERAND_ACCS :
 186       print_keyword (cd, info, & m32r_cgen_opval_h_accums, fields->f_accs, 0);
 187       break;
 188     case M32R_OPERAND_DCR :
 189       print_keyword (cd, info, & m32r_cgen_opval_cr_names, fields->f_r1, 0);
 190       break;
 191     case M32R_OPERAND_DISP16 :
 192       print_address (cd, info, fields->f_disp16, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
 193       break;
 194     case M32R_OPERAND_DISP24 :
 195       print_address (cd, info, fields->f_disp24, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
 196       break;
 197     case M32R_OPERAND_DISP8 :
 198       print_address (cd, info, fields->f_disp8, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
 199       break;
 200     case M32R_OPERAND_DR :
 201       print_keyword (cd, info, & m32r_cgen_opval_gr_names, fields->f_r1, 0);
 202       break;
 203     case M32R_OPERAND_HASH :
 204       print_hash (cd, info, 0, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
 205       break;
 206     case M32R_OPERAND_HI16 :
 207       print_normal (cd, info, fields->f_hi16, 0|(1<<CGEN_OPERAND_SIGN_OPT), pc, length);
 208       break;
 209     case M32R_OPERAND_IMM1 :
 210       print_normal (cd, info, fields->f_imm1, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
 211       break;
 212     case M32R_OPERAND_SCR :
 213       print_keyword (cd, info, & m32r_cgen_opval_cr_names, fields->f_r2, 0);
 214       break;
 215     case M32R_OPERAND_SIMM16 :
 216       print_normal (cd, info, fields->f_simm16, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
 217       break;
 218     case M32R_OPERAND_SIMM8 :
 219       print_normal (cd, info, fields->f_simm8, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
 220       break;
 221     case M32R_OPERAND_SLO16 :
 222       print_normal (cd, info, fields->f_simm16, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
 223       break;
 224     case M32R_OPERAND_SR :
 225       print_keyword (cd, info, & m32r_cgen_opval_gr_names, fields->f_r2, 0);
 226       break;
 227     case M32R_OPERAND_SRC1 :
 228       print_keyword (cd, info, & m32r_cgen_opval_gr_names, fields->f_r1, 0);
 229       break;
 230     case M32R_OPERAND_SRC2 :
 231       print_keyword (cd, info, & m32r_cgen_opval_gr_names, fields->f_r2, 0);
 232       break;
 233     case M32R_OPERAND_UIMM16 :
 234       print_normal (cd, info, fields->f_uimm16, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
 235       break;
 236     case M32R_OPERAND_UIMM24 :
 237       print_address (cd, info, fields->f_uimm24, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR), pc, length);
 238       break;
 239     case M32R_OPERAND_UIMM4 :
 240       print_normal (cd, info, fields->f_uimm4, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
 241       break;
 242     case M32R_OPERAND_UIMM5 :
 243       print_normal (cd, info, fields->f_uimm5, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
 244       break;
 245     case M32R_OPERAND_ULO16 :
 246       print_normal (cd, info, fields->f_uimm16, 0, pc, length);
 247       break;
 248
 249     default :
 250       /* xgettext:c-format */
 251       fprintf (stderr, _("Unrecognized field %d while printing insn.\n"),
 252                opindex);
 253     abort ();
 254   }
 255 }
 256
 257 cgen_print_fn * const m32r_cgen_print_handlers[] =
 258 {
 259   print_insn_normal,
 260 };
 261
 262
 263 void
 264 m32r_cgen_init_dis (cd)
 265      CGEN_CPU_DESC cd;
 266 {
 267   m32r_cgen_init_opcode_table (cd);
 268   m32r_cgen_init_ibld_table (cd);
 269   cd->print_handlers = & m32r_cgen_print_handlers[0];
 270   cd->print_operand = m32r_cgen_print_operand;
 271 }
 272
 273 \f
 274 /* Default print handler.  */
 275
 276 static void
 277 print_normal (cd, dis_info, value, attrs, pc, length)
 278      CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
 279      PTR dis_info;
 280      long value;
 281      unsigned int attrs;
 282      bfd_vma pc ATTRIBUTE_UNUSED;
 283      int length ATTRIBUTE_UNUSED;
 284 {
 285   disassemble_info *info = (disassemble_info *) dis_info;
 286
 287 #ifdef CGEN_PRINT_NORMAL
 288   CGEN_PRINT_NORMAL (cd, info, value, attrs, pc, length);
 289 #endif
 290
 291   /* Print the operand as directed by the attributes.  */
 292   if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
 293     ; /* nothing to do */
 294   else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
 295     (*info->fprintf_func) (info->stream, "%ld", value);
 296   else
 297     (*info->fprintf_func) (info->stream, "0x%lx", value);
 298 }
 299
 300 /* Default address handler.  */
 301
 302 static void
 303 print_address (cd, dis_info, value, attrs, pc, length)
 304      CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
 305      PTR dis_info;
 306      bfd_vma value;
 307      unsigned int attrs;
 308      bfd_vma pc ATTRIBUTE_UNUSED;
 309      int length ATTRIBUTE_UNUSED;
 310 {
 311   disassemble_info *info = (disassemble_info *) dis_info;
 312
 313 #ifdef CGEN_PRINT_ADDRESS
 314   CGEN_PRINT_ADDRESS (cd, info, value, attrs, pc, length);
 315 #endif
 316
 317   /* Print the operand as directed by the attributes.  */
 318   if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
 319     ; /* nothing to do */
 320   else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR))
 321     (*info->print_address_func) (value, info);
 322   else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR))
 323     (*info->print_address_func) (value, info);
 324   else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
 325     (*info->fprintf_func) (info->stream, "%ld", (long) value);
 326   else
 327     (*info->fprintf_func) (info->stream, "0x%lx", (long) value);
 328 }
 329
 330 /* Keyword print handler.  */
 331
 332 static void
 333 print_keyword (cd, dis_info, keyword_table, value, attrs)
 334      CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
 335      PTR dis_info;
 336      CGEN_KEYWORD *keyword_table;
 337      long value;
 338      unsigned int attrs ATTRIBUTE_UNUSED;
 339 {
 340   disassemble_info *info = (disassemble_info *) dis_info;
 341   const CGEN_KEYWORD_ENTRY *ke;
 342
 343   ke = cgen_keyword_lookup_value (keyword_table, value);
 344   if (ke != NULL)
 345     (*info->fprintf_func) (info->stream, "%s", ke->name);
 346   else
 347     (*info->fprintf_func) (info->stream, "???");
 348 }
 349 \f
 350 /* Default insn printer.
 351
 352    DIS_INFO is defined as `PTR' so the disassembler needn't know anything
 353    about disassemble_info.  */
 354
 355 static void
 356 print_insn_normal (cd, dis_info, insn, fields, pc, length)
 357      CGEN_CPU_DESC cd;
 358      PTR dis_info;
 359      const CGEN_INSN *insn;
 360      CGEN_FIELDS *fields;
 361      bfd_vma pc;
 362      int length;
 363 {
 364   const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
 365   disassemble_info *info = (disassemble_info *) dis_info;
 366   const CGEN_SYNTAX_CHAR_TYPE *syn;
 367
 368   CGEN_INIT_PRINT (cd);
 369
 370   for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
 371     {
 372       if (CGEN_SYNTAX_MNEMONIC_P (*syn))
 373         {
 374           (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn));
 375           continue;
 376         }
 377       if (CGEN_SYNTAX_CHAR_P (*syn))
 378         {
 379           (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn));
 380           continue;
 381         }
 382
 383       /* We have an operand.  */
 384       m32r_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info,
 385                                  fields, CGEN_INSN_ATTRS (insn), pc, length);
 386     }
 387 }
 388 \f
 389 /* Subroutine of print_insn. Reads an insn into the given buffers and updates
 390    the extract info.
 391    Returns 0 if all is well, non-zero otherwise.  */
 392
 393 static int
 394 read_insn (cd, pc, info, buf, buflen, ex_info, insn_value)
 395      CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
 396      bfd_vma pc;
 397      disassemble_info *info;
 398      char *buf;
 399      int buflen;
 400      CGEN_EXTRACT_INFO *ex_info;
 401      unsigned long *insn_value;
 402 {
 403   int status = (*info->read_memory_func) (pc, buf, buflen, info);
 404   if (status != 0)
 405     {
 406       (*info->memory_error_func) (status, pc, info);
 407       return -1;
 408     }
 409
 410   ex_info->dis_info = info;
 411   ex_info->valid = (1 << buflen) - 1;
 412   ex_info->insn_bytes = buf;
 413
 414   *insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG);
 415   return 0;
 416 }
 417
 418 /* Utility to print an insn.
 419    BUF is the base part of the insn, target byte order, BUFLEN bytes long.
 420    The result is the size of the insn in bytes or zero for an unknown insn
 421    or -1 if an error occurs fetching data (memory_error_func will have
 422    been called).  */
 423
 424 static int
 425 print_insn (cd, pc, info, buf, buflen)
 426      CGEN_CPU_DESC cd;
 427      bfd_vma pc;
 428      disassemble_info *info;
 429      char *buf;
 430      unsigned int buflen;
 431 {
 432   CGEN_INSN_INT insn_value;
 433   const CGEN_INSN_LIST *insn_list;
 434   CGEN_EXTRACT_INFO ex_info;
 435   int basesize;
 436
 437   /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */
 438   basesize = cd->base_insn_bitsize < buflen * 8 ?
 439                                      cd->base_insn_bitsize : buflen * 8;
 440   insn_value = cgen_get_insn_value (cd, buf, basesize);
 441
 442
 443   /* Fill in ex_info fields like read_insn would.  Don't actually call
 444      read_insn, since the incoming buffer is already read (and possibly
 445      modified a la m32r).  */
 446   ex_info.valid = (1 << buflen) - 1;
 447   ex_info.dis_info = info;
 448   ex_info.insn_bytes = buf;
 449
 450   /* The instructions are stored in hash lists.
 451      Pick the first one and keep trying until we find the right one.  */
 452
 453   insn_list = CGEN_DIS_LOOKUP_INSN (cd, buf, insn_value);
 454   while (insn_list != NULL)
 455     {
 456       const CGEN_INSN *insn = insn_list->insn;
 457       CGEN_FIELDS fields;
 458       int length;
 459       unsigned long insn_value_cropped;
 460
 461 #ifdef CGEN_VALIDATE_INSN_SUPPORTED
 462       /* Not needed as insn shouldn't be in hash lists if not supported.  */
 463       /* Supported by this cpu?  */
 464       if (! m32r_cgen_insn_supported (cd, insn))
 465         {
 466           insn_list = CGEN_DIS_NEXT_INSN (insn_list);
 467           continue;
 468         }
 469 #endif
 470
 471       /* Basic bit mask must be correct.  */
 472       /* ??? May wish to allow target to defer this check until the extract
 473          handler.  */
 474
 475       /* Base size may exceed this instruction's size.  Extract the
 476          relevant part from the buffer. */
 477       if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen &&
 478           (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
 479         insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
 480                                            info->endian == BFD_ENDIAN_BIG);
 481       else
 482         insn_value_cropped = insn_value;
 483
 484       if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn))
 485           == CGEN_INSN_BASE_VALUE (insn))
 486         {
 487           /* Printing is handled in two passes.  The first pass parses the
 488              machine insn and extracts the fields.  The second pass prints
 489              them.  */
 490
 491           /* Make sure the entire insn is loaded into insn_value, if it
 492              can fit.  */
 493           if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) &&
 494               (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
 495             {
 496               unsigned long full_insn_value;
 497               int rc = read_insn (cd, pc, info, buf,
 498                                   CGEN_INSN_BITSIZE (insn) / 8,
 499                                   & ex_info, & full_insn_value);
 500               if (rc != 0)
 501                 return rc;
 502               length = CGEN_EXTRACT_FN (cd, insn)
 503                 (cd, insn, &ex_info, full_insn_value, &fields, pc);
 504             }
 505           else
 506             length = CGEN_EXTRACT_FN (cd, insn)
 507               (cd, insn, &ex_info, insn_value_cropped, &fields, pc);
 508
 509           /* length < 0 -> error */
 510           if (length < 0)
 511             return length;
 512           if (length > 0)
 513             {
 514               CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length);
 515               /* length is in bits, result is in bytes */
 516               return length / 8;
 517             }
 518         }
 519
 520       insn_list = CGEN_DIS_NEXT_INSN (insn_list);
 521     }
 522
 523   return 0;
 524 }
 525
 526 /* Default value for CGEN_PRINT_INSN.
 527    The result is the size of the insn in bytes or zero for an unknown insn
 528    or -1 if an error occured fetching bytes.  */
 529
 530 #ifndef CGEN_PRINT_INSN
 531 #define CGEN_PRINT_INSN default_print_insn
 532 #endif
 533
 534 static int
 535 default_print_insn (cd, pc, info)
 536      CGEN_CPU_DESC cd;
 537      bfd_vma pc;
 538      disassemble_info *info;
 539 {
 540   char buf[CGEN_MAX_INSN_SIZE];
 541   int buflen;
 542   int status;
 543
 544   /* Attempt to read the base part of the insn.  */
 545   buflen = cd->base_insn_bitsize / 8;
 546   status = (*info->read_memory_func) (pc, buf, buflen, info);
 547
 548   /* Try again with the minimum part, if min < base.  */
 549   if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize))
 550     {
 551       buflen = cd->min_insn_bitsize / 8;
 552       status = (*info->read_memory_func) (pc, buf, buflen, info);
 553     }
 554
 555   if (status != 0)
 556     {
 557       (*info->memory_error_func) (status, pc, info);
 558       return -1;
 559     }
 560
 561   return print_insn (cd, pc, info, buf, buflen);
 562 }
 563
 564 /* Main entry point.
 565    Print one instruction from PC on INFO->STREAM.
 566    Return the size of the instruction (in bytes).  */
 567
 568 typedef struct cpu_desc_list {
 569   struct cpu_desc_list *next;
 570   int isa;
 571   int mach;
 572   int endian;
 573   CGEN_CPU_DESC cd;
 574 } cpu_desc_list;
 575
 576 int
 577 print_insn_m32r (pc, info)
 578      bfd_vma pc;
 579      disassemble_info *info;
 580 {
 581   static cpu_desc_list *cd_list = 0;
 582   cpu_desc_list *cl = 0;
 583   static CGEN_CPU_DESC cd = 0;
 584   static int prev_isa;
 585   static int prev_mach;
 586   static int prev_endian;
 587   int length;
 588   int isa,mach;
 589   int endian = (info->endian == BFD_ENDIAN_BIG
 590                 ? CGEN_ENDIAN_BIG
 591                 : CGEN_ENDIAN_LITTLE);
 592   enum bfd_architecture arch;
 593
 594   /* ??? gdb will set mach but leave the architecture as "unknown" */
 595 #ifndef CGEN_BFD_ARCH
 596 #define CGEN_BFD_ARCH bfd_arch_m32r
 597 #endif
 598   arch = info->arch;
 599   if (arch == bfd_arch_unknown)
 600     arch = CGEN_BFD_ARCH;
 601
 602   /* There's no standard way to compute the machine or isa number
 603      so we leave it to the target.  */
 604 #ifdef CGEN_COMPUTE_MACH
 605   mach = CGEN_COMPUTE_MACH (info);
 606 #else
 607   mach = info->mach;
 608 #endif
 609
 610 #ifdef CGEN_COMPUTE_ISA
 611   isa = CGEN_COMPUTE_ISA (info);
 612 #else
 613   isa = info->insn_sets;
 614 #endif
 615
 616   /* If we've switched cpu's, try to find a handle we've used before */
 617   if (cd
 618       && (isa != prev_isa
 619           || mach != prev_mach
 620           || endian != prev_endian))
 621     {
 622       cd = 0;
 623       for (cl = cd_list; cl; cl = cl->next)
 624         {
 625           if (cl->isa == isa &&
 626               cl->mach == mach &&
 627               cl->endian == endian)
 628             {
 629               cd = cl->cd;
 630               break;
 631             }
 632         }
 633     }
 634
 635   /* If we haven't initialized yet, initialize the opcode table.  */
 636   if (! cd)
 637     {
 638       const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach);
 639       const char *mach_name;
 640
 641       if (!arch_type)
 642         abort ();
 643       mach_name = arch_type->printable_name;
 644
 645       prev_isa = isa;
 646       prev_mach = mach;
 647       prev_endian = endian;
 648       cd = m32r_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa,
 649                                  CGEN_CPU_OPEN_BFDMACH, mach_name,
 650                                  CGEN_CPU_OPEN_ENDIAN, prev_endian,
 651                                  CGEN_CPU_OPEN_END);
 652       if (!cd)
 653         abort ();
 654
 655       /* save this away for future reference */
 656       cl = xmalloc (sizeof (struct cpu_desc_list));
 657       cl->cd = cd;
 658       cl->isa = isa;
 659       cl->mach = mach;
 660       cl->endian = endian;
 661       cl->next = cd_list;
 662       cd_list = cl;
 663
 664       m32r_cgen_init_dis (cd);
 665     }
 666
 667   /* We try to have as much common code as possible.
 668      But at this point some targets need to take over.  */
 669   /* ??? Some targets may need a hook elsewhere.  Try to avoid this,
 670      but if not possible try to move this hook elsewhere rather than
 671      have two hooks.  */
 672   length = CGEN_PRINT_INSN (cd, pc, info);
 673   if (length > 0)
 674     return length;
 675   if (length < 0)
 676     return -1;
 677
 678   (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
 679   return cd->default_insn_bitsize / 8;
 680 }