1 /* mips-opc.c -- MIPS opcode list.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002
3 Free Software Foundation, Inc.
4 Contributed by Ralph Campbell and OSF
5 Commented and modified by Ian Lance Taylor, Cygnus Support
6 Extended for MIPS32 support by Anders Norlander, and by SiByte, Inc.
7 MIPS-3D support added by Broadcom Corporation (SiByte).
9 This file is part of GDB, GAS, and the GNU binutils.
11 GDB, GAS, and the GNU binutils are free software; you can redistribute
12 them and/or modify them under the terms of the GNU General Public
13 License as published by the Free Software Foundation; either version
14 1, or (at your option) any later version.
16 GDB, GAS, and the GNU binutils are distributed in the hope that they
17 will be useful, but WITHOUT ANY WARRANTY; without even the implied
18 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
19 the GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with this file; see the file COPYING. If not, write to the Free
23 Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
27 #include "opcode/mips.h"
29 /* Short hand so the lines aren't too long. */
31 #define LDD INSN_LOAD_MEMORY_DELAY
32 #define LCD INSN_LOAD_COPROC_DELAY
33 #define UBD INSN_UNCOND_BRANCH_DELAY
34 #define CBD INSN_COND_BRANCH_DELAY
35 #define COD INSN_COPROC_MOVE_DELAY
36 #define CLD INSN_COPROC_MEMORY_DELAY
37 #define CBL INSN_COND_BRANCH_LIKELY
38 #define TRAP INSN_TRAP
39 #define SM INSN_STORE_MEMORY
41 #define WR_d INSN_WRITE_GPR_D
42 #define WR_t INSN_WRITE_GPR_T
43 #define WR_31 INSN_WRITE_GPR_31
44 #define WR_D INSN_WRITE_FPR_D
45 #define WR_T INSN_WRITE_FPR_T
46 #define WR_S INSN_WRITE_FPR_S
47 #define RD_s INSN_READ_GPR_S
48 #define RD_b INSN_READ_GPR_S
49 #define RD_t INSN_READ_GPR_T
50 #define RD_S INSN_READ_FPR_S
51 #define RD_T INSN_READ_FPR_T
52 #define RD_R INSN_READ_FPR_R
53 #define WR_CC INSN_WRITE_COND_CODE
54 #define RD_CC INSN_READ_COND_CODE
55 #define RD_C0 INSN_COP
56 #define RD_C1 INSN_COP
57 #define RD_C2 INSN_COP
58 #define RD_C3 INSN_COP
59 #define WR_C0 INSN_COP
60 #define WR_C1 INSN_COP
61 #define WR_C2 INSN_COP
62 #define WR_C3 INSN_COP
64 #define WR_HI INSN_WRITE_HI
65 #define RD_HI INSN_READ_HI
66 #define MOD_HI WR_HI|RD_HI
68 #define WR_LO INSN_WRITE_LO
69 #define RD_LO INSN_READ_LO
70 #define MOD_LO WR_LO|RD_LO
72 #define WR_HILO WR_HI|WR_LO
73 #define RD_HILO RD_HI|RD_LO
74 #define MOD_HILO WR_HILO|RD_HILO
76 #define IS_M INSN_MULT
83 #define I32 INSN_ISA32
84 #define I64 INSN_ISA64
86 /* MIPS64 MIPS-3D ASE support. */
87 #define M3D INSN_MIPS3D
105 /* The order of overloaded instructions matters. Label arguments and
106 register arguments look the same. Instructions that can have either
107 for arguments must apear in the correct order in this table for the
108 assembler to pick the right one. In other words, entries with
109 immediate operands must apear after the same instruction with
112 Because of the lookup algorithm used, entries with the same opcode
113 name must be contiguous.
115 Many instructions are short hand for other instructions (i.e., The
116 jal <register> instruction is short for jalr <register>). */
118 const struct mips_opcode mips_builtin_opcodes
[] =
120 /* These instructions appear first so that the disassembler will find
121 them first. The assemblers uses a hash table based on the
122 instruction name anyhow. */
123 /* name, args, match, mask, pinfo, membership */
124 {"pref", "k,o(b)", 0xcc000000, 0xfc000000, RD_b
, I4
|I32
|G3
},
125 {"prefx", "h,t(b)", 0x4c00000f, 0xfc0007ff, RD_b
|RD_t
, I4
},
126 {"nop", "", 0x00000000, 0xffffffff, 0, I1
},
127 {"ssnop", "", 0x00000040, 0xffffffff, 0, I32
},
128 {"li", "t,j", 0x24000000, 0xffe00000, WR_t
, I1
}, /* addiu */
129 {"li", "t,i", 0x34000000, 0xffe00000, WR_t
, I1
}, /* ori */
130 {"li", "t,I", 0, (int) M_LI
, INSN_MACRO
, I1
},
131 {"move", "d,s", 0, (int) M_MOVE
, INSN_MACRO
, I1
},
132 {"move", "d,s", 0x0000002d, 0xfc1f07ff, WR_d
|RD_s
, I3
},/* daddu */
133 {"move", "d,s", 0x00000021, 0xfc1f07ff, WR_d
|RD_s
, I1
},/* addu */
134 {"move", "d,s", 0x00000025, 0xfc1f07ff, WR_d
|RD_s
, I1
},/* or */
135 {"b", "p", 0x10000000, 0xffff0000, UBD
, I1
},/* beq 0,0 */
136 {"b", "p", 0x04010000, 0xffff0000, UBD
, I1
},/* bgez 0 */
137 {"bal", "p", 0x04110000, 0xffff0000, UBD
|WR_31
, I1
},/* bgezal 0*/
139 {"abs", "d,v", 0, (int) M_ABS
, INSN_MACRO
, I1
},
140 {"abs.s", "D,V", 0x46000005, 0xffff003f, WR_D
|RD_S
|FP_S
, I1
},
141 {"abs.d", "D,V", 0x46200005, 0xffff003f, WR_D
|RD_S
|FP_D
, I1
},
142 {"abs.ps", "D,V", 0x46c00005, 0xffff003f, WR_D
|RD_S
|FP_D
, I5
},
143 {"add", "d,v,t", 0x00000020, 0xfc0007ff, WR_d
|RD_s
|RD_t
, I1
},
144 {"add", "t,r,I", 0, (int) M_ADD_I
, INSN_MACRO
, I1
},
145 {"add.s", "D,V,T", 0x46000000, 0xffe0003f, WR_D
|RD_S
|RD_T
|FP_S
, I1
},
146 {"add.d", "D,V,T", 0x46200000, 0xffe0003f, WR_D
|RD_S
|RD_T
|FP_D
, I1
},
147 {"add.ps", "D,V,T", 0x46c00000, 0xffe0003f, WR_D
|RD_S
|RD_T
|FP_D
, I5
},
148 {"addi", "t,r,j", 0x20000000, 0xfc000000, WR_t
|RD_s
, I1
},
149 {"addiu", "t,r,j", 0x24000000, 0xfc000000, WR_t
|RD_s
, I1
},
150 {"addr.ps", "D,S,T", 0x46c00018, 0xffe0003f, WR_D
|RD_S
|RD_T
|FP_D
, M3D
},
151 {"addu", "d,v,t", 0x00000021, 0xfc0007ff, WR_d
|RD_s
|RD_t
, I1
},
152 {"addu", "t,r,I", 0, (int) M_ADDU_I
, INSN_MACRO
, I1
},
153 {"alnv.ps", "D,V,T,s", 0x4c00001e, 0xfc00003f, WR_D
|RD_S
|RD_T
|FP_D
, I5
},
154 {"and", "d,v,t", 0x00000024, 0xfc0007ff, WR_d
|RD_s
|RD_t
, I1
},
155 {"and", "t,r,I", 0, (int) M_AND_I
, INSN_MACRO
, I1
},
156 {"andi", "t,r,i", 0x30000000, 0xfc000000, WR_t
|RD_s
, I1
},
157 /* b is at the top of the table. */
158 /* bal is at the top of the table. */
159 {"bc0f", "p", 0x41000000, 0xffff0000, CBD
|RD_CC
, I1
},
160 {"bc0fl", "p", 0x41020000, 0xffff0000, CBL
|RD_CC
, I2
|T3
},
161 {"bc0t", "p", 0x41010000, 0xffff0000, CBD
|RD_CC
, I1
},
162 {"bc0tl", "p", 0x41030000, 0xffff0000, CBL
|RD_CC
, I2
|T3
},
163 {"bc1any2f", "N,p", 0x45200000, 0xffe30000, CBD
|RD_CC
|FP_S
, M3D
},
164 {"bc1any2t", "N,p", 0x45210000, 0xffe30000, CBD
|RD_CC
|FP_S
, M3D
},
165 {"bc1any4f", "N,p", 0x45400000, 0xffe30000, CBD
|RD_CC
|FP_S
, M3D
},
166 {"bc1any4t", "N,p", 0x45410000, 0xffe30000, CBD
|RD_CC
|FP_S
, M3D
},
167 {"bc1f", "p", 0x45000000, 0xffff0000, CBD
|RD_CC
|FP_S
, I1
},
168 {"bc1f", "N,p", 0x45000000, 0xffe30000, CBD
|RD_CC
|FP_S
, I4
|I32
},
169 {"bc1fl", "p", 0x45020000, 0xffff0000, CBL
|RD_CC
|FP_S
, I2
|T3
},
170 {"bc1fl", "N,p", 0x45020000, 0xffe30000, CBL
|RD_CC
|FP_S
, I4
|I32
},
171 {"bc1t", "p", 0x45010000, 0xffff0000, CBD
|RD_CC
|FP_S
, I1
},
172 {"bc1t", "N,p", 0x45010000, 0xffe30000, CBD
|RD_CC
|FP_S
, I4
|I32
},
173 {"bc1tl", "p", 0x45030000, 0xffff0000, CBL
|RD_CC
|FP_S
, I2
|T3
},
174 {"bc1tl", "N,p", 0x45030000, 0xffe30000, CBL
|RD_CC
|FP_S
, I4
|I32
},
175 {"bc2f", "p", 0x49000000, 0xffff0000, CBD
|RD_CC
, I1
},
176 {"bc2fl", "p", 0x49020000, 0xffff0000, CBL
|RD_CC
, I2
|T3
},
177 {"bc2t", "p", 0x49010000, 0xffff0000, CBD
|RD_CC
, I1
},
178 {"bc2tl", "p", 0x49030000, 0xffff0000, CBL
|RD_CC
, I2
|T3
},
179 {"bc3f", "p", 0x4d000000, 0xffff0000, CBD
|RD_CC
, I1
},
180 {"bc3fl", "p", 0x4d020000, 0xffff0000, CBL
|RD_CC
, I2
|T3
},
181 {"bc3t", "p", 0x4d010000, 0xffff0000, CBD
|RD_CC
, I1
},
182 {"bc3tl", "p", 0x4d030000, 0xffff0000, CBL
|RD_CC
, I2
|T3
},
183 {"beqz", "s,p", 0x10000000, 0xfc1f0000, CBD
|RD_s
, I1
},
184 {"beqzl", "s,p", 0x50000000, 0xfc1f0000, CBL
|RD_s
, I2
|T3
},
185 {"beq", "s,t,p", 0x10000000, 0xfc000000, CBD
|RD_s
|RD_t
, I1
},
186 {"beq", "s,I,p", 0, (int) M_BEQ_I
, INSN_MACRO
, I1
},
187 {"beql", "s,t,p", 0x50000000, 0xfc000000, CBL
|RD_s
|RD_t
, I2
|T3
},
188 {"beql", "s,I,p", 0, (int) M_BEQL_I
, INSN_MACRO
, I2
|T3
},
189 {"bge", "s,t,p", 0, (int) M_BGE
, INSN_MACRO
, I1
},
190 {"bge", "s,I,p", 0, (int) M_BGE_I
, INSN_MACRO
, I1
},
191 {"bgel", "s,t,p", 0, (int) M_BGEL
, INSN_MACRO
, I2
|T3
},
192 {"bgel", "s,I,p", 0, (int) M_BGEL_I
, INSN_MACRO
, I2
|T3
},
193 {"bgeu", "s,t,p", 0, (int) M_BGEU
, INSN_MACRO
, I1
},
194 {"bgeu", "s,I,p", 0, (int) M_BGEU_I
, INSN_MACRO
, I1
},
195 {"bgeul", "s,t,p", 0, (int) M_BGEUL
, INSN_MACRO
, I2
|T3
},
196 {"bgeul", "s,I,p", 0, (int) M_BGEUL_I
, INSN_MACRO
, I2
|T3
},
197 {"bgez", "s,p", 0x04010000, 0xfc1f0000, CBD
|RD_s
, I1
},
198 {"bgezl", "s,p", 0x04030000, 0xfc1f0000, CBL
|RD_s
, I2
|T3
},
199 {"bgezal", "s,p", 0x04110000, 0xfc1f0000, CBD
|RD_s
|WR_31
, I1
},
200 {"bgezall", "s,p", 0x04130000, 0xfc1f0000, CBL
|RD_s
|WR_31
, I2
|T3
},
201 {"bgt", "s,t,p", 0, (int) M_BGT
, INSN_MACRO
, I1
},
202 {"bgt", "s,I,p", 0, (int) M_BGT_I
, INSN_MACRO
, I1
},
203 {"bgtl", "s,t,p", 0, (int) M_BGTL
, INSN_MACRO
, I2
|T3
},
204 {"bgtl", "s,I,p", 0, (int) M_BGTL_I
, INSN_MACRO
, I2
|T3
},
205 {"bgtu", "s,t,p", 0, (int) M_BGTU
, INSN_MACRO
, I1
},
206 {"bgtu", "s,I,p", 0, (int) M_BGTU_I
, INSN_MACRO
, I1
},
207 {"bgtul", "s,t,p", 0, (int) M_BGTUL
, INSN_MACRO
, I2
|T3
},
208 {"bgtul", "s,I,p", 0, (int) M_BGTUL_I
, INSN_MACRO
, I2
|T3
},
209 {"bgtz", "s,p", 0x1c000000, 0xfc1f0000, CBD
|RD_s
, I1
},
210 {"bgtzl", "s,p", 0x5c000000, 0xfc1f0000, CBL
|RD_s
, I2
|T3
},
211 {"ble", "s,t,p", 0, (int) M_BLE
, INSN_MACRO
, I1
},
212 {"ble", "s,I,p", 0, (int) M_BLE_I
, INSN_MACRO
, I1
},
213 {"blel", "s,t,p", 0, (int) M_BLEL
, INSN_MACRO
, I2
|T3
},
214 {"blel", "s,I,p", 0, (int) M_BLEL_I
, INSN_MACRO
, I2
|T3
},
215 {"bleu", "s,t,p", 0, (int) M_BLEU
, INSN_MACRO
, I1
},
216 {"bleu", "s,I,p", 0, (int) M_BLEU_I
, INSN_MACRO
, I1
},
217 {"bleul", "s,t,p", 0, (int) M_BLEUL
, INSN_MACRO
, I2
|T3
},
218 {"bleul", "s,I,p", 0, (int) M_BLEUL_I
, INSN_MACRO
, I2
|T3
},
219 {"blez", "s,p", 0x18000000, 0xfc1f0000, CBD
|RD_s
, I1
},
220 {"blezl", "s,p", 0x58000000, 0xfc1f0000, CBL
|RD_s
, I2
|T3
},
221 {"blt", "s,t,p", 0, (int) M_BLT
, INSN_MACRO
, I1
},
222 {"blt", "s,I,p", 0, (int) M_BLT_I
, INSN_MACRO
, I1
},
223 {"bltl", "s,t,p", 0, (int) M_BLTL
, INSN_MACRO
, I2
|T3
},
224 {"bltl", "s,I,p", 0, (int) M_BLTL_I
, INSN_MACRO
, I2
|T3
},
225 {"bltu", "s,t,p", 0, (int) M_BLTU
, INSN_MACRO
, I1
},
226 {"bltu", "s,I,p", 0, (int) M_BLTU_I
, INSN_MACRO
, I1
},
227 {"bltul", "s,t,p", 0, (int) M_BLTUL
, INSN_MACRO
, I2
|T3
},
228 {"bltul", "s,I,p", 0, (int) M_BLTUL_I
, INSN_MACRO
, I2
|T3
},
229 {"bltz", "s,p", 0x04000000, 0xfc1f0000, CBD
|RD_s
, I1
},
230 {"bltzl", "s,p", 0x04020000, 0xfc1f0000, CBL
|RD_s
, I2
|T3
},
231 {"bltzal", "s,p", 0x04100000, 0xfc1f0000, CBD
|RD_s
|WR_31
, I1
},
232 {"bltzall", "s,p", 0x04120000, 0xfc1f0000, CBL
|RD_s
|WR_31
, I2
|T3
},
233 {"bnez", "s,p", 0x14000000, 0xfc1f0000, CBD
|RD_s
, I1
},
234 {"bnezl", "s,p", 0x54000000, 0xfc1f0000, CBL
|RD_s
, I2
|T3
},
235 {"bne", "s,t,p", 0x14000000, 0xfc000000, CBD
|RD_s
|RD_t
, I1
},
236 {"bne", "s,I,p", 0, (int) M_BNE_I
, INSN_MACRO
, I1
},
237 {"bnel", "s,t,p", 0x54000000, 0xfc000000, CBL
|RD_s
|RD_t
, I2
|T3
},
238 {"bnel", "s,I,p", 0, (int) M_BNEL_I
, INSN_MACRO
, I2
|T3
},
239 {"break", "", 0x0000000d, 0xffffffff, TRAP
, I1
},
240 {"break", "B", 0x0000000d, 0xfc00003f, TRAP
, I32
},
241 {"break", "c", 0x0000000d, 0xfc00ffff, TRAP
, I1
},
242 {"break", "c,q", 0x0000000d, 0xfc00003f, TRAP
, I1
},
243 {"c.f.d", "S,T", 0x46200030, 0xffe007ff, RD_S
|RD_T
|WR_CC
|FP_D
, I1
},
244 {"c.f.d", "M,S,T", 0x46200030, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_D
, I4
|I32
},
245 {"c.f.s", "S,T", 0x46000030, 0xffe007ff, RD_S
|RD_T
|WR_CC
|FP_S
, I1
},
246 {"c.f.s", "M,S,T", 0x46000030, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_S
, I4
|I32
},
247 {"c.f.ps", "S,T", 0x46c00030, 0xffe007ff, RD_S
|RD_T
|WR_CC
|FP_D
, I5
},
248 {"c.f.ps", "M,S,T", 0x46c00030, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_D
, I5
},
249 {"c.un.d", "S,T", 0x46200031, 0xffe007ff, RD_S
|RD_T
|WR_CC
|FP_D
, I1
},
250 {"c.un.d", "M,S,T", 0x46200031, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_D
, I4
|I32
},
251 {"c.un.s", "S,T", 0x46000031, 0xffe007ff, RD_S
|RD_T
|WR_CC
|FP_S
, I1
},
252 {"c.un.s", "M,S,T", 0x46000031, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_S
, I4
|I32
},
253 {"c.un.ps", "S,T", 0x46c00031, 0xffe007ff, RD_S
|RD_T
|WR_CC
|FP_D
, I5
},
254 {"c.un.ps", "M,S,T", 0x46c00031, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_D
, I5
},
255 {"c.eq.d", "S,T", 0x46200032, 0xffe007ff, RD_S
|RD_T
|WR_CC
|FP_D
, I1
},
256 {"c.eq.d", "M,S,T", 0x46200032, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_D
, I4
|I32
},
257 {"c.eq.s", "S,T", 0x46000032, 0xffe007ff, RD_S
|RD_T
|WR_CC
|FP_S
, I1
},
258 {"c.eq.s", "M,S,T", 0x46000032, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_S
, I4
|I32
},
259 {"c.eq.ps", "S,T", 0x46c00032, 0xffe007ff, RD_S
|RD_T
|WR_CC
|FP_D
, I5
},
260 {"c.eq.ps", "M,S,T", 0x46c00032, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_D
, I5
},
261 {"c.ueq.d", "S,T", 0x46200033, 0xffe007ff, RD_S
|RD_T
|WR_CC
|FP_D
, I1
},
262 {"c.ueq.d", "M,S,T", 0x46200033, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_D
, I4
|I32
},
263 {"c.ueq.s", "S,T", 0x46000033, 0xffe007ff, RD_S
|RD_T
|WR_CC
|FP_S
, I1
},
264 {"c.ueq.s", "M,S,T", 0x46000033, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_S
, I4
|I32
},
265 {"c.ueq.ps","S,T", 0x46c00033, 0xffe007ff, RD_S
|RD_T
|WR_CC
|FP_D
, I5
},
266 {"c.ueq.ps","M,S,T", 0x46c00033, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_D
, I5
},
267 {"c.olt.d", "S,T", 0x46200034, 0xffe007ff, RD_S
|RD_T
|WR_CC
|FP_D
, I1
},
268 {"c.olt.d", "M,S,T", 0x46200034, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_D
, I4
|I32
},
269 {"c.olt.s", "S,T", 0x46000034, 0xffe007ff, RD_S
|RD_T
|WR_CC
|FP_S
, I1
},
270 {"c.olt.s", "M,S,T", 0x46000034, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_S
, I4
|I32
},
271 {"c.olt.ps","S,T", 0x46c00034, 0xffe007ff, RD_S
|RD_T
|WR_CC
|FP_D
, I5
},
272 {"c.olt.ps","M,S,T", 0x46c00034, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_D
, I5
},
273 {"c.ult.d", "S,T", 0x46200035, 0xffe007ff, RD_S
|RD_T
|WR_CC
|FP_D
, I1
},
274 {"c.ult.d", "M,S,T", 0x46200035, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_D
, I4
|I32
},
275 {"c.ult.s", "S,T", 0x46000035, 0xffe007ff, RD_S
|RD_T
|WR_CC
|FP_S
, I1
},
276 {"c.ult.s", "M,S,T", 0x46000035, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_S
, I4
|I32
},
277 {"c.ult.ps","S,T", 0x46c00035, 0xffe007ff, RD_S
|RD_T
|WR_CC
|FP_D
, I5
},
278 {"c.ult.ps","M,S,T", 0x46c00035, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_D
, I5
},
279 {"c.ole.d", "S,T", 0x46200036, 0xffe007ff, RD_S
|RD_T
|WR_CC
|FP_D
, I1
},
280 {"c.ole.d", "M,S,T", 0x46200036, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_D
, I4
|I32
},
281 {"c.ole.s", "S,T", 0x46000036, 0xffe007ff, RD_S
|RD_T
|WR_CC
|FP_S
, I1
},
282 {"c.ole.s", "M,S,T", 0x46000036, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_S
, I4
|I32
},
283 {"c.ole.ps","S,T", 0x46c00036, 0xffe007ff, RD_S
|RD_T
|WR_CC
|FP_D
, I5
},
284 {"c.ole.ps","M,S,T", 0x46c00036, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_D
, I5
},
285 {"c.ule.d", "S,T", 0x46200037, 0xffe007ff, RD_S
|RD_T
|WR_CC
|FP_D
, I1
},
286 {"c.ule.d", "M,S,T", 0x46200037, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_D
, I4
|I32
},
287 {"c.ule.s", "S,T", 0x46000037, 0xffe007ff, RD_S
|RD_T
|WR_CC
|FP_S
, I1
},
288 {"c.ule.s", "M,S,T", 0x46000037, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_S
, I4
|I32
},
289 {"c.ule.ps","S,T", 0x46c00037, 0xffe007ff, RD_S
|RD_T
|WR_CC
|FP_D
, I5
},
290 {"c.ule.ps","M,S,T", 0x46c00037, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_D
, I5
},
291 {"c.sf.d", "S,T", 0x46200038, 0xffe007ff, RD_S
|RD_T
|WR_CC
|FP_D
, I1
},
292 {"c.sf.d", "M,S,T", 0x46200038, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_D
, I4
|I32
},
293 {"c.sf.s", "S,T", 0x46000038, 0xffe007ff, RD_S
|RD_T
|WR_CC
|FP_S
, I1
},
294 {"c.sf.s", "M,S,T", 0x46000038, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_S
, I4
|I32
},
295 {"c.sf.ps", "S,T", 0x46c00038, 0xffe007ff, RD_S
|RD_T
|WR_CC
|FP_D
, I5
},
296 {"c.sf.ps", "M,S,T", 0x46c00038, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_D
, I5
},
297 {"c.ngle.d","S,T", 0x46200039, 0xffe007ff, RD_S
|RD_T
|WR_CC
|FP_D
, I1
},
298 {"c.ngle.d","M,S,T", 0x46200039, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_D
, I4
|I32
},
299 {"c.ngle.s","S,T", 0x46000039, 0xffe007ff, RD_S
|RD_T
|WR_CC
|FP_S
, I1
},
300 {"c.ngle.s","M,S,T", 0x46000039, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_S
, I4
|I32
},
301 {"c.ngle.ps","S,T", 0x46c00039, 0xffe007ff, RD_S
|RD_T
|WR_CC
|FP_D
, I5
},
302 {"c.ngle.ps","M,S,T", 0x46c00039, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_D
, I5
},
303 {"c.seq.d", "S,T", 0x4620003a, 0xffe007ff, RD_S
|RD_T
|WR_CC
|FP_D
, I1
},
304 {"c.seq.d", "M,S,T", 0x4620003a, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_D
, I4
|I32
},
305 {"c.seq.s", "S,T", 0x4600003a, 0xffe007ff, RD_S
|RD_T
|WR_CC
|FP_S
, I1
},
306 {"c.seq.s", "M,S,T", 0x4600003a, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_S
, I4
|I32
},
307 {"c.seq.ps","S,T", 0x46c0003a, 0xffe007ff, RD_S
|RD_T
|WR_CC
|FP_D
, I5
},
308 {"c.seq.ps","M,S,T", 0x46c0003a, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_D
, I5
},
309 {"c.ngl.d", "S,T", 0x4620003b, 0xffe007ff, RD_S
|RD_T
|WR_CC
|FP_D
, I1
},
310 {"c.ngl.d", "M,S,T", 0x4620003b, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_D
, I4
|I32
},
311 {"c.ngl.s", "S,T", 0x4600003b, 0xffe007ff, RD_S
|RD_T
|WR_CC
|FP_S
, I1
},
312 {"c.ngl.s", "M,S,T", 0x4600003b, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_S
, I4
|I32
},
313 {"c.ngl.ps","S,T", 0x46c0003b, 0xffe007ff, RD_S
|RD_T
|WR_CC
|FP_D
, I5
},
314 {"c.ngl.ps","M,S,T", 0x46c0003b, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_D
, I5
},
315 {"c.lt.d", "S,T", 0x4620003c, 0xffe007ff, RD_S
|RD_T
|WR_CC
|FP_D
, I1
},
316 {"c.lt.d", "M,S,T", 0x4620003c, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_D
, I4
|I32
},
317 {"c.lt.s", "S,T", 0x4600003c, 0xffe007ff, RD_S
|RD_T
|WR_CC
|FP_S
, I1
},
318 {"c.lt.s", "M,S,T", 0x4600003c, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_S
, I4
|I32
},
319 {"c.lt.ps", "S,T", 0x46c0003c, 0xffe007ff, RD_S
|RD_T
|WR_CC
|FP_D
, I5
},
320 {"c.lt.ps", "M,S,T", 0x46c0003c, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_D
, I5
},
321 {"c.nge.d", "S,T", 0x4620003d, 0xffe007ff, RD_S
|RD_T
|WR_CC
|FP_D
, I1
},
322 {"c.nge.d", "M,S,T", 0x4620003d, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_D
, I4
|I32
},
323 {"c.nge.s", "S,T", 0x4600003d, 0xffe007ff, RD_S
|RD_T
|WR_CC
|FP_S
, I1
},
324 {"c.nge.s", "M,S,T", 0x4600003d, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_S
, I4
|I32
},
325 {"c.nge.ps","S,T", 0x46c0003d, 0xffe007ff, RD_S
|RD_T
|WR_CC
|FP_D
, I5
},
326 {"c.nge.ps","M,S,T", 0x46c0003d, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_D
, I5
},
327 {"c.le.d", "S,T", 0x4620003e, 0xffe007ff, RD_S
|RD_T
|WR_CC
|FP_D
, I1
},
328 {"c.le.d", "M,S,T", 0x4620003e, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_D
, I4
|I32
},
329 {"c.le.s", "S,T", 0x4600003e, 0xffe007ff, RD_S
|RD_T
|WR_CC
|FP_S
, I1
},
330 {"c.le.s", "M,S,T", 0x4600003e, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_S
, I4
|I32
},
331 {"c.le.ps", "S,T", 0x46c0003e, 0xffe007ff, RD_S
|RD_T
|WR_CC
|FP_D
, I5
},
332 {"c.le.ps", "M,S,T", 0x46c0003e, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_D
, I5
},
333 {"c.ngt.d", "S,T", 0x4620003f, 0xffe007ff, RD_S
|RD_T
|WR_CC
|FP_D
, I1
},
334 {"c.ngt.d", "M,S,T", 0x4620003f, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_D
, I4
|I32
},
335 {"c.ngt.s", "S,T", 0x4600003f, 0xffe007ff, RD_S
|RD_T
|WR_CC
|FP_S
, I1
},
336 {"c.ngt.s", "M,S,T", 0x4600003f, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_S
, I4
|I32
},
337 {"c.ngt.ps","S,T", 0x46c0003f, 0xffe007ff, RD_S
|RD_T
|WR_CC
|FP_D
, I5
},
338 {"c.ngt.ps","M,S,T", 0x46c0003f, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_D
, I5
},
339 {"cabs.eq.d", "M,S,T", 0x46200072, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_D
, M3D
},
340 {"cabs.eq.ps", "M,S,T", 0x46c00072, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_D
, M3D
},
341 {"cabs.eq.s", "M,S,T", 0x46000072, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_S
, M3D
},
342 {"cabs.f.d", "M,S,T", 0x46200070, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_D
, M3D
},
343 {"cabs.f.ps", "M,S,T", 0x46c00070, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_D
, M3D
},
344 {"cabs.f.s", "M,S,T", 0x46000070, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_S
, M3D
},
345 {"cabs.le.d", "M,S,T", 0x4620007e, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_D
, M3D
},
346 {"cabs.le.ps", "M,S,T", 0x46c0007e, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_D
, M3D
},
347 {"cabs.le.s", "M,S,T", 0x4600007e, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_S
, M3D
},
348 {"cabs.lt.d", "M,S,T", 0x4620007c, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_D
, M3D
},
349 {"cabs.lt.ps", "M,S,T", 0x46c0007c, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_D
, M3D
},
350 {"cabs.lt.s", "M,S,T", 0x4600007c, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_S
, M3D
},
351 {"cabs.nge.d", "M,S,T", 0x4620007d, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_D
, M3D
},
352 {"cabs.nge.ps","M,S,T", 0x46c0007d, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_D
, M3D
},
353 {"cabs.nge.s", "M,S,T", 0x4600007d, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_S
, M3D
},
354 {"cabs.ngl.d", "M,S,T", 0x4620007b, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_D
, M3D
},
355 {"cabs.ngl.ps","M,S,T", 0x46c0007b, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_D
, M3D
},
356 {"cabs.ngl.s", "M,S,T", 0x4600007b, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_S
, M3D
},
357 {"cabs.ngle.d","M,S,T", 0x46200079, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_D
, M3D
},
358 {"cabs.ngle.ps","M,S,T",0x46c00079, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_D
, M3D
},
359 {"cabs.ngle.s","M,S,T", 0x46000079, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_S
, M3D
},
360 {"cabs.ngt.d", "M,S,T", 0x4620007f, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_D
, M3D
},
361 {"cabs.ngt.ps","M,S,T", 0x46c0007f, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_D
, M3D
},
362 {"cabs.ngt.s", "M,S,T", 0x4600007f, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_S
, M3D
},
363 {"cabs.ole.d", "M,S,T", 0x46200076, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_D
, M3D
},
364 {"cabs.ole.ps","M,S,T", 0x46c00076, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_D
, M3D
},
365 {"cabs.ole.s", "M,S,T", 0x46000076, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_S
, M3D
},
366 {"cabs.olt.d", "M,S,T", 0x46200074, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_D
, M3D
},
367 {"cabs.olt.ps","M,S,T", 0x46c00074, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_D
, M3D
},
368 {"cabs.olt.s", "M,S,T", 0x46000074, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_S
, M3D
},
369 {"cabs.seq.d", "M,S,T", 0x4620007a, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_D
, M3D
},
370 {"cabs.seq.ps","M,S,T", 0x46c0007a, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_D
, M3D
},
371 {"cabs.seq.s", "M,S,T", 0x4600007a, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_S
, M3D
},
372 {"cabs.sf.d", "M,S,T", 0x46200078, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_D
, M3D
},
373 {"cabs.sf.ps", "M,S,T", 0x46c00078, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_D
, M3D
},
374 {"cabs.sf.s", "M,S,T", 0x46000078, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_S
, M3D
},
375 {"cabs.ueq.d", "M,S,T", 0x46200073, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_D
, M3D
},
376 {"cabs.ueq.ps","M,S,T", 0x46c00073, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_D
, M3D
},
377 {"cabs.ueq.s", "M,S,T", 0x46000073, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_S
, M3D
},
378 {"cabs.ule.d", "M,S,T", 0x46200077, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_D
, M3D
},
379 {"cabs.ule.ps","M,S,T", 0x46c00077, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_D
, M3D
},
380 {"cabs.ule.s", "M,S,T", 0x46000077, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_S
, M3D
},
381 {"cabs.ult.d", "M,S,T", 0x46200075, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_D
, M3D
},
382 {"cabs.ult.ps","M,S,T", 0x46c00075, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_D
, M3D
},
383 {"cabs.ult.s", "M,S,T", 0x46000075, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_S
, M3D
},
384 {"cabs.un.d", "M,S,T", 0x46200071, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_D
, M3D
},
385 {"cabs.un.ps", "M,S,T", 0x46c00071, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_D
, M3D
},
386 {"cabs.un.s", "M,S,T", 0x46000071, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_S
, M3D
},
387 {"cache", "k,o(b)", 0xbc000000, 0xfc000000, RD_b
, I3
|I32
|T3
},
388 {"ceil.l.d", "D,S", 0x4620000a, 0xffff003f, WR_D
|RD_S
|FP_D
, I3
},
389 {"ceil.l.s", "D,S", 0x4600000a, 0xffff003f, WR_D
|RD_S
|FP_S
, I3
},
390 {"ceil.w.d", "D,S", 0x4620000e, 0xffff003f, WR_D
|RD_S
|FP_D
, I2
},
391 {"ceil.w.s", "D,S", 0x4600000e, 0xffff003f, WR_D
|RD_S
|FP_S
, I2
},
392 {"cfc0", "t,G", 0x40400000, 0xffe007ff, LCD
|WR_t
|RD_C0
, I1
},
393 {"cfc1", "t,G", 0x44400000, 0xffe007ff, LCD
|WR_t
|RD_C1
|FP_S
, I1
},
394 {"cfc1", "t,S", 0x44400000, 0xffe007ff, LCD
|WR_t
|RD_C1
|FP_S
, I1
},
395 {"cfc2", "t,G", 0x48400000, 0xffe007ff, LCD
|WR_t
|RD_C2
, I1
},
396 {"cfc3", "t,G", 0x4c400000, 0xffe007ff, LCD
|WR_t
|RD_C3
, I1
},
397 {"clo", "U,s", 0x70000021, 0xfc0007ff, WR_d
|WR_t
|RD_s
, I32
},
398 {"clz", "U,s", 0x70000020, 0xfc0007ff, WR_d
|WR_t
|RD_s
, I32
},
399 {"ctc0", "t,G", 0x40c00000, 0xffe007ff, COD
|RD_t
|WR_CC
, I1
},
400 {"ctc1", "t,G", 0x44c00000, 0xffe007ff, COD
|RD_t
|WR_CC
|FP_S
, I1
},
401 {"ctc1", "t,S", 0x44c00000, 0xffe007ff, COD
|RD_t
|WR_CC
|FP_S
, I1
},
402 {"ctc2", "t,G", 0x48c00000, 0xffe007ff, COD
|RD_t
|WR_CC
, I1
},
403 {"ctc3", "t,G", 0x4cc00000, 0xffe007ff, COD
|RD_t
|WR_CC
, I1
},
404 {"cvt.d.l", "D,S", 0x46a00021, 0xffff003f, WR_D
|RD_S
|FP_D
, I3
},
405 {"cvt.d.s", "D,S", 0x46000021, 0xffff003f, WR_D
|RD_S
|FP_D
|FP_S
, I1
},
406 {"cvt.d.w", "D,S", 0x46800021, 0xffff003f, WR_D
|RD_S
|FP_D
, I1
},
407 {"cvt.l.d", "D,S", 0x46200025, 0xffff003f, WR_D
|RD_S
|FP_D
, I3
},
408 {"cvt.l.s", "D,S", 0x46000025, 0xffff003f, WR_D
|RD_S
|FP_S
, I3
},
409 {"cvt.s.l", "D,S", 0x46a00020, 0xffff003f, WR_D
|RD_S
|FP_S
, I3
},
410 {"cvt.s.d", "D,S", 0x46200020, 0xffff003f, WR_D
|RD_S
|FP_S
|FP_D
, I1
},
411 {"cvt.s.w", "D,S", 0x46800020, 0xffff003f, WR_D
|RD_S
|FP_S
, I1
},
412 {"cvt.s.pl","D,S", 0x46c00028, 0xffff003f, WR_D
|RD_S
|FP_S
|FP_D
, I5
},
413 {"cvt.s.pu","D,S", 0x46c00020, 0xffff003f, WR_D
|RD_S
|FP_S
|FP_D
, I5
},
414 {"cvt.w.d", "D,S", 0x46200024, 0xffff003f, WR_D
|RD_S
|FP_D
, I1
},
415 {"cvt.w.s", "D,S", 0x46000024, 0xffff003f, WR_D
|RD_S
|FP_S
, I1
},
416 {"cvt.ps.pw", "D,S", 0x46800026, 0xffff003f, WR_D
|RD_S
|FP_S
|FP_D
, M3D
},
417 {"cvt.ps.s","D,V,T", 0x46000026, 0xffe0003f, WR_D
|RD_S
|RD_T
|FP_D
, I5
},
418 {"cvt.pw.ps", "D,S", 0x46c00024, 0xffff003f, WR_D
|RD_S
|FP_S
|FP_D
, M3D
},
419 {"dabs", "d,v", 0, (int) M_DABS
, INSN_MACRO
, I3
},
420 {"dadd", "d,v,t", 0x0000002c, 0xfc0007ff, WR_d
|RD_s
|RD_t
, I3
},
421 {"dadd", "t,r,I", 0, (int) M_DADD_I
, INSN_MACRO
, I3
},
422 {"daddi", "t,r,j", 0x60000000, 0xfc000000, WR_t
|RD_s
, I3
},
423 {"daddiu", "t,r,j", 0x64000000, 0xfc000000, WR_t
|RD_s
, I3
},
424 {"daddu", "d,v,t", 0x0000002d, 0xfc0007ff, WR_d
|RD_s
|RD_t
, I3
},
425 {"daddu", "t,r,I", 0, (int) M_DADDU_I
, INSN_MACRO
, I3
},
426 {"dclo", "U,s", 0x70000025, 0xfc0007ff, RD_s
|WR_d
|WR_t
, I64
},
427 {"dclz", "U,s", 0x70000024, 0xfc0007ff, RD_s
|WR_d
|WR_t
, I64
},
428 /* dctr and dctw are used on the r5000. */
429 {"dctr", "o(b)", 0xbc050000, 0xfc1f0000, RD_b
, I3
},
430 {"dctw", "o(b)", 0xbc090000, 0xfc1f0000, RD_b
, I3
},
431 {"deret", "", 0x4200001f, 0xffffffff, 0, I32
|G2
},
432 /* For ddiv, see the comments about div. */
433 {"ddiv", "z,s,t", 0x0000001e, 0xfc00ffff, RD_s
|RD_t
|WR_HILO
, I3
},
434 {"ddiv", "d,v,t", 0, (int) M_DDIV_3
, INSN_MACRO
, I3
},
435 {"ddiv", "d,v,I", 0, (int) M_DDIV_3I
, INSN_MACRO
, I3
},
436 /* For ddivu, see the comments about div. */
437 {"ddivu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s
|RD_t
|WR_HILO
, I3
},
438 {"ddivu", "d,v,t", 0, (int) M_DDIVU_3
, INSN_MACRO
, I3
},
439 {"ddivu", "d,v,I", 0, (int) M_DDIVU_3I
, INSN_MACRO
, I3
},
440 /* The MIPS assembler treats the div opcode with two operands as
441 though the first operand appeared twice (the first operand is both
442 a source and a destination). To get the div machine instruction,
443 you must use an explicit destination of $0. */
444 {"div", "z,s,t", 0x0000001a, 0xfc00ffff, RD_s
|RD_t
|WR_HILO
, I1
},
445 {"div", "z,t", 0x0000001a, 0xffe0ffff, RD_s
|RD_t
|WR_HILO
, I1
},
446 {"div", "d,v,t", 0, (int) M_DIV_3
, INSN_MACRO
, I1
},
447 {"div", "d,v,I", 0, (int) M_DIV_3I
, INSN_MACRO
, I1
},
448 {"div.d", "D,V,T", 0x46200003, 0xffe0003f, WR_D
|RD_S
|RD_T
|FP_D
, I1
},
449 {"div.s", "D,V,T", 0x46000003, 0xffe0003f, WR_D
|RD_S
|RD_T
|FP_S
, I1
},
450 {"div.ps", "D,V,T", 0x46c00003, 0xffe0003f, WR_D
|RD_S
|RD_T
|FP_D
, SB1
},
451 /* For divu, see the comments about div. */
452 {"divu", "z,s,t", 0x0000001b, 0xfc00ffff, RD_s
|RD_t
|WR_HILO
, I1
},
453 {"divu", "z,t", 0x0000001b, 0xffe0ffff, RD_s
|RD_t
|WR_HILO
, I1
},
454 {"divu", "d,v,t", 0, (int) M_DIVU_3
, INSN_MACRO
, I1
},
455 {"divu", "d,v,I", 0, (int) M_DIVU_3I
, INSN_MACRO
, I1
},
456 {"dla", "t,o(b)", 0x64000000, 0xfc000000, WR_t
|RD_s
, I3
}, /* daddiu */
457 {"dla", "t,A(b)", 0, (int) M_DLA_AB
, INSN_MACRO
, I3
},
458 {"dli", "t,j", 0x24000000, 0xffe00000, WR_t
, I3
}, /* addiu */
459 {"dli", "t,i", 0x34000000, 0xffe00000, WR_t
, I3
}, /* ori */
460 {"dli", "t,I", 0, (int) M_DLI
, INSN_MACRO
, I3
},
462 {"dmadd16", "s,t", 0x00000029, 0xfc00ffff, RD_s
|RD_t
|MOD_LO
, V1
},
463 {"dmfc0", "t,G", 0x40200000, 0xffe007ff, LCD
|WR_t
|RD_C0
, I3
},
464 {"dmfc0", "t,G,H", 0x40200000, 0xffe007f8, LCD
|WR_t
|RD_C0
, I64
},
465 {"dmtc0", "t,G", 0x40a00000, 0xffe007ff, COD
|RD_t
|WR_C0
|WR_CC
, I3
},
466 {"dmtc0", "t,G,H", 0x40a00000, 0xffe007f8, COD
|RD_t
|WR_C0
|WR_CC
, I64
},
467 {"dmfc1", "t,S", 0x44200000, 0xffe007ff, LCD
|WR_t
|RD_S
|FP_S
, I3
},
468 {"dmfc1", "t,G", 0x44200000, 0xffe007ff, LCD
|WR_t
|RD_S
|FP_S
, I3
},
469 {"dmtc1", "t,S", 0x44a00000, 0xffe007ff, COD
|RD_t
|WR_S
|FP_S
, I3
},
470 {"dmtc1", "t,G", 0x44a00000, 0xffe007ff, COD
|RD_t
|WR_S
|FP_S
, I3
},
471 {"dmfc2", "t,G", 0x48200000, 0xffe007ff, LCD
|WR_t
|RD_C2
, I3
},
472 {"dmfc2", "t,G,H", 0x48200000, 0xffe007f8, LCD
|WR_t
|RD_C2
, I64
},
473 {"dmtc2", "t,G", 0x48a00000, 0xffe007ff, COD
|RD_t
|WR_C2
|WR_CC
, I3
},
474 {"dmtc2", "t,G,H", 0x48a00000, 0xffe007f8, COD
|RD_t
|WR_C2
|WR_CC
, I64
},
475 {"dmfc3", "t,G", 0x4c200000, 0xffe007ff, LCD
|WR_t
|RD_C3
, I3
},
476 {"dmfc3", "t,G,H", 0x4c200000, 0xffe007f8, LCD
|WR_t
|RD_C3
, I64
},
477 {"dmtc3", "t,G", 0x4ca00000, 0xffe007ff, COD
|RD_t
|WR_C3
|WR_CC
, I3
},
478 {"dmtc3", "t,G,H", 0x4ca00000, 0xffe007f8, COD
|RD_t
|WR_C3
|WR_CC
, I64
},
479 {"dmul", "d,v,t", 0, (int) M_DMUL
, INSN_MACRO
, I3
},
480 {"dmul", "d,v,I", 0, (int) M_DMUL_I
, INSN_MACRO
, I3
},
481 {"dmulo", "d,v,t", 0, (int) M_DMULO
, INSN_MACRO
, I3
},
482 {"dmulo", "d,v,I", 0, (int) M_DMULO_I
, INSN_MACRO
, I3
},
483 {"dmulou", "d,v,t", 0, (int) M_DMULOU
, INSN_MACRO
, I3
},
484 {"dmulou", "d,v,I", 0, (int) M_DMULOU_I
, INSN_MACRO
, I3
},
485 {"dmult", "s,t", 0x0000001c, 0xfc00ffff, RD_s
|RD_t
|WR_HILO
, I3
},
486 {"dmultu", "s,t", 0x0000001d, 0xfc00ffff, RD_s
|RD_t
|WR_HILO
, I3
},
487 {"dneg", "d,w", 0x0000002e, 0xffe007ff, WR_d
|RD_t
, I3
}, /* dsub 0 */
488 {"dnegu", "d,w", 0x0000002f, 0xffe007ff, WR_d
|RD_t
, I3
}, /* dsubu 0*/
489 {"drem", "z,s,t", 0x0000001e, 0xfc00ffff, RD_s
|RD_t
|WR_HILO
, I3
},
490 {"drem", "d,v,t", 3, (int) M_DREM_3
, INSN_MACRO
, I3
},
491 {"drem", "d,v,I", 3, (int) M_DREM_3I
, INSN_MACRO
, I3
},
492 {"dremu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s
|RD_t
|WR_HILO
, I3
},
493 {"dremu", "d,v,t", 3, (int) M_DREMU_3
, INSN_MACRO
, I3
},
494 {"dremu", "d,v,I", 3, (int) M_DREMU_3I
, INSN_MACRO
, I3
},
495 {"dsllv", "d,t,s", 0x00000014, 0xfc0007ff, WR_d
|RD_t
|RD_s
, I3
},
496 {"dsll32", "d,w,<", 0x0000003c, 0xffe0003f, WR_d
|RD_t
, I3
},
497 {"dsll", "d,w,s", 0x00000014, 0xfc0007ff, WR_d
|RD_t
|RD_s
, I3
}, /* dsllv */
498 {"dsll", "d,w,>", 0x0000003c, 0xffe0003f, WR_d
|RD_t
, I3
}, /* dsll32 */
499 {"dsll", "d,w,<", 0x00000038, 0xffe0003f, WR_d
|RD_t
, I3
},
500 {"dsrav", "d,t,s", 0x00000017, 0xfc0007ff, WR_d
|RD_t
|RD_s
, I3
},
501 {"dsra32", "d,w,<", 0x0000003f, 0xffe0003f, WR_d
|RD_t
, I3
},
502 {"dsra", "d,w,s", 0x00000017, 0xfc0007ff, WR_d
|RD_t
|RD_s
, I3
}, /* dsrav */
503 {"dsra", "d,w,>", 0x0000003f, 0xffe0003f, WR_d
|RD_t
, I3
}, /* dsra32 */
504 {"dsra", "d,w,<", 0x0000003b, 0xffe0003f, WR_d
|RD_t
, I3
},
505 {"dsrlv", "d,t,s", 0x00000016, 0xfc0007ff, WR_d
|RD_t
|RD_s
, I3
},
506 {"dsrl32", "d,w,<", 0x0000003e, 0xffe0003f, WR_d
|RD_t
, I3
},
507 {"dsrl", "d,w,s", 0x00000016, 0xfc0007ff, WR_d
|RD_t
|RD_s
, I3
}, /* dsrlv */
508 {"dsrl", "d,w,>", 0x0000003e, 0xffe0003f, WR_d
|RD_t
, I3
}, /* dsrl32 */
509 {"dsrl", "d,w,<", 0x0000003a, 0xffe0003f, WR_d
|RD_t
, I3
},
510 {"dsub", "d,v,t", 0x0000002e, 0xfc0007ff, WR_d
|RD_s
|RD_t
, I3
},
511 {"dsub", "d,v,I", 0, (int) M_DSUB_I
, INSN_MACRO
, I3
},
512 {"dsubu", "d,v,t", 0x0000002f, 0xfc0007ff, WR_d
|RD_s
|RD_t
, I3
},
513 {"dsubu", "d,v,I", 0, (int) M_DSUBU_I
, INSN_MACRO
, I3
},
514 {"eret", "", 0x42000018, 0xffffffff, 0, I3
|I32
},
515 {"floor.l.d", "D,S", 0x4620000b, 0xffff003f, WR_D
|RD_S
|FP_D
, I3
},
516 {"floor.l.s", "D,S", 0x4600000b, 0xffff003f, WR_D
|RD_S
|FP_S
, I3
},
517 {"floor.w.d", "D,S", 0x4620000f, 0xffff003f, WR_D
|RD_S
|FP_D
, I2
},
518 {"floor.w.s", "D,S", 0x4600000f, 0xffff003f, WR_D
|RD_S
|FP_S
, I2
},
519 {"flushi", "", 0xbc010000, 0xffffffff, 0, L1
},
520 {"flushd", "", 0xbc020000, 0xffffffff, 0, L1
},
521 {"flushid", "", 0xbc030000, 0xffffffff, 0, L1
},
522 {"hibernate","", 0x42000023, 0xffffffff, 0, V1
},
523 {"jr", "s", 0x00000008, 0xfc1fffff, UBD
|RD_s
, I1
},
524 {"j", "s", 0x00000008, 0xfc1fffff, UBD
|RD_s
, I1
}, /* jr */
525 /* SVR4 PIC code requires special handling for j, so it must be a
527 {"j", "a", 0, (int) M_J_A
, INSN_MACRO
, I1
},
528 /* This form of j is used by the disassembler and internally by the
529 assembler, but will never match user input (because the line above
530 will match first). */
531 {"j", "a", 0x08000000, 0xfc000000, UBD
, I1
},
532 {"jalr", "s", 0x0000f809, 0xfc1fffff, UBD
|RD_s
|WR_d
, I1
},
533 {"jalr", "d,s", 0x00000009, 0xfc1f07ff, UBD
|RD_s
|WR_d
, I1
},
534 /* SVR4 PIC code requires special handling for jal, so it must be a
536 {"jal", "d,s", 0, (int) M_JAL_2
, INSN_MACRO
, I1
},
537 {"jal", "s", 0, (int) M_JAL_1
, INSN_MACRO
, I1
},
538 {"jal", "a", 0, (int) M_JAL_A
, INSN_MACRO
, I1
},
539 /* This form of jal is used by the disassembler and internally by the
540 assembler, but will never match user input (because the line above
541 will match first). */
542 {"jal", "a", 0x0c000000, 0xfc000000, UBD
|WR_31
, I1
},
543 /* jalx really should only be avaliable if mips16 is available,
544 but for now make it I1. */
545 {"jalx", "a", 0x74000000, 0xfc000000, UBD
|WR_31
, I1
},
546 {"la", "t,o(b)", 0x24000000, 0xfc000000, WR_t
|RD_s
, I1
}, /* addiu */
547 {"la", "t,A(b)", 0, (int) M_LA_AB
, INSN_MACRO
, I1
},
548 {"lb", "t,o(b)", 0x80000000, 0xfc000000, LDD
|RD_b
|WR_t
, I1
},
549 {"lb", "t,A(b)", 0, (int) M_LB_AB
, INSN_MACRO
, I1
},
550 {"lbu", "t,o(b)", 0x90000000, 0xfc000000, LDD
|RD_b
|WR_t
, I1
},
551 {"lbu", "t,A(b)", 0, (int) M_LBU_AB
, INSN_MACRO
, I1
},
552 {"ld", "t,o(b)", 0xdc000000, 0xfc000000, WR_t
|RD_b
, I3
},
553 {"ld", "t,o(b)", 0, (int) M_LD_OB
, INSN_MACRO
, I1
},
554 {"ld", "t,A(b)", 0, (int) M_LD_AB
, INSN_MACRO
, I1
},
555 {"ldc1", "T,o(b)", 0xd4000000, 0xfc000000, CLD
|RD_b
|WR_T
|FP_D
, I2
},
556 {"ldc1", "E,o(b)", 0xd4000000, 0xfc000000, CLD
|RD_b
|WR_T
|FP_D
, I2
},
557 {"ldc1", "T,A(b)", 0, (int) M_LDC1_AB
, INSN_MACRO
, I2
},
558 {"ldc1", "E,A(b)", 0, (int) M_LDC1_AB
, INSN_MACRO
, I2
},
559 {"l.d", "T,o(b)", 0xd4000000, 0xfc000000, CLD
|RD_b
|WR_T
|FP_D
, I2
}, /* ldc1 */
560 {"l.d", "T,o(b)", 0, (int) M_L_DOB
, INSN_MACRO
, I1
},
561 {"l.d", "T,A(b)", 0, (int) M_L_DAB
, INSN_MACRO
, I1
},
562 {"ldc2", "E,o(b)", 0xd8000000, 0xfc000000, CLD
|RD_b
|WR_CC
, I2
},
563 {"ldc2", "E,A(b)", 0, (int) M_LDC2_AB
, INSN_MACRO
, I2
},
564 {"ldc3", "E,o(b)", 0xdc000000, 0xfc000000, CLD
|RD_b
|WR_CC
, I2
},
565 {"ldc3", "E,A(b)", 0, (int) M_LDC3_AB
, INSN_MACRO
, I2
},
566 {"ldl", "t,o(b)", 0x68000000, 0xfc000000, LDD
|WR_t
|RD_b
, I3
},
567 {"ldl", "t,A(b)", 0, (int) M_LDL_AB
, INSN_MACRO
, I3
},
568 {"ldr", "t,o(b)", 0x6c000000, 0xfc000000, LDD
|WR_t
|RD_b
, I3
},
569 {"ldr", "t,A(b)", 0, (int) M_LDR_AB
, INSN_MACRO
, I3
},
570 {"ldxc1", "D,t(b)", 0x4c000001, 0xfc00f83f, LDD
|WR_D
|RD_t
|RD_b
, I4
},
571 {"lh", "t,o(b)", 0x84000000, 0xfc000000, LDD
|RD_b
|WR_t
, I1
},
572 {"lh", "t,A(b)", 0, (int) M_LH_AB
, INSN_MACRO
, I1
},
573 {"lhu", "t,o(b)", 0x94000000, 0xfc000000, LDD
|RD_b
|WR_t
, I1
},
574 {"lhu", "t,A(b)", 0, (int) M_LHU_AB
, INSN_MACRO
, I1
},
575 /* li is at the start of the table. */
576 {"li.d", "t,F", 0, (int) M_LI_D
, INSN_MACRO
, I1
},
577 {"li.d", "T,L", 0, (int) M_LI_DD
, INSN_MACRO
, I1
},
578 {"li.s", "t,f", 0, (int) M_LI_S
, INSN_MACRO
, I1
},
579 {"li.s", "T,l", 0, (int) M_LI_SS
, INSN_MACRO
, I1
},
580 {"ll", "t,o(b)", 0xc0000000, 0xfc000000, LDD
|RD_b
|WR_t
, I2
},
581 {"ll", "t,A(b)", 0, (int) M_LL_AB
, INSN_MACRO
, I2
},
582 {"lld", "t,o(b)", 0xd0000000, 0xfc000000, LDD
|RD_b
|WR_t
, I3
},
583 {"lld", "t,A(b)", 0, (int) M_LLD_AB
, INSN_MACRO
, I3
},
584 {"lui", "t,u", 0x3c000000, 0xffe00000, WR_t
, I1
},
585 {"luxc1", "D,t(b)", 0x4c000005, 0xfc00f83f, LDD
|WR_D
|RD_t
|RD_b
, I5
},
586 {"lw", "t,o(b)", 0x8c000000, 0xfc000000, LDD
|RD_b
|WR_t
, I1
},
587 {"lw", "t,A(b)", 0, (int) M_LW_AB
, INSN_MACRO
, I1
},
588 {"lwc0", "E,o(b)", 0xc0000000, 0xfc000000, CLD
|RD_b
|WR_CC
, I1
},
589 {"lwc0", "E,A(b)", 0, (int) M_LWC0_AB
, INSN_MACRO
, I1
},
590 {"lwc1", "T,o(b)", 0xc4000000, 0xfc000000, CLD
|RD_b
|WR_T
|FP_S
, I1
},
591 {"lwc1", "E,o(b)", 0xc4000000, 0xfc000000, CLD
|RD_b
|WR_T
|FP_S
, I1
},
592 {"lwc1", "T,A(b)", 0, (int) M_LWC1_AB
, INSN_MACRO
, I1
},
593 {"lwc1", "E,A(b)", 0, (int) M_LWC1_AB
, INSN_MACRO
, I1
},
594 {"l.s", "T,o(b)", 0xc4000000, 0xfc000000, CLD
|RD_b
|WR_T
|FP_S
, I1
}, /* lwc1 */
595 {"l.s", "T,A(b)", 0, (int) M_LWC1_AB
, INSN_MACRO
, I1
},
596 {"lwc2", "E,o(b)", 0xc8000000, 0xfc000000, CLD
|RD_b
|WR_CC
, I1
},
597 {"lwc2", "E,A(b)", 0, (int) M_LWC2_AB
, INSN_MACRO
, I1
},
598 {"lwc3", "E,o(b)", 0xcc000000, 0xfc000000, CLD
|RD_b
|WR_CC
, I1
},
599 {"lwc3", "E,A(b)", 0, (int) M_LWC3_AB
, INSN_MACRO
, I1
},
600 {"lwl", "t,o(b)", 0x88000000, 0xfc000000, LDD
|RD_b
|WR_t
, I1
},
601 {"lwl", "t,A(b)", 0, (int) M_LWL_AB
, INSN_MACRO
, I1
},
602 {"lcache", "t,o(b)", 0x88000000, 0xfc000000, LDD
|RD_b
|WR_t
, I2
}, /* same */
603 {"lcache", "t,A(b)", 0, (int) M_LWL_AB
, INSN_MACRO
, I2
}, /* as lwl */
604 {"lwr", "t,o(b)", 0x98000000, 0xfc000000, LDD
|RD_b
|WR_t
, I1
},
605 {"lwr", "t,A(b)", 0, (int) M_LWR_AB
, INSN_MACRO
, I1
},
606 {"flush", "t,o(b)", 0x98000000, 0xfc000000, LDD
|RD_b
|WR_t
, I2
}, /* same */
607 {"flush", "t,A(b)", 0, (int) M_LWR_AB
, INSN_MACRO
, I2
}, /* as lwr */
608 {"lwu", "t,o(b)", 0x9c000000, 0xfc000000, LDD
|RD_b
|WR_t
, I3
},
609 {"lwu", "t,A(b)", 0, (int) M_LWU_AB
, INSN_MACRO
, I3
},
610 {"lwxc1", "D,t(b)", 0x4c000000, 0xfc00f83f, LDD
|WR_D
|RD_t
|RD_b
, I4
},
611 {"mad", "s,t", 0x70000000, 0xfc00ffff, RD_s
|RD_t
|MOD_HILO
, P3
},
612 {"madu", "s,t", 0x70000001, 0xfc00ffff, RD_s
|RD_t
|MOD_HILO
, P3
},
613 {"madd.d", "D,R,S,T", 0x4c000021, 0xfc00003f, RD_R
|RD_S
|RD_T
|WR_D
|FP_D
, I4
},
614 {"madd.s", "D,R,S,T", 0x4c000020, 0xfc00003f, RD_R
|RD_S
|RD_T
|WR_D
|FP_S
, I4
},
615 {"madd.ps", "D,R,S,T", 0x4c000026, 0xfc00003f, RD_R
|RD_S
|RD_T
|WR_D
|FP_D
, I5
},
616 {"madd", "s,t", 0x0000001c, 0xfc00ffff, RD_s
|RD_t
|WR_HILO
, L1
},
617 {"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s
|RD_t
|MOD_HILO
, I32
},
618 {"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s
|RD_t
|WR_HILO
|IS_M
, G1
},
619 {"madd", "d,s,t", 0x70000000, 0xfc0007ff, RD_s
|RD_t
|WR_HILO
|WR_d
|IS_M
, G1
},
620 {"maddu", "s,t", 0x0000001d, 0xfc00ffff, RD_s
|RD_t
|WR_HILO
, L1
},
621 {"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s
|RD_t
|MOD_HILO
, I32
},
622 {"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s
|RD_t
|WR_HILO
|IS_M
, G1
},
623 {"maddu", "d,s,t", 0x70000001, 0xfc0007ff, RD_s
|RD_t
|WR_HILO
|WR_d
|IS_M
, G1
},
624 {"madd16", "s,t", 0x00000028, 0xfc00ffff, RD_s
|RD_t
|MOD_HILO
, V1
},
625 {"mfpc", "t,P", 0x4000c801, 0xffe0ffc1, LCD
|WR_t
|RD_C0
, M1
},
626 {"mfps", "t,P", 0x4000c800, 0xffe0ffc1, LCD
|WR_t
|RD_C0
, M1
},
627 {"mfc0", "t,G", 0x40000000, 0xffe007ff, LCD
|WR_t
|RD_C0
, I1
},
628 {"mfc0", "t,G,H", 0x40000000, 0xffe007f8, LCD
|WR_t
|RD_C0
, I32
},
629 {"mfc1", "t,S", 0x44000000, 0xffe007ff, LCD
|WR_t
|RD_S
|FP_S
, I1
},
630 {"mfc1", "t,G", 0x44000000, 0xffe007ff, LCD
|WR_t
|RD_S
|FP_S
, I1
},
631 {"mfc2", "t,G", 0x48000000, 0xffe007ff, LCD
|WR_t
|RD_C2
, I1
},
632 {"mfc2", "t,G,H", 0x48000000, 0xffe007f8, LCD
|WR_t
|RD_C2
, I32
},
633 {"mfc3", "t,G", 0x4c000000, 0xffe007ff, LCD
|WR_t
|RD_C3
, I1
},
634 {"mfc3", "t,G,H", 0x4c000000, 0xffe007f8, LCD
|WR_t
|RD_C3
, I32
},
635 {"mfhi", "d", 0x00000010, 0xffff07ff, WR_d
|RD_HI
, I1
},
636 {"mflo", "d", 0x00000012, 0xffff07ff, WR_d
|RD_LO
, I1
},
637 {"mov.d", "D,S", 0x46200006, 0xffff003f, WR_D
|RD_S
|FP_D
, I1
},
638 {"mov.s", "D,S", 0x46000006, 0xffff003f, WR_D
|RD_S
|FP_S
, I1
},
639 {"mov.ps", "D,S", 0x46c00006, 0xffff003f, WR_D
|RD_S
|FP_D
, I5
},
640 {"movf", "d,s,N", 0x00000001, 0xfc0307ff, WR_d
|RD_s
|RD_CC
|FP_D
|FP_S
, I4
|I32
},
641 {"movf.d", "D,S,N", 0x46200011, 0xffe3003f, WR_D
|RD_S
|RD_CC
|FP_D
, I4
|I32
},
642 {"movf.s", "D,S,N", 0x46000011, 0xffe3003f, WR_D
|RD_S
|RD_CC
|FP_S
, I4
|I32
},
643 {"movf.ps", "D,S,N", 0x46c00011, 0xffe3003f, WR_D
|RD_S
|RD_CC
|FP_D
, I5
},
644 {"movn", "d,v,t", 0x0000000b, 0xfc0007ff, WR_d
|RD_s
|RD_t
, I4
|I32
},
645 {"ffc", "d,v", 0x0000000b, 0xfc1f07ff, WR_d
|RD_s
, L1
},
646 {"movn.d", "D,S,t", 0x46200013, 0xffe0003f, WR_D
|RD_S
|RD_t
|FP_D
, I4
|I32
},
647 {"movn.s", "D,S,t", 0x46000013, 0xffe0003f, WR_D
|RD_S
|RD_t
|FP_S
, I4
|I32
},
648 {"movn.ps", "D,S,t", 0x46c00013, 0xffe0003f, WR_D
|RD_S
|RD_t
|FP_D
, I5
},
649 {"movt", "d,s,N", 0x00010001, 0xfc0307ff, WR_d
|RD_s
|RD_CC
, I4
|I32
},
650 {"movt.d", "D,S,N", 0x46210011, 0xffe3003f, WR_D
|RD_S
|RD_CC
|FP_D
, I4
|I32
},
651 {"movt.s", "D,S,N", 0x46010011, 0xffe3003f, WR_D
|RD_S
|RD_CC
|FP_S
, I4
|I32
},
652 {"movt.ps", "D,S,N", 0x46c10011, 0xffe3003f, WR_D
|RD_S
|RD_CC
|FP_D
, I5
},
653 {"movz", "d,v,t", 0x0000000a, 0xfc0007ff, WR_d
|RD_s
|RD_t
, I4
|I32
},
654 {"ffs", "d,v", 0x0000000a, 0xfc1f07ff, WR_d
|RD_s
, L1
},
655 {"movz.d", "D,S,t", 0x46200012, 0xffe0003f, WR_D
|RD_S
|RD_t
|FP_D
, I4
|I32
},
656 {"movz.s", "D,S,t", 0x46000012, 0xffe0003f, WR_D
|RD_S
|RD_t
|FP_S
, I4
|I32
},
657 {"movz.ps", "D,S,t", 0x46c00012, 0xffe0003f, WR_D
|RD_S
|RD_t
|FP_D
, I5
},
658 /* move is at the top of the table. */
659 {"msub.d", "D,R,S,T", 0x4c000029, 0xfc00003f, RD_R
|RD_S
|RD_T
|WR_D
|FP_D
, I4
},
660 {"msub.s", "D,R,S,T", 0x4c000028, 0xfc00003f, RD_R
|RD_S
|RD_T
|WR_D
|FP_S
, I4
},
661 {"msub.ps", "D,R,S,T", 0x4c00002e, 0xfc00003f, RD_R
|RD_S
|RD_T
|WR_D
|FP_D
, I5
},
662 {"msub", "s,t", 0x0000001e, 0xfc00ffff, RD_s
|RD_t
|WR_HILO
, L1
},
663 {"msub", "s,t", 0x70000004, 0xfc00ffff, RD_s
|RD_t
|MOD_HILO
, I32
},
664 {"msubu", "s,t", 0x0000001f, 0xfc00ffff, RD_s
|RD_t
|WR_HILO
, L1
},
665 {"msubu", "s,t", 0x70000005, 0xfc00ffff, RD_s
|RD_t
|MOD_HILO
, I32
},
666 {"mtpc", "t,P", 0x4080c801, 0xffe0ffc1, COD
|RD_t
|WR_C0
, M1
},
667 {"mtps", "t,P", 0x4080c800, 0xffe0ffc1, COD
|RD_t
|WR_C0
, M1
},
668 {"mtc0", "t,G", 0x40800000, 0xffe007ff, COD
|RD_t
|WR_C0
|WR_CC
, I1
},
669 {"mtc0", "t,G,H", 0x40800000, 0xffe007f8, COD
|RD_t
|WR_C0
|WR_CC
, I32
},
670 {"mtc1", "t,S", 0x44800000, 0xffe007ff, COD
|RD_t
|WR_S
|FP_S
, I1
},
671 {"mtc1", "t,G", 0x44800000, 0xffe007ff, COD
|RD_t
|WR_S
|FP_S
, I1
},
672 {"mtc2", "t,G", 0x48800000, 0xffe007ff, COD
|RD_t
|WR_C2
|WR_CC
, I1
},
673 {"mtc2", "t,G,H", 0x48800000, 0xffe007f8, COD
|RD_t
|WR_C2
|WR_CC
, I32
},
674 {"mtc3", "t,G", 0x4c800000, 0xffe007ff, COD
|RD_t
|WR_C3
|WR_CC
, I1
},
675 {"mtc3", "t,G,H", 0x4c800000, 0xffe007f8, COD
|RD_t
|WR_C3
|WR_CC
, I32
},
676 {"mthi", "s", 0x00000011, 0xfc1fffff, RD_s
|WR_HI
, I1
},
677 {"mtlo", "s", 0x00000013, 0xfc1fffff, RD_s
|WR_LO
, I1
},
678 {"mul.d", "D,V,T", 0x46200002, 0xffe0003f, WR_D
|RD_S
|RD_T
|FP_D
, I1
},
679 {"mul.s", "D,V,T", 0x46000002, 0xffe0003f, WR_D
|RD_S
|RD_T
|FP_S
, I1
},
680 {"mul.ps", "D,V,T", 0x46c00002, 0xffe0003f, WR_D
|RD_S
|RD_T
|FP_D
, I5
},
681 {"mul", "d,v,t", 0x70000002, 0xfc0007ff, WR_d
|RD_s
|RD_t
|WR_HILO
, I32
|P3
},
682 {"mul", "d,v,t", 0, (int) M_MUL
, INSN_MACRO
, I1
},
683 {"mul", "d,v,I", 0, (int) M_MUL_I
, INSN_MACRO
, I1
},
684 {"mulo", "d,v,t", 0, (int) M_MULO
, INSN_MACRO
, I1
},
685 {"mulo", "d,v,I", 0, (int) M_MULO_I
, INSN_MACRO
, I1
},
686 {"mulou", "d,v,t", 0, (int) M_MULOU
, INSN_MACRO
, I1
},
687 {"mulou", "d,v,I", 0, (int) M_MULOU_I
, INSN_MACRO
, I1
},
688 {"mulr.ps", "D,S,T", 0x46c0001a, 0xffe0003f, WR_D
|RD_S
|RD_T
|FP_D
, M3D
},
689 {"mult", "s,t", 0x00000018, 0xfc00ffff, RD_s
|RD_t
|WR_HILO
|IS_M
, I1
},
690 {"mult", "d,s,t", 0x00000018, 0xfc0007ff, RD_s
|RD_t
|WR_HILO
|WR_d
|IS_M
, G1
},
691 {"multu", "s,t", 0x00000019, 0xfc00ffff, RD_s
|RD_t
|WR_HILO
|IS_M
, I1
},
692 {"multu", "d,s,t", 0x00000019, 0xfc0007ff, RD_s
|RD_t
|WR_HILO
|WR_d
|IS_M
, G1
},
693 {"neg", "d,w", 0x00000022, 0xffe007ff, WR_d
|RD_t
, I1
}, /* sub 0 */
694 {"negu", "d,w", 0x00000023, 0xffe007ff, WR_d
|RD_t
, I1
}, /* subu 0 */
695 {"neg.d", "D,V", 0x46200007, 0xffff003f, WR_D
|RD_S
|FP_D
, I1
},
696 {"neg.s", "D,V", 0x46000007, 0xffff003f, WR_D
|RD_S
|FP_S
, I1
},
697 {"neg.ps", "D,V", 0x46c00007, 0xffff003f, WR_D
|RD_S
|FP_D
, I5
},
698 {"nmadd.d", "D,R,S,T", 0x4c000031, 0xfc00003f, RD_R
|RD_S
|RD_T
|WR_D
|FP_D
, I4
},
699 {"nmadd.s", "D,R,S,T", 0x4c000030, 0xfc00003f, RD_R
|RD_S
|RD_T
|WR_D
|FP_S
, I4
},
700 {"nmadd.ps","D,R,S,T", 0x4c000036, 0xfc00003f, RD_R
|RD_S
|RD_T
|WR_D
|FP_D
, I5
},
701 {"nmsub.d", "D,R,S,T", 0x4c000039, 0xfc00003f, RD_R
|RD_S
|RD_T
|WR_D
|FP_D
, I4
},
702 {"nmsub.s", "D,R,S,T", 0x4c000038, 0xfc00003f, RD_R
|RD_S
|RD_T
|WR_D
|FP_S
, I4
},
703 {"nmsub.ps","D,R,S,T", 0x4c00003e, 0xfc00003f, RD_R
|RD_S
|RD_T
|WR_D
|FP_D
, I5
},
704 /* nop is at the start of the table. */
705 {"nor", "d,v,t", 0x00000027, 0xfc0007ff, WR_d
|RD_s
|RD_t
, I1
},
706 {"nor", "t,r,I", 0, (int) M_NOR_I
, INSN_MACRO
, I1
},
707 {"not", "d,v", 0x00000027, 0xfc1f07ff, WR_d
|RD_s
|RD_t
, I1
},/*nor d,s,0*/
708 {"or", "d,v,t", 0x00000025, 0xfc0007ff, WR_d
|RD_s
|RD_t
, I1
},
709 {"or", "t,r,I", 0, (int) M_OR_I
, INSN_MACRO
, I1
},
710 {"ori", "t,r,i", 0x34000000, 0xfc000000, WR_t
|RD_s
, I1
},
712 {"pll.ps", "D,V,T", 0x46c0002c, 0xffe0003f, WR_D
|RD_S
|RD_T
|FP_D
, I5
},
713 {"plu.ps", "D,V,T", 0x46c0002d, 0xffe0003f, WR_D
|RD_S
|RD_T
|FP_D
, I5
},
715 /* pref and prefx are at the start of the table. */
717 {"pul.ps", "D,V,T", 0x46c0002e, 0xffe0003f, WR_D
|RD_S
|RD_T
|FP_D
, I5
},
718 {"puu.ps", "D,V,T", 0x46c0002f, 0xffe0003f, WR_D
|RD_S
|RD_T
|FP_D
, I5
},
720 {"recip.d", "D,S", 0x46200015, 0xffff003f, WR_D
|RD_S
|FP_D
, I4
},
721 {"recip.ps","D,S", 0x46c00015, 0xffff003f, WR_D
|RD_S
|FP_D
, SB1
},
722 {"recip.s", "D,S", 0x46000015, 0xffff003f, WR_D
|RD_S
|FP_S
, I4
},
723 {"recip1.d", "D,S", 0x4620001d, 0xffff003f, WR_D
|RD_S
|FP_D
, M3D
},
724 {"recip1.ps", "D,S", 0x46c0001d, 0xffff003f, WR_D
|RD_S
|FP_S
, M3D
},
725 {"recip1.s", "D,S", 0x4600001d, 0xffff003f, WR_D
|RD_S
|FP_S
, M3D
},
726 {"recip2.d", "D,S,T", 0x4620001c, 0xffe0003f, WR_D
|RD_S
|RD_T
|FP_D
, M3D
},
727 {"recip2.ps", "D,S,T", 0x46c0001c, 0xffe0003f, WR_D
|RD_S
|RD_T
|FP_S
, M3D
},
728 {"recip2.s", "D,S,T", 0x4600001c, 0xffe0003f, WR_D
|RD_S
|RD_T
|FP_S
, M3D
},
729 {"rem", "z,s,t", 0x0000001a, 0xfc00ffff, RD_s
|RD_t
|WR_HILO
, I1
},
730 {"rem", "d,v,t", 0, (int) M_REM_3
, INSN_MACRO
, I1
},
731 {"rem", "d,v,I", 0, (int) M_REM_3I
, INSN_MACRO
, I1
},
732 {"remu", "z,s,t", 0x0000001b, 0xfc00ffff, RD_s
|RD_t
|WR_HILO
, I1
},
733 {"remu", "d,v,t", 0, (int) M_REMU_3
, INSN_MACRO
, I1
},
734 {"remu", "d,v,I", 0, (int) M_REMU_3I
, INSN_MACRO
, I1
},
735 {"rfe", "", 0x42000010, 0xffffffff, 0, I1
|T3
},
736 {"rol", "d,v,t", 0, (int) M_ROL
, INSN_MACRO
, I1
},
737 {"rol", "d,v,I", 0, (int) M_ROL_I
, INSN_MACRO
, I1
},
738 {"ror", "d,v,t", 0, (int) M_ROR
, INSN_MACRO
, I1
},
739 {"ror", "d,v,I", 0, (int) M_ROR_I
, INSN_MACRO
, I1
},
740 {"round.l.d", "D,S", 0x46200008, 0xffff003f, WR_D
|RD_S
|FP_D
, I3
},
741 {"round.l.s", "D,S", 0x46000008, 0xffff003f, WR_D
|RD_S
|FP_S
, I3
},
742 {"round.w.d", "D,S", 0x4620000c, 0xffff003f, WR_D
|RD_S
|FP_D
, I2
},
743 {"round.w.s", "D,S", 0x4600000c, 0xffff003f, WR_D
|RD_S
|FP_S
, I2
},
744 {"rsqrt.d", "D,S", 0x46200016, 0xffff003f, WR_D
|RD_S
|FP_D
, I4
},
745 {"rsqrt.ps","D,S", 0x46c00016, 0xffff003f, WR_D
|RD_S
|FP_D
, SB1
},
746 {"rsqrt.s", "D,S", 0x46000016, 0xffff003f, WR_D
|RD_S
|FP_S
, I4
},
747 {"rsqrt1.d", "D,S", 0x4620001e, 0xffff003f, WR_D
|RD_S
|FP_D
, M3D
},
748 {"rsqrt1.ps", "D,S", 0x46c0001e, 0xffff003f, WR_D
|RD_S
|FP_S
, M3D
},
749 {"rsqrt1.s", "D,S", 0x4600001e, 0xffff003f, WR_D
|RD_S
|FP_S
, M3D
},
750 {"rsqrt2.d", "D,S,T", 0x4620001f, 0xffe0003f, WR_D
|RD_S
|RD_T
|FP_D
, M3D
},
751 {"rsqrt2.ps", "D,S,T", 0x46c0001f, 0xffe0003f, WR_D
|RD_S
|RD_T
|FP_S
, M3D
},
752 {"rsqrt2.s", "D,S,T", 0x4600001f, 0xffe0003f, WR_D
|RD_S
|RD_T
|FP_S
, M3D
},
753 {"sb", "t,o(b)", 0xa0000000, 0xfc000000, SM
|RD_t
|RD_b
, I1
},
754 {"sb", "t,A(b)", 0, (int) M_SB_AB
, INSN_MACRO
, I1
},
755 {"sc", "t,o(b)", 0xe0000000, 0xfc000000, SM
|RD_t
|WR_t
|RD_b
, I2
},
756 {"sc", "t,A(b)", 0, (int) M_SC_AB
, INSN_MACRO
, I2
},
757 {"scd", "t,o(b)", 0xf0000000, 0xfc000000, SM
|RD_t
|WR_t
|RD_b
, I3
},
758 {"scd", "t,A(b)", 0, (int) M_SCD_AB
, INSN_MACRO
, I3
},
759 {"sd", "t,o(b)", 0xfc000000, 0xfc000000, SM
|RD_t
|RD_b
, I3
},
760 {"sd", "t,o(b)", 0, (int) M_SD_OB
, INSN_MACRO
, I1
},
761 {"sd", "t,A(b)", 0, (int) M_SD_AB
, INSN_MACRO
, I1
},
762 {"sdbbp", "", 0x0000000e, 0xffffffff, TRAP
, G2
},
763 {"sdbbp", "c", 0x0000000e, 0xfc00ffff, TRAP
, G2
},
764 {"sdbbp", "c,q", 0x0000000e, 0xfc00003f, TRAP
, G2
},
765 {"sdbbp", "", 0x7000003f, 0xffffffff, TRAP
, I32
},
766 {"sdbbp", "B", 0x7000003f, 0xfc00003f, TRAP
, I32
},
767 {"sdc1", "T,o(b)", 0xf4000000, 0xfc000000, SM
|RD_T
|RD_b
|FP_D
, I2
},
768 {"sdc1", "E,o(b)", 0xf4000000, 0xfc000000, SM
|RD_T
|RD_b
|FP_D
, I2
},
769 {"sdc1", "T,A(b)", 0, (int) M_SDC1_AB
, INSN_MACRO
, I2
},
770 {"sdc1", "E,A(b)", 0, (int) M_SDC1_AB
, INSN_MACRO
, I2
},
771 {"sdc2", "E,o(b)", 0xf8000000, 0xfc000000, SM
|RD_C2
|RD_b
, I2
},
772 {"sdc2", "E,A(b)", 0, (int) M_SDC2_AB
, INSN_MACRO
, I2
},
773 {"sdc3", "E,o(b)", 0xfc000000, 0xfc000000, SM
|RD_C3
|RD_b
, I2
},
774 {"sdc3", "E,A(b)", 0, (int) M_SDC3_AB
, INSN_MACRO
, I2
},
775 {"s.d", "T,o(b)", 0xf4000000, 0xfc000000, SM
|RD_T
|RD_b
|FP_D
, I2
},
776 {"s.d", "T,o(b)", 0, (int) M_S_DOB
, INSN_MACRO
, I1
},
777 {"s.d", "T,A(b)", 0, (int) M_S_DAB
, INSN_MACRO
, I1
},
778 {"sdl", "t,o(b)", 0xb0000000, 0xfc000000, SM
|RD_t
|RD_b
, I3
},
779 {"sdl", "t,A(b)", 0, (int) M_SDL_AB
, INSN_MACRO
, I3
},
780 {"sdr", "t,o(b)", 0xb4000000, 0xfc000000, SM
|RD_t
|RD_b
, I3
},
781 {"sdr", "t,A(b)", 0, (int) M_SDR_AB
, INSN_MACRO
, I3
},
782 {"sdxc1", "S,t(b)", 0x4c000009, 0xfc0007ff, SM
|RD_S
|RD_t
|RD_b
, I4
},
783 {"selsl", "d,v,t", 0x00000005, 0xfc0007ff, WR_d
|RD_s
|RD_t
, L1
},
784 {"selsr", "d,v,t", 0x00000001, 0xfc0007ff, WR_d
|RD_s
|RD_t
, L1
},
785 {"seq", "d,v,t", 0, (int) M_SEQ
, INSN_MACRO
, I1
},
786 {"seq", "d,v,I", 0, (int) M_SEQ_I
, INSN_MACRO
, I1
},
787 {"sge", "d,v,t", 0, (int) M_SGE
, INSN_MACRO
, I1
},
788 {"sge", "d,v,I", 0, (int) M_SGE_I
, INSN_MACRO
, I1
},
789 {"sgeu", "d,v,t", 0, (int) M_SGEU
, INSN_MACRO
, I1
},
790 {"sgeu", "d,v,I", 0, (int) M_SGEU_I
, INSN_MACRO
, I1
},
791 {"sgt", "d,v,t", 0, (int) M_SGT
, INSN_MACRO
, I1
},
792 {"sgt", "d,v,I", 0, (int) M_SGT_I
, INSN_MACRO
, I1
},
793 {"sgtu", "d,v,t", 0, (int) M_SGTU
, INSN_MACRO
, I1
},
794 {"sgtu", "d,v,I", 0, (int) M_SGTU_I
, INSN_MACRO
, I1
},
795 {"sh", "t,o(b)", 0xa4000000, 0xfc000000, SM
|RD_t
|RD_b
, I1
},
796 {"sh", "t,A(b)", 0, (int) M_SH_AB
, INSN_MACRO
, I1
},
797 {"sle", "d,v,t", 0, (int) M_SLE
, INSN_MACRO
, I1
},
798 {"sle", "d,v,I", 0, (int) M_SLE_I
, INSN_MACRO
, I1
},
799 {"sleu", "d,v,t", 0, (int) M_SLEU
, INSN_MACRO
, I1
},
800 {"sleu", "d,v,I", 0, (int) M_SLEU_I
, INSN_MACRO
, I1
},
801 {"sllv", "d,t,s", 0x00000004, 0xfc0007ff, WR_d
|RD_t
|RD_s
, I1
},
802 {"sll", "d,w,s", 0x00000004, 0xfc0007ff, WR_d
|RD_t
|RD_s
, I1
}, /* sllv */
803 {"sll", "d,w,<", 0x00000000, 0xffe0003f, WR_d
|RD_t
, I1
},
804 {"slt", "d,v,t", 0x0000002a, 0xfc0007ff, WR_d
|RD_s
|RD_t
, I1
},
805 {"slt", "d,v,I", 0, (int) M_SLT_I
, INSN_MACRO
, I1
},
806 {"slti", "t,r,j", 0x28000000, 0xfc000000, WR_t
|RD_s
, I1
},
807 {"sltiu", "t,r,j", 0x2c000000, 0xfc000000, WR_t
|RD_s
, I1
},
808 {"sltu", "d,v,t", 0x0000002b, 0xfc0007ff, WR_d
|RD_s
|RD_t
, I1
},
809 {"sltu", "d,v,I", 0, (int) M_SLTU_I
, INSN_MACRO
, I1
},
810 {"sne", "d,v,t", 0, (int) M_SNE
, INSN_MACRO
, I1
},
811 {"sne", "d,v,I", 0, (int) M_SNE_I
, INSN_MACRO
, I1
},
812 {"sqrt.d", "D,S", 0x46200004, 0xffff003f, WR_D
|RD_S
|FP_D
, I2
},
813 {"sqrt.s", "D,S", 0x46000004, 0xffff003f, WR_D
|RD_S
|FP_S
, I2
},
814 {"sqrt.ps", "D,S", 0x46c00004, 0xffff003f, WR_D
|RD_S
|FP_D
, SB1
},
815 {"srav", "d,t,s", 0x00000007, 0xfc0007ff, WR_d
|RD_t
|RD_s
, I1
},
816 {"sra", "d,w,s", 0x00000007, 0xfc0007ff, WR_d
|RD_t
|RD_s
, I1
}, /* srav */
817 {"sra", "d,w,<", 0x00000003, 0xffe0003f, WR_d
|RD_t
, I1
},
818 {"srlv", "d,t,s", 0x00000006, 0xfc0007ff, WR_d
|RD_t
|RD_s
, I1
},
819 {"srl", "d,w,s", 0x00000006, 0xfc0007ff, WR_d
|RD_t
|RD_s
, I1
}, /* srlv */
820 {"srl", "d,w,<", 0x00000002, 0xffe0003f, WR_d
|RD_t
, I1
},
821 /* ssnop is at the start of the table. */
822 {"standby", "", 0x42000021, 0xffffffff, 0, V1
},
823 {"sub", "d,v,t", 0x00000022, 0xfc0007ff, WR_d
|RD_s
|RD_t
, I1
},
824 {"sub", "d,v,I", 0, (int) M_SUB_I
, INSN_MACRO
, I1
},
825 {"sub.d", "D,V,T", 0x46200001, 0xffe0003f, WR_D
|RD_S
|RD_T
|FP_D
, I1
},
826 {"sub.s", "D,V,T", 0x46000001, 0xffe0003f, WR_D
|RD_S
|RD_T
|FP_S
, I1
},
827 {"sub.ps", "D,V,T", 0x46c00001, 0xffe0003f, WR_D
|RD_S
|RD_T
|FP_D
, I5
},
828 {"subu", "d,v,t", 0x00000023, 0xfc0007ff, WR_d
|RD_s
|RD_t
, I1
},
829 {"subu", "d,v,I", 0, (int) M_SUBU_I
, INSN_MACRO
, I1
},
830 {"suspend", "", 0x42000022, 0xffffffff, 0, V1
},
831 {"suxc1", "S,t(b)", 0x4c00000d, 0xfc0007ff, SM
|RD_S
|RD_t
|RD_b
, I5
},
832 {"sw", "t,o(b)", 0xac000000, 0xfc000000, SM
|RD_t
|RD_b
, I1
},
833 {"sw", "t,A(b)", 0, (int) M_SW_AB
, INSN_MACRO
, I1
},
834 {"swc0", "E,o(b)", 0xe0000000, 0xfc000000, SM
|RD_C0
|RD_b
, I1
},
835 {"swc0", "E,A(b)", 0, (int) M_SWC0_AB
, INSN_MACRO
, I1
},
836 {"swc1", "T,o(b)", 0xe4000000, 0xfc000000, SM
|RD_T
|RD_b
|FP_S
, I1
},
837 {"swc1", "E,o(b)", 0xe4000000, 0xfc000000, SM
|RD_T
|RD_b
|FP_S
, I1
},
838 {"swc1", "T,A(b)", 0, (int) M_SWC1_AB
, INSN_MACRO
, I1
},
839 {"swc1", "E,A(b)", 0, (int) M_SWC1_AB
, INSN_MACRO
, I1
},
840 {"s.s", "T,o(b)", 0xe4000000, 0xfc000000, SM
|RD_T
|RD_b
|FP_S
, I1
}, /* swc1 */
841 {"s.s", "T,A(b)", 0, (int) M_SWC1_AB
, INSN_MACRO
, I1
},
842 {"swc2", "E,o(b)", 0xe8000000, 0xfc000000, SM
|RD_C2
|RD_b
, I1
},
843 {"swc2", "E,A(b)", 0, (int) M_SWC2_AB
, INSN_MACRO
, I1
},
844 {"swc3", "E,o(b)", 0xec000000, 0xfc000000, SM
|RD_C3
|RD_b
, I1
},
845 {"swc3", "E,A(b)", 0, (int) M_SWC3_AB
, INSN_MACRO
, I1
},
846 {"swl", "t,o(b)", 0xa8000000, 0xfc000000, SM
|RD_t
|RD_b
, I1
},
847 {"swl", "t,A(b)", 0, (int) M_SWL_AB
, INSN_MACRO
, I1
},
848 {"scache", "t,o(b)", 0xa8000000, 0xfc000000, RD_t
|RD_b
, I2
}, /* same */
849 {"scache", "t,A(b)", 0, (int) M_SWL_AB
, INSN_MACRO
, I2
}, /* as swl */
850 {"swr", "t,o(b)", 0xb8000000, 0xfc000000, SM
|RD_t
|RD_b
, I1
},
851 {"swr", "t,A(b)", 0, (int) M_SWR_AB
, INSN_MACRO
, I1
},
852 {"invalidate", "t,o(b)",0xb8000000, 0xfc000000, RD_t
|RD_b
, I2
}, /* same */
853 {"invalidate", "t,A(b)",0, (int) M_SWR_AB
, INSN_MACRO
, I2
}, /* as swr */
854 {"swxc1", "S,t(b)", 0x4c000008, 0xfc0007ff, SM
|RD_S
|RD_t
|RD_b
, I4
},
855 {"sync", "", 0x0000000f, 0xffffffff, INSN_SYNC
, I2
|G1
},
856 {"sync.p", "", 0x0000040f, 0xffffffff, INSN_SYNC
, I2
},
857 {"sync.l", "", 0x0000000f, 0xffffffff, INSN_SYNC
, I2
},
858 {"syscall", "", 0x0000000c, 0xffffffff, TRAP
, I1
},
859 {"syscall", "B", 0x0000000c, 0xfc00003f, TRAP
, I1
},
860 {"teqi", "s,j", 0x040c0000, 0xfc1f0000, RD_s
|TRAP
, I2
},
861 {"teq", "s,t", 0x00000034, 0xfc00ffff, RD_s
|RD_t
|TRAP
, I2
},
862 {"teq", "s,t,q", 0x00000034, 0xfc00003f, RD_s
|RD_t
|TRAP
, I2
},
863 {"teq", "s,j", 0x040c0000, 0xfc1f0000, RD_s
|TRAP
, I2
}, /* teqi */
864 {"teq", "s,I", 0, (int) M_TEQ_I
, INSN_MACRO
, I2
},
865 {"tgei", "s,j", 0x04080000, 0xfc1f0000, RD_s
|TRAP
, I2
},
866 {"tge", "s,t", 0x00000030, 0xfc00ffff, RD_s
|RD_t
|TRAP
, I2
},
867 {"tge", "s,t,q", 0x00000030, 0xfc00003f, RD_s
|RD_t
|TRAP
, I2
},
868 {"tge", "s,j", 0x04080000, 0xfc1f0000, RD_s
|TRAP
, I2
}, /* tgei */
869 {"tge", "s,I", 0, (int) M_TGE_I
, INSN_MACRO
, I2
},
870 {"tgeiu", "s,j", 0x04090000, 0xfc1f0000, RD_s
|TRAP
, I2
},
871 {"tgeu", "s,t", 0x00000031, 0xfc00ffff, RD_s
|RD_t
|TRAP
, I2
},
872 {"tgeu", "s,t,q", 0x00000031, 0xfc00003f, RD_s
|RD_t
|TRAP
, I2
},
873 {"tgeu", "s,j", 0x04090000, 0xfc1f0000, RD_s
|TRAP
, I2
}, /* tgeiu */
874 {"tgeu", "s,I", 0, (int) M_TGEU_I
, INSN_MACRO
, I2
},
875 {"tlbp", "", 0x42000008, 0xffffffff, INSN_TLB
, I1
},
876 {"tlbr", "", 0x42000001, 0xffffffff, INSN_TLB
, I1
},
877 {"tlbwi", "", 0x42000002, 0xffffffff, INSN_TLB
, I1
},
878 {"tlbwr", "", 0x42000006, 0xffffffff, INSN_TLB
, I1
},
879 {"tlti", "s,j", 0x040a0000, 0xfc1f0000, RD_s
|TRAP
, I2
},
880 {"tlt", "s,t", 0x00000032, 0xfc00ffff, RD_s
|RD_t
|TRAP
, I2
},
881 {"tlt", "s,t,q", 0x00000032, 0xfc00003f, RD_s
|RD_t
|TRAP
, I2
},
882 {"tlt", "s,j", 0x040a0000, 0xfc1f0000, RD_s
|TRAP
, I2
}, /* tlti */
883 {"tlt", "s,I", 0, (int) M_TLT_I
, INSN_MACRO
, I2
},
884 {"tltiu", "s,j", 0x040b0000, 0xfc1f0000, RD_s
|TRAP
, I2
},
885 {"tltu", "s,t", 0x00000033, 0xfc00ffff, RD_s
|RD_t
|TRAP
, I2
},
886 {"tltu", "s,t,q", 0x00000033, 0xfc00003f, RD_s
|RD_t
|TRAP
, I2
},
887 {"tltu", "s,j", 0x040b0000, 0xfc1f0000, RD_s
|TRAP
, I2
}, /* tltiu */
888 {"tltu", "s,I", 0, (int) M_TLTU_I
, INSN_MACRO
, I2
},
889 {"tnei", "s,j", 0x040e0000, 0xfc1f0000, RD_s
|TRAP
, I2
},
890 {"tne", "s,t", 0x00000036, 0xfc00ffff, RD_s
|RD_t
|TRAP
, I2
},
891 {"tne", "s,t,q", 0x00000036, 0xfc00003f, RD_s
|RD_t
|TRAP
, I2
},
892 {"tne", "s,j", 0x040e0000, 0xfc1f0000, RD_s
|TRAP
, I2
}, /* tnei */
893 {"tne", "s,I", 0, (int) M_TNE_I
, INSN_MACRO
, I2
},
894 {"trunc.l.d", "D,S", 0x46200009, 0xffff003f, WR_D
|RD_S
|FP_D
, I3
},
895 {"trunc.l.s", "D,S", 0x46000009, 0xffff003f, WR_D
|RD_S
|FP_S
, I3
},
896 {"trunc.w.d", "D,S", 0x4620000d, 0xffff003f, WR_D
|RD_S
|FP_D
, I2
},
897 {"trunc.w.d", "D,S,x", 0x4620000d, 0xffff003f, WR_D
|RD_S
|FP_D
, I2
},
898 {"trunc.w.d", "D,S,t", 0, (int) M_TRUNCWD
, INSN_MACRO
, I1
},
899 {"trunc.w.s", "D,S", 0x4600000d, 0xffff003f, WR_D
|RD_S
|FP_S
, I2
},
900 {"trunc.w.s", "D,S,x", 0x4600000d, 0xffff003f, WR_D
|RD_S
|FP_S
, I2
},
901 {"trunc.w.s", "D,S,t", 0, (int) M_TRUNCWS
, INSN_MACRO
, I1
},
902 {"uld", "t,o(b)", 0, (int) M_ULD
, INSN_MACRO
, I3
},
903 {"uld", "t,A(b)", 0, (int) M_ULD_A
, INSN_MACRO
, I3
},
904 {"ulh", "t,o(b)", 0, (int) M_ULH
, INSN_MACRO
, I1
},
905 {"ulh", "t,A(b)", 0, (int) M_ULH_A
, INSN_MACRO
, I1
},
906 {"ulhu", "t,o(b)", 0, (int) M_ULHU
, INSN_MACRO
, I1
},
907 {"ulhu", "t,A(b)", 0, (int) M_ULHU_A
, INSN_MACRO
, I1
},
908 {"ulw", "t,o(b)", 0, (int) M_ULW
, INSN_MACRO
, I1
},
909 {"ulw", "t,A(b)", 0, (int) M_ULW_A
, INSN_MACRO
, I1
},
910 {"usd", "t,o(b)", 0, (int) M_USD
, INSN_MACRO
, I3
},
911 {"usd", "t,A(b)", 0, (int) M_USD_A
, INSN_MACRO
, I3
},
912 {"ush", "t,o(b)", 0, (int) M_USH
, INSN_MACRO
, I1
},
913 {"ush", "t,A(b)", 0, (int) M_USH_A
, INSN_MACRO
, I1
},
914 {"usw", "t,o(b)", 0, (int) M_USW
, INSN_MACRO
, I1
},
915 {"usw", "t,A(b)", 0, (int) M_USW_A
, INSN_MACRO
, I1
},
916 {"xor", "d,v,t", 0x00000026, 0xfc0007ff, WR_d
|RD_s
|RD_t
, I1
},
917 {"xor", "t,r,I", 0, (int) M_XOR_I
, INSN_MACRO
, I1
},
918 {"xori", "t,r,i", 0x38000000, 0xfc000000, WR_t
|RD_s
, I1
},
919 {"wait", "", 0x42000020, 0xffffffff, TRAP
, I3
|I32
},
920 {"wait", "J", 0x42000020, 0xfe00003f, TRAP
, I32
},
921 {"waiti", "", 0x42000020, 0xffffffff, TRAP
, L1
},
922 {"wb", "o(b)", 0xbc040000, 0xfc1f0000, SM
|RD_b
, L1
},
923 /* No hazard protection on coprocessor instructions--they shouldn't
924 change the state of the processor and if they do it's up to the
925 user to put in nops as necessary. These are at the end so that the
926 disassembler recognizes more specific versions first. */
927 {"c0", "C", 0x42000000, 0xfe000000, 0, I1
},
928 {"c1", "C", 0x46000000, 0xfe000000, 0, I1
},
929 {"c2", "C", 0x4a000000, 0xfe000000, 0, I1
},
930 {"c3", "C", 0x4e000000, 0xfe000000, 0, I1
},
931 {"cop0", "C", 0, (int) M_COP0
, INSN_MACRO
, I1
},
932 {"cop1", "C", 0, (int) M_COP1
, INSN_MACRO
, I1
},
933 {"cop2", "C", 0, (int) M_COP2
, INSN_MACRO
, I1
},
934 {"cop3", "C", 0, (int) M_COP3
, INSN_MACRO
, I1
},
936 /* Conflicts with the 4650's "mul" instruction. Nobody's using the
937 4010 any more, so move this insn out of the way. If the object
938 format gave us more info, we could do this right. */
939 {"addciu", "t,r,j", 0x70000000, 0xfc000000, WR_t
|RD_s
, L1
},
942 #define MIPS_NUM_OPCODES \
943 ((sizeof mips_builtin_opcodes) / (sizeof (mips_builtin_opcodes[0])))
944 const int bfd_mips_num_builtin_opcodes
= MIPS_NUM_OPCODES
;
946 /* const removed from the following to allow for dynamic extensions to the
947 * built-in instruction set. */
948 struct mips_opcode
*mips_opcodes
=
949 (struct mips_opcode
*) mips_builtin_opcodes
;
950 int bfd_mips_num_opcodes
= MIPS_NUM_OPCODES
;
951 #undef MIPS_NUM_OPCODES