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bfd/
[binutils.git] / gas / config / tc-arm.c
blobe98733d6dd09641fb3758f33dea9f378765a034e
1 /* tc-arm.c -- Assemble for the ARM
2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
3 2004, 2005
4 Free Software Foundation, Inc.
5 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
6 Modified by David Taylor (dtaylor@armltd.co.uk)
7 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
8 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
9 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
10
11 This file is part of GAS, the GNU Assembler.
12
13 GAS is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 2, or (at your option)
16 any later version.
17
18 GAS is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
22
23 You should have received a copy of the GNU General Public License
24 along with GAS; see the file COPYING. If not, write to the Free
25 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
26 02110-1301, USA. */
27
28 #include <string.h>
29 #define NO_RELOC 0
30 #include "as.h"
31 #include "safe-ctype.h"
32
33 /* Need TARGET_CPU. */
34 #include "config.h"
35 #include "subsegs.h"
36 #include "obstack.h"
37 #include "symbols.h"
38 #include "listing.h"
39
40 #include "opcode/arm.h"
41
42 #ifdef OBJ_ELF
43 #include "elf/arm.h"
44 #include "dwarf2dbg.h"
45 #include "dw2gencfi.h"
46 #endif
47
48 /* XXX Set this to 1 after the next binutils release. */
49 #define WARN_DEPRECATED 0
50
51 #ifdef OBJ_ELF
52 /* Must be at least the size of the largest unwind opcode (currently two). */
53 #define ARM_OPCODE_CHUNK_SIZE 8
54
55 /* This structure holds the unwinding state. */
56
57 static struct
58 {
59 symbolS * proc_start;
60 symbolS * table_entry;
61 symbolS * personality_routine;
62 int personality_index;
63 /* The segment containing the function. */
64 segT saved_seg;
65 subsegT saved_subseg;
66 /* Opcodes generated from this function. */
67 unsigned char * opcodes;
68 int opcode_count;
69 int opcode_alloc;
70 /* The number of bytes pushed to the stack. */
71 offsetT frame_size;
72 /* We don't add stack adjustment opcodes immediately so that we can merge
73 multiple adjustments. We can also omit the final adjustment
74 when using a frame pointer. */
75 offsetT pending_offset;
76 /* These two fields are set by both unwind_movsp and unwind_setfp. They
77 hold the reg+offset to use when restoring sp from a frame pointer. */
78 offsetT fp_offset;
79 int fp_reg;
80 /* Nonzero if an unwind_setfp directive has been seen. */
81 unsigned fp_used:1;
82 /* Nonzero if the last opcode restores sp from fp_reg. */
83 unsigned sp_restored:1;
84 } unwind;
85
86 /* Bit N indicates that an R_ARM_NONE relocation has been output for
87 __aeabi_unwind_cpp_prN already if set. This enables dependencies to be
88 emitted only once per section, to save unnecessary bloat. */
89 static unsigned int marked_pr_dependency = 0;
90
91 #endif /* OBJ_ELF */
92
93 enum arm_float_abi
94 {
95 ARM_FLOAT_ABI_HARD,
96 ARM_FLOAT_ABI_SOFTFP,
97 ARM_FLOAT_ABI_SOFT
98 };
99
100 /* Types of processor to assemble for. */
101 #ifndef CPU_DEFAULT
102 #if defined __XSCALE__
103 #define CPU_DEFAULT ARM_ARCH_XSCALE
104 #else
105 #if defined __thumb__
106 #define CPU_DEFAULT ARM_ARCH_V5T
107 #endif
108 #endif
109 #endif
110
111 #ifndef FPU_DEFAULT
112 # ifdef TE_LINUX
113 # define FPU_DEFAULT FPU_ARCH_FPA
114 # elif defined (TE_NetBSD)
115 # ifdef OBJ_ELF
116 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
117 # else
118 /* Legacy a.out format. */
119 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
120 # endif
121 # elif defined (TE_VXWORKS)
122 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
123 # else
124 /* For backwards compatibility, default to FPA. */
125 # define FPU_DEFAULT FPU_ARCH_FPA
126 # endif
127 #endif /* ifndef FPU_DEFAULT */
128
129 #define streq(a, b) (strcmp (a, b) == 0)
130
131 static arm_feature_set cpu_variant;
132 static arm_feature_set arm_arch_used;
133 static arm_feature_set thumb_arch_used;
134
135 /* Flags stored in private area of BFD structure. */
136 static int uses_apcs_26 = FALSE;
137 static int atpcs = FALSE;
138 static int support_interwork = FALSE;
139 static int uses_apcs_float = FALSE;
140 static int pic_code = FALSE;
141
142 /* Variables that we set while parsing command-line options. Once all
143 options have been read we re-process these values to set the real
144 assembly flags. */
145 static const arm_feature_set *legacy_cpu = NULL;
146 static const arm_feature_set *legacy_fpu = NULL;
147
148 static const arm_feature_set *mcpu_cpu_opt = NULL;
149 static const arm_feature_set *mcpu_fpu_opt = NULL;
150 static const arm_feature_set *march_cpu_opt = NULL;
151 static const arm_feature_set *march_fpu_opt = NULL;
152 static const arm_feature_set *mfpu_opt = NULL;
153
154 /* Constants for known architecture features. */
155 static const arm_feature_set fpu_default = FPU_DEFAULT;
156 static const arm_feature_set fpu_arch_vfp_v1 = FPU_ARCH_VFP_V1;
157 static const arm_feature_set fpu_arch_vfp_v2 = FPU_ARCH_VFP_V2;
158 static const arm_feature_set fpu_arch_fpa = FPU_ARCH_FPA;
159 static const arm_feature_set fpu_any_hard = FPU_ANY_HARD;
160 static const arm_feature_set fpu_arch_maverick = FPU_ARCH_MAVERICK;
161 static const arm_feature_set fpu_endian_pure = FPU_ARCH_ENDIAN_PURE;
162
163 #ifdef CPU_DEFAULT
164 static const arm_feature_set cpu_default = CPU_DEFAULT;
165 #endif
166
167 static const arm_feature_set arm_ext_v1 = ARM_FEATURE (ARM_EXT_V1, 0);
168 static const arm_feature_set arm_ext_v2 = ARM_FEATURE (ARM_EXT_V1, 0);
169 static const arm_feature_set arm_ext_v2s = ARM_FEATURE (ARM_EXT_V2S, 0);
170 static const arm_feature_set arm_ext_v3 = ARM_FEATURE (ARM_EXT_V3, 0);
171 static const arm_feature_set arm_ext_v3m = ARM_FEATURE (ARM_EXT_V3M, 0);
172 static const arm_feature_set arm_ext_v4 = ARM_FEATURE (ARM_EXT_V4, 0);
173 static const arm_feature_set arm_ext_v4t = ARM_FEATURE (ARM_EXT_V4T, 0);
174 static const arm_feature_set arm_ext_v5 = ARM_FEATURE (ARM_EXT_V5, 0);
175 static const arm_feature_set arm_ext_v4t_5 =
176 ARM_FEATURE (ARM_EXT_V4T | ARM_EXT_V5, 0);
177 static const arm_feature_set arm_ext_v5t = ARM_FEATURE (ARM_EXT_V5T, 0);
178 static const arm_feature_set arm_ext_v5e = ARM_FEATURE (ARM_EXT_V5E, 0);
179 static const arm_feature_set arm_ext_v5exp = ARM_FEATURE (ARM_EXT_V5ExP, 0);
180 static const arm_feature_set arm_ext_v5j = ARM_FEATURE (ARM_EXT_V5J, 0);
181 static const arm_feature_set arm_ext_v6 = ARM_FEATURE (ARM_EXT_V6, 0);
182 static const arm_feature_set arm_ext_v6k = ARM_FEATURE (ARM_EXT_V6K, 0);
183 static const arm_feature_set arm_ext_v6z = ARM_FEATURE (ARM_EXT_V6Z, 0);
184 static const arm_feature_set arm_ext_v6t2 = ARM_FEATURE (ARM_EXT_V6T2, 0);
185 static const arm_feature_set arm_ext_v6_notm = ARM_FEATURE (ARM_EXT_V6_NOTM, 0);
186 static const arm_feature_set arm_ext_div = ARM_FEATURE (ARM_EXT_DIV, 0);
187 static const arm_feature_set arm_ext_v7 = ARM_FEATURE (ARM_EXT_V7, 0);
188 static const arm_feature_set arm_ext_v7a = ARM_FEATURE (ARM_EXT_V7A, 0);
189 static const arm_feature_set arm_ext_v7r = ARM_FEATURE (ARM_EXT_V7R, 0);
190 static const arm_feature_set arm_ext_v7m = ARM_FEATURE (ARM_EXT_V7M, 0);
191
192 static const arm_feature_set arm_arch_any = ARM_ANY;
193 static const arm_feature_set arm_arch_full = ARM_FEATURE (-1, -1);
194 static const arm_feature_set arm_arch_t2 = ARM_ARCH_THUMB2;
195 static const arm_feature_set arm_arch_none = ARM_ARCH_NONE;
196
197 static const arm_feature_set arm_cext_iwmmxt =
198 ARM_FEATURE (0, ARM_CEXT_IWMMXT);
199 static const arm_feature_set arm_cext_xscale =
200 ARM_FEATURE (0, ARM_CEXT_XSCALE);
201 static const arm_feature_set arm_cext_maverick =
202 ARM_FEATURE (0, ARM_CEXT_MAVERICK);
203 static const arm_feature_set fpu_fpa_ext_v1 = ARM_FEATURE (0, FPU_FPA_EXT_V1);
204 static const arm_feature_set fpu_fpa_ext_v2 = ARM_FEATURE (0, FPU_FPA_EXT_V2);
205 static const arm_feature_set fpu_vfp_ext_v1xd =
206 ARM_FEATURE (0, FPU_VFP_EXT_V1xD);
207 static const arm_feature_set fpu_vfp_ext_v1 = ARM_FEATURE (0, FPU_VFP_EXT_V1);
208 static const arm_feature_set fpu_vfp_ext_v2 = ARM_FEATURE (0, FPU_VFP_EXT_V2);
209
210 static int mfloat_abi_opt = -1;
211 /* Record user cpu selection for object attributes. */
212 static arm_feature_set selected_cpu = ARM_ARCH_NONE;
213 /* Must be long enough to hold any of the names in arm_cpus. */
214 static char selected_cpu_name[16];
215 #ifdef OBJ_ELF
216 # ifdef EABI_DEFAULT
217 static int meabi_flags = EABI_DEFAULT;
218 # else
219 static int meabi_flags = EF_ARM_EABI_UNKNOWN;
220 # endif
221 #endif
222
223 #ifdef OBJ_ELF
224 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
225 symbolS * GOT_symbol;
226 #endif
227
228 /* 0: assemble for ARM,
229 1: assemble for Thumb,
230 2: assemble for Thumb even though target CPU does not support thumb
231 instructions. */
232 static int thumb_mode = 0;
233
234 /* If unified_syntax is true, we are processing the new unified
235 ARM/Thumb syntax. Important differences from the old ARM mode:
236
237 - Immediate operands do not require a # prefix.
238 - Conditional affixes always appear at the end of the
239 instruction. (For backward compatibility, those instructions
240 that formerly had them in the middle, continue to accept them
241 there.)
242 - The IT instruction may appear, and if it does is validated
243 against subsequent conditional affixes. It does not generate
244 machine code.
245
246 Important differences from the old Thumb mode:
247
248 - Immediate operands do not require a # prefix.
249 - Most of the V6T2 instructions are only available in unified mode.
250 - The .N and .W suffixes are recognized and honored (it is an error
251 if they cannot be honored).
252 - All instructions set the flags if and only if they have an 's' affix.
253 - Conditional affixes may be used. They are validated against
254 preceding IT instructions. Unlike ARM mode, you cannot use a
255 conditional affix except in the scope of an IT instruction. */
256
257 static bfd_boolean unified_syntax = FALSE;
258
259 struct arm_it
260 {
261 const char * error;
262 unsigned long instruction;
263 int size;
264 int size_req;
265 int cond;
266 /* Set to the opcode if the instruction needs relaxation.
267 Zero if the instruction is not relaxed. */
268 unsigned long relax;
269 struct
270 {
271 bfd_reloc_code_real_type type;
272 expressionS exp;
273 int pc_rel;
274 } reloc;
275
276 struct
277 {
278 unsigned reg;
279 signed int imm;
280 unsigned present : 1; /* Operand present. */
281 unsigned isreg : 1; /* Operand was a register. */
282 unsigned immisreg : 1; /* .imm field is a second register. */
283 unsigned hasreloc : 1; /* Operand has relocation suffix. */
284 unsigned writeback : 1; /* Operand has trailing ! */
285 unsigned preind : 1; /* Preindexed address. */
286 unsigned postind : 1; /* Postindexed address. */
287 unsigned negative : 1; /* Index register was negated. */
288 unsigned shifted : 1; /* Shift applied to operation. */
289 unsigned shift_kind : 3; /* Shift operation (enum shift_kind). */
290 } operands[6];
291 };
292
293 static struct arm_it inst;
294
295 #define NUM_FLOAT_VALS 8
296
297 const char * fp_const[] =
298 {
299 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
300 };
301
302 /* Number of littlenums required to hold an extended precision number. */
303 #define MAX_LITTLENUMS 6
304
305 LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS];
306
307 #define FAIL (-1)
308 #define SUCCESS (0)
309
310 #define SUFF_S 1
311 #define SUFF_D 2
312 #define SUFF_E 3
313 #define SUFF_P 4
314
315 #define CP_T_X 0x00008000
316 #define CP_T_Y 0x00400000
317
318 #define CONDS_BIT 0x00100000
319 #define LOAD_BIT 0x00100000
320
321 #define DOUBLE_LOAD_FLAG 0x00000001
322
323 struct asm_cond
324 {
325 const char * template;
326 unsigned long value;
327 };
328
329 #define COND_ALWAYS 0xE
330
331 struct asm_psr
332 {
333 const char *template;
334 unsigned long field;
335 };
336
337 struct asm_barrier_opt
338 {
339 const char *template;
340 unsigned long value;
341 };
342
343 /* The bit that distinguishes CPSR and SPSR. */
344 #define SPSR_BIT (1 << 22)
345
346 /* The individual PSR flag bits. */
347 #define PSR_c (1 << 16)
348 #define PSR_x (1 << 17)
349 #define PSR_s (1 << 18)
350 #define PSR_f (1 << 19)
351
352 struct reloc_entry
353 {
354 char *name;
355 bfd_reloc_code_real_type reloc;
356 };
357
358 enum vfp_sp_reg_pos
359 {
360 VFP_REG_Sd, VFP_REG_Sm, VFP_REG_Sn
361 };
362
363 enum vfp_ldstm_type
364 {
365 VFP_LDSTMIA, VFP_LDSTMDB, VFP_LDSTMIAX, VFP_LDSTMDBX
366 };
367
368 /* ARM register categories. This includes coprocessor numbers and various
369 architecture extensions' registers. */
370 enum arm_reg_type
371 {
372 REG_TYPE_RN,
373 REG_TYPE_CP,
374 REG_TYPE_CN,
375 REG_TYPE_FN,
376 REG_TYPE_VFS,
377 REG_TYPE_VFD,
378 REG_TYPE_VFC,
379 REG_TYPE_MVF,
380 REG_TYPE_MVD,
381 REG_TYPE_MVFX,
382 REG_TYPE_MVDX,
383 REG_TYPE_MVAX,
384 REG_TYPE_DSPSC,
385 REG_TYPE_MMXWR,
386 REG_TYPE_MMXWC,
387 REG_TYPE_MMXWCG,
388 REG_TYPE_XSCALE,
389 };
390
391 /* Structure for a hash table entry for a register. */
392 struct reg_entry
393 {
394 const char *name;
395 unsigned char number;
396 unsigned char type;
397 unsigned char builtin;
398 };
399
400 /* Diagnostics used when we don't get a register of the expected type. */
401 const char *const reg_expected_msgs[] =
402 {
403 N_("ARM register expected"),
404 N_("bad or missing co-processor number"),
405 N_("co-processor register expected"),
406 N_("FPA register expected"),
407 N_("VFP single precision register expected"),
408 N_("VFP double precision register expected"),
409 N_("VFP system register expected"),
410 N_("Maverick MVF register expected"),
411 N_("Maverick MVD register expected"),
412 N_("Maverick MVFX register expected"),
413 N_("Maverick MVDX register expected"),
414 N_("Maverick MVAX register expected"),
415 N_("Maverick DSPSC register expected"),
416 N_("iWMMXt data register expected"),
417 N_("iWMMXt control register expected"),
418 N_("iWMMXt scalar register expected"),
419 N_("XScale accumulator register expected"),
420 };
421
422 /* Some well known registers that we refer to directly elsewhere. */
423 #define REG_SP 13
424 #define REG_LR 14
425 #define REG_PC 15
426
427 /* ARM instructions take 4bytes in the object file, Thumb instructions
428 take 2: */
429 #define INSN_SIZE 4
430
431 struct asm_opcode
432 {
433 /* Basic string to match. */
434 const char *template;
435
436 /* Parameters to instruction. */
437 unsigned char operands[8];
438
439 /* Conditional tag - see opcode_lookup. */
440 unsigned int tag : 4;
441
442 /* Basic instruction code. */
443 unsigned int avalue : 28;
444
445 /* Thumb-format instruction code. */
446 unsigned int tvalue;
447
448 /* Which architecture variant provides this instruction. */
449 const arm_feature_set *avariant;
450 const arm_feature_set *tvariant;
451
452 /* Function to call to encode instruction in ARM format. */
453 void (* aencode) (void);
454
455 /* Function to call to encode instruction in Thumb format. */
456 void (* tencode) (void);
457 };
458
459 /* Defines for various bits that we will want to toggle. */
460 #define INST_IMMEDIATE 0x02000000
461 #define OFFSET_REG 0x02000000
462 #define HWOFFSET_IMM 0x00400000
463 #define SHIFT_BY_REG 0x00000010
464 #define PRE_INDEX 0x01000000
465 #define INDEX_UP 0x00800000
466 #define WRITE_BACK 0x00200000
467 #define LDM_TYPE_2_OR_3 0x00400000
468
469 #define LITERAL_MASK 0xf000f000
470 #define OPCODE_MASK 0xfe1fffff
471 #define V4_STR_BIT 0x00000020
472
473 #define DATA_OP_SHIFT 21
474
475 #define T2_OPCODE_MASK 0xfe1fffff
476 #define T2_DATA_OP_SHIFT 21
477
478 /* Codes to distinguish the arithmetic instructions. */
479 #define OPCODE_AND 0
480 #define OPCODE_EOR 1
481 #define OPCODE_SUB 2
482 #define OPCODE_RSB 3
483 #define OPCODE_ADD 4
484 #define OPCODE_ADC 5
485 #define OPCODE_SBC 6
486 #define OPCODE_RSC 7
487 #define OPCODE_TST 8
488 #define OPCODE_TEQ 9
489 #define OPCODE_CMP 10
490 #define OPCODE_CMN 11
491 #define OPCODE_ORR 12
492 #define OPCODE_MOV 13
493 #define OPCODE_BIC 14
494 #define OPCODE_MVN 15
495
496 #define T2_OPCODE_AND 0
497 #define T2_OPCODE_BIC 1
498 #define T2_OPCODE_ORR 2
499 #define T2_OPCODE_ORN 3
500 #define T2_OPCODE_EOR 4
501 #define T2_OPCODE_ADD 8
502 #define T2_OPCODE_ADC 10
503 #define T2_OPCODE_SBC 11
504 #define T2_OPCODE_SUB 13
505 #define T2_OPCODE_RSB 14
506
507 #define T_OPCODE_MUL 0x4340
508 #define T_OPCODE_TST 0x4200
509 #define T_OPCODE_CMN 0x42c0
510 #define T_OPCODE_NEG 0x4240
511 #define T_OPCODE_MVN 0x43c0
512
513 #define T_OPCODE_ADD_R3 0x1800
514 #define T_OPCODE_SUB_R3 0x1a00
515 #define T_OPCODE_ADD_HI 0x4400
516 #define T_OPCODE_ADD_ST 0xb000
517 #define T_OPCODE_SUB_ST 0xb080
518 #define T_OPCODE_ADD_SP 0xa800
519 #define T_OPCODE_ADD_PC 0xa000
520 #define T_OPCODE_ADD_I8 0x3000
521 #define T_OPCODE_SUB_I8 0x3800
522 #define T_OPCODE_ADD_I3 0x1c00
523 #define T_OPCODE_SUB_I3 0x1e00
524
525 #define T_OPCODE_ASR_R 0x4100
526 #define T_OPCODE_LSL_R 0x4080
527 #define T_OPCODE_LSR_R 0x40c0
528 #define T_OPCODE_ROR_R 0x41c0
529 #define T_OPCODE_ASR_I 0x1000
530 #define T_OPCODE_LSL_I 0x0000
531 #define T_OPCODE_LSR_I 0x0800
532
533 #define T_OPCODE_MOV_I8 0x2000
534 #define T_OPCODE_CMP_I8 0x2800
535 #define T_OPCODE_CMP_LR 0x4280
536 #define T_OPCODE_MOV_HR 0x4600
537 #define T_OPCODE_CMP_HR 0x4500
538
539 #define T_OPCODE_LDR_PC 0x4800
540 #define T_OPCODE_LDR_SP 0x9800
541 #define T_OPCODE_STR_SP 0x9000
542 #define T_OPCODE_LDR_IW 0x6800
543 #define T_OPCODE_STR_IW 0x6000
544 #define T_OPCODE_LDR_IH 0x8800
545 #define T_OPCODE_STR_IH 0x8000
546 #define T_OPCODE_LDR_IB 0x7800
547 #define T_OPCODE_STR_IB 0x7000
548 #define T_OPCODE_LDR_RW 0x5800
549 #define T_OPCODE_STR_RW 0x5000
550 #define T_OPCODE_LDR_RH 0x5a00
551 #define T_OPCODE_STR_RH 0x5200
552 #define T_OPCODE_LDR_RB 0x5c00
553 #define T_OPCODE_STR_RB 0x5400
554
555 #define T_OPCODE_PUSH 0xb400
556 #define T_OPCODE_POP 0xbc00
557
558 #define T_OPCODE_BRANCH 0xe000
559
560 #define THUMB_SIZE 2 /* Size of thumb instruction. */
561 #define THUMB_PP_PC_LR 0x0100
562 #define THUMB_LOAD_BIT 0x0800
563
564 #define BAD_ARGS _("bad arguments to instruction")
565 #define BAD_PC _("r15 not allowed here")
566 #define BAD_COND _("instruction cannot be conditional")
567 #define BAD_OVERLAP _("registers may not be the same")
568 #define BAD_HIREG _("lo register required")
569 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
570 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
571
572 static struct hash_control *arm_ops_hsh;
573 static struct hash_control *arm_cond_hsh;
574 static struct hash_control *arm_shift_hsh;
575 static struct hash_control *arm_psr_hsh;
576 static struct hash_control *arm_v7m_psr_hsh;
577 static struct hash_control *arm_reg_hsh;
578 static struct hash_control *arm_reloc_hsh;
579 static struct hash_control *arm_barrier_opt_hsh;
580
581 /* Stuff needed to resolve the label ambiguity
582 As:
583 ...
584 label: <insn>
585 may differ from:
586 ...
587 label:
588 <insn>
589 */
590
591 symbolS * last_label_seen;
592 static int label_is_thumb_function_name = FALSE;
593 \f
594 /* Literal pool structure. Held on a per-section
595 and per-sub-section basis. */
596
597 #define MAX_LITERAL_POOL_SIZE 1024
598 typedef struct literal_pool
599 {
600 expressionS literals [MAX_LITERAL_POOL_SIZE];
601 unsigned int next_free_entry;
602 unsigned int id;
603 symbolS * symbol;
604 segT section;
605 subsegT sub_section;
606 struct literal_pool * next;
607 } literal_pool;
608
609 /* Pointer to a linked list of literal pools. */
610 literal_pool * list_of_pools = NULL;
611
612 /* State variables for IT block handling. */
613 static bfd_boolean current_it_mask = 0;
614 static int current_cc;
615
616 \f
617 /* Pure syntax. */
618
619 /* This array holds the chars that always start a comment. If the
620 pre-processor is disabled, these aren't very useful. */
621 const char comment_chars[] = "@";
622
623 /* This array holds the chars that only start a comment at the beginning of
624 a line. If the line seems to have the form '# 123 filename'
625 .line and .file directives will appear in the pre-processed output. */
626 /* Note that input_file.c hand checks for '#' at the beginning of the
627 first line of the input file. This is because the compiler outputs
628 #NO_APP at the beginning of its output. */
629 /* Also note that comments like this one will always work. */
630 const char line_comment_chars[] = "#";
631
632 const char line_separator_chars[] = ";";
633
634 /* Chars that can be used to separate mant
635 from exp in floating point numbers. */
636 const char EXP_CHARS[] = "eE";
637
638 /* Chars that mean this number is a floating point constant. */
639 /* As in 0f12.456 */
640 /* or 0d1.2345e12 */
641
642 const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
643
644 /* Prefix characters that indicate the start of an immediate
645 value. */
646 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
647
648 /* Separator character handling. */
649
650 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
651
652 static inline int
653 skip_past_char (char ** str, char c)
654 {
655 if (**str == c)
656 {
657 (*str)++;
658 return SUCCESS;
659 }
660 else
661 return FAIL;
662 }
663 #define skip_past_comma(str) skip_past_char (str, ',')
664
665 /* Arithmetic expressions (possibly involving symbols). */
666
667 /* Return TRUE if anything in the expression is a bignum. */
668
669 static int
670 walk_no_bignums (symbolS * sp)
671 {
672 if (symbol_get_value_expression (sp)->X_op == O_big)
673 return 1;
674
675 if (symbol_get_value_expression (sp)->X_add_symbol)
676 {
677 return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol)
678 || (symbol_get_value_expression (sp)->X_op_symbol
679 && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol)));
680 }
681
682 return 0;
683 }
684
685 static int in_my_get_expression = 0;
686
687 /* Third argument to my_get_expression. */
688 #define GE_NO_PREFIX 0
689 #define GE_IMM_PREFIX 1
690 #define GE_OPT_PREFIX 2
691
692 static int
693 my_get_expression (expressionS * ep, char ** str, int prefix_mode)
694 {
695 char * save_in;
696 segT seg;
697
698 /* In unified syntax, all prefixes are optional. */
699 if (unified_syntax)
700 prefix_mode = GE_OPT_PREFIX;
701
702 switch (prefix_mode)
703 {
704 case GE_NO_PREFIX: break;
705 case GE_IMM_PREFIX:
706 if (!is_immediate_prefix (**str))
707 {
708 inst.error = _("immediate expression requires a # prefix");
709 return FAIL;
710 }
711 (*str)++;
712 break;
713 case GE_OPT_PREFIX:
714 if (is_immediate_prefix (**str))
715 (*str)++;
716 break;
717 default: abort ();
718 }
719
720 memset (ep, 0, sizeof (expressionS));
721
722 save_in = input_line_pointer;
723 input_line_pointer = *str;
724 in_my_get_expression = 1;
725 seg = expression (ep);
726 in_my_get_expression = 0;
727
728 if (ep->X_op == O_illegal)
729 {
730 /* We found a bad expression in md_operand(). */
731 *str = input_line_pointer;
732 input_line_pointer = save_in;
733 if (inst.error == NULL)
734 inst.error = _("bad expression");
735 return 1;
736 }
737
738 #ifdef OBJ_AOUT
739 if (seg != absolute_section
740 && seg != text_section
741 && seg != data_section
742 && seg != bss_section
743 && seg != undefined_section)
744 {
745 inst.error = _("bad segment");
746 *str = input_line_pointer;
747 input_line_pointer = save_in;
748 return 1;
749 }
750 #endif
751
752 /* Get rid of any bignums now, so that we don't generate an error for which
753 we can't establish a line number later on. Big numbers are never valid
754 in instructions, which is where this routine is always called. */
755 if (ep->X_op == O_big
756 || (ep->X_add_symbol
757 && (walk_no_bignums (ep->X_add_symbol)
758 || (ep->X_op_symbol
759 && walk_no_bignums (ep->X_op_symbol)))))
760 {
761 inst.error = _("invalid constant");
762 *str = input_line_pointer;
763 input_line_pointer = save_in;
764 return 1;
765 }
766
767 *str = input_line_pointer;
768 input_line_pointer = save_in;
769 return 0;
770 }
771
772 /* Turn a string in input_line_pointer into a floating point constant
773 of type TYPE, and store the appropriate bytes in *LITP. The number
774 of LITTLENUMS emitted is stored in *SIZEP. An error message is
775 returned, or NULL on OK.
776
777 Note that fp constants aren't represent in the normal way on the ARM.
778 In big endian mode, things are as expected. However, in little endian
779 mode fp constants are big-endian word-wise, and little-endian byte-wise
780 within the words. For example, (double) 1.1 in big endian mode is
781 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
782 the byte sequence 99 99 f1 3f 9a 99 99 99.
783
784 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
785
786 char *
787 md_atof (int type, char * litP, int * sizeP)
788 {
789 int prec;
790 LITTLENUM_TYPE words[MAX_LITTLENUMS];
791 char *t;
792 int i;
793
794 switch (type)
795 {
796 case 'f':
797 case 'F':
798 case 's':
799 case 'S':
800 prec = 2;
801 break;
802
803 case 'd':
804 case 'D':
805 case 'r':
806 case 'R':
807 prec = 4;
808 break;
809
810 case 'x':
811 case 'X':
812 prec = 6;
813 break;
814
815 case 'p':
816 case 'P':
817 prec = 6;
818 break;
819
820 default:
821 *sizeP = 0;
822 return _("bad call to MD_ATOF()");
823 }
824
825 t = atof_ieee (input_line_pointer, type, words);
826 if (t)
827 input_line_pointer = t;
828 *sizeP = prec * 2;
829
830 if (target_big_endian)
831 {
832 for (i = 0; i < prec; i++)
833 {
834 md_number_to_chars (litP, (valueT) words[i], 2);
835 litP += 2;
836 }
837 }
838 else
839 {
840 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
841 for (i = prec - 1; i >= 0; i--)
842 {
843 md_number_to_chars (litP, (valueT) words[i], 2);
844 litP += 2;
845 }
846 else
847 /* For a 4 byte float the order of elements in `words' is 1 0.
848 For an 8 byte float the order is 1 0 3 2. */
849 for (i = 0; i < prec; i += 2)
850 {
851 md_number_to_chars (litP, (valueT) words[i + 1], 2);
852 md_number_to_chars (litP + 2, (valueT) words[i], 2);
853 litP += 4;
854 }
855 }
856
857 return 0;
858 }
859
860 /* We handle all bad expressions here, so that we can report the faulty
861 instruction in the error message. */
862 void
863 md_operand (expressionS * expr)
864 {
865 if (in_my_get_expression)
866 expr->X_op = O_illegal;
867 }
868
869 /* Immediate values. */
870
871 /* Generic immediate-value read function for use in directives.
872 Accepts anything that 'expression' can fold to a constant.
873 *val receives the number. */
874 #ifdef OBJ_ELF
875 static int
876 immediate_for_directive (int *val)
877 {
878 expressionS exp;
879 exp.X_op = O_illegal;
880
881 if (is_immediate_prefix (*input_line_pointer))
882 {
883 input_line_pointer++;
884 expression (&exp);
885 }
886
887 if (exp.X_op != O_constant)
888 {
889 as_bad (_("expected #constant"));
890 ignore_rest_of_line ();
891 return FAIL;
892 }
893 *val = exp.X_add_number;
894 return SUCCESS;
895 }
896 #endif
897
898 /* Register parsing. */
899
900 /* Generic register parser. CCP points to what should be the
901 beginning of a register name. If it is indeed a valid register
902 name, advance CCP over it and return the reg_entry structure;
903 otherwise return NULL. Does not issue diagnostics. */
904
905 static struct reg_entry *
906 arm_reg_parse_multi (char **ccp)
907 {
908 char *start = *ccp;
909 char *p;
910 struct reg_entry *reg;
911
912 #ifdef REGISTER_PREFIX
913 if (*start != REGISTER_PREFIX)
914 return NULL;
915 start++;
916 #endif
917 #ifdef OPTIONAL_REGISTER_PREFIX
918 if (*start == OPTIONAL_REGISTER_PREFIX)
919 start++;
920 #endif
921
922 p = start;
923 if (!ISALPHA (*p) || !is_name_beginner (*p))
924 return NULL;
925
926 do
927 p++;
928 while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_');
929
930 reg = (struct reg_entry *) hash_find_n (arm_reg_hsh, start, p - start);
931
932 if (!reg)
933 return NULL;
934
935 *ccp = p;
936 return reg;
937 }
938
939 /* As above, but the register must be of type TYPE, and the return
940 value is the register number or FAIL. */
941
942 static int
943 arm_reg_parse (char **ccp, enum arm_reg_type type)
944 {
945 char *start = *ccp;
946 struct reg_entry *reg = arm_reg_parse_multi (ccp);
947
948 if (reg && reg->type == type)
949 return reg->number;
950
951 /* Alternative syntaxes are accepted for a few register classes. */
952 switch (type)
953 {
954 case REG_TYPE_MVF:
955 case REG_TYPE_MVD:
956 case REG_TYPE_MVFX:
957 case REG_TYPE_MVDX:
958 /* Generic coprocessor register names are allowed for these. */
959 if (reg && reg->type == REG_TYPE_CN)
960 return reg->number;
961 break;
962
963 case REG_TYPE_CP:
964 /* For backward compatibility, a bare number is valid here. */
965 {
966 unsigned long processor = strtoul (start, ccp, 10);
967 if (*ccp != start && processor <= 15)
968 return processor;
969 }
970
971 case REG_TYPE_MMXWC:
972 /* WC includes WCG. ??? I'm not sure this is true for all
973 instructions that take WC registers. */
974 if (reg && reg->type == REG_TYPE_MMXWCG)
975 return reg->number;
976 break;
977
978 default:
979 break;
980 }
981
982 *ccp = start;
983 return FAIL;
984 }
985
986 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
987 static long
988 parse_reg_list (char ** strp)
989 {
990 char * str = * strp;
991 long range = 0;
992 int another_range;
993
994 /* We come back here if we get ranges concatenated by '+' or '|'. */
995 do
996 {
997 another_range = 0;
998
999 if (*str == '{')
1000 {
1001 int in_range = 0;
1002 int cur_reg = -1;
1003
1004 str++;
1005 do
1006 {
1007 int reg;
1008
1009 if ((reg = arm_reg_parse (&str, REG_TYPE_RN)) == FAIL)
1010 {
1011 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
1012 return FAIL;
1013 }
1014
1015 if (in_range)
1016 {
1017 int i;
1018
1019 if (reg <= cur_reg)
1020 {
1021 inst.error = _("bad range in register list");
1022 return FAIL;
1023 }
1024
1025 for (i = cur_reg + 1; i < reg; i++)
1026 {
1027 if (range & (1 << i))
1028 as_tsktsk
1029 (_("Warning: duplicated register (r%d) in register list"),
1030 i);
1031 else
1032 range |= 1 << i;
1033 }
1034 in_range = 0;
1035 }
1036
1037 if (range & (1 << reg))
1038 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1039 reg);
1040 else if (reg <= cur_reg)
1041 as_tsktsk (_("Warning: register range not in ascending order"));
1042
1043 range |= 1 << reg;
1044 cur_reg = reg;
1045 }
1046 while (skip_past_comma (&str) != FAIL
1047 || (in_range = 1, *str++ == '-'));
1048 str--;
1049
1050 if (*str++ != '}')
1051 {
1052 inst.error = _("missing `}'");
1053 return FAIL;
1054 }
1055 }
1056 else
1057 {
1058 expressionS expr;
1059
1060 if (my_get_expression (&expr, &str, GE_NO_PREFIX))
1061 return FAIL;
1062
1063 if (expr.X_op == O_constant)
1064 {
1065 if (expr.X_add_number
1066 != (expr.X_add_number & 0x0000ffff))
1067 {
1068 inst.error = _("invalid register mask");
1069 return FAIL;
1070 }
1071
1072 if ((range & expr.X_add_number) != 0)
1073 {
1074 int regno = range & expr.X_add_number;
1075
1076 regno &= -regno;
1077 regno = (1 << regno) - 1;
1078 as_tsktsk
1079 (_("Warning: duplicated register (r%d) in register list"),
1080 regno);
1081 }
1082
1083 range |= expr.X_add_number;
1084 }
1085 else
1086 {
1087 if (inst.reloc.type != 0)
1088 {
1089 inst.error = _("expression too complex");
1090 return FAIL;
1091 }
1092
1093 memcpy (&inst.reloc.exp, &expr, sizeof (expressionS));
1094 inst.reloc.type = BFD_RELOC_ARM_MULTI;
1095 inst.reloc.pc_rel = 0;
1096 }
1097 }
1098
1099 if (*str == '|' || *str == '+')
1100 {
1101 str++;
1102 another_range = 1;
1103 }
1104 }
1105 while (another_range);
1106
1107 *strp = str;
1108 return range;
1109 }
1110
1111 /* Parse a VFP register list. If the string is invalid return FAIL.
1112 Otherwise return the number of registers, and set PBASE to the first
1113 register. Double precision registers are matched if DP is nonzero. */
1114
1115 static int
1116 parse_vfp_reg_list (char **str, unsigned int *pbase, int dp)
1117 {
1118 int base_reg;
1119 int new_base;
1120 int regtype;
1121 int max_regs;
1122 int count = 0;
1123 int warned = 0;
1124 unsigned long mask = 0;
1125 int i;
1126
1127 if (**str != '{')
1128 return FAIL;
1129
1130 (*str)++;
1131
1132 if (dp)
1133 {
1134 regtype = REG_TYPE_VFD;
1135 max_regs = 16;
1136 }
1137 else
1138 {
1139 regtype = REG_TYPE_VFS;
1140 max_regs = 32;
1141 }
1142
1143 base_reg = max_regs;
1144
1145 do
1146 {
1147 new_base = arm_reg_parse (str, regtype);
1148 if (new_base == FAIL)
1149 {
1150 inst.error = gettext (reg_expected_msgs[regtype]);
1151 return FAIL;
1152 }
1153
1154 if (new_base < base_reg)
1155 base_reg = new_base;
1156
1157 if (mask & (1 << new_base))
1158 {
1159 inst.error = _("invalid register list");
1160 return FAIL;
1161 }
1162
1163 if ((mask >> new_base) != 0 && ! warned)
1164 {
1165 as_tsktsk (_("register list not in ascending order"));
1166 warned = 1;
1167 }
1168
1169 mask |= 1 << new_base;
1170 count++;
1171
1172 if (**str == '-') /* We have the start of a range expression */
1173 {
1174 int high_range;
1175
1176 (*str)++;
1177
1178 if ((high_range = arm_reg_parse (str, regtype)) == FAIL)
1179 {
1180 inst.error = gettext (reg_expected_msgs[regtype]);
1181 return FAIL;
1182 }
1183
1184 if (high_range <= new_base)
1185 {
1186 inst.error = _("register range not in ascending order");
1187 return FAIL;
1188 }
1189
1190 for (new_base++; new_base <= high_range; new_base++)
1191 {
1192 if (mask & (1 << new_base))
1193 {
1194 inst.error = _("invalid register list");
1195 return FAIL;
1196 }
1197
1198 mask |= 1 << new_base;
1199 count++;
1200 }
1201 }
1202 }
1203 while (skip_past_comma (str) != FAIL);
1204
1205 (*str)++;
1206
1207 /* Sanity check -- should have raised a parse error above. */
1208 if (count == 0 || count > max_regs)
1209 abort ();
1210
1211 *pbase = base_reg;
1212
1213 /* Final test -- the registers must be consecutive. */
1214 mask >>= base_reg;
1215 for (i = 0; i < count; i++)
1216 {
1217 if ((mask & (1u << i)) == 0)
1218 {
1219 inst.error = _("non-contiguous register range");
1220 return FAIL;
1221 }
1222 }
1223
1224 return count;
1225 }
1226
1227 /* Parse an explicit relocation suffix on an expression. This is
1228 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
1229 arm_reloc_hsh contains no entries, so this function can only
1230 succeed if there is no () after the word. Returns -1 on error,
1231 BFD_RELOC_UNUSED if there wasn't any suffix. */
1232 static int
1233 parse_reloc (char **str)
1234 {
1235 struct reloc_entry *r;
1236 char *p, *q;
1237
1238 if (**str != '(')
1239 return BFD_RELOC_UNUSED;
1240
1241 p = *str + 1;
1242 q = p;
1243
1244 while (*q && *q != ')' && *q != ',')
1245 q++;
1246 if (*q != ')')
1247 return -1;
1248
1249 if ((r = hash_find_n (arm_reloc_hsh, p, q - p)) == NULL)
1250 return -1;
1251
1252 *str = q + 1;
1253 return r->reloc;
1254 }
1255
1256 /* Directives: register aliases. */
1257
1258 static void
1259 insert_reg_alias (char *str, int number, int type)
1260 {
1261 struct reg_entry *new;
1262 const char *name;
1263
1264 if ((new = hash_find (arm_reg_hsh, str)) != 0)
1265 {
1266 if (new->builtin)
1267 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str);
1268
1269 /* Only warn about a redefinition if it's not defined as the
1270 same register. */
1271 else if (new->number != number || new->type != type)
1272 as_warn (_("ignoring redefinition of register alias '%s'"), str);
1273
1274 return;
1275 }
1276
1277 name = xstrdup (str);
1278 new = xmalloc (sizeof (struct reg_entry));
1279
1280 new->name = name;
1281 new->number = number;
1282 new->type = type;
1283 new->builtin = FALSE;
1284
1285 if (hash_insert (arm_reg_hsh, name, (PTR) new))
1286 abort ();
1287 }
1288
1289 /* Look for the .req directive. This is of the form:
1290
1291 new_register_name .req existing_register_name
1292
1293 If we find one, or if it looks sufficiently like one that we want to
1294 handle any error here, return non-zero. Otherwise return zero. */
1295
1296 static int
1297 create_register_alias (char * newname, char *p)
1298 {
1299 struct reg_entry *old;
1300 char *oldname, *nbuf;
1301 size_t nlen;
1302
1303 /* The input scrubber ensures that whitespace after the mnemonic is
1304 collapsed to single spaces. */
1305 oldname = p;
1306 if (strncmp (oldname, " .req ", 6) != 0)
1307 return 0;
1308
1309 oldname += 6;
1310 if (*oldname == '\0')
1311 return 0;
1312
1313 old = hash_find (arm_reg_hsh, oldname);
1314 if (!old)
1315 {
1316 as_warn (_("unknown register '%s' -- .req ignored"), oldname);
1317 return 1;
1318 }
1319
1320 /* If TC_CASE_SENSITIVE is defined, then newname already points to
1321 the desired alias name, and p points to its end. If not, then
1322 the desired alias name is in the global original_case_string. */
1323 #ifdef TC_CASE_SENSITIVE
1324 nlen = p - newname;
1325 #else
1326 newname = original_case_string;
1327 nlen = strlen (newname);
1328 #endif
1329
1330 nbuf = alloca (nlen + 1);
1331 memcpy (nbuf, newname, nlen);
1332 nbuf[nlen] = '\0';
1333
1334 /* Create aliases under the new name as stated; an all-lowercase
1335 version of the new name; and an all-uppercase version of the new
1336 name. */
1337 insert_reg_alias (nbuf, old->number, old->type);
1338
1339 for (p = nbuf; *p; p++)
1340 *p = TOUPPER (*p);
1341
1342 if (strncmp (nbuf, newname, nlen))
1343 insert_reg_alias (nbuf, old->number, old->type);
1344
1345 for (p = nbuf; *p; p++)
1346 *p = TOLOWER (*p);
1347
1348 if (strncmp (nbuf, newname, nlen))
1349 insert_reg_alias (nbuf, old->number, old->type);
1350
1351 return 1;
1352 }
1353
1354 /* Should never be called, as .req goes between the alias and the
1355 register name, not at the beginning of the line. */
1356 static void
1357 s_req (int a ATTRIBUTE_UNUSED)
1358 {
1359 as_bad (_("invalid syntax for .req directive"));
1360 }
1361
1362 /* The .unreq directive deletes an alias which was previously defined
1363 by .req. For example:
1364
1365 my_alias .req r11
1366 .unreq my_alias */
1367
1368 static void
1369 s_unreq (int a ATTRIBUTE_UNUSED)
1370 {
1371 char * name;
1372 char saved_char;
1373
1374 name = input_line_pointer;
1375
1376 while (*input_line_pointer != 0
1377 && *input_line_pointer != ' '
1378 && *input_line_pointer != '\n')
1379 ++input_line_pointer;
1380
1381 saved_char = *input_line_pointer;
1382 *input_line_pointer = 0;
1383
1384 if (!*name)
1385 as_bad (_("invalid syntax for .unreq directive"));
1386 else
1387 {
1388 struct reg_entry *reg = hash_find (arm_reg_hsh, name);
1389
1390 if (!reg)
1391 as_bad (_("unknown register alias '%s'"), name);
1392 else if (reg->builtin)
1393 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
1394 name);
1395 else
1396 {
1397 hash_delete (arm_reg_hsh, name);
1398 free ((char *) reg->name);
1399 free (reg);
1400 }
1401 }
1402
1403 *input_line_pointer = saved_char;
1404 demand_empty_rest_of_line ();
1405 }
1406
1407 /* Directives: Instruction set selection. */
1408
1409 #ifdef OBJ_ELF
1410 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
1411 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
1412 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
1413 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
1414
1415 static enum mstate mapstate = MAP_UNDEFINED;
1416
1417 static void
1418 mapping_state (enum mstate state)
1419 {
1420 symbolS * symbolP;
1421 const char * symname;
1422 int type;
1423
1424 if (mapstate == state)
1425 /* The mapping symbol has already been emitted.
1426 There is nothing else to do. */
1427 return;
1428
1429 mapstate = state;
1430
1431 switch (state)
1432 {
1433 case MAP_DATA:
1434 symname = "$d";
1435 type = BSF_NO_FLAGS;
1436 break;
1437 case MAP_ARM:
1438 symname = "$a";
1439 type = BSF_NO_FLAGS;
1440 break;
1441 case MAP_THUMB:
1442 symname = "$t";
1443 type = BSF_NO_FLAGS;
1444 break;
1445 case MAP_UNDEFINED:
1446 return;
1447 default:
1448 abort ();
1449 }
1450
1451 seg_info (now_seg)->tc_segment_info_data.mapstate = state;
1452
1453 symbolP = symbol_new (symname, now_seg, (valueT) frag_now_fix (), frag_now);
1454 symbol_table_insert (symbolP);
1455 symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL;
1456
1457 switch (state)
1458 {
1459 case MAP_ARM:
1460 THUMB_SET_FUNC (symbolP, 0);
1461 ARM_SET_THUMB (symbolP, 0);
1462 ARM_SET_INTERWORK (symbolP, support_interwork);
1463 break;
1464
1465 case MAP_THUMB:
1466 THUMB_SET_FUNC (symbolP, 1);
1467 ARM_SET_THUMB (symbolP, 1);
1468 ARM_SET_INTERWORK (symbolP, support_interwork);
1469 break;
1470
1471 case MAP_DATA:
1472 default:
1473 return;
1474 }
1475 }
1476 #else
1477 #define mapping_state(x) /* nothing */
1478 #endif
1479
1480 /* Find the real, Thumb encoded start of a Thumb function. */
1481
1482 static symbolS *
1483 find_real_start (symbolS * symbolP)
1484 {
1485 char * real_start;
1486 const char * name = S_GET_NAME (symbolP);
1487 symbolS * new_target;
1488
1489 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
1490 #define STUB_NAME ".real_start_of"
1491
1492 if (name == NULL)
1493 abort ();
1494
1495 /* The compiler may generate BL instructions to local labels because
1496 it needs to perform a branch to a far away location. These labels
1497 do not have a corresponding ".real_start_of" label. We check
1498 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
1499 the ".real_start_of" convention for nonlocal branches. */
1500 if (S_IS_LOCAL (symbolP) || name[0] == '.')
1501 return symbolP;
1502
1503 real_start = ACONCAT ((STUB_NAME, name, NULL));
1504 new_target = symbol_find (real_start);
1505
1506 if (new_target == NULL)
1507 {
1508 as_warn ("Failed to find real start of function: %s\n", name);
1509 new_target = symbolP;
1510 }
1511
1512 return new_target;
1513 }
1514
1515 static void
1516 opcode_select (int width)
1517 {
1518 switch (width)
1519 {
1520 case 16:
1521 if (! thumb_mode)
1522 {
1523 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
1524 as_bad (_("selected processor does not support THUMB opcodes"));
1525
1526 thumb_mode = 1;
1527 /* No need to force the alignment, since we will have been
1528 coming from ARM mode, which is word-aligned. */
1529 record_alignment (now_seg, 1);
1530 }
1531 mapping_state (MAP_THUMB);
1532 break;
1533
1534 case 32:
1535 if (thumb_mode)
1536 {
1537 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
1538 as_bad (_("selected processor does not support ARM opcodes"));
1539
1540 thumb_mode = 0;
1541
1542 if (!need_pass_2)
1543 frag_align (2, 0, 0);
1544
1545 record_alignment (now_seg, 1);
1546 }
1547 mapping_state (MAP_ARM);
1548 break;
1549
1550 default:
1551 as_bad (_("invalid instruction size selected (%d)"), width);
1552 }
1553 }
1554
1555 static void
1556 s_arm (int ignore ATTRIBUTE_UNUSED)
1557 {
1558 opcode_select (32);
1559 demand_empty_rest_of_line ();
1560 }
1561
1562 static void
1563 s_thumb (int ignore ATTRIBUTE_UNUSED)
1564 {
1565 opcode_select (16);
1566 demand_empty_rest_of_line ();
1567 }
1568
1569 static void
1570 s_code (int unused ATTRIBUTE_UNUSED)
1571 {
1572 int temp;
1573
1574 temp = get_absolute_expression ();
1575 switch (temp)
1576 {
1577 case 16:
1578 case 32:
1579 opcode_select (temp);
1580 break;
1581
1582 default:
1583 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp);
1584 }
1585 }
1586
1587 static void
1588 s_force_thumb (int ignore ATTRIBUTE_UNUSED)
1589 {
1590 /* If we are not already in thumb mode go into it, EVEN if
1591 the target processor does not support thumb instructions.
1592 This is used by gcc/config/arm/lib1funcs.asm for example
1593 to compile interworking support functions even if the
1594 target processor should not support interworking. */
1595 if (! thumb_mode)
1596 {
1597 thumb_mode = 2;
1598 record_alignment (now_seg, 1);
1599 }
1600
1601 demand_empty_rest_of_line ();
1602 }
1603
1604 static void
1605 s_thumb_func (int ignore ATTRIBUTE_UNUSED)
1606 {
1607 s_thumb (0);
1608
1609 /* The following label is the name/address of the start of a Thumb function.
1610 We need to know this for the interworking support. */
1611 label_is_thumb_function_name = TRUE;
1612 }
1613
1614 /* Perform a .set directive, but also mark the alias as
1615 being a thumb function. */
1616
1617 static void
1618 s_thumb_set (int equiv)
1619 {
1620 /* XXX the following is a duplicate of the code for s_set() in read.c
1621 We cannot just call that code as we need to get at the symbol that
1622 is created. */
1623 char * name;
1624 char delim;
1625 char * end_name;
1626 symbolS * symbolP;
1627
1628 /* Especial apologies for the random logic:
1629 This just grew, and could be parsed much more simply!
1630 Dean - in haste. */
1631 name = input_line_pointer;
1632 delim = get_symbol_end ();
1633 end_name = input_line_pointer;
1634 *end_name = delim;
1635
1636 if (*input_line_pointer != ',')
1637 {
1638 *end_name = 0;
1639 as_bad (_("expected comma after name \"%s\""), name);
1640 *end_name = delim;
1641 ignore_rest_of_line ();
1642 return;
1643 }
1644
1645 input_line_pointer++;
1646 *end_name = 0;
1647
1648 if (name[0] == '.' && name[1] == '\0')
1649 {
1650 /* XXX - this should not happen to .thumb_set. */
1651 abort ();
1652 }
1653
1654 if ((symbolP = symbol_find (name)) == NULL
1655 && (symbolP = md_undefined_symbol (name)) == NULL)
1656 {
1657 #ifndef NO_LISTING
1658 /* When doing symbol listings, play games with dummy fragments living
1659 outside the normal fragment chain to record the file and line info
1660 for this symbol. */
1661 if (listing & LISTING_SYMBOLS)
1662 {
1663 extern struct list_info_struct * listing_tail;
1664 fragS * dummy_frag = xmalloc (sizeof (fragS));
1665
1666 memset (dummy_frag, 0, sizeof (fragS));
1667 dummy_frag->fr_type = rs_fill;
1668 dummy_frag->line = listing_tail;
1669 symbolP = symbol_new (name, undefined_section, 0, dummy_frag);
1670 dummy_frag->fr_symbol = symbolP;
1671 }
1672 else
1673 #endif
1674 symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag);
1675
1676 #ifdef OBJ_COFF
1677 /* "set" symbols are local unless otherwise specified. */
1678 SF_SET_LOCAL (symbolP);
1679 #endif /* OBJ_COFF */
1680 } /* Make a new symbol. */
1681
1682 symbol_table_insert (symbolP);
1683
1684 * end_name = delim;
1685
1686 if (equiv
1687 && S_IS_DEFINED (symbolP)
1688 && S_GET_SEGMENT (symbolP) != reg_section)
1689 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP));
1690
1691 pseudo_set (symbolP);
1692
1693 demand_empty_rest_of_line ();
1694
1695 /* XXX Now we come to the Thumb specific bit of code. */
1696
1697 THUMB_SET_FUNC (symbolP, 1);
1698 ARM_SET_THUMB (symbolP, 1);
1699 #if defined OBJ_ELF || defined OBJ_COFF
1700 ARM_SET_INTERWORK (symbolP, support_interwork);
1701 #endif
1702 }
1703
1704 /* Directives: Mode selection. */
1705
1706 /* .syntax [unified|divided] - choose the new unified syntax
1707 (same for Arm and Thumb encoding, modulo slight differences in what
1708 can be represented) or the old divergent syntax for each mode. */
1709 static void
1710 s_syntax (int unused ATTRIBUTE_UNUSED)
1711 {
1712 char *name, delim;
1713
1714 name = input_line_pointer;
1715 delim = get_symbol_end ();
1716
1717 if (!strcasecmp (name, "unified"))
1718 unified_syntax = TRUE;
1719 else if (!strcasecmp (name, "divided"))
1720 unified_syntax = FALSE;
1721 else
1722 {
1723 as_bad (_("unrecognized syntax mode \"%s\""), name);
1724 return;
1725 }
1726 *input_line_pointer = delim;
1727 demand_empty_rest_of_line ();
1728 }
1729
1730 /* Directives: sectioning and alignment. */
1731
1732 /* Same as s_align_ptwo but align 0 => align 2. */
1733
1734 static void
1735 s_align (int unused ATTRIBUTE_UNUSED)
1736 {
1737 int temp;
1738 long temp_fill;
1739 long max_alignment = 15;
1740
1741 temp = get_absolute_expression ();
1742 if (temp > max_alignment)
1743 as_bad (_("alignment too large: %d assumed"), temp = max_alignment);
1744 else if (temp < 0)
1745 {
1746 as_bad (_("alignment negative. 0 assumed."));
1747 temp = 0;
1748 }
1749
1750 if (*input_line_pointer == ',')
1751 {
1752 input_line_pointer++;
1753 temp_fill = get_absolute_expression ();
1754 }
1755 else
1756 temp_fill = 0;
1757
1758 if (!temp)
1759 temp = 2;
1760
1761 /* Only make a frag if we HAVE to. */
1762 if (temp && !need_pass_2)
1763 frag_align (temp, (int) temp_fill, 0);
1764 demand_empty_rest_of_line ();
1765
1766 record_alignment (now_seg, temp);
1767 }
1768
1769 static void
1770 s_bss (int ignore ATTRIBUTE_UNUSED)
1771 {
1772 /* We don't support putting frags in the BSS segment, we fake it by
1773 marking in_bss, then looking at s_skip for clues. */
1774 subseg_set (bss_section, 0);
1775 demand_empty_rest_of_line ();
1776 mapping_state (MAP_DATA);
1777 }
1778
1779 static void
1780 s_even (int ignore ATTRIBUTE_UNUSED)
1781 {
1782 /* Never make frag if expect extra pass. */
1783 if (!need_pass_2)
1784 frag_align (1, 0, 0);
1785
1786 record_alignment (now_seg, 1);
1787
1788 demand_empty_rest_of_line ();
1789 }
1790
1791 /* Directives: Literal pools. */
1792
1793 static literal_pool *
1794 find_literal_pool (void)
1795 {
1796 literal_pool * pool;
1797
1798 for (pool = list_of_pools; pool != NULL; pool = pool->next)
1799 {
1800 if (pool->section == now_seg
1801 && pool->sub_section == now_subseg)
1802 break;
1803 }
1804
1805 return pool;
1806 }
1807
1808 static literal_pool *
1809 find_or_make_literal_pool (void)
1810 {
1811 /* Next literal pool ID number. */
1812 static unsigned int latest_pool_num = 1;
1813 literal_pool * pool;
1814
1815 pool = find_literal_pool ();
1816
1817 if (pool == NULL)
1818 {
1819 /* Create a new pool. */
1820 pool = xmalloc (sizeof (* pool));
1821 if (! pool)
1822 return NULL;
1823
1824 pool->next_free_entry = 0;
1825 pool->section = now_seg;
1826 pool->sub_section = now_subseg;
1827 pool->next = list_of_pools;
1828 pool->symbol = NULL;
1829
1830 /* Add it to the list. */
1831 list_of_pools = pool;
1832 }
1833
1834 /* New pools, and emptied pools, will have a NULL symbol. */
1835 if (pool->symbol == NULL)
1836 {
1837 pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section,
1838 (valueT) 0, &zero_address_frag);
1839 pool->id = latest_pool_num ++;
1840 }
1841
1842 /* Done. */
1843 return pool;
1844 }
1845
1846 /* Add the literal in the global 'inst'
1847 structure to the relevent literal pool. */
1848
1849 static int
1850 add_to_lit_pool (void)
1851 {
1852 literal_pool * pool;
1853 unsigned int entry;
1854
1855 pool = find_or_make_literal_pool ();
1856
1857 /* Check if this literal value is already in the pool. */
1858 for (entry = 0; entry < pool->next_free_entry; entry ++)
1859 {
1860 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
1861 && (inst.reloc.exp.X_op == O_constant)
1862 && (pool->literals[entry].X_add_number
1863 == inst.reloc.exp.X_add_number)
1864 && (pool->literals[entry].X_unsigned
1865 == inst.reloc.exp.X_unsigned))
1866 break;
1867
1868 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
1869 && (inst.reloc.exp.X_op == O_symbol)
1870 && (pool->literals[entry].X_add_number
1871 == inst.reloc.exp.X_add_number)
1872 && (pool->literals[entry].X_add_symbol
1873 == inst.reloc.exp.X_add_symbol)
1874 && (pool->literals[entry].X_op_symbol
1875 == inst.reloc.exp.X_op_symbol))
1876 break;
1877 }
1878
1879 /* Do we need to create a new entry? */
1880 if (entry == pool->next_free_entry)
1881 {
1882 if (entry >= MAX_LITERAL_POOL_SIZE)
1883 {
1884 inst.error = _("literal pool overflow");
1885 return FAIL;
1886 }
1887
1888 pool->literals[entry] = inst.reloc.exp;
1889 pool->next_free_entry += 1;
1890 }
1891
1892 inst.reloc.exp.X_op = O_symbol;
1893 inst.reloc.exp.X_add_number = ((int) entry) * 4;
1894 inst.reloc.exp.X_add_symbol = pool->symbol;
1895
1896 return SUCCESS;
1897 }
1898
1899 /* Can't use symbol_new here, so have to create a symbol and then at
1900 a later date assign it a value. Thats what these functions do. */
1901
1902 static void
1903 symbol_locate (symbolS * symbolP,
1904 const char * name, /* It is copied, the caller can modify. */
1905 segT segment, /* Segment identifier (SEG_<something>). */
1906 valueT valu, /* Symbol value. */
1907 fragS * frag) /* Associated fragment. */
1908 {
1909 unsigned int name_length;
1910 char * preserved_copy_of_name;
1911
1912 name_length = strlen (name) + 1; /* +1 for \0. */
1913 obstack_grow (&notes, name, name_length);
1914 preserved_copy_of_name = obstack_finish (&notes);
1915
1916 #ifdef tc_canonicalize_symbol_name
1917 preserved_copy_of_name =
1918 tc_canonicalize_symbol_name (preserved_copy_of_name);
1919 #endif
1920
1921 S_SET_NAME (symbolP, preserved_copy_of_name);
1922
1923 S_SET_SEGMENT (symbolP, segment);
1924 S_SET_VALUE (symbolP, valu);
1925 symbol_clear_list_pointers (symbolP);
1926
1927 symbol_set_frag (symbolP, frag);
1928
1929 /* Link to end of symbol chain. */
1930 {
1931 extern int symbol_table_frozen;
1932
1933 if (symbol_table_frozen)
1934 abort ();
1935 }
1936
1937 symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP);
1938
1939 obj_symbol_new_hook (symbolP);
1940
1941 #ifdef tc_symbol_new_hook
1942 tc_symbol_new_hook (symbolP);
1943 #endif
1944
1945 #ifdef DEBUG_SYMS
1946 verify_symbol_chain (symbol_rootP, symbol_lastP);
1947 #endif /* DEBUG_SYMS */
1948 }
1949
1950
1951 static void
1952 s_ltorg (int ignored ATTRIBUTE_UNUSED)
1953 {
1954 unsigned int entry;
1955 literal_pool * pool;
1956 char sym_name[20];
1957
1958 pool = find_literal_pool ();
1959 if (pool == NULL
1960 || pool->symbol == NULL
1961 || pool->next_free_entry == 0)
1962 return;
1963
1964 mapping_state (MAP_DATA);
1965
1966 /* Align pool as you have word accesses.
1967 Only make a frag if we have to. */
1968 if (!need_pass_2)
1969 frag_align (2, 0, 0);
1970
1971 record_alignment (now_seg, 2);
1972
1973 sprintf (sym_name, "$$lit_\002%x", pool->id);
1974
1975 symbol_locate (pool->symbol, sym_name, now_seg,
1976 (valueT) frag_now_fix (), frag_now);
1977 symbol_table_insert (pool->symbol);
1978
1979 ARM_SET_THUMB (pool->symbol, thumb_mode);
1980
1981 #if defined OBJ_COFF || defined OBJ_ELF
1982 ARM_SET_INTERWORK (pool->symbol, support_interwork);
1983 #endif
1984
1985 for (entry = 0; entry < pool->next_free_entry; entry ++)
1986 /* First output the expression in the instruction to the pool. */
1987 emit_expr (&(pool->literals[entry]), 4); /* .word */
1988
1989 /* Mark the pool as empty. */
1990 pool->next_free_entry = 0;
1991 pool->symbol = NULL;
1992 }
1993
1994 #ifdef OBJ_ELF
1995 /* Forward declarations for functions below, in the MD interface
1996 section. */
1997 static void fix_new_arm (fragS *, int, short, expressionS *, int, int);
1998 static valueT create_unwind_entry (int);
1999 static void start_unwind_section (const segT, int);
2000 static void add_unwind_opcode (valueT, int);
2001 static void flush_pending_unwind (void);
2002
2003 /* Directives: Data. */
2004
2005 static void
2006 s_arm_elf_cons (int nbytes)
2007 {
2008 expressionS exp;
2009
2010 #ifdef md_flush_pending_output
2011 md_flush_pending_output ();
2012 #endif
2013
2014 if (is_it_end_of_statement ())
2015 {
2016 demand_empty_rest_of_line ();
2017 return;
2018 }
2019
2020 #ifdef md_cons_align
2021 md_cons_align (nbytes);
2022 #endif
2023
2024 mapping_state (MAP_DATA);
2025 do
2026 {
2027 int reloc;
2028 char *base = input_line_pointer;
2029
2030 expression (& exp);
2031
2032 if (exp.X_op != O_symbol)
2033 emit_expr (&exp, (unsigned int) nbytes);
2034 else
2035 {
2036 char *before_reloc = input_line_pointer;
2037 reloc = parse_reloc (&input_line_pointer);
2038 if (reloc == -1)
2039 {
2040 as_bad (_("unrecognized relocation suffix"));
2041 ignore_rest_of_line ();
2042 return;
2043 }
2044 else if (reloc == BFD_RELOC_UNUSED)
2045 emit_expr (&exp, (unsigned int) nbytes);
2046 else
2047 {
2048 reloc_howto_type *howto = bfd_reloc_type_lookup (stdoutput, reloc);
2049 int size = bfd_get_reloc_size (howto);
2050
2051 if (reloc == BFD_RELOC_ARM_PLT32)
2052 {
2053 as_bad (_("(plt) is only valid on branch targets"));
2054 reloc = BFD_RELOC_UNUSED;
2055 size = 0;
2056 }
2057
2058 if (size > nbytes)
2059 as_bad (_("%s relocations do not fit in %d bytes"),
2060 howto->name, nbytes);
2061 else
2062 {
2063 /* We've parsed an expression stopping at O_symbol.
2064 But there may be more expression left now that we
2065 have parsed the relocation marker. Parse it again.
2066 XXX Surely there is a cleaner way to do this. */
2067 char *p = input_line_pointer;
2068 int offset;
2069 char *save_buf = alloca (input_line_pointer - base);
2070 memcpy (save_buf, base, input_line_pointer - base);
2071 memmove (base + (input_line_pointer - before_reloc),
2072 base, before_reloc - base);
2073
2074 input_line_pointer = base + (input_line_pointer-before_reloc);
2075 expression (&exp);
2076 memcpy (base, save_buf, p - base);
2077
2078 offset = nbytes - size;
2079 p = frag_more ((int) nbytes);
2080 fix_new_exp (frag_now, p - frag_now->fr_literal + offset,
2081 size, &exp, 0, reloc);
2082 }
2083 }
2084 }
2085 }
2086 while (*input_line_pointer++ == ',');
2087
2088 /* Put terminator back into stream. */
2089 input_line_pointer --;
2090 demand_empty_rest_of_line ();
2091 }
2092
2093
2094 /* Parse a .rel31 directive. */
2095
2096 static void
2097 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED)
2098 {
2099 expressionS exp;
2100 char *p;
2101 valueT highbit;
2102
2103 highbit = 0;
2104 if (*input_line_pointer == '1')
2105 highbit = 0x80000000;
2106 else if (*input_line_pointer != '0')
2107 as_bad (_("expected 0 or 1"));
2108
2109 input_line_pointer++;
2110 if (*input_line_pointer != ',')
2111 as_bad (_("missing comma"));
2112 input_line_pointer++;
2113
2114 #ifdef md_flush_pending_output
2115 md_flush_pending_output ();
2116 #endif
2117
2118 #ifdef md_cons_align
2119 md_cons_align (4);
2120 #endif
2121
2122 mapping_state (MAP_DATA);
2123
2124 expression (&exp);
2125
2126 p = frag_more (4);
2127 md_number_to_chars (p, highbit, 4);
2128 fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 1,
2129 BFD_RELOC_ARM_PREL31);
2130
2131 demand_empty_rest_of_line ();
2132 }
2133
2134 /* Directives: AEABI stack-unwind tables. */
2135
2136 /* Parse an unwind_fnstart directive. Simply records the current location. */
2137
2138 static void
2139 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED)
2140 {
2141 demand_empty_rest_of_line ();
2142 /* Mark the start of the function. */
2143 unwind.proc_start = expr_build_dot ();
2144
2145 /* Reset the rest of the unwind info. */
2146 unwind.opcode_count = 0;
2147 unwind.table_entry = NULL;
2148 unwind.personality_routine = NULL;
2149 unwind.personality_index = -1;
2150 unwind.frame_size = 0;
2151 unwind.fp_offset = 0;
2152 unwind.fp_reg = 13;
2153 unwind.fp_used = 0;
2154 unwind.sp_restored = 0;
2155 }
2156
2157
2158 /* Parse a handlerdata directive. Creates the exception handling table entry
2159 for the function. */
2160
2161 static void
2162 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED)
2163 {
2164 demand_empty_rest_of_line ();
2165 if (unwind.table_entry)
2166 as_bad (_("dupicate .handlerdata directive"));
2167
2168 create_unwind_entry (1);
2169 }
2170
2171 /* Parse an unwind_fnend directive. Generates the index table entry. */
2172
2173 static void
2174 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED)
2175 {
2176 long where;
2177 char *ptr;
2178 valueT val;
2179
2180 demand_empty_rest_of_line ();
2181
2182 /* Add eh table entry. */
2183 if (unwind.table_entry == NULL)
2184 val = create_unwind_entry (0);
2185 else
2186 val = 0;
2187
2188 /* Add index table entry. This is two words. */
2189 start_unwind_section (unwind.saved_seg, 1);
2190 frag_align (2, 0, 0);
2191 record_alignment (now_seg, 2);
2192
2193 ptr = frag_more (8);
2194 where = frag_now_fix () - 8;
2195
2196 /* Self relative offset of the function start. */
2197 fix_new (frag_now, where, 4, unwind.proc_start, 0, 1,
2198 BFD_RELOC_ARM_PREL31);
2199
2200 /* Indicate dependency on EHABI-defined personality routines to the
2201 linker, if it hasn't been done already. */
2202 if (unwind.personality_index >= 0 && unwind.personality_index < 3
2203 && !(marked_pr_dependency & (1 << unwind.personality_index)))
2204 {
2205 static const char *const name[] = {
2206 "__aeabi_unwind_cpp_pr0",
2207 "__aeabi_unwind_cpp_pr1",
2208 "__aeabi_unwind_cpp_pr2"
2209 };
2210 symbolS *pr = symbol_find_or_make (name[unwind.personality_index]);
2211 fix_new (frag_now, where, 0, pr, 0, 1, BFD_RELOC_NONE);
2212 marked_pr_dependency |= 1 << unwind.personality_index;
2213 seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency
2214 = marked_pr_dependency;
2215 }
2216
2217 if (val)
2218 /* Inline exception table entry. */
2219 md_number_to_chars (ptr + 4, val, 4);
2220 else
2221 /* Self relative offset of the table entry. */
2222 fix_new (frag_now, where + 4, 4, unwind.table_entry, 0, 1,
2223 BFD_RELOC_ARM_PREL31);
2224
2225 /* Restore the original section. */
2226 subseg_set (unwind.saved_seg, unwind.saved_subseg);
2227 }
2228
2229
2230 /* Parse an unwind_cantunwind directive. */
2231
2232 static void
2233 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED)
2234 {
2235 demand_empty_rest_of_line ();
2236 if (unwind.personality_routine || unwind.personality_index != -1)
2237 as_bad (_("personality routine specified for cantunwind frame"));
2238
2239 unwind.personality_index = -2;
2240 }
2241
2242
2243 /* Parse a personalityindex directive. */
2244
2245 static void
2246 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED)
2247 {
2248 expressionS exp;
2249
2250 if (unwind.personality_routine || unwind.personality_index != -1)
2251 as_bad (_("duplicate .personalityindex directive"));
2252
2253 expression (&exp);
2254
2255 if (exp.X_op != O_constant
2256 || exp.X_add_number < 0 || exp.X_add_number > 15)
2257 {
2258 as_bad (_("bad personality routine number"));
2259 ignore_rest_of_line ();
2260 return;
2261 }
2262
2263 unwind.personality_index = exp.X_add_number;
2264
2265 demand_empty_rest_of_line ();
2266 }
2267
2268
2269 /* Parse a personality directive. */
2270
2271 static void
2272 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED)
2273 {
2274 char *name, *p, c;
2275
2276 if (unwind.personality_routine || unwind.personality_index != -1)
2277 as_bad (_("duplicate .personality directive"));
2278
2279 name = input_line_pointer;
2280 c = get_symbol_end ();
2281 p = input_line_pointer;
2282 unwind.personality_routine = symbol_find_or_make (name);
2283 *p = c;
2284 demand_empty_rest_of_line ();
2285 }
2286
2287
2288 /* Parse a directive saving core registers. */
2289
2290 static void
2291 s_arm_unwind_save_core (void)
2292 {
2293 valueT op;
2294 long range;
2295 int n;
2296
2297 range = parse_reg_list (&input_line_pointer);
2298 if (range == FAIL)
2299 {
2300 as_bad (_("expected register list"));
2301 ignore_rest_of_line ();
2302 return;
2303 }
2304
2305 demand_empty_rest_of_line ();
2306
2307 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
2308 into .unwind_save {..., sp...}. We aren't bothered about the value of
2309 ip because it is clobbered by calls. */
2310 if (unwind.sp_restored && unwind.fp_reg == 12
2311 && (range & 0x3000) == 0x1000)
2312 {
2313 unwind.opcode_count--;
2314 unwind.sp_restored = 0;
2315 range = (range | 0x2000) & ~0x1000;
2316 unwind.pending_offset = 0;
2317 }
2318
2319 /* Pop r4-r15. */
2320 if (range & 0xfff0)
2321 {
2322 /* See if we can use the short opcodes. These pop a block of up to 8
2323 registers starting with r4, plus maybe r14. */
2324 for (n = 0; n < 8; n++)
2325 {
2326 /* Break at the first non-saved register. */
2327 if ((range & (1 << (n + 4))) == 0)
2328 break;
2329 }
2330 /* See if there are any other bits set. */
2331 if (n == 0 || (range & (0xfff0 << n) & 0xbff0) != 0)
2332 {
2333 /* Use the long form. */
2334 op = 0x8000 | ((range >> 4) & 0xfff);
2335 add_unwind_opcode (op, 2);
2336 }
2337 else
2338 {
2339 /* Use the short form. */
2340 if (range & 0x4000)
2341 op = 0xa8; /* Pop r14. */
2342 else
2343 op = 0xa0; /* Do not pop r14. */
2344 op |= (n - 1);
2345 add_unwind_opcode (op, 1);
2346 }
2347 }
2348
2349 /* Pop r0-r3. */
2350 if (range & 0xf)
2351 {
2352 op = 0xb100 | (range & 0xf);
2353 add_unwind_opcode (op, 2);
2354 }
2355
2356 /* Record the number of bytes pushed. */
2357 for (n = 0; n < 16; n++)
2358 {
2359 if (range & (1 << n))
2360 unwind.frame_size += 4;
2361 }
2362 }
2363
2364
2365 /* Parse a directive saving FPA registers. */
2366
2367 static void
2368 s_arm_unwind_save_fpa (int reg)
2369 {
2370 expressionS exp;
2371 int num_regs;
2372 valueT op;
2373
2374 /* Get Number of registers to transfer. */
2375 if (skip_past_comma (&input_line_pointer) != FAIL)
2376 expression (&exp);
2377 else
2378 exp.X_op = O_illegal;
2379
2380 if (exp.X_op != O_constant)
2381 {
2382 as_bad (_("expected , <constant>"));
2383 ignore_rest_of_line ();
2384 return;
2385 }
2386
2387 num_regs = exp.X_add_number;
2388
2389 if (num_regs < 1 || num_regs > 4)
2390 {
2391 as_bad (_("number of registers must be in the range [1:4]"));
2392 ignore_rest_of_line ();
2393 return;
2394 }
2395
2396 demand_empty_rest_of_line ();
2397
2398 if (reg == 4)
2399 {
2400 /* Short form. */
2401 op = 0xb4 | (num_regs - 1);
2402 add_unwind_opcode (op, 1);
2403 }
2404 else
2405 {
2406 /* Long form. */
2407 op = 0xc800 | (reg << 4) | (num_regs - 1);
2408 add_unwind_opcode (op, 2);
2409 }
2410 unwind.frame_size += num_regs * 12;
2411 }
2412
2413
2414 /* Parse a directive saving VFP registers. */
2415
2416 static void
2417 s_arm_unwind_save_vfp (void)
2418 {
2419 int count;
2420 unsigned int reg;
2421 valueT op;
2422
2423 count = parse_vfp_reg_list (&input_line_pointer, &reg, 1);
2424 if (count == FAIL)
2425 {
2426 as_bad (_("expected register list"));
2427 ignore_rest_of_line ();
2428 return;
2429 }
2430
2431 demand_empty_rest_of_line ();
2432
2433 if (reg == 8)
2434 {
2435 /* Short form. */
2436 op = 0xb8 | (count - 1);
2437 add_unwind_opcode (op, 1);
2438 }
2439 else
2440 {
2441 /* Long form. */
2442 op = 0xb300 | (reg << 4) | (count - 1);
2443 add_unwind_opcode (op, 2);
2444 }
2445 unwind.frame_size += count * 8 + 4;
2446 }
2447
2448
2449 /* Parse a directive saving iWMMXt data registers. */
2450
2451 static void
2452 s_arm_unwind_save_mmxwr (void)
2453 {
2454 int reg;
2455 int hi_reg;
2456 int i;
2457 unsigned mask = 0;
2458 valueT op;
2459
2460 if (*input_line_pointer == '{')
2461 input_line_pointer++;
2462
2463 do
2464 {
2465 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
2466
2467 if (reg == FAIL)
2468 {
2469 as_bad (_(reg_expected_msgs[REG_TYPE_MMXWR]));
2470 goto error;
2471 }
2472
2473 if (mask >> reg)
2474 as_tsktsk (_("register list not in ascending order"));
2475 mask |= 1 << reg;
2476
2477 if (*input_line_pointer == '-')
2478 {
2479 input_line_pointer++;
2480 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
2481 if (hi_reg == FAIL)
2482 {
2483 as_bad (_(reg_expected_msgs[REG_TYPE_MMXWR]));
2484 goto error;
2485 }
2486 else if (reg >= hi_reg)
2487 {
2488 as_bad (_("bad register range"));
2489 goto error;
2490 }
2491 for (; reg < hi_reg; reg++)
2492 mask |= 1 << reg;
2493 }
2494 }
2495 while (skip_past_comma (&input_line_pointer) != FAIL);
2496
2497 if (*input_line_pointer == '}')
2498 input_line_pointer++;
2499
2500 demand_empty_rest_of_line ();
2501
2502 /* Generate any deferred opcodes becuuse we're going to be looking at
2503 the list. */
2504 flush_pending_unwind ();
2505
2506 for (i = 0; i < 16; i++)
2507 {
2508 if (mask & (1 << i))
2509 unwind.frame_size += 8;
2510 }
2511
2512 /* Attempt to combine with a previous opcode. We do this because gcc
2513 likes to output separate unwind directives for a single block of
2514 registers. */
2515 if (unwind.opcode_count > 0)
2516 {
2517 i = unwind.opcodes[unwind.opcode_count - 1];
2518 if ((i & 0xf8) == 0xc0)
2519 {
2520 i &= 7;
2521 /* Only merge if the blocks are contiguous. */
2522 if (i < 6)
2523 {
2524 if ((mask & 0xfe00) == (1 << 9))
2525 {
2526 mask |= ((1 << (i + 11)) - 1) & 0xfc00;
2527 unwind.opcode_count--;
2528 }
2529 }
2530 else if (i == 6 && unwind.opcode_count >= 2)
2531 {
2532 i = unwind.opcodes[unwind.opcode_count - 2];
2533 reg = i >> 4;
2534 i &= 0xf;
2535
2536 op = 0xffff << (reg - 1);
2537 if (reg > 0
2538 || ((mask & op) == (1u << (reg - 1))))
2539 {
2540 op = (1 << (reg + i + 1)) - 1;
2541 op &= ~((1 << reg) - 1);
2542 mask |= op;
2543 unwind.opcode_count -= 2;
2544 }
2545 }
2546 }
2547 }
2548
2549 hi_reg = 15;
2550 /* We want to generate opcodes in the order the registers have been
2551 saved, ie. descending order. */
2552 for (reg = 15; reg >= -1; reg--)
2553 {
2554 /* Save registers in blocks. */
2555 if (reg < 0
2556 || !(mask & (1 << reg)))
2557 {
2558 /* We found an unsaved reg. Generate opcodes to save the
2559 preceeding block. */
2560 if (reg != hi_reg)
2561 {
2562 if (reg == 9)
2563 {
2564 /* Short form. */
2565 op = 0xc0 | (hi_reg - 10);
2566 add_unwind_opcode (op, 1);
2567 }
2568 else
2569 {
2570 /* Long form. */
2571 op = 0xc600 | ((reg + 1) << 4) | ((hi_reg - reg) - 1);
2572 add_unwind_opcode (op, 2);
2573 }
2574 }
2575 hi_reg = reg - 1;
2576 }
2577 }
2578
2579 return;
2580 error:
2581 ignore_rest_of_line ();
2582 }
2583
2584 static void
2585 s_arm_unwind_save_mmxwcg (void)
2586 {
2587 int reg;
2588 int hi_reg;
2589 unsigned mask = 0;
2590 valueT op;
2591
2592 if (*input_line_pointer == '{')
2593 input_line_pointer++;
2594
2595 do
2596 {
2597 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
2598
2599 if (reg == FAIL)
2600 {
2601 as_bad (_(reg_expected_msgs[REG_TYPE_MMXWCG]));
2602 goto error;
2603 }
2604
2605 reg -= 8;
2606 if (mask >> reg)
2607 as_tsktsk (_("register list not in ascending order"));
2608 mask |= 1 << reg;
2609
2610 if (*input_line_pointer == '-')
2611 {
2612 input_line_pointer++;
2613 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
2614 if (hi_reg == FAIL)
2615 {
2616 as_bad (_(reg_expected_msgs[REG_TYPE_MMXWCG]));
2617 goto error;
2618 }
2619 else if (reg >= hi_reg)
2620 {
2621 as_bad (_("bad register range"));
2622 goto error;
2623 }
2624 for (; reg < hi_reg; reg++)
2625 mask |= 1 << reg;
2626 }
2627 }
2628 while (skip_past_comma (&input_line_pointer) != FAIL);
2629
2630 if (*input_line_pointer == '}')
2631 input_line_pointer++;
2632
2633 demand_empty_rest_of_line ();
2634
2635 /* Generate any deferred opcodes becuuse we're going to be looking at
2636 the list. */
2637 flush_pending_unwind ();
2638
2639 for (reg = 0; reg < 16; reg++)
2640 {
2641 if (mask & (1 << reg))
2642 unwind.frame_size += 4;
2643 }
2644 op = 0xc700 | mask;
2645 add_unwind_opcode (op, 2);
2646 return;
2647 error:
2648 ignore_rest_of_line ();
2649 }
2650
2651
2652 /* Parse an unwind_save directive. */
2653
2654 static void
2655 s_arm_unwind_save (int ignored ATTRIBUTE_UNUSED)
2656 {
2657 char *peek;
2658 struct reg_entry *reg;
2659 bfd_boolean had_brace = FALSE;
2660
2661 /* Figure out what sort of save we have. */
2662 peek = input_line_pointer;
2663
2664 if (*peek == '{')
2665 {
2666 had_brace = TRUE;
2667 peek++;
2668 }
2669
2670 reg = arm_reg_parse_multi (&peek);
2671
2672 if (!reg)
2673 {
2674 as_bad (_("register expected"));
2675 ignore_rest_of_line ();
2676 return;
2677 }
2678
2679 switch (reg->type)
2680 {
2681 case REG_TYPE_FN:
2682 if (had_brace)
2683 {
2684 as_bad (_("FPA .unwind_save does not take a register list"));
2685 ignore_rest_of_line ();
2686 return;
2687 }
2688 s_arm_unwind_save_fpa (reg->number);
2689 return;
2690
2691 case REG_TYPE_RN: s_arm_unwind_save_core (); return;
2692 case REG_TYPE_VFD: s_arm_unwind_save_vfp (); return;
2693 case REG_TYPE_MMXWR: s_arm_unwind_save_mmxwr (); return;
2694 case REG_TYPE_MMXWCG: s_arm_unwind_save_mmxwcg (); return;
2695
2696 default:
2697 as_bad (_(".unwind_save does not support this kind of register"));
2698 ignore_rest_of_line ();
2699 }
2700 }
2701
2702
2703 /* Parse an unwind_movsp directive. */
2704
2705 static void
2706 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED)
2707 {
2708 int reg;
2709 valueT op;
2710
2711 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
2712 if (reg == FAIL)
2713 {
2714 as_bad (_(reg_expected_msgs[REG_TYPE_RN]));
2715 ignore_rest_of_line ();
2716 return;
2717 }
2718 demand_empty_rest_of_line ();
2719
2720 if (reg == REG_SP || reg == REG_PC)
2721 {
2722 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
2723 return;
2724 }
2725
2726 if (unwind.fp_reg != REG_SP)
2727 as_bad (_("unexpected .unwind_movsp directive"));
2728
2729 /* Generate opcode to restore the value. */
2730 op = 0x90 | reg;
2731 add_unwind_opcode (op, 1);
2732
2733 /* Record the information for later. */
2734 unwind.fp_reg = reg;
2735 unwind.fp_offset = unwind.frame_size;
2736 unwind.sp_restored = 1;
2737 }
2738
2739 /* Parse an unwind_pad directive. */
2740
2741 static void
2742 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED)
2743 {
2744 int offset;
2745
2746 if (immediate_for_directive (&offset) == FAIL)
2747 return;
2748
2749 if (offset & 3)
2750 {
2751 as_bad (_("stack increment must be multiple of 4"));
2752 ignore_rest_of_line ();
2753 return;
2754 }
2755
2756 /* Don't generate any opcodes, just record the details for later. */
2757 unwind.frame_size += offset;
2758 unwind.pending_offset += offset;
2759
2760 demand_empty_rest_of_line ();
2761 }
2762
2763 /* Parse an unwind_setfp directive. */
2764
2765 static void
2766 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED)
2767 {
2768 int sp_reg;
2769 int fp_reg;
2770 int offset;
2771
2772 fp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
2773 if (skip_past_comma (&input_line_pointer) == FAIL)
2774 sp_reg = FAIL;
2775 else
2776 sp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
2777
2778 if (fp_reg == FAIL || sp_reg == FAIL)
2779 {
2780 as_bad (_("expected <reg>, <reg>"));
2781 ignore_rest_of_line ();
2782 return;
2783 }
2784
2785 /* Optional constant. */
2786 if (skip_past_comma (&input_line_pointer) != FAIL)
2787 {
2788 if (immediate_for_directive (&offset) == FAIL)
2789 return;
2790 }
2791 else
2792 offset = 0;
2793
2794 demand_empty_rest_of_line ();
2795
2796 if (sp_reg != 13 && sp_reg != unwind.fp_reg)
2797 {
2798 as_bad (_("register must be either sp or set by a previous"
2799 "unwind_movsp directive"));
2800 return;
2801 }
2802
2803 /* Don't generate any opcodes, just record the information for later. */
2804 unwind.fp_reg = fp_reg;
2805 unwind.fp_used = 1;
2806 if (sp_reg == 13)
2807 unwind.fp_offset = unwind.frame_size - offset;
2808 else
2809 unwind.fp_offset -= offset;
2810 }
2811
2812 /* Parse an unwind_raw directive. */
2813
2814 static void
2815 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED)
2816 {
2817 expressionS exp;
2818 /* This is an arbitary limit. */
2819 unsigned char op[16];
2820 int count;
2821
2822 expression (&exp);
2823 if (exp.X_op == O_constant
2824 && skip_past_comma (&input_line_pointer) != FAIL)
2825 {
2826 unwind.frame_size += exp.X_add_number;
2827 expression (&exp);
2828 }
2829 else
2830 exp.X_op = O_illegal;
2831
2832 if (exp.X_op != O_constant)
2833 {
2834 as_bad (_("expected <offset>, <opcode>"));
2835 ignore_rest_of_line ();
2836 return;
2837 }
2838
2839 count = 0;
2840
2841 /* Parse the opcode. */
2842 for (;;)
2843 {
2844 if (count >= 16)
2845 {
2846 as_bad (_("unwind opcode too long"));
2847 ignore_rest_of_line ();
2848 }
2849 if (exp.X_op != O_constant || exp.X_add_number & ~0xff)
2850 {
2851 as_bad (_("invalid unwind opcode"));
2852 ignore_rest_of_line ();
2853 return;
2854 }
2855 op[count++] = exp.X_add_number;
2856
2857 /* Parse the next byte. */
2858 if (skip_past_comma (&input_line_pointer) == FAIL)
2859 break;
2860
2861 expression (&exp);
2862 }
2863
2864 /* Add the opcode bytes in reverse order. */
2865 while (count--)
2866 add_unwind_opcode (op[count], 1);
2867
2868 demand_empty_rest_of_line ();
2869 }
2870
2871
2872 /* Parse a .eabi_attribute directive. */
2873
2874 static void
2875 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED)
2876 {
2877 expressionS exp;
2878 bfd_boolean is_string;
2879 int tag;
2880 unsigned int i = 0;
2881 char *s = NULL;
2882 char saved_char;
2883
2884 expression (& exp);
2885 if (exp.X_op != O_constant)
2886 goto bad;
2887
2888 tag = exp.X_add_number;
2889 if (tag == 4 || tag == 5 || tag == 32 || (tag > 32 && (tag & 1) != 0))
2890 is_string = 1;
2891 else
2892 is_string = 0;
2893
2894 if (skip_past_comma (&input_line_pointer) == FAIL)
2895 goto bad;
2896 if (tag == 32 || !is_string)
2897 {
2898 expression (& exp);
2899 if (exp.X_op != O_constant)
2900 {
2901 as_bad (_("expected numeric constant"));
2902 ignore_rest_of_line ();
2903 return;
2904 }
2905 i = exp.X_add_number;
2906 }
2907 if (tag == Tag_compatibility
2908 && skip_past_comma (&input_line_pointer) == FAIL)
2909 {
2910 as_bad (_("expected comma"));
2911 ignore_rest_of_line ();
2912 return;
2913 }
2914 if (is_string)
2915 {
2916 skip_whitespace(input_line_pointer);
2917 if (*input_line_pointer != '"')
2918 goto bad_string;
2919 input_line_pointer++;
2920 s = input_line_pointer;
2921 while (*input_line_pointer && *input_line_pointer != '"')
2922 input_line_pointer++;
2923 if (*input_line_pointer != '"')
2924 goto bad_string;
2925 saved_char = *input_line_pointer;
2926 *input_line_pointer = 0;
2927 }
2928 else
2929 {
2930 s = NULL;
2931 saved_char = 0;
2932 }
2933
2934 if (tag == Tag_compatibility)
2935 elf32_arm_add_eabi_attr_compat (stdoutput, i, s);
2936 else if (is_string)
2937 elf32_arm_add_eabi_attr_string (stdoutput, tag, s);
2938 else
2939 elf32_arm_add_eabi_attr_int (stdoutput, tag, i);
2940
2941 if (s)
2942 {
2943 *input_line_pointer = saved_char;
2944 input_line_pointer++;
2945 }
2946 demand_empty_rest_of_line ();
2947 return;
2948 bad_string:
2949 as_bad (_("bad string constant"));
2950 ignore_rest_of_line ();
2951 return;
2952 bad:
2953 as_bad (_("expected <tag> , <value>"));
2954 ignore_rest_of_line ();
2955 }
2956
2957 static void s_arm_arch (int);
2958 static void s_arm_cpu (int);
2959 static void s_arm_fpu (int);
2960 #endif /* OBJ_ELF */
2961
2962 /* This table describes all the machine specific pseudo-ops the assembler
2963 has to support. The fields are:
2964 pseudo-op name without dot
2965 function to call to execute this pseudo-op
2966 Integer arg to pass to the function. */
2967
2968 const pseudo_typeS md_pseudo_table[] =
2969 {
2970 /* Never called because '.req' does not start a line. */
2971 { "req", s_req, 0 },
2972 { "unreq", s_unreq, 0 },
2973 { "bss", s_bss, 0 },
2974 { "align", s_align, 0 },
2975 { "arm", s_arm, 0 },
2976 { "thumb", s_thumb, 0 },
2977 { "code", s_code, 0 },
2978 { "force_thumb", s_force_thumb, 0 },
2979 { "thumb_func", s_thumb_func, 0 },
2980 { "thumb_set", s_thumb_set, 0 },
2981 { "even", s_even, 0 },
2982 { "ltorg", s_ltorg, 0 },
2983 { "pool", s_ltorg, 0 },
2984 { "syntax", s_syntax, 0 },
2985 #ifdef OBJ_ELF
2986 { "word", s_arm_elf_cons, 4 },
2987 { "long", s_arm_elf_cons, 4 },
2988 { "rel31", s_arm_rel31, 0 },
2989 { "fnstart", s_arm_unwind_fnstart, 0 },
2990 { "fnend", s_arm_unwind_fnend, 0 },
2991 { "cantunwind", s_arm_unwind_cantunwind, 0 },
2992 { "personality", s_arm_unwind_personality, 0 },
2993 { "personalityindex", s_arm_unwind_personalityindex, 0 },
2994 { "handlerdata", s_arm_unwind_handlerdata, 0 },
2995 { "save", s_arm_unwind_save, 0 },
2996 { "movsp", s_arm_unwind_movsp, 0 },
2997 { "pad", s_arm_unwind_pad, 0 },
2998 { "setfp", s_arm_unwind_setfp, 0 },
2999 { "unwind_raw", s_arm_unwind_raw, 0 },
3000 { "cpu", s_arm_cpu, 0 },
3001 { "arch", s_arm_arch, 0 },
3002 { "fpu", s_arm_fpu, 0 },
3003 { "eabi_attribute", s_arm_eabi_attribute, 0 },
3004 #else
3005 { "word", cons, 4},
3006 #endif
3007 { "extend", float_cons, 'x' },
3008 { "ldouble", float_cons, 'x' },
3009 { "packed", float_cons, 'p' },
3010 { 0, 0, 0 }
3011 };
3012 \f
3013 /* Parser functions used exclusively in instruction operands. */
3014
3015 /* Generic immediate-value read function for use in insn parsing.
3016 STR points to the beginning of the immediate (the leading #);
3017 VAL receives the value; if the value is outside [MIN, MAX]
3018 issue an error. PREFIX_OPT is true if the immediate prefix is
3019 optional. */
3020
3021 static int
3022 parse_immediate (char **str, int *val, int min, int max,
3023 bfd_boolean prefix_opt)
3024 {
3025 expressionS exp;
3026 my_get_expression (&exp, str, prefix_opt ? GE_OPT_PREFIX : GE_IMM_PREFIX);
3027 if (exp.X_op != O_constant)
3028 {
3029 inst.error = _("constant expression required");
3030 return FAIL;
3031 }
3032
3033 if (exp.X_add_number < min || exp.X_add_number > max)
3034 {
3035 inst.error = _("immediate value out of range");
3036 return FAIL;
3037 }
3038
3039 *val = exp.X_add_number;
3040 return SUCCESS;
3041 }
3042
3043 /* Returns the pseudo-register number of an FPA immediate constant,
3044 or FAIL if there isn't a valid constant here. */
3045
3046 static int
3047 parse_fpa_immediate (char ** str)
3048 {
3049 LITTLENUM_TYPE words[MAX_LITTLENUMS];
3050 char * save_in;
3051 expressionS exp;
3052 int i;
3053 int j;
3054
3055 /* First try and match exact strings, this is to guarantee
3056 that some formats will work even for cross assembly. */
3057
3058 for (i = 0; fp_const[i]; i++)
3059 {
3060 if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0)
3061 {
3062 char *start = *str;
3063
3064 *str += strlen (fp_const[i]);
3065 if (is_end_of_line[(unsigned char) **str])
3066 return i + 8;
3067 *str = start;
3068 }
3069 }
3070
3071 /* Just because we didn't get a match doesn't mean that the constant
3072 isn't valid, just that it is in a format that we don't
3073 automatically recognize. Try parsing it with the standard
3074 expression routines. */
3075
3076 memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE));
3077
3078 /* Look for a raw floating point number. */
3079 if ((save_in = atof_ieee (*str, 'x', words)) != NULL
3080 && is_end_of_line[(unsigned char) *save_in])
3081 {
3082 for (i = 0; i < NUM_FLOAT_VALS; i++)
3083 {
3084 for (j = 0; j < MAX_LITTLENUMS; j++)
3085 {
3086 if (words[j] != fp_values[i][j])
3087 break;
3088 }
3089
3090 if (j == MAX_LITTLENUMS)
3091 {
3092 *str = save_in;
3093 return i + 8;
3094 }
3095 }
3096 }
3097
3098 /* Try and parse a more complex expression, this will probably fail
3099 unless the code uses a floating point prefix (eg "0f"). */
3100 save_in = input_line_pointer;
3101 input_line_pointer = *str;
3102 if (expression (&exp) == absolute_section
3103 && exp.X_op == O_big
3104 && exp.X_add_number < 0)
3105 {
3106 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
3107 Ditto for 15. */
3108 if (gen_to_words (words, 5, (long) 15) == 0)
3109 {
3110 for (i = 0; i < NUM_FLOAT_VALS; i++)
3111 {
3112 for (j = 0; j < MAX_LITTLENUMS; j++)
3113 {
3114 if (words[j] != fp_values[i][j])
3115 break;
3116 }
3117
3118 if (j == MAX_LITTLENUMS)
3119 {
3120 *str = input_line_pointer;
3121 input_line_pointer = save_in;
3122 return i + 8;
3123 }
3124 }
3125 }
3126 }
3127
3128 *str = input_line_pointer;
3129 input_line_pointer = save_in;
3130 inst.error = _("invalid FPA immediate expression");
3131 return FAIL;
3132 }
3133
3134 /* Shift operands. */
3135 enum shift_kind
3136 {
3137 SHIFT_LSL, SHIFT_LSR, SHIFT_ASR, SHIFT_ROR, SHIFT_RRX
3138 };
3139
3140 struct asm_shift_name
3141 {
3142 const char *name;
3143 enum shift_kind kind;
3144 };
3145
3146 /* Third argument to parse_shift. */
3147 enum parse_shift_mode
3148 {
3149 NO_SHIFT_RESTRICT, /* Any kind of shift is accepted. */
3150 SHIFT_IMMEDIATE, /* Shift operand must be an immediate. */
3151 SHIFT_LSL_OR_ASR_IMMEDIATE, /* Shift must be LSL or ASR immediate. */
3152 SHIFT_ASR_IMMEDIATE, /* Shift must be ASR immediate. */
3153 SHIFT_LSL_IMMEDIATE, /* Shift must be LSL immediate. */
3154 };
3155
3156 /* Parse a <shift> specifier on an ARM data processing instruction.
3157 This has three forms:
3158
3159 (LSL|LSR|ASL|ASR|ROR) Rs
3160 (LSL|LSR|ASL|ASR|ROR) #imm
3161 RRX
3162
3163 Note that ASL is assimilated to LSL in the instruction encoding, and
3164 RRX to ROR #0 (which cannot be written as such). */
3165
3166 static int
3167 parse_shift (char **str, int i, enum parse_shift_mode mode)
3168 {
3169 const struct asm_shift_name *shift_name;
3170 enum shift_kind shift;
3171 char *s = *str;
3172 char *p = s;
3173 int reg;
3174
3175 for (p = *str; ISALPHA (*p); p++)
3176 ;
3177
3178 if (p == *str)
3179 {
3180 inst.error = _("shift expression expected");
3181 return FAIL;
3182 }
3183
3184 shift_name = hash_find_n (arm_shift_hsh, *str, p - *str);
3185
3186 if (shift_name == NULL)
3187 {
3188 inst.error = _("shift expression expected");
3189 return FAIL;
3190 }
3191
3192 shift = shift_name->kind;
3193
3194 switch (mode)
3195 {
3196 case NO_SHIFT_RESTRICT:
3197 case SHIFT_IMMEDIATE: break;
3198
3199 case SHIFT_LSL_OR_ASR_IMMEDIATE:
3200 if (shift != SHIFT_LSL && shift != SHIFT_ASR)
3201 {
3202 inst.error = _("'LSL' or 'ASR' required");
3203 return FAIL;
3204 }
3205 break;
3206
3207 case SHIFT_LSL_IMMEDIATE:
3208 if (shift != SHIFT_LSL)
3209 {
3210 inst.error = _("'LSL' required");
3211 return FAIL;
3212 }
3213 break;
3214
3215 case SHIFT_ASR_IMMEDIATE:
3216 if (shift != SHIFT_ASR)
3217 {
3218 inst.error = _("'ASR' required");
3219 return FAIL;
3220 }
3221 break;
3222
3223 default: abort ();
3224 }
3225
3226 if (shift != SHIFT_RRX)
3227 {
3228 /* Whitespace can appear here if the next thing is a bare digit. */
3229 skip_whitespace (p);
3230
3231 if (mode == NO_SHIFT_RESTRICT
3232 && (reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
3233 {
3234 inst.operands[i].imm = reg;
3235 inst.operands[i].immisreg = 1;
3236 }
3237 else if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
3238 return FAIL;
3239 }
3240 inst.operands[i].shift_kind = shift;
3241 inst.operands[i].shifted = 1;
3242 *str = p;
3243 return SUCCESS;
3244 }
3245
3246 /* Parse a <shifter_operand> for an ARM data processing instruction:
3247
3248 #<immediate>
3249 #<immediate>, <rotate>
3250 <Rm>
3251 <Rm>, <shift>
3252
3253 where <shift> is defined by parse_shift above, and <rotate> is a
3254 multiple of 2 between 0 and 30. Validation of immediate operands
3255 is deferred to md_apply_fix. */
3256
3257 static int
3258 parse_shifter_operand (char **str, int i)
3259 {
3260 int value;
3261 expressionS expr;
3262
3263 if ((value = arm_reg_parse (str, REG_TYPE_RN)) != FAIL)
3264 {
3265 inst.operands[i].reg = value;
3266 inst.operands[i].isreg = 1;
3267
3268 /* parse_shift will override this if appropriate */
3269 inst.reloc.exp.X_op = O_constant;
3270 inst.reloc.exp.X_add_number = 0;
3271
3272 if (skip_past_comma (str) == FAIL)
3273 return SUCCESS;
3274
3275 /* Shift operation on register. */
3276 return parse_shift (str, i, NO_SHIFT_RESTRICT);
3277 }
3278
3279 if (my_get_expression (&inst.reloc.exp, str, GE_IMM_PREFIX))
3280 return FAIL;
3281
3282 if (skip_past_comma (str) == SUCCESS)
3283 {
3284 /* #x, y -- ie explicit rotation by Y. */
3285 if (my_get_expression (&expr, str, GE_NO_PREFIX))
3286 return FAIL;
3287
3288 if (expr.X_op != O_constant || inst.reloc.exp.X_op != O_constant)
3289 {
3290 inst.error = _("constant expression expected");
3291 return FAIL;
3292 }
3293
3294 value = expr.X_add_number;
3295 if (value < 0 || value > 30 || value % 2 != 0)
3296 {
3297 inst.error = _("invalid rotation");
3298 return FAIL;
3299 }
3300 if (inst.reloc.exp.X_add_number < 0 || inst.reloc.exp.X_add_number > 255)
3301 {
3302 inst.error = _("invalid constant");
3303 return FAIL;
3304 }
3305
3306 /* Convert to decoded value. md_apply_fix will put it back. */
3307 inst.reloc.exp.X_add_number
3308 = (((inst.reloc.exp.X_add_number << (32 - value))
3309 | (inst.reloc.exp.X_add_number >> value)) & 0xffffffff);
3310 }
3311
3312 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
3313 inst.reloc.pc_rel = 0;
3314 return SUCCESS;
3315 }
3316
3317 /* Parse all forms of an ARM address expression. Information is written
3318 to inst.operands[i] and/or inst.reloc.
3319
3320 Preindexed addressing (.preind=1):
3321
3322 [Rn, #offset] .reg=Rn .reloc.exp=offset
3323 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
3324 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
3325 .shift_kind=shift .reloc.exp=shift_imm
3326
3327 These three may have a trailing ! which causes .writeback to be set also.
3328
3329 Postindexed addressing (.postind=1, .writeback=1):
3330
3331 [Rn], #offset .reg=Rn .reloc.exp=offset
3332 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
3333 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
3334 .shift_kind=shift .reloc.exp=shift_imm
3335
3336 Unindexed addressing (.preind=0, .postind=0):
3337
3338 [Rn], {option} .reg=Rn .imm=option .immisreg=0
3339
3340 Other:
3341
3342 [Rn]{!} shorthand for [Rn,#0]{!}
3343 =immediate .isreg=0 .reloc.exp=immediate
3344 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
3345
3346 It is the caller's responsibility to check for addressing modes not
3347 supported by the instruction, and to set inst.reloc.type. */
3348
3349 static int
3350 parse_address (char **str, int i)
3351 {
3352 char *p = *str;
3353 int reg;
3354
3355 if (skip_past_char (&p, '[') == FAIL)
3356 {
3357 if (skip_past_char (&p, '=') == FAIL)
3358 {
3359 /* bare address - translate to PC-relative offset */
3360 inst.reloc.pc_rel = 1;
3361 inst.operands[i].reg = REG_PC;
3362 inst.operands[i].isreg = 1;
3363 inst.operands[i].preind = 1;
3364 }
3365 /* else a load-constant pseudo op, no special treatment needed here */
3366
3367 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
3368 return FAIL;
3369
3370 *str = p;
3371 return SUCCESS;
3372 }
3373
3374 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
3375 {
3376 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
3377 return FAIL;
3378 }
3379 inst.operands[i].reg = reg;
3380 inst.operands[i].isreg = 1;
3381
3382 if (skip_past_comma (&p) == SUCCESS)
3383 {
3384 inst.operands[i].preind = 1;
3385
3386 if (*p == '+') p++;
3387 else if (*p == '-') p++, inst.operands[i].negative = 1;
3388
3389 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
3390 {
3391 inst.operands[i].imm = reg;
3392 inst.operands[i].immisreg = 1;
3393
3394 if (skip_past_comma (&p) == SUCCESS)
3395 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
3396 return FAIL;
3397 }
3398 else
3399 {
3400 if (inst.operands[i].negative)
3401 {
3402 inst.operands[i].negative = 0;
3403 p--;
3404 }
3405 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
3406 return FAIL;
3407 }
3408 }
3409
3410 if (skip_past_char (&p, ']') == FAIL)
3411 {
3412 inst.error = _("']' expected");
3413 return FAIL;
3414 }
3415
3416 if (skip_past_char (&p, '!') == SUCCESS)
3417 inst.operands[i].writeback = 1;
3418
3419 else if (skip_past_comma (&p) == SUCCESS)
3420 {
3421 if (skip_past_char (&p, '{') == SUCCESS)
3422 {
3423 /* [Rn], {expr} - unindexed, with option */
3424 if (parse_immediate (&p, &inst.operands[i].imm,
3425 0, 255, TRUE) == FAIL)
3426 return FAIL;
3427
3428 if (skip_past_char (&p, '}') == FAIL)
3429 {
3430 inst.error = _("'}' expected at end of 'option' field");
3431 return FAIL;
3432 }
3433 if (inst.operands[i].preind)
3434 {
3435 inst.error = _("cannot combine index with option");
3436 return FAIL;
3437 }
3438 *str = p;
3439 return SUCCESS;
3440 }
3441 else
3442 {
3443 inst.operands[i].postind = 1;
3444 inst.operands[i].writeback = 1;
3445
3446 if (inst.operands[i].preind)
3447 {
3448 inst.error = _("cannot combine pre- and post-indexing");
3449 return FAIL;
3450 }
3451
3452 if (*p == '+') p++;
3453 else if (*p == '-') p++, inst.operands[i].negative = 1;
3454
3455 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
3456 {
3457 inst.operands[i].imm = reg;
3458 inst.operands[i].immisreg = 1;
3459
3460 if (skip_past_comma (&p) == SUCCESS)
3461 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
3462 return FAIL;
3463 }
3464 else
3465 {
3466 if (inst.operands[i].negative)
3467 {
3468 inst.operands[i].negative = 0;
3469 p--;
3470 }
3471 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
3472 return FAIL;
3473 }
3474 }
3475 }
3476
3477 /* If at this point neither .preind nor .postind is set, we have a
3478 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
3479 if (inst.operands[i].preind == 0 && inst.operands[i].postind == 0)
3480 {
3481 inst.operands[i].preind = 1;
3482 inst.reloc.exp.X_op = O_constant;
3483 inst.reloc.exp.X_add_number = 0;
3484 }
3485 *str = p;
3486 return SUCCESS;
3487 }
3488
3489 /* Miscellaneous. */
3490
3491 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
3492 or a bitmask suitable to be or-ed into the ARM msr instruction. */
3493 static int
3494 parse_psr (char **str)
3495 {
3496 char *p;
3497 unsigned long psr_field;
3498 const struct asm_psr *psr;
3499 char *start;
3500
3501 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
3502 feature for ease of use and backwards compatibility. */
3503 p = *str;
3504 if (strncasecmp (p, "SPSR", 4) == 0)
3505 psr_field = SPSR_BIT;
3506 else if (strncasecmp (p, "CPSR", 4) == 0)
3507 psr_field = 0;
3508 else
3509 {
3510 start = p;
3511 do
3512 p++;
3513 while (ISALNUM (*p) || *p == '_');
3514
3515 psr = hash_find_n (arm_v7m_psr_hsh, start, p - start);
3516 if (!psr)
3517 return FAIL;
3518
3519 *str = p;
3520 return psr->field;
3521 }
3522
3523 p += 4;
3524 if (*p == '_')
3525 {
3526 /* A suffix follows. */
3527 p++;
3528 start = p;
3529
3530 do
3531 p++;
3532 while (ISALNUM (*p) || *p == '_');
3533
3534 psr = hash_find_n (arm_psr_hsh, start, p - start);
3535 if (!psr)
3536 goto error;
3537
3538 psr_field |= psr->field;
3539 }
3540 else
3541 {
3542 if (ISALNUM (*p))
3543 goto error; /* Garbage after "[CS]PSR". */
3544
3545 psr_field |= (PSR_c | PSR_f);
3546 }
3547 *str = p;
3548 return psr_field;
3549
3550 error:
3551 inst.error = _("flag for {c}psr instruction expected");
3552 return FAIL;
3553 }
3554
3555 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
3556 value suitable for splatting into the AIF field of the instruction. */
3557
3558 static int
3559 parse_cps_flags (char **str)
3560 {
3561 int val = 0;
3562 int saw_a_flag = 0;
3563 char *s = *str;
3564
3565 for (;;)
3566 switch (*s++)
3567 {
3568 case '\0': case ',':
3569 goto done;
3570
3571 case 'a': case 'A': saw_a_flag = 1; val |= 0x4; break;
3572 case 'i': case 'I': saw_a_flag = 1; val |= 0x2; break;
3573 case 'f': case 'F': saw_a_flag = 1; val |= 0x1; break;
3574
3575 default:
3576 inst.error = _("unrecognized CPS flag");
3577 return FAIL;
3578 }
3579
3580 done:
3581 if (saw_a_flag == 0)
3582 {
3583 inst.error = _("missing CPS flags");
3584 return FAIL;
3585 }
3586
3587 *str = s - 1;
3588 return val;
3589 }
3590
3591 /* Parse an endian specifier ("BE" or "LE", case insensitive);
3592 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
3593
3594 static int
3595 parse_endian_specifier (char **str)
3596 {
3597 int little_endian;
3598 char *s = *str;
3599
3600 if (strncasecmp (s, "BE", 2))
3601 little_endian = 0;
3602 else if (strncasecmp (s, "LE", 2))
3603 little_endian = 1;
3604 else
3605 {
3606 inst.error = _("valid endian specifiers are be or le");
3607 return FAIL;
3608 }
3609
3610 if (ISALNUM (s[2]) || s[2] == '_')
3611 {
3612 inst.error = _("valid endian specifiers are be or le");
3613 return FAIL;
3614 }
3615
3616 *str = s + 2;
3617 return little_endian;
3618 }
3619
3620 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
3621 value suitable for poking into the rotate field of an sxt or sxta
3622 instruction, or FAIL on error. */
3623
3624 static int
3625 parse_ror (char **str)
3626 {
3627 int rot;
3628 char *s = *str;
3629
3630 if (strncasecmp (s, "ROR", 3) == 0)
3631 s += 3;
3632 else
3633 {
3634 inst.error = _("missing rotation field after comma");
3635 return FAIL;
3636 }
3637
3638 if (parse_immediate (&s, &rot, 0, 24, FALSE) == FAIL)
3639 return FAIL;
3640
3641 switch (rot)
3642 {
3643 case 0: *str = s; return 0x0;
3644 case 8: *str = s; return 0x1;
3645 case 16: *str = s; return 0x2;
3646 case 24: *str = s; return 0x3;
3647
3648 default:
3649 inst.error = _("rotation can only be 0, 8, 16, or 24");
3650 return FAIL;
3651 }
3652 }
3653
3654 /* Parse a conditional code (from conds[] below). The value returned is in the
3655 range 0 .. 14, or FAIL. */
3656 static int
3657 parse_cond (char **str)
3658 {
3659 char *p, *q;
3660 const struct asm_cond *c;
3661
3662 p = q = *str;
3663 while (ISALPHA (*q))
3664 q++;
3665
3666 c = hash_find_n (arm_cond_hsh, p, q - p);
3667 if (!c)
3668 {
3669 inst.error = _("condition required");
3670 return FAIL;
3671 }
3672
3673 *str = q;
3674 return c->value;
3675 }
3676
3677 /* Parse an option for a barrier instruction. Returns the encoding for the
3678 option, or FAIL. */
3679 static int
3680 parse_barrier (char **str)
3681 {
3682 char *p, *q;
3683 const struct asm_barrier_opt *o;
3684
3685 p = q = *str;
3686 while (ISALPHA (*q))
3687 q++;
3688
3689 o = hash_find_n (arm_barrier_opt_hsh, p, q - p);
3690 if (!o)
3691 return FAIL;
3692
3693 *str = q;
3694 return o->value;
3695 }
3696
3697 /* Parse the operands of a table branch instruction. Similar to a memory
3698 operand. */
3699 static int
3700 parse_tb (char **str)
3701 {
3702 char * p = *str;
3703 int reg;
3704
3705 if (skip_past_char (&p, '[') == FAIL)
3706 return FAIL;
3707
3708 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
3709 {
3710 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
3711 return FAIL;
3712 }
3713 inst.operands[0].reg = reg;
3714
3715 if (skip_past_comma (&p) == FAIL)
3716 return FAIL;
3717
3718 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
3719 {
3720 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
3721 return FAIL;
3722 }
3723 inst.operands[0].imm = reg;
3724
3725 if (skip_past_comma (&p) == SUCCESS)
3726 {
3727 if (parse_shift (&p, 0, SHIFT_LSL_IMMEDIATE) == FAIL)
3728 return FAIL;
3729 if (inst.reloc.exp.X_add_number != 1)
3730 {
3731 inst.error = _("invalid shift");
3732 return FAIL;
3733 }
3734 inst.operands[0].shifted = 1;
3735 }
3736
3737 if (skip_past_char (&p, ']') == FAIL)
3738 {
3739 inst.error = _("']' expected");
3740 return FAIL;
3741 }
3742 *str = p;
3743 return SUCCESS;
3744 }
3745
3746 /* Matcher codes for parse_operands. */
3747 enum operand_parse_code
3748 {
3749 OP_stop, /* end of line */
3750
3751 OP_RR, /* ARM register */
3752 OP_RRnpc, /* ARM register, not r15 */
3753 OP_RRnpcb, /* ARM register, not r15, in square brackets */
3754 OP_RRw, /* ARM register, not r15, optional trailing ! */
3755 OP_RCP, /* Coprocessor number */
3756 OP_RCN, /* Coprocessor register */
3757 OP_RF, /* FPA register */
3758 OP_RVS, /* VFP single precision register */
3759 OP_RVD, /* VFP double precision register */
3760 OP_RVC, /* VFP control register */
3761 OP_RMF, /* Maverick F register */
3762 OP_RMD, /* Maverick D register */
3763 OP_RMFX, /* Maverick FX register */
3764 OP_RMDX, /* Maverick DX register */
3765 OP_RMAX, /* Maverick AX register */
3766 OP_RMDS, /* Maverick DSPSC register */
3767 OP_RIWR, /* iWMMXt wR register */
3768 OP_RIWC, /* iWMMXt wC register */
3769 OP_RIWG, /* iWMMXt wCG register */
3770 OP_RXA, /* XScale accumulator register */
3771
3772 OP_REGLST, /* ARM register list */
3773 OP_VRSLST, /* VFP single-precision register list */
3774 OP_VRDLST, /* VFP double-precision register list */
3775
3776 OP_I7, /* immediate value 0 .. 7 */
3777 OP_I15, /* 0 .. 15 */
3778 OP_I16, /* 1 .. 16 */
3779 OP_I31, /* 0 .. 31 */
3780 OP_I31w, /* 0 .. 31, optional trailing ! */
3781 OP_I32, /* 1 .. 32 */
3782 OP_I63s, /* -64 .. 63 */
3783 OP_I255, /* 0 .. 255 */
3784 OP_Iffff, /* 0 .. 65535 */
3785
3786 OP_I4b, /* immediate, prefix optional, 1 .. 4 */
3787 OP_I7b, /* 0 .. 7 */
3788 OP_I15b, /* 0 .. 15 */
3789 OP_I31b, /* 0 .. 31 */
3790
3791 OP_SH, /* shifter operand */
3792 OP_ADDR, /* Memory address expression (any mode) */
3793 OP_EXP, /* arbitrary expression */
3794 OP_EXPi, /* same, with optional immediate prefix */
3795 OP_EXPr, /* same, with optional relocation suffix */
3796
3797 OP_CPSF, /* CPS flags */
3798 OP_ENDI, /* Endianness specifier */
3799 OP_PSR, /* CPSR/SPSR mask for msr */
3800 OP_COND, /* conditional code */
3801 OP_TB, /* Table branch. */
3802
3803 OP_RRnpc_I0, /* ARM register or literal 0 */
3804 OP_RR_EXr, /* ARM register or expression with opt. reloc suff. */
3805 OP_RR_EXi, /* ARM register or expression with imm prefix */
3806 OP_RF_IF, /* FPA register or immediate */
3807 OP_RIWR_RIWC, /* iWMMXt R or C reg */
3808
3809 /* Optional operands. */
3810 OP_oI7b, /* immediate, prefix optional, 0 .. 7 */
3811 OP_oI31b, /* 0 .. 31 */
3812 OP_oIffffb, /* 0 .. 65535 */
3813 OP_oI255c, /* curly-brace enclosed, 0 .. 255 */
3814
3815 OP_oRR, /* ARM register */
3816 OP_oRRnpc, /* ARM register, not the PC */
3817 OP_oSHll, /* LSL immediate */
3818 OP_oSHar, /* ASR immediate */
3819 OP_oSHllar, /* LSL or ASR immediate */
3820 OP_oROR, /* ROR 0/8/16/24 */
3821 OP_oBARRIER, /* Option argument for a barrier instruction. */
3822
3823 OP_FIRST_OPTIONAL = OP_oI7b
3824 };
3825
3826 /* Generic instruction operand parser. This does no encoding and no
3827 semantic validation; it merely squirrels values away in the inst
3828 structure. Returns SUCCESS or FAIL depending on whether the
3829 specified grammar matched. */
3830 static int
3831 parse_operands (char *str, const unsigned char *pattern)
3832 {
3833 unsigned const char *upat = pattern;
3834 char *backtrack_pos = 0;
3835 const char *backtrack_error = 0;
3836 int i, val, backtrack_index = 0;
3837
3838 #define po_char_or_fail(chr) do { \
3839 if (skip_past_char (&str, chr) == FAIL) \
3840 goto bad_args; \
3841 } while (0)
3842
3843 #define po_reg_or_fail(regtype) do { \
3844 val = arm_reg_parse (&str, regtype); \
3845 if (val == FAIL) \
3846 { \
3847 inst.error = _(reg_expected_msgs[regtype]); \
3848 goto failure; \
3849 } \
3850 inst.operands[i].reg = val; \
3851 inst.operands[i].isreg = 1; \
3852 } while (0)
3853
3854 #define po_reg_or_goto(regtype, label) do { \
3855 val = arm_reg_parse (&str, regtype); \
3856 if (val == FAIL) \
3857 goto label; \
3858 \
3859 inst.operands[i].reg = val; \
3860 inst.operands[i].isreg = 1; \
3861 } while (0)
3862
3863 #define po_imm_or_fail(min, max, popt) do { \
3864 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
3865 goto failure; \
3866 inst.operands[i].imm = val; \
3867 } while (0)
3868
3869 #define po_misc_or_fail(expr) do { \
3870 if (expr) \
3871 goto failure; \
3872 } while (0)
3873
3874 skip_whitespace (str);
3875
3876 for (i = 0; upat[i] != OP_stop; i++)
3877 {
3878 if (upat[i] >= OP_FIRST_OPTIONAL)
3879 {
3880 /* Remember where we are in case we need to backtrack. */
3881 assert (!backtrack_pos);
3882 backtrack_pos = str;
3883 backtrack_error = inst.error;
3884 backtrack_index = i;
3885 }
3886
3887 if (i > 0)
3888 po_char_or_fail (',');
3889
3890 switch (upat[i])
3891 {
3892 /* Registers */
3893 case OP_oRRnpc:
3894 case OP_RRnpc:
3895 case OP_oRR:
3896 case OP_RR: po_reg_or_fail (REG_TYPE_RN); break;
3897 case OP_RCP: po_reg_or_fail (REG_TYPE_CP); break;
3898 case OP_RCN: po_reg_or_fail (REG_TYPE_CN); break;
3899 case OP_RF: po_reg_or_fail (REG_TYPE_FN); break;
3900 case OP_RVS: po_reg_or_fail (REG_TYPE_VFS); break;
3901 case OP_RVD: po_reg_or_fail (REG_TYPE_VFD); break;
3902 case OP_RVC: po_reg_or_fail (REG_TYPE_VFC); break;
3903 case OP_RMF: po_reg_or_fail (REG_TYPE_MVF); break;
3904 case OP_RMD: po_reg_or_fail (REG_TYPE_MVD); break;
3905 case OP_RMFX: po_reg_or_fail (REG_TYPE_MVFX); break;
3906 case OP_RMDX: po_reg_or_fail (REG_TYPE_MVDX); break;
3907 case OP_RMAX: po_reg_or_fail (REG_TYPE_MVAX); break;
3908 case OP_RMDS: po_reg_or_fail (REG_TYPE_DSPSC); break;
3909 case OP_RIWR: po_reg_or_fail (REG_TYPE_MMXWR); break;
3910 case OP_RIWC: po_reg_or_fail (REG_TYPE_MMXWC); break;
3911 case OP_RIWG: po_reg_or_fail (REG_TYPE_MMXWCG); break;
3912 case OP_RXA: po_reg_or_fail (REG_TYPE_XSCALE); break;
3913
3914 case OP_RRnpcb:
3915 po_char_or_fail ('[');
3916 po_reg_or_fail (REG_TYPE_RN);
3917 po_char_or_fail (']');
3918 break;
3919
3920 case OP_RRw:
3921 po_reg_or_fail (REG_TYPE_RN);
3922 if (skip_past_char (&str, '!') == SUCCESS)
3923 inst.operands[i].writeback = 1;
3924 break;
3925
3926 /* Immediates */
3927 case OP_I7: po_imm_or_fail ( 0, 7, FALSE); break;
3928 case OP_I15: po_imm_or_fail ( 0, 15, FALSE); break;
3929 case OP_I16: po_imm_or_fail ( 1, 16, FALSE); break;
3930 case OP_I31: po_imm_or_fail ( 0, 31, FALSE); break;
3931 case OP_I32: po_imm_or_fail ( 1, 32, FALSE); break;
3932 case OP_I63s: po_imm_or_fail (-64, 63, FALSE); break;
3933 case OP_I255: po_imm_or_fail ( 0, 255, FALSE); break;
3934 case OP_Iffff: po_imm_or_fail ( 0, 0xffff, FALSE); break;
3935
3936 case OP_I4b: po_imm_or_fail ( 1, 4, TRUE); break;
3937 case OP_oI7b:
3938 case OP_I7b: po_imm_or_fail ( 0, 7, TRUE); break;
3939 case OP_I15b: po_imm_or_fail ( 0, 15, TRUE); break;
3940 case OP_oI31b:
3941 case OP_I31b: po_imm_or_fail ( 0, 31, TRUE); break;
3942 case OP_oIffffb: po_imm_or_fail ( 0, 0xffff, TRUE); break;
3943
3944 /* Immediate variants */
3945 case OP_oI255c:
3946 po_char_or_fail ('{');
3947 po_imm_or_fail (0, 255, TRUE);
3948 po_char_or_fail ('}');
3949 break;
3950
3951 case OP_I31w:
3952 /* The expression parser chokes on a trailing !, so we have
3953 to find it first and zap it. */
3954 {
3955 char *s = str;
3956 while (*s && *s != ',')
3957 s++;
3958 if (s[-1] == '!')
3959 {
3960 s[-1] = '\0';
3961 inst.operands[i].writeback = 1;
3962 }
3963 po_imm_or_fail (0, 31, TRUE);
3964 if (str == s - 1)
3965 str = s;
3966 }
3967 break;
3968
3969 /* Expressions */
3970 case OP_EXPi: EXPi:
3971 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
3972 GE_OPT_PREFIX));
3973 break;
3974
3975 case OP_EXP:
3976 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
3977 GE_NO_PREFIX));
3978 break;
3979
3980 case OP_EXPr: EXPr:
3981 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
3982 GE_NO_PREFIX));
3983 if (inst.reloc.exp.X_op == O_symbol)
3984 {
3985 val = parse_reloc (&str);
3986 if (val == -1)
3987 {
3988 inst.error = _("unrecognized relocation suffix");
3989 goto failure;
3990 }
3991 else if (val != BFD_RELOC_UNUSED)
3992 {
3993 inst.operands[i].imm = val;
3994 inst.operands[i].hasreloc = 1;
3995 }
3996 }
3997 break;
3998
3999 /* Register or expression */
4000 case OP_RR_EXr: po_reg_or_goto (REG_TYPE_RN, EXPr); break;
4001 case OP_RR_EXi: po_reg_or_goto (REG_TYPE_RN, EXPi); break;
4002
4003 /* Register or immediate */
4004 case OP_RRnpc_I0: po_reg_or_goto (REG_TYPE_RN, I0); break;
4005 I0: po_imm_or_fail (0, 0, FALSE); break;
4006
4007 case OP_RF_IF: po_reg_or_goto (REG_TYPE_FN, IF); break;
4008 IF:
4009 if (!is_immediate_prefix (*str))
4010 goto bad_args;
4011 str++;
4012 val = parse_fpa_immediate (&str);
4013 if (val == FAIL)
4014 goto failure;
4015 /* FPA immediates are encoded as registers 8-15.
4016 parse_fpa_immediate has already applied the offset. */
4017 inst.operands[i].reg = val;
4018 inst.operands[i].isreg = 1;
4019 break;
4020
4021 /* Two kinds of register */
4022 case OP_RIWR_RIWC:
4023 {
4024 struct reg_entry *rege = arm_reg_parse_multi (&str);
4025 if (rege->type != REG_TYPE_MMXWR
4026 && rege->type != REG_TYPE_MMXWC
4027 && rege->type != REG_TYPE_MMXWCG)
4028 {
4029 inst.error = _("iWMMXt data or control register expected");
4030 goto failure;
4031 }
4032 inst.operands[i].reg = rege->number;
4033 inst.operands[i].isreg = (rege->type == REG_TYPE_MMXWR);
4034 }
4035 break;
4036
4037 /* Misc */
4038 case OP_CPSF: val = parse_cps_flags (&str); break;
4039 case OP_ENDI: val = parse_endian_specifier (&str); break;
4040 case OP_oROR: val = parse_ror (&str); break;
4041 case OP_PSR: val = parse_psr (&str); break;
4042 case OP_COND: val = parse_cond (&str); break;
4043 case OP_oBARRIER:val = parse_barrier (&str); break;
4044
4045 case OP_TB:
4046 po_misc_or_fail (parse_tb (&str));
4047 break;
4048
4049 /* Register lists */
4050 case OP_REGLST:
4051 val = parse_reg_list (&str);
4052 if (*str == '^')
4053 {
4054 inst.operands[1].writeback = 1;
4055 str++;
4056 }
4057 break;
4058
4059 case OP_VRSLST:
4060 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, 0);
4061 break;
4062
4063 case OP_VRDLST:
4064 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, 1);
4065 break;
4066
4067 /* Addressing modes */
4068 case OP_ADDR:
4069 po_misc_or_fail (parse_address (&str, i));
4070 break;
4071
4072 case OP_SH:
4073 po_misc_or_fail (parse_shifter_operand (&str, i));
4074 break;
4075
4076 case OP_oSHll:
4077 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_IMMEDIATE));
4078 break;
4079
4080 case OP_oSHar:
4081 po_misc_or_fail (parse_shift (&str, i, SHIFT_ASR_IMMEDIATE));
4082 break;
4083
4084 case OP_oSHllar:
4085 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_OR_ASR_IMMEDIATE));
4086 break;
4087
4088 default:
4089 as_fatal ("unhandled operand code %d", upat[i]);
4090 }
4091
4092 /* Various value-based sanity checks and shared operations. We
4093 do not signal immediate failures for the register constraints;
4094 this allows a syntax error to take precedence. */
4095 switch (upat[i])
4096 {
4097 case OP_oRRnpc:
4098 case OP_RRnpc:
4099 case OP_RRnpcb:
4100 case OP_RRw:
4101 case OP_RRnpc_I0:
4102 if (inst.operands[i].isreg && inst.operands[i].reg == REG_PC)
4103 inst.error = BAD_PC;
4104 break;
4105
4106 case OP_CPSF:
4107 case OP_ENDI:
4108 case OP_oROR:
4109 case OP_PSR:
4110 case OP_COND:
4111 case OP_oBARRIER:
4112 case OP_REGLST:
4113 case OP_VRSLST:
4114 case OP_VRDLST:
4115 if (val == FAIL)
4116 goto failure;
4117 inst.operands[i].imm = val;
4118 break;
4119
4120 default:
4121 break;
4122 }
4123
4124 /* If we get here, this operand was successfully parsed. */
4125 inst.operands[i].present = 1;
4126 continue;
4127
4128 bad_args:
4129 inst.error = BAD_ARGS;
4130
4131 failure:
4132 if (!backtrack_pos)
4133 return FAIL;
4134
4135 /* Do not backtrack over a trailing optional argument that
4136 absorbed some text. We will only fail again, with the
4137 'garbage following instruction' error message, which is
4138 probably less helpful than the current one. */
4139 if (backtrack_index == i && backtrack_pos != str
4140 && upat[i+1] == OP_stop)
4141 return FAIL;
4142
4143 /* Try again, skipping the optional argument at backtrack_pos. */
4144 str = backtrack_pos;
4145 inst.error = backtrack_error;
4146 inst.operands[backtrack_index].present = 0;
4147 i = backtrack_index;
4148 backtrack_pos = 0;
4149 }
4150
4151 /* Check that we have parsed all the arguments. */
4152 if (*str != '\0' && !inst.error)
4153 inst.error = _("garbage following instruction");
4154
4155 return inst.error ? FAIL : SUCCESS;
4156 }
4157
4158 #undef po_char_or_fail
4159 #undef po_reg_or_fail
4160 #undef po_reg_or_goto
4161 #undef po_imm_or_fail
4162 \f
4163 /* Shorthand macro for instruction encoding functions issuing errors. */
4164 #define constraint(expr, err) do { \
4165 if (expr) \
4166 { \
4167 inst.error = err; \
4168 return; \
4169 } \
4170 } while (0)
4171
4172 /* Functions for operand encoding. ARM, then Thumb. */
4173
4174 #define rotate_left(v, n) (v << n | v >> (32 - n))
4175
4176 /* If VAL can be encoded in the immediate field of an ARM instruction,
4177 return the encoded form. Otherwise, return FAIL. */
4178
4179 static unsigned int
4180 encode_arm_immediate (unsigned int val)
4181 {
4182 unsigned int a, i;
4183
4184 for (i = 0; i < 32; i += 2)
4185 if ((a = rotate_left (val, i)) <= 0xff)
4186 return a | (i << 7); /* 12-bit pack: [shift-cnt,const]. */
4187
4188 return FAIL;
4189 }
4190
4191 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
4192 return the encoded form. Otherwise, return FAIL. */
4193 static unsigned int
4194 encode_thumb32_immediate (unsigned int val)
4195 {
4196 unsigned int a, i;
4197
4198 if (val <= 0xff)
4199 return val;
4200
4201 for (i = 1; i <= 24; i++)
4202 {
4203 a = val >> i;
4204 if ((val & ~(0xff << i)) == 0)
4205 return ((val >> i) & 0x7f) | ((32 - i) << 7);
4206 }
4207
4208 a = val & 0xff;
4209 if (val == ((a << 16) | a))
4210 return 0x100 | a;
4211 if (val == ((a << 24) | (a << 16) | (a << 8) | a))
4212 return 0x300 | a;
4213
4214 a = val & 0xff00;
4215 if (val == ((a << 16) | a))
4216 return 0x200 | (a >> 8);
4217
4218 return FAIL;
4219 }
4220 /* Encode a VFP SP register number into inst.instruction. */
4221
4222 static void
4223 encode_arm_vfp_sp_reg (int reg, enum vfp_sp_reg_pos pos)
4224 {
4225 switch (pos)
4226 {
4227 case VFP_REG_Sd:
4228 inst.instruction |= ((reg >> 1) << 12) | ((reg & 1) << 22);
4229 break;
4230
4231 case VFP_REG_Sn:
4232 inst.instruction |= ((reg >> 1) << 16) | ((reg & 1) << 7);
4233 break;
4234
4235 case VFP_REG_Sm:
4236 inst.instruction |= ((reg >> 1) << 0) | ((reg & 1) << 5);
4237 break;
4238
4239 default:
4240 abort ();
4241 }
4242 }
4243
4244 /* Encode a <shift> in an ARM-format instruction. The immediate,
4245 if any, is handled by md_apply_fix. */
4246 static void
4247 encode_arm_shift (int i)
4248 {
4249 if (inst.operands[i].shift_kind == SHIFT_RRX)
4250 inst.instruction |= SHIFT_ROR << 5;
4251 else
4252 {
4253 inst.instruction |= inst.operands[i].shift_kind << 5;
4254 if (inst.operands[i].immisreg)
4255 {
4256 inst.instruction |= SHIFT_BY_REG;
4257 inst.instruction |= inst.operands[i].imm << 8;
4258 }
4259 else
4260 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
4261 }
4262 }
4263
4264 static void
4265 encode_arm_shifter_operand (int i)
4266 {
4267 if (inst.operands[i].isreg)
4268 {
4269 inst.instruction |= inst.operands[i].reg;
4270 encode_arm_shift (i);
4271 }
4272 else
4273 inst.instruction |= INST_IMMEDIATE;
4274 }
4275
4276 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
4277 static void
4278 encode_arm_addr_mode_common (int i, bfd_boolean is_t)
4279 {
4280 assert (inst.operands[i].isreg);
4281 inst.instruction |= inst.operands[i].reg << 16;
4282
4283 if (inst.operands[i].preind)
4284 {
4285 if (is_t)
4286 {
4287 inst.error = _("instruction does not accept preindexed addressing");
4288 return;
4289 }
4290 inst.instruction |= PRE_INDEX;
4291 if (inst.operands[i].writeback)
4292 inst.instruction |= WRITE_BACK;
4293
4294 }
4295 else if (inst.operands[i].postind)
4296 {
4297 assert (inst.operands[i].writeback);
4298 if (is_t)
4299 inst.instruction |= WRITE_BACK;
4300 }
4301 else /* unindexed - only for coprocessor */
4302 {
4303 inst.error = _("instruction does not accept unindexed addressing");
4304 return;
4305 }
4306
4307 if (((inst.instruction & WRITE_BACK) || !(inst.instruction & PRE_INDEX))
4308 && (((inst.instruction & 0x000f0000) >> 16)
4309 == ((inst.instruction & 0x0000f000) >> 12)))
4310 as_warn ((inst.instruction & LOAD_BIT)
4311 ? _("destination register same as write-back base")
4312 : _("source register same as write-back base"));
4313 }
4314
4315 /* inst.operands[i] was set up by parse_address. Encode it into an
4316 ARM-format mode 2 load or store instruction. If is_t is true,
4317 reject forms that cannot be used with a T instruction (i.e. not
4318 post-indexed). */
4319 static void
4320 encode_arm_addr_mode_2 (int i, bfd_boolean is_t)
4321 {
4322 encode_arm_addr_mode_common (i, is_t);
4323
4324 if (inst.operands[i].immisreg)
4325 {
4326 inst.instruction |= INST_IMMEDIATE; /* yes, this is backwards */
4327 inst.instruction |= inst.operands[i].imm;
4328 if (!inst.operands[i].negative)
4329 inst.instruction |= INDEX_UP;
4330 if (inst.operands[i].shifted)
4331 {
4332 if (inst.operands[i].shift_kind == SHIFT_RRX)
4333 inst.instruction |= SHIFT_ROR << 5;
4334 else
4335 {
4336 inst.instruction |= inst.operands[i].shift_kind << 5;
4337 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
4338 }
4339 }
4340 }
4341 else /* immediate offset in inst.reloc */
4342 {
4343 if (inst.reloc.type == BFD_RELOC_UNUSED)
4344 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM;
4345 }
4346 }
4347
4348 /* inst.operands[i] was set up by parse_address. Encode it into an
4349 ARM-format mode 3 load or store instruction. Reject forms that
4350 cannot be used with such instructions. If is_t is true, reject
4351 forms that cannot be used with a T instruction (i.e. not
4352 post-indexed). */
4353 static void
4354 encode_arm_addr_mode_3 (int i, bfd_boolean is_t)
4355 {
4356 if (inst.operands[i].immisreg && inst.operands[i].shifted)
4357 {
4358 inst.error = _("instruction does not accept scaled register index");
4359 return;
4360 }
4361
4362 encode_arm_addr_mode_common (i, is_t);
4363
4364 if (inst.operands[i].immisreg)
4365 {
4366 inst.instruction |= inst.operands[i].imm;
4367 if (!inst.operands[i].negative)
4368 inst.instruction |= INDEX_UP;
4369 }
4370 else /* immediate offset in inst.reloc */
4371 {
4372 inst.instruction |= HWOFFSET_IMM;
4373 if (inst.reloc.type == BFD_RELOC_UNUSED)
4374 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
4375 }
4376 }
4377
4378 /* inst.operands[i] was set up by parse_address. Encode it into an
4379 ARM-format instruction. Reject all forms which cannot be encoded
4380 into a coprocessor load/store instruction. If wb_ok is false,
4381 reject use of writeback; if unind_ok is false, reject use of
4382 unindexed addressing. If reloc_override is not 0, use it instead
4383 of BFD_ARM_CP_OFF_IMM. */
4384
4385 static int
4386 encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override)
4387 {
4388 inst.instruction |= inst.operands[i].reg << 16;
4389
4390 assert (!(inst.operands[i].preind && inst.operands[i].postind));
4391
4392 if (!inst.operands[i].preind && !inst.operands[i].postind) /* unindexed */
4393 {
4394 assert (!inst.operands[i].writeback);
4395 if (!unind_ok)
4396 {
4397 inst.error = _("instruction does not support unindexed addressing");
4398 return FAIL;
4399 }
4400 inst.instruction |= inst.operands[i].imm;
4401 inst.instruction |= INDEX_UP;
4402 return SUCCESS;
4403 }
4404
4405 if (inst.operands[i].preind)
4406 inst.instruction |= PRE_INDEX;
4407
4408 if (inst.operands[i].writeback)
4409 {
4410 if (inst.operands[i].reg == REG_PC)
4411 {
4412 inst.error = _("pc may not be used with write-back");
4413 return FAIL;
4414 }
4415 if (!wb_ok)
4416 {
4417 inst.error = _("instruction does not support writeback");
4418 return FAIL;
4419 }
4420 inst.instruction |= WRITE_BACK;
4421 }
4422
4423 if (reloc_override)
4424 inst.reloc.type = reloc_override;
4425 else if (thumb_mode)
4426 inst.reloc.type = BFD_RELOC_ARM_T32_CP_OFF_IMM;
4427 else
4428 inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM;
4429 return SUCCESS;
4430 }
4431
4432 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
4433 Determine whether it can be performed with a move instruction; if
4434 it can, convert inst.instruction to that move instruction and
4435 return 1; if it can't, convert inst.instruction to a literal-pool
4436 load and return 0. If this is not a valid thing to do in the
4437 current context, set inst.error and return 1.
4438
4439 inst.operands[i] describes the destination register. */
4440
4441 static int
4442 move_or_literal_pool (int i, bfd_boolean thumb_p, bfd_boolean mode_3)
4443 {
4444 if ((inst.instruction & (thumb_p ? THUMB_LOAD_BIT : LOAD_BIT)) == 0)
4445 {
4446 inst.error = _("invalid pseudo operation");
4447 return 1;
4448 }
4449 if (inst.reloc.exp.X_op != O_constant && inst.reloc.exp.X_op != O_symbol)
4450 {
4451 inst.error = _("constant expression expected");
4452 return 1;
4453 }
4454 if (inst.reloc.exp.X_op == O_constant)
4455 {
4456 if (thumb_p)
4457 {
4458 if ((inst.reloc.exp.X_add_number & ~0xFF) == 0)
4459 {
4460 /* This can be done with a mov(1) instruction. */
4461 inst.instruction = T_OPCODE_MOV_I8 | (inst.operands[i].reg << 8);
4462 inst.instruction |= inst.reloc.exp.X_add_number;
4463 return 1;
4464 }
4465 }
4466 else
4467 {
4468 int value = encode_arm_immediate (inst.reloc.exp.X_add_number);
4469 if (value != FAIL)
4470 {
4471 /* This can be done with a mov instruction. */
4472 inst.instruction &= LITERAL_MASK;
4473 inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT);
4474 inst.instruction |= value & 0xfff;
4475 return 1;
4476 }
4477
4478 value = encode_arm_immediate (~inst.reloc.exp.X_add_number);
4479 if (value != FAIL)
4480 {
4481 /* This can be done with a mvn instruction. */
4482 inst.instruction &= LITERAL_MASK;
4483 inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT);
4484 inst.instruction |= value & 0xfff;
4485 return 1;
4486 }
4487 }
4488 }
4489
4490 if (add_to_lit_pool () == FAIL)
4491 {
4492 inst.error = _("literal pool insertion failed");
4493 return 1;
4494 }
4495 inst.operands[1].reg = REG_PC;
4496 inst.operands[1].isreg = 1;
4497 inst.operands[1].preind = 1;
4498 inst.reloc.pc_rel = 1;
4499 inst.reloc.type = (thumb_p
4500 ? BFD_RELOC_ARM_THUMB_OFFSET
4501 : (mode_3
4502 ? BFD_RELOC_ARM_HWLITERAL
4503 : BFD_RELOC_ARM_LITERAL));
4504 return 0;
4505 }
4506
4507 /* Functions for instruction encoding, sorted by subarchitecture.
4508 First some generics; their names are taken from the conventional
4509 bit positions for register arguments in ARM format instructions. */
4510
4511 static void
4512 do_noargs (void)
4513 {
4514 }
4515
4516 static void
4517 do_rd (void)
4518 {
4519 inst.instruction |= inst.operands[0].reg << 12;
4520 }
4521
4522 static void
4523 do_rd_rm (void)
4524 {
4525 inst.instruction |= inst.operands[0].reg << 12;
4526 inst.instruction |= inst.operands[1].reg;
4527 }
4528
4529 static void
4530 do_rd_rn (void)
4531 {
4532 inst.instruction |= inst.operands[0].reg << 12;
4533 inst.instruction |= inst.operands[1].reg << 16;
4534 }
4535
4536 static void
4537 do_rn_rd (void)
4538 {
4539 inst.instruction |= inst.operands[0].reg << 16;
4540 inst.instruction |= inst.operands[1].reg << 12;
4541 }
4542
4543 static void
4544 do_rd_rm_rn (void)
4545 {
4546 unsigned Rn = inst.operands[2].reg;
4547 /* Enforce resutrictions on SWP instruction. */
4548 if ((inst.instruction & 0x0fbfffff) == 0x01000090)
4549 constraint (Rn == inst.operands[0].reg || Rn == inst.operands[1].reg,
4550 _("Rn must not overlap other operands"));
4551 inst.instruction |= inst.operands[0].reg << 12;
4552 inst.instruction |= inst.operands[1].reg;
4553 inst.instruction |= Rn << 16;
4554 }
4555
4556 static void
4557 do_rd_rn_rm (void)
4558 {
4559 inst.instruction |= inst.operands[0].reg << 12;
4560 inst.instruction |= inst.operands[1].reg << 16;
4561 inst.instruction |= inst.operands[2].reg;
4562 }
4563
4564 static void
4565 do_rm_rd_rn (void)
4566 {
4567 inst.instruction |= inst.operands[0].reg;
4568 inst.instruction |= inst.operands[1].reg << 12;
4569 inst.instruction |= inst.operands[2].reg << 16;
4570 }
4571
4572 static void
4573 do_imm0 (void)
4574 {
4575 inst.instruction |= inst.operands[0].imm;
4576 }
4577
4578 static void
4579 do_rd_cpaddr (void)
4580 {
4581 inst.instruction |= inst.operands[0].reg << 12;
4582 encode_arm_cp_address (1, TRUE, TRUE, 0);
4583 }
4584
4585 /* ARM instructions, in alphabetical order by function name (except
4586 that wrapper functions appear immediately after the function they
4587 wrap). */
4588
4589 /* This is a pseudo-op of the form "adr rd, label" to be converted
4590 into a relative address of the form "add rd, pc, #label-.-8". */
4591
4592 static void
4593 do_adr (void)
4594 {
4595 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
4596
4597 /* Frag hacking will turn this into a sub instruction if the offset turns
4598 out to be negative. */
4599 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
4600 inst.reloc.pc_rel = 1;
4601 inst.reloc.exp.X_add_number -= 8;
4602 }
4603
4604 /* This is a pseudo-op of the form "adrl rd, label" to be converted
4605 into a relative address of the form:
4606 add rd, pc, #low(label-.-8)"
4607 add rd, rd, #high(label-.-8)" */
4608
4609 static void
4610 do_adrl (void)
4611 {
4612 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
4613
4614 /* Frag hacking will turn this into a sub instruction if the offset turns
4615 out to be negative. */
4616 inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE;
4617 inst.reloc.pc_rel = 1;
4618 inst.size = INSN_SIZE * 2;
4619 inst.reloc.exp.X_add_number -= 8;
4620 }
4621
4622 static void
4623 do_arit (void)
4624 {
4625 if (!inst.operands[1].present)
4626 inst.operands[1].reg = inst.operands[0].reg;
4627 inst.instruction |= inst.operands[0].reg << 12;
4628 inst.instruction |= inst.operands[1].reg << 16;
4629 encode_arm_shifter_operand (2);
4630 }
4631
4632 static void
4633 do_barrier (void)
4634 {
4635 if (inst.operands[0].present)
4636 {
4637 constraint ((inst.instruction & 0xf0) != 0x40
4638 && inst.operands[0].imm != 0xf,
4639 "bad barrier type");
4640 inst.instruction |= inst.operands[0].imm;
4641 }
4642 else
4643 inst.instruction |= 0xf;
4644 }
4645
4646 static void
4647 do_bfc (void)
4648 {
4649 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
4650 constraint (msb > 32, _("bit-field extends past end of register"));
4651 /* The instruction encoding stores the LSB and MSB,
4652 not the LSB and width. */
4653 inst.instruction |= inst.operands[0].reg << 12;
4654 inst.instruction |= inst.operands[1].imm << 7;
4655 inst.instruction |= (msb - 1) << 16;
4656 }
4657
4658 static void
4659 do_bfi (void)
4660 {
4661 unsigned int msb;
4662
4663 /* #0 in second position is alternative syntax for bfc, which is
4664 the same instruction but with REG_PC in the Rm field. */
4665 if (!inst.operands[1].isreg)
4666 inst.operands[1].reg = REG_PC;
4667
4668 msb = inst.operands[2].imm + inst.operands[3].imm;
4669 constraint (msb > 32, _("bit-field extends past end of register"));
4670 /* The instruction encoding stores the LSB and MSB,
4671 not the LSB and width. */
4672 inst.instruction |= inst.operands[0].reg << 12;
4673 inst.instruction |= inst.operands[1].reg;
4674 inst.instruction |= inst.operands[2].imm << 7;
4675 inst.instruction |= (msb - 1) << 16;
4676 }
4677
4678 static void
4679 do_bfx (void)
4680 {
4681 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
4682 _("bit-field extends past end of register"));
4683 inst.instruction |= inst.operands[0].reg << 12;
4684 inst.instruction |= inst.operands[1].reg;
4685 inst.instruction |= inst.operands[2].imm << 7;
4686 inst.instruction |= (inst.operands[3].imm - 1) << 16;
4687 }
4688
4689 /* ARM V5 breakpoint instruction (argument parse)
4690 BKPT <16 bit unsigned immediate>
4691 Instruction is not conditional.
4692 The bit pattern given in insns[] has the COND_ALWAYS condition,
4693 and it is an error if the caller tried to override that. */
4694
4695 static void
4696 do_bkpt (void)
4697 {
4698 /* Top 12 of 16 bits to bits 19:8. */
4699 inst.instruction |= (inst.operands[0].imm & 0xfff0) << 4;
4700
4701 /* Bottom 4 of 16 bits to bits 3:0. */
4702 inst.instruction |= inst.operands[0].imm & 0xf;
4703 }
4704
4705 static void
4706 encode_branch (int default_reloc)
4707 {
4708 if (inst.operands[0].hasreloc)
4709 {
4710 constraint (inst.operands[0].imm != BFD_RELOC_ARM_PLT32,
4711 _("the only suffix valid here is '(plt)'"));
4712 inst.reloc.type = BFD_RELOC_ARM_PLT32;
4713 }
4714 else
4715 {
4716 inst.reloc.type = default_reloc;
4717 }
4718 inst.reloc.pc_rel = 1;
4719 }
4720
4721 static void
4722 do_branch (void)
4723 {
4724 #ifdef OBJ_ELF
4725 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
4726 encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
4727 else
4728 #endif
4729 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
4730 }
4731
4732 static void
4733 do_bl (void)
4734 {
4735 #ifdef OBJ_ELF
4736 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
4737 {
4738 if (inst.cond == COND_ALWAYS)
4739 encode_branch (BFD_RELOC_ARM_PCREL_CALL);
4740 else
4741 encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
4742 }
4743 else
4744 #endif
4745 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
4746 }
4747
4748 /* ARM V5 branch-link-exchange instruction (argument parse)
4749 BLX <target_addr> ie BLX(1)
4750 BLX{<condition>} <Rm> ie BLX(2)
4751 Unfortunately, there are two different opcodes for this mnemonic.
4752 So, the insns[].value is not used, and the code here zaps values
4753 into inst.instruction.
4754 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
4755
4756 static void
4757 do_blx (void)
4758 {
4759 if (inst.operands[0].isreg)
4760 {
4761 /* Arg is a register; the opcode provided by insns[] is correct.
4762 It is not illegal to do "blx pc", just useless. */
4763 if (inst.operands[0].reg == REG_PC)
4764 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
4765
4766 inst.instruction |= inst.operands[0].reg;
4767 }
4768 else
4769 {
4770 /* Arg is an address; this instruction cannot be executed
4771 conditionally, and the opcode must be adjusted. */
4772 constraint (inst.cond != COND_ALWAYS, BAD_COND);
4773 inst.instruction = 0xfa000000;
4774 #ifdef OBJ_ELF
4775 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
4776 encode_branch (BFD_RELOC_ARM_PCREL_CALL);
4777 else
4778 #endif
4779 encode_branch (BFD_RELOC_ARM_PCREL_BLX);
4780 }
4781 }
4782
4783 static void
4784 do_bx (void)
4785 {
4786 if (inst.operands[0].reg == REG_PC)
4787 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
4788
4789 inst.instruction |= inst.operands[0].reg;
4790 }
4791
4792
4793 /* ARM v5TEJ. Jump to Jazelle code. */
4794
4795 static void
4796 do_bxj (void)
4797 {
4798 if (inst.operands[0].reg == REG_PC)
4799 as_tsktsk (_("use of r15 in bxj is not really useful"));
4800
4801 inst.instruction |= inst.operands[0].reg;
4802 }
4803
4804 /* Co-processor data operation:
4805 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
4806 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
4807 static void
4808 do_cdp (void)
4809 {
4810 inst.instruction |= inst.operands[0].reg << 8;
4811 inst.instruction |= inst.operands[1].imm << 20;
4812 inst.instruction |= inst.operands[2].reg << 12;
4813 inst.instruction |= inst.operands[3].reg << 16;
4814 inst.instruction |= inst.operands[4].reg;
4815 inst.instruction |= inst.operands[5].imm << 5;
4816 }
4817
4818 static void
4819 do_cmp (void)
4820 {
4821 inst.instruction |= inst.operands[0].reg << 16;
4822 encode_arm_shifter_operand (1);
4823 }
4824
4825 /* Transfer between coprocessor and ARM registers.
4826 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
4827 MRC2
4828 MCR{cond}
4829 MCR2
4830
4831 No special properties. */
4832
4833 static void
4834 do_co_reg (void)
4835 {
4836 inst.instruction |= inst.operands[0].reg << 8;
4837 inst.instruction |= inst.operands[1].imm << 21;
4838 inst.instruction |= inst.operands[2].reg << 12;
4839 inst.instruction |= inst.operands[3].reg << 16;
4840 inst.instruction |= inst.operands[4].reg;
4841 inst.instruction |= inst.operands[5].imm << 5;
4842 }
4843
4844 /* Transfer between coprocessor register and pair of ARM registers.
4845 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
4846 MCRR2
4847 MRRC{cond}
4848 MRRC2
4849
4850 Two XScale instructions are special cases of these:
4851
4852 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
4853 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
4854
4855 Result unpredicatable if Rd or Rn is R15. */
4856
4857 static void
4858 do_co_reg2c (void)
4859 {
4860 inst.instruction |= inst.operands[0].reg << 8;
4861 inst.instruction |= inst.operands[1].imm << 4;
4862 inst.instruction |= inst.operands[2].reg << 12;
4863 inst.instruction |= inst.operands[3].reg << 16;
4864 inst.instruction |= inst.operands[4].reg;
4865 }
4866
4867 static void
4868 do_cpsi (void)
4869 {
4870 inst.instruction |= inst.operands[0].imm << 6;
4871 inst.instruction |= inst.operands[1].imm;
4872 }
4873
4874 static void
4875 do_dbg (void)
4876 {
4877 inst.instruction |= inst.operands[0].imm;
4878 }
4879
4880 static void
4881 do_it (void)
4882 {
4883 /* There is no IT instruction in ARM mode. We
4884 process it but do not generate code for it. */
4885 inst.size = 0;
4886 }
4887
4888 static void
4889 do_ldmstm (void)
4890 {
4891 int base_reg = inst.operands[0].reg;
4892 int range = inst.operands[1].imm;
4893
4894 inst.instruction |= base_reg << 16;
4895 inst.instruction |= range;
4896
4897 if (inst.operands[1].writeback)
4898 inst.instruction |= LDM_TYPE_2_OR_3;
4899
4900 if (inst.operands[0].writeback)
4901 {
4902 inst.instruction |= WRITE_BACK;
4903 /* Check for unpredictable uses of writeback. */
4904 if (inst.instruction & LOAD_BIT)
4905 {
4906 /* Not allowed in LDM type 2. */
4907 if ((inst.instruction & LDM_TYPE_2_OR_3)
4908 && ((range & (1 << REG_PC)) == 0))
4909 as_warn (_("writeback of base register is UNPREDICTABLE"));
4910 /* Only allowed if base reg not in list for other types. */
4911 else if (range & (1 << base_reg))
4912 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
4913 }
4914 else /* STM. */
4915 {
4916 /* Not allowed for type 2. */
4917 if (inst.instruction & LDM_TYPE_2_OR_3)
4918 as_warn (_("writeback of base register is UNPREDICTABLE"));
4919 /* Only allowed if base reg not in list, or first in list. */
4920 else if ((range & (1 << base_reg))
4921 && (range & ((1 << base_reg) - 1)))
4922 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
4923 }
4924 }
4925 }
4926
4927 /* ARMv5TE load-consecutive (argument parse)
4928 Mode is like LDRH.
4929
4930 LDRccD R, mode
4931 STRccD R, mode. */
4932
4933 static void
4934 do_ldrd (void)
4935 {
4936 constraint (inst.operands[0].reg % 2 != 0,
4937 _("first destination register must be even"));
4938 constraint (inst.operands[1].present
4939 && inst.operands[1].reg != inst.operands[0].reg + 1,
4940 _("can only load two consecutive registers"));
4941 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
4942 constraint (!inst.operands[2].isreg, _("'[' expected"));
4943
4944 if (!inst.operands[1].present)
4945 inst.operands[1].reg = inst.operands[0].reg + 1;
4946
4947 if (inst.instruction & LOAD_BIT)
4948 {
4949 /* encode_arm_addr_mode_3 will diagnose overlap between the base
4950 register and the first register written; we have to diagnose
4951 overlap between the base and the second register written here. */
4952
4953 if (inst.operands[2].reg == inst.operands[1].reg
4954 && (inst.operands[2].writeback || inst.operands[2].postind))
4955 as_warn (_("base register written back, and overlaps "
4956 "second destination register"));
4957
4958 /* For an index-register load, the index register must not overlap the
4959 destination (even if not write-back). */
4960 else if (inst.operands[2].immisreg
4961 && ((unsigned) inst.operands[2].imm == inst.operands[0].reg
4962 || (unsigned) inst.operands[2].imm == inst.operands[1].reg))
4963 as_warn (_("index register overlaps destination register"));
4964 }
4965
4966 inst.instruction |= inst.operands[0].reg << 12;
4967 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE);
4968 }
4969
4970 static void
4971 do_ldrex (void)
4972 {
4973 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
4974 || inst.operands[1].postind || inst.operands[1].writeback
4975 || inst.operands[1].immisreg || inst.operands[1].shifted
4976 || inst.operands[1].negative
4977 /* This can arise if the programmer has written
4978 strex rN, rM, foo
4979 or if they have mistakenly used a register name as the last
4980 operand, eg:
4981 strex rN, rM, rX
4982 It is very difficult to distinguish between these two cases
4983 because "rX" might actually be a label. ie the register
4984 name has been occluded by a symbol of the same name. So we
4985 just generate a general 'bad addressing mode' type error
4986 message and leave it up to the programmer to discover the
4987 true cause and fix their mistake. */
4988 || (inst.operands[1].reg == REG_PC),
4989 BAD_ADDR_MODE);
4990
4991 constraint (inst.reloc.exp.X_op != O_constant
4992 || inst.reloc.exp.X_add_number != 0,
4993 _("offset must be zero in ARM encoding"));
4994
4995 inst.instruction |= inst.operands[0].reg << 12;
4996 inst.instruction |= inst.operands[1].reg << 16;
4997 inst.reloc.type = BFD_RELOC_UNUSED;
4998 }
4999
5000 static void
5001 do_ldrexd (void)
5002 {
5003 constraint (inst.operands[0].reg % 2 != 0,
5004 _("even register required"));
5005 constraint (inst.operands[1].present
5006 && inst.operands[1].reg != inst.operands[0].reg + 1,
5007 _("can only load two consecutive registers"));
5008 /* If op 1 were present and equal to PC, this function wouldn't
5009 have been called in the first place. */
5010 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
5011
5012 inst.instruction |= inst.operands[0].reg << 12;
5013 inst.instruction |= inst.operands[2].reg << 16;
5014 }
5015
5016 static void
5017 do_ldst (void)
5018 {
5019 inst.instruction |= inst.operands[0].reg << 12;
5020 if (!inst.operands[1].isreg)
5021 if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/FALSE))
5022 return;
5023 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE);
5024 }
5025
5026 static void
5027 do_ldstt (void)
5028 {
5029 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
5030 reject [Rn,...]. */
5031 if (inst.operands[1].preind)
5032 {
5033 constraint (inst.reloc.exp.X_op != O_constant ||
5034 inst.reloc.exp.X_add_number != 0,
5035 _("this instruction requires a post-indexed address"));
5036
5037 inst.operands[1].preind = 0;
5038 inst.operands[1].postind = 1;
5039 inst.operands[1].writeback = 1;
5040 }
5041 inst.instruction |= inst.operands[0].reg << 12;
5042 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE);
5043 }
5044
5045 /* Halfword and signed-byte load/store operations. */
5046
5047 static void
5048 do_ldstv4 (void)
5049 {
5050 inst.instruction |= inst.operands[0].reg << 12;
5051 if (!inst.operands[1].isreg)
5052 if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/TRUE))
5053 return;
5054 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE);
5055 }
5056
5057 static void
5058 do_ldsttv4 (void)
5059 {
5060 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
5061 reject [Rn,...]. */
5062 if (inst.operands[1].preind)
5063 {
5064 constraint (inst.reloc.exp.X_op != O_constant ||
5065 inst.reloc.exp.X_add_number != 0,
5066 _("this instruction requires a post-indexed address"));
5067
5068 inst.operands[1].preind = 0;
5069 inst.operands[1].postind = 1;
5070 inst.operands[1].writeback = 1;
5071 }
5072 inst.instruction |= inst.operands[0].reg << 12;
5073 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE);
5074 }
5075
5076 /* Co-processor register load/store.
5077 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
5078 static void
5079 do_lstc (void)
5080 {
5081 inst.instruction |= inst.operands[0].reg << 8;
5082 inst.instruction |= inst.operands[1].reg << 12;
5083 encode_arm_cp_address (2, TRUE, TRUE, 0);
5084 }
5085
5086 static void
5087 do_mlas (void)
5088 {
5089 /* This restriction does not apply to mls (nor to mla in v6, but
5090 that's hard to detect at present). */
5091 if (inst.operands[0].reg == inst.operands[1].reg
5092 && !(inst.instruction & 0x00400000))
5093 as_tsktsk (_("rd and rm should be different in mla"));
5094
5095 inst.instruction |= inst.operands[0].reg << 16;
5096 inst.instruction |= inst.operands[1].reg;
5097 inst.instruction |= inst.operands[2].reg << 8;
5098 inst.instruction |= inst.operands[3].reg << 12;
5099
5100 }
5101
5102 static void
5103 do_mov (void)
5104 {
5105 inst.instruction |= inst.operands[0].reg << 12;
5106 encode_arm_shifter_operand (1);
5107 }
5108
5109 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
5110 static void
5111 do_mov16 (void)
5112 {
5113 inst.instruction |= inst.operands[0].reg << 12;
5114 /* The value is in two pieces: 0:11, 16:19. */
5115 inst.instruction |= (inst.operands[1].imm & 0x00000fff);
5116 inst.instruction |= (inst.operands[1].imm & 0x0000f000) << 4;
5117 }
5118
5119 static void
5120 do_mrs (void)
5121 {
5122 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
5123 constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f))
5124 != (PSR_c|PSR_f),
5125 _("'CPSR' or 'SPSR' expected"));
5126 inst.instruction |= inst.operands[0].reg << 12;
5127 inst.instruction |= (inst.operands[1].imm & SPSR_BIT);
5128 }
5129
5130 /* Two possible forms:
5131 "{C|S}PSR_<field>, Rm",
5132 "{C|S}PSR_f, #expression". */
5133
5134 static void
5135 do_msr (void)
5136 {
5137 inst.instruction |= inst.operands[0].imm;
5138 if (inst.operands[1].isreg)
5139 inst.instruction |= inst.operands[1].reg;
5140 else
5141 {
5142 inst.instruction |= INST_IMMEDIATE;
5143 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
5144 inst.reloc.pc_rel = 0;
5145 }
5146 }
5147
5148 static void
5149 do_mul (void)
5150 {
5151 if (!inst.operands[2].present)
5152 inst.operands[2].reg = inst.operands[0].reg;
5153 inst.instruction |= inst.operands[0].reg << 16;
5154 inst.instruction |= inst.operands[1].reg;
5155 inst.instruction |= inst.operands[2].reg << 8;
5156
5157 if (inst.operands[0].reg == inst.operands[1].reg)
5158 as_tsktsk (_("rd and rm should be different in mul"));
5159 }
5160
5161 /* Long Multiply Parser
5162 UMULL RdLo, RdHi, Rm, Rs
5163 SMULL RdLo, RdHi, Rm, Rs
5164 UMLAL RdLo, RdHi, Rm, Rs
5165 SMLAL RdLo, RdHi, Rm, Rs. */
5166
5167 static void
5168 do_mull (void)
5169 {
5170 inst.instruction |= inst.operands[0].reg << 12;
5171 inst.instruction |= inst.operands[1].reg << 16;
5172 inst.instruction |= inst.operands[2].reg;
5173 inst.instruction |= inst.operands[3].reg << 8;
5174
5175 /* rdhi, rdlo and rm must all be different. */
5176 if (inst.operands[0].reg == inst.operands[1].reg
5177 || inst.operands[0].reg == inst.operands[2].reg
5178 || inst.operands[1].reg == inst.operands[2].reg)
5179 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
5180 }
5181
5182 static void
5183 do_nop (void)
5184 {
5185 if (inst.operands[0].present)
5186 {
5187 /* Architectural NOP hints are CPSR sets with no bits selected. */
5188 inst.instruction &= 0xf0000000;
5189 inst.instruction |= 0x0320f000 + inst.operands[0].imm;
5190 }
5191 }
5192
5193 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
5194 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
5195 Condition defaults to COND_ALWAYS.
5196 Error if Rd, Rn or Rm are R15. */
5197
5198 static void
5199 do_pkhbt (void)
5200 {
5201 inst.instruction |= inst.operands[0].reg << 12;
5202 inst.instruction |= inst.operands[1].reg << 16;
5203 inst.instruction |= inst.operands[2].reg;
5204 if (inst.operands[3].present)
5205 encode_arm_shift (3);
5206 }
5207
5208 /* ARM V6 PKHTB (Argument Parse). */
5209
5210 static void
5211 do_pkhtb (void)
5212 {
5213 if (!inst.operands[3].present)
5214 {
5215 /* If the shift specifier is omitted, turn the instruction
5216 into pkhbt rd, rm, rn. */
5217 inst.instruction &= 0xfff00010;
5218 inst.instruction |= inst.operands[0].reg << 12;
5219 inst.instruction |= inst.operands[1].reg;
5220 inst.instruction |= inst.operands[2].reg << 16;
5221 }
5222 else
5223 {
5224 inst.instruction |= inst.operands[0].reg << 12;
5225 inst.instruction |= inst.operands[1].reg << 16;
5226 inst.instruction |= inst.operands[2].reg;
5227 encode_arm_shift (3);
5228 }
5229 }
5230
5231 /* ARMv5TE: Preload-Cache
5232
5233 PLD <addr_mode>
5234
5235 Syntactically, like LDR with B=1, W=0, L=1. */
5236
5237 static void
5238 do_pld (void)
5239 {
5240 constraint (!inst.operands[0].isreg,
5241 _("'[' expected after PLD mnemonic"));
5242 constraint (inst.operands[0].postind,
5243 _("post-indexed expression used in preload instruction"));
5244 constraint (inst.operands[0].writeback,
5245 _("writeback used in preload instruction"));
5246 constraint (!inst.operands[0].preind,
5247 _("unindexed addressing used in preload instruction"));
5248 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
5249 }
5250
5251 /* ARMv7: PLI <addr_mode> */
5252 static void
5253 do_pli (void)
5254 {
5255 constraint (!inst.operands[0].isreg,
5256 _("'[' expected after PLI mnemonic"));
5257 constraint (inst.operands[0].postind,
5258 _("post-indexed expression used in preload instruction"));
5259 constraint (inst.operands[0].writeback,
5260 _("writeback used in preload instruction"));
5261 constraint (!inst.operands[0].preind,
5262 _("unindexed addressing used in preload instruction"));
5263 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
5264 inst.instruction &= ~PRE_INDEX;
5265 }
5266
5267 static void
5268 do_push_pop (void)
5269 {
5270 inst.operands[1] = inst.operands[0];
5271 memset (&inst.operands[0], 0, sizeof inst.operands[0]);
5272 inst.operands[0].isreg = 1;
5273 inst.operands[0].writeback = 1;
5274 inst.operands[0].reg = REG_SP;
5275 do_ldmstm ();
5276 }
5277
5278 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
5279 word at the specified address and the following word
5280 respectively.
5281 Unconditionally executed.
5282 Error if Rn is R15. */
5283
5284 static void
5285 do_rfe (void)
5286 {
5287 inst.instruction |= inst.operands[0].reg << 16;
5288 if (inst.operands[0].writeback)
5289 inst.instruction |= WRITE_BACK;
5290 }
5291
5292 /* ARM V6 ssat (argument parse). */
5293
5294 static void
5295 do_ssat (void)
5296 {
5297 inst.instruction |= inst.operands[0].reg << 12;
5298 inst.instruction |= (inst.operands[1].imm - 1) << 16;
5299 inst.instruction |= inst.operands[2].reg;
5300
5301 if (inst.operands[3].present)
5302 encode_arm_shift (3);
5303 }
5304
5305 /* ARM V6 usat (argument parse). */
5306
5307 static void
5308 do_usat (void)
5309 {
5310 inst.instruction |= inst.operands[0].reg << 12;
5311 inst.instruction |= inst.operands[1].imm << 16;
5312 inst.instruction |= inst.operands[2].reg;
5313
5314 if (inst.operands[3].present)
5315 encode_arm_shift (3);
5316 }
5317
5318 /* ARM V6 ssat16 (argument parse). */
5319
5320 static void
5321 do_ssat16 (void)
5322 {
5323 inst.instruction |= inst.operands[0].reg << 12;
5324 inst.instruction |= ((inst.operands[1].imm - 1) << 16);
5325 inst.instruction |= inst.operands[2].reg;
5326 }
5327
5328 static void
5329 do_usat16 (void)
5330 {
5331 inst.instruction |= inst.operands[0].reg << 12;
5332 inst.instruction |= inst.operands[1].imm << 16;
5333 inst.instruction |= inst.operands[2].reg;
5334 }
5335
5336 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
5337 preserving the other bits.
5338
5339 setend <endian_specifier>, where <endian_specifier> is either
5340 BE or LE. */
5341
5342 static void
5343 do_setend (void)
5344 {
5345 if (inst.operands[0].imm)
5346 inst.instruction |= 0x200;
5347 }
5348
5349 static void
5350 do_shift (void)
5351 {
5352 unsigned int Rm = (inst.operands[1].present
5353 ? inst.operands[1].reg
5354 : inst.operands[0].reg);
5355
5356 inst.instruction |= inst.operands[0].reg << 12;
5357 inst.instruction |= Rm;
5358 if (inst.operands[2].isreg) /* Rd, {Rm,} Rs */
5359 {
5360 inst.instruction |= inst.operands[2].reg << 8;
5361 inst.instruction |= SHIFT_BY_REG;
5362 }
5363 else
5364 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
5365 }
5366
5367 static void
5368 do_smc (void)
5369 {
5370 inst.reloc.type = BFD_RELOC_ARM_SMC;
5371 inst.reloc.pc_rel = 0;
5372 }
5373
5374 static void
5375 do_swi (void)
5376 {
5377 inst.reloc.type = BFD_RELOC_ARM_SWI;
5378 inst.reloc.pc_rel = 0;
5379 }
5380
5381 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
5382 SMLAxy{cond} Rd,Rm,Rs,Rn
5383 SMLAWy{cond} Rd,Rm,Rs,Rn
5384 Error if any register is R15. */
5385
5386 static void
5387 do_smla (void)
5388 {
5389 inst.instruction |= inst.operands[0].reg << 16;
5390 inst.instruction |= inst.operands[1].reg;
5391 inst.instruction |= inst.operands[2].reg << 8;
5392 inst.instruction |= inst.operands[3].reg << 12;
5393 }
5394
5395 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
5396 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
5397 Error if any register is R15.
5398 Warning if Rdlo == Rdhi. */
5399
5400 static void
5401 do_smlal (void)
5402 {
5403 inst.instruction |= inst.operands[0].reg << 12;
5404 inst.instruction |= inst.operands[1].reg << 16;
5405 inst.instruction |= inst.operands[2].reg;
5406 inst.instruction |= inst.operands[3].reg << 8;
5407
5408 if (inst.operands[0].reg == inst.operands[1].reg)
5409 as_tsktsk (_("rdhi and rdlo must be different"));
5410 }
5411
5412 /* ARM V5E (El Segundo) signed-multiply (argument parse)
5413 SMULxy{cond} Rd,Rm,Rs
5414 Error if any register is R15. */
5415
5416 static void
5417 do_smul (void)
5418 {
5419 inst.instruction |= inst.operands[0].reg << 16;
5420 inst.instruction |= inst.operands[1].reg;
5421 inst.instruction |= inst.operands[2].reg << 8;
5422 }
5423
5424 /* ARM V6 srs (argument parse). */
5425
5426 static void
5427 do_srs (void)
5428 {
5429 inst.instruction |= inst.operands[0].imm;
5430 if (inst.operands[0].writeback)
5431 inst.instruction |= WRITE_BACK;
5432 }
5433
5434 /* ARM V6 strex (argument parse). */
5435
5436 static void
5437 do_strex (void)
5438 {
5439 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
5440 || inst.operands[2].postind || inst.operands[2].writeback
5441 || inst.operands[2].immisreg || inst.operands[2].shifted
5442 || inst.operands[2].negative
5443 /* See comment in do_ldrex(). */
5444 || (inst.operands[2].reg == REG_PC),
5445 BAD_ADDR_MODE);
5446
5447 constraint (inst.operands[0].reg == inst.operands[1].reg
5448 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
5449
5450 constraint (inst.reloc.exp.X_op != O_constant
5451 || inst.reloc.exp.X_add_number != 0,
5452 _("offset must be zero in ARM encoding"));
5453
5454 inst.instruction |= inst.operands[0].reg << 12;
5455 inst.instruction |= inst.operands[1].reg;
5456 inst.instruction |= inst.operands[2].reg << 16;
5457 inst.reloc.type = BFD_RELOC_UNUSED;
5458 }
5459
5460 static void
5461 do_strexd (void)
5462 {
5463 constraint (inst.operands[1].reg % 2 != 0,
5464 _("even register required"));
5465 constraint (inst.operands[2].present
5466 && inst.operands[2].reg != inst.operands[1].reg + 1,
5467 _("can only store two consecutive registers"));
5468 /* If op 2 were present and equal to PC, this function wouldn't
5469 have been called in the first place. */
5470 constraint (inst.operands[1].reg == REG_LR, _("r14 not allowed here"));
5471
5472 constraint (inst.operands[0].reg == inst.operands[1].reg
5473 || inst.operands[0].reg == inst.operands[1].reg + 1
5474 || inst.operands[0].reg == inst.operands[3].reg,
5475 BAD_OVERLAP);
5476
5477 inst.instruction |= inst.operands[0].reg << 12;
5478 inst.instruction |= inst.operands[1].reg;
5479 inst.instruction |= inst.operands[3].reg << 16;
5480 }
5481
5482 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
5483 extends it to 32-bits, and adds the result to a value in another
5484 register. You can specify a rotation by 0, 8, 16, or 24 bits
5485 before extracting the 16-bit value.
5486 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
5487 Condition defaults to COND_ALWAYS.
5488 Error if any register uses R15. */
5489
5490 static void
5491 do_sxtah (void)
5492 {
5493 inst.instruction |= inst.operands[0].reg << 12;
5494 inst.instruction |= inst.operands[1].reg << 16;
5495 inst.instruction |= inst.operands[2].reg;
5496 inst.instruction |= inst.operands[3].imm << 10;
5497 }
5498
5499 /* ARM V6 SXTH.
5500
5501 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
5502 Condition defaults to COND_ALWAYS.
5503 Error if any register uses R15. */
5504
5505 static void
5506 do_sxth (void)
5507 {
5508 inst.instruction |= inst.operands[0].reg << 12;
5509 inst.instruction |= inst.operands[1].reg;
5510 inst.instruction |= inst.operands[2].imm << 10;
5511 }
5512 \f
5513 /* VFP instructions. In a logical order: SP variant first, monad
5514 before dyad, arithmetic then move then load/store. */
5515
5516 static void
5517 do_vfp_sp_monadic (void)
5518 {
5519 encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sd);
5520 encode_arm_vfp_sp_reg (inst.operands[1].reg, VFP_REG_Sm);
5521 }
5522
5523 static void
5524 do_vfp_sp_dyadic (void)
5525 {
5526 encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sd);
5527 encode_arm_vfp_sp_reg (inst.operands[1].reg, VFP_REG_Sn);
5528 encode_arm_vfp_sp_reg (inst.operands[2].reg, VFP_REG_Sm);
5529 }
5530
5531 static void
5532 do_vfp_sp_compare_z (void)
5533 {
5534 encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sd);
5535 }
5536
5537 static void
5538 do_vfp_dp_sp_cvt (void)
5539 {
5540 inst.instruction |= inst.operands[0].reg << 12;
5541 encode_arm_vfp_sp_reg (inst.operands[1].reg, VFP_REG_Sm);
5542 }
5543
5544 static void
5545 do_vfp_sp_dp_cvt (void)
5546 {
5547 encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sd);
5548 inst.instruction |= inst.operands[1].reg;
5549 }
5550
5551 static void
5552 do_vfp_reg_from_sp (void)
5553 {
5554 inst.instruction |= inst.operands[0].reg << 12;
5555 encode_arm_vfp_sp_reg (inst.operands[1].reg, VFP_REG_Sn);
5556 }
5557
5558 static void
5559 do_vfp_reg2_from_sp2 (void)
5560 {
5561 constraint (inst.operands[2].imm != 2,
5562 _("only two consecutive VFP SP registers allowed here"));
5563 inst.instruction |= inst.operands[0].reg << 12;
5564 inst.instruction |= inst.operands[1].reg << 16;
5565 encode_arm_vfp_sp_reg (inst.operands[2].reg, VFP_REG_Sm);
5566 }
5567
5568 static void
5569 do_vfp_sp_from_reg (void)
5570 {
5571 encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sn);
5572 inst.instruction |= inst.operands[1].reg << 12;
5573 }
5574
5575 static void
5576 do_vfp_sp2_from_reg2 (void)
5577 {
5578 constraint (inst.operands[0].imm != 2,
5579 _("only two consecutive VFP SP registers allowed here"));
5580 encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sm);
5581 inst.instruction |= inst.operands[1].reg << 12;
5582 inst.instruction |= inst.operands[2].reg << 16;
5583 }
5584
5585 static void
5586 do_vfp_sp_ldst (void)
5587 {
5588 encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sd);
5589 encode_arm_cp_address (1, FALSE, TRUE, 0);
5590 }
5591
5592 static void
5593 do_vfp_dp_ldst (void)
5594 {
5595 inst.instruction |= inst.operands[0].reg << 12;
5596 encode_arm_cp_address (1, FALSE, TRUE, 0);
5597 }
5598
5599
5600 static void
5601 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type)
5602 {
5603 if (inst.operands[0].writeback)
5604 inst.instruction |= WRITE_BACK;
5605 else
5606 constraint (ldstm_type != VFP_LDSTMIA,
5607 _("this addressing mode requires base-register writeback"));
5608 inst.instruction |= inst.operands[0].reg << 16;
5609 encode_arm_vfp_sp_reg (inst.operands[1].reg, VFP_REG_Sd);
5610 inst.instruction |= inst.operands[1].imm;
5611 }
5612
5613 static void
5614 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type)
5615 {
5616 int count;
5617
5618 if (inst.operands[0].writeback)
5619 inst.instruction |= WRITE_BACK;
5620 else
5621 constraint (ldstm_type != VFP_LDSTMIA && ldstm_type != VFP_LDSTMIAX,
5622 _("this addressing mode requires base-register writeback"));
5623
5624 inst.instruction |= inst.operands[0].reg << 16;
5625 inst.instruction |= inst.operands[1].reg << 12;
5626
5627 count = inst.operands[1].imm << 1;
5628 if (ldstm_type == VFP_LDSTMIAX || ldstm_type == VFP_LDSTMDBX)
5629 count += 1;
5630
5631 inst.instruction |= count;
5632 }
5633
5634 static void
5635 do_vfp_sp_ldstmia (void)
5636 {
5637 vfp_sp_ldstm (VFP_LDSTMIA);
5638 }
5639
5640 static void
5641 do_vfp_sp_ldstmdb (void)
5642 {
5643 vfp_sp_ldstm (VFP_LDSTMDB);
5644 }
5645
5646 static void
5647 do_vfp_dp_ldstmia (void)
5648 {
5649 vfp_dp_ldstm (VFP_LDSTMIA);
5650 }
5651
5652 static void
5653 do_vfp_dp_ldstmdb (void)
5654 {
5655 vfp_dp_ldstm (VFP_LDSTMDB);
5656 }
5657
5658 static void
5659 do_vfp_xp_ldstmia (void)
5660 {
5661 vfp_dp_ldstm (VFP_LDSTMIAX);
5662 }
5663
5664 static void
5665 do_vfp_xp_ldstmdb (void)
5666 {
5667 vfp_dp_ldstm (VFP_LDSTMDBX);
5668 }
5669 \f
5670 /* FPA instructions. Also in a logical order. */
5671
5672 static void
5673 do_fpa_cmp (void)
5674 {
5675 inst.instruction |= inst.operands[0].reg << 16;
5676 inst.instruction |= inst.operands[1].reg;
5677 }
5678
5679 static void
5680 do_fpa_ldmstm (void)
5681 {
5682 inst.instruction |= inst.operands[0].reg << 12;
5683 switch (inst.operands[1].imm)
5684 {
5685 case 1: inst.instruction |= CP_T_X; break;
5686 case 2: inst.instruction |= CP_T_Y; break;
5687 case 3: inst.instruction |= CP_T_Y | CP_T_X; break;
5688 case 4: break;
5689 default: abort ();
5690 }
5691
5692 if (inst.instruction & (PRE_INDEX | INDEX_UP))
5693 {
5694 /* The instruction specified "ea" or "fd", so we can only accept
5695 [Rn]{!}. The instruction does not really support stacking or
5696 unstacking, so we have to emulate these by setting appropriate
5697 bits and offsets. */
5698 constraint (inst.reloc.exp.X_op != O_constant
5699 || inst.reloc.exp.X_add_number != 0,
5700 _("this instruction does not support indexing"));
5701
5702 if ((inst.instruction & PRE_INDEX) || inst.operands[2].writeback)
5703 inst.reloc.exp.X_add_number = 12 * inst.operands[1].imm;
5704
5705 if (!(inst.instruction & INDEX_UP))
5706 inst.reloc.exp.X_add_number = -inst.reloc.exp.X_add_number;
5707
5708 if (!(inst.instruction & PRE_INDEX) && inst.operands[2].writeback)
5709 {
5710 inst.operands[2].preind = 0;
5711 inst.operands[2].postind = 1;
5712 }
5713 }
5714
5715 encode_arm_cp_address (2, TRUE, TRUE, 0);
5716 }
5717 \f
5718 /* iWMMXt instructions: strictly in alphabetical order. */
5719
5720 static void
5721 do_iwmmxt_tandorc (void)
5722 {
5723 constraint (inst.operands[0].reg != REG_PC, _("only r15 allowed here"));
5724 }
5725
5726 static void
5727 do_iwmmxt_textrc (void)
5728 {
5729 inst.instruction |= inst.operands[0].reg << 12;
5730 inst.instruction |= inst.operands[1].imm;
5731 }
5732
5733 static void
5734 do_iwmmxt_textrm (void)
5735 {
5736 inst.instruction |= inst.operands[0].reg << 12;
5737 inst.instruction |= inst.operands[1].reg << 16;
5738 inst.instruction |= inst.operands[2].imm;
5739 }
5740
5741 static void
5742 do_iwmmxt_tinsr (void)
5743 {
5744 inst.instruction |= inst.operands[0].reg << 16;
5745 inst.instruction |= inst.operands[1].reg << 12;
5746 inst.instruction |= inst.operands[2].imm;
5747 }
5748
5749 static void
5750 do_iwmmxt_tmia (void)
5751 {
5752 inst.instruction |= inst.operands[0].reg << 5;
5753 inst.instruction |= inst.operands[1].reg;
5754 inst.instruction |= inst.operands[2].reg << 12;
5755 }
5756
5757 static void
5758 do_iwmmxt_waligni (void)
5759 {
5760 inst.instruction |= inst.operands[0].reg << 12;
5761 inst.instruction |= inst.operands[1].reg << 16;
5762 inst.instruction |= inst.operands[2].reg;
5763 inst.instruction |= inst.operands[3].imm << 20;
5764 }
5765
5766 static void
5767 do_iwmmxt_wmov (void)
5768 {
5769 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
5770 inst.instruction |= inst.operands[0].reg << 12;
5771 inst.instruction |= inst.operands[1].reg << 16;
5772 inst.instruction |= inst.operands[1].reg;
5773 }
5774
5775 static void
5776 do_iwmmxt_wldstbh (void)
5777 {
5778 int reloc;
5779 inst.instruction |= inst.operands[0].reg << 12;
5780 inst.reloc.exp.X_add_number *= 4;
5781 if (thumb_mode)
5782 reloc = BFD_RELOC_ARM_T32_CP_OFF_IMM_S2;
5783 else
5784 reloc = BFD_RELOC_ARM_CP_OFF_IMM_S2;
5785 encode_arm_cp_address (1, TRUE, FALSE, reloc);
5786 }
5787
5788 static void
5789 do_iwmmxt_wldstw (void)
5790 {
5791 /* RIWR_RIWC clears .isreg for a control register. */
5792 if (!inst.operands[0].isreg)
5793 {
5794 constraint (inst.cond != COND_ALWAYS, BAD_COND);
5795 inst.instruction |= 0xf0000000;
5796 }
5797
5798 inst.instruction |= inst.operands[0].reg << 12;
5799 encode_arm_cp_address (1, TRUE, TRUE, 0);
5800 }
5801
5802 static void
5803 do_iwmmxt_wldstd (void)
5804 {
5805 inst.instruction |= inst.operands[0].reg << 12;
5806 encode_arm_cp_address (1, TRUE, FALSE, 0);
5807 }
5808
5809 static void
5810 do_iwmmxt_wshufh (void)
5811 {
5812 inst.instruction |= inst.operands[0].reg << 12;
5813 inst.instruction |= inst.operands[1].reg << 16;
5814 inst.instruction |= ((inst.operands[2].imm & 0xf0) << 16);
5815 inst.instruction |= (inst.operands[2].imm & 0x0f);
5816 }
5817
5818 static void
5819 do_iwmmxt_wzero (void)
5820 {
5821 /* WZERO reg is an alias for WANDN reg, reg, reg. */
5822 inst.instruction |= inst.operands[0].reg;
5823 inst.instruction |= inst.operands[0].reg << 12;
5824 inst.instruction |= inst.operands[0].reg << 16;
5825 }
5826 \f
5827 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
5828 operations first, then control, shift, and load/store. */
5829
5830 /* Insns like "foo X,Y,Z". */
5831
5832 static void
5833 do_mav_triple (void)
5834 {
5835 inst.instruction |= inst.operands[0].reg << 16;
5836 inst.instruction |= inst.operands[1].reg;
5837 inst.instruction |= inst.operands[2].reg << 12;
5838 }
5839
5840 /* Insns like "foo W,X,Y,Z".
5841 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
5842
5843 static void
5844 do_mav_quad (void)
5845 {
5846 inst.instruction |= inst.operands[0].reg << 5;
5847 inst.instruction |= inst.operands[1].reg << 12;
5848 inst.instruction |= inst.operands[2].reg << 16;
5849 inst.instruction |= inst.operands[3].reg;
5850 }
5851
5852 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
5853 static void
5854 do_mav_dspsc (void)
5855 {
5856 inst.instruction |= inst.operands[1].reg << 12;
5857 }
5858
5859 /* Maverick shift immediate instructions.
5860 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
5861 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
5862
5863 static void
5864 do_mav_shift (void)
5865 {
5866 int imm = inst.operands[2].imm;
5867
5868 inst.instruction |= inst.operands[0].reg << 12;
5869 inst.instruction |= inst.operands[1].reg << 16;
5870
5871 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
5872 Bits 5-7 of the insn should have bits 4-6 of the immediate.
5873 Bit 4 should be 0. */
5874 imm = (imm & 0xf) | ((imm & 0x70) << 1);
5875
5876 inst.instruction |= imm;
5877 }
5878 \f
5879 /* XScale instructions. Also sorted arithmetic before move. */
5880
5881 /* Xscale multiply-accumulate (argument parse)
5882 MIAcc acc0,Rm,Rs
5883 MIAPHcc acc0,Rm,Rs
5884 MIAxycc acc0,Rm,Rs. */
5885
5886 static void
5887 do_xsc_mia (void)
5888 {
5889 inst.instruction |= inst.operands[1].reg;
5890 inst.instruction |= inst.operands[2].reg << 12;
5891 }
5892
5893 /* Xscale move-accumulator-register (argument parse)
5894
5895 MARcc acc0,RdLo,RdHi. */
5896
5897 static void
5898 do_xsc_mar (void)
5899 {
5900 inst.instruction |= inst.operands[1].reg << 12;
5901 inst.instruction |= inst.operands[2].reg << 16;
5902 }
5903
5904 /* Xscale move-register-accumulator (argument parse)
5905
5906 MRAcc RdLo,RdHi,acc0. */
5907
5908 static void
5909 do_xsc_mra (void)
5910 {
5911 constraint (inst.operands[0].reg == inst.operands[1].reg, BAD_OVERLAP);
5912 inst.instruction |= inst.operands[0].reg << 12;
5913 inst.instruction |= inst.operands[1].reg << 16;
5914 }
5915 \f
5916 /* Encoding functions relevant only to Thumb. */
5917
5918 /* inst.operands[i] is a shifted-register operand; encode
5919 it into inst.instruction in the format used by Thumb32. */
5920
5921 static void
5922 encode_thumb32_shifted_operand (int i)
5923 {
5924 unsigned int value = inst.reloc.exp.X_add_number;
5925 unsigned int shift = inst.operands[i].shift_kind;
5926
5927 constraint (inst.operands[i].immisreg,
5928 _("shift by register not allowed in thumb mode"));
5929 inst.instruction |= inst.operands[i].reg;
5930 if (shift == SHIFT_RRX)
5931 inst.instruction |= SHIFT_ROR << 4;
5932 else
5933 {
5934 constraint (inst.reloc.exp.X_op != O_constant,
5935 _("expression too complex"));
5936
5937 constraint (value > 32
5938 || (value == 32 && (shift == SHIFT_LSL
5939 || shift == SHIFT_ROR)),
5940 _("shift expression is too large"));
5941
5942 if (value == 0)
5943 shift = SHIFT_LSL;
5944 else if (value == 32)
5945 value = 0;
5946
5947 inst.instruction |= shift << 4;
5948 inst.instruction |= (value & 0x1c) << 10;
5949 inst.instruction |= (value & 0x03) << 6;
5950 }
5951 }
5952
5953
5954 /* inst.operands[i] was set up by parse_address. Encode it into a
5955 Thumb32 format load or store instruction. Reject forms that cannot
5956 be used with such instructions. If is_t is true, reject forms that
5957 cannot be used with a T instruction; if is_d is true, reject forms
5958 that cannot be used with a D instruction. */
5959
5960 static void
5961 encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d)
5962 {
5963 bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);
5964
5965 constraint (!inst.operands[i].isreg,
5966 _("Thumb does not support the ldr =N pseudo-operation"));
5967
5968 inst.instruction |= inst.operands[i].reg << 16;
5969 if (inst.operands[i].immisreg)
5970 {
5971 constraint (is_pc, _("cannot use register index with PC-relative addressing"));
5972 constraint (is_t || is_d, _("cannot use register index with this instruction"));
5973 constraint (inst.operands[i].negative,
5974 _("Thumb does not support negative register indexing"));
5975 constraint (inst.operands[i].postind,
5976 _("Thumb does not support register post-indexing"));
5977 constraint (inst.operands[i].writeback,
5978 _("Thumb does not support register indexing with writeback"));
5979 constraint (inst.operands[i].shifted && inst.operands[i].shift_kind != SHIFT_LSL,
5980 _("Thumb supports only LSL in shifted register indexing"));
5981
5982 inst.instruction |= inst.operands[i].imm;
5983 if (inst.operands[i].shifted)
5984 {
5985 constraint (inst.reloc.exp.X_op != O_constant,
5986 _("expression too complex"));
5987 constraint (inst.reloc.exp.X_add_number < 0
5988 || inst.reloc.exp.X_add_number > 3,
5989 _("shift out of range"));
5990 inst.instruction |= inst.reloc.exp.X_add_number << 4;
5991 }
5992 inst.reloc.type = BFD_RELOC_UNUSED;
5993 }
5994 else if (inst.operands[i].preind)
5995 {
5996 constraint (is_pc && inst.operands[i].writeback,
5997 _("cannot use writeback with PC-relative addressing"));
5998 constraint (is_t && inst.operands[i].writeback,
5999 _("cannot use writeback with this instruction"));
6000
6001 if (is_d)
6002 {
6003 inst.instruction |= 0x01000000;
6004 if (inst.operands[i].writeback)
6005 inst.instruction |= 0x00200000;
6006 }
6007 else
6008 {
6009 inst.instruction |= 0x00000c00;
6010 if (inst.operands[i].writeback)
6011 inst.instruction |= 0x00000100;
6012 }
6013 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
6014 }
6015 else if (inst.operands[i].postind)
6016 {
6017 assert (inst.operands[i].writeback);
6018 constraint (is_pc, _("cannot use post-indexing with PC-relative addressing"));
6019 constraint (is_t, _("cannot use post-indexing with this instruction"));
6020
6021 if (is_d)
6022 inst.instruction |= 0x00200000;
6023 else
6024 inst.instruction |= 0x00000900;
6025 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
6026 }
6027 else /* unindexed - only for coprocessor */
6028 inst.error = _("instruction does not accept unindexed addressing");
6029 }
6030
6031 /* Table of Thumb instructions which exist in both 16- and 32-bit
6032 encodings (the latter only in post-V6T2 cores). The index is the
6033 value used in the insns table below. When there is more than one
6034 possible 16-bit encoding for the instruction, this table always
6035 holds variant (1).
6036 Also contains several pseudo-instructions used during relaxation. */
6037 #define T16_32_TAB \
6038 X(adc, 4140, eb400000), \
6039 X(adcs, 4140, eb500000), \
6040 X(add, 1c00, eb000000), \
6041 X(adds, 1c00, eb100000), \
6042 X(addi, 0000, f1000000), \
6043 X(addis, 0000, f1100000), \
6044 X(add_pc,000f, f20f0000), \
6045 X(add_sp,000d, f10d0000), \
6046 X(adr, 000f, f20f0000), \
6047 X(and, 4000, ea000000), \
6048 X(ands, 4000, ea100000), \
6049 X(asr, 1000, fa40f000), \
6050 X(asrs, 1000, fa50f000), \
6051 X(b, e000, f000b000), \
6052 X(bcond, d000, f0008000), \
6053 X(bic, 4380, ea200000), \
6054 X(bics, 4380, ea300000), \
6055 X(cmn, 42c0, eb100f00), \
6056 X(cmp, 2800, ebb00f00), \
6057 X(cpsie, b660, f3af8400), \
6058 X(cpsid, b670, f3af8600), \
6059 X(cpy, 4600, ea4f0000), \
6060 X(dec_sp,80dd, f1bd0d00), \
6061 X(eor, 4040, ea800000), \
6062 X(eors, 4040, ea900000), \
6063 X(inc_sp,00dd, f10d0d00), \
6064 X(ldmia, c800, e8900000), \
6065 X(ldr, 6800, f8500000), \
6066 X(ldrb, 7800, f8100000), \
6067 X(ldrh, 8800, f8300000), \
6068 X(ldrsb, 5600, f9100000), \
6069 X(ldrsh, 5e00, f9300000), \
6070 X(ldr_pc,4800, f85f0000), \
6071 X(ldr_pc2,4800, f85f0000), \
6072 X(ldr_sp,9800, f85d0000), \
6073 X(lsl, 0000, fa00f000), \
6074 X(lsls, 0000, fa10f000), \
6075 X(lsr, 0800, fa20f000), \
6076 X(lsrs, 0800, fa30f000), \
6077 X(mov, 2000, ea4f0000), \
6078 X(movs, 2000, ea5f0000), \
6079 X(mul, 4340, fb00f000), \
6080 X(muls, 4340, ffffffff), /* no 32b muls */ \
6081 X(mvn, 43c0, ea6f0000), \
6082 X(mvns, 43c0, ea7f0000), \
6083 X(neg, 4240, f1c00000), /* rsb #0 */ \
6084 X(negs, 4240, f1d00000), /* rsbs #0 */ \
6085 X(orr, 4300, ea400000), \
6086 X(orrs, 4300, ea500000), \
6087 X(pop, bc00, e8bd0000), /* ldmia sp!,... */ \
6088 X(push, b400, e92d0000), /* stmdb sp!,... */ \
6089 X(rev, ba00, fa90f080), \
6090 X(rev16, ba40, fa90f090), \
6091 X(revsh, bac0, fa90f0b0), \
6092 X(ror, 41c0, fa60f000), \
6093 X(rors, 41c0, fa70f000), \
6094 X(sbc, 4180, eb600000), \
6095 X(sbcs, 4180, eb700000), \
6096 X(stmia, c000, e8800000), \
6097 X(str, 6000, f8400000), \
6098 X(strb, 7000, f8000000), \
6099 X(strh, 8000, f8200000), \
6100 X(str_sp,9000, f84d0000), \
6101 X(sub, 1e00, eba00000), \
6102 X(subs, 1e00, ebb00000), \
6103 X(subi, 8000, f1a00000), \
6104 X(subis, 8000, f1b00000), \
6105 X(sxtb, b240, fa4ff080), \
6106 X(sxth, b200, fa0ff080), \
6107 X(tst, 4200, ea100f00), \
6108 X(uxtb, b2c0, fa5ff080), \
6109 X(uxth, b280, fa1ff080), \
6110 X(nop, bf00, f3af8000), \
6111 X(yield, bf10, f3af8001), \
6112 X(wfe, bf20, f3af8002), \
6113 X(wfi, bf30, f3af8003), \
6114 X(sev, bf40, f3af9004), /* typo, 8004? */
6115
6116 /* To catch errors in encoding functions, the codes are all offset by
6117 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
6118 as 16-bit instructions. */
6119 #define X(a,b,c) T_MNEM_##a
6120 enum t16_32_codes { T16_32_OFFSET = 0xF7FF, T16_32_TAB };
6121 #undef X
6122
6123 #define X(a,b,c) 0x##b
6124 static const unsigned short thumb_op16[] = { T16_32_TAB };
6125 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
6126 #undef X
6127
6128 #define X(a,b,c) 0x##c
6129 static const unsigned int thumb_op32[] = { T16_32_TAB };
6130 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
6131 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
6132 #undef X
6133 #undef T16_32_TAB
6134
6135 /* Thumb instruction encoders, in alphabetical order. */
6136
6137 /* ADDW or SUBW. */
6138 static void
6139 do_t_add_sub_w (void)
6140 {
6141 int Rd, Rn;
6142
6143 Rd = inst.operands[0].reg;
6144 Rn = inst.operands[1].reg;
6145
6146 constraint (Rd == 15, _("PC not allowed as destination"));
6147 inst.instruction |= (Rn << 16) | (Rd << 8);
6148 inst.reloc.type = BFD_RELOC_ARM_T32_IMM12;
6149 }
6150
6151 /* Parse an add or subtract instruction. We get here with inst.instruction
6152 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
6153
6154 static void
6155 do_t_add_sub (void)
6156 {
6157 int Rd, Rs, Rn;
6158
6159 Rd = inst.operands[0].reg;
6160 Rs = (inst.operands[1].present
6161 ? inst.operands[1].reg /* Rd, Rs, foo */
6162 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
6163
6164 if (unified_syntax)
6165 {
6166 bfd_boolean flags;
6167 bfd_boolean narrow;
6168 int opcode;
6169
6170 flags = (inst.instruction == T_MNEM_adds
6171 || inst.instruction == T_MNEM_subs);
6172 if (flags)
6173 narrow = (current_it_mask == 0);
6174 else
6175 narrow = (current_it_mask != 0);
6176 if (!inst.operands[2].isreg)
6177 {
6178 opcode = 0;
6179 if (inst.size_req != 4)
6180 {
6181 int add;
6182
6183 add = (inst.instruction == T_MNEM_add
6184 || inst.instruction == T_MNEM_adds);
6185 /* Attempt to use a narrow opcode, with relaxation if
6186 appropriate. */
6187 if (Rd == REG_SP && Rs == REG_SP && !flags)
6188 opcode = add ? T_MNEM_inc_sp : T_MNEM_dec_sp;
6189 else if (Rd <= 7 && Rs == REG_SP && add && !flags)
6190 opcode = T_MNEM_add_sp;
6191 else if (Rd <= 7 && Rs == REG_PC && add && !flags)
6192 opcode = T_MNEM_add_pc;
6193 else if (Rd <= 7 && Rs <= 7 && narrow)
6194 {
6195 if (flags)
6196 opcode = add ? T_MNEM_addis : T_MNEM_subis;
6197 else
6198 opcode = add ? T_MNEM_addi : T_MNEM_subi;
6199 }
6200 if (opcode)
6201 {
6202 inst.instruction = THUMB_OP16(opcode);
6203 inst.instruction |= (Rd << 4) | Rs;
6204 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
6205 if (inst.size_req != 2)
6206 inst.relax = opcode;
6207 }
6208 else
6209 constraint (inst.size_req == 2, BAD_HIREG);
6210 }
6211 if (inst.size_req == 4
6212 || (inst.size_req != 2 && !opcode))
6213 {
6214 /* ??? Convert large immediates to addw/subw. */
6215 inst.instruction = THUMB_OP32 (inst.instruction);
6216 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
6217 inst.instruction |= inst.operands[0].reg << 8;
6218 inst.instruction |= inst.operands[1].reg << 16;
6219 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
6220 }
6221 }
6222 else
6223 {
6224 Rn = inst.operands[2].reg;
6225 /* See if we can do this with a 16-bit instruction. */
6226 if (!inst.operands[2].shifted && inst.size_req != 4)
6227 {
6228 if (Rd > 7 || Rs > 7 || Rn > 7)
6229 narrow = FALSE;
6230
6231 if (narrow)
6232 {
6233 inst.instruction = ((inst.instruction == T_MNEM_adds
6234 || inst.instruction == T_MNEM_add)
6235 ? T_OPCODE_ADD_R3
6236 : T_OPCODE_SUB_R3);
6237 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
6238 return;
6239 }
6240
6241 if (inst.instruction == T_MNEM_add)
6242 {
6243 if (Rd == Rs)
6244 {
6245 inst.instruction = T_OPCODE_ADD_HI;
6246 inst.instruction |= (Rd & 8) << 4;
6247 inst.instruction |= (Rd & 7);
6248 inst.instruction |= Rn << 3;
6249 return;
6250 }
6251 /* ... because addition is commutative! */
6252 else if (Rd == Rn)
6253 {
6254 inst.instruction = T_OPCODE_ADD_HI;
6255 inst.instruction |= (Rd & 8) << 4;
6256 inst.instruction |= (Rd & 7);
6257 inst.instruction |= Rs << 3;
6258 return;
6259 }
6260 }
6261 }
6262 /* If we get here, it can't be done in 16 bits. */
6263 constraint (inst.operands[2].shifted && inst.operands[2].immisreg,
6264 _("shift must be constant"));
6265 inst.instruction = THUMB_OP32 (inst.instruction);
6266 inst.instruction |= Rd << 8;
6267 inst.instruction |= Rs << 16;
6268 encode_thumb32_shifted_operand (2);
6269 }
6270 }
6271 else
6272 {
6273 constraint (inst.instruction == T_MNEM_adds
6274 || inst.instruction == T_MNEM_subs,
6275 BAD_THUMB32);
6276
6277 if (!inst.operands[2].isreg) /* Rd, Rs, #imm */
6278 {
6279 constraint ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP))
6280 || (Rs > 7 && Rs != REG_SP && Rs != REG_PC),
6281 BAD_HIREG);
6282
6283 inst.instruction = (inst.instruction == T_MNEM_add
6284 ? 0x0000 : 0x8000);
6285 inst.instruction |= (Rd << 4) | Rs;
6286 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
6287 return;
6288 }
6289
6290 Rn = inst.operands[2].reg;
6291 constraint (inst.operands[2].shifted, _("unshifted register required"));
6292
6293 /* We now have Rd, Rs, and Rn set to registers. */
6294 if (Rd > 7 || Rs > 7 || Rn > 7)
6295 {
6296 /* Can't do this for SUB. */
6297 constraint (inst.instruction == T_MNEM_sub, BAD_HIREG);
6298 inst.instruction = T_OPCODE_ADD_HI;
6299 inst.instruction |= (Rd & 8) << 4;
6300 inst.instruction |= (Rd & 7);
6301 if (Rs == Rd)
6302 inst.instruction |= Rn << 3;
6303 else if (Rn == Rd)
6304 inst.instruction |= Rs << 3;
6305 else
6306 constraint (1, _("dest must overlap one source register"));
6307 }
6308 else
6309 {
6310 inst.instruction = (inst.instruction == T_MNEM_add
6311 ? T_OPCODE_ADD_R3 : T_OPCODE_SUB_R3);
6312 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
6313 }
6314 }
6315 }
6316
6317 static void
6318 do_t_adr (void)
6319 {
6320 if (unified_syntax && inst.size_req == 0 && inst.operands[0].reg <= 7)
6321 {
6322 /* Defer to section relaxation. */
6323 inst.relax = inst.instruction;
6324 inst.instruction = THUMB_OP16 (inst.instruction);
6325 inst.instruction |= inst.operands[0].reg << 4;
6326 }
6327 else if (unified_syntax && inst.size_req != 2)
6328 {
6329 /* Generate a 32-bit opcode. */
6330 inst.instruction = THUMB_OP32 (inst.instruction);
6331 inst.instruction |= inst.operands[0].reg << 8;
6332 inst.reloc.type = BFD_RELOC_ARM_T32_ADD_PC12;
6333 inst.reloc.pc_rel = 1;
6334 }
6335 else
6336 {
6337 /* Generate a 16-bit opcode. */
6338 inst.instruction = THUMB_OP16 (inst.instruction);
6339 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
6340 inst.reloc.exp.X_add_number -= 4; /* PC relative adjust. */
6341 inst.reloc.pc_rel = 1;
6342
6343 inst.instruction |= inst.operands[0].reg << 4;
6344 }
6345 }
6346
6347 /* Arithmetic instructions for which there is just one 16-bit
6348 instruction encoding, and it allows only two low registers.
6349 For maximal compatibility with ARM syntax, we allow three register
6350 operands even when Thumb-32 instructions are not available, as long
6351 as the first two are identical. For instance, both "sbc r0,r1" and
6352 "sbc r0,r0,r1" are allowed. */
6353 static void
6354 do_t_arit3 (void)
6355 {
6356 int Rd, Rs, Rn;
6357
6358 Rd = inst.operands[0].reg;
6359 Rs = (inst.operands[1].present
6360 ? inst.operands[1].reg /* Rd, Rs, foo */
6361 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
6362 Rn = inst.operands[2].reg;
6363
6364 if (unified_syntax)
6365 {
6366 if (!inst.operands[2].isreg)
6367 {
6368 /* For an immediate, we always generate a 32-bit opcode;
6369 section relaxation will shrink it later if possible. */
6370 inst.instruction = THUMB_OP32 (inst.instruction);
6371 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
6372 inst.instruction |= Rd << 8;
6373 inst.instruction |= Rs << 16;
6374 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
6375 }
6376 else
6377 {
6378 bfd_boolean narrow;
6379
6380 /* See if we can do this with a 16-bit instruction. */
6381 if (THUMB_SETS_FLAGS (inst.instruction))
6382 narrow = current_it_mask == 0;
6383 else
6384 narrow = current_it_mask != 0;
6385
6386 if (Rd > 7 || Rn > 7 || Rs > 7)
6387 narrow = FALSE;
6388 if (inst.operands[2].shifted)
6389 narrow = FALSE;
6390 if (inst.size_req == 4)
6391 narrow = FALSE;
6392
6393 if (narrow
6394 && Rd == Rs)
6395 {
6396 inst.instruction = THUMB_OP16 (inst.instruction);
6397 inst.instruction |= Rd;
6398 inst.instruction |= Rn << 3;
6399 return;
6400 }
6401
6402 /* If we get here, it can't be done in 16 bits. */
6403 constraint (inst.operands[2].shifted
6404 && inst.operands[2].immisreg,
6405 _("shift must be constant"));
6406 inst.instruction = THUMB_OP32 (inst.instruction);
6407 inst.instruction |= Rd << 8;
6408 inst.instruction |= Rs << 16;
6409 encode_thumb32_shifted_operand (2);
6410 }
6411 }
6412 else
6413 {
6414 /* On its face this is a lie - the instruction does set the
6415 flags. However, the only supported mnemonic in this mode
6416 says it doesn't. */
6417 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
6418
6419 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
6420 _("unshifted register required"));
6421 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
6422 constraint (Rd != Rs,
6423 _("dest and source1 must be the same register"));
6424
6425 inst.instruction = THUMB_OP16 (inst.instruction);
6426 inst.instruction |= Rd;
6427 inst.instruction |= Rn << 3;
6428 }
6429 }
6430
6431 /* Similarly, but for instructions where the arithmetic operation is
6432 commutative, so we can allow either of them to be different from
6433 the destination operand in a 16-bit instruction. For instance, all
6434 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
6435 accepted. */
6436 static void
6437 do_t_arit3c (void)
6438 {
6439 int Rd, Rs, Rn;
6440
6441 Rd = inst.operands[0].reg;
6442 Rs = (inst.operands[1].present
6443 ? inst.operands[1].reg /* Rd, Rs, foo */
6444 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
6445 Rn = inst.operands[2].reg;
6446
6447 if (unified_syntax)
6448 {
6449 if (!inst.operands[2].isreg)
6450 {
6451 /* For an immediate, we always generate a 32-bit opcode;
6452 section relaxation will shrink it later if possible. */
6453 inst.instruction = THUMB_OP32 (inst.instruction);
6454 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
6455 inst.instruction |= Rd << 8;
6456 inst.instruction |= Rs << 16;
6457 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
6458 }
6459 else
6460 {
6461 bfd_boolean narrow;
6462
6463 /* See if we can do this with a 16-bit instruction. */
6464 if (THUMB_SETS_FLAGS (inst.instruction))
6465 narrow = current_it_mask == 0;
6466 else
6467 narrow = current_it_mask != 0;
6468
6469 if (Rd > 7 || Rn > 7 || Rs > 7)
6470 narrow = FALSE;
6471 if (inst.operands[2].shifted)
6472 narrow = FALSE;
6473 if (inst.size_req == 4)
6474 narrow = FALSE;
6475
6476 if (narrow)
6477 {
6478 if (Rd == Rs)
6479 {
6480 inst.instruction = THUMB_OP16 (inst.instruction);
6481 inst.instruction |= Rd;
6482 inst.instruction |= Rn << 3;
6483 return;
6484 }
6485 if (Rd == Rn)
6486 {
6487 inst.instruction = THUMB_OP16 (inst.instruction);
6488 inst.instruction |= Rd;
6489 inst.instruction |= Rs << 3;
6490 return;
6491 }
6492 }
6493
6494 /* If we get here, it can't be done in 16 bits. */
6495 constraint (inst.operands[2].shifted
6496 && inst.operands[2].immisreg,
6497 _("shift must be constant"));
6498 inst.instruction = THUMB_OP32 (inst.instruction);
6499 inst.instruction |= Rd << 8;
6500 inst.instruction |= Rs << 16;
6501 encode_thumb32_shifted_operand (2);
6502 }
6503 }
6504 else
6505 {
6506 /* On its face this is a lie - the instruction does set the
6507 flags. However, the only supported mnemonic in this mode
6508 says it doesn't. */
6509 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
6510
6511 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
6512 _("unshifted register required"));
6513 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
6514
6515 inst.instruction = THUMB_OP16 (inst.instruction);
6516 inst.instruction |= Rd;
6517
6518 if (Rd == Rs)
6519 inst.instruction |= Rn << 3;
6520 else if (Rd == Rn)
6521 inst.instruction |= Rs << 3;
6522 else
6523 constraint (1, _("dest must overlap one source register"));
6524 }
6525 }
6526
6527 static void
6528 do_t_barrier (void)
6529 {
6530 if (inst.operands[0].present)
6531 {
6532 constraint ((inst.instruction & 0xf0) != 0x40
6533 && inst.operands[0].imm != 0xf,
6534 "bad barrier type");
6535 inst.instruction |= inst.operands[0].imm;
6536 }
6537 else
6538 inst.instruction |= 0xf;
6539 }
6540
6541 static void
6542 do_t_bfc (void)
6543 {
6544 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
6545 constraint (msb > 32, _("bit-field extends past end of register"));
6546 /* The instruction encoding stores the LSB and MSB,
6547 not the LSB and width. */
6548 inst.instruction |= inst.operands[0].reg << 8;
6549 inst.instruction |= (inst.operands[1].imm & 0x1c) << 10;
6550 inst.instruction |= (inst.operands[1].imm & 0x03) << 6;
6551 inst.instruction |= msb - 1;
6552 }
6553
6554 static void
6555 do_t_bfi (void)
6556 {
6557 unsigned int msb;
6558
6559 /* #0 in second position is alternative syntax for bfc, which is
6560 the same instruction but with REG_PC in the Rm field. */
6561 if (!inst.operands[1].isreg)
6562 inst.operands[1].reg = REG_PC;
6563
6564 msb = inst.operands[2].imm + inst.operands[3].imm;
6565 constraint (msb > 32, _("bit-field extends past end of register"));
6566 /* The instruction encoding stores the LSB and MSB,
6567 not the LSB and width. */
6568 inst.instruction |= inst.operands[0].reg << 8;
6569 inst.instruction |= inst.operands[1].reg << 16;
6570 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
6571 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
6572 inst.instruction |= msb - 1;
6573 }
6574
6575 static void
6576 do_t_bfx (void)
6577 {
6578 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
6579 _("bit-field extends past end of register"));
6580 inst.instruction |= inst.operands[0].reg << 8;
6581 inst.instruction |= inst.operands[1].reg << 16;
6582 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
6583 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
6584 inst.instruction |= inst.operands[3].imm - 1;
6585 }
6586
6587 /* ARM V5 Thumb BLX (argument parse)
6588 BLX <target_addr> which is BLX(1)
6589 BLX <Rm> which is BLX(2)
6590 Unfortunately, there are two different opcodes for this mnemonic.
6591 So, the insns[].value is not used, and the code here zaps values
6592 into inst.instruction.
6593
6594 ??? How to take advantage of the additional two bits of displacement
6595 available in Thumb32 mode? Need new relocation? */
6596
6597 static void
6598 do_t_blx (void)
6599 {
6600 if (inst.operands[0].isreg)
6601 /* We have a register, so this is BLX(2). */
6602 inst.instruction |= inst.operands[0].reg << 3;
6603 else
6604 {
6605 /* No register. This must be BLX(1). */
6606 inst.instruction = 0xf000e800;
6607 #ifdef OBJ_ELF
6608 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
6609 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23;
6610 else
6611 #endif
6612 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BLX;
6613 inst.reloc.pc_rel = 1;
6614 }
6615 }
6616
6617 static void
6618 do_t_branch (void)
6619 {
6620 int opcode;
6621 if (inst.cond != COND_ALWAYS)
6622 opcode = T_MNEM_bcond;
6623 else
6624 opcode = inst.instruction;
6625
6626 if (unified_syntax && inst.size_req == 4)
6627 {
6628 inst.instruction = THUMB_OP32(opcode);
6629 if (inst.cond == COND_ALWAYS)
6630 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH25;
6631 else
6632 {
6633 assert (inst.cond != 0xF);
6634 inst.instruction |= inst.cond << 22;
6635 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH20;
6636 }
6637 }
6638 else
6639 {
6640 inst.instruction = THUMB_OP16(opcode);
6641 if (inst.cond == COND_ALWAYS)
6642 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH12;
6643 else
6644 {
6645 inst.instruction |= inst.cond << 8;
6646 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH9;
6647 }
6648 /* Allow section relaxation. */
6649 if (unified_syntax && inst.size_req != 2)
6650 inst.relax = opcode;
6651 }
6652
6653 inst.reloc.pc_rel = 1;
6654 }
6655
6656 static void
6657 do_t_bkpt (void)
6658 {
6659 if (inst.operands[0].present)
6660 {
6661 constraint (inst.operands[0].imm > 255,
6662 _("immediate value out of range"));
6663 inst.instruction |= inst.operands[0].imm;
6664 }
6665 }
6666
6667 static void
6668 do_t_branch23 (void)
6669 {
6670 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23;
6671 inst.reloc.pc_rel = 1;
6672
6673 /* If the destination of the branch is a defined symbol which does not have
6674 the THUMB_FUNC attribute, then we must be calling a function which has
6675 the (interfacearm) attribute. We look for the Thumb entry point to that
6676 function and change the branch to refer to that function instead. */
6677 if ( inst.reloc.exp.X_op == O_symbol
6678 && inst.reloc.exp.X_add_symbol != NULL
6679 && S_IS_DEFINED (inst.reloc.exp.X_add_symbol)
6680 && ! THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol))
6681 inst.reloc.exp.X_add_symbol =
6682 find_real_start (inst.reloc.exp.X_add_symbol);
6683 }
6684
6685 static void
6686 do_t_bx (void)
6687 {
6688 inst.instruction |= inst.operands[0].reg << 3;
6689 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
6690 should cause the alignment to be checked once it is known. This is
6691 because BX PC only works if the instruction is word aligned. */
6692 }
6693
6694 static void
6695 do_t_bxj (void)
6696 {
6697 if (inst.operands[0].reg == REG_PC)
6698 as_tsktsk (_("use of r15 in bxj is not really useful"));
6699
6700 inst.instruction |= inst.operands[0].reg << 16;
6701 }
6702
6703 static void
6704 do_t_clz (void)
6705 {
6706 inst.instruction |= inst.operands[0].reg << 8;
6707 inst.instruction |= inst.operands[1].reg << 16;
6708 inst.instruction |= inst.operands[1].reg;
6709 }
6710
6711 static void
6712 do_t_cpsi (void)
6713 {
6714 if (unified_syntax
6715 && (inst.operands[1].present || inst.size_req == 4)
6716 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6_notm))
6717 {
6718 unsigned int imod = (inst.instruction & 0x0030) >> 4;
6719 inst.instruction = 0xf3af8000;
6720 inst.instruction |= imod << 9;
6721 inst.instruction |= inst.operands[0].imm << 5;
6722 if (inst.operands[1].present)
6723 inst.instruction |= 0x100 | inst.operands[1].imm;
6724 }
6725 else
6726 {
6727 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)
6728 && (inst.operands[0].imm & 4),
6729 _("selected processor does not support 'A' form "
6730 "of this instruction"));
6731 constraint (inst.operands[1].present || inst.size_req == 4,
6732 _("Thumb does not support the 2-argument "
6733 "form of this instruction"));
6734 inst.instruction |= inst.operands[0].imm;
6735 }
6736 }
6737
6738 /* THUMB CPY instruction (argument parse). */
6739
6740 static void
6741 do_t_cpy (void)
6742 {
6743 if (inst.size_req == 4)
6744 {
6745 inst.instruction = THUMB_OP32 (T_MNEM_mov);
6746 inst.instruction |= inst.operands[0].reg << 8;
6747 inst.instruction |= inst.operands[1].reg;
6748 }
6749 else
6750 {
6751 inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
6752 inst.instruction |= (inst.operands[0].reg & 0x7);
6753 inst.instruction |= inst.operands[1].reg << 3;
6754 }
6755 }
6756
6757 static void
6758 do_t_czb (void)
6759 {
6760 constraint (inst.operands[0].reg > 7, BAD_HIREG);
6761 inst.instruction |= inst.operands[0].reg;
6762 inst.reloc.pc_rel = 1;
6763 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH7;
6764 }
6765
6766 static void
6767 do_t_dbg (void)
6768 {
6769 inst.instruction |= inst.operands[0].imm;
6770 }
6771
6772 static void
6773 do_t_div (void)
6774 {
6775 if (!inst.operands[1].present)
6776 inst.operands[1].reg = inst.operands[0].reg;
6777 inst.instruction |= inst.operands[0].reg << 8;
6778 inst.instruction |= inst.operands[1].reg << 16;
6779 inst.instruction |= inst.operands[2].reg;
6780 }
6781
6782 static void
6783 do_t_hint (void)
6784 {
6785 if (unified_syntax && inst.size_req == 4)
6786 inst.instruction = THUMB_OP32 (inst.instruction);
6787 else
6788 inst.instruction = THUMB_OP16 (inst.instruction);
6789 }
6790
6791 static void
6792 do_t_it (void)
6793 {
6794 unsigned int cond = inst.operands[0].imm;
6795
6796 current_it_mask = (inst.instruction & 0xf) | 0x10;
6797 current_cc = cond;
6798
6799 /* If the condition is a negative condition, invert the mask. */
6800 if ((cond & 0x1) == 0x0)
6801 {
6802 unsigned int mask = inst.instruction & 0x000f;
6803
6804 if ((mask & 0x7) == 0)
6805 /* no conversion needed */;
6806 else if ((mask & 0x3) == 0)
6807 mask ^= 0x8;
6808 else if ((mask & 0x1) == 0)
6809 mask ^= 0xC;
6810 else
6811 mask ^= 0xE;
6812
6813 inst.instruction &= 0xfff0;
6814 inst.instruction |= mask;
6815 }
6816
6817 inst.instruction |= cond << 4;
6818 }
6819
6820 static void
6821 do_t_ldmstm (void)
6822 {
6823 /* This really doesn't seem worth it. */
6824 constraint (inst.reloc.type != BFD_RELOC_UNUSED,
6825 _("expression too complex"));
6826 constraint (inst.operands[1].writeback,
6827 _("Thumb load/store multiple does not support {reglist}^"));
6828
6829 if (unified_syntax)
6830 {
6831 /* See if we can use a 16-bit instruction. */
6832 if (inst.instruction < 0xffff /* not ldmdb/stmdb */
6833 && inst.size_req != 4
6834 && inst.operands[0].reg <= 7
6835 && !(inst.operands[1].imm & ~0xff)
6836 && (inst.instruction == T_MNEM_stmia
6837 ? inst.operands[0].writeback
6838 : (inst.operands[0].writeback
6839 == !(inst.operands[1].imm & (1 << inst.operands[0].reg)))))
6840 {
6841 if (inst.instruction == T_MNEM_stmia
6842 && (inst.operands[1].imm & (1 << inst.operands[0].reg))
6843 && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1)))
6844 as_warn (_("value stored for r%d is UNPREDICTABLE"),
6845 inst.operands[0].reg);
6846
6847 inst.instruction = THUMB_OP16 (inst.instruction);
6848 inst.instruction |= inst.operands[0].reg << 8;
6849 inst.instruction |= inst.operands[1].imm;
6850 }
6851 else
6852 {
6853 if (inst.operands[1].imm & (1 << 13))
6854 as_warn (_("SP should not be in register list"));
6855 if (inst.instruction == T_MNEM_stmia)
6856 {
6857 if (inst.operands[1].imm & (1 << 15))
6858 as_warn (_("PC should not be in register list"));
6859 if (inst.operands[1].imm & (1 << inst.operands[0].reg))
6860 as_warn (_("value stored for r%d is UNPREDICTABLE"),
6861 inst.operands[0].reg);
6862 }
6863 else
6864 {
6865 if (inst.operands[1].imm & (1 << 14)
6866 && inst.operands[1].imm & (1 << 15))
6867 as_warn (_("LR and PC should not both be in register list"));
6868 if ((inst.operands[1].imm & (1 << inst.operands[0].reg))
6869 && inst.operands[0].writeback)
6870 as_warn (_("base register should not be in register list "
6871 "when written back"));
6872 }
6873 if (inst.instruction < 0xffff)
6874 inst.instruction = THUMB_OP32 (inst.instruction);
6875 inst.instruction |= inst.operands[0].reg << 16;
6876 inst.instruction |= inst.operands[1].imm;
6877 if (inst.operands[0].writeback)
6878 inst.instruction |= WRITE_BACK;
6879 }
6880 }
6881 else
6882 {
6883 constraint (inst.operands[0].reg > 7
6884 || (inst.operands[1].imm & ~0xff), BAD_HIREG);
6885 if (inst.instruction == T_MNEM_stmia)
6886 {
6887 if (!inst.operands[0].writeback)
6888 as_warn (_("this instruction will write back the base register"));
6889 if ((inst.operands[1].imm & (1 << inst.operands[0].reg))
6890 && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1)))
6891 as_warn (_("value stored for r%d is UNPREDICTABLE"),
6892 inst.operands[0].reg);
6893 }
6894 else
6895 {
6896 if (!inst.operands[0].writeback
6897 && !(inst.operands[1].imm & (1 << inst.operands[0].reg)))
6898 as_warn (_("this instruction will write back the base register"));
6899 else if (inst.operands[0].writeback
6900 && (inst.operands[1].imm & (1 << inst.operands[0].reg)))
6901 as_warn (_("this instruction will not write back the base register"));
6902 }
6903
6904 inst.instruction = THUMB_OP16 (inst.instruction);
6905 inst.instruction |= inst.operands[0].reg << 8;
6906 inst.instruction |= inst.operands[1].imm;
6907 }
6908 }
6909
6910 static void
6911 do_t_ldrex (void)
6912 {
6913 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
6914 || inst.operands[1].postind || inst.operands[1].writeback
6915 || inst.operands[1].immisreg || inst.operands[1].shifted
6916 || inst.operands[1].negative,
6917 BAD_ADDR_MODE);
6918
6919 inst.instruction |= inst.operands[0].reg << 12;
6920 inst.instruction |= inst.operands[1].reg << 16;
6921 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8;
6922 }
6923
6924 static void
6925 do_t_ldrexd (void)
6926 {
6927 if (!inst.operands[1].present)
6928 {
6929 constraint (inst.operands[0].reg == REG_LR,
6930 _("r14 not allowed as first register "
6931 "when second register is omitted"));
6932 inst.operands[1].reg = inst.operands[0].reg + 1;
6933 }
6934 constraint (inst.operands[0].reg == inst.operands[1].reg,
6935 BAD_OVERLAP);
6936
6937 inst.instruction |= inst.operands[0].reg << 12;
6938 inst.instruction |= inst.operands[1].reg << 8;
6939 inst.instruction |= inst.operands[2].reg << 16;
6940 }
6941
6942 static void
6943 do_t_ldst (void)
6944 {
6945 unsigned long opcode;
6946 int Rn;
6947
6948 opcode = inst.instruction;
6949 if (unified_syntax)
6950 {
6951 if (inst.operands[1].isreg
6952 && !inst.operands[1].writeback
6953 && !inst.operands[1].shifted && !inst.operands[1].postind
6954 && !inst.operands[1].negative && inst.operands[0].reg <= 7
6955 && opcode <= 0xffff
6956 && inst.size_req != 4)
6957 {
6958 /* Insn may have a 16-bit form. */
6959 Rn = inst.operands[1].reg;
6960 if (inst.operands[1].immisreg)
6961 {
6962 inst.instruction = THUMB_OP16 (opcode);
6963 /* [Rn, Ri] */
6964 if (Rn <= 7 && inst.operands[1].imm <= 7)
6965 goto op16;
6966 }
6967 else if ((Rn <= 7 && opcode != T_MNEM_ldrsh
6968 && opcode != T_MNEM_ldrsb)
6969 || ((Rn == REG_PC || Rn == REG_SP) && opcode == T_MNEM_ldr)
6970 || (Rn == REG_SP && opcode == T_MNEM_str))
6971 {
6972 /* [Rn, #const] */
6973 if (Rn > 7)
6974 {
6975 if (Rn == REG_PC)
6976 {
6977 if (inst.reloc.pc_rel)
6978 opcode = T_MNEM_ldr_pc2;
6979 else
6980 opcode = T_MNEM_ldr_pc;
6981 }
6982 else
6983 {
6984 if (opcode == T_MNEM_ldr)
6985 opcode = T_MNEM_ldr_sp;
6986 else
6987 opcode = T_MNEM_str_sp;
6988 }
6989 inst.instruction = inst.operands[0].reg << 8;
6990 }
6991 else
6992 {
6993 inst.instruction = inst.operands[0].reg;
6994 inst.instruction |= inst.operands[1].reg << 3;
6995 }
6996 inst.instruction |= THUMB_OP16 (opcode);
6997 if (inst.size_req == 2)
6998 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
6999 else
7000 inst.relax = opcode;
7001 return;
7002 }
7003 }
7004 /* Definitely a 32-bit variant. */
7005 inst.instruction = THUMB_OP32 (opcode);
7006 inst.instruction |= inst.operands[0].reg << 12;
7007 encode_thumb32_addr_mode (1, /*is_t=*/FALSE, /*is_d=*/FALSE);
7008 return;
7009 }
7010
7011 constraint (inst.operands[0].reg > 7, BAD_HIREG);
7012
7013 if (inst.instruction == T_MNEM_ldrsh || inst.instruction == T_MNEM_ldrsb)
7014 {
7015 /* Only [Rn,Rm] is acceptable. */
7016 constraint (inst.operands[1].reg > 7 || inst.operands[1].imm > 7, BAD_HIREG);
7017 constraint (!inst.operands[1].isreg || !inst.operands[1].immisreg
7018 || inst.operands[1].postind || inst.operands[1].shifted
7019 || inst.operands[1].negative,
7020 _("Thumb does not support this addressing mode"));
7021 inst.instruction = THUMB_OP16 (inst.instruction);
7022 goto op16;
7023 }
7024
7025 inst.instruction = THUMB_OP16 (inst.instruction);
7026 if (!inst.operands[1].isreg)
7027 if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE))
7028 return;
7029
7030 constraint (!inst.operands[1].preind
7031 || inst.operands[1].shifted
7032 || inst.operands[1].writeback,
7033 _("Thumb does not support this addressing mode"));
7034 if (inst.operands[1].reg == REG_PC || inst.operands[1].reg == REG_SP)
7035 {
7036 constraint (inst.instruction & 0x0600,
7037 _("byte or halfword not valid for base register"));
7038 constraint (inst.operands[1].reg == REG_PC
7039 && !(inst.instruction & THUMB_LOAD_BIT),
7040 _("r15 based store not allowed"));
7041 constraint (inst.operands[1].immisreg,
7042 _("invalid base register for register offset"));
7043
7044 if (inst.operands[1].reg == REG_PC)
7045 inst.instruction = T_OPCODE_LDR_PC;
7046 else if (inst.instruction & THUMB_LOAD_BIT)
7047 inst.instruction = T_OPCODE_LDR_SP;
7048 else
7049 inst.instruction = T_OPCODE_STR_SP;
7050
7051 inst.instruction |= inst.operands[0].reg << 8;
7052 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
7053 return;
7054 }
7055
7056 constraint (inst.operands[1].reg > 7, BAD_HIREG);
7057 if (!inst.operands[1].immisreg)
7058 {
7059 /* Immediate offset. */
7060 inst.instruction |= inst.operands[0].reg;
7061 inst.instruction |= inst.operands[1].reg << 3;
7062 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
7063 return;
7064 }
7065
7066 /* Register offset. */
7067 constraint (inst.operands[1].imm > 7, BAD_HIREG);
7068 constraint (inst.operands[1].negative,
7069 _("Thumb does not support this addressing mode"));
7070
7071 op16:
7072 switch (inst.instruction)
7073 {
7074 case T_OPCODE_STR_IW: inst.instruction = T_OPCODE_STR_RW; break;
7075 case T_OPCODE_STR_IH: inst.instruction = T_OPCODE_STR_RH; break;
7076 case T_OPCODE_STR_IB: inst.instruction = T_OPCODE_STR_RB; break;
7077 case T_OPCODE_LDR_IW: inst.instruction = T_OPCODE_LDR_RW; break;
7078 case T_OPCODE_LDR_IH: inst.instruction = T_OPCODE_LDR_RH; break;
7079 case T_OPCODE_LDR_IB: inst.instruction = T_OPCODE_LDR_RB; break;
7080 case 0x5600 /* ldrsb */:
7081 case 0x5e00 /* ldrsh */: break;
7082 default: abort ();
7083 }
7084
7085 inst.instruction |= inst.operands[0].reg;
7086 inst.instruction |= inst.operands[1].reg << 3;
7087 inst.instruction |= inst.operands[1].imm << 6;
7088 }
7089
7090 static void
7091 do_t_ldstd (void)
7092 {
7093 if (!inst.operands[1].present)
7094 {
7095 inst.operands[1].reg = inst.operands[0].reg + 1;
7096 constraint (inst.operands[0].reg == REG_LR,
7097 _("r14 not allowed here"));
7098 }
7099 inst.instruction |= inst.operands[0].reg << 12;
7100 inst.instruction |= inst.operands[1].reg << 8;
7101 encode_thumb32_addr_mode (2, /*is_t=*/FALSE, /*is_d=*/TRUE);
7102
7103 }
7104
7105 static void
7106 do_t_ldstt (void)
7107 {
7108 inst.instruction |= inst.operands[0].reg << 12;
7109 encode_thumb32_addr_mode (1, /*is_t=*/TRUE, /*is_d=*/FALSE);
7110 }
7111
7112 static void
7113 do_t_mla (void)
7114 {
7115 inst.instruction |= inst.operands[0].reg << 8;
7116 inst.instruction |= inst.operands[1].reg << 16;
7117 inst.instruction |= inst.operands[2].reg;
7118 inst.instruction |= inst.operands[3].reg << 12;
7119 }
7120
7121 static void
7122 do_t_mlal (void)
7123 {
7124 inst.instruction |= inst.operands[0].reg << 12;
7125 inst.instruction |= inst.operands[1].reg << 8;
7126 inst.instruction |= inst.operands[2].reg << 16;
7127 inst.instruction |= inst.operands[3].reg;
7128 }
7129
7130 static void
7131 do_t_mov_cmp (void)
7132 {
7133 if (unified_syntax)
7134 {
7135 int r0off = (inst.instruction == T_MNEM_mov
7136 || inst.instruction == T_MNEM_movs) ? 8 : 16;
7137 unsigned long opcode;
7138 bfd_boolean narrow;
7139 bfd_boolean low_regs;
7140
7141 low_regs = (inst.operands[0].reg <= 7 && inst.operands[1].reg <= 7);
7142 opcode = inst.instruction;
7143 if (current_it_mask)
7144 narrow = opcode != T_MNEM_movs;
7145 else
7146 narrow = opcode != T_MNEM_movs || low_regs;
7147 if (inst.size_req == 4
7148 || inst.operands[1].shifted)
7149 narrow = FALSE;
7150
7151 if (!inst.operands[1].isreg)
7152 {
7153 /* Immediate operand. */
7154 if (current_it_mask == 0 && opcode == T_MNEM_mov)
7155 narrow = 0;
7156 if (low_regs && narrow)
7157 {
7158 inst.instruction = THUMB_OP16 (opcode);
7159 inst.instruction |= inst.operands[0].reg << 8;
7160 if (inst.size_req == 2)
7161 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
7162 else
7163 inst.relax = opcode;
7164 }
7165 else
7166 {
7167 inst.instruction = THUMB_OP32 (inst.instruction);
7168 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
7169 inst.instruction |= inst.operands[0].reg << r0off;
7170 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
7171 }
7172 }
7173 else if (!narrow)
7174 {
7175 inst.instruction = THUMB_OP32 (inst.instruction);
7176 inst.instruction |= inst.operands[0].reg << r0off;
7177 encode_thumb32_shifted_operand (1);
7178 }
7179 else
7180 switch (inst.instruction)
7181 {
7182 case T_MNEM_mov:
7183 inst.instruction = T_OPCODE_MOV_HR;
7184 inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
7185 inst.instruction |= (inst.operands[0].reg & 0x7);
7186 inst.instruction |= inst.operands[1].reg << 3;
7187 break;
7188
7189 case T_MNEM_movs:
7190 /* We know we have low registers at this point.
7191 Generate ADD Rd, Rs, #0. */
7192 inst.instruction = T_OPCODE_ADD_I3;
7193 inst.instruction |= inst.operands[0].reg;
7194 inst.instruction |= inst.operands[1].reg << 3;
7195 break;
7196
7197 case T_MNEM_cmp:
7198 if (low_regs)
7199 {
7200 inst.instruction = T_OPCODE_CMP_LR;
7201 inst.instruction |= inst.operands[0].reg;
7202 inst.instruction |= inst.operands[1].reg << 3;
7203 }
7204 else
7205 {
7206 inst.instruction = T_OPCODE_CMP_HR;
7207 inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
7208 inst.instruction |= (inst.operands[0].reg & 0x7);
7209 inst.instruction |= inst.operands[1].reg << 3;
7210 }
7211 break;
7212 }
7213 return;
7214 }
7215
7216 inst.instruction = THUMB_OP16 (inst.instruction);
7217 if (inst.operands[1].isreg)
7218 {
7219 if (inst.operands[0].reg < 8 && inst.operands[1].reg < 8)
7220 {
7221 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
7222 since a MOV instruction produces unpredictable results. */
7223 if (inst.instruction == T_OPCODE_MOV_I8)
7224 inst.instruction = T_OPCODE_ADD_I3;
7225 else
7226 inst.instruction = T_OPCODE_CMP_LR;
7227
7228 inst.instruction |= inst.operands[0].reg;
7229 inst.instruction |= inst.operands[1].reg << 3;
7230 }
7231 else
7232 {
7233 if (inst.instruction == T_OPCODE_MOV_I8)
7234 inst.instruction = T_OPCODE_MOV_HR;
7235 else
7236 inst.instruction = T_OPCODE_CMP_HR;
7237 do_t_cpy ();
7238 }
7239 }
7240 else
7241 {
7242 constraint (inst.operands[0].reg > 7,
7243 _("only lo regs allowed with immediate"));
7244 inst.instruction |= inst.operands[0].reg << 8;
7245 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
7246 }
7247 }
7248
7249 static void
7250 do_t_mov16 (void)
7251 {
7252 inst.instruction |= inst.operands[0].reg << 8;
7253 inst.instruction |= (inst.operands[1].imm & 0xf000) << 4;
7254 inst.instruction |= (inst.operands[1].imm & 0x0800) << 15;
7255 inst.instruction |= (inst.operands[1].imm & 0x0700) << 4;
7256 inst.instruction |= (inst.operands[1].imm & 0x00ff);
7257 }
7258
7259 static void
7260 do_t_mvn_tst (void)
7261 {
7262 if (unified_syntax)
7263 {
7264 int r0off = (inst.instruction == T_MNEM_mvn
7265 || inst.instruction == T_MNEM_mvns) ? 8 : 16;
7266 bfd_boolean narrow;
7267
7268 if (inst.size_req == 4
7269 || inst.instruction > 0xffff
7270 || inst.operands[1].shifted
7271 || inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
7272 narrow = FALSE;
7273 else if (inst.instruction == T_MNEM_cmn)
7274 narrow = TRUE;
7275 else if (THUMB_SETS_FLAGS (inst.instruction))
7276 narrow = (current_it_mask == 0);
7277 else
7278 narrow = (current_it_mask != 0);
7279
7280 if (!inst.operands[1].isreg)
7281 {
7282 /* For an immediate, we always generate a 32-bit opcode;
7283 section relaxation will shrink it later if possible. */
7284 if (inst.instruction < 0xffff)
7285 inst.instruction = THUMB_OP32 (inst.instruction);
7286 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
7287 inst.instruction |= inst.operands[0].reg << r0off;
7288 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
7289 }
7290 else
7291 {
7292 /* See if we can do this with a 16-bit instruction. */
7293 if (narrow)
7294 {
7295 inst.instruction = THUMB_OP16 (inst.instruction);
7296 inst.instruction |= inst.operands[0].reg;
7297 inst.instruction |= inst.operands[1].reg << 3;
7298 }
7299 else
7300 {
7301 constraint (inst.operands[1].shifted
7302 && inst.operands[1].immisreg,
7303 _("shift must be constant"));
7304 if (inst.instruction < 0xffff)
7305 inst.instruction = THUMB_OP32 (inst.instruction);
7306 inst.instruction |= inst.operands[0].reg << r0off;
7307 encode_thumb32_shifted_operand (1);
7308 }
7309 }
7310 }
7311 else
7312 {
7313 constraint (inst.instruction > 0xffff
7314 || inst.instruction == T_MNEM_mvns, BAD_THUMB32);
7315 constraint (!inst.operands[1].isreg || inst.operands[1].shifted,
7316 _("unshifted register required"));
7317 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7,
7318 BAD_HIREG);
7319
7320 inst.instruction = THUMB_OP16 (inst.instruction);
7321 inst.instruction |= inst.operands[0].reg;
7322 inst.instruction |= inst.operands[1].reg << 3;
7323 }
7324 }
7325
7326 static void
7327 do_t_mrs (void)
7328 {
7329 int flags;
7330 flags = inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
7331 if (flags == 0)
7332 {
7333 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7m),
7334 _("selected processor does not support "
7335 "requested special purpose register"));
7336 }
7337 else
7338 {
7339 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1),
7340 _("selected processor does not support "
7341 "requested special purpose register %x"));
7342 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
7343 constraint ((flags & ~SPSR_BIT) != (PSR_c|PSR_f),
7344 _("'CPSR' or 'SPSR' expected"));
7345 }
7346
7347 inst.instruction |= inst.operands[0].reg << 8;
7348 inst.instruction |= (flags & SPSR_BIT) >> 2;
7349 inst.instruction |= inst.operands[1].imm & 0xff;
7350 }
7351
7352 static void
7353 do_t_msr (void)
7354 {
7355 int flags;
7356
7357 constraint (!inst.operands[1].isreg,
7358 _("Thumb encoding does not support an immediate here"));
7359 flags = inst.operands[0].imm;
7360 if (flags & ~0xff)
7361 {
7362 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1),
7363 _("selected processor does not support "
7364 "requested special purpose register"));
7365 }
7366 else
7367 {
7368 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7m),
7369 _("selected processor does not support "
7370 "requested special purpose register"));
7371 flags |= PSR_f;
7372 }
7373 inst.instruction |= (flags & SPSR_BIT) >> 2;
7374 inst.instruction |= (flags & ~SPSR_BIT) >> 8;
7375 inst.instruction |= (flags & 0xff);
7376 inst.instruction |= inst.operands[1].reg << 16;
7377 }
7378
7379 static void
7380 do_t_mul (void)
7381 {
7382 if (!inst.operands[2].present)
7383 inst.operands[2].reg = inst.operands[0].reg;
7384
7385 /* There is no 32-bit MULS and no 16-bit MUL. */
7386 if (unified_syntax && inst.instruction == T_MNEM_mul)
7387 {
7388 inst.instruction = THUMB_OP32 (inst.instruction);
7389 inst.instruction |= inst.operands[0].reg << 8;
7390 inst.instruction |= inst.operands[1].reg << 16;
7391 inst.instruction |= inst.operands[2].reg << 0;
7392 }
7393 else
7394 {
7395 constraint (!unified_syntax
7396 && inst.instruction == T_MNEM_muls, BAD_THUMB32);
7397 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7,
7398 BAD_HIREG);
7399
7400 inst.instruction = THUMB_OP16 (inst.instruction);
7401 inst.instruction |= inst.operands[0].reg;
7402
7403 if (inst.operands[0].reg == inst.operands[1].reg)
7404 inst.instruction |= inst.operands[2].reg << 3;
7405 else if (inst.operands[0].reg == inst.operands[2].reg)
7406 inst.instruction |= inst.operands[1].reg << 3;
7407 else
7408 constraint (1, _("dest must overlap one source register"));
7409 }
7410 }
7411
7412 static void
7413 do_t_mull (void)
7414 {
7415 inst.instruction |= inst.operands[0].reg << 12;
7416 inst.instruction |= inst.operands[1].reg << 8;
7417 inst.instruction |= inst.operands[2].reg << 16;
7418 inst.instruction |= inst.operands[3].reg;
7419
7420 if (inst.operands[0].reg == inst.operands[1].reg)
7421 as_tsktsk (_("rdhi and rdlo must be different"));
7422 }
7423
7424 static void
7425 do_t_nop (void)
7426 {
7427 if (unified_syntax)
7428 {
7429 if (inst.size_req == 4 || inst.operands[0].imm > 15)
7430 {
7431 inst.instruction = THUMB_OP32 (inst.instruction);
7432 inst.instruction |= inst.operands[0].imm;
7433 }
7434 else
7435 {
7436 inst.instruction = THUMB_OP16 (inst.instruction);
7437 inst.instruction |= inst.operands[0].imm << 4;
7438 }
7439 }
7440 else
7441 {
7442 constraint (inst.operands[0].present,
7443 _("Thumb does not support NOP with hints"));
7444 inst.instruction = 0x46c0;
7445 }
7446 }
7447
7448 static void
7449 do_t_neg (void)
7450 {
7451 if (unified_syntax)
7452 {
7453 bfd_boolean narrow;
7454
7455 if (THUMB_SETS_FLAGS (inst.instruction))
7456 narrow = (current_it_mask == 0);
7457 else
7458 narrow = (current_it_mask != 0);
7459 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
7460 narrow = FALSE;
7461 if (inst.size_req == 4)
7462 narrow = FALSE;
7463
7464 if (!narrow)
7465 {
7466 inst.instruction = THUMB_OP32 (inst.instruction);
7467 inst.instruction |= inst.operands[0].reg << 8;
7468 inst.instruction |= inst.operands[1].reg << 16;
7469 }
7470 else
7471 {
7472 inst.instruction = THUMB_OP16 (inst.instruction);
7473 inst.instruction |= inst.operands[0].reg;
7474 inst.instruction |= inst.operands[1].reg << 3;
7475 }
7476 }
7477 else
7478 {
7479 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7,
7480 BAD_HIREG);
7481 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
7482
7483 inst.instruction = THUMB_OP16 (inst.instruction);
7484 inst.instruction |= inst.operands[0].reg;
7485 inst.instruction |= inst.operands[1].reg << 3;
7486 }
7487 }
7488
7489 static void
7490 do_t_pkhbt (void)
7491 {
7492 inst.instruction |= inst.operands[0].reg << 8;
7493 inst.instruction |= inst.operands[1].reg << 16;
7494 inst.instruction |= inst.operands[2].reg;
7495 if (inst.operands[3].present)
7496 {
7497 unsigned int val = inst.reloc.exp.X_add_number;
7498 constraint (inst.reloc.exp.X_op != O_constant,
7499 _("expression too complex"));
7500 inst.instruction |= (val & 0x1c) << 10;
7501 inst.instruction |= (val & 0x03) << 6;
7502 }
7503 }
7504
7505 static void
7506 do_t_pkhtb (void)
7507 {
7508 if (!inst.operands[3].present)
7509 inst.instruction &= ~0x00000020;
7510 do_t_pkhbt ();
7511 }
7512
7513 static void
7514 do_t_pld (void)
7515 {
7516 encode_thumb32_addr_mode (0, /*is_t=*/FALSE, /*is_d=*/FALSE);
7517 }
7518
7519 static void
7520 do_t_push_pop (void)
7521 {
7522 unsigned mask;
7523
7524 constraint (inst.operands[0].writeback,
7525 _("push/pop do not support {reglist}^"));
7526 constraint (inst.reloc.type != BFD_RELOC_UNUSED,
7527 _("expression too complex"));
7528
7529 mask = inst.operands[0].imm;
7530 if ((mask & ~0xff) == 0)
7531 inst.instruction = THUMB_OP16 (inst.instruction);
7532 else if ((inst.instruction == T_MNEM_push
7533 && (mask & ~0xff) == 1 << REG_LR)
7534 || (inst.instruction == T_MNEM_pop
7535 && (mask & ~0xff) == 1 << REG_PC))
7536 {
7537 inst.instruction = THUMB_OP16 (inst.instruction);
7538 inst.instruction |= THUMB_PP_PC_LR;
7539 mask &= 0xff;
7540 }
7541 else if (unified_syntax)
7542 {
7543 if (mask & (1 << 13))
7544 inst.error = _("SP not allowed in register list");
7545 if (inst.instruction == T_MNEM_push)
7546 {
7547 if (mask & (1 << 15))
7548 inst.error = _("PC not allowed in register list");
7549 }
7550 else
7551 {
7552 if (mask & (1 << 14)
7553 && mask & (1 << 15))
7554 inst.error = _("LR and PC should not both be in register list");
7555 }
7556 if ((mask & (mask - 1)) == 0)
7557 {
7558 /* Single register push/pop implemented as str/ldr. */
7559 if (inst.instruction == T_MNEM_push)
7560 inst.instruction = 0xf84d0d04; /* str reg, [sp, #-4]! */
7561 else
7562 inst.instruction = 0xf85d0b04; /* ldr reg, [sp], #4 */
7563 mask = ffs(mask) - 1;
7564 mask <<= 12;
7565 }
7566 else
7567 inst.instruction = THUMB_OP32 (inst.instruction);
7568 }
7569 else
7570 {
7571 inst.error = _("invalid register list to push/pop instruction");
7572 return;
7573 }
7574
7575 inst.instruction |= mask;
7576 }
7577
7578 static void
7579 do_t_rbit (void)
7580 {
7581 inst.instruction |= inst.operands[0].reg << 8;
7582 inst.instruction |= inst.operands[1].reg << 16;
7583 }
7584
7585 static void
7586 do_t_rev (void)
7587 {
7588 if (inst.operands[0].reg <= 7 && inst.operands[1].reg <= 7
7589 && inst.size_req != 4)
7590 {
7591 inst.instruction = THUMB_OP16 (inst.instruction);
7592 inst.instruction |= inst.operands[0].reg;
7593 inst.instruction |= inst.operands[1].reg << 3;
7594 }
7595 else if (unified_syntax)
7596 {
7597 inst.instruction = THUMB_OP32 (inst.instruction);
7598 inst.instruction |= inst.operands[0].reg << 8;
7599 inst.instruction |= inst.operands[1].reg << 16;
7600 inst.instruction |= inst.operands[1].reg;
7601 }
7602 else
7603 inst.error = BAD_HIREG;
7604 }
7605
7606 static void
7607 do_t_rsb (void)
7608 {
7609 int Rd, Rs;
7610
7611 Rd = inst.operands[0].reg;
7612 Rs = (inst.operands[1].present
7613 ? inst.operands[1].reg /* Rd, Rs, foo */
7614 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
7615
7616 inst.instruction |= Rd << 8;
7617 inst.instruction |= Rs << 16;
7618 if (!inst.operands[2].isreg)
7619 {
7620 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
7621 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
7622 }
7623 else
7624 encode_thumb32_shifted_operand (2);
7625 }
7626
7627 static void
7628 do_t_setend (void)
7629 {
7630 if (inst.operands[0].imm)
7631 inst.instruction |= 0x8;
7632 }
7633
7634 static void
7635 do_t_shift (void)
7636 {
7637 if (!inst.operands[1].present)
7638 inst.operands[1].reg = inst.operands[0].reg;
7639
7640 if (unified_syntax)
7641 {
7642 bfd_boolean narrow;
7643 int shift_kind;
7644
7645 switch (inst.instruction)
7646 {
7647 case T_MNEM_asr:
7648 case T_MNEM_asrs: shift_kind = SHIFT_ASR; break;
7649 case T_MNEM_lsl:
7650 case T_MNEM_lsls: shift_kind = SHIFT_LSL; break;
7651 case T_MNEM_lsr:
7652 case T_MNEM_lsrs: shift_kind = SHIFT_LSR; break;
7653 case T_MNEM_ror:
7654 case T_MNEM_rors: shift_kind = SHIFT_ROR; break;
7655 default: abort ();
7656 }
7657
7658 if (THUMB_SETS_FLAGS (inst.instruction))
7659 narrow = (current_it_mask == 0);
7660 else
7661 narrow = (current_it_mask != 0);
7662 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
7663 narrow = FALSE;
7664 if (!inst.operands[2].isreg && shift_kind == SHIFT_ROR)
7665 narrow = FALSE;
7666 if (inst.operands[2].isreg
7667 && (inst.operands[1].reg != inst.operands[0].reg
7668 || inst.operands[2].reg > 7))
7669 narrow = FALSE;
7670 if (inst.size_req == 4)
7671 narrow = FALSE;
7672
7673 if (!narrow)
7674 {
7675 if (inst.operands[2].isreg)
7676 {
7677 inst.instruction = THUMB_OP32 (inst.instruction);
7678 inst.instruction |= inst.operands[0].reg << 8;
7679 inst.instruction |= inst.operands[1].reg << 16;
7680 inst.instruction |= inst.operands[2].reg;
7681 }
7682 else
7683 {
7684 inst.operands[1].shifted = 1;
7685 inst.operands[1].shift_kind = shift_kind;
7686 inst.instruction = THUMB_OP32 (THUMB_SETS_FLAGS (inst.instruction)
7687 ? T_MNEM_movs : T_MNEM_mov);
7688 inst.instruction |= inst.operands[0].reg << 8;
7689 encode_thumb32_shifted_operand (1);
7690 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
7691 inst.reloc.type = BFD_RELOC_UNUSED;
7692 }
7693 }
7694 else
7695 {
7696 if (inst.operands[2].isreg)
7697 {
7698 switch (shift_kind)
7699 {
7700 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_R; break;
7701 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_R; break;
7702 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_R; break;
7703 case SHIFT_ROR: inst.instruction = T_OPCODE_ROR_R; break;
7704 default: abort ();
7705 }
7706
7707 inst.instruction |= inst.operands[0].reg;
7708 inst.instruction |= inst.operands[2].reg << 3;
7709 }
7710 else
7711 {
7712 switch (shift_kind)
7713 {
7714 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
7715 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
7716 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
7717 default: abort ();
7718 }
7719 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
7720 inst.instruction |= inst.operands[0].reg;
7721 inst.instruction |= inst.operands[1].reg << 3;
7722 }
7723 }
7724 }
7725 else
7726 {
7727 constraint (inst.operands[0].reg > 7
7728 || inst.operands[1].reg > 7, BAD_HIREG);
7729 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
7730
7731 if (inst.operands[2].isreg) /* Rd, {Rs,} Rn */
7732 {
7733 constraint (inst.operands[2].reg > 7, BAD_HIREG);
7734 constraint (inst.operands[0].reg != inst.operands[1].reg,
7735 _("source1 and dest must be same register"));
7736
7737 switch (inst.instruction)
7738 {
7739 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_R; break;
7740 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_R; break;
7741 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_R; break;
7742 case T_MNEM_ror: inst.instruction = T_OPCODE_ROR_R; break;
7743 default: abort ();
7744 }
7745
7746 inst.instruction |= inst.operands[0].reg;
7747 inst.instruction |= inst.operands[2].reg << 3;
7748 }
7749 else
7750 {
7751 switch (inst.instruction)
7752 {
7753 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_I; break;
7754 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_I; break;
7755 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_I; break;
7756 case T_MNEM_ror: inst.error = _("ror #imm not supported"); return;
7757 default: abort ();
7758 }
7759 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
7760 inst.instruction |= inst.operands[0].reg;
7761 inst.instruction |= inst.operands[1].reg << 3;
7762 }
7763 }
7764 }
7765
7766 static void
7767 do_t_simd (void)
7768 {
7769 inst.instruction |= inst.operands[0].reg << 8;
7770 inst.instruction |= inst.operands[1].reg << 16;
7771 inst.instruction |= inst.operands[2].reg;
7772 }
7773
7774 static void
7775 do_t_smc (void)
7776 {
7777 unsigned int value = inst.reloc.exp.X_add_number;
7778 constraint (inst.reloc.exp.X_op != O_constant,
7779 _("expression too complex"));
7780 inst.reloc.type = BFD_RELOC_UNUSED;
7781 inst.instruction |= (value & 0xf000) >> 12;
7782 inst.instruction |= (value & 0x0ff0);
7783 inst.instruction |= (value & 0x000f) << 16;
7784 }
7785
7786 static void
7787 do_t_ssat (void)
7788 {
7789 inst.instruction |= inst.operands[0].reg << 8;
7790 inst.instruction |= inst.operands[1].imm - 1;
7791 inst.instruction |= inst.operands[2].reg << 16;
7792
7793 if (inst.operands[3].present)
7794 {
7795 constraint (inst.reloc.exp.X_op != O_constant,
7796 _("expression too complex"));
7797
7798 if (inst.reloc.exp.X_add_number != 0)
7799 {
7800 if (inst.operands[3].shift_kind == SHIFT_ASR)
7801 inst.instruction |= 0x00200000; /* sh bit */
7802 inst.instruction |= (inst.reloc.exp.X_add_number & 0x1c) << 10;
7803 inst.instruction |= (inst.reloc.exp.X_add_number & 0x03) << 6;
7804 }
7805 inst.reloc.type = BFD_RELOC_UNUSED;
7806 }
7807 }
7808
7809 static void
7810 do_t_ssat16 (void)
7811 {
7812 inst.instruction |= inst.operands[0].reg << 8;
7813 inst.instruction |= inst.operands[1].imm - 1;
7814 inst.instruction |= inst.operands[2].reg << 16;
7815 }
7816
7817 static void
7818 do_t_strex (void)
7819 {
7820 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
7821 || inst.operands[2].postind || inst.operands[2].writeback
7822 || inst.operands[2].immisreg || inst.operands[2].shifted
7823 || inst.operands[2].negative,
7824 BAD_ADDR_MODE);
7825
7826 inst.instruction |= inst.operands[0].reg << 8;
7827 inst.instruction |= inst.operands[1].reg << 12;
7828 inst.instruction |= inst.operands[2].reg << 16;
7829 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8;
7830 }
7831
7832 static void
7833 do_t_strexd (void)
7834 {
7835 if (!inst.operands[2].present)
7836 inst.operands[2].reg = inst.operands[1].reg + 1;
7837
7838 constraint (inst.operands[0].reg == inst.operands[1].reg
7839 || inst.operands[0].reg == inst.operands[2].reg
7840 || inst.operands[0].reg == inst.operands[3].reg
7841 || inst.operands[1].reg == inst.operands[2].reg,
7842 BAD_OVERLAP);
7843
7844 inst.instruction |= inst.operands[0].reg;
7845 inst.instruction |= inst.operands[1].reg << 12;
7846 inst.instruction |= inst.operands[2].reg << 8;
7847 inst.instruction |= inst.operands[3].reg << 16;
7848 }
7849
7850 static void
7851 do_t_sxtah (void)
7852 {
7853 inst.instruction |= inst.operands[0].reg << 8;
7854 inst.instruction |= inst.operands[1].reg << 16;
7855 inst.instruction |= inst.operands[2].reg;
7856 inst.instruction |= inst.operands[3].imm << 4;
7857 }
7858
7859 static void
7860 do_t_sxth (void)
7861 {
7862 if (inst.instruction <= 0xffff && inst.size_req != 4
7863 && inst.operands[0].reg <= 7 && inst.operands[1].reg <= 7
7864 && (!inst.operands[2].present || inst.operands[2].imm == 0))
7865 {
7866 inst.instruction = THUMB_OP16 (inst.instruction);
7867 inst.instruction |= inst.operands[0].reg;
7868 inst.instruction |= inst.operands[1].reg << 3;
7869 }
7870 else if (unified_syntax)
7871 {
7872 if (inst.instruction <= 0xffff)
7873 inst.instruction = THUMB_OP32 (inst.instruction);
7874 inst.instruction |= inst.operands[0].reg << 8;
7875 inst.instruction |= inst.operands[1].reg;
7876 inst.instruction |= inst.operands[2].imm << 4;
7877 }
7878 else
7879 {
7880 constraint (inst.operands[2].present && inst.operands[2].imm != 0,
7881 _("Thumb encoding does not support rotation"));
7882 constraint (1, BAD_HIREG);
7883 }
7884 }
7885
7886 static void
7887 do_t_swi (void)
7888 {
7889 inst.reloc.type = BFD_RELOC_ARM_SWI;
7890 }
7891
7892 static void
7893 do_t_tb (void)
7894 {
7895 int half;
7896
7897 half = (inst.instruction & 0x10) != 0;
7898 constraint (inst.operands[0].imm == 15,
7899 _("PC is not a valid index register"));
7900 constraint (!half && inst.operands[0].shifted,
7901 _("instruction does not allow shifted index"));
7902 constraint (half && !inst.operands[0].shifted,
7903 _("instruction requires shifted index"));
7904 inst.instruction |= (inst.operands[0].reg << 16) | inst.operands[0].imm;
7905 }
7906
7907 static void
7908 do_t_usat (void)
7909 {
7910 inst.instruction |= inst.operands[0].reg << 8;
7911 inst.instruction |= inst.operands[1].imm;
7912 inst.instruction |= inst.operands[2].reg << 16;
7913
7914 if (inst.operands[3].present)
7915 {
7916 constraint (inst.reloc.exp.X_op != O_constant,
7917 _("expression too complex"));
7918 if (inst.reloc.exp.X_add_number != 0)
7919 {
7920 if (inst.operands[3].shift_kind == SHIFT_ASR)
7921 inst.instruction |= 0x00200000; /* sh bit */
7922
7923 inst.instruction |= (inst.reloc.exp.X_add_number & 0x1c) << 10;
7924 inst.instruction |= (inst.reloc.exp.X_add_number & 0x03) << 6;
7925 }
7926 inst.reloc.type = BFD_RELOC_UNUSED;
7927 }
7928 }
7929
7930 static void
7931 do_t_usat16 (void)
7932 {
7933 inst.instruction |= inst.operands[0].reg << 8;
7934 inst.instruction |= inst.operands[1].imm;
7935 inst.instruction |= inst.operands[2].reg << 16;
7936 }
7937 \f
7938 /* Overall per-instruction processing. */
7939
7940 /* We need to be able to fix up arbitrary expressions in some statements.
7941 This is so that we can handle symbols that are an arbitrary distance from
7942 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
7943 which returns part of an address in a form which will be valid for
7944 a data instruction. We do this by pushing the expression into a symbol
7945 in the expr_section, and creating a fix for that. */
7946
7947 static void
7948 fix_new_arm (fragS * frag,
7949 int where,
7950 short int size,
7951 expressionS * exp,
7952 int pc_rel,
7953 int reloc)
7954 {
7955 fixS * new_fix;
7956
7957 switch (exp->X_op)
7958 {
7959 case O_constant:
7960 case O_symbol:
7961 case O_add:
7962 case O_subtract:
7963 new_fix = fix_new_exp (frag, where, size, exp, pc_rel, reloc);
7964 break;
7965
7966 default:
7967 new_fix = fix_new (frag, where, size, make_expr_symbol (exp), 0,
7968 pc_rel, reloc);
7969 break;
7970 }
7971
7972 /* Mark whether the fix is to a THUMB instruction, or an ARM
7973 instruction. */
7974 new_fix->tc_fix_data = thumb_mode;
7975 }
7976
7977 /* Create a frg for an instruction requiring relaxation. */
7978 static void
7979 output_relax_insn (void)
7980 {
7981 char * to;
7982 symbolS *sym;
7983 int offset;
7984
7985 switch (inst.reloc.exp.X_op)
7986 {
7987 case O_symbol:
7988 sym = inst.reloc.exp.X_add_symbol;
7989 offset = inst.reloc.exp.X_add_number;
7990 break;
7991 case O_constant:
7992 sym = NULL;
7993 offset = inst.reloc.exp.X_add_number;
7994 break;
7995 default:
7996 sym = make_expr_symbol (&inst.reloc.exp);
7997 offset = 0;
7998 break;
7999 }
8000 to = frag_var (rs_machine_dependent, INSN_SIZE, THUMB_SIZE,
8001 inst.relax, sym, offset, NULL/*offset, opcode*/);
8002 md_number_to_chars (to, inst.instruction, THUMB_SIZE);
8003
8004 #ifdef OBJ_ELF
8005 dwarf2_emit_insn (INSN_SIZE);
8006 #endif
8007 }
8008
8009 /* Write a 32-bit thumb instruction to buf. */
8010 static void
8011 put_thumb32_insn (char * buf, unsigned long insn)
8012 {
8013 md_number_to_chars (buf, insn >> 16, THUMB_SIZE);
8014 md_number_to_chars (buf + THUMB_SIZE, insn, THUMB_SIZE);
8015 }
8016
8017 static void
8018 output_inst (const char * str)
8019 {
8020 char * to = NULL;
8021
8022 if (inst.error)
8023 {
8024 as_bad ("%s -- `%s'", inst.error, str);
8025 return;
8026 }
8027 if (inst.relax) {
8028 output_relax_insn();
8029 return;
8030 }
8031 if (inst.size == 0)
8032 return;
8033
8034 to = frag_more (inst.size);
8035
8036 if (thumb_mode && (inst.size > THUMB_SIZE))
8037 {
8038 assert (inst.size == (2 * THUMB_SIZE));
8039 put_thumb32_insn (to, inst.instruction);
8040 }
8041 else if (inst.size > INSN_SIZE)
8042 {
8043 assert (inst.size == (2 * INSN_SIZE));
8044 md_number_to_chars (to, inst.instruction, INSN_SIZE);
8045 md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE);
8046 }
8047 else
8048 md_number_to_chars (to, inst.instruction, inst.size);
8049
8050 if (inst.reloc.type != BFD_RELOC_UNUSED)
8051 fix_new_arm (frag_now, to - frag_now->fr_literal,
8052 inst.size, & inst.reloc.exp, inst.reloc.pc_rel,
8053 inst.reloc.type);
8054
8055 #ifdef OBJ_ELF
8056 dwarf2_emit_insn (inst.size);
8057 #endif
8058 }
8059
8060 /* Tag values used in struct asm_opcode's tag field. */
8061 enum opcode_tag
8062 {
8063 OT_unconditional, /* Instruction cannot be conditionalized.
8064 The ARM condition field is still 0xE. */
8065 OT_unconditionalF, /* Instruction cannot be conditionalized
8066 and carries 0xF in its ARM condition field. */
8067 OT_csuffix, /* Instruction takes a conditional suffix. */
8068 OT_cinfix3, /* Instruction takes a conditional infix,
8069 beginning at character index 3. (In
8070 unified mode, it becomes a suffix.) */
8071 OT_cinfix3_legacy, /* Legacy instruction takes a conditional infix at
8072 character index 3, even in unified mode. Used for
8073 legacy instructions where suffix and infix forms
8074 may be ambiguous. */
8075 OT_csuf_or_in3, /* Instruction takes either a conditional
8076 suffix or an infix at character index 3. */
8077 OT_odd_infix_unc, /* This is the unconditional variant of an
8078 instruction that takes a conditional infix
8079 at an unusual position. In unified mode,
8080 this variant will accept a suffix. */
8081 OT_odd_infix_0 /* Values greater than or equal to OT_odd_infix_0
8082 are the conditional variants of instructions that
8083 take conditional infixes in unusual positions.
8084 The infix appears at character index
8085 (tag - OT_odd_infix_0). These are not accepted
8086 in unified mode. */
8087 };
8088
8089 /* Subroutine of md_assemble, responsible for looking up the primary
8090 opcode from the mnemonic the user wrote. STR points to the
8091 beginning of the mnemonic.
8092
8093 This is not simply a hash table lookup, because of conditional
8094 variants. Most instructions have conditional variants, which are
8095 expressed with a _conditional affix_ to the mnemonic. If we were
8096 to encode each conditional variant as a literal string in the opcode
8097 table, it would have approximately 20,000 entries.
8098
8099 Most mnemonics take this affix as a suffix, and in unified syntax,
8100 'most' is upgraded to 'all'. However, in the divided syntax, some
8101 instructions take the affix as an infix, notably the s-variants of
8102 the arithmetic instructions. Of those instructions, all but six
8103 have the infix appear after the third character of the mnemonic.
8104
8105 Accordingly, the algorithm for looking up primary opcodes given
8106 an identifier is:
8107
8108 1. Look up the identifier in the opcode table.
8109 If we find a match, go to step U.
8110
8111 2. Look up the last two characters of the identifier in the
8112 conditions table. If we find a match, look up the first N-2
8113 characters of the identifier in the opcode table. If we
8114 find a match, go to step CE.
8115
8116 3. Look up the fourth and fifth characters of the identifier in
8117 the conditions table. If we find a match, extract those
8118 characters from the identifier, and look up the remaining
8119 characters in the opcode table. If we find a match, go
8120 to step CM.
8121
8122 4. Fail.
8123
8124 U. Examine the tag field of the opcode structure, in case this is
8125 one of the six instructions with its conditional infix in an
8126 unusual place. If it is, the tag tells us where to find the
8127 infix; look it up in the conditions table and set inst.cond
8128 accordingly. Otherwise, this is an unconditional instruction.
8129 Again set inst.cond accordingly. Return the opcode structure.
8130
8131 CE. Examine the tag field to make sure this is an instruction that
8132 should receive a conditional suffix. If it is not, fail.
8133 Otherwise, set inst.cond from the suffix we already looked up,
8134 and return the opcode structure.
8135
8136 CM. Examine the tag field to make sure this is an instruction that
8137 should receive a conditional infix after the third character.
8138 If it is not, fail. Otherwise, undo the edits to the current
8139 line of input and proceed as for case CE. */
8140
8141 static const struct asm_opcode *
8142 opcode_lookup (char **str)
8143 {
8144 char *end, *base;
8145 char *affix;
8146 const struct asm_opcode *opcode;
8147 const struct asm_cond *cond;
8148 char save[2];
8149
8150 /* Scan up to the end of the mnemonic, which must end in white space,
8151 '.' (in unified mode only), or end of string. */
8152 for (base = end = *str; *end != '\0'; end++)
8153 if (*end == ' ' || (unified_syntax && *end == '.'))
8154 break;
8155
8156 if (end == base)
8157 return 0;
8158
8159 /* Handle a possible width suffix. */
8160 if (end[0] == '.')
8161 {
8162 if (end[1] == 'w' && (end[2] == ' ' || end[2] == '\0'))
8163 inst.size_req = 4;
8164 else if (end[1] == 'n' && (end[2] == ' ' || end[2] == '\0'))
8165 inst.size_req = 2;
8166 else
8167 return 0;
8168
8169 *str = end + 2;
8170 }
8171 else
8172 *str = end;
8173
8174 /* Look for unaffixed or special-case affixed mnemonic. */
8175 opcode = hash_find_n (arm_ops_hsh, base, end - base);
8176 if (opcode)
8177 {
8178 /* step U */
8179 if (opcode->tag < OT_odd_infix_0)
8180 {
8181 inst.cond = COND_ALWAYS;
8182 return opcode;
8183 }
8184
8185 if (unified_syntax)
8186 as_warn (_("conditional infixes are deprecated in unified syntax"));
8187 affix = base + (opcode->tag - OT_odd_infix_0);
8188 cond = hash_find_n (arm_cond_hsh, affix, 2);
8189 assert (cond);
8190
8191 inst.cond = cond->value;
8192 return opcode;
8193 }
8194
8195 /* Cannot have a conditional suffix on a mnemonic of less than two
8196 characters. */
8197 if (end - base < 3)
8198 return 0;
8199
8200 /* Look for suffixed mnemonic. */
8201 affix = end - 2;
8202 cond = hash_find_n (arm_cond_hsh, affix, 2);
8203 opcode = hash_find_n (arm_ops_hsh, base, affix - base);
8204 if (opcode && cond)
8205 {
8206 /* step CE */
8207 switch (opcode->tag)
8208 {
8209 case OT_cinfix3_legacy:
8210 /* Ignore conditional suffixes matched on infix only mnemonics. */
8211 break;
8212
8213 case OT_cinfix3:
8214 case OT_odd_infix_unc:
8215 if (!unified_syntax)
8216 return 0;
8217 /* else fall through */
8218
8219 case OT_csuffix:
8220 case OT_csuf_or_in3:
8221 inst.cond = cond->value;
8222 return opcode;
8223
8224 case OT_unconditional:
8225 case OT_unconditionalF:
8226 /* delayed diagnostic */
8227 inst.error = BAD_COND;
8228 inst.cond = COND_ALWAYS;
8229 return opcode;
8230
8231 default:
8232 return 0;
8233 }
8234 }
8235
8236 /* Cannot have a usual-position infix on a mnemonic of less than
8237 six characters (five would be a suffix). */
8238 if (end - base < 6)
8239 return 0;
8240
8241 /* Look for infixed mnemonic in the usual position. */
8242 affix = base + 3;
8243 cond = hash_find_n (arm_cond_hsh, affix, 2);
8244 if (!cond)
8245 return 0;
8246
8247 memcpy (save, affix, 2);
8248 memmove (affix, affix + 2, (end - affix) - 2);
8249 opcode = hash_find_n (arm_ops_hsh, base, (end - base) - 2);
8250 memmove (affix + 2, affix, (end - affix) - 2);
8251 memcpy (affix, save, 2);
8252
8253 if (opcode && (opcode->tag == OT_cinfix3 || opcode->tag == OT_csuf_or_in3
8254 || opcode->tag == OT_cinfix3_legacy))
8255 {
8256 /* step CM */
8257 if (unified_syntax && opcode->tag == OT_cinfix3)
8258 as_warn (_("conditional infixes are deprecated in unified syntax"));
8259
8260 inst.cond = cond->value;
8261 return opcode;
8262 }
8263
8264 return 0;
8265 }
8266
8267 void
8268 md_assemble (char *str)
8269 {
8270 char *p = str;
8271 const struct asm_opcode * opcode;
8272
8273 /* Align the previous label if needed. */
8274 if (last_label_seen != NULL)
8275 {
8276 symbol_set_frag (last_label_seen, frag_now);
8277 S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ());
8278 S_SET_SEGMENT (last_label_seen, now_seg);
8279 }
8280
8281 memset (&inst, '\0', sizeof (inst));
8282 inst.reloc.type = BFD_RELOC_UNUSED;
8283
8284 opcode = opcode_lookup (&p);
8285 if (!opcode)
8286 {
8287 /* It wasn't an instruction, but it might be a register alias of
8288 the form alias .req reg. */
8289 if (!create_register_alias (str, p))
8290 as_bad (_("bad instruction `%s'"), str);
8291
8292 return;
8293 }
8294
8295 if (thumb_mode)
8296 {
8297 arm_feature_set variant;
8298
8299 variant = cpu_variant;
8300 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
8301 if (!ARM_CPU_HAS_FEATURE (variant, arm_arch_t2))
8302 ARM_CLEAR_FEATURE (variant, variant, fpu_any_hard);
8303 /* Check that this instruction is supported for this CPU. */
8304 if (!opcode->tvariant
8305 || (thumb_mode == 1
8306 && !ARM_CPU_HAS_FEATURE (variant, *opcode->tvariant)))
8307 {
8308 as_bad (_("selected processor does not support `%s'"), str);
8309 return;
8310 }
8311 if (inst.cond != COND_ALWAYS && !unified_syntax
8312 && opcode->tencode != do_t_branch)
8313 {
8314 as_bad (_("Thumb does not support conditional execution"));
8315 return;
8316 }
8317
8318 /* Check conditional suffixes. */
8319 if (current_it_mask)
8320 {
8321 int cond;
8322 cond = current_cc ^ ((current_it_mask >> 4) & 1) ^ 1;
8323 if (cond != inst.cond)
8324 {
8325 as_bad (_("incorrect condition in IT block"));
8326 return;
8327 }
8328 current_it_mask <<= 1;
8329 current_it_mask &= 0x1f;
8330 }
8331 else if (inst.cond != COND_ALWAYS && opcode->tencode != do_t_branch)
8332 {
8333 as_bad (_("thumb conditional instrunction not in IT block"));
8334 return;
8335 }
8336
8337 mapping_state (MAP_THUMB);
8338 inst.instruction = opcode->tvalue;
8339
8340 if (!parse_operands (p, opcode->operands))
8341 opcode->tencode ();
8342
8343 /* Clear current_it_mask at the end of an IT block. */
8344 if (current_it_mask == 0x10)
8345 current_it_mask = 0;
8346
8347 if (!(inst.error || inst.relax))
8348 {
8349 assert (inst.instruction < 0xe800 || inst.instruction > 0xffff);
8350 inst.size = (inst.instruction > 0xffff ? 4 : 2);
8351 if (inst.size_req && inst.size_req != inst.size)
8352 {
8353 as_bad (_("cannot honor width suffix -- `%s'"), str);
8354 return;
8355 }
8356 }
8357 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
8358 *opcode->tvariant);
8359 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
8360 set those bits when Thumb-2 32-bit instuctions are seen. ie.
8361 anything other than bl/blx.
8362 This is overly pessimistic for relaxable instructions. */
8363 if ((inst.size == 4 && (inst.instruction & 0xf800e800) != 0xf000e800)
8364 || inst.relax)
8365 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
8366 arm_ext_v6t2);
8367 }
8368 else
8369 {
8370 /* Check that this instruction is supported for this CPU. */
8371 if (!opcode->avariant ||
8372 !ARM_CPU_HAS_FEATURE (cpu_variant, *opcode->avariant))
8373 {
8374 as_bad (_("selected processor does not support `%s'"), str);
8375 return;
8376 }
8377 if (inst.size_req)
8378 {
8379 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str);
8380 return;
8381 }
8382
8383 mapping_state (MAP_ARM);
8384 inst.instruction = opcode->avalue;
8385 if (opcode->tag == OT_unconditionalF)
8386 inst.instruction |= 0xF << 28;
8387 else
8388 inst.instruction |= inst.cond << 28;
8389 inst.size = INSN_SIZE;
8390 if (!parse_operands (p, opcode->operands))
8391 opcode->aencode ();
8392 /* Arm mode bx is marked as both v4T and v5 because it's still required
8393 on a hypothetical non-thumb v5 core. */
8394 if (ARM_CPU_HAS_FEATURE (*opcode->avariant, arm_ext_v4t)
8395 || ARM_CPU_HAS_FEATURE (*opcode->avariant, arm_ext_v5))
8396 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, arm_ext_v4t);
8397 else
8398 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
8399 *opcode->avariant);
8400 }
8401 output_inst (str);
8402 }
8403
8404 /* Various frobbings of labels and their addresses. */
8405
8406 void
8407 arm_start_line_hook (void)
8408 {
8409 last_label_seen = NULL;
8410 }
8411
8412 void
8413 arm_frob_label (symbolS * sym)
8414 {
8415 last_label_seen = sym;
8416
8417 ARM_SET_THUMB (sym, thumb_mode);
8418
8419 #if defined OBJ_COFF || defined OBJ_ELF
8420 ARM_SET_INTERWORK (sym, support_interwork);
8421 #endif
8422
8423 /* Note - do not allow local symbols (.Lxxx) to be labeled
8424 as Thumb functions. This is because these labels, whilst
8425 they exist inside Thumb code, are not the entry points for
8426 possible ARM->Thumb calls. Also, these labels can be used
8427 as part of a computed goto or switch statement. eg gcc
8428 can generate code that looks like this:
8429
8430 ldr r2, [pc, .Laaa]
8431 lsl r3, r3, #2
8432 ldr r2, [r3, r2]
8433 mov pc, r2
8434
8435 .Lbbb: .word .Lxxx
8436 .Lccc: .word .Lyyy
8437 ..etc...
8438 .Laaa: .word Lbbb
8439
8440 The first instruction loads the address of the jump table.
8441 The second instruction converts a table index into a byte offset.
8442 The third instruction gets the jump address out of the table.
8443 The fourth instruction performs the jump.
8444
8445 If the address stored at .Laaa is that of a symbol which has the
8446 Thumb_Func bit set, then the linker will arrange for this address
8447 to have the bottom bit set, which in turn would mean that the
8448 address computation performed by the third instruction would end
8449 up with the bottom bit set. Since the ARM is capable of unaligned
8450 word loads, the instruction would then load the incorrect address
8451 out of the jump table, and chaos would ensue. */
8452 if (label_is_thumb_function_name
8453 && (S_GET_NAME (sym)[0] != '.' || S_GET_NAME (sym)[1] != 'L')
8454 && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
8455 {
8456 /* When the address of a Thumb function is taken the bottom
8457 bit of that address should be set. This will allow
8458 interworking between Arm and Thumb functions to work
8459 correctly. */
8460
8461 THUMB_SET_FUNC (sym, 1);
8462
8463 label_is_thumb_function_name = FALSE;
8464 }
8465
8466 #ifdef OBJ_ELF
8467 dwarf2_emit_label (sym);
8468 #endif
8469 }
8470
8471 int
8472 arm_data_in_code (void)
8473 {
8474 if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5))
8475 {
8476 *input_line_pointer = '/';
8477 input_line_pointer += 5;
8478 *input_line_pointer = 0;
8479 return 1;
8480 }
8481
8482 return 0;
8483 }
8484
8485 char *
8486 arm_canonicalize_symbol_name (char * name)
8487 {
8488 int len;
8489
8490 if (thumb_mode && (len = strlen (name)) > 5
8491 && streq (name + len - 5, "/data"))
8492 *(name + len - 5) = 0;
8493
8494 return name;
8495 }
8496 \f
8497 /* Table of all register names defined by default. The user can
8498 define additional names with .req. Note that all register names
8499 should appear in both upper and lowercase variants. Some registers
8500 also have mixed-case names. */
8501
8502 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE }
8503 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
8504 #define REGSET(p,t) \
8505 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
8506 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
8507 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
8508 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
8509
8510 static const struct reg_entry reg_names[] =
8511 {
8512 /* ARM integer registers. */
8513 REGSET(r, RN), REGSET(R, RN),
8514
8515 /* ATPCS synonyms. */
8516 REGDEF(a1,0,RN), REGDEF(a2,1,RN), REGDEF(a3, 2,RN), REGDEF(a4, 3,RN),
8517 REGDEF(v1,4,RN), REGDEF(v2,5,RN), REGDEF(v3, 6,RN), REGDEF(v4, 7,RN),
8518 REGDEF(v5,8,RN), REGDEF(v6,9,RN), REGDEF(v7,10,RN), REGDEF(v8,11,RN),
8519
8520 REGDEF(A1,0,RN), REGDEF(A2,1,RN), REGDEF(A3, 2,RN), REGDEF(A4, 3,RN),
8521 REGDEF(V1,4,RN), REGDEF(V2,5,RN), REGDEF(V3, 6,RN), REGDEF(V4, 7,RN),
8522 REGDEF(V5,8,RN), REGDEF(V6,9,RN), REGDEF(V7,10,RN), REGDEF(V8,11,RN),
8523
8524 /* Well-known aliases. */
8525 REGDEF(wr, 7,RN), REGDEF(sb, 9,RN), REGDEF(sl,10,RN), REGDEF(fp,11,RN),
8526 REGDEF(ip,12,RN), REGDEF(sp,13,RN), REGDEF(lr,14,RN), REGDEF(pc,15,RN),
8527
8528 REGDEF(WR, 7,RN), REGDEF(SB, 9,RN), REGDEF(SL,10,RN), REGDEF(FP,11,RN),
8529 REGDEF(IP,12,RN), REGDEF(SP,13,RN), REGDEF(LR,14,RN), REGDEF(PC,15,RN),
8530
8531 /* Coprocessor numbers. */
8532 REGSET(p, CP), REGSET(P, CP),
8533
8534 /* Coprocessor register numbers. The "cr" variants are for backward
8535 compatibility. */
8536 REGSET(c, CN), REGSET(C, CN),
8537 REGSET(cr, CN), REGSET(CR, CN),
8538
8539 /* FPA registers. */
8540 REGNUM(f,0,FN), REGNUM(f,1,FN), REGNUM(f,2,FN), REGNUM(f,3,FN),
8541 REGNUM(f,4,FN), REGNUM(f,5,FN), REGNUM(f,6,FN), REGNUM(f,7, FN),
8542
8543 REGNUM(F,0,FN), REGNUM(F,1,FN), REGNUM(F,2,FN), REGNUM(F,3,FN),
8544 REGNUM(F,4,FN), REGNUM(F,5,FN), REGNUM(F,6,FN), REGNUM(F,7, FN),
8545
8546 /* VFP SP registers. */
8547 REGSET(s,VFS),
8548 REGNUM(s,16,VFS), REGNUM(s,17,VFS), REGNUM(s,18,VFS), REGNUM(s,19,VFS),
8549 REGNUM(s,20,VFS), REGNUM(s,21,VFS), REGNUM(s,22,VFS), REGNUM(s,23,VFS),
8550 REGNUM(s,24,VFS), REGNUM(s,25,VFS), REGNUM(s,26,VFS), REGNUM(s,27,VFS),
8551 REGNUM(s,28,VFS), REGNUM(s,29,VFS), REGNUM(s,30,VFS), REGNUM(s,31,VFS),
8552
8553 REGSET(S,VFS),
8554 REGNUM(S,16,VFS), REGNUM(S,17,VFS), REGNUM(S,18,VFS), REGNUM(S,19,VFS),
8555 REGNUM(S,20,VFS), REGNUM(S,21,VFS), REGNUM(S,22,VFS), REGNUM(S,23,VFS),
8556 REGNUM(S,24,VFS), REGNUM(S,25,VFS), REGNUM(S,26,VFS), REGNUM(S,27,VFS),
8557 REGNUM(S,28,VFS), REGNUM(S,29,VFS), REGNUM(S,30,VFS), REGNUM(S,31,VFS),
8558
8559 /* VFP DP Registers. */
8560 REGSET(d,VFD), REGSET(D,VFS),
8561
8562 /* VFP control registers. */
8563 REGDEF(fpsid,0,VFC), REGDEF(fpscr,1,VFC), REGDEF(fpexc,8,VFC),
8564 REGDEF(FPSID,0,VFC), REGDEF(FPSCR,1,VFC), REGDEF(FPEXC,8,VFC),
8565
8566 /* Maverick DSP coprocessor registers. */
8567 REGSET(mvf,MVF), REGSET(mvd,MVD), REGSET(mvfx,MVFX), REGSET(mvdx,MVDX),
8568 REGSET(MVF,MVF), REGSET(MVD,MVD), REGSET(MVFX,MVFX), REGSET(MVDX,MVDX),
8569
8570 REGNUM(mvax,0,MVAX), REGNUM(mvax,1,MVAX),
8571 REGNUM(mvax,2,MVAX), REGNUM(mvax,3,MVAX),
8572 REGDEF(dspsc,0,DSPSC),
8573
8574 REGNUM(MVAX,0,MVAX), REGNUM(MVAX,1,MVAX),
8575 REGNUM(MVAX,2,MVAX), REGNUM(MVAX,3,MVAX),
8576 REGDEF(DSPSC,0,DSPSC),
8577
8578 /* iWMMXt data registers - p0, c0-15. */
8579 REGSET(wr,MMXWR), REGSET(wR,MMXWR), REGSET(WR, MMXWR),
8580
8581 /* iWMMXt control registers - p1, c0-3. */
8582 REGDEF(wcid, 0,MMXWC), REGDEF(wCID, 0,MMXWC), REGDEF(WCID, 0,MMXWC),
8583 REGDEF(wcon, 1,MMXWC), REGDEF(wCon, 1,MMXWC), REGDEF(WCON, 1,MMXWC),
8584 REGDEF(wcssf, 2,MMXWC), REGDEF(wCSSF, 2,MMXWC), REGDEF(WCSSF, 2,MMXWC),
8585 REGDEF(wcasf, 3,MMXWC), REGDEF(wCASF, 3,MMXWC), REGDEF(WCASF, 3,MMXWC),
8586
8587 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
8588 REGDEF(wcgr0, 8,MMXWCG), REGDEF(wCGR0, 8,MMXWCG), REGDEF(WCGR0, 8,MMXWCG),
8589 REGDEF(wcgr1, 9,MMXWCG), REGDEF(wCGR1, 9,MMXWCG), REGDEF(WCGR1, 9,MMXWCG),
8590 REGDEF(wcgr2,10,MMXWCG), REGDEF(wCGR2,10,MMXWCG), REGDEF(WCGR2,10,MMXWCG),
8591 REGDEF(wcgr3,11,MMXWCG), REGDEF(wCGR3,11,MMXWCG), REGDEF(WCGR3,11,MMXWCG),
8592
8593 /* XScale accumulator registers. */
8594 REGNUM(acc,0,XSCALE), REGNUM(ACC,0,XSCALE),
8595 };
8596 #undef REGDEF
8597 #undef REGNUM
8598 #undef REGSET
8599
8600 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
8601 within psr_required_here. */
8602 static const struct asm_psr psrs[] =
8603 {
8604 /* Backward compatibility notation. Note that "all" is no longer
8605 truly all possible PSR bits. */
8606 {"all", PSR_c | PSR_f},
8607 {"flg", PSR_f},
8608 {"ctl", PSR_c},
8609
8610 /* Individual flags. */
8611 {"f", PSR_f},
8612 {"c", PSR_c},
8613 {"x", PSR_x},
8614 {"s", PSR_s},
8615 /* Combinations of flags. */
8616 {"fs", PSR_f | PSR_s},
8617 {"fx", PSR_f | PSR_x},
8618 {"fc", PSR_f | PSR_c},
8619 {"sf", PSR_s | PSR_f},
8620 {"sx", PSR_s | PSR_x},
8621 {"sc", PSR_s | PSR_c},
8622 {"xf", PSR_x | PSR_f},
8623 {"xs", PSR_x | PSR_s},
8624 {"xc", PSR_x | PSR_c},
8625 {"cf", PSR_c | PSR_f},
8626 {"cs", PSR_c | PSR_s},
8627 {"cx", PSR_c | PSR_x},
8628 {"fsx", PSR_f | PSR_s | PSR_x},
8629 {"fsc", PSR_f | PSR_s | PSR_c},
8630 {"fxs", PSR_f | PSR_x | PSR_s},
8631 {"fxc", PSR_f | PSR_x | PSR_c},
8632 {"fcs", PSR_f | PSR_c | PSR_s},
8633 {"fcx", PSR_f | PSR_c | PSR_x},
8634 {"sfx", PSR_s | PSR_f | PSR_x},
8635 {"sfc", PSR_s | PSR_f | PSR_c},
8636 {"sxf", PSR_s | PSR_x | PSR_f},
8637 {"sxc", PSR_s | PSR_x | PSR_c},
8638 {"scf", PSR_s | PSR_c | PSR_f},
8639 {"scx", PSR_s | PSR_c | PSR_x},
8640 {"xfs", PSR_x | PSR_f | PSR_s},
8641 {"xfc", PSR_x | PSR_f | PSR_c},
8642 {"xsf", PSR_x | PSR_s | PSR_f},
8643 {"xsc", PSR_x | PSR_s | PSR_c},
8644 {"xcf", PSR_x | PSR_c | PSR_f},
8645 {"xcs", PSR_x | PSR_c | PSR_s},
8646 {"cfs", PSR_c | PSR_f | PSR_s},
8647 {"cfx", PSR_c | PSR_f | PSR_x},
8648 {"csf", PSR_c | PSR_s | PSR_f},
8649 {"csx", PSR_c | PSR_s | PSR_x},
8650 {"cxf", PSR_c | PSR_x | PSR_f},
8651 {"cxs", PSR_c | PSR_x | PSR_s},
8652 {"fsxc", PSR_f | PSR_s | PSR_x | PSR_c},
8653 {"fscx", PSR_f | PSR_s | PSR_c | PSR_x},
8654 {"fxsc", PSR_f | PSR_x | PSR_s | PSR_c},
8655 {"fxcs", PSR_f | PSR_x | PSR_c | PSR_s},
8656 {"fcsx", PSR_f | PSR_c | PSR_s | PSR_x},
8657 {"fcxs", PSR_f | PSR_c | PSR_x | PSR_s},
8658 {"sfxc", PSR_s | PSR_f | PSR_x | PSR_c},
8659 {"sfcx", PSR_s | PSR_f | PSR_c | PSR_x},
8660 {"sxfc", PSR_s | PSR_x | PSR_f | PSR_c},
8661 {"sxcf", PSR_s | PSR_x | PSR_c | PSR_f},
8662 {"scfx", PSR_s | PSR_c | PSR_f | PSR_x},
8663 {"scxf", PSR_s | PSR_c | PSR_x | PSR_f},
8664 {"xfsc", PSR_x | PSR_f | PSR_s | PSR_c},
8665 {"xfcs", PSR_x | PSR_f | PSR_c | PSR_s},
8666 {"xsfc", PSR_x | PSR_s | PSR_f | PSR_c},
8667 {"xscf", PSR_x | PSR_s | PSR_c | PSR_f},
8668 {"xcfs", PSR_x | PSR_c | PSR_f | PSR_s},
8669 {"xcsf", PSR_x | PSR_c | PSR_s | PSR_f},
8670 {"cfsx", PSR_c | PSR_f | PSR_s | PSR_x},
8671 {"cfxs", PSR_c | PSR_f | PSR_x | PSR_s},
8672 {"csfx", PSR_c | PSR_s | PSR_f | PSR_x},
8673 {"csxf", PSR_c | PSR_s | PSR_x | PSR_f},
8674 {"cxfs", PSR_c | PSR_x | PSR_f | PSR_s},
8675 {"cxsf", PSR_c | PSR_x | PSR_s | PSR_f},
8676 };
8677
8678 /* Table of V7M psr names. */
8679 static const struct asm_psr v7m_psrs[] =
8680 {
8681 {"apsr", 0 },
8682 {"iapsr", 1 },
8683 {"eapsr", 2 },
8684 {"psr", 3 },
8685 {"ipsr", 5 },
8686 {"epsr", 6 },
8687 {"iepsr", 7 },
8688 {"msp", 8 },
8689 {"psp", 9 },
8690 {"primask", 16},
8691 {"basepri", 17},
8692 {"basepri_max", 18},
8693 {"faultmask", 19},
8694 {"control", 20}
8695 };
8696
8697 /* Table of all shift-in-operand names. */
8698 static const struct asm_shift_name shift_names [] =
8699 {
8700 { "asl", SHIFT_LSL }, { "ASL", SHIFT_LSL },
8701 { "lsl", SHIFT_LSL }, { "LSL", SHIFT_LSL },
8702 { "lsr", SHIFT_LSR }, { "LSR", SHIFT_LSR },
8703 { "asr", SHIFT_ASR }, { "ASR", SHIFT_ASR },
8704 { "ror", SHIFT_ROR }, { "ROR", SHIFT_ROR },
8705 { "rrx", SHIFT_RRX }, { "RRX", SHIFT_RRX }
8706 };
8707
8708 /* Table of all explicit relocation names. */
8709 #ifdef OBJ_ELF
8710 static struct reloc_entry reloc_names[] =
8711 {
8712 { "got", BFD_RELOC_ARM_GOT32 }, { "GOT", BFD_RELOC_ARM_GOT32 },
8713 { "gotoff", BFD_RELOC_ARM_GOTOFF }, { "GOTOFF", BFD_RELOC_ARM_GOTOFF },
8714 { "plt", BFD_RELOC_ARM_PLT32 }, { "PLT", BFD_RELOC_ARM_PLT32 },
8715 { "target1", BFD_RELOC_ARM_TARGET1 }, { "TARGET1", BFD_RELOC_ARM_TARGET1 },
8716 { "target2", BFD_RELOC_ARM_TARGET2 }, { "TARGET2", BFD_RELOC_ARM_TARGET2 },
8717 { "sbrel", BFD_RELOC_ARM_SBREL32 }, { "SBREL", BFD_RELOC_ARM_SBREL32 },
8718 { "tlsgd", BFD_RELOC_ARM_TLS_GD32}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32},
8719 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32},
8720 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32},
8721 { "gottpoff",BFD_RELOC_ARM_TLS_IE32}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32},
8722 { "tpoff", BFD_RELOC_ARM_TLS_LE32}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32}
8723 };
8724 #endif
8725
8726 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
8727 static const struct asm_cond conds[] =
8728 {
8729 {"eq", 0x0},
8730 {"ne", 0x1},
8731 {"cs", 0x2}, {"hs", 0x2},
8732 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
8733 {"mi", 0x4},
8734 {"pl", 0x5},
8735 {"vs", 0x6},
8736 {"vc", 0x7},
8737 {"hi", 0x8},
8738 {"ls", 0x9},
8739 {"ge", 0xa},
8740 {"lt", 0xb},
8741 {"gt", 0xc},
8742 {"le", 0xd},
8743 {"al", 0xe}
8744 };
8745
8746 static struct asm_barrier_opt barrier_opt_names[] =
8747 {
8748 { "sy", 0xf },
8749 { "un", 0x7 },
8750 { "st", 0xe },
8751 { "unst", 0x6 }
8752 };
8753
8754 /* Table of ARM-format instructions. */
8755
8756 /* Macros for gluing together operand strings. N.B. In all cases
8757 other than OPS0, the trailing OP_stop comes from default
8758 zero-initialization of the unspecified elements of the array. */
8759 #define OPS0() { OP_stop, }
8760 #define OPS1(a) { OP_##a, }
8761 #define OPS2(a,b) { OP_##a,OP_##b, }
8762 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
8763 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
8764 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
8765 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
8766
8767 /* These macros abstract out the exact format of the mnemonic table and
8768 save some repeated characters. */
8769
8770 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
8771 #define TxCE(mnem, op, top, nops, ops, ae, te) \
8772 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
8773 THUMB_VARIANT, do_##ae, do_##te }
8774
8775 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
8776 a T_MNEM_xyz enumerator. */
8777 #define TCE(mnem, aop, top, nops, ops, ae, te) \
8778 TxCE(mnem, aop, 0x##top, nops, ops, ae, te)
8779 #define tCE(mnem, aop, top, nops, ops, ae, te) \
8780 TxCE(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
8781
8782 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
8783 infix after the third character. */
8784 #define TxC3(mnem, op, top, nops, ops, ae, te) \
8785 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
8786 THUMB_VARIANT, do_##ae, do_##te }
8787 #define TC3(mnem, aop, top, nops, ops, ae, te) \
8788 TxC3(mnem, aop, 0x##top, nops, ops, ae, te)
8789 #define tC3(mnem, aop, top, nops, ops, ae, te) \
8790 TxC3(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
8791
8792 /* Mnemonic with a conditional infix in an unusual place. Each and every variant has to
8793 appear in the condition table. */
8794 #define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \
8795 { #m1 #m2 #m3, OPS##nops ops, sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \
8796 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te }
8797
8798 #define TxCM(m1, m2, op, top, nops, ops, ae, te) \
8799 TxCM_(m1, , m2, op, top, nops, ops, ae, te), \
8800 TxCM_(m1, eq, m2, op, top, nops, ops, ae, te), \
8801 TxCM_(m1, ne, m2, op, top, nops, ops, ae, te), \
8802 TxCM_(m1, cs, m2, op, top, nops, ops, ae, te), \
8803 TxCM_(m1, hs, m2, op, top, nops, ops, ae, te), \
8804 TxCM_(m1, cc, m2, op, top, nops, ops, ae, te), \
8805 TxCM_(m1, ul, m2, op, top, nops, ops, ae, te), \
8806 TxCM_(m1, lo, m2, op, top, nops, ops, ae, te), \
8807 TxCM_(m1, mi, m2, op, top, nops, ops, ae, te), \
8808 TxCM_(m1, pl, m2, op, top, nops, ops, ae, te), \
8809 TxCM_(m1, vs, m2, op, top, nops, ops, ae, te), \
8810 TxCM_(m1, vc, m2, op, top, nops, ops, ae, te), \
8811 TxCM_(m1, hi, m2, op, top, nops, ops, ae, te), \
8812 TxCM_(m1, ls, m2, op, top, nops, ops, ae, te), \
8813 TxCM_(m1, ge, m2, op, top, nops, ops, ae, te), \
8814 TxCM_(m1, lt, m2, op, top, nops, ops, ae, te), \
8815 TxCM_(m1, gt, m2, op, top, nops, ops, ae, te), \
8816 TxCM_(m1, le, m2, op, top, nops, ops, ae, te), \
8817 TxCM_(m1, al, m2, op, top, nops, ops, ae, te)
8818
8819 #define TCM(m1,m2, aop, top, nops, ops, ae, te) \
8820 TxCM(m1,m2, aop, 0x##top, nops, ops, ae, te)
8821 #define tCM(m1,m2, aop, top, nops, ops, ae, te) \
8822 TxCM(m1,m2, aop, T_MNEM_##top, nops, ops, ae, te)
8823
8824 /* Mnemonic that cannot be conditionalized. The ARM condition-code
8825 field is still 0xE. */
8826 #define TUE(mnem, op, top, nops, ops, ae, te) \
8827 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
8828 THUMB_VARIANT, do_##ae, do_##te }
8829
8830 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
8831 condition code field. */
8832 #define TUF(mnem, op, top, nops, ops, ae, te) \
8833 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
8834 THUMB_VARIANT, do_##ae, do_##te }
8835
8836 /* ARM-only variants of all the above. */
8837 #define CE(mnem, op, nops, ops, ae) \
8838 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
8839
8840 #define C3(mnem, op, nops, ops, ae) \
8841 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
8842
8843 /* Legacy mnemonics that always have conditional infix after the third
8844 character. */
8845 #define CL(mnem, op, nops, ops, ae) \
8846 { #mnem, OPS##nops ops, OT_cinfix3_legacy, \
8847 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
8848
8849 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
8850 #define cCE(mnem, op, nops, ops, ae) \
8851 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
8852
8853 /* Legacy coprocessor instructions where conditional infix and conditional
8854 suffix are ambiguous. For consistency this includes all FPA instructions,
8855 not just the potentially ambiguous ones. */
8856 #define cCL(mnem, op, nops, ops, ae) \
8857 { #mnem, OPS##nops ops, OT_cinfix3_legacy, \
8858 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
8859
8860 /* Coprocessor, takes either a suffix or a position-3 infix
8861 (for an FPA corner case). */
8862 #define C3E(mnem, op, nops, ops, ae) \
8863 { #mnem, OPS##nops ops, OT_csuf_or_in3, \
8864 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
8865
8866 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
8867 { #m1 #m2 #m3, OPS##nops ops, \
8868 sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \
8869 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
8870
8871 #define CM(m1, m2, op, nops, ops, ae) \
8872 xCM_(m1, , m2, op, nops, ops, ae), \
8873 xCM_(m1, eq, m2, op, nops, ops, ae), \
8874 xCM_(m1, ne, m2, op, nops, ops, ae), \
8875 xCM_(m1, cs, m2, op, nops, ops, ae), \
8876 xCM_(m1, hs, m2, op, nops, ops, ae), \
8877 xCM_(m1, cc, m2, op, nops, ops, ae), \
8878 xCM_(m1, ul, m2, op, nops, ops, ae), \
8879 xCM_(m1, lo, m2, op, nops, ops, ae), \
8880 xCM_(m1, mi, m2, op, nops, ops, ae), \
8881 xCM_(m1, pl, m2, op, nops, ops, ae), \
8882 xCM_(m1, vs, m2, op, nops, ops, ae), \
8883 xCM_(m1, vc, m2, op, nops, ops, ae), \
8884 xCM_(m1, hi, m2, op, nops, ops, ae), \
8885 xCM_(m1, ls, m2, op, nops, ops, ae), \
8886 xCM_(m1, ge, m2, op, nops, ops, ae), \
8887 xCM_(m1, lt, m2, op, nops, ops, ae), \
8888 xCM_(m1, gt, m2, op, nops, ops, ae), \
8889 xCM_(m1, le, m2, op, nops, ops, ae), \
8890 xCM_(m1, al, m2, op, nops, ops, ae)
8891
8892 #define UE(mnem, op, nops, ops, ae) \
8893 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
8894
8895 #define UF(mnem, op, nops, ops, ae) \
8896 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
8897
8898 #define do_0 0
8899
8900 /* Thumb-only, unconditional. */
8901 #define UT(mnem, op, nops, ops, te) TUE(mnem, 0, op, nops, ops, 0, te)
8902
8903 static const struct asm_opcode insns[] =
8904 {
8905 #define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */
8906 #define THUMB_VARIANT &arm_ext_v4t
8907 tCE(and, 0000000, and, 3, (RR, oRR, SH), arit, t_arit3c),
8908 tC3(ands, 0100000, ands, 3, (RR, oRR, SH), arit, t_arit3c),
8909 tCE(eor, 0200000, eor, 3, (RR, oRR, SH), arit, t_arit3c),
8910 tC3(eors, 0300000, eors, 3, (RR, oRR, SH), arit, t_arit3c),
8911 tCE(sub, 0400000, sub, 3, (RR, oRR, SH), arit, t_add_sub),
8912 tC3(subs, 0500000, subs, 3, (RR, oRR, SH), arit, t_add_sub),
8913 tCE(add, 0800000, add, 3, (RR, oRR, SH), arit, t_add_sub),
8914 tC3(adds, 0900000, adds, 3, (RR, oRR, SH), arit, t_add_sub),
8915 tCE(adc, 0a00000, adc, 3, (RR, oRR, SH), arit, t_arit3c),
8916 tC3(adcs, 0b00000, adcs, 3, (RR, oRR, SH), arit, t_arit3c),
8917 tCE(sbc, 0c00000, sbc, 3, (RR, oRR, SH), arit, t_arit3),
8918 tC3(sbcs, 0d00000, sbcs, 3, (RR, oRR, SH), arit, t_arit3),
8919 tCE(orr, 1800000, orr, 3, (RR, oRR, SH), arit, t_arit3c),
8920 tC3(orrs, 1900000, orrs, 3, (RR, oRR, SH), arit, t_arit3c),
8921 tCE(bic, 1c00000, bic, 3, (RR, oRR, SH), arit, t_arit3),
8922 tC3(bics, 1d00000, bics, 3, (RR, oRR, SH), arit, t_arit3),
8923
8924 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
8925 for setting PSR flag bits. They are obsolete in V6 and do not
8926 have Thumb equivalents. */
8927 tCE(tst, 1100000, tst, 2, (RR, SH), cmp, t_mvn_tst),
8928 tC3(tsts, 1100000, tst, 2, (RR, SH), cmp, t_mvn_tst),
8929 CL(tstp, 110f000, 2, (RR, SH), cmp),
8930 tCE(cmp, 1500000, cmp, 2, (RR, SH), cmp, t_mov_cmp),
8931 tC3(cmps, 1500000, cmp, 2, (RR, SH), cmp, t_mov_cmp),
8932 CL(cmpp, 150f000, 2, (RR, SH), cmp),
8933 tCE(cmn, 1700000, cmn, 2, (RR, SH), cmp, t_mvn_tst),
8934 tC3(cmns, 1700000, cmn, 2, (RR, SH), cmp, t_mvn_tst),
8935 CL(cmnp, 170f000, 2, (RR, SH), cmp),
8936
8937 tCE(mov, 1a00000, mov, 2, (RR, SH), mov, t_mov_cmp),
8938 tC3(movs, 1b00000, movs, 2, (RR, SH), mov, t_mov_cmp),
8939 tCE(mvn, 1e00000, mvn, 2, (RR, SH), mov, t_mvn_tst),
8940 tC3(mvns, 1f00000, mvns, 2, (RR, SH), mov, t_mvn_tst),
8941
8942 tCE(ldr, 4100000, ldr, 2, (RR, ADDR), ldst, t_ldst),
8943 tC3(ldrb, 4500000, ldrb, 2, (RR, ADDR), ldst, t_ldst),
8944 tCE(str, 4000000, str, 2, (RR, ADDR), ldst, t_ldst),
8945 tC3(strb, 4400000, strb, 2, (RR, ADDR), ldst, t_ldst),
8946
8947 tC3(stmia, 8800000, stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
8948 tC3(stmea, 8800000, stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
8949 tC3(ldmia, 8900000, ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
8950 tC3(ldmfd, 8900000, ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
8951
8952 TCE(swi, f000000, df00, 1, (EXPi), swi, t_swi),
8953 tCE(b, a000000, b, 1, (EXPr), branch, t_branch),
8954 TCE(bl, b000000, f000f800, 1, (EXPr), bl, t_branch23),
8955
8956 /* Pseudo ops. */
8957 tCE(adr, 28f0000, adr, 2, (RR, EXP), adr, t_adr),
8958 C3(adrl, 28f0000, 2, (RR, EXP), adrl),
8959 tCE(nop, 1a00000, nop, 1, (oI255c), nop, t_nop),
8960
8961 /* Thumb-compatibility pseudo ops. */
8962 tCE(lsl, 1a00000, lsl, 3, (RR, oRR, SH), shift, t_shift),
8963 tC3(lsls, 1b00000, lsls, 3, (RR, oRR, SH), shift, t_shift),
8964 tCE(lsr, 1a00020, lsr, 3, (RR, oRR, SH), shift, t_shift),
8965 tC3(lsrs, 1b00020, lsrs, 3, (RR, oRR, SH), shift, t_shift),
8966 tCE(asr, 1a00040, asr, 3, (RR, oRR, SH), shift, t_shift),
8967 tC3(asrs, 1b00040, asrs, 3, (RR, oRR, SH), shift, t_shift),
8968 tCE(ror, 1a00060, ror, 3, (RR, oRR, SH), shift, t_shift),
8969 tC3(rors, 1b00060, rors, 3, (RR, oRR, SH), shift, t_shift),
8970 tCE(neg, 2600000, neg, 2, (RR, RR), rd_rn, t_neg),
8971 tC3(negs, 2700000, negs, 2, (RR, RR), rd_rn, t_neg),
8972 tCE(push, 92d0000, push, 1, (REGLST), push_pop, t_push_pop),
8973 tCE(pop, 8bd0000, pop, 1, (REGLST), push_pop, t_push_pop),
8974
8975 #undef THUMB_VARIANT
8976 #define THUMB_VARIANT &arm_ext_v6
8977 TCE(cpy, 1a00000, 4600, 2, (RR, RR), rd_rm, t_cpy),
8978
8979 /* V1 instructions with no Thumb analogue prior to V6T2. */
8980 #undef THUMB_VARIANT
8981 #define THUMB_VARIANT &arm_ext_v6t2
8982 TCE(rsb, 0600000, ebc00000, 3, (RR, oRR, SH), arit, t_rsb),
8983 TC3(rsbs, 0700000, ebd00000, 3, (RR, oRR, SH), arit, t_rsb),
8984 TCE(teq, 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
8985 TC3(teqs, 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
8986 CL(teqp, 130f000, 2, (RR, SH), cmp),
8987
8988 TC3(ldrt, 4300000, f8500e00, 2, (RR, ADDR), ldstt, t_ldstt),
8989 TC3(ldrbt, 4700000, f8300e00, 2, (RR, ADDR), ldstt, t_ldstt),
8990 TC3(strt, 4200000, f8400e00, 2, (RR, ADDR), ldstt, t_ldstt),
8991 TC3(strbt, 4600000, f8200e00, 2, (RR, ADDR), ldstt, t_ldstt),
8992
8993 TC3(stmdb, 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
8994 TC3(stmfd, 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
8995
8996 TC3(ldmdb, 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
8997 TC3(ldmea, 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
8998
8999 /* V1 instructions with no Thumb analogue at all. */
9000 CE(rsc, 0e00000, 3, (RR, oRR, SH), arit),
9001 C3(rscs, 0f00000, 3, (RR, oRR, SH), arit),
9002
9003 C3(stmib, 9800000, 2, (RRw, REGLST), ldmstm),
9004 C3(stmfa, 9800000, 2, (RRw, REGLST), ldmstm),
9005 C3(stmda, 8000000, 2, (RRw, REGLST), ldmstm),
9006 C3(stmed, 8000000, 2, (RRw, REGLST), ldmstm),
9007 C3(ldmib, 9900000, 2, (RRw, REGLST), ldmstm),
9008 C3(ldmed, 9900000, 2, (RRw, REGLST), ldmstm),
9009 C3(ldmda, 8100000, 2, (RRw, REGLST), ldmstm),
9010 C3(ldmfa, 8100000, 2, (RRw, REGLST), ldmstm),
9011
9012 #undef ARM_VARIANT
9013 #define ARM_VARIANT &arm_ext_v2 /* ARM 2 - multiplies. */
9014 #undef THUMB_VARIANT
9015 #define THUMB_VARIANT &arm_ext_v4t
9016 tCE(mul, 0000090, mul, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
9017 tC3(muls, 0100090, muls, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
9018
9019 #undef THUMB_VARIANT
9020 #define THUMB_VARIANT &arm_ext_v6t2
9021 TCE(mla, 0200090, fb000000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
9022 C3(mlas, 0300090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas),
9023
9024 /* Generic coprocessor instructions. */
9025 TCE(cdp, e000000, ee000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
9026 TCE(ldc, c100000, ec100000, 3, (RCP, RCN, ADDR), lstc, lstc),
9027 TC3(ldcl, c500000, ec500000, 3, (RCP, RCN, ADDR), lstc, lstc),
9028 TCE(stc, c000000, ec000000, 3, (RCP, RCN, ADDR), lstc, lstc),
9029 TC3(stcl, c400000, ec400000, 3, (RCP, RCN, ADDR), lstc, lstc),
9030 TCE(mcr, e000010, ee000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
9031 TCE(mrc, e100010, ee100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
9032
9033 #undef ARM_VARIANT
9034 #define ARM_VARIANT &arm_ext_v2s /* ARM 3 - swp instructions. */
9035 CE(swp, 1000090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
9036 C3(swpb, 1400090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
9037
9038 #undef ARM_VARIANT
9039 #define ARM_VARIANT &arm_ext_v3 /* ARM 6 Status register instructions. */
9040 TCE(mrs, 10f0000, f3ef8000, 2, (RR, PSR), mrs, t_mrs),
9041 TCE(msr, 120f000, f3808000, 2, (PSR, RR_EXi), msr, t_msr),
9042
9043 #undef ARM_VARIANT
9044 #define ARM_VARIANT &arm_ext_v3m /* ARM 7M long multiplies. */
9045 TCE(smull, 0c00090, fb800000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
9046 CM(smull,s, 0d00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
9047 TCE(umull, 0800090, fba00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
9048 CM(umull,s, 0900090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
9049 TCE(smlal, 0e00090, fbc00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
9050 CM(smlal,s, 0f00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
9051 TCE(umlal, 0a00090, fbe00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
9052 CM(umlal,s, 0b00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
9053
9054 #undef ARM_VARIANT
9055 #define ARM_VARIANT &arm_ext_v4 /* ARM Architecture 4. */
9056 #undef THUMB_VARIANT
9057 #define THUMB_VARIANT &arm_ext_v4t
9058 tC3(ldrh, 01000b0, ldrh, 2, (RR, ADDR), ldstv4, t_ldst),
9059 tC3(strh, 00000b0, strh, 2, (RR, ADDR), ldstv4, t_ldst),
9060 tC3(ldrsh, 01000f0, ldrsh, 2, (RR, ADDR), ldstv4, t_ldst),
9061 tC3(ldrsb, 01000d0, ldrsb, 2, (RR, ADDR), ldstv4, t_ldst),
9062 tCM(ld,sh, 01000f0, ldrsh, 2, (RR, ADDR), ldstv4, t_ldst),
9063 tCM(ld,sb, 01000d0, ldrsb, 2, (RR, ADDR), ldstv4, t_ldst),
9064
9065 #undef ARM_VARIANT
9066 #define ARM_VARIANT &arm_ext_v4t_5
9067 /* ARM Architecture 4T. */
9068 /* Note: bx (and blx) are required on V5, even if the processor does
9069 not support Thumb. */
9070 TCE(bx, 12fff10, 4700, 1, (RR), bx, t_bx),
9071
9072 #undef ARM_VARIANT
9073 #define ARM_VARIANT &arm_ext_v5 /* ARM Architecture 5T. */
9074 #undef THUMB_VARIANT
9075 #define THUMB_VARIANT &arm_ext_v5t
9076 /* Note: blx has 2 variants; the .value coded here is for
9077 BLX(2). Only this variant has conditional execution. */
9078 TCE(blx, 12fff30, 4780, 1, (RR_EXr), blx, t_blx),
9079 TUE(bkpt, 1200070, be00, 1, (oIffffb), bkpt, t_bkpt),
9080
9081 #undef THUMB_VARIANT
9082 #define THUMB_VARIANT &arm_ext_v6t2
9083 TCE(clz, 16f0f10, fab0f080, 2, (RRnpc, RRnpc), rd_rm, t_clz),
9084 TUF(ldc2, c100000, fc100000, 3, (RCP, RCN, ADDR), lstc, lstc),
9085 TUF(ldc2l, c500000, fc500000, 3, (RCP, RCN, ADDR), lstc, lstc),
9086 TUF(stc2, c000000, fc000000, 3, (RCP, RCN, ADDR), lstc, lstc),
9087 TUF(stc2l, c400000, fc400000, 3, (RCP, RCN, ADDR), lstc, lstc),
9088 TUF(cdp2, e000000, fe000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
9089 TUF(mcr2, e000010, fe000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
9090 TUF(mrc2, e100010, fe100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
9091
9092 #undef ARM_VARIANT
9093 #define ARM_VARIANT &arm_ext_v5exp /* ARM Architecture 5TExP. */
9094 TCE(smlabb, 1000080, fb100000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
9095 TCE(smlatb, 10000a0, fb100020, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
9096 TCE(smlabt, 10000c0, fb100010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
9097 TCE(smlatt, 10000e0, fb100030, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
9098
9099 TCE(smlawb, 1200080, fb300000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
9100 TCE(smlawt, 12000c0, fb300010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
9101
9102 TCE(smlalbb, 1400080, fbc00080, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
9103 TCE(smlaltb, 14000a0, fbc000a0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
9104 TCE(smlalbt, 14000c0, fbc00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
9105 TCE(smlaltt, 14000e0, fbc000b0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
9106
9107 TCE(smulbb, 1600080, fb10f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
9108 TCE(smultb, 16000a0, fb10f020, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
9109 TCE(smulbt, 16000c0, fb10f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
9110 TCE(smultt, 16000e0, fb10f030, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
9111
9112 TCE(smulwb, 12000a0, fb30f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
9113 TCE(smulwt, 12000e0, fb30f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
9114
9115 TCE(qadd, 1000050, fa80f080, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn),
9116 TCE(qdadd, 1400050, fa80f090, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn),
9117 TCE(qsub, 1200050, fa80f0a0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn),
9118 TCE(qdsub, 1600050, fa80f0b0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn),
9119
9120 #undef ARM_VARIANT
9121 #define ARM_VARIANT &arm_ext_v5e /* ARM Architecture 5TE. */
9122 TUF(pld, 450f000, f810f000, 1, (ADDR), pld, t_pld),
9123 TC3(ldrd, 00000d0, e9500000, 3, (RRnpc, oRRnpc, ADDR), ldrd, t_ldstd),
9124 TC3(strd, 00000f0, e9400000, 3, (RRnpc, oRRnpc, ADDR), ldrd, t_ldstd),
9125
9126 TCE(mcrr, c400000, ec400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
9127 TCE(mrrc, c500000, ec500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
9128
9129 #undef ARM_VARIANT
9130 #define ARM_VARIANT &arm_ext_v5j /* ARM Architecture 5TEJ. */
9131 TCE(bxj, 12fff20, f3c08f00, 1, (RR), bxj, t_bxj),
9132
9133 #undef ARM_VARIANT
9134 #define ARM_VARIANT &arm_ext_v6 /* ARM V6. */
9135 #undef THUMB_VARIANT
9136 #define THUMB_VARIANT &arm_ext_v6
9137 TUF(cpsie, 1080000, b660, 2, (CPSF, oI31b), cpsi, t_cpsi),
9138 TUF(cpsid, 10c0000, b670, 2, (CPSF, oI31b), cpsi, t_cpsi),
9139 tCE(rev, 6bf0f30, rev, 2, (RRnpc, RRnpc), rd_rm, t_rev),
9140 tCE(rev16, 6bf0fb0, rev16, 2, (RRnpc, RRnpc), rd_rm, t_rev),
9141 tCE(revsh, 6ff0fb0, revsh, 2, (RRnpc, RRnpc), rd_rm, t_rev),
9142 tCE(sxth, 6bf0070, sxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
9143 tCE(uxth, 6ff0070, uxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
9144 tCE(sxtb, 6af0070, sxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
9145 tCE(uxtb, 6ef0070, uxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
9146 TUF(setend, 1010000, b650, 1, (ENDI), setend, t_setend),
9147
9148 #undef THUMB_VARIANT
9149 #define THUMB_VARIANT &arm_ext_v6t2
9150 TCE(ldrex, 1900f9f, e8500f00, 2, (RRnpc, ADDR), ldrex, t_ldrex),
9151 TUF(mcrr2, c400000, fc400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
9152 TUF(mrrc2, c500000, fc500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
9153
9154 TCE(ssat, 6a00010, f3000000, 4, (RRnpc, I32, RRnpc, oSHllar),ssat, t_ssat),
9155 TCE(usat, 6e00010, f3800000, 4, (RRnpc, I31, RRnpc, oSHllar),usat, t_usat),
9156
9157 /* ARM V6 not included in V7M (eg. integer SIMD). */
9158 #undef THUMB_VARIANT
9159 #define THUMB_VARIANT &arm_ext_v6_notm
9160 TUF(cps, 1020000, f3af8100, 1, (I31b), imm0, imm0),
9161 TCE(pkhbt, 6800010, eac00000, 4, (RRnpc, RRnpc, RRnpc, oSHll), pkhbt, t_pkhbt),
9162 TCE(pkhtb, 6800050, eac00020, 4, (RRnpc, RRnpc, RRnpc, oSHar), pkhtb, t_pkhtb),
9163 TCE(qadd16, 6200f10, fa90f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9164 TCE(qadd8, 6200f90, fa80f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9165 TCE(qaddsubx, 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9166 TCE(qsub16, 6200f70, fad0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9167 TCE(qsub8, 6200ff0, fac0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9168 TCE(qsubaddx, 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9169 TCE(sadd16, 6100f10, fa90f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9170 TCE(sadd8, 6100f90, fa80f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9171 TCE(saddsubx, 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9172 TCE(shadd16, 6300f10, fa90f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9173 TCE(shadd8, 6300f90, fa80f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9174 TCE(shaddsubx, 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9175 TCE(shsub16, 6300f70, fad0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9176 TCE(shsub8, 6300ff0, fac0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9177 TCE(shsubaddx, 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9178 TCE(ssub16, 6100f70, fad0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9179 TCE(ssub8, 6100ff0, fac0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9180 TCE(ssubaddx, 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9181 TCE(uadd16, 6500f10, fa90f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9182 TCE(uadd8, 6500f90, fa80f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9183 TCE(uaddsubx, 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9184 TCE(uhadd16, 6700f10, fa90f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9185 TCE(uhadd8, 6700f90, fa80f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9186 TCE(uhaddsubx, 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9187 TCE(uhsub16, 6700f70, fad0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9188 TCE(uhsub8, 6700ff0, fac0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9189 TCE(uhsubaddx, 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9190 TCE(uqadd16, 6600f10, fa90f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9191 TCE(uqadd8, 6600f90, fa80f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9192 TCE(uqaddsubx, 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9193 TCE(uqsub16, 6600f70, fad0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9194 TCE(uqsub8, 6600ff0, fac0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9195 TCE(uqsubaddx, 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9196 TCE(usub16, 6500f70, fad0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9197 TCE(usub8, 6500ff0, fac0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9198 TCE(usubaddx, 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9199 TUF(rfeia, 8900a00, e990c000, 1, (RRw), rfe, rfe),
9200 UF(rfeib, 9900a00, 1, (RRw), rfe),
9201 UF(rfeda, 8100a00, 1, (RRw), rfe),
9202 TUF(rfedb, 9100a00, e810c000, 1, (RRw), rfe, rfe),
9203 TUF(rfefd, 8900a00, e990c000, 1, (RRw), rfe, rfe),
9204 UF(rfefa, 9900a00, 1, (RRw), rfe),
9205 UF(rfeea, 8100a00, 1, (RRw), rfe),
9206 TUF(rfeed, 9100a00, e810c000, 1, (RRw), rfe, rfe),
9207 TCE(sxtah, 6b00070, fa00f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
9208 TCE(sxtab16, 6800070, fa20f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
9209 TCE(sxtab, 6a00070, fa40f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
9210 TCE(sxtb16, 68f0070, fa2ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
9211 TCE(uxtah, 6f00070, fa10f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
9212 TCE(uxtab16, 6c00070, fa30f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
9213 TCE(uxtab, 6e00070, fa50f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
9214 TCE(uxtb16, 6cf0070, fa3ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
9215 TCE(sel, 6800fb0, faa0f080, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9216 TCE(smlad, 7000010, fb200000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
9217 TCE(smladx, 7000030, fb200010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
9218 TCE(smlald, 7400010, fbc000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
9219 TCE(smlaldx, 7400030, fbc000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
9220 TCE(smlsd, 7000050, fb400000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
9221 TCE(smlsdx, 7000070, fb400010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
9222 TCE(smlsld, 7400050, fbd000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
9223 TCE(smlsldx, 7400070, fbd000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
9224 TCE(smmla, 7500010, fb500000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
9225 TCE(smmlar, 7500030, fb500010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
9226 TCE(smmls, 75000d0, fb600000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
9227 TCE(smmlsr, 75000f0, fb600010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
9228 TCE(smmul, 750f010, fb50f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
9229 TCE(smmulr, 750f030, fb50f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
9230 TCE(smuad, 700f010, fb20f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
9231 TCE(smuadx, 700f030, fb20f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
9232 TCE(smusd, 700f050, fb40f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
9233 TCE(smusdx, 700f070, fb40f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
9234 TUF(srsia, 8cd0500, e980c000, 1, (I31w), srs, srs),
9235 UF(srsib, 9cd0500, 1, (I31w), srs),
9236 UF(srsda, 84d0500, 1, (I31w), srs),
9237 TUF(srsdb, 94d0500, e800c000, 1, (I31w), srs, srs),
9238 TCE(ssat16, 6a00f30, f3200000, 3, (RRnpc, I16, RRnpc), ssat16, t_ssat16),
9239 TCE(strex, 1800f90, e8400000, 3, (RRnpc, RRnpc, ADDR), strex, t_strex),
9240 TCE(umaal, 0400090, fbe00060, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal, t_mlal),
9241 TCE(usad8, 780f010, fb70f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
9242 TCE(usada8, 7800010, fb700000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
9243 TCE(usat16, 6e00f30, f3a00000, 3, (RRnpc, I15, RRnpc), usat16, t_usat16),
9244
9245 #undef ARM_VARIANT
9246 #define ARM_VARIANT &arm_ext_v6k
9247 #undef THUMB_VARIANT
9248 #define THUMB_VARIANT &arm_ext_v6k
9249 tCE(yield, 320f001, yield, 0, (), noargs, t_hint),
9250 tCE(wfe, 320f002, wfe, 0, (), noargs, t_hint),
9251 tCE(wfi, 320f003, wfi, 0, (), noargs, t_hint),
9252 tCE(sev, 320f004, sev, 0, (), noargs, t_hint),
9253
9254 #undef THUMB_VARIANT
9255 #define THUMB_VARIANT &arm_ext_v6_notm
9256 TCE(ldrexd, 1b00f9f, e8d0007f, 3, (RRnpc, oRRnpc, RRnpcb), ldrexd, t_ldrexd),
9257 TCE(strexd, 1a00f90, e8c00070, 4, (RRnpc, RRnpc, oRRnpc, RRnpcb), strexd, t_strexd),
9258
9259 #undef THUMB_VARIANT
9260 #define THUMB_VARIANT &arm_ext_v6t2
9261 TCE(ldrexb, 1d00f9f, e8d00f4f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
9262 TCE(ldrexh, 1f00f9f, e8d00f5f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
9263 TCE(strexb, 1c00f90, e8c00f40, 3, (RRnpc, RRnpc, ADDR), strex, rm_rd_rn),
9264 TCE(strexh, 1e00f90, e8c00f50, 3, (RRnpc, RRnpc, ADDR), strex, rm_rd_rn),
9265 TUF(clrex, 57ff01f, f3bf8f2f, 0, (), noargs, noargs),
9266
9267 #undef ARM_VARIANT
9268 #define ARM_VARIANT &arm_ext_v6z
9269 TCE(smc, 1600070, f7f08000, 1, (EXPi), smc, t_smc),
9270
9271 #undef ARM_VARIANT
9272 #define ARM_VARIANT &arm_ext_v6t2
9273 TCE(bfc, 7c0001f, f36f0000, 3, (RRnpc, I31, I32), bfc, t_bfc),
9274 TCE(bfi, 7c00010, f3600000, 4, (RRnpc, RRnpc_I0, I31, I32), bfi, t_bfi),
9275 TCE(sbfx, 7a00050, f3400000, 4, (RR, RR, I31, I32), bfx, t_bfx),
9276 TCE(ubfx, 7e00050, f3c00000, 4, (RR, RR, I31, I32), bfx, t_bfx),
9277
9278 TCE(mls, 0600090, fb000010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
9279 TCE(movw, 3000000, f2400000, 2, (RRnpc, Iffff), mov16, t_mov16),
9280 TCE(movt, 3400000, f2c00000, 2, (RRnpc, Iffff), mov16, t_mov16),
9281 TCE(rbit, 3ff0f30, fa90f0a0, 2, (RR, RR), rd_rm, t_rbit),
9282
9283 TC3(ldrht, 03000b0, f8300e00, 2, (RR, ADDR), ldsttv4, t_ldstt),
9284 TC3(ldrsht, 03000f0, f9300e00, 2, (RR, ADDR), ldsttv4, t_ldstt),
9285 TC3(ldrsbt, 03000d0, f9100e00, 2, (RR, ADDR), ldsttv4, t_ldstt),
9286 TC3(strht, 02000b0, f8200e00, 2, (RR, ADDR), ldsttv4, t_ldstt),
9287
9288 UT(cbnz, b900, 2, (RR, EXP), t_czb),
9289 UT(cbz, b100, 2, (RR, EXP), t_czb),
9290 /* ARM does not really have an IT instruction. */
9291 TUE(it, 0, bf08, 1, (COND), it, t_it),
9292 TUE(itt, 0, bf0c, 1, (COND), it, t_it),
9293 TUE(ite, 0, bf04, 1, (COND), it, t_it),
9294 TUE(ittt, 0, bf0e, 1, (COND), it, t_it),
9295 TUE(itet, 0, bf06, 1, (COND), it, t_it),
9296 TUE(itte, 0, bf0a, 1, (COND), it, t_it),
9297 TUE(itee, 0, bf02, 1, (COND), it, t_it),
9298 TUE(itttt, 0, bf0f, 1, (COND), it, t_it),
9299 TUE(itett, 0, bf07, 1, (COND), it, t_it),
9300 TUE(ittet, 0, bf0b, 1, (COND), it, t_it),
9301 TUE(iteet, 0, bf03, 1, (COND), it, t_it),
9302 TUE(ittte, 0, bf0d, 1, (COND), it, t_it),
9303 TUE(itete, 0, bf05, 1, (COND), it, t_it),
9304 TUE(ittee, 0, bf09, 1, (COND), it, t_it),
9305 TUE(iteee, 0, bf01, 1, (COND), it, t_it),
9306
9307 /* Thumb2 only instructions. */
9308 #undef ARM_VARIANT
9309 #define ARM_VARIANT NULL
9310
9311 TCE(addw, 0, f2000000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
9312 TCE(subw, 0, f2a00000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
9313 TCE(tbb, 0, e8d0f000, 1, (TB), 0, t_tb),
9314 TCE(tbh, 0, e8d0f010, 1, (TB), 0, t_tb),
9315
9316 /* Thumb-2 hardware division instructions (R and M profiles only). */
9317 #undef THUMB_VARIANT
9318 #define THUMB_VARIANT &arm_ext_div
9319 TCE(sdiv, 0, fb90f0f0, 3, (RR, oRR, RR), 0, t_div),
9320 TCE(udiv, 0, fbb0f0f0, 3, (RR, oRR, RR), 0, t_div),
9321
9322 /* ARM V7 instructions. */
9323 #undef ARM_VARIANT
9324 #define ARM_VARIANT &arm_ext_v7
9325 #undef THUMB_VARIANT
9326 #define THUMB_VARIANT &arm_ext_v7
9327 TUF(pli, 450f000, f910f000, 1, (ADDR), pli, t_pld),
9328 TCE(dbg, 320f0f0, f3af80f0, 1, (I15), dbg, t_dbg),
9329 TUF(dmb, 57ff050, f3bf8f50, 1, (oBARRIER), barrier, t_barrier),
9330 TUF(dsb, 57ff040, f3bf8f40, 1, (oBARRIER), barrier, t_barrier),
9331 TUF(isb, 57ff060, f3bf8f60, 1, (oBARRIER), barrier, t_barrier),
9332
9333 #undef ARM_VARIANT
9334 #define ARM_VARIANT &fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
9335 cCE(wfs, e200110, 1, (RR), rd),
9336 cCE(rfs, e300110, 1, (RR), rd),
9337 cCE(wfc, e400110, 1, (RR), rd),
9338 cCE(rfc, e500110, 1, (RR), rd),
9339
9340 cCL(ldfs, c100100, 2, (RF, ADDR), rd_cpaddr),
9341 cCL(ldfd, c108100, 2, (RF, ADDR), rd_cpaddr),
9342 cCL(ldfe, c500100, 2, (RF, ADDR), rd_cpaddr),
9343 cCL(ldfp, c508100, 2, (RF, ADDR), rd_cpaddr),
9344
9345 cCL(stfs, c000100, 2, (RF, ADDR), rd_cpaddr),
9346 cCL(stfd, c008100, 2, (RF, ADDR), rd_cpaddr),
9347 cCL(stfe, c400100, 2, (RF, ADDR), rd_cpaddr),
9348 cCL(stfp, c408100, 2, (RF, ADDR), rd_cpaddr),
9349
9350 cCL(mvfs, e008100, 2, (RF, RF_IF), rd_rm),
9351 cCL(mvfsp, e008120, 2, (RF, RF_IF), rd_rm),
9352 cCL(mvfsm, e008140, 2, (RF, RF_IF), rd_rm),
9353 cCL(mvfsz, e008160, 2, (RF, RF_IF), rd_rm),
9354 cCL(mvfd, e008180, 2, (RF, RF_IF), rd_rm),
9355 cCL(mvfdp, e0081a0, 2, (RF, RF_IF), rd_rm),
9356 cCL(mvfdm, e0081c0, 2, (RF, RF_IF), rd_rm),
9357 cCL(mvfdz, e0081e0, 2, (RF, RF_IF), rd_rm),
9358 cCL(mvfe, e088100, 2, (RF, RF_IF), rd_rm),
9359 cCL(mvfep, e088120, 2, (RF, RF_IF), rd_rm),
9360 cCL(mvfem, e088140, 2, (RF, RF_IF), rd_rm),
9361 cCL(mvfez, e088160, 2, (RF, RF_IF), rd_rm),
9362
9363 cCL(mnfs, e108100, 2, (RF, RF_IF), rd_rm),
9364 cCL(mnfsp, e108120, 2, (RF, RF_IF), rd_rm),
9365 cCL(mnfsm, e108140, 2, (RF, RF_IF), rd_rm),
9366 cCL(mnfsz, e108160, 2, (RF, RF_IF), rd_rm),
9367 cCL(mnfd, e108180, 2, (RF, RF_IF), rd_rm),
9368 cCL(mnfdp, e1081a0, 2, (RF, RF_IF), rd_rm),
9369 cCL(mnfdm, e1081c0, 2, (RF, RF_IF), rd_rm),
9370 cCL(mnfdz, e1081e0, 2, (RF, RF_IF), rd_rm),
9371 cCL(mnfe, e188100, 2, (RF, RF_IF), rd_rm),
9372 cCL(mnfep, e188120, 2, (RF, RF_IF), rd_rm),
9373 cCL(mnfem, e188140, 2, (RF, RF_IF), rd_rm),
9374 cCL(mnfez, e188160, 2, (RF, RF_IF), rd_rm),
9375
9376 cCL(abss, e208100, 2, (RF, RF_IF), rd_rm),
9377 cCL(abssp, e208120, 2, (RF, RF_IF), rd_rm),
9378 cCL(abssm, e208140, 2, (RF, RF_IF), rd_rm),
9379 cCL(abssz, e208160, 2, (RF, RF_IF), rd_rm),
9380 cCL(absd, e208180, 2, (RF, RF_IF), rd_rm),
9381 cCL(absdp, e2081a0, 2, (RF, RF_IF), rd_rm),
9382 cCL(absdm, e2081c0, 2, (RF, RF_IF), rd_rm),
9383 cCL(absdz, e2081e0, 2, (RF, RF_IF), rd_rm),
9384 cCL(abse, e288100, 2, (RF, RF_IF), rd_rm),
9385 cCL(absep, e288120, 2, (RF, RF_IF), rd_rm),
9386 cCL(absem, e288140, 2, (RF, RF_IF), rd_rm),
9387 cCL(absez, e288160, 2, (RF, RF_IF), rd_rm),
9388
9389 cCL(rnds, e308100, 2, (RF, RF_IF), rd_rm),
9390 cCL(rndsp, e308120, 2, (RF, RF_IF), rd_rm),
9391 cCL(rndsm, e308140, 2, (RF, RF_IF), rd_rm),
9392 cCL(rndsz, e308160, 2, (RF, RF_IF), rd_rm),
9393 cCL(rndd, e308180, 2, (RF, RF_IF), rd_rm),
9394 cCL(rnddp, e3081a0, 2, (RF, RF_IF), rd_rm),
9395 cCL(rnddm, e3081c0, 2, (RF, RF_IF), rd_rm),
9396 cCL(rnddz, e3081e0, 2, (RF, RF_IF), rd_rm),
9397 cCL(rnde, e388100, 2, (RF, RF_IF), rd_rm),
9398 cCL(rndep, e388120, 2, (RF, RF_IF), rd_rm),
9399 cCL(rndem, e388140, 2, (RF, RF_IF), rd_rm),
9400 cCL(rndez, e388160, 2, (RF, RF_IF), rd_rm),
9401
9402 cCL(sqts, e408100, 2, (RF, RF_IF), rd_rm),
9403 cCL(sqtsp, e408120, 2, (RF, RF_IF), rd_rm),
9404 cCL(sqtsm, e408140, 2, (RF, RF_IF), rd_rm),
9405 cCL(sqtsz, e408160, 2, (RF, RF_IF), rd_rm),
9406 cCL(sqtd, e408180, 2, (RF, RF_IF), rd_rm),
9407 cCL(sqtdp, e4081a0, 2, (RF, RF_IF), rd_rm),
9408 cCL(sqtdm, e4081c0, 2, (RF, RF_IF), rd_rm),
9409 cCL(sqtdz, e4081e0, 2, (RF, RF_IF), rd_rm),
9410 cCL(sqte, e488100, 2, (RF, RF_IF), rd_rm),
9411 cCL(sqtep, e488120, 2, (RF, RF_IF), rd_rm),
9412 cCL(sqtem, e488140, 2, (RF, RF_IF), rd_rm),
9413 cCL(sqtez, e488160, 2, (RF, RF_IF), rd_rm),
9414
9415 cCL(logs, e508100, 2, (RF, RF_IF), rd_rm),
9416 cCL(logsp, e508120, 2, (RF, RF_IF), rd_rm),
9417 cCL(logsm, e508140, 2, (RF, RF_IF), rd_rm),
9418 cCL(logsz, e508160, 2, (RF, RF_IF), rd_rm),
9419 cCL(logd, e508180, 2, (RF, RF_IF), rd_rm),
9420 cCL(logdp, e5081a0, 2, (RF, RF_IF), rd_rm),
9421 cCL(logdm, e5081c0, 2, (RF, RF_IF), rd_rm),
9422 cCL(logdz, e5081e0, 2, (RF, RF_IF), rd_rm),
9423 cCL(loge, e588100, 2, (RF, RF_IF), rd_rm),
9424 cCL(logep, e588120, 2, (RF, RF_IF), rd_rm),
9425 cCL(logem, e588140, 2, (RF, RF_IF), rd_rm),
9426 cCL(logez, e588160, 2, (RF, RF_IF), rd_rm),
9427
9428 cCL(lgns, e608100, 2, (RF, RF_IF), rd_rm),
9429 cCL(lgnsp, e608120, 2, (RF, RF_IF), rd_rm),
9430 cCL(lgnsm, e608140, 2, (RF, RF_IF), rd_rm),
9431 cCL(lgnsz, e608160, 2, (RF, RF_IF), rd_rm),
9432 cCL(lgnd, e608180, 2, (RF, RF_IF), rd_rm),
9433 cCL(lgndp, e6081a0, 2, (RF, RF_IF), rd_rm),
9434 cCL(lgndm, e6081c0, 2, (RF, RF_IF), rd_rm),
9435 cCL(lgndz, e6081e0, 2, (RF, RF_IF), rd_rm),
9436 cCL(lgne, e688100, 2, (RF, RF_IF), rd_rm),
9437 cCL(lgnep, e688120, 2, (RF, RF_IF), rd_rm),
9438 cCL(lgnem, e688140, 2, (RF, RF_IF), rd_rm),
9439 cCL(lgnez, e688160, 2, (RF, RF_IF), rd_rm),
9440
9441 cCL(exps, e708100, 2, (RF, RF_IF), rd_rm),
9442 cCL(expsp, e708120, 2, (RF, RF_IF), rd_rm),
9443 cCL(expsm, e708140, 2, (RF, RF_IF), rd_rm),
9444 cCL(expsz, e708160, 2, (RF, RF_IF), rd_rm),
9445 cCL(expd, e708180, 2, (RF, RF_IF), rd_rm),
9446 cCL(expdp, e7081a0, 2, (RF, RF_IF), rd_rm),
9447 cCL(expdm, e7081c0, 2, (RF, RF_IF), rd_rm),
9448 cCL(expdz, e7081e0, 2, (RF, RF_IF), rd_rm),
9449 cCL(expe, e788100, 2, (RF, RF_IF), rd_rm),
9450 cCL(expep, e788120, 2, (RF, RF_IF), rd_rm),
9451 cCL(expem, e788140, 2, (RF, RF_IF), rd_rm),
9452 cCL(expdz, e788160, 2, (RF, RF_IF), rd_rm),
9453
9454 cCL(sins, e808100, 2, (RF, RF_IF), rd_rm),
9455 cCL(sinsp, e808120, 2, (RF, RF_IF), rd_rm),
9456 cCL(sinsm, e808140, 2, (RF, RF_IF), rd_rm),
9457 cCL(sinsz, e808160, 2, (RF, RF_IF), rd_rm),
9458 cCL(sind, e808180, 2, (RF, RF_IF), rd_rm),
9459 cCL(sindp, e8081a0, 2, (RF, RF_IF), rd_rm),
9460 cCL(sindm, e8081c0, 2, (RF, RF_IF), rd_rm),
9461 cCL(sindz, e8081e0, 2, (RF, RF_IF), rd_rm),
9462 cCL(sine, e888100, 2, (RF, RF_IF), rd_rm),
9463 cCL(sinep, e888120, 2, (RF, RF_IF), rd_rm),
9464 cCL(sinem, e888140, 2, (RF, RF_IF), rd_rm),
9465 cCL(sinez, e888160, 2, (RF, RF_IF), rd_rm),
9466
9467 cCL(coss, e908100, 2, (RF, RF_IF), rd_rm),
9468 cCL(cossp, e908120, 2, (RF, RF_IF), rd_rm),
9469 cCL(cossm, e908140, 2, (RF, RF_IF), rd_rm),
9470 cCL(cossz, e908160, 2, (RF, RF_IF), rd_rm),
9471 cCL(cosd, e908180, 2, (RF, RF_IF), rd_rm),
9472 cCL(cosdp, e9081a0, 2, (RF, RF_IF), rd_rm),
9473 cCL(cosdm, e9081c0, 2, (RF, RF_IF), rd_rm),
9474 cCL(cosdz, e9081e0, 2, (RF, RF_IF), rd_rm),
9475 cCL(cose, e988100, 2, (RF, RF_IF), rd_rm),
9476 cCL(cosep, e988120, 2, (RF, RF_IF), rd_rm),
9477 cCL(cosem, e988140, 2, (RF, RF_IF), rd_rm),
9478 cCL(cosez, e988160, 2, (RF, RF_IF), rd_rm),
9479
9480 cCL(tans, ea08100, 2, (RF, RF_IF), rd_rm),
9481 cCL(tansp, ea08120, 2, (RF, RF_IF), rd_rm),
9482 cCL(tansm, ea08140, 2, (RF, RF_IF), rd_rm),
9483 cCL(tansz, ea08160, 2, (RF, RF_IF), rd_rm),
9484 cCL(tand, ea08180, 2, (RF, RF_IF), rd_rm),
9485 cCL(tandp, ea081a0, 2, (RF, RF_IF), rd_rm),
9486 cCL(tandm, ea081c0, 2, (RF, RF_IF), rd_rm),
9487 cCL(tandz, ea081e0, 2, (RF, RF_IF), rd_rm),
9488 cCL(tane, ea88100, 2, (RF, RF_IF), rd_rm),
9489 cCL(tanep, ea88120, 2, (RF, RF_IF), rd_rm),
9490 cCL(tanem, ea88140, 2, (RF, RF_IF), rd_rm),
9491 cCL(tanez, ea88160, 2, (RF, RF_IF), rd_rm),
9492
9493 cCL(asns, eb08100, 2, (RF, RF_IF), rd_rm),
9494 cCL(asnsp, eb08120, 2, (RF, RF_IF), rd_rm),
9495 cCL(asnsm, eb08140, 2, (RF, RF_IF), rd_rm),
9496 cCL(asnsz, eb08160, 2, (RF, RF_IF), rd_rm),
9497 cCL(asnd, eb08180, 2, (RF, RF_IF), rd_rm),
9498 cCL(asndp, eb081a0, 2, (RF, RF_IF), rd_rm),
9499 cCL(asndm, eb081c0, 2, (RF, RF_IF), rd_rm),
9500 cCL(asndz, eb081e0, 2, (RF, RF_IF), rd_rm),
9501 cCL(asne, eb88100, 2, (RF, RF_IF), rd_rm),
9502 cCL(asnep, eb88120, 2, (RF, RF_IF), rd_rm),
9503 cCL(asnem, eb88140, 2, (RF, RF_IF), rd_rm),
9504 cCL(asnez, eb88160, 2, (RF, RF_IF), rd_rm),
9505
9506 cCL(acss, ec08100, 2, (RF, RF_IF), rd_rm),
9507 cCL(acssp, ec08120, 2, (RF, RF_IF), rd_rm),
9508 cCL(acssm, ec08140, 2, (RF, RF_IF), rd_rm),
9509 cCL(acssz, ec08160, 2, (RF, RF_IF), rd_rm),
9510 cCL(acsd, ec08180, 2, (RF, RF_IF), rd_rm),
9511 cCL(acsdp, ec081a0, 2, (RF, RF_IF), rd_rm),
9512 cCL(acsdm, ec081c0, 2, (RF, RF_IF), rd_rm),
9513 cCL(acsdz, ec081e0, 2, (RF, RF_IF), rd_rm),
9514 cCL(acse, ec88100, 2, (RF, RF_IF), rd_rm),
9515 cCL(acsep, ec88120, 2, (RF, RF_IF), rd_rm),
9516 cCL(acsem, ec88140, 2, (RF, RF_IF), rd_rm),
9517 cCL(acsez, ec88160, 2, (RF, RF_IF), rd_rm),
9518
9519 cCL(atns, ed08100, 2, (RF, RF_IF), rd_rm),
9520 cCL(atnsp, ed08120, 2, (RF, RF_IF), rd_rm),
9521 cCL(atnsm, ed08140, 2, (RF, RF_IF), rd_rm),
9522 cCL(atnsz, ed08160, 2, (RF, RF_IF), rd_rm),
9523 cCL(atnd, ed08180, 2, (RF, RF_IF), rd_rm),
9524 cCL(atndp, ed081a0, 2, (RF, RF_IF), rd_rm),
9525 cCL(atndm, ed081c0, 2, (RF, RF_IF), rd_rm),
9526 cCL(atndz, ed081e0, 2, (RF, RF_IF), rd_rm),
9527 cCL(atne, ed88100, 2, (RF, RF_IF), rd_rm),
9528 cCL(atnep, ed88120, 2, (RF, RF_IF), rd_rm),
9529 cCL(atnem, ed88140, 2, (RF, RF_IF), rd_rm),
9530 cCL(atnez, ed88160, 2, (RF, RF_IF), rd_rm),
9531
9532 cCL(urds, ee08100, 2, (RF, RF_IF), rd_rm),
9533 cCL(urdsp, ee08120, 2, (RF, RF_IF), rd_rm),
9534 cCL(urdsm, ee08140, 2, (RF, RF_IF), rd_rm),
9535 cCL(urdsz, ee08160, 2, (RF, RF_IF), rd_rm),
9536 cCL(urdd, ee08180, 2, (RF, RF_IF), rd_rm),
9537 cCL(urddp, ee081a0, 2, (RF, RF_IF), rd_rm),
9538 cCL(urddm, ee081c0, 2, (RF, RF_IF), rd_rm),
9539 cCL(urddz, ee081e0, 2, (RF, RF_IF), rd_rm),
9540 cCL(urde, ee88100, 2, (RF, RF_IF), rd_rm),
9541 cCL(urdep, ee88120, 2, (RF, RF_IF), rd_rm),
9542 cCL(urdem, ee88140, 2, (RF, RF_IF), rd_rm),
9543 cCL(urdez, ee88160, 2, (RF, RF_IF), rd_rm),
9544
9545 cCL(nrms, ef08100, 2, (RF, RF_IF), rd_rm),
9546 cCL(nrmsp, ef08120, 2, (RF, RF_IF), rd_rm),
9547 cCL(nrmsm, ef08140, 2, (RF, RF_IF), rd_rm),
9548 cCL(nrmsz, ef08160, 2, (RF, RF_IF), rd_rm),
9549 cCL(nrmd, ef08180, 2, (RF, RF_IF), rd_rm),
9550 cCL(nrmdp, ef081a0, 2, (RF, RF_IF), rd_rm),
9551 cCL(nrmdm, ef081c0, 2, (RF, RF_IF), rd_rm),
9552 cCL(nrmdz, ef081e0, 2, (RF, RF_IF), rd_rm),
9553 cCL(nrme, ef88100, 2, (RF, RF_IF), rd_rm),
9554 cCL(nrmep, ef88120, 2, (RF, RF_IF), rd_rm),
9555 cCL(nrmem, ef88140, 2, (RF, RF_IF), rd_rm),
9556 cCL(nrmez, ef88160, 2, (RF, RF_IF), rd_rm),
9557
9558 cCL(adfs, e000100, 3, (RF, RF, RF_IF), rd_rn_rm),
9559 cCL(adfsp, e000120, 3, (RF, RF, RF_IF), rd_rn_rm),
9560 cCL(adfsm, e000140, 3, (RF, RF, RF_IF), rd_rn_rm),
9561 cCL(adfsz, e000160, 3, (RF, RF, RF_IF), rd_rn_rm),
9562 cCL(adfd, e000180, 3, (RF, RF, RF_IF), rd_rn_rm),
9563 cCL(adfdp, e0001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
9564 cCL(adfdm, e0001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
9565 cCL(adfdz, e0001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
9566 cCL(adfe, e080100, 3, (RF, RF, RF_IF), rd_rn_rm),
9567 cCL(adfep, e080120, 3, (RF, RF, RF_IF), rd_rn_rm),
9568 cCL(adfem, e080140, 3, (RF, RF, RF_IF), rd_rn_rm),
9569 cCL(adfez, e080160, 3, (RF, RF, RF_IF), rd_rn_rm),
9570
9571 cCL(sufs, e200100, 3, (RF, RF, RF_IF), rd_rn_rm),
9572 cCL(sufsp, e200120, 3, (RF, RF, RF_IF), rd_rn_rm),
9573 cCL(sufsm, e200140, 3, (RF, RF, RF_IF), rd_rn_rm),
9574 cCL(sufsz, e200160, 3, (RF, RF, RF_IF), rd_rn_rm),
9575 cCL(sufd, e200180, 3, (RF, RF, RF_IF), rd_rn_rm),
9576 cCL(sufdp, e2001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
9577 cCL(sufdm, e2001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
9578 cCL(sufdz, e2001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
9579 cCL(sufe, e280100, 3, (RF, RF, RF_IF), rd_rn_rm),
9580 cCL(sufep, e280120, 3, (RF, RF, RF_IF), rd_rn_rm),
9581 cCL(sufem, e280140, 3, (RF, RF, RF_IF), rd_rn_rm),
9582 cCL(sufez, e280160, 3, (RF, RF, RF_IF), rd_rn_rm),
9583
9584 cCL(rsfs, e300100, 3, (RF, RF, RF_IF), rd_rn_rm),
9585 cCL(rsfsp, e300120, 3, (RF, RF, RF_IF), rd_rn_rm),
9586 cCL(rsfsm, e300140, 3, (RF, RF, RF_IF), rd_rn_rm),
9587 cCL(rsfsz, e300160, 3, (RF, RF, RF_IF), rd_rn_rm),
9588 cCL(rsfd, e300180, 3, (RF, RF, RF_IF), rd_rn_rm),
9589 cCL(rsfdp, e3001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
9590 cCL(rsfdm, e3001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
9591 cCL(rsfdz, e3001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
9592 cCL(rsfe, e380100, 3, (RF, RF, RF_IF), rd_rn_rm),
9593 cCL(rsfep, e380120, 3, (RF, RF, RF_IF), rd_rn_rm),
9594 cCL(rsfem, e380140, 3, (RF, RF, RF_IF), rd_rn_rm),
9595 cCL(rsfez, e380160, 3, (RF, RF, RF_IF), rd_rn_rm),
9596
9597 cCL(mufs, e100100, 3, (RF, RF, RF_IF), rd_rn_rm),
9598 cCL(mufsp, e100120, 3, (RF, RF, RF_IF), rd_rn_rm),
9599 cCL(mufsm, e100140, 3, (RF, RF, RF_IF), rd_rn_rm),
9600 cCL(mufsz, e100160, 3, (RF, RF, RF_IF), rd_rn_rm),
9601 cCL(mufd, e100180, 3, (RF, RF, RF_IF), rd_rn_rm),
9602 cCL(mufdp, e1001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
9603 cCL(mufdm, e1001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
9604 cCL(mufdz, e1001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
9605 cCL(mufe, e180100, 3, (RF, RF, RF_IF), rd_rn_rm),
9606 cCL(mufep, e180120, 3, (RF, RF, RF_IF), rd_rn_rm),
9607 cCL(mufem, e180140, 3, (RF, RF, RF_IF), rd_rn_rm),
9608 cCL(mufez, e180160, 3, (RF, RF, RF_IF), rd_rn_rm),
9609
9610 cCL(dvfs, e400100, 3, (RF, RF, RF_IF), rd_rn_rm),
9611 cCL(dvfsp, e400120, 3, (RF, RF, RF_IF), rd_rn_rm),
9612 cCL(dvfsm, e400140, 3, (RF, RF, RF_IF), rd_rn_rm),
9613 cCL(dvfsz, e400160, 3, (RF, RF, RF_IF), rd_rn_rm),
9614 cCL(dvfd, e400180, 3, (RF, RF, RF_IF), rd_rn_rm),
9615 cCL(dvfdp, e4001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
9616 cCL(dvfdm, e4001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
9617 cCL(dvfdz, e4001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
9618 cCL(dvfe, e480100, 3, (RF, RF, RF_IF), rd_rn_rm),
9619 cCL(dvfep, e480120, 3, (RF, RF, RF_IF), rd_rn_rm),
9620 cCL(dvfem, e480140, 3, (RF, RF, RF_IF), rd_rn_rm),
9621 cCL(dvfez, e480160, 3, (RF, RF, RF_IF), rd_rn_rm),
9622
9623 cCL(rdfs, e500100, 3, (RF, RF, RF_IF), rd_rn_rm),
9624 cCL(rdfsp, e500120, 3, (RF, RF, RF_IF), rd_rn_rm),
9625 cCL(rdfsm, e500140, 3, (RF, RF, RF_IF), rd_rn_rm),
9626 cCL(rdfsz, e500160, 3, (RF, RF, RF_IF), rd_rn_rm),
9627 cCL(rdfd, e500180, 3, (RF, RF, RF_IF), rd_rn_rm),
9628 cCL(rdfdp, e5001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
9629 cCL(rdfdm, e5001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
9630 cCL(rdfdz, e5001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
9631 cCL(rdfe, e580100, 3, (RF, RF, RF_IF), rd_rn_rm),
9632 cCL(rdfep, e580120, 3, (RF, RF, RF_IF), rd_rn_rm),
9633 cCL(rdfem, e580140, 3, (RF, RF, RF_IF), rd_rn_rm),
9634 cCL(rdfez, e580160, 3, (RF, RF, RF_IF), rd_rn_rm),
9635
9636 cCL(pows, e600100, 3, (RF, RF, RF_IF), rd_rn_rm),
9637 cCL(powsp, e600120, 3, (RF, RF, RF_IF), rd_rn_rm),
9638 cCL(powsm, e600140, 3, (RF, RF, RF_IF), rd_rn_rm),
9639 cCL(powsz, e600160, 3, (RF, RF, RF_IF), rd_rn_rm),
9640 cCL(powd, e600180, 3, (RF, RF, RF_IF), rd_rn_rm),
9641 cCL(powdp, e6001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
9642 cCL(powdm, e6001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
9643 cCL(powdz, e6001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
9644 cCL(powe, e680100, 3, (RF, RF, RF_IF), rd_rn_rm),
9645 cCL(powep, e680120, 3, (RF, RF, RF_IF), rd_rn_rm),
9646 cCL(powem, e680140, 3, (RF, RF, RF_IF), rd_rn_rm),
9647 cCL(powez, e680160, 3, (RF, RF, RF_IF), rd_rn_rm),
9648
9649 cCL(rpws, e700100, 3, (RF, RF, RF_IF), rd_rn_rm),
9650 cCL(rpwsp, e700120, 3, (RF, RF, RF_IF), rd_rn_rm),
9651 cCL(rpwsm, e700140, 3, (RF, RF, RF_IF), rd_rn_rm),
9652 cCL(rpwsz, e700160, 3, (RF, RF, RF_IF), rd_rn_rm),
9653 cCL(rpwd, e700180, 3, (RF, RF, RF_IF), rd_rn_rm),
9654 cCL(rpwdp, e7001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
9655 cCL(rpwdm, e7001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
9656 cCL(rpwdz, e7001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
9657 cCL(rpwe, e780100, 3, (RF, RF, RF_IF), rd_rn_rm),
9658 cCL(rpwep, e780120, 3, (RF, RF, RF_IF), rd_rn_rm),
9659 cCL(rpwem, e780140, 3, (RF, RF, RF_IF), rd_rn_rm),
9660 cCL(rpwez, e780160, 3, (RF, RF, RF_IF), rd_rn_rm),
9661
9662 cCL(rmfs, e800100, 3, (RF, RF, RF_IF), rd_rn_rm),
9663 cCL(rmfsp, e800120, 3, (RF, RF, RF_IF), rd_rn_rm),
9664 cCL(rmfsm, e800140, 3, (RF, RF, RF_IF), rd_rn_rm),
9665 cCL(rmfsz, e800160, 3, (RF, RF, RF_IF), rd_rn_rm),
9666 cCL(rmfd, e800180, 3, (RF, RF, RF_IF), rd_rn_rm),
9667 cCL(rmfdp, e8001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
9668 cCL(rmfdm, e8001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
9669 cCL(rmfdz, e8001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
9670 cCL(rmfe, e880100, 3, (RF, RF, RF_IF), rd_rn_rm),
9671 cCL(rmfep, e880120, 3, (RF, RF, RF_IF), rd_rn_rm),
9672 cCL(rmfem, e880140, 3, (RF, RF, RF_IF), rd_rn_rm),
9673 cCL(rmfez, e880160, 3, (RF, RF, RF_IF), rd_rn_rm),
9674
9675 cCL(fmls, e900100, 3, (RF, RF, RF_IF), rd_rn_rm),
9676 cCL(fmlsp, e900120, 3, (RF, RF, RF_IF), rd_rn_rm),
9677 cCL(fmlsm, e900140, 3, (RF, RF, RF_IF), rd_rn_rm),
9678 cCL(fmlsz, e900160, 3, (RF, RF, RF_IF), rd_rn_rm),
9679 cCL(fmld, e900180, 3, (RF, RF, RF_IF), rd_rn_rm),
9680 cCL(fmldp, e9001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
9681 cCL(fmldm, e9001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
9682 cCL(fmldz, e9001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
9683 cCL(fmle, e980100, 3, (RF, RF, RF_IF), rd_rn_rm),
9684 cCL(fmlep, e980120, 3, (RF, RF, RF_IF), rd_rn_rm),
9685 cCL(fmlem, e980140, 3, (RF, RF, RF_IF), rd_rn_rm),
9686 cCL(fmlez, e980160, 3, (RF, RF, RF_IF), rd_rn_rm),
9687
9688 cCL(fdvs, ea00100, 3, (RF, RF, RF_IF), rd_rn_rm),
9689 cCL(fdvsp, ea00120, 3, (RF, RF, RF_IF), rd_rn_rm),
9690 cCL(fdvsm, ea00140, 3, (RF, RF, RF_IF), rd_rn_rm),
9691 cCL(fdvsz, ea00160, 3, (RF, RF, RF_IF), rd_rn_rm),
9692 cCL(fdvd, ea00180, 3, (RF, RF, RF_IF), rd_rn_rm),
9693 cCL(fdvdp, ea001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
9694 cCL(fdvdm, ea001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
9695 cCL(fdvdz, ea001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
9696 cCL(fdve, ea80100, 3, (RF, RF, RF_IF), rd_rn_rm),
9697 cCL(fdvep, ea80120, 3, (RF, RF, RF_IF), rd_rn_rm),
9698 cCL(fdvem, ea80140, 3, (RF, RF, RF_IF), rd_rn_rm),
9699 cCL(fdvez, ea80160, 3, (RF, RF, RF_IF), rd_rn_rm),
9700
9701 cCL(frds, eb00100, 3, (RF, RF, RF_IF), rd_rn_rm),
9702 cCL(frdsp, eb00120, 3, (RF, RF, RF_IF), rd_rn_rm),
9703 cCL(frdsm, eb00140, 3, (RF, RF, RF_IF), rd_rn_rm),
9704 cCL(frdsz, eb00160, 3, (RF, RF, RF_IF), rd_rn_rm),
9705 cCL(frdd, eb00180, 3, (RF, RF, RF_IF), rd_rn_rm),
9706 cCL(frddp, eb001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
9707 cCL(frddm, eb001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
9708 cCL(frddz, eb001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
9709 cCL(frde, eb80100, 3, (RF, RF, RF_IF), rd_rn_rm),
9710 cCL(frdep, eb80120, 3, (RF, RF, RF_IF), rd_rn_rm),
9711 cCL(frdem, eb80140, 3, (RF, RF, RF_IF), rd_rn_rm),
9712 cCL(frdez, eb80160, 3, (RF, RF, RF_IF), rd_rn_rm),
9713
9714 cCL(pols, ec00100, 3, (RF, RF, RF_IF), rd_rn_rm),
9715 cCL(polsp, ec00120, 3, (RF, RF, RF_IF), rd_rn_rm),
9716 cCL(polsm, ec00140, 3, (RF, RF, RF_IF), rd_rn_rm),
9717 cCL(polsz, ec00160, 3, (RF, RF, RF_IF), rd_rn_rm),
9718 cCL(pold, ec00180, 3, (RF, RF, RF_IF), rd_rn_rm),
9719 cCL(poldp, ec001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
9720 cCL(poldm, ec001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
9721 cCL(poldz, ec001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
9722 cCL(pole, ec80100, 3, (RF, RF, RF_IF), rd_rn_rm),
9723 cCL(polep, ec80120, 3, (RF, RF, RF_IF), rd_rn_rm),
9724 cCL(polem, ec80140, 3, (RF, RF, RF_IF), rd_rn_rm),
9725 cCL(polez, ec80160, 3, (RF, RF, RF_IF), rd_rn_rm),
9726
9727 cCE(cmf, e90f110, 2, (RF, RF_IF), fpa_cmp),
9728 C3E(cmfe, ed0f110, 2, (RF, RF_IF), fpa_cmp),
9729 cCE(cnf, eb0f110, 2, (RF, RF_IF), fpa_cmp),
9730 C3E(cnfe, ef0f110, 2, (RF, RF_IF), fpa_cmp),
9731
9732 cCL(flts, e000110, 2, (RF, RR), rn_rd),
9733 cCL(fltsp, e000130, 2, (RF, RR), rn_rd),
9734 cCL(fltsm, e000150, 2, (RF, RR), rn_rd),
9735 cCL(fltsz, e000170, 2, (RF, RR), rn_rd),
9736 cCL(fltd, e000190, 2, (RF, RR), rn_rd),
9737 cCL(fltdp, e0001b0, 2, (RF, RR), rn_rd),
9738 cCL(fltdm, e0001d0, 2, (RF, RR), rn_rd),
9739 cCL(fltdz, e0001f0, 2, (RF, RR), rn_rd),
9740 cCL(flte, e080110, 2, (RF, RR), rn_rd),
9741 cCL(fltep, e080130, 2, (RF, RR), rn_rd),
9742 cCL(fltem, e080150, 2, (RF, RR), rn_rd),
9743 cCL(fltez, e080170, 2, (RF, RR), rn_rd),
9744
9745 /* The implementation of the FIX instruction is broken on some
9746 assemblers, in that it accepts a precision specifier as well as a
9747 rounding specifier, despite the fact that this is meaningless.
9748 To be more compatible, we accept it as well, though of course it
9749 does not set any bits. */
9750 cCE(fix, e100110, 2, (RR, RF), rd_rm),
9751 cCL(fixp, e100130, 2, (RR, RF), rd_rm),
9752 cCL(fixm, e100150, 2, (RR, RF), rd_rm),
9753 cCL(fixz, e100170, 2, (RR, RF), rd_rm),
9754 cCL(fixsp, e100130, 2, (RR, RF), rd_rm),
9755 cCL(fixsm, e100150, 2, (RR, RF), rd_rm),
9756 cCL(fixsz, e100170, 2, (RR, RF), rd_rm),
9757 cCL(fixdp, e100130, 2, (RR, RF), rd_rm),
9758 cCL(fixdm, e100150, 2, (RR, RF), rd_rm),
9759 cCL(fixdz, e100170, 2, (RR, RF), rd_rm),
9760 cCL(fixep, e100130, 2, (RR, RF), rd_rm),
9761 cCL(fixem, e100150, 2, (RR, RF), rd_rm),
9762 cCL(fixez, e100170, 2, (RR, RF), rd_rm),
9763
9764 /* Instructions that were new with the real FPA, call them V2. */
9765 #undef ARM_VARIANT
9766 #define ARM_VARIANT &fpu_fpa_ext_v2
9767 cCE(lfm, c100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
9768 cCL(lfmfd, c900200, 3, (RF, I4b, ADDR), fpa_ldmstm),
9769 cCL(lfmea, d100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
9770 cCE(sfm, c000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
9771 cCL(sfmfd, d000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
9772 cCL(sfmea, c800200, 3, (RF, I4b, ADDR), fpa_ldmstm),
9773
9774 #undef ARM_VARIANT
9775 #define ARM_VARIANT &fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
9776 /* Moves and type conversions. */
9777 cCE(fcpys, eb00a40, 2, (RVS, RVS), vfp_sp_monadic),
9778 cCE(fmrs, e100a10, 2, (RR, RVS), vfp_reg_from_sp),
9779 cCE(fmsr, e000a10, 2, (RVS, RR), vfp_sp_from_reg),
9780 cCE(fmstat, ef1fa10, 0, (), noargs),
9781 cCE(fsitos, eb80ac0, 2, (RVS, RVS), vfp_sp_monadic),
9782 cCE(fuitos, eb80a40, 2, (RVS, RVS), vfp_sp_monadic),
9783 cCE(ftosis, ebd0a40, 2, (RVS, RVS), vfp_sp_monadic),
9784 cCE(ftosizs, ebd0ac0, 2, (RVS, RVS), vfp_sp_monadic),
9785 cCE(ftouis, ebc0a40, 2, (RVS, RVS), vfp_sp_monadic),
9786 cCE(ftouizs, ebc0ac0, 2, (RVS, RVS), vfp_sp_monadic),
9787 cCE(fmrx, ef00a10, 2, (RR, RVC), rd_rn),
9788 cCE(fmxr, ee00a10, 2, (RVC, RR), rn_rd),
9789
9790 /* Memory operations. */
9791 cCE(flds, d100a00, 2, (RVS, ADDR), vfp_sp_ldst),
9792 cCE(fsts, d000a00, 2, (RVS, ADDR), vfp_sp_ldst),
9793 cCE(fldmias, c900a00, 2, (RRw, VRSLST), vfp_sp_ldstmia),
9794 cCE(fldmfds, c900a00, 2, (RRw, VRSLST), vfp_sp_ldstmia),
9795 cCE(fldmdbs, d300a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb),
9796 cCE(fldmeas, d300a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb),
9797 cCE(fldmiax, c900b00, 2, (RRw, VRDLST), vfp_xp_ldstmia),
9798 cCE(fldmfdx, c900b00, 2, (RRw, VRDLST), vfp_xp_ldstmia),
9799 cCE(fldmdbx, d300b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb),
9800 cCE(fldmeax, d300b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb),
9801 cCE(fstmias, c800a00, 2, (RRw, VRSLST), vfp_sp_ldstmia),
9802 cCE(fstmeas, c800a00, 2, (RRw, VRSLST), vfp_sp_ldstmia),
9803 cCE(fstmdbs, d200a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb),
9804 cCE(fstmfds, d200a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb),
9805 cCE(fstmiax, c800b00, 2, (RRw, VRDLST), vfp_xp_ldstmia),
9806 cCE(fstmeax, c800b00, 2, (RRw, VRDLST), vfp_xp_ldstmia),
9807 cCE(fstmdbx, d200b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb),
9808 cCE(fstmfdx, d200b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb),
9809
9810 /* Monadic operations. */
9811 cCE(fabss, eb00ac0, 2, (RVS, RVS), vfp_sp_monadic),
9812 cCE(fnegs, eb10a40, 2, (RVS, RVS), vfp_sp_monadic),
9813 cCE(fsqrts, eb10ac0, 2, (RVS, RVS), vfp_sp_monadic),
9814
9815 /* Dyadic operations. */
9816 cCE(fadds, e300a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
9817 cCE(fsubs, e300a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
9818 cCE(fmuls, e200a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
9819 cCE(fdivs, e800a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
9820 cCE(fmacs, e000a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
9821 cCE(fmscs, e100a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
9822 cCE(fnmuls, e200a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
9823 cCE(fnmacs, e000a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
9824 cCE(fnmscs, e100a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
9825
9826 /* Comparisons. */
9827 cCE(fcmps, eb40a40, 2, (RVS, RVS), vfp_sp_monadic),
9828 cCE(fcmpzs, eb50a40, 1, (RVS), vfp_sp_compare_z),
9829 cCE(fcmpes, eb40ac0, 2, (RVS, RVS), vfp_sp_monadic),
9830 cCE(fcmpezs, eb50ac0, 1, (RVS), vfp_sp_compare_z),
9831
9832 #undef ARM_VARIANT
9833 #define ARM_VARIANT &fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
9834 /* Moves and type conversions. */
9835 cCE(fcpyd, eb00b40, 2, (RVD, RVD), rd_rm),
9836 cCE(fcvtds, eb70ac0, 2, (RVD, RVS), vfp_dp_sp_cvt),
9837 cCE(fcvtsd, eb70bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
9838 cCE(fmdhr, e200b10, 2, (RVD, RR), rn_rd),
9839 cCE(fmdlr, e000b10, 2, (RVD, RR), rn_rd),
9840 cCE(fmrdh, e300b10, 2, (RR, RVD), rd_rn),
9841 cCE(fmrdl, e100b10, 2, (RR, RVD), rd_rn),
9842 cCE(fsitod, eb80bc0, 2, (RVD, RVS), vfp_dp_sp_cvt),
9843 cCE(fuitod, eb80b40, 2, (RVD, RVS), vfp_dp_sp_cvt),
9844 cCE(ftosid, ebd0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
9845 cCE(ftosizd, ebd0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
9846 cCE(ftouid, ebc0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
9847 cCE(ftouizd, ebc0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
9848
9849 /* Memory operations. */
9850 cCE(fldd, d100b00, 2, (RVD, ADDR), vfp_dp_ldst),
9851 cCE(fstd, d000b00, 2, (RVD, ADDR), vfp_dp_ldst),
9852 cCE(fldmiad, c900b00, 2, (RRw, VRDLST), vfp_dp_ldstmia),
9853 cCE(fldmfdd, c900b00, 2, (RRw, VRDLST), vfp_dp_ldstmia),
9854 cCE(fldmdbd, d300b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb),
9855 cCE(fldmead, d300b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb),
9856 cCE(fstmiad, c800b00, 2, (RRw, VRDLST), vfp_dp_ldstmia),
9857 cCE(fstmead, c800b00, 2, (RRw, VRDLST), vfp_dp_ldstmia),
9858 cCE(fstmdbd, d200b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb),
9859 cCE(fstmfdd, d200b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb),
9860
9861 /* Monadic operations. */
9862 cCE(fabsd, eb00bc0, 2, (RVD, RVD), rd_rm),
9863 cCE(fnegd, eb10b40, 2, (RVD, RVD), rd_rm),
9864 cCE(fsqrtd, eb10bc0, 2, (RVD, RVD), rd_rm),
9865
9866 /* Dyadic operations. */
9867 cCE(faddd, e300b00, 3, (RVD, RVD, RVD), rd_rn_rm),
9868 cCE(fsubd, e300b40, 3, (RVD, RVD, RVD), rd_rn_rm),
9869 cCE(fmuld, e200b00, 3, (RVD, RVD, RVD), rd_rn_rm),
9870 cCE(fdivd, e800b00, 3, (RVD, RVD, RVD), rd_rn_rm),
9871 cCE(fmacd, e000b00, 3, (RVD, RVD, RVD), rd_rn_rm),
9872 cCE(fmscd, e100b00, 3, (RVD, RVD, RVD), rd_rn_rm),
9873 cCE(fnmuld, e200b40, 3, (RVD, RVD, RVD), rd_rn_rm),
9874 cCE(fnmacd, e000b40, 3, (RVD, RVD, RVD), rd_rn_rm),
9875 cCE(fnmscd, e100b40, 3, (RVD, RVD, RVD), rd_rn_rm),
9876
9877 /* Comparisons. */
9878 cCE(fcmpd, eb40b40, 2, (RVD, RVD), rd_rm),
9879 cCE(fcmpzd, eb50b40, 1, (RVD), rd),
9880 cCE(fcmped, eb40bc0, 2, (RVD, RVD), rd_rm),
9881 cCE(fcmpezd, eb50bc0, 1, (RVD), rd),
9882
9883 #undef ARM_VARIANT
9884 #define ARM_VARIANT &fpu_vfp_ext_v2
9885 cCE(fmsrr, c400a10, 3, (VRSLST, RR, RR), vfp_sp2_from_reg2),
9886 cCE(fmrrs, c500a10, 3, (RR, RR, VRSLST), vfp_reg2_from_sp2),
9887 cCE(fmdrr, c400b10, 3, (RVD, RR, RR), rm_rd_rn),
9888 cCE(fmrrd, c500b10, 3, (RR, RR, RVD), rd_rn_rm),
9889
9890 #undef ARM_VARIANT
9891 #define ARM_VARIANT &arm_cext_xscale /* Intel XScale extensions. */
9892 cCE(mia, e200010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
9893 cCE(miaph, e280010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
9894 cCE(miabb, e2c0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
9895 cCE(miabt, e2d0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
9896 cCE(miatb, e2e0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
9897 cCE(miatt, e2f0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
9898 cCE(mar, c400000, 3, (RXA, RRnpc, RRnpc), xsc_mar),
9899 cCE(mra, c500000, 3, (RRnpc, RRnpc, RXA), xsc_mra),
9900
9901 #undef ARM_VARIANT
9902 #define ARM_VARIANT &arm_cext_iwmmxt /* Intel Wireless MMX technology. */
9903 cCE(tandcb, e13f130, 1, (RR), iwmmxt_tandorc),
9904 cCE(tandch, e53f130, 1, (RR), iwmmxt_tandorc),
9905 cCE(tandcw, e93f130, 1, (RR), iwmmxt_tandorc),
9906 cCE(tbcstb, e400010, 2, (RIWR, RR), rn_rd),
9907 cCE(tbcsth, e400050, 2, (RIWR, RR), rn_rd),
9908 cCE(tbcstw, e400090, 2, (RIWR, RR), rn_rd),
9909 cCE(textrcb, e130170, 2, (RR, I7), iwmmxt_textrc),
9910 cCE(textrch, e530170, 2, (RR, I7), iwmmxt_textrc),
9911 cCE(textrcw, e930170, 2, (RR, I7), iwmmxt_textrc),
9912 cCE(textrmub, e100070, 3, (RR, RIWR, I7), iwmmxt_textrm),
9913 cCE(textrmuh, e500070, 3, (RR, RIWR, I7), iwmmxt_textrm),
9914 cCE(textrmuw, e900070, 3, (RR, RIWR, I7), iwmmxt_textrm),
9915 cCE(textrmsb, e100078, 3, (RR, RIWR, I7), iwmmxt_textrm),
9916 cCE(textrmsh, e500078, 3, (RR, RIWR, I7), iwmmxt_textrm),
9917 cCE(textrmsw, e900078, 3, (RR, RIWR, I7), iwmmxt_textrm),
9918 cCE(tinsrb, e600010, 3, (RIWR, RR, I7), iwmmxt_tinsr),
9919 cCE(tinsrh, e600050, 3, (RIWR, RR, I7), iwmmxt_tinsr),
9920 cCE(tinsrw, e600090, 3, (RIWR, RR, I7), iwmmxt_tinsr),
9921 cCE(tmcr, e000110, 2, (RIWC, RR), rn_rd),
9922 cCE(tmcrr, c400000, 3, (RIWR, RR, RR), rm_rd_rn),
9923 cCE(tmia, e200010, 3, (RIWR, RR, RR), iwmmxt_tmia),
9924 cCE(tmiaph, e280010, 3, (RIWR, RR, RR), iwmmxt_tmia),
9925 cCE(tmiabb, e2c0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
9926 cCE(tmiabt, e2d0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
9927 cCE(tmiatb, e2e0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
9928 cCE(tmiatt, e2f0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
9929 cCE(tmovmskb, e100030, 2, (RR, RIWR), rd_rn),
9930 cCE(tmovmskh, e500030, 2, (RR, RIWR), rd_rn),
9931 cCE(tmovmskw, e900030, 2, (RR, RIWR), rd_rn),
9932 cCE(tmrc, e100110, 2, (RR, RIWC), rd_rn),
9933 cCE(tmrrc, c500000, 3, (RR, RR, RIWR), rd_rn_rm),
9934 cCE(torcb, e13f150, 1, (RR), iwmmxt_tandorc),
9935 cCE(torch, e53f150, 1, (RR), iwmmxt_tandorc),
9936 cCE(torcw, e93f150, 1, (RR), iwmmxt_tandorc),
9937 cCE(waccb, e0001c0, 2, (RIWR, RIWR), rd_rn),
9938 cCE(wacch, e4001c0, 2, (RIWR, RIWR), rd_rn),
9939 cCE(waccw, e8001c0, 2, (RIWR, RIWR), rd_rn),
9940 cCE(waddbss, e300180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9941 cCE(waddb, e000180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9942 cCE(waddbus, e100180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9943 cCE(waddhss, e700180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9944 cCE(waddh, e400180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9945 cCE(waddhus, e500180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9946 cCE(waddwss, eb00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9947 cCE(waddw, e800180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9948 cCE(waddwus, e900180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9949 cCE(waligni, e000020, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_waligni),
9950 cCE(walignr0, e800020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9951 cCE(walignr1, e900020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9952 cCE(walignr2, ea00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9953 cCE(walignr3, eb00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9954 cCE(wand, e200000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9955 cCE(wandn, e300000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9956 cCE(wavg2b, e800000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9957 cCE(wavg2br, e900000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9958 cCE(wavg2h, ec00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9959 cCE(wavg2hr, ed00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9960 cCE(wcmpeqb, e000060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9961 cCE(wcmpeqh, e400060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9962 cCE(wcmpeqw, e800060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9963 cCE(wcmpgtub, e100060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9964 cCE(wcmpgtuh, e500060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9965 cCE(wcmpgtuw, e900060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9966 cCE(wcmpgtsb, e300060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9967 cCE(wcmpgtsh, e700060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9968 cCE(wcmpgtsw, eb00060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9969 cCE(wldrb, c100000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
9970 cCE(wldrh, c500000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
9971 cCE(wldrw, c100100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
9972 cCE(wldrd, c500100, 2, (RIWR, ADDR), iwmmxt_wldstd),
9973 cCE(wmacs, e600100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9974 cCE(wmacsz, e700100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9975 cCE(wmacu, e400100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9976 cCE(wmacuz, e500100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9977 cCE(wmadds, ea00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9978 cCE(wmaddu, e800100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9979 cCE(wmaxsb, e200160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9980 cCE(wmaxsh, e600160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9981 cCE(wmaxsw, ea00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9982 cCE(wmaxub, e000160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9983 cCE(wmaxuh, e400160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9984 cCE(wmaxuw, e800160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9985 cCE(wminsb, e300160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9986 cCE(wminsh, e700160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9987 cCE(wminsw, eb00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9988 cCE(wminub, e100160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9989 cCE(wminuh, e500160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9990 cCE(wminuw, e900160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9991 cCE(wmov, e000000, 2, (RIWR, RIWR), iwmmxt_wmov),
9992 cCE(wmulsm, e300100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9993 cCE(wmulsl, e200100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9994 cCE(wmulum, e100100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9995 cCE(wmulul, e000100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9996 cCE(wor, e000000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9997 cCE(wpackhss, e700080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9998 cCE(wpackhus, e500080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9999 cCE(wpackwss, eb00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10000 cCE(wpackwus, e900080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10001 cCE(wpackdss, ef00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10002 cCE(wpackdus, ed00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10003 cCE(wrorh, e700040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10004 cCE(wrorhg, e700148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
10005 cCE(wrorw, eb00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10006 cCE(wrorwg, eb00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
10007 cCE(wrord, ef00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10008 cCE(wrordg, ef00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
10009 cCE(wsadb, e000120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10010 cCE(wsadbz, e100120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10011 cCE(wsadh, e400120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10012 cCE(wsadhz, e500120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10013 cCE(wshufh, e0001e0, 3, (RIWR, RIWR, I255), iwmmxt_wshufh),
10014 cCE(wsllh, e500040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10015 cCE(wsllhg, e500148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
10016 cCE(wsllw, e900040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10017 cCE(wsllwg, e900148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
10018 cCE(wslld, ed00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10019 cCE(wslldg, ed00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
10020 cCE(wsrah, e400040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10021 cCE(wsrahg, e400148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
10022 cCE(wsraw, e800040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10023 cCE(wsrawg, e800148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
10024 cCE(wsrad, ec00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10025 cCE(wsradg, ec00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
10026 cCE(wsrlh, e600040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10027 cCE(wsrlhg, e600148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
10028 cCE(wsrlw, ea00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10029 cCE(wsrlwg, ea00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
10030 cCE(wsrld, ee00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10031 cCE(wsrldg, ee00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
10032 cCE(wstrb, c000000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
10033 cCE(wstrh, c400000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
10034 cCE(wstrw, c000100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
10035 cCE(wstrd, c400100, 2, (RIWR, ADDR), iwmmxt_wldstd),
10036 cCE(wsubbss, e3001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10037 cCE(wsubb, e0001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10038 cCE(wsubbus, e1001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10039 cCE(wsubhss, e7001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10040 cCE(wsubh, e4001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10041 cCE(wsubhus, e5001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10042 cCE(wsubwss, eb001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10043 cCE(wsubw, e8001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10044 cCE(wsubwus, e9001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10045 cCE(wunpckehub,e0000c0, 2, (RIWR, RIWR), rd_rn),
10046 cCE(wunpckehuh,e4000c0, 2, (RIWR, RIWR), rd_rn),
10047 cCE(wunpckehuw,e8000c0, 2, (RIWR, RIWR), rd_rn),
10048 cCE(wunpckehsb,e2000c0, 2, (RIWR, RIWR), rd_rn),
10049 cCE(wunpckehsh,e6000c0, 2, (RIWR, RIWR), rd_rn),
10050 cCE(wunpckehsw,ea000c0, 2, (RIWR, RIWR), rd_rn),
10051 cCE(wunpckihb, e1000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10052 cCE(wunpckihh, e5000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10053 cCE(wunpckihw, e9000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10054 cCE(wunpckelub,e0000e0, 2, (RIWR, RIWR), rd_rn),
10055 cCE(wunpckeluh,e4000e0, 2, (RIWR, RIWR), rd_rn),
10056 cCE(wunpckeluw,e8000e0, 2, (RIWR, RIWR), rd_rn),
10057 cCE(wunpckelsb,e2000e0, 2, (RIWR, RIWR), rd_rn),
10058 cCE(wunpckelsh,e6000e0, 2, (RIWR, RIWR), rd_rn),
10059 cCE(wunpckelsw,ea000e0, 2, (RIWR, RIWR), rd_rn),
10060 cCE(wunpckilb, e1000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10061 cCE(wunpckilh, e5000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10062 cCE(wunpckilw, e9000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10063 cCE(wxor, e100000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10064 cCE(wzero, e300000, 1, (RIWR), iwmmxt_wzero),
10065
10066 #undef ARM_VARIANT
10067 #define ARM_VARIANT &arm_cext_maverick /* Cirrus Maverick instructions. */
10068 cCE(cfldrs, c100400, 2, (RMF, ADDR), rd_cpaddr),
10069 cCE(cfldrd, c500400, 2, (RMD, ADDR), rd_cpaddr),
10070 cCE(cfldr32, c100500, 2, (RMFX, ADDR), rd_cpaddr),
10071 cCE(cfldr64, c500500, 2, (RMDX, ADDR), rd_cpaddr),
10072 cCE(cfstrs, c000400, 2, (RMF, ADDR), rd_cpaddr),
10073 cCE(cfstrd, c400400, 2, (RMD, ADDR), rd_cpaddr),
10074 cCE(cfstr32, c000500, 2, (RMFX, ADDR), rd_cpaddr),
10075 cCE(cfstr64, c400500, 2, (RMDX, ADDR), rd_cpaddr),
10076 cCE(cfmvsr, e000450, 2, (RMF, RR), rn_rd),
10077 cCE(cfmvrs, e100450, 2, (RR, RMF), rd_rn),
10078 cCE(cfmvdlr, e000410, 2, (RMD, RR), rn_rd),
10079 cCE(cfmvrdl, e100410, 2, (RR, RMD), rd_rn),
10080 cCE(cfmvdhr, e000430, 2, (RMD, RR), rn_rd),
10081 cCE(cfmvrdh, e100430, 2, (RR, RMD), rd_rn),
10082 cCE(cfmv64lr, e000510, 2, (RMDX, RR), rn_rd),
10083 cCE(cfmvr64l, e100510, 2, (RR, RMDX), rd_rn),
10084 cCE(cfmv64hr, e000530, 2, (RMDX, RR), rn_rd),
10085 cCE(cfmvr64h, e100530, 2, (RR, RMDX), rd_rn),
10086 cCE(cfmval32, e200440, 2, (RMAX, RMFX), rd_rn),
10087 cCE(cfmv32al, e100440, 2, (RMFX, RMAX), rd_rn),
10088 cCE(cfmvam32, e200460, 2, (RMAX, RMFX), rd_rn),
10089 cCE(cfmv32am, e100460, 2, (RMFX, RMAX), rd_rn),
10090 cCE(cfmvah32, e200480, 2, (RMAX, RMFX), rd_rn),
10091 cCE(cfmv32ah, e100480, 2, (RMFX, RMAX), rd_rn),
10092 cCE(cfmva32, e2004a0, 2, (RMAX, RMFX), rd_rn),
10093 cCE(cfmv32a, e1004a0, 2, (RMFX, RMAX), rd_rn),
10094 cCE(cfmva64, e2004c0, 2, (RMAX, RMDX), rd_rn),
10095 cCE(cfmv64a, e1004c0, 2, (RMDX, RMAX), rd_rn),
10096 cCE(cfmvsc32, e2004e0, 2, (RMDS, RMDX), mav_dspsc),
10097 cCE(cfmv32sc, e1004e0, 2, (RMDX, RMDS), rd),
10098 cCE(cfcpys, e000400, 2, (RMF, RMF), rd_rn),
10099 cCE(cfcpyd, e000420, 2, (RMD, RMD), rd_rn),
10100 cCE(cfcvtsd, e000460, 2, (RMD, RMF), rd_rn),
10101 cCE(cfcvtds, e000440, 2, (RMF, RMD), rd_rn),
10102 cCE(cfcvt32s, e000480, 2, (RMF, RMFX), rd_rn),
10103 cCE(cfcvt32d, e0004a0, 2, (RMD, RMFX), rd_rn),
10104 cCE(cfcvt64s, e0004c0, 2, (RMF, RMDX), rd_rn),
10105 cCE(cfcvt64d, e0004e0, 2, (RMD, RMDX), rd_rn),
10106 cCE(cfcvts32, e100580, 2, (RMFX, RMF), rd_rn),
10107 cCE(cfcvtd32, e1005a0, 2, (RMFX, RMD), rd_rn),
10108 cCE(cftruncs32,e1005c0, 2, (RMFX, RMF), rd_rn),
10109 cCE(cftruncd32,e1005e0, 2, (RMFX, RMD), rd_rn),
10110 cCE(cfrshl32, e000550, 3, (RMFX, RMFX, RR), mav_triple),
10111 cCE(cfrshl64, e000570, 3, (RMDX, RMDX, RR), mav_triple),
10112 cCE(cfsh32, e000500, 3, (RMFX, RMFX, I63s), mav_shift),
10113 cCE(cfsh64, e200500, 3, (RMDX, RMDX, I63s), mav_shift),
10114 cCE(cfcmps, e100490, 3, (RR, RMF, RMF), rd_rn_rm),
10115 cCE(cfcmpd, e1004b0, 3, (RR, RMD, RMD), rd_rn_rm),
10116 cCE(cfcmp32, e100590, 3, (RR, RMFX, RMFX), rd_rn_rm),
10117 cCE(cfcmp64, e1005b0, 3, (RR, RMDX, RMDX), rd_rn_rm),
10118 cCE(cfabss, e300400, 2, (RMF, RMF), rd_rn),
10119 cCE(cfabsd, e300420, 2, (RMD, RMD), rd_rn),
10120 cCE(cfnegs, e300440, 2, (RMF, RMF), rd_rn),
10121 cCE(cfnegd, e300460, 2, (RMD, RMD), rd_rn),
10122 cCE(cfadds, e300480, 3, (RMF, RMF, RMF), rd_rn_rm),
10123 cCE(cfaddd, e3004a0, 3, (RMD, RMD, RMD), rd_rn_rm),
10124 cCE(cfsubs, e3004c0, 3, (RMF, RMF, RMF), rd_rn_rm),
10125 cCE(cfsubd, e3004e0, 3, (RMD, RMD, RMD), rd_rn_rm),
10126 cCE(cfmuls, e100400, 3, (RMF, RMF, RMF), rd_rn_rm),
10127 cCE(cfmuld, e100420, 3, (RMD, RMD, RMD), rd_rn_rm),
10128 cCE(cfabs32, e300500, 2, (RMFX, RMFX), rd_rn),
10129 cCE(cfabs64, e300520, 2, (RMDX, RMDX), rd_rn),
10130 cCE(cfneg32, e300540, 2, (RMFX, RMFX), rd_rn),
10131 cCE(cfneg64, e300560, 2, (RMDX, RMDX), rd_rn),
10132 cCE(cfadd32, e300580, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
10133 cCE(cfadd64, e3005a0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
10134 cCE(cfsub32, e3005c0, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
10135 cCE(cfsub64, e3005e0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
10136 cCE(cfmul32, e100500, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
10137 cCE(cfmul64, e100520, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
10138 cCE(cfmac32, e100540, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
10139 cCE(cfmsc32, e100560, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
10140 cCE(cfmadd32, e000600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
10141 cCE(cfmsub32, e100600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
10142 cCE(cfmadda32, e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
10143 cCE(cfmsuba32, e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
10144 };
10145 #undef ARM_VARIANT
10146 #undef THUMB_VARIANT
10147 #undef TCE
10148 #undef TCM
10149 #undef TUE
10150 #undef TUF
10151 #undef TCC
10152 #undef cCE
10153 #undef cCL
10154 #undef C3E
10155 #undef CE
10156 #undef CM
10157 #undef UE
10158 #undef UF
10159 #undef UT
10160 #undef OPS0
10161 #undef OPS1
10162 #undef OPS2
10163 #undef OPS3
10164 #undef OPS4
10165 #undef OPS5
10166 #undef OPS6
10167 #undef do_0
10168 \f
10169 /* MD interface: bits in the object file. */
10170
10171 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
10172 for use in the a.out file, and stores them in the array pointed to by buf.
10173 This knows about the endian-ness of the target machine and does
10174 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
10175 2 (short) and 4 (long) Floating numbers are put out as a series of
10176 LITTLENUMS (shorts, here at least). */
10177
10178 void
10179 md_number_to_chars (char * buf, valueT val, int n)
10180 {
10181 if (target_big_endian)
10182 number_to_chars_bigendian (buf, val, n);
10183 else
10184 number_to_chars_littleendian (buf, val, n);
10185 }
10186
10187 static valueT
10188 md_chars_to_number (char * buf, int n)
10189 {
10190 valueT result = 0;
10191 unsigned char * where = (unsigned char *) buf;
10192
10193 if (target_big_endian)
10194 {
10195 while (n--)
10196 {
10197 result <<= 8;
10198 result |= (*where++ & 255);
10199 }
10200 }
10201 else
10202 {
10203 while (n--)
10204 {
10205 result <<= 8;
10206 result |= (where[n] & 255);
10207 }
10208 }
10209
10210 return result;
10211 }
10212
10213 /* MD interface: Sections. */
10214
10215 /* Estimate the size of a frag before relaxing. Assume everything fits in
10216 2 bytes. */
10217
10218 int
10219 md_estimate_size_before_relax (fragS * fragp,
10220 segT segtype ATTRIBUTE_UNUSED)
10221 {
10222 fragp->fr_var = 2;
10223 return 2;
10224 }
10225
10226 /* Convert a machine dependent frag. */
10227
10228 void
10229 md_convert_frag (bfd *abfd, segT asec ATTRIBUTE_UNUSED, fragS *fragp)
10230 {
10231 unsigned long insn;
10232 unsigned long old_op;
10233 char *buf;
10234 expressionS exp;
10235 fixS *fixp;
10236 int reloc_type;
10237 int pc_rel;
10238 int opcode;
10239
10240 buf = fragp->fr_literal + fragp->fr_fix;
10241
10242 old_op = bfd_get_16(abfd, buf);
10243 if (fragp->fr_symbol) {
10244 exp.X_op = O_symbol;
10245 exp.X_add_symbol = fragp->fr_symbol;
10246 } else {
10247 exp.X_op = O_constant;
10248 }
10249 exp.X_add_number = fragp->fr_offset;
10250 opcode = fragp->fr_subtype;
10251 switch (opcode)
10252 {
10253 case T_MNEM_ldr_pc:
10254 case T_MNEM_ldr_pc2:
10255 case T_MNEM_ldr_sp:
10256 case T_MNEM_str_sp:
10257 case T_MNEM_ldr:
10258 case T_MNEM_ldrb:
10259 case T_MNEM_ldrh:
10260 case T_MNEM_str:
10261 case T_MNEM_strb:
10262 case T_MNEM_strh:
10263 if (fragp->fr_var == 4)
10264 {
10265 insn = THUMB_OP32(opcode);
10266 if ((old_op >> 12) == 4 || (old_op >> 12) == 9)
10267 {
10268 insn |= (old_op & 0x700) << 4;
10269 }
10270 else
10271 {
10272 insn |= (old_op & 7) << 12;
10273 insn |= (old_op & 0x38) << 13;
10274 }
10275 insn |= 0x00000c00;
10276 put_thumb32_insn (buf, insn);
10277 reloc_type = BFD_RELOC_ARM_T32_OFFSET_IMM;
10278 }
10279 else
10280 {
10281 reloc_type = BFD_RELOC_ARM_THUMB_OFFSET;
10282 }
10283 pc_rel = (opcode == T_MNEM_ldr_pc2);
10284 break;
10285 case T_MNEM_adr:
10286 if (fragp->fr_var == 4)
10287 {
10288 insn = THUMB_OP32 (opcode);
10289 insn |= (old_op & 0xf0) << 4;
10290 put_thumb32_insn (buf, insn);
10291 reloc_type = BFD_RELOC_ARM_T32_ADD_PC12;
10292 }
10293 else
10294 {
10295 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
10296 exp.X_add_number -= 4;
10297 }
10298 pc_rel = 1;
10299 break;
10300 case T_MNEM_mov:
10301 case T_MNEM_movs:
10302 case T_MNEM_cmp:
10303 case T_MNEM_cmn:
10304 if (fragp->fr_var == 4)
10305 {
10306 int r0off = (opcode == T_MNEM_mov
10307 || opcode == T_MNEM_movs) ? 0 : 8;
10308 insn = THUMB_OP32 (opcode);
10309 insn = (insn & 0xe1ffffff) | 0x10000000;
10310 insn |= (old_op & 0x700) << r0off;
10311 put_thumb32_insn (buf, insn);
10312 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
10313 }
10314 else
10315 {
10316 reloc_type = BFD_RELOC_ARM_THUMB_IMM;
10317 }
10318 pc_rel = 0;
10319 break;
10320 case T_MNEM_b:
10321 if (fragp->fr_var == 4)
10322 {
10323 insn = THUMB_OP32(opcode);
10324 put_thumb32_insn (buf, insn);
10325 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH25;
10326 }
10327 else
10328 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH12;
10329 pc_rel = 1;
10330 break;
10331 case T_MNEM_bcond:
10332 if (fragp->fr_var == 4)
10333 {
10334 insn = THUMB_OP32(opcode);
10335 insn |= (old_op & 0xf00) << 14;
10336 put_thumb32_insn (buf, insn);
10337 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH20;
10338 }
10339 else
10340 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH9;
10341 pc_rel = 1;
10342 break;
10343 case T_MNEM_add_sp:
10344 case T_MNEM_add_pc:
10345 case T_MNEM_inc_sp:
10346 case T_MNEM_dec_sp:
10347 if (fragp->fr_var == 4)
10348 {
10349 /* ??? Choose between add and addw. */
10350 insn = THUMB_OP32 (opcode);
10351 insn |= (old_op & 0xf0) << 4;
10352 put_thumb32_insn (buf, insn);
10353 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
10354 }
10355 else
10356 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
10357 pc_rel = 0;
10358 break;
10359
10360 case T_MNEM_addi:
10361 case T_MNEM_addis:
10362 case T_MNEM_subi:
10363 case T_MNEM_subis:
10364 if (fragp->fr_var == 4)
10365 {
10366 insn = THUMB_OP32 (opcode);
10367 insn |= (old_op & 0xf0) << 4;
10368 insn |= (old_op & 0xf) << 16;
10369 put_thumb32_insn (buf, insn);
10370 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
10371 }
10372 else
10373 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
10374 pc_rel = 0;
10375 break;
10376 default:
10377 abort();
10378 }
10379 fixp = fix_new_exp (fragp, fragp->fr_fix, fragp->fr_var, &exp, pc_rel,
10380 reloc_type);
10381 fixp->fx_file = fragp->fr_file;
10382 fixp->fx_line = fragp->fr_line;
10383 fragp->fr_fix += fragp->fr_var;
10384 }
10385
10386 /* Return the size of a relaxable immediate operand instruction.
10387 SHIFT and SIZE specify the form of the allowable immediate. */
10388 static int
10389 relax_immediate (fragS *fragp, int size, int shift)
10390 {
10391 offsetT offset;
10392 offsetT mask;
10393 offsetT low;
10394
10395 /* ??? Should be able to do better than this. */
10396 if (fragp->fr_symbol)
10397 return 4;
10398
10399 low = (1 << shift) - 1;
10400 mask = (1 << (shift + size)) - (1 << shift);
10401 offset = fragp->fr_offset;
10402 /* Force misaligned offsets to 32-bit variant. */
10403 if (offset & low)
10404 return -4;
10405 if (offset & ~mask)
10406 return 4;
10407 return 2;
10408 }
10409
10410 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
10411 load. */
10412 static int
10413 relax_adr (fragS *fragp, asection *sec)
10414 {
10415 addressT addr;
10416 offsetT val;
10417
10418 /* Assume worst case for symbols not known to be in the same section. */
10419 if (!S_IS_DEFINED(fragp->fr_symbol)
10420 || sec != S_GET_SEGMENT (fragp->fr_symbol))
10421 return 4;
10422
10423 val = S_GET_VALUE(fragp->fr_symbol) + fragp->fr_offset;
10424 addr = fragp->fr_address + fragp->fr_fix;
10425 addr = (addr + 4) & ~3;
10426 /* Fix the insn as the 4-byte version if the target address is not
10427 sufficiently aligned. This is prevents an infinite loop when two
10428 instructions have contradictory range/alignment requirements. */
10429 if (val & 3)
10430 return -4;
10431 val -= addr;
10432 if (val < 0 || val > 1020)
10433 return 4;
10434 return 2;
10435 }
10436
10437 /* Return the size of a relaxable add/sub immediate instruction. */
10438 static int
10439 relax_addsub (fragS *fragp, asection *sec)
10440 {
10441 char *buf;
10442 int op;
10443
10444 buf = fragp->fr_literal + fragp->fr_fix;
10445 op = bfd_get_16(sec->owner, buf);
10446 if ((op & 0xf) == ((op >> 4) & 0xf))
10447 return relax_immediate (fragp, 8, 0);
10448 else
10449 return relax_immediate (fragp, 3, 0);
10450 }
10451
10452
10453 /* Return the size of a relaxable branch instruction. BITS is the
10454 size of the offset field in the narrow instruction. */
10455
10456 static int
10457 relax_branch (fragS *fragp, asection *sec, int bits)
10458 {
10459 addressT addr;
10460 offsetT val;
10461 offsetT limit;
10462
10463 /* Assume worst case for symbols not known to be in the same section. */
10464 if (!S_IS_DEFINED(fragp->fr_symbol)
10465 || sec != S_GET_SEGMENT (fragp->fr_symbol))
10466 return 4;
10467
10468 val = S_GET_VALUE(fragp->fr_symbol) + fragp->fr_offset;
10469 addr = fragp->fr_address + fragp->fr_fix + 4;
10470 val -= addr;
10471
10472 /* Offset is a signed value *2 */
10473 limit = 1 << bits;
10474 if (val >= limit || val < -limit)
10475 return 4;
10476 return 2;
10477 }
10478
10479
10480 /* Relax a machine dependent frag. This returns the amount by which
10481 the current size of the frag should change. */
10482
10483 int
10484 arm_relax_frag (asection *sec, fragS *fragp, long stretch ATTRIBUTE_UNUSED)
10485 {
10486 int oldsize;
10487 int newsize;
10488
10489 oldsize = fragp->fr_var;
10490 switch (fragp->fr_subtype)
10491 {
10492 case T_MNEM_ldr_pc2:
10493 newsize = relax_adr(fragp, sec);
10494 break;
10495 case T_MNEM_ldr_pc:
10496 case T_MNEM_ldr_sp:
10497 case T_MNEM_str_sp:
10498 newsize = relax_immediate(fragp, 8, 2);
10499 break;
10500 case T_MNEM_ldr:
10501 case T_MNEM_str:
10502 newsize = relax_immediate(fragp, 5, 2);
10503 break;
10504 case T_MNEM_ldrh:
10505 case T_MNEM_strh:
10506 newsize = relax_immediate(fragp, 5, 1);
10507 break;
10508 case T_MNEM_ldrb:
10509 case T_MNEM_strb:
10510 newsize = relax_immediate(fragp, 5, 0);
10511 break;
10512 case T_MNEM_adr:
10513 newsize = relax_adr(fragp, sec);
10514 break;
10515 case T_MNEM_mov:
10516 case T_MNEM_movs:
10517 case T_MNEM_cmp:
10518 case T_MNEM_cmn:
10519 newsize = relax_immediate(fragp, 8, 0);
10520 break;
10521 case T_MNEM_b:
10522 newsize = relax_branch(fragp, sec, 11);
10523 break;
10524 case T_MNEM_bcond:
10525 newsize = relax_branch(fragp, sec, 8);
10526 break;
10527 case T_MNEM_add_sp:
10528 case T_MNEM_add_pc:
10529 newsize = relax_immediate (fragp, 8, 2);
10530 break;
10531 case T_MNEM_inc_sp:
10532 case T_MNEM_dec_sp:
10533 newsize = relax_immediate (fragp, 7, 2);
10534 break;
10535 case T_MNEM_addi:
10536 case T_MNEM_addis:
10537 case T_MNEM_subi:
10538 case T_MNEM_subis:
10539 newsize = relax_addsub (fragp, sec);
10540 break;
10541 default:
10542 abort();
10543 }
10544 if (newsize < 0)
10545 {
10546 fragp->fr_var = -newsize;
10547 md_convert_frag (sec->owner, sec, fragp);
10548 frag_wane(fragp);
10549 return -(newsize + oldsize);
10550 }
10551 fragp->fr_var = newsize;
10552 return newsize - oldsize;
10553 }
10554
10555 /* Round up a section size to the appropriate boundary. */
10556
10557 valueT
10558 md_section_align (segT segment ATTRIBUTE_UNUSED,
10559 valueT size)
10560 {
10561 #ifdef OBJ_ELF
10562 return size;
10563 #else
10564 /* Round all sects to multiple of 4. */
10565 return (size + 3) & ~3;
10566 #endif
10567 }
10568
10569 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
10570 of an rs_align_code fragment. */
10571
10572 void
10573 arm_handle_align (fragS * fragP)
10574 {
10575 static char const arm_noop[4] = { 0x00, 0x00, 0xa0, 0xe1 };
10576 static char const thumb_noop[2] = { 0xc0, 0x46 };
10577 static char const arm_bigend_noop[4] = { 0xe1, 0xa0, 0x00, 0x00 };
10578 static char const thumb_bigend_noop[2] = { 0x46, 0xc0 };
10579
10580 int bytes, fix, noop_size;
10581 char * p;
10582 const char * noop;
10583
10584 if (fragP->fr_type != rs_align_code)
10585 return;
10586
10587 bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix;
10588 p = fragP->fr_literal + fragP->fr_fix;
10589 fix = 0;
10590
10591 if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE)
10592 bytes &= MAX_MEM_FOR_RS_ALIGN_CODE;
10593
10594 if (fragP->tc_frag_data)
10595 {
10596 if (target_big_endian)
10597 noop = thumb_bigend_noop;
10598 else
10599 noop = thumb_noop;
10600 noop_size = sizeof (thumb_noop);
10601 }
10602 else
10603 {
10604 if (target_big_endian)
10605 noop = arm_bigend_noop;
10606 else
10607 noop = arm_noop;
10608 noop_size = sizeof (arm_noop);
10609 }
10610
10611 if (bytes & (noop_size - 1))
10612 {
10613 fix = bytes & (noop_size - 1);
10614 memset (p, 0, fix);
10615 p += fix;
10616 bytes -= fix;
10617 }
10618
10619 while (bytes >= noop_size)
10620 {
10621 memcpy (p, noop, noop_size);
10622 p += noop_size;
10623 bytes -= noop_size;
10624 fix += noop_size;
10625 }
10626
10627 fragP->fr_fix += fix;
10628 fragP->fr_var = noop_size;
10629 }
10630
10631 /* Called from md_do_align. Used to create an alignment
10632 frag in a code section. */
10633
10634 void
10635 arm_frag_align_code (int n, int max)
10636 {
10637 char * p;
10638
10639 /* We assume that there will never be a requirement
10640 to support alignments greater than 32 bytes. */
10641 if (max > MAX_MEM_FOR_RS_ALIGN_CODE)
10642 as_fatal (_("alignments greater than 32 bytes not supported in .text sections."));
10643
10644 p = frag_var (rs_align_code,
10645 MAX_MEM_FOR_RS_ALIGN_CODE,
10646 1,
10647 (relax_substateT) max,
10648 (symbolS *) NULL,
10649 (offsetT) n,
10650 (char *) NULL);
10651 *p = 0;
10652 }
10653
10654 /* Perform target specific initialisation of a frag. */
10655
10656 void
10657 arm_init_frag (fragS * fragP)
10658 {
10659 /* Record whether this frag is in an ARM or a THUMB area. */
10660 fragP->tc_frag_data = thumb_mode;
10661 }
10662
10663 #ifdef OBJ_ELF
10664 /* When we change sections we need to issue a new mapping symbol. */
10665
10666 void
10667 arm_elf_change_section (void)
10668 {
10669 flagword flags;
10670 segment_info_type *seginfo;
10671
10672 /* Link an unlinked unwind index table section to the .text section. */
10673 if (elf_section_type (now_seg) == SHT_ARM_EXIDX
10674 && elf_linked_to_section (now_seg) == NULL)
10675 elf_linked_to_section (now_seg) = text_section;
10676
10677 if (!SEG_NORMAL (now_seg))
10678 return;
10679
10680 flags = bfd_get_section_flags (stdoutput, now_seg);
10681
10682 /* We can ignore sections that only contain debug info. */
10683 if ((flags & SEC_ALLOC) == 0)
10684 return;
10685
10686 seginfo = seg_info (now_seg);
10687 mapstate = seginfo->tc_segment_info_data.mapstate;
10688 marked_pr_dependency = seginfo->tc_segment_info_data.marked_pr_dependency;
10689 }
10690
10691 int
10692 arm_elf_section_type (const char * str, size_t len)
10693 {
10694 if (len == 5 && strncmp (str, "exidx", 5) == 0)
10695 return SHT_ARM_EXIDX;
10696
10697 return -1;
10698 }
10699 \f
10700 /* Code to deal with unwinding tables. */
10701
10702 static void add_unwind_adjustsp (offsetT);
10703
10704 /* Cenerate and deferred unwind frame offset. */
10705
10706 static void
10707 flush_pending_unwind (void)
10708 {
10709 offsetT offset;
10710
10711 offset = unwind.pending_offset;
10712 unwind.pending_offset = 0;
10713 if (offset != 0)
10714 add_unwind_adjustsp (offset);
10715 }
10716
10717 /* Add an opcode to this list for this function. Two-byte opcodes should
10718 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
10719 order. */
10720
10721 static void
10722 add_unwind_opcode (valueT op, int length)
10723 {
10724 /* Add any deferred stack adjustment. */
10725 if (unwind.pending_offset)
10726 flush_pending_unwind ();
10727
10728 unwind.sp_restored = 0;
10729
10730 if (unwind.opcode_count + length > unwind.opcode_alloc)
10731 {
10732 unwind.opcode_alloc += ARM_OPCODE_CHUNK_SIZE;
10733 if (unwind.opcodes)
10734 unwind.opcodes = xrealloc (unwind.opcodes,
10735 unwind.opcode_alloc);
10736 else
10737 unwind.opcodes = xmalloc (unwind.opcode_alloc);
10738 }
10739 while (length > 0)
10740 {
10741 length--;
10742 unwind.opcodes[unwind.opcode_count] = op & 0xff;
10743 op >>= 8;
10744 unwind.opcode_count++;
10745 }
10746 }
10747
10748 /* Add unwind opcodes to adjust the stack pointer. */
10749
10750 static void
10751 add_unwind_adjustsp (offsetT offset)
10752 {
10753 valueT op;
10754
10755 if (offset > 0x200)
10756 {
10757 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
10758 char bytes[5];
10759 int n;
10760 valueT o;
10761
10762 /* Long form: 0xb2, uleb128. */
10763 /* This might not fit in a word so add the individual bytes,
10764 remembering the list is built in reverse order. */
10765 o = (valueT) ((offset - 0x204) >> 2);
10766 if (o == 0)
10767 add_unwind_opcode (0, 1);
10768
10769 /* Calculate the uleb128 encoding of the offset. */
10770 n = 0;
10771 while (o)
10772 {
10773 bytes[n] = o & 0x7f;
10774 o >>= 7;
10775 if (o)
10776 bytes[n] |= 0x80;
10777 n++;
10778 }
10779 /* Add the insn. */
10780 for (; n; n--)
10781 add_unwind_opcode (bytes[n - 1], 1);
10782 add_unwind_opcode (0xb2, 1);
10783 }
10784 else if (offset > 0x100)
10785 {
10786 /* Two short opcodes. */
10787 add_unwind_opcode (0x3f, 1);
10788 op = (offset - 0x104) >> 2;
10789 add_unwind_opcode (op, 1);
10790 }
10791 else if (offset > 0)
10792 {
10793 /* Short opcode. */
10794 op = (offset - 4) >> 2;
10795 add_unwind_opcode (op, 1);
10796 }
10797 else if (offset < 0)
10798 {
10799 offset = -offset;
10800 while (offset > 0x100)
10801 {
10802 add_unwind_opcode (0x7f, 1);
10803 offset -= 0x100;
10804 }
10805 op = ((offset - 4) >> 2) | 0x40;
10806 add_unwind_opcode (op, 1);
10807 }
10808 }
10809
10810 /* Finish the list of unwind opcodes for this function. */
10811 static void
10812 finish_unwind_opcodes (void)
10813 {
10814 valueT op;
10815
10816 if (unwind.fp_used)
10817 {
10818 /* Adjust sp as neccessary. */
10819 unwind.pending_offset += unwind.fp_offset - unwind.frame_size;
10820 flush_pending_unwind ();
10821
10822 /* After restoring sp from the frame pointer. */
10823 op = 0x90 | unwind.fp_reg;
10824 add_unwind_opcode (op, 1);
10825 }
10826 else
10827 flush_pending_unwind ();
10828 }
10829
10830
10831 /* Start an exception table entry. If idx is nonzero this is an index table
10832 entry. */
10833
10834 static void
10835 start_unwind_section (const segT text_seg, int idx)
10836 {
10837 const char * text_name;
10838 const char * prefix;
10839 const char * prefix_once;
10840 const char * group_name;
10841 size_t prefix_len;
10842 size_t text_len;
10843 char * sec_name;
10844 size_t sec_name_len;
10845 int type;
10846 int flags;
10847 int linkonce;
10848
10849 if (idx)
10850 {
10851 prefix = ELF_STRING_ARM_unwind;
10852 prefix_once = ELF_STRING_ARM_unwind_once;
10853 type = SHT_ARM_EXIDX;
10854 }
10855 else
10856 {
10857 prefix = ELF_STRING_ARM_unwind_info;
10858 prefix_once = ELF_STRING_ARM_unwind_info_once;
10859 type = SHT_PROGBITS;
10860 }
10861
10862 text_name = segment_name (text_seg);
10863 if (streq (text_name, ".text"))
10864 text_name = "";
10865
10866 if (strncmp (text_name, ".gnu.linkonce.t.",
10867 strlen (".gnu.linkonce.t.")) == 0)
10868 {
10869 prefix = prefix_once;
10870 text_name += strlen (".gnu.linkonce.t.");
10871 }
10872
10873 prefix_len = strlen (prefix);
10874 text_len = strlen (text_name);
10875 sec_name_len = prefix_len + text_len;
10876 sec_name = xmalloc (sec_name_len + 1);
10877 memcpy (sec_name, prefix, prefix_len);
10878 memcpy (sec_name + prefix_len, text_name, text_len);
10879 sec_name[prefix_len + text_len] = '\0';
10880
10881 flags = SHF_ALLOC;
10882 linkonce = 0;
10883 group_name = 0;
10884
10885 /* Handle COMDAT group. */
10886 if (prefix != prefix_once && (text_seg->flags & SEC_LINK_ONCE) != 0)
10887 {
10888 group_name = elf_group_name (text_seg);
10889 if (group_name == NULL)
10890 {
10891 as_bad ("Group section `%s' has no group signature",
10892 segment_name (text_seg));
10893 ignore_rest_of_line ();
10894 return;
10895 }
10896 flags |= SHF_GROUP;
10897 linkonce = 1;
10898 }
10899
10900 obj_elf_change_section (sec_name, type, flags, 0, group_name, linkonce, 0);
10901
10902 /* Set the setion link for index tables. */
10903 if (idx)
10904 elf_linked_to_section (now_seg) = text_seg;
10905 }
10906
10907
10908 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
10909 personality routine data. Returns zero, or the index table value for
10910 and inline entry. */
10911
10912 static valueT
10913 create_unwind_entry (int have_data)
10914 {
10915 int size;
10916 addressT where;
10917 char *ptr;
10918 /* The current word of data. */
10919 valueT data;
10920 /* The number of bytes left in this word. */
10921 int n;
10922
10923 finish_unwind_opcodes ();
10924
10925 /* Remember the current text section. */
10926 unwind.saved_seg = now_seg;
10927 unwind.saved_subseg = now_subseg;
10928
10929 start_unwind_section (now_seg, 0);
10930
10931 if (unwind.personality_routine == NULL)
10932 {
10933 if (unwind.personality_index == -2)
10934 {
10935 if (have_data)
10936 as_bad (_("handerdata in cantunwind frame"));
10937 return 1; /* EXIDX_CANTUNWIND. */
10938 }
10939
10940 /* Use a default personality routine if none is specified. */
10941 if (unwind.personality_index == -1)
10942 {
10943 if (unwind.opcode_count > 3)
10944 unwind.personality_index = 1;
10945 else
10946 unwind.personality_index = 0;
10947 }
10948
10949 /* Space for the personality routine entry. */
10950 if (unwind.personality_index == 0)
10951 {
10952 if (unwind.opcode_count > 3)
10953 as_bad (_("too many unwind opcodes for personality routine 0"));
10954
10955 if (!have_data)
10956 {
10957 /* All the data is inline in the index table. */
10958 data = 0x80;
10959 n = 3;
10960 while (unwind.opcode_count > 0)
10961 {
10962 unwind.opcode_count--;
10963 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
10964 n--;
10965 }
10966
10967 /* Pad with "finish" opcodes. */
10968 while (n--)
10969 data = (data << 8) | 0xb0;
10970
10971 return data;
10972 }
10973 size = 0;
10974 }
10975 else
10976 /* We get two opcodes "free" in the first word. */
10977 size = unwind.opcode_count - 2;
10978 }
10979 else
10980 /* An extra byte is required for the opcode count. */
10981 size = unwind.opcode_count + 1;
10982
10983 size = (size + 3) >> 2;
10984 if (size > 0xff)
10985 as_bad (_("too many unwind opcodes"));
10986
10987 frag_align (2, 0, 0);
10988 record_alignment (now_seg, 2);
10989 unwind.table_entry = expr_build_dot ();
10990
10991 /* Allocate the table entry. */
10992 ptr = frag_more ((size << 2) + 4);
10993 where = frag_now_fix () - ((size << 2) + 4);
10994
10995 switch (unwind.personality_index)
10996 {
10997 case -1:
10998 /* ??? Should this be a PLT generating relocation? */
10999 /* Custom personality routine. */
11000 fix_new (frag_now, where, 4, unwind.personality_routine, 0, 1,
11001 BFD_RELOC_ARM_PREL31);
11002
11003 where += 4;
11004 ptr += 4;
11005
11006 /* Set the first byte to the number of additional words. */
11007 data = size - 1;
11008 n = 3;
11009 break;
11010
11011 /* ABI defined personality routines. */
11012 case 0:
11013 /* Three opcodes bytes are packed into the first word. */
11014 data = 0x80;
11015 n = 3;
11016 break;
11017
11018 case 1:
11019 case 2:
11020 /* The size and first two opcode bytes go in the first word. */
11021 data = ((0x80 + unwind.personality_index) << 8) | size;
11022 n = 2;
11023 break;
11024
11025 default:
11026 /* Should never happen. */
11027 abort ();
11028 }
11029
11030 /* Pack the opcodes into words (MSB first), reversing the list at the same
11031 time. */
11032 while (unwind.opcode_count > 0)
11033 {
11034 if (n == 0)
11035 {
11036 md_number_to_chars (ptr, data, 4);
11037 ptr += 4;
11038 n = 4;
11039 data = 0;
11040 }
11041 unwind.opcode_count--;
11042 n--;
11043 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
11044 }
11045
11046 /* Finish off the last word. */
11047 if (n < 4)
11048 {
11049 /* Pad with "finish" opcodes. */
11050 while (n--)
11051 data = (data << 8) | 0xb0;
11052
11053 md_number_to_chars (ptr, data, 4);
11054 }
11055
11056 if (!have_data)
11057 {
11058 /* Add an empty descriptor if there is no user-specified data. */
11059 ptr = frag_more (4);
11060 md_number_to_chars (ptr, 0, 4);
11061 }
11062
11063 return 0;
11064 }
11065
11066 /* Convert REGNAME to a DWARF-2 register number. */
11067
11068 int
11069 tc_arm_regname_to_dw2regnum (const char *regname)
11070 {
11071 int reg = arm_reg_parse ((char **) &regname, REG_TYPE_RN);
11072
11073 if (reg == FAIL)
11074 return -1;
11075
11076 return reg;
11077 }
11078
11079 /* Initialize the DWARF-2 unwind information for this procedure. */
11080
11081 void
11082 tc_arm_frame_initial_instructions (void)
11083 {
11084 cfi_add_CFA_def_cfa (REG_SP, 0);
11085 }
11086 #endif /* OBJ_ELF */
11087
11088
11089 /* MD interface: Symbol and relocation handling. */
11090
11091 /* Return the address within the segment that a PC-relative fixup is
11092 relative to. For ARM, PC-relative fixups applied to instructions
11093 are generally relative to the location of the fixup plus 8 bytes.
11094 Thumb branches are offset by 4, and Thumb loads relative to PC
11095 require special handling. */
11096
11097 long
11098 md_pcrel_from_section (fixS * fixP, segT seg)
11099 {
11100 offsetT base = fixP->fx_where + fixP->fx_frag->fr_address;
11101
11102 /* If this is pc-relative and we are going to emit a relocation
11103 then we just want to put out any pipeline compensation that the linker
11104 will need. Otherwise we want to use the calculated base. */
11105 if (fixP->fx_pcrel
11106 && ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg)
11107 || arm_force_relocation (fixP)))
11108 base = 0;
11109
11110 switch (fixP->fx_r_type)
11111 {
11112 /* PC relative addressing on the Thumb is slightly odd as the
11113 bottom two bits of the PC are forced to zero for the
11114 calculation. This happens *after* application of the
11115 pipeline offset. However, Thumb adrl already adjusts for
11116 this, so we need not do it again. */
11117 case BFD_RELOC_ARM_THUMB_ADD:
11118 return base & ~3;
11119
11120 case BFD_RELOC_ARM_THUMB_OFFSET:
11121 case BFD_RELOC_ARM_T32_OFFSET_IMM:
11122 case BFD_RELOC_ARM_T32_ADD_PC12:
11123 case BFD_RELOC_ARM_T32_CP_OFF_IMM:
11124 return (base + 4) & ~3;
11125
11126 /* Thumb branches are simply offset by +4. */
11127 case BFD_RELOC_THUMB_PCREL_BRANCH7:
11128 case BFD_RELOC_THUMB_PCREL_BRANCH9:
11129 case BFD_RELOC_THUMB_PCREL_BRANCH12:
11130 case BFD_RELOC_THUMB_PCREL_BRANCH20:
11131 case BFD_RELOC_THUMB_PCREL_BRANCH23:
11132 case BFD_RELOC_THUMB_PCREL_BRANCH25:
11133 case BFD_RELOC_THUMB_PCREL_BLX:
11134 return base + 4;
11135
11136 /* ARM mode branches are offset by +8. However, the Windows CE
11137 loader expects the relocation not to take this into account. */
11138 case BFD_RELOC_ARM_PCREL_BRANCH:
11139 case BFD_RELOC_ARM_PCREL_CALL:
11140 case BFD_RELOC_ARM_PCREL_JUMP:
11141 case BFD_RELOC_ARM_PCREL_BLX:
11142 case BFD_RELOC_ARM_PLT32:
11143 #ifdef TE_WINCE
11144 return base;
11145 #else
11146 return base + 8;
11147 #endif
11148
11149 /* ARM mode loads relative to PC are also offset by +8. Unlike
11150 branches, the Windows CE loader *does* expect the relocation
11151 to take this into account. */
11152 case BFD_RELOC_ARM_OFFSET_IMM:
11153 case BFD_RELOC_ARM_OFFSET_IMM8:
11154 case BFD_RELOC_ARM_HWLITERAL:
11155 case BFD_RELOC_ARM_LITERAL:
11156 case BFD_RELOC_ARM_CP_OFF_IMM:
11157 return base + 8;
11158
11159
11160 /* Other PC-relative relocations are un-offset. */
11161 default:
11162 return base;
11163 }
11164 }
11165
11166 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
11167 Otherwise we have no need to default values of symbols. */
11168
11169 symbolS *
11170 md_undefined_symbol (char * name ATTRIBUTE_UNUSED)
11171 {
11172 #ifdef OBJ_ELF
11173 if (name[0] == '_' && name[1] == 'G'
11174 && streq (name, GLOBAL_OFFSET_TABLE_NAME))
11175 {
11176 if (!GOT_symbol)
11177 {
11178 if (symbol_find (name))
11179 as_bad ("GOT already in the symbol table");
11180
11181 GOT_symbol = symbol_new (name, undefined_section,
11182 (valueT) 0, & zero_address_frag);
11183 }
11184
11185 return GOT_symbol;
11186 }
11187 #endif
11188
11189 return 0;
11190 }
11191
11192 /* Subroutine of md_apply_fix. Check to see if an immediate can be
11193 computed as two separate immediate values, added together. We
11194 already know that this value cannot be computed by just one ARM
11195 instruction. */
11196
11197 static unsigned int
11198 validate_immediate_twopart (unsigned int val,
11199 unsigned int * highpart)
11200 {
11201 unsigned int a;
11202 unsigned int i;
11203
11204 for (i = 0; i < 32; i += 2)
11205 if (((a = rotate_left (val, i)) & 0xff) != 0)
11206 {
11207 if (a & 0xff00)
11208 {
11209 if (a & ~ 0xffff)
11210 continue;
11211 * highpart = (a >> 8) | ((i + 24) << 7);
11212 }
11213 else if (a & 0xff0000)
11214 {
11215 if (a & 0xff000000)
11216 continue;
11217 * highpart = (a >> 16) | ((i + 16) << 7);
11218 }
11219 else
11220 {
11221 assert (a & 0xff000000);
11222 * highpart = (a >> 24) | ((i + 8) << 7);
11223 }
11224
11225 return (a & 0xff) | (i << 7);
11226 }
11227
11228 return FAIL;
11229 }
11230
11231 static int
11232 validate_offset_imm (unsigned int val, int hwse)
11233 {
11234 if ((hwse && val > 255) || val > 4095)
11235 return FAIL;
11236 return val;
11237 }
11238
11239 /* Subroutine of md_apply_fix. Do those data_ops which can take a
11240 negative immediate constant by altering the instruction. A bit of
11241 a hack really.
11242 MOV <-> MVN
11243 AND <-> BIC
11244 ADC <-> SBC
11245 by inverting the second operand, and
11246 ADD <-> SUB
11247 CMP <-> CMN
11248 by negating the second operand. */
11249
11250 static int
11251 negate_data_op (unsigned long * instruction,
11252 unsigned long value)
11253 {
11254 int op, new_inst;
11255 unsigned long negated, inverted;
11256
11257 negated = encode_arm_immediate (-value);
11258 inverted = encode_arm_immediate (~value);
11259
11260 op = (*instruction >> DATA_OP_SHIFT) & 0xf;
11261 switch (op)
11262 {
11263 /* First negates. */
11264 case OPCODE_SUB: /* ADD <-> SUB */
11265 new_inst = OPCODE_ADD;
11266 value = negated;
11267 break;
11268
11269 case OPCODE_ADD:
11270 new_inst = OPCODE_SUB;
11271 value = negated;
11272 break;
11273
11274 case OPCODE_CMP: /* CMP <-> CMN */
11275 new_inst = OPCODE_CMN;
11276 value = negated;
11277 break;
11278
11279 case OPCODE_CMN:
11280 new_inst = OPCODE_CMP;
11281 value = negated;
11282 break;
11283
11284 /* Now Inverted ops. */
11285 case OPCODE_MOV: /* MOV <-> MVN */
11286 new_inst = OPCODE_MVN;
11287 value = inverted;
11288 break;
11289
11290 case OPCODE_MVN:
11291 new_inst = OPCODE_MOV;
11292 value = inverted;
11293 break;
11294
11295 case OPCODE_AND: /* AND <-> BIC */
11296 new_inst = OPCODE_BIC;
11297 value = inverted;
11298 break;
11299
11300 case OPCODE_BIC:
11301 new_inst = OPCODE_AND;
11302 value = inverted;
11303 break;
11304
11305 case OPCODE_ADC: /* ADC <-> SBC */
11306 new_inst = OPCODE_SBC;
11307 value = inverted;
11308 break;
11309
11310 case OPCODE_SBC:
11311 new_inst = OPCODE_ADC;
11312 value = inverted;
11313 break;
11314
11315 /* We cannot do anything. */
11316 default:
11317 return FAIL;
11318 }
11319
11320 if (value == (unsigned) FAIL)
11321 return FAIL;
11322
11323 *instruction &= OPCODE_MASK;
11324 *instruction |= new_inst << DATA_OP_SHIFT;
11325 return value;
11326 }
11327
11328 /* Like negate_data_op, but for Thumb-2. */
11329
11330 static unsigned int
11331 thumb32_negate_data_op (offsetT *instruction, offsetT value)
11332 {
11333 int op, new_inst;
11334 int rd;
11335 offsetT negated, inverted;
11336
11337 negated = encode_thumb32_immediate (-value);
11338 inverted = encode_thumb32_immediate (~value);
11339
11340 rd = (*instruction >> 8) & 0xf;
11341 op = (*instruction >> T2_DATA_OP_SHIFT) & 0xf;
11342 switch (op)
11343 {
11344 /* ADD <-> SUB. Includes CMP <-> CMN. */
11345 case T2_OPCODE_SUB:
11346 new_inst = T2_OPCODE_ADD;
11347 value = negated;
11348 break;
11349
11350 case T2_OPCODE_ADD:
11351 new_inst = T2_OPCODE_SUB;
11352 value = negated;
11353 break;
11354
11355 /* ORR <-> ORN. Includes MOV <-> MVN. */
11356 case T2_OPCODE_ORR:
11357 new_inst = T2_OPCODE_ORN;
11358 value = inverted;
11359 break;
11360
11361 case T2_OPCODE_ORN:
11362 new_inst = T2_OPCODE_ORR;
11363 value = inverted;
11364 break;
11365
11366 /* AND <-> BIC. TST has no inverted equivalent. */
11367 case T2_OPCODE_AND:
11368 new_inst = T2_OPCODE_BIC;
11369 if (rd == 15)
11370 value = FAIL;
11371 else
11372 value = inverted;
11373 break;
11374
11375 case T2_OPCODE_BIC:
11376 new_inst = T2_OPCODE_AND;
11377 value = inverted;
11378 break;
11379
11380 /* ADC <-> SBC */
11381 case T2_OPCODE_ADC:
11382 new_inst = T2_OPCODE_SBC;
11383 value = inverted;
11384 break;
11385
11386 case T2_OPCODE_SBC:
11387 new_inst = T2_OPCODE_ADC;
11388 value = inverted;
11389 break;
11390
11391 /* We cannot do anything. */
11392 default:
11393 return FAIL;
11394 }
11395
11396 if (value == FAIL)
11397 return FAIL;
11398
11399 *instruction &= T2_OPCODE_MASK;
11400 *instruction |= new_inst << T2_DATA_OP_SHIFT;
11401 return value;
11402 }
11403
11404 /* Read a 32-bit thumb instruction from buf. */
11405 static unsigned long
11406 get_thumb32_insn (char * buf)
11407 {
11408 unsigned long insn;
11409 insn = md_chars_to_number (buf, THUMB_SIZE) << 16;
11410 insn |= md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
11411
11412 return insn;
11413 }
11414
11415 void
11416 md_apply_fix (fixS * fixP,
11417 valueT * valP,
11418 segT seg)
11419 {
11420 offsetT value = * valP;
11421 offsetT newval;
11422 unsigned int newimm;
11423 unsigned long temp;
11424 int sign;
11425 char * buf = fixP->fx_where + fixP->fx_frag->fr_literal;
11426
11427 assert (fixP->fx_r_type <= BFD_RELOC_UNUSED);
11428
11429 /* Note whether this will delete the relocation. */
11430 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
11431 fixP->fx_done = 1;
11432
11433 /* On a 64-bit host, silently truncate 'value' to 32 bits for
11434 consistency with the behavior on 32-bit hosts. Remember value
11435 for emit_reloc. */
11436 value &= 0xffffffff;
11437 value ^= 0x80000000;
11438 value -= 0x80000000;
11439
11440 *valP = value;
11441 fixP->fx_addnumber = value;
11442
11443 /* Same treatment for fixP->fx_offset. */
11444 fixP->fx_offset &= 0xffffffff;
11445 fixP->fx_offset ^= 0x80000000;
11446 fixP->fx_offset -= 0x80000000;
11447
11448 switch (fixP->fx_r_type)
11449 {
11450 case BFD_RELOC_NONE:
11451 /* This will need to go in the object file. */
11452 fixP->fx_done = 0;
11453 break;
11454
11455 case BFD_RELOC_ARM_IMMEDIATE:
11456 /* We claim that this fixup has been processed here,
11457 even if in fact we generate an error because we do
11458 not have a reloc for it, so tc_gen_reloc will reject it. */
11459 fixP->fx_done = 1;
11460
11461 if (fixP->fx_addsy
11462 && ! S_IS_DEFINED (fixP->fx_addsy))
11463 {
11464 as_bad_where (fixP->fx_file, fixP->fx_line,
11465 _("undefined symbol %s used as an immediate value"),
11466 S_GET_NAME (fixP->fx_addsy));
11467 break;
11468 }
11469
11470 newimm = encode_arm_immediate (value);
11471 temp = md_chars_to_number (buf, INSN_SIZE);
11472
11473 /* If the instruction will fail, see if we can fix things up by
11474 changing the opcode. */
11475 if (newimm == (unsigned int) FAIL
11476 && (newimm = negate_data_op (&temp, value)) == (unsigned int) FAIL)
11477 {
11478 as_bad_where (fixP->fx_file, fixP->fx_line,
11479 _("invalid constant (%lx) after fixup"),
11480 (unsigned long) value);
11481 break;
11482 }
11483
11484 newimm |= (temp & 0xfffff000);
11485 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
11486 break;
11487
11488 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
11489 {
11490 unsigned int highpart = 0;
11491 unsigned int newinsn = 0xe1a00000; /* nop. */
11492
11493 newimm = encode_arm_immediate (value);
11494 temp = md_chars_to_number (buf, INSN_SIZE);
11495
11496 /* If the instruction will fail, see if we can fix things up by
11497 changing the opcode. */
11498 if (newimm == (unsigned int) FAIL
11499 && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL)
11500 {
11501 /* No ? OK - try using two ADD instructions to generate
11502 the value. */
11503 newimm = validate_immediate_twopart (value, & highpart);
11504
11505 /* Yes - then make sure that the second instruction is
11506 also an add. */
11507 if (newimm != (unsigned int) FAIL)
11508 newinsn = temp;
11509 /* Still No ? Try using a negated value. */
11510 else if ((newimm = validate_immediate_twopart (- value, & highpart)) != (unsigned int) FAIL)
11511 temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT;
11512 /* Otherwise - give up. */
11513 else
11514 {
11515 as_bad_where (fixP->fx_file, fixP->fx_line,
11516 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
11517 (long) value);
11518 break;
11519 }
11520
11521 /* Replace the first operand in the 2nd instruction (which
11522 is the PC) with the destination register. We have
11523 already added in the PC in the first instruction and we
11524 do not want to do it again. */
11525 newinsn &= ~ 0xf0000;
11526 newinsn |= ((newinsn & 0x0f000) << 4);
11527 }
11528
11529 newimm |= (temp & 0xfffff000);
11530 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
11531
11532 highpart |= (newinsn & 0xfffff000);
11533 md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE);
11534 }
11535 break;
11536
11537 case BFD_RELOC_ARM_OFFSET_IMM:
11538 if (!fixP->fx_done && seg->use_rela_p)
11539 value = 0;
11540
11541 case BFD_RELOC_ARM_LITERAL:
11542 sign = value >= 0;
11543
11544 if (value < 0)
11545 value = - value;
11546
11547 if (validate_offset_imm (value, 0) == FAIL)
11548 {
11549 if (fixP->fx_r_type == BFD_RELOC_ARM_LITERAL)
11550 as_bad_where (fixP->fx_file, fixP->fx_line,
11551 _("invalid literal constant: pool needs to be closer"));
11552 else
11553 as_bad_where (fixP->fx_file, fixP->fx_line,
11554 _("bad immediate value for offset (%ld)"),
11555 (long) value);
11556 break;
11557 }
11558
11559 newval = md_chars_to_number (buf, INSN_SIZE);
11560 newval &= 0xff7ff000;
11561 newval |= value | (sign ? INDEX_UP : 0);
11562 md_number_to_chars (buf, newval, INSN_SIZE);
11563 break;
11564
11565 case BFD_RELOC_ARM_OFFSET_IMM8:
11566 case BFD_RELOC_ARM_HWLITERAL:
11567 sign = value >= 0;
11568
11569 if (value < 0)
11570 value = - value;
11571
11572 if (validate_offset_imm (value, 1) == FAIL)
11573 {
11574 if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL)
11575 as_bad_where (fixP->fx_file, fixP->fx_line,
11576 _("invalid literal constant: pool needs to be closer"));
11577 else
11578 as_bad (_("bad immediate value for half-word offset (%ld)"),
11579 (long) value);
11580 break;
11581 }
11582
11583 newval = md_chars_to_number (buf, INSN_SIZE);
11584 newval &= 0xff7ff0f0;
11585 newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0);
11586 md_number_to_chars (buf, newval, INSN_SIZE);
11587 break;
11588
11589 case BFD_RELOC_ARM_T32_OFFSET_U8:
11590 if (value < 0 || value > 1020 || value % 4 != 0)
11591 as_bad_where (fixP->fx_file, fixP->fx_line,
11592 _("bad immediate value for offset (%ld)"), (long) value);
11593 value /= 4;
11594
11595 newval = md_chars_to_number (buf+2, THUMB_SIZE);
11596 newval |= value;
11597 md_number_to_chars (buf+2, newval, THUMB_SIZE);
11598 break;
11599
11600 case BFD_RELOC_ARM_T32_OFFSET_IMM:
11601 /* This is a complicated relocation used for all varieties of Thumb32
11602 load/store instruction with immediate offset:
11603
11604 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
11605 *4, optional writeback(W)
11606 (doubleword load/store)
11607
11608 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
11609 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
11610 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
11611 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
11612 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
11613
11614 Uppercase letters indicate bits that are already encoded at
11615 this point. Lowercase letters are our problem. For the
11616 second block of instructions, the secondary opcode nybble
11617 (bits 8..11) is present, and bit 23 is zero, even if this is
11618 a PC-relative operation. */
11619 newval = md_chars_to_number (buf, THUMB_SIZE);
11620 newval <<= 16;
11621 newval |= md_chars_to_number (buf+THUMB_SIZE, THUMB_SIZE);
11622
11623 if ((newval & 0xf0000000) == 0xe0000000)
11624 {
11625 /* Doubleword load/store: 8-bit offset, scaled by 4. */
11626 if (value >= 0)
11627 newval |= (1 << 23);
11628 else
11629 value = -value;
11630 if (value % 4 != 0)
11631 {
11632 as_bad_where (fixP->fx_file, fixP->fx_line,
11633 _("offset not a multiple of 4"));
11634 break;
11635 }
11636 value /= 4;
11637 if (value > 0xff)
11638 {
11639 as_bad_where (fixP->fx_file, fixP->fx_line,
11640 _("offset out of range"));
11641 break;
11642 }
11643 newval &= ~0xff;
11644 }
11645 else if ((newval & 0x000f0000) == 0x000f0000)
11646 {
11647 /* PC-relative, 12-bit offset. */
11648 if (value >= 0)
11649 newval |= (1 << 23);
11650 else
11651 value = -value;
11652 if (value > 0xfff)
11653 {
11654 as_bad_where (fixP->fx_file, fixP->fx_line,
11655 _("offset out of range"));
11656 break;
11657 }
11658 newval &= ~0xfff;
11659 }
11660 else if ((newval & 0x00000100) == 0x00000100)
11661 {
11662 /* Writeback: 8-bit, +/- offset. */
11663 if (value >= 0)
11664 newval |= (1 << 9);
11665 else
11666 value = -value;
11667 if (value > 0xff)
11668 {
11669 as_bad_where (fixP->fx_file, fixP->fx_line,
11670 _("offset out of range"));
11671 break;
11672 }
11673 newval &= ~0xff;
11674 }
11675 else if ((newval & 0x00000f00) == 0x00000e00)
11676 {
11677 /* T-instruction: positive 8-bit offset. */
11678 if (value < 0 || value > 0xff)
11679 {
11680 as_bad_where (fixP->fx_file, fixP->fx_line,
11681 _("offset out of range"));
11682 break;
11683 }
11684 newval &= ~0xff;
11685 newval |= value;
11686 }
11687 else
11688 {
11689 /* Positive 12-bit or negative 8-bit offset. */
11690 int limit;
11691 if (value >= 0)
11692 {
11693 newval |= (1 << 23);
11694 limit = 0xfff;
11695 }
11696 else
11697 {
11698 value = -value;
11699 limit = 0xff;
11700 }
11701 if (value > limit)
11702 {
11703 as_bad_where (fixP->fx_file, fixP->fx_line,
11704 _("offset out of range"));
11705 break;
11706 }
11707 newval &= ~limit;
11708 }
11709
11710 newval |= value;
11711 md_number_to_chars (buf, (newval >> 16) & 0xffff, THUMB_SIZE);
11712 md_number_to_chars (buf + THUMB_SIZE, newval & 0xffff, THUMB_SIZE);
11713 break;
11714
11715 case BFD_RELOC_ARM_SHIFT_IMM:
11716 newval = md_chars_to_number (buf, INSN_SIZE);
11717 if (((unsigned long) value) > 32
11718 || (value == 32
11719 && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60)))
11720 {
11721 as_bad_where (fixP->fx_file, fixP->fx_line,
11722 _("shift expression is too large"));
11723 break;
11724 }
11725
11726 if (value == 0)
11727 /* Shifts of zero must be done as lsl. */
11728 newval &= ~0x60;
11729 else if (value == 32)
11730 value = 0;
11731 newval &= 0xfffff07f;
11732 newval |= (value & 0x1f) << 7;
11733 md_number_to_chars (buf, newval, INSN_SIZE);
11734 break;
11735
11736 case BFD_RELOC_ARM_T32_IMMEDIATE:
11737 case BFD_RELOC_ARM_T32_IMM12:
11738 case BFD_RELOC_ARM_T32_ADD_PC12:
11739 /* We claim that this fixup has been processed here,
11740 even if in fact we generate an error because we do
11741 not have a reloc for it, so tc_gen_reloc will reject it. */
11742 fixP->fx_done = 1;
11743
11744 if (fixP->fx_addsy
11745 && ! S_IS_DEFINED (fixP->fx_addsy))
11746 {
11747 as_bad_where (fixP->fx_file, fixP->fx_line,
11748 _("undefined symbol %s used as an immediate value"),
11749 S_GET_NAME (fixP->fx_addsy));
11750 break;
11751 }
11752
11753 newval = md_chars_to_number (buf, THUMB_SIZE);
11754 newval <<= 16;
11755 newval |= md_chars_to_number (buf+2, THUMB_SIZE);
11756
11757 /* FUTURE: Implement analogue of negate_data_op for T32. */
11758 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE)
11759 {
11760 newimm = encode_thumb32_immediate (value);
11761 if (newimm == (unsigned int) FAIL)
11762 newimm = thumb32_negate_data_op (&newval, value);
11763 }
11764 else
11765 {
11766 /* 12 bit immediate for addw/subw. */
11767 if (value < 0)
11768 {
11769 value = -value;
11770 newval ^= 0x00a00000;
11771 }
11772 if (value > 0xfff)
11773 newimm = (unsigned int) FAIL;
11774 else
11775 newimm = value;
11776 }
11777
11778 if (newimm == (unsigned int)FAIL)
11779 {
11780 as_bad_where (fixP->fx_file, fixP->fx_line,
11781 _("invalid constant (%lx) after fixup"),
11782 (unsigned long) value);
11783 break;
11784 }
11785
11786 newval |= (newimm & 0x800) << 15;
11787 newval |= (newimm & 0x700) << 4;
11788 newval |= (newimm & 0x0ff);
11789
11790 md_number_to_chars (buf, (valueT) ((newval >> 16) & 0xffff), THUMB_SIZE);
11791 md_number_to_chars (buf+2, (valueT) (newval & 0xffff), THUMB_SIZE);
11792 break;
11793
11794 case BFD_RELOC_ARM_SMC:
11795 if (((unsigned long) value) > 0xffff)
11796 as_bad_where (fixP->fx_file, fixP->fx_line,
11797 _("invalid smc expression"));
11798 newval = md_chars_to_number (buf, INSN_SIZE);
11799 newval |= (value & 0xf) | ((value & 0xfff0) << 4);
11800 md_number_to_chars (buf, newval, INSN_SIZE);
11801 break;
11802
11803 case BFD_RELOC_ARM_SWI:
11804 if (fixP->tc_fix_data != 0)
11805 {
11806 if (((unsigned long) value) > 0xff)
11807 as_bad_where (fixP->fx_file, fixP->fx_line,
11808 _("invalid swi expression"));
11809 newval = md_chars_to_number (buf, THUMB_SIZE);
11810 newval |= value;
11811 md_number_to_chars (buf, newval, THUMB_SIZE);
11812 }
11813 else
11814 {
11815 if (((unsigned long) value) > 0x00ffffff)
11816 as_bad_where (fixP->fx_file, fixP->fx_line,
11817 _("invalid swi expression"));
11818 newval = md_chars_to_number (buf, INSN_SIZE);
11819 newval |= value;
11820 md_number_to_chars (buf, newval, INSN_SIZE);
11821 }
11822 break;
11823
11824 case BFD_RELOC_ARM_MULTI:
11825 if (((unsigned long) value) > 0xffff)
11826 as_bad_where (fixP->fx_file, fixP->fx_line,
11827 _("invalid expression in load/store multiple"));
11828 newval = value | md_chars_to_number (buf, INSN_SIZE);
11829 md_number_to_chars (buf, newval, INSN_SIZE);
11830 break;
11831
11832 #ifdef OBJ_ELF
11833 case BFD_RELOC_ARM_PCREL_CALL:
11834 newval = md_chars_to_number (buf, INSN_SIZE);
11835 if ((newval & 0xf0000000) == 0xf0000000)
11836 temp = 1;
11837 else
11838 temp = 3;
11839 goto arm_branch_common;
11840
11841 case BFD_RELOC_ARM_PCREL_JUMP:
11842 case BFD_RELOC_ARM_PLT32:
11843 #endif
11844 case BFD_RELOC_ARM_PCREL_BRANCH:
11845 temp = 3;
11846 goto arm_branch_common;
11847
11848 case BFD_RELOC_ARM_PCREL_BLX:
11849 temp = 1;
11850 arm_branch_common:
11851 /* We are going to store value (shifted right by two) in the
11852 instruction, in a 24 bit, signed field. Bits 26 through 32 either
11853 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
11854 also be be clear. */
11855 if (value & temp)
11856 as_bad_where (fixP->fx_file, fixP->fx_line,
11857 _("misaligned branch destination"));
11858 if ((value & (offsetT)0xfe000000) != (offsetT)0
11859 && (value & (offsetT)0xfe000000) != (offsetT)0xfe000000)
11860 as_bad_where (fixP->fx_file, fixP->fx_line,
11861 _("branch out of range"));
11862
11863 if (fixP->fx_done || !seg->use_rela_p)
11864 {
11865 newval = md_chars_to_number (buf, INSN_SIZE);
11866 newval |= (value >> 2) & 0x00ffffff;
11867 md_number_to_chars (buf, newval, INSN_SIZE);
11868 }
11869 break;
11870
11871 case BFD_RELOC_THUMB_PCREL_BRANCH7: /* CZB */
11872 /* CZB can only branch forward. */
11873 if (value & ~0x7e)
11874 as_bad_where (fixP->fx_file, fixP->fx_line,
11875 _("branch out of range"));
11876
11877 if (fixP->fx_done || !seg->use_rela_p)
11878 {
11879 newval = md_chars_to_number (buf, THUMB_SIZE);
11880 newval |= ((value & 0x2e) << 2) | ((value & 0x40) << 3);
11881 md_number_to_chars (buf, newval, THUMB_SIZE);
11882 }
11883 break;
11884
11885 case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */
11886 if ((value & ~0xff) && ((value & ~0xff) != ~0xff))
11887 as_bad_where (fixP->fx_file, fixP->fx_line,
11888 _("branch out of range"));
11889
11890 if (fixP->fx_done || !seg->use_rela_p)
11891 {
11892 newval = md_chars_to_number (buf, THUMB_SIZE);
11893 newval |= (value & 0x1ff) >> 1;
11894 md_number_to_chars (buf, newval, THUMB_SIZE);
11895 }
11896 break;
11897
11898 case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch. */
11899 if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff))
11900 as_bad_where (fixP->fx_file, fixP->fx_line,
11901 _("branch out of range"));
11902
11903 if (fixP->fx_done || !seg->use_rela_p)
11904 {
11905 newval = md_chars_to_number (buf, THUMB_SIZE);
11906 newval |= (value & 0xfff) >> 1;
11907 md_number_to_chars (buf, newval, THUMB_SIZE);
11908 }
11909 break;
11910
11911 case BFD_RELOC_THUMB_PCREL_BRANCH20:
11912 if ((value & ~0x1fffff) && ((value & ~0x1fffff) != ~0x1fffff))
11913 as_bad_where (fixP->fx_file, fixP->fx_line,
11914 _("conditional branch out of range"));
11915
11916 if (fixP->fx_done || !seg->use_rela_p)
11917 {
11918 offsetT newval2;
11919 addressT S, J1, J2, lo, hi;
11920
11921 S = (value & 0x00100000) >> 20;
11922 J2 = (value & 0x00080000) >> 19;
11923 J1 = (value & 0x00040000) >> 18;
11924 hi = (value & 0x0003f000) >> 12;
11925 lo = (value & 0x00000ffe) >> 1;
11926
11927 newval = md_chars_to_number (buf, THUMB_SIZE);
11928 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
11929 newval |= (S << 10) | hi;
11930 newval2 |= (J1 << 13) | (J2 << 11) | lo;
11931 md_number_to_chars (buf, newval, THUMB_SIZE);
11932 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
11933 }
11934 break;
11935
11936 case BFD_RELOC_THUMB_PCREL_BLX:
11937 case BFD_RELOC_THUMB_PCREL_BRANCH23:
11938 if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff))
11939 as_bad_where (fixP->fx_file, fixP->fx_line,
11940 _("branch out of range"));
11941
11942 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
11943 /* For a BLX instruction, make sure that the relocation is rounded up
11944 to a word boundary. This follows the semantics of the instruction
11945 which specifies that bit 1 of the target address will come from bit
11946 1 of the base address. */
11947 value = (value + 1) & ~ 1;
11948
11949 if (fixP->fx_done || !seg->use_rela_p)
11950 {
11951 offsetT newval2;
11952
11953 newval = md_chars_to_number (buf, THUMB_SIZE);
11954 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
11955 newval |= (value & 0x7fffff) >> 12;
11956 newval2 |= (value & 0xfff) >> 1;
11957 md_number_to_chars (buf, newval, THUMB_SIZE);
11958 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
11959 }
11960 break;
11961
11962 case BFD_RELOC_THUMB_PCREL_BRANCH25:
11963 if ((value & ~0x1ffffff) && ((value & ~0x1ffffff) != ~0x1ffffff))
11964 as_bad_where (fixP->fx_file, fixP->fx_line,
11965 _("branch out of range"));
11966
11967 if (fixP->fx_done || !seg->use_rela_p)
11968 {
11969 offsetT newval2;
11970 addressT S, I1, I2, lo, hi;
11971
11972 S = (value & 0x01000000) >> 24;
11973 I1 = (value & 0x00800000) >> 23;
11974 I2 = (value & 0x00400000) >> 22;
11975 hi = (value & 0x003ff000) >> 12;
11976 lo = (value & 0x00000ffe) >> 1;
11977
11978 I1 = !(I1 ^ S);
11979 I2 = !(I2 ^ S);
11980
11981 newval = md_chars_to_number (buf, THUMB_SIZE);
11982 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
11983 newval |= (S << 10) | hi;
11984 newval2 |= (I1 << 13) | (I2 << 11) | lo;
11985 md_number_to_chars (buf, newval, THUMB_SIZE);
11986 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
11987 }
11988 break;
11989
11990 case BFD_RELOC_8:
11991 if (fixP->fx_done || !seg->use_rela_p)
11992 md_number_to_chars (buf, value, 1);
11993 break;
11994
11995 case BFD_RELOC_16:
11996 if (fixP->fx_done || !seg->use_rela_p)
11997 md_number_to_chars (buf, value, 2);
11998 break;
11999
12000 #ifdef OBJ_ELF
12001 case BFD_RELOC_ARM_TLS_GD32:
12002 case BFD_RELOC_ARM_TLS_LE32:
12003 case BFD_RELOC_ARM_TLS_IE32:
12004 case BFD_RELOC_ARM_TLS_LDM32:
12005 case BFD_RELOC_ARM_TLS_LDO32:
12006 S_SET_THREAD_LOCAL (fixP->fx_addsy);
12007 /* fall through */
12008
12009 case BFD_RELOC_ARM_GOT32:
12010 case BFD_RELOC_ARM_GOTOFF:
12011 case BFD_RELOC_ARM_TARGET2:
12012 if (fixP->fx_done || !seg->use_rela_p)
12013 md_number_to_chars (buf, 0, 4);
12014 break;
12015 #endif
12016
12017 case BFD_RELOC_RVA:
12018 case BFD_RELOC_32:
12019 case BFD_RELOC_ARM_TARGET1:
12020 case BFD_RELOC_ARM_ROSEGREL32:
12021 case BFD_RELOC_ARM_SBREL32:
12022 case BFD_RELOC_32_PCREL:
12023 if (fixP->fx_done || !seg->use_rela_p)
12024 md_number_to_chars (buf, value, 4);
12025 break;
12026
12027 #ifdef OBJ_ELF
12028 case BFD_RELOC_ARM_PREL31:
12029 if (fixP->fx_done || !seg->use_rela_p)
12030 {
12031 newval = md_chars_to_number (buf, 4) & 0x80000000;
12032 if ((value ^ (value >> 1)) & 0x40000000)
12033 {
12034 as_bad_where (fixP->fx_file, fixP->fx_line,
12035 _("rel31 relocation overflow"));
12036 }
12037 newval |= value & 0x7fffffff;
12038 md_number_to_chars (buf, newval, 4);
12039 }
12040 break;
12041 #endif
12042
12043 case BFD_RELOC_ARM_CP_OFF_IMM:
12044 case BFD_RELOC_ARM_T32_CP_OFF_IMM:
12045 if (value < -1023 || value > 1023 || (value & 3))
12046 as_bad_where (fixP->fx_file, fixP->fx_line,
12047 _("co-processor offset out of range"));
12048 cp_off_common:
12049 sign = value >= 0;
12050 if (value < 0)
12051 value = -value;
12052 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
12053 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
12054 newval = md_chars_to_number (buf, INSN_SIZE);
12055 else
12056 newval = get_thumb32_insn (buf);
12057 newval &= 0xff7fff00;
12058 newval |= (value >> 2) | (sign ? INDEX_UP : 0);
12059 if (value == 0)
12060 newval &= ~WRITE_BACK;
12061 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
12062 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
12063 md_number_to_chars (buf, newval, INSN_SIZE);
12064 else
12065 put_thumb32_insn (buf, newval);
12066 break;
12067
12068 case BFD_RELOC_ARM_CP_OFF_IMM_S2:
12069 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2:
12070 if (value < -255 || value > 255)
12071 as_bad_where (fixP->fx_file, fixP->fx_line,
12072 _("co-processor offset out of range"));
12073 goto cp_off_common;
12074
12075 case BFD_RELOC_ARM_THUMB_OFFSET:
12076 newval = md_chars_to_number (buf, THUMB_SIZE);
12077 /* Exactly what ranges, and where the offset is inserted depends
12078 on the type of instruction, we can establish this from the
12079 top 4 bits. */
12080 switch (newval >> 12)
12081 {
12082 case 4: /* PC load. */
12083 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
12084 forced to zero for these loads; md_pcrel_from has already
12085 compensated for this. */
12086 if (value & 3)
12087 as_bad_where (fixP->fx_file, fixP->fx_line,
12088 _("invalid offset, target not word aligned (0x%08lX)"),
12089 (((unsigned long) fixP->fx_frag->fr_address
12090 + (unsigned long) fixP->fx_where) & ~3)
12091 + (unsigned long) value);
12092
12093 if (value & ~0x3fc)
12094 as_bad_where (fixP->fx_file, fixP->fx_line,
12095 _("invalid offset, value too big (0x%08lX)"),
12096 (long) value);
12097
12098 newval |= value >> 2;
12099 break;
12100
12101 case 9: /* SP load/store. */
12102 if (value & ~0x3fc)
12103 as_bad_where (fixP->fx_file, fixP->fx_line,
12104 _("invalid offset, value too big (0x%08lX)"),
12105 (long) value);
12106 newval |= value >> 2;
12107 break;
12108
12109 case 6: /* Word load/store. */
12110 if (value & ~0x7c)
12111 as_bad_where (fixP->fx_file, fixP->fx_line,
12112 _("invalid offset, value too big (0x%08lX)"),
12113 (long) value);
12114 newval |= value << 4; /* 6 - 2. */
12115 break;
12116
12117 case 7: /* Byte load/store. */
12118 if (value & ~0x1f)
12119 as_bad_where (fixP->fx_file, fixP->fx_line,
12120 _("invalid offset, value too big (0x%08lX)"),
12121 (long) value);
12122 newval |= value << 6;
12123 break;
12124
12125 case 8: /* Halfword load/store. */
12126 if (value & ~0x3e)
12127 as_bad_where (fixP->fx_file, fixP->fx_line,
12128 _("invalid offset, value too big (0x%08lX)"),
12129 (long) value);
12130 newval |= value << 5; /* 6 - 1. */
12131 break;
12132
12133 default:
12134 as_bad_where (fixP->fx_file, fixP->fx_line,
12135 "Unable to process relocation for thumb opcode: %lx",
12136 (unsigned long) newval);
12137 break;
12138 }
12139 md_number_to_chars (buf, newval, THUMB_SIZE);
12140 break;
12141
12142 case BFD_RELOC_ARM_THUMB_ADD:
12143 /* This is a complicated relocation, since we use it for all of
12144 the following immediate relocations:
12145
12146 3bit ADD/SUB
12147 8bit ADD/SUB
12148 9bit ADD/SUB SP word-aligned
12149 10bit ADD PC/SP word-aligned
12150
12151 The type of instruction being processed is encoded in the
12152 instruction field:
12153
12154 0x8000 SUB
12155 0x00F0 Rd
12156 0x000F Rs
12157 */
12158 newval = md_chars_to_number (buf, THUMB_SIZE);
12159 {
12160 int rd = (newval >> 4) & 0xf;
12161 int rs = newval & 0xf;
12162 int subtract = !!(newval & 0x8000);
12163
12164 /* Check for HI regs, only very restricted cases allowed:
12165 Adjusting SP, and using PC or SP to get an address. */
12166 if ((rd > 7 && (rd != REG_SP || rs != REG_SP))
12167 || (rs > 7 && rs != REG_SP && rs != REG_PC))
12168 as_bad_where (fixP->fx_file, fixP->fx_line,
12169 _("invalid Hi register with immediate"));
12170
12171 /* If value is negative, choose the opposite instruction. */
12172 if (value < 0)
12173 {
12174 value = -value;
12175 subtract = !subtract;
12176 if (value < 0)
12177 as_bad_where (fixP->fx_file, fixP->fx_line,
12178 _("immediate value out of range"));
12179 }
12180
12181 if (rd == REG_SP)
12182 {
12183 if (value & ~0x1fc)
12184 as_bad_where (fixP->fx_file, fixP->fx_line,
12185 _("invalid immediate for stack address calculation"));
12186 newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST;
12187 newval |= value >> 2;
12188 }
12189 else if (rs == REG_PC || rs == REG_SP)
12190 {
12191 if (subtract || value & ~0x3fc)
12192 as_bad_where (fixP->fx_file, fixP->fx_line,
12193 _("invalid immediate for address calculation (value = 0x%08lX)"),
12194 (unsigned long) value);
12195 newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP);
12196 newval |= rd << 8;
12197 newval |= value >> 2;
12198 }
12199 else if (rs == rd)
12200 {
12201 if (value & ~0xff)
12202 as_bad_where (fixP->fx_file, fixP->fx_line,
12203 _("immediate value out of range"));
12204 newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8;
12205 newval |= (rd << 8) | value;
12206 }
12207 else
12208 {
12209 if (value & ~0x7)
12210 as_bad_where (fixP->fx_file, fixP->fx_line,
12211 _("immediate value out of range"));
12212 newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3;
12213 newval |= rd | (rs << 3) | (value << 6);
12214 }
12215 }
12216 md_number_to_chars (buf, newval, THUMB_SIZE);
12217 break;
12218
12219 case BFD_RELOC_ARM_THUMB_IMM:
12220 newval = md_chars_to_number (buf, THUMB_SIZE);
12221 if (value < 0 || value > 255)
12222 as_bad_where (fixP->fx_file, fixP->fx_line,
12223 _("invalid immediate: %ld is too large"),
12224 (long) value);
12225 newval |= value;
12226 md_number_to_chars (buf, newval, THUMB_SIZE);
12227 break;
12228
12229 case BFD_RELOC_ARM_THUMB_SHIFT:
12230 /* 5bit shift value (0..32). LSL cannot take 32. */
12231 newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf83f;
12232 temp = newval & 0xf800;
12233 if (value < 0 || value > 32 || (value == 32 && temp == T_OPCODE_LSL_I))
12234 as_bad_where (fixP->fx_file, fixP->fx_line,
12235 _("invalid shift value: %ld"), (long) value);
12236 /* Shifts of zero must be encoded as LSL. */
12237 if (value == 0)
12238 newval = (newval & 0x003f) | T_OPCODE_LSL_I;
12239 /* Shifts of 32 are encoded as zero. */
12240 else if (value == 32)
12241 value = 0;
12242 newval |= value << 6;
12243 md_number_to_chars (buf, newval, THUMB_SIZE);
12244 break;
12245
12246 case BFD_RELOC_VTABLE_INHERIT:
12247 case BFD_RELOC_VTABLE_ENTRY:
12248 fixP->fx_done = 0;
12249 return;
12250
12251 case BFD_RELOC_UNUSED:
12252 default:
12253 as_bad_where (fixP->fx_file, fixP->fx_line,
12254 _("bad relocation fixup type (%d)"), fixP->fx_r_type);
12255 }
12256 }
12257
12258 /* Translate internal representation of relocation info to BFD target
12259 format. */
12260
12261 arelent *
12262 tc_gen_reloc (asection *section, fixS *fixp)
12263 {
12264 arelent * reloc;
12265 bfd_reloc_code_real_type code;
12266
12267 reloc = xmalloc (sizeof (arelent));
12268
12269 reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
12270 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
12271 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
12272
12273 if (fixp->fx_pcrel)
12274 {
12275 if (section->use_rela_p)
12276 fixp->fx_offset -= md_pcrel_from_section (fixp, section);
12277 else
12278 fixp->fx_offset = reloc->address;
12279 }
12280 reloc->addend = fixp->fx_offset;
12281
12282 switch (fixp->fx_r_type)
12283 {
12284 case BFD_RELOC_8:
12285 if (fixp->fx_pcrel)
12286 {
12287 code = BFD_RELOC_8_PCREL;
12288 break;
12289 }
12290
12291 case BFD_RELOC_16:
12292 if (fixp->fx_pcrel)
12293 {
12294 code = BFD_RELOC_16_PCREL;
12295 break;
12296 }
12297
12298 case BFD_RELOC_32:
12299 if (fixp->fx_pcrel)
12300 {
12301 code = BFD_RELOC_32_PCREL;
12302 break;
12303 }
12304
12305 case BFD_RELOC_NONE:
12306 case BFD_RELOC_ARM_PCREL_BRANCH:
12307 case BFD_RELOC_ARM_PCREL_BLX:
12308 case BFD_RELOC_RVA:
12309 case BFD_RELOC_THUMB_PCREL_BRANCH7:
12310 case BFD_RELOC_THUMB_PCREL_BRANCH9:
12311 case BFD_RELOC_THUMB_PCREL_BRANCH12:
12312 case BFD_RELOC_THUMB_PCREL_BRANCH20:
12313 case BFD_RELOC_THUMB_PCREL_BRANCH23:
12314 case BFD_RELOC_THUMB_PCREL_BRANCH25:
12315 case BFD_RELOC_THUMB_PCREL_BLX:
12316 case BFD_RELOC_VTABLE_ENTRY:
12317 case BFD_RELOC_VTABLE_INHERIT:
12318 code = fixp->fx_r_type;
12319 break;
12320
12321 case BFD_RELOC_ARM_LITERAL:
12322 case BFD_RELOC_ARM_HWLITERAL:
12323 /* If this is called then the a literal has
12324 been referenced across a section boundary. */
12325 as_bad_where (fixp->fx_file, fixp->fx_line,
12326 _("literal referenced across section boundary"));
12327 return NULL;
12328
12329 #ifdef OBJ_ELF
12330 case BFD_RELOC_ARM_GOT32:
12331 case BFD_RELOC_ARM_GOTOFF:
12332 case BFD_RELOC_ARM_PLT32:
12333 case BFD_RELOC_ARM_TARGET1:
12334 case BFD_RELOC_ARM_ROSEGREL32:
12335 case BFD_RELOC_ARM_SBREL32:
12336 case BFD_RELOC_ARM_PREL31:
12337 case BFD_RELOC_ARM_TARGET2:
12338 case BFD_RELOC_ARM_TLS_LE32:
12339 case BFD_RELOC_ARM_TLS_LDO32:
12340 case BFD_RELOC_ARM_PCREL_CALL:
12341 case BFD_RELOC_ARM_PCREL_JUMP:
12342 code = fixp->fx_r_type;
12343 break;
12344
12345 case BFD_RELOC_ARM_TLS_GD32:
12346 case BFD_RELOC_ARM_TLS_IE32:
12347 case BFD_RELOC_ARM_TLS_LDM32:
12348 /* BFD will include the symbol's address in the addend.
12349 But we don't want that, so subtract it out again here. */
12350 if (!S_IS_COMMON (fixp->fx_addsy))
12351 reloc->addend -= (*reloc->sym_ptr_ptr)->value;
12352 code = fixp->fx_r_type;
12353 break;
12354 #endif
12355
12356 case BFD_RELOC_ARM_IMMEDIATE:
12357 as_bad_where (fixp->fx_file, fixp->fx_line,
12358 _("internal relocation (type: IMMEDIATE) not fixed up"));
12359 return NULL;
12360
12361 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
12362 as_bad_where (fixp->fx_file, fixp->fx_line,
12363 _("ADRL used for a symbol not defined in the same file"));
12364 return NULL;
12365
12366 case BFD_RELOC_ARM_OFFSET_IMM:
12367 if (section->use_rela_p)
12368 {
12369 code = fixp->fx_r_type;
12370 break;
12371 }
12372
12373 if (fixp->fx_addsy != NULL
12374 && !S_IS_DEFINED (fixp->fx_addsy)
12375 && S_IS_LOCAL (fixp->fx_addsy))
12376 {
12377 as_bad_where (fixp->fx_file, fixp->fx_line,
12378 _("undefined local label `%s'"),
12379 S_GET_NAME (fixp->fx_addsy));
12380 return NULL;
12381 }
12382
12383 as_bad_where (fixp->fx_file, fixp->fx_line,
12384 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
12385 return NULL;
12386
12387 default:
12388 {
12389 char * type;
12390
12391 switch (fixp->fx_r_type)
12392 {
12393 case BFD_RELOC_NONE: type = "NONE"; break;
12394 case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break;
12395 case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break;
12396 case BFD_RELOC_ARM_SMC: type = "SMC"; break;
12397 case BFD_RELOC_ARM_SWI: type = "SWI"; break;
12398 case BFD_RELOC_ARM_MULTI: type = "MULTI"; break;
12399 case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break;
12400 case BFD_RELOC_ARM_T32_CP_OFF_IMM: type = "T32_CP_OFF_IMM"; break;
12401 case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break;
12402 case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break;
12403 case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break;
12404 case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break;
12405 default: type = _("<unknown>"); break;
12406 }
12407 as_bad_where (fixp->fx_file, fixp->fx_line,
12408 _("cannot represent %s relocation in this object file format"),
12409 type);
12410 return NULL;
12411 }
12412 }
12413
12414 #ifdef OBJ_ELF
12415 if ((code == BFD_RELOC_32_PCREL || code == BFD_RELOC_32)
12416 && GOT_symbol
12417 && fixp->fx_addsy == GOT_symbol)
12418 {
12419 code = BFD_RELOC_ARM_GOTPC;
12420 reloc->addend = fixp->fx_offset = reloc->address;
12421 }
12422 #endif
12423
12424 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
12425
12426 if (reloc->howto == NULL)
12427 {
12428 as_bad_where (fixp->fx_file, fixp->fx_line,
12429 _("cannot represent %s relocation in this object file format"),
12430 bfd_get_reloc_code_name (code));
12431 return NULL;
12432 }
12433
12434 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
12435 vtable entry to be used in the relocation's section offset. */
12436 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
12437 reloc->address = fixp->fx_offset;
12438
12439 return reloc;
12440 }
12441
12442 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
12443
12444 void
12445 cons_fix_new_arm (fragS * frag,
12446 int where,
12447 int size,
12448 expressionS * exp)
12449 {
12450 bfd_reloc_code_real_type type;
12451 int pcrel = 0;
12452
12453 /* Pick a reloc.
12454 FIXME: @@ Should look at CPU word size. */
12455 switch (size)
12456 {
12457 case 1:
12458 type = BFD_RELOC_8;
12459 break;
12460 case 2:
12461 type = BFD_RELOC_16;
12462 break;
12463 case 4:
12464 default:
12465 type = BFD_RELOC_32;
12466 break;
12467 case 8:
12468 type = BFD_RELOC_64;
12469 break;
12470 }
12471
12472 fix_new_exp (frag, where, (int) size, exp, pcrel, type);
12473 }
12474
12475 #if defined OBJ_COFF || defined OBJ_ELF
12476 void
12477 arm_validate_fix (fixS * fixP)
12478 {
12479 /* If the destination of the branch is a defined symbol which does not have
12480 the THUMB_FUNC attribute, then we must be calling a function which has
12481 the (interfacearm) attribute. We look for the Thumb entry point to that
12482 function and change the branch to refer to that function instead. */
12483 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23
12484 && fixP->fx_addsy != NULL
12485 && S_IS_DEFINED (fixP->fx_addsy)
12486 && ! THUMB_IS_FUNC (fixP->fx_addsy))
12487 {
12488 fixP->fx_addsy = find_real_start (fixP->fx_addsy);
12489 }
12490 }
12491 #endif
12492
12493 int
12494 arm_force_relocation (struct fix * fixp)
12495 {
12496 #if defined (OBJ_COFF) && defined (TE_PE)
12497 if (fixp->fx_r_type == BFD_RELOC_RVA)
12498 return 1;
12499 #endif
12500
12501 /* Resolve these relocations even if the symbol is extern or weak. */
12502 if (fixp->fx_r_type == BFD_RELOC_ARM_IMMEDIATE
12503 || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM
12504 || fixp->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE
12505 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
12506 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMM12
12507 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_PC12)
12508 return 0;
12509
12510 return generic_force_reloc (fixp);
12511 }
12512
12513 #ifdef OBJ_COFF
12514 /* This is a little hack to help the gas/arm/adrl.s test. It prevents
12515 local labels from being added to the output symbol table when they
12516 are used with the ADRL pseudo op. The ADRL relocation should always
12517 be resolved before the binbary is emitted, so it is safe to say that
12518 it is adjustable. */
12519
12520 bfd_boolean
12521 arm_fix_adjustable (fixS * fixP)
12522 {
12523 if (fixP->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE)
12524 return 1;
12525 return 0;
12526 }
12527 #endif
12528
12529 #ifdef OBJ_ELF
12530 /* Relocations against Thumb function names must be left unadjusted,
12531 so that the linker can use this information to correctly set the
12532 bottom bit of their addresses. The MIPS version of this function
12533 also prevents relocations that are mips-16 specific, but I do not
12534 know why it does this.
12535
12536 FIXME:
12537 There is one other problem that ought to be addressed here, but
12538 which currently is not: Taking the address of a label (rather
12539 than a function) and then later jumping to that address. Such
12540 addresses also ought to have their bottom bit set (assuming that
12541 they reside in Thumb code), but at the moment they will not. */
12542
12543 bfd_boolean
12544 arm_fix_adjustable (fixS * fixP)
12545 {
12546 if (fixP->fx_addsy == NULL)
12547 return 1;
12548
12549 if (THUMB_IS_FUNC (fixP->fx_addsy)
12550 && fixP->fx_subsy == NULL)
12551 return 0;
12552
12553 /* We need the symbol name for the VTABLE entries. */
12554 if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
12555 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
12556 return 0;
12557
12558 /* Don't allow symbols to be discarded on GOT related relocs. */
12559 if (fixP->fx_r_type == BFD_RELOC_ARM_PLT32
12560 || fixP->fx_r_type == BFD_RELOC_ARM_GOT32
12561 || fixP->fx_r_type == BFD_RELOC_ARM_GOTOFF
12562 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32
12563 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LE32
12564 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32
12565 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32
12566 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDO32
12567 || fixP->fx_r_type == BFD_RELOC_ARM_TARGET2)
12568 return 0;
12569
12570 return 1;
12571 }
12572
12573 const char *
12574 elf32_arm_target_format (void)
12575 {
12576 #ifdef TE_SYMBIAN
12577 return (target_big_endian
12578 ? "elf32-bigarm-symbian"
12579 : "elf32-littlearm-symbian");
12580 #elif defined (TE_VXWORKS)
12581 return (target_big_endian
12582 ? "elf32-bigarm-vxworks"
12583 : "elf32-littlearm-vxworks");
12584 #else
12585 if (target_big_endian)
12586 return "elf32-bigarm";
12587 else
12588 return "elf32-littlearm";
12589 #endif
12590 }
12591
12592 void
12593 armelf_frob_symbol (symbolS * symp,
12594 int * puntp)
12595 {
12596 elf_frob_symbol (symp, puntp);
12597 }
12598 #endif
12599
12600 /* MD interface: Finalization. */
12601
12602 /* A good place to do this, although this was probably not intended
12603 for this kind of use. We need to dump the literal pool before
12604 references are made to a null symbol pointer. */
12605
12606 void
12607 arm_cleanup (void)
12608 {
12609 literal_pool * pool;
12610
12611 for (pool = list_of_pools; pool; pool = pool->next)
12612 {
12613 /* Put it at the end of the relevent section. */
12614 subseg_set (pool->section, pool->sub_section);
12615 #ifdef OBJ_ELF
12616 arm_elf_change_section ();
12617 #endif
12618 s_ltorg (0);
12619 }
12620 }
12621
12622 /* Adjust the symbol table. This marks Thumb symbols as distinct from
12623 ARM ones. */
12624
12625 void
12626 arm_adjust_symtab (void)
12627 {
12628 #ifdef OBJ_COFF
12629 symbolS * sym;
12630
12631 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
12632 {
12633 if (ARM_IS_THUMB (sym))
12634 {
12635 if (THUMB_IS_FUNC (sym))
12636 {
12637 /* Mark the symbol as a Thumb function. */
12638 if ( S_GET_STORAGE_CLASS (sym) == C_STAT
12639 || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */
12640 S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC);
12641
12642 else if (S_GET_STORAGE_CLASS (sym) == C_EXT)
12643 S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC);
12644 else
12645 as_bad (_("%s: unexpected function type: %d"),
12646 S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym));
12647 }
12648 else switch (S_GET_STORAGE_CLASS (sym))
12649 {
12650 case C_EXT:
12651 S_SET_STORAGE_CLASS (sym, C_THUMBEXT);
12652 break;
12653 case C_STAT:
12654 S_SET_STORAGE_CLASS (sym, C_THUMBSTAT);
12655 break;
12656 case C_LABEL:
12657 S_SET_STORAGE_CLASS (sym, C_THUMBLABEL);
12658 break;
12659 default:
12660 /* Do nothing. */
12661 break;
12662 }
12663 }
12664
12665 if (ARM_IS_INTERWORK (sym))
12666 coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF;
12667 }
12668 #endif
12669 #ifdef OBJ_ELF
12670 symbolS * sym;
12671 char bind;
12672
12673 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
12674 {
12675 if (ARM_IS_THUMB (sym))
12676 {
12677 elf_symbol_type * elf_sym;
12678
12679 elf_sym = elf_symbol (symbol_get_bfdsym (sym));
12680 bind = ELF_ST_BIND (elf_sym->internal_elf_sym.st_info);
12681
12682 if (! bfd_is_arm_mapping_symbol_name (elf_sym->symbol.name))
12683 {
12684 /* If it's a .thumb_func, declare it as so,
12685 otherwise tag label as .code 16. */
12686 if (THUMB_IS_FUNC (sym))
12687 elf_sym->internal_elf_sym.st_info =
12688 ELF_ST_INFO (bind, STT_ARM_TFUNC);
12689 else
12690 elf_sym->internal_elf_sym.st_info =
12691 ELF_ST_INFO (bind, STT_ARM_16BIT);
12692 }
12693 }
12694 }
12695 #endif
12696 }
12697
12698 /* MD interface: Initialization. */
12699
12700 static void
12701 set_constant_flonums (void)
12702 {
12703 int i;
12704
12705 for (i = 0; i < NUM_FLOAT_VALS; i++)
12706 if (atof_ieee ((char *) fp_const[i], 'x', fp_values[i]) == NULL)
12707 abort ();
12708 }
12709
12710 void
12711 md_begin (void)
12712 {
12713 unsigned mach;
12714 unsigned int i;
12715
12716 if ( (arm_ops_hsh = hash_new ()) == NULL
12717 || (arm_cond_hsh = hash_new ()) == NULL
12718 || (arm_shift_hsh = hash_new ()) == NULL
12719 || (arm_psr_hsh = hash_new ()) == NULL
12720 || (arm_v7m_psr_hsh = hash_new ()) == NULL
12721 || (arm_reg_hsh = hash_new ()) == NULL
12722 || (arm_reloc_hsh = hash_new ()) == NULL
12723 || (arm_barrier_opt_hsh = hash_new ()) == NULL)
12724 as_fatal (_("virtual memory exhausted"));
12725
12726 for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++)
12727 hash_insert (arm_ops_hsh, insns[i].template, (PTR) (insns + i));
12728 for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++)
12729 hash_insert (arm_cond_hsh, conds[i].template, (PTR) (conds + i));
12730 for (i = 0; i < sizeof (shift_names) / sizeof (struct asm_shift_name); i++)
12731 hash_insert (arm_shift_hsh, shift_names[i].name, (PTR) (shift_names + i));
12732 for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++)
12733 hash_insert (arm_psr_hsh, psrs[i].template, (PTR) (psrs + i));
12734 for (i = 0; i < sizeof (v7m_psrs) / sizeof (struct asm_psr); i++)
12735 hash_insert (arm_v7m_psr_hsh, v7m_psrs[i].template, (PTR) (v7m_psrs + i));
12736 for (i = 0; i < sizeof (reg_names) / sizeof (struct reg_entry); i++)
12737 hash_insert (arm_reg_hsh, reg_names[i].name, (PTR) (reg_names + i));
12738 for (i = 0;
12739 i < sizeof (barrier_opt_names) / sizeof (struct asm_barrier_opt);
12740 i++)
12741 hash_insert (arm_barrier_opt_hsh, barrier_opt_names[i].template,
12742 (PTR) (barrier_opt_names + i));
12743 #ifdef OBJ_ELF
12744 for (i = 0; i < sizeof (reloc_names) / sizeof (struct reloc_entry); i++)
12745 hash_insert (arm_reloc_hsh, reloc_names[i].name, (PTR) (reloc_names + i));
12746 #endif
12747
12748 set_constant_flonums ();
12749
12750 /* Set the cpu variant based on the command-line options. We prefer
12751 -mcpu= over -march= if both are set (as for GCC); and we prefer
12752 -mfpu= over any other way of setting the floating point unit.
12753 Use of legacy options with new options are faulted. */
12754 if (legacy_cpu)
12755 {
12756 if (mcpu_cpu_opt || march_cpu_opt)
12757 as_bad (_("use of old and new-style options to set CPU type"));
12758
12759 mcpu_cpu_opt = legacy_cpu;
12760 }
12761 else if (!mcpu_cpu_opt)
12762 mcpu_cpu_opt = march_cpu_opt;
12763
12764 if (legacy_fpu)
12765 {
12766 if (mfpu_opt)
12767 as_bad (_("use of old and new-style options to set FPU type"));
12768
12769 mfpu_opt = legacy_fpu;
12770 }
12771 else if (!mfpu_opt)
12772 {
12773 #if !(defined (TE_LINUX) || defined (TE_NetBSD) || defined (TE_VXWORKS))
12774 /* Some environments specify a default FPU. If they don't, infer it
12775 from the processor. */
12776 if (mcpu_fpu_opt)
12777 mfpu_opt = mcpu_fpu_opt;
12778 else
12779 mfpu_opt = march_fpu_opt;
12780 #else
12781 mfpu_opt = &fpu_default;
12782 #endif
12783 }
12784
12785 if (!mfpu_opt)
12786 {
12787 if (!mcpu_cpu_opt)
12788 mfpu_opt = &fpu_default;
12789 else if (ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt, arm_ext_v5))
12790 mfpu_opt = &fpu_arch_vfp_v2;
12791 else
12792 mfpu_opt = &fpu_arch_fpa;
12793 }
12794
12795 #ifdef CPU_DEFAULT
12796 if (!mcpu_cpu_opt)
12797 {
12798 mcpu_cpu_opt = &cpu_default;
12799 selected_cpu = cpu_default;
12800 }
12801 #else
12802 if (mcpu_cpu_opt)
12803 selected_cpu = *mcpu_cpu_opt;
12804 else
12805 mcpu_cpu_opt = &arm_arch_any;
12806 #endif
12807
12808 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
12809
12810 arm_arch_used = thumb_arch_used = arm_arch_none;
12811
12812 #if defined OBJ_COFF || defined OBJ_ELF
12813 {
12814 unsigned int flags = 0;
12815
12816 #if defined OBJ_ELF
12817 flags = meabi_flags;
12818
12819 switch (meabi_flags)
12820 {
12821 case EF_ARM_EABI_UNKNOWN:
12822 #endif
12823 /* Set the flags in the private structure. */
12824 if (uses_apcs_26) flags |= F_APCS26;
12825 if (support_interwork) flags |= F_INTERWORK;
12826 if (uses_apcs_float) flags |= F_APCS_FLOAT;
12827 if (pic_code) flags |= F_PIC;
12828 if (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_any_hard))
12829 flags |= F_SOFT_FLOAT;
12830
12831 switch (mfloat_abi_opt)
12832 {
12833 case ARM_FLOAT_ABI_SOFT:
12834 case ARM_FLOAT_ABI_SOFTFP:
12835 flags |= F_SOFT_FLOAT;
12836 break;
12837
12838 case ARM_FLOAT_ABI_HARD:
12839 if (flags & F_SOFT_FLOAT)
12840 as_bad (_("hard-float conflicts with specified fpu"));
12841 break;
12842 }
12843
12844 /* Using pure-endian doubles (even if soft-float). */
12845 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
12846 flags |= F_VFP_FLOAT;
12847
12848 #if defined OBJ_ELF
12849 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_maverick))
12850 flags |= EF_ARM_MAVERICK_FLOAT;
12851 break;
12852
12853 case EF_ARM_EABI_VER4:
12854 /* No additional flags to set. */
12855 break;
12856
12857 default:
12858 abort ();
12859 }
12860 #endif
12861 bfd_set_private_flags (stdoutput, flags);
12862
12863 /* We have run out flags in the COFF header to encode the
12864 status of ATPCS support, so instead we create a dummy,
12865 empty, debug section called .arm.atpcs. */
12866 if (atpcs)
12867 {
12868 asection * sec;
12869
12870 sec = bfd_make_section (stdoutput, ".arm.atpcs");
12871
12872 if (sec != NULL)
12873 {
12874 bfd_set_section_flags
12875 (stdoutput, sec, SEC_READONLY | SEC_DEBUGGING /* | SEC_HAS_CONTENTS */);
12876 bfd_set_section_size (stdoutput, sec, 0);
12877 bfd_set_section_contents (stdoutput, sec, NULL, 0, 0);
12878 }
12879 }
12880 }
12881 #endif
12882
12883 /* Record the CPU type as well. */
12884 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt))
12885 mach = bfd_mach_arm_iWMMXt;
12886 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_xscale))
12887 mach = bfd_mach_arm_XScale;
12888 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_maverick))
12889 mach = bfd_mach_arm_ep9312;
12890 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5e))
12891 mach = bfd_mach_arm_5TE;
12892 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5))
12893 {
12894 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
12895 mach = bfd_mach_arm_5T;
12896 else
12897 mach = bfd_mach_arm_5;
12898 }
12899 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4))
12900 {
12901 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
12902 mach = bfd_mach_arm_4T;
12903 else
12904 mach = bfd_mach_arm_4;
12905 }
12906 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3m))
12907 mach = bfd_mach_arm_3M;
12908 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3))
12909 mach = bfd_mach_arm_3;
12910 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2s))
12911 mach = bfd_mach_arm_2a;
12912 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2))
12913 mach = bfd_mach_arm_2;
12914 else
12915 mach = bfd_mach_arm_unknown;
12916
12917 bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach);
12918 }
12919
12920 /* Command line processing. */
12921
12922 /* md_parse_option
12923 Invocation line includes a switch not recognized by the base assembler.
12924 See if it's a processor-specific option.
12925
12926 This routine is somewhat complicated by the need for backwards
12927 compatibility (since older releases of gcc can't be changed).
12928 The new options try to make the interface as compatible as
12929 possible with GCC.
12930
12931 New options (supported) are:
12932
12933 -mcpu=<cpu name> Assemble for selected processor
12934 -march=<architecture name> Assemble for selected architecture
12935 -mfpu=<fpu architecture> Assemble for selected FPU.
12936 -EB/-mbig-endian Big-endian
12937 -EL/-mlittle-endian Little-endian
12938 -k Generate PIC code
12939 -mthumb Start in Thumb mode
12940 -mthumb-interwork Code supports ARM/Thumb interworking
12941
12942 For now we will also provide support for:
12943
12944 -mapcs-32 32-bit Program counter
12945 -mapcs-26 26-bit Program counter
12946 -macps-float Floats passed in FP registers
12947 -mapcs-reentrant Reentrant code
12948 -matpcs
12949 (sometime these will probably be replaced with -mapcs=<list of options>
12950 and -matpcs=<list of options>)
12951
12952 The remaining options are only supported for back-wards compatibility.
12953 Cpu variants, the arm part is optional:
12954 -m[arm]1 Currently not supported.
12955 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
12956 -m[arm]3 Arm 3 processor
12957 -m[arm]6[xx], Arm 6 processors
12958 -m[arm]7[xx][t][[d]m] Arm 7 processors
12959 -m[arm]8[10] Arm 8 processors
12960 -m[arm]9[20][tdmi] Arm 9 processors
12961 -mstrongarm[110[0]] StrongARM processors
12962 -mxscale XScale processors
12963 -m[arm]v[2345[t[e]]] Arm architectures
12964 -mall All (except the ARM1)
12965 FP variants:
12966 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
12967 -mfpe-old (No float load/store multiples)
12968 -mvfpxd VFP Single precision
12969 -mvfp All VFP
12970 -mno-fpu Disable all floating point instructions
12971
12972 The following CPU names are recognized:
12973 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
12974 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
12975 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
12976 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
12977 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
12978 arm10t arm10e, arm1020t, arm1020e, arm10200e,
12979 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
12980
12981 */
12982
12983 const char * md_shortopts = "m:k";
12984
12985 #ifdef ARM_BI_ENDIAN
12986 #define OPTION_EB (OPTION_MD_BASE + 0)
12987 #define OPTION_EL (OPTION_MD_BASE + 1)
12988 #else
12989 #if TARGET_BYTES_BIG_ENDIAN
12990 #define OPTION_EB (OPTION_MD_BASE + 0)
12991 #else
12992 #define OPTION_EL (OPTION_MD_BASE + 1)
12993 #endif
12994 #endif
12995
12996 struct option md_longopts[] =
12997 {
12998 #ifdef OPTION_EB
12999 {"EB", no_argument, NULL, OPTION_EB},
13000 #endif
13001 #ifdef OPTION_EL
13002 {"EL", no_argument, NULL, OPTION_EL},
13003 #endif
13004 {NULL, no_argument, NULL, 0}
13005 };
13006
13007 size_t md_longopts_size = sizeof (md_longopts);
13008
13009 struct arm_option_table
13010 {
13011 char *option; /* Option name to match. */
13012 char *help; /* Help information. */
13013 int *var; /* Variable to change. */
13014 int value; /* What to change it to. */
13015 char *deprecated; /* If non-null, print this message. */
13016 };
13017
13018 struct arm_option_table arm_opts[] =
13019 {
13020 {"k", N_("generate PIC code"), &pic_code, 1, NULL},
13021 {"mthumb", N_("assemble Thumb code"), &thumb_mode, 1, NULL},
13022 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
13023 &support_interwork, 1, NULL},
13024 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26, 0, NULL},
13025 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26, 1, NULL},
13026 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float,
13027 1, NULL},
13028 {"mapcs-reentrant", N_("re-entrant code"), &pic_code, 1, NULL},
13029 {"matpcs", N_("code is ATPCS conformant"), &atpcs, 1, NULL},
13030 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL},
13031 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 0,
13032 NULL},
13033
13034 /* These are recognized by the assembler, but have no affect on code. */
13035 {"mapcs-frame", N_("use frame pointer"), NULL, 0, NULL},
13036 {"mapcs-stack-check", N_("use stack size checking"), NULL, 0, NULL},
13037 {NULL, NULL, NULL, 0, NULL}
13038 };
13039
13040 struct arm_legacy_option_table
13041 {
13042 char *option; /* Option name to match. */
13043 const arm_feature_set **var; /* Variable to change. */
13044 const arm_feature_set value; /* What to change it to. */
13045 char *deprecated; /* If non-null, print this message. */
13046 };
13047
13048 const struct arm_legacy_option_table arm_legacy_opts[] =
13049 {
13050 /* DON'T add any new processors to this list -- we want the whole list
13051 to go away... Add them to the processors table instead. */
13052 {"marm1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
13053 {"m1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
13054 {"marm2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
13055 {"m2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
13056 {"marm250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
13057 {"m250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
13058 {"marm3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
13059 {"m3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
13060 {"marm6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
13061 {"m6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
13062 {"marm600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
13063 {"m600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
13064 {"marm610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
13065 {"m610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
13066 {"marm620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
13067 {"m620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
13068 {"marm7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
13069 {"m7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
13070 {"marm70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
13071 {"m70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
13072 {"marm700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
13073 {"m700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
13074 {"marm700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
13075 {"m700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
13076 {"marm710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
13077 {"m710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
13078 {"marm710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
13079 {"m710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
13080 {"marm720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
13081 {"m720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
13082 {"marm7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
13083 {"m7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
13084 {"marm7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
13085 {"m7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
13086 {"marm7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
13087 {"m7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
13088 {"marm7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
13089 {"m7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
13090 {"marm7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
13091 {"m7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
13092 {"marm7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
13093 {"m7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
13094 {"marm7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
13095 {"m7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
13096 {"marm7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
13097 {"m7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
13098 {"marm7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
13099 {"m7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
13100 {"marm7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
13101 {"m7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
13102 {"marm710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
13103 {"m710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
13104 {"marm720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
13105 {"m720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
13106 {"marm740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
13107 {"m740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
13108 {"marm8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
13109 {"m8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
13110 {"marm810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
13111 {"m810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
13112 {"marm9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
13113 {"m9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
13114 {"marm9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
13115 {"m9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
13116 {"marm920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
13117 {"m920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
13118 {"marm940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
13119 {"m940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
13120 {"mstrongarm", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=strongarm")},
13121 {"mstrongarm110", &legacy_cpu, ARM_ARCH_V4,
13122 N_("use -mcpu=strongarm110")},
13123 {"mstrongarm1100", &legacy_cpu, ARM_ARCH_V4,
13124 N_("use -mcpu=strongarm1100")},
13125 {"mstrongarm1110", &legacy_cpu, ARM_ARCH_V4,
13126 N_("use -mcpu=strongarm1110")},
13127 {"mxscale", &legacy_cpu, ARM_ARCH_XSCALE, N_("use -mcpu=xscale")},
13128 {"miwmmxt", &legacy_cpu, ARM_ARCH_IWMMXT, N_("use -mcpu=iwmmxt")},
13129 {"mall", &legacy_cpu, ARM_ANY, N_("use -mcpu=all")},
13130
13131 /* Architecture variants -- don't add any more to this list either. */
13132 {"mv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
13133 {"marmv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
13134 {"mv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
13135 {"marmv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
13136 {"mv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
13137 {"marmv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
13138 {"mv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
13139 {"marmv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
13140 {"mv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
13141 {"marmv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
13142 {"mv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
13143 {"marmv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
13144 {"mv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
13145 {"marmv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
13146 {"mv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
13147 {"marmv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
13148 {"mv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
13149 {"marmv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
13150
13151 /* Floating point variants -- don't add any more to this list either. */
13152 {"mfpe-old", &legacy_fpu, FPU_ARCH_FPE, N_("use -mfpu=fpe")},
13153 {"mfpa10", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa10")},
13154 {"mfpa11", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa11")},
13155 {"mno-fpu", &legacy_fpu, ARM_ARCH_NONE,
13156 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
13157
13158 {NULL, NULL, ARM_ARCH_NONE, NULL}
13159 };
13160
13161 struct arm_cpu_option_table
13162 {
13163 char *name;
13164 const arm_feature_set value;
13165 /* For some CPUs we assume an FPU unless the user explicitly sets
13166 -mfpu=... */
13167 const arm_feature_set default_fpu;
13168 /* The canonical name of the CPU, or NULL to use NAME converted to upper
13169 case. */
13170 const char *canonical_name;
13171 };
13172
13173 /* This list should, at a minimum, contain all the cpu names
13174 recognized by GCC. */
13175 static const struct arm_cpu_option_table arm_cpus[] =
13176 {
13177 {"all", ARM_ANY, FPU_ARCH_FPA, NULL},
13178 {"arm1", ARM_ARCH_V1, FPU_ARCH_FPA, NULL},
13179 {"arm2", ARM_ARCH_V2, FPU_ARCH_FPA, NULL},
13180 {"arm250", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL},
13181 {"arm3", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL},
13182 {"arm6", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
13183 {"arm60", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
13184 {"arm600", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
13185 {"arm610", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
13186 {"arm620", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
13187 {"arm7", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
13188 {"arm7m", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL},
13189 {"arm7d", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
13190 {"arm7dm", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL},
13191 {"arm7di", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
13192 {"arm7dmi", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL},
13193 {"arm70", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
13194 {"arm700", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
13195 {"arm700i", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
13196 {"arm710", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
13197 {"arm710t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
13198 {"arm720", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
13199 {"arm720t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
13200 {"arm740t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
13201 {"arm710c", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
13202 {"arm7100", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
13203 {"arm7500", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
13204 {"arm7500fe", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
13205 {"arm7t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
13206 {"arm7tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
13207 {"arm7tdmi-s", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
13208 {"arm8", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
13209 {"arm810", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
13210 {"strongarm", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
13211 {"strongarm1", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
13212 {"strongarm110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
13213 {"strongarm1100", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
13214 {"strongarm1110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
13215 {"arm9", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
13216 {"arm920", ARM_ARCH_V4T, FPU_ARCH_FPA, "ARM920T"},
13217 {"arm920t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
13218 {"arm922t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
13219 {"arm940t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
13220 {"arm9tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
13221 /* For V5 or later processors we default to using VFP; but the user
13222 should really set the FPU type explicitly. */
13223 {"arm9e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL},
13224 {"arm9e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
13225 {"arm926ej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"},
13226 {"arm926ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"},
13227 {"arm926ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL},
13228 {"arm946e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL},
13229 {"arm946e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM946E-S"},
13230 {"arm946e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
13231 {"arm966e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL},
13232 {"arm966e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM966E-S"},
13233 {"arm966e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
13234 {"arm968e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
13235 {"arm10t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL},
13236 {"arm10tdmi", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL},
13237 {"arm10e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
13238 {"arm1020", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM1020E"},
13239 {"arm1020t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL},
13240 {"arm1020e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
13241 {"arm1022e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
13242 {"arm1026ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM1026EJ-S"},
13243 {"arm1026ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL},
13244 {"arm1136js", ARM_ARCH_V6, FPU_NONE, "ARM1136J-S"},
13245 {"arm1136j-s", ARM_ARCH_V6, FPU_NONE, NULL},
13246 {"arm1136jfs", ARM_ARCH_V6, FPU_ARCH_VFP_V2, "ARM1136JF-S"},
13247 {"arm1136jf-s", ARM_ARCH_V6, FPU_ARCH_VFP_V2, NULL},
13248 {"mpcore", ARM_ARCH_V6K, FPU_ARCH_VFP_V2, NULL},
13249 {"mpcorenovfp", ARM_ARCH_V6K, FPU_NONE, NULL},
13250 {"arm1156t2-s", ARM_ARCH_V6T2, FPU_NONE, NULL},
13251 {"arm1156t2f-s", ARM_ARCH_V6T2, FPU_ARCH_VFP_V2, NULL},
13252 {"arm1176jz-s", ARM_ARCH_V6ZK, FPU_NONE, NULL},
13253 {"arm1176jzf-s", ARM_ARCH_V6ZK, FPU_ARCH_VFP_V2, NULL},
13254 {"cortex-a8", ARM_ARCH_V7A, FPU_ARCH_VFP_V2, NULL},
13255 {"cortex-r4", ARM_ARCH_V7R, FPU_NONE, NULL},
13256 {"cortex-m3", ARM_ARCH_V7M, FPU_NONE, NULL},
13257 /* ??? XSCALE is really an architecture. */
13258 {"xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL},
13259 /* ??? iwmmxt is not a processor. */
13260 {"iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP_V2, NULL},
13261 {"i80200", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL},
13262 /* Maverick */
13263 {"ep9312", ARM_FEATURE(ARM_AEXT_V4T, ARM_CEXT_MAVERICK), FPU_ARCH_MAVERICK, "ARM920T"},
13264 {NULL, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL}
13265 };
13266
13267 struct arm_arch_option_table
13268 {
13269 char *name;
13270 const arm_feature_set value;
13271 const arm_feature_set default_fpu;
13272 };
13273
13274 /* This list should, at a minimum, contain all the architecture names
13275 recognized by GCC. */
13276 static const struct arm_arch_option_table arm_archs[] =
13277 {
13278 {"all", ARM_ANY, FPU_ARCH_FPA},
13279 {"armv1", ARM_ARCH_V1, FPU_ARCH_FPA},
13280 {"armv2", ARM_ARCH_V2, FPU_ARCH_FPA},
13281 {"armv2a", ARM_ARCH_V2S, FPU_ARCH_FPA},
13282 {"armv2s", ARM_ARCH_V2S, FPU_ARCH_FPA},
13283 {"armv3", ARM_ARCH_V3, FPU_ARCH_FPA},
13284 {"armv3m", ARM_ARCH_V3M, FPU_ARCH_FPA},
13285 {"armv4", ARM_ARCH_V4, FPU_ARCH_FPA},
13286 {"armv4xm", ARM_ARCH_V4xM, FPU_ARCH_FPA},
13287 {"armv4t", ARM_ARCH_V4T, FPU_ARCH_FPA},
13288 {"armv4txm", ARM_ARCH_V4TxM, FPU_ARCH_FPA},
13289 {"armv5", ARM_ARCH_V5, FPU_ARCH_VFP},
13290 {"armv5t", ARM_ARCH_V5T, FPU_ARCH_VFP},
13291 {"armv5txm", ARM_ARCH_V5TxM, FPU_ARCH_VFP},
13292 {"armv5te", ARM_ARCH_V5TE, FPU_ARCH_VFP},
13293 {"armv5texp", ARM_ARCH_V5TExP, FPU_ARCH_VFP},
13294 {"armv5tej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP},
13295 {"armv6", ARM_ARCH_V6, FPU_ARCH_VFP},
13296 {"armv6j", ARM_ARCH_V6, FPU_ARCH_VFP},
13297 {"armv6k", ARM_ARCH_V6K, FPU_ARCH_VFP},
13298 {"armv6z", ARM_ARCH_V6Z, FPU_ARCH_VFP},
13299 {"armv6zk", ARM_ARCH_V6ZK, FPU_ARCH_VFP},
13300 {"armv6t2", ARM_ARCH_V6T2, FPU_ARCH_VFP},
13301 {"armv6kt2", ARM_ARCH_V6KT2, FPU_ARCH_VFP},
13302 {"armv6zt2", ARM_ARCH_V6ZT2, FPU_ARCH_VFP},
13303 {"armv6zkt2", ARM_ARCH_V6ZKT2, FPU_ARCH_VFP},
13304 {"armv7", ARM_ARCH_V7, FPU_ARCH_VFP},
13305 {"armv7a", ARM_ARCH_V7A, FPU_ARCH_VFP},
13306 {"armv7r", ARM_ARCH_V7R, FPU_ARCH_VFP},
13307 {"armv7m", ARM_ARCH_V7M, FPU_ARCH_VFP},
13308 {"xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP},
13309 {"iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP},
13310 {NULL, ARM_ARCH_NONE, ARM_ARCH_NONE}
13311 };
13312
13313 /* ISA extensions in the co-processor space. */
13314 struct arm_option_cpu_value_table
13315 {
13316 char *name;
13317 const arm_feature_set value;
13318 };
13319
13320 static const struct arm_option_cpu_value_table arm_extensions[] =
13321 {
13322 {"maverick", ARM_FEATURE (0, ARM_CEXT_MAVERICK)},
13323 {"xscale", ARM_FEATURE (0, ARM_CEXT_XSCALE)},
13324 {"iwmmxt", ARM_FEATURE (0, ARM_CEXT_IWMMXT)},
13325 {NULL, ARM_ARCH_NONE}
13326 };
13327
13328 /* This list should, at a minimum, contain all the fpu names
13329 recognized by GCC. */
13330 static const struct arm_option_cpu_value_table arm_fpus[] =
13331 {
13332 {"softfpa", FPU_NONE},
13333 {"fpe", FPU_ARCH_FPE},
13334 {"fpe2", FPU_ARCH_FPE},
13335 {"fpe3", FPU_ARCH_FPA}, /* Third release supports LFM/SFM. */
13336 {"fpa", FPU_ARCH_FPA},
13337 {"fpa10", FPU_ARCH_FPA},
13338 {"fpa11", FPU_ARCH_FPA},
13339 {"arm7500fe", FPU_ARCH_FPA},
13340 {"softvfp", FPU_ARCH_VFP},
13341 {"softvfp+vfp", FPU_ARCH_VFP_V2},
13342 {"vfp", FPU_ARCH_VFP_V2},
13343 {"vfp9", FPU_ARCH_VFP_V2},
13344 {"vfp10", FPU_ARCH_VFP_V2},
13345 {"vfp10-r0", FPU_ARCH_VFP_V1},
13346 {"vfpxd", FPU_ARCH_VFP_V1xD},
13347 {"arm1020t", FPU_ARCH_VFP_V1},
13348 {"arm1020e", FPU_ARCH_VFP_V2},
13349 {"arm1136jfs", FPU_ARCH_VFP_V2},
13350 {"arm1136jf-s", FPU_ARCH_VFP_V2},
13351 {"maverick", FPU_ARCH_MAVERICK},
13352 {NULL, ARM_ARCH_NONE}
13353 };
13354
13355 struct arm_option_value_table
13356 {
13357 char *name;
13358 long value;
13359 };
13360
13361 static const struct arm_option_value_table arm_float_abis[] =
13362 {
13363 {"hard", ARM_FLOAT_ABI_HARD},
13364 {"softfp", ARM_FLOAT_ABI_SOFTFP},
13365 {"soft", ARM_FLOAT_ABI_SOFT},
13366 {NULL, 0}
13367 };
13368
13369 #ifdef OBJ_ELF
13370 /* We only know how to output GNU and ver 4 (AAELF) formats. */
13371 static const struct arm_option_value_table arm_eabis[] =
13372 {
13373 {"gnu", EF_ARM_EABI_UNKNOWN},
13374 {"4", EF_ARM_EABI_VER4},
13375 {NULL, 0}
13376 };
13377 #endif
13378
13379 struct arm_long_option_table
13380 {
13381 char * option; /* Substring to match. */
13382 char * help; /* Help information. */
13383 int (* func) (char * subopt); /* Function to decode sub-option. */
13384 char * deprecated; /* If non-null, print this message. */
13385 };
13386
13387 static int
13388 arm_parse_extension (char * str, const arm_feature_set **opt_p)
13389 {
13390 arm_feature_set *ext_set = xmalloc (sizeof (arm_feature_set));
13391
13392 /* Copy the feature set, so that we can modify it. */
13393 *ext_set = **opt_p;
13394 *opt_p = ext_set;
13395
13396 while (str != NULL && *str != 0)
13397 {
13398 const struct arm_option_cpu_value_table * opt;
13399 char * ext;
13400 int optlen;
13401
13402 if (*str != '+')
13403 {
13404 as_bad (_("invalid architectural extension"));
13405 return 0;
13406 }
13407
13408 str++;
13409 ext = strchr (str, '+');
13410
13411 if (ext != NULL)
13412 optlen = ext - str;
13413 else
13414 optlen = strlen (str);
13415
13416 if (optlen == 0)
13417 {
13418 as_bad (_("missing architectural extension"));
13419 return 0;
13420 }
13421
13422 for (opt = arm_extensions; opt->name != NULL; opt++)
13423 if (strncmp (opt->name, str, optlen) == 0)
13424 {
13425 ARM_MERGE_FEATURE_SETS (*ext_set, *ext_set, opt->value);
13426 break;
13427 }
13428
13429 if (opt->name == NULL)
13430 {
13431 as_bad (_("unknown architectural extnsion `%s'"), str);
13432 return 0;
13433 }
13434
13435 str = ext;
13436 };
13437
13438 return 1;
13439 }
13440
13441 static int
13442 arm_parse_cpu (char * str)
13443 {
13444 const struct arm_cpu_option_table * opt;
13445 char * ext = strchr (str, '+');
13446 int optlen;
13447
13448 if (ext != NULL)
13449 optlen = ext - str;
13450 else
13451 optlen = strlen (str);
13452
13453 if (optlen == 0)
13454 {
13455 as_bad (_("missing cpu name `%s'"), str);
13456 return 0;
13457 }
13458
13459 for (opt = arm_cpus; opt->name != NULL; opt++)
13460 if (strncmp (opt->name, str, optlen) == 0)
13461 {
13462 mcpu_cpu_opt = &opt->value;
13463 mcpu_fpu_opt = &opt->default_fpu;
13464 if (opt->canonical_name)
13465 strcpy(selected_cpu_name, opt->canonical_name);
13466 else
13467 {
13468 int i;
13469 for (i = 0; i < optlen; i++)
13470 selected_cpu_name[i] = TOUPPER (opt->name[i]);
13471 selected_cpu_name[i] = 0;
13472 }
13473
13474 if (ext != NULL)
13475 return arm_parse_extension (ext, &mcpu_cpu_opt);
13476
13477 return 1;
13478 }
13479
13480 as_bad (_("unknown cpu `%s'"), str);
13481 return 0;
13482 }
13483
13484 static int
13485 arm_parse_arch (char * str)
13486 {
13487 const struct arm_arch_option_table *opt;
13488 char *ext = strchr (str, '+');
13489 int optlen;
13490
13491 if (ext != NULL)
13492 optlen = ext - str;
13493 else
13494 optlen = strlen (str);
13495
13496 if (optlen == 0)
13497 {
13498 as_bad (_("missing architecture name `%s'"), str);
13499 return 0;
13500 }
13501
13502 for (opt = arm_archs; opt->name != NULL; opt++)
13503 if (streq (opt->name, str))
13504 {
13505 march_cpu_opt = &opt->value;
13506 march_fpu_opt = &opt->default_fpu;
13507 strcpy(selected_cpu_name, opt->name);
13508
13509 if (ext != NULL)
13510 return arm_parse_extension (ext, &march_cpu_opt);
13511
13512 return 1;
13513 }
13514
13515 as_bad (_("unknown architecture `%s'\n"), str);
13516 return 0;
13517 }
13518
13519 static int
13520 arm_parse_fpu (char * str)
13521 {
13522 const struct arm_option_cpu_value_table * opt;
13523
13524 for (opt = arm_fpus; opt->name != NULL; opt++)
13525 if (streq (opt->name, str))
13526 {
13527 mfpu_opt = &opt->value;
13528 return 1;
13529 }
13530
13531 as_bad (_("unknown floating point format `%s'\n"), str);
13532 return 0;
13533 }
13534
13535 static int
13536 arm_parse_float_abi (char * str)
13537 {
13538 const struct arm_option_value_table * opt;
13539
13540 for (opt = arm_float_abis; opt->name != NULL; opt++)
13541 if (streq (opt->name, str))
13542 {
13543 mfloat_abi_opt = opt->value;
13544 return 1;
13545 }
13546
13547 as_bad (_("unknown floating point abi `%s'\n"), str);
13548 return 0;
13549 }
13550
13551 #ifdef OBJ_ELF
13552 static int
13553 arm_parse_eabi (char * str)
13554 {
13555 const struct arm_option_value_table *opt;
13556
13557 for (opt = arm_eabis; opt->name != NULL; opt++)
13558 if (streq (opt->name, str))
13559 {
13560 meabi_flags = opt->value;
13561 return 1;
13562 }
13563 as_bad (_("unknown EABI `%s'\n"), str);
13564 return 0;
13565 }
13566 #endif
13567
13568 struct arm_long_option_table arm_long_opts[] =
13569 {
13570 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
13571 arm_parse_cpu, NULL},
13572 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
13573 arm_parse_arch, NULL},
13574 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
13575 arm_parse_fpu, NULL},
13576 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
13577 arm_parse_float_abi, NULL},
13578 #ifdef OBJ_ELF
13579 {"meabi=", N_("<ver>\t assemble for eabi version <ver>"),
13580 arm_parse_eabi, NULL},
13581 #endif
13582 {NULL, NULL, 0, NULL}
13583 };
13584
13585 int
13586 md_parse_option (int c, char * arg)
13587 {
13588 struct arm_option_table *opt;
13589 const struct arm_legacy_option_table *fopt;
13590 struct arm_long_option_table *lopt;
13591
13592 switch (c)
13593 {
13594 #ifdef OPTION_EB
13595 case OPTION_EB:
13596 target_big_endian = 1;
13597 break;
13598 #endif
13599
13600 #ifdef OPTION_EL
13601 case OPTION_EL:
13602 target_big_endian = 0;
13603 break;
13604 #endif
13605
13606 case 'a':
13607 /* Listing option. Just ignore these, we don't support additional
13608 ones. */
13609 return 0;
13610
13611 default:
13612 for (opt = arm_opts; opt->option != NULL; opt++)
13613 {
13614 if (c == opt->option[0]
13615 && ((arg == NULL && opt->option[1] == 0)
13616 || streq (arg, opt->option + 1)))
13617 {
13618 #if WARN_DEPRECATED
13619 /* If the option is deprecated, tell the user. */
13620 if (opt->deprecated != NULL)
13621 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
13622 arg ? arg : "", _(opt->deprecated));
13623 #endif
13624
13625 if (opt->var != NULL)
13626 *opt->var = opt->value;
13627
13628 return 1;
13629 }
13630 }
13631
13632 for (fopt = arm_legacy_opts; fopt->option != NULL; fopt++)
13633 {
13634 if (c == fopt->option[0]
13635 && ((arg == NULL && fopt->option[1] == 0)
13636 || streq (arg, fopt->option + 1)))
13637 {
13638 #if WARN_DEPRECATED
13639 /* If the option is deprecated, tell the user. */
13640 if (fopt->deprecated != NULL)
13641 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
13642 arg ? arg : "", _(fopt->deprecated));
13643 #endif
13644
13645 if (fopt->var != NULL)
13646 *fopt->var = &fopt->value;
13647
13648 return 1;
13649 }
13650 }
13651
13652 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
13653 {
13654 /* These options are expected to have an argument. */
13655 if (c == lopt->option[0]
13656 && arg != NULL
13657 && strncmp (arg, lopt->option + 1,
13658 strlen (lopt->option + 1)) == 0)
13659 {
13660 #if WARN_DEPRECATED
13661 /* If the option is deprecated, tell the user. */
13662 if (lopt->deprecated != NULL)
13663 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, arg,
13664 _(lopt->deprecated));
13665 #endif
13666
13667 /* Call the sup-option parser. */
13668 return lopt->func (arg + strlen (lopt->option) - 1);
13669 }
13670 }
13671
13672 return 0;
13673 }
13674
13675 return 1;
13676 }
13677
13678 void
13679 md_show_usage (FILE * fp)
13680 {
13681 struct arm_option_table *opt;
13682 struct arm_long_option_table *lopt;
13683
13684 fprintf (fp, _(" ARM-specific assembler options:\n"));
13685
13686 for (opt = arm_opts; opt->option != NULL; opt++)
13687 if (opt->help != NULL)
13688 fprintf (fp, " -%-23s%s\n", opt->option, _(opt->help));
13689
13690 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
13691 if (lopt->help != NULL)
13692 fprintf (fp, " -%s%s\n", lopt->option, _(lopt->help));
13693
13694 #ifdef OPTION_EB
13695 fprintf (fp, _("\
13696 -EB assemble code for a big-endian cpu\n"));
13697 #endif
13698
13699 #ifdef OPTION_EL
13700 fprintf (fp, _("\
13701 -EL assemble code for a little-endian cpu\n"));
13702 #endif
13703 }
13704
13705
13706 #ifdef OBJ_ELF
13707 typedef struct
13708 {
13709 int val;
13710 arm_feature_set flags;
13711 } cpu_arch_ver_table;
13712
13713 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
13714 least features first. */
13715 static const cpu_arch_ver_table cpu_arch_ver[] =
13716 {
13717 {1, ARM_ARCH_V4},
13718 {2, ARM_ARCH_V4T},
13719 {3, ARM_ARCH_V5},
13720 {4, ARM_ARCH_V5TE},
13721 {5, ARM_ARCH_V5TEJ},
13722 {6, ARM_ARCH_V6},
13723 {7, ARM_ARCH_V6Z},
13724 {8, ARM_ARCH_V6K},
13725 {9, ARM_ARCH_V6T2},
13726 {10, ARM_ARCH_V7A},
13727 {10, ARM_ARCH_V7R},
13728 {10, ARM_ARCH_V7M},
13729 {0, ARM_ARCH_NONE}
13730 };
13731
13732 /* Set the public EABI object attributes. */
13733 static void
13734 aeabi_set_public_attributes (void)
13735 {
13736 int arch;
13737 arm_feature_set flags;
13738 arm_feature_set tmp;
13739 const cpu_arch_ver_table *p;
13740
13741 /* Choose the architecture based on the capabilities of the requested cpu
13742 (if any) and/or the instructions actually used. */
13743 ARM_MERGE_FEATURE_SETS (flags, arm_arch_used, thumb_arch_used);
13744 ARM_MERGE_FEATURE_SETS (flags, flags, *mfpu_opt);
13745 ARM_MERGE_FEATURE_SETS (flags, flags, selected_cpu);
13746
13747 tmp = flags;
13748 arch = 0;
13749 for (p = cpu_arch_ver; p->val; p++)
13750 {
13751 if (ARM_CPU_HAS_FEATURE (tmp, p->flags))
13752 {
13753 arch = p->val;
13754 ARM_CLEAR_FEATURE (tmp, tmp, p->flags);
13755 }
13756 }
13757
13758 /* Tag_CPU_name. */
13759 if (selected_cpu_name[0])
13760 {
13761 char *p;
13762
13763 p = selected_cpu_name;
13764 if (strncmp(p, "armv", 4) == 0)
13765 {
13766 int i;
13767
13768 p += 4;
13769 for (i = 0; p[i]; i++)
13770 p[i] = TOUPPER (p[i]);
13771 }
13772 elf32_arm_add_eabi_attr_string (stdoutput, 5, p);
13773 }
13774 /* Tag_CPU_arch. */
13775 elf32_arm_add_eabi_attr_int (stdoutput, 6, arch);
13776 /* Tag_CPU_arch_profile. */
13777 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a))
13778 elf32_arm_add_eabi_attr_int (stdoutput, 7, 'A');
13779 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7r))
13780 elf32_arm_add_eabi_attr_int (stdoutput, 7, 'R');
13781 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7m))
13782 elf32_arm_add_eabi_attr_int (stdoutput, 7, 'M');
13783 /* Tag_ARM_ISA_use. */
13784 if (ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_full))
13785 elf32_arm_add_eabi_attr_int (stdoutput, 8, 1);
13786 /* Tag_THUMB_ISA_use. */
13787 if (ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_full))
13788 elf32_arm_add_eabi_attr_int (stdoutput, 9,
13789 ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_t2) ? 2 : 1);
13790 /* Tag_VFP_arch. */
13791 if (ARM_CPU_HAS_FEATURE (thumb_arch_used, fpu_arch_vfp_v2)
13792 || ARM_CPU_HAS_FEATURE (arm_arch_used, fpu_arch_vfp_v2))
13793 elf32_arm_add_eabi_attr_int (stdoutput, 10, 2);
13794 else if (ARM_CPU_HAS_FEATURE (thumb_arch_used, fpu_arch_vfp_v1)
13795 || ARM_CPU_HAS_FEATURE (arm_arch_used, fpu_arch_vfp_v1))
13796 elf32_arm_add_eabi_attr_int (stdoutput, 10, 1);
13797 /* Tag_WMMX_arch. */
13798 if (ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_cext_iwmmxt)
13799 || ARM_CPU_HAS_FEATURE (arm_arch_used, arm_cext_iwmmxt))
13800 elf32_arm_add_eabi_attr_int (stdoutput, 11, 1);
13801 }
13802
13803 /* Add the .ARM.attributes section. */
13804 void
13805 arm_md_end (void)
13806 {
13807 segT s;
13808 char *p;
13809 addressT addr;
13810 offsetT size;
13811
13812 if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
13813 return;
13814
13815 aeabi_set_public_attributes ();
13816 size = elf32_arm_eabi_attr_size (stdoutput);
13817 s = subseg_new (".ARM.attributes", 0);
13818 bfd_set_section_flags (stdoutput, s, SEC_READONLY | SEC_DATA);
13819 addr = frag_now_fix ();
13820 p = frag_more (size);
13821 elf32_arm_set_eabi_attr_contents (stdoutput, (bfd_byte *)p, size);
13822 }
13823
13824
13825 /* Parse a .cpu directive. */
13826
13827 static void
13828 s_arm_cpu (int ignored ATTRIBUTE_UNUSED)
13829 {
13830 const struct arm_cpu_option_table *opt;
13831 char *name;
13832 char saved_char;
13833
13834 name = input_line_pointer;
13835 while (*input_line_pointer && !ISSPACE(*input_line_pointer))
13836 input_line_pointer++;
13837 saved_char = *input_line_pointer;
13838 *input_line_pointer = 0;
13839
13840 /* Skip the first "all" entry. */
13841 for (opt = arm_cpus + 1; opt->name != NULL; opt++)
13842 if (streq (opt->name, name))
13843 {
13844 mcpu_cpu_opt = &opt->value;
13845 selected_cpu = opt->value;
13846 if (opt->canonical_name)
13847 strcpy(selected_cpu_name, opt->canonical_name);
13848 else
13849 {
13850 int i;
13851 for (i = 0; opt->name[i]; i++)
13852 selected_cpu_name[i] = TOUPPER (opt->name[i]);
13853 selected_cpu_name[i] = 0;
13854 }
13855 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
13856 *input_line_pointer = saved_char;
13857 demand_empty_rest_of_line ();
13858 return;
13859 }
13860 as_bad (_("unknown cpu `%s'"), name);
13861 *input_line_pointer = saved_char;
13862 ignore_rest_of_line ();
13863 }
13864
13865
13866 /* Parse a .arch directive. */
13867
13868 static void
13869 s_arm_arch (int ignored ATTRIBUTE_UNUSED)
13870 {
13871 const struct arm_arch_option_table *opt;
13872 char saved_char;
13873 char *name;
13874
13875 name = input_line_pointer;
13876 while (*input_line_pointer && !ISSPACE(*input_line_pointer))
13877 input_line_pointer++;
13878 saved_char = *input_line_pointer;
13879 *input_line_pointer = 0;
13880
13881 /* Skip the first "all" entry. */
13882 for (opt = arm_archs + 1; opt->name != NULL; opt++)
13883 if (streq (opt->name, name))
13884 {
13885 mcpu_cpu_opt = &opt->value;
13886 selected_cpu = opt->value;
13887 strcpy(selected_cpu_name, opt->name);
13888 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
13889 *input_line_pointer = saved_char;
13890 demand_empty_rest_of_line ();
13891 return;
13892 }
13893
13894 as_bad (_("unknown architecture `%s'\n"), name);
13895 *input_line_pointer = saved_char;
13896 ignore_rest_of_line ();
13897 }
13898
13899
13900 /* Parse a .fpu directive. */
13901
13902 static void
13903 s_arm_fpu (int ignored ATTRIBUTE_UNUSED)
13904 {
13905 const struct arm_option_cpu_value_table *opt;
13906 char saved_char;
13907 char *name;
13908
13909 name = input_line_pointer;
13910 while (*input_line_pointer && !ISSPACE(*input_line_pointer))
13911 input_line_pointer++;
13912 saved_char = *input_line_pointer;
13913 *input_line_pointer = 0;
13914
13915 for (opt = arm_fpus; opt->name != NULL; opt++)
13916 if (streq (opt->name, name))
13917 {
13918 mfpu_opt = &opt->value;
13919 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
13920 *input_line_pointer = saved_char;
13921 demand_empty_rest_of_line ();
13922 return;
13923 }
13924
13925 as_bad (_("unknown floating point format `%s'\n"), name);
13926 *input_line_pointer = saved_char;
13927 ignore_rest_of_line ();
13928 }
13929 #endif /* OBJ_ELF */
13930
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