opcodes/i386-opc.h

   1 /* Declarations for Intel 80386 opcode table
   2    Copyright 2007, 2008, 2009, 2010
   3    Free Software Foundation, Inc.
   4
   5    This file is part of the GNU opcodes library.
   6
   7    This library is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3, or (at your option)
  10    any later version.
  11
  12    It is distributed in the hope that it will be useful, but WITHOUT
  13    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15    License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GAS; see the file COPYING.  If not, write to the Free
  19    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
  20    02110-1301, USA.  */
  21
  22 #include "opcode/i386.h"
  23 #ifdef HAVE_LIMITS_H
  24 #include <limits.h>
  25 #endif
  26
  27 #ifndef CHAR_BIT
  28 #define CHAR_BIT 8
  29 #endif
  30
  31 /* Position of cpu flags bitfiled.  */
  32
  33 enum
  34 {
  35   /* i186 or better required */
  36   Cpu186 = 0,
  37   /* i286 or better required */
  38   Cpu286,
  39   /* i386 or better required */
  40   Cpu386,
  41   /* i486 or better required */
  42   Cpu486,
  43   /* i585 or better required */
  44   Cpu586,
  45   /* i686 or better required */
  46   Cpu686,
  47   /* CLFLUSH Instuction support required */
  48   CpuClflush,
  49   /* SYSCALL Instuctions support required */
  50   CpuSYSCALL,
  51   /* Floating point support required */
  52   Cpu8087,
  53   /* i287 support required */
  54   Cpu287,
  55   /* i387 support required */
  56   Cpu387,
  57   /* i686 and floating point support required */
  58   Cpu687,
  59   /* SSE3 and floating point support required */
  60   CpuFISTTP,
  61   /* MMX support required */
  62   CpuMMX,
  63   /* SSE support required */
  64   CpuSSE,
  65   /* SSE2 support required */
  66   CpuSSE2,
  67   /* 3dnow! support required */
  68   Cpu3dnow,
  69   /* 3dnow! Extensions support required */
  70   Cpu3dnowA,
  71   /* SSE3 support required */
  72   CpuSSE3,
  73   /* VIA PadLock required */
  74   CpuPadLock,
  75   /* AMD Secure Virtual Machine Ext-s required */
  76   CpuSVME,
  77   /* VMX Instructions required */
  78   CpuVMX,
  79   /* SMX Instructions required */
  80   CpuSMX,
  81   /* SSSE3 support required */
  82   CpuSSSE3,
  83   /* SSE4a support required */
  84   CpuSSE4a,
  85   /* ABM New Instructions required */
  86   CpuABM,
  87   /* SSE4.1 support required */
  88   CpuSSE4_1,
  89   /* SSE4.2 support required */
  90   CpuSSE4_2,
  91   /* AVX support required */
  92   CpuAVX,
  93   /* Intel L1OM support required */
  94   CpuL1OM,
  95   /* Xsave/xrstor New Instuctions support required */
  96   CpuXsave,
  97   /* Xsaveopt New Instuctions support required */
  98   CpuXsaveopt,
  99   /* AES support required */
 100   CpuAES,
 101   /* PCLMUL support required */
 102   CpuPCLMUL,
 103   /* FMA support required */
 104   CpuFMA,
 105   /* FMA4 support required */
 106   CpuFMA4,
 107   /* XOP support required */
 108   CpuXOP,
 109   /* LWP support required */
 110   CpuLWP,
 111   /* MOVBE Instuction support required */
 112   CpuMovbe,
 113   /* EPT Instructions required */
 114   CpuEPT,
 115   /* RDTSCP Instuction support required */
 116   CpuRdtscp,
 117   /* FSGSBASE Instructions required */
 118   CpuFSGSBase,
 119   /* RDRND Instructions required */
 120   CpuRdRnd,
 121   /* F16C Instructions required */
 122   CpuF16C,
 123   /* 64bit support available, used by -march= in assembler.  */
 124   CpuLM,
 125   /* 64bit support required  */
 126   Cpu64,
 127   /* Not supported in the 64bit mode  */
 128   CpuNo64,
 129   /* The last bitfield in i386_cpu_flags.  */
 130   CpuMax = CpuNo64
 131 };
 132
 133 #define CpuNumOfUints \
 134   (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
 135 #define CpuNumOfBits \
 136   (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 137
 138 /* If you get a compiler error for zero width of the unused field,
 139    comment it out.  */
 140 #define CpuUnused       (CpuMax + 1)
 141
 142 /* We can check if an instruction is available with array instead
 143    of bitfield. */
 144 typedef union i386_cpu_flags
 145 {
 146   struct
 147     {
 148       unsigned int cpui186:1;
 149       unsigned int cpui286:1;
 150       unsigned int cpui386:1;
 151       unsigned int cpui486:1;
 152       unsigned int cpui586:1;
 153       unsigned int cpui686:1;
 154       unsigned int cpuclflush:1;
 155       unsigned int cpusyscall:1;
 156       unsigned int cpu8087:1;
 157       unsigned int cpu287:1;
 158       unsigned int cpu387:1;
 159       unsigned int cpu687:1;
 160       unsigned int cpufisttp:1;
 161       unsigned int cpummx:1;
 162       unsigned int cpusse:1;
 163       unsigned int cpusse2:1;
 164       unsigned int cpua3dnow:1;
 165       unsigned int cpua3dnowa:1;
 166       unsigned int cpusse3:1;
 167       unsigned int cpupadlock:1;
 168       unsigned int cpusvme:1;
 169       unsigned int cpuvmx:1;
 170       unsigned int cpusmx:1;
 171       unsigned int cpussse3:1;
 172       unsigned int cpusse4a:1;
 173       unsigned int cpuabm:1;
 174       unsigned int cpusse4_1:1;
 175       unsigned int cpusse4_2:1;
 176       unsigned int cpuavx:1;
 177       unsigned int cpul1om:1;
 178       unsigned int cpuxsave:1;
 179       unsigned int cpuxsaveopt:1;
 180       unsigned int cpuaes:1;
 181       unsigned int cpupclmul:1;
 182       unsigned int cpufma:1;
 183       unsigned int cpufma4:1;
 184       unsigned int cpuxop:1;
 185       unsigned int cpulwp:1;
 186       unsigned int cpumovbe:1;
 187       unsigned int cpuept:1;
 188       unsigned int cpurdtscp:1;
 189       unsigned int cpufsgsbase:1;
 190       unsigned int cpurdrnd:1;
 191       unsigned int cpuf16c:1;
 192       unsigned int cpulm:1;
 193       unsigned int cpu64:1;
 194       unsigned int cpuno64:1;
 195 #ifdef CpuUnused
 196       unsigned int unused:(CpuNumOfBits - CpuUnused);
 197 #endif
 198     } bitfield;
 199   unsigned int array[CpuNumOfUints];
 200 } i386_cpu_flags;
 201
 202 /* Position of opcode_modifier bits.  */
 203
 204 enum
 205 {
 206   /* has direction bit. */
 207   D = 0,
 208   /* set if operands can be words or dwords encoded the canonical way */
 209   W,
 210   /* Skip the current insn and use the next insn in i386-opc.tbl to swap
 211      operand in encoding.  */
 212   S,
 213   /* insn has a modrm byte. */
 214   Modrm,
 215   /* register is in low 3 bits of opcode */
 216   ShortForm,
 217   /* special case for jump insns.  */
 218   Jump,
 219   /* call and jump */
 220   JumpDword,
 221   /* loop and jecxz */
 222   JumpByte,
 223   /* special case for intersegment leaps/calls */
 224   JumpInterSegment,
 225   /* FP insn memory format bit, sized by 0x4 */
 226   FloatMF,
 227   /* src/dest swap for floats. */
 228   FloatR,
 229   /* has float insn direction bit. */
 230   FloatD,
 231   /* needs size prefix if in 32-bit mode */
 232   Size16,
 233   /* needs size prefix if in 16-bit mode */
 234   Size32,
 235   /* needs size prefix if in 64-bit mode */
 236   Size64,
 237   /* instruction ignores operand size prefix and in Intel mode ignores
 238      mnemonic size suffix check.  */
 239   IgnoreSize,
 240   /* default insn size depends on mode */
 241   DefaultSize,
 242   /* b suffix on instruction illegal */
 243   No_bSuf,
 244   /* w suffix on instruction illegal */
 245   No_wSuf,
 246   /* l suffix on instruction illegal */
 247   No_lSuf,
 248   /* s suffix on instruction illegal */
 249   No_sSuf,
 250   /* q suffix on instruction illegal */
 251   No_qSuf,
 252   /* long double suffix on instruction illegal */
 253   No_ldSuf,
 254   /* instruction needs FWAIT */
 255   FWait,
 256   /* quick test for string instructions */
 257   IsString,
 258   /* quick test for lockable instructions */
 259   IsLockable,
 260   /* fake an extra reg operand for clr, imul and special register
 261      processing for some instructions.  */
 262   RegKludge,
 263   /* The first operand must be xmm0 */
 264   FirstXmm0,
 265   /* An implicit xmm0 as the first operand */
 266   Implicit1stXmm0,
 267   /* Convert to DWORD */
 268   ToDword,
 269   /* Convert to QWORD */
 270   ToQword,
 271   /* Address prefix changes operand 0 */
 272   AddrPrefixOp0,
 273   /* opcode is a prefix */
 274   IsPrefix,
 275   /* instruction has extension in 8 bit imm */
 276   ImmExt,
 277   /* instruction don't need Rex64 prefix.  */
 278   NoRex64,
 279   /* instruction require Rex64 prefix.  */
 280   Rex64,
 281   /* deprecated fp insn, gets a warning */
 282   Ugh,
 283   /* insn has VEX prefix:
 284         1: 128bit VEX prefix.
 285         2: 256bit VEX prefix.
 286         3: Scalar VEX prefix.
 287    */
 288 #define VEX128          1
 289 #define VEX256          2
 290 #define VEXScalar       3
 291   Vex,
 292   /* How to encode VEX.vvvv:
 293      0: VEX.vvvv must be 1111b.
 294      1: VEX.NDS.  Register-only source is encoded in VEX.vvvv where
 295         the content of source registers will be preserved.
 296         VEX.DDS.  The second register operand is encoded in VEX.vvvv
 297         where the content of first source register will be overwritten
 298         by the result.
 299         For assembler, there are no difference between VEX.NDS and
 300         VEX.DDS.
 301      2. VEX.NDD.  Register destination is encoded in VEX.vvvv.
 302      3. VEX.LWP.  Register destination is encoded in VEX.vvvv and one
 303         of the operands can access a memory location.
 304    */
 305 #define VEXXDS  1
 306 #define VEXNDD  2
 307 #define VEXLWP  3
 308   VexVVVV,
 309   /* How the VEX.W bit is used:
 310      0: Set by the REX.W bit.
 311      1: VEX.W0.  Should always be 0.
 312      2: VEX.W1.  Should always be 1.
 313    */
 314 #define VEXW0   1
 315 #define VEXW1   2
 316   VexW,
 317   /* VEX opcode prefix:
 318      0: VEX 0x0F opcode prefix.
 319      1: VEX 0x0F38 opcode prefix.
 320      2: VEX 0x0F3A opcode prefix
 321      3: XOP 0x08 opcode prefix.
 322      4: XOP 0x09 opcode prefix
 323      5: XOP 0x0A opcode prefix.
 324    */
 325 #define VEX0F           0
 326 #define VEX0F38         1
 327 #define VEX0F3A         2
 328 #define XOP08           3
 329 #define XOP09           4
 330 #define XOP0A           5
 331   VexOpcode,
 332   /* number of VEX source operands:
 333      0: <= 2 source operands.
 334      1: 2 XOP source operands.
 335      2: 3 source operands.
 336    */
 337 #define XOP2SOURCES     1
 338 #define VEX3SOURCES     2
 339   VexSources,
 340   /* instruction has VEX 8 bit imm */
 341   VexImmExt,
 342   /* SSE to AVX support required */
 343   SSE2AVX,
 344   /* No AVX equivalent */
 345   NoAVX,
 346   /* Compatible with old (<= 2.8.1) versions of gcc  */
 347   OldGcc,
 348   /* AT&T mnemonic.  */
 349   ATTMnemonic,
 350   /* AT&T syntax.  */
 351   ATTSyntax,
 352   /* Intel syntax.  */
 353   IntelSyntax,
 354   /* The last bitfield in i386_opcode_modifier.  */
 355   Opcode_Modifier_Max
 356 };
 357
 358 typedef struct i386_opcode_modifier
 359 {
 360   unsigned int d:1;
 361   unsigned int w:1;
 362   unsigned int s:1;
 363   unsigned int modrm:1;
 364   unsigned int shortform:1;
 365   unsigned int jump:1;
 366   unsigned int jumpdword:1;
 367   unsigned int jumpbyte:1;
 368   unsigned int jumpintersegment:1;
 369   unsigned int floatmf:1;
 370   unsigned int floatr:1;
 371   unsigned int floatd:1;
 372   unsigned int size16:1;
 373   unsigned int size32:1;
 374   unsigned int size64:1;
 375   unsigned int ignoresize:1;
 376   unsigned int defaultsize:1;
 377   unsigned int no_bsuf:1;
 378   unsigned int no_wsuf:1;
 379   unsigned int no_lsuf:1;
 380   unsigned int no_ssuf:1;
 381   unsigned int no_qsuf:1;
 382   unsigned int no_ldsuf:1;
 383   unsigned int fwait:1;
 384   unsigned int isstring:1;
 385   unsigned int islockable:1;
 386   unsigned int regkludge:1;
 387   unsigned int firstxmm0:1;
 388   unsigned int implicit1stxmm0:1;
 389   unsigned int todword:1;
 390   unsigned int toqword:1;
 391   unsigned int addrprefixop0:1;
 392   unsigned int isprefix:1;
 393   unsigned int immext:1;
 394   unsigned int norex64:1;
 395   unsigned int rex64:1;
 396   unsigned int ugh:1;
 397   unsigned int vex:2;
 398   unsigned int vexvvvv:2;
 399   unsigned int vexw:2;
 400   unsigned int vexopcode:3;
 401   unsigned int vexsources:2;
 402   unsigned int veximmext:1;
 403   unsigned int sse2avx:1;
 404   unsigned int noavx:1;
 405   unsigned int oldgcc:1;
 406   unsigned int attmnemonic:1;
 407   unsigned int attsyntax:1;
 408   unsigned int intelsyntax:1;
 409 } i386_opcode_modifier;
 410
 411 /* Position of operand_type bits.  */
 412
 413 enum
 414 {
 415   /* 8bit register */
 416   Reg8 = 0,
 417   /* 16bit register */
 418   Reg16,
 419   /* 32bit register */
 420   Reg32,
 421   /* 64bit register */
 422   Reg64,
 423   /* Floating pointer stack register */
 424   FloatReg,
 425   /* MMX register */
 426   RegMMX,
 427   /* SSE register */
 428   RegXMM,
 429   /* AVX registers */
 430   RegYMM,
 431   /* Control register */
 432   Control,
 433   /* Debug register */
 434   Debug,
 435   /* Test register */
 436   Test,
 437   /* 2 bit segment register */
 438   SReg2,
 439   /* 3 bit segment register */
 440   SReg3,
 441   /* 1 bit immediate */
 442   Imm1,
 443   /* 8 bit immediate */
 444   Imm8,
 445   /* 8 bit immediate sign extended */
 446   Imm8S,
 447   /* 16 bit immediate */
 448   Imm16,
 449   /* 32 bit immediate */
 450   Imm32,
 451   /* 32 bit immediate sign extended */
 452   Imm32S,
 453   /* 64 bit immediate */
 454   Imm64,
 455   /* 8bit/16bit/32bit displacements are used in different ways,
 456      depending on the instruction.  For jumps, they specify the
 457      size of the PC relative displacement, for instructions with
 458      memory operand, they specify the size of the offset relative
 459      to the base register, and for instructions with memory offset
 460      such as `mov 1234,%al' they specify the size of the offset
 461      relative to the segment base.  */
 462   /* 8 bit displacement */
 463   Disp8,
 464   /* 16 bit displacement */
 465   Disp16,
 466   /* 32 bit displacement */
 467   Disp32,
 468   /* 32 bit signed displacement */
 469   Disp32S,
 470   /* 64 bit displacement */
 471   Disp64,
 472   /* Accumulator %al/%ax/%eax/%rax */
 473   Acc,
 474   /* Floating pointer top stack register %st(0) */
 475   FloatAcc,
 476   /* Register which can be used for base or index in memory operand.  */
 477   BaseIndex,
 478   /* Register to hold in/out port addr = dx */
 479   InOutPortReg,
 480   /* Register to hold shift count = cl */
 481   ShiftCount,
 482   /* Absolute address for jump.  */
 483   JumpAbsolute,
 484   /* String insn operand with fixed es segment */
 485   EsSeg,
 486   /* RegMem is for instructions with a modrm byte where the register
 487      destination operand should be encoded in the mod and regmem fields.
 488      Normally, it will be encoded in the reg field. We add a RegMem
 489      flag to the destination register operand to indicate that it should
 490      be encoded in the regmem field.  */
 491   RegMem,
 492   /* Memory.  */
 493   Mem,
 494   /* BYTE memory. */
 495   Byte,
 496   /* WORD memory. 2 byte */
 497   Word,
 498   /* DWORD memory. 4 byte */
 499   Dword,
 500   /* FWORD memory. 6 byte */
 501   Fword,
 502   /* QWORD memory. 8 byte */
 503   Qword,
 504   /* TBYTE memory. 10 byte */
 505   Tbyte,
 506   /* XMMWORD memory. */
 507   Xmmword,
 508   /* YMMWORD memory. */
 509   Ymmword,
 510   /* Unspecified memory size.  */
 511   Unspecified,
 512   /* Any memory size.  */
 513   Anysize,
 514
 515   /* Vector 4 bit immediate.  */
 516   Vec_Imm4,
 517
 518   /* The last bitfield in i386_operand_type.  */
 519   OTMax
 520 };
 521
 522 #define OTNumOfUints \
 523   (OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
 524 #define OTNumOfBits \
 525   (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 526
 527 /* If you get a compiler error for zero width of the unused field,
 528    comment it out.  */
 529 #define OTUnused                (OTMax + 1)
 530
 531 typedef union i386_operand_type
 532 {
 533   struct
 534     {
 535       unsigned int reg8:1;
 536       unsigned int reg16:1;
 537       unsigned int reg32:1;
 538       unsigned int reg64:1;
 539       unsigned int floatreg:1;
 540       unsigned int regmmx:1;
 541       unsigned int regxmm:1;
 542       unsigned int regymm:1;
 543       unsigned int control:1;
 544       unsigned int debug:1;
 545       unsigned int test:1;
 546       unsigned int sreg2:1;
 547       unsigned int sreg3:1;
 548       unsigned int imm1:1;
 549       unsigned int imm8:1;
 550       unsigned int imm8s:1;
 551       unsigned int imm16:1;
 552       unsigned int imm32:1;
 553       unsigned int imm32s:1;
 554       unsigned int imm64:1;
 555       unsigned int disp8:1;
 556       unsigned int disp16:1;
 557       unsigned int disp32:1;
 558       unsigned int disp32s:1;
 559       unsigned int disp64:1;
 560       unsigned int acc:1;
 561       unsigned int floatacc:1;
 562       unsigned int baseindex:1;
 563       unsigned int inoutportreg:1;
 564       unsigned int shiftcount:1;
 565       unsigned int jumpabsolute:1;
 566       unsigned int esseg:1;
 567       unsigned int regmem:1;
 568       unsigned int mem:1;
 569       unsigned int byte:1;
 570       unsigned int word:1;
 571       unsigned int dword:1;
 572       unsigned int fword:1;
 573       unsigned int qword:1;
 574       unsigned int tbyte:1;
 575       unsigned int xmmword:1;
 576       unsigned int ymmword:1;
 577       unsigned int unspecified:1;
 578       unsigned int anysize:1;
 579       unsigned int vec_imm4:1;
 580 #ifdef OTUnused
 581       unsigned int unused:(OTNumOfBits - OTUnused);
 582 #endif
 583     } bitfield;
 584   unsigned int array[OTNumOfUints];
 585 } i386_operand_type;
 586
 587 typedef struct insn_template
 588 {
 589   /* instruction name sans width suffix ("mov" for movl insns) */
 590   char *name;
 591
 592   /* how many operands */
 593   unsigned int operands;
 594
 595   /* base_opcode is the fundamental opcode byte without optional
 596      prefix(es).  */
 597   unsigned int base_opcode;
 598 #define Opcode_D        0x2 /* Direction bit:
 599                                set if Reg --> Regmem;
 600                                unset if Regmem --> Reg. */
 601 #define Opcode_FloatR   0x8 /* Bit to swap src/dest for float insns. */
 602 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
 603
 604   /* extension_opcode is the 3 bit extension for group <n> insns.
 605      This field is also used to store the 8-bit opcode suffix for the
 606      AMD 3DNow! instructions.
 607      If this template has no extension opcode (the usual case) use None
 608      Instructions */
 609   unsigned int extension_opcode;
 610 #define None 0xffff             /* If no extension_opcode is possible.  */
 611
 612   /* Opcode length.  */
 613   unsigned char opcode_length;
 614
 615   /* cpu feature flags */
 616   i386_cpu_flags cpu_flags;
 617
 618   /* the bits in opcode_modifier are used to generate the final opcode from
 619      the base_opcode.  These bits also are used to detect alternate forms of
 620      the same instruction */
 621   i386_opcode_modifier opcode_modifier;
 622
 623   /* operand_types[i] describes the type of operand i.  This is made
 624      by OR'ing together all of the possible type masks.  (e.g.
 625      'operand_types[i] = Reg|Imm' specifies that operand i can be
 626      either a register or an immediate operand.  */
 627   i386_operand_type operand_types[MAX_OPERANDS];
 628 }
 629 insn_template;
 630
 631 extern const insn_template i386_optab[];
 632
 633 /* these are for register name --> number & type hash lookup */
 634 typedef struct
 635 {
 636   char *reg_name;
 637   i386_operand_type reg_type;
 638   unsigned char reg_flags;
 639 #define RegRex      0x1  /* Extended register.  */
 640 #define RegRex64    0x2  /* Extended 8 bit register.  */
 641   unsigned char reg_num;
 642 #define RegRip  ((unsigned char ) ~0)
 643 #define RegEip  (RegRip - 1)
 644 /* EIZ and RIZ are fake index registers.  */
 645 #define RegEiz  (RegEip - 1)
 646 #define RegRiz  (RegEiz - 1)
 647 /* FLAT is a fake segment register (Intel mode).  */
 648 #define RegFlat     ((unsigned char) ~0)
 649   signed char dw2_regnum[2];
 650 #define Dw2Inval (-1)
 651 }
 652 reg_entry;
 653
 654 /* Entries in i386_regtab.  */
 655 #define REGNAM_AL 1
 656 #define REGNAM_AX 25
 657 #define REGNAM_EAX 41
 658
 659 extern const reg_entry i386_regtab[];
 660 extern const unsigned int i386_regtab_size;
 661
 662 typedef struct
 663 {
 664   char *seg_name;
 665   unsigned int seg_prefix;
 666 }
 667 seg_entry;
 668
 669 extern const seg_entry cs;
 670 extern const seg_entry ds;
 671 extern const seg_entry ss;
 672 extern const seg_entry es;
 673 extern const seg_entry fs;
 674 extern const seg_entry gs;