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include/opcode/
[binutils.git] / opcodes / mips-dis.c
blobca65d71f59960fbd9ce04cf4374f0610761c719c
1 /* Print mips instructions for GDB, the GNU debugger, or for objdump.
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
5 Contributed by Nobuyuki Hikichi(hikichi@sra.co.jp).
6
7 This file is part of the GNU opcodes library.
8
9 This library is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
12 any later version.
13
14 It is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
22 MA 02110-1301, USA. */
23
24 #include "sysdep.h"
25 #include "dis-asm.h"
26 #include "libiberty.h"
27 #include "opcode/mips.h"
28 #include "opintl.h"
29
30 /* FIXME: These are needed to figure out if the code is mips16 or
31 not. The low bit of the address is often a good indicator. No
32 symbol table is available when this code runs out in an embedded
33 system as when it is used for disassembler support in a monitor. */
34
35 #if !defined(EMBEDDED_ENV)
36 #define SYMTAB_AVAILABLE 1
37 #include "elf-bfd.h"
38 #include "elf/mips.h"
39 #endif
40
41 /* Mips instructions are at maximum this many bytes long. */
42 #define INSNLEN 4
43
44 \f
45 /* FIXME: These should be shared with gdb somehow. */
46
47 struct mips_cp0sel_name
48 {
49 unsigned int cp0reg;
50 unsigned int sel;
51 const char * const name;
52 };
53
54 /* The mips16 registers. */
55 static const unsigned int mips16_to_32_reg_map[] =
56 {
57 16, 17, 2, 3, 4, 5, 6, 7
58 };
59
60 #define mips16_reg_names(rn) mips_gpr_names[mips16_to_32_reg_map[rn]]
61
62
63 static const char * const mips_gpr_names_numeric[32] =
64 {
65 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
66 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
67 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
68 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
69 };
70
71 static const char * const mips_gpr_names_oldabi[32] =
72 {
73 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
74 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
75 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
76 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
77 };
78
79 static const char * const mips_gpr_names_newabi[32] =
80 {
81 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
82 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
83 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
84 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
85 };
86
87 static const char * const mips_fpr_names_numeric[32] =
88 {
89 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
90 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
91 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
92 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31"
93 };
94
95 static const char * const mips_fpr_names_32[32] =
96 {
97 "fv0", "fv0f", "fv1", "fv1f", "ft0", "ft0f", "ft1", "ft1f",
98 "ft2", "ft2f", "ft3", "ft3f", "fa0", "fa0f", "fa1", "fa1f",
99 "ft4", "ft4f", "ft5", "ft5f", "fs0", "fs0f", "fs1", "fs1f",
100 "fs2", "fs2f", "fs3", "fs3f", "fs4", "fs4f", "fs5", "fs5f"
101 };
102
103 static const char * const mips_fpr_names_n32[32] =
104 {
105 "fv0", "ft14", "fv1", "ft15", "ft0", "ft1", "ft2", "ft3",
106 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3",
107 "fa4", "fa5", "fa6", "fa7", "fs0", "ft8", "fs1", "ft9",
108 "fs2", "ft10", "fs3", "ft11", "fs4", "ft12", "fs5", "ft13"
109 };
110
111 static const char * const mips_fpr_names_64[32] =
112 {
113 "fv0", "ft12", "fv1", "ft13", "ft0", "ft1", "ft2", "ft3",
114 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3",
115 "fa4", "fa5", "fa6", "fa7", "ft8", "ft9", "ft10", "ft11",
116 "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7"
117 };
118
119 static const char * const mips_cp0_names_numeric[32] =
120 {
121 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
122 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
123 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
124 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
125 };
126
127 static const char * const mips_cp0_names_r3000[32] =
128 {
129 "c0_index", "c0_random", "c0_entrylo", "$3",
130 "c0_context", "$5", "$6", "$7",
131 "c0_badvaddr", "$9", "c0_entryhi", "$11",
132 "c0_sr", "c0_cause", "c0_epc", "c0_prid",
133 "$16", "$17", "$18", "$19",
134 "$20", "$21", "$22", "$23",
135 "$24", "$25", "$26", "$27",
136 "$28", "$29", "$30", "$31",
137 };
138
139 static const char * const mips_cp0_names_r4000[32] =
140 {
141 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
142 "c0_context", "c0_pagemask", "c0_wired", "$7",
143 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
144 "c0_sr", "c0_cause", "c0_epc", "c0_prid",
145 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
146 "c0_xcontext", "$21", "$22", "$23",
147 "$24", "$25", "c0_ecc", "c0_cacheerr",
148 "c0_taglo", "c0_taghi", "c0_errorepc", "$31",
149 };
150
151 static const char * const mips_cp0_names_mips3264[32] =
152 {
153 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
154 "c0_context", "c0_pagemask", "c0_wired", "$7",
155 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
156 "c0_status", "c0_cause", "c0_epc", "c0_prid",
157 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
158 "c0_xcontext", "$21", "$22", "c0_debug",
159 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr",
160 "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave",
161 };
162
163 static const struct mips_cp0sel_name mips_cp0sel_names_mips3264[] =
164 {
165 { 16, 1, "c0_config1" },
166 { 16, 2, "c0_config2" },
167 { 16, 3, "c0_config3" },
168 { 18, 1, "c0_watchlo,1" },
169 { 18, 2, "c0_watchlo,2" },
170 { 18, 3, "c0_watchlo,3" },
171 { 18, 4, "c0_watchlo,4" },
172 { 18, 5, "c0_watchlo,5" },
173 { 18, 6, "c0_watchlo,6" },
174 { 18, 7, "c0_watchlo,7" },
175 { 19, 1, "c0_watchhi,1" },
176 { 19, 2, "c0_watchhi,2" },
177 { 19, 3, "c0_watchhi,3" },
178 { 19, 4, "c0_watchhi,4" },
179 { 19, 5, "c0_watchhi,5" },
180 { 19, 6, "c0_watchhi,6" },
181 { 19, 7, "c0_watchhi,7" },
182 { 25, 1, "c0_perfcnt,1" },
183 { 25, 2, "c0_perfcnt,2" },
184 { 25, 3, "c0_perfcnt,3" },
185 { 25, 4, "c0_perfcnt,4" },
186 { 25, 5, "c0_perfcnt,5" },
187 { 25, 6, "c0_perfcnt,6" },
188 { 25, 7, "c0_perfcnt,7" },
189 { 27, 1, "c0_cacheerr,1" },
190 { 27, 2, "c0_cacheerr,2" },
191 { 27, 3, "c0_cacheerr,3" },
192 { 28, 1, "c0_datalo" },
193 { 29, 1, "c0_datahi" }
194 };
195
196 static const char * const mips_cp0_names_mips3264r2[32] =
197 {
198 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
199 "c0_context", "c0_pagemask", "c0_wired", "c0_hwrena",
200 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
201 "c0_status", "c0_cause", "c0_epc", "c0_prid",
202 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
203 "c0_xcontext", "$21", "$22", "c0_debug",
204 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr",
205 "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave",
206 };
207
208 static const struct mips_cp0sel_name mips_cp0sel_names_mips3264r2[] =
209 {
210 { 4, 1, "c0_contextconfig" },
211 { 0, 1, "c0_mvpcontrol" },
212 { 0, 2, "c0_mvpconf0" },
213 { 0, 3, "c0_mvpconf1" },
214 { 1, 1, "c0_vpecontrol" },
215 { 1, 2, "c0_vpeconf0" },
216 { 1, 3, "c0_vpeconf1" },
217 { 1, 4, "c0_yqmask" },
218 { 1, 5, "c0_vpeschedule" },
219 { 1, 6, "c0_vpeschefback" },
220 { 2, 1, "c0_tcstatus" },
221 { 2, 2, "c0_tcbind" },
222 { 2, 3, "c0_tcrestart" },
223 { 2, 4, "c0_tchalt" },
224 { 2, 5, "c0_tccontext" },
225 { 2, 6, "c0_tcschedule" },
226 { 2, 7, "c0_tcschefback" },
227 { 5, 1, "c0_pagegrain" },
228 { 6, 1, "c0_srsconf0" },
229 { 6, 2, "c0_srsconf1" },
230 { 6, 3, "c0_srsconf2" },
231 { 6, 4, "c0_srsconf3" },
232 { 6, 5, "c0_srsconf4" },
233 { 12, 1, "c0_intctl" },
234 { 12, 2, "c0_srsctl" },
235 { 12, 3, "c0_srsmap" },
236 { 15, 1, "c0_ebase" },
237 { 16, 1, "c0_config1" },
238 { 16, 2, "c0_config2" },
239 { 16, 3, "c0_config3" },
240 { 18, 1, "c0_watchlo,1" },
241 { 18, 2, "c0_watchlo,2" },
242 { 18, 3, "c0_watchlo,3" },
243 { 18, 4, "c0_watchlo,4" },
244 { 18, 5, "c0_watchlo,5" },
245 { 18, 6, "c0_watchlo,6" },
246 { 18, 7, "c0_watchlo,7" },
247 { 19, 1, "c0_watchhi,1" },
248 { 19, 2, "c0_watchhi,2" },
249 { 19, 3, "c0_watchhi,3" },
250 { 19, 4, "c0_watchhi,4" },
251 { 19, 5, "c0_watchhi,5" },
252 { 19, 6, "c0_watchhi,6" },
253 { 19, 7, "c0_watchhi,7" },
254 { 23, 1, "c0_tracecontrol" },
255 { 23, 2, "c0_tracecontrol2" },
256 { 23, 3, "c0_usertracedata" },
257 { 23, 4, "c0_tracebpc" },
258 { 25, 1, "c0_perfcnt,1" },
259 { 25, 2, "c0_perfcnt,2" },
260 { 25, 3, "c0_perfcnt,3" },
261 { 25, 4, "c0_perfcnt,4" },
262 { 25, 5, "c0_perfcnt,5" },
263 { 25, 6, "c0_perfcnt,6" },
264 { 25, 7, "c0_perfcnt,7" },
265 { 27, 1, "c0_cacheerr,1" },
266 { 27, 2, "c0_cacheerr,2" },
267 { 27, 3, "c0_cacheerr,3" },
268 { 28, 1, "c0_datalo" },
269 { 28, 2, "c0_taglo1" },
270 { 28, 3, "c0_datalo1" },
271 { 28, 4, "c0_taglo2" },
272 { 28, 5, "c0_datalo2" },
273 { 28, 6, "c0_taglo3" },
274 { 28, 7, "c0_datalo3" },
275 { 29, 1, "c0_datahi" },
276 { 29, 2, "c0_taghi1" },
277 { 29, 3, "c0_datahi1" },
278 { 29, 4, "c0_taghi2" },
279 { 29, 5, "c0_datahi2" },
280 { 29, 6, "c0_taghi3" },
281 { 29, 7, "c0_datahi3" },
282 };
283
284 /* SB-1: MIPS64 (mips_cp0_names_mips3264) with minor mods. */
285 static const char * const mips_cp0_names_sb1[32] =
286 {
287 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
288 "c0_context", "c0_pagemask", "c0_wired", "$7",
289 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
290 "c0_status", "c0_cause", "c0_epc", "c0_prid",
291 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
292 "c0_xcontext", "$21", "$22", "c0_debug",
293 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr_i",
294 "c0_taglo_i", "c0_taghi_i", "c0_errorepc", "c0_desave",
295 };
296
297 static const struct mips_cp0sel_name mips_cp0sel_names_sb1[] =
298 {
299 { 16, 1, "c0_config1" },
300 { 18, 1, "c0_watchlo,1" },
301 { 19, 1, "c0_watchhi,1" },
302 { 22, 0, "c0_perftrace" },
303 { 23, 3, "c0_edebug" },
304 { 25, 1, "c0_perfcnt,1" },
305 { 25, 2, "c0_perfcnt,2" },
306 { 25, 3, "c0_perfcnt,3" },
307 { 25, 4, "c0_perfcnt,4" },
308 { 25, 5, "c0_perfcnt,5" },
309 { 25, 6, "c0_perfcnt,6" },
310 { 25, 7, "c0_perfcnt,7" },
311 { 26, 1, "c0_buserr_pa" },
312 { 27, 1, "c0_cacheerr_d" },
313 { 27, 3, "c0_cacheerr_d_pa" },
314 { 28, 1, "c0_datalo_i" },
315 { 28, 2, "c0_taglo_d" },
316 { 28, 3, "c0_datalo_d" },
317 { 29, 1, "c0_datahi_i" },
318 { 29, 2, "c0_taghi_d" },
319 { 29, 3, "c0_datahi_d" },
320 };
321
322 /* Xlr cop0 register names. */
323 static const char * const mips_cp0_names_xlr[32] = {
324 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
325 "c0_context", "c0_pagemask", "c0_wired", "$7",
326 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
327 "c0_status", "c0_cause", "c0_epc", "c0_prid",
328 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
329 "c0_xcontext", "$21", "$22", "c0_debug",
330 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr_i",
331 "c0_taglo_i", "c0_taghi_i", "c0_errorepc", "c0_desave",
332 };
333
334 /* XLR's CP0 Select Registers. */
335
336 static const struct mips_cp0sel_name mips_cp0sel_names_xlr[] = {
337 { 9, 6, "c0_extintreq" },
338 { 9, 7, "c0_extintmask" },
339 { 15, 1, "c0_ebase" },
340 { 16, 1, "c0_config1" },
341 { 16, 2, "c0_config2" },
342 { 16, 3, "c0_config3" },
343 { 16, 7, "c0_procid2" },
344 { 18, 1, "c0_watchlo,1" },
345 { 18, 2, "c0_watchlo,2" },
346 { 18, 3, "c0_watchlo,3" },
347 { 18, 4, "c0_watchlo,4" },
348 { 18, 5, "c0_watchlo,5" },
349 { 18, 6, "c0_watchlo,6" },
350 { 18, 7, "c0_watchlo,7" },
351 { 19, 1, "c0_watchhi,1" },
352 { 19, 2, "c0_watchhi,2" },
353 { 19, 3, "c0_watchhi,3" },
354 { 19, 4, "c0_watchhi,4" },
355 { 19, 5, "c0_watchhi,5" },
356 { 19, 6, "c0_watchhi,6" },
357 { 19, 7, "c0_watchhi,7" },
358 { 25, 1, "c0_perfcnt,1" },
359 { 25, 2, "c0_perfcnt,2" },
360 { 25, 3, "c0_perfcnt,3" },
361 { 25, 4, "c0_perfcnt,4" },
362 { 25, 5, "c0_perfcnt,5" },
363 { 25, 6, "c0_perfcnt,6" },
364 { 25, 7, "c0_perfcnt,7" },
365 { 27, 1, "c0_cacheerr,1" },
366 { 27, 2, "c0_cacheerr,2" },
367 { 27, 3, "c0_cacheerr,3" },
368 { 28, 1, "c0_datalo" },
369 { 29, 1, "c0_datahi" }
370 };
371
372 static const char * const mips_hwr_names_numeric[32] =
373 {
374 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
375 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
376 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
377 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
378 };
379
380 static const char * const mips_hwr_names_mips3264r2[32] =
381 {
382 "hwr_cpunum", "hwr_synci_step", "hwr_cc", "hwr_ccres",
383 "$4", "$5", "$6", "$7",
384 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
385 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
386 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
387 };
388
389 struct mips_abi_choice
390 {
391 const char * name;
392 const char * const *gpr_names;
393 const char * const *fpr_names;
394 };
395
396 struct mips_abi_choice mips_abi_choices[] =
397 {
398 { "numeric", mips_gpr_names_numeric, mips_fpr_names_numeric },
399 { "32", mips_gpr_names_oldabi, mips_fpr_names_32 },
400 { "n32", mips_gpr_names_newabi, mips_fpr_names_n32 },
401 { "64", mips_gpr_names_newabi, mips_fpr_names_64 },
402 };
403
404 struct mips_arch_choice
405 {
406 const char *name;
407 int bfd_mach_valid;
408 unsigned long bfd_mach;
409 int processor;
410 int isa;
411 const char * const *cp0_names;
412 const struct mips_cp0sel_name *cp0sel_names;
413 unsigned int cp0sel_names_len;
414 const char * const *hwr_names;
415 };
416
417 const struct mips_arch_choice mips_arch_choices[] =
418 {
419 { "numeric", 0, 0, 0, 0,
420 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
421
422 { "r3000", 1, bfd_mach_mips3000, CPU_R3000, ISA_MIPS1,
423 mips_cp0_names_r3000, NULL, 0, mips_hwr_names_numeric },
424 { "r3900", 1, bfd_mach_mips3900, CPU_R3900, ISA_MIPS1,
425 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
426 { "r4000", 1, bfd_mach_mips4000, CPU_R4000, ISA_MIPS3,
427 mips_cp0_names_r4000, NULL, 0, mips_hwr_names_numeric },
428 { "r4010", 1, bfd_mach_mips4010, CPU_R4010, ISA_MIPS2,
429 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
430 { "vr4100", 1, bfd_mach_mips4100, CPU_VR4100, ISA_MIPS3,
431 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
432 { "vr4111", 1, bfd_mach_mips4111, CPU_R4111, ISA_MIPS3,
433 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
434 { "vr4120", 1, bfd_mach_mips4120, CPU_VR4120, ISA_MIPS3,
435 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
436 { "r4300", 1, bfd_mach_mips4300, CPU_R4300, ISA_MIPS3,
437 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
438 { "r4400", 1, bfd_mach_mips4400, CPU_R4400, ISA_MIPS3,
439 mips_cp0_names_r4000, NULL, 0, mips_hwr_names_numeric },
440 { "r4600", 1, bfd_mach_mips4600, CPU_R4600, ISA_MIPS3,
441 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
442 { "r4650", 1, bfd_mach_mips4650, CPU_R4650, ISA_MIPS3,
443 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
444 { "r5000", 1, bfd_mach_mips5000, CPU_R5000, ISA_MIPS4,
445 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
446 { "vr5400", 1, bfd_mach_mips5400, CPU_VR5400, ISA_MIPS4,
447 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
448 { "vr5500", 1, bfd_mach_mips5500, CPU_VR5500, ISA_MIPS4,
449 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
450 { "r6000", 1, bfd_mach_mips6000, CPU_R6000, ISA_MIPS2,
451 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
452 { "rm7000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4,
453 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
454 { "rm9000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4,
455 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
456 { "r8000", 1, bfd_mach_mips8000, CPU_R8000, ISA_MIPS4,
457 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
458 { "r10000", 1, bfd_mach_mips10000, CPU_R10000, ISA_MIPS4,
459 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
460 { "r12000", 1, bfd_mach_mips12000, CPU_R12000, ISA_MIPS4,
461 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
462 { "r14000", 1, bfd_mach_mips14000, CPU_R14000, ISA_MIPS4,
463 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
464 { "r16000", 1, bfd_mach_mips16000, CPU_R16000, ISA_MIPS4,
465 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
466 { "mips5", 1, bfd_mach_mips5, CPU_MIPS5, ISA_MIPS5,
467 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
468
469 /* For stock MIPS32, disassemble all applicable MIPS-specified ASEs.
470 Note that MIPS-3D and MDMX are not applicable to MIPS32. (See
471 _MIPS32 Architecture For Programmers Volume I: Introduction to the
472 MIPS32 Architecture_ (MIPS Document Number MD00082, Revision 0.95),
473 page 1. */
474 { "mips32", 1, bfd_mach_mipsisa32, CPU_MIPS32,
475 ISA_MIPS32 | INSN_SMARTMIPS,
476 mips_cp0_names_mips3264,
477 mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
478 mips_hwr_names_numeric },
479
480 { "mips32r2", 1, bfd_mach_mipsisa32r2, CPU_MIPS32R2,
481 (ISA_MIPS32R2 | INSN_SMARTMIPS | INSN_DSP | INSN_DSPR2
482 | INSN_MIPS3D | INSN_MT),
483 mips_cp0_names_mips3264r2,
484 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
485 mips_hwr_names_mips3264r2 },
486
487 /* For stock MIPS64, disassemble all applicable MIPS-specified ASEs. */
488 { "mips64", 1, bfd_mach_mipsisa64, CPU_MIPS64,
489 ISA_MIPS64 | INSN_MIPS3D | INSN_MDMX,
490 mips_cp0_names_mips3264,
491 mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
492 mips_hwr_names_numeric },
493
494 { "mips64r2", 1, bfd_mach_mipsisa64r2, CPU_MIPS64R2,
495 (ISA_MIPS64R2 | INSN_MIPS3D | INSN_DSP | INSN_DSPR2
496 | INSN_DSP64 | INSN_MT | INSN_MDMX),
497 mips_cp0_names_mips3264r2,
498 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
499 mips_hwr_names_mips3264r2 },
500
501 { "sb1", 1, bfd_mach_mips_sb1, CPU_SB1,
502 ISA_MIPS64 | INSN_MIPS3D | INSN_SB1,
503 mips_cp0_names_sb1,
504 mips_cp0sel_names_sb1, ARRAY_SIZE (mips_cp0sel_names_sb1),
505 mips_hwr_names_numeric },
506
507 { "loongson2e", 1, bfd_mach_mips_loongson_2e, CPU_LOONGSON_2E,
508 ISA_MIPS3 | INSN_LOONGSON_2E, mips_cp0_names_numeric,
509 NULL, 0, mips_hwr_names_numeric },
510
511 { "loongson2f", 1, bfd_mach_mips_loongson_2f, CPU_LOONGSON_2F,
512 ISA_MIPS3 | INSN_LOONGSON_2F, mips_cp0_names_numeric,
513 NULL, 0, mips_hwr_names_numeric },
514
515 { "loongson3a", 1, bfd_mach_mips_loongson_3a, CPU_LOONGSON_3A,
516 ISA_MIPS64 | INSN_LOONGSON_3A, mips_cp0_names_numeric,
517 NULL, 0, mips_hwr_names_numeric },
518
519 { "octeon", 1, bfd_mach_mips_octeon, CPU_OCTEON,
520 ISA_MIPS64R2 | INSN_OCTEON, mips_cp0_names_numeric, NULL, 0,
521 mips_hwr_names_numeric },
522
523 { "xlr", 1, bfd_mach_mips_xlr, CPU_XLR,
524 ISA_MIPS64 | INSN_XLR,
525 mips_cp0_names_xlr,
526 mips_cp0sel_names_xlr, ARRAY_SIZE (mips_cp0sel_names_xlr),
527 mips_hwr_names_numeric },
528
529 /* This entry, mips16, is here only for ISA/processor selection; do
530 not print its name. */
531 { "", 1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS3,
532 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
533 };
534
535 /* ISA and processor type to disassemble for, and register names to use.
536 set_default_mips_dis_options and parse_mips_dis_options fill in these
537 values. */
538 static int mips_processor;
539 static int mips_isa;
540 static const char * const *mips_gpr_names;
541 static const char * const *mips_fpr_names;
542 static const char * const *mips_cp0_names;
543 static const struct mips_cp0sel_name *mips_cp0sel_names;
544 static int mips_cp0sel_names_len;
545 static const char * const *mips_hwr_names;
546
547 /* Other options */
548 static int no_aliases; /* If set disassemble as most general inst. */
549 \f
550 static const struct mips_abi_choice *
551 choose_abi_by_name (const char *name, unsigned int namelen)
552 {
553 const struct mips_abi_choice *c;
554 unsigned int i;
555
556 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_abi_choices) && c == NULL; i++)
557 if (strncmp (mips_abi_choices[i].name, name, namelen) == 0
558 && strlen (mips_abi_choices[i].name) == namelen)
559 c = &mips_abi_choices[i];
560
561 return c;
562 }
563
564 static const struct mips_arch_choice *
565 choose_arch_by_name (const char *name, unsigned int namelen)
566 {
567 const struct mips_arch_choice *c = NULL;
568 unsigned int i;
569
570 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++)
571 if (strncmp (mips_arch_choices[i].name, name, namelen) == 0
572 && strlen (mips_arch_choices[i].name) == namelen)
573 c = &mips_arch_choices[i];
574
575 return c;
576 }
577
578 static const struct mips_arch_choice *
579 choose_arch_by_number (unsigned long mach)
580 {
581 static unsigned long hint_bfd_mach;
582 static const struct mips_arch_choice *hint_arch_choice;
583 const struct mips_arch_choice *c;
584 unsigned int i;
585
586 /* We optimize this because even if the user specifies no
587 flags, this will be done for every instruction! */
588 if (hint_bfd_mach == mach
589 && hint_arch_choice != NULL
590 && hint_arch_choice->bfd_mach == hint_bfd_mach)
591 return hint_arch_choice;
592
593 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++)
594 {
595 if (mips_arch_choices[i].bfd_mach_valid
596 && mips_arch_choices[i].bfd_mach == mach)
597 {
598 c = &mips_arch_choices[i];
599 hint_bfd_mach = mach;
600 hint_arch_choice = c;
601 }
602 }
603 return c;
604 }
605
606 /* Check if the object uses NewABI conventions. */
607
608 static int
609 is_newabi (Elf_Internal_Ehdr *header)
610 {
611 /* There are no old-style ABIs which use 64-bit ELF. */
612 if (header->e_ident[EI_CLASS] == ELFCLASS64)
613 return 1;
614
615 /* If a 32-bit ELF file, n32 is a new-style ABI. */
616 if ((header->e_flags & EF_MIPS_ABI2) != 0)
617 return 1;
618
619 return 0;
620 }
621
622 static void
623 set_default_mips_dis_options (struct disassemble_info *info)
624 {
625 const struct mips_arch_choice *chosen_arch;
626
627 /* Defaults: mipsIII/r3000 (?!), (o)32-style ("oldabi") GPR names,
628 and numeric FPR, CP0 register, and HWR names. */
629 mips_isa = ISA_MIPS3;
630 mips_processor = CPU_R3000;
631 mips_gpr_names = mips_gpr_names_oldabi;
632 mips_fpr_names = mips_fpr_names_numeric;
633 mips_cp0_names = mips_cp0_names_numeric;
634 mips_cp0sel_names = NULL;
635 mips_cp0sel_names_len = 0;
636 mips_hwr_names = mips_hwr_names_numeric;
637 no_aliases = 0;
638
639 /* If an ELF "newabi" binary, use the n32/(n)64 GPR names. */
640 if (info->flavour == bfd_target_elf_flavour && info->section != NULL)
641 {
642 Elf_Internal_Ehdr *header;
643
644 header = elf_elfheader (info->section->owner);
645 if (is_newabi (header))
646 mips_gpr_names = mips_gpr_names_newabi;
647 }
648
649 /* Set ISA, architecture, and cp0 register names as best we can. */
650 #if ! SYMTAB_AVAILABLE
651 /* This is running out on a target machine, not in a host tool.
652 FIXME: Where does mips_target_info come from? */
653 target_processor = mips_target_info.processor;
654 mips_isa = mips_target_info.isa;
655 #else
656 chosen_arch = choose_arch_by_number (info->mach);
657 if (chosen_arch != NULL)
658 {
659 mips_processor = chosen_arch->processor;
660 mips_isa = chosen_arch->isa;
661 mips_cp0_names = chosen_arch->cp0_names;
662 mips_cp0sel_names = chosen_arch->cp0sel_names;
663 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
664 mips_hwr_names = chosen_arch->hwr_names;
665 }
666 #endif
667 }
668
669 static void
670 parse_mips_dis_option (const char *option, unsigned int len)
671 {
672 unsigned int i, optionlen, vallen;
673 const char *val;
674 const struct mips_abi_choice *chosen_abi;
675 const struct mips_arch_choice *chosen_arch;
676
677 /* Try to match options that are simple flags */
678 if (CONST_STRNEQ (option, "no-aliases"))
679 {
680 no_aliases = 1;
681 return;
682 }
683
684 /* Look for the = that delimits the end of the option name. */
685 for (i = 0; i < len; i++)
686 if (option[i] == '=')
687 break;
688
689 if (i == 0) /* Invalid option: no name before '='. */
690 return;
691 if (i == len) /* Invalid option: no '='. */
692 return;
693 if (i == (len - 1)) /* Invalid option: no value after '='. */
694 return;
695
696 optionlen = i;
697 val = option + (optionlen + 1);
698 vallen = len - (optionlen + 1);
699
700 if (strncmp ("gpr-names", option, optionlen) == 0
701 && strlen ("gpr-names") == optionlen)
702 {
703 chosen_abi = choose_abi_by_name (val, vallen);
704 if (chosen_abi != NULL)
705 mips_gpr_names = chosen_abi->gpr_names;
706 return;
707 }
708
709 if (strncmp ("fpr-names", option, optionlen) == 0
710 && strlen ("fpr-names") == optionlen)
711 {
712 chosen_abi = choose_abi_by_name (val, vallen);
713 if (chosen_abi != NULL)
714 mips_fpr_names = chosen_abi->fpr_names;
715 return;
716 }
717
718 if (strncmp ("cp0-names", option, optionlen) == 0
719 && strlen ("cp0-names") == optionlen)
720 {
721 chosen_arch = choose_arch_by_name (val, vallen);
722 if (chosen_arch != NULL)
723 {
724 mips_cp0_names = chosen_arch->cp0_names;
725 mips_cp0sel_names = chosen_arch->cp0sel_names;
726 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
727 }
728 return;
729 }
730
731 if (strncmp ("hwr-names", option, optionlen) == 0
732 && strlen ("hwr-names") == optionlen)
733 {
734 chosen_arch = choose_arch_by_name (val, vallen);
735 if (chosen_arch != NULL)
736 mips_hwr_names = chosen_arch->hwr_names;
737 return;
738 }
739
740 if (strncmp ("reg-names", option, optionlen) == 0
741 && strlen ("reg-names") == optionlen)
742 {
743 /* We check both ABI and ARCH here unconditionally, so
744 that "numeric" will do the desirable thing: select
745 numeric register names for all registers. Other than
746 that, a given name probably won't match both. */
747 chosen_abi = choose_abi_by_name (val, vallen);
748 if (chosen_abi != NULL)
749 {
750 mips_gpr_names = chosen_abi->gpr_names;
751 mips_fpr_names = chosen_abi->fpr_names;
752 }
753 chosen_arch = choose_arch_by_name (val, vallen);
754 if (chosen_arch != NULL)
755 {
756 mips_cp0_names = chosen_arch->cp0_names;
757 mips_cp0sel_names = chosen_arch->cp0sel_names;
758 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
759 mips_hwr_names = chosen_arch->hwr_names;
760 }
761 return;
762 }
763
764 /* Invalid option. */
765 }
766
767 static void
768 parse_mips_dis_options (const char *options)
769 {
770 const char *option_end;
771
772 if (options == NULL)
773 return;
774
775 while (*options != '\0')
776 {
777 /* Skip empty options. */
778 if (*options == ',')
779 {
780 options++;
781 continue;
782 }
783
784 /* We know that *options is neither NUL or a comma. */
785 option_end = options + 1;
786 while (*option_end != ',' && *option_end != '\0')
787 option_end++;
788
789 parse_mips_dis_option (options, option_end - options);
790
791 /* Go on to the next one. If option_end points to a comma, it
792 will be skipped above. */
793 options = option_end;
794 }
795 }
796
797 static const struct mips_cp0sel_name *
798 lookup_mips_cp0sel_name (const struct mips_cp0sel_name *names,
799 unsigned int len,
800 unsigned int cp0reg,
801 unsigned int sel)
802 {
803 unsigned int i;
804
805 for (i = 0; i < len; i++)
806 if (names[i].cp0reg == cp0reg && names[i].sel == sel)
807 return &names[i];
808 return NULL;
809 }
810 \f
811 /* Print insn arguments for 32/64-bit code. */
812
813 static void
814 print_insn_args (const char *d,
815 register unsigned long int l,
816 bfd_vma pc,
817 struct disassemble_info *info,
818 const struct mips_opcode *opp)
819 {
820 int op, delta;
821 unsigned int lsb, msb, msbd;
822
823 lsb = 0;
824
825 for (; *d != '\0'; d++)
826 {
827 switch (*d)
828 {
829 case ',':
830 case '(':
831 case ')':
832 case '[':
833 case ']':
834 (*info->fprintf_func) (info->stream, "%c", *d);
835 break;
836
837 case '+':
838 /* Extension character; switch for second char. */
839 d++;
840 switch (*d)
841 {
842 case '\0':
843 /* xgettext:c-format */
844 (*info->fprintf_func) (info->stream,
845 _("# internal error, incomplete extension sequence (+)"));
846 return;
847
848 case 'A':
849 lsb = (l >> OP_SH_SHAMT) & OP_MASK_SHAMT;
850 (*info->fprintf_func) (info->stream, "0x%x", lsb);
851 break;
852
853 case 'B':
854 msb = (l >> OP_SH_INSMSB) & OP_MASK_INSMSB;
855 (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1);
856 break;
857
858 case '1':
859 (*info->fprintf_func) (info->stream, "0x%lx",
860 (l >> OP_SH_UDI1) & OP_MASK_UDI1);
861 break;
862
863 case '2':
864 (*info->fprintf_func) (info->stream, "0x%lx",
865 (l >> OP_SH_UDI2) & OP_MASK_UDI2);
866 break;
867
868 case '3':
869 (*info->fprintf_func) (info->stream, "0x%lx",
870 (l >> OP_SH_UDI3) & OP_MASK_UDI3);
871 break;
872
873 case '4':
874 (*info->fprintf_func) (info->stream, "0x%lx",
875 (l >> OP_SH_UDI4) & OP_MASK_UDI4);
876 break;
877
878 case 'C':
879 case 'H':
880 msbd = (l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD;
881 (*info->fprintf_func) (info->stream, "0x%x", msbd + 1);
882 break;
883
884 case 'D':
885 {
886 const struct mips_cp0sel_name *n;
887 unsigned int cp0reg, sel;
888
889 cp0reg = (l >> OP_SH_RD) & OP_MASK_RD;
890 sel = (l >> OP_SH_SEL) & OP_MASK_SEL;
891
892 /* CP0 register including 'sel' code for mtcN (et al.), to be
893 printed textually if known. If not known, print both
894 CP0 register name and sel numerically since CP0 register
895 with sel 0 may have a name unrelated to register being
896 printed. */
897 n = lookup_mips_cp0sel_name(mips_cp0sel_names,
898 mips_cp0sel_names_len, cp0reg, sel);
899 if (n != NULL)
900 (*info->fprintf_func) (info->stream, "%s", n->name);
901 else
902 (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel);
903 break;
904 }
905
906 case 'E':
907 lsb = ((l >> OP_SH_SHAMT) & OP_MASK_SHAMT) + 32;
908 (*info->fprintf_func) (info->stream, "0x%x", lsb);
909 break;
910
911 case 'F':
912 msb = ((l >> OP_SH_INSMSB) & OP_MASK_INSMSB) + 32;
913 (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1);
914 break;
915
916 case 'G':
917 msbd = ((l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD) + 32;
918 (*info->fprintf_func) (info->stream, "0x%x", msbd + 1);
919 break;
920
921 case 't': /* Coprocessor 0 reg name */
922 (*info->fprintf_func) (info->stream, "%s",
923 mips_cp0_names[(l >> OP_SH_RT) &
924 OP_MASK_RT]);
925 break;
926
927 case 'T': /* Coprocessor 0 reg name */
928 {
929 const struct mips_cp0sel_name *n;
930 unsigned int cp0reg, sel;
931
932 cp0reg = (l >> OP_SH_RT) & OP_MASK_RT;
933 sel = (l >> OP_SH_SEL) & OP_MASK_SEL;
934
935 /* CP0 register including 'sel' code for mftc0, to be
936 printed textually if known. If not known, print both
937 CP0 register name and sel numerically since CP0 register
938 with sel 0 may have a name unrelated to register being
939 printed. */
940 n = lookup_mips_cp0sel_name(mips_cp0sel_names,
941 mips_cp0sel_names_len, cp0reg, sel);
942 if (n != NULL)
943 (*info->fprintf_func) (info->stream, "%s", n->name);
944 else
945 (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel);
946 break;
947 }
948
949 case 'x': /* bbit bit index */
950 (*info->fprintf_func) (info->stream, "0x%lx",
951 (l >> OP_SH_BBITIND) & OP_MASK_BBITIND);
952 break;
953
954 case 'p': /* cins, cins32, exts and exts32 position */
955 (*info->fprintf_func) (info->stream, "0x%lx",
956 (l >> OP_SH_CINSPOS) & OP_MASK_CINSPOS);
957 break;
958
959 case 's': /* cins and exts length-minus-one */
960 (*info->fprintf_func) (info->stream, "0x%lx",
961 (l >> OP_SH_CINSLM1) & OP_MASK_CINSLM1);
962 break;
963
964 case 'S': /* cins32 and exts32 length-minus-one field */
965 (*info->fprintf_func) (info->stream, "0x%lx",
966 (l >> OP_SH_CINSLM1) & OP_MASK_CINSLM1);
967 break;
968
969 case 'Q': /* seqi/snei immediate field */
970 op = (l >> OP_SH_SEQI) & OP_MASK_SEQI;
971 /* Sign-extend it. */
972 op = (op ^ 512) - 512;
973 (*info->fprintf_func) (info->stream, "%d", op);
974 break;
975
976 case 'a': /* 8-bit signed offset in bit 6 */
977 delta = (l >> OP_SH_OFFSET_A) & OP_MASK_OFFSET_A;
978 if (delta & 0x80)
979 delta |= ~OP_MASK_OFFSET_A;
980 (*info->fprintf_func) (info->stream, "%d", delta);
981 break;
982
983 case 'b': /* 8-bit signed offset in bit 3 */
984 delta = (l >> OP_SH_OFFSET_B) & OP_MASK_OFFSET_B;
985 if (delta & 0x80)
986 delta |= ~OP_MASK_OFFSET_B;
987 (*info->fprintf_func) (info->stream, "%d", delta);
988 break;
989
990 case 'c': /* 9-bit signed offset in bit 6 */
991 delta = (l >> OP_SH_OFFSET_C) & OP_MASK_OFFSET_C;
992 if (delta & 0x100)
993 delta |= ~OP_MASK_OFFSET_C;
994 (*info->fprintf_func) (info->stream, "%d", delta);
995 break;
996
997 case 'z':
998 (*info->fprintf_func) (info->stream, "%s",
999 mips_gpr_names[(l >> OP_SH_RZ) & OP_MASK_RZ]);
1000 break;
1001
1002 case 'Z':
1003 (*info->fprintf_func) (info->stream, "%s",
1004 mips_fpr_names[(l >> OP_SH_FZ) & OP_MASK_FZ]);
1005 break;
1006
1007 default:
1008 /* xgettext:c-format */
1009 (*info->fprintf_func) (info->stream,
1010 _("# internal error, undefined extension sequence (+%c)"),
1011 *d);
1012 return;
1013 }
1014 break;
1015
1016 case '2':
1017 (*info->fprintf_func) (info->stream, "0x%lx",
1018 (l >> OP_SH_BP) & OP_MASK_BP);
1019 break;
1020
1021 case '3':
1022 (*info->fprintf_func) (info->stream, "0x%lx",
1023 (l >> OP_SH_SA3) & OP_MASK_SA3);
1024 break;
1025
1026 case '4':
1027 (*info->fprintf_func) (info->stream, "0x%lx",
1028 (l >> OP_SH_SA4) & OP_MASK_SA4);
1029 break;
1030
1031 case '5':
1032 (*info->fprintf_func) (info->stream, "0x%lx",
1033 (l >> OP_SH_IMM8) & OP_MASK_IMM8);
1034 break;
1035
1036 case '6':
1037 (*info->fprintf_func) (info->stream, "0x%lx",
1038 (l >> OP_SH_RS) & OP_MASK_RS);
1039 break;
1040
1041 case '7':
1042 (*info->fprintf_func) (info->stream, "$ac%ld",
1043 (l >> OP_SH_DSPACC) & OP_MASK_DSPACC);
1044 break;
1045
1046 case '8':
1047 (*info->fprintf_func) (info->stream, "0x%lx",
1048 (l >> OP_SH_WRDSP) & OP_MASK_WRDSP);
1049 break;
1050
1051 case '9':
1052 (*info->fprintf_func) (info->stream, "$ac%ld",
1053 (l >> OP_SH_DSPACC_S) & OP_MASK_DSPACC_S);
1054 break;
1055
1056 case '0': /* dsp 6-bit signed immediate in bit 20 */
1057 delta = ((l >> OP_SH_DSPSFT) & OP_MASK_DSPSFT);
1058 if (delta & 0x20) /* test sign bit */
1059 delta |= ~OP_MASK_DSPSFT;
1060 (*info->fprintf_func) (info->stream, "%d", delta);
1061 break;
1062
1063 case ':': /* dsp 7-bit signed immediate in bit 19 */
1064 delta = ((l >> OP_SH_DSPSFT_7) & OP_MASK_DSPSFT_7);
1065 if (delta & 0x40) /* test sign bit */
1066 delta |= ~OP_MASK_DSPSFT_7;
1067 (*info->fprintf_func) (info->stream, "%d", delta);
1068 break;
1069
1070 case '\'':
1071 (*info->fprintf_func) (info->stream, "0x%lx",
1072 (l >> OP_SH_RDDSP) & OP_MASK_RDDSP);
1073 break;
1074
1075 case '@': /* dsp 10-bit signed immediate in bit 16 */
1076 delta = ((l >> OP_SH_IMM10) & OP_MASK_IMM10);
1077 if (delta & 0x200) /* test sign bit */
1078 delta |= ~OP_MASK_IMM10;
1079 (*info->fprintf_func) (info->stream, "%d", delta);
1080 break;
1081
1082 case '!':
1083 (*info->fprintf_func) (info->stream, "%ld",
1084 (l >> OP_SH_MT_U) & OP_MASK_MT_U);
1085 break;
1086
1087 case '$':
1088 (*info->fprintf_func) (info->stream, "%ld",
1089 (l >> OP_SH_MT_H) & OP_MASK_MT_H);
1090 break;
1091
1092 case '*':
1093 (*info->fprintf_func) (info->stream, "$ac%ld",
1094 (l >> OP_SH_MTACC_T) & OP_MASK_MTACC_T);
1095 break;
1096
1097 case '&':
1098 (*info->fprintf_func) (info->stream, "$ac%ld",
1099 (l >> OP_SH_MTACC_D) & OP_MASK_MTACC_D);
1100 break;
1101
1102 case 'g':
1103 /* Coprocessor register for CTTC1, MTTC2, MTHC2, CTTC2. */
1104 (*info->fprintf_func) (info->stream, "$%ld",
1105 (l >> OP_SH_RD) & OP_MASK_RD);
1106 break;
1107
1108 case 's':
1109 case 'b':
1110 case 'r':
1111 case 'v':
1112 (*info->fprintf_func) (info->stream, "%s",
1113 mips_gpr_names[(l >> OP_SH_RS) & OP_MASK_RS]);
1114 break;
1115
1116 case 't':
1117 case 'w':
1118 (*info->fprintf_func) (info->stream, "%s",
1119 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
1120 break;
1121
1122 case 'i':
1123 case 'u':
1124 (*info->fprintf_func) (info->stream, "0x%lx",
1125 (l >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE);
1126 break;
1127
1128 case 'j': /* Same as i, but sign-extended. */
1129 case 'o':
1130 delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA;
1131 if (delta & 0x8000)
1132 delta |= ~0xffff;
1133 (*info->fprintf_func) (info->stream, "%d",
1134 delta);
1135 break;
1136
1137 case 'h':
1138 (*info->fprintf_func) (info->stream, "0x%x",
1139 (unsigned int) ((l >> OP_SH_PREFX)
1140 & OP_MASK_PREFX));
1141 break;
1142
1143 case 'k':
1144 (*info->fprintf_func) (info->stream, "0x%x",
1145 (unsigned int) ((l >> OP_SH_CACHE)
1146 & OP_MASK_CACHE));
1147 break;
1148
1149 case 'a':
1150 info->target = (((pc + 4) & ~(bfd_vma) 0x0fffffff)
1151 | (((l >> OP_SH_TARGET) & OP_MASK_TARGET) << 2));
1152 /* For gdb disassembler, force odd address on jalx. */
1153 if (info->flavour == bfd_target_unknown_flavour
1154 && strcmp (opp->name, "jalx") == 0)
1155 info->target |= 1;
1156 (*info->print_address_func) (info->target, info);
1157 break;
1158
1159 case 'p':
1160 /* Sign extend the displacement. */
1161 delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA;
1162 if (delta & 0x8000)
1163 delta |= ~0xffff;
1164 info->target = (delta << 2) + pc + INSNLEN;
1165 (*info->print_address_func) (info->target, info);
1166 break;
1167
1168 case 'd':
1169 (*info->fprintf_func) (info->stream, "%s",
1170 mips_gpr_names[(l >> OP_SH_RD) & OP_MASK_RD]);
1171 break;
1172
1173 case 'U':
1174 {
1175 /* First check for both rd and rt being equal. */
1176 unsigned int reg = (l >> OP_SH_RD) & OP_MASK_RD;
1177 if (reg == ((l >> OP_SH_RT) & OP_MASK_RT))
1178 (*info->fprintf_func) (info->stream, "%s",
1179 mips_gpr_names[reg]);
1180 else
1181 {
1182 /* If one is zero use the other. */
1183 if (reg == 0)
1184 (*info->fprintf_func) (info->stream, "%s",
1185 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
1186 else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0)
1187 (*info->fprintf_func) (info->stream, "%s",
1188 mips_gpr_names[reg]);
1189 else /* Bogus, result depends on processor. */
1190 (*info->fprintf_func) (info->stream, "%s or %s",
1191 mips_gpr_names[reg],
1192 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
1193 }
1194 }
1195 break;
1196
1197 case 'z':
1198 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]);
1199 break;
1200
1201 case '<':
1202 case '1':
1203 (*info->fprintf_func) (info->stream, "0x%lx",
1204 (l >> OP_SH_SHAMT) & OP_MASK_SHAMT);
1205 break;
1206
1207 case 'c':
1208 (*info->fprintf_func) (info->stream, "0x%lx",
1209 (l >> OP_SH_CODE) & OP_MASK_CODE);
1210 break;
1211
1212 case 'q':
1213 (*info->fprintf_func) (info->stream, "0x%lx",
1214 (l >> OP_SH_CODE2) & OP_MASK_CODE2);
1215 break;
1216
1217 case 'C':
1218 (*info->fprintf_func) (info->stream, "0x%lx",
1219 (l >> OP_SH_COPZ) & OP_MASK_COPZ);
1220 break;
1221
1222 case 'B':
1223 (*info->fprintf_func) (info->stream, "0x%lx",
1224
1225 (l >> OP_SH_CODE20) & OP_MASK_CODE20);
1226 break;
1227
1228 case 'J':
1229 (*info->fprintf_func) (info->stream, "0x%lx",
1230 (l >> OP_SH_CODE19) & OP_MASK_CODE19);
1231 break;
1232
1233 case 'S':
1234 case 'V':
1235 (*info->fprintf_func) (info->stream, "%s",
1236 mips_fpr_names[(l >> OP_SH_FS) & OP_MASK_FS]);
1237 break;
1238
1239 case 'T':
1240 case 'W':
1241 (*info->fprintf_func) (info->stream, "%s",
1242 mips_fpr_names[(l >> OP_SH_FT) & OP_MASK_FT]);
1243 break;
1244
1245 case 'D':
1246 (*info->fprintf_func) (info->stream, "%s",
1247 mips_fpr_names[(l >> OP_SH_FD) & OP_MASK_FD]);
1248 break;
1249
1250 case 'R':
1251 (*info->fprintf_func) (info->stream, "%s",
1252 mips_fpr_names[(l >> OP_SH_FR) & OP_MASK_FR]);
1253 break;
1254
1255 case 'E':
1256 /* Coprocessor register for lwcN instructions, et al.
1257
1258 Note that there is no load/store cp0 instructions, and
1259 that FPU (cp1) instructions disassemble this field using
1260 'T' format. Therefore, until we gain understanding of
1261 cp2 register names, we can simply print the register
1262 numbers. */
1263 (*info->fprintf_func) (info->stream, "$%ld",
1264 (l >> OP_SH_RT) & OP_MASK_RT);
1265 break;
1266
1267 case 'G':
1268 /* Coprocessor register for mtcN instructions, et al. Note
1269 that FPU (cp1) instructions disassemble this field using
1270 'S' format. Therefore, we only need to worry about cp0,
1271 cp2, and cp3. */
1272 op = (l >> OP_SH_OP) & OP_MASK_OP;
1273 if (op == OP_OP_COP0)
1274 (*info->fprintf_func) (info->stream, "%s",
1275 mips_cp0_names[(l >> OP_SH_RD) & OP_MASK_RD]);
1276 else
1277 (*info->fprintf_func) (info->stream, "$%ld",
1278 (l >> OP_SH_RD) & OP_MASK_RD);
1279 break;
1280
1281 case 'K':
1282 (*info->fprintf_func) (info->stream, "%s",
1283 mips_hwr_names[(l >> OP_SH_RD) & OP_MASK_RD]);
1284 break;
1285
1286 case 'N':
1287 (*info->fprintf_func) (info->stream,
1288 ((opp->pinfo & (FP_D | FP_S)) != 0
1289 ? "$fcc%ld" : "$cc%ld"),
1290 (l >> OP_SH_BCC) & OP_MASK_BCC);
1291 break;
1292
1293 case 'M':
1294 (*info->fprintf_func) (info->stream, "$fcc%ld",
1295 (l >> OP_SH_CCC) & OP_MASK_CCC);
1296 break;
1297
1298 case 'P':
1299 (*info->fprintf_func) (info->stream, "%ld",
1300 (l >> OP_SH_PERFREG) & OP_MASK_PERFREG);
1301 break;
1302
1303 case 'e':
1304 (*info->fprintf_func) (info->stream, "%ld",
1305 (l >> OP_SH_VECBYTE) & OP_MASK_VECBYTE);
1306 break;
1307
1308 case '%':
1309 (*info->fprintf_func) (info->stream, "%ld",
1310 (l >> OP_SH_VECALIGN) & OP_MASK_VECALIGN);
1311 break;
1312
1313 case 'H':
1314 (*info->fprintf_func) (info->stream, "%ld",
1315 (l >> OP_SH_SEL) & OP_MASK_SEL);
1316 break;
1317
1318 case 'O':
1319 (*info->fprintf_func) (info->stream, "%ld",
1320 (l >> OP_SH_ALN) & OP_MASK_ALN);
1321 break;
1322
1323 case 'Q':
1324 {
1325 unsigned int vsel = (l >> OP_SH_VSEL) & OP_MASK_VSEL;
1326
1327 if ((vsel & 0x10) == 0)
1328 {
1329 int fmt;
1330
1331 vsel &= 0x0f;
1332 for (fmt = 0; fmt < 3; fmt++, vsel >>= 1)
1333 if ((vsel & 1) == 0)
1334 break;
1335 (*info->fprintf_func) (info->stream, "$v%ld[%d]",
1336 (l >> OP_SH_FT) & OP_MASK_FT,
1337 vsel >> 1);
1338 }
1339 else if ((vsel & 0x08) == 0)
1340 {
1341 (*info->fprintf_func) (info->stream, "$v%ld",
1342 (l >> OP_SH_FT) & OP_MASK_FT);
1343 }
1344 else
1345 {
1346 (*info->fprintf_func) (info->stream, "0x%lx",
1347 (l >> OP_SH_FT) & OP_MASK_FT);
1348 }
1349 }
1350 break;
1351
1352 case 'X':
1353 (*info->fprintf_func) (info->stream, "$v%ld",
1354 (l >> OP_SH_FD) & OP_MASK_FD);
1355 break;
1356
1357 case 'Y':
1358 (*info->fprintf_func) (info->stream, "$v%ld",
1359 (l >> OP_SH_FS) & OP_MASK_FS);
1360 break;
1361
1362 case 'Z':
1363 (*info->fprintf_func) (info->stream, "$v%ld",
1364 (l >> OP_SH_FT) & OP_MASK_FT);
1365 break;
1366
1367 default:
1368 /* xgettext:c-format */
1369 (*info->fprintf_func) (info->stream,
1370 _("# internal error, undefined modifier (%c)"),
1371 *d);
1372 return;
1373 }
1374 }
1375 }
1376 \f
1377 /* Print the mips instruction at address MEMADDR in debugged memory,
1378 on using INFO. Returns length of the instruction, in bytes, which is
1379 always INSNLEN. BIGENDIAN must be 1 if this is big-endian code, 0 if
1380 this is little-endian code. */
1381
1382 static int
1383 print_insn_mips (bfd_vma memaddr,
1384 unsigned long int word,
1385 struct disassemble_info *info)
1386 {
1387 const struct mips_opcode *op;
1388 static bfd_boolean init = 0;
1389 static const struct mips_opcode *mips_hash[OP_MASK_OP + 1];
1390
1391 /* Build a hash table to shorten the search time. */
1392 if (! init)
1393 {
1394 unsigned int i;
1395
1396 for (i = 0; i <= OP_MASK_OP; i++)
1397 {
1398 for (op = mips_opcodes; op < &mips_opcodes[NUMOPCODES]; op++)
1399 {
1400 if (op->pinfo == INSN_MACRO
1401 || (no_aliases && (op->pinfo2 & INSN2_ALIAS)))
1402 continue;
1403 if (i == ((op->match >> OP_SH_OP) & OP_MASK_OP))
1404 {
1405 mips_hash[i] = op;
1406 break;
1407 }
1408 }
1409 }
1410
1411 init = 1;
1412 }
1413
1414 info->bytes_per_chunk = INSNLEN;
1415 info->display_endian = info->endian;
1416 info->insn_info_valid = 1;
1417 info->branch_delay_insns = 0;
1418 info->data_size = 0;
1419 info->insn_type = dis_nonbranch;
1420 info->target = 0;
1421 info->target2 = 0;
1422
1423 op = mips_hash[(word >> OP_SH_OP) & OP_MASK_OP];
1424 if (op != NULL)
1425 {
1426 for (; op < &mips_opcodes[NUMOPCODES]; op++)
1427 {
1428 if (op->pinfo != INSN_MACRO
1429 && !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
1430 && (word & op->mask) == op->match)
1431 {
1432 const char *d;
1433
1434 /* We always allow to disassemble the jalx instruction. */
1435 if (! OPCODE_IS_MEMBER (op, mips_isa, mips_processor)
1436 && strcmp (op->name, "jalx"))
1437 continue;
1438
1439 /* Figure out instruction type and branch delay information. */
1440 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
1441 {
1442 if ((op->pinfo & (INSN_WRITE_GPR_31
1443 | INSN_WRITE_GPR_D)) != 0)
1444 info->insn_type = dis_jsr;
1445 else
1446 info->insn_type = dis_branch;
1447 info->branch_delay_insns = 1;
1448 }
1449 else if ((op->pinfo & (INSN_COND_BRANCH_DELAY
1450 | INSN_COND_BRANCH_LIKELY)) != 0)
1451 {
1452 if ((op->pinfo & INSN_WRITE_GPR_31) != 0)
1453 info->insn_type = dis_condjsr;
1454 else
1455 info->insn_type = dis_condbranch;
1456 info->branch_delay_insns = 1;
1457 }
1458 else if ((op->pinfo & (INSN_STORE_MEMORY
1459 | INSN_LOAD_MEMORY_DELAY)) != 0)
1460 info->insn_type = dis_dref;
1461
1462 (*info->fprintf_func) (info->stream, "%s", op->name);
1463
1464 d = op->args;
1465 if (d != NULL && *d != '\0')
1466 {
1467 (*info->fprintf_func) (info->stream, "\t");
1468 print_insn_args (d, word, memaddr, info, op);
1469 }
1470
1471 return INSNLEN;
1472 }
1473 }
1474 }
1475
1476 /* Handle undefined instructions. */
1477 info->insn_type = dis_noninsn;
1478 (*info->fprintf_func) (info->stream, "0x%lx", word);
1479 return INSNLEN;
1480 }
1481 \f
1482 /* Disassemble an operand for a mips16 instruction. */
1483
1484 static void
1485 print_mips16_insn_arg (char type,
1486 const struct mips_opcode *op,
1487 int l,
1488 bfd_boolean use_extend,
1489 int extend,
1490 bfd_vma memaddr,
1491 struct disassemble_info *info)
1492 {
1493 switch (type)
1494 {
1495 case ',':
1496 case '(':
1497 case ')':
1498 (*info->fprintf_func) (info->stream, "%c", type);
1499 break;
1500
1501 case 'y':
1502 case 'w':
1503 (*info->fprintf_func) (info->stream, "%s",
1504 mips16_reg_names(((l >> MIPS16OP_SH_RY)
1505 & MIPS16OP_MASK_RY)));
1506 break;
1507
1508 case 'x':
1509 case 'v':
1510 (*info->fprintf_func) (info->stream, "%s",
1511 mips16_reg_names(((l >> MIPS16OP_SH_RX)
1512 & MIPS16OP_MASK_RX)));
1513 break;
1514
1515 case 'z':
1516 (*info->fprintf_func) (info->stream, "%s",
1517 mips16_reg_names(((l >> MIPS16OP_SH_RZ)
1518 & MIPS16OP_MASK_RZ)));
1519 break;
1520
1521 case 'Z':
1522 (*info->fprintf_func) (info->stream, "%s",
1523 mips16_reg_names(((l >> MIPS16OP_SH_MOVE32Z)
1524 & MIPS16OP_MASK_MOVE32Z)));
1525 break;
1526
1527 case '0':
1528 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]);
1529 break;
1530
1531 case 'S':
1532 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[29]);
1533 break;
1534
1535 case 'P':
1536 (*info->fprintf_func) (info->stream, "$pc");
1537 break;
1538
1539 case 'R':
1540 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[31]);
1541 break;
1542
1543 case 'X':
1544 (*info->fprintf_func) (info->stream, "%s",
1545 mips_gpr_names[((l >> MIPS16OP_SH_REGR32)
1546 & MIPS16OP_MASK_REGR32)]);
1547 break;
1548
1549 case 'Y':
1550 (*info->fprintf_func) (info->stream, "%s",
1551 mips_gpr_names[MIPS16OP_EXTRACT_REG32R (l)]);
1552 break;
1553
1554 case '<':
1555 case '>':
1556 case '[':
1557 case ']':
1558 case '4':
1559 case '5':
1560 case 'H':
1561 case 'W':
1562 case 'D':
1563 case 'j':
1564 case '6':
1565 case '8':
1566 case 'V':
1567 case 'C':
1568 case 'U':
1569 case 'k':
1570 case 'K':
1571 case 'p':
1572 case 'q':
1573 case 'A':
1574 case 'B':
1575 case 'E':
1576 {
1577 int immed, nbits, shift, signedp, extbits, pcrel, extu, branch;
1578
1579 shift = 0;
1580 signedp = 0;
1581 extbits = 16;
1582 pcrel = 0;
1583 extu = 0;
1584 branch = 0;
1585 switch (type)
1586 {
1587 case '<':
1588 nbits = 3;
1589 immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
1590 extbits = 5;
1591 extu = 1;
1592 break;
1593 case '>':
1594 nbits = 3;
1595 immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
1596 extbits = 5;
1597 extu = 1;
1598 break;
1599 case '[':
1600 nbits = 3;
1601 immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
1602 extbits = 6;
1603 extu = 1;
1604 break;
1605 case ']':
1606 nbits = 3;
1607 immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
1608 extbits = 6;
1609 extu = 1;
1610 break;
1611 case '4':
1612 nbits = 4;
1613 immed = (l >> MIPS16OP_SH_IMM4) & MIPS16OP_MASK_IMM4;
1614 signedp = 1;
1615 extbits = 15;
1616 break;
1617 case '5':
1618 nbits = 5;
1619 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1620 info->insn_type = dis_dref;
1621 info->data_size = 1;
1622 break;
1623 case 'H':
1624 nbits = 5;
1625 shift = 1;
1626 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1627 info->insn_type = dis_dref;
1628 info->data_size = 2;
1629 break;
1630 case 'W':
1631 nbits = 5;
1632 shift = 2;
1633 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1634 if ((op->pinfo & MIPS16_INSN_READ_PC) == 0
1635 && (op->pinfo & MIPS16_INSN_READ_SP) == 0)
1636 {
1637 info->insn_type = dis_dref;
1638 info->data_size = 4;
1639 }
1640 break;
1641 case 'D':
1642 nbits = 5;
1643 shift = 3;
1644 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1645 info->insn_type = dis_dref;
1646 info->data_size = 8;
1647 break;
1648 case 'j':
1649 nbits = 5;
1650 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1651 signedp = 1;
1652 break;
1653 case '6':
1654 nbits = 6;
1655 immed = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6;
1656 break;
1657 case '8':
1658 nbits = 8;
1659 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1660 break;
1661 case 'V':
1662 nbits = 8;
1663 shift = 2;
1664 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1665 /* FIXME: This might be lw, or it might be addiu to $sp or
1666 $pc. We assume it's load. */
1667 info->insn_type = dis_dref;
1668 info->data_size = 4;
1669 break;
1670 case 'C':
1671 nbits = 8;
1672 shift = 3;
1673 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1674 info->insn_type = dis_dref;
1675 info->data_size = 8;
1676 break;
1677 case 'U':
1678 nbits = 8;
1679 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1680 extu = 1;
1681 break;
1682 case 'k':
1683 nbits = 8;
1684 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1685 signedp = 1;
1686 break;
1687 case 'K':
1688 nbits = 8;
1689 shift = 3;
1690 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1691 signedp = 1;
1692 break;
1693 case 'p':
1694 nbits = 8;
1695 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1696 signedp = 1;
1697 pcrel = 1;
1698 branch = 1;
1699 break;
1700 case 'q':
1701 nbits = 11;
1702 immed = (l >> MIPS16OP_SH_IMM11) & MIPS16OP_MASK_IMM11;
1703 signedp = 1;
1704 pcrel = 1;
1705 branch = 1;
1706 break;
1707 case 'A':
1708 nbits = 8;
1709 shift = 2;
1710 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1711 pcrel = 1;
1712 /* FIXME: This can be lw or la. We assume it is lw. */
1713 info->insn_type = dis_dref;
1714 info->data_size = 4;
1715 break;
1716 case 'B':
1717 nbits = 5;
1718 shift = 3;
1719 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1720 pcrel = 1;
1721 info->insn_type = dis_dref;
1722 info->data_size = 8;
1723 break;
1724 case 'E':
1725 nbits = 5;
1726 shift = 2;
1727 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1728 pcrel = 1;
1729 break;
1730 default:
1731 abort ();
1732 }
1733
1734 if (! use_extend)
1735 {
1736 if (signedp && immed >= (1 << (nbits - 1)))
1737 immed -= 1 << nbits;
1738 immed <<= shift;
1739 if ((type == '<' || type == '>' || type == '[' || type == ']')
1740 && immed == 0)
1741 immed = 8;
1742 }
1743 else
1744 {
1745 if (extbits == 16)
1746 immed |= ((extend & 0x1f) << 11) | (extend & 0x7e0);
1747 else if (extbits == 15)
1748 immed |= ((extend & 0xf) << 11) | (extend & 0x7f0);
1749 else
1750 immed = ((extend >> 6) & 0x1f) | (extend & 0x20);
1751 immed &= (1 << extbits) - 1;
1752 if (! extu && immed >= (1 << (extbits - 1)))
1753 immed -= 1 << extbits;
1754 }
1755
1756 if (! pcrel)
1757 (*info->fprintf_func) (info->stream, "%d", immed);
1758 else
1759 {
1760 bfd_vma baseaddr;
1761
1762 if (branch)
1763 {
1764 immed *= 2;
1765 baseaddr = memaddr + 2;
1766 }
1767 else if (use_extend)
1768 baseaddr = memaddr - 2;
1769 else
1770 {
1771 int status;
1772 bfd_byte buffer[2];
1773
1774 baseaddr = memaddr;
1775
1776 /* If this instruction is in the delay slot of a jr
1777 instruction, the base address is the address of the
1778 jr instruction. If it is in the delay slot of jalr
1779 instruction, the base address is the address of the
1780 jalr instruction. This test is unreliable: we have
1781 no way of knowing whether the previous word is
1782 instruction or data. */
1783 status = (*info->read_memory_func) (memaddr - 4, buffer, 2,
1784 info);
1785 if (status == 0
1786 && (((info->endian == BFD_ENDIAN_BIG
1787 ? bfd_getb16 (buffer)
1788 : bfd_getl16 (buffer))
1789 & 0xf800) == 0x1800))
1790 baseaddr = memaddr - 4;
1791 else
1792 {
1793 status = (*info->read_memory_func) (memaddr - 2, buffer,
1794 2, info);
1795 if (status == 0
1796 && (((info->endian == BFD_ENDIAN_BIG
1797 ? bfd_getb16 (buffer)
1798 : bfd_getl16 (buffer))
1799 & 0xf81f) == 0xe800))
1800 baseaddr = memaddr - 2;
1801 }
1802 }
1803 info->target = (baseaddr & ~((1 << shift) - 1)) + immed;
1804 if (pcrel && branch
1805 && info->flavour == bfd_target_unknown_flavour)
1806 /* For gdb disassembler, maintain odd address. */
1807 info->target |= 1;
1808 (*info->print_address_func) (info->target, info);
1809 }
1810 }
1811 break;
1812
1813 case 'a':
1814 {
1815 int jalx = l & 0x400;
1816
1817 if (! use_extend)
1818 extend = 0;
1819 l = ((l & 0x1f) << 23) | ((l & 0x3e0) << 13) | (extend << 2);
1820 if (!jalx && info->flavour == bfd_target_unknown_flavour)
1821 /* For gdb disassembler, maintain odd address. */
1822 l |= 1;
1823 }
1824 info->target = ((memaddr + 4) & ~(bfd_vma) 0x0fffffff) | l;
1825 (*info->print_address_func) (info->target, info);
1826 break;
1827
1828 case 'l':
1829 case 'L':
1830 {
1831 int need_comma, amask, smask;
1832
1833 need_comma = 0;
1834
1835 l = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6;
1836
1837 amask = (l >> 3) & 7;
1838
1839 if (amask > 0 && amask < 5)
1840 {
1841 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]);
1842 if (amask > 1)
1843 (*info->fprintf_func) (info->stream, "-%s",
1844 mips_gpr_names[amask + 3]);
1845 need_comma = 1;
1846 }
1847
1848 smask = (l >> 1) & 3;
1849 if (smask == 3)
1850 {
1851 (*info->fprintf_func) (info->stream, "%s??",
1852 need_comma ? "," : "");
1853 need_comma = 1;
1854 }
1855 else if (smask > 0)
1856 {
1857 (*info->fprintf_func) (info->stream, "%s%s",
1858 need_comma ? "," : "",
1859 mips_gpr_names[16]);
1860 if (smask > 1)
1861 (*info->fprintf_func) (info->stream, "-%s",
1862 mips_gpr_names[smask + 15]);
1863 need_comma = 1;
1864 }
1865
1866 if (l & 1)
1867 {
1868 (*info->fprintf_func) (info->stream, "%s%s",
1869 need_comma ? "," : "",
1870 mips_gpr_names[31]);
1871 need_comma = 1;
1872 }
1873
1874 if (amask == 5 || amask == 6)
1875 {
1876 (*info->fprintf_func) (info->stream, "%s$f0",
1877 need_comma ? "," : "");
1878 if (amask == 6)
1879 (*info->fprintf_func) (info->stream, "-$f1");
1880 }
1881 }
1882 break;
1883
1884 case 'm':
1885 case 'M':
1886 /* MIPS16e save/restore. */
1887 {
1888 int need_comma = 0;
1889 int amask, args, statics;
1890 int nsreg, smask;
1891 int framesz;
1892 int i, j;
1893
1894 l = l & 0x7f;
1895 if (use_extend)
1896 l |= extend << 16;
1897
1898 amask = (l >> 16) & 0xf;
1899 if (amask == MIPS16_ALL_ARGS)
1900 {
1901 args = 4;
1902 statics = 0;
1903 }
1904 else if (amask == MIPS16_ALL_STATICS)
1905 {
1906 args = 0;
1907 statics = 4;
1908 }
1909 else
1910 {
1911 args = amask >> 2;
1912 statics = amask & 3;
1913 }
1914
1915 if (args > 0) {
1916 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]);
1917 if (args > 1)
1918 (*info->fprintf_func) (info->stream, "-%s",
1919 mips_gpr_names[4 + args - 1]);
1920 need_comma = 1;
1921 }
1922
1923 framesz = (((l >> 16) & 0xf0) | (l & 0x0f)) * 8;
1924 if (framesz == 0 && !use_extend)
1925 framesz = 128;
1926
1927 (*info->fprintf_func) (info->stream, "%s%d",
1928 need_comma ? "," : "",
1929 framesz);
1930
1931 if (l & 0x40) /* $ra */
1932 (*info->fprintf_func) (info->stream, ",%s", mips_gpr_names[31]);
1933
1934 nsreg = (l >> 24) & 0x7;
1935 smask = 0;
1936 if (l & 0x20) /* $s0 */
1937 smask |= 1 << 0;
1938 if (l & 0x10) /* $s1 */
1939 smask |= 1 << 1;
1940 if (nsreg > 0) /* $s2-$s8 */
1941 smask |= ((1 << nsreg) - 1) << 2;
1942
1943 /* Find first set static reg bit. */
1944 for (i = 0; i < 9; i++)
1945 {
1946 if (smask & (1 << i))
1947 {
1948 (*info->fprintf_func) (info->stream, ",%s",
1949 mips_gpr_names[i == 8 ? 30 : (16 + i)]);
1950 /* Skip over string of set bits. */
1951 for (j = i; smask & (2 << j); j++)
1952 continue;
1953 if (j > i)
1954 (*info->fprintf_func) (info->stream, "-%s",
1955 mips_gpr_names[j == 8 ? 30 : (16 + j)]);
1956 i = j + 1;
1957 }
1958 }
1959
1960 /* Statics $ax - $a3. */
1961 if (statics == 1)
1962 (*info->fprintf_func) (info->stream, ",%s", mips_gpr_names[7]);
1963 else if (statics > 0)
1964 (*info->fprintf_func) (info->stream, ",%s-%s",
1965 mips_gpr_names[7 - statics + 1],
1966 mips_gpr_names[7]);
1967 }
1968 break;
1969
1970 default:
1971 /* xgettext:c-format */
1972 (*info->fprintf_func)
1973 (info->stream,
1974 _("# internal disassembler error, unrecognised modifier (%c)"),
1975 type);
1976 abort ();
1977 }
1978 }
1979
1980 /* Disassemble mips16 instructions. */
1981
1982 static int
1983 print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info)
1984 {
1985 int status;
1986 bfd_byte buffer[2];
1987 int length;
1988 int insn;
1989 bfd_boolean use_extend;
1990 int extend = 0;
1991 const struct mips_opcode *op, *opend;
1992
1993 info->bytes_per_chunk = 2;
1994 info->display_endian = info->endian;
1995 info->insn_info_valid = 1;
1996 info->branch_delay_insns = 0;
1997 info->data_size = 0;
1998 info->insn_type = dis_nonbranch;
1999 info->target = 0;
2000 info->target2 = 0;
2001
2002 status = (*info->read_memory_func) (memaddr, buffer, 2, info);
2003 if (status != 0)
2004 {
2005 (*info->memory_error_func) (status, memaddr, info);
2006 return -1;
2007 }
2008
2009 length = 2;
2010
2011 if (info->endian == BFD_ENDIAN_BIG)
2012 insn = bfd_getb16 (buffer);
2013 else
2014 insn = bfd_getl16 (buffer);
2015
2016 /* Handle the extend opcode specially. */
2017 use_extend = FALSE;
2018 if ((insn & 0xf800) == 0xf000)
2019 {
2020 use_extend = TRUE;
2021 extend = insn & 0x7ff;
2022
2023 memaddr += 2;
2024
2025 status = (*info->read_memory_func) (memaddr, buffer, 2, info);
2026 if (status != 0)
2027 {
2028 (*info->fprintf_func) (info->stream, "extend 0x%x",
2029 (unsigned int) extend);
2030 (*info->memory_error_func) (status, memaddr, info);
2031 return -1;
2032 }
2033
2034 if (info->endian == BFD_ENDIAN_BIG)
2035 insn = bfd_getb16 (buffer);
2036 else
2037 insn = bfd_getl16 (buffer);
2038
2039 /* Check for an extend opcode followed by an extend opcode. */
2040 if ((insn & 0xf800) == 0xf000)
2041 {
2042 (*info->fprintf_func) (info->stream, "extend 0x%x",
2043 (unsigned int) extend);
2044 info->insn_type = dis_noninsn;
2045 return length;
2046 }
2047
2048 length += 2;
2049 }
2050
2051 /* FIXME: Should probably use a hash table on the major opcode here. */
2052
2053 opend = mips16_opcodes + bfd_mips16_num_opcodes;
2054 for (op = mips16_opcodes; op < opend; op++)
2055 {
2056 if (op->pinfo != INSN_MACRO
2057 && !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
2058 && (insn & op->mask) == op->match)
2059 {
2060 const char *s;
2061
2062 if (strchr (op->args, 'a') != NULL)
2063 {
2064 if (use_extend)
2065 {
2066 (*info->fprintf_func) (info->stream, "extend 0x%x",
2067 (unsigned int) extend);
2068 info->insn_type = dis_noninsn;
2069 return length - 2;
2070 }
2071
2072 use_extend = FALSE;
2073
2074 memaddr += 2;
2075
2076 status = (*info->read_memory_func) (memaddr, buffer, 2,
2077 info);
2078 if (status == 0)
2079 {
2080 use_extend = TRUE;
2081 if (info->endian == BFD_ENDIAN_BIG)
2082 extend = bfd_getb16 (buffer);
2083 else
2084 extend = bfd_getl16 (buffer);
2085 length += 2;
2086 }
2087 }
2088
2089 (*info->fprintf_func) (info->stream, "%s", op->name);
2090 if (op->args[0] != '\0')
2091 (*info->fprintf_func) (info->stream, "\t");
2092
2093 for (s = op->args; *s != '\0'; s++)
2094 {
2095 if (*s == ','
2096 && s[1] == 'w'
2097 && (((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX)
2098 == ((insn >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY)))
2099 {
2100 /* Skip the register and the comma. */
2101 ++s;
2102 continue;
2103 }
2104 if (*s == ','
2105 && s[1] == 'v'
2106 && (((insn >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ)
2107 == ((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX)))
2108 {
2109 /* Skip the register and the comma. */
2110 ++s;
2111 continue;
2112 }
2113 print_mips16_insn_arg (*s, op, insn, use_extend, extend, memaddr,
2114 info);
2115 }
2116
2117 /* Figure out branch instruction type and delay slot information. */
2118 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
2119 info->branch_delay_insns = 1;
2120 if ((op->pinfo & (INSN_UNCOND_BRANCH_DELAY
2121 | MIPS16_INSN_UNCOND_BRANCH)) != 0)
2122 {
2123 if ((op->pinfo & INSN_WRITE_GPR_31) != 0)
2124 info->insn_type = dis_jsr;
2125 else
2126 info->insn_type = dis_branch;
2127 }
2128 else if ((op->pinfo & MIPS16_INSN_COND_BRANCH) != 0)
2129 info->insn_type = dis_condbranch;
2130
2131 return length;
2132 }
2133 }
2134
2135 if (use_extend)
2136 (*info->fprintf_func) (info->stream, "0x%x", extend | 0xf000);
2137 (*info->fprintf_func) (info->stream, "0x%x", insn);
2138 info->insn_type = dis_noninsn;
2139
2140 return length;
2141 }
2142
2143 /* In an environment where we do not know the symbol type of the
2144 instruction we are forced to assume that the low order bit of the
2145 instructions' address may mark it as a mips16 instruction. If we
2146 are single stepping, or the pc is within the disassembled function,
2147 this works. Otherwise, we need a clue. Sometimes. */
2148
2149 static int
2150 _print_insn_mips (bfd_vma memaddr,
2151 struct disassemble_info *info,
2152 enum bfd_endian endianness)
2153 {
2154 bfd_byte buffer[INSNLEN];
2155 int status;
2156
2157 set_default_mips_dis_options (info);
2158 parse_mips_dis_options (info->disassembler_options);
2159
2160 #if 1
2161 /* FIXME: If odd address, this is CLEARLY a mips 16 instruction. */
2162 /* Only a few tools will work this way. */
2163 if (memaddr & 0x01)
2164 return print_insn_mips16 (memaddr, info);
2165 #endif
2166
2167 #if SYMTAB_AVAILABLE
2168 if (info->mach == bfd_mach_mips16
2169 || (info->symbols != NULL
2170 && bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour
2171 && ELF_ST_IS_MIPS16 ((*(elf_symbol_type **) info->symbols)
2172 ->internal_elf_sym.st_other)))
2173 return print_insn_mips16 (memaddr, info);
2174 #endif
2175
2176 status = (*info->read_memory_func) (memaddr, buffer, INSNLEN, info);
2177 if (status == 0)
2178 {
2179 unsigned long insn;
2180
2181 if (endianness == BFD_ENDIAN_BIG)
2182 insn = (unsigned long) bfd_getb32 (buffer);
2183 else
2184 insn = (unsigned long) bfd_getl32 (buffer);
2185
2186 return print_insn_mips (memaddr, insn, info);
2187 }
2188 else
2189 {
2190 (*info->memory_error_func) (status, memaddr, info);
2191 return -1;
2192 }
2193 }
2194
2195 int
2196 print_insn_big_mips (bfd_vma memaddr, struct disassemble_info *info)
2197 {
2198 return _print_insn_mips (memaddr, info, BFD_ENDIAN_BIG);
2199 }
2200
2201 int
2202 print_insn_little_mips (bfd_vma memaddr, struct disassemble_info *info)
2203 {
2204 return _print_insn_mips (memaddr, info, BFD_ENDIAN_LITTLE);
2205 }
2206 \f
2207 void
2208 print_mips_disassembler_options (FILE *stream)
2209 {
2210 unsigned int i;
2211
2212 fprintf (stream, _("\n\
2213 The following MIPS specific disassembler options are supported for use\n\
2214 with the -M switch (multiple options should be separated by commas):\n"));
2215
2216 fprintf (stream, _("\n\
2217 gpr-names=ABI Print GPR names according to specified ABI.\n\
2218 Default: based on binary being disassembled.\n"));
2219
2220 fprintf (stream, _("\n\
2221 fpr-names=ABI Print FPR names according to specified ABI.\n\
2222 Default: numeric.\n"));
2223
2224 fprintf (stream, _("\n\
2225 cp0-names=ARCH Print CP0 register names according to\n\
2226 specified architecture.\n\
2227 Default: based on binary being disassembled.\n"));
2228
2229 fprintf (stream, _("\n\
2230 hwr-names=ARCH Print HWR names according to specified \n\
2231 architecture.\n\
2232 Default: based on binary being disassembled.\n"));
2233
2234 fprintf (stream, _("\n\
2235 reg-names=ABI Print GPR and FPR names according to\n\
2236 specified ABI.\n"));
2237
2238 fprintf (stream, _("\n\
2239 reg-names=ARCH Print CP0 register and HWR names according to\n\
2240 specified architecture.\n"));
2241
2242 fprintf (stream, _("\n\
2243 For the options above, the following values are supported for \"ABI\":\n\
2244 "));
2245 for (i = 0; i < ARRAY_SIZE (mips_abi_choices); i++)
2246 fprintf (stream, " %s", mips_abi_choices[i].name);
2247 fprintf (stream, _("\n"));
2248
2249 fprintf (stream, _("\n\
2250 For the options above, The following values are supported for \"ARCH\":\n\
2251 "));
2252 for (i = 0; i < ARRAY_SIZE (mips_arch_choices); i++)
2253 if (*mips_arch_choices[i].name != '\0')
2254 fprintf (stream, " %s", mips_arch_choices[i].name);
2255 fprintf (stream, _("\n"));
2256
2257 fprintf (stream, _("\n"));
2258 }
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