opcodes/cris-opc.c

   1 /* cris-opc.c -- Table of opcodes for the CRIS processor.
   2    Copyright 2000, 2001, 2004 Free Software Foundation, Inc.
   3    Contributed by Axis Communications AB, Lund, Sweden.
   4    Originally written for GAS 1.38.1 by Mikael Asker.
   5    Reorganized by Hans-Peter Nilsson.
   6
   7 This file is part of GAS, GDB and the GNU binutils.
   8
   9 GAS, GDB, and GNU binutils is free software; you can redistribute it
  10 and/or modify it under the terms of the GNU General Public License as
  11 published by the Free Software Foundation; either version 2, or (at your
  12 option) any later version.
  13
  14 GAS, GDB, and GNU binutils are distributed in the hope that they will be
  15 useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 GNU General Public License for more details.
  18
  19 You should have received a copy of the GNU General Public License
  20 along with this program; if not, write to the Free Software
  21 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  22
  23 #include "opcode/cris.h"
  24
  25 #ifndef NULL
  26 #define NULL (0)
  27 #endif
  28
  29 /* This table isn't used for CRISv32 and the size of immediate operands.  */
  30 const struct cris_spec_reg
  31 cris_spec_regs[] =
  32 {
  33   {"bz",  0,  1, cris_ver_v32p,    NULL},
  34   {"p0",  0,  1, 0,                NULL},
  35   {"vr",  1,  1, 0,                NULL},
  36   {"p1",  1,  1, 0,                NULL},
  37   {"pid", 2,  1, cris_ver_v32p,    NULL},
  38   {"p2",  2,  1, cris_ver_v32p,    NULL},
  39   {"p2",  2,  1, cris_ver_warning, NULL},
  40   {"srs", 3,  1, cris_ver_v32p,    NULL},
  41   {"p3",  3,  1, cris_ver_v32p,    NULL},
  42   {"p3",  3,  1, cris_ver_warning, NULL},
  43   {"wz",  4,  2, cris_ver_v32p,    NULL},
  44   {"p4",  4,  2, 0,                NULL},
  45   {"ccr", 5,  2, cris_ver_v0_10,   NULL},
  46   {"exs", 5,  4, cris_ver_v32p,    NULL},
  47   {"p5",  5,  2, cris_ver_v0_10,   NULL},
  48   {"p5",  5,  4, cris_ver_v32p,    NULL},
  49   {"dcr0",6,  2, cris_ver_v0_3,    NULL},
  50   {"eda", 6,  4, cris_ver_v32p,    NULL},
  51   {"p6",  6,  2, cris_ver_v0_3,    NULL},
  52   {"p6",  6,  4, cris_ver_v32p,    NULL},
  53   {"dcr1/mof", 7, 4, cris_ver_v10p,
  54    "Register `dcr1/mof' with ambiguous size specified.  Guessing 4 bytes"},
  55   {"dcr1/mof", 7, 2, cris_ver_v0_3,
  56    "Register `dcr1/mof' with ambiguous size specified.  Guessing 2 bytes"},
  57   {"mof", 7,  4, cris_ver_v10p,    NULL},
  58   {"dcr1",7,  2, cris_ver_v0_3,    NULL},
  59   {"p7",  7,  4, cris_ver_v10p,    NULL},
  60   {"p7",  7,  2, cris_ver_v0_3,    NULL},
  61   {"dz",  8,  4, cris_ver_v32p,    NULL},
  62   {"p8",  8,  4, 0,                NULL},
  63   {"ibr", 9,  4, cris_ver_v0_10,   NULL},
  64   {"ebp", 9,  4, cris_ver_v32p,    NULL},
  65   {"p9",  9,  4, 0,                NULL},
  66   {"irp", 10, 4, cris_ver_v0_10,   NULL},
  67   {"erp", 10, 4, cris_ver_v32p,    NULL},
  68   {"p10", 10, 4, 0,                NULL},
  69   {"srp", 11, 4, 0,                NULL},
  70   {"p11", 11, 4, 0,                NULL},
  71   /* For disassembly use only.  Accept at assembly with a warning.  */
  72   {"bar/dtp0", 12, 4, cris_ver_warning,
  73    "Ambiguous register `bar/dtp0' specified"},
  74   {"nrp", 12, 4, cris_ver_v32p,    NULL},
  75   {"bar", 12, 4, cris_ver_v8_10,   NULL},
  76   {"dtp0",12, 4, cris_ver_v0_3,    NULL},
  77   {"p12", 12, 4, 0,                NULL},
  78   /* For disassembly use only.  Accept at assembly with a warning.  */
  79   {"dccr/dtp1",13, 4, cris_ver_warning,
  80    "Ambiguous register `dccr/dtp1' specified"},
  81   {"ccs", 13, 4, cris_ver_v32p,    NULL},
  82   {"dccr",13, 4, cris_ver_v8_10,   NULL},
  83   {"dtp1",13, 4, cris_ver_v0_3,    NULL},
  84   {"p13", 13, 4, 0,                NULL},
  85   {"brp", 14, 4, cris_ver_v3_10,   NULL},
  86   {"usp", 14, 4, cris_ver_v32p,    NULL},
  87   {"p14", 14, 4, cris_ver_v3p,     NULL},
  88   {"usp", 15, 4, cris_ver_v10,     NULL},
  89   {"spc", 15, 4, cris_ver_v32p,    NULL},
  90   {"p15", 15, 4, cris_ver_v10p,    NULL},
  91   {NULL, 0, 0, cris_ver_version_all, NULL}
  92 };
  93
  94 /* Add version specifiers to this table when necessary.
  95    The (now) regular coding of register names suggests a simpler
  96    implementation.  */
  97 const struct cris_support_reg cris_support_regs[] =
  98 {
  99   {"s0", 0},
 100   {"s1", 1},
 101   {"s2", 2},
 102   {"s3", 3},
 103   {"s4", 4},
 104   {"s5", 5},
 105   {"s6", 6},
 106   {"s7", 7},
 107   {"s8", 8},
 108   {"s9", 9},
 109   {"s10", 10},
 110   {"s11", 11},
 111   {"s12", 12},
 112   {"s13", 13},
 113   {"s14", 14},
 114   {"s15", 15},
 115   {NULL, 0}
 116 };
 117
 118 /* All CRIS opcodes are 16 bits.
 119
 120    - The match component is a mask saying which bits must match a
 121      particular opcode in order for an instruction to be an instance
 122      of that opcode.
 123
 124    - The args component is a string containing characters symbolically
 125      matching the operands of an instruction.  Used for both assembly
 126      and disassembly.
 127
 128      Operand-matching characters:
 129      [ ] , space
 130         Verbatim.
 131      A  The string "ACR" (case-insensitive).
 132      B  Not really an operand.  It causes a "BDAP -size,SP" prefix to be
 133         output for the PUSH alias-instructions and recognizes a push-
 134         prefix at disassembly.  This letter isn't recognized for v32.
 135         Must be followed by a R or P letter.
 136      !  Non-match pattern, will not match if there's a prefix insn.
 137      b  Non-matching operand, used for branches with 16-bit
 138         displacement. Only recognized by the disassembler.
 139      c  5-bit unsigned immediate in bits <4:0>.
 140      C  4-bit unsigned immediate in bits <3:0>.
 141      d  At assembly, optionally (as in put other cases before this one)
 142         ".d" or ".D" at the start of the operands, followed by one space
 143         character.  At disassembly, nothing.
 144      D  General register in bits <15:12> and <3:0>.
 145      f  List of flags in bits <15:12> and <3:0>.
 146      i  6-bit signed immediate in bits <5:0>.
 147      I  6-bit unsigned immediate in bits <5:0>.
 148      M  Size modifier (B, W or D) for CLEAR instructions.
 149      m  Size modifier (B, W or D) in bits <5:4>
 150      N  A 32-bit dword, like in the difference between s and y.
 151         This has no effect on bits in the opcode.  Can also be expressed
 152         as "[pc+]" in input.
 153      n  As N, but PC-relative (to the start of the instruction).
 154      o  [-128..127] word offset in bits <7:1> and <0>.  Used by 8-bit
 155         branch instructions.
 156      O  [-128..127] offset in bits <7:0>.  Also matches a comma and a
 157         general register after the expression, in bits <15:12>.  Used
 158         only for the BDAP prefix insn (in v32 the ADDOQ insn; same opcode).
 159      P  Special register in bits <15:12>.
 160      p  Indicates that the insn is a prefix insn.  Must be first
 161         character.
 162      Q  As O, but don't relax; force an 8-bit offset.
 163      R  General register in bits <15:12>.
 164      r  General register in bits <3:0>.
 165      S  Source operand in bit <10> and a prefix; a 3-operand prefix
 166         without side-effect.
 167      s  Source operand in bits <10> and <3:0>, optionally with a
 168         side-effect prefix, except [pc] (the name, not R15 as in ACR)
 169         isn't allowed for v32 and higher.
 170      T  Support register in bits <15:12>.
 171      u  4-bit (PC-relative) unsigned immediate word offset in bits <3:0>.
 172      U  Relaxes to either u or n, instruction is assumed LAPCQ or LAPC.
 173         Not recognized at disassembly.
 174      x  Register-dot-modifier, for example "r5.w" in bits <15:12> and <5:4>.
 175      y  Like 's' but do not allow an integer at assembly.
 176      Y  The difference s-y; only an integer is allowed.
 177      z  Size modifier (B or W) in bit <4>.  */
 178
 179
 180 /* Please note the order of the opcodes in this table is significant.
 181    The assembler requires that all instances of the same mnemonic must
 182    be consecutive.  If they aren't, the assembler might not recognize
 183    them, or may indicate an internal error.
 184
 185    The disassembler should not normally care about the order of the
 186    opcodes, but will prefer an earlier alternative if the "match-score"
 187    (see cris-dis.c) is computed as equal.
 188
 189    It should not be significant for proper execution that this table is
 190    in alphabetical order, but please follow that convention for an easy
 191    overview.  */
 192
 193 const struct cris_opcode
 194 cris_opcodes[] =
 195 {
 196   {"abs",     0x06B0, 0x0940,             "r,R",     0, SIZE_NONE,     0,
 197    cris_abs_op},
 198
 199   {"add",     0x0600, 0x09c0,             "m r,R",   0, SIZE_NONE,     0,
 200    cris_reg_mode_add_sub_cmp_and_or_move_op},
 201
 202   {"add",     0x0A00, 0x01c0,             "m s,R",   0, SIZE_FIELD,    0,
 203    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
 204
 205   {"add",     0x0A00, 0x01c0,             "m S,D",   0, SIZE_NONE,
 206    cris_ver_v0_10,
 207    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
 208
 209   {"add",     0x0a00, 0x05c0,             "m S,R,r", 0, SIZE_NONE,
 210    cris_ver_v0_10,
 211    cris_three_operand_add_sub_cmp_and_or_op},
 212
 213   {"add",     0x0A00, 0x01c0,             "m s,R",   0, SIZE_FIELD,
 214    cris_ver_v32p,
 215    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
 216
 217   {"addc",    0x0570, 0x0A80,             "r,R",     0, SIZE_FIX_32,
 218    cris_ver_v32p,
 219    cris_not_implemented_op},
 220
 221   {"addc",    0x09A0, 0x0250,             "s,R",     0, SIZE_FIX_32,
 222    cris_ver_v32p,
 223    cris_not_implemented_op},
 224
 225   {"addi",    0x0540, 0x0A80,             "x,r,A",   0, SIZE_NONE,
 226    cris_ver_v32p,
 227    cris_addi_op},
 228
 229   {"addi",    0x0500, 0x0Ac0,             "x,r",     0, SIZE_NONE,     0,
 230    cris_addi_op},
 231
 232   /* This collates after "addo", but we want to disassemble as "addoq",
 233      not "addo".  */
 234   {"addoq",   0x0100, 0x0E00,             "Q,A",     0, SIZE_NONE,
 235    cris_ver_v32p,
 236    cris_not_implemented_op},
 237
 238   {"addo",    0x0940, 0x0280,             "m s,R,A", 0, SIZE_FIELD_SIGNED,
 239    cris_ver_v32p,
 240    cris_not_implemented_op},
 241
 242   /* This must be located after the insn above, lest we misinterpret
 243      "addo.b -1,r0,acr" as "addo .b-1,r0,acr".  FIXME: Sounds like a
 244      parser bug.  */
 245   {"addo",   0x0100, 0x0E00,              "O,A",     0, SIZE_NONE,
 246    cris_ver_v32p,
 247    cris_not_implemented_op},
 248
 249   {"addq",    0x0200, 0x0Dc0,             "I,R",     0, SIZE_NONE,     0,
 250    cris_quick_mode_add_sub_op},
 251
 252   {"adds",    0x0420, 0x0Bc0,             "z r,R",   0, SIZE_NONE,     0,
 253    cris_reg_mode_add_sub_cmp_and_or_move_op},
 254
 255   /* FIXME: SIZE_FIELD_SIGNED and all necessary changes.  */
 256   {"adds",    0x0820, 0x03c0,             "z s,R",   0, SIZE_FIELD,    0,
 257    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
 258
 259   {"adds",    0x0820, 0x03c0,             "z S,D",   0, SIZE_NONE,
 260    cris_ver_v0_10,
 261    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
 262
 263   {"adds",    0x0820, 0x07c0,             "z S,R,r", 0, SIZE_NONE,
 264    cris_ver_v0_10,
 265    cris_three_operand_add_sub_cmp_and_or_op},
 266
 267   {"addu",    0x0400, 0x0be0,             "z r,R",   0, SIZE_NONE,     0,
 268    cris_reg_mode_add_sub_cmp_and_or_move_op},
 269
 270   /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes.  */
 271   {"addu",    0x0800, 0x03e0,             "z s,R",   0, SIZE_FIELD,    0,
 272    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
 273
 274   {"addu",    0x0800, 0x03e0,             "z S,D",   0, SIZE_NONE,
 275    cris_ver_v0_10,
 276    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
 277
 278   {"addu",    0x0800, 0x07e0,             "z S,R,r", 0, SIZE_NONE,
 279    cris_ver_v0_10,
 280    cris_three_operand_add_sub_cmp_and_or_op},
 281
 282   {"and",     0x0700, 0x08C0,             "m r,R",   0, SIZE_NONE,     0,
 283    cris_reg_mode_add_sub_cmp_and_or_move_op},
 284
 285   {"and",     0x0B00, 0x00C0,             "m s,R",   0, SIZE_FIELD,    0,
 286    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
 287
 288   {"and",     0x0B00, 0x00C0,             "m S,D",   0, SIZE_NONE,
 289    cris_ver_v0_10,
 290    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
 291
 292   {"and",     0x0B00, 0x04C0,             "m S,R,r", 0, SIZE_NONE,
 293    cris_ver_v0_10,
 294    cris_three_operand_add_sub_cmp_and_or_op},
 295
 296   {"andq",    0x0300, 0x0CC0,             "i,R",     0, SIZE_NONE,     0,
 297    cris_quick_mode_and_cmp_move_or_op},
 298
 299   {"asr",     0x0780, 0x0840,             "m r,R",   0, SIZE_NONE,     0,
 300    cris_asr_op},
 301
 302   {"asrq",    0x03a0, 0x0c40,             "c,R",     0, SIZE_NONE,     0,
 303    cris_asrq_op},
 304
 305   {"ax",      0x15B0, 0xEA4F,             "",        0, SIZE_NONE,     0,
 306    cris_ax_ei_setf_op},
 307
 308   /* FIXME: Should use branch #defines.  */
 309   {"b",       0x0dff, 0x0200,             "b",       1, SIZE_NONE,     0,
 310    cris_sixteen_bit_offset_branch_op},
 311
 312   {"ba",
 313    BA_QUICK_OPCODE,
 314    0x0F00+(0xF-CC_A)*0x1000,              "o",       1, SIZE_NONE,     0,
 315    cris_eight_bit_offset_branch_op},
 316
 317   /* Needs to come after the usual "ba o", which might be relaxed to
 318      this one.  */
 319   {"ba",     BA_DWORD_OPCODE,
 320    0xffff & (~BA_DWORD_OPCODE),           "n",       0, SIZE_FIX_32,
 321    cris_ver_v32p,
 322    cris_none_reg_mode_jump_op},
 323
 324   {"bas",     0x0EBF, 0x0140,             "n,P",     0, SIZE_FIX_32,
 325    cris_ver_v32p,
 326    cris_none_reg_mode_jump_op},
 327
 328   {"basc",     0x0EFF, 0x0100,            "n,P",     0, SIZE_FIX_32,
 329    cris_ver_v32p,
 330    cris_none_reg_mode_jump_op},
 331
 332   {"bcc",
 333    BRANCH_QUICK_OPCODE+CC_CC*0x1000,
 334    0x0f00+(0xF-CC_CC)*0x1000,             "o",       1, SIZE_NONE,     0,
 335    cris_eight_bit_offset_branch_op},
 336
 337   {"bcs",
 338    BRANCH_QUICK_OPCODE+CC_CS*0x1000,
 339    0x0f00+(0xF-CC_CS)*0x1000,             "o",       1, SIZE_NONE,     0,
 340    cris_eight_bit_offset_branch_op},
 341
 342   {"bdap",
 343    BDAP_INDIR_OPCODE, BDAP_INDIR_Z_BITS,  "pm s,R",  0, SIZE_FIELD_SIGNED,
 344    cris_ver_v0_10,
 345    cris_bdap_prefix},
 346
 347   {"bdap",
 348    BDAP_QUICK_OPCODE, BDAP_QUICK_Z_BITS,  "pO",      0, SIZE_NONE,
 349    cris_ver_v0_10,
 350    cris_quick_mode_bdap_prefix},
 351
 352   {"beq",
 353    BRANCH_QUICK_OPCODE+CC_EQ*0x1000,
 354    0x0f00+(0xF-CC_EQ)*0x1000,             "o",       1, SIZE_NONE,     0,
 355    cris_eight_bit_offset_branch_op},
 356
 357   /* This is deliberately put before "bext" to trump it, even though not
 358      in alphabetical order, since we don't do excluding version checks
 359      for v0..v10.  */
 360   {"bwf",
 361    BRANCH_QUICK_OPCODE+CC_EXT*0x1000,
 362    0x0f00+(0xF-CC_EXT)*0x1000,            "o",       1, SIZE_NONE,
 363    cris_ver_v10,
 364    cris_eight_bit_offset_branch_op},
 365
 366   {"bext",
 367    BRANCH_QUICK_OPCODE+CC_EXT*0x1000,
 368    0x0f00+(0xF-CC_EXT)*0x1000,            "o",       1, SIZE_NONE,
 369    cris_ver_v0_3,
 370    cris_eight_bit_offset_branch_op},
 371
 372   {"bge",
 373    BRANCH_QUICK_OPCODE+CC_GE*0x1000,
 374    0x0f00+(0xF-CC_GE)*0x1000,             "o",       1, SIZE_NONE,     0,
 375    cris_eight_bit_offset_branch_op},
 376
 377   {"bgt",
 378    BRANCH_QUICK_OPCODE+CC_GT*0x1000,
 379    0x0f00+(0xF-CC_GT)*0x1000,             "o",       1, SIZE_NONE,     0,
 380    cris_eight_bit_offset_branch_op},
 381
 382   {"bhi",
 383    BRANCH_QUICK_OPCODE+CC_HI*0x1000,
 384    0x0f00+(0xF-CC_HI)*0x1000,             "o",       1, SIZE_NONE,     0,
 385    cris_eight_bit_offset_branch_op},
 386
 387   {"bhs",
 388    BRANCH_QUICK_OPCODE+CC_HS*0x1000,
 389    0x0f00+(0xF-CC_HS)*0x1000,             "o",       1, SIZE_NONE,     0,
 390    cris_eight_bit_offset_branch_op},
 391
 392   {"biap", BIAP_OPCODE, BIAP_Z_BITS,      "pm r,R",  0, SIZE_NONE,
 393    cris_ver_v0_10,
 394    cris_biap_prefix},
 395
 396   {"ble",
 397    BRANCH_QUICK_OPCODE+CC_LE*0x1000,
 398    0x0f00+(0xF-CC_LE)*0x1000,             "o",       1, SIZE_NONE,     0,
 399    cris_eight_bit_offset_branch_op},
 400
 401   {"blo",
 402    BRANCH_QUICK_OPCODE+CC_LO*0x1000,
 403    0x0f00+(0xF-CC_LO)*0x1000,             "o",       1, SIZE_NONE,     0,
 404    cris_eight_bit_offset_branch_op},
 405
 406   {"bls",
 407    BRANCH_QUICK_OPCODE+CC_LS*0x1000,
 408    0x0f00+(0xF-CC_LS)*0x1000,             "o",       1, SIZE_NONE,     0,
 409    cris_eight_bit_offset_branch_op},
 410
 411   {"blt",
 412    BRANCH_QUICK_OPCODE+CC_LT*0x1000,
 413    0x0f00+(0xF-CC_LT)*0x1000,             "o",       1, SIZE_NONE,     0,
 414    cris_eight_bit_offset_branch_op},
 415
 416   {"bmi",
 417    BRANCH_QUICK_OPCODE+CC_MI*0x1000,
 418    0x0f00+(0xF-CC_MI)*0x1000,             "o",       1, SIZE_NONE,     0,
 419    cris_eight_bit_offset_branch_op},
 420
 421   {"bmod",    0x0ab0, 0x0140,             "s,R",     0, SIZE_FIX_32,
 422    cris_ver_sim_v0_10,
 423    cris_not_implemented_op},
 424
 425   {"bmod",    0x0ab0, 0x0140,             "S,D",     0, SIZE_NONE,
 426    cris_ver_sim_v0_10,
 427    cris_not_implemented_op},
 428
 429   {"bmod",    0x0ab0, 0x0540,             "S,R,r",   0, SIZE_NONE,
 430    cris_ver_sim_v0_10,
 431    cris_not_implemented_op},
 432
 433   {"bne",
 434    BRANCH_QUICK_OPCODE+CC_NE*0x1000,
 435    0x0f00+(0xF-CC_NE)*0x1000,             "o",       1, SIZE_NONE,     0,
 436    cris_eight_bit_offset_branch_op},
 437
 438   {"bound",   0x05c0, 0x0A00,             "m r,R",   0, SIZE_NONE,     0,
 439    cris_two_operand_bound_op},
 440   /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes.  */
 441   {"bound",   0x09c0, 0x0200,             "m s,R",   0, SIZE_FIELD,
 442    cris_ver_v0_10,
 443    cris_two_operand_bound_op},
 444   /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes.  */
 445   {"bound",   0x0dcf, 0x0200,             "m Y,R",   0, SIZE_FIELD,    0,
 446    cris_two_operand_bound_op},
 447   {"bound",   0x09c0, 0x0200,             "m S,D",   0, SIZE_NONE,
 448    cris_ver_v0_10,
 449    cris_two_operand_bound_op},
 450   {"bound",   0x09c0, 0x0600,             "m S,R,r", 0, SIZE_NONE,
 451    cris_ver_v0_10,
 452    cris_three_operand_bound_op},
 453
 454   {"bpl",
 455    BRANCH_QUICK_OPCODE+CC_PL*0x1000,
 456    0x0f00+(0xF-CC_PL)*0x1000,             "o",       1, SIZE_NONE,     0,
 457    cris_eight_bit_offset_branch_op},
 458
 459   {"break",   0xe930, 0x16c0,             "C",       0, SIZE_NONE,
 460    cris_ver_v3p,
 461    cris_break_op},
 462
 463   {"bsb",
 464    BRANCH_QUICK_OPCODE+CC_EXT*0x1000,
 465    0x0f00+(0xF-CC_EXT)*0x1000,            "o",       1, SIZE_NONE,
 466    cris_ver_v32p,
 467    cris_eight_bit_offset_branch_op},
 468
 469   {"bsr",     0xBEBF, 0x4140,             "n",       0, SIZE_FIX_32,
 470    cris_ver_v32p,
 471    cris_none_reg_mode_jump_op},
 472
 473   {"bsrc",     0xBEFF, 0x4100,            "n",       0, SIZE_FIX_32,
 474    cris_ver_v32p,
 475    cris_none_reg_mode_jump_op},
 476
 477   {"bstore",  0x0af0, 0x0100,             "s,R",     0, SIZE_FIX_32,
 478    cris_ver_warning,
 479    cris_not_implemented_op},
 480
 481   {"bstore",  0x0af0, 0x0100,             "S,D",     0, SIZE_NONE,
 482    cris_ver_warning,
 483    cris_not_implemented_op},
 484
 485   {"bstore",  0x0af0, 0x0500,             "S,R,r",   0, SIZE_NONE,
 486    cris_ver_warning,
 487    cris_not_implemented_op},
 488
 489   {"btst",    0x04F0, 0x0B00,             "r,R",     0, SIZE_NONE,     0,
 490    cris_btst_nop_op},
 491   {"btstq",   0x0380, 0x0C60,             "c,R",     0, SIZE_NONE,     0,
 492    cris_btst_nop_op},
 493
 494   {"bvc",
 495    BRANCH_QUICK_OPCODE+CC_VC*0x1000,
 496    0x0f00+(0xF-CC_VC)*0x1000,             "o",       1, SIZE_NONE,     0,
 497    cris_eight_bit_offset_branch_op},
 498
 499   {"bvs",
 500    BRANCH_QUICK_OPCODE+CC_VS*0x1000,
 501    0x0f00+(0xF-CC_VS)*0x1000,             "o",       1, SIZE_NONE,     0,
 502    cris_eight_bit_offset_branch_op},
 503
 504   {"clear",   0x0670, 0x3980,             "M r",     0, SIZE_NONE,     0,
 505    cris_reg_mode_clear_op},
 506
 507   {"clear",   0x0A70, 0x3180,             "M y",     0, SIZE_NONE,     0,
 508    cris_none_reg_mode_clear_test_op},
 509
 510   {"clear",   0x0A70, 0x3180,             "M S",     0, SIZE_NONE,
 511    cris_ver_v0_10,
 512    cris_none_reg_mode_clear_test_op},
 513
 514   {"clearf",  0x05F0, 0x0A00,             "f",       0, SIZE_NONE,     0,
 515    cris_clearf_di_op},
 516
 517   {"cmp",     0x06C0, 0x0900,             "m r,R",   0, SIZE_NONE,     0,
 518    cris_reg_mode_add_sub_cmp_and_or_move_op},
 519
 520   {"cmp",     0x0Ac0, 0x0100,             "m s,R",   0, SIZE_FIELD,    0,
 521    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
 522
 523   {"cmp",     0x0Ac0, 0x0100,             "m S,D",   0, SIZE_NONE,
 524    cris_ver_v0_10,
 525    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
 526
 527   {"cmpq",    0x02C0, 0x0D00,             "i,R",     0, SIZE_NONE,     0,
 528    cris_quick_mode_and_cmp_move_or_op},
 529
 530   /* FIXME: SIZE_FIELD_SIGNED and all necessary changes.  */
 531   {"cmps",    0x08e0, 0x0300,             "z s,R",   0, SIZE_FIELD,    0,
 532    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
 533
 534   {"cmps",    0x08e0, 0x0300,             "z S,D",   0, SIZE_NONE,
 535    cris_ver_v0_10,
 536    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
 537
 538   /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes.  */
 539   {"cmpu",    0x08c0, 0x0320,             "z s,R" ,  0, SIZE_FIELD,    0,
 540    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
 541
 542   {"cmpu",    0x08c0, 0x0320,             "z S,D",   0, SIZE_NONE,
 543    cris_ver_v0_10,
 544    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
 545
 546   {"di",      0x25F0, 0xDA0F,             "",        0, SIZE_NONE,     0,
 547    cris_clearf_di_op},
 548
 549   {"dip",     DIP_OPCODE, DIP_Z_BITS,     "ps",      0, SIZE_FIX_32,
 550    cris_ver_v0_10,
 551    cris_dip_prefix},
 552
 553   {"div",     0x0980, 0x0640,             "m R,r",   0, SIZE_FIELD,    0,
 554    cris_not_implemented_op},
 555
 556   {"dstep",   0x06f0, 0x0900,             "r,R",     0, SIZE_NONE,     0,
 557    cris_dstep_logshift_mstep_neg_not_op},
 558
 559   {"ei",      0x25B0, 0xDA4F,             "",        0, SIZE_NONE,     0,
 560    cris_ax_ei_setf_op},
 561
 562   {"fidxd",    0x0ab0, 0xf540,            "[r]",     0, SIZE_NONE,
 563    cris_ver_v32p,
 564    cris_not_implemented_op},
 565
 566   {"fidxi",    0x0d30, 0xF2C0,            "[r]",     0, SIZE_NONE,
 567    cris_ver_v32p,
 568    cris_not_implemented_op},
 569
 570   {"ftagd",    0x1AB0, 0xE540,            "[r]",     0, SIZE_NONE,
 571    cris_ver_v32p,
 572    cris_not_implemented_op},
 573
 574   {"ftagi",    0x1D30, 0xE2C0,            "[r]",     0, SIZE_NONE,
 575    cris_ver_v32p,
 576    cris_not_implemented_op},
 577
 578   {"halt",    0xF930, 0x06CF,             "",        0, SIZE_NONE,
 579    cris_ver_v32p,
 580    cris_not_implemented_op},
 581
 582   {"jas",    0x09B0, 0x0640,              "r,P",     0, SIZE_NONE,
 583    cris_ver_v32p,
 584    cris_reg_mode_jump_op},
 585
 586   {"jas",    0x0DBF, 0x0240,              "N,P",     0, SIZE_FIX_32,
 587    cris_ver_v32p,
 588    cris_reg_mode_jump_op},
 589
 590   {"jasc",    0x0B30, 0x04C0,             "r,P",     0, SIZE_NONE,
 591    cris_ver_v32p,
 592    cris_reg_mode_jump_op},
 593
 594   {"jasc",    0x0F3F, 0x00C0,             "N,P",     0, SIZE_FIX_32,
 595    cris_ver_v32p,
 596    cris_reg_mode_jump_op},
 597
 598   {"jbrc",    0x69b0, 0x9640,             "r",       0, SIZE_NONE,
 599    cris_ver_v8_10,
 600    cris_reg_mode_jump_op},
 601
 602   {"jbrc",    0x6930, 0x92c0,             "s",       0, SIZE_FIX_32,
 603    cris_ver_v8_10,
 604    cris_none_reg_mode_jump_op},
 605
 606   {"jbrc",    0x6930, 0x92c0,             "S",       0, SIZE_NONE,
 607    cris_ver_v8_10,
 608    cris_none_reg_mode_jump_op},
 609
 610   {"jir",     0xA9b0, 0x5640,             "r",       0, SIZE_NONE,
 611    cris_ver_v8_10,
 612    cris_reg_mode_jump_op},
 613
 614   {"jir",     0xA930, 0x52c0,             "s",       0, SIZE_FIX_32,
 615    cris_ver_v8_10,
 616    cris_none_reg_mode_jump_op},
 617
 618   {"jir",     0xA930, 0x52c0,             "S",       0, SIZE_NONE,
 619    cris_ver_v8_10,
 620    cris_none_reg_mode_jump_op},
 621
 622   {"jirc",    0x29b0, 0xd640,             "r",       0, SIZE_NONE,
 623    cris_ver_v8_10,
 624    cris_reg_mode_jump_op},
 625
 626   {"jirc",    0x2930, 0xd2c0,             "s",       0, SIZE_FIX_32,
 627    cris_ver_v8_10,
 628    cris_none_reg_mode_jump_op},
 629
 630   {"jirc",    0x2930, 0xd2c0,             "S",       0, SIZE_NONE,
 631    cris_ver_v8_10,
 632    cris_none_reg_mode_jump_op},
 633
 634   {"jsr",     0xB9b0, 0x4640,             "r",       0, SIZE_NONE,     0,
 635    cris_reg_mode_jump_op},
 636
 637   {"jsr",     0xB930, 0x42c0,             "s",       0, SIZE_FIX_32,
 638    cris_ver_v0_10,
 639    cris_none_reg_mode_jump_op},
 640
 641   {"jsr",     0xBDBF, 0x4240,             "N",       0, SIZE_FIX_32,
 642    cris_ver_v32p,
 643    cris_none_reg_mode_jump_op},
 644
 645   {"jsr",     0xB930, 0x42c0,             "S",       0, SIZE_NONE,
 646    cris_ver_v0_10,
 647    cris_none_reg_mode_jump_op},
 648
 649   {"jsrc",    0x39b0, 0xc640,             "r",       0, SIZE_NONE,
 650    cris_ver_v8_10,
 651    cris_reg_mode_jump_op},
 652
 653   {"jsrc",    0x3930, 0xc2c0,             "s",       0, SIZE_FIX_32,
 654    cris_ver_v8_10,
 655    cris_none_reg_mode_jump_op},
 656
 657   {"jsrc",    0x3930, 0xc2c0,             "S",       0, SIZE_NONE,
 658    cris_ver_v8_10,
 659    cris_none_reg_mode_jump_op},
 660
 661   {"jsrc",    0xBB30, 0x44C0,             "r",       0, SIZE_NONE,
 662    cris_ver_v32p,
 663    cris_reg_mode_jump_op},
 664
 665   {"jsrc",    0xBF3F, 0x40C0,             "N",       0, SIZE_FIX_32,
 666    cris_ver_v32p,
 667    cris_reg_mode_jump_op},
 668
 669   {"jump",    0x09b0, 0xF640,             "r",       0, SIZE_NONE,     0,
 670    cris_reg_mode_jump_op},
 671
 672   {"jump",
 673    JUMP_INDIR_OPCODE, JUMP_INDIR_Z_BITS,  "s",       0, SIZE_FIX_32,
 674    cris_ver_v0_10,
 675    cris_none_reg_mode_jump_op},
 676
 677   {"jump",
 678    JUMP_INDIR_OPCODE, JUMP_INDIR_Z_BITS,  "S",       0, SIZE_NONE,
 679    cris_ver_v0_10,
 680    cris_none_reg_mode_jump_op},
 681
 682   {"jump",    0x09F0, 0x060F,             "P",       0, SIZE_NONE,
 683    cris_ver_v32p,
 684    cris_none_reg_mode_jump_op},
 685
 686   {"jump",
 687    JUMP_PC_INCR_OPCODE_V32,
 688    (0xffff & ~JUMP_PC_INCR_OPCODE_V32),   "N",       0, SIZE_FIX_32,
 689    cris_ver_v32p,
 690    cris_none_reg_mode_jump_op},
 691
 692   {"jmpu",    0x8930, 0x72c0,             "s",       0, SIZE_FIX_32,
 693    cris_ver_v10,
 694    cris_none_reg_mode_jump_op},
 695
 696   {"jmpu",    0x8930, 0x72c0,              "S",      0, SIZE_NONE,
 697    cris_ver_v10,
 698    cris_none_reg_mode_jump_op},
 699
 700   {"lapc",    0x0970, 0x0680,             "U,R",    0, SIZE_NONE,
 701    cris_ver_v32p,
 702    cris_not_implemented_op},
 703
 704   {"lapc",    0x0D7F, 0x0280,             "dn,R",    0, SIZE_FIX_32,
 705    cris_ver_v32p,
 706    cris_not_implemented_op},
 707
 708   {"lapcq",   0x0970, 0x0680,             "u,R",     0, SIZE_NONE,
 709    cris_ver_v32p,
 710    cris_addi_op},
 711
 712   {"lsl",     0x04C0, 0x0B00,             "m r,R",   0, SIZE_NONE,     0,
 713    cris_dstep_logshift_mstep_neg_not_op},
 714
 715   {"lslq",    0x03c0, 0x0C20,             "c,R",     0, SIZE_NONE,     0,
 716    cris_dstep_logshift_mstep_neg_not_op},
 717
 718   {"lsr",     0x07C0, 0x0800,             "m r,R",   0, SIZE_NONE,     0,
 719    cris_dstep_logshift_mstep_neg_not_op},
 720
 721   {"lsrq",    0x03e0, 0x0C00,             "c,R",     0, SIZE_NONE,     0,
 722    cris_dstep_logshift_mstep_neg_not_op},
 723
 724   {"lz",      0x0730, 0x08C0,             "r,R",     0, SIZE_NONE,
 725    cris_ver_v3p,
 726    cris_not_implemented_op},
 727
 728   {"mcp",      0x07f0, 0x0800,            "P,r",     0, SIZE_NONE,
 729    cris_ver_v32p,
 730    cris_not_implemented_op},
 731
 732   {"move",    0x0640, 0x0980,             "m r,R",   0, SIZE_NONE,     0,
 733    cris_reg_mode_add_sub_cmp_and_or_move_op},
 734
 735   {"move",    0x0A40, 0x0180,             "m s,R",   0, SIZE_FIELD,    0,
 736    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
 737
 738   {"move",    0x0A40, 0x0180,             "m S,D",   0, SIZE_NONE,
 739    cris_ver_v0_10,
 740    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
 741
 742   {"move",    0x0630, 0x09c0,             "r,P",     0, SIZE_NONE,     0,
 743    cris_move_to_preg_op},
 744
 745   {"move",    0x0670, 0x0980,             "P,r",     0, SIZE_NONE,     0,
 746    cris_reg_mode_move_from_preg_op},
 747
 748   {"move",    0x0BC0, 0x0000,             "m R,y",   0, SIZE_FIELD,    0,
 749    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
 750
 751   {"move",    0x0BC0, 0x0000,             "m D,S",   0, SIZE_NONE,
 752    cris_ver_v0_10,
 753    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
 754
 755   {"move",    0x0A30, 0x01c0,             "s,P",     0, SIZE_SPEC_REG, 0,
 756    cris_move_to_preg_op},
 757
 758   {"move",    0x0A30, 0x01c0,             "S,P",     0, SIZE_NONE,
 759    cris_ver_v0_10,
 760    cris_move_to_preg_op},
 761
 762   {"move",    0x0A70, 0x0180,             "P,y",     0, SIZE_SPEC_REG, 0,
 763    cris_none_reg_mode_move_from_preg_op},
 764
 765   {"move",    0x0A70, 0x0180,             "P,S",     0, SIZE_NONE,
 766    cris_ver_v0_10,
 767    cris_none_reg_mode_move_from_preg_op},
 768
 769   {"move",    0x0B70, 0x0480,             "r,T",     0, SIZE_NONE,
 770    cris_ver_v32p,
 771    cris_not_implemented_op},
 772
 773   {"move",    0x0F70, 0x0080,             "T,r",     0, SIZE_NONE,
 774    cris_ver_v32p,
 775    cris_not_implemented_op},
 776
 777   {"movem",   0x0BF0, 0x0000,             "R,y",     0, SIZE_FIX_32,   0,
 778    cris_move_reg_to_mem_movem_op},
 779
 780   {"movem",   0x0BF0, 0x0000,             "D,S",     0, SIZE_NONE,
 781    cris_ver_v0_10,
 782    cris_move_reg_to_mem_movem_op},
 783
 784   {"movem",   0x0BB0, 0x0040,             "s,R",     0, SIZE_FIX_32,   0,
 785    cris_move_mem_to_reg_movem_op},
 786
 787   {"movem",   0x0BB0, 0x0040,             "S,D",     0, SIZE_NONE,
 788    cris_ver_v0_10,
 789    cris_move_mem_to_reg_movem_op},
 790
 791   {"moveq",   0x0240, 0x0D80,             "i,R",     0, SIZE_NONE,     0,
 792    cris_quick_mode_and_cmp_move_or_op},
 793
 794   {"movs",    0x0460, 0x0B80,             "z r,R",   0, SIZE_NONE,     0,
 795    cris_reg_mode_add_sub_cmp_and_or_move_op},
 796
 797   /* FIXME: SIZE_FIELD_SIGNED and all necessary changes.  */
 798   {"movs",    0x0860, 0x0380,             "z s,R",   0, SIZE_FIELD,    0,
 799    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
 800
 801   {"movs",    0x0860, 0x0380,             "z S,D",   0, SIZE_NONE,
 802    cris_ver_v0_10,
 803    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
 804
 805   {"movu",    0x0440, 0x0Ba0,             "z r,R",   0, SIZE_NONE,     0,
 806    cris_reg_mode_add_sub_cmp_and_or_move_op},
 807
 808   /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes.  */
 809   {"movu",    0x0840, 0x03a0,             "z s,R",   0, SIZE_FIELD,    0,
 810    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
 811
 812   {"movu",    0x0840, 0x03a0,             "z S,D",   0, SIZE_NONE,
 813    cris_ver_v0_10,
 814    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
 815
 816   {"mstep",   0x07f0, 0x0800,             "r,R",     0, SIZE_NONE,
 817    cris_ver_v0_10,
 818    cris_dstep_logshift_mstep_neg_not_op},
 819
 820   {"muls",    0x0d00, 0x02c0,             "m r,R",   0, SIZE_NONE,
 821    cris_ver_v10p,
 822    cris_muls_op},
 823
 824   {"mulu",    0x0900, 0x06c0,             "m r,R",   0, SIZE_NONE,
 825    cris_ver_v10p,
 826    cris_mulu_op},
 827
 828   {"neg",     0x0580, 0x0A40,             "m r,R",   0, SIZE_NONE,     0,
 829    cris_dstep_logshift_mstep_neg_not_op},
 830
 831   {"nop",     NOP_OPCODE, NOP_Z_BITS,     "",        0, SIZE_NONE,
 832    cris_ver_v0_10,
 833    cris_btst_nop_op},
 834
 835   {"nop",     NOP_OPCODE_V32, NOP_Z_BITS_V32, "",    0, SIZE_NONE,
 836    cris_ver_v32p,
 837    cris_btst_nop_op},
 838
 839   {"not",     0x8770, 0x7880,             "r",       0, SIZE_NONE,     0,
 840    cris_dstep_logshift_mstep_neg_not_op},
 841
 842   {"or",      0x0740, 0x0880,             "m r,R",   0, SIZE_NONE,     0,
 843    cris_reg_mode_add_sub_cmp_and_or_move_op},
 844
 845   {"or",      0x0B40, 0x0080,             "m s,R",   0, SIZE_FIELD,    0,
 846    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
 847
 848   {"or",      0x0B40, 0x0080,             "m S,D",   0, SIZE_NONE,
 849    cris_ver_v0_10,
 850    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
 851
 852   {"or",      0x0B40, 0x0480,             "m S,R,r", 0, SIZE_NONE,
 853    cris_ver_v0_10,
 854    cris_three_operand_add_sub_cmp_and_or_op},
 855
 856   {"orq",     0x0340, 0x0C80,             "i,R",     0, SIZE_NONE,     0,
 857    cris_quick_mode_and_cmp_move_or_op},
 858
 859   {"pop",     0x0E6E, 0x0191,             "!R",      0, SIZE_NONE,
 860    cris_ver_v0_10,
 861    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
 862
 863   {"pop",     0x0e3e, 0x01c1,             "!P",      0, SIZE_NONE,
 864    cris_ver_v0_10,
 865    cris_none_reg_mode_move_from_preg_op},
 866
 867   {"push",    0x0FEE, 0x0011,             "BR",      0, SIZE_NONE,
 868    cris_ver_v0_10,
 869    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
 870
 871   {"push",    0x0E7E, 0x0181,             "BP",      0, SIZE_NONE,
 872    cris_ver_v0_10,
 873    cris_move_to_preg_op},
 874
 875   {"rbf",     0x3b30, 0xc0c0,             "y",       0, SIZE_NONE,
 876    cris_ver_v10,
 877    cris_not_implemented_op},
 878
 879   {"rbf",     0x3b30, 0xc0c0,             "S",       0, SIZE_NONE,
 880    cris_ver_v10,
 881    cris_not_implemented_op},
 882
 883   {"rfe",     0x2930, 0xD6CF,             "",        0, SIZE_NONE,
 884    cris_ver_v32p,
 885    cris_not_implemented_op},
 886
 887   {"rfg",     0x4930, 0xB6CF,             "",        0, SIZE_NONE,
 888    cris_ver_v32p,
 889    cris_not_implemented_op},
 890
 891   {"rfn",     0x5930, 0xA6CF,             "",        0, SIZE_NONE,
 892    cris_ver_v32p,
 893    cris_not_implemented_op},
 894
 895   {"ret",     0xB67F, 0x4980,             "",        1, SIZE_NONE,
 896    cris_ver_v0_10,
 897    cris_reg_mode_move_from_preg_op},
 898
 899   {"ret",     0xB9F0, 0x460F,             "",        1, SIZE_NONE,
 900    cris_ver_v32p,
 901    cris_reg_mode_move_from_preg_op},
 902
 903   {"retb",    0xe67f, 0x1980,             "",        1, SIZE_NONE,
 904    cris_ver_v0_10,
 905    cris_reg_mode_move_from_preg_op},
 906
 907   {"rete",     0xA9F0, 0x560F,            "",        1, SIZE_NONE,
 908    cris_ver_v32p,
 909    cris_reg_mode_move_from_preg_op},
 910
 911   {"reti",    0xA67F, 0x5980,             "",        1, SIZE_NONE,
 912    cris_ver_v0_10,
 913    cris_reg_mode_move_from_preg_op},
 914
 915   {"retn",     0xC9F0, 0x360F,            "",        1, SIZE_NONE,
 916    cris_ver_v32p,
 917    cris_reg_mode_move_from_preg_op},
 918
 919   {"sbfs",    0x3b70, 0xc080,             "y",       0, SIZE_NONE,
 920    cris_ver_v10,
 921    cris_not_implemented_op},
 922
 923   {"sbfs",    0x3b70, 0xc080,             "S",       0, SIZE_NONE,
 924    cris_ver_v10,
 925    cris_not_implemented_op},
 926
 927   {"sa",
 928    0x0530+CC_A*0x1000,
 929    0x0AC0+(0xf-CC_A)*0x1000,              "r",       0, SIZE_NONE,     0,
 930    cris_scc_op},
 931
 932   {"ssb",
 933    0x0530+CC_EXT*0x1000,
 934    0x0AC0+(0xf-CC_EXT)*0x1000,            "r",       0, SIZE_NONE,
 935    cris_ver_v32p,
 936    cris_scc_op},
 937
 938   {"scc",
 939    0x0530+CC_CC*0x1000,
 940    0x0AC0+(0xf-CC_CC)*0x1000,             "r",       0, SIZE_NONE,     0,
 941    cris_scc_op},
 942
 943   {"scs",
 944    0x0530+CC_CS*0x1000,
 945    0x0AC0+(0xf-CC_CS)*0x1000,             "r",       0, SIZE_NONE,     0,
 946    cris_scc_op},
 947
 948   {"seq",
 949    0x0530+CC_EQ*0x1000,
 950    0x0AC0+(0xf-CC_EQ)*0x1000,             "r",       0, SIZE_NONE,     0,
 951    cris_scc_op},
 952
 953   {"setf",    0x05b0, 0x0A40,             "f",       0, SIZE_NONE,     0,
 954    cris_ax_ei_setf_op},
 955
 956   {"sfe",    0x3930, 0xC6CF,              "",        0, SIZE_NONE,
 957    cris_ver_v32p,
 958    cris_not_implemented_op},
 959
 960   /* Need to have "swf" in front of "sext" so it is the one displayed in
 961      disassembly.  */
 962   {"swf",
 963    0x0530+CC_EXT*0x1000,
 964    0x0AC0+(0xf-CC_EXT)*0x1000,            "r",       0, SIZE_NONE,
 965    cris_ver_v10,
 966    cris_scc_op},
 967
 968   {"sext",
 969    0x0530+CC_EXT*0x1000,
 970    0x0AC0+(0xf-CC_EXT)*0x1000,            "r",       0, SIZE_NONE,
 971    cris_ver_v0_3,
 972    cris_scc_op},
 973
 974   {"sge",
 975    0x0530+CC_GE*0x1000,
 976    0x0AC0+(0xf-CC_GE)*0x1000,             "r",       0, SIZE_NONE,     0,
 977    cris_scc_op},
 978
 979   {"sgt",
 980    0x0530+CC_GT*0x1000,
 981    0x0AC0+(0xf-CC_GT)*0x1000,             "r",       0, SIZE_NONE,     0,
 982    cris_scc_op},
 983
 984   {"shi",
 985    0x0530+CC_HI*0x1000,
 986    0x0AC0+(0xf-CC_HI)*0x1000,             "r",       0, SIZE_NONE,     0,
 987    cris_scc_op},
 988
 989   {"shs",
 990    0x0530+CC_HS*0x1000,
 991    0x0AC0+(0xf-CC_HS)*0x1000,             "r",       0, SIZE_NONE,     0,
 992    cris_scc_op},
 993
 994   {"sle",
 995    0x0530+CC_LE*0x1000,
 996    0x0AC0+(0xf-CC_LE)*0x1000,             "r",       0, SIZE_NONE,     0,
 997    cris_scc_op},
 998
 999   {"slo",
1000    0x0530+CC_LO*0x1000,
1001    0x0AC0+(0xf-CC_LO)*0x1000,             "r",       0, SIZE_NONE,     0,
1002    cris_scc_op},
1003
1004   {"sls",
1005    0x0530+CC_LS*0x1000,
1006    0x0AC0+(0xf-CC_LS)*0x1000,             "r",       0, SIZE_NONE,     0,
1007    cris_scc_op},
1008
1009   {"slt",
1010    0x0530+CC_LT*0x1000,
1011    0x0AC0+(0xf-CC_LT)*0x1000,             "r",       0, SIZE_NONE,     0,
1012    cris_scc_op},
1013
1014   {"smi",
1015    0x0530+CC_MI*0x1000,
1016    0x0AC0+(0xf-CC_MI)*0x1000,             "r",       0, SIZE_NONE,     0,
1017    cris_scc_op},
1018
1019   {"sne",
1020    0x0530+CC_NE*0x1000,
1021    0x0AC0+(0xf-CC_NE)*0x1000,             "r",       0, SIZE_NONE,     0,
1022    cris_scc_op},
1023
1024   {"spl",
1025    0x0530+CC_PL*0x1000,
1026    0x0AC0+(0xf-CC_PL)*0x1000,             "r",       0, SIZE_NONE,     0,
1027    cris_scc_op},
1028
1029   {"sub",     0x0680, 0x0940,             "m r,R",   0, SIZE_NONE,     0,
1030    cris_reg_mode_add_sub_cmp_and_or_move_op},
1031
1032   {"sub",     0x0a80, 0x0140,             "m s,R",   0, SIZE_FIELD,    0,
1033    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
1034
1035   {"sub",     0x0a80, 0x0140,             "m S,D",   0, SIZE_NONE,
1036    cris_ver_v0_10,
1037    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
1038
1039   {"sub",     0x0a80, 0x0540,             "m S,R,r", 0, SIZE_NONE,
1040    cris_ver_v0_10,
1041    cris_three_operand_add_sub_cmp_and_or_op},
1042
1043   {"subq",    0x0280, 0x0d40,             "I,R",     0, SIZE_NONE,     0,
1044    cris_quick_mode_add_sub_op},
1045
1046   {"subs",    0x04a0, 0x0b40,             "z r,R",   0, SIZE_NONE,     0,
1047    cris_reg_mode_add_sub_cmp_and_or_move_op},
1048
1049   /* FIXME: SIZE_FIELD_SIGNED and all necessary changes.  */
1050   {"subs",    0x08a0, 0x0340,             "z s,R",   0, SIZE_FIELD,    0,
1051    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
1052
1053   {"subs",    0x08a0, 0x0340,             "z S,D",   0, SIZE_NONE,
1054    cris_ver_v0_10,
1055    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
1056
1057   {"subs",    0x08a0, 0x0740,             "z S,R,r", 0, SIZE_NONE,
1058    cris_ver_v0_10,
1059    cris_three_operand_add_sub_cmp_and_or_op},
1060
1061   {"subu",    0x0480, 0x0b60,             "z r,R",   0, SIZE_NONE,     0,
1062    cris_reg_mode_add_sub_cmp_and_or_move_op},
1063
1064   /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes.  */
1065   {"subu",    0x0880, 0x0360,             "z s,R",   0, SIZE_FIELD,    0,
1066    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
1067
1068   {"subu",    0x0880, 0x0360,             "z S,D",   0, SIZE_NONE,
1069    cris_ver_v0_10,
1070    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
1071
1072   {"subu",    0x0880, 0x0760,             "z S,R,r", 0, SIZE_NONE,
1073    cris_ver_v0_10,
1074    cris_three_operand_add_sub_cmp_and_or_op},
1075
1076   {"svc",
1077    0x0530+CC_VC*0x1000,
1078    0x0AC0+(0xf-CC_VC)*0x1000,             "r",       0, SIZE_NONE,     0,
1079    cris_scc_op},
1080
1081   {"svs",
1082    0x0530+CC_VS*0x1000,
1083    0x0AC0+(0xf-CC_VS)*0x1000,             "r",       0, SIZE_NONE,     0,
1084    cris_scc_op},
1085
1086   /* The insn "swapn" is the same as "not" and will be disassembled as
1087      such, but the swap* family of mnmonics are generally v8-and-higher
1088      only, so count it in.  */
1089   {"swapn",   0x8770, 0x7880,             "r",       0, SIZE_NONE,
1090    cris_ver_v8p,
1091    cris_not_implemented_op},
1092
1093   {"swapw",   0x4770, 0xb880,             "r",       0, SIZE_NONE,
1094    cris_ver_v8p,
1095    cris_not_implemented_op},
1096
1097   {"swapnw",  0xc770, 0x3880,             "r",       0, SIZE_NONE,
1098    cris_ver_v8p,
1099    cris_not_implemented_op},
1100
1101   {"swapb",   0x2770, 0xd880,             "r",       0, SIZE_NONE,
1102    cris_ver_v8p,
1103    cris_not_implemented_op},
1104
1105   {"swapnb",  0xA770, 0x5880,             "r",       0, SIZE_NONE,
1106    cris_ver_v8p,
1107    cris_not_implemented_op},
1108
1109   {"swapwb",  0x6770, 0x9880,             "r",       0, SIZE_NONE,
1110    cris_ver_v8p,
1111    cris_not_implemented_op},
1112
1113   {"swapnwb", 0xE770, 0x1880,             "r",       0, SIZE_NONE,
1114    cris_ver_v8p,
1115    cris_not_implemented_op},
1116
1117   {"swapr",   0x1770, 0xe880,             "r",       0, SIZE_NONE,
1118    cris_ver_v8p,
1119    cris_not_implemented_op},
1120
1121   {"swapnr",  0x9770, 0x6880,             "r",       0, SIZE_NONE,
1122    cris_ver_v8p,
1123    cris_not_implemented_op},
1124
1125   {"swapwr",  0x5770, 0xa880,             "r",       0, SIZE_NONE,
1126    cris_ver_v8p,
1127    cris_not_implemented_op},
1128
1129   {"swapnwr", 0xd770, 0x2880,             "r",       0, SIZE_NONE,
1130    cris_ver_v8p,
1131    cris_not_implemented_op},
1132
1133   {"swapbr",  0x3770, 0xc880,             "r",       0, SIZE_NONE,
1134    cris_ver_v8p,
1135    cris_not_implemented_op},
1136
1137   {"swapnbr", 0xb770, 0x4880,             "r",       0, SIZE_NONE,
1138    cris_ver_v8p,
1139    cris_not_implemented_op},
1140
1141   {"swapwbr", 0x7770, 0x8880,             "r",       0, SIZE_NONE,
1142    cris_ver_v8p,
1143    cris_not_implemented_op},
1144
1145   {"swapnwbr", 0xf770, 0x0880,            "r",       0, SIZE_NONE,
1146    cris_ver_v8p,
1147    cris_not_implemented_op},
1148
1149   {"test",    0x0640, 0x0980,             "m D",     0, SIZE_NONE,
1150    cris_ver_v0_10,
1151    cris_reg_mode_test_op},
1152
1153   {"test",    0x0b80, 0xf040,             "m y",     0, SIZE_FIELD,    0,
1154    cris_none_reg_mode_clear_test_op},
1155
1156   {"test",    0x0b80, 0xf040,             "m S",     0, SIZE_NONE,
1157    cris_ver_v0_10,
1158    cris_none_reg_mode_clear_test_op},
1159
1160   {"xor",     0x07B0, 0x0840,             "r,R",     0, SIZE_NONE,     0,
1161    cris_xor_op},
1162
1163   {NULL, 0, 0, NULL, 0, 0, 0, cris_not_implemented_op}
1164 };
1165
1166 /* Condition-names, indexed by the CC_* numbers as found in cris.h. */
1167 const char * const
1168 cris_cc_strings[] =
1169 {
1170   "hs",
1171   "lo",
1172   "ne",
1173   "eq",
1174   "vc",
1175   "vs",
1176   "pl",
1177   "mi",
1178   "ls",
1179   "hi",
1180   "ge",
1181   "lt",
1182   "gt",
1183   "le",
1184   "a",
1185   /* This is a placeholder.  In v0, this would be "ext".  In v32, this
1186      is "sb".  See cris_conds15.  */
1187   "wf"
1188 };
1189
1190 /* Different names and semantics for condition 1111 (0xf).  */
1191 const struct cris_cond15 cris_cond15s[] =
1192 {
1193   /* FIXME: In what version did condition "ext" disappear?  */
1194   {"ext", cris_ver_v0_3},
1195   {"wf", cris_ver_v10},
1196   {"sb", cris_ver_v32p},
1197   {NULL, 0}
1198 };
1199
1200
1201 /*
1202  * Local variables:
1203  * eval: (c-set-style "gnu")
1204  * indent-tabs-mode: t
1205  * End:
1206  */