file configure.info-2 was initially added on branch binutils-2_10-branch.
[binutils.git] / opcodes / m32r-desc.c
blob360c38f16426f447fb1fc3d7d9607e2835aaf32f
1 /* CPU data for m32r.
3 THIS FILE IS MACHINE GENERATED WITH CGEN.
5 Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
7 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
12 any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License along
20 with this program; if not, write to the Free Software Foundation, Inc.,
21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
25 #include "sysdep.h"
26 #include <ctype.h>
27 #include <stdio.h>
28 #include <stdarg.h>
29 #include "ansidecl.h"
30 #include "bfd.h"
31 #include "symcat.h"
32 #include "m32r-desc.h"
33 #include "m32r-opc.h"
34 #include "opintl.h"
36 /* Attributes. */
38 static const CGEN_ATTR_ENTRY bool_attr[] =
40 { "#f", 0 },
41 { "#t", 1 },
42 { 0, 0 }
45 static const CGEN_ATTR_ENTRY MACH_attr[] =
47 { "base", MACH_BASE },
48 { "m32r", MACH_M32R },
49 { "m32rx", MACH_M32RX },
50 { "max", MACH_MAX },
51 { 0, 0 }
54 static const CGEN_ATTR_ENTRY ISA_attr[] =
56 { "m32r", ISA_M32R },
57 { "max", ISA_MAX },
58 { 0, 0 }
61 static const CGEN_ATTR_ENTRY PIPE_attr[] =
63 { "NONE", PIPE_NONE },
64 { "O", PIPE_O },
65 { "S", PIPE_S },
66 { "OS", PIPE_OS },
67 { 0, 0 }
70 const CGEN_ATTR_TABLE m32r_cgen_ifield_attr_table[] =
72 { "MACH", & MACH_attr[0] },
73 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
74 { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
75 { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
76 { "RESERVED", &bool_attr[0], &bool_attr[0] },
77 { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
78 { "SIGNED", &bool_attr[0], &bool_attr[0] },
79 { "RELOC", &bool_attr[0], &bool_attr[0] },
80 { 0, 0, 0 }
83 const CGEN_ATTR_TABLE m32r_cgen_hardware_attr_table[] =
85 { "MACH", & MACH_attr[0] },
86 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
87 { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
88 { "PC", &bool_attr[0], &bool_attr[0] },
89 { "PROFILE", &bool_attr[0], &bool_attr[0] },
90 { 0, 0, 0 }
93 const CGEN_ATTR_TABLE m32r_cgen_operand_attr_table[] =
95 { "MACH", & MACH_attr[0] },
96 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
97 { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
98 { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
99 { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
100 { "SIGNED", &bool_attr[0], &bool_attr[0] },
101 { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
102 { "RELAX", &bool_attr[0], &bool_attr[0] },
103 { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
104 { "RELOC", &bool_attr[0], &bool_attr[0] },
105 { "HASH-PREFIX", &bool_attr[0], &bool_attr[0] },
106 { 0, 0, 0 }
109 const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[] =
111 { "MACH", & MACH_attr[0] },
112 { "PIPE", & PIPE_attr[0] },
113 { "ALIAS", &bool_attr[0], &bool_attr[0] },
114 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
115 { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
116 { "COND-CTI", &bool_attr[0], &bool_attr[0] },
117 { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
118 { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
119 { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
120 { "RELAX", &bool_attr[0], &bool_attr[0] },
121 { "NO-DIS", &bool_attr[0], &bool_attr[0] },
122 { "PBB", &bool_attr[0], &bool_attr[0] },
123 { "FILL-SLOT", &bool_attr[0], &bool_attr[0] },
124 { "SPECIAL", &bool_attr[0], &bool_attr[0] },
125 { 0, 0, 0 }
128 /* Instruction set variants. */
130 static const CGEN_ISA m32r_cgen_isa_table[] = {
131 { "m32r", 32, 32, 16, 32, },
132 { 0 }
135 /* Machine variants. */
137 static const CGEN_MACH m32r_cgen_mach_table[] = {
138 { "m32r", "m32r", MACH_M32R },
139 { "m32rx", "m32rx", MACH_M32RX },
140 { 0 }
143 static CGEN_KEYWORD_ENTRY m32r_cgen_opval_gr_names_entries[] =
145 { "fp", 13 },
146 { "lr", 14 },
147 { "sp", 15 },
148 { "r0", 0 },
149 { "r1", 1 },
150 { "r2", 2 },
151 { "r3", 3 },
152 { "r4", 4 },
153 { "r5", 5 },
154 { "r6", 6 },
155 { "r7", 7 },
156 { "r8", 8 },
157 { "r9", 9 },
158 { "r10", 10 },
159 { "r11", 11 },
160 { "r12", 12 },
161 { "r13", 13 },
162 { "r14", 14 },
163 { "r15", 15 }
166 CGEN_KEYWORD m32r_cgen_opval_gr_names =
168 & m32r_cgen_opval_gr_names_entries[0],
172 static CGEN_KEYWORD_ENTRY m32r_cgen_opval_cr_names_entries[] =
174 { "psw", 0 },
175 { "cbr", 1 },
176 { "spi", 2 },
177 { "spu", 3 },
178 { "bpc", 6 },
179 { "bbpsw", 8 },
180 { "bbpc", 14 },
181 { "cr0", 0 },
182 { "cr1", 1 },
183 { "cr2", 2 },
184 { "cr3", 3 },
185 { "cr4", 4 },
186 { "cr5", 5 },
187 { "cr6", 6 },
188 { "cr7", 7 },
189 { "cr8", 8 },
190 { "cr9", 9 },
191 { "cr10", 10 },
192 { "cr11", 11 },
193 { "cr12", 12 },
194 { "cr13", 13 },
195 { "cr14", 14 },
196 { "cr15", 15 }
199 CGEN_KEYWORD m32r_cgen_opval_cr_names =
201 & m32r_cgen_opval_cr_names_entries[0],
205 static CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_accums_entries[] =
207 { "a0", 0 },
208 { "a1", 1 }
211 CGEN_KEYWORD m32r_cgen_opval_h_accums =
213 & m32r_cgen_opval_h_accums_entries[0],
219 /* The hardware table. */
221 #define A(a) (1 << CONCAT2 (CGEN_HW_,a))
223 const CGEN_HW_ENTRY m32r_cgen_hw_table[] =
225 { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
226 { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
227 { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
228 { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
229 { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
230 { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { (1<<MACH_BASE) } } },
231 { "h-hi16", HW_H_HI16, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
232 { "h-slo16", HW_H_SLO16, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
233 { "h-ulo16", HW_H_ULO16, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
234 { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_gr_names, { 0|A(CACHE_ADDR)|A(PROFILE), { (1<<MACH_BASE) } } },
235 { "h-cr", HW_H_CR, CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_cr_names, { 0, { (1<<MACH_BASE) } } },
236 { "h-accum", HW_H_ACCUM, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
237 { "h-accums", HW_H_ACCUMS, CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_accums, { 0, { (1<<MACH_M32RX) } } },
238 { "h-cond", HW_H_COND, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
239 { "h-psw", HW_H_PSW, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
240 { "h-bpsw", HW_H_BPSW, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
241 { "h-bbpsw", HW_H_BBPSW, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
242 { "h-lock", HW_H_LOCK, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
243 { 0 }
246 #undef A
248 /* The instruction field table. */
250 #define A(a) (1 << CONCAT2 (CGEN_IFLD_,a))
252 const CGEN_IFLD m32r_cgen_ifld_table[] =
254 { M32R_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } } },
255 { M32R_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } } },
256 { M32R_F_OP1, "f-op1", 0, 32, 0, 4, { 0, { (1<<MACH_BASE) } } },
257 { M32R_F_OP2, "f-op2", 0, 32, 8, 4, { 0, { (1<<MACH_BASE) } } },
258 { M32R_F_COND, "f-cond", 0, 32, 4, 4, { 0, { (1<<MACH_BASE) } } },
259 { M32R_F_R1, "f-r1", 0, 32, 4, 4, { 0, { (1<<MACH_BASE) } } },
260 { M32R_F_R2, "f-r2", 0, 32, 12, 4, { 0, { (1<<MACH_BASE) } } },
261 { M32R_F_SIMM8, "f-simm8", 0, 32, 8, 8, { 0, { (1<<MACH_BASE) } } },
262 { M32R_F_SIMM16, "f-simm16", 0, 32, 16, 16, { 0, { (1<<MACH_BASE) } } },
263 { M32R_F_SHIFT_OP2, "f-shift-op2", 0, 32, 8, 3, { 0, { (1<<MACH_BASE) } } },
264 { M32R_F_UIMM4, "f-uimm4", 0, 32, 12, 4, { 0, { (1<<MACH_BASE) } } },
265 { M32R_F_UIMM5, "f-uimm5", 0, 32, 11, 5, { 0, { (1<<MACH_BASE) } } },
266 { M32R_F_UIMM16, "f-uimm16", 0, 32, 16, 16, { 0, { (1<<MACH_BASE) } } },
267 { M32R_F_UIMM24, "f-uimm24", 0, 32, 8, 24, { 0|A(RELOC)|A(ABS_ADDR), { (1<<MACH_BASE) } } },
268 { M32R_F_HI16, "f-hi16", 0, 32, 16, 16, { 0|A(SIGN_OPT), { (1<<MACH_BASE) } } },
269 { M32R_F_DISP8, "f-disp8", 0, 32, 8, 8, { 0|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
270 { M32R_F_DISP16, "f-disp16", 0, 32, 16, 16, { 0|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
271 { M32R_F_DISP24, "f-disp24", 0, 32, 8, 24, { 0|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
272 { M32R_F_OP23, "f-op23", 0, 32, 9, 3, { 0, { (1<<MACH_BASE) } } },
273 { M32R_F_OP3, "f-op3", 0, 32, 14, 2, { 0, { (1<<MACH_BASE) } } },
274 { M32R_F_ACC, "f-acc", 0, 32, 8, 1, { 0, { (1<<MACH_BASE) } } },
275 { M32R_F_ACCS, "f-accs", 0, 32, 12, 2, { 0, { (1<<MACH_BASE) } } },
276 { M32R_F_ACCD, "f-accd", 0, 32, 4, 2, { 0, { (1<<MACH_BASE) } } },
277 { M32R_F_BITS67, "f-bits67", 0, 32, 6, 2, { 0, { (1<<MACH_BASE) } } },
278 { M32R_F_BIT14, "f-bit14", 0, 32, 14, 1, { 0, { (1<<MACH_BASE) } } },
279 { M32R_F_IMM1, "f-imm1", 0, 32, 15, 1, { 0, { (1<<MACH_BASE) } } },
280 { 0 }
283 #undef A
285 /* The operand table. */
287 #define A(a) (1 << CONCAT2 (CGEN_OPERAND_,a))
288 #define OPERAND(op) CONCAT2 (M32R_OPERAND_,op)
290 const CGEN_OPERAND m32r_cgen_operand_table[] =
292 /* pc: program counter */
293 { "pc", M32R_OPERAND_PC, HW_H_PC, 0, 0,
294 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
295 /* sr: source register */
296 { "sr", M32R_OPERAND_SR, HW_H_GR, 12, 4,
297 { 0, { (1<<MACH_BASE) } } },
298 /* dr: destination register */
299 { "dr", M32R_OPERAND_DR, HW_H_GR, 4, 4,
300 { 0, { (1<<MACH_BASE) } } },
301 /* src1: source register 1 */
302 { "src1", M32R_OPERAND_SRC1, HW_H_GR, 4, 4,
303 { 0, { (1<<MACH_BASE) } } },
304 /* src2: source register 2 */
305 { "src2", M32R_OPERAND_SRC2, HW_H_GR, 12, 4,
306 { 0, { (1<<MACH_BASE) } } },
307 /* scr: source control register */
308 { "scr", M32R_OPERAND_SCR, HW_H_CR, 12, 4,
309 { 0, { (1<<MACH_BASE) } } },
310 /* dcr: destination control register */
311 { "dcr", M32R_OPERAND_DCR, HW_H_CR, 4, 4,
312 { 0, { (1<<MACH_BASE) } } },
313 /* simm8: 8 bit signed immediate */
314 { "simm8", M32R_OPERAND_SIMM8, HW_H_SINT, 8, 8,
315 { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
316 /* simm16: 16 bit signed immediate */
317 { "simm16", M32R_OPERAND_SIMM16, HW_H_SINT, 16, 16,
318 { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
319 /* uimm4: 4 bit trap number */
320 { "uimm4", M32R_OPERAND_UIMM4, HW_H_UINT, 12, 4,
321 { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
322 /* uimm5: 5 bit shift count */
323 { "uimm5", M32R_OPERAND_UIMM5, HW_H_UINT, 11, 5,
324 { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
325 /* uimm16: 16 bit unsigned immediate */
326 { "uimm16", M32R_OPERAND_UIMM16, HW_H_UINT, 16, 16,
327 { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
328 /* imm1: 1 bit immediate */
329 { "imm1", M32R_OPERAND_IMM1, HW_H_UINT, 15, 1,
330 { 0|A(HASH_PREFIX), { (1<<MACH_M32RX) } } },
331 /* accd: accumulator destination register */
332 { "accd", M32R_OPERAND_ACCD, HW_H_ACCUMS, 4, 2,
333 { 0, { (1<<MACH_M32RX) } } },
334 /* accs: accumulator source register */
335 { "accs", M32R_OPERAND_ACCS, HW_H_ACCUMS, 12, 2,
336 { 0, { (1<<MACH_M32RX) } } },
337 /* acc: accumulator reg (d) */
338 { "acc", M32R_OPERAND_ACC, HW_H_ACCUMS, 8, 1,
339 { 0, { (1<<MACH_M32RX) } } },
340 /* hash: # prefix */
341 { "hash", M32R_OPERAND_HASH, HW_H_SINT, 0, 0,
342 { 0, { (1<<MACH_BASE) } } },
343 /* hi16: high 16 bit immediate, sign optional */
344 { "hi16", M32R_OPERAND_HI16, HW_H_HI16, 16, 16,
345 { 0|A(SIGN_OPT), { (1<<MACH_BASE) } } },
346 /* slo16: 16 bit signed immediate, for low() */
347 { "slo16", M32R_OPERAND_SLO16, HW_H_SLO16, 16, 16,
348 { 0, { (1<<MACH_BASE) } } },
349 /* ulo16: 16 bit unsigned immediate, for low() */
350 { "ulo16", M32R_OPERAND_ULO16, HW_H_ULO16, 16, 16,
351 { 0, { (1<<MACH_BASE) } } },
352 /* uimm24: 24 bit address */
353 { "uimm24", M32R_OPERAND_UIMM24, HW_H_ADDR, 8, 24,
354 { 0|A(HASH_PREFIX)|A(RELOC)|A(ABS_ADDR), { (1<<MACH_BASE) } } },
355 /* disp8: 8 bit displacement */
356 { "disp8", M32R_OPERAND_DISP8, HW_H_IADDR, 8, 8,
357 { 0|A(RELAX)|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
358 /* disp16: 16 bit displacement */
359 { "disp16", M32R_OPERAND_DISP16, HW_H_IADDR, 16, 16,
360 { 0|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
361 /* disp24: 24 bit displacement */
362 { "disp24", M32R_OPERAND_DISP24, HW_H_IADDR, 8, 24,
363 { 0|A(RELAX)|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
364 /* condbit: condition bit */
365 { "condbit", M32R_OPERAND_CONDBIT, HW_H_COND, 0, 0,
366 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
367 /* accum: accumulator */
368 { "accum", M32R_OPERAND_ACCUM, HW_H_ACCUM, 0, 0,
369 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
370 { 0 }
373 #undef A
375 #define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
376 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
378 /* The instruction table. */
380 static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] =
382 /* Special null first entry.
383 A `num' value of zero is thus invalid.
384 Also, the special `invalid' insn resides here. */
385 { 0, 0, 0 },
386 /* add $dr,$sr */
388 M32R_INSN_ADD, "add", "add", 16,
389 { 0, { (1<<MACH_BASE), PIPE_OS } }
391 /* add3 $dr,$sr,$hash$slo16 */
393 M32R_INSN_ADD3, "add3", "add3", 32,
394 { 0, { (1<<MACH_BASE), PIPE_NONE } }
396 /* and $dr,$sr */
398 M32R_INSN_AND, "and", "and", 16,
399 { 0, { (1<<MACH_BASE), PIPE_OS } }
401 /* and3 $dr,$sr,$uimm16 */
403 M32R_INSN_AND3, "and3", "and3", 32,
404 { 0, { (1<<MACH_BASE), PIPE_NONE } }
406 /* or $dr,$sr */
408 M32R_INSN_OR, "or", "or", 16,
409 { 0, { (1<<MACH_BASE), PIPE_OS } }
411 /* or3 $dr,$sr,$hash$ulo16 */
413 M32R_INSN_OR3, "or3", "or3", 32,
414 { 0, { (1<<MACH_BASE), PIPE_NONE } }
416 /* xor $dr,$sr */
418 M32R_INSN_XOR, "xor", "xor", 16,
419 { 0, { (1<<MACH_BASE), PIPE_OS } }
421 /* xor3 $dr,$sr,$uimm16 */
423 M32R_INSN_XOR3, "xor3", "xor3", 32,
424 { 0, { (1<<MACH_BASE), PIPE_NONE } }
426 /* addi $dr,$simm8 */
428 M32R_INSN_ADDI, "addi", "addi", 16,
429 { 0, { (1<<MACH_BASE), PIPE_OS } }
431 /* addv $dr,$sr */
433 M32R_INSN_ADDV, "addv", "addv", 16,
434 { 0, { (1<<MACH_BASE), PIPE_OS } }
436 /* addv3 $dr,$sr,$simm16 */
438 M32R_INSN_ADDV3, "addv3", "addv3", 32,
439 { 0, { (1<<MACH_BASE), PIPE_NONE } }
441 /* addx $dr,$sr */
443 M32R_INSN_ADDX, "addx", "addx", 16,
444 { 0, { (1<<MACH_BASE), PIPE_OS } }
446 /* bc.s $disp8 */
448 M32R_INSN_BC8, "bc8", "bc.s", 16,
449 { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_O } }
451 /* bc.l $disp24 */
453 M32R_INSN_BC24, "bc24", "bc.l", 32,
454 { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
456 /* beq $src1,$src2,$disp16 */
458 M32R_INSN_BEQ, "beq", "beq", 32,
459 { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
461 /* beqz $src2,$disp16 */
463 M32R_INSN_BEQZ, "beqz", "beqz", 32,
464 { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
466 /* bgez $src2,$disp16 */
468 M32R_INSN_BGEZ, "bgez", "bgez", 32,
469 { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
471 /* bgtz $src2,$disp16 */
473 M32R_INSN_BGTZ, "bgtz", "bgtz", 32,
474 { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
476 /* blez $src2,$disp16 */
478 M32R_INSN_BLEZ, "blez", "blez", 32,
479 { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
481 /* bltz $src2,$disp16 */
483 M32R_INSN_BLTZ, "bltz", "bltz", 32,
484 { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
486 /* bnez $src2,$disp16 */
488 M32R_INSN_BNEZ, "bnez", "bnez", 32,
489 { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
491 /* bl.s $disp8 */
493 M32R_INSN_BL8, "bl8", "bl.s", 16,
494 { 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
496 /* bl.l $disp24 */
498 M32R_INSN_BL24, "bl24", "bl.l", 32,
499 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
501 /* bcl.s $disp8 */
503 M32R_INSN_BCL8, "bcl8", "bcl.s", 16,
504 { 0|A(FILL_SLOT)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
506 /* bcl.l $disp24 */
508 M32R_INSN_BCL24, "bcl24", "bcl.l", 32,
509 { 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
511 /* bnc.s $disp8 */
513 M32R_INSN_BNC8, "bnc8", "bnc.s", 16,
514 { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_O } }
516 /* bnc.l $disp24 */
518 M32R_INSN_BNC24, "bnc24", "bnc.l", 32,
519 { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
521 /* bne $src1,$src2,$disp16 */
523 M32R_INSN_BNE, "bne", "bne", 32,
524 { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
526 /* bra.s $disp8 */
528 M32R_INSN_BRA8, "bra8", "bra.s", 16,
529 { 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
531 /* bra.l $disp24 */
533 M32R_INSN_BRA24, "bra24", "bra.l", 32,
534 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
536 /* bncl.s $disp8 */
538 M32R_INSN_BNCL8, "bncl8", "bncl.s", 16,
539 { 0|A(FILL_SLOT)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
541 /* bncl.l $disp24 */
543 M32R_INSN_BNCL24, "bncl24", "bncl.l", 32,
544 { 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
546 /* cmp $src1,$src2 */
548 M32R_INSN_CMP, "cmp", "cmp", 16,
549 { 0, { (1<<MACH_BASE), PIPE_OS } }
551 /* cmpi $src2,$simm16 */
553 M32R_INSN_CMPI, "cmpi", "cmpi", 32,
554 { 0, { (1<<MACH_BASE), PIPE_NONE } }
556 /* cmpu $src1,$src2 */
558 M32R_INSN_CMPU, "cmpu", "cmpu", 16,
559 { 0, { (1<<MACH_BASE), PIPE_OS } }
561 /* cmpui $src2,$simm16 */
563 M32R_INSN_CMPUI, "cmpui", "cmpui", 32,
564 { 0, { (1<<MACH_BASE), PIPE_NONE } }
566 /* cmpeq $src1,$src2 */
568 M32R_INSN_CMPEQ, "cmpeq", "cmpeq", 16,
569 { 0, { (1<<MACH_M32RX), PIPE_OS } }
571 /* cmpz $src2 */
573 M32R_INSN_CMPZ, "cmpz", "cmpz", 16,
574 { 0, { (1<<MACH_M32RX), PIPE_OS } }
576 /* div $dr,$sr */
578 M32R_INSN_DIV, "div", "div", 32,
579 { 0, { (1<<MACH_BASE), PIPE_NONE } }
581 /* divu $dr,$sr */
583 M32R_INSN_DIVU, "divu", "divu", 32,
584 { 0, { (1<<MACH_BASE), PIPE_NONE } }
586 /* rem $dr,$sr */
588 M32R_INSN_REM, "rem", "rem", 32,
589 { 0, { (1<<MACH_BASE), PIPE_NONE } }
591 /* remu $dr,$sr */
593 M32R_INSN_REMU, "remu", "remu", 32,
594 { 0, { (1<<MACH_BASE), PIPE_NONE } }
596 /* divh $dr,$sr */
598 M32R_INSN_DIVH, "divh", "divh", 32,
599 { 0, { (1<<MACH_M32RX), PIPE_NONE } }
601 /* jc $sr */
603 M32R_INSN_JC, "jc", "jc", 16,
604 { 0|A(SPECIAL)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
606 /* jnc $sr */
608 M32R_INSN_JNC, "jnc", "jnc", 16,
609 { 0|A(SPECIAL)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
611 /* jl $sr */
613 M32R_INSN_JL, "jl", "jl", 16,
614 { 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
616 /* jmp $sr */
618 M32R_INSN_JMP, "jmp", "jmp", 16,
619 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
621 /* ld $dr,@$sr */
623 M32R_INSN_LD, "ld", "ld", 16,
624 { 0, { (1<<MACH_BASE), PIPE_O } }
626 /* ld $dr,@($slo16,$sr) */
628 M32R_INSN_LD_D, "ld-d", "ld", 32,
629 { 0, { (1<<MACH_BASE), PIPE_NONE } }
631 /* ldb $dr,@$sr */
633 M32R_INSN_LDB, "ldb", "ldb", 16,
634 { 0, { (1<<MACH_BASE), PIPE_O } }
636 /* ldb $dr,@($slo16,$sr) */
638 M32R_INSN_LDB_D, "ldb-d", "ldb", 32,
639 { 0, { (1<<MACH_BASE), PIPE_NONE } }
641 /* ldh $dr,@$sr */
643 M32R_INSN_LDH, "ldh", "ldh", 16,
644 { 0, { (1<<MACH_BASE), PIPE_O } }
646 /* ldh $dr,@($slo16,$sr) */
648 M32R_INSN_LDH_D, "ldh-d", "ldh", 32,
649 { 0, { (1<<MACH_BASE), PIPE_NONE } }
651 /* ldub $dr,@$sr */
653 M32R_INSN_LDUB, "ldub", "ldub", 16,
654 { 0, { (1<<MACH_BASE), PIPE_O } }
656 /* ldub $dr,@($slo16,$sr) */
658 M32R_INSN_LDUB_D, "ldub-d", "ldub", 32,
659 { 0, { (1<<MACH_BASE), PIPE_NONE } }
661 /* lduh $dr,@$sr */
663 M32R_INSN_LDUH, "lduh", "lduh", 16,
664 { 0, { (1<<MACH_BASE), PIPE_O } }
666 /* lduh $dr,@($slo16,$sr) */
668 M32R_INSN_LDUH_D, "lduh-d", "lduh", 32,
669 { 0, { (1<<MACH_BASE), PIPE_NONE } }
671 /* ld $dr,@$sr+ */
673 M32R_INSN_LD_PLUS, "ld-plus", "ld", 16,
674 { 0, { (1<<MACH_BASE), PIPE_O } }
676 /* ld24 $dr,$uimm24 */
678 M32R_INSN_LD24, "ld24", "ld24", 32,
679 { 0, { (1<<MACH_BASE), PIPE_NONE } }
681 /* ldi8 $dr,$simm8 */
683 M32R_INSN_LDI8, "ldi8", "ldi8", 16,
684 { 0, { (1<<MACH_BASE), PIPE_OS } }
686 /* ldi16 $dr,$hash$slo16 */
688 M32R_INSN_LDI16, "ldi16", "ldi16", 32,
689 { 0, { (1<<MACH_BASE), PIPE_NONE } }
691 /* lock $dr,@$sr */
693 M32R_INSN_LOCK, "lock", "lock", 16,
694 { 0, { (1<<MACH_BASE), PIPE_O } }
696 /* machi $src1,$src2 */
698 M32R_INSN_MACHI, "machi", "machi", 16,
699 { 0, { (1<<MACH_M32R), PIPE_S } }
701 /* machi $src1,$src2,$acc */
703 M32R_INSN_MACHI_A, "machi-a", "machi", 16,
704 { 0, { (1<<MACH_M32RX), PIPE_S } }
706 /* maclo $src1,$src2 */
708 M32R_INSN_MACLO, "maclo", "maclo", 16,
709 { 0, { (1<<MACH_M32R), PIPE_S } }
711 /* maclo $src1,$src2,$acc */
713 M32R_INSN_MACLO_A, "maclo-a", "maclo", 16,
714 { 0, { (1<<MACH_M32RX), PIPE_S } }
716 /* macwhi $src1,$src2 */
718 M32R_INSN_MACWHI, "macwhi", "macwhi", 16,
719 { 0, { (1<<MACH_M32R), PIPE_S } }
721 /* macwhi $src1,$src2,$acc */
723 M32R_INSN_MACWHI_A, "macwhi-a", "macwhi", 16,
724 { 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
726 /* macwlo $src1,$src2 */
728 M32R_INSN_MACWLO, "macwlo", "macwlo", 16,
729 { 0, { (1<<MACH_M32R), PIPE_S } }
731 /* macwlo $src1,$src2,$acc */
733 M32R_INSN_MACWLO_A, "macwlo-a", "macwlo", 16,
734 { 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
736 /* mul $dr,$sr */
738 M32R_INSN_MUL, "mul", "mul", 16,
739 { 0, { (1<<MACH_BASE), PIPE_S } }
741 /* mulhi $src1,$src2 */
743 M32R_INSN_MULHI, "mulhi", "mulhi", 16,
744 { 0, { (1<<MACH_M32R), PIPE_S } }
746 /* mulhi $src1,$src2,$acc */
748 M32R_INSN_MULHI_A, "mulhi-a", "mulhi", 16,
749 { 0, { (1<<MACH_M32RX), PIPE_S } }
751 /* mullo $src1,$src2 */
753 M32R_INSN_MULLO, "mullo", "mullo", 16,
754 { 0, { (1<<MACH_M32R), PIPE_S } }
756 /* mullo $src1,$src2,$acc */
758 M32R_INSN_MULLO_A, "mullo-a", "mullo", 16,
759 { 0, { (1<<MACH_M32RX), PIPE_S } }
761 /* mulwhi $src1,$src2 */
763 M32R_INSN_MULWHI, "mulwhi", "mulwhi", 16,
764 { 0, { (1<<MACH_M32R), PIPE_S } }
766 /* mulwhi $src1,$src2,$acc */
768 M32R_INSN_MULWHI_A, "mulwhi-a", "mulwhi", 16,
769 { 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
771 /* mulwlo $src1,$src2 */
773 M32R_INSN_MULWLO, "mulwlo", "mulwlo", 16,
774 { 0, { (1<<MACH_M32R), PIPE_S } }
776 /* mulwlo $src1,$src2,$acc */
778 M32R_INSN_MULWLO_A, "mulwlo-a", "mulwlo", 16,
779 { 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
781 /* mv $dr,$sr */
783 M32R_INSN_MV, "mv", "mv", 16,
784 { 0, { (1<<MACH_BASE), PIPE_OS } }
786 /* mvfachi $dr */
788 M32R_INSN_MVFACHI, "mvfachi", "mvfachi", 16,
789 { 0, { (1<<MACH_M32R), PIPE_S } }
791 /* mvfachi $dr,$accs */
793 M32R_INSN_MVFACHI_A, "mvfachi-a", "mvfachi", 16,
794 { 0, { (1<<MACH_M32RX), PIPE_S } }
796 /* mvfaclo $dr */
798 M32R_INSN_MVFACLO, "mvfaclo", "mvfaclo", 16,
799 { 0, { (1<<MACH_M32R), PIPE_S } }
801 /* mvfaclo $dr,$accs */
803 M32R_INSN_MVFACLO_A, "mvfaclo-a", "mvfaclo", 16,
804 { 0, { (1<<MACH_M32RX), PIPE_S } }
806 /* mvfacmi $dr */
808 M32R_INSN_MVFACMI, "mvfacmi", "mvfacmi", 16,
809 { 0, { (1<<MACH_M32R), PIPE_S } }
811 /* mvfacmi $dr,$accs */
813 M32R_INSN_MVFACMI_A, "mvfacmi-a", "mvfacmi", 16,
814 { 0, { (1<<MACH_M32RX), PIPE_S } }
816 /* mvfc $dr,$scr */
818 M32R_INSN_MVFC, "mvfc", "mvfc", 16,
819 { 0, { (1<<MACH_BASE), PIPE_O } }
821 /* mvtachi $src1 */
823 M32R_INSN_MVTACHI, "mvtachi", "mvtachi", 16,
824 { 0, { (1<<MACH_M32R), PIPE_S } }
826 /* mvtachi $src1,$accs */
828 M32R_INSN_MVTACHI_A, "mvtachi-a", "mvtachi", 16,
829 { 0, { (1<<MACH_M32RX), PIPE_S } }
831 /* mvtaclo $src1 */
833 M32R_INSN_MVTACLO, "mvtaclo", "mvtaclo", 16,
834 { 0, { (1<<MACH_M32R), PIPE_S } }
836 /* mvtaclo $src1,$accs */
838 M32R_INSN_MVTACLO_A, "mvtaclo-a", "mvtaclo", 16,
839 { 0, { (1<<MACH_M32RX), PIPE_S } }
841 /* mvtc $sr,$dcr */
843 M32R_INSN_MVTC, "mvtc", "mvtc", 16,
844 { 0, { (1<<MACH_BASE), PIPE_O } }
846 /* neg $dr,$sr */
848 M32R_INSN_NEG, "neg", "neg", 16,
849 { 0, { (1<<MACH_BASE), PIPE_OS } }
851 /* nop */
853 M32R_INSN_NOP, "nop", "nop", 16,
854 { 0, { (1<<MACH_BASE), PIPE_OS } }
856 /* not $dr,$sr */
858 M32R_INSN_NOT, "not", "not", 16,
859 { 0, { (1<<MACH_BASE), PIPE_OS } }
861 /* rac */
863 M32R_INSN_RAC, "rac", "rac", 16,
864 { 0, { (1<<MACH_M32R), PIPE_S } }
866 /* rac $accd,$accs,$imm1 */
868 M32R_INSN_RAC_DSI, "rac-dsi", "rac", 16,
869 { 0, { (1<<MACH_M32RX), PIPE_S } }
871 /* rach */
873 M32R_INSN_RACH, "rach", "rach", 16,
874 { 0, { (1<<MACH_M32R), PIPE_S } }
876 /* rach $accd,$accs,$imm1 */
878 M32R_INSN_RACH_DSI, "rach-dsi", "rach", 16,
879 { 0, { (1<<MACH_M32RX), PIPE_S } }
881 /* rte */
883 M32R_INSN_RTE, "rte", "rte", 16,
884 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
886 /* seth $dr,$hash$hi16 */
888 M32R_INSN_SETH, "seth", "seth", 32,
889 { 0, { (1<<MACH_BASE), PIPE_NONE } }
891 /* sll $dr,$sr */
893 M32R_INSN_SLL, "sll", "sll", 16,
894 { 0, { (1<<MACH_BASE), PIPE_O } }
896 /* sll3 $dr,$sr,$simm16 */
898 M32R_INSN_SLL3, "sll3", "sll3", 32,
899 { 0, { (1<<MACH_BASE), PIPE_NONE } }
901 /* slli $dr,$uimm5 */
903 M32R_INSN_SLLI, "slli", "slli", 16,
904 { 0, { (1<<MACH_BASE), PIPE_O } }
906 /* sra $dr,$sr */
908 M32R_INSN_SRA, "sra", "sra", 16,
909 { 0, { (1<<MACH_BASE), PIPE_O } }
911 /* sra3 $dr,$sr,$simm16 */
913 M32R_INSN_SRA3, "sra3", "sra3", 32,
914 { 0, { (1<<MACH_BASE), PIPE_NONE } }
916 /* srai $dr,$uimm5 */
918 M32R_INSN_SRAI, "srai", "srai", 16,
919 { 0, { (1<<MACH_BASE), PIPE_O } }
921 /* srl $dr,$sr */
923 M32R_INSN_SRL, "srl", "srl", 16,
924 { 0, { (1<<MACH_BASE), PIPE_O } }
926 /* srl3 $dr,$sr,$simm16 */
928 M32R_INSN_SRL3, "srl3", "srl3", 32,
929 { 0, { (1<<MACH_BASE), PIPE_NONE } }
931 /* srli $dr,$uimm5 */
933 M32R_INSN_SRLI, "srli", "srli", 16,
934 { 0, { (1<<MACH_BASE), PIPE_O } }
936 /* st $src1,@$src2 */
938 M32R_INSN_ST, "st", "st", 16,
939 { 0, { (1<<MACH_BASE), PIPE_O } }
941 /* st $src1,@($slo16,$src2) */
943 M32R_INSN_ST_D, "st-d", "st", 32,
944 { 0, { (1<<MACH_BASE), PIPE_NONE } }
946 /* stb $src1,@$src2 */
948 M32R_INSN_STB, "stb", "stb", 16,
949 { 0, { (1<<MACH_BASE), PIPE_O } }
951 /* stb $src1,@($slo16,$src2) */
953 M32R_INSN_STB_D, "stb-d", "stb", 32,
954 { 0, { (1<<MACH_BASE), PIPE_NONE } }
956 /* sth $src1,@$src2 */
958 M32R_INSN_STH, "sth", "sth", 16,
959 { 0, { (1<<MACH_BASE), PIPE_O } }
961 /* sth $src1,@($slo16,$src2) */
963 M32R_INSN_STH_D, "sth-d", "sth", 32,
964 { 0, { (1<<MACH_BASE), PIPE_NONE } }
966 /* st $src1,@+$src2 */
968 M32R_INSN_ST_PLUS, "st-plus", "st", 16,
969 { 0, { (1<<MACH_BASE), PIPE_O } }
971 /* st $src1,@-$src2 */
973 M32R_INSN_ST_MINUS, "st-minus", "st", 16,
974 { 0, { (1<<MACH_BASE), PIPE_O } }
976 /* sub $dr,$sr */
978 M32R_INSN_SUB, "sub", "sub", 16,
979 { 0, { (1<<MACH_BASE), PIPE_OS } }
981 /* subv $dr,$sr */
983 M32R_INSN_SUBV, "subv", "subv", 16,
984 { 0, { (1<<MACH_BASE), PIPE_OS } }
986 /* subx $dr,$sr */
988 M32R_INSN_SUBX, "subx", "subx", 16,
989 { 0, { (1<<MACH_BASE), PIPE_OS } }
991 /* trap $uimm4 */
993 M32R_INSN_TRAP, "trap", "trap", 16,
994 { 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
996 /* unlock $src1,@$src2 */
998 M32R_INSN_UNLOCK, "unlock", "unlock", 16,
999 { 0, { (1<<MACH_BASE), PIPE_O } }
1001 /* satb $dr,$sr */
1003 M32R_INSN_SATB, "satb", "satb", 32,
1004 { 0, { (1<<MACH_M32RX), PIPE_NONE } }
1006 /* sath $dr,$sr */
1008 M32R_INSN_SATH, "sath", "sath", 32,
1009 { 0, { (1<<MACH_M32RX), PIPE_NONE } }
1011 /* sat $dr,$sr */
1013 M32R_INSN_SAT, "sat", "sat", 32,
1014 { 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_NONE } }
1016 /* pcmpbz $src2 */
1018 M32R_INSN_PCMPBZ, "pcmpbz", "pcmpbz", 16,
1019 { 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_OS } }
1021 /* sadd */
1023 M32R_INSN_SADD, "sadd", "sadd", 16,
1024 { 0, { (1<<MACH_M32RX), PIPE_S } }
1026 /* macwu1 $src1,$src2 */
1028 M32R_INSN_MACWU1, "macwu1", "macwu1", 16,
1029 { 0, { (1<<MACH_M32RX), PIPE_S } }
1031 /* msblo $src1,$src2 */
1033 M32R_INSN_MSBLO, "msblo", "msblo", 16,
1034 { 0, { (1<<MACH_M32RX), PIPE_S } }
1036 /* mulwu1 $src1,$src2 */
1038 M32R_INSN_MULWU1, "mulwu1", "mulwu1", 16,
1039 { 0, { (1<<MACH_M32RX), PIPE_S } }
1041 /* maclh1 $src1,$src2 */
1043 M32R_INSN_MACLH1, "maclh1", "maclh1", 16,
1044 { 0, { (1<<MACH_M32RX), PIPE_S } }
1046 /* sc */
1048 M32R_INSN_SC, "sc", "sc", 16,
1049 { 0|A(SPECIAL)|A(SKIP_CTI), { (1<<MACH_M32RX), PIPE_O } }
1051 /* snc */
1053 M32R_INSN_SNC, "snc", "snc", 16,
1054 { 0|A(SPECIAL)|A(SKIP_CTI), { (1<<MACH_M32RX), PIPE_O } }
1058 #undef A
1059 #undef MNEM
1060 #undef OP
1062 /* Initialize anything needed to be done once, before any cpu_open call. */
1064 static void
1065 init_tables ()
1069 /* Subroutine of m32r_cgen_cpu_open to look up a mach via its bfd name. */
1071 static const CGEN_MACH *
1072 lookup_mach_via_bfd_name (table, name)
1073 const CGEN_MACH *table;
1074 const char *name;
1076 while (table->name)
1078 if (strcmp (name, table->bfd_name) == 0)
1079 return table;
1080 ++table;
1082 abort ();
1085 /* Subroutine of m32r_cgen_cpu_open to build the hardware table. */
1087 static void
1088 build_hw_table (cd)
1089 CGEN_CPU_TABLE *cd;
1091 int i;
1092 int machs = cd->machs;
1093 const CGEN_HW_ENTRY *init = & m32r_cgen_hw_table[0];
1094 /* MAX_HW is only an upper bound on the number of selected entries.
1095 However each entry is indexed by it's enum so there can be holes in
1096 the table. */
1097 const CGEN_HW_ENTRY **selected =
1098 (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
1100 cd->hw_table.init_entries = init;
1101 cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
1102 memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
1103 /* ??? For now we just use machs to determine which ones we want. */
1104 for (i = 0; init[i].name != NULL; ++i)
1105 if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
1106 & machs)
1107 selected[init[i].type] = &init[i];
1108 cd->hw_table.entries = selected;
1109 cd->hw_table.num_entries = MAX_HW;
1112 /* Subroutine of m32r_cgen_cpu_open to build the hardware table. */
1114 static void
1115 build_ifield_table (cd)
1116 CGEN_CPU_TABLE *cd;
1118 cd->ifld_table = & m32r_cgen_ifld_table[0];
1121 /* Subroutine of m32r_cgen_cpu_open to build the hardware table. */
1123 static void
1124 build_operand_table (cd)
1125 CGEN_CPU_TABLE *cd;
1127 int i;
1128 int machs = cd->machs;
1129 const CGEN_OPERAND *init = & m32r_cgen_operand_table[0];
1130 /* MAX_OPERANDS is only an upper bound on the number of selected entries.
1131 However each entry is indexed by it's enum so there can be holes in
1132 the table. */
1133 const CGEN_OPERAND **selected =
1134 (const CGEN_OPERAND **) xmalloc (MAX_OPERANDS * sizeof (CGEN_OPERAND *));
1136 cd->operand_table.init_entries = init;
1137 cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
1138 memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
1139 /* ??? For now we just use mach to determine which ones we want. */
1140 for (i = 0; init[i].name != NULL; ++i)
1141 if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
1142 & machs)
1143 selected[init[i].type] = &init[i];
1144 cd->operand_table.entries = selected;
1145 cd->operand_table.num_entries = MAX_OPERANDS;
1148 /* Subroutine of m32r_cgen_cpu_open to build the hardware table.
1149 ??? This could leave out insns not supported by the specified mach/isa,
1150 but that would cause errors like "foo only supported by bar" to become
1151 "unknown insn", so for now we include all insns and require the app to
1152 do the checking later.
1153 ??? On the other hand, parsing of such insns may require their hardware or
1154 operand elements to be in the table [which they mightn't be]. */
1156 static void
1157 build_insn_table (cd)
1158 CGEN_CPU_TABLE *cd;
1160 int i;
1161 const CGEN_IBASE *ib = & m32r_cgen_insn_table[0];
1162 CGEN_INSN *insns = (CGEN_INSN *) xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
1164 memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
1165 for (i = 0; i < MAX_INSNS; ++i)
1166 insns[i].base = &ib[i];
1167 cd->insn_table.init_entries = insns;
1168 cd->insn_table.entry_size = sizeof (CGEN_IBASE);
1169 cd->insn_table.num_init_entries = MAX_INSNS;
1172 /* Subroutine of m32r_cgen_cpu_open to rebuild the tables. */
1174 static void
1175 m32r_cgen_rebuild_tables (cd)
1176 CGEN_CPU_TABLE *cd;
1178 int i,n_isas,n_machs;
1179 unsigned int isas = cd->isas;
1180 unsigned int machs = cd->machs;
1182 cd->int_insn_p = CGEN_INT_INSN_P;
1184 /* Data derived from the isa spec. */
1185 #define UNSET (CGEN_SIZE_UNKNOWN + 1)
1186 cd->default_insn_bitsize = UNSET;
1187 cd->base_insn_bitsize = UNSET;
1188 cd->min_insn_bitsize = 65535; /* some ridiculously big number */
1189 cd->max_insn_bitsize = 0;
1190 for (i = 0; i < MAX_ISAS; ++i)
1191 if (((1 << i) & isas) != 0)
1193 const CGEN_ISA *isa = & m32r_cgen_isa_table[i];
1195 /* Default insn sizes of all selected isas must be equal or we set
1196 the result to 0, meaning "unknown". */
1197 if (cd->default_insn_bitsize == UNSET)
1198 cd->default_insn_bitsize = isa->default_insn_bitsize;
1199 else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
1200 ; /* this is ok */
1201 else
1202 cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
1204 /* Base insn sizes of all selected isas must be equal or we set
1205 the result to 0, meaning "unknown". */
1206 if (cd->base_insn_bitsize == UNSET)
1207 cd->base_insn_bitsize = isa->base_insn_bitsize;
1208 else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
1209 ; /* this is ok */
1210 else
1211 cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
1213 /* Set min,max insn sizes. */
1214 if (isa->min_insn_bitsize < cd->min_insn_bitsize)
1215 cd->min_insn_bitsize = isa->min_insn_bitsize;
1216 if (isa->max_insn_bitsize > cd->max_insn_bitsize)
1217 cd->max_insn_bitsize = isa->max_insn_bitsize;
1219 ++n_isas;
1222 /* Data derived from the mach spec. */
1223 for (i = 0; i < MAX_MACHS; ++i)
1224 if (((1 << i) & machs) != 0)
1226 const CGEN_MACH *mach = & m32r_cgen_mach_table[i];
1228 ++n_machs;
1231 /* Determine which hw elements are used by MACH. */
1232 build_hw_table (cd);
1234 /* Build the ifield table. */
1235 build_ifield_table (cd);
1237 /* Determine which operands are used by MACH/ISA. */
1238 build_operand_table (cd);
1240 /* Build the instruction table. */
1241 build_insn_table (cd);
1244 /* Initialize a cpu table and return a descriptor.
1245 It's much like opening a file, and must be the first function called.
1246 The arguments are a set of (type/value) pairs, terminated with
1247 CGEN_CPU_OPEN_END.
1249 Currently supported values:
1250 CGEN_CPU_OPEN_ISAS: bitmap of values in enum isa_attr
1251 CGEN_CPU_OPEN_MACHS: bitmap of values in enum mach_attr
1252 CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
1253 CGEN_CPU_OPEN_ENDIAN: specify endian choice
1254 CGEN_CPU_OPEN_END: terminates arguments
1256 ??? Simultaneous multiple isas might not make sense, but it's not (yet)
1257 precluded.
1259 ??? We only support ISO C stdargs here, not K&R.
1260 Laziness, plus experiment to see if anything requires K&R - eventually
1261 K&R will no longer be supported - e.g. GDB is currently trying this. */
1263 CGEN_CPU_DESC
1264 m32r_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
1266 CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
1267 static int init_p;
1268 unsigned int isas = 0; /* 0 = "unspecified" */
1269 unsigned int machs = 0; /* 0 = "unspecified" */
1270 enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
1271 va_list ap;
1273 if (! init_p)
1275 init_tables ();
1276 init_p = 1;
1279 memset (cd, 0, sizeof (*cd));
1281 va_start (ap, arg_type);
1282 while (arg_type != CGEN_CPU_OPEN_END)
1284 switch (arg_type)
1286 case CGEN_CPU_OPEN_ISAS :
1287 isas = va_arg (ap, unsigned int);
1288 break;
1289 case CGEN_CPU_OPEN_MACHS :
1290 machs = va_arg (ap, unsigned int);
1291 break;
1292 case CGEN_CPU_OPEN_BFDMACH :
1294 const char *name = va_arg (ap, const char *);
1295 const CGEN_MACH *mach =
1296 lookup_mach_via_bfd_name (m32r_cgen_mach_table, name);
1298 machs |= mach->num << 1;
1299 break;
1301 case CGEN_CPU_OPEN_ENDIAN :
1302 endian = va_arg (ap, enum cgen_endian);
1303 break;
1304 default :
1305 fprintf (stderr, "m32r_cgen_cpu_open: unsupported argument `%d'\n",
1306 arg_type);
1307 abort (); /* ??? return NULL? */
1309 arg_type = va_arg (ap, enum cgen_cpu_open_arg);
1311 va_end (ap);
1313 /* mach unspecified means "all" */
1314 if (machs == 0)
1315 machs = (1 << MAX_MACHS) - 1;
1316 /* base mach is always selected */
1317 machs |= 1;
1318 /* isa unspecified means "all" */
1319 if (isas == 0)
1320 isas = (1 << MAX_ISAS) - 1;
1321 if (endian == CGEN_ENDIAN_UNKNOWN)
1323 /* ??? If target has only one, could have a default. */
1324 fprintf (stderr, "m32r_cgen_cpu_open: no endianness specified\n");
1325 abort ();
1328 cd->isas = isas;
1329 cd->machs = machs;
1330 cd->endian = endian;
1331 /* FIXME: for the sparc case we can determine insn-endianness statically.
1332 The worry here is where both data and insn endian can be independently
1333 chosen, in which case this function will need another argument.
1334 Actually, will want to allow for more arguments in the future anyway. */
1335 cd->insn_endian = endian;
1337 /* Table (re)builder. */
1338 cd->rebuild_tables = m32r_cgen_rebuild_tables;
1339 m32r_cgen_rebuild_tables (cd);
1341 /* Initialise flags. */
1342 cd->signed_overflow_ok_p = 0;
1344 return (CGEN_CPU_DESC) cd;
1347 /* Cover fn to m32r_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
1348 MACH_NAME is the bfd name of the mach. */
1350 CGEN_CPU_DESC
1351 m32r_cgen_cpu_open_1 (mach_name, endian)
1352 const char *mach_name;
1353 enum cgen_endian endian;
1355 return m32r_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
1356 CGEN_CPU_OPEN_ENDIAN, endian,
1357 CGEN_CPU_OPEN_END);
1360 /* Close a cpu table.
1361 ??? This can live in a machine independent file, but there's currently
1362 no place to put this file (there's no libcgen). libopcodes is the wrong
1363 place as some simulator ports use this but they don't use libopcodes. */
1365 void
1366 m32r_cgen_cpu_close (cd)
1367 CGEN_CPU_DESC cd;
1369 if (cd->insn_table.init_entries)
1370 free ((CGEN_INSN *) cd->insn_table.init_entries);
1371 if (cd->hw_table.entries)
1372 free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
1373 free (cd);