1 /* tc-ia64.c -- Assembler for the HP/Intel IA-64 architecture.
2 Copyright (C) 1998, 1999, 2000, 2001 Free Software Foundation.
3 Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
35 - labels are wrong if automatic alignment is introduced
36 (e.g., checkout the second real10 definition in test-data.s)
38 <reg>.safe_across_calls and any other DV-related directives I don't
39 have documentation for.
40 verify mod-sched-brs reads/writes are checked/marked (and other
46 #include "dwarf2dbg.h"
49 #include "opcode/ia64.h"
53 #define NELEMS(a) ((int) (sizeof (a)/sizeof ((a)[0])))
54 #define MIN(a,b) ((a) < (b) ? (a) : (b))
57 #define PREV_SLOT md.slot[(md.curr_slot + NUM_SLOTS - 1) % NUM_SLOTS]
58 #define CURR_SLOT md.slot[md.curr_slot]
60 #define O_pseudo_fixup (O_max + 1)
64 SPECIAL_SECTION_BSS
= 0,
66 SPECIAL_SECTION_SDATA
,
67 SPECIAL_SECTION_RODATA
,
68 SPECIAL_SECTION_COMMENT
,
69 SPECIAL_SECTION_UNWIND
,
70 SPECIAL_SECTION_UNWIND_INFO
83 FUNC_LT_FPTR_RELATIVE
,
89 REG_FR
= (REG_GR
+ 128),
90 REG_AR
= (REG_FR
+ 128),
91 REG_CR
= (REG_AR
+ 128),
92 REG_P
= (REG_CR
+ 128),
93 REG_BR
= (REG_P
+ 64),
94 REG_IP
= (REG_BR
+ 8),
101 /* The following are pseudo-registers for use by gas only. */
113 /* The following pseudo-registers are used for unwind directives only: */
121 DYNREG_GR
= 0, /* dynamic general purpose register */
122 DYNREG_FR
, /* dynamic floating point register */
123 DYNREG_PR
, /* dynamic predicate register */
127 /* On the ia64, we can't know the address of a text label until the
128 instructions are packed into a bundle. To handle this, we keep
129 track of the list of labels that appear in front of each
133 struct label_fix
*next
;
137 extern int target_big_endian
;
139 /* Characters which always start a comment. */
140 const char comment_chars
[] = "";
142 /* Characters which start a comment at the beginning of a line. */
143 const char line_comment_chars
[] = "#";
145 /* Characters which may be used to separate multiple commands on a
147 const char line_separator_chars
[] = ";";
149 /* Characters which are used to indicate an exponent in a floating
151 const char EXP_CHARS
[] = "eE";
153 /* Characters which mean that a number is a floating point constant,
155 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
157 /* ia64-specific option processing: */
159 const char *md_shortopts
= "m:N:x::";
161 struct option md_longopts
[] =
163 #define OPTION_MCONSTANT_GP (OPTION_MD_BASE + 1)
164 {"mconstant-gp", no_argument
, NULL
, OPTION_MCONSTANT_GP
},
165 #define OPTION_MAUTO_PIC (OPTION_MD_BASE + 2)
166 {"mauto-pic", no_argument
, NULL
, OPTION_MAUTO_PIC
}
169 size_t md_longopts_size
= sizeof (md_longopts
);
173 struct hash_control
*pseudo_hash
; /* pseudo opcode hash table */
174 struct hash_control
*reg_hash
; /* register name hash table */
175 struct hash_control
*dynreg_hash
; /* dynamic register hash table */
176 struct hash_control
*const_hash
; /* constant hash table */
177 struct hash_control
*entry_hash
; /* code entry hint hash table */
179 symbolS
*regsym
[REG_NUM
];
181 /* If X_op is != O_absent, the registername for the instruction's
182 qualifying predicate. If NULL, p0 is assumed for instructions
183 that are predicatable. */
190 explicit_mode
: 1, /* which mode we're in */
191 default_explicit_mode
: 1, /* which mode is the default */
192 mode_explicitly_set
: 1, /* was the current mode explicitly set? */
195 /* Each bundle consists of up to three instructions. We keep
196 track of four most recent instructions so we can correctly set
197 the end_of_insn_group for the last instruction in a bundle. */
199 int num_slots_in_use
;
203 end_of_insn_group
: 1,
204 manual_bundling_on
: 1,
205 manual_bundling_off
: 1;
206 signed char user_template
; /* user-selected template, if any */
207 unsigned char qp_regno
; /* qualifying predicate */
208 /* This duplicates a good fraction of "struct fix" but we
209 can't use a "struct fix" instead since we can't call
210 fix_new_exp() until we know the address of the instruction. */
214 bfd_reloc_code_real_type code
;
215 enum ia64_opnd opnd
; /* type of operand in need of fix */
216 unsigned int is_pcrel
: 1; /* is operand pc-relative? */
217 expressionS expr
; /* the value to be inserted */
219 fixup
[2]; /* at most two fixups per insn */
220 struct ia64_opcode
*idesc
;
221 struct label_fix
*label_fixups
;
222 struct label_fix
*tag_fixups
;
223 struct unw_rec_list
*unwind_record
; /* Unwind directive. */
226 unsigned int src_line
;
227 struct dwarf2_line_info debug_line
;
235 struct dynreg
*next
; /* next dynamic register */
237 unsigned short base
; /* the base register number */
238 unsigned short num_regs
; /* # of registers in this set */
240 *dynreg
[DYNREG_NUM_TYPES
], in
, loc
, out
, rot
;
242 flagword flags
; /* ELF-header flags */
245 unsigned hint
:1; /* is this hint currently valid? */
246 bfd_vma offset
; /* mem.offset offset */
247 bfd_vma base
; /* mem.offset base */
250 int path
; /* number of alt. entry points seen */
251 const char **entry_labels
; /* labels of all alternate paths in
252 the current DV-checking block. */
253 int maxpaths
; /* size currently allocated for
255 /* Support for hardware errata workarounds. */
257 /* Record data about the last three insn groups. */
260 /* B-step workaround.
261 For each predicate register, this is set if the corresponding insn
262 group conditionally sets this register with one of the affected
265 /* B-step workaround.
266 For each general register, this is set if the corresponding insn
267 a) is conditional one one of the predicate registers for which
268 P_REG_SET is 1 in the corresponding entry of the previous group,
269 b) sets this general register with one of the affected
271 int g_reg_set_conditionally
[128];
277 /* application registers: */
283 #define AR_BSPSTORE 18
298 {"ar.k0", 0}, {"ar.k1", 1}, {"ar.k2", 2}, {"ar.k3", 3},
299 {"ar.k4", 4}, {"ar.k5", 5}, {"ar.k6", 6}, {"ar.k7", 7},
300 {"ar.rsc", 16}, {"ar.bsp", 17},
301 {"ar.bspstore", 18}, {"ar.rnat", 19},
302 {"ar.fcr", 21}, {"ar.eflag", 24},
303 {"ar.csd", 25}, {"ar.ssd", 26},
304 {"ar.cflg", 27}, {"ar.fsr", 28},
305 {"ar.fir", 29}, {"ar.fdr", 30},
306 {"ar.ccv", 32}, {"ar.unat", 36},
307 {"ar.fpsr", 40}, {"ar.itc", 44},
308 {"ar.pfs", 64}, {"ar.lc", 65},
329 /* control registers: */
371 static const struct const_desc
378 /* PSR constant masks: */
381 {"psr.be", ((valueT
) 1) << 1},
382 {"psr.up", ((valueT
) 1) << 2},
383 {"psr.ac", ((valueT
) 1) << 3},
384 {"psr.mfl", ((valueT
) 1) << 4},
385 {"psr.mfh", ((valueT
) 1) << 5},
387 {"psr.ic", ((valueT
) 1) << 13},
388 {"psr.i", ((valueT
) 1) << 14},
389 {"psr.pk", ((valueT
) 1) << 15},
391 {"psr.dt", ((valueT
) 1) << 17},
392 {"psr.dfl", ((valueT
) 1) << 18},
393 {"psr.dfh", ((valueT
) 1) << 19},
394 {"psr.sp", ((valueT
) 1) << 20},
395 {"psr.pp", ((valueT
) 1) << 21},
396 {"psr.di", ((valueT
) 1) << 22},
397 {"psr.si", ((valueT
) 1) << 23},
398 {"psr.db", ((valueT
) 1) << 24},
399 {"psr.lp", ((valueT
) 1) << 25},
400 {"psr.tb", ((valueT
) 1) << 26},
401 {"psr.rt", ((valueT
) 1) << 27},
402 /* 28-31: reserved */
403 /* 32-33: cpl (current privilege level) */
404 {"psr.is", ((valueT
) 1) << 34},
405 {"psr.mc", ((valueT
) 1) << 35},
406 {"psr.it", ((valueT
) 1) << 36},
407 {"psr.id", ((valueT
) 1) << 37},
408 {"psr.da", ((valueT
) 1) << 38},
409 {"psr.dd", ((valueT
) 1) << 39},
410 {"psr.ss", ((valueT
) 1) << 40},
411 /* 41-42: ri (restart instruction) */
412 {"psr.ed", ((valueT
) 1) << 43},
413 {"psr.bn", ((valueT
) 1) << 44},
416 /* indirect register-sets/memory: */
425 { "CPUID", IND_CPUID
},
426 { "cpuid", IND_CPUID
},
438 /* Pseudo functions used to indicate relocation types (these functions
439 start with an at sign (@). */
461 /* reloc pseudo functions (these must come first!): */
462 { "fptr", PSEUDO_FUNC_RELOC
, { 0 } },
463 { "gprel", PSEUDO_FUNC_RELOC
, { 0 } },
464 { "ltoff", PSEUDO_FUNC_RELOC
, { 0 } },
465 { "pcrel", PSEUDO_FUNC_RELOC
, { 0 } },
466 { "pltoff", PSEUDO_FUNC_RELOC
, { 0 } },
467 { "secrel", PSEUDO_FUNC_RELOC
, { 0 } },
468 { "segrel", PSEUDO_FUNC_RELOC
, { 0 } },
469 { "ltv", PSEUDO_FUNC_RELOC
, { 0 } },
470 { "", 0, { 0 } }, /* placeholder for FUNC_LT_FPTR_RELATIVE */
472 /* mbtype4 constants: */
473 { "alt", PSEUDO_FUNC_CONST
, { 0xa } },
474 { "brcst", PSEUDO_FUNC_CONST
, { 0x0 } },
475 { "mix", PSEUDO_FUNC_CONST
, { 0x8 } },
476 { "rev", PSEUDO_FUNC_CONST
, { 0xb } },
477 { "shuf", PSEUDO_FUNC_CONST
, { 0x9 } },
479 /* fclass constants: */
480 { "nat", PSEUDO_FUNC_CONST
, { 0x100 } },
481 { "qnan", PSEUDO_FUNC_CONST
, { 0x080 } },
482 { "snan", PSEUDO_FUNC_CONST
, { 0x040 } },
483 { "pos", PSEUDO_FUNC_CONST
, { 0x001 } },
484 { "neg", PSEUDO_FUNC_CONST
, { 0x002 } },
485 { "zero", PSEUDO_FUNC_CONST
, { 0x004 } },
486 { "unorm", PSEUDO_FUNC_CONST
, { 0x008 } },
487 { "norm", PSEUDO_FUNC_CONST
, { 0x010 } },
488 { "inf", PSEUDO_FUNC_CONST
, { 0x020 } },
490 { "natval", PSEUDO_FUNC_CONST
, { 0x100 } }, /* old usage */
492 /* unwind-related constants: */
493 { "svr4", PSEUDO_FUNC_CONST
, { 0 } },
494 { "hpux", PSEUDO_FUNC_CONST
, { 1 } },
495 { "nt", PSEUDO_FUNC_CONST
, { 2 } },
497 /* unwind-related registers: */
498 { "priunat",PSEUDO_FUNC_REG
, { REG_PRIUNAT
} }
501 /* 41-bit nop opcodes (one per unit): */
502 static const bfd_vma nop
[IA64_NUM_UNITS
] =
504 0x0000000000LL
, /* NIL => break 0 */
505 0x0008000000LL
, /* I-unit nop */
506 0x0008000000LL
, /* M-unit nop */
507 0x4000000000LL
, /* B-unit nop */
508 0x0008000000LL
, /* F-unit nop */
509 0x0008000000LL
, /* L-"unit" nop */
510 0x0008000000LL
, /* X-unit nop */
513 /* Can't be `const' as it's passed to input routines (which have the
514 habit of setting temporary sentinels. */
515 static char special_section_name
[][20] =
517 {".bss"}, {".sbss"}, {".sdata"}, {".rodata"}, {".comment"},
518 {".IA_64.unwind"}, {".IA_64.unwind_info"}
521 /* The best template for a particular sequence of up to three
523 #define N IA64_NUM_TYPES
524 static unsigned char best_template
[N
][N
][N
];
527 /* Resource dependencies currently in effect */
529 int depind
; /* dependency index */
530 const struct ia64_dependency
*dependency
; /* actual dependency */
531 unsigned specific
:1, /* is this a specific bit/regno? */
532 link_to_qp_branch
:1; /* will a branch on the same QP clear it?*/
533 int index
; /* specific regno/bit within dependency */
534 int note
; /* optional qualifying note (0 if none) */
538 int insn_srlz
; /* current insn serialization state */
539 int data_srlz
; /* current data serialization state */
540 int qp_regno
; /* qualifying predicate for this usage */
541 char *file
; /* what file marked this dependency */
542 unsigned int line
; /* what line marked this dependency */
543 struct mem_offset mem_offset
; /* optional memory offset hint */
544 enum { CMP_NONE
, CMP_OR
, CMP_AND
} cmp_type
; /* OR or AND compare? */
545 int path
; /* corresponding code entry index */
547 static int regdepslen
= 0;
548 static int regdepstotlen
= 0;
549 static const char *dv_mode
[] = { "RAW", "WAW", "WAR" };
550 static const char *dv_sem
[] = { "none", "implied", "impliedf",
551 "data", "instr", "specific", "stop", "other" };
552 static const char *dv_cmp_type
[] = { "none", "OR", "AND" };
554 /* Current state of PR mutexation */
555 static struct qpmutex
{
558 } *qp_mutexes
= NULL
; /* QP mutex bitmasks */
559 static int qp_mutexeslen
= 0;
560 static int qp_mutexestotlen
= 0;
561 static valueT qp_safe_across_calls
= 0;
563 /* Current state of PR implications */
564 static struct qp_imply
{
567 unsigned p2_branched
:1;
569 } *qp_implies
= NULL
;
570 static int qp_implieslen
= 0;
571 static int qp_impliestotlen
= 0;
573 /* Keep track of static GR values so that indirect register usage can
574 sometimes be tracked. */
579 } gr_values
[128] = {{ 1, 0, 0 }};
581 /* These are the routines required to output the various types of
584 /* A slot_number is a frag address plus the slot index (0-2). We use the
585 frag address here so that if there is a section switch in the middle of
586 a function, then instructions emitted to a different section are not
587 counted. Since there may be more than one frag for a function, this
588 means we also need to keep track of which frag this address belongs to
589 so we can compute inter-frag distances. This also nicely solves the
590 problem with nops emitted for align directives, which can't easily be
591 counted, but can easily be derived from frag sizes. */
593 typedef struct unw_rec_list
{
595 unsigned long slot_number
;
597 struct unw_rec_list
*next
;
600 #define SLOT_NUM_NOT_SET (unsigned)-1
604 unsigned long next_slot_number
;
605 fragS
*next_slot_frag
;
607 /* Maintain a list of unwind entries for the current function. */
611 /* Any unwind entires that should be attached to the current slot
612 that an insn is being constructed for. */
613 unw_rec_list
*current_entry
;
615 /* These are used to create the unwind table entry for this function. */
618 symbolS
*info
; /* pointer to unwind info */
619 symbolS
*personality_routine
;
621 subsegT saved_text_subseg
;
622 unsigned int force_unwind_entry
: 1; /* force generation of unwind entry? */
624 /* TRUE if processing unwind directives in a prologue region. */
629 typedef void (*vbyte_func
) PARAMS ((int, char *, char *));
631 /* Forward delarations: */
632 static int ar_is_in_integer_unit
PARAMS ((int regnum
));
633 static void set_section
PARAMS ((char *name
));
634 static unsigned int set_regstack
PARAMS ((unsigned int, unsigned int,
635 unsigned int, unsigned int));
636 static void dot_radix
PARAMS ((int));
637 static void dot_special_section
PARAMS ((int));
638 static void dot_proc
PARAMS ((int));
639 static void dot_fframe
PARAMS ((int));
640 static void dot_vframe
PARAMS ((int));
641 static void dot_vframesp
PARAMS ((int));
642 static void dot_vframepsp
PARAMS ((int));
643 static void dot_save
PARAMS ((int));
644 static void dot_restore
PARAMS ((int));
645 static void dot_restorereg
PARAMS ((int));
646 static void dot_restorereg_p
PARAMS ((int));
647 static void dot_handlerdata
PARAMS ((int));
648 static void dot_unwentry
PARAMS ((int));
649 static void dot_altrp
PARAMS ((int));
650 static void dot_savemem
PARAMS ((int));
651 static void dot_saveg
PARAMS ((int));
652 static void dot_savef
PARAMS ((int));
653 static void dot_saveb
PARAMS ((int));
654 static void dot_savegf
PARAMS ((int));
655 static void dot_spill
PARAMS ((int));
656 static void dot_spillreg
PARAMS ((int));
657 static void dot_spillmem
PARAMS ((int));
658 static void dot_spillreg_p
PARAMS ((int));
659 static void dot_spillmem_p
PARAMS ((int));
660 static void dot_label_state
PARAMS ((int));
661 static void dot_copy_state
PARAMS ((int));
662 static void dot_unwabi
PARAMS ((int));
663 static void dot_personality
PARAMS ((int));
664 static void dot_body
PARAMS ((int));
665 static void dot_prologue
PARAMS ((int));
666 static void dot_endp
PARAMS ((int));
667 static void dot_template
PARAMS ((int));
668 static void dot_regstk
PARAMS ((int));
669 static void dot_rot
PARAMS ((int));
670 static void dot_byteorder
PARAMS ((int));
671 static void dot_psr
PARAMS ((int));
672 static void dot_alias
PARAMS ((int));
673 static void dot_ln
PARAMS ((int));
674 static char *parse_section_name
PARAMS ((void));
675 static void dot_xdata
PARAMS ((int));
676 static void stmt_float_cons
PARAMS ((int));
677 static void stmt_cons_ua
PARAMS ((int));
678 static void dot_xfloat_cons
PARAMS ((int));
679 static void dot_xstringer
PARAMS ((int));
680 static void dot_xdata_ua
PARAMS ((int));
681 static void dot_xfloat_cons_ua
PARAMS ((int));
682 static void print_prmask
PARAMS ((valueT mask
));
683 static void dot_pred_rel
PARAMS ((int));
684 static void dot_reg_val
PARAMS ((int));
685 static void dot_dv_mode
PARAMS ((int));
686 static void dot_entry
PARAMS ((int));
687 static void dot_mem_offset
PARAMS ((int));
688 static void add_unwind_entry
PARAMS((unw_rec_list
*ptr
));
689 static symbolS
*declare_register
PARAMS ((const char *name
, int regnum
));
690 static void declare_register_set
PARAMS ((const char *, int, int));
691 static unsigned int operand_width
PARAMS ((enum ia64_opnd
));
692 static int operand_match
PARAMS ((const struct ia64_opcode
*idesc
,
693 int index
, expressionS
*e
));
694 static int parse_operand
PARAMS ((expressionS
*e
));
695 static struct ia64_opcode
* parse_operands
PARAMS ((struct ia64_opcode
*));
696 static void build_insn
PARAMS ((struct slot
*, bfd_vma
*));
697 static void emit_one_bundle
PARAMS ((void));
698 static void fix_insn
PARAMS ((fixS
*, const struct ia64_operand
*, valueT
));
699 static bfd_reloc_code_real_type ia64_gen_real_reloc_type
PARAMS ((struct symbol
*sym
,
700 bfd_reloc_code_real_type r_type
));
701 static void insn_group_break
PARAMS ((int, int, int));
702 static void mark_resource
PARAMS ((struct ia64_opcode
*, const struct ia64_dependency
*,
703 struct rsrc
*, int depind
, int path
));
704 static void add_qp_mutex
PARAMS((valueT mask
));
705 static void add_qp_imply
PARAMS((int p1
, int p2
));
706 static void clear_qp_branch_flag
PARAMS((valueT mask
));
707 static void clear_qp_mutex
PARAMS((valueT mask
));
708 static void clear_qp_implies
PARAMS((valueT p1_mask
, valueT p2_mask
));
709 static void clear_register_values
PARAMS ((void));
710 static void print_dependency
PARAMS ((const char *action
, int depind
));
711 static void instruction_serialization
PARAMS ((void));
712 static void data_serialization
PARAMS ((void));
713 static void remove_marked_resource
PARAMS ((struct rsrc
*));
714 static int is_conditional_branch
PARAMS ((struct ia64_opcode
*));
715 static int is_taken_branch
PARAMS ((struct ia64_opcode
*));
716 static int is_interruption_or_rfi
PARAMS ((struct ia64_opcode
*));
717 static int depends_on
PARAMS ((int, struct ia64_opcode
*));
718 static int specify_resource
PARAMS ((const struct ia64_dependency
*,
719 struct ia64_opcode
*, int, struct rsrc
[], int, int));
720 static int check_dv
PARAMS((struct ia64_opcode
*idesc
));
721 static void check_dependencies
PARAMS((struct ia64_opcode
*));
722 static void mark_resources
PARAMS((struct ia64_opcode
*));
723 static void update_dependencies
PARAMS((struct ia64_opcode
*));
724 static void note_register_values
PARAMS((struct ia64_opcode
*));
725 static int qp_mutex
PARAMS ((int, int, int));
726 static int resources_match
PARAMS ((struct rsrc
*, struct ia64_opcode
*, int, int, int));
727 static void output_vbyte_mem
PARAMS ((int, char *, char *));
728 static void count_output
PARAMS ((int, char *, char *));
729 static void output_R1_format
PARAMS ((vbyte_func
, unw_record_type
, int));
730 static void output_R2_format
PARAMS ((vbyte_func
, int, int, unsigned long));
731 static void output_R3_format
PARAMS ((vbyte_func
, unw_record_type
, unsigned long));
732 static void output_P1_format
PARAMS ((vbyte_func
, int));
733 static void output_P2_format
PARAMS ((vbyte_func
, int, int));
734 static void output_P3_format
PARAMS ((vbyte_func
, unw_record_type
, int));
735 static void output_P4_format
PARAMS ((vbyte_func
, unsigned char *, unsigned long));
736 static void output_P5_format
PARAMS ((vbyte_func
, int, unsigned long));
737 static void output_P6_format
PARAMS ((vbyte_func
, unw_record_type
, int));
738 static void output_P7_format
PARAMS ((vbyte_func
, unw_record_type
, unsigned long, unsigned long));
739 static void output_P8_format
PARAMS ((vbyte_func
, unw_record_type
, unsigned long));
740 static void output_P9_format
PARAMS ((vbyte_func
, int, int));
741 static void output_P10_format
PARAMS ((vbyte_func
, int, int));
742 static void output_B1_format
PARAMS ((vbyte_func
, unw_record_type
, unsigned long));
743 static void output_B2_format
PARAMS ((vbyte_func
, unsigned long, unsigned long));
744 static void output_B3_format
PARAMS ((vbyte_func
, unsigned long, unsigned long));
745 static void output_B4_format
PARAMS ((vbyte_func
, unw_record_type
, unsigned long));
746 static char format_ab_reg
PARAMS ((int, int));
747 static void output_X1_format
PARAMS ((vbyte_func
, unw_record_type
, int, int, unsigned long,
749 static void output_X2_format
PARAMS ((vbyte_func
, int, int, int, int, int, unsigned long));
750 static void output_X3_format
PARAMS ((vbyte_func
, unw_record_type
, int, int, int, unsigned long,
752 static void output_X4_format
PARAMS ((vbyte_func
, int, int, int, int, int, int, unsigned long));
753 static void free_list_records
PARAMS ((unw_rec_list
*));
754 static unw_rec_list
*output_prologue
PARAMS ((void));
755 static unw_rec_list
*output_prologue_gr
PARAMS ((unsigned int, unsigned int));
756 static unw_rec_list
*output_body
PARAMS ((void));
757 static unw_rec_list
*output_mem_stack_f
PARAMS ((unsigned int));
758 static unw_rec_list
*output_mem_stack_v
PARAMS ((void));
759 static unw_rec_list
*output_psp_gr
PARAMS ((unsigned int));
760 static unw_rec_list
*output_psp_sprel
PARAMS ((unsigned int));
761 static unw_rec_list
*output_rp_when
PARAMS ((void));
762 static unw_rec_list
*output_rp_gr
PARAMS ((unsigned int));
763 static unw_rec_list
*output_rp_br
PARAMS ((unsigned int));
764 static unw_rec_list
*output_rp_psprel
PARAMS ((unsigned int));
765 static unw_rec_list
*output_rp_sprel
PARAMS ((unsigned int));
766 static unw_rec_list
*output_pfs_when
PARAMS ((void));
767 static unw_rec_list
*output_pfs_gr
PARAMS ((unsigned int));
768 static unw_rec_list
*output_pfs_psprel
PARAMS ((unsigned int));
769 static unw_rec_list
*output_pfs_sprel
PARAMS ((unsigned int));
770 static unw_rec_list
*output_preds_when
PARAMS ((void));
771 static unw_rec_list
*output_preds_gr
PARAMS ((unsigned int));
772 static unw_rec_list
*output_preds_psprel
PARAMS ((unsigned int));
773 static unw_rec_list
*output_preds_sprel
PARAMS ((unsigned int));
774 static unw_rec_list
*output_fr_mem
PARAMS ((unsigned int));
775 static unw_rec_list
*output_frgr_mem
PARAMS ((unsigned int, unsigned int));
776 static unw_rec_list
*output_gr_gr
PARAMS ((unsigned int, unsigned int));
777 static unw_rec_list
*output_gr_mem
PARAMS ((unsigned int));
778 static unw_rec_list
*output_br_mem
PARAMS ((unsigned int));
779 static unw_rec_list
*output_br_gr
PARAMS ((unsigned int, unsigned int));
780 static unw_rec_list
*output_spill_base
PARAMS ((unsigned int));
781 static unw_rec_list
*output_unat_when
PARAMS ((void));
782 static unw_rec_list
*output_unat_gr
PARAMS ((unsigned int));
783 static unw_rec_list
*output_unat_psprel
PARAMS ((unsigned int));
784 static unw_rec_list
*output_unat_sprel
PARAMS ((unsigned int));
785 static unw_rec_list
*output_lc_when
PARAMS ((void));
786 static unw_rec_list
*output_lc_gr
PARAMS ((unsigned int));
787 static unw_rec_list
*output_lc_psprel
PARAMS ((unsigned int));
788 static unw_rec_list
*output_lc_sprel
PARAMS ((unsigned int));
789 static unw_rec_list
*output_fpsr_when
PARAMS ((void));
790 static unw_rec_list
*output_fpsr_gr
PARAMS ((unsigned int));
791 static unw_rec_list
*output_fpsr_psprel
PARAMS ((unsigned int));
792 static unw_rec_list
*output_fpsr_sprel
PARAMS ((unsigned int));
793 static unw_rec_list
*output_priunat_when_gr
PARAMS ((void));
794 static unw_rec_list
*output_priunat_when_mem
PARAMS ((void));
795 static unw_rec_list
*output_priunat_gr
PARAMS ((unsigned int));
796 static unw_rec_list
*output_priunat_psprel
PARAMS ((unsigned int));
797 static unw_rec_list
*output_priunat_sprel
PARAMS ((unsigned int));
798 static unw_rec_list
*output_bsp_when
PARAMS ((void));
799 static unw_rec_list
*output_bsp_gr
PARAMS ((unsigned int));
800 static unw_rec_list
*output_bsp_psprel
PARAMS ((unsigned int));
801 static unw_rec_list
*output_bsp_sprel
PARAMS ((unsigned int));
802 static unw_rec_list
*output_bspstore_when
PARAMS ((void));
803 static unw_rec_list
*output_bspstore_gr
PARAMS ((unsigned int));
804 static unw_rec_list
*output_bspstore_psprel
PARAMS ((unsigned int));
805 static unw_rec_list
*output_bspstore_sprel
PARAMS ((unsigned int));
806 static unw_rec_list
*output_rnat_when
PARAMS ((void));
807 static unw_rec_list
*output_rnat_gr
PARAMS ((unsigned int));
808 static unw_rec_list
*output_rnat_psprel
PARAMS ((unsigned int));
809 static unw_rec_list
*output_rnat_sprel
PARAMS ((unsigned int));
810 static unw_rec_list
*output_unwabi
PARAMS ((unsigned long, unsigned long));
811 static unw_rec_list
*output_epilogue
PARAMS ((unsigned long));
812 static unw_rec_list
*output_label_state
PARAMS ((unsigned long));
813 static unw_rec_list
*output_copy_state
PARAMS ((unsigned long));
814 static unw_rec_list
*output_spill_psprel
PARAMS ((unsigned int, unsigned int, unsigned int));
815 static unw_rec_list
*output_spill_sprel
PARAMS ((unsigned int, unsigned int, unsigned int));
816 static unw_rec_list
*output_spill_psprel_p
PARAMS ((unsigned int, unsigned int, unsigned int,
818 static unw_rec_list
*output_spill_sprel_p
PARAMS ((unsigned int, unsigned int, unsigned int,
820 static unw_rec_list
*output_spill_reg
PARAMS ((unsigned int, unsigned int, unsigned int,
822 static unw_rec_list
*output_spill_reg_p
PARAMS ((unsigned int, unsigned int, unsigned int,
823 unsigned int, unsigned int));
824 static void process_one_record
PARAMS ((unw_rec_list
*, vbyte_func
));
825 static void process_unw_records
PARAMS ((unw_rec_list
*, vbyte_func
));
826 static int calc_record_size
PARAMS ((unw_rec_list
*));
827 static void set_imask
PARAMS ((unw_rec_list
*, unsigned long, unsigned long, unsigned int));
828 static int count_bits
PARAMS ((unsigned long));
829 static unsigned long slot_index
PARAMS ((unsigned long, fragS
*,
830 unsigned long, fragS
*));
831 static unw_rec_list
*optimize_unw_records
PARAMS ((unw_rec_list
*));
832 static void fixup_unw_records
PARAMS ((unw_rec_list
*));
833 static int output_unw_records
PARAMS ((unw_rec_list
*, void **));
834 static int convert_expr_to_ab_reg
PARAMS ((expressionS
*, unsigned int *, unsigned int *));
835 static int convert_expr_to_xy_reg
PARAMS ((expressionS
*, unsigned int *, unsigned int *));
836 static int generate_unwind_image
PARAMS ((const char *));
838 /* Build the unwind section name by appending the (possibly stripped)
839 text section NAME to the unwind PREFIX. The resulting string
840 pointer is assigned to RESULT. The string is allocated on the
841 stack, so this must be a macro... */
842 #define make_unw_section_name(special, text_name, result) \
844 char *_prefix = special_section_name[special]; \
845 size_t _prefix_len = strlen (_prefix), _text_len = strlen (text_name); \
846 char *_result = alloca (_prefix_len + _text_len + 1); \
847 memcpy(_result, _prefix, _prefix_len); \
848 memcpy(_result + _prefix_len, text_name, _text_len); \
849 _result[_prefix_len + _text_len] = '\0'; \
854 /* Determine if application register REGNUM resides in the integer
855 unit (as opposed to the memory unit). */
857 ar_is_in_integer_unit (reg
)
862 return (reg
== 64 /* pfs */
863 || reg
== 65 /* lc */
864 || reg
== 66 /* ec */
865 /* ??? ias accepts and puts these in the integer unit. */
866 || (reg
>= 112 && reg
<= 127));
869 /* Switch to section NAME and create section if necessary. It's
870 rather ugly that we have to manipulate input_line_pointer but I
871 don't see any other way to accomplish the same thing without
872 changing obj-elf.c (which may be the Right Thing, in the end). */
877 char *saved_input_line_pointer
;
879 saved_input_line_pointer
= input_line_pointer
;
880 input_line_pointer
= name
;
882 input_line_pointer
= saved_input_line_pointer
;
885 /* Map SHF_IA_64_SHORT to SEC_SMALL_DATA. */
888 ia64_elf_section_flags (flags
, attr
, type
)
890 int attr
, type ATTRIBUTE_UNUSED
;
892 if (attr
& SHF_IA_64_SHORT
)
893 flags
|= SEC_SMALL_DATA
;
898 ia64_elf_section_type (str
, len
)
902 len
= sizeof (ELF_STRING_ia64_unwind_info
) - 1;
903 if (strncmp (str
, ELF_STRING_ia64_unwind_info
, len
) == 0)
906 len
= sizeof (ELF_STRING_ia64_unwind
) - 1;
907 if (strncmp (str
, ELF_STRING_ia64_unwind
, len
) == 0)
908 return SHT_IA_64_UNWIND
;
914 set_regstack (ins
, locs
, outs
, rots
)
915 unsigned int ins
, locs
, outs
, rots
;
920 sof
= ins
+ locs
+ outs
;
923 as_bad ("Size of frame exceeds maximum of 96 registers");
928 as_warn ("Size of rotating registers exceeds frame size");
931 md
.in
.base
= REG_GR
+ 32;
932 md
.loc
.base
= md
.in
.base
+ ins
;
933 md
.out
.base
= md
.loc
.base
+ locs
;
935 md
.in
.num_regs
= ins
;
936 md
.loc
.num_regs
= locs
;
937 md
.out
.num_regs
= outs
;
938 md
.rot
.num_regs
= rots
;
945 struct label_fix
*lfix
;
947 subsegT saved_subseg
;
950 if (!md
.last_text_seg
)
954 saved_subseg
= now_subseg
;
956 subseg_set (md
.last_text_seg
, 0);
958 while (md
.num_slots_in_use
> 0)
959 emit_one_bundle (); /* force out queued instructions */
961 /* In case there are labels following the last instruction, resolve
963 for (lfix
= CURR_SLOT
.label_fixups
; lfix
; lfix
= lfix
->next
)
965 S_SET_VALUE (lfix
->sym
, frag_now_fix ());
966 symbol_set_frag (lfix
->sym
, frag_now
);
968 CURR_SLOT
.label_fixups
= 0;
969 for (lfix
= CURR_SLOT
.tag_fixups
; lfix
; lfix
= lfix
->next
)
971 S_SET_VALUE (lfix
->sym
, frag_now_fix ());
972 symbol_set_frag (lfix
->sym
, frag_now
);
974 CURR_SLOT
.tag_fixups
= 0;
976 /* In case there are unwind directives following the last instruction,
977 resolve those now. We only handle body and prologue directives here.
978 Give an error for others. */
979 for (ptr
= unwind
.current_entry
; ptr
; ptr
= ptr
->next
)
981 if (ptr
->r
.type
== prologue
|| ptr
->r
.type
== prologue_gr
982 || ptr
->r
.type
== body
)
984 ptr
->slot_number
= (unsigned long) frag_more (0);
985 ptr
->slot_frag
= frag_now
;
988 as_bad (_("Unwind directive not followed by an instruction."));
990 unwind
.current_entry
= NULL
;
992 subseg_set (saved_seg
, saved_subseg
);
994 if (md
.qp
.X_op
== O_register
)
995 as_bad ("qualifying predicate not followed by instruction");
999 ia64_do_align (nbytes
)
1002 char *saved_input_line_pointer
= input_line_pointer
;
1004 input_line_pointer
= "";
1005 s_align_bytes (nbytes
);
1006 input_line_pointer
= saved_input_line_pointer
;
1010 ia64_cons_align (nbytes
)
1015 char *saved_input_line_pointer
= input_line_pointer
;
1016 input_line_pointer
= "";
1017 s_align_bytes (nbytes
);
1018 input_line_pointer
= saved_input_line_pointer
;
1022 /* Output COUNT bytes to a memory location. */
1023 static unsigned char *vbyte_mem_ptr
= NULL
;
1026 output_vbyte_mem (count
, ptr
, comment
)
1029 char *comment ATTRIBUTE_UNUSED
;
1032 if (vbyte_mem_ptr
== NULL
)
1037 for (x
= 0; x
< count
; x
++)
1038 *(vbyte_mem_ptr
++) = ptr
[x
];
1041 /* Count the number of bytes required for records. */
1042 static int vbyte_count
= 0;
1044 count_output (count
, ptr
, comment
)
1046 char *ptr ATTRIBUTE_UNUSED
;
1047 char *comment ATTRIBUTE_UNUSED
;
1049 vbyte_count
+= count
;
1053 output_R1_format (f
, rtype
, rlen
)
1055 unw_record_type rtype
;
1062 output_R3_format (f
, rtype
, rlen
);
1068 else if (rtype
!= prologue
)
1069 as_bad ("record type is not valid");
1071 byte
= UNW_R1
| (r
<< 5) | (rlen
& 0x1f);
1072 (*f
) (1, &byte
, NULL
);
1076 output_R2_format (f
, mask
, grsave
, rlen
)
1083 mask
= (mask
& 0x0f);
1084 grsave
= (grsave
& 0x7f);
1086 bytes
[0] = (UNW_R2
| (mask
>> 1));
1087 bytes
[1] = (((mask
& 0x01) << 7) | grsave
);
1088 count
+= output_leb128 (bytes
+ 2, rlen
, 0);
1089 (*f
) (count
, bytes
, NULL
);
1093 output_R3_format (f
, rtype
, rlen
)
1095 unw_record_type rtype
;
1102 output_R1_format (f
, rtype
, rlen
);
1108 else if (rtype
!= prologue
)
1109 as_bad ("record type is not valid");
1110 bytes
[0] = (UNW_R3
| r
);
1111 count
= output_leb128 (bytes
+ 1, rlen
, 0);
1112 (*f
) (count
+ 1, bytes
, NULL
);
1116 output_P1_format (f
, brmask
)
1121 byte
= UNW_P1
| (brmask
& 0x1f);
1122 (*f
) (1, &byte
, NULL
);
1126 output_P2_format (f
, brmask
, gr
)
1132 brmask
= (brmask
& 0x1f);
1133 bytes
[0] = UNW_P2
| (brmask
>> 1);
1134 bytes
[1] = (((brmask
& 1) << 7) | gr
);
1135 (*f
) (2, bytes
, NULL
);
1139 output_P3_format (f
, rtype
, reg
)
1141 unw_record_type rtype
;
1186 as_bad ("Invalid record type for P3 format.");
1188 bytes
[0] = (UNW_P3
| (r
>> 1));
1189 bytes
[1] = (((r
& 1) << 7) | reg
);
1190 (*f
) (2, bytes
, NULL
);
1194 output_P4_format (f
, imask
, imask_size
)
1196 unsigned char *imask
;
1197 unsigned long imask_size
;
1200 (*f
) (imask_size
, imask
, NULL
);
1204 output_P5_format (f
, grmask
, frmask
)
1207 unsigned long frmask
;
1210 grmask
= (grmask
& 0x0f);
1213 bytes
[1] = ((grmask
<< 4) | ((frmask
& 0x000f0000) >> 16));
1214 bytes
[2] = ((frmask
& 0x0000ff00) >> 8);
1215 bytes
[3] = (frmask
& 0x000000ff);
1216 (*f
) (4, bytes
, NULL
);
1220 output_P6_format (f
, rtype
, rmask
)
1222 unw_record_type rtype
;
1228 if (rtype
== gr_mem
)
1230 else if (rtype
!= fr_mem
)
1231 as_bad ("Invalid record type for format P6");
1232 byte
= (UNW_P6
| (r
<< 4) | (rmask
& 0x0f));
1233 (*f
) (1, &byte
, NULL
);
1237 output_P7_format (f
, rtype
, w1
, w2
)
1239 unw_record_type rtype
;
1246 count
+= output_leb128 (bytes
+ 1, w1
, 0);
1251 count
+= output_leb128 (bytes
+ count
, w2
>> 4, 0);
1301 bytes
[0] = (UNW_P7
| r
);
1302 (*f
) (count
, bytes
, NULL
);
1306 output_P8_format (f
, rtype
, t
)
1308 unw_record_type rtype
;
1347 case bspstore_psprel
:
1350 case bspstore_sprel
:
1362 case priunat_when_gr
:
1365 case priunat_psprel
:
1371 case priunat_when_mem
:
1378 count
+= output_leb128 (bytes
+ 2, t
, 0);
1379 (*f
) (count
, bytes
, NULL
);
1383 output_P9_format (f
, grmask
, gr
)
1390 bytes
[1] = (grmask
& 0x0f);
1391 bytes
[2] = (gr
& 0x7f);
1392 (*f
) (3, bytes
, NULL
);
1396 output_P10_format (f
, abi
, context
)
1403 bytes
[1] = (abi
& 0xff);
1404 bytes
[2] = (context
& 0xff);
1405 (*f
) (3, bytes
, NULL
);
1409 output_B1_format (f
, rtype
, label
)
1411 unw_record_type rtype
;
1412 unsigned long label
;
1418 output_B4_format (f
, rtype
, label
);
1421 if (rtype
== copy_state
)
1423 else if (rtype
!= label_state
)
1424 as_bad ("Invalid record type for format B1");
1426 byte
= (UNW_B1
| (r
<< 5) | (label
& 0x1f));
1427 (*f
) (1, &byte
, NULL
);
1431 output_B2_format (f
, ecount
, t
)
1433 unsigned long ecount
;
1440 output_B3_format (f
, ecount
, t
);
1443 bytes
[0] = (UNW_B2
| (ecount
& 0x1f));
1444 count
+= output_leb128 (bytes
+ 1, t
, 0);
1445 (*f
) (count
, bytes
, NULL
);
1449 output_B3_format (f
, ecount
, t
)
1451 unsigned long ecount
;
1458 output_B2_format (f
, ecount
, t
);
1462 count
+= output_leb128 (bytes
+ 1, t
, 0);
1463 count
+= output_leb128 (bytes
+ count
, ecount
, 0);
1464 (*f
) (count
, bytes
, NULL
);
1468 output_B4_format (f
, rtype
, label
)
1470 unw_record_type rtype
;
1471 unsigned long label
;
1478 output_B1_format (f
, rtype
, label
);
1482 if (rtype
== copy_state
)
1484 else if (rtype
!= label_state
)
1485 as_bad ("Invalid record type for format B1");
1487 bytes
[0] = (UNW_B4
| (r
<< 3));
1488 count
+= output_leb128 (bytes
+ 1, label
, 0);
1489 (*f
) (count
, bytes
, NULL
);
1493 format_ab_reg (ab
, reg
)
1500 ret
= (ab
<< 5) | reg
;
1505 output_X1_format (f
, rtype
, ab
, reg
, t
, w1
)
1507 unw_record_type rtype
;
1517 if (rtype
== spill_sprel
)
1519 else if (rtype
!= spill_psprel
)
1520 as_bad ("Invalid record type for format X1");
1521 bytes
[1] = ((r
<< 7) | format_ab_reg (ab
, reg
));
1522 count
+= output_leb128 (bytes
+ 2, t
, 0);
1523 count
+= output_leb128 (bytes
+ count
, w1
, 0);
1524 (*f
) (count
, bytes
, NULL
);
1528 output_X2_format (f
, ab
, reg
, x
, y
, treg
, t
)
1537 bytes
[1] = (((x
& 1) << 7) | format_ab_reg (ab
, reg
));
1538 bytes
[2] = (((y
& 1) << 7) | (treg
& 0x7f));
1539 count
+= output_leb128 (bytes
+ 3, t
, 0);
1540 (*f
) (count
, bytes
, NULL
);
1544 output_X3_format (f
, rtype
, qp
, ab
, reg
, t
, w1
)
1546 unw_record_type rtype
;
1557 if (rtype
== spill_sprel_p
)
1559 else if (rtype
!= spill_psprel_p
)
1560 as_bad ("Invalid record type for format X3");
1561 bytes
[1] = ((r
<< 7) | (qp
& 0x3f));
1562 bytes
[2] = format_ab_reg (ab
, reg
);
1563 count
+= output_leb128 (bytes
+ 3, t
, 0);
1564 count
+= output_leb128 (bytes
+ count
, w1
, 0);
1565 (*f
) (count
, bytes
, NULL
);
1569 output_X4_format (f
, qp
, ab
, reg
, x
, y
, treg
, t
)
1579 bytes
[1] = (qp
& 0x3f);
1580 bytes
[2] = (((x
& 1) << 7) | format_ab_reg (ab
, reg
));
1581 bytes
[3] = (((y
& 1) << 7) | (treg
& 0x7f));
1582 count
+= output_leb128 (bytes
+ 4, t
, 0);
1583 (*f
) (count
, bytes
, NULL
);
1586 /* This function allocates a record list structure, and initializes fields. */
1588 static unw_rec_list
*
1589 alloc_record (unw_record_type t
)
1592 ptr
= xmalloc (sizeof (*ptr
));
1594 ptr
->slot_number
= SLOT_NUM_NOT_SET
;
1599 /* This function frees an entire list of record structures. */
1602 free_list_records (unw_rec_list
*first
)
1605 for (ptr
= first
; ptr
!= NULL
;)
1607 unw_rec_list
*tmp
= ptr
;
1609 if ((tmp
->r
.type
== prologue
|| tmp
->r
.type
== prologue_gr
)
1610 && tmp
->r
.record
.r
.mask
.i
)
1611 free (tmp
->r
.record
.r
.mask
.i
);
1618 static unw_rec_list
*
1621 unw_rec_list
*ptr
= alloc_record (prologue
);
1622 memset (&ptr
->r
.record
.r
.mask
, 0, sizeof (ptr
->r
.record
.r
.mask
));
1626 static unw_rec_list
*
1627 output_prologue_gr (saved_mask
, reg
)
1628 unsigned int saved_mask
;
1631 unw_rec_list
*ptr
= alloc_record (prologue_gr
);
1632 memset (&ptr
->r
.record
.r
.mask
, 0, sizeof (ptr
->r
.record
.r
.mask
));
1633 ptr
->r
.record
.r
.grmask
= saved_mask
;
1634 ptr
->r
.record
.r
.grsave
= reg
;
1638 static unw_rec_list
*
1641 unw_rec_list
*ptr
= alloc_record (body
);
1645 static unw_rec_list
*
1646 output_mem_stack_f (size
)
1649 unw_rec_list
*ptr
= alloc_record (mem_stack_f
);
1650 ptr
->r
.record
.p
.size
= size
;
1654 static unw_rec_list
*
1655 output_mem_stack_v ()
1657 unw_rec_list
*ptr
= alloc_record (mem_stack_v
);
1661 static unw_rec_list
*
1665 unw_rec_list
*ptr
= alloc_record (psp_gr
);
1666 ptr
->r
.record
.p
.gr
= gr
;
1670 static unw_rec_list
*
1671 output_psp_sprel (offset
)
1672 unsigned int offset
;
1674 unw_rec_list
*ptr
= alloc_record (psp_sprel
);
1675 ptr
->r
.record
.p
.spoff
= offset
/ 4;
1679 static unw_rec_list
*
1682 unw_rec_list
*ptr
= alloc_record (rp_when
);
1686 static unw_rec_list
*
1690 unw_rec_list
*ptr
= alloc_record (rp_gr
);
1691 ptr
->r
.record
.p
.gr
= gr
;
1695 static unw_rec_list
*
1699 unw_rec_list
*ptr
= alloc_record (rp_br
);
1700 ptr
->r
.record
.p
.br
= br
;
1704 static unw_rec_list
*
1705 output_rp_psprel (offset
)
1706 unsigned int offset
;
1708 unw_rec_list
*ptr
= alloc_record (rp_psprel
);
1709 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
1713 static unw_rec_list
*
1714 output_rp_sprel (offset
)
1715 unsigned int offset
;
1717 unw_rec_list
*ptr
= alloc_record (rp_sprel
);
1718 ptr
->r
.record
.p
.spoff
= offset
/ 4;
1722 static unw_rec_list
*
1725 unw_rec_list
*ptr
= alloc_record (pfs_when
);
1729 static unw_rec_list
*
1733 unw_rec_list
*ptr
= alloc_record (pfs_gr
);
1734 ptr
->r
.record
.p
.gr
= gr
;
1738 static unw_rec_list
*
1739 output_pfs_psprel (offset
)
1740 unsigned int offset
;
1742 unw_rec_list
*ptr
= alloc_record (pfs_psprel
);
1743 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
1747 static unw_rec_list
*
1748 output_pfs_sprel (offset
)
1749 unsigned int offset
;
1751 unw_rec_list
*ptr
= alloc_record (pfs_sprel
);
1752 ptr
->r
.record
.p
.spoff
= offset
/ 4;
1756 static unw_rec_list
*
1757 output_preds_when ()
1759 unw_rec_list
*ptr
= alloc_record (preds_when
);
1763 static unw_rec_list
*
1764 output_preds_gr (gr
)
1767 unw_rec_list
*ptr
= alloc_record (preds_gr
);
1768 ptr
->r
.record
.p
.gr
= gr
;
1772 static unw_rec_list
*
1773 output_preds_psprel (offset
)
1774 unsigned int offset
;
1776 unw_rec_list
*ptr
= alloc_record (preds_psprel
);
1777 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
1781 static unw_rec_list
*
1782 output_preds_sprel (offset
)
1783 unsigned int offset
;
1785 unw_rec_list
*ptr
= alloc_record (preds_sprel
);
1786 ptr
->r
.record
.p
.spoff
= offset
/ 4;
1790 static unw_rec_list
*
1791 output_fr_mem (mask
)
1794 unw_rec_list
*ptr
= alloc_record (fr_mem
);
1795 ptr
->r
.record
.p
.rmask
= mask
;
1799 static unw_rec_list
*
1800 output_frgr_mem (gr_mask
, fr_mask
)
1801 unsigned int gr_mask
;
1802 unsigned int fr_mask
;
1804 unw_rec_list
*ptr
= alloc_record (frgr_mem
);
1805 ptr
->r
.record
.p
.grmask
= gr_mask
;
1806 ptr
->r
.record
.p
.frmask
= fr_mask
;
1810 static unw_rec_list
*
1811 output_gr_gr (mask
, reg
)
1815 unw_rec_list
*ptr
= alloc_record (gr_gr
);
1816 ptr
->r
.record
.p
.grmask
= mask
;
1817 ptr
->r
.record
.p
.gr
= reg
;
1821 static unw_rec_list
*
1822 output_gr_mem (mask
)
1825 unw_rec_list
*ptr
= alloc_record (gr_mem
);
1826 ptr
->r
.record
.p
.rmask
= mask
;
1830 static unw_rec_list
*
1831 output_br_mem (unsigned int mask
)
1833 unw_rec_list
*ptr
= alloc_record (br_mem
);
1834 ptr
->r
.record
.p
.brmask
= mask
;
1838 static unw_rec_list
*
1839 output_br_gr (save_mask
, reg
)
1840 unsigned int save_mask
;
1843 unw_rec_list
*ptr
= alloc_record (br_gr
);
1844 ptr
->r
.record
.p
.brmask
= save_mask
;
1845 ptr
->r
.record
.p
.gr
= reg
;
1849 static unw_rec_list
*
1850 output_spill_base (offset
)
1851 unsigned int offset
;
1853 unw_rec_list
*ptr
= alloc_record (spill_base
);
1854 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
1858 static unw_rec_list
*
1861 unw_rec_list
*ptr
= alloc_record (unat_when
);
1865 static unw_rec_list
*
1869 unw_rec_list
*ptr
= alloc_record (unat_gr
);
1870 ptr
->r
.record
.p
.gr
= gr
;
1874 static unw_rec_list
*
1875 output_unat_psprel (offset
)
1876 unsigned int offset
;
1878 unw_rec_list
*ptr
= alloc_record (unat_psprel
);
1879 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
1883 static unw_rec_list
*
1884 output_unat_sprel (offset
)
1885 unsigned int offset
;
1887 unw_rec_list
*ptr
= alloc_record (unat_sprel
);
1888 ptr
->r
.record
.p
.spoff
= offset
/ 4;
1892 static unw_rec_list
*
1895 unw_rec_list
*ptr
= alloc_record (lc_when
);
1899 static unw_rec_list
*
1903 unw_rec_list
*ptr
= alloc_record (lc_gr
);
1904 ptr
->r
.record
.p
.gr
= gr
;
1908 static unw_rec_list
*
1909 output_lc_psprel (offset
)
1910 unsigned int offset
;
1912 unw_rec_list
*ptr
= alloc_record (lc_psprel
);
1913 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
1917 static unw_rec_list
*
1918 output_lc_sprel (offset
)
1919 unsigned int offset
;
1921 unw_rec_list
*ptr
= alloc_record (lc_sprel
);
1922 ptr
->r
.record
.p
.spoff
= offset
/ 4;
1926 static unw_rec_list
*
1929 unw_rec_list
*ptr
= alloc_record (fpsr_when
);
1933 static unw_rec_list
*
1937 unw_rec_list
*ptr
= alloc_record (fpsr_gr
);
1938 ptr
->r
.record
.p
.gr
= gr
;
1942 static unw_rec_list
*
1943 output_fpsr_psprel (offset
)
1944 unsigned int offset
;
1946 unw_rec_list
*ptr
= alloc_record (fpsr_psprel
);
1947 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
1951 static unw_rec_list
*
1952 output_fpsr_sprel (offset
)
1953 unsigned int offset
;
1955 unw_rec_list
*ptr
= alloc_record (fpsr_sprel
);
1956 ptr
->r
.record
.p
.spoff
= offset
/ 4;
1960 static unw_rec_list
*
1961 output_priunat_when_gr ()
1963 unw_rec_list
*ptr
= alloc_record (priunat_when_gr
);
1967 static unw_rec_list
*
1968 output_priunat_when_mem ()
1970 unw_rec_list
*ptr
= alloc_record (priunat_when_mem
);
1974 static unw_rec_list
*
1975 output_priunat_gr (gr
)
1978 unw_rec_list
*ptr
= alloc_record (priunat_gr
);
1979 ptr
->r
.record
.p
.gr
= gr
;
1983 static unw_rec_list
*
1984 output_priunat_psprel (offset
)
1985 unsigned int offset
;
1987 unw_rec_list
*ptr
= alloc_record (priunat_psprel
);
1988 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
1992 static unw_rec_list
*
1993 output_priunat_sprel (offset
)
1994 unsigned int offset
;
1996 unw_rec_list
*ptr
= alloc_record (priunat_sprel
);
1997 ptr
->r
.record
.p
.spoff
= offset
/ 4;
2001 static unw_rec_list
*
2004 unw_rec_list
*ptr
= alloc_record (bsp_when
);
2008 static unw_rec_list
*
2012 unw_rec_list
*ptr
= alloc_record (bsp_gr
);
2013 ptr
->r
.record
.p
.gr
= gr
;
2017 static unw_rec_list
*
2018 output_bsp_psprel (offset
)
2019 unsigned int offset
;
2021 unw_rec_list
*ptr
= alloc_record (bsp_psprel
);
2022 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
2026 static unw_rec_list
*
2027 output_bsp_sprel (offset
)
2028 unsigned int offset
;
2030 unw_rec_list
*ptr
= alloc_record (bsp_sprel
);
2031 ptr
->r
.record
.p
.spoff
= offset
/ 4;
2035 static unw_rec_list
*
2036 output_bspstore_when ()
2038 unw_rec_list
*ptr
= alloc_record (bspstore_when
);
2042 static unw_rec_list
*
2043 output_bspstore_gr (gr
)
2046 unw_rec_list
*ptr
= alloc_record (bspstore_gr
);
2047 ptr
->r
.record
.p
.gr
= gr
;
2051 static unw_rec_list
*
2052 output_bspstore_psprel (offset
)
2053 unsigned int offset
;
2055 unw_rec_list
*ptr
= alloc_record (bspstore_psprel
);
2056 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
2060 static unw_rec_list
*
2061 output_bspstore_sprel (offset
)
2062 unsigned int offset
;
2064 unw_rec_list
*ptr
= alloc_record (bspstore_sprel
);
2065 ptr
->r
.record
.p
.spoff
= offset
/ 4;
2069 static unw_rec_list
*
2072 unw_rec_list
*ptr
= alloc_record (rnat_when
);
2076 static unw_rec_list
*
2080 unw_rec_list
*ptr
= alloc_record (rnat_gr
);
2081 ptr
->r
.record
.p
.gr
= gr
;
2085 static unw_rec_list
*
2086 output_rnat_psprel (offset
)
2087 unsigned int offset
;
2089 unw_rec_list
*ptr
= alloc_record (rnat_psprel
);
2090 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
2094 static unw_rec_list
*
2095 output_rnat_sprel (offset
)
2096 unsigned int offset
;
2098 unw_rec_list
*ptr
= alloc_record (rnat_sprel
);
2099 ptr
->r
.record
.p
.spoff
= offset
/ 4;
2103 static unw_rec_list
*
2104 output_unwabi (abi
, context
)
2106 unsigned long context
;
2108 unw_rec_list
*ptr
= alloc_record (unwabi
);
2109 ptr
->r
.record
.p
.abi
= abi
;
2110 ptr
->r
.record
.p
.context
= context
;
2114 static unw_rec_list
*
2115 output_epilogue (unsigned long ecount
)
2117 unw_rec_list
*ptr
= alloc_record (epilogue
);
2118 ptr
->r
.record
.b
.ecount
= ecount
;
2122 static unw_rec_list
*
2123 output_label_state (unsigned long label
)
2125 unw_rec_list
*ptr
= alloc_record (label_state
);
2126 ptr
->r
.record
.b
.label
= label
;
2130 static unw_rec_list
*
2131 output_copy_state (unsigned long label
)
2133 unw_rec_list
*ptr
= alloc_record (copy_state
);
2134 ptr
->r
.record
.b
.label
= label
;
2138 static unw_rec_list
*
2139 output_spill_psprel (ab
, reg
, offset
)
2142 unsigned int offset
;
2144 unw_rec_list
*ptr
= alloc_record (spill_psprel
);
2145 ptr
->r
.record
.x
.ab
= ab
;
2146 ptr
->r
.record
.x
.reg
= reg
;
2147 ptr
->r
.record
.x
.pspoff
= offset
/ 4;
2151 static unw_rec_list
*
2152 output_spill_sprel (ab
, reg
, offset
)
2155 unsigned int offset
;
2157 unw_rec_list
*ptr
= alloc_record (spill_sprel
);
2158 ptr
->r
.record
.x
.ab
= ab
;
2159 ptr
->r
.record
.x
.reg
= reg
;
2160 ptr
->r
.record
.x
.spoff
= offset
/ 4;
2164 static unw_rec_list
*
2165 output_spill_psprel_p (ab
, reg
, offset
, predicate
)
2168 unsigned int offset
;
2169 unsigned int predicate
;
2171 unw_rec_list
*ptr
= alloc_record (spill_psprel_p
);
2172 ptr
->r
.record
.x
.ab
= ab
;
2173 ptr
->r
.record
.x
.reg
= reg
;
2174 ptr
->r
.record
.x
.pspoff
= offset
/ 4;
2175 ptr
->r
.record
.x
.qp
= predicate
;
2179 static unw_rec_list
*
2180 output_spill_sprel_p (ab
, reg
, offset
, predicate
)
2183 unsigned int offset
;
2184 unsigned int predicate
;
2186 unw_rec_list
*ptr
= alloc_record (spill_sprel_p
);
2187 ptr
->r
.record
.x
.ab
= ab
;
2188 ptr
->r
.record
.x
.reg
= reg
;
2189 ptr
->r
.record
.x
.spoff
= offset
/ 4;
2190 ptr
->r
.record
.x
.qp
= predicate
;
2194 static unw_rec_list
*
2195 output_spill_reg (ab
, reg
, targ_reg
, xy
)
2198 unsigned int targ_reg
;
2201 unw_rec_list
*ptr
= alloc_record (spill_reg
);
2202 ptr
->r
.record
.x
.ab
= ab
;
2203 ptr
->r
.record
.x
.reg
= reg
;
2204 ptr
->r
.record
.x
.treg
= targ_reg
;
2205 ptr
->r
.record
.x
.xy
= xy
;
2209 static unw_rec_list
*
2210 output_spill_reg_p (ab
, reg
, targ_reg
, xy
, predicate
)
2213 unsigned int targ_reg
;
2215 unsigned int predicate
;
2217 unw_rec_list
*ptr
= alloc_record (spill_reg_p
);
2218 ptr
->r
.record
.x
.ab
= ab
;
2219 ptr
->r
.record
.x
.reg
= reg
;
2220 ptr
->r
.record
.x
.treg
= targ_reg
;
2221 ptr
->r
.record
.x
.xy
= xy
;
2222 ptr
->r
.record
.x
.qp
= predicate
;
2226 /* Given a unw_rec_list process the correct format with the
2227 specified function. */
2230 process_one_record (ptr
, f
)
2234 unsigned long fr_mask
, gr_mask
;
2236 switch (ptr
->r
.type
)
2242 /* These are taken care of by prologue/prologue_gr. */
2247 if (ptr
->r
.type
== prologue_gr
)
2248 output_R2_format (f
, ptr
->r
.record
.r
.grmask
,
2249 ptr
->r
.record
.r
.grsave
, ptr
->r
.record
.r
.rlen
);
2251 output_R1_format (f
, ptr
->r
.type
, ptr
->r
.record
.r
.rlen
);
2253 /* Output descriptor(s) for union of register spills (if any). */
2254 gr_mask
= ptr
->r
.record
.r
.mask
.gr_mem
;
2255 fr_mask
= ptr
->r
.record
.r
.mask
.fr_mem
;
2258 if ((fr_mask
& ~0xfUL
) == 0)
2259 output_P6_format (f
, fr_mem
, fr_mask
);
2262 output_P5_format (f
, gr_mask
, fr_mask
);
2267 output_P6_format (f
, gr_mem
, gr_mask
);
2268 if (ptr
->r
.record
.r
.mask
.br_mem
)
2269 output_P1_format (f
, ptr
->r
.record
.r
.mask
.br_mem
);
2271 /* output imask descriptor if necessary: */
2272 if (ptr
->r
.record
.r
.mask
.i
)
2273 output_P4_format (f
, ptr
->r
.record
.r
.mask
.i
,
2274 ptr
->r
.record
.r
.imask_size
);
2278 output_R1_format (f
, ptr
->r
.type
, ptr
->r
.record
.r
.rlen
);
2282 output_P7_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.t
,
2283 ptr
->r
.record
.p
.size
);
2296 output_P3_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.gr
);
2299 output_P3_format (f
, rp_br
, ptr
->r
.record
.p
.br
);
2302 output_P7_format (f
, psp_sprel
, ptr
->r
.record
.p
.spoff
, 0);
2310 output_P7_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.t
, 0);
2319 output_P7_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.pspoff
, 0);
2329 case bspstore_sprel
:
2331 output_P8_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.spoff
);
2334 output_P9_format (f
, ptr
->r
.record
.p
.grmask
, ptr
->r
.record
.p
.gr
);
2337 output_P2_format (f
, ptr
->r
.record
.p
.brmask
, ptr
->r
.record
.p
.gr
);
2340 as_bad ("spill_mask record unimplemented.");
2342 case priunat_when_gr
:
2343 case priunat_when_mem
:
2347 output_P8_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.t
);
2349 case priunat_psprel
:
2351 case bspstore_psprel
:
2353 output_P8_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.pspoff
);
2356 output_P10_format (f
, ptr
->r
.record
.p
.abi
, ptr
->r
.record
.p
.context
);
2359 output_B3_format (f
, ptr
->r
.record
.b
.ecount
, ptr
->r
.record
.b
.t
);
2363 output_B4_format (f
, ptr
->r
.type
, ptr
->r
.record
.b
.label
);
2366 output_X1_format (f
, ptr
->r
.type
, ptr
->r
.record
.x
.ab
,
2367 ptr
->r
.record
.x
.reg
, ptr
->r
.record
.x
.t
,
2368 ptr
->r
.record
.x
.pspoff
);
2371 output_X1_format (f
, ptr
->r
.type
, ptr
->r
.record
.x
.ab
,
2372 ptr
->r
.record
.x
.reg
, ptr
->r
.record
.x
.t
,
2373 ptr
->r
.record
.x
.spoff
);
2376 output_X2_format (f
, ptr
->r
.record
.x
.ab
, ptr
->r
.record
.x
.reg
,
2377 ptr
->r
.record
.x
.xy
>> 1, ptr
->r
.record
.x
.xy
,
2378 ptr
->r
.record
.x
.treg
, ptr
->r
.record
.x
.t
);
2380 case spill_psprel_p
:
2381 output_X3_format (f
, ptr
->r
.type
, ptr
->r
.record
.x
.qp
,
2382 ptr
->r
.record
.x
.ab
, ptr
->r
.record
.x
.reg
,
2383 ptr
->r
.record
.x
.t
, ptr
->r
.record
.x
.pspoff
);
2386 output_X3_format (f
, ptr
->r
.type
, ptr
->r
.record
.x
.qp
,
2387 ptr
->r
.record
.x
.ab
, ptr
->r
.record
.x
.reg
,
2388 ptr
->r
.record
.x
.t
, ptr
->r
.record
.x
.spoff
);
2391 output_X4_format (f
, ptr
->r
.record
.x
.qp
, ptr
->r
.record
.x
.ab
,
2392 ptr
->r
.record
.x
.reg
, ptr
->r
.record
.x
.xy
>> 1,
2393 ptr
->r
.record
.x
.xy
, ptr
->r
.record
.x
.treg
,
2397 as_bad ("record_type_not_valid");
2402 /* Given a unw_rec_list list, process all the records with
2403 the specified function. */
2405 process_unw_records (list
, f
)
2410 for (ptr
= list
; ptr
; ptr
= ptr
->next
)
2411 process_one_record (ptr
, f
);
2414 /* Determine the size of a record list in bytes. */
2416 calc_record_size (list
)
2420 process_unw_records (list
, count_output
);
2424 /* Update IMASK bitmask to reflect the fact that one or more registers
2425 of type TYPE are saved starting at instruction with index T. If N
2426 bits are set in REGMASK, it is assumed that instructions T through
2427 T+N-1 save these registers.
2431 1: instruction saves next fp reg
2432 2: instruction saves next general reg
2433 3: instruction saves next branch reg */
2435 set_imask (region
, regmask
, t
, type
)
2436 unw_rec_list
*region
;
2437 unsigned long regmask
;
2441 unsigned char *imask
;
2442 unsigned long imask_size
;
2446 imask
= region
->r
.record
.r
.mask
.i
;
2447 imask_size
= region
->r
.record
.r
.imask_size
;
2450 imask_size
= (region
->r
.record
.r
.rlen
* 2 + 7) / 8 + 1;
2451 imask
= xmalloc (imask_size
);
2452 memset (imask
, 0, imask_size
);
2454 region
->r
.record
.r
.imask_size
= imask_size
;
2455 region
->r
.record
.r
.mask
.i
= imask
;
2459 pos
= 2 * (3 - t
% 4);
2462 if (i
>= imask_size
)
2464 as_bad ("Ignoring attempt to spill beyond end of region");
2468 imask
[i
] |= (type
& 0x3) << pos
;
2470 regmask
&= (regmask
- 1);
2481 count_bits (unsigned long mask
)
2493 /* Return the number of instruction slots from FIRST_ADDR to SLOT_ADDR.
2494 SLOT_FRAG is the frag containing SLOT_ADDR, and FIRST_FRAG is the frag
2495 containing FIRST_ADDR. */
2498 slot_index (slot_addr
, slot_frag
, first_addr
, first_frag
)
2499 unsigned long slot_addr
;
2501 unsigned long first_addr
;
2504 unsigned long index
= 0;
2506 /* First time we are called, the initial address and frag are invalid. */
2507 if (first_addr
== 0)
2510 /* If the two addresses are in different frags, then we need to add in
2511 the remaining size of this frag, and then the entire size of intermediate
2513 while (slot_frag
!= first_frag
)
2515 unsigned long start_addr
= (unsigned long) &first_frag
->fr_literal
;
2517 /* Add in the full size of the frag converted to instruction slots. */
2518 index
+= 3 * (first_frag
->fr_fix
>> 4);
2519 /* Subtract away the initial part before first_addr. */
2520 index
-= (3 * ((first_addr
>> 4) - (start_addr
>> 4))
2521 + ((first_addr
& 0x3) - (start_addr
& 0x3)));
2523 /* Move to the beginning of the next frag. */
2524 first_frag
= first_frag
->fr_next
;
2525 first_addr
= (unsigned long) &first_frag
->fr_literal
;
2528 /* Add in the used part of the last frag. */
2529 index
+= (3 * ((slot_addr
>> 4) - (first_addr
>> 4))
2530 + ((slot_addr
& 0x3) - (first_addr
& 0x3)));
2534 /* Optimize unwind record directives. */
2536 static unw_rec_list
*
2537 optimize_unw_records (list
)
2543 /* If the only unwind record is ".prologue" or ".prologue" followed
2544 by ".body", then we can optimize the unwind directives away. */
2545 if (list
->r
.type
== prologue
2546 && (list
->next
== NULL
2547 || (list
->next
->r
.type
== body
&& list
->next
->next
== NULL
)))
2553 /* Given a complete record list, process any records which have
2554 unresolved fields, (ie length counts for a prologue). After
2555 this has been run, all neccessary information should be available
2556 within each record to generate an image. */
2559 fixup_unw_records (list
)
2562 unw_rec_list
*ptr
, *region
= 0;
2563 unsigned long first_addr
= 0, rlen
= 0, t
;
2564 fragS
*first_frag
= 0;
2566 for (ptr
= list
; ptr
; ptr
= ptr
->next
)
2568 if (ptr
->slot_number
== SLOT_NUM_NOT_SET
)
2569 as_bad (" Insn slot not set in unwind record.");
2570 t
= slot_index (ptr
->slot_number
, ptr
->slot_frag
,
2571 first_addr
, first_frag
);
2572 switch (ptr
->r
.type
)
2579 int size
, dir_len
= 0;
2580 unsigned long last_addr
;
2583 first_addr
= ptr
->slot_number
;
2584 first_frag
= ptr
->slot_frag
;
2585 ptr
->slot_number
= 0;
2586 /* Find either the next body/prologue start, or the end of
2587 the list, and determine the size of the region. */
2588 last_addr
= unwind
.next_slot_number
;
2589 last_frag
= unwind
.next_slot_frag
;
2590 for (last
= ptr
->next
; last
!= NULL
; last
= last
->next
)
2591 if (last
->r
.type
== prologue
|| last
->r
.type
== prologue_gr
2592 || last
->r
.type
== body
)
2594 last_addr
= last
->slot_number
;
2595 last_frag
= last
->slot_frag
;
2598 else if (!last
->next
)
2600 /* In the absence of an explicit .body directive,
2601 the prologue ends after the last instruction
2602 covered by an unwind directive. */
2603 if (ptr
->r
.type
!= body
)
2605 last_addr
= last
->slot_number
;
2606 last_frag
= last
->slot_frag
;
2607 switch (last
->r
.type
)
2610 dir_len
= (count_bits (last
->r
.record
.p
.frmask
)
2611 + count_bits (last
->r
.record
.p
.grmask
));
2615 dir_len
+= count_bits (last
->r
.record
.p
.rmask
);
2619 dir_len
+= count_bits (last
->r
.record
.p
.brmask
);
2622 dir_len
+= count_bits (last
->r
.record
.p
.grmask
);
2631 size
= (slot_index (last_addr
, last_frag
, first_addr
, first_frag
)
2633 rlen
= ptr
->r
.record
.r
.rlen
= size
;
2638 ptr
->r
.record
.b
.t
= rlen
- 1 - t
;
2649 case priunat_when_gr
:
2650 case priunat_when_mem
:
2654 ptr
->r
.record
.p
.t
= t
;
2662 case spill_psprel_p
:
2663 ptr
->r
.record
.x
.t
= t
;
2669 as_bad ("frgr_mem record before region record!\n");
2672 region
->r
.record
.r
.mask
.fr_mem
|= ptr
->r
.record
.p
.frmask
;
2673 region
->r
.record
.r
.mask
.gr_mem
|= ptr
->r
.record
.p
.grmask
;
2674 set_imask (region
, ptr
->r
.record
.p
.frmask
, t
, 1);
2675 set_imask (region
, ptr
->r
.record
.p
.grmask
, t
, 2);
2680 as_bad ("fr_mem record before region record!\n");
2683 region
->r
.record
.r
.mask
.fr_mem
|= ptr
->r
.record
.p
.rmask
;
2684 set_imask (region
, ptr
->r
.record
.p
.rmask
, t
, 1);
2689 as_bad ("gr_mem record before region record!\n");
2692 region
->r
.record
.r
.mask
.gr_mem
|= ptr
->r
.record
.p
.rmask
;
2693 set_imask (region
, ptr
->r
.record
.p
.rmask
, t
, 2);
2698 as_bad ("br_mem record before region record!\n");
2701 region
->r
.record
.r
.mask
.br_mem
|= ptr
->r
.record
.p
.brmask
;
2702 set_imask (region
, ptr
->r
.record
.p
.brmask
, t
, 3);
2708 as_bad ("gr_gr record before region record!\n");
2711 set_imask (region
, ptr
->r
.record
.p
.grmask
, t
, 2);
2716 as_bad ("br_gr record before region record!\n");
2719 set_imask (region
, ptr
->r
.record
.p
.brmask
, t
, 3);
2728 /* Generate an unwind image from a record list. Returns the number of
2729 bytes in the resulting image. The memory image itselof is returned
2730 in the 'ptr' parameter. */
2732 output_unw_records (list
, ptr
)
2736 int size
, x
, extra
= 0;
2741 list
= optimize_unw_records (list
);
2742 fixup_unw_records (list
);
2743 size
= calc_record_size (list
);
2745 /* pad to 8 byte boundry. */
2750 if (size
> 0 || unwind
.force_unwind_entry
)
2752 unwind
.force_unwind_entry
= 0;
2754 /* Add 8 for the header + 8 more bytes for the personality offset. */
2755 mem
= xmalloc (size
+ extra
+ 16);
2757 vbyte_mem_ptr
= mem
+ 8;
2758 /* Clear the padding area and personality. */
2759 memset (mem
+ 8 + size
, 0 , extra
+ 8);
2760 /* Initialize the header area. */
2761 md_number_to_chars (mem
,
2762 (((bfd_vma
) 1 << 48) /* version */
2763 | (unwind
.personality_routine
2764 ? ((bfd_vma
) 3 << 32) /* U & E handler flags */
2766 | ((size
+ extra
) / 8)), /* length (dwords) */
2769 process_unw_records (list
, output_vbyte_mem
);
2779 convert_expr_to_ab_reg (e
, ab
, regp
)
2786 if (e
->X_op
!= O_register
)
2789 reg
= e
->X_add_number
;
2790 if (reg
>= (REG_GR
+ 4) && reg
<= (REG_GR
+ 7))
2793 *regp
= reg
- REG_GR
;
2795 else if ((reg
>= (REG_FR
+ 2) && reg
<= (REG_FR
+ 5))
2796 || (reg
>= (REG_FR
+ 16) && reg
<= (REG_FR
+ 31)))
2799 *regp
= reg
- REG_FR
;
2801 else if (reg
>= (REG_BR
+ 1) && reg
<= (REG_BR
+ 5))
2804 *regp
= reg
- REG_BR
;
2811 case REG_PR
: *regp
= 0; break;
2812 case REG_PSP
: *regp
= 1; break;
2813 case REG_PRIUNAT
: *regp
= 2; break;
2814 case REG_BR
+ 0: *regp
= 3; break;
2815 case REG_AR
+ AR_BSP
: *regp
= 4; break;
2816 case REG_AR
+ AR_BSPSTORE
: *regp
= 5; break;
2817 case REG_AR
+ AR_RNAT
: *regp
= 6; break;
2818 case REG_AR
+ AR_UNAT
: *regp
= 7; break;
2819 case REG_AR
+ AR_FPSR
: *regp
= 8; break;
2820 case REG_AR
+ AR_PFS
: *regp
= 9; break;
2821 case REG_AR
+ AR_LC
: *regp
= 10; break;
2831 convert_expr_to_xy_reg (e
, xy
, regp
)
2838 if (e
->X_op
!= O_register
)
2841 reg
= e
->X_add_number
;
2843 if (/* reg >= REG_GR && */ reg
<= (REG_GR
+ 127))
2846 *regp
= reg
- REG_GR
;
2848 else if (reg
>= REG_FR
&& reg
<= (REG_FR
+ 127))
2851 *regp
= reg
- REG_FR
;
2853 else if (reg
>= REG_BR
&& reg
<= (REG_BR
+ 7))
2856 *regp
= reg
- REG_BR
;
2865 int dummy ATTRIBUTE_UNUSED
;
2870 radix
= *input_line_pointer
++;
2872 if (radix
!= 'C' && !is_end_of_line
[(unsigned char) radix
])
2874 as_bad ("Radix `%c' unsupported", *input_line_pointer
);
2875 ignore_rest_of_line ();
2880 /* .sbss, .bss etc. are macros that expand into ".section SECNAME". */
2882 dot_special_section (which
)
2885 set_section ((char *) special_section_name
[which
]);
2889 add_unwind_entry (ptr
)
2893 unwind
.tail
->next
= ptr
;
2898 /* The current entry can in fact be a chain of unwind entries. */
2899 if (unwind
.current_entry
== NULL
)
2900 unwind
.current_entry
= ptr
;
2905 int dummy ATTRIBUTE_UNUSED
;
2911 if (e
.X_op
!= O_constant
)
2912 as_bad ("Operand to .fframe must be a constant");
2914 add_unwind_entry (output_mem_stack_f (e
.X_add_number
));
2919 int dummy ATTRIBUTE_UNUSED
;
2925 reg
= e
.X_add_number
- REG_GR
;
2926 if (e
.X_op
== O_register
&& reg
< 128)
2928 add_unwind_entry (output_mem_stack_v ());
2929 if (! (unwind
.prologue_mask
& 2))
2930 add_unwind_entry (output_psp_gr (reg
));
2933 as_bad ("First operand to .vframe must be a general register");
2937 dot_vframesp (dummy
)
2938 int dummy ATTRIBUTE_UNUSED
;
2943 if (e
.X_op
== O_constant
)
2945 add_unwind_entry (output_mem_stack_v ());
2946 add_unwind_entry (output_psp_sprel (e
.X_add_number
));
2949 as_bad ("First operand to .vframesp must be a general register");
2953 dot_vframepsp (dummy
)
2954 int dummy ATTRIBUTE_UNUSED
;
2959 if (e
.X_op
== O_constant
)
2961 add_unwind_entry (output_mem_stack_v ());
2962 add_unwind_entry (output_psp_sprel (e
.X_add_number
));
2965 as_bad ("First operand to .vframepsp must be a general register");
2970 int dummy ATTRIBUTE_UNUSED
;
2976 sep
= parse_operand (&e1
);
2978 as_bad ("No second operand to .save");
2979 sep
= parse_operand (&e2
);
2981 reg1
= e1
.X_add_number
;
2982 reg2
= e2
.X_add_number
- REG_GR
;
2984 /* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'. */
2985 if (e1
.X_op
== O_register
)
2987 if (e2
.X_op
== O_register
&& reg2
>= 0 && reg2
< 128)
2991 case REG_AR
+ AR_BSP
:
2992 add_unwind_entry (output_bsp_when ());
2993 add_unwind_entry (output_bsp_gr (reg2
));
2995 case REG_AR
+ AR_BSPSTORE
:
2996 add_unwind_entry (output_bspstore_when ());
2997 add_unwind_entry (output_bspstore_gr (reg2
));
2999 case REG_AR
+ AR_RNAT
:
3000 add_unwind_entry (output_rnat_when ());
3001 add_unwind_entry (output_rnat_gr (reg2
));
3003 case REG_AR
+ AR_UNAT
:
3004 add_unwind_entry (output_unat_when ());
3005 add_unwind_entry (output_unat_gr (reg2
));
3007 case REG_AR
+ AR_FPSR
:
3008 add_unwind_entry (output_fpsr_when ());
3009 add_unwind_entry (output_fpsr_gr (reg2
));
3011 case REG_AR
+ AR_PFS
:
3012 add_unwind_entry (output_pfs_when ());
3013 if (! (unwind
.prologue_mask
& 4))
3014 add_unwind_entry (output_pfs_gr (reg2
));
3016 case REG_AR
+ AR_LC
:
3017 add_unwind_entry (output_lc_when ());
3018 add_unwind_entry (output_lc_gr (reg2
));
3021 add_unwind_entry (output_rp_when ());
3022 if (! (unwind
.prologue_mask
& 8))
3023 add_unwind_entry (output_rp_gr (reg2
));
3026 add_unwind_entry (output_preds_when ());
3027 if (! (unwind
.prologue_mask
& 1))
3028 add_unwind_entry (output_preds_gr (reg2
));
3031 add_unwind_entry (output_priunat_when_gr ());
3032 add_unwind_entry (output_priunat_gr (reg2
));
3035 as_bad ("First operand not a valid register");
3039 as_bad (" Second operand not a valid register");
3042 as_bad ("First operand not a register");
3047 int dummy ATTRIBUTE_UNUSED
;
3050 unsigned long ecount
= 0;
3053 sep
= parse_operand (&e1
);
3054 if (e1
.X_op
!= O_register
|| e1
.X_add_number
!= REG_GR
+ 12)
3056 as_bad ("First operand to .restore must be stack pointer (sp)");
3062 parse_operand (&e2
);
3063 if (e1
.X_op
!= O_constant
)
3065 as_bad ("Second operand to .restore must be constant");
3070 add_unwind_entry (output_epilogue (ecount
));
3074 dot_restorereg (dummy
)
3075 int dummy ATTRIBUTE_UNUSED
;
3077 unsigned int ab
, reg
;
3082 if (!convert_expr_to_ab_reg (&e
, &ab
, ®
))
3084 as_bad ("First operand to .restorereg must be a preserved register");
3087 add_unwind_entry (output_spill_reg (ab
, reg
, 0, 0));
3091 dot_restorereg_p (dummy
)
3092 int dummy ATTRIBUTE_UNUSED
;
3094 unsigned int qp
, ab
, reg
;
3098 sep
= parse_operand (&e1
);
3101 as_bad ("No second operand to .restorereg.p");
3105 parse_operand (&e2
);
3107 qp
= e1
.X_add_number
- REG_P
;
3108 if (e1
.X_op
!= O_register
|| qp
> 63)
3110 as_bad ("First operand to .restorereg.p must be a predicate");
3114 if (!convert_expr_to_ab_reg (&e2
, &ab
, ®
))
3116 as_bad ("Second operand to .restorereg.p must be a preserved register");
3119 add_unwind_entry (output_spill_reg_p (ab
, reg
, 0, 0, qp
));
3123 generate_unwind_image (text_name
)
3124 const char *text_name
;
3127 unsigned char *unw_rec
;
3129 /* Force out pending instructions, to make sure all unwind records have
3130 a valid slot_number field. */
3131 ia64_flush_insns ();
3133 /* Generate the unwind record. */
3134 size
= output_unw_records (unwind
.list
, (void **) &unw_rec
);
3136 as_bad ("Unwind record is not a multiple of 8 bytes.");
3138 /* If there are unwind records, switch sections, and output the info. */
3141 unsigned char *where
;
3145 make_unw_section_name (SPECIAL_SECTION_UNWIND_INFO
, text_name
, sec_name
);
3146 set_section (sec_name
);
3147 bfd_set_section_flags (stdoutput
, now_seg
,
3148 SEC_LOAD
| SEC_ALLOC
| SEC_READONLY
);
3150 /* Make sure the section has 8 byte alignment. */
3151 record_alignment (now_seg
, 3);
3153 /* Set expression which points to start of unwind descriptor area. */
3154 unwind
.info
= expr_build_dot ();
3156 where
= (unsigned char *) frag_more (size
);
3158 /* Issue a label for this address, and keep track of it to put it
3159 in the unwind section. */
3161 /* Copy the information from the unwind record into this section. The
3162 data is already in the correct byte order. */
3163 memcpy (where
, unw_rec
, size
);
3165 /* Add the personality address to the image. */
3166 if (unwind
.personality_routine
!= 0)
3168 exp
.X_op
= O_symbol
;
3169 exp
.X_add_symbol
= unwind
.personality_routine
;
3170 exp
.X_add_number
= 0;
3171 fix_new_exp (frag_now
, frag_now_fix () - 8, 8,
3172 &exp
, 0, BFD_RELOC_IA64_LTOFF_FPTR64LSB
);
3173 unwind
.personality_routine
= 0;
3177 free_list_records (unwind
.list
);
3178 unwind
.list
= unwind
.tail
= unwind
.current_entry
= NULL
;
3184 dot_handlerdata (dummy
)
3185 int dummy ATTRIBUTE_UNUSED
;
3187 const char *text_name
= segment_name (now_seg
);
3189 /* If text section name starts with ".text" (which it should),
3190 strip this prefix off. */
3191 if (strcmp (text_name
, ".text") == 0)
3194 unwind
.force_unwind_entry
= 1;
3196 /* Remember which segment we're in so we can switch back after .endp */
3197 unwind
.saved_text_seg
= now_seg
;
3198 unwind
.saved_text_subseg
= now_subseg
;
3200 /* Generate unwind info into unwind-info section and then leave that
3201 section as the currently active one so dataXX directives go into
3202 the language specific data area of the unwind info block. */
3203 generate_unwind_image (text_name
);
3204 demand_empty_rest_of_line ();
3208 dot_unwentry (dummy
)
3209 int dummy ATTRIBUTE_UNUSED
;
3211 unwind
.force_unwind_entry
= 1;
3212 demand_empty_rest_of_line ();
3217 int dummy ATTRIBUTE_UNUSED
;
3223 reg
= e
.X_add_number
- REG_BR
;
3224 if (e
.X_op
== O_register
&& reg
< 8)
3225 add_unwind_entry (output_rp_br (reg
));
3227 as_bad ("First operand not a valid branch register");
3231 dot_savemem (psprel
)
3238 sep
= parse_operand (&e1
);
3240 as_bad ("No second operand to .save%ssp", psprel
? "p" : "");
3241 sep
= parse_operand (&e2
);
3243 reg1
= e1
.X_add_number
;
3244 val
= e2
.X_add_number
;
3246 /* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'. */
3247 if (e1
.X_op
== O_register
)
3249 if (e2
.X_op
== O_constant
)
3253 case REG_AR
+ AR_BSP
:
3254 add_unwind_entry (output_bsp_when ());
3255 add_unwind_entry ((psprel
3257 : output_bsp_sprel
) (val
));
3259 case REG_AR
+ AR_BSPSTORE
:
3260 add_unwind_entry (output_bspstore_when ());
3261 add_unwind_entry ((psprel
3262 ? output_bspstore_psprel
3263 : output_bspstore_sprel
) (val
));
3265 case REG_AR
+ AR_RNAT
:
3266 add_unwind_entry (output_rnat_when ());
3267 add_unwind_entry ((psprel
3268 ? output_rnat_psprel
3269 : output_rnat_sprel
) (val
));
3271 case REG_AR
+ AR_UNAT
:
3272 add_unwind_entry (output_unat_when ());
3273 add_unwind_entry ((psprel
3274 ? output_unat_psprel
3275 : output_unat_sprel
) (val
));
3277 case REG_AR
+ AR_FPSR
:
3278 add_unwind_entry (output_fpsr_when ());
3279 add_unwind_entry ((psprel
3280 ? output_fpsr_psprel
3281 : output_fpsr_sprel
) (val
));
3283 case REG_AR
+ AR_PFS
:
3284 add_unwind_entry (output_pfs_when ());
3285 add_unwind_entry ((psprel
3287 : output_pfs_sprel
) (val
));
3289 case REG_AR
+ AR_LC
:
3290 add_unwind_entry (output_lc_when ());
3291 add_unwind_entry ((psprel
3293 : output_lc_sprel
) (val
));
3296 add_unwind_entry (output_rp_when ());
3297 add_unwind_entry ((psprel
3299 : output_rp_sprel
) (val
));
3302 add_unwind_entry (output_preds_when ());
3303 add_unwind_entry ((psprel
3304 ? output_preds_psprel
3305 : output_preds_sprel
) (val
));
3308 add_unwind_entry (output_priunat_when_mem ());
3309 add_unwind_entry ((psprel
3310 ? output_priunat_psprel
3311 : output_priunat_sprel
) (val
));
3314 as_bad ("First operand not a valid register");
3318 as_bad (" Second operand not a valid constant");
3321 as_bad ("First operand not a register");
3326 int dummy ATTRIBUTE_UNUSED
;
3330 sep
= parse_operand (&e1
);
3332 parse_operand (&e2
);
3334 if (e1
.X_op
!= O_constant
)
3335 as_bad ("First operand to .save.g must be a constant.");
3338 int grmask
= e1
.X_add_number
;
3340 add_unwind_entry (output_gr_mem (grmask
));
3343 int reg
= e2
.X_add_number
- REG_GR
;
3344 if (e2
.X_op
== O_register
&& reg
>= 0 && reg
< 128)
3345 add_unwind_entry (output_gr_gr (grmask
, reg
));
3347 as_bad ("Second operand is an invalid register.");
3354 int dummy ATTRIBUTE_UNUSED
;
3358 sep
= parse_operand (&e1
);
3360 if (e1
.X_op
!= O_constant
)
3361 as_bad ("Operand to .save.f must be a constant.");
3363 add_unwind_entry (output_fr_mem (e1
.X_add_number
));
3368 int dummy ATTRIBUTE_UNUSED
;
3375 sep
= parse_operand (&e1
);
3376 if (e1
.X_op
!= O_constant
)
3378 as_bad ("First operand to .save.b must be a constant.");
3381 brmask
= e1
.X_add_number
;
3385 sep
= parse_operand (&e2
);
3386 reg
= e2
.X_add_number
- REG_GR
;
3387 if (e2
.X_op
!= O_register
|| reg
> 127)
3389 as_bad ("Second operand to .save.b must be a general register.");
3392 add_unwind_entry (output_br_gr (brmask
, e2
.X_add_number
));
3395 add_unwind_entry (output_br_mem (brmask
));
3397 if (!is_end_of_line
[sep
] && !is_it_end_of_statement ())
3398 ignore_rest_of_line ();
3403 int dummy ATTRIBUTE_UNUSED
;
3407 sep
= parse_operand (&e1
);
3409 parse_operand (&e2
);
3411 if (e1
.X_op
!= O_constant
|| sep
!= ',' || e2
.X_op
!= O_constant
)
3412 as_bad ("Both operands of .save.gf must be constants.");
3415 int grmask
= e1
.X_add_number
;
3416 int frmask
= e2
.X_add_number
;
3417 add_unwind_entry (output_frgr_mem (grmask
, frmask
));
3423 int dummy ATTRIBUTE_UNUSED
;
3428 sep
= parse_operand (&e
);
3429 if (!is_end_of_line
[sep
] && !is_it_end_of_statement ())
3430 ignore_rest_of_line ();
3432 if (e
.X_op
!= O_constant
)
3433 as_bad ("Operand to .spill must be a constant");
3435 add_unwind_entry (output_spill_base (e
.X_add_number
));
3439 dot_spillreg (dummy
)
3440 int dummy ATTRIBUTE_UNUSED
;
3442 int sep
, ab
, xy
, reg
, treg
;
3445 sep
= parse_operand (&e1
);
3448 as_bad ("No second operand to .spillreg");
3452 parse_operand (&e2
);
3454 if (!convert_expr_to_ab_reg (&e1
, &ab
, ®
))
3456 as_bad ("First operand to .spillreg must be a preserved register");
3460 if (!convert_expr_to_xy_reg (&e2
, &xy
, &treg
))
3462 as_bad ("Second operand to .spillreg must be a register");
3466 add_unwind_entry (output_spill_reg (ab
, reg
, treg
, xy
));
3470 dot_spillmem (psprel
)
3476 sep
= parse_operand (&e1
);
3479 as_bad ("Second operand missing");
3483 parse_operand (&e2
);
3485 if (!convert_expr_to_ab_reg (&e1
, &ab
, ®
))
3487 as_bad ("First operand to .spill%s must be a preserved register",
3488 psprel
? "psp" : "sp");
3492 if (e2
.X_op
!= O_constant
)
3494 as_bad ("Second operand to .spill%s must be a constant",
3495 psprel
? "psp" : "sp");
3500 add_unwind_entry (output_spill_psprel (ab
, reg
, e2
.X_add_number
));
3502 add_unwind_entry (output_spill_sprel (ab
, reg
, e2
.X_add_number
));
3506 dot_spillreg_p (dummy
)
3507 int dummy ATTRIBUTE_UNUSED
;
3509 int sep
, ab
, xy
, reg
, treg
;
3510 expressionS e1
, e2
, e3
;
3513 sep
= parse_operand (&e1
);
3516 as_bad ("No second and third operand to .spillreg.p");
3520 sep
= parse_operand (&e2
);
3523 as_bad ("No third operand to .spillreg.p");
3527 parse_operand (&e3
);
3529 qp
= e1
.X_add_number
- REG_P
;
3531 if (e1
.X_op
!= O_register
|| qp
> 63)
3533 as_bad ("First operand to .spillreg.p must be a predicate");
3537 if (!convert_expr_to_ab_reg (&e2
, &ab
, ®
))
3539 as_bad ("Second operand to .spillreg.p must be a preserved register");
3543 if (!convert_expr_to_xy_reg (&e3
, &xy
, &treg
))
3545 as_bad ("Third operand to .spillreg.p must be a register");
3549 add_unwind_entry (output_spill_reg_p (ab
, reg
, treg
, xy
, qp
));
3553 dot_spillmem_p (psprel
)
3556 expressionS e1
, e2
, e3
;
3560 sep
= parse_operand (&e1
);
3563 as_bad ("Second operand missing");
3567 parse_operand (&e2
);
3570 as_bad ("Second operand missing");
3574 parse_operand (&e3
);
3576 qp
= e1
.X_add_number
- REG_P
;
3577 if (e1
.X_op
!= O_register
|| qp
> 63)
3579 as_bad ("First operand to .spill%s_p must be a predicate",
3580 psprel
? "psp" : "sp");
3584 if (!convert_expr_to_ab_reg (&e2
, &ab
, ®
))
3586 as_bad ("Second operand to .spill%s_p must be a preserved register",
3587 psprel
? "psp" : "sp");
3591 if (e3
.X_op
!= O_constant
)
3593 as_bad ("Third operand to .spill%s_p must be a constant",
3594 psprel
? "psp" : "sp");
3599 add_unwind_entry (output_spill_psprel_p (qp
, ab
, reg
, e3
.X_add_number
));
3601 add_unwind_entry (output_spill_sprel_p (qp
, ab
, reg
, e3
.X_add_number
));
3605 dot_label_state (dummy
)
3606 int dummy ATTRIBUTE_UNUSED
;
3611 if (e
.X_op
!= O_constant
)
3613 as_bad ("Operand to .label_state must be a constant");
3616 add_unwind_entry (output_label_state (e
.X_add_number
));
3620 dot_copy_state (dummy
)
3621 int dummy ATTRIBUTE_UNUSED
;
3626 if (e
.X_op
!= O_constant
)
3628 as_bad ("Operand to .copy_state must be a constant");
3631 add_unwind_entry (output_copy_state (e
.X_add_number
));
3636 int dummy ATTRIBUTE_UNUSED
;
3641 sep
= parse_operand (&e1
);
3644 as_bad ("Second operand to .unwabi missing");
3647 sep
= parse_operand (&e2
);
3648 if (!is_end_of_line
[sep
] && !is_it_end_of_statement ())
3649 ignore_rest_of_line ();
3651 if (e1
.X_op
!= O_constant
)
3653 as_bad ("First operand to .unwabi must be a constant");
3657 if (e2
.X_op
!= O_constant
)
3659 as_bad ("Second operand to .unwabi must be a constant");
3663 add_unwind_entry (output_unwabi (e1
.X_add_number
, e2
.X_add_number
));
3667 dot_personality (dummy
)
3668 int dummy ATTRIBUTE_UNUSED
;
3672 name
= input_line_pointer
;
3673 c
= get_symbol_end ();
3674 p
= input_line_pointer
;
3675 unwind
.personality_routine
= symbol_find_or_make (name
);
3676 unwind
.force_unwind_entry
= 1;
3679 demand_empty_rest_of_line ();
3684 int dummy ATTRIBUTE_UNUSED
;
3689 unwind
.proc_start
= expr_build_dot ();
3690 /* Parse names of main and alternate entry points and mark them as
3691 function symbols: */
3695 name
= input_line_pointer
;
3696 c
= get_symbol_end ();
3697 p
= input_line_pointer
;
3698 sym
= symbol_find_or_make (name
);
3699 if (unwind
.proc_start
== 0)
3701 unwind
.proc_start
= sym
;
3703 symbol_get_bfdsym (sym
)->flags
|= BSF_FUNCTION
;
3706 if (*input_line_pointer
!= ',')
3708 ++input_line_pointer
;
3710 demand_empty_rest_of_line ();
3713 unwind
.list
= unwind
.tail
= unwind
.current_entry
= NULL
;
3714 unwind
.personality_routine
= 0;
3719 int dummy ATTRIBUTE_UNUSED
;
3721 unwind
.prologue
= 0;
3722 unwind
.prologue_mask
= 0;
3724 add_unwind_entry (output_body ());
3725 demand_empty_rest_of_line ();
3729 dot_prologue (dummy
)
3730 int dummy ATTRIBUTE_UNUSED
;
3733 int mask
= 0, grsave
= 0;
3735 if (!is_it_end_of_statement ())
3738 sep
= parse_operand (&e1
);
3740 as_bad ("No second operand to .prologue");
3741 sep
= parse_operand (&e2
);
3742 if (!is_end_of_line
[sep
] && !is_it_end_of_statement ())
3743 ignore_rest_of_line ();
3745 if (e1
.X_op
== O_constant
)
3747 mask
= e1
.X_add_number
;
3749 if (e2
.X_op
== O_constant
)
3750 grsave
= e2
.X_add_number
;
3751 else if (e2
.X_op
== O_register
3752 && (grsave
= e2
.X_add_number
- REG_GR
) < 128)
3755 as_bad ("Second operand not a constant or general register");
3757 add_unwind_entry (output_prologue_gr (mask
, grsave
));
3760 as_bad ("First operand not a constant");
3763 add_unwind_entry (output_prologue ());
3765 unwind
.prologue
= 1;
3766 unwind
.prologue_mask
= mask
;
3771 int dummy ATTRIBUTE_UNUSED
;
3775 int bytes_per_address
;
3778 subsegT saved_subseg
;
3779 const char *sec_name
, *text_name
;
3781 if (unwind
.saved_text_seg
)
3783 saved_seg
= unwind
.saved_text_seg
;
3784 saved_subseg
= unwind
.saved_text_subseg
;
3785 unwind
.saved_text_seg
= NULL
;
3789 saved_seg
= now_seg
;
3790 saved_subseg
= now_subseg
;
3794 Use a slightly ugly scheme to derive the unwind section names from
3795 the text section name:
3797 text sect. unwind table sect.
3798 name: name: comments:
3799 ---------- ----------------- --------------------------------
3801 .text.foo .IA_64.unwind.text.foo
3802 .foo .IA_64.unwind.foo
3803 _info .IA_64.unwind_info gas issues error message (ditto)
3804 _infoFOO .IA_64.unwind_infoFOO gas issues error message (ditto)
3806 This mapping is done so that:
3808 (a) An object file with unwind info only in .text will use
3809 unwind section names .IA_64.unwind and .IA_64.unwind_info.
3810 This follows the letter of the ABI and also ensures backwards
3811 compatibility with older toolchains.
3813 (b) An object file with unwind info in multiple text sections
3814 will use separate unwind sections for each text section.
3815 This allows us to properly set the "sh_info" and "sh_link"
3816 fields in SHT_IA_64_UNWIND as required by the ABI and also
3817 lets GNU ld support programs with multiple segments
3818 containing unwind info (as might be the case for certain
3819 embedded applications).
3821 (c) An error is issued if there would be a name clash.
3823 text_name
= segment_name (saved_seg
);
3824 if (strncmp (text_name
, "_info", 5) == 0)
3826 as_bad ("Illegal section name `%s' (causes unwind section name clash)",
3828 ignore_rest_of_line ();
3831 if (strcmp (text_name
, ".text") == 0)
3835 demand_empty_rest_of_line ();
3837 insn_group_break (1, 0, 0);
3839 /* If there wasn't a .handlerdata, we haven't generated an image yet. */
3841 generate_unwind_image (text_name
);
3843 if (unwind
.info
|| unwind
.force_unwind_entry
)
3845 subseg_set (md
.last_text_seg
, 0);
3846 unwind
.proc_end
= expr_build_dot ();
3848 make_unw_section_name (SPECIAL_SECTION_UNWIND
, text_name
, sec_name
);
3849 set_section ((char *) sec_name
);
3850 bfd_set_section_flags (stdoutput
, now_seg
,
3851 SEC_LOAD
| SEC_ALLOC
| SEC_READONLY
);
3853 /* Make sure the section has 8 byte alignment. */
3854 record_alignment (now_seg
, 3);
3856 ptr
= frag_more (24);
3857 where
= frag_now_fix () - 24;
3858 bytes_per_address
= bfd_arch_bits_per_address (stdoutput
) / 8;
3860 /* Issue the values of a) Proc Begin, b) Proc End, c) Unwind Record. */
3861 e
.X_op
= O_pseudo_fixup
;
3862 e
.X_op_symbol
= pseudo_func
[FUNC_SEG_RELATIVE
].u
.sym
;
3864 e
.X_add_symbol
= unwind
.proc_start
;
3865 ia64_cons_fix_new (frag_now
, where
, bytes_per_address
, &e
);
3867 e
.X_op
= O_pseudo_fixup
;
3868 e
.X_op_symbol
= pseudo_func
[FUNC_SEG_RELATIVE
].u
.sym
;
3870 e
.X_add_symbol
= unwind
.proc_end
;
3871 ia64_cons_fix_new (frag_now
, where
+ bytes_per_address
,
3872 bytes_per_address
, &e
);
3876 e
.X_op
= O_pseudo_fixup
;
3877 e
.X_op_symbol
= pseudo_func
[FUNC_SEG_RELATIVE
].u
.sym
;
3879 e
.X_add_symbol
= unwind
.info
;
3880 ia64_cons_fix_new (frag_now
, where
+ (bytes_per_address
* 2),
3881 bytes_per_address
, &e
);
3884 md_number_to_chars (ptr
+ (bytes_per_address
* 2), 0,
3888 subseg_set (saved_seg
, saved_subseg
);
3889 unwind
.proc_start
= unwind
.proc_end
= unwind
.info
= 0;
3893 dot_template (template)
3896 CURR_SLOT
.user_template
= template;
3901 int dummy ATTRIBUTE_UNUSED
;
3903 int ins
, locs
, outs
, rots
;
3905 if (is_it_end_of_statement ())
3906 ins
= locs
= outs
= rots
= 0;
3909 ins
= get_absolute_expression ();
3910 if (*input_line_pointer
++ != ',')
3912 locs
= get_absolute_expression ();
3913 if (*input_line_pointer
++ != ',')
3915 outs
= get_absolute_expression ();
3916 if (*input_line_pointer
++ != ',')
3918 rots
= get_absolute_expression ();
3920 set_regstack (ins
, locs
, outs
, rots
);
3924 as_bad ("Comma expected");
3925 ignore_rest_of_line ();
3932 unsigned num_regs
, num_alloced
= 0;
3933 struct dynreg
**drpp
, *dr
;
3934 int ch
, base_reg
= 0;
3940 case DYNREG_GR
: base_reg
= REG_GR
+ 32; break;
3941 case DYNREG_FR
: base_reg
= REG_FR
+ 32; break;
3942 case DYNREG_PR
: base_reg
= REG_P
+ 16; break;
3946 /* First, remove existing names from hash table. */
3947 for (dr
= md
.dynreg
[type
]; dr
&& dr
->num_regs
; dr
= dr
->next
)
3949 hash_delete (md
.dynreg_hash
, dr
->name
);
3953 drpp
= &md
.dynreg
[type
];
3956 start
= input_line_pointer
;
3957 ch
= get_symbol_end ();
3958 *input_line_pointer
= ch
;
3959 len
= (input_line_pointer
- start
);
3962 if (*input_line_pointer
!= '[')
3964 as_bad ("Expected '['");
3967 ++input_line_pointer
; /* skip '[' */
3969 num_regs
= get_absolute_expression ();
3971 if (*input_line_pointer
++ != ']')
3973 as_bad ("Expected ']'");
3978 num_alloced
+= num_regs
;
3982 if (num_alloced
> md
.rot
.num_regs
)
3984 as_bad ("Used more than the declared %d rotating registers",
3990 if (num_alloced
> 96)
3992 as_bad ("Used more than the available 96 rotating registers");
3997 if (num_alloced
> 48)
3999 as_bad ("Used more than the available 48 rotating registers");
4008 name
= obstack_alloc (¬es
, len
+ 1);
4009 memcpy (name
, start
, len
);
4014 *drpp
= obstack_alloc (¬es
, sizeof (*dr
));
4015 memset (*drpp
, 0, sizeof (*dr
));
4020 dr
->num_regs
= num_regs
;
4021 dr
->base
= base_reg
;
4023 base_reg
+= num_regs
;
4025 if (hash_insert (md
.dynreg_hash
, name
, dr
))
4027 as_bad ("Attempt to redefine register set `%s'", name
);
4031 if (*input_line_pointer
!= ',')
4033 ++input_line_pointer
; /* skip comma */
4036 demand_empty_rest_of_line ();
4040 ignore_rest_of_line ();
4044 dot_byteorder (byteorder
)
4047 target_big_endian
= byteorder
;
4052 int dummy ATTRIBUTE_UNUSED
;
4059 option
= input_line_pointer
;
4060 ch
= get_symbol_end ();
4061 if (strcmp (option
, "lsb") == 0)
4062 md
.flags
&= ~EF_IA_64_BE
;
4063 else if (strcmp (option
, "msb") == 0)
4064 md
.flags
|= EF_IA_64_BE
;
4065 else if (strcmp (option
, "abi32") == 0)
4066 md
.flags
&= ~EF_IA_64_ABI64
;
4067 else if (strcmp (option
, "abi64") == 0)
4068 md
.flags
|= EF_IA_64_ABI64
;
4070 as_bad ("Unknown psr option `%s'", option
);
4071 *input_line_pointer
= ch
;
4074 if (*input_line_pointer
!= ',')
4077 ++input_line_pointer
;
4080 demand_empty_rest_of_line ();
4085 int dummy ATTRIBUTE_UNUSED
;
4087 as_bad (".alias not implemented yet");
4092 int dummy ATTRIBUTE_UNUSED
;
4094 new_logical_line (0, get_absolute_expression ());
4095 demand_empty_rest_of_line ();
4099 parse_section_name ()
4105 if (*input_line_pointer
!= '"')
4107 as_bad ("Missing section name");
4108 ignore_rest_of_line ();
4111 name
= demand_copy_C_string (&len
);
4114 ignore_rest_of_line ();
4118 if (*input_line_pointer
!= ',')
4120 as_bad ("Comma expected after section name");
4121 ignore_rest_of_line ();
4124 ++input_line_pointer
; /* skip comma */
4132 char *name
= parse_section_name ();
4138 obj_elf_previous (0);
4141 /* Why doesn't float_cons() call md_cons_align() the way cons() does? */
4144 stmt_float_cons (kind
)
4151 case 'd': size
= 8; break;
4152 case 'x': size
= 10; break;
4159 ia64_do_align (size
);
4167 int saved_auto_align
= md
.auto_align
;
4171 md
.auto_align
= saved_auto_align
;
4175 dot_xfloat_cons (kind
)
4178 char *name
= parse_section_name ();
4183 stmt_float_cons (kind
);
4184 obj_elf_previous (0);
4188 dot_xstringer (zero
)
4191 char *name
= parse_section_name ();
4197 obj_elf_previous (0);
4204 int saved_auto_align
= md
.auto_align
;
4205 char *name
= parse_section_name ();
4212 md
.auto_align
= saved_auto_align
;
4213 obj_elf_previous (0);
4217 dot_xfloat_cons_ua (kind
)
4220 int saved_auto_align
= md
.auto_align
;
4221 char *name
= parse_section_name ();
4227 stmt_float_cons (kind
);
4228 md
.auto_align
= saved_auto_align
;
4229 obj_elf_previous (0);
4232 /* .reg.val <regname>,value */
4236 int dummy ATTRIBUTE_UNUSED
;
4241 if (reg
.X_op
!= O_register
)
4243 as_bad (_("Register name expected"));
4244 ignore_rest_of_line ();
4246 else if (*input_line_pointer
++ != ',')
4248 as_bad (_("Comma expected"));
4249 ignore_rest_of_line ();
4253 valueT value
= get_absolute_expression ();
4254 int regno
= reg
.X_add_number
;
4255 if (regno
< REG_GR
|| regno
> REG_GR
+ 128)
4256 as_warn (_("Register value annotation ignored"));
4259 gr_values
[regno
- REG_GR
].known
= 1;
4260 gr_values
[regno
- REG_GR
].value
= value
;
4261 gr_values
[regno
- REG_GR
].path
= md
.path
;
4264 demand_empty_rest_of_line ();
4267 /* select dv checking mode
4272 A stop is inserted when changing modes
4279 if (md
.manual_bundling
)
4280 as_warn (_("Directive invalid within a bundle"));
4282 if (type
== 'E' || type
== 'A')
4283 md
.mode_explicitly_set
= 0;
4285 md
.mode_explicitly_set
= 1;
4292 if (md
.explicit_mode
)
4293 insn_group_break (1, 0, 0);
4294 md
.explicit_mode
= 0;
4298 if (!md
.explicit_mode
)
4299 insn_group_break (1, 0, 0);
4300 md
.explicit_mode
= 1;
4304 if (md
.explicit_mode
!= md
.default_explicit_mode
)
4305 insn_group_break (1, 0, 0);
4306 md
.explicit_mode
= md
.default_explicit_mode
;
4307 md
.mode_explicitly_set
= 0;
4318 for (regno
= 0; regno
< 64; regno
++)
4320 if (mask
& ((valueT
) 1 << regno
))
4322 fprintf (stderr
, "%s p%d", comma
, regno
);
4329 .pred.rel.clear [p1 [,p2 [,...]]] (also .pred.rel "clear")
4330 .pred.rel.imply p1, p2 (also .pred.rel "imply")
4331 .pred.rel.mutex p1, p2 [,...] (also .pred.rel "mutex")
4332 .pred.safe_across_calls p1 [, p2 [,...]]
4341 int p1
= -1, p2
= -1;
4345 if (*input_line_pointer
!= '"')
4347 as_bad (_("Missing predicate relation type"));
4348 ignore_rest_of_line ();
4354 char *form
= demand_copy_C_string (&len
);
4355 if (strcmp (form
, "mutex") == 0)
4357 else if (strcmp (form
, "clear") == 0)
4359 else if (strcmp (form
, "imply") == 0)
4363 as_bad (_("Unrecognized predicate relation type"));
4364 ignore_rest_of_line ();
4368 if (*input_line_pointer
== ',')
4369 ++input_line_pointer
;
4379 if (toupper (*input_line_pointer
) != 'P'
4380 || (regno
= atoi (++input_line_pointer
)) < 0
4383 as_bad (_("Predicate register expected"));
4384 ignore_rest_of_line ();
4387 while (isdigit (*input_line_pointer
))
4388 ++input_line_pointer
;
4395 as_warn (_("Duplicate predicate register ignored"));
4398 /* See if it's a range. */
4399 if (*input_line_pointer
== '-')
4402 ++input_line_pointer
;
4404 if (toupper (*input_line_pointer
) != 'P'
4405 || (regno
= atoi (++input_line_pointer
)) < 0
4408 as_bad (_("Predicate register expected"));
4409 ignore_rest_of_line ();
4412 while (isdigit (*input_line_pointer
))
4413 ++input_line_pointer
;
4417 as_bad (_("Bad register range"));
4418 ignore_rest_of_line ();
4429 if (*input_line_pointer
!= ',')
4431 ++input_line_pointer
;
4440 clear_qp_mutex (mask
);
4441 clear_qp_implies (mask
, (valueT
) 0);
4444 if (count
!= 2 || p1
== -1 || p2
== -1)
4445 as_bad (_("Predicate source and target required"));
4446 else if (p1
== 0 || p2
== 0)
4447 as_bad (_("Use of p0 is not valid in this context"));
4449 add_qp_imply (p1
, p2
);
4454 as_bad (_("At least two PR arguments expected"));
4459 as_bad (_("Use of p0 is not valid in this context"));
4462 add_qp_mutex (mask
);
4465 /* note that we don't override any existing relations */
4468 as_bad (_("At least one PR argument expected"));
4473 fprintf (stderr
, "Safe across calls: ");
4474 print_prmask (mask
);
4475 fprintf (stderr
, "\n");
4477 qp_safe_across_calls
= mask
;
4480 demand_empty_rest_of_line ();
4483 /* .entry label [, label [, ...]]
4484 Hint to DV code that the given labels are to be considered entry points.
4485 Otherwise, only global labels are considered entry points. */
4489 int dummy ATTRIBUTE_UNUSED
;
4498 name
= input_line_pointer
;
4499 c
= get_symbol_end ();
4500 symbolP
= symbol_find_or_make (name
);
4502 err
= hash_insert (md
.entry_hash
, S_GET_NAME (symbolP
), (PTR
) symbolP
);
4504 as_fatal (_("Inserting \"%s\" into entry hint table failed: %s"),
4507 *input_line_pointer
= c
;
4509 c
= *input_line_pointer
;
4512 input_line_pointer
++;
4514 if (*input_line_pointer
== '\n')
4520 demand_empty_rest_of_line ();
4523 /* .mem.offset offset, base
4524 "base" is used to distinguish between offsets from a different base. */
4527 dot_mem_offset (dummy
)
4528 int dummy ATTRIBUTE_UNUSED
;
4530 md
.mem_offset
.hint
= 1;
4531 md
.mem_offset
.offset
= get_absolute_expression ();
4532 if (*input_line_pointer
!= ',')
4534 as_bad (_("Comma expected"));
4535 ignore_rest_of_line ();
4538 ++input_line_pointer
;
4539 md
.mem_offset
.base
= get_absolute_expression ();
4540 demand_empty_rest_of_line ();
4543 /* ia64-specific pseudo-ops: */
4544 const pseudo_typeS md_pseudo_table
[] =
4546 { "radix", dot_radix
, 0 },
4547 { "lcomm", s_lcomm_bytes
, 1 },
4548 { "bss", dot_special_section
, SPECIAL_SECTION_BSS
},
4549 { "sbss", dot_special_section
, SPECIAL_SECTION_SBSS
},
4550 { "sdata", dot_special_section
, SPECIAL_SECTION_SDATA
},
4551 { "rodata", dot_special_section
, SPECIAL_SECTION_RODATA
},
4552 { "comment", dot_special_section
, SPECIAL_SECTION_COMMENT
},
4553 { "ia_64.unwind", dot_special_section
, SPECIAL_SECTION_UNWIND
},
4554 { "ia_64.unwind_info", dot_special_section
, SPECIAL_SECTION_UNWIND_INFO
},
4555 { "proc", dot_proc
, 0 },
4556 { "body", dot_body
, 0 },
4557 { "prologue", dot_prologue
, 0 },
4558 { "endp", dot_endp
, 0 },
4559 { "file", dwarf2_directive_file
, 0 },
4560 { "loc", dwarf2_directive_loc
, 0 },
4562 { "fframe", dot_fframe
, 0 },
4563 { "vframe", dot_vframe
, 0 },
4564 { "vframesp", dot_vframesp
, 0 },
4565 { "vframepsp", dot_vframepsp
, 0 },
4566 { "save", dot_save
, 0 },
4567 { "restore", dot_restore
, 0 },
4568 { "restorereg", dot_restorereg
, 0 },
4569 { "restorereg.p", dot_restorereg_p
, 0 },
4570 { "handlerdata", dot_handlerdata
, 0 },
4571 { "unwentry", dot_unwentry
, 0 },
4572 { "altrp", dot_altrp
, 0 },
4573 { "savesp", dot_savemem
, 0 },
4574 { "savepsp", dot_savemem
, 1 },
4575 { "save.g", dot_saveg
, 0 },
4576 { "save.f", dot_savef
, 0 },
4577 { "save.b", dot_saveb
, 0 },
4578 { "save.gf", dot_savegf
, 0 },
4579 { "spill", dot_spill
, 0 },
4580 { "spillreg", dot_spillreg
, 0 },
4581 { "spillsp", dot_spillmem
, 0 },
4582 { "spillpsp", dot_spillmem
, 1 },
4583 { "spillreg.p", dot_spillreg_p
, 0 },
4584 { "spillsp.p", dot_spillmem_p
, 0 },
4585 { "spillpsp.p", dot_spillmem_p
, 1 },
4586 { "label_state", dot_label_state
, 0 },
4587 { "copy_state", dot_copy_state
, 0 },
4588 { "unwabi", dot_unwabi
, 0 },
4589 { "personality", dot_personality
, 0 },
4591 { "estate", dot_estate
, 0 },
4593 { "mii", dot_template
, 0x0 },
4594 { "mli", dot_template
, 0x2 }, /* old format, for compatibility */
4595 { "mlx", dot_template
, 0x2 },
4596 { "mmi", dot_template
, 0x4 },
4597 { "mfi", dot_template
, 0x6 },
4598 { "mmf", dot_template
, 0x7 },
4599 { "mib", dot_template
, 0x8 },
4600 { "mbb", dot_template
, 0x9 },
4601 { "bbb", dot_template
, 0xb },
4602 { "mmb", dot_template
, 0xc },
4603 { "mfb", dot_template
, 0xe },
4605 { "lb", dot_scope
, 0 },
4606 { "le", dot_scope
, 1 },
4608 { "align", s_align_bytes
, 0 },
4609 { "regstk", dot_regstk
, 0 },
4610 { "rotr", dot_rot
, DYNREG_GR
},
4611 { "rotf", dot_rot
, DYNREG_FR
},
4612 { "rotp", dot_rot
, DYNREG_PR
},
4613 { "lsb", dot_byteorder
, 0 },
4614 { "msb", dot_byteorder
, 1 },
4615 { "psr", dot_psr
, 0 },
4616 { "alias", dot_alias
, 0 },
4617 { "ln", dot_ln
, 0 }, /* source line info (for debugging) */
4619 { "xdata1", dot_xdata
, 1 },
4620 { "xdata2", dot_xdata
, 2 },
4621 { "xdata4", dot_xdata
, 4 },
4622 { "xdata8", dot_xdata
, 8 },
4623 { "xreal4", dot_xfloat_cons
, 'f' },
4624 { "xreal8", dot_xfloat_cons
, 'd' },
4625 { "xreal10", dot_xfloat_cons
, 'x' },
4626 { "xstring", dot_xstringer
, 0 },
4627 { "xstringz", dot_xstringer
, 1 },
4629 /* unaligned versions: */
4630 { "xdata2.ua", dot_xdata_ua
, 2 },
4631 { "xdata4.ua", dot_xdata_ua
, 4 },
4632 { "xdata8.ua", dot_xdata_ua
, 8 },
4633 { "xreal4.ua", dot_xfloat_cons_ua
, 'f' },
4634 { "xreal8.ua", dot_xfloat_cons_ua
, 'd' },
4635 { "xreal10.ua", dot_xfloat_cons_ua
, 'x' },
4637 /* annotations/DV checking support */
4638 { "entry", dot_entry
, 0 },
4639 { "mem.offset", dot_mem_offset
, 0 },
4640 { "pred.rel", dot_pred_rel
, 0 },
4641 { "pred.rel.clear", dot_pred_rel
, 'c' },
4642 { "pred.rel.imply", dot_pred_rel
, 'i' },
4643 { "pred.rel.mutex", dot_pred_rel
, 'm' },
4644 { "pred.safe_across_calls", dot_pred_rel
, 's' },
4645 { "reg.val", dot_reg_val
, 0 },
4646 { "auto", dot_dv_mode
, 'a' },
4647 { "explicit", dot_dv_mode
, 'e' },
4648 { "default", dot_dv_mode
, 'd' },
4653 static const struct pseudo_opcode
4656 void (*handler
) (int);
4661 /* these are more like pseudo-ops, but don't start with a dot */
4662 { "data1", cons
, 1 },
4663 { "data2", cons
, 2 },
4664 { "data4", cons
, 4 },
4665 { "data8", cons
, 8 },
4666 { "real4", stmt_float_cons
, 'f' },
4667 { "real8", stmt_float_cons
, 'd' },
4668 { "real10", stmt_float_cons
, 'x' },
4669 { "string", stringer
, 0 },
4670 { "stringz", stringer
, 1 },
4672 /* unaligned versions: */
4673 { "data2.ua", stmt_cons_ua
, 2 },
4674 { "data4.ua", stmt_cons_ua
, 4 },
4675 { "data8.ua", stmt_cons_ua
, 8 },
4676 { "real4.ua", float_cons
, 'f' },
4677 { "real8.ua", float_cons
, 'd' },
4678 { "real10.ua", float_cons
, 'x' },
4681 /* Declare a register by creating a symbol for it and entering it in
4682 the symbol table. */
4685 declare_register (name
, regnum
)
4692 sym
= symbol_new (name
, reg_section
, regnum
, &zero_address_frag
);
4694 err
= hash_insert (md
.reg_hash
, S_GET_NAME (sym
), (PTR
) sym
);
4696 as_fatal ("Inserting \"%s\" into register table failed: %s",
4703 declare_register_set (prefix
, num_regs
, base_regnum
)
4711 for (i
= 0; i
< num_regs
; ++i
)
4713 sprintf (name
, "%s%u", prefix
, i
);
4714 declare_register (name
, base_regnum
+ i
);
4719 operand_width (opnd
)
4720 enum ia64_opnd opnd
;
4722 const struct ia64_operand
*odesc
= &elf64_ia64_operands
[opnd
];
4723 unsigned int bits
= 0;
4727 for (i
= 0; i
< NELEMS (odesc
->field
) && odesc
->field
[i
].bits
; ++i
)
4728 bits
+= odesc
->field
[i
].bits
;
4734 operand_match (idesc
, index
, e
)
4735 const struct ia64_opcode
*idesc
;
4739 enum ia64_opnd opnd
= idesc
->operands
[index
];
4740 int bits
, relocatable
= 0;
4741 struct insn_fix
*fix
;
4748 case IA64_OPND_AR_CCV
:
4749 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_AR
+ 32)
4753 case IA64_OPND_AR_PFS
:
4754 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_AR
+ 64)
4759 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_GR
+ 0)
4764 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_IP
)
4769 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_PR
)
4773 case IA64_OPND_PR_ROT
:
4774 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_PR_ROT
)
4779 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_PSR
)
4783 case IA64_OPND_PSR_L
:
4784 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_PSR_L
)
4788 case IA64_OPND_PSR_UM
:
4789 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_PSR_UM
)
4794 if (e
->X_op
== O_constant
&& e
->X_add_number
== 1)
4799 if (e
->X_op
== O_constant
&& e
->X_add_number
== 8)
4804 if (e
->X_op
== O_constant
&& e
->X_add_number
== 16)
4808 /* register operands: */
4811 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_AR
4812 && e
->X_add_number
< REG_AR
+ 128)
4818 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_BR
4819 && e
->X_add_number
< REG_BR
+ 8)
4824 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_CR
4825 && e
->X_add_number
< REG_CR
+ 128)
4833 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_FR
4834 && e
->X_add_number
< REG_FR
+ 128)
4840 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_P
4841 && e
->X_add_number
< REG_P
+ 64)
4848 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_GR
4849 && e
->X_add_number
< REG_GR
+ 128)
4853 case IA64_OPND_R3_2
:
4854 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_GR
4855 && e
->X_add_number
< REG_GR
+ 4)
4859 /* indirect operands: */
4860 case IA64_OPND_CPUID_R3
:
4861 case IA64_OPND_DBR_R3
:
4862 case IA64_OPND_DTR_R3
:
4863 case IA64_OPND_ITR_R3
:
4864 case IA64_OPND_IBR_R3
:
4865 case IA64_OPND_MSR_R3
:
4866 case IA64_OPND_PKR_R3
:
4867 case IA64_OPND_PMC_R3
:
4868 case IA64_OPND_PMD_R3
:
4869 case IA64_OPND_RR_R3
:
4870 if (e
->X_op
== O_index
&& e
->X_op_symbol
4871 && (S_GET_VALUE (e
->X_op_symbol
) - IND_CPUID
4872 == opnd
- IA64_OPND_CPUID_R3
))
4877 if (e
->X_op
== O_index
&& !e
->X_op_symbol
)
4881 /* immediate operands: */
4882 case IA64_OPND_CNT2a
:
4883 case IA64_OPND_LEN4
:
4884 case IA64_OPND_LEN6
:
4885 bits
= operand_width (idesc
->operands
[index
]);
4886 if (e
->X_op
== O_constant
4887 && (bfd_vma
) (e
->X_add_number
- 1) < ((bfd_vma
) 1 << bits
))
4891 case IA64_OPND_CNT2b
:
4892 if (e
->X_op
== O_constant
4893 && (bfd_vma
) (e
->X_add_number
- 1) < 3)
4897 case IA64_OPND_CNT2c
:
4898 val
= e
->X_add_number
;
4899 if (e
->X_op
== O_constant
4900 && (val
== 0 || val
== 7 || val
== 15 || val
== 16))
4905 /* SOR must be an integer multiple of 8 */
4906 if (e
->X_add_number
& 0x7)
4910 if (e
->X_op
== O_constant
&&
4911 (bfd_vma
) e
->X_add_number
<= 96)
4915 case IA64_OPND_IMMU62
:
4916 if (e
->X_op
== O_constant
)
4918 if ((bfd_vma
) e
->X_add_number
< ((bfd_vma
) 1 << 62))
4923 /* FIXME -- need 62-bit relocation type */
4924 as_bad (_("62-bit relocation not yet implemented"));
4928 case IA64_OPND_IMMU64
:
4929 if (e
->X_op
== O_symbol
|| e
->X_op
== O_pseudo_fixup
4930 || e
->X_op
== O_subtract
)
4932 fix
= CURR_SLOT
.fixup
+ CURR_SLOT
.num_fixups
;
4933 fix
->code
= BFD_RELOC_IA64_IMM64
;
4934 if (e
->X_op
!= O_subtract
)
4936 fix
->code
= ia64_gen_real_reloc_type (e
->X_op_symbol
, fix
->code
);
4937 if (e
->X_op
== O_pseudo_fixup
)
4941 fix
->opnd
= idesc
->operands
[index
];
4944 ++CURR_SLOT
.num_fixups
;
4947 else if (e
->X_op
== O_constant
)
4951 case IA64_OPND_CCNT5
:
4952 case IA64_OPND_CNT5
:
4953 case IA64_OPND_CNT6
:
4954 case IA64_OPND_CPOS6a
:
4955 case IA64_OPND_CPOS6b
:
4956 case IA64_OPND_CPOS6c
:
4957 case IA64_OPND_IMMU2
:
4958 case IA64_OPND_IMMU7a
:
4959 case IA64_OPND_IMMU7b
:
4960 case IA64_OPND_IMMU21
:
4961 case IA64_OPND_IMMU24
:
4962 case IA64_OPND_MBTYPE4
:
4963 case IA64_OPND_MHTYPE8
:
4964 case IA64_OPND_POS6
:
4965 bits
= operand_width (idesc
->operands
[index
]);
4966 if (e
->X_op
== O_constant
4967 && (bfd_vma
) e
->X_add_number
< ((bfd_vma
) 1 << bits
))
4971 case IA64_OPND_IMMU9
:
4972 bits
= operand_width (idesc
->operands
[index
]);
4973 if (e
->X_op
== O_constant
4974 && (bfd_vma
) e
->X_add_number
< ((bfd_vma
) 1 << bits
))
4976 int lobits
= e
->X_add_number
& 0x3;
4977 if (((bfd_vma
) e
->X_add_number
& 0x3C) != 0 && lobits
== 0)
4978 e
->X_add_number
|= (bfd_vma
) 0x3;
4983 case IA64_OPND_IMM44
:
4984 /* least 16 bits must be zero */
4985 if ((e
->X_add_number
& 0xffff) != 0)
4986 as_warn (_("lower 16 bits of mask ignored"));
4988 if (e
->X_op
== O_constant
4989 && ((e
->X_add_number
>= 0
4990 && (bfd_vma
) e
->X_add_number
< ((bfd_vma
) 1 << 44))
4991 || (e
->X_add_number
< 0
4992 && (bfd_vma
) -e
->X_add_number
<= ((bfd_vma
) 1 << 44))))
4995 if (e
->X_add_number
>= 0
4996 && (e
->X_add_number
& ((bfd_vma
) 1 << 43)) != 0)
4998 e
->X_add_number
|= ~(((bfd_vma
) 1 << 44) - 1);
5004 case IA64_OPND_IMM17
:
5005 /* bit 0 is a don't care (pr0 is hardwired to 1) */
5006 if (e
->X_op
== O_constant
5007 && ((e
->X_add_number
>= 0
5008 && (bfd_vma
) e
->X_add_number
< ((bfd_vma
) 1 << 17))
5009 || (e
->X_add_number
< 0
5010 && (bfd_vma
) -e
->X_add_number
<= ((bfd_vma
) 1 << 17))))
5013 if (e
->X_add_number
>= 0
5014 && (e
->X_add_number
& ((bfd_vma
) 1 << 16)) != 0)
5016 e
->X_add_number
|= ~(((bfd_vma
) 1 << 17) - 1);
5022 case IA64_OPND_IMM14
:
5023 case IA64_OPND_IMM22
:
5025 case IA64_OPND_IMM1
:
5026 case IA64_OPND_IMM8
:
5027 case IA64_OPND_IMM8U4
:
5028 case IA64_OPND_IMM8M1
:
5029 case IA64_OPND_IMM8M1U4
:
5030 case IA64_OPND_IMM8M1U8
:
5031 case IA64_OPND_IMM9a
:
5032 case IA64_OPND_IMM9b
:
5033 bits
= operand_width (idesc
->operands
[index
]);
5034 if (relocatable
&& (e
->X_op
== O_symbol
5035 || e
->X_op
== O_subtract
5036 || e
->X_op
== O_pseudo_fixup
))
5038 fix
= CURR_SLOT
.fixup
+ CURR_SLOT
.num_fixups
;
5040 if (idesc
->operands
[index
] == IA64_OPND_IMM14
)
5041 fix
->code
= BFD_RELOC_IA64_IMM14
;
5043 fix
->code
= BFD_RELOC_IA64_IMM22
;
5045 if (e
->X_op
!= O_subtract
)
5047 fix
->code
= ia64_gen_real_reloc_type (e
->X_op_symbol
, fix
->code
);
5048 if (e
->X_op
== O_pseudo_fixup
)
5052 fix
->opnd
= idesc
->operands
[index
];
5055 ++CURR_SLOT
.num_fixups
;
5058 else if (e
->X_op
!= O_constant
5059 && ! (e
->X_op
== O_big
&& opnd
== IA64_OPND_IMM8M1U8
))
5062 if (opnd
== IA64_OPND_IMM8M1U4
)
5064 /* Zero is not valid for unsigned compares that take an adjusted
5065 constant immediate range. */
5066 if (e
->X_add_number
== 0)
5069 /* Sign-extend 32-bit unsigned numbers, so that the following range
5070 checks will work. */
5071 val
= e
->X_add_number
;
5072 if (((val
& (~(bfd_vma
) 0 << 32)) == 0)
5073 && ((val
& ((bfd_vma
) 1 << 31)) != 0))
5074 val
= ((val
<< 32) >> 32);
5076 /* Check for 0x100000000. This is valid because
5077 0x100000000-1 is the same as ((uint32_t) -1). */
5078 if (val
== ((bfd_signed_vma
) 1 << 32))
5083 else if (opnd
== IA64_OPND_IMM8M1U8
)
5085 /* Zero is not valid for unsigned compares that take an adjusted
5086 constant immediate range. */
5087 if (e
->X_add_number
== 0)
5090 /* Check for 0x10000000000000000. */
5091 if (e
->X_op
== O_big
)
5093 if (generic_bignum
[0] == 0
5094 && generic_bignum
[1] == 0
5095 && generic_bignum
[2] == 0
5096 && generic_bignum
[3] == 0
5097 && generic_bignum
[4] == 1)
5103 val
= e
->X_add_number
- 1;
5105 else if (opnd
== IA64_OPND_IMM8M1
)
5106 val
= e
->X_add_number
- 1;
5107 else if (opnd
== IA64_OPND_IMM8U4
)
5109 /* Sign-extend 32-bit unsigned numbers, so that the following range
5110 checks will work. */
5111 val
= e
->X_add_number
;
5112 if (((val
& (~(bfd_vma
) 0 << 32)) == 0)
5113 && ((val
& ((bfd_vma
) 1 << 31)) != 0))
5114 val
= ((val
<< 32) >> 32);
5117 val
= e
->X_add_number
;
5119 if ((val
>= 0 && (bfd_vma
) val
< ((bfd_vma
) 1 << (bits
- 1)))
5120 || (val
< 0 && (bfd_vma
) -val
<= ((bfd_vma
) 1 << (bits
- 1))))
5124 case IA64_OPND_INC3
:
5125 /* +/- 1, 4, 8, 16 */
5126 val
= e
->X_add_number
;
5129 if (e
->X_op
== O_constant
5130 && (val
== 1 || val
== 4 || val
== 8 || val
== 16))
5134 case IA64_OPND_TGT25
:
5135 case IA64_OPND_TGT25b
:
5136 case IA64_OPND_TGT25c
:
5137 case IA64_OPND_TGT64
:
5138 if (e
->X_op
== O_symbol
)
5140 fix
= CURR_SLOT
.fixup
+ CURR_SLOT
.num_fixups
;
5141 if (opnd
== IA64_OPND_TGT25
)
5142 fix
->code
= BFD_RELOC_IA64_PCREL21F
;
5143 else if (opnd
== IA64_OPND_TGT25b
)
5144 fix
->code
= BFD_RELOC_IA64_PCREL21M
;
5145 else if (opnd
== IA64_OPND_TGT25c
)
5146 fix
->code
= BFD_RELOC_IA64_PCREL21B
;
5147 else if (opnd
== IA64_OPND_TGT64
)
5148 fix
->code
= BFD_RELOC_IA64_PCREL60B
;
5152 fix
->code
= ia64_gen_real_reloc_type (e
->X_op_symbol
, fix
->code
);
5153 fix
->opnd
= idesc
->operands
[index
];
5156 ++CURR_SLOT
.num_fixups
;
5159 case IA64_OPND_TAG13
:
5160 case IA64_OPND_TAG13b
:
5167 fix
= CURR_SLOT
.fixup
+ CURR_SLOT
.num_fixups
;
5168 fix
->code
= ia64_gen_real_reloc_type (e
->X_op_symbol
, 0);
5169 fix
->opnd
= idesc
->operands
[index
];
5172 ++CURR_SLOT
.num_fixups
;
5192 memset (e
, 0, sizeof (*e
));
5195 if (*input_line_pointer
!= '}')
5197 sep
= *input_line_pointer
++;
5201 if (!md
.manual_bundling
)
5202 as_warn ("Found '}' when manual bundling is off");
5204 CURR_SLOT
.manual_bundling_off
= 1;
5205 md
.manual_bundling
= 0;
5211 /* Returns the next entry in the opcode table that matches the one in
5212 IDESC, and frees the entry in IDESC. If no matching entry is
5213 found, NULL is returned instead. */
5215 static struct ia64_opcode
*
5216 get_next_opcode (struct ia64_opcode
*idesc
)
5218 struct ia64_opcode
*next
= ia64_find_next_opcode (idesc
);
5219 ia64_free_opcode (idesc
);
5223 /* Parse the operands for the opcode and find the opcode variant that
5224 matches the specified operands, or NULL if no match is possible. */
5226 static struct ia64_opcode
*
5227 parse_operands (idesc
)
5228 struct ia64_opcode
*idesc
;
5230 int i
= 0, highest_unmatched_operand
, num_operands
= 0, num_outputs
= 0;
5232 enum ia64_opnd expected_operand
= IA64_OPND_NIL
;
5234 char *first_arg
= 0, *end
, *saved_input_pointer
;
5237 assert (strlen (idesc
->name
) <= 128);
5239 strcpy (mnemonic
, idesc
->name
);
5240 if (idesc
->operands
[2] == IA64_OPND_SOF
)
5242 /* To make the common idiom "alloc loc?=ar.pfs,0,1,0,0" work, we
5243 can't parse the first operand until we have parsed the
5244 remaining operands of the "alloc" instruction. */
5246 first_arg
= input_line_pointer
;
5247 end
= strchr (input_line_pointer
, '=');
5250 as_bad ("Expected separator `='");
5253 input_line_pointer
= end
+ 1;
5258 for (; i
< NELEMS (CURR_SLOT
.opnd
); ++i
)
5260 sep
= parse_operand (CURR_SLOT
.opnd
+ i
);
5261 if (CURR_SLOT
.opnd
[i
].X_op
== O_absent
)
5266 if (sep
!= '=' && sep
!= ',')
5271 if (num_outputs
> 0)
5272 as_bad ("Duplicate equal sign (=) in instruction");
5274 num_outputs
= i
+ 1;
5279 as_bad ("Illegal operand separator `%c'", sep
);
5283 if (idesc
->operands
[2] == IA64_OPND_SOF
)
5285 /* map alloc r1=ar.pfs,i,l,o,r to alloc r1=ar.pfs,(i+l+o),(i+l),r */
5286 know (strcmp (idesc
->name
, "alloc") == 0);
5287 if (num_operands
== 5 /* first_arg not included in this count! */
5288 && CURR_SLOT
.opnd
[2].X_op
== O_constant
5289 && CURR_SLOT
.opnd
[3].X_op
== O_constant
5290 && CURR_SLOT
.opnd
[4].X_op
== O_constant
5291 && CURR_SLOT
.opnd
[5].X_op
== O_constant
)
5293 sof
= set_regstack (CURR_SLOT
.opnd
[2].X_add_number
,
5294 CURR_SLOT
.opnd
[3].X_add_number
,
5295 CURR_SLOT
.opnd
[4].X_add_number
,
5296 CURR_SLOT
.opnd
[5].X_add_number
);
5298 /* now we can parse the first arg: */
5299 saved_input_pointer
= input_line_pointer
;
5300 input_line_pointer
= first_arg
;
5301 sep
= parse_operand (CURR_SLOT
.opnd
+ 0);
5303 --num_outputs
; /* force error */
5304 input_line_pointer
= saved_input_pointer
;
5306 CURR_SLOT
.opnd
[2].X_add_number
= sof
;
5307 CURR_SLOT
.opnd
[3].X_add_number
5308 = sof
- CURR_SLOT
.opnd
[4].X_add_number
;
5309 CURR_SLOT
.opnd
[4] = CURR_SLOT
.opnd
[5];
5313 highest_unmatched_operand
= 0;
5314 expected_operand
= idesc
->operands
[0];
5315 for (; idesc
; idesc
= get_next_opcode (idesc
))
5317 if (num_outputs
!= idesc
->num_outputs
)
5318 continue; /* mismatch in # of outputs */
5320 CURR_SLOT
.num_fixups
= 0;
5321 for (i
= 0; i
< num_operands
&& idesc
->operands
[i
]; ++i
)
5322 if (!operand_match (idesc
, i
, CURR_SLOT
.opnd
+ i
))
5325 if (i
!= num_operands
)
5327 if (i
> highest_unmatched_operand
)
5329 highest_unmatched_operand
= i
;
5330 expected_operand
= idesc
->operands
[i
];
5335 if (num_operands
< NELEMS (idesc
->operands
)
5336 && idesc
->operands
[num_operands
])
5337 continue; /* mismatch in number of arguments */
5343 if (expected_operand
)
5344 as_bad ("Operand %u of `%s' should be %s",
5345 highest_unmatched_operand
+ 1, mnemonic
,
5346 elf64_ia64_operands
[expected_operand
].desc
);
5348 as_bad ("Operand mismatch");
5354 /* Keep track of state necessary to determine whether a NOP is necessary
5355 to avoid an erratum in A and B step Itanium chips, and return 1 if we
5356 detect a case where additional NOPs may be necessary. */
5358 errata_nop_necessary_p (slot
, insn_unit
)
5360 enum ia64_unit insn_unit
;
5363 struct group
*this_group
= md
.last_groups
+ md
.group_idx
;
5364 struct group
*prev_group
= md
.last_groups
+ (md
.group_idx
+ 2) % 3;
5365 struct ia64_opcode
*idesc
= slot
->idesc
;
5367 /* Test whether this could be the first insn in a problematic sequence. */
5368 if (insn_unit
== IA64_UNIT_F
)
5370 for (i
= 0; i
< idesc
->num_outputs
; i
++)
5371 if (idesc
->operands
[i
] == IA64_OPND_P1
5372 || idesc
->operands
[i
] == IA64_OPND_P2
)
5374 int regno
= slot
->opnd
[i
].X_add_number
- REG_P
;
5375 /* Ignore invalid operands; they generate errors elsewhere. */
5378 this_group
->p_reg_set
[regno
] = 1;
5382 /* Test whether this could be the second insn in a problematic sequence. */
5383 if (insn_unit
== IA64_UNIT_M
&& slot
->qp_regno
> 0
5384 && prev_group
->p_reg_set
[slot
->qp_regno
])
5386 for (i
= 0; i
< idesc
->num_outputs
; i
++)
5387 if (idesc
->operands
[i
] == IA64_OPND_R1
5388 || idesc
->operands
[i
] == IA64_OPND_R2
5389 || idesc
->operands
[i
] == IA64_OPND_R3
)
5391 int regno
= slot
->opnd
[i
].X_add_number
- REG_GR
;
5392 /* Ignore invalid operands; they generate errors elsewhere. */
5395 if (strncmp (idesc
->name
, "add", 3) != 0
5396 && strncmp (idesc
->name
, "sub", 3) != 0
5397 && strncmp (idesc
->name
, "shladd", 6) != 0
5398 && (idesc
->flags
& IA64_OPCODE_POSTINC
) == 0)
5399 this_group
->g_reg_set_conditionally
[regno
] = 1;
5403 /* Test whether this could be the third insn in a problematic sequence. */
5404 for (i
= 0; i
< NELEMS (idesc
->operands
) && idesc
->operands
[i
]; i
++)
5406 if (/* For fc, ptc, ptr, tak, thash, tpa, ttag, probe, ptr, ptc. */
5407 idesc
->operands
[i
] == IA64_OPND_R3
5408 /* For mov indirect. */
5409 || idesc
->operands
[i
] == IA64_OPND_RR_R3
5410 || idesc
->operands
[i
] == IA64_OPND_DBR_R3
5411 || idesc
->operands
[i
] == IA64_OPND_IBR_R3
5412 || idesc
->operands
[i
] == IA64_OPND_PKR_R3
5413 || idesc
->operands
[i
] == IA64_OPND_PMC_R3
5414 || idesc
->operands
[i
] == IA64_OPND_PMD_R3
5415 || idesc
->operands
[i
] == IA64_OPND_MSR_R3
5416 || idesc
->operands
[i
] == IA64_OPND_CPUID_R3
5418 || idesc
->operands
[i
] == IA64_OPND_ITR_R3
5419 || idesc
->operands
[i
] == IA64_OPND_DTR_R3
5420 /* Normal memory addresses (load, store, xchg, cmpxchg, etc.). */
5421 || idesc
->operands
[i
] == IA64_OPND_MR3
)
5423 int regno
= slot
->opnd
[i
].X_add_number
- REG_GR
;
5424 /* Ignore invalid operands; they generate errors elsewhere. */
5427 if (idesc
->operands
[i
] == IA64_OPND_R3
)
5429 if (strcmp (idesc
->name
, "fc") != 0
5430 && strcmp (idesc
->name
, "tak") != 0
5431 && strcmp (idesc
->name
, "thash") != 0
5432 && strcmp (idesc
->name
, "tpa") != 0
5433 && strcmp (idesc
->name
, "ttag") != 0
5434 && strncmp (idesc
->name
, "ptr", 3) != 0
5435 && strncmp (idesc
->name
, "ptc", 3) != 0
5436 && strncmp (idesc
->name
, "probe", 5) != 0)
5439 if (prev_group
->g_reg_set_conditionally
[regno
])
5447 build_insn (slot
, insnp
)
5451 const struct ia64_operand
*odesc
, *o2desc
;
5452 struct ia64_opcode
*idesc
= slot
->idesc
;
5453 bfd_signed_vma insn
, val
;
5457 insn
= idesc
->opcode
| slot
->qp_regno
;
5459 for (i
= 0; i
< NELEMS (idesc
->operands
) && idesc
->operands
[i
]; ++i
)
5461 if (slot
->opnd
[i
].X_op
== O_register
5462 || slot
->opnd
[i
].X_op
== O_constant
5463 || slot
->opnd
[i
].X_op
== O_index
)
5464 val
= slot
->opnd
[i
].X_add_number
;
5465 else if (slot
->opnd
[i
].X_op
== O_big
)
5467 /* This must be the value 0x10000000000000000. */
5468 assert (idesc
->operands
[i
] == IA64_OPND_IMM8M1U8
);
5474 switch (idesc
->operands
[i
])
5476 case IA64_OPND_IMMU64
:
5477 *insnp
++ = (val
>> 22) & 0x1ffffffffffLL
;
5478 insn
|= (((val
& 0x7f) << 13) | (((val
>> 7) & 0x1ff) << 27)
5479 | (((val
>> 16) & 0x1f) << 22) | (((val
>> 21) & 0x1) << 21)
5480 | (((val
>> 63) & 0x1) << 36));
5483 case IA64_OPND_IMMU62
:
5484 val
&= 0x3fffffffffffffffULL
;
5485 if (val
!= slot
->opnd
[i
].X_add_number
)
5486 as_warn (_("Value truncated to 62 bits"));
5487 *insnp
++ = (val
>> 21) & 0x1ffffffffffLL
;
5488 insn
|= (((val
& 0xfffff) << 6) | (((val
>> 20) & 0x1) << 36));
5491 case IA64_OPND_TGT64
:
5493 *insnp
++ = ((val
>> 20) & 0x7fffffffffLL
) << 2;
5494 insn
|= ((((val
>> 59) & 0x1) << 36)
5495 | (((val
>> 0) & 0xfffff) << 13));
5526 case IA64_OPND_R3_2
:
5527 case IA64_OPND_CPUID_R3
:
5528 case IA64_OPND_DBR_R3
:
5529 case IA64_OPND_DTR_R3
:
5530 case IA64_OPND_ITR_R3
:
5531 case IA64_OPND_IBR_R3
:
5533 case IA64_OPND_MSR_R3
:
5534 case IA64_OPND_PKR_R3
:
5535 case IA64_OPND_PMC_R3
:
5536 case IA64_OPND_PMD_R3
:
5537 case IA64_OPND_RR_R3
:
5545 odesc
= elf64_ia64_operands
+ idesc
->operands
[i
];
5546 err
= (*odesc
->insert
) (odesc
, val
, &insn
);
5548 as_bad_where (slot
->src_file
, slot
->src_line
,
5549 "Bad operand value: %s", err
);
5550 if (idesc
->flags
& IA64_OPCODE_PSEUDO
)
5552 if ((idesc
->flags
& IA64_OPCODE_F2_EQ_F3
)
5553 && odesc
== elf64_ia64_operands
+ IA64_OPND_F3
)
5555 o2desc
= elf64_ia64_operands
+ IA64_OPND_F2
;
5556 (*o2desc
->insert
) (o2desc
, val
, &insn
);
5558 if ((idesc
->flags
& IA64_OPCODE_LEN_EQ_64MCNT
)
5559 && (odesc
== elf64_ia64_operands
+ IA64_OPND_CPOS6a
5560 || odesc
== elf64_ia64_operands
+ IA64_OPND_POS6
))
5562 o2desc
= elf64_ia64_operands
+ IA64_OPND_LEN6
;
5563 (*o2desc
->insert
) (o2desc
, 64 - val
, &insn
);
5573 unsigned int manual_bundling_on
= 0, manual_bundling_off
= 0;
5574 unsigned int manual_bundling
= 0;
5575 enum ia64_unit required_unit
, insn_unit
= 0;
5576 enum ia64_insn_type type
[3], insn_type
;
5577 unsigned int template, orig_template
;
5578 bfd_vma insn
[3] = { -1, -1, -1 };
5579 struct ia64_opcode
*idesc
;
5580 int end_of_insn_group
= 0, user_template
= -1;
5581 int n
, i
, j
, first
, curr
;
5583 bfd_vma t0
= 0, t1
= 0;
5584 struct label_fix
*lfix
;
5585 struct insn_fix
*ifix
;
5590 first
= (md
.curr_slot
+ NUM_SLOTS
- md
.num_slots_in_use
) % NUM_SLOTS
;
5591 know (first
>= 0 & first
< NUM_SLOTS
);
5592 n
= MIN (3, md
.num_slots_in_use
);
5594 /* Determine template: user user_template if specified, best match
5597 if (md
.slot
[first
].user_template
>= 0)
5598 user_template
= template = md
.slot
[first
].user_template
;
5601 /* Auto select appropriate template. */
5602 memset (type
, 0, sizeof (type
));
5604 for (i
= 0; i
< n
; ++i
)
5606 if (md
.slot
[curr
].label_fixups
&& i
!= 0)
5608 type
[i
] = md
.slot
[curr
].idesc
->type
;
5609 curr
= (curr
+ 1) % NUM_SLOTS
;
5611 template = best_template
[type
[0]][type
[1]][type
[2]];
5614 /* initialize instructions with appropriate nops: */
5615 for (i
= 0; i
< 3; ++i
)
5616 insn
[i
] = nop
[ia64_templ_desc
[template].exec_unit
[i
]];
5620 /* now fill in slots with as many insns as possible: */
5622 idesc
= md
.slot
[curr
].idesc
;
5623 end_of_insn_group
= 0;
5624 for (i
= 0; i
< 3 && md
.num_slots_in_use
> 0; ++i
)
5626 /* Set the slot number for prologue/body records now as those
5627 refer to the current point, not the point after the
5628 instruction has been issued: */
5629 /* Don't try to delete prologue/body records here, as that will cause
5630 them to also be deleted from the master list of unwind records. */
5631 for (ptr
= md
.slot
[curr
].unwind_record
; ptr
; ptr
= ptr
->next
)
5632 if (ptr
->r
.type
== prologue
|| ptr
->r
.type
== prologue_gr
5633 || ptr
->r
.type
== body
)
5635 ptr
->slot_number
= (unsigned long) f
+ i
;
5636 ptr
->slot_frag
= frag_now
;
5639 if (idesc
->flags
& IA64_OPCODE_SLOT2
)
5641 if (manual_bundling
&& i
!= 2)
5642 as_bad_where (md
.slot
[curr
].src_file
, md
.slot
[curr
].src_line
,
5643 "`%s' must be last in bundle", idesc
->name
);
5647 if (idesc
->flags
& IA64_OPCODE_LAST
)
5650 unsigned int required_template
;
5652 /* If we need a stop bit after an M slot, our only choice is
5653 template 5 (M;;MI). If we need a stop bit after a B
5654 slot, our only choice is to place it at the end of the
5655 bundle, because the only available templates are MIB,
5656 MBB, BBB, MMB, and MFB. We don't handle anything other
5657 than M and B slots because these are the only kind of
5658 instructions that can have the IA64_OPCODE_LAST bit set. */
5659 required_template
= template;
5660 switch (idesc
->type
)
5664 required_template
= 5;
5672 as_bad_where (md
.slot
[curr
].src_file
, md
.slot
[curr
].src_line
,
5673 "Internal error: don't know how to force %s to end"
5674 "of instruction group", idesc
->name
);
5678 if (manual_bundling
&& i
!= required_slot
)
5679 as_bad_where (md
.slot
[curr
].src_file
, md
.slot
[curr
].src_line
,
5680 "`%s' must be last in instruction group",
5682 if (required_slot
< i
)
5683 /* Can't fit this instruction. */
5687 if (required_template
!= template)
5689 /* If we switch the template, we need to reset the NOPs
5690 after slot i. The slot-types of the instructions ahead
5691 of i never change, so we don't need to worry about
5692 changing NOPs in front of this slot. */
5693 for (j
= i
; j
< 3; ++j
)
5694 insn
[j
] = nop
[ia64_templ_desc
[required_template
].exec_unit
[j
]];
5696 template = required_template
;
5698 if (curr
!= first
&& md
.slot
[curr
].label_fixups
)
5700 if (manual_bundling_on
)
5701 as_bad_where (md
.slot
[curr
].src_file
, md
.slot
[curr
].src_line
,
5702 "Label must be first in a bundle");
5703 /* This insn must go into the first slot of a bundle. */
5707 manual_bundling_on
= md
.slot
[curr
].manual_bundling_on
;
5708 manual_bundling_off
= md
.slot
[curr
].manual_bundling_off
;
5710 if (manual_bundling_on
)
5713 manual_bundling
= 1;
5715 break; /* need to start a new bundle */
5718 if (end_of_insn_group
&& md
.num_slots_in_use
>= 1)
5720 /* We need an instruction group boundary in the middle of a
5721 bundle. See if we can switch to an other template with
5722 an appropriate boundary. */
5724 orig_template
= template;
5725 if (i
== 1 && (user_template
== 4
5726 || (user_template
< 0
5727 && (ia64_templ_desc
[template].exec_unit
[0]
5731 end_of_insn_group
= 0;
5733 else if (i
== 2 && (user_template
== 0
5734 || (user_template
< 0
5735 && (ia64_templ_desc
[template].exec_unit
[1]
5737 /* This test makes sure we don't switch the template if
5738 the next instruction is one that needs to be first in
5739 an instruction group. Since all those instructions are
5740 in the M group, there is no way such an instruction can
5741 fit in this bundle even if we switch the template. The
5742 reason we have to check for this is that otherwise we
5743 may end up generating "MI;;I M.." which has the deadly
5744 effect that the second M instruction is no longer the
5745 first in the bundle! --davidm 99/12/16 */
5746 && (idesc
->flags
& IA64_OPCODE_FIRST
) == 0)
5749 end_of_insn_group
= 0;
5751 else if (curr
!= first
)
5752 /* can't fit this insn */
5755 if (template != orig_template
)
5756 /* if we switch the template, we need to reset the NOPs
5757 after slot i. The slot-types of the instructions ahead
5758 of i never change, so we don't need to worry about
5759 changing NOPs in front of this slot. */
5760 for (j
= i
; j
< 3; ++j
)
5761 insn
[j
] = nop
[ia64_templ_desc
[template].exec_unit
[j
]];
5763 required_unit
= ia64_templ_desc
[template].exec_unit
[i
];
5765 /* resolve dynamic opcodes such as "break" and "nop": */
5766 if (idesc
->type
== IA64_TYPE_DYN
)
5768 if ((strcmp (idesc
->name
, "nop") == 0)
5769 || (strcmp (idesc
->name
, "break") == 0))
5770 insn_unit
= required_unit
;
5771 else if (strcmp (idesc
->name
, "chk.s") == 0)
5773 insn_unit
= IA64_UNIT_M
;
5774 if (required_unit
== IA64_UNIT_I
)
5775 insn_unit
= IA64_UNIT_I
;
5778 as_fatal ("emit_one_bundle: unexpected dynamic op");
5780 sprintf (mnemonic
, "%s.%c", idesc
->name
, "?imbf??"[insn_unit
]);
5781 ia64_free_opcode (idesc
);
5782 md
.slot
[curr
].idesc
= idesc
= ia64_find_opcode (mnemonic
);
5784 know (!idesc
->next
); /* no resolved dynamic ops have collisions */
5789 insn_type
= idesc
->type
;
5790 insn_unit
= IA64_UNIT_NIL
;
5794 if (required_unit
== IA64_UNIT_I
|| required_unit
== IA64_UNIT_M
)
5795 insn_unit
= required_unit
;
5797 case IA64_TYPE_X
: insn_unit
= IA64_UNIT_L
; break;
5798 case IA64_TYPE_I
: insn_unit
= IA64_UNIT_I
; break;
5799 case IA64_TYPE_M
: insn_unit
= IA64_UNIT_M
; break;
5800 case IA64_TYPE_B
: insn_unit
= IA64_UNIT_B
; break;
5801 case IA64_TYPE_F
: insn_unit
= IA64_UNIT_F
; break;
5806 if (insn_unit
!= required_unit
)
5808 if (required_unit
== IA64_UNIT_L
5809 && insn_unit
== IA64_UNIT_I
5810 && !(idesc
->flags
& IA64_OPCODE_X_IN_MLX
))
5812 /* we got ourselves an MLX template but the current
5813 instruction isn't an X-unit, or an I-unit instruction
5814 that can go into the X slot of an MLX template. Duh. */
5815 if (md
.num_slots_in_use
>= NUM_SLOTS
)
5817 as_bad_where (md
.slot
[curr
].src_file
,
5818 md
.slot
[curr
].src_line
,
5819 "`%s' can't go in X slot of "
5820 "MLX template", idesc
->name
);
5821 /* drop this insn so we don't livelock: */
5822 --md
.num_slots_in_use
;
5826 continue; /* try next slot */
5832 addr
= frag_now
->fr_address
+ frag_now_fix () - 16 + i
;
5833 dwarf2_gen_line_info (addr
, &md
.slot
[curr
].debug_line
);
5836 if (errata_nop_necessary_p (md
.slot
+ curr
, insn_unit
))
5837 as_warn (_("Additional NOP may be necessary to workaround Itanium processor A/B step errata"));
5839 build_insn (md
.slot
+ curr
, insn
+ i
);
5841 /* Set slot counts for non prologue/body unwind records. */
5842 for (ptr
= md
.slot
[curr
].unwind_record
; ptr
; ptr
= ptr
->next
)
5843 if (ptr
->r
.type
!= prologue
&& ptr
->r
.type
!= prologue_gr
5844 && ptr
->r
.type
!= body
)
5846 ptr
->slot_number
= (unsigned long) f
+ i
;
5847 ptr
->slot_frag
= frag_now
;
5849 md
.slot
[curr
].unwind_record
= NULL
;
5851 if (required_unit
== IA64_UNIT_L
)
5854 /* skip one slot for long/X-unit instructions */
5857 --md
.num_slots_in_use
;
5859 /* now is a good time to fix up the labels for this insn: */
5860 for (lfix
= md
.slot
[curr
].label_fixups
; lfix
; lfix
= lfix
->next
)
5862 S_SET_VALUE (lfix
->sym
, frag_now_fix () - 16);
5863 symbol_set_frag (lfix
->sym
, frag_now
);
5865 /* and fix up the tags also. */
5866 for (lfix
= md
.slot
[curr
].tag_fixups
; lfix
; lfix
= lfix
->next
)
5868 S_SET_VALUE (lfix
->sym
, frag_now_fix () - 16 + i
);
5869 symbol_set_frag (lfix
->sym
, frag_now
);
5872 for (j
= 0; j
< md
.slot
[curr
].num_fixups
; ++j
)
5874 ifix
= md
.slot
[curr
].fixup
+ j
;
5875 fix
= fix_new_exp (frag_now
, frag_now_fix () - 16 + i
, 8,
5876 &ifix
->expr
, ifix
->is_pcrel
, ifix
->code
);
5877 fix
->tc_fix_data
.opnd
= ifix
->opnd
;
5878 fix
->fx_plt
= (fix
->fx_r_type
== BFD_RELOC_IA64_PLTOFF22
);
5879 fix
->fx_file
= md
.slot
[curr
].src_file
;
5880 fix
->fx_line
= md
.slot
[curr
].src_line
;
5883 end_of_insn_group
= md
.slot
[curr
].end_of_insn_group
;
5885 if (end_of_insn_group
)
5887 md
.group_idx
= (md
.group_idx
+ 1) % 3;
5888 memset (md
.last_groups
+ md
.group_idx
, 0, sizeof md
.last_groups
[0]);
5892 ia64_free_opcode (md
.slot
[curr
].idesc
);
5893 memset (md
.slot
+ curr
, 0, sizeof (md
.slot
[curr
]));
5894 md
.slot
[curr
].user_template
= -1;
5896 if (manual_bundling_off
)
5898 manual_bundling
= 0;
5901 curr
= (curr
+ 1) % NUM_SLOTS
;
5902 idesc
= md
.slot
[curr
].idesc
;
5904 if (manual_bundling
)
5906 if (md
.num_slots_in_use
> 0)
5907 as_bad_where (md
.slot
[curr
].src_file
, md
.slot
[curr
].src_line
,
5908 "`%s' does not fit into %s template",
5909 idesc
->name
, ia64_templ_desc
[template].name
);
5911 as_bad_where (md
.slot
[curr
].src_file
, md
.slot
[curr
].src_line
,
5912 "Missing '}' at end of file");
5914 know (md
.num_slots_in_use
< NUM_SLOTS
);
5916 t0
= end_of_insn_group
| (template << 1) | (insn
[0] << 5) | (insn
[1] << 46);
5917 t1
= ((insn
[1] >> 18) & 0x7fffff) | (insn
[2] << 23);
5919 number_to_chars_littleendian (f
+ 0, t0
, 8);
5920 number_to_chars_littleendian (f
+ 8, t1
, 8);
5922 unwind
.next_slot_number
= (unsigned long) f
+ 16;
5923 unwind
.next_slot_frag
= frag_now
;
5927 md_parse_option (c
, arg
)
5933 /* Switches from the Intel assembler. */
5935 if (strcmp (arg
, "ilp64") == 0
5936 || strcmp (arg
, "lp64") == 0
5937 || strcmp (arg
, "p64") == 0)
5939 md
.flags
|= EF_IA_64_ABI64
;
5941 else if (strcmp (arg
, "ilp32") == 0)
5943 md
.flags
&= ~EF_IA_64_ABI64
;
5945 else if (strcmp (arg
, "le") == 0)
5947 md
.flags
&= ~EF_IA_64_BE
;
5949 else if (strcmp (arg
, "be") == 0)
5951 md
.flags
|= EF_IA_64_BE
;
5958 if (strcmp (arg
, "so") == 0)
5960 /* Suppress signon message. */
5962 else if (strcmp (arg
, "pi") == 0)
5964 /* Reject privileged instructions. FIXME */
5966 else if (strcmp (arg
, "us") == 0)
5968 /* Allow union of signed and unsigned range. FIXME */
5970 else if (strcmp (arg
, "close_fcalls") == 0)
5972 /* Do not resolve global function calls. */
5979 /* temp[="prefix"] Insert temporary labels into the object file
5980 symbol table prefixed by "prefix".
5981 Default prefix is ":temp:".
5986 /* indirect=<tgt> Assume unannotated indirect branches behavior
5987 according to <tgt> --
5988 exit: branch out from the current context (default)
5989 labels: all labels in context may be branch targets
5991 if (strncmp (arg
, "indirect=", 9) != 0)
5996 /* -X conflicts with an ignored option, use -x instead */
5998 if (!arg
|| strcmp (arg
, "explicit") == 0)
6000 /* set default mode to explicit */
6001 md
.default_explicit_mode
= 1;
6004 else if (strcmp (arg
, "auto") == 0)
6006 md
.default_explicit_mode
= 0;
6008 else if (strcmp (arg
, "debug") == 0)
6012 else if (strcmp (arg
, "debugx") == 0)
6014 md
.default_explicit_mode
= 1;
6019 as_bad (_("Unrecognized option '-x%s'"), arg
);
6024 /* nops Print nops statistics. */
6027 /* GNU specific switches for gcc. */
6028 case OPTION_MCONSTANT_GP
:
6029 md
.flags
|= EF_IA_64_CONS_GP
;
6032 case OPTION_MAUTO_PIC
:
6033 md
.flags
|= EF_IA_64_NOFUNCDESC_CONS_GP
;
6044 md_show_usage (stream
)
6049 -milp32|-milp64|-mlp64|-mp64 select data model (default -mlp64)\n\
6050 -mle | -mbe select little- or big-endian byte order (default -mle)\n\
6051 -x | -xexplicit turn on dependency violation checking (default)\n\
6052 -xauto automagically remove dependency violations\n\
6053 -xdebug debug dependency violation checker\n"),
6057 /* Return true if TYPE fits in TEMPL at SLOT. */
6060 match (int templ
, int type
, int slot
)
6062 enum ia64_unit unit
;
6065 unit
= ia64_templ_desc
[templ
].exec_unit
[slot
];
6068 case IA64_TYPE_DYN
: result
= 1; break; /* for nop and break */
6070 result
= (unit
== IA64_UNIT_I
|| unit
== IA64_UNIT_M
);
6072 case IA64_TYPE_X
: result
= (unit
== IA64_UNIT_L
); break;
6073 case IA64_TYPE_I
: result
= (unit
== IA64_UNIT_I
); break;
6074 case IA64_TYPE_M
: result
= (unit
== IA64_UNIT_M
); break;
6075 case IA64_TYPE_B
: result
= (unit
== IA64_UNIT_B
); break;
6076 case IA64_TYPE_F
: result
= (unit
== IA64_UNIT_F
); break;
6077 default: result
= 0; break;
6082 /* Add a bit of extra goodness if a nop of type F or B would fit
6083 in TEMPL at SLOT. */
6086 extra_goodness (int templ
, int slot
)
6088 if (slot
== 1 && match (templ
, IA64_TYPE_F
, slot
))
6090 if (slot
== 2 && match (templ
, IA64_TYPE_B
, slot
))
6095 /* This function is called once, at assembler startup time. It sets
6096 up all the tables, etc. that the MD part of the assembler will need
6097 that can be determined before arguments are parsed. */
6101 int i
, j
, k
, t
, total
, ar_base
, cr_base
, goodness
, best
, regnum
, ok
;
6106 md
.explicit_mode
= md
.default_explicit_mode
;
6108 bfd_set_section_alignment (stdoutput
, text_section
, 4);
6110 target_big_endian
= TARGET_BYTES_BIG_ENDIAN
;
6111 pseudo_func
[FUNC_FPTR_RELATIVE
].u
.sym
=
6112 symbol_new (".<fptr>", undefined_section
, FUNC_FPTR_RELATIVE
,
6113 &zero_address_frag
);
6115 pseudo_func
[FUNC_GP_RELATIVE
].u
.sym
=
6116 symbol_new (".<gprel>", undefined_section
, FUNC_GP_RELATIVE
,
6117 &zero_address_frag
);
6119 pseudo_func
[FUNC_LT_RELATIVE
].u
.sym
=
6120 symbol_new (".<ltoff>", undefined_section
, FUNC_LT_RELATIVE
,
6121 &zero_address_frag
);
6123 pseudo_func
[FUNC_PC_RELATIVE
].u
.sym
=
6124 symbol_new (".<pcrel>", undefined_section
, FUNC_PC_RELATIVE
,
6125 &zero_address_frag
);
6127 pseudo_func
[FUNC_PLT_RELATIVE
].u
.sym
=
6128 symbol_new (".<pltoff>", undefined_section
, FUNC_PLT_RELATIVE
,
6129 &zero_address_frag
);
6131 pseudo_func
[FUNC_SEC_RELATIVE
].u
.sym
=
6132 symbol_new (".<secrel>", undefined_section
, FUNC_SEC_RELATIVE
,
6133 &zero_address_frag
);
6135 pseudo_func
[FUNC_SEG_RELATIVE
].u
.sym
=
6136 symbol_new (".<segrel>", undefined_section
, FUNC_SEG_RELATIVE
,
6137 &zero_address_frag
);
6139 pseudo_func
[FUNC_LTV_RELATIVE
].u
.sym
=
6140 symbol_new (".<ltv>", undefined_section
, FUNC_LTV_RELATIVE
,
6141 &zero_address_frag
);
6143 pseudo_func
[FUNC_LT_FPTR_RELATIVE
].u
.sym
=
6144 symbol_new (".<ltoff.fptr>", undefined_section
, FUNC_LT_FPTR_RELATIVE
,
6145 &zero_address_frag
);
6147 /* Compute the table of best templates. We compute goodness as a
6148 base 4 value, in which each match counts for 3, each F counts
6149 for 2, each B counts for 1. This should maximize the number of
6150 F and B nops in the chosen bundles, which is good because these
6151 pipelines are least likely to be overcommitted. */
6152 for (i
= 0; i
< IA64_NUM_TYPES
; ++i
)
6153 for (j
= 0; j
< IA64_NUM_TYPES
; ++j
)
6154 for (k
= 0; k
< IA64_NUM_TYPES
; ++k
)
6157 for (t
= 0; t
< NELEMS (ia64_templ_desc
); ++t
)
6160 if (match (t
, i
, 0))
6162 if (match (t
, j
, 1))
6164 if (match (t
, k
, 2))
6165 goodness
= 3 + 3 + 3;
6167 goodness
= 3 + 3 + extra_goodness (t
, 2);
6169 else if (match (t
, j
, 2))
6170 goodness
= 3 + 3 + extra_goodness (t
, 1);
6174 goodness
+= extra_goodness (t
, 1);
6175 goodness
+= extra_goodness (t
, 2);
6178 else if (match (t
, i
, 1))
6180 if (match (t
, j
, 2))
6183 goodness
= 3 + extra_goodness (t
, 2);
6185 else if (match (t
, i
, 2))
6186 goodness
= 3 + extra_goodness (t
, 1);
6188 if (goodness
> best
)
6191 best_template
[i
][j
][k
] = t
;
6196 for (i
= 0; i
< NUM_SLOTS
; ++i
)
6197 md
.slot
[i
].user_template
= -1;
6199 md
.pseudo_hash
= hash_new ();
6200 for (i
= 0; i
< NELEMS (pseudo_opcode
); ++i
)
6202 err
= hash_insert (md
.pseudo_hash
, pseudo_opcode
[i
].name
,
6203 (void *) (pseudo_opcode
+ i
));
6205 as_fatal ("ia64.md_begin: can't hash `%s': %s",
6206 pseudo_opcode
[i
].name
, err
);
6209 md
.reg_hash
= hash_new ();
6210 md
.dynreg_hash
= hash_new ();
6211 md
.const_hash
= hash_new ();
6212 md
.entry_hash
= hash_new ();
6214 /* general registers: */
6217 for (i
= 0; i
< total
; ++i
)
6219 sprintf (name
, "r%d", i
- REG_GR
);
6220 md
.regsym
[i
] = declare_register (name
, i
);
6223 /* floating point registers: */
6225 for (; i
< total
; ++i
)
6227 sprintf (name
, "f%d", i
- REG_FR
);
6228 md
.regsym
[i
] = declare_register (name
, i
);
6231 /* application registers: */
6234 for (; i
< total
; ++i
)
6236 sprintf (name
, "ar%d", i
- REG_AR
);
6237 md
.regsym
[i
] = declare_register (name
, i
);
6240 /* control registers: */
6243 for (; i
< total
; ++i
)
6245 sprintf (name
, "cr%d", i
- REG_CR
);
6246 md
.regsym
[i
] = declare_register (name
, i
);
6249 /* predicate registers: */
6251 for (; i
< total
; ++i
)
6253 sprintf (name
, "p%d", i
- REG_P
);
6254 md
.regsym
[i
] = declare_register (name
, i
);
6257 /* branch registers: */
6259 for (; i
< total
; ++i
)
6261 sprintf (name
, "b%d", i
- REG_BR
);
6262 md
.regsym
[i
] = declare_register (name
, i
);
6265 md
.regsym
[REG_IP
] = declare_register ("ip", REG_IP
);
6266 md
.regsym
[REG_CFM
] = declare_register ("cfm", REG_CFM
);
6267 md
.regsym
[REG_PR
] = declare_register ("pr", REG_PR
);
6268 md
.regsym
[REG_PR_ROT
] = declare_register ("pr.rot", REG_PR_ROT
);
6269 md
.regsym
[REG_PSR
] = declare_register ("psr", REG_PSR
);
6270 md
.regsym
[REG_PSR_L
] = declare_register ("psr.l", REG_PSR_L
);
6271 md
.regsym
[REG_PSR_UM
] = declare_register ("psr.um", REG_PSR_UM
);
6273 for (i
= 0; i
< NELEMS (indirect_reg
); ++i
)
6275 regnum
= indirect_reg
[i
].regnum
;
6276 md
.regsym
[regnum
] = declare_register (indirect_reg
[i
].name
, regnum
);
6279 /* define synonyms for application registers: */
6280 for (i
= REG_AR
; i
< REG_AR
+ NELEMS (ar
); ++i
)
6281 md
.regsym
[i
] = declare_register (ar
[i
- REG_AR
].name
,
6282 REG_AR
+ ar
[i
- REG_AR
].regnum
);
6284 /* define synonyms for control registers: */
6285 for (i
= REG_CR
; i
< REG_CR
+ NELEMS (cr
); ++i
)
6286 md
.regsym
[i
] = declare_register (cr
[i
- REG_CR
].name
,
6287 REG_CR
+ cr
[i
- REG_CR
].regnum
);
6289 declare_register ("gp", REG_GR
+ 1);
6290 declare_register ("sp", REG_GR
+ 12);
6291 declare_register ("rp", REG_BR
+ 0);
6293 /* pseudo-registers used to specify unwind info: */
6294 declare_register ("psp", REG_PSP
);
6296 declare_register_set ("ret", 4, REG_GR
+ 8);
6297 declare_register_set ("farg", 8, REG_FR
+ 8);
6298 declare_register_set ("fret", 8, REG_FR
+ 8);
6300 for (i
= 0; i
< NELEMS (const_bits
); ++i
)
6302 err
= hash_insert (md
.const_hash
, const_bits
[i
].name
,
6303 (PTR
) (const_bits
+ i
));
6305 as_fatal ("Inserting \"%s\" into constant hash table failed: %s",
6309 /* Set the architecture and machine depending on defaults and command line
6311 if (md
.flags
& EF_IA_64_ABI64
)
6312 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_ia64
, bfd_mach_ia64_elf64
);
6314 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_ia64
, bfd_mach_ia64_elf32
);
6317 as_warn (_("Could not set architecture and machine"));
6319 md
.mem_offset
.hint
= 0;
6322 md
.entry_labels
= NULL
;
6325 /* Set the elf type to 64 bit ABI by default. Cannot do this in md_begin
6326 because that is called after md_parse_option which is where we do the
6327 dynamic changing of md.flags based on -mlp64 or -milp32. Also, set the
6328 default endianness. */
6331 ia64_init (argc
, argv
)
6332 int argc ATTRIBUTE_UNUSED
;
6333 char **argv ATTRIBUTE_UNUSED
;
6335 md
.flags
= EF_IA_64_ABI64
;
6336 if (TARGET_BYTES_BIG_ENDIAN
)
6337 md
.flags
|= EF_IA_64_BE
;
6340 /* Return a string for the target object file format. */
6343 ia64_target_format ()
6345 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
6347 if (md
.flags
& EF_IA_64_BE
)
6349 if (md
.flags
& EF_IA_64_ABI64
)
6350 return "elf64-ia64-big";
6352 return "elf32-ia64-big";
6356 if (md
.flags
& EF_IA_64_ABI64
)
6357 return "elf64-ia64-little";
6359 return "elf32-ia64-little";
6363 return "unknown-format";
6367 ia64_end_of_source ()
6369 /* terminate insn group upon reaching end of file: */
6370 insn_group_break (1, 0, 0);
6372 /* emits slots we haven't written yet: */
6373 ia64_flush_insns ();
6375 bfd_set_private_flags (stdoutput
, md
.flags
);
6377 md
.mem_offset
.hint
= 0;
6383 if (md
.qp
.X_op
== O_register
)
6384 as_bad ("qualifying predicate not followed by instruction");
6385 md
.qp
.X_op
= O_absent
;
6387 if (ignore_input ())
6390 if (input_line_pointer
[0] == ';' && input_line_pointer
[-1] == ';')
6392 if (md
.detect_dv
&& !md
.explicit_mode
)
6393 as_warn (_("Explicit stops are ignored in auto mode"));
6395 insn_group_break (1, 0, 0);
6399 /* This is a hook for ia64_frob_label, so that it can distinguish tags from
6401 static int defining_tag
= 0;
6404 ia64_unrecognized_line (ch
)
6410 expression (&md
.qp
);
6411 if (*input_line_pointer
++ != ')')
6413 as_bad ("Expected ')'");
6416 if (md
.qp
.X_op
!= O_register
)
6418 as_bad ("Qualifying predicate expected");
6421 if (md
.qp
.X_add_number
< REG_P
|| md
.qp
.X_add_number
>= REG_P
+ 64)
6423 as_bad ("Predicate register expected");
6429 if (md
.manual_bundling
)
6430 as_warn ("Found '{' when manual bundling is already turned on");
6432 CURR_SLOT
.manual_bundling_on
= 1;
6433 md
.manual_bundling
= 1;
6435 /* Bundling is only acceptable in explicit mode
6436 or when in default automatic mode. */
6437 if (md
.detect_dv
&& !md
.explicit_mode
)
6439 if (!md
.mode_explicitly_set
6440 && !md
.default_explicit_mode
)
6443 as_warn (_("Found '{' after explicit switch to automatic mode"));
6448 if (!md
.manual_bundling
)
6449 as_warn ("Found '}' when manual bundling is off");
6451 PREV_SLOT
.manual_bundling_off
= 1;
6452 md
.manual_bundling
= 0;
6454 /* switch back to automatic mode, if applicable */
6457 && !md
.mode_explicitly_set
6458 && !md
.default_explicit_mode
)
6461 /* Allow '{' to follow on the same line. We also allow ";;", but that
6462 happens automatically because ';' is an end of line marker. */
6464 if (input_line_pointer
[0] == '{')
6466 input_line_pointer
++;
6467 return ia64_unrecognized_line ('{');
6470 demand_empty_rest_of_line ();
6479 if (md
.qp
.X_op
== O_register
)
6481 as_bad ("Tag must come before qualifying predicate.");
6484 s
= input_line_pointer
;
6485 c
= get_symbol_end ();
6488 /* Put ':' back for error messages' sake. */
6489 *input_line_pointer
++ = ':';
6490 as_bad ("Expected ':'");
6496 /* Put ':' back for error messages' sake. */
6497 *input_line_pointer
++ = ':';
6498 if (*input_line_pointer
++ != ']')
6500 as_bad ("Expected ']'");
6505 as_bad ("Tag name expected");
6515 /* Not a valid line. */
6520 ia64_frob_label (sym
)
6523 struct label_fix
*fix
;
6525 /* Tags need special handling since they are not bundle breaks like
6529 fix
= obstack_alloc (¬es
, sizeof (*fix
));
6531 fix
->next
= CURR_SLOT
.tag_fixups
;
6532 CURR_SLOT
.tag_fixups
= fix
;
6537 if (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
)
6539 md
.last_text_seg
= now_seg
;
6540 fix
= obstack_alloc (¬es
, sizeof (*fix
));
6542 fix
->next
= CURR_SLOT
.label_fixups
;
6543 CURR_SLOT
.label_fixups
= fix
;
6545 /* Keep track of how many code entry points we've seen. */
6546 if (md
.path
== md
.maxpaths
)
6549 md
.entry_labels
= (const char **)
6550 xrealloc ((void *) md
.entry_labels
,
6551 md
.maxpaths
* sizeof (char *));
6553 md
.entry_labels
[md
.path
++] = S_GET_NAME (sym
);
6558 ia64_flush_pending_output ()
6560 if (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
)
6562 /* ??? This causes many unnecessary stop bits to be emitted.
6563 Unfortunately, it isn't clear if it is safe to remove this. */
6564 insn_group_break (1, 0, 0);
6565 ia64_flush_insns ();
6569 /* Do ia64-specific expression optimization. All that's done here is
6570 to transform index expressions that are either due to the indexing
6571 of rotating registers or due to the indexing of indirect register
6574 ia64_optimize_expr (l
, op
, r
)
6583 if (l
->X_op
== O_register
&& r
->X_op
== O_constant
)
6585 num_regs
= (l
->X_add_number
>> 16);
6586 if ((unsigned) r
->X_add_number
>= num_regs
)
6589 as_bad ("No current frame");
6591 as_bad ("Index out of range 0..%u", num_regs
- 1);
6592 r
->X_add_number
= 0;
6594 l
->X_add_number
= (l
->X_add_number
& 0xffff) + r
->X_add_number
;
6597 else if (l
->X_op
== O_register
&& r
->X_op
== O_register
)
6599 if (l
->X_add_number
< IND_CPUID
|| l
->X_add_number
> IND_RR
6600 || l
->X_add_number
== IND_MEM
)
6602 as_bad ("Indirect register set name expected");
6603 l
->X_add_number
= IND_CPUID
;
6606 l
->X_op_symbol
= md
.regsym
[l
->X_add_number
];
6607 l
->X_add_number
= r
->X_add_number
;
6615 ia64_parse_name (name
, e
)
6619 struct const_desc
*cdesc
;
6620 struct dynreg
*dr
= 0;
6621 unsigned int regnum
;
6625 /* first see if NAME is a known register name: */
6626 sym
= hash_find (md
.reg_hash
, name
);
6629 e
->X_op
= O_register
;
6630 e
->X_add_number
= S_GET_VALUE (sym
);
6634 cdesc
= hash_find (md
.const_hash
, name
);
6637 e
->X_op
= O_constant
;
6638 e
->X_add_number
= cdesc
->value
;
6642 /* check for inN, locN, or outN: */
6646 if (name
[1] == 'n' && isdigit (name
[2]))
6654 if (name
[1] == 'o' && name
[2] == 'c' && isdigit (name
[3]))
6662 if (name
[1] == 'u' && name
[2] == 't' && isdigit (name
[3]))
6675 /* The name is inN, locN, or outN; parse the register number. */
6676 regnum
= strtoul (name
, &end
, 10);
6677 if (end
> name
&& *end
== '\0')
6679 if ((unsigned) regnum
>= dr
->num_regs
)
6682 as_bad ("No current frame");
6684 as_bad ("Register number out of range 0..%u",
6688 e
->X_op
= O_register
;
6689 e
->X_add_number
= dr
->base
+ regnum
;
6694 if ((dr
= hash_find (md
.dynreg_hash
, name
)))
6696 /* We've got ourselves the name of a rotating register set.
6697 Store the base register number in the low 16 bits of
6698 X_add_number and the size of the register set in the top 16
6700 e
->X_op
= O_register
;
6701 e
->X_add_number
= dr
->base
| (dr
->num_regs
<< 16);
6707 /* Remove the '#' suffix that indicates a symbol as opposed to a register. */
6710 ia64_canonicalize_symbol_name (name
)
6713 size_t len
= strlen (name
);
6714 if (len
> 1 && name
[len
- 1] == '#')
6715 name
[len
- 1] = '\0';
6720 is_conditional_branch (idesc
)
6721 struct ia64_opcode
*idesc
;
6723 return (strncmp (idesc
->name
, "br", 2) == 0
6724 && (strcmp (idesc
->name
, "br") == 0
6725 || strncmp (idesc
->name
, "br.cond", 7) == 0
6726 || strncmp (idesc
->name
, "br.call", 7) == 0
6727 || strncmp (idesc
->name
, "br.ret", 6) == 0
6728 || strcmp (idesc
->name
, "brl") == 0
6729 || strncmp (idesc
->name
, "brl.cond", 7) == 0
6730 || strncmp (idesc
->name
, "brl.call", 7) == 0
6731 || strncmp (idesc
->name
, "brl.ret", 6) == 0));
6734 /* Return whether the given opcode is a taken branch. If there's any doubt,
6738 is_taken_branch (idesc
)
6739 struct ia64_opcode
*idesc
;
6741 return ((is_conditional_branch (idesc
) && CURR_SLOT
.qp_regno
== 0)
6742 || strncmp (idesc
->name
, "br.ia", 5) == 0);
6745 /* Return whether the given opcode is an interruption or rfi. If there's any
6746 doubt, returns zero. */
6749 is_interruption_or_rfi (idesc
)
6750 struct ia64_opcode
*idesc
;
6752 if (strcmp (idesc
->name
, "rfi") == 0)
6757 /* Returns the index of the given dependency in the opcode's list of chks, or
6758 -1 if there is no dependency. */
6761 depends_on (depind
, idesc
)
6763 struct ia64_opcode
*idesc
;
6766 const struct ia64_opcode_dependency
*dep
= idesc
->dependencies
;
6767 for (i
= 0; i
< dep
->nchks
; i
++)
6769 if (depind
== DEP (dep
->chks
[i
]))
6775 /* Determine a set of specific resources used for a particular resource
6776 class. Returns the number of specific resources identified For those
6777 cases which are not determinable statically, the resource returned is
6780 Meanings of value in 'NOTE':
6781 1) only read/write when the register number is explicitly encoded in the
6783 2) only read CFM when accessing a rotating GR, FR, or PR. mov pr only
6784 accesses CFM when qualifying predicate is in the rotating region.
6785 3) general register value is used to specify an indirect register; not
6786 determinable statically.
6787 4) only read the given resource when bits 7:0 of the indirect index
6788 register value does not match the register number of the resource; not
6789 determinable statically.
6790 5) all rules are implementation specific.
6791 6) only when both the index specified by the reader and the index specified
6792 by the writer have the same value in bits 63:61; not determinable
6794 7) only access the specified resource when the corresponding mask bit is
6796 8) PSR.dfh is only read when these insns reference FR32-127. PSR.dfl is
6797 only read when these insns reference FR2-31
6798 9) PSR.mfl is only written when these insns write FR2-31. PSR.mfh is only
6799 written when these insns write FR32-127
6800 10) The PSR.bn bit is only accessed when one of GR16-31 is specified in the
6802 11) The target predicates are written independently of PR[qp], but source
6803 registers are only read if PR[qp] is true. Since the state of PR[qp]
6804 cannot statically be determined, all source registers are marked used.
6805 12) This insn only reads the specified predicate register when that
6806 register is the PR[qp].
6807 13) This reference to ld-c only applies to teh GR whose value is loaded
6808 with data returned from memory, not the post-incremented address register.
6809 14) The RSE resource includes the implementation-specific RSE internal
6810 state resources. At least one (and possibly more) of these resources are
6811 read by each instruction listed in IC:rse-readers. At least one (and
6812 possibly more) of these resources are written by each insn listed in
6814 15+16) Represents reserved instructions, which the assembler does not
6817 Memory resources (i.e. locations in memory) are *not* marked or tracked by
6818 this code; there are no dependency violations based on memory access.
6821 #define MAX_SPECS 256
6826 specify_resource (dep
, idesc
, type
, specs
, note
, path
)
6827 const struct ia64_dependency
*dep
;
6828 struct ia64_opcode
*idesc
;
6829 int type
; /* is this a DV chk or a DV reg? */
6830 struct rsrc specs
[MAX_SPECS
]; /* returned specific resources */
6831 int note
; /* resource note for this insn's usage */
6832 int path
; /* which execution path to examine */
6839 if (dep
->mode
== IA64_DV_WAW
6840 || (dep
->mode
== IA64_DV_RAW
&& type
== DV_REG
)
6841 || (dep
->mode
== IA64_DV_WAR
&& type
== DV_CHK
))
6844 /* template for any resources we identify */
6845 tmpl
.dependency
= dep
;
6847 tmpl
.insn_srlz
= tmpl
.data_srlz
= 0;
6848 tmpl
.qp_regno
= CURR_SLOT
.qp_regno
;
6849 tmpl
.link_to_qp_branch
= 1;
6850 tmpl
.mem_offset
.hint
= 0;
6853 tmpl
.cmp_type
= CMP_NONE
;
6856 as_warn (_("Unhandled dependency %s for %s (%s), note %d"), \
6857 dep->name, idesc->name, (rsrc_write?"write":"read"), note)
6858 #define KNOWN(REG) (gr_values[REG].known && gr_values[REG].path >= path)
6860 /* we don't need to track these */
6861 if (dep
->semantics
== IA64_DVS_NONE
)
6864 switch (dep
->specifier
)
6869 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_AR3
)
6871 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_AR
;
6872 if (regno
>= 0 && regno
<= 7)
6874 specs
[count
] = tmpl
;
6875 specs
[count
++].index
= regno
;
6881 for (i
= 0; i
< 8; i
++)
6883 specs
[count
] = tmpl
;
6884 specs
[count
++].index
= i
;
6893 case IA64_RS_AR_UNAT
:
6894 /* This is a mov =AR or mov AR= instruction. */
6895 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_AR3
)
6897 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_AR
;
6898 if (regno
== AR_UNAT
)
6900 specs
[count
++] = tmpl
;
6905 /* This is a spill/fill, or other instruction that modifies the
6908 /* Unless we can determine the specific bits used, mark the whole
6909 thing; bits 8:3 of the memory address indicate the bit used in
6910 UNAT. The .mem.offset hint may be used to eliminate a small
6911 subset of conflicts. */
6912 specs
[count
] = tmpl
;
6913 if (md
.mem_offset
.hint
)
6916 fprintf (stderr
, " Using hint for spill/fill\n");
6917 /* The index isn't actually used, just set it to something
6918 approximating the bit index. */
6919 specs
[count
].index
= (md
.mem_offset
.offset
>> 3) & 0x3F;
6920 specs
[count
].mem_offset
.hint
= 1;
6921 specs
[count
].mem_offset
.offset
= md
.mem_offset
.offset
;
6922 specs
[count
++].mem_offset
.base
= md
.mem_offset
.base
;
6926 specs
[count
++].specific
= 0;
6934 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_AR3
)
6936 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_AR
;
6937 if ((regno
>= 8 && regno
<= 15)
6938 || (regno
>= 20 && regno
<= 23)
6939 || (regno
>= 31 && regno
<= 39)
6940 || (regno
>= 41 && regno
<= 47)
6941 || (regno
>= 67 && regno
<= 111))
6943 specs
[count
] = tmpl
;
6944 specs
[count
++].index
= regno
;
6957 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_AR3
)
6959 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_AR
;
6960 if ((regno
>= 48 && regno
<= 63)
6961 || (regno
>= 112 && regno
<= 127))
6963 specs
[count
] = tmpl
;
6964 specs
[count
++].index
= regno
;
6970 for (i
= 48; i
< 64; i
++)
6972 specs
[count
] = tmpl
;
6973 specs
[count
++].index
= i
;
6975 for (i
= 112; i
< 128; i
++)
6977 specs
[count
] = tmpl
;
6978 specs
[count
++].index
= i
;
6996 for (i
= 0; i
< idesc
->num_outputs
; i
++)
6997 if (idesc
->operands
[i
] == IA64_OPND_B1
6998 || idesc
->operands
[i
] == IA64_OPND_B2
)
7000 specs
[count
] = tmpl
;
7001 specs
[count
++].index
=
7002 CURR_SLOT
.opnd
[i
].X_add_number
- REG_BR
;
7007 for (i
= idesc
->num_outputs
;i
< NELEMS (idesc
->operands
); i
++)
7008 if (idesc
->operands
[i
] == IA64_OPND_B1
7009 || idesc
->operands
[i
] == IA64_OPND_B2
)
7011 specs
[count
] = tmpl
;
7012 specs
[count
++].index
=
7013 CURR_SLOT
.opnd
[i
].X_add_number
- REG_BR
;
7019 case IA64_RS_CPUID
: /* four or more registers */
7022 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_CPUID_R3
)
7024 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_GR
;
7025 if (regno
>= 0 && regno
< NELEMS (gr_values
)
7028 specs
[count
] = tmpl
;
7029 specs
[count
++].index
= gr_values
[regno
].value
& 0xFF;
7033 specs
[count
] = tmpl
;
7034 specs
[count
++].specific
= 0;
7044 case IA64_RS_DBR
: /* four or more registers */
7047 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_DBR_R3
)
7049 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_GR
;
7050 if (regno
>= 0 && regno
< NELEMS (gr_values
)
7053 specs
[count
] = tmpl
;
7054 specs
[count
++].index
= gr_values
[regno
].value
& 0xFF;
7058 specs
[count
] = tmpl
;
7059 specs
[count
++].specific
= 0;
7063 else if (note
== 0 && !rsrc_write
)
7065 specs
[count
] = tmpl
;
7066 specs
[count
++].specific
= 0;
7074 case IA64_RS_IBR
: /* four or more registers */
7077 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_IBR_R3
)
7079 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_GR
;
7080 if (regno
>= 0 && regno
< NELEMS (gr_values
)
7083 specs
[count
] = tmpl
;
7084 specs
[count
++].index
= gr_values
[regno
].value
& 0xFF;
7088 specs
[count
] = tmpl
;
7089 specs
[count
++].specific
= 0;
7102 /* These are implementation specific. Force all references to
7103 conflict with all other references. */
7104 specs
[count
] = tmpl
;
7105 specs
[count
++].specific
= 0;
7113 case IA64_RS_PKR
: /* 16 or more registers */
7114 if (note
== 3 || note
== 4)
7116 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_PKR_R3
)
7118 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_GR
;
7119 if (regno
>= 0 && regno
< NELEMS (gr_values
)
7124 specs
[count
] = tmpl
;
7125 specs
[count
++].index
= gr_values
[regno
].value
& 0xFF;
7128 for (i
= 0; i
< NELEMS (gr_values
); i
++)
7130 /* Uses all registers *except* the one in R3. */
7131 if ((unsigned)i
!= (gr_values
[regno
].value
& 0xFF))
7133 specs
[count
] = tmpl
;
7134 specs
[count
++].index
= i
;
7140 specs
[count
] = tmpl
;
7141 specs
[count
++].specific
= 0;
7148 specs
[count
] = tmpl
;
7149 specs
[count
++].specific
= 0;
7153 case IA64_RS_PMC
: /* four or more registers */
7156 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_PMC_R3
7157 || (!rsrc_write
&& idesc
->operands
[1] == IA64_OPND_PMD_R3
))
7160 int index
= ((idesc
->operands
[1] == IA64_OPND_R3
&& !rsrc_write
)
7162 int regno
= CURR_SLOT
.opnd
[index
].X_add_number
- REG_GR
;
7163 if (regno
>= 0 && regno
< NELEMS (gr_values
)
7166 specs
[count
] = tmpl
;
7167 specs
[count
++].index
= gr_values
[regno
].value
& 0xFF;
7171 specs
[count
] = tmpl
;
7172 specs
[count
++].specific
= 0;
7182 case IA64_RS_PMD
: /* four or more registers */
7185 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_PMD_R3
)
7187 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_GR
;
7188 if (regno
>= 0 && regno
< NELEMS (gr_values
)
7191 specs
[count
] = tmpl
;
7192 specs
[count
++].index
= gr_values
[regno
].value
& 0xFF;
7196 specs
[count
] = tmpl
;
7197 specs
[count
++].specific
= 0;
7207 case IA64_RS_RR
: /* eight registers */
7210 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_RR_R3
)
7212 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_GR
;
7213 if (regno
>= 0 && regno
< NELEMS (gr_values
)
7216 specs
[count
] = tmpl
;
7217 specs
[count
++].index
= (gr_values
[regno
].value
>> 61) & 0x7;
7221 specs
[count
] = tmpl
;
7222 specs
[count
++].specific
= 0;
7226 else if (note
== 0 && !rsrc_write
)
7228 specs
[count
] = tmpl
;
7229 specs
[count
++].specific
= 0;
7237 case IA64_RS_CR_IRR
:
7240 /* handle mov-from-CR-IVR; it's a read that writes CR[IRR] */
7241 int regno
= CURR_SLOT
.opnd
[1].X_add_number
- REG_CR
;
7243 && idesc
->operands
[1] == IA64_OPND_CR3
7246 for (i
= 0; i
< 4; i
++)
7248 specs
[count
] = tmpl
;
7249 specs
[count
++].index
= CR_IRR0
+ i
;
7255 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_CR
;
7256 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_CR3
7258 && regno
<= CR_IRR3
)
7260 specs
[count
] = tmpl
;
7261 specs
[count
++].index
= regno
;
7270 case IA64_RS_CR_LRR
:
7277 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_CR
;
7278 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_CR3
7279 && (regno
== CR_LRR0
|| regno
== CR_LRR1
))
7281 specs
[count
] = tmpl
;
7282 specs
[count
++].index
= regno
;
7290 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_CR3
)
7292 specs
[count
] = tmpl
;
7293 specs
[count
++].index
=
7294 CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_CR
;
7309 else if (rsrc_write
)
7311 if (dep
->specifier
== IA64_RS_FRb
7312 && idesc
->operands
[0] == IA64_OPND_F1
)
7314 specs
[count
] = tmpl
;
7315 specs
[count
++].index
= CURR_SLOT
.opnd
[0].X_add_number
- REG_FR
;
7320 for (i
= idesc
->num_outputs
; i
< NELEMS (idesc
->operands
); i
++)
7322 if (idesc
->operands
[i
] == IA64_OPND_F2
7323 || idesc
->operands
[i
] == IA64_OPND_F3
7324 || idesc
->operands
[i
] == IA64_OPND_F4
)
7326 specs
[count
] = tmpl
;
7327 specs
[count
++].index
=
7328 CURR_SLOT
.opnd
[i
].X_add_number
- REG_FR
;
7337 /* This reference applies only to the GR whose value is loaded with
7338 data returned from memory. */
7339 specs
[count
] = tmpl
;
7340 specs
[count
++].index
= CURR_SLOT
.opnd
[0].X_add_number
- REG_GR
;
7346 for (i
= 0; i
< idesc
->num_outputs
; i
++)
7347 if (idesc
->operands
[i
] == IA64_OPND_R1
7348 || idesc
->operands
[i
] == IA64_OPND_R2
7349 || idesc
->operands
[i
] == IA64_OPND_R3
)
7351 specs
[count
] = tmpl
;
7352 specs
[count
++].index
=
7353 CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
7355 if (idesc
->flags
& IA64_OPCODE_POSTINC
)
7356 for (i
= 0; i
< NELEMS (idesc
->operands
); i
++)
7357 if (idesc
->operands
[i
] == IA64_OPND_MR3
)
7359 specs
[count
] = tmpl
;
7360 specs
[count
++].index
=
7361 CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
7366 /* Look for anything that reads a GR. */
7367 for (i
= 0; i
< NELEMS (idesc
->operands
); i
++)
7369 if (idesc
->operands
[i
] == IA64_OPND_MR3
7370 || idesc
->operands
[i
] == IA64_OPND_CPUID_R3
7371 || idesc
->operands
[i
] == IA64_OPND_DBR_R3
7372 || idesc
->operands
[i
] == IA64_OPND_IBR_R3
7373 || idesc
->operands
[i
] == IA64_OPND_MSR_R3
7374 || idesc
->operands
[i
] == IA64_OPND_PKR_R3
7375 || idesc
->operands
[i
] == IA64_OPND_PMC_R3
7376 || idesc
->operands
[i
] == IA64_OPND_PMD_R3
7377 || idesc
->operands
[i
] == IA64_OPND_RR_R3
7378 || ((i
>= idesc
->num_outputs
)
7379 && (idesc
->operands
[i
] == IA64_OPND_R1
7380 || idesc
->operands
[i
] == IA64_OPND_R2
7381 || idesc
->operands
[i
] == IA64_OPND_R3
7382 /* addl source register. */
7383 || idesc
->operands
[i
] == IA64_OPND_R3_2
)))
7385 specs
[count
] = tmpl
;
7386 specs
[count
++].index
=
7387 CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
7398 /* This is the same as IA64_RS_PRr, except that the register range is
7399 from 1 - 15, and there are no rotating register reads/writes here. */
7403 for (i
= 1; i
< 16; i
++)
7405 specs
[count
] = tmpl
;
7406 specs
[count
++].index
= i
;
7412 /* Mark only those registers indicated by the mask. */
7415 mask
= CURR_SLOT
.opnd
[2].X_add_number
;
7416 for (i
= 1; i
< 16; i
++)
7417 if (mask
& ((valueT
) 1 << i
))
7419 specs
[count
] = tmpl
;
7420 specs
[count
++].index
= i
;
7428 else if (note
== 11) /* note 11 implies note 1 as well */
7432 for (i
= 0; i
< idesc
->num_outputs
; i
++)
7434 if (idesc
->operands
[i
] == IA64_OPND_P1
7435 || idesc
->operands
[i
] == IA64_OPND_P2
)
7437 int regno
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_P
;
7438 if (regno
>= 1 && regno
< 16)
7440 specs
[count
] = tmpl
;
7441 specs
[count
++].index
= regno
;
7451 else if (note
== 12)
7453 if (CURR_SLOT
.qp_regno
>= 1 && CURR_SLOT
.qp_regno
< 16)
7455 specs
[count
] = tmpl
;
7456 specs
[count
++].index
= CURR_SLOT
.qp_regno
;
7463 int p1
= CURR_SLOT
.opnd
[0].X_add_number
- REG_P
;
7464 int p2
= CURR_SLOT
.opnd
[1].X_add_number
- REG_P
;
7465 int or_andcm
= strstr(idesc
->name
, "or.andcm") != NULL
;
7466 int and_orcm
= strstr(idesc
->name
, "and.orcm") != NULL
;
7468 if ((idesc
->operands
[0] == IA64_OPND_P1
7469 || idesc
->operands
[0] == IA64_OPND_P2
)
7470 && p1
>= 1 && p1
< 16)
7472 specs
[count
] = tmpl
;
7473 specs
[count
].cmp_type
=
7474 (or_andcm
? CMP_OR
: (and_orcm
? CMP_AND
: CMP_NONE
));
7475 specs
[count
++].index
= p1
;
7477 if ((idesc
->operands
[1] == IA64_OPND_P1
7478 || idesc
->operands
[1] == IA64_OPND_P2
)
7479 && p2
>= 1 && p2
< 16)
7481 specs
[count
] = tmpl
;
7482 specs
[count
].cmp_type
=
7483 (or_andcm
? CMP_AND
: (and_orcm
? CMP_OR
: CMP_NONE
));
7484 specs
[count
++].index
= p2
;
7489 if (CURR_SLOT
.qp_regno
>= 1 && CURR_SLOT
.qp_regno
< 16)
7491 specs
[count
] = tmpl
;
7492 specs
[count
++].index
= CURR_SLOT
.qp_regno
;
7494 if (idesc
->operands
[1] == IA64_OPND_PR
)
7496 for (i
= 1; i
< 16; i
++)
7498 specs
[count
] = tmpl
;
7499 specs
[count
++].index
= i
;
7510 /* This is the general case for PRs. IA64_RS_PR and IA64_RS_PR63 are
7511 simplified cases of this. */
7515 for (i
= 16; i
< 63; i
++)
7517 specs
[count
] = tmpl
;
7518 specs
[count
++].index
= i
;
7524 /* Mark only those registers indicated by the mask. */
7526 && idesc
->operands
[0] == IA64_OPND_PR
)
7528 mask
= CURR_SLOT
.opnd
[2].X_add_number
;
7529 if (mask
& ((valueT
) 1<<16))
7530 for (i
= 16; i
< 63; i
++)
7532 specs
[count
] = tmpl
;
7533 specs
[count
++].index
= i
;
7537 && idesc
->operands
[0] == IA64_OPND_PR_ROT
)
7539 for (i
= 16; i
< 63; i
++)
7541 specs
[count
] = tmpl
;
7542 specs
[count
++].index
= i
;
7550 else if (note
== 11) /* note 11 implies note 1 as well */
7554 for (i
= 0; i
< idesc
->num_outputs
; i
++)
7556 if (idesc
->operands
[i
] == IA64_OPND_P1
7557 || idesc
->operands
[i
] == IA64_OPND_P2
)
7559 int regno
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_P
;
7560 if (regno
>= 16 && regno
< 63)
7562 specs
[count
] = tmpl
;
7563 specs
[count
++].index
= regno
;
7573 else if (note
== 12)
7575 if (CURR_SLOT
.qp_regno
>= 16 && CURR_SLOT
.qp_regno
< 63)
7577 specs
[count
] = tmpl
;
7578 specs
[count
++].index
= CURR_SLOT
.qp_regno
;
7585 int p1
= CURR_SLOT
.opnd
[0].X_add_number
- REG_P
;
7586 int p2
= CURR_SLOT
.opnd
[1].X_add_number
- REG_P
;
7587 int or_andcm
= strstr(idesc
->name
, "or.andcm") != NULL
;
7588 int and_orcm
= strstr(idesc
->name
, "and.orcm") != NULL
;
7590 if ((idesc
->operands
[0] == IA64_OPND_P1
7591 || idesc
->operands
[0] == IA64_OPND_P2
)
7592 && p1
>= 16 && p1
< 63)
7594 specs
[count
] = tmpl
;
7595 specs
[count
].cmp_type
=
7596 (or_andcm
? CMP_OR
: (and_orcm
? CMP_AND
: CMP_NONE
));
7597 specs
[count
++].index
= p1
;
7599 if ((idesc
->operands
[1] == IA64_OPND_P1
7600 || idesc
->operands
[1] == IA64_OPND_P2
)
7601 && p2
>= 16 && p2
< 63)
7603 specs
[count
] = tmpl
;
7604 specs
[count
].cmp_type
=
7605 (or_andcm
? CMP_AND
: (and_orcm
? CMP_OR
: CMP_NONE
));
7606 specs
[count
++].index
= p2
;
7611 if (CURR_SLOT
.qp_regno
>= 16 && CURR_SLOT
.qp_regno
< 63)
7613 specs
[count
] = tmpl
;
7614 specs
[count
++].index
= CURR_SLOT
.qp_regno
;
7616 if (idesc
->operands
[1] == IA64_OPND_PR
)
7618 for (i
= 16; i
< 63; i
++)
7620 specs
[count
] = tmpl
;
7621 specs
[count
++].index
= i
;
7633 /* Verify that the instruction is using the PSR bit indicated in
7637 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_PSR_UM
)
7639 if (dep
->regindex
< 6)
7641 specs
[count
++] = tmpl
;
7644 else if (idesc
->operands
[!rsrc_write
] == IA64_OPND_PSR
)
7646 if (dep
->regindex
< 32
7647 || dep
->regindex
== 35
7648 || dep
->regindex
== 36
7649 || (!rsrc_write
&& dep
->regindex
== PSR_CPL
))
7651 specs
[count
++] = tmpl
;
7654 else if (idesc
->operands
[!rsrc_write
] == IA64_OPND_PSR_L
)
7656 if (dep
->regindex
< 32
7657 || dep
->regindex
== 35
7658 || dep
->regindex
== 36
7659 || (rsrc_write
&& dep
->regindex
== PSR_CPL
))
7661 specs
[count
++] = tmpl
;
7666 /* Several PSR bits have very specific dependencies. */
7667 switch (dep
->regindex
)
7670 specs
[count
++] = tmpl
;
7675 specs
[count
++] = tmpl
;
7679 /* Only certain CR accesses use PSR.ic */
7680 if (idesc
->operands
[0] == IA64_OPND_CR3
7681 || idesc
->operands
[1] == IA64_OPND_CR3
)
7684 ((idesc
->operands
[0] == IA64_OPND_CR3
)
7687 CURR_SLOT
.opnd
[index
].X_add_number
- REG_CR
;
7702 specs
[count
++] = tmpl
;
7711 specs
[count
++] = tmpl
;
7715 /* Only some AR accesses use cpl */
7716 if (idesc
->operands
[0] == IA64_OPND_AR3
7717 || idesc
->operands
[1] == IA64_OPND_AR3
)
7720 ((idesc
->operands
[0] == IA64_OPND_AR3
)
7723 CURR_SLOT
.opnd
[index
].X_add_number
- REG_AR
;
7730 && regno
<= AR_K7
))))
7732 specs
[count
++] = tmpl
;
7737 specs
[count
++] = tmpl
;
7747 if (idesc
->operands
[0] == IA64_OPND_IMMU24
)
7749 mask
= CURR_SLOT
.opnd
[0].X_add_number
;
7755 if (mask
& ((valueT
) 1 << dep
->regindex
))
7757 specs
[count
++] = tmpl
;
7762 int min
= dep
->regindex
== PSR_DFL
? 2 : 32;
7763 int max
= dep
->regindex
== PSR_DFL
? 31 : 127;
7764 /* dfh is read on FR32-127; dfl is read on FR2-31 */
7765 for (i
= 0; i
< NELEMS (idesc
->operands
); i
++)
7767 if (idesc
->operands
[i
] == IA64_OPND_F1
7768 || idesc
->operands
[i
] == IA64_OPND_F2
7769 || idesc
->operands
[i
] == IA64_OPND_F3
7770 || idesc
->operands
[i
] == IA64_OPND_F4
)
7772 int reg
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_FR
;
7773 if (reg
>= min
&& reg
<= max
)
7775 specs
[count
++] = tmpl
;
7782 int min
= dep
->regindex
== PSR_MFL
? 2 : 32;
7783 int max
= dep
->regindex
== PSR_MFL
? 31 : 127;
7784 /* mfh is read on writes to FR32-127; mfl is read on writes to
7786 for (i
= 0; i
< idesc
->num_outputs
; i
++)
7788 if (idesc
->operands
[i
] == IA64_OPND_F1
)
7790 int reg
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_FR
;
7791 if (reg
>= min
&& reg
<= max
)
7793 specs
[count
++] = tmpl
;
7798 else if (note
== 10)
7800 for (i
= 0; i
< NELEMS (idesc
->operands
); i
++)
7802 if (idesc
->operands
[i
] == IA64_OPND_R1
7803 || idesc
->operands
[i
] == IA64_OPND_R2
7804 || idesc
->operands
[i
] == IA64_OPND_R3
)
7806 int regno
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
7807 if (regno
>= 16 && regno
<= 31)
7809 specs
[count
++] = tmpl
;
7820 case IA64_RS_AR_FPSR
:
7821 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_AR3
)
7823 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_AR
;
7824 if (regno
== AR_FPSR
)
7826 specs
[count
++] = tmpl
;
7831 specs
[count
++] = tmpl
;
7836 /* Handle all AR[REG] resources */
7837 if (note
== 0 || note
== 1)
7839 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_AR
;
7840 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_AR3
7841 && regno
== dep
->regindex
)
7843 specs
[count
++] = tmpl
;
7845 /* other AR[REG] resources may be affected by AR accesses */
7846 else if (idesc
->operands
[0] == IA64_OPND_AR3
)
7849 regno
= CURR_SLOT
.opnd
[0].X_add_number
- REG_AR
;
7850 switch (dep
->regindex
)
7856 if (regno
== AR_BSPSTORE
)
7858 specs
[count
++] = tmpl
;
7862 (regno
== AR_BSPSTORE
7863 || regno
== AR_RNAT
))
7865 specs
[count
++] = tmpl
;
7870 else if (idesc
->operands
[1] == IA64_OPND_AR3
)
7873 regno
= CURR_SLOT
.opnd
[1].X_add_number
- REG_AR
;
7874 switch (dep
->regindex
)
7879 if (regno
== AR_BSPSTORE
|| regno
== AR_RNAT
)
7881 specs
[count
++] = tmpl
;
7888 specs
[count
++] = tmpl
;
7898 /* Handle all CR[REG] resources */
7899 if (note
== 0 || note
== 1)
7901 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_CR3
)
7903 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_CR
;
7904 if (regno
== dep
->regindex
)
7906 specs
[count
++] = tmpl
;
7908 else if (!rsrc_write
)
7910 /* Reads from CR[IVR] affect other resources. */
7911 if (regno
== CR_IVR
)
7913 if ((dep
->regindex
>= CR_IRR0
7914 && dep
->regindex
<= CR_IRR3
)
7915 || dep
->regindex
== CR_TPR
)
7917 specs
[count
++] = tmpl
;
7924 specs
[count
++] = tmpl
;
7933 case IA64_RS_INSERVICE
:
7934 /* look for write of EOI (67) or read of IVR (65) */
7935 if ((idesc
->operands
[0] == IA64_OPND_CR3
7936 && CURR_SLOT
.opnd
[0].X_add_number
- REG_CR
== CR_EOI
)
7937 || (idesc
->operands
[1] == IA64_OPND_CR3
7938 && CURR_SLOT
.opnd
[1].X_add_number
- REG_CR
== CR_IVR
))
7940 specs
[count
++] = tmpl
;
7947 specs
[count
++] = tmpl
;
7958 specs
[count
++] = tmpl
;
7962 /* Check if any of the registers accessed are in the rotating region.
7963 mov to/from pr accesses CFM only when qp_regno is in the rotating
7965 for (i
= 0; i
< NELEMS (idesc
->operands
); i
++)
7967 if (idesc
->operands
[i
] == IA64_OPND_R1
7968 || idesc
->operands
[i
] == IA64_OPND_R2
7969 || idesc
->operands
[i
] == IA64_OPND_R3
)
7971 int num
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
7972 /* Assumes that md.rot.num_regs is always valid */
7973 if (md
.rot
.num_regs
> 0
7975 && num
< 31 + md
.rot
.num_regs
)
7977 specs
[count
] = tmpl
;
7978 specs
[count
++].specific
= 0;
7981 else if (idesc
->operands
[i
] == IA64_OPND_F1
7982 || idesc
->operands
[i
] == IA64_OPND_F2
7983 || idesc
->operands
[i
] == IA64_OPND_F3
7984 || idesc
->operands
[i
] == IA64_OPND_F4
)
7986 int num
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_FR
;
7989 specs
[count
] = tmpl
;
7990 specs
[count
++].specific
= 0;
7993 else if (idesc
->operands
[i
] == IA64_OPND_P1
7994 || idesc
->operands
[i
] == IA64_OPND_P2
)
7996 int num
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_P
;
7999 specs
[count
] = tmpl
;
8000 specs
[count
++].specific
= 0;
8004 if (CURR_SLOT
.qp_regno
> 15)
8006 specs
[count
] = tmpl
;
8007 specs
[count
++].specific
= 0;
8012 /* This is the same as IA64_RS_PRr, except simplified to account for
8013 the fact that there is only one register. */
8017 specs
[count
++] = tmpl
;
8022 if (idesc
->operands
[2] == IA64_OPND_IMM17
)
8023 mask
= CURR_SLOT
.opnd
[2].X_add_number
;
8024 if (mask
& ((valueT
) 1 << 63))
8025 specs
[count
++] = tmpl
;
8027 else if (note
== 11)
8029 if ((idesc
->operands
[0] == IA64_OPND_P1
8030 && CURR_SLOT
.opnd
[0].X_add_number
- REG_P
== 63)
8031 || (idesc
->operands
[1] == IA64_OPND_P2
8032 && CURR_SLOT
.opnd
[1].X_add_number
- REG_P
== 63))
8034 specs
[count
++] = tmpl
;
8037 else if (note
== 12)
8039 if (CURR_SLOT
.qp_regno
== 63)
8041 specs
[count
++] = tmpl
;
8048 int p1
= CURR_SLOT
.opnd
[0].X_add_number
- REG_P
;
8049 int p2
= CURR_SLOT
.opnd
[1].X_add_number
- REG_P
;
8050 int or_andcm
= strstr(idesc
->name
, "or.andcm") != NULL
;
8051 int and_orcm
= strstr(idesc
->name
, "and.orcm") != NULL
;
8054 && (idesc
->operands
[0] == IA64_OPND_P1
8055 || idesc
->operands
[0] == IA64_OPND_P2
))
8057 specs
[count
] = tmpl
;
8058 specs
[count
++].cmp_type
=
8059 (or_andcm
? CMP_OR
: (and_orcm
? CMP_AND
: CMP_NONE
));
8062 && (idesc
->operands
[1] == IA64_OPND_P1
8063 || idesc
->operands
[1] == IA64_OPND_P2
))
8065 specs
[count
] = tmpl
;
8066 specs
[count
++].cmp_type
=
8067 (or_andcm
? CMP_AND
: (and_orcm
? CMP_OR
: CMP_NONE
));
8072 if (CURR_SLOT
.qp_regno
== 63)
8074 specs
[count
++] = tmpl
;
8085 /* FIXME we can identify some individual RSE written resources, but RSE
8086 read resources have not yet been completely identified, so for now
8087 treat RSE as a single resource */
8088 if (strncmp (idesc
->name
, "mov", 3) == 0)
8092 if (idesc
->operands
[0] == IA64_OPND_AR3
8093 && CURR_SLOT
.opnd
[0].X_add_number
- REG_AR
== AR_BSPSTORE
)
8095 specs
[count
] = tmpl
;
8096 specs
[count
++].index
= 0; /* IA64_RSE_BSPLOAD/RNATBITINDEX */
8101 if (idesc
->operands
[0] == IA64_OPND_AR3
)
8103 if (CURR_SLOT
.opnd
[0].X_add_number
- REG_AR
== AR_BSPSTORE
8104 || CURR_SLOT
.opnd
[0].X_add_number
- REG_AR
== AR_RNAT
)
8106 specs
[count
++] = tmpl
;
8109 else if (idesc
->operands
[1] == IA64_OPND_AR3
)
8111 if (CURR_SLOT
.opnd
[1].X_add_number
- REG_AR
== AR_BSP
8112 || CURR_SLOT
.opnd
[1].X_add_number
- REG_AR
== AR_BSPSTORE
8113 || CURR_SLOT
.opnd
[1].X_add_number
- REG_AR
== AR_RNAT
)
8115 specs
[count
++] = tmpl
;
8122 specs
[count
++] = tmpl
;
8127 /* FIXME -- do any of these need to be non-specific? */
8128 specs
[count
++] = tmpl
;
8132 as_bad (_("Unrecognized dependency specifier %d\n"), dep
->specifier
);
8139 /* Clear branch flags on marked resources. This breaks the link between the
8140 QP of the marking instruction and a subsequent branch on the same QP. */
8143 clear_qp_branch_flag (mask
)
8147 for (i
= 0; i
< regdepslen
; i
++)
8149 valueT bit
= ((valueT
) 1 << regdeps
[i
].qp_regno
);
8150 if ((bit
& mask
) != 0)
8152 regdeps
[i
].link_to_qp_branch
= 0;
8157 /* Remove any mutexes which contain any of the PRs indicated in the mask.
8159 Any changes to a PR clears the mutex relations which include that PR. */
8162 clear_qp_mutex (mask
)
8168 while (i
< qp_mutexeslen
)
8170 if ((qp_mutexes
[i
].prmask
& mask
) != 0)
8174 fprintf (stderr
, " Clearing mutex relation");
8175 print_prmask (qp_mutexes
[i
].prmask
);
8176 fprintf (stderr
, "\n");
8178 qp_mutexes
[i
] = qp_mutexes
[--qp_mutexeslen
];
8185 /* Clear implies relations which contain PRs in the given masks.
8186 P1_MASK indicates the source of the implies relation, while P2_MASK
8187 indicates the implied PR. */
8190 clear_qp_implies (p1_mask
, p2_mask
)
8197 while (i
< qp_implieslen
)
8199 if ((((valueT
) 1 << qp_implies
[i
].p1
) & p1_mask
) != 0
8200 || (((valueT
) 1 << qp_implies
[i
].p2
) & p2_mask
) != 0)
8203 fprintf (stderr
, "Clearing implied relation PR%d->PR%d\n",
8204 qp_implies
[i
].p1
, qp_implies
[i
].p2
);
8205 qp_implies
[i
] = qp_implies
[--qp_implieslen
];
8212 /* Add the PRs specified to the list of implied relations. */
8215 add_qp_imply (p1
, p2
)
8222 /* p0 is not meaningful here. */
8223 if (p1
== 0 || p2
== 0)
8229 /* If it exists already, ignore it. */
8230 for (i
= 0; i
< qp_implieslen
; i
++)
8232 if (qp_implies
[i
].p1
== p1
8233 && qp_implies
[i
].p2
== p2
8234 && qp_implies
[i
].path
== md
.path
8235 && !qp_implies
[i
].p2_branched
)
8239 if (qp_implieslen
== qp_impliestotlen
)
8241 qp_impliestotlen
+= 20;
8242 qp_implies
= (struct qp_imply
*)
8243 xrealloc ((void *) qp_implies
,
8244 qp_impliestotlen
* sizeof (struct qp_imply
));
8247 fprintf (stderr
, " Registering PR%d implies PR%d\n", p1
, p2
);
8248 qp_implies
[qp_implieslen
].p1
= p1
;
8249 qp_implies
[qp_implieslen
].p2
= p2
;
8250 qp_implies
[qp_implieslen
].path
= md
.path
;
8251 qp_implies
[qp_implieslen
++].p2_branched
= 0;
8253 /* Add in the implied transitive relations; for everything that p2 implies,
8254 make p1 imply that, too; for everything that implies p1, make it imply p2
8256 for (i
= 0; i
< qp_implieslen
; i
++)
8258 if (qp_implies
[i
].p1
== p2
)
8259 add_qp_imply (p1
, qp_implies
[i
].p2
);
8260 if (qp_implies
[i
].p2
== p1
)
8261 add_qp_imply (qp_implies
[i
].p1
, p2
);
8263 /* Add in mutex relations implied by this implies relation; for each mutex
8264 relation containing p2, duplicate it and replace p2 with p1. */
8265 bit
= (valueT
) 1 << p1
;
8266 mask
= (valueT
) 1 << p2
;
8267 for (i
= 0; i
< qp_mutexeslen
; i
++)
8269 if (qp_mutexes
[i
].prmask
& mask
)
8270 add_qp_mutex ((qp_mutexes
[i
].prmask
& ~mask
) | bit
);
8274 /* Add the PRs specified in the mask to the mutex list; this means that only
8275 one of the PRs can be true at any time. PR0 should never be included in
8285 if (qp_mutexeslen
== qp_mutexestotlen
)
8287 qp_mutexestotlen
+= 20;
8288 qp_mutexes
= (struct qpmutex
*)
8289 xrealloc ((void *) qp_mutexes
,
8290 qp_mutexestotlen
* sizeof (struct qpmutex
));
8294 fprintf (stderr
, " Registering mutex on");
8295 print_prmask (mask
);
8296 fprintf (stderr
, "\n");
8298 qp_mutexes
[qp_mutexeslen
].path
= md
.path
;
8299 qp_mutexes
[qp_mutexeslen
++].prmask
= mask
;
8303 clear_register_values ()
8307 fprintf (stderr
, " Clearing register values\n");
8308 for (i
= 1; i
< NELEMS (gr_values
); i
++)
8309 gr_values
[i
].known
= 0;
8312 /* Keep track of register values/changes which affect DV tracking.
8314 optimization note: should add a flag to classes of insns where otherwise we
8315 have to examine a group of strings to identify them. */
8318 note_register_values (idesc
)
8319 struct ia64_opcode
*idesc
;
8321 valueT qp_changemask
= 0;
8324 /* Invalidate values for registers being written to. */
8325 for (i
= 0; i
< idesc
->num_outputs
; i
++)
8327 if (idesc
->operands
[i
] == IA64_OPND_R1
8328 || idesc
->operands
[i
] == IA64_OPND_R2
8329 || idesc
->operands
[i
] == IA64_OPND_R3
)
8331 int regno
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
8332 if (regno
> 0 && regno
< NELEMS (gr_values
))
8333 gr_values
[regno
].known
= 0;
8335 else if (idesc
->operands
[i
] == IA64_OPND_R3_2
)
8337 int regno
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
8338 if (regno
> 0 && regno
< 4)
8339 gr_values
[regno
].known
= 0;
8341 else if (idesc
->operands
[i
] == IA64_OPND_P1
8342 || idesc
->operands
[i
] == IA64_OPND_P2
)
8344 int regno
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_P
;
8345 qp_changemask
|= (valueT
) 1 << regno
;
8347 else if (idesc
->operands
[i
] == IA64_OPND_PR
)
8349 if (idesc
->operands
[2] & (valueT
) 0x10000)
8350 qp_changemask
= ~(valueT
) 0x1FFFF | idesc
->operands
[2];
8352 qp_changemask
= idesc
->operands
[2];
8355 else if (idesc
->operands
[i
] == IA64_OPND_PR_ROT
)
8357 if (idesc
->operands
[1] & ((valueT
) 1 << 43))
8358 qp_changemask
= ~(valueT
) 0xFFFFFFFFFFF | idesc
->operands
[1];
8360 qp_changemask
= idesc
->operands
[1];
8361 qp_changemask
&= ~(valueT
) 0xFFFF;
8366 /* Always clear qp branch flags on any PR change. */
8367 /* FIXME there may be exceptions for certain compares. */
8368 clear_qp_branch_flag (qp_changemask
);
8370 /* Invalidate rotating registers on insns which affect RRBs in CFM. */
8371 if (idesc
->flags
& IA64_OPCODE_MOD_RRBS
)
8373 qp_changemask
|= ~(valueT
) 0xFFFF;
8374 if (strcmp (idesc
->name
, "clrrrb.pr") != 0)
8376 for (i
= 32; i
< 32 + md
.rot
.num_regs
; i
++)
8377 gr_values
[i
].known
= 0;
8379 clear_qp_mutex (qp_changemask
);
8380 clear_qp_implies (qp_changemask
, qp_changemask
);
8382 /* After a call, all register values are undefined, except those marked
8384 else if (strncmp (idesc
->name
, "br.call", 6) == 0
8385 || strncmp (idesc
->name
, "brl.call", 7) == 0)
8387 /* FIXME keep GR values which are marked as "safe_across_calls" */
8388 clear_register_values ();
8389 clear_qp_mutex (~qp_safe_across_calls
);
8390 clear_qp_implies (~qp_safe_across_calls
, ~qp_safe_across_calls
);
8391 clear_qp_branch_flag (~qp_safe_across_calls
);
8393 else if (is_interruption_or_rfi (idesc
)
8394 || is_taken_branch (idesc
))
8396 clear_register_values ();
8397 clear_qp_mutex (~(valueT
) 0);
8398 clear_qp_implies (~(valueT
) 0, ~(valueT
) 0);
8400 /* Look for mutex and implies relations. */
8401 else if ((idesc
->operands
[0] == IA64_OPND_P1
8402 || idesc
->operands
[0] == IA64_OPND_P2
)
8403 && (idesc
->operands
[1] == IA64_OPND_P1
8404 || idesc
->operands
[1] == IA64_OPND_P2
))
8406 int p1
= CURR_SLOT
.opnd
[0].X_add_number
- REG_P
;
8407 int p2
= CURR_SLOT
.opnd
[1].X_add_number
- REG_P
;
8408 valueT p1mask
= (valueT
) 1 << p1
;
8409 valueT p2mask
= (valueT
) 1 << p2
;
8411 /* If one of the PRs is PR0, we can't really do anything. */
8412 if (p1
== 0 || p2
== 0)
8415 fprintf (stderr
, " Ignoring PRs due to inclusion of p0\n");
8417 /* In general, clear mutexes and implies which include P1 or P2,
8418 with the following exceptions. */
8419 else if (strstr (idesc
->name
, ".or.andcm") != NULL
)
8421 add_qp_mutex (p1mask
| p2mask
);
8422 clear_qp_implies (p2mask
, p1mask
);
8424 else if (strstr (idesc
->name
, ".and.orcm") != NULL
)
8426 add_qp_mutex (p1mask
| p2mask
);
8427 clear_qp_implies (p1mask
, p2mask
);
8429 else if (strstr (idesc
->name
, ".and") != NULL
)
8431 clear_qp_implies (0, p1mask
| p2mask
);
8433 else if (strstr (idesc
->name
, ".or") != NULL
)
8435 clear_qp_mutex (p1mask
| p2mask
);
8436 clear_qp_implies (p1mask
| p2mask
, 0);
8440 clear_qp_implies (p1mask
| p2mask
, p1mask
| p2mask
);
8441 if (strstr (idesc
->name
, ".unc") != NULL
)
8443 add_qp_mutex (p1mask
| p2mask
);
8444 if (CURR_SLOT
.qp_regno
!= 0)
8446 add_qp_imply (CURR_SLOT
.opnd
[0].X_add_number
- REG_P
,
8447 CURR_SLOT
.qp_regno
);
8448 add_qp_imply (CURR_SLOT
.opnd
[1].X_add_number
- REG_P
,
8449 CURR_SLOT
.qp_regno
);
8452 else if (CURR_SLOT
.qp_regno
== 0)
8454 add_qp_mutex (p1mask
| p2mask
);
8458 clear_qp_mutex (p1mask
| p2mask
);
8462 /* Look for mov imm insns into GRs. */
8463 else if (idesc
->operands
[0] == IA64_OPND_R1
8464 && (idesc
->operands
[1] == IA64_OPND_IMM22
8465 || idesc
->operands
[1] == IA64_OPND_IMMU64
)
8466 && (strcmp (idesc
->name
, "mov") == 0
8467 || strcmp (idesc
->name
, "movl") == 0))
8469 int regno
= CURR_SLOT
.opnd
[0].X_add_number
- REG_GR
;
8470 if (regno
> 0 && regno
< NELEMS (gr_values
))
8472 gr_values
[regno
].known
= 1;
8473 gr_values
[regno
].value
= CURR_SLOT
.opnd
[1].X_add_number
;
8474 gr_values
[regno
].path
= md
.path
;
8477 fprintf (stderr
, " Know gr%d = ", regno
);
8478 fprintf_vma (stderr
, gr_values
[regno
].value
);
8479 fputs ("\n", stderr
);
8485 clear_qp_mutex (qp_changemask
);
8486 clear_qp_implies (qp_changemask
, qp_changemask
);
8490 /* Return whether the given predicate registers are currently mutex. */
8493 qp_mutex (p1
, p2
, path
)
8503 mask
= ((valueT
) 1 << p1
) | (valueT
) 1 << p2
;
8504 for (i
= 0; i
< qp_mutexeslen
; i
++)
8506 if (qp_mutexes
[i
].path
>= path
8507 && (qp_mutexes
[i
].prmask
& mask
) == mask
)
8514 /* Return whether the given resource is in the given insn's list of chks
8515 Return 1 if the conflict is absolutely determined, 2 if it's a potential
8519 resources_match (rs
, idesc
, note
, qp_regno
, path
)
8521 struct ia64_opcode
*idesc
;
8526 struct rsrc specs
[MAX_SPECS
];
8529 /* If the marked resource's qp_regno and the given qp_regno are mutex,
8530 we don't need to check. One exception is note 11, which indicates that
8531 target predicates are written regardless of PR[qp]. */
8532 if (qp_mutex (rs
->qp_regno
, qp_regno
, path
)
8536 count
= specify_resource (rs
->dependency
, idesc
, DV_CHK
, specs
, note
, path
);
8539 /* UNAT checking is a bit more specific than other resources */
8540 if (rs
->dependency
->specifier
== IA64_RS_AR_UNAT
8541 && specs
[count
].mem_offset
.hint
8542 && rs
->mem_offset
.hint
)
8544 if (rs
->mem_offset
.base
== specs
[count
].mem_offset
.base
)
8546 if (((rs
->mem_offset
.offset
>> 3) & 0x3F) ==
8547 ((specs
[count
].mem_offset
.offset
>> 3) & 0x3F))
8554 /* Skip apparent PR write conflicts where both writes are an AND or both
8555 writes are an OR. */
8556 if (rs
->dependency
->specifier
== IA64_RS_PR
8557 || rs
->dependency
->specifier
== IA64_RS_PRr
8558 || rs
->dependency
->specifier
== IA64_RS_PR63
)
8560 if (specs
[count
].cmp_type
!= CMP_NONE
8561 && specs
[count
].cmp_type
== rs
->cmp_type
)
8564 fprintf (stderr
, " %s on parallel compare allowed (PR%d)\n",
8565 dv_mode
[rs
->dependency
->mode
],
8566 rs
->dependency
->specifier
!= IA64_RS_PR63
?
8567 specs
[count
].index
: 63);
8572 " %s on parallel compare conflict %s vs %s on PR%d\n",
8573 dv_mode
[rs
->dependency
->mode
],
8574 dv_cmp_type
[rs
->cmp_type
],
8575 dv_cmp_type
[specs
[count
].cmp_type
],
8576 rs
->dependency
->specifier
!= IA64_RS_PR63
?
8577 specs
[count
].index
: 63);
8581 /* If either resource is not specific, conservatively assume a conflict
8583 if (!specs
[count
].specific
|| !rs
->specific
)
8585 else if (specs
[count
].index
== rs
->index
)
8590 fprintf (stderr
, " No %s conflicts\n", rs
->dependency
->name
);
8596 /* Indicate an instruction group break; if INSERT_STOP is non-zero, then
8597 insert a stop to create the break. Update all resource dependencies
8598 appropriately. If QP_REGNO is non-zero, only apply the break to resources
8599 which use the same QP_REGNO and have the link_to_qp_branch flag set.
8600 If SAVE_CURRENT is non-zero, don't affect resources marked by the current
8604 insn_group_break (insert_stop
, qp_regno
, save_current
)
8611 if (insert_stop
&& md
.num_slots_in_use
> 0)
8612 PREV_SLOT
.end_of_insn_group
= 1;
8616 fprintf (stderr
, " Insn group break%s",
8617 (insert_stop
? " (w/stop)" : ""));
8619 fprintf (stderr
, " effective for QP=%d", qp_regno
);
8620 fprintf (stderr
, "\n");
8624 while (i
< regdepslen
)
8626 const struct ia64_dependency
*dep
= regdeps
[i
].dependency
;
8629 && regdeps
[i
].qp_regno
!= qp_regno
)
8636 && CURR_SLOT
.src_file
== regdeps
[i
].file
8637 && CURR_SLOT
.src_line
== regdeps
[i
].line
)
8643 /* clear dependencies which are automatically cleared by a stop, or
8644 those that have reached the appropriate state of insn serialization */
8645 if (dep
->semantics
== IA64_DVS_IMPLIED
8646 || dep
->semantics
== IA64_DVS_IMPLIEDF
8647 || regdeps
[i
].insn_srlz
== STATE_SRLZ
)
8649 print_dependency ("Removing", i
);
8650 regdeps
[i
] = regdeps
[--regdepslen
];
8654 if (dep
->semantics
== IA64_DVS_DATA
8655 || dep
->semantics
== IA64_DVS_INSTR
8656 || dep
->semantics
== IA64_DVS_SPECIFIC
)
8658 if (regdeps
[i
].insn_srlz
== STATE_NONE
)
8659 regdeps
[i
].insn_srlz
= STATE_STOP
;
8660 if (regdeps
[i
].data_srlz
== STATE_NONE
)
8661 regdeps
[i
].data_srlz
= STATE_STOP
;
8668 /* Add the given resource usage spec to the list of active dependencies. */
8671 mark_resource (idesc
, dep
, spec
, depind
, path
)
8672 struct ia64_opcode
*idesc ATTRIBUTE_UNUSED
;
8673 const struct ia64_dependency
*dep ATTRIBUTE_UNUSED
;
8678 if (regdepslen
== regdepstotlen
)
8680 regdepstotlen
+= 20;
8681 regdeps
= (struct rsrc
*)
8682 xrealloc ((void *) regdeps
,
8683 regdepstotlen
* sizeof (struct rsrc
));
8686 regdeps
[regdepslen
] = *spec
;
8687 regdeps
[regdepslen
].depind
= depind
;
8688 regdeps
[regdepslen
].path
= path
;
8689 regdeps
[regdepslen
].file
= CURR_SLOT
.src_file
;
8690 regdeps
[regdepslen
].line
= CURR_SLOT
.src_line
;
8692 print_dependency ("Adding", regdepslen
);
8698 print_dependency (action
, depind
)
8704 fprintf (stderr
, " %s %s '%s'",
8705 action
, dv_mode
[(regdeps
[depind
].dependency
)->mode
],
8706 (regdeps
[depind
].dependency
)->name
);
8707 if (regdeps
[depind
].specific
&& regdeps
[depind
].index
!= 0)
8708 fprintf (stderr
, " (%d)", regdeps
[depind
].index
);
8709 if (regdeps
[depind
].mem_offset
.hint
)
8711 fputs (" ", stderr
);
8712 fprintf_vma (stderr
, regdeps
[depind
].mem_offset
.base
);
8713 fputs ("+", stderr
);
8714 fprintf_vma (stderr
, regdeps
[depind
].mem_offset
.offset
);
8716 fprintf (stderr
, "\n");
8721 instruction_serialization ()
8725 fprintf (stderr
, " Instruction serialization\n");
8726 for (i
= 0; i
< regdepslen
; i
++)
8727 if (regdeps
[i
].insn_srlz
== STATE_STOP
)
8728 regdeps
[i
].insn_srlz
= STATE_SRLZ
;
8732 data_serialization ()
8736 fprintf (stderr
, " Data serialization\n");
8737 while (i
< regdepslen
)
8739 if (regdeps
[i
].data_srlz
== STATE_STOP
8740 /* Note: as of 991210, all "other" dependencies are cleared by a
8741 data serialization. This might change with new tables */
8742 || (regdeps
[i
].dependency
)->semantics
== IA64_DVS_OTHER
)
8744 print_dependency ("Removing", i
);
8745 regdeps
[i
] = regdeps
[--regdepslen
];
8752 /* Insert stops and serializations as needed to avoid DVs. */
8755 remove_marked_resource (rs
)
8758 switch (rs
->dependency
->semantics
)
8760 case IA64_DVS_SPECIFIC
:
8762 fprintf (stderr
, "Implementation-specific, assume worst case...\n");
8763 /* ...fall through... */
8764 case IA64_DVS_INSTR
:
8766 fprintf (stderr
, "Inserting instr serialization\n");
8767 if (rs
->insn_srlz
< STATE_STOP
)
8768 insn_group_break (1, 0, 0);
8769 if (rs
->insn_srlz
< STATE_SRLZ
)
8771 int oldqp
= CURR_SLOT
.qp_regno
;
8772 struct ia64_opcode
*oldidesc
= CURR_SLOT
.idesc
;
8773 /* Manually jam a srlz.i insn into the stream */
8774 CURR_SLOT
.qp_regno
= 0;
8775 CURR_SLOT
.idesc
= ia64_find_opcode ("srlz.i");
8776 instruction_serialization ();
8777 md
.curr_slot
= (md
.curr_slot
+ 1) % NUM_SLOTS
;
8778 if (++md
.num_slots_in_use
>= NUM_SLOTS
)
8780 CURR_SLOT
.qp_regno
= oldqp
;
8781 CURR_SLOT
.idesc
= oldidesc
;
8783 insn_group_break (1, 0, 0);
8785 case IA64_DVS_OTHER
: /* as of rev2 (991220) of the DV tables, all
8786 "other" types of DV are eliminated
8787 by a data serialization */
8790 fprintf (stderr
, "Inserting data serialization\n");
8791 if (rs
->data_srlz
< STATE_STOP
)
8792 insn_group_break (1, 0, 0);
8794 int oldqp
= CURR_SLOT
.qp_regno
;
8795 struct ia64_opcode
*oldidesc
= CURR_SLOT
.idesc
;
8796 /* Manually jam a srlz.d insn into the stream */
8797 CURR_SLOT
.qp_regno
= 0;
8798 CURR_SLOT
.idesc
= ia64_find_opcode ("srlz.d");
8799 data_serialization ();
8800 md
.curr_slot
= (md
.curr_slot
+ 1) % NUM_SLOTS
;
8801 if (++md
.num_slots_in_use
>= NUM_SLOTS
)
8803 CURR_SLOT
.qp_regno
= oldqp
;
8804 CURR_SLOT
.idesc
= oldidesc
;
8807 case IA64_DVS_IMPLIED
:
8808 case IA64_DVS_IMPLIEDF
:
8810 fprintf (stderr
, "Inserting stop\n");
8811 insn_group_break (1, 0, 0);
8818 /* Check the resources used by the given opcode against the current dependency
8821 The check is run once for each execution path encountered. In this case,
8822 a unique execution path is the sequence of instructions following a code
8823 entry point, e.g. the following has three execution paths, one starting
8824 at L0, one at L1, and one at L2.
8833 check_dependencies (idesc
)
8834 struct ia64_opcode
*idesc
;
8836 const struct ia64_opcode_dependency
*opdeps
= idesc
->dependencies
;
8840 /* Note that the number of marked resources may change within the
8841 loop if in auto mode. */
8843 while (i
< regdepslen
)
8845 struct rsrc
*rs
= ®deps
[i
];
8846 const struct ia64_dependency
*dep
= rs
->dependency
;
8851 if (dep
->semantics
== IA64_DVS_NONE
8852 || (chkind
= depends_on (rs
->depind
, idesc
)) == -1)
8858 note
= NOTE (opdeps
->chks
[chkind
]);
8860 /* Check this resource against each execution path seen thus far. */
8861 for (path
= 0; path
<= md
.path
; path
++)
8865 /* If the dependency wasn't on the path being checked, ignore it. */
8866 if (rs
->path
< path
)
8869 /* If the QP for this insn implies a QP which has branched, don't
8870 bother checking. Ed. NOTE: I don't think this check is terribly
8871 useful; what's the point of generating code which will only be
8872 reached if its QP is zero?
8873 This code was specifically inserted to handle the following code,
8874 based on notes from Intel's DV checking code, where p1 implies p2.
8880 if (CURR_SLOT
.qp_regno
!= 0)
8884 for (implies
= 0; implies
< qp_implieslen
; implies
++)
8886 if (qp_implies
[implies
].path
>= path
8887 && qp_implies
[implies
].p1
== CURR_SLOT
.qp_regno
8888 && qp_implies
[implies
].p2_branched
)
8898 if ((matchtype
= resources_match (rs
, idesc
, note
,
8899 CURR_SLOT
.qp_regno
, path
)) != 0)
8902 char pathmsg
[256] = "";
8903 char indexmsg
[256] = "";
8904 int certain
= (matchtype
== 1 && CURR_SLOT
.qp_regno
== 0);
8907 sprintf (pathmsg
, " when entry is at label '%s'",
8908 md
.entry_labels
[path
- 1]);
8909 if (rs
->specific
&& rs
->index
!= 0)
8910 sprintf (indexmsg
, ", specific resource number is %d",
8912 sprintf (msg
, "Use of '%s' %s %s dependency '%s' (%s)%s%s",
8914 (certain
? "violates" : "may violate"),
8915 dv_mode
[dep
->mode
], dep
->name
,
8916 dv_sem
[dep
->semantics
],
8919 if (md
.explicit_mode
)
8921 as_warn ("%s", msg
);
8923 as_warn (_("Only the first path encountering the conflict "
8925 as_warn_where (rs
->file
, rs
->line
,
8926 _("This is the location of the "
8927 "conflicting usage"));
8928 /* Don't bother checking other paths, to avoid duplicating
8935 fprintf (stderr
, "%s @ %s:%d\n", msg
, rs
->file
, rs
->line
);
8937 remove_marked_resource (rs
);
8939 /* since the set of dependencies has changed, start over */
8940 /* FIXME -- since we're removing dvs as we go, we
8941 probably don't really need to start over... */
8954 /* Register new dependencies based on the given opcode. */
8957 mark_resources (idesc
)
8958 struct ia64_opcode
*idesc
;
8961 const struct ia64_opcode_dependency
*opdeps
= idesc
->dependencies
;
8962 int add_only_qp_reads
= 0;
8964 /* A conditional branch only uses its resources if it is taken; if it is
8965 taken, we stop following that path. The other branch types effectively
8966 *always* write their resources. If it's not taken, register only QP
8968 if (is_conditional_branch (idesc
) || is_interruption_or_rfi (idesc
))
8970 add_only_qp_reads
= 1;
8974 fprintf (stderr
, "Registering '%s' resource usage\n", idesc
->name
);
8976 for (i
= 0; i
< opdeps
->nregs
; i
++)
8978 const struct ia64_dependency
*dep
;
8979 struct rsrc specs
[MAX_SPECS
];
8984 dep
= ia64_find_dependency (opdeps
->regs
[i
]);
8985 note
= NOTE (opdeps
->regs
[i
]);
8987 if (add_only_qp_reads
8988 && !(dep
->mode
== IA64_DV_WAR
8989 && (dep
->specifier
== IA64_RS_PR
8990 || dep
->specifier
== IA64_RS_PRr
8991 || dep
->specifier
== IA64_RS_PR63
)))
8994 count
= specify_resource (dep
, idesc
, DV_REG
, specs
, note
, md
.path
);
8997 if (md
.debug_dv
&& !count
)
8998 fprintf (stderr
, " No %s %s usage found (path %d)\n",
8999 dv_mode
[dep
->mode
], dep
->name
, md
.path
);
9004 mark_resource (idesc
, dep
, &specs
[count
],
9005 DEP (opdeps
->regs
[i
]), md
.path
);
9008 /* The execution path may affect register values, which may in turn
9009 affect which indirect-access resources are accessed. */
9010 switch (dep
->specifier
)
9022 for (path
= 0; path
< md
.path
; path
++)
9024 count
= specify_resource (dep
, idesc
, DV_REG
, specs
, note
, path
);
9026 mark_resource (idesc
, dep
, &specs
[count
],
9027 DEP (opdeps
->regs
[i
]), path
);
9034 /* Remove dependencies when they no longer apply. */
9037 update_dependencies (idesc
)
9038 struct ia64_opcode
*idesc
;
9042 if (strcmp (idesc
->name
, "srlz.i") == 0)
9044 instruction_serialization ();
9046 else if (strcmp (idesc
->name
, "srlz.d") == 0)
9048 data_serialization ();
9050 else if (is_interruption_or_rfi (idesc
)
9051 || is_taken_branch (idesc
))
9053 /* Although technically the taken branch doesn't clear dependencies
9054 which require a srlz.[id], we don't follow the branch; the next
9055 instruction is assumed to start with a clean slate. */
9059 else if (is_conditional_branch (idesc
)
9060 && CURR_SLOT
.qp_regno
!= 0)
9062 int is_call
= strstr (idesc
->name
, ".call") != NULL
;
9064 for (i
= 0; i
< qp_implieslen
; i
++)
9066 /* If the conditional branch's predicate is implied by the predicate
9067 in an existing dependency, remove that dependency. */
9068 if (qp_implies
[i
].p2
== CURR_SLOT
.qp_regno
)
9071 /* Note that this implied predicate takes a branch so that if
9072 a later insn generates a DV but its predicate implies this
9073 one, we can avoid the false DV warning. */
9074 qp_implies
[i
].p2_branched
= 1;
9075 while (depind
< regdepslen
)
9077 if (regdeps
[depind
].qp_regno
== qp_implies
[i
].p1
)
9079 print_dependency ("Removing", depind
);
9080 regdeps
[depind
] = regdeps
[--regdepslen
];
9087 /* Any marked resources which have this same predicate should be
9088 cleared, provided that the QP hasn't been modified between the
9089 marking instruction and the branch. */
9092 insn_group_break (0, CURR_SLOT
.qp_regno
, 1);
9097 while (i
< regdepslen
)
9099 if (regdeps
[i
].qp_regno
== CURR_SLOT
.qp_regno
9100 && regdeps
[i
].link_to_qp_branch
9101 && (regdeps
[i
].file
!= CURR_SLOT
.src_file
9102 || regdeps
[i
].line
!= CURR_SLOT
.src_line
))
9104 /* Treat like a taken branch */
9105 print_dependency ("Removing", i
);
9106 regdeps
[i
] = regdeps
[--regdepslen
];
9115 /* Examine the current instruction for dependency violations. */
9119 struct ia64_opcode
*idesc
;
9123 fprintf (stderr
, "Checking %s for violations (line %d, %d/%d)\n",
9124 idesc
->name
, CURR_SLOT
.src_line
,
9125 idesc
->dependencies
->nchks
,
9126 idesc
->dependencies
->nregs
);
9129 /* Look through the list of currently marked resources; if the current
9130 instruction has the dependency in its chks list which uses that resource,
9131 check against the specific resources used. */
9132 check_dependencies (idesc
);
9134 /* Look up the instruction's regdeps (RAW writes, WAW writes, and WAR reads),
9135 then add them to the list of marked resources. */
9136 mark_resources (idesc
);
9138 /* There are several types of dependency semantics, and each has its own
9139 requirements for being cleared
9141 Instruction serialization (insns separated by interruption, rfi, or
9142 writer + srlz.i + reader, all in separate groups) clears DVS_INSTR.
9144 Data serialization (instruction serialization, or writer + srlz.d +
9145 reader, where writer and srlz.d are in separate groups) clears
9146 DVS_DATA. (This also clears DVS_OTHER, but that is not guaranteed to
9147 always be the case).
9149 Instruction group break (groups separated by stop, taken branch,
9150 interruption or rfi) clears DVS_IMPLIED and DVS_IMPLIEDF.
9152 update_dependencies (idesc
);
9154 /* Sometimes, knowing a register value allows us to avoid giving a false DV
9155 warning. Keep track of as many as possible that are useful. */
9156 note_register_values (idesc
);
9158 /* We don't need or want this anymore. */
9159 md
.mem_offset
.hint
= 0;
9164 /* Translate one line of assembly. Pseudo ops and labels do not show
9170 char *saved_input_line_pointer
, *mnemonic
;
9171 const struct pseudo_opcode
*pdesc
;
9172 struct ia64_opcode
*idesc
;
9173 unsigned char qp_regno
;
9177 saved_input_line_pointer
= input_line_pointer
;
9178 input_line_pointer
= str
;
9180 /* extract the opcode (mnemonic): */
9182 mnemonic
= input_line_pointer
;
9183 ch
= get_symbol_end ();
9184 pdesc
= (struct pseudo_opcode
*) hash_find (md
.pseudo_hash
, mnemonic
);
9187 *input_line_pointer
= ch
;
9188 (*pdesc
->handler
) (pdesc
->arg
);
9192 /* Find the instruction descriptor matching the arguments. */
9194 idesc
= ia64_find_opcode (mnemonic
);
9195 *input_line_pointer
= ch
;
9198 as_bad ("Unknown opcode `%s'", mnemonic
);
9202 idesc
= parse_operands (idesc
);
9206 /* Handle the dynamic ops we can handle now: */
9207 if (idesc
->type
== IA64_TYPE_DYN
)
9209 if (strcmp (idesc
->name
, "add") == 0)
9211 if (CURR_SLOT
.opnd
[2].X_op
== O_register
9212 && CURR_SLOT
.opnd
[2].X_add_number
< 4)
9216 ia64_free_opcode (idesc
);
9217 idesc
= ia64_find_opcode (mnemonic
);
9219 know (!idesc
->next
);
9222 else if (strcmp (idesc
->name
, "mov") == 0)
9224 enum ia64_opnd opnd1
, opnd2
;
9227 opnd1
= idesc
->operands
[0];
9228 opnd2
= idesc
->operands
[1];
9229 if (opnd1
== IA64_OPND_AR3
)
9231 else if (opnd2
== IA64_OPND_AR3
)
9235 if (CURR_SLOT
.opnd
[rop
].X_op
== O_register
9236 && ar_is_in_integer_unit (CURR_SLOT
.opnd
[rop
].X_add_number
))
9240 ia64_free_opcode (idesc
);
9241 idesc
= ia64_find_opcode (mnemonic
);
9242 while (idesc
!= NULL
9243 && (idesc
->operands
[0] != opnd1
9244 || idesc
->operands
[1] != opnd2
))
9245 idesc
= get_next_opcode (idesc
);
9250 if (md
.qp
.X_op
== O_register
)
9252 qp_regno
= md
.qp
.X_add_number
- REG_P
;
9253 md
.qp
.X_op
= O_absent
;
9256 flags
= idesc
->flags
;
9258 if ((flags
& IA64_OPCODE_FIRST
) != 0)
9259 insn_group_break (1, 0, 0);
9261 if ((flags
& IA64_OPCODE_NO_PRED
) != 0 && qp_regno
!= 0)
9263 as_bad ("`%s' cannot be predicated", idesc
->name
);
9267 /* Build the instruction. */
9268 CURR_SLOT
.qp_regno
= qp_regno
;
9269 CURR_SLOT
.idesc
= idesc
;
9270 as_where (&CURR_SLOT
.src_file
, &CURR_SLOT
.src_line
);
9271 dwarf2_where (&CURR_SLOT
.debug_line
);
9273 /* Add unwind entry, if there is one. */
9274 if (unwind
.current_entry
)
9276 CURR_SLOT
.unwind_record
= unwind
.current_entry
;
9277 unwind
.current_entry
= NULL
;
9280 /* Check for dependency violations. */
9284 md
.curr_slot
= (md
.curr_slot
+ 1) % NUM_SLOTS
;
9285 if (++md
.num_slots_in_use
>= NUM_SLOTS
)
9288 if ((flags
& IA64_OPCODE_LAST
) != 0)
9289 insn_group_break (1, 0, 0);
9291 md
.last_text_seg
= now_seg
;
9294 input_line_pointer
= saved_input_line_pointer
;
9297 /* Called when symbol NAME cannot be found in the symbol table.
9298 Should be used for dynamic valued symbols only. */
9301 md_undefined_symbol (name
)
9302 char *name ATTRIBUTE_UNUSED
;
9307 /* Called for any expression that can not be recognized. When the
9308 function is called, `input_line_pointer' will point to the start of
9315 enum pseudo_type pseudo_type
;
9320 switch (*input_line_pointer
)
9323 /* Find what relocation pseudo-function we're dealing with. */
9325 ch
= *++input_line_pointer
;
9326 for (i
= 0; i
< NELEMS (pseudo_func
); ++i
)
9327 if (pseudo_func
[i
].name
&& pseudo_func
[i
].name
[0] == ch
)
9329 len
= strlen (pseudo_func
[i
].name
);
9330 if (strncmp (pseudo_func
[i
].name
+ 1,
9331 input_line_pointer
+ 1, len
- 1) == 0
9332 && !is_part_of_name (input_line_pointer
[len
]))
9334 input_line_pointer
+= len
;
9335 pseudo_type
= pseudo_func
[i
].type
;
9339 switch (pseudo_type
)
9341 case PSEUDO_FUNC_RELOC
:
9343 if (*input_line_pointer
!= '(')
9345 as_bad ("Expected '('");
9349 ++input_line_pointer
;
9351 if (*input_line_pointer
++ != ')')
9353 as_bad ("Missing ')'");
9356 if (e
->X_op
!= O_symbol
)
9358 if (e
->X_op
!= O_pseudo_fixup
)
9360 as_bad ("Not a symbolic expression");
9363 if (S_GET_VALUE (e
->X_op_symbol
) == FUNC_FPTR_RELATIVE
9364 && i
== FUNC_LT_RELATIVE
)
9365 i
= FUNC_LT_FPTR_RELATIVE
;
9368 as_bad ("Illegal combination of relocation functions");
9372 /* Make sure gas doesn't get rid of local symbols that are used
9374 e
->X_op
= O_pseudo_fixup
;
9375 e
->X_op_symbol
= pseudo_func
[i
].u
.sym
;
9378 case PSEUDO_FUNC_CONST
:
9379 e
->X_op
= O_constant
;
9380 e
->X_add_number
= pseudo_func
[i
].u
.ival
;
9383 case PSEUDO_FUNC_REG
:
9384 e
->X_op
= O_register
;
9385 e
->X_add_number
= pseudo_func
[i
].u
.ival
;
9389 name
= input_line_pointer
- 1;
9391 as_bad ("Unknown pseudo function `%s'", name
);
9397 ++input_line_pointer
;
9399 if (*input_line_pointer
!= ']')
9401 as_bad ("Closing bracket misssing");
9406 if (e
->X_op
!= O_register
)
9407 as_bad ("Register expected as index");
9409 ++input_line_pointer
;
9420 ignore_rest_of_line ();
9423 /* Return 1 if it's OK to adjust a reloc by replacing the symbol with
9424 a section symbol plus some offset. For relocs involving @fptr(),
9425 directives we don't want such adjustments since we need to have the
9426 original symbol's name in the reloc. */
9428 ia64_fix_adjustable (fix
)
9431 /* Prevent all adjustments to global symbols */
9432 if (S_IS_EXTERN (fix
->fx_addsy
) || S_IS_WEAK (fix
->fx_addsy
))
9435 switch (fix
->fx_r_type
)
9437 case BFD_RELOC_IA64_FPTR64I
:
9438 case BFD_RELOC_IA64_FPTR32MSB
:
9439 case BFD_RELOC_IA64_FPTR32LSB
:
9440 case BFD_RELOC_IA64_FPTR64MSB
:
9441 case BFD_RELOC_IA64_FPTR64LSB
:
9442 case BFD_RELOC_IA64_LTOFF_FPTR22
:
9443 case BFD_RELOC_IA64_LTOFF_FPTR64I
:
9453 ia64_force_relocation (fix
)
9456 switch (fix
->fx_r_type
)
9458 case BFD_RELOC_IA64_FPTR64I
:
9459 case BFD_RELOC_IA64_FPTR32MSB
:
9460 case BFD_RELOC_IA64_FPTR32LSB
:
9461 case BFD_RELOC_IA64_FPTR64MSB
:
9462 case BFD_RELOC_IA64_FPTR64LSB
:
9464 case BFD_RELOC_IA64_LTOFF22
:
9465 case BFD_RELOC_IA64_LTOFF64I
:
9466 case BFD_RELOC_IA64_LTOFF_FPTR22
:
9467 case BFD_RELOC_IA64_LTOFF_FPTR64I
:
9468 case BFD_RELOC_IA64_PLTOFF22
:
9469 case BFD_RELOC_IA64_PLTOFF64I
:
9470 case BFD_RELOC_IA64_PLTOFF64MSB
:
9471 case BFD_RELOC_IA64_PLTOFF64LSB
:
9480 /* Decide from what point a pc-relative relocation is relative to,
9481 relative to the pc-relative fixup. Er, relatively speaking. */
9483 ia64_pcrel_from_section (fix
, sec
)
9487 unsigned long off
= fix
->fx_frag
->fr_address
+ fix
->fx_where
;
9489 if (bfd_get_section_flags (stdoutput
, sec
) & SEC_CODE
)
9495 /* This is called whenever some data item (not an instruction) needs a
9496 fixup. We pick the right reloc code depending on the byteorder
9497 currently in effect. */
9499 ia64_cons_fix_new (f
, where
, nbytes
, exp
)
9505 bfd_reloc_code_real_type code
;
9510 /* There are no reloc for 8 and 16 bit quantities, but we allow
9511 them here since they will work fine as long as the expression
9512 is fully defined at the end of the pass over the source file. */
9513 case 1: code
= BFD_RELOC_8
; break;
9514 case 2: code
= BFD_RELOC_16
; break;
9516 if (target_big_endian
)
9517 code
= BFD_RELOC_IA64_DIR32MSB
;
9519 code
= BFD_RELOC_IA64_DIR32LSB
;
9523 if (target_big_endian
)
9524 code
= BFD_RELOC_IA64_DIR64MSB
;
9526 code
= BFD_RELOC_IA64_DIR64LSB
;
9530 as_bad ("Unsupported fixup size %d", nbytes
);
9531 ignore_rest_of_line ();
9534 if (exp
->X_op
== O_pseudo_fixup
)
9537 exp
->X_op
= O_symbol
;
9538 code
= ia64_gen_real_reloc_type (exp
->X_op_symbol
, code
);
9540 fix
= fix_new_exp (f
, where
, nbytes
, exp
, 0, code
);
9541 /* We need to store the byte order in effect in case we're going
9542 to fix an 8 or 16 bit relocation (for which there no real
9543 relocs available). See md_apply_fix(). */
9544 fix
->tc_fix_data
.bigendian
= target_big_endian
;
9547 /* Return the actual relocation we wish to associate with the pseudo
9548 reloc described by SYM and R_TYPE. SYM should be one of the
9549 symbols in the pseudo_func array, or NULL. */
9551 static bfd_reloc_code_real_type
9552 ia64_gen_real_reloc_type (sym
, r_type
)
9554 bfd_reloc_code_real_type r_type
;
9556 bfd_reloc_code_real_type
new = 0;
9563 switch (S_GET_VALUE (sym
))
9565 case FUNC_FPTR_RELATIVE
:
9568 case BFD_RELOC_IA64_IMM64
: new = BFD_RELOC_IA64_FPTR64I
; break;
9569 case BFD_RELOC_IA64_DIR32MSB
: new = BFD_RELOC_IA64_FPTR32MSB
; break;
9570 case BFD_RELOC_IA64_DIR32LSB
: new = BFD_RELOC_IA64_FPTR32LSB
; break;
9571 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_FPTR64MSB
; break;
9572 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_FPTR64LSB
; break;
9577 case FUNC_GP_RELATIVE
:
9580 case BFD_RELOC_IA64_IMM22
: new = BFD_RELOC_IA64_GPREL22
; break;
9581 case BFD_RELOC_IA64_IMM64
: new = BFD_RELOC_IA64_GPREL64I
; break;
9582 case BFD_RELOC_IA64_DIR32MSB
: new = BFD_RELOC_IA64_GPREL32MSB
; break;
9583 case BFD_RELOC_IA64_DIR32LSB
: new = BFD_RELOC_IA64_GPREL32LSB
; break;
9584 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_GPREL64MSB
; break;
9585 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_GPREL64LSB
; break;
9590 case FUNC_LT_RELATIVE
:
9593 case BFD_RELOC_IA64_IMM22
: new = BFD_RELOC_IA64_LTOFF22
; break;
9594 case BFD_RELOC_IA64_IMM64
: new = BFD_RELOC_IA64_LTOFF64I
; break;
9599 case FUNC_PC_RELATIVE
:
9602 case BFD_RELOC_IA64_IMM22
: new = BFD_RELOC_IA64_PCREL22
; break;
9603 case BFD_RELOC_IA64_IMM64
: new = BFD_RELOC_IA64_PCREL64I
; break;
9604 case BFD_RELOC_IA64_DIR32MSB
: new = BFD_RELOC_IA64_PCREL32MSB
; break;
9605 case BFD_RELOC_IA64_DIR32LSB
: new = BFD_RELOC_IA64_PCREL32LSB
; break;
9606 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_PCREL64MSB
; break;
9607 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_PCREL64LSB
; break;
9612 case FUNC_PLT_RELATIVE
:
9615 case BFD_RELOC_IA64_IMM22
: new = BFD_RELOC_IA64_PLTOFF22
; break;
9616 case BFD_RELOC_IA64_IMM64
: new = BFD_RELOC_IA64_PLTOFF64I
; break;
9617 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_PLTOFF64MSB
;break;
9618 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_PLTOFF64LSB
;break;
9623 case FUNC_SEC_RELATIVE
:
9626 case BFD_RELOC_IA64_DIR32MSB
: new = BFD_RELOC_IA64_SECREL32MSB
;break;
9627 case BFD_RELOC_IA64_DIR32LSB
: new = BFD_RELOC_IA64_SECREL32LSB
;break;
9628 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_SECREL64MSB
;break;
9629 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_SECREL64LSB
;break;
9634 case FUNC_SEG_RELATIVE
:
9637 case BFD_RELOC_IA64_DIR32MSB
: new = BFD_RELOC_IA64_SEGREL32MSB
;break;
9638 case BFD_RELOC_IA64_DIR32LSB
: new = BFD_RELOC_IA64_SEGREL32LSB
;break;
9639 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_SEGREL64MSB
;break;
9640 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_SEGREL64LSB
;break;
9645 case FUNC_LTV_RELATIVE
:
9648 case BFD_RELOC_IA64_DIR32MSB
: new = BFD_RELOC_IA64_LTV32MSB
; break;
9649 case BFD_RELOC_IA64_DIR32LSB
: new = BFD_RELOC_IA64_LTV32LSB
; break;
9650 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_LTV64MSB
; break;
9651 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_LTV64LSB
; break;
9656 case FUNC_LT_FPTR_RELATIVE
:
9659 case BFD_RELOC_IA64_IMM22
:
9660 new = BFD_RELOC_IA64_LTOFF_FPTR22
; break;
9661 case BFD_RELOC_IA64_IMM64
:
9662 new = BFD_RELOC_IA64_LTOFF_FPTR64I
; break;
9670 /* Hmmmm. Should this ever occur? */
9677 /* Here is where generate the appropriate reloc for pseudo relocation
9680 ia64_validate_fix (fix
)
9683 switch (fix
->fx_r_type
)
9685 case BFD_RELOC_IA64_FPTR64I
:
9686 case BFD_RELOC_IA64_FPTR32MSB
:
9687 case BFD_RELOC_IA64_FPTR64LSB
:
9688 case BFD_RELOC_IA64_LTOFF_FPTR22
:
9689 case BFD_RELOC_IA64_LTOFF_FPTR64I
:
9690 if (fix
->fx_offset
!= 0)
9691 as_bad_where (fix
->fx_file
, fix
->fx_line
,
9692 "No addend allowed in @fptr() relocation");
9702 fix_insn (fix
, odesc
, value
)
9704 const struct ia64_operand
*odesc
;
9707 bfd_vma insn
[3], t0
, t1
, control_bits
;
9712 slot
= fix
->fx_where
& 0x3;
9713 fixpos
= fix
->fx_frag
->fr_literal
+ (fix
->fx_where
- slot
);
9715 /* Bundles are always in little-endian byte order */
9716 t0
= bfd_getl64 (fixpos
);
9717 t1
= bfd_getl64 (fixpos
+ 8);
9718 control_bits
= t0
& 0x1f;
9719 insn
[0] = (t0
>> 5) & 0x1ffffffffffLL
;
9720 insn
[1] = ((t0
>> 46) & 0x3ffff) | ((t1
& 0x7fffff) << 18);
9721 insn
[2] = (t1
>> 23) & 0x1ffffffffffLL
;
9724 if (odesc
- elf64_ia64_operands
== IA64_OPND_IMMU64
)
9726 insn
[1] = (value
>> 22) & 0x1ffffffffffLL
;
9727 insn
[2] |= (((value
& 0x7f) << 13)
9728 | (((value
>> 7) & 0x1ff) << 27)
9729 | (((value
>> 16) & 0x1f) << 22)
9730 | (((value
>> 21) & 0x1) << 21)
9731 | (((value
>> 63) & 0x1) << 36));
9733 else if (odesc
- elf64_ia64_operands
== IA64_OPND_IMMU62
)
9735 if (value
& ~0x3fffffffffffffffULL
)
9736 err
= "integer operand out of range";
9737 insn
[1] = (value
>> 21) & 0x1ffffffffffLL
;
9738 insn
[2] |= (((value
& 0xfffff) << 6) | (((value
>> 20) & 0x1) << 36));
9740 else if (odesc
- elf64_ia64_operands
== IA64_OPND_TGT64
)
9743 insn
[1] = ((value
>> 20) & 0x7fffffffffLL
) << 2;
9744 insn
[2] |= ((((value
>> 59) & 0x1) << 36)
9745 | (((value
>> 0) & 0xfffff) << 13));
9748 err
= (*odesc
->insert
) (odesc
, value
, insn
+ slot
);
9751 as_bad_where (fix
->fx_file
, fix
->fx_line
, err
);
9753 t0
= control_bits
| (insn
[0] << 5) | (insn
[1] << 46);
9754 t1
= ((insn
[1] >> 18) & 0x7fffff) | (insn
[2] << 23);
9755 number_to_chars_littleendian (fixpos
+ 0, t0
, 8);
9756 number_to_chars_littleendian (fixpos
+ 8, t1
, 8);
9759 /* Attempt to simplify or even eliminate a fixup. The return value is
9760 ignored; perhaps it was once meaningful, but now it is historical.
9761 To indicate that a fixup has been eliminated, set FIXP->FX_DONE.
9763 If fixp->fx_addsy is non-NULL, we'll have to generate a reloc entry
9766 md_apply_fix3 (fix
, valuep
, seg
)
9769 segT seg ATTRIBUTE_UNUSED
;
9772 valueT value
= *valuep
;
9775 fixpos
= fix
->fx_frag
->fr_literal
+ fix
->fx_where
;
9779 switch (fix
->fx_r_type
)
9781 case BFD_RELOC_IA64_DIR32MSB
:
9782 fix
->fx_r_type
= BFD_RELOC_IA64_PCREL32MSB
;
9786 case BFD_RELOC_IA64_DIR32LSB
:
9787 fix
->fx_r_type
= BFD_RELOC_IA64_PCREL32LSB
;
9791 case BFD_RELOC_IA64_DIR64MSB
:
9792 fix
->fx_r_type
= BFD_RELOC_IA64_PCREL64MSB
;
9796 case BFD_RELOC_IA64_DIR64LSB
:
9797 fix
->fx_r_type
= BFD_RELOC_IA64_PCREL64LSB
;
9807 switch (fix
->fx_r_type
)
9810 as_bad_where (fix
->fx_file
, fix
->fx_line
,
9811 "%s must have a constant value",
9812 elf64_ia64_operands
[fix
->tc_fix_data
.opnd
].desc
);
9819 /* ??? This is a hack copied from tc-i386.c to make PCREL relocs
9820 work. There should be a better way to handle this. */
9822 fix
->fx_offset
+= fix
->fx_where
+ fix
->fx_frag
->fr_address
;
9824 else if (fix
->tc_fix_data
.opnd
== IA64_OPND_NIL
)
9826 if (fix
->tc_fix_data
.bigendian
)
9827 number_to_chars_bigendian (fixpos
, value
, fix
->fx_size
);
9829 number_to_chars_littleendian (fixpos
, value
, fix
->fx_size
);
9835 fix_insn (fix
, elf64_ia64_operands
+ fix
->tc_fix_data
.opnd
, value
);
9842 /* Generate the BFD reloc to be stuck in the object file from the
9843 fixup used internally in the assembler. */
9846 tc_gen_reloc (sec
, fixp
)
9847 asection
*sec ATTRIBUTE_UNUSED
;
9852 reloc
= xmalloc (sizeof (*reloc
));
9853 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
9854 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
9855 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
9856 reloc
->addend
= fixp
->fx_offset
;
9857 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
9861 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
9862 "Cannot represent %s relocation in object file",
9863 bfd_get_reloc_code_name (fixp
->fx_r_type
));
9868 /* Turn a string in input_line_pointer into a floating point constant
9869 of type TYPE, and store the appropriate bytes in *LIT. The number
9870 of LITTLENUMS emitted is stored in *SIZE. An error message is
9871 returned, or NULL on OK. */
9873 #define MAX_LITTLENUMS 5
9876 md_atof (type
, lit
, size
)
9881 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
9882 LITTLENUM_TYPE
*word
;
9912 return "Bad call to MD_ATOF()";
9914 t
= atof_ieee (input_line_pointer
, type
, words
);
9916 input_line_pointer
= t
;
9917 *size
= prec
* sizeof (LITTLENUM_TYPE
);
9919 for (word
= words
+ prec
- 1; prec
--;)
9921 md_number_to_chars (lit
, (long) (*word
--), sizeof (LITTLENUM_TYPE
));
9922 lit
+= sizeof (LITTLENUM_TYPE
);
9927 /* Round up a section's size to the appropriate boundary. */
9929 md_section_align (seg
, size
)
9933 int align
= bfd_get_section_alignment (stdoutput
, seg
);
9934 valueT mask
= ((valueT
) 1 << align
) - 1;
9936 return (size
+ mask
) & ~mask
;
9939 /* Handle ia64 specific semantics of the align directive. */
9942 ia64_md_do_align (n
, fill
, len
, max
)
9943 int n ATTRIBUTE_UNUSED
;
9944 const char *fill ATTRIBUTE_UNUSED
;
9945 int len ATTRIBUTE_UNUSED
;
9946 int max ATTRIBUTE_UNUSED
;
9948 if (subseg_text_p (now_seg
))
9949 ia64_flush_insns ();
9952 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
9953 of an rs_align_code fragment. */
9956 ia64_handle_align (fragp
)
9959 /* Use mfi bundle of nops with no stop bits. */
9960 static const unsigned char be_nop
[]
9961 = { 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00,
9962 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x0c};
9963 static const unsigned char le_nop
[]
9964 = { 0x0c, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
9965 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00};
9970 if (fragp
->fr_type
!= rs_align_code
)
9973 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
9974 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
9976 /* Make sure we are on a 16-byte boundary, in case someone has been
9977 putting data into a text section. */
9980 int fix
= bytes
& 15;
9984 fragp
->fr_fix
+= fix
;
9987 memcpy (p
, (target_big_endian
? be_nop
: le_nop
), 16);