opcodes/arc-dis.c

   1 /* Instruction printing code for the ARC.
   2    Copyright 1994, 1995, 1997, 1998, 2000, 2001
   3    Free Software Foundation, Inc.
   4    Contributed by Doug Evans (dje@cygnus.com).
   5
   6    This program is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 2 of the License, or
   9    (at your option) any later version.
  10
  11    This program is distributed in the hope that it will be useful,
  12    but WITHOUT ANY WARRANTY; without even the implied warranty of
  13    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14    GNU General Public License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  19
  20 #include <ansidecl.h>
  21 #include <libiberty.h>
  22 #include "dis-asm.h"
  23 #include "opcode/arc.h"
  24 #include "elf-bfd.h"
  25 #include "elf/arc.h"
  26 #include <string.h>
  27 #include "opintl.h"
  28
  29 #include <ctype.h>
  30 #include <stdarg.h>
  31 #include "arc-dis.h"
  32 #include "arc-ext.h"
  33
  34 #ifndef dbg
  35 #define dbg (0)
  36 #endif
  37
  38 #define BIT(word,n)     ((word) & (1 << n))
  39 #define BITS(word,s,e)  (((word) << (31 - e)) >> (s + (31 - e)))
  40 #define OPCODE(word)    (BITS ((word), 27, 31))
  41 #define FIELDA(word)    (BITS ((word), 21, 26))
  42 #define FIELDB(word)    (BITS ((word), 15, 20))
  43 #define FIELDC(word)    (BITS ((word),  9, 14))
  44
  45 /* FIELD D is signed in all of its uses, so we make sure argument is
  46    treated as signed for bit shifting purposes:  */
  47 #define FIELDD(word)    (BITS (((signed int)word), 0, 8))
  48
  49 #define PUT_NEXT_WORD_IN(a)                                                     \
  50   do                                                                            \
  51     {                                                                           \
  52       if (is_limm == 1 && !NEXT_WORD (1))                                       \
  53         mwerror (state, _("Illegal limm reference in last instruction!\n"));    \
  54         a = state->words[1];                                                    \
  55     }                                                                           \
  56   while (0)
  57
  58 #define CHECK_FLAG_COND_NULLIFY()                               \
  59   do                                                            \
  60     {                                                           \
  61       if (is_shimm == 0)                                        \
  62         {                                                       \
  63           flag = BIT (state->words[0], 8);                      \
  64           state->nullifyMode = BITS (state->words[0], 5, 6);    \
  65           cond = BITS (state->words[0], 0, 4);                  \
  66         }                                                       \
  67     }                                                           \
  68   while (0)
  69
  70 #define CHECK_COND()                            \
  71   do                                            \
  72     {                                           \
  73       if (is_shimm == 0)                        \
  74         cond = BITS (state->words[0], 0, 4);    \
  75     }                                           \
  76   while (0)
  77
  78 #define CHECK_FIELD(field)                      \
  79   do                                            \
  80     {                                           \
  81       if (field == 62)                          \
  82         {                                       \
  83           is_limm++;                            \
  84           field##isReg = 0;                     \
  85           PUT_NEXT_WORD_IN (field);             \
  86           limm_value = field;                   \
  87         }                                       \
  88       else if (field > 60)                      \
  89         {                                       \
  90           field##isReg = 0;                     \
  91           is_shimm++;                           \
  92           flag = (field == 61);                 \
  93           field = FIELDD (state->words[0]);     \
  94         }                                       \
  95     }                                           \
  96   while (0)
  97
  98 #define CHECK_FIELD_A()                         \
  99   do                                            \
 100     {                                           \
 101       fieldA = FIELDA(state->words[0]);         \
 102       if (fieldA > 60)                          \
 103         {                                       \
 104           fieldAisReg = 0;                      \
 105           fieldA = 0;                           \
 106         }                                       \
 107     }                                           \
 108   while (0)
 109
 110 #define CHECK_FIELD_B()                         \
 111   do                                            \
 112     {                                           \
 113       fieldB = FIELDB (state->words[0]);        \
 114       CHECK_FIELD (fieldB);                     \
 115     }                                           \
 116   while (0)
 117
 118 #define CHECK_FIELD_C()                         \
 119   do                                            \
 120     {                                           \
 121       fieldC = FIELDC (state->words[0]);        \
 122       CHECK_FIELD (fieldC);                     \
 123     }                                           \
 124   while (0)
 125
 126 #define IS_SMALL(x) (((field##x) < 256) && ((field##x) > -257))
 127 #define IS_REG(x)   (field##x##isReg)
 128 #define WRITE_FORMAT_LB_Rx_RB(x)     WRITE_FORMAT(x,"[","]","","")
 129 #define WRITE_FORMAT_x_COMMA_LB(x)   WRITE_FORMAT(x,"",",[","",",[")
 130 #define WRITE_FORMAT_COMMA_x_RB(x)   WRITE_FORMAT(x,",","]",",","]")
 131 #define WRITE_FORMAT_x_RB(x)         WRITE_FORMAT(x,"","]","","]")
 132 #define WRITE_FORMAT_COMMA_x(x)      WRITE_FORMAT(x,",","",",","")
 133 #define WRITE_FORMAT_x_COMMA(x)      WRITE_FORMAT(x,"",",","",",")
 134 #define WRITE_FORMAT_x(x)            WRITE_FORMAT(x,"","","","")
 135 #define WRITE_FORMAT(x,cb1,ca1,cb,ca) strcat (formatString,             \
 136                                      (IS_REG (x) ? cb1"%r"ca1 :         \
 137                                       usesAuxReg ? cb"%a"ca :           \
 138                                       IS_SMALL (x) ? cb"%d"ca : cb"%h"ca))
 139 #define WRITE_FORMAT_RB()       strcat (formatString, "]")
 140 #define WRITE_COMMENT(str)      (state->comm[state->commNum++] = (str))
 141 #define WRITE_NOP_COMMENT()     if (!fieldAisReg && !flag) WRITE_COMMENT ("nop");
 142
 143 #define NEXT_WORD(x)    (offset += 4, state->words[x])
 144
 145 #define add_target(x)   (state->targets[state->tcnt++] = (x))
 146
 147 static char comment_prefix[] = "\t; ";
 148
 149 static const char *core_reg_name PARAMS ((struct arcDisState *, int));
 150 static const char *aux_reg_name PARAMS ((struct arcDisState *, int));
 151 static const char *cond_code_name PARAMS ((struct arcDisState *, int));
 152 static const char *instruction_name
 153   PARAMS ((struct arcDisState *, int, int, int *));
 154 static void mwerror PARAMS ((struct arcDisState *, const char *));
 155 static const char *post_address PARAMS ((struct arcDisState *, int));
 156 static void write_comments_
 157   PARAMS ((struct arcDisState *, int, int, long int));
 158 static void write_instr_name_
 159   PARAMS ((struct arcDisState *, const char *, int, int, int, int, int, int));
 160 static int dsmOneArcInst PARAMS ((bfd_vma, struct arcDisState *));
 161 static const char *_coreRegName PARAMS ((void *, int));
 162 static int decodeInstr PARAMS ((bfd_vma, disassemble_info *));
 163
 164 static const char *
 165 core_reg_name (state, val)
 166      struct arcDisState * state;
 167      int                  val;
 168 {
 169   if (state->coreRegName)
 170     return (*state->coreRegName)(state->_this, val);
 171   return 0;
 172 }
 173
 174 static const char *
 175 aux_reg_name (state, val)
 176      struct arcDisState * state;
 177      int                  val;
 178 {
 179   if (state->auxRegName)
 180     return (*state->auxRegName)(state->_this, val);
 181   return 0;
 182 }
 183
 184 static const char *
 185 cond_code_name (state, val)
 186      struct arcDisState * state;
 187      int                  val;
 188 {
 189   if (state->condCodeName)
 190     return (*state->condCodeName)(state->_this, val);
 191   return 0;
 192 }
 193
 194 static const char *
 195 instruction_name (state, op1, op2, flags)
 196      struct arcDisState * state;
 197      int    op1;
 198      int    op2;
 199      int *  flags;
 200 {
 201   if (state->instName)
 202     return (*state->instName)(state->_this, op1, op2, flags);
 203   return 0;
 204 }
 205
 206 static void
 207 mwerror (state, msg)
 208      struct arcDisState * state;
 209      const char * msg;
 210 {
 211   if (state->err != 0)
 212     (*state->err)(state->_this, (msg));
 213 }
 214
 215 static const char *
 216 post_address (state, addr)
 217      struct arcDisState * state;
 218      int addr;
 219 {
 220   static char id[3 * ARRAY_SIZE (state->addresses)];
 221   int j, i = state->acnt;
 222
 223   if (i < ((int) ARRAY_SIZE (state->addresses)))
 224     {
 225       state->addresses[i] = addr;
 226       ++state->acnt;
 227       j = i*3;
 228       id[j+0] = '@';
 229       id[j+1] = '0'+i;
 230       id[j+2] = 0;
 231
 232       return id + j;
 233     }
 234   return "";
 235 }
 236
 237 static void
 238 my_sprintf (
 239             struct arcDisState * state,
 240             char * buf,
 241             const char * format,
 242             ...)
 243 {
 244   char *bp;
 245   const char *p;
 246   int size, leading_zero, regMap[2];
 247   long auxNum;
 248   va_list ap;
 249
 250   va_start (ap, format);
 251
 252   bp = buf;
 253   *bp = 0;
 254   p = format;
 255   auxNum = -1;
 256   regMap[0] = 0;
 257   regMap[1] = 0;
 258
 259   while (1)
 260     switch (*p++)
 261       {
 262     case 0:
 263       goto DOCOMM; /* (return)  */
 264       default:
 265         *bp++ = p[-1];
 266         break;
 267       case '%':
 268         size = 0;
 269         leading_zero = 0;
 270       RETRY: ;
 271         switch (*p++)
 272           {
 273           case '0':
 274           case '1':
 275           case '2':
 276           case '3':
 277           case '4':
 278           case '5':
 279           case '6':
 280           case '7':
 281           case '8':
 282           case '9':
 283             {
 284               /* size.  */
 285               size = p[-1] - '0';
 286               if (size == 0)
 287                 leading_zero = 1; /* e.g. %08x  */
 288               while (*p >= '0' && *p <= '9')
 289                 {
 290                   size = size * 10 + *p - '0';
 291                   p++;
 292                 }
 293               goto RETRY;
 294             }
 295 #define inc_bp() bp = bp + strlen (bp)
 296
 297           case 'h':
 298             {
 299               unsigned u = va_arg (ap, int);
 300
 301               /* Hex.  We can change the format to 0x%08x in
 302                  one place, here, if we wish.
 303                  We add underscores for easy reading.  */
 304               if (u > 65536)
 305                 sprintf (bp, "0x%x_%04x", u >> 16, u & 0xffff);
 306               else
 307                 sprintf (bp, "0x%x", u);
 308               inc_bp ();
 309             }
 310             break;
 311           case 'X': case 'x':
 312             {
 313               int val = va_arg (ap, int);
 314
 315               if (size != 0)
 316                 if (leading_zero)
 317                   sprintf (bp, "%0*x", size, val);
 318                 else
 319                   sprintf (bp, "%*x", size, val);
 320               else
 321                 sprintf (bp, "%x", val);
 322               inc_bp ();
 323             }
 324             break;
 325           case 'd':
 326             {
 327               int val = va_arg (ap, int);
 328
 329               if (size != 0)
 330                 sprintf (bp, "%*d", size, val);
 331               else
 332                 sprintf (bp, "%d", val);
 333               inc_bp ();
 334             }
 335             break;
 336           case 'r':
 337             {
 338               /* Register.  */
 339               int val = va_arg (ap, int);
 340
 341 #define REG2NAME(num, name) case num: sprintf (bp, ""name); \
 342   regMap[(num < 32) ? 0 : 1] |= 1 << (num - ((num < 32) ? 0 : 32)); break;
 343
 344               switch (val)
 345                 {
 346                   REG2NAME (26, "gp");
 347                   REG2NAME (27, "fp");
 348                   REG2NAME (28, "sp");
 349                   REG2NAME (29, "ilink1");
 350                   REG2NAME (30, "ilink2");
 351                   REG2NAME (31, "blink");
 352                   REG2NAME (60, "lp_count");
 353                 default:
 354                   {
 355                     const char * ext;
 356
 357                     ext = core_reg_name (state, val);
 358                     if (ext)
 359                       sprintf (bp, "%s", ext);
 360                     else
 361                       sprintf (bp,"r%d",val);
 362                   }
 363                   break;
 364                 }
 365               inc_bp ();
 366             } break;
 367
 368           case 'a':
 369             {
 370               /* Aux Register.  */
 371               int val = va_arg (ap, int);
 372
 373 #define AUXREG2NAME(num, name) case num: sprintf (bp,name); break;
 374
 375               switch (val)
 376                 {
 377                   AUXREG2NAME (0x0, "status");
 378                   AUXREG2NAME (0x1, "semaphore");
 379                   AUXREG2NAME (0x2, "lp_start");
 380                   AUXREG2NAME (0x3, "lp_end");
 381                   AUXREG2NAME (0x4, "identity");
 382                   AUXREG2NAME (0x5, "debug");
 383                 default:
 384                   {
 385                     const char *ext;
 386
 387                     ext = aux_reg_name (state, val);
 388                     if (ext)
 389                       sprintf (bp, "%s", ext);
 390                     else
 391                       my_sprintf (state, bp, "%h", val);
 392                   }
 393                   break;
 394                 }
 395               inc_bp ();
 396             }
 397             break;
 398
 399           case 's':
 400             {
 401               sprintf (bp, "%s", va_arg (ap, char *));
 402               inc_bp ();
 403             }
 404             break;
 405
 406           default:
 407             fprintf (stderr, "?? format %c\n", p[-1]);
 408             break;
 409           }
 410       }
 411
 412  DOCOMM: *bp = 0;
 413 }
 414
 415 static void
 416 write_comments_(state, shimm, is_limm, limm_value)
 417      struct arcDisState * state;
 418      int shimm;
 419      int is_limm;
 420      long limm_value;
 421 {
 422   if (state->commentBuffer != 0)
 423     {
 424       int i;
 425
 426       if (is_limm)
 427         {
 428           const char *name = post_address (state, limm_value + shimm);
 429
 430           if (*name != 0)
 431             WRITE_COMMENT (name);
 432         }
 433       for (i = 0; i < state->commNum; i++)
 434         {
 435           if (i == 0)
 436             strcpy (state->commentBuffer, comment_prefix);
 437           else
 438             strcat (state->commentBuffer, ", ");
 439           strncat (state->commentBuffer, state->comm[i], sizeof (state->commentBuffer));
 440         }
 441     }
 442 }
 443
 444 #define write_comments2(x) write_comments_(state, x, is_limm, limm_value)
 445 #define write_comments() write_comments2(0)
 446
 447 static const char *condName[] = {
 448   /* 0..15.  */
 449   ""   , "z"  , "nz" , "p"  , "n"  , "c"  , "nc" , "v"  ,
 450   "nv" , "gt" , "ge" , "lt" , "le" , "hi" , "ls" , "pnz"
 451 };
 452
 453 static void
 454 write_instr_name_(state, instrName, cond, condCodeIsPartOfName, flag, signExtend, addrWriteBack, directMem)
 455      struct arcDisState * state;
 456      const char * instrName;
 457      int cond;
 458      int condCodeIsPartOfName;
 459      int flag;
 460      int signExtend;
 461      int addrWriteBack;
 462      int directMem;
 463 {
 464   strcpy (state->instrBuffer, instrName);
 465
 466   if (cond > 0)
 467     {
 468       const char *cc = 0;
 469
 470       if (!condCodeIsPartOfName)
 471         strcat (state->instrBuffer, ".");
 472
 473       if (cond < 16)
 474         cc = condName[cond];
 475       else
 476         cc = cond_code_name (state, cond);
 477
 478       if (!cc)
 479         cc = "???";
 480
 481       strcat (state->instrBuffer, cc);
 482     }
 483
 484   if (flag)
 485     strcat (state->instrBuffer, ".f");
 486
 487   switch (state->nullifyMode)
 488     {
 489     case BR_exec_always:
 490       strcat (state->instrBuffer, ".d");
 491       break;
 492     case BR_exec_when_jump:
 493       strcat (state->instrBuffer, ".jd");
 494       break;
 495     }
 496
 497   if (signExtend)
 498     strcat (state->instrBuffer, ".x");
 499
 500   if (addrWriteBack)
 501     strcat (state->instrBuffer, ".a");
 502
 503   if (directMem)
 504     strcat (state->instrBuffer, ".di");
 505 }
 506
 507 #define write_instr_name()                                              \
 508   do                                                                    \
 509     {                                                                   \
 510       write_instr_name_(state, instrName,cond, condCodeIsPartOfName,    \
 511                         flag, signExtend, addrWriteBack, directMem);    \
 512       formatString[0] = '\0';                                           \
 513     }                                                                   \
 514   while (0)
 515
 516 enum {
 517   op_LD0 = 0, op_LD1 = 1, op_ST  = 2, op_3   = 3,
 518   op_BC  = 4, op_BLC = 5, op_LPC = 6, op_JC  = 7,
 519   op_ADD = 8, op_ADC = 9, op_SUB = 10, op_SBC = 11,
 520   op_AND = 12, op_OR  = 13, op_BIC = 14, op_XOR = 15
 521 };
 522
 523 extern disassemble_info tm_print_insn_info;
 524
 525 static int
 526 dsmOneArcInst (addr, state)
 527      bfd_vma              addr;
 528      struct arcDisState * state;
 529 {
 530   int condCodeIsPartOfName = 0;
 531   int decodingClass;
 532   const char * instrName;
 533   int repeatsOp = 0;
 534   int fieldAisReg = 1;
 535   int fieldBisReg = 1;
 536   int fieldCisReg = 1;
 537   int fieldA;
 538   int fieldB;
 539   int fieldC = 0;
 540   int flag = 0;
 541   int cond = 0;
 542   int is_shimm = 0;
 543   int is_limm = 0;
 544   long limm_value = 0;
 545   int signExtend = 0;
 546   int addrWriteBack = 0;
 547   int directMem = 0;
 548   int is_linked = 0;
 549   int offset = 0;
 550   int usesAuxReg = 0;
 551   int flags;
 552   int ignoreFirstOpd;
 553   char formatString[60];
 554
 555   state->instructionLen = 4;
 556   state->nullifyMode = BR_exec_when_no_jump;
 557   state->opWidth = 12;
 558   state->isBranch = 0;
 559
 560   state->_mem_load = 0;
 561   state->_ea_present = 0;
 562   state->_load_len = 0;
 563   state->ea_reg1 = no_reg;
 564   state->ea_reg2 = no_reg;
 565   state->_offset = 0;
 566
 567   if (! NEXT_WORD (0))
 568     return 0;
 569
 570   state->_opcode = OPCODE (state->words[0]);
 571   instrName = 0;
 572   decodingClass = 0; /* default!  */
 573   repeatsOp = 0;
 574   condCodeIsPartOfName=0;
 575   state->commNum = 0;
 576   state->tcnt = 0;
 577   state->acnt = 0;
 578   state->flow = noflow;
 579   ignoreFirstOpd = 0;
 580
 581   if (state->commentBuffer)
 582     state->commentBuffer[0] = '\0';
 583
 584   switch (state->_opcode)
 585     {
 586     case op_LD0:
 587       switch (BITS (state->words[0],1,2))
 588         {
 589         case 0:
 590           instrName = "ld";
 591           state->_load_len = 4;
 592           break;
 593         case 1:
 594           instrName = "ldb";
 595           state->_load_len = 1;
 596           break;
 597         case 2:
 598           instrName = "ldw";
 599           state->_load_len = 2;
 600           break;
 601         default:
 602           instrName = "??? (0[3])";
 603           state->flow = invalid_instr;
 604           break;
 605         }
 606       decodingClass = 5;
 607       break;
 608
 609     case op_LD1:
 610       if (BIT (state->words[0],13))
 611         {
 612           instrName = "lr";
 613           decodingClass = 10;
 614         }
 615       else
 616         {
 617           switch (BITS (state->words[0],10,11))
 618             {
 619             case 0:
 620               instrName = "ld";
 621               state->_load_len = 4;
 622               break;
 623             case 1:
 624               instrName = "ldb";
 625               state->_load_len = 1;
 626               break;
 627             case 2:
 628               instrName = "ldw";
 629               state->_load_len = 2;
 630               break;
 631             default:
 632               instrName = "??? (1[3])";
 633               state->flow = invalid_instr;
 634               break;
 635             }
 636           decodingClass = 6;
 637         }
 638       break;
 639
 640     case op_ST:
 641       if (BIT (state->words[0],25))
 642         {
 643           instrName = "sr";
 644           decodingClass = 8;
 645         }
 646       else
 647         {
 648           switch (BITS (state->words[0],22,23))
 649             {
 650             case 0:
 651               instrName = "st";
 652               break;
 653             case 1:
 654               instrName = "stb";
 655               break;
 656             case 2:
 657               instrName = "stw";
 658               break;
 659             default:
 660               instrName = "??? (2[3])";
 661               state->flow = invalid_instr;
 662               break;
 663             }
 664           decodingClass = 7;
 665         }
 666       break;
 667
 668     case op_3:
 669       decodingClass = 1;  /* default for opcode 3...  */
 670       switch (FIELDC (state->words[0]))
 671         {
 672         case  0:
 673           instrName = "flag";
 674           decodingClass = 2;
 675           break;
 676         case  1:
 677           instrName = "asr";
 678           break;
 679         case  2:
 680           instrName = "lsr";
 681           break;
 682         case  3:
 683           instrName = "ror";
 684           break;
 685         case  4:
 686           instrName = "rrc";
 687           break;
 688         case  5:
 689           instrName = "sexb";
 690           break;
 691         case  6:
 692           instrName = "sexw";
 693           break;
 694         case  7:
 695           instrName = "extb";
 696           break;
 697         case  8:
 698           instrName = "extw";
 699           break;
 700         case  0x3f:
 701           {
 702             decodingClass = 9;
 703             switch( FIELDD (state->words[0]) )
 704               {
 705               case 0:
 706                 instrName = "brk";
 707                 break;
 708               case 1:
 709                 instrName = "sleep";
 710                 break;
 711               case 2:
 712                 instrName = "swi";
 713                 break;
 714               default:
 715                 instrName = "???";
 716                 state->flow=invalid_instr;
 717                 break;
 718               }
 719           }
 720           break;
 721
 722           /* ARC Extension Library Instructions
 723              NOTE: We assume that extension codes are these instrs.  */
 724         default:
 725           instrName = instruction_name (state,
 726                                         state->_opcode,
 727                                         FIELDC (state->words[0]),
 728                                         & flags);
 729           if (!instrName)
 730             {
 731               instrName = "???";
 732               state->flow = invalid_instr;
 733             }
 734           if (flags & IGNORE_FIRST_OPD)
 735             ignoreFirstOpd = 1;
 736           break;
 737         }
 738       break;
 739
 740     case op_BC:
 741       instrName = "b";
 742     case op_BLC:
 743       if (!instrName)
 744         instrName = "bl";
 745     case op_LPC:
 746       if (!instrName)
 747         instrName = "lp";
 748     case op_JC:
 749       if (!instrName)
 750         {
 751           if (BITS (state->words[0],9,9))
 752             {
 753               instrName = "jl";
 754               is_linked = 1;
 755             }
 756           else
 757             {
 758               instrName = "j";
 759               is_linked = 0;
 760             }
 761         }
 762       condCodeIsPartOfName = 1;
 763       decodingClass = ((state->_opcode == op_JC) ? 4 : 3);
 764       state->isBranch = 1;
 765       break;
 766
 767     case op_ADD:
 768     case op_ADC:
 769     case op_AND:
 770       repeatsOp = (FIELDC (state->words[0]) == FIELDB (state->words[0]));
 771       decodingClass = 0;
 772
 773       switch (state->_opcode)
 774         {
 775         case op_ADD:
 776           instrName = (repeatsOp ? "asl" : "add");
 777           break;
 778         case op_ADC:
 779           instrName = (repeatsOp ? "rlc" : "adc");
 780           break;
 781         case op_AND:
 782           instrName = (repeatsOp ? "mov" : "and");
 783           break;
 784         }
 785       break;
 786
 787     case op_SUB: instrName = "sub";
 788       break;
 789     case op_SBC: instrName = "sbc";
 790       break;
 791     case op_OR:  instrName = "or";
 792       break;
 793     case op_BIC: instrName = "bic";
 794       break;
 795
 796     case op_XOR:
 797       if (state->words[0] == 0x7fffffff)
 798         {
 799           /* nop encoded as xor -1, -1, -1  */
 800           instrName = "nop";
 801           decodingClass = 9;
 802         }
 803       else
 804         instrName = "xor";
 805       break;
 806
 807     default:
 808       instrName = instruction_name (state,state->_opcode,0,&flags);
 809       /* if (instrName) printf("FLAGS=0x%x\n", flags);  */
 810       if (!instrName)
 811         {
 812           instrName = "???";
 813           state->flow=invalid_instr;
 814         }
 815       if (flags & IGNORE_FIRST_OPD)
 816         ignoreFirstOpd = 1;
 817       break;
 818     }
 819
 820   fieldAisReg = fieldBisReg = fieldCisReg = 1; /* Assume regs for now.  */
 821   flag = cond = is_shimm = is_limm = 0;
 822   state->nullifyMode = BR_exec_when_no_jump;    /* 0  */
 823   signExtend = addrWriteBack = directMem = 0;
 824   usesAuxReg = 0;
 825
 826   switch (decodingClass)
 827     {
 828     case 0:
 829       CHECK_FIELD_A ();
 830       CHECK_FIELD_B ();
 831       if (!repeatsOp)
 832         CHECK_FIELD_C ();
 833       CHECK_FLAG_COND_NULLIFY ();
 834
 835       write_instr_name ();
 836       if (!ignoreFirstOpd)
 837         {
 838           WRITE_FORMAT_x (A);
 839           WRITE_FORMAT_COMMA_x (B);
 840           if (!repeatsOp)
 841             WRITE_FORMAT_COMMA_x (C);
 842           WRITE_NOP_COMMENT ();
 843           my_sprintf (state, state->operandBuffer, formatString, fieldA, fieldB, fieldC);
 844         }
 845       else
 846         {
 847           WRITE_FORMAT_x (B);
 848           if (!repeatsOp)
 849             WRITE_FORMAT_COMMA_x (C);
 850           my_sprintf (state, state->operandBuffer, formatString, fieldB, fieldC);
 851         }
 852       write_comments ();
 853       break;
 854
 855     case 1:
 856       CHECK_FIELD_A ();
 857       CHECK_FIELD_B ();
 858       CHECK_FLAG_COND_NULLIFY ();
 859
 860       write_instr_name ();
 861       if (!ignoreFirstOpd)
 862         {
 863           WRITE_FORMAT_x (A);
 864           WRITE_FORMAT_COMMA_x (B);
 865           WRITE_NOP_COMMENT ();
 866           my_sprintf (state, state->operandBuffer, formatString, fieldA, fieldB);
 867         }
 868       else
 869         {
 870           WRITE_FORMAT_x (B);
 871           my_sprintf (state, state->operandBuffer, formatString, fieldB);
 872         }
 873       write_comments ();
 874       break;
 875
 876     case 2:
 877       CHECK_FIELD_B ();
 878       CHECK_FLAG_COND_NULLIFY ();
 879       flag = 0; /* this is the FLAG instruction -- it's redundant  */
 880
 881       write_instr_name ();
 882       WRITE_FORMAT_x (B);
 883       my_sprintf (state, state->operandBuffer, formatString, fieldB);
 884       write_comments ();
 885       break;
 886
 887     case 3:
 888       fieldA = BITS (state->words[0],7,26) << 2;
 889       fieldA = (fieldA << 10) >> 10; /* make it signed  */
 890       fieldA += addr + 4;
 891       CHECK_FLAG_COND_NULLIFY ();
 892       flag = 0;
 893
 894       write_instr_name ();
 895       /* This address could be a label we know. Convert it.  */
 896       if (state->_opcode != op_LPC /* LP  */)
 897         {
 898         add_target (fieldA); /* For debugger.  */
 899         state->flow = state->_opcode == op_BLC /* BL  */
 900           ? direct_call
 901           : direct_jump;
 902         /* indirect calls are achieved by "lr blink,[status];
 903            lr dest<- func addr; j [dest]"  */
 904         }
 905
 906       strcat (formatString, "%s"); /* address/label name */
 907       my_sprintf (state, state->operandBuffer, formatString, post_address (state, fieldA));
 908       write_comments ();
 909       break;
 910
 911     case 4:
 912       /* For op_JC -- jump to address specified.
 913          Also covers jump and link--bit 9 of the instr. word
 914          selects whether linked, thus "is_linked" is set above.  */
 915       fieldA = 0;
 916       CHECK_FIELD_B ();
 917       CHECK_FLAG_COND_NULLIFY ();
 918
 919       if (!fieldBisReg)
 920         {
 921           fieldAisReg = 0;
 922           fieldA = (fieldB >> 25) & 0x7F; /* flags */
 923           fieldB = (fieldB & 0xFFFFFF) << 2;
 924           state->flow = is_linked ? direct_call : direct_jump;
 925           add_target (fieldB);
 926           /* screwy JLcc requires .jd mode to execute correctly
 927            * but we pretend it is .nd (no delay slot).  */
 928           if (is_linked && state->nullifyMode == BR_exec_when_jump)
 929             state->nullifyMode = BR_exec_when_no_jump;
 930         }
 931       else
 932         {
 933           state->flow = is_linked ? indirect_call : indirect_jump;
 934           /* We should also treat this as indirect call if NOT linked
 935            * but the preceding instruction was a "lr blink,[status]"
 936            * and we have a delay slot with "add blink,blink,2".
 937            * For now we can't detect such.  */
 938           state->register_for_indirect_jump = fieldB;
 939         }
 940
 941       write_instr_name ();
 942       strcat (formatString,
 943               IS_REG (B) ? "[%r]" : "%s"); /* address/label name  */
 944       if (fieldA != 0)
 945         {
 946           fieldAisReg = 0;
 947           WRITE_FORMAT_COMMA_x (A);
 948         }
 949       if (IS_REG (B))
 950         my_sprintf (state, state->operandBuffer, formatString, fieldB, fieldA);
 951       else
 952         my_sprintf (state, state->operandBuffer, formatString,
 953                     post_address (state, fieldB), fieldA);
 954       write_comments ();
 955       break;
 956
 957     case 5:
 958       /* LD instruction.
 959          B and C can be regs, or one (both?) can be limm.  */
 960       CHECK_FIELD_A ();
 961       CHECK_FIELD_B ();
 962       CHECK_FIELD_C ();
 963       if (dbg)
 964         printf ("5:b reg %d %d c reg %d %d  \n",
 965                 fieldBisReg,fieldB,fieldCisReg,fieldC);
 966       state->_offset = 0;
 967       state->_ea_present = 1;
 968       if (fieldBisReg)
 969         state->ea_reg1 = fieldB;
 970       else
 971         state->_offset += fieldB;
 972       if (fieldCisReg)
 973         state->ea_reg2 = fieldC;
 974       else
 975         state->_offset += fieldC;
 976       state->_mem_load = 1;
 977
 978       directMem     = BIT (state->words[0],5);
 979       addrWriteBack = BIT (state->words[0],3);
 980       signExtend    = BIT (state->words[0],0);
 981
 982       write_instr_name ();
 983       WRITE_FORMAT_x_COMMA_LB(A);
 984       if (fieldBisReg || fieldB != 0)
 985         WRITE_FORMAT_x_COMMA (B);
 986       else
 987         fieldB = fieldC;
 988
 989       WRITE_FORMAT_x_RB (C);
 990       my_sprintf (state, state->operandBuffer, formatString, fieldA, fieldB, fieldC);
 991       write_comments ();
 992       break;
 993
 994     case 6:
 995       /* LD instruction.  */
 996       CHECK_FIELD_B ();
 997       CHECK_FIELD_A ();
 998       fieldC = FIELDD (state->words[0]);
 999
1000       if (dbg)
1001         printf ("6:b reg %d %d c 0x%x  \n",
1002                 fieldBisReg, fieldB, fieldC);
1003       state->_ea_present = 1;
1004       state->_offset = fieldC;
1005       state->_mem_load = 1;
1006       if (fieldBisReg)
1007         state->ea_reg1 = fieldB;
1008       /* field B is either a shimm (same as fieldC) or limm (different!)
1009          Say ea is not present, so only one of us will do the name lookup.  */
1010       else
1011         state->_offset += fieldB, state->_ea_present = 0;
1012
1013       directMem     = BIT (state->words[0],14);
1014       addrWriteBack = BIT (state->words[0],12);
1015       signExtend    = BIT (state->words[0],9);
1016
1017       write_instr_name ();
1018       WRITE_FORMAT_x_COMMA_LB (A);
1019       if (!fieldBisReg)
1020         {
1021           fieldB = state->_offset;
1022           WRITE_FORMAT_x_RB (B);
1023         }
1024       else
1025         {
1026           WRITE_FORMAT_x (B);
1027           if (fieldC != 0 && !BIT (state->words[0],13))
1028             {
1029               fieldCisReg = 0;
1030               WRITE_FORMAT_COMMA_x_RB (C);
1031             }
1032           else
1033             WRITE_FORMAT_RB ();
1034         }
1035       my_sprintf (state, state->operandBuffer, formatString, fieldA, fieldB, fieldC);
1036       write_comments ();
1037       break;
1038
1039     case 7:
1040       /* ST instruction.  */
1041       CHECK_FIELD_B();
1042       CHECK_FIELD_C();
1043       fieldA = FIELDD(state->words[0]); /* shimm  */
1044
1045       /* [B,A offset]  */
1046       if (dbg) printf("7:b reg %d %x off %x\n",
1047                                  fieldBisReg,fieldB,fieldA);
1048       state->_ea_present = 1;
1049       state->_offset = fieldA;
1050       if (fieldBisReg)
1051         state->ea_reg1 = fieldB;
1052       /* field B is either a shimm (same as fieldA) or limm (different!)
1053          Say ea is not present, so only one of us will do the name lookup.
1054          (for is_limm we do the name translation here).  */
1055       else
1056         state->_offset += fieldB, state->_ea_present = 0;
1057
1058       directMem     = BIT(state->words[0],26);
1059       addrWriteBack = BIT(state->words[0],24);
1060
1061       write_instr_name();
1062       WRITE_FORMAT_x_COMMA_LB(C);
1063
1064       if (!fieldBisReg)
1065         {
1066           fieldB = state->_offset;
1067           WRITE_FORMAT_x_RB(B);
1068         }
1069       else
1070         {
1071           WRITE_FORMAT_x(B);
1072           if (fieldBisReg && fieldA != 0)
1073             {
1074               fieldAisReg = 0;
1075               WRITE_FORMAT_COMMA_x_RB(A);
1076             }
1077           else
1078             WRITE_FORMAT_RB();
1079         }
1080       my_sprintf (state, state->operandBuffer, formatString, fieldC, fieldB, fieldA);
1081       write_comments2(fieldA);
1082       break;
1083     case 8:
1084       /* SR instruction  */
1085       CHECK_FIELD_B();
1086       CHECK_FIELD_C();
1087
1088       write_instr_name();
1089       WRITE_FORMAT_x_COMMA_LB(C);
1090       /* Try to print B as an aux reg if it is not a core reg.  */
1091       usesAuxReg = 1;
1092       WRITE_FORMAT_x(B);
1093       WRITE_FORMAT_RB();
1094       my_sprintf (state, state->operandBuffer, formatString, fieldC, fieldB);
1095       write_comments();
1096       break;
1097
1098     case 9:
1099       write_instr_name();
1100       state->operandBuffer[0] = '\0';
1101       break;
1102
1103     case 10:
1104       /* LR instruction */
1105       CHECK_FIELD_A();
1106       CHECK_FIELD_B();
1107
1108       write_instr_name();
1109       WRITE_FORMAT_x_COMMA_LB(A);
1110       /* Try to print B as an aux reg if it is not a core reg. */
1111       usesAuxReg = 1;
1112       WRITE_FORMAT_x(B);
1113       WRITE_FORMAT_RB();
1114       my_sprintf (state, state->operandBuffer, formatString, fieldA, fieldB);
1115       write_comments();
1116       break;
1117
1118     case 11:
1119       CHECK_COND();
1120       write_instr_name();
1121       state->operandBuffer[0] = '\0';
1122       break;
1123
1124     default:
1125       mwerror (state, "Bad decoding class in ARC disassembler");
1126       break;
1127     }
1128
1129   state->_cond = cond;
1130   return state->instructionLen = offset;
1131 }
1132
1133
1134 /* Returns the name the user specified core extension register.  */
1135 static const char *
1136 _coreRegName(arg, regval)
1137      void * arg ATTRIBUTE_UNUSED;
1138      int regval;
1139 {
1140   return arcExtMap_coreRegName (regval);
1141 }
1142
1143 /* Returns the name the user specified AUX extension register.  */
1144 static const char *
1145 _auxRegName(void *_this ATTRIBUTE_UNUSED, int regval)
1146 {
1147     return arcExtMap_auxRegName(regval);
1148 }
1149
1150
1151 /* Returns the name the user specified condition code name.  */
1152 static const char *
1153 _condCodeName(void *_this ATTRIBUTE_UNUSED, int regval)
1154 {
1155     return arcExtMap_condCodeName(regval);
1156 }
1157
1158 /* Returns the name the user specified extension instruction.  */
1159 static const char *
1160 _instName (void *_this ATTRIBUTE_UNUSED, int majop, int minop, int *flags)
1161 {
1162     return arcExtMap_instName(majop, minop, flags);
1163 }
1164
1165 /* Decode an instruction returning the size of the instruction
1166    in bytes or zero if unrecognized.  */
1167 static int
1168 decodeInstr (address, info)
1169      bfd_vma            address; /* Address of this instruction.  */
1170      disassemble_info * info;
1171 {
1172   int status;
1173   bfd_byte buffer[4];
1174   struct arcDisState s; /* ARC Disassembler state  */
1175   void *stream = info->stream; /* output stream  */
1176   fprintf_ftype func = info->fprintf_func;
1177   int bytes;
1178
1179   memset (&s, 0, sizeof(struct arcDisState));
1180
1181   /* read first instruction  */
1182   status = (*info->read_memory_func) (address, buffer, 4, info);
1183   if (status != 0)
1184     {
1185       (*info->memory_error_func) (status, address, info);
1186       return 0;
1187     }
1188   if (info->endian == BFD_ENDIAN_LITTLE)
1189     s.words[0] = bfd_getl32(buffer);
1190   else
1191     s.words[0] = bfd_getb32(buffer);
1192   /* always read second word in case of limm  */
1193
1194   /* we ignore the result since last insn may not have a limm  */
1195   status = (*info->read_memory_func) (address + 4, buffer, 4, info);
1196   if (info->endian == BFD_ENDIAN_LITTLE)
1197     s.words[1] = bfd_getl32(buffer);
1198   else
1199     s.words[1] = bfd_getb32(buffer);
1200
1201   s._this = &s;
1202   s.coreRegName = _coreRegName;
1203   s.auxRegName = _auxRegName;
1204   s.condCodeName = _condCodeName;
1205   s.instName = _instName;
1206
1207   /* disassemble  */
1208   bytes = dsmOneArcInst(address, (void *)&s);
1209
1210   /* display the disassembly instruction  */
1211   (*func) (stream, "%08x ", s.words[0]);
1212   (*func) (stream, "    ");
1213
1214   (*func) (stream, "%-10s ", s.instrBuffer);
1215
1216   if (__TRANSLATION_REQUIRED(s))
1217     {
1218       bfd_vma addr = s.addresses[s.operandBuffer[1] - '0'];
1219       (*info->print_address_func) ((bfd_vma) addr, info);
1220       (*func) (stream, "\n");
1221     }
1222   else
1223     (*func) (stream, "%s",s.operandBuffer);
1224   return s.instructionLen;
1225 }
1226
1227 /* Return the print_insn function to use.
1228    Side effect: load (possibly empty) extension section  */
1229
1230 disassembler_ftype
1231 arc_get_disassembler (void *ptr)
1232 {
1233   if (ptr)
1234     build_ARC_extmap (ptr);
1235   return decodeInstr;
1236 }