1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002
3 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
29 #include "safe-ctype.h"
38 #include "opcode/mips.h"
42 #define DBG(x) printf x
48 /* Clean up namespace so we can include obj-elf.h too. */
49 static int mips_output_flavor
PARAMS ((void));
50 static int mips_output_flavor () { return OUTPUT_FLAVOR
; }
51 #undef OBJ_PROCESS_STAB
58 #undef obj_frob_file_after_relocs
59 #undef obj_frob_symbol
61 #undef obj_sec_sym_ok_for_reloc
62 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
65 /* Fix any of them that we actually care about. */
67 #define OUTPUT_FLAVOR mips_output_flavor()
74 #ifndef ECOFF_DEBUGGING
75 #define NO_ECOFF_DEBUGGING
76 #define ECOFF_DEBUGGING 0
81 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
82 static char *mips_regmask_frag
;
87 #define PIC_CALL_REG 25
95 #define ILLEGAL_REG (32)
97 /* Allow override of standard little-endian ECOFF format. */
99 #ifndef ECOFF_LITTLE_FORMAT
100 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
103 extern int target_big_endian
;
105 /* The name of the readonly data section. */
106 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
108 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
110 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
112 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
116 /* The ABI to use. */
127 /* MIPS ABI we are using for this output file. */
128 static enum mips_abi_level file_mips_abi
= NO_ABI
;
130 /* This is the set of options which may be modified by the .set
131 pseudo-op. We use a struct so that .set push and .set pop are more
134 struct mips_set_options
136 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
137 if it has not been initialized. Changed by `.set mipsN', and the
138 -mipsN command line option, and the default CPU. */
140 /* Enabled Application Specific Extensions (ASEs). These are set to -1
141 if they have not been initialized. Changed by `.set <asename>', by
142 command line options, and based on the default architecture. */
144 /* Whether we are assembling for the mips16 processor. 0 if we are
145 not, 1 if we are, and -1 if the value has not been initialized.
146 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
147 -nomips16 command line options, and the default CPU. */
149 /* Non-zero if we should not reorder instructions. Changed by `.set
150 reorder' and `.set noreorder'. */
152 /* Non-zero if we should not permit the $at ($1) register to be used
153 in instructions. Changed by `.set at' and `.set noat'. */
155 /* Non-zero if we should warn when a macro instruction expands into
156 more than one machine instruction. Changed by `.set nomacro' and
158 int warn_about_macros
;
159 /* Non-zero if we should not move instructions. Changed by `.set
160 move', `.set volatile', `.set nomove', and `.set novolatile'. */
162 /* Non-zero if we should not optimize branches by moving the target
163 of the branch into the delay slot. Actually, we don't perform
164 this optimization anyhow. Changed by `.set bopt' and `.set
167 /* Non-zero if we should not autoextend mips16 instructions.
168 Changed by `.set autoextend' and `.set noautoextend'. */
170 /* Restrict general purpose registers and floating point registers
171 to 32 bit. This is initially determined when -mgp32 or -mfp32
172 is passed but can changed if the assembler code uses .set mipsN. */
175 /* The ABI currently in use. This is changed by .set mipsN to loosen
176 restrictions and doesn't affect the whole file. */
177 enum mips_abi_level abi
;
180 /* True if -mgp32 was passed. */
181 static int file_mips_gp32
= -1;
183 /* True if -mfp32 was passed. */
184 static int file_mips_fp32
= -1;
186 /* This is the struct we use to hold the current set of options. Note
187 that we must set the isa field to ISA_UNKNOWN and the mips16 field to
188 -1 to indicate that they have not been initialized. */
190 static struct mips_set_options mips_opts
=
192 ISA_UNKNOWN
, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, NO_ABI
195 /* These variables are filled in with the masks of registers used.
196 The object format code reads them and puts them in the appropriate
198 unsigned long mips_gprmask
;
199 unsigned long mips_cprmask
[4];
201 /* MIPS ISA we are using for this output file. */
202 static int file_mips_isa
= ISA_UNKNOWN
;
204 /* True if -mips3d was passed or implied by arguments passed on the
205 command line (e.g., by -march). */
206 static int file_ase_mips3d
;
208 /* The argument of the -mcpu= flag. Historical for code generation. */
209 static int mips_cpu
= CPU_UNKNOWN
;
211 /* The argument of the -march= flag. The architecture we are assembling. */
212 static int mips_arch
= CPU_UNKNOWN
;
214 /* The argument of the -mtune= flag. The architecture for which we
216 static int mips_tune
= CPU_UNKNOWN
;
218 /* Whether we should mark the file EABI64 or EABI32. */
219 static int mips_eabi64
= 0;
221 /* If they asked for mips1 or mips2 and a cpu that is
222 mips3 or greater, then mark the object file 32BITMODE. */
223 static int mips_32bitmode
= 0;
225 /* Some ISA's have delay slots for instructions which read or write
226 from a coprocessor (eg. mips1-mips3); some don't (eg mips4).
227 Return true if instructions marked INSN_LOAD_COPROC_DELAY,
228 INSN_COPROC_MOVE_DELAY, or INSN_WRITE_COND_CODE actually have a
229 delay slot in this ISA. The uses of this macro assume that any
230 ISA that has delay slots for one of these, has them for all. They
231 also assume that ISAs which don't have delays for these insns, don't
232 have delays for the INSN_LOAD_MEMORY_DELAY instructions either. */
233 #define ISA_HAS_COPROC_DELAYS(ISA) ( \
235 || (ISA) == ISA_MIPS2 \
236 || (ISA) == ISA_MIPS3 \
239 /* Return true if ISA supports 64 bit gp register instructions. */
240 #define ISA_HAS_64BIT_REGS(ISA) ( \
242 || (ISA) == ISA_MIPS4 \
243 || (ISA) == ISA_MIPS5 \
244 || (ISA) == ISA_MIPS64 \
247 #define HAVE_32BIT_GPRS \
249 || mips_opts.abi == O32_ABI \
250 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
252 #define HAVE_32BIT_FPRS \
254 || mips_opts.abi == O32_ABI \
255 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
257 #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS)
258 #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS)
260 #define HAVE_NEWABI (mips_opts.abi == N32_ABI || mips_opts.abi == N64_ABI)
262 #define HAVE_64BIT_OBJECTS (mips_opts.abi == N64_ABI)
264 /* We can only have 64bit addresses if the object file format
266 #define HAVE_32BIT_ADDRESSES \
268 || ((bfd_arch_bits_per_address (stdoutput) == 32 \
269 || ! HAVE_64BIT_OBJECTS) \
270 && mips_pic != EMBEDDED_PIC))
272 #define HAVE_64BIT_ADDRESSES (! HAVE_32BIT_ADDRESSES)
274 /* Return true if the given CPU supports the MIPS3D ASE. */
275 #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \
278 /* Whether the processor uses hardware interlocks to protect
279 reads from the HI and LO registers, and thus does not
280 require nops to be inserted. */
282 #define hilo_interlocks (mips_arch == CPU_R4010 \
283 || mips_arch == CPU_SB1 \
286 /* Whether the processor uses hardware interlocks to protect reads
287 from the GPRs, and thus does not require nops to be inserted. */
288 #define gpr_interlocks \
289 (mips_opts.isa != ISA_MIPS1 \
290 || mips_arch == CPU_R3900)
292 /* As with other "interlocks" this is used by hardware that has FP
293 (co-processor) interlocks. */
294 /* Itbl support may require additional care here. */
295 #define cop_interlocks (mips_arch == CPU_R4300 \
296 || mips_arch == CPU_SB1 \
299 /* Is this a mfhi or mflo instruction? */
300 #define MF_HILO_INSN(PINFO) \
301 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
303 /* MIPS PIC level. */
307 /* Do not generate PIC code. */
310 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
311 not sure what it is supposed to do. */
314 /* Generate PIC code as in the SVR4 MIPS ABI. */
317 /* Generate PIC code without using a global offset table: the data
318 segment has a maximum size of 64K, all data references are off
319 the $gp register, and all text references are PC relative. This
320 is used on some embedded systems. */
324 static enum mips_pic_level mips_pic
;
326 /* Warn about all NOPS that the assembler generates. */
327 static int warn_nops
= 0;
329 /* 1 if we should generate 32 bit offsets from the $gp register in
330 SVR4_PIC mode. Currently has no meaning in other modes. */
331 static int mips_big_got
= 0;
333 /* 1 if trap instructions should used for overflow rather than break
335 static int mips_trap
= 0;
337 /* 1 if double width floating point constants should not be constructed
338 by assembling two single width halves into two single width floating
339 point registers which just happen to alias the double width destination
340 register. On some architectures this aliasing can be disabled by a bit
341 in the status register, and the setting of this bit cannot be determined
342 automatically at assemble time. */
343 static int mips_disable_float_construction
;
345 /* Non-zero if any .set noreorder directives were used. */
347 static int mips_any_noreorder
;
349 /* Non-zero if nops should be inserted when the register referenced in
350 an mfhi/mflo instruction is read in the next two instructions. */
351 static int mips_7000_hilo_fix
;
353 /* The size of the small data section. */
354 static unsigned int g_switch_value
= 8;
355 /* Whether the -G option was used. */
356 static int g_switch_seen
= 0;
361 /* If we can determine in advance that GP optimization won't be
362 possible, we can skip the relaxation stuff that tries to produce
363 GP-relative references. This makes delay slot optimization work
366 This function can only provide a guess, but it seems to work for
367 gcc output. It needs to guess right for gcc, otherwise gcc
368 will put what it thinks is a GP-relative instruction in a branch
371 I don't know if a fix is needed for the SVR4_PIC mode. I've only
372 fixed it for the non-PIC mode. KR 95/04/07 */
373 static int nopic_need_relax
PARAMS ((symbolS
*, int));
375 /* handle of the OPCODE hash table */
376 static struct hash_control
*op_hash
= NULL
;
378 /* The opcode hash table we use for the mips16. */
379 static struct hash_control
*mips16_op_hash
= NULL
;
381 /* This array holds the chars that always start a comment. If the
382 pre-processor is disabled, these aren't very useful */
383 const char comment_chars
[] = "#";
385 /* This array holds the chars that only start a comment at the beginning of
386 a line. If the line seems to have the form '# 123 filename'
387 .line and .file directives will appear in the pre-processed output */
388 /* Note that input_file.c hand checks for '#' at the beginning of the
389 first line of the input file. This is because the compiler outputs
390 #NO_APP at the beginning of its output. */
391 /* Also note that C style comments are always supported. */
392 const char line_comment_chars
[] = "#";
394 /* This array holds machine specific line separator characters. */
395 const char line_separator_chars
[] = ";";
397 /* Chars that can be used to separate mant from exp in floating point nums */
398 const char EXP_CHARS
[] = "eE";
400 /* Chars that mean this number is a floating point constant */
403 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
405 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
406 changed in read.c . Ideally it shouldn't have to know about it at all,
407 but nothing is ideal around here.
410 static char *insn_error
;
412 static int auto_align
= 1;
414 /* When outputting SVR4 PIC code, the assembler needs to know the
415 offset in the stack frame from which to restore the $gp register.
416 This is set by the .cprestore pseudo-op, and saved in this
418 static offsetT mips_cprestore_offset
= -1;
420 /* Similiar for NewABI PIC code, where $gp is callee-saved. NewABI has some
421 more optimizations, it can use a register value instead of a memory-saved
422 offset and even an other register than $gp as global pointer. */
423 static offsetT mips_cpreturn_offset
= -1;
424 static int mips_cpreturn_register
= -1;
425 static int mips_gp_register
= GP
;
426 static int mips_gprel_offset
= 0;
428 /* Whether mips_cprestore_offset has been set in the current function
429 (or whether it has already been warned about, if not). */
430 static int mips_cprestore_valid
= 0;
432 /* This is the register which holds the stack frame, as set by the
433 .frame pseudo-op. This is needed to implement .cprestore. */
434 static int mips_frame_reg
= SP
;
436 /* Whether mips_frame_reg has been set in the current function
437 (or whether it has already been warned about, if not). */
438 static int mips_frame_reg_valid
= 0;
440 /* To output NOP instructions correctly, we need to keep information
441 about the previous two instructions. */
443 /* Whether we are optimizing. The default value of 2 means to remove
444 unneeded NOPs and swap branch instructions when possible. A value
445 of 1 means to not swap branches. A value of 0 means to always
447 static int mips_optimize
= 2;
449 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
450 equivalent to seeing no -g option at all. */
451 static int mips_debug
= 0;
453 /* The previous instruction. */
454 static struct mips_cl_insn prev_insn
;
456 /* The instruction before prev_insn. */
457 static struct mips_cl_insn prev_prev_insn
;
459 /* If we don't want information for prev_insn or prev_prev_insn, we
460 point the insn_mo field at this dummy integer. */
461 static const struct mips_opcode dummy_opcode
= { NULL
, NULL
, 0, 0, 0, 0 };
463 /* Non-zero if prev_insn is valid. */
464 static int prev_insn_valid
;
466 /* The frag for the previous instruction. */
467 static struct frag
*prev_insn_frag
;
469 /* The offset into prev_insn_frag for the previous instruction. */
470 static long prev_insn_where
;
472 /* The reloc type for the previous instruction, if any. */
473 static bfd_reloc_code_real_type prev_insn_reloc_type
[3];
475 /* The reloc for the previous instruction, if any. */
476 static fixS
*prev_insn_fixp
[3];
478 /* Non-zero if the previous instruction was in a delay slot. */
479 static int prev_insn_is_delay_slot
;
481 /* Non-zero if the previous instruction was in a .set noreorder. */
482 static int prev_insn_unreordered
;
484 /* Non-zero if the previous instruction uses an extend opcode (if
486 static int prev_insn_extended
;
488 /* Non-zero if the previous previous instruction was in a .set
490 static int prev_prev_insn_unreordered
;
492 /* If this is set, it points to a frag holding nop instructions which
493 were inserted before the start of a noreorder section. If those
494 nops turn out to be unnecessary, the size of the frag can be
496 static fragS
*prev_nop_frag
;
498 /* The number of nop instructions we created in prev_nop_frag. */
499 static int prev_nop_frag_holds
;
501 /* The number of nop instructions that we know we need in
503 static int prev_nop_frag_required
;
505 /* The number of instructions we've seen since prev_nop_frag. */
506 static int prev_nop_frag_since
;
508 /* For ECOFF and ELF, relocations against symbols are done in two
509 parts, with a HI relocation and a LO relocation. Each relocation
510 has only 16 bits of space to store an addend. This means that in
511 order for the linker to handle carries correctly, it must be able
512 to locate both the HI and the LO relocation. This means that the
513 relocations must appear in order in the relocation table.
515 In order to implement this, we keep track of each unmatched HI
516 relocation. We then sort them so that they immediately precede the
517 corresponding LO relocation. */
522 struct mips_hi_fixup
*next
;
525 /* The section this fixup is in. */
529 /* The list of unmatched HI relocs. */
531 static struct mips_hi_fixup
*mips_hi_fixup_list
;
533 /* Map normal MIPS register numbers to mips16 register numbers. */
535 #define X ILLEGAL_REG
536 static const int mips32_to_16_reg_map
[] =
538 X
, X
, 2, 3, 4, 5, 6, 7,
539 X
, X
, X
, X
, X
, X
, X
, X
,
540 0, 1, X
, X
, X
, X
, X
, X
,
541 X
, X
, X
, X
, X
, X
, X
, X
545 /* Map mips16 register numbers to normal MIPS register numbers. */
547 static const unsigned int mips16_to_32_reg_map
[] =
549 16, 17, 2, 3, 4, 5, 6, 7
552 /* Since the MIPS does not have multiple forms of PC relative
553 instructions, we do not have to do relaxing as is done on other
554 platforms. However, we do have to handle GP relative addressing
555 correctly, which turns out to be a similar problem.
557 Every macro that refers to a symbol can occur in (at least) two
558 forms, one with GP relative addressing and one without. For
559 example, loading a global variable into a register generally uses
560 a macro instruction like this:
562 If i can be addressed off the GP register (this is true if it is in
563 the .sbss or .sdata section, or if it is known to be smaller than
564 the -G argument) this will generate the following instruction:
566 This instruction will use a GPREL reloc. If i can not be addressed
567 off the GP register, the following instruction sequence will be used:
570 In this case the first instruction will have a HI16 reloc, and the
571 second reloc will have a LO16 reloc. Both relocs will be against
574 The issue here is that we may not know whether i is GP addressable
575 until after we see the instruction that uses it. Therefore, we
576 want to be able to choose the final instruction sequence only at
577 the end of the assembly. This is similar to the way other
578 platforms choose the size of a PC relative instruction only at the
581 When generating position independent code we do not use GP
582 addressing in quite the same way, but the issue still arises as
583 external symbols and local symbols must be handled differently.
585 We handle these issues by actually generating both possible
586 instruction sequences. The longer one is put in a frag_var with
587 type rs_machine_dependent. We encode what to do with the frag in
588 the subtype field. We encode (1) the number of existing bytes to
589 replace, (2) the number of new bytes to use, (3) the offset from
590 the start of the existing bytes to the first reloc we must generate
591 (that is, the offset is applied from the start of the existing
592 bytes after they are replaced by the new bytes, if any), (4) the
593 offset from the start of the existing bytes to the second reloc,
594 (5) whether a third reloc is needed (the third reloc is always four
595 bytes after the second reloc), and (6) whether to warn if this
596 variant is used (this is sometimes needed if .set nomacro or .set
597 noat is in effect). All these numbers are reasonably small.
599 Generating two instruction sequences must be handled carefully to
600 ensure that delay slots are handled correctly. Fortunately, there
601 are a limited number of cases. When the second instruction
602 sequence is generated, append_insn is directed to maintain the
603 existing delay slot information, so it continues to apply to any
604 code after the second instruction sequence. This means that the
605 second instruction sequence must not impose any requirements not
606 required by the first instruction sequence.
608 These variant frags are then handled in functions called by the
609 machine independent code. md_estimate_size_before_relax returns
610 the final size of the frag. md_convert_frag sets up the final form
611 of the frag. tc_gen_reloc adjust the first reloc and adds a second
613 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
617 | (((reloc1) + 64) << 9) \
618 | (((reloc2) + 64) << 2) \
619 | ((reloc3) ? (1 << 1) : 0) \
621 #define RELAX_OLD(i) (((i) >> 23) & 0x7f)
622 #define RELAX_NEW(i) (((i) >> 16) & 0x7f)
623 #define RELAX_RELOC1(i) ((valueT) (((i) >> 9) & 0x7f) - 64)
624 #define RELAX_RELOC2(i) ((valueT) (((i) >> 2) & 0x7f) - 64)
625 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
626 #define RELAX_WARN(i) ((i) & 1)
628 /* For mips16 code, we use an entirely different form of relaxation.
629 mips16 supports two versions of most instructions which take
630 immediate values: a small one which takes some small value, and a
631 larger one which takes a 16 bit value. Since branches also follow
632 this pattern, relaxing these values is required.
634 We can assemble both mips16 and normal MIPS code in a single
635 object. Therefore, we need to support this type of relaxation at
636 the same time that we support the relaxation described above. We
637 use the high bit of the subtype field to distinguish these cases.
639 The information we store for this type of relaxation is the
640 argument code found in the opcode file for this relocation, whether
641 the user explicitly requested a small or extended form, and whether
642 the relocation is in a jump or jal delay slot. That tells us the
643 size of the value, and how it should be stored. We also store
644 whether the fragment is considered to be extended or not. We also
645 store whether this is known to be a branch to a different section,
646 whether we have tried to relax this frag yet, and whether we have
647 ever extended a PC relative fragment because of a shift count. */
648 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
651 | ((small) ? 0x100 : 0) \
652 | ((ext) ? 0x200 : 0) \
653 | ((dslot) ? 0x400 : 0) \
654 | ((jal_dslot) ? 0x800 : 0))
655 #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0)
656 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
657 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
658 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
659 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
660 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
661 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
662 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
663 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
664 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
665 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
666 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
668 /* Prototypes for static functions. */
671 #define internalError() \
672 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
674 #define internalError() as_fatal (_("MIPS internal Error"));
677 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
679 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
680 unsigned int reg
, enum mips_regclass
class));
681 static int reg_needs_delay
PARAMS ((unsigned int));
682 static void mips16_mark_labels
PARAMS ((void));
683 static void append_insn
PARAMS ((char *place
,
684 struct mips_cl_insn
* ip
,
686 bfd_reloc_code_real_type
*r
,
688 static void mips_no_prev_insn
PARAMS ((int));
689 static void mips_emit_delays
PARAMS ((boolean
));
691 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
692 const char *name
, const char *fmt
,
695 static void macro_build ();
697 static void mips16_macro_build
PARAMS ((char *, int *, expressionS
*,
698 const char *, const char *,
700 static void macro_build_jalr
PARAMS ((int, expressionS
*));
701 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
702 expressionS
* ep
, int regnum
));
703 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
704 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
706 static void load_register
PARAMS ((int *, int, expressionS
*, int));
707 static void load_address
PARAMS ((int *, int, expressionS
*, int *));
708 static void move_register
PARAMS ((int *, int, int));
709 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
710 static void mips16_macro
PARAMS ((struct mips_cl_insn
* ip
));
711 #ifdef LOSING_COMPILER
712 static void macro2
PARAMS ((struct mips_cl_insn
* ip
));
714 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
715 static void mips16_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
716 static void mips16_immed
PARAMS ((char *, unsigned int, int, offsetT
, boolean
,
717 boolean
, boolean
, unsigned long *,
718 boolean
*, unsigned short *));
719 static int my_getPercentOp
PARAMS ((char **, unsigned int *, int *));
720 static int my_getSmallParser
PARAMS ((char **, unsigned int *, int *));
721 static int my_getSmallExpression
PARAMS ((expressionS
*, char *));
722 static void my_getExpression
PARAMS ((expressionS
*, char *));
724 static int support_64bit_objects
PARAMS((void));
726 static symbolS
*get_symbol
PARAMS ((void));
727 static void mips_align
PARAMS ((int to
, int fill
, symbolS
*label
));
728 static void s_align
PARAMS ((int));
729 static void s_change_sec
PARAMS ((int));
730 static void s_cons
PARAMS ((int));
731 static void s_float_cons
PARAMS ((int));
732 static void s_mips_globl
PARAMS ((int));
733 static void s_option
PARAMS ((int));
734 static void s_mipsset
PARAMS ((int));
735 static void s_abicalls
PARAMS ((int));
736 static void s_cpload
PARAMS ((int));
737 static void s_cpsetup
PARAMS ((int));
738 static void s_cplocal
PARAMS ((int));
739 static void s_cprestore
PARAMS ((int));
740 static void s_cpreturn
PARAMS ((int));
741 static void s_gpvalue
PARAMS ((int));
742 static void s_gpword
PARAMS ((int));
743 static void s_cpadd
PARAMS ((int));
744 static void s_insn
PARAMS ((int));
745 static void md_obj_begin
PARAMS ((void));
746 static void md_obj_end
PARAMS ((void));
747 static long get_number
PARAMS ((void));
748 static void s_mips_ent
PARAMS ((int));
749 static void s_mips_end
PARAMS ((int));
750 static void s_mips_frame
PARAMS ((int));
751 static void s_mips_mask
PARAMS ((int));
752 static void s_mips_stab
PARAMS ((int));
753 static void s_mips_weakext
PARAMS ((int));
754 static void s_file
PARAMS ((int));
755 static int mips16_extended_frag
PARAMS ((fragS
*, asection
*, long));
756 static const char *mips_isa_to_str
PARAMS ((int));
757 static const char *mips_cpu_to_str
PARAMS ((int));
758 static int validate_mips_insn
PARAMS ((const struct mips_opcode
*));
759 static void show
PARAMS ((FILE *, char *, int *, int *));
761 static int mips_need_elf_addend_fixup
PARAMS ((fixS
*));
764 /* Return values of my_getSmallExpression(). */
771 /* Direct relocation creation by %percent_op(). */
790 /* Table and functions used to map between CPU/ISA names, and
791 ISA levels, and CPU numbers. */
795 const char *name
; /* CPU or ISA name. */
796 int is_isa
; /* Is this an ISA? (If 0, a CPU.) */
797 int isa
; /* ISA level. */
798 int cpu
; /* CPU number (default CPU if ISA). */
801 static const struct mips_cpu_info
*mips_cpu_info_from_name
PARAMS ((const char *));
802 static const struct mips_cpu_info
*mips_cpu_info_from_isa
PARAMS ((int));
803 static const struct mips_cpu_info
*mips_cpu_info_from_cpu
PARAMS ((int));
807 The following pseudo-ops from the Kane and Heinrich MIPS book
808 should be defined here, but are currently unsupported: .alias,
809 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
811 The following pseudo-ops from the Kane and Heinrich MIPS book are
812 specific to the type of debugging information being generated, and
813 should be defined by the object format: .aent, .begin, .bend,
814 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
817 The following pseudo-ops from the Kane and Heinrich MIPS book are
818 not MIPS CPU specific, but are also not specific to the object file
819 format. This file is probably the best place to define them, but
820 they are not currently supported: .asm0, .endr, .lab, .repeat,
823 static const pseudo_typeS mips_pseudo_table
[] =
825 /* MIPS specific pseudo-ops. */
826 {"option", s_option
, 0},
827 {"set", s_mipsset
, 0},
828 {"rdata", s_change_sec
, 'r'},
829 {"sdata", s_change_sec
, 's'},
830 {"livereg", s_ignore
, 0},
831 {"abicalls", s_abicalls
, 0},
832 {"cpload", s_cpload
, 0},
833 {"cpsetup", s_cpsetup
, 0},
834 {"cplocal", s_cplocal
, 0},
835 {"cprestore", s_cprestore
, 0},
836 {"cpreturn", s_cpreturn
, 0},
837 {"gpvalue", s_gpvalue
, 0},
838 {"gpword", s_gpword
, 0},
839 {"cpadd", s_cpadd
, 0},
842 /* Relatively generic pseudo-ops that happen to be used on MIPS
844 {"asciiz", stringer
, 1},
845 {"bss", s_change_sec
, 'b'},
848 {"dword", s_cons
, 3},
849 {"weakext", s_mips_weakext
, 0},
851 /* These pseudo-ops are defined in read.c, but must be overridden
852 here for one reason or another. */
853 {"align", s_align
, 0},
855 {"data", s_change_sec
, 'd'},
856 {"double", s_float_cons
, 'd'},
857 {"float", s_float_cons
, 'f'},
858 {"globl", s_mips_globl
, 0},
859 {"global", s_mips_globl
, 0},
860 {"hword", s_cons
, 1},
865 {"short", s_cons
, 1},
866 {"single", s_float_cons
, 'f'},
867 {"stabn", s_mips_stab
, 'n'},
868 {"text", s_change_sec
, 't'},
871 #ifdef MIPS_STABS_ELF
872 { "extern", ecoff_directive_extern
, 0},
878 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
880 /* These pseudo-ops should be defined by the object file format.
881 However, a.out doesn't support them, so we have versions here. */
882 {"aent", s_mips_ent
, 1},
883 {"bgnb", s_ignore
, 0},
884 {"end", s_mips_end
, 0},
885 {"endb", s_ignore
, 0},
886 {"ent", s_mips_ent
, 0},
888 {"fmask", s_mips_mask
, 'F'},
889 {"frame", s_mips_frame
, 0},
890 {"loc", s_ignore
, 0},
891 {"mask", s_mips_mask
, 'R'},
892 {"verstamp", s_ignore
, 0},
896 extern void pop_insert
PARAMS ((const pseudo_typeS
*));
901 pop_insert (mips_pseudo_table
);
902 if (! ECOFF_DEBUGGING
)
903 pop_insert (mips_nonecoff_pseudo_table
);
906 /* Symbols labelling the current insn. */
908 struct insn_label_list
910 struct insn_label_list
*next
;
914 static struct insn_label_list
*insn_labels
;
915 static struct insn_label_list
*free_insn_labels
;
917 static void mips_clear_insn_labels
PARAMS ((void));
920 mips_clear_insn_labels ()
922 register struct insn_label_list
**pl
;
924 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
930 static char *expr_end
;
932 /* Expressions which appear in instructions. These are set by
935 static expressionS imm_expr
;
936 static expressionS offset_expr
;
938 /* Relocs associated with imm_expr and offset_expr. */
940 static bfd_reloc_code_real_type imm_reloc
[3]
941 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
942 static bfd_reloc_code_real_type offset_reloc
[3]
943 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
945 /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */
947 static boolean imm_unmatched_hi
;
949 /* These are set by mips16_ip if an explicit extension is used. */
951 static boolean mips16_small
, mips16_ext
;
953 #ifdef MIPS_STABS_ELF
954 /* The pdr segment for per procedure frame/regmask info */
960 mips_isa_to_str (isa
)
963 const struct mips_cpu_info
*ci
;
966 ci
= mips_cpu_info_from_isa (isa
);
970 sprintf (s
, "ISA#%d", isa
);
975 mips_cpu_to_str (cpu
)
978 const struct mips_cpu_info
*ci
;
981 ci
= mips_cpu_info_from_cpu (cpu
);
985 sprintf (s
, "CPU#%d", cpu
);
989 /* The default target format to use. */
992 mips_target_format ()
994 switch (OUTPUT_FLAVOR
)
996 case bfd_target_aout_flavour
:
997 return target_big_endian
? "a.out-mips-big" : "a.out-mips-little";
998 case bfd_target_ecoff_flavour
:
999 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
1000 case bfd_target_coff_flavour
:
1002 case bfd_target_elf_flavour
:
1004 /* This is traditional mips */
1005 return (target_big_endian
1006 ? (HAVE_64BIT_OBJECTS
? "elf64-tradbigmips"
1007 : "elf32-tradbigmips")
1008 : (HAVE_64BIT_OBJECTS
? "elf64-tradlittlemips"
1009 : "elf32-tradlittlemips"));
1011 return (target_big_endian
1012 ? (HAVE_64BIT_OBJECTS
? "elf64-bigmips" : "elf32-bigmips")
1013 : (HAVE_64BIT_OBJECTS
? "elf64-littlemips"
1014 : "elf32-littlemips"));
1022 /* This function is called once, at assembler startup time. It should
1023 set up all the tables, etc. that the MD part of the assembler will need. */
1028 register const char *retval
= NULL
;
1033 int mips_isa_from_cpu
;
1034 int target_cpu_had_mips16
= 0;
1035 const struct mips_cpu_info
*ci
;
1037 /* GP relative stuff not working for PE */
1038 if (strncmp (TARGET_OS
, "pe", 2) == 0
1039 && g_switch_value
!= 0)
1042 as_bad (_("-G not supported in this configuration."));
1047 if (strcmp (cpu
+ (sizeof TARGET_CPU
) - 3, "el") == 0)
1049 a
= xmalloc (sizeof TARGET_CPU
);
1050 strcpy (a
, TARGET_CPU
);
1051 a
[(sizeof TARGET_CPU
) - 3] = '\0';
1055 if (strncmp (cpu
, "mips16", sizeof "mips16" - 1) == 0)
1057 target_cpu_had_mips16
= 1;
1058 cpu
+= sizeof "mips16" - 1;
1061 if (mips_opts
.mips16
< 0)
1062 mips_opts
.mips16
= target_cpu_had_mips16
;
1064 /* Backward compatibility for historic -mcpu= option. Check for
1065 incompatible options, warn if -mcpu is used. */
1066 if (mips_cpu
!= CPU_UNKNOWN
1067 && mips_arch
!= CPU_UNKNOWN
1068 && mips_cpu
!= mips_arch
)
1070 as_fatal (_("The -mcpu option can't be used together with -march. "
1071 "Use -mtune instead of -mcpu."));
1074 if (mips_cpu
!= CPU_UNKNOWN
1075 && mips_tune
!= CPU_UNKNOWN
1076 && mips_cpu
!= mips_tune
)
1078 as_fatal (_("The -mcpu option can't be used together with -mtune. "
1079 "Use -march instead of -mcpu."));
1083 /* For backward compatibility, let -mipsN set various defaults. */
1084 /* This code should go away, to be replaced with something rather more
1085 draconian. Until GCC 3.1 has been released for some reasonable
1086 amount of time, however, we need to support this. */
1087 if (mips_opts
.isa
!= ISA_UNKNOWN
)
1089 /* Translate -mipsN to the appropriate settings of file_mips_gp32
1090 and file_mips_fp32. Tag binaries as using the mipsN ISA. */
1091 if (file_mips_gp32
< 0)
1093 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
1098 if (file_mips_fp32
< 0)
1100 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
1106 ci
= mips_cpu_info_from_isa (mips_opts
.isa
);
1107 assert (ci
!= NULL
);
1108 /* -mipsN has higher priority than -mcpu but lower than -march. */
1109 if (mips_arch
== CPU_UNKNOWN
)
1110 mips_arch
= ci
->cpu
;
1112 /* Default mips_abi. */
1113 if (mips_opts
.abi
== NO_ABI
)
1115 if (mips_opts
.isa
== ISA_MIPS1
|| mips_opts
.isa
== ISA_MIPS2
)
1116 mips_opts
.abi
= O32_ABI
;
1117 else if (mips_opts
.isa
== ISA_MIPS3
|| mips_opts
.isa
== ISA_MIPS4
)
1118 mips_opts
.abi
= O64_ABI
;
1122 if (mips_arch
== CPU_UNKNOWN
&& mips_cpu
!= CPU_UNKNOWN
)
1124 ci
= mips_cpu_info_from_cpu (mips_cpu
);
1125 assert (ci
!= NULL
);
1126 mips_arch
= ci
->cpu
;
1127 as_warn (_("The -mcpu option is deprecated. Please use -march and "
1128 "-mtune instead."));
1131 /* Set tune from -mcpu, not from -mipsN. */
1132 if (mips_tune
== CPU_UNKNOWN
&& mips_cpu
!= CPU_UNKNOWN
)
1134 ci
= mips_cpu_info_from_cpu (mips_cpu
);
1135 assert (ci
!= NULL
);
1136 mips_tune
= ci
->cpu
;
1139 /* At this point, mips_arch will either be CPU_UNKNOWN if no ARCH was
1140 specified on the command line, or some other value if one was.
1141 Similarly, mips_opts.isa will be ISA_UNKNOWN if not specified on
1142 the command line, or will be set otherwise if one was. */
1144 if (mips_arch
!= CPU_UNKNOWN
&& mips_opts
.isa
!= ISA_UNKNOWN
)
1145 /* Handled above. */;
1147 if (mips_arch
== CPU_UNKNOWN
&& mips_cpu
!= CPU_UNKNOWN
)
1149 ci
= mips_cpu_info_from_cpu (mips_cpu
);
1150 assert (ci
!= NULL
);
1151 mips_arch
= ci
->cpu
;
1152 as_warn (_("The -mcpu option is deprecated. Please use -march and "
1153 "-mtune instead."));
1156 /* At this point, mips_arch will either be CPU_UNKNOWN if no ARCH was
1157 specified on the command line, or some other value if one was.
1158 Similarly, mips_opts.isa will be ISA_UNKNOWN if not specified on
1159 the command line, or will be set otherwise if one was. */
1161 if (mips_arch
!= CPU_UNKNOWN
&& mips_opts
.isa
!= ISA_UNKNOWN
)
1163 /* We have to check if the isa is the default isa of arch. Otherwise
1164 we'll get invalid object file headers. */
1165 ci
= mips_cpu_info_from_cpu (mips_arch
);
1166 assert (ci
!= NULL
);
1167 if (mips_opts
.isa
!= ci
->isa
)
1169 /* This really should be an error instead of a warning, but old
1170 compilers only have -mcpu which sets both arch and tune. For
1171 now, we discard arch and preserve tune. */
1172 as_warn (_("The -march option is incompatible to -mipsN and "
1173 "therefore ignored."));
1174 if (mips_tune
== CPU_UNKNOWN
)
1175 mips_tune
= mips_arch
;
1176 ci
= mips_cpu_info_from_isa (mips_opts
.isa
);
1177 assert (ci
!= NULL
);
1178 mips_arch
= ci
->cpu
;
1182 else if (mips_arch
!= CPU_UNKNOWN
&& mips_opts
.isa
== ISA_UNKNOWN
)
1184 /* We have ARCH, we need ISA. */
1185 ci
= mips_cpu_info_from_cpu (mips_arch
);
1186 assert (ci
!= NULL
);
1187 mips_opts
.isa
= ci
->isa
;
1189 else if (mips_arch
== CPU_UNKNOWN
&& mips_opts
.isa
!= ISA_UNKNOWN
)
1191 /* We have ISA, we need default ARCH. */
1192 ci
= mips_cpu_info_from_isa (mips_opts
.isa
);
1193 assert (ci
!= NULL
);
1194 mips_arch
= ci
->cpu
;
1198 /* We need to set both ISA and ARCH from target cpu. */
1199 ci
= mips_cpu_info_from_name (cpu
);
1201 ci
= mips_cpu_info_from_cpu (CPU_R3000
);
1202 assert (ci
!= NULL
);
1203 mips_opts
.isa
= ci
->isa
;
1204 mips_arch
= ci
->cpu
;
1207 if (mips_tune
== CPU_UNKNOWN
)
1208 mips_tune
= mips_arch
;
1210 ci
= mips_cpu_info_from_cpu (mips_arch
);
1211 assert (ci
!= NULL
);
1212 mips_isa_from_cpu
= ci
->isa
;
1214 /* End of TARGET_CPU processing, get rid of malloced memory
1223 if (mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
1224 as_bad (_("trap exception not supported at ISA 1"));
1226 /* Set the EABI kind based on the ISA before the user gets
1227 to change the ISA with directives. This isn't really
1228 the best, but then neither is basing the abi on the isa. */
1229 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
)
1230 && mips_opts
.abi
== EABI_ABI
)
1233 /* If they asked for mips1 or mips2 and a cpu that is
1234 mips3 or greater, then mark the object file 32BITMODE. */
1235 if (mips_isa_from_cpu
!= ISA_UNKNOWN
1236 && ! ISA_HAS_64BIT_REGS (mips_opts
.isa
)
1237 && ISA_HAS_64BIT_REGS (mips_isa_from_cpu
))
1240 /* If the selected architecture includes support for ASEs, enable
1241 generation of code for them. */
1242 if (mips_opts
.ase_mips3d
== -1 && CPU_HAS_MIPS3D (mips_arch
))
1243 mips_opts
.ase_mips3d
= 1;
1245 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, mips_arch
))
1246 as_warn (_("Could not set architecture and machine"));
1248 if (file_mips_gp32
< 0)
1250 if (file_mips_fp32
< 0)
1253 file_mips_isa
= mips_opts
.isa
;
1254 file_mips_abi
= mips_opts
.abi
;
1255 file_ase_mips3d
= mips_opts
.ase_mips3d
;
1256 mips_opts
.gp32
= file_mips_gp32
;
1257 mips_opts
.fp32
= file_mips_fp32
;
1262 op_hash
= hash_new ();
1264 for (i
= 0; i
< NUMOPCODES
;)
1266 const char *name
= mips_opcodes
[i
].name
;
1268 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
1271 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
1272 mips_opcodes
[i
].name
, retval
);
1273 /* Probably a memory allocation problem? Give up now. */
1274 as_fatal (_("Broken assembler. No assembly attempted."));
1278 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
1280 if (!validate_mips_insn (&mips_opcodes
[i
]))
1285 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
1288 mips16_op_hash
= hash_new ();
1291 while (i
< bfd_mips16_num_opcodes
)
1293 const char *name
= mips16_opcodes
[i
].name
;
1295 retval
= hash_insert (mips16_op_hash
, name
, (PTR
) &mips16_opcodes
[i
]);
1297 as_fatal (_("internal: can't hash `%s': %s"),
1298 mips16_opcodes
[i
].name
, retval
);
1301 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
1302 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
1303 != mips16_opcodes
[i
].match
))
1305 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
1306 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
1311 while (i
< bfd_mips16_num_opcodes
1312 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
1316 as_fatal (_("Broken assembler. No assembly attempted."));
1318 /* We add all the general register names to the symbol table. This
1319 helps us detect invalid uses of them. */
1320 for (i
= 0; i
< 32; i
++)
1324 sprintf (buf
, "$%d", i
);
1325 symbol_table_insert (symbol_new (buf
, reg_section
, i
,
1326 &zero_address_frag
));
1328 symbol_table_insert (symbol_new ("$fp", reg_section
, FP
,
1329 &zero_address_frag
));
1330 symbol_table_insert (symbol_new ("$sp", reg_section
, SP
,
1331 &zero_address_frag
));
1332 symbol_table_insert (symbol_new ("$gp", reg_section
, GP
,
1333 &zero_address_frag
));
1334 symbol_table_insert (symbol_new ("$at", reg_section
, AT
,
1335 &zero_address_frag
));
1336 symbol_table_insert (symbol_new ("$kt0", reg_section
, KT0
,
1337 &zero_address_frag
));
1338 symbol_table_insert (symbol_new ("$kt1", reg_section
, KT1
,
1339 &zero_address_frag
));
1340 symbol_table_insert (symbol_new ("$pc", reg_section
, -1,
1341 &zero_address_frag
));
1343 mips_no_prev_insn (false);
1346 mips_cprmask
[0] = 0;
1347 mips_cprmask
[1] = 0;
1348 mips_cprmask
[2] = 0;
1349 mips_cprmask
[3] = 0;
1351 /* set the default alignment for the text section (2**2) */
1352 record_alignment (text_section
, 2);
1354 if (USE_GLOBAL_POINTER_OPT
)
1355 bfd_set_gp_size (stdoutput
, g_switch_value
);
1357 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1359 /* On a native system, sections must be aligned to 16 byte
1360 boundaries. When configured for an embedded ELF target, we
1362 if (strcmp (TARGET_OS
, "elf") != 0)
1364 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
1365 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
1366 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
1369 /* Create a .reginfo section for register masks and a .mdebug
1370 section for debugging information. */
1378 subseg
= now_subseg
;
1380 /* The ABI says this section should be loaded so that the
1381 running program can access it. However, we don't load it
1382 if we are configured for an embedded target */
1383 flags
= SEC_READONLY
| SEC_DATA
;
1384 if (strcmp (TARGET_OS
, "elf") != 0)
1385 flags
|= SEC_ALLOC
| SEC_LOAD
;
1387 if (file_mips_abi
!= N64_ABI
)
1389 sec
= subseg_new (".reginfo", (subsegT
) 0);
1391 bfd_set_section_flags (stdoutput
, sec
, flags
);
1392 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
1395 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
1400 /* The 64-bit ABI uses a .MIPS.options section rather than
1401 .reginfo section. */
1402 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
1403 bfd_set_section_flags (stdoutput
, sec
, flags
);
1404 bfd_set_section_alignment (stdoutput
, sec
, 3);
1407 /* Set up the option header. */
1409 Elf_Internal_Options opthdr
;
1412 opthdr
.kind
= ODK_REGINFO
;
1413 opthdr
.size
= (sizeof (Elf_External_Options
)
1414 + sizeof (Elf64_External_RegInfo
));
1417 f
= frag_more (sizeof (Elf_External_Options
));
1418 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
1419 (Elf_External_Options
*) f
);
1421 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
1426 if (ECOFF_DEBUGGING
)
1428 sec
= subseg_new (".mdebug", (subsegT
) 0);
1429 (void) bfd_set_section_flags (stdoutput
, sec
,
1430 SEC_HAS_CONTENTS
| SEC_READONLY
);
1431 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1434 #ifdef MIPS_STABS_ELF
1435 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
1436 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
1437 SEC_READONLY
| SEC_RELOC
| SEC_DEBUGGING
);
1438 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
1441 subseg_set (seg
, subseg
);
1445 if (! ECOFF_DEBUGGING
)
1452 if (! ECOFF_DEBUGGING
)
1460 struct mips_cl_insn insn
;
1461 bfd_reloc_code_real_type unused_reloc
[3]
1462 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1464 imm_expr
.X_op
= O_absent
;
1465 imm_unmatched_hi
= false;
1466 offset_expr
.X_op
= O_absent
;
1467 imm_reloc
[0] = BFD_RELOC_UNUSED
;
1468 imm_reloc
[1] = BFD_RELOC_UNUSED
;
1469 imm_reloc
[2] = BFD_RELOC_UNUSED
;
1470 offset_reloc
[0] = BFD_RELOC_UNUSED
;
1471 offset_reloc
[1] = BFD_RELOC_UNUSED
;
1472 offset_reloc
[2] = BFD_RELOC_UNUSED
;
1474 if (mips_opts
.mips16
)
1475 mips16_ip (str
, &insn
);
1478 mips_ip (str
, &insn
);
1479 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1480 str
, insn
.insn_opcode
));
1485 as_bad ("%s `%s'", insn_error
, str
);
1489 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1491 if (mips_opts
.mips16
)
1492 mips16_macro (&insn
);
1498 if (imm_expr
.X_op
!= O_absent
)
1499 append_insn (NULL
, &insn
, &imm_expr
, imm_reloc
, imm_unmatched_hi
);
1500 else if (offset_expr
.X_op
!= O_absent
)
1501 append_insn (NULL
, &insn
, &offset_expr
, offset_reloc
, false);
1503 append_insn (NULL
, &insn
, NULL
, unused_reloc
, false);
1507 /* See whether instruction IP reads register REG. CLASS is the type
1511 insn_uses_reg (ip
, reg
, class)
1512 struct mips_cl_insn
*ip
;
1514 enum mips_regclass
class;
1516 if (class == MIPS16_REG
)
1518 assert (mips_opts
.mips16
);
1519 reg
= mips16_to_32_reg_map
[reg
];
1520 class = MIPS_GR_REG
;
1523 /* Don't report on general register 0, since it never changes. */
1524 if (class == MIPS_GR_REG
&& reg
== 0)
1527 if (class == MIPS_FP_REG
)
1529 assert (! mips_opts
.mips16
);
1530 /* If we are called with either $f0 or $f1, we must check $f0.
1531 This is not optimal, because it will introduce an unnecessary
1532 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1533 need to distinguish reading both $f0 and $f1 or just one of
1534 them. Note that we don't have to check the other way,
1535 because there is no instruction that sets both $f0 and $f1
1536 and requires a delay. */
1537 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
1538 && ((((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
) &~(unsigned)1)
1539 == (reg
&~ (unsigned) 1)))
1541 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
1542 && ((((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
) &~(unsigned)1)
1543 == (reg
&~ (unsigned) 1)))
1546 else if (! mips_opts
.mips16
)
1548 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
1549 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
1551 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
1552 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
1557 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
1558 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1559 & MIPS16OP_MASK_RX
)]
1562 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
1563 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1564 & MIPS16OP_MASK_RY
)]
1567 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
1568 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1569 & MIPS16OP_MASK_MOVE32Z
)]
1572 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
1574 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
1576 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
1578 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
1579 && ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1580 & MIPS16OP_MASK_REGR32
) == reg
)
1587 /* This function returns true if modifying a register requires a
1591 reg_needs_delay (reg
)
1594 unsigned long prev_pinfo
;
1596 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1597 if (! mips_opts
.noreorder
1598 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1599 && ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1600 || (! gpr_interlocks
1601 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1603 /* A load from a coprocessor or from memory. All load
1604 delays delay the use of general register rt for one
1605 instruction on the r3000. The r6000 and r4000 use
1607 /* Itbl support may require additional care here. */
1608 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1609 if (reg
== ((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
))
1616 /* Mark instruction labels in mips16 mode. This permits the linker to
1617 handle them specially, such as generating jalx instructions when
1618 needed. We also make them odd for the duration of the assembly, in
1619 order to generate the right sort of code. We will make them even
1620 in the adjust_symtab routine, while leaving them marked. This is
1621 convenient for the debugger and the disassembler. The linker knows
1622 to make them odd again. */
1625 mips16_mark_labels ()
1627 if (mips_opts
.mips16
)
1629 struct insn_label_list
*l
;
1632 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1635 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1636 S_SET_OTHER (l
->label
, STO_MIPS16
);
1638 val
= S_GET_VALUE (l
->label
);
1640 S_SET_VALUE (l
->label
, val
+ 1);
1645 /* Output an instruction. PLACE is where to put the instruction; if
1646 it is NULL, this uses frag_more to get room. IP is the instruction
1647 information. ADDRESS_EXPR is an operand of the instruction to be
1648 used with RELOC_TYPE. */
1651 append_insn (place
, ip
, address_expr
, reloc_type
, unmatched_hi
)
1653 struct mips_cl_insn
*ip
;
1654 expressionS
*address_expr
;
1655 bfd_reloc_code_real_type
*reloc_type
;
1656 boolean unmatched_hi
;
1658 register unsigned long prev_pinfo
, pinfo
;
1663 /* Mark instruction labels in mips16 mode. */
1664 mips16_mark_labels ();
1666 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1667 pinfo
= ip
->insn_mo
->pinfo
;
1669 if (place
== NULL
&& (! mips_opts
.noreorder
|| prev_nop_frag
!= NULL
))
1673 /* If the previous insn required any delay slots, see if we need
1674 to insert a NOP or two. There are eight kinds of possible
1675 hazards, of which an instruction can have at most one type.
1676 (1) a load from memory delay
1677 (2) a load from a coprocessor delay
1678 (3) an unconditional branch delay
1679 (4) a conditional branch delay
1680 (5) a move to coprocessor register delay
1681 (6) a load coprocessor register from memory delay
1682 (7) a coprocessor condition code delay
1683 (8) a HI/LO special register delay
1685 There are a lot of optimizations we could do that we don't.
1686 In particular, we do not, in general, reorder instructions.
1687 If you use gcc with optimization, it will reorder
1688 instructions and generally do much more optimization then we
1689 do here; repeating all that work in the assembler would only
1690 benefit hand written assembly code, and does not seem worth
1693 /* This is how a NOP is emitted. */
1694 #define emit_nop() \
1696 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1697 : md_number_to_chars (frag_more (4), 0, 4))
1699 /* The previous insn might require a delay slot, depending upon
1700 the contents of the current insn. */
1701 if (! mips_opts
.mips16
1702 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1703 && (((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1704 && ! cop_interlocks
)
1705 || (! gpr_interlocks
1706 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1708 /* A load from a coprocessor or from memory. All load
1709 delays delay the use of general register rt for one
1710 instruction on the r3000. The r6000 and r4000 use
1712 /* Itbl support may require additional care here. */
1713 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1714 if (mips_optimize
== 0
1715 || insn_uses_reg (ip
,
1716 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1721 else if (! mips_opts
.mips16
1722 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1723 && (((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
1724 && ! cop_interlocks
)
1725 || (mips_opts
.isa
== ISA_MIPS1
1726 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))))
1728 /* A generic coprocessor delay. The previous instruction
1729 modified a coprocessor general or control register. If
1730 it modified a control register, we need to avoid any
1731 coprocessor instruction (this is probably not always
1732 required, but it sometimes is). If it modified a general
1733 register, we avoid using that register.
1735 On the r6000 and r4000 loading a coprocessor register
1736 from memory is interlocked, and does not require a delay.
1738 This case is not handled very well. There is no special
1739 knowledge of CP0 handling, and the coprocessors other
1740 than the floating point unit are not distinguished at
1742 /* Itbl support may require additional care here. FIXME!
1743 Need to modify this to include knowledge about
1744 user specified delays! */
1745 if (prev_pinfo
& INSN_WRITE_FPR_T
)
1747 if (mips_optimize
== 0
1748 || insn_uses_reg (ip
,
1749 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
1754 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
1756 if (mips_optimize
== 0
1757 || insn_uses_reg (ip
,
1758 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
1765 /* We don't know exactly what the previous instruction
1766 does. If the current instruction uses a coprocessor
1767 register, we must insert a NOP. If previous
1768 instruction may set the condition codes, and the
1769 current instruction uses them, we must insert two
1771 /* Itbl support may require additional care here. */
1772 if (mips_optimize
== 0
1773 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
1774 && (pinfo
& INSN_READ_COND_CODE
)))
1776 else if (pinfo
& INSN_COP
)
1780 else if (! mips_opts
.mips16
1781 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1782 && (prev_pinfo
& INSN_WRITE_COND_CODE
)
1783 && ! cop_interlocks
)
1785 /* The previous instruction sets the coprocessor condition
1786 codes, but does not require a general coprocessor delay
1787 (this means it is a floating point comparison
1788 instruction). If this instruction uses the condition
1789 codes, we need to insert a single NOP. */
1790 /* Itbl support may require additional care here. */
1791 if (mips_optimize
== 0
1792 || (pinfo
& INSN_READ_COND_CODE
))
1796 /* If we're fixing up mfhi/mflo for the r7000 and the
1797 previous insn was an mfhi/mflo and the current insn
1798 reads the register that the mfhi/mflo wrote to, then
1801 else if (mips_7000_hilo_fix
1802 && MF_HILO_INSN (prev_pinfo
)
1803 && insn_uses_reg (ip
, ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1810 /* If we're fixing up mfhi/mflo for the r7000 and the
1811 2nd previous insn was an mfhi/mflo and the current insn
1812 reads the register that the mfhi/mflo wrote to, then
1815 else if (mips_7000_hilo_fix
1816 && MF_HILO_INSN (prev_prev_insn
.insn_opcode
)
1817 && insn_uses_reg (ip
, ((prev_prev_insn
.insn_opcode
>> OP_SH_RD
)
1825 else if (prev_pinfo
& INSN_READ_LO
)
1827 /* The previous instruction reads the LO register; if the
1828 current instruction writes to the LO register, we must
1829 insert two NOPS. Some newer processors have interlocks.
1830 Also the tx39's multiply instructions can be exectuted
1831 immediatly after a read from HI/LO (without the delay),
1832 though the tx39's divide insns still do require the
1834 if (! (hilo_interlocks
1835 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
1836 && (mips_optimize
== 0
1837 || (pinfo
& INSN_WRITE_LO
)))
1839 /* Most mips16 branch insns don't have a delay slot.
1840 If a read from LO is immediately followed by a branch
1841 to a write to LO we have a read followed by a write
1842 less than 2 insns away. We assume the target of
1843 a branch might be a write to LO, and insert a nop
1844 between a read and an immediately following branch. */
1845 else if (mips_opts
.mips16
1846 && (mips_optimize
== 0
1847 || (pinfo
& MIPS16_INSN_BRANCH
)))
1850 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1852 /* The previous instruction reads the HI register; if the
1853 current instruction writes to the HI register, we must
1854 insert a NOP. Some newer processors have interlocks.
1855 Also the note tx39's multiply above. */
1856 if (! (hilo_interlocks
1857 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
1858 && (mips_optimize
== 0
1859 || (pinfo
& INSN_WRITE_HI
)))
1861 /* Most mips16 branch insns don't have a delay slot.
1862 If a read from HI is immediately followed by a branch
1863 to a write to HI we have a read followed by a write
1864 less than 2 insns away. We assume the target of
1865 a branch might be a write to HI, and insert a nop
1866 between a read and an immediately following branch. */
1867 else if (mips_opts
.mips16
1868 && (mips_optimize
== 0
1869 || (pinfo
& MIPS16_INSN_BRANCH
)))
1873 /* If the previous instruction was in a noreorder section, then
1874 we don't want to insert the nop after all. */
1875 /* Itbl support may require additional care here. */
1876 if (prev_insn_unreordered
)
1879 /* There are two cases which require two intervening
1880 instructions: 1) setting the condition codes using a move to
1881 coprocessor instruction which requires a general coprocessor
1882 delay and then reading the condition codes 2) reading the HI
1883 or LO register and then writing to it (except on processors
1884 which have interlocks). If we are not already emitting a NOP
1885 instruction, we must check for these cases compared to the
1886 instruction previous to the previous instruction. */
1887 if ((! mips_opts
.mips16
1888 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1889 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1890 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1891 && (pinfo
& INSN_READ_COND_CODE
)
1892 && ! cop_interlocks
)
1893 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
1894 && (pinfo
& INSN_WRITE_LO
)
1895 && ! (hilo_interlocks
1896 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
))))
1897 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1898 && (pinfo
& INSN_WRITE_HI
)
1899 && ! (hilo_interlocks
1900 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
)))))
1905 if (prev_prev_insn_unreordered
)
1908 if (prev_prev_nop
&& nops
== 0)
1911 /* If we are being given a nop instruction, don't bother with
1912 one of the nops we would otherwise output. This will only
1913 happen when a nop instruction is used with mips_optimize set
1916 && ! mips_opts
.noreorder
1917 && ip
->insn_opcode
== (unsigned) (mips_opts
.mips16
? 0x6500 : 0))
1920 /* Now emit the right number of NOP instructions. */
1921 if (nops
> 0 && ! mips_opts
.noreorder
)
1924 unsigned long old_frag_offset
;
1926 struct insn_label_list
*l
;
1928 old_frag
= frag_now
;
1929 old_frag_offset
= frag_now_fix ();
1931 for (i
= 0; i
< nops
; i
++)
1936 listing_prev_line ();
1937 /* We may be at the start of a variant frag. In case we
1938 are, make sure there is enough space for the frag
1939 after the frags created by listing_prev_line. The
1940 argument to frag_grow here must be at least as large
1941 as the argument to all other calls to frag_grow in
1942 this file. We don't have to worry about being in the
1943 middle of a variant frag, because the variants insert
1944 all needed nop instructions themselves. */
1948 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1952 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
1953 symbol_set_frag (l
->label
, frag_now
);
1954 val
= (valueT
) frag_now_fix ();
1955 /* mips16 text labels are stored as odd. */
1956 if (mips_opts
.mips16
)
1958 S_SET_VALUE (l
->label
, val
);
1961 #ifndef NO_ECOFF_DEBUGGING
1962 if (ECOFF_DEBUGGING
)
1963 ecoff_fix_loc (old_frag
, old_frag_offset
);
1966 else if (prev_nop_frag
!= NULL
)
1968 /* We have a frag holding nops we may be able to remove. If
1969 we don't need any nops, we can decrease the size of
1970 prev_nop_frag by the size of one instruction. If we do
1971 need some nops, we count them in prev_nops_required. */
1972 if (prev_nop_frag_since
== 0)
1976 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1977 --prev_nop_frag_holds
;
1980 prev_nop_frag_required
+= nops
;
1984 if (prev_prev_nop
== 0)
1986 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1987 --prev_nop_frag_holds
;
1990 ++prev_nop_frag_required
;
1993 if (prev_nop_frag_holds
<= prev_nop_frag_required
)
1994 prev_nop_frag
= NULL
;
1996 ++prev_nop_frag_since
;
1998 /* Sanity check: by the time we reach the second instruction
1999 after prev_nop_frag, we should have used up all the nops
2000 one way or another. */
2001 assert (prev_nop_frag_since
<= 1 || prev_nop_frag
== NULL
);
2005 if (*reloc_type
> BFD_RELOC_UNUSED
)
2007 /* We need to set up a variant frag. */
2008 assert (mips_opts
.mips16
&& address_expr
!= NULL
);
2009 f
= frag_var (rs_machine_dependent
, 4, 0,
2010 RELAX_MIPS16_ENCODE (*reloc_type
- BFD_RELOC_UNUSED
,
2011 mips16_small
, mips16_ext
,
2013 & INSN_UNCOND_BRANCH_DELAY
),
2014 (*prev_insn_reloc_type
2015 == BFD_RELOC_MIPS16_JMP
)),
2016 make_expr_symbol (address_expr
), 0, NULL
);
2018 else if (place
!= NULL
)
2020 else if (mips_opts
.mips16
2022 && *reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2024 /* Make sure there is enough room to swap this instruction with
2025 a following jump instruction. */
2031 if (mips_opts
.mips16
2032 && mips_opts
.noreorder
2033 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
2034 as_warn (_("extended instruction in delay slot"));
2039 fixp
[0] = fixp
[1] = fixp
[2] = NULL
;
2040 if (address_expr
!= NULL
&& *reloc_type
< BFD_RELOC_UNUSED
)
2042 if (address_expr
->X_op
== O_constant
)
2046 switch (*reloc_type
)
2049 ip
->insn_opcode
|= address_expr
->X_add_number
;
2052 case BFD_RELOC_MIPS_HIGHEST
:
2053 tmp
= (address_expr
->X_add_number
+ 0x800080008000) >> 16;
2055 ip
->insn_opcode
|= (tmp
>> 16) & 0xffff;
2058 case BFD_RELOC_MIPS_HIGHER
:
2059 tmp
= (address_expr
->X_add_number
+ 0x80008000) >> 16;
2060 ip
->insn_opcode
|= (tmp
>> 16) & 0xffff;
2063 case BFD_RELOC_HI16_S
:
2064 ip
->insn_opcode
|= ((address_expr
->X_add_number
+ 0x8000)
2068 case BFD_RELOC_HI16
:
2069 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 16) & 0xffff;
2072 case BFD_RELOC_LO16
:
2073 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
2076 case BFD_RELOC_MIPS_JMP
:
2077 if ((address_expr
->X_add_number
& 3) != 0)
2078 as_bad (_("jump to misaligned address (0x%lx)"),
2079 (unsigned long) address_expr
->X_add_number
);
2080 if (address_expr
->X_add_number
& ~0xfffffff
2081 || address_expr
->X_add_number
> 0x7fffffc)
2082 as_bad (_("jump address range overflow (0x%lx)"),
2083 (unsigned long) address_expr
->X_add_number
);
2084 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
2087 case BFD_RELOC_MIPS16_JMP
:
2088 if ((address_expr
->X_add_number
& 3) != 0)
2089 as_bad (_("jump to misaligned address (0x%lx)"),
2090 (unsigned long) address_expr
->X_add_number
);
2091 if (address_expr
->X_add_number
& ~0xfffffff
2092 || address_expr
->X_add_number
> 0x7fffffc)
2093 as_bad (_("jump address range overflow (0x%lx)"),
2094 (unsigned long) address_expr
->X_add_number
);
2096 (((address_expr
->X_add_number
& 0x7c0000) << 3)
2097 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
2098 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
2101 case BFD_RELOC_16_PCREL
:
2102 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
2105 case BFD_RELOC_16_PCREL_S2
:
2115 /* Don't generate a reloc if we are writing into a variant frag. */
2118 fixp
[0] = fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
2120 (*reloc_type
== BFD_RELOC_16_PCREL
2121 || *reloc_type
== BFD_RELOC_16_PCREL_S2
),
2124 /* These relocations can have an addend that won't fit in
2125 4 octets for 64bit assembly. */
2126 if (HAVE_64BIT_GPRS
&&
2127 (*reloc_type
== BFD_RELOC_16
2128 || *reloc_type
== BFD_RELOC_32
2129 || *reloc_type
== BFD_RELOC_MIPS_JMP
2130 || *reloc_type
== BFD_RELOC_HI16_S
2131 || *reloc_type
== BFD_RELOC_LO16
2132 || *reloc_type
== BFD_RELOC_GPREL16
2133 || *reloc_type
== BFD_RELOC_MIPS_LITERAL
2134 || *reloc_type
== BFD_RELOC_GPREL32
2135 || *reloc_type
== BFD_RELOC_64
2136 || *reloc_type
== BFD_RELOC_CTOR
2137 || *reloc_type
== BFD_RELOC_MIPS_SUB
2138 || *reloc_type
== BFD_RELOC_MIPS_HIGHEST
2139 || *reloc_type
== BFD_RELOC_MIPS_HIGHER
2140 || *reloc_type
== BFD_RELOC_MIPS_SCN_DISP
2141 || *reloc_type
== BFD_RELOC_MIPS_REL16
2142 || *reloc_type
== BFD_RELOC_MIPS_RELGOT
))
2143 fixp
[0]->fx_no_overflow
= 1;
2147 struct mips_hi_fixup
*hi_fixup
;
2149 assert (*reloc_type
== BFD_RELOC_HI16_S
);
2150 hi_fixup
= ((struct mips_hi_fixup
*)
2151 xmalloc (sizeof (struct mips_hi_fixup
)));
2152 hi_fixup
->fixp
= fixp
[0];
2153 hi_fixup
->seg
= now_seg
;
2154 hi_fixup
->next
= mips_hi_fixup_list
;
2155 mips_hi_fixup_list
= hi_fixup
;
2158 if (reloc_type
[1] != BFD_RELOC_UNUSED
)
2160 /* FIXME: This symbol can be one of
2161 RSS_UNDEF, RSS_GP, RSS_GP0, RSS_LOC. */
2162 address_expr
->X_op
= O_absent
;
2163 address_expr
->X_add_symbol
= 0;
2164 address_expr
->X_add_number
= 0;
2166 fixp
[1] = fix_new_exp (frag_now
, f
- frag_now
->fr_literal
,
2167 4, address_expr
, false,
2170 /* These relocations can have an addend that won't fit in
2171 4 octets for 64bit assembly. */
2172 if (HAVE_64BIT_GPRS
&&
2173 (*reloc_type
== BFD_RELOC_16
2174 || *reloc_type
== BFD_RELOC_32
2175 || *reloc_type
== BFD_RELOC_MIPS_JMP
2176 || *reloc_type
== BFD_RELOC_HI16_S
2177 || *reloc_type
== BFD_RELOC_LO16
2178 || *reloc_type
== BFD_RELOC_GPREL16
2179 || *reloc_type
== BFD_RELOC_MIPS_LITERAL
2180 || *reloc_type
== BFD_RELOC_GPREL32
2181 || *reloc_type
== BFD_RELOC_64
2182 || *reloc_type
== BFD_RELOC_CTOR
2183 || *reloc_type
== BFD_RELOC_MIPS_SUB
2184 || *reloc_type
== BFD_RELOC_MIPS_HIGHEST
2185 || *reloc_type
== BFD_RELOC_MIPS_HIGHER
2186 || *reloc_type
== BFD_RELOC_MIPS_SCN_DISP
2187 || *reloc_type
== BFD_RELOC_MIPS_REL16
2188 || *reloc_type
== BFD_RELOC_MIPS_RELGOT
))
2189 fixp
[1]->fx_no_overflow
= 1;
2191 if (reloc_type
[2] != BFD_RELOC_UNUSED
)
2193 address_expr
->X_op
= O_absent
;
2194 address_expr
->X_add_symbol
= 0;
2195 address_expr
->X_add_number
= 0;
2197 fixp
[2] = fix_new_exp (frag_now
,
2198 f
- frag_now
->fr_literal
, 4,
2199 address_expr
, false,
2202 /* These relocations can have an addend that won't fit in
2203 4 octets for 64bit assembly. */
2204 if (HAVE_64BIT_GPRS
&&
2205 (*reloc_type
== BFD_RELOC_16
2206 || *reloc_type
== BFD_RELOC_32
2207 || *reloc_type
== BFD_RELOC_MIPS_JMP
2208 || *reloc_type
== BFD_RELOC_HI16_S
2209 || *reloc_type
== BFD_RELOC_LO16
2210 || *reloc_type
== BFD_RELOC_GPREL16
2211 || *reloc_type
== BFD_RELOC_MIPS_LITERAL
2212 || *reloc_type
== BFD_RELOC_GPREL32
2213 || *reloc_type
== BFD_RELOC_64
2214 || *reloc_type
== BFD_RELOC_CTOR
2215 || *reloc_type
== BFD_RELOC_MIPS_SUB
2216 || *reloc_type
== BFD_RELOC_MIPS_HIGHEST
2217 || *reloc_type
== BFD_RELOC_MIPS_HIGHER
2218 || *reloc_type
== BFD_RELOC_MIPS_SCN_DISP
2219 || *reloc_type
== BFD_RELOC_MIPS_REL16
2220 || *reloc_type
== BFD_RELOC_MIPS_RELGOT
))
2221 fixp
[2]->fx_no_overflow
= 1;
2228 if (! mips_opts
.mips16
)
2229 md_number_to_chars (f
, ip
->insn_opcode
, 4);
2230 else if (*reloc_type
== BFD_RELOC_MIPS16_JMP
)
2232 md_number_to_chars (f
, ip
->insn_opcode
>> 16, 2);
2233 md_number_to_chars (f
+ 2, ip
->insn_opcode
& 0xffff, 2);
2239 md_number_to_chars (f
, 0xf000 | ip
->extend
, 2);
2242 md_number_to_chars (f
, ip
->insn_opcode
, 2);
2245 /* Update the register mask information. */
2246 if (! mips_opts
.mips16
)
2248 if (pinfo
& INSN_WRITE_GPR_D
)
2249 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
2250 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
2251 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
2252 if (pinfo
& INSN_READ_GPR_S
)
2253 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
2254 if (pinfo
& INSN_WRITE_GPR_31
)
2255 mips_gprmask
|= 1 << RA
;
2256 if (pinfo
& INSN_WRITE_FPR_D
)
2257 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
2258 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
2259 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
2260 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
2261 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
2262 if ((pinfo
& INSN_READ_FPR_R
) != 0)
2263 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
2264 if (pinfo
& INSN_COP
)
2266 /* We don't keep enough information to sort these cases out.
2267 The itbl support does keep this information however, although
2268 we currently don't support itbl fprmats as part of the cop
2269 instruction. May want to add this support in the future. */
2271 /* Never set the bit for $0, which is always zero. */
2272 mips_gprmask
&= ~1 << 0;
2276 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
2277 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
2278 & MIPS16OP_MASK_RX
);
2279 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
2280 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
2281 & MIPS16OP_MASK_RY
);
2282 if (pinfo
& MIPS16_INSN_WRITE_Z
)
2283 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RZ
)
2284 & MIPS16OP_MASK_RZ
);
2285 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
2286 mips_gprmask
|= 1 << TREG
;
2287 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
2288 mips_gprmask
|= 1 << SP
;
2289 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
2290 mips_gprmask
|= 1 << RA
;
2291 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2292 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
2293 if (pinfo
& MIPS16_INSN_READ_Z
)
2294 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
2295 & MIPS16OP_MASK_MOVE32Z
);
2296 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
2297 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
2298 & MIPS16OP_MASK_REGR32
);
2301 if (place
== NULL
&& ! mips_opts
.noreorder
)
2303 /* Filling the branch delay slot is more complex. We try to
2304 switch the branch with the previous instruction, which we can
2305 do if the previous instruction does not set up a condition
2306 that the branch tests and if the branch is not itself the
2307 target of any branch. */
2308 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2309 || (pinfo
& INSN_COND_BRANCH_DELAY
))
2311 if (mips_optimize
< 2
2312 /* If we have seen .set volatile or .set nomove, don't
2314 || mips_opts
.nomove
!= 0
2315 /* If we had to emit any NOP instructions, then we
2316 already know we can not swap. */
2318 /* If we don't even know the previous insn, we can not
2320 || ! prev_insn_valid
2321 /* If the previous insn is already in a branch delay
2322 slot, then we can not swap. */
2323 || prev_insn_is_delay_slot
2324 /* If the previous previous insn was in a .set
2325 noreorder, we can't swap. Actually, the MIPS
2326 assembler will swap in this situation. However, gcc
2327 configured -with-gnu-as will generate code like
2333 in which we can not swap the bne and INSN. If gcc is
2334 not configured -with-gnu-as, it does not output the
2335 .set pseudo-ops. We don't have to check
2336 prev_insn_unreordered, because prev_insn_valid will
2337 be 0 in that case. We don't want to use
2338 prev_prev_insn_valid, because we do want to be able
2339 to swap at the start of a function. */
2340 || prev_prev_insn_unreordered
2341 /* If the branch is itself the target of a branch, we
2342 can not swap. We cheat on this; all we check for is
2343 whether there is a label on this instruction. If
2344 there are any branches to anything other than a
2345 label, users must use .set noreorder. */
2346 || insn_labels
!= NULL
2347 /* If the previous instruction is in a variant frag, we
2348 can not do the swap. This does not apply to the
2349 mips16, which uses variant frags for different
2351 || (! mips_opts
.mips16
2352 && prev_insn_frag
->fr_type
== rs_machine_dependent
)
2353 /* If the branch reads the condition codes, we don't
2354 even try to swap, because in the sequence
2359 we can not swap, and I don't feel like handling that
2361 || (! mips_opts
.mips16
2362 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2363 && (pinfo
& INSN_READ_COND_CODE
))
2364 /* We can not swap with an instruction that requires a
2365 delay slot, becase the target of the branch might
2366 interfere with that instruction. */
2367 || (! mips_opts
.mips16
2368 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2370 /* Itbl support may require additional care here. */
2371 & (INSN_LOAD_COPROC_DELAY
2372 | INSN_COPROC_MOVE_DELAY
2373 | INSN_WRITE_COND_CODE
)))
2374 || (! (hilo_interlocks
2375 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
2379 || (! mips_opts
.mips16
2381 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))
2382 || (! mips_opts
.mips16
2383 && mips_opts
.isa
== ISA_MIPS1
2384 /* Itbl support may require additional care here. */
2385 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))
2386 /* We can not swap with a branch instruction. */
2388 & (INSN_UNCOND_BRANCH_DELAY
2389 | INSN_COND_BRANCH_DELAY
2390 | INSN_COND_BRANCH_LIKELY
))
2391 /* We do not swap with a trap instruction, since it
2392 complicates trap handlers to have the trap
2393 instruction be in a delay slot. */
2394 || (prev_pinfo
& INSN_TRAP
)
2395 /* If the branch reads a register that the previous
2396 instruction sets, we can not swap. */
2397 || (! mips_opts
.mips16
2398 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2399 && insn_uses_reg (ip
,
2400 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
2403 || (! mips_opts
.mips16
2404 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2405 && insn_uses_reg (ip
,
2406 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
2409 || (mips_opts
.mips16
2410 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
2411 && insn_uses_reg (ip
,
2412 ((prev_insn
.insn_opcode
2414 & MIPS16OP_MASK_RX
),
2416 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
2417 && insn_uses_reg (ip
,
2418 ((prev_insn
.insn_opcode
2420 & MIPS16OP_MASK_RY
),
2422 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
2423 && insn_uses_reg (ip
,
2424 ((prev_insn
.insn_opcode
2426 & MIPS16OP_MASK_RZ
),
2428 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
2429 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
2430 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2431 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
2432 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2433 && insn_uses_reg (ip
,
2434 MIPS16OP_EXTRACT_REG32R (prev_insn
.
2437 /* If the branch writes a register that the previous
2438 instruction sets, we can not swap (we know that
2439 branches write only to RD or to $31). */
2440 || (! mips_opts
.mips16
2441 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2442 && (((pinfo
& INSN_WRITE_GPR_D
)
2443 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
2444 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2445 || ((pinfo
& INSN_WRITE_GPR_31
)
2446 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
2449 || (! mips_opts
.mips16
2450 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2451 && (((pinfo
& INSN_WRITE_GPR_D
)
2452 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
2453 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2454 || ((pinfo
& INSN_WRITE_GPR_31
)
2455 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
2458 || (mips_opts
.mips16
2459 && (pinfo
& MIPS16_INSN_WRITE_31
)
2460 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2461 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2462 && (MIPS16OP_EXTRACT_REG32R (prev_insn
.insn_opcode
)
2464 /* If the branch writes a register that the previous
2465 instruction reads, we can not swap (we know that
2466 branches only write to RD or to $31). */
2467 || (! mips_opts
.mips16
2468 && (pinfo
& INSN_WRITE_GPR_D
)
2469 && insn_uses_reg (&prev_insn
,
2470 ((ip
->insn_opcode
>> OP_SH_RD
)
2473 || (! mips_opts
.mips16
2474 && (pinfo
& INSN_WRITE_GPR_31
)
2475 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
2476 || (mips_opts
.mips16
2477 && (pinfo
& MIPS16_INSN_WRITE_31
)
2478 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
2479 /* If we are generating embedded PIC code, the branch
2480 might be expanded into a sequence which uses $at, so
2481 we can't swap with an instruction which reads it. */
2482 || (mips_pic
== EMBEDDED_PIC
2483 && insn_uses_reg (&prev_insn
, AT
, MIPS_GR_REG
))
2484 /* If the previous previous instruction has a load
2485 delay, and sets a register that the branch reads, we
2487 || (! mips_opts
.mips16
2488 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2489 /* Itbl support may require additional care here. */
2490 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
2491 || (! gpr_interlocks
2492 && (prev_prev_insn
.insn_mo
->pinfo
2493 & INSN_LOAD_MEMORY_DELAY
)))
2494 && insn_uses_reg (ip
,
2495 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
2498 /* If one instruction sets a condition code and the
2499 other one uses a condition code, we can not swap. */
2500 || ((pinfo
& INSN_READ_COND_CODE
)
2501 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
2502 || ((pinfo
& INSN_WRITE_COND_CODE
)
2503 && (prev_pinfo
& INSN_READ_COND_CODE
))
2504 /* If the previous instruction uses the PC, we can not
2506 || (mips_opts
.mips16
2507 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
2508 /* If the previous instruction was extended, we can not
2510 || (mips_opts
.mips16
&& prev_insn_extended
)
2511 /* If the previous instruction had a fixup in mips16
2512 mode, we can not swap. This normally means that the
2513 previous instruction was a 4 byte branch anyhow. */
2514 || (mips_opts
.mips16
&& prev_insn_fixp
[0])
2515 /* If the previous instruction is a sync, sync.l, or
2516 sync.p, we can not swap. */
2517 || (prev_pinfo
& INSN_SYNC
))
2519 /* We could do even better for unconditional branches to
2520 portions of this object file; we could pick up the
2521 instruction at the destination, put it in the delay
2522 slot, and bump the destination address. */
2524 /* Update the previous insn information. */
2525 prev_prev_insn
= *ip
;
2526 prev_insn
.insn_mo
= &dummy_opcode
;
2530 /* It looks like we can actually do the swap. */
2531 if (! mips_opts
.mips16
)
2536 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2537 memcpy (temp
, prev_f
, 4);
2538 memcpy (prev_f
, f
, 4);
2539 memcpy (f
, temp
, 4);
2540 if (prev_insn_fixp
[0])
2542 prev_insn_fixp
[0]->fx_frag
= frag_now
;
2543 prev_insn_fixp
[0]->fx_where
= f
- frag_now
->fr_literal
;
2545 if (prev_insn_fixp
[1])
2547 prev_insn_fixp
[1]->fx_frag
= frag_now
;
2548 prev_insn_fixp
[1]->fx_where
= f
- frag_now
->fr_literal
;
2550 if (prev_insn_fixp
[2])
2552 prev_insn_fixp
[2]->fx_frag
= frag_now
;
2553 prev_insn_fixp
[2]->fx_where
= f
- frag_now
->fr_literal
;
2557 fixp
[0]->fx_frag
= prev_insn_frag
;
2558 fixp
[0]->fx_where
= prev_insn_where
;
2562 fixp
[1]->fx_frag
= prev_insn_frag
;
2563 fixp
[1]->fx_where
= prev_insn_where
;
2567 fixp
[2]->fx_frag
= prev_insn_frag
;
2568 fixp
[2]->fx_where
= prev_insn_where
;
2576 assert (prev_insn_fixp
[0] == NULL
);
2577 assert (prev_insn_fixp
[1] == NULL
);
2578 assert (prev_insn_fixp
[2] == NULL
);
2579 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2580 memcpy (temp
, prev_f
, 2);
2581 memcpy (prev_f
, f
, 2);
2582 if (*reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2584 assert (*reloc_type
== BFD_RELOC_UNUSED
);
2585 memcpy (f
, temp
, 2);
2589 memcpy (f
, f
+ 2, 2);
2590 memcpy (f
+ 2, temp
, 2);
2594 fixp
[0]->fx_frag
= prev_insn_frag
;
2595 fixp
[0]->fx_where
= prev_insn_where
;
2599 fixp
[1]->fx_frag
= prev_insn_frag
;
2600 fixp
[1]->fx_where
= prev_insn_where
;
2604 fixp
[2]->fx_frag
= prev_insn_frag
;
2605 fixp
[2]->fx_where
= prev_insn_where
;
2609 /* Update the previous insn information; leave prev_insn
2611 prev_prev_insn
= *ip
;
2613 prev_insn_is_delay_slot
= 1;
2615 /* If that was an unconditional branch, forget the previous
2616 insn information. */
2617 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2619 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2620 prev_insn
.insn_mo
= &dummy_opcode
;
2623 prev_insn_fixp
[0] = NULL
;
2624 prev_insn_fixp
[1] = NULL
;
2625 prev_insn_fixp
[2] = NULL
;
2626 prev_insn_reloc_type
[0] = BFD_RELOC_UNUSED
;
2627 prev_insn_reloc_type
[1] = BFD_RELOC_UNUSED
;
2628 prev_insn_reloc_type
[2] = BFD_RELOC_UNUSED
;
2629 prev_insn_extended
= 0;
2631 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
2633 /* We don't yet optimize a branch likely. What we should do
2634 is look at the target, copy the instruction found there
2635 into the delay slot, and increment the branch to jump to
2636 the next instruction. */
2638 /* Update the previous insn information. */
2639 prev_prev_insn
= *ip
;
2640 prev_insn
.insn_mo
= &dummy_opcode
;
2641 prev_insn_fixp
[0] = NULL
;
2642 prev_insn_fixp
[1] = NULL
;
2643 prev_insn_fixp
[2] = NULL
;
2644 prev_insn_reloc_type
[0] = BFD_RELOC_UNUSED
;
2645 prev_insn_reloc_type
[1] = BFD_RELOC_UNUSED
;
2646 prev_insn_reloc_type
[2] = BFD_RELOC_UNUSED
;
2647 prev_insn_extended
= 0;
2651 /* Update the previous insn information. */
2653 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2655 prev_prev_insn
= prev_insn
;
2658 /* Any time we see a branch, we always fill the delay slot
2659 immediately; since this insn is not a branch, we know it
2660 is not in a delay slot. */
2661 prev_insn_is_delay_slot
= 0;
2663 prev_insn_fixp
[0] = fixp
[0];
2664 prev_insn_fixp
[1] = fixp
[1];
2665 prev_insn_fixp
[2] = fixp
[2];
2666 prev_insn_reloc_type
[0] = reloc_type
[0];
2667 prev_insn_reloc_type
[1] = reloc_type
[1];
2668 prev_insn_reloc_type
[2] = reloc_type
[2];
2669 if (mips_opts
.mips16
)
2670 prev_insn_extended
= (ip
->use_extend
2671 || *reloc_type
> BFD_RELOC_UNUSED
);
2674 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2675 prev_insn_unreordered
= 0;
2676 prev_insn_frag
= frag_now
;
2677 prev_insn_where
= f
- frag_now
->fr_literal
;
2678 prev_insn_valid
= 1;
2680 else if (place
== NULL
)
2682 /* We need to record a bit of information even when we are not
2683 reordering, in order to determine the base address for mips16
2684 PC relative relocs. */
2685 prev_prev_insn
= prev_insn
;
2687 prev_insn_reloc_type
[0] = reloc_type
[0];
2688 prev_insn_reloc_type
[1] = reloc_type
[1];
2689 prev_insn_reloc_type
[2] = reloc_type
[2];
2690 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2691 prev_insn_unreordered
= 1;
2694 /* We just output an insn, so the next one doesn't have a label. */
2695 mips_clear_insn_labels ();
2697 /* We must ensure that a fixup associated with an unmatched %hi
2698 reloc does not become a variant frag. Otherwise, the
2699 rearrangement of %hi relocs in frob_file may confuse
2703 frag_wane (frag_now
);
2708 /* This function forgets that there was any previous instruction or
2709 label. If PRESERVE is non-zero, it remembers enough information to
2710 know whether nops are needed before a noreorder section. */
2713 mips_no_prev_insn (preserve
)
2718 prev_insn
.insn_mo
= &dummy_opcode
;
2719 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2720 prev_nop_frag
= NULL
;
2721 prev_nop_frag_holds
= 0;
2722 prev_nop_frag_required
= 0;
2723 prev_nop_frag_since
= 0;
2725 prev_insn_valid
= 0;
2726 prev_insn_is_delay_slot
= 0;
2727 prev_insn_unreordered
= 0;
2728 prev_insn_extended
= 0;
2729 prev_insn_reloc_type
[0] = BFD_RELOC_UNUSED
;
2730 prev_insn_reloc_type
[1] = BFD_RELOC_UNUSED
;
2731 prev_insn_reloc_type
[2] = BFD_RELOC_UNUSED
;
2732 prev_prev_insn_unreordered
= 0;
2733 mips_clear_insn_labels ();
2736 /* This function must be called whenever we turn on noreorder or emit
2737 something other than instructions. It inserts any NOPS which might
2738 be needed by the previous instruction, and clears the information
2739 kept for the previous instructions. The INSNS parameter is true if
2740 instructions are to follow. */
2743 mips_emit_delays (insns
)
2746 if (! mips_opts
.noreorder
)
2751 if ((! mips_opts
.mips16
2752 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2753 && (! cop_interlocks
2754 && (prev_insn
.insn_mo
->pinfo
2755 & (INSN_LOAD_COPROC_DELAY
2756 | INSN_COPROC_MOVE_DELAY
2757 | INSN_WRITE_COND_CODE
))))
2758 || (! hilo_interlocks
2759 && (prev_insn
.insn_mo
->pinfo
2762 || (! mips_opts
.mips16
2764 && (prev_insn
.insn_mo
->pinfo
2765 & INSN_LOAD_MEMORY_DELAY
))
2766 || (! mips_opts
.mips16
2767 && mips_opts
.isa
== ISA_MIPS1
2768 && (prev_insn
.insn_mo
->pinfo
2769 & INSN_COPROC_MEMORY_DELAY
)))
2771 /* Itbl support may require additional care here. */
2773 if ((! mips_opts
.mips16
2774 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2775 && (! cop_interlocks
2776 && prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2777 || (! hilo_interlocks
2778 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2779 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2782 if (prev_insn_unreordered
)
2785 else if ((! mips_opts
.mips16
2786 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2787 && (! cop_interlocks
2788 && prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2789 || (! hilo_interlocks
2790 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2791 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2793 /* Itbl support may require additional care here. */
2794 if (! prev_prev_insn_unreordered
)
2800 struct insn_label_list
*l
;
2804 /* Record the frag which holds the nop instructions, so
2805 that we can remove them if we don't need them. */
2806 frag_grow (mips_opts
.mips16
? nops
* 2 : nops
* 4);
2807 prev_nop_frag
= frag_now
;
2808 prev_nop_frag_holds
= nops
;
2809 prev_nop_frag_required
= 0;
2810 prev_nop_frag_since
= 0;
2813 for (; nops
> 0; --nops
)
2818 /* Move on to a new frag, so that it is safe to simply
2819 decrease the size of prev_nop_frag. */
2820 frag_wane (frag_now
);
2824 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2828 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2829 symbol_set_frag (l
->label
, frag_now
);
2830 val
= (valueT
) frag_now_fix ();
2831 /* mips16 text labels are stored as odd. */
2832 if (mips_opts
.mips16
)
2834 S_SET_VALUE (l
->label
, val
);
2839 /* Mark instruction labels in mips16 mode. */
2841 mips16_mark_labels ();
2843 mips_no_prev_insn (insns
);
2846 /* Build an instruction created by a macro expansion. This is passed
2847 a pointer to the count of instructions created so far, an
2848 expression, the name of the instruction to build, an operand format
2849 string, and corresponding arguments. */
2853 macro_build (char *place
,
2861 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
2870 struct mips_cl_insn insn
;
2871 bfd_reloc_code_real_type r
[3];
2875 va_start (args
, fmt
);
2881 * If the macro is about to expand into a second instruction,
2882 * print a warning if needed. We need to pass ip as a parameter
2883 * to generate a better warning message here...
2885 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
2886 as_warn (_("Macro instruction expanded into multiple instructions"));
2889 * If the macro is about to expand into a second instruction,
2890 * and it is in a delay slot, print a warning.
2894 && mips_opts
.noreorder
2895 && (prev_prev_insn
.insn_mo
->pinfo
2896 & (INSN_UNCOND_BRANCH_DELAY
| INSN_COND_BRANCH_DELAY
2897 | INSN_COND_BRANCH_LIKELY
)) != 0)
2898 as_warn (_("Macro instruction expanded into multiple instructions in a branch delay slot"));
2901 ++*counter
; /* bump instruction counter */
2903 if (mips_opts
.mips16
)
2905 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
);
2910 r
[0] = BFD_RELOC_UNUSED
;
2911 r
[1] = BFD_RELOC_UNUSED
;
2912 r
[2] = BFD_RELOC_UNUSED
;
2913 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2914 assert (insn
.insn_mo
);
2915 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2917 /* Search until we get a match for NAME. */
2920 /* It is assumed here that macros will never generate
2921 MIPS-3D instructions. */
2922 if (strcmp (fmt
, insn
.insn_mo
->args
) == 0
2923 && insn
.insn_mo
->pinfo
!= INSN_MACRO
2924 && OPCODE_IS_MEMBER (insn
.insn_mo
, mips_opts
.isa
, mips_arch
)
2925 && (mips_arch
!= CPU_R4650
|| (insn
.insn_mo
->pinfo
& FP_D
) == 0))
2929 assert (insn
.insn_mo
->name
);
2930 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2933 insn
.insn_opcode
= insn
.insn_mo
->match
;
2949 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RT
;
2953 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE
;
2958 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FT
;
2963 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RD
;
2968 int tmp
= va_arg (args
, int);
2970 insn
.insn_opcode
|= tmp
<< OP_SH_RT
;
2971 insn
.insn_opcode
|= tmp
<< OP_SH_RD
;
2977 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FS
;
2984 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_SHAMT
;
2988 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FD
;
2992 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE20
;
2996 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE19
;
3000 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE2
;
3007 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RS
;
3013 *r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
3014 assert (*r
== BFD_RELOC_GPREL16
3015 || *r
== BFD_RELOC_MIPS_LITERAL
3016 || *r
== BFD_RELOC_MIPS_HIGHER
3017 || *r
== BFD_RELOC_HI16_S
3018 || *r
== BFD_RELOC_LO16
3019 || *r
== BFD_RELOC_MIPS_GOT16
3020 || *r
== BFD_RELOC_MIPS_CALL16
3021 || *r
== BFD_RELOC_MIPS_GOT_DISP
3022 || *r
== BFD_RELOC_MIPS_GOT_PAGE
3023 || *r
== BFD_RELOC_MIPS_GOT_OFST
3024 || *r
== BFD_RELOC_MIPS_GOT_LO16
3025 || *r
== BFD_RELOC_MIPS_CALL_LO16
3026 || (ep
->X_op
== O_subtract
3027 && *r
== BFD_RELOC_PCREL_LO16
));
3031 *r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
3033 && (ep
->X_op
== O_constant
3034 || (ep
->X_op
== O_symbol
3035 && (*r
== BFD_RELOC_MIPS_HIGHEST
3036 || *r
== BFD_RELOC_HI16_S
3037 || *r
== BFD_RELOC_HI16
3038 || *r
== BFD_RELOC_GPREL16
3039 || *r
== BFD_RELOC_MIPS_GOT_HI16
3040 || *r
== BFD_RELOC_MIPS_CALL_HI16
))
3041 || (ep
->X_op
== O_subtract
3042 && *r
== BFD_RELOC_PCREL_HI16_S
)));
3046 assert (ep
!= NULL
);
3048 * This allows macro() to pass an immediate expression for
3049 * creating short branches without creating a symbol.
3050 * Note that the expression still might come from the assembly
3051 * input, in which case the value is not checked for range nor
3052 * is a relocation entry generated (yuck).
3054 if (ep
->X_op
== O_constant
)
3056 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
3060 if (mips_pic
== EMBEDDED_PIC
)
3061 *r
= BFD_RELOC_16_PCREL_S2
;
3063 *r
= BFD_RELOC_16_PCREL
;
3067 assert (ep
!= NULL
);
3068 *r
= BFD_RELOC_MIPS_JMP
;
3072 insn
.insn_opcode
|= va_arg (args
, unsigned long);
3081 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3083 append_insn (place
, &insn
, ep
, r
, false);
3087 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
)
3089 int *counter ATTRIBUTE_UNUSED
;
3095 struct mips_cl_insn insn
;
3096 bfd_reloc_code_real_type r
[3]
3097 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3099 insn
.insn_mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
3100 assert (insn
.insn_mo
);
3101 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3103 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
3104 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
3107 assert (insn
.insn_mo
->name
);
3108 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3111 insn
.insn_opcode
= insn
.insn_mo
->match
;
3112 insn
.use_extend
= false;
3131 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RY
;
3136 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RX
;
3140 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RZ
;
3144 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_MOVE32Z
;
3154 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_REGR32
;
3161 regno
= va_arg (args
, int);
3162 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
3163 insn
.insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
3184 assert (ep
!= NULL
);
3186 if (ep
->X_op
!= O_constant
)
3187 *r
= (int) BFD_RELOC_UNUSED
+ c
;
3190 mips16_immed (NULL
, 0, c
, ep
->X_add_number
, false, false,
3191 false, &insn
.insn_opcode
, &insn
.use_extend
,
3194 *r
= BFD_RELOC_UNUSED
;
3200 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_IMM6
;
3207 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3209 append_insn (place
, &insn
, ep
, r
, false);
3213 * Generate a "jalr" instruction with a relocation hint to the called
3214 * function. This occurs in NewABI PIC code.
3217 macro_build_jalr (icnt
, ep
)
3223 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr", "d,s",
3226 fix_new_exp (frag_now
, 0, 0, ep
, false, BFD_RELOC_MIPS_JALR
);
3230 * Generate a "lui" instruction.
3233 macro_build_lui (place
, counter
, ep
, regnum
)
3239 expressionS high_expr
;
3240 struct mips_cl_insn insn
;
3241 bfd_reloc_code_real_type r
[3]
3242 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3243 CONST
char *name
= "lui";
3244 CONST
char *fmt
= "t,u";
3246 assert (! mips_opts
.mips16
);
3252 high_expr
.X_op
= O_constant
;
3253 high_expr
.X_add_number
= ep
->X_add_number
;
3256 if (high_expr
.X_op
== O_constant
)
3258 /* we can compute the instruction now without a relocation entry */
3259 high_expr
.X_add_number
= ((high_expr
.X_add_number
+ 0x8000)
3261 *r
= BFD_RELOC_UNUSED
;
3263 else if (! HAVE_NEWABI
)
3265 assert (ep
->X_op
== O_symbol
);
3266 /* _gp_disp is a special case, used from s_cpload. */
3267 assert (mips_pic
== NO_PIC
3268 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
3269 *r
= BFD_RELOC_HI16_S
;
3273 * If the macro is about to expand into a second instruction,
3274 * print a warning if needed. We need to pass ip as a parameter
3275 * to generate a better warning message here...
3277 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
3278 as_warn (_("Macro instruction expanded into multiple instructions"));
3281 ++*counter
; /* bump instruction counter */
3283 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
3284 assert (insn
.insn_mo
);
3285 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3286 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
3288 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
3289 if (*r
== BFD_RELOC_UNUSED
)
3291 insn
.insn_opcode
|= high_expr
.X_add_number
;
3292 append_insn (place
, &insn
, NULL
, r
, false);
3295 append_insn (place
, &insn
, &high_expr
, r
, false);
3299 * Generates code to set the $at register to true (one)
3300 * if reg is less than the immediate expression.
3303 set_at (counter
, reg
, unsignedp
)
3308 if (imm_expr
.X_op
== O_constant
3309 && imm_expr
.X_add_number
>= -0x8000
3310 && imm_expr
.X_add_number
< 0x8000)
3311 macro_build ((char *) NULL
, counter
, &imm_expr
,
3312 unsignedp
? "sltiu" : "slti",
3313 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
3316 load_register (counter
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
3317 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3318 unsignedp
? "sltu" : "slt",
3319 "d,v,t", AT
, reg
, AT
);
3323 /* Warn if an expression is not a constant. */
3326 check_absolute_expr (ip
, ex
)
3327 struct mips_cl_insn
*ip
;
3330 if (ex
->X_op
== O_big
)
3331 as_bad (_("unsupported large constant"));
3332 else if (ex
->X_op
!= O_constant
)
3333 as_bad (_("Instruction %s requires absolute expression"), ip
->insn_mo
->name
);
3336 /* Count the leading zeroes by performing a binary chop. This is a
3337 bulky bit of source, but performance is a LOT better for the
3338 majority of values than a simple loop to count the bits:
3339 for (lcnt = 0; (lcnt < 32); lcnt++)
3340 if ((v) & (1 << (31 - lcnt)))
3342 However it is not code size friendly, and the gain will drop a bit
3343 on certain cached systems.
3345 #define COUNT_TOP_ZEROES(v) \
3346 (((v) & ~0xffff) == 0 \
3347 ? ((v) & ~0xff) == 0 \
3348 ? ((v) & ~0xf) == 0 \
3349 ? ((v) & ~0x3) == 0 \
3350 ? ((v) & ~0x1) == 0 \
3355 : ((v) & ~0x7) == 0 \
3358 : ((v) & ~0x3f) == 0 \
3359 ? ((v) & ~0x1f) == 0 \
3362 : ((v) & ~0x7f) == 0 \
3365 : ((v) & ~0xfff) == 0 \
3366 ? ((v) & ~0x3ff) == 0 \
3367 ? ((v) & ~0x1ff) == 0 \
3370 : ((v) & ~0x7ff) == 0 \
3373 : ((v) & ~0x3fff) == 0 \
3374 ? ((v) & ~0x1fff) == 0 \
3377 : ((v) & ~0x7fff) == 0 \
3380 : ((v) & ~0xffffff) == 0 \
3381 ? ((v) & ~0xfffff) == 0 \
3382 ? ((v) & ~0x3ffff) == 0 \
3383 ? ((v) & ~0x1ffff) == 0 \
3386 : ((v) & ~0x7ffff) == 0 \
3389 : ((v) & ~0x3fffff) == 0 \
3390 ? ((v) & ~0x1fffff) == 0 \
3393 : ((v) & ~0x7fffff) == 0 \
3396 : ((v) & ~0xfffffff) == 0 \
3397 ? ((v) & ~0x3ffffff) == 0 \
3398 ? ((v) & ~0x1ffffff) == 0 \
3401 : ((v) & ~0x7ffffff) == 0 \
3404 : ((v) & ~0x3fffffff) == 0 \
3405 ? ((v) & ~0x1fffffff) == 0 \
3408 : ((v) & ~0x7fffffff) == 0 \
3412 /* Is the given value a sign-extended 32-bit value? */
3413 #define IS_SEXT_32BIT_NUM(x) \
3414 (((x) &~ (offsetT) 0x7fffffff) == 0 \
3415 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
3418 * This routine generates the least number of instructions neccessary to load
3419 * an absolute expression value into a register.
3422 load_register (counter
, reg
, ep
, dbl
)
3429 expressionS hi32
, lo32
;
3431 if (ep
->X_op
!= O_big
)
3433 assert (ep
->X_op
== O_constant
);
3434 if (ep
->X_add_number
< 0x8000
3435 && (ep
->X_add_number
>= 0
3436 || (ep
->X_add_number
>= -0x8000
3439 || sizeof (ep
->X_add_number
) > 4))))
3441 /* We can handle 16 bit signed values with an addiu to
3442 $zero. No need to ever use daddiu here, since $zero and
3443 the result are always correct in 32 bit mode. */
3444 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
3445 (int) BFD_RELOC_LO16
);
3448 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
3450 /* We can handle 16 bit unsigned values with an ori to
3452 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
3453 (int) BFD_RELOC_LO16
);
3456 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)
3459 || sizeof (ep
->X_add_number
) > 4
3460 || (ep
->X_add_number
& 0x80000000) == 0))
3461 || ((HAVE_32BIT_GPRS
|| ! dbl
)
3462 && (ep
->X_add_number
&~ (offsetT
) 0xffffffff) == 0)
3465 && ((ep
->X_add_number
&~ (offsetT
) 0xffffffff)
3466 == ~ (offsetT
) 0xffffffff)))
3468 /* 32 bit values require an lui. */
3469 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
3470 (int) BFD_RELOC_HI16
);
3471 if ((ep
->X_add_number
& 0xffff) != 0)
3472 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
3473 (int) BFD_RELOC_LO16
);
3478 /* The value is larger than 32 bits. */
3480 if (HAVE_32BIT_GPRS
)
3482 as_bad (_("Number (0x%lx) larger than 32 bits"),
3483 (unsigned long) ep
->X_add_number
);
3484 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
3485 (int) BFD_RELOC_LO16
);
3489 if (ep
->X_op
!= O_big
)
3492 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3493 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3494 hi32
.X_add_number
&= 0xffffffff;
3496 lo32
.X_add_number
&= 0xffffffff;
3500 assert (ep
->X_add_number
> 2);
3501 if (ep
->X_add_number
== 3)
3502 generic_bignum
[3] = 0;
3503 else if (ep
->X_add_number
> 4)
3504 as_bad (_("Number larger than 64 bits"));
3505 lo32
.X_op
= O_constant
;
3506 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
3507 hi32
.X_op
= O_constant
;
3508 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
3511 if (hi32
.X_add_number
== 0)
3516 unsigned long hi
, lo
;
3518 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
3520 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
3522 macro_build ((char *) NULL
, counter
, &lo32
, "addiu", "t,r,j",
3523 reg
, 0, (int) BFD_RELOC_LO16
);
3526 if (lo32
.X_add_number
& 0x80000000)
3528 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3529 (int) BFD_RELOC_HI16
);
3530 if (lo32
.X_add_number
& 0xffff)
3531 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i",
3532 reg
, reg
, (int) BFD_RELOC_LO16
);
3537 /* Check for 16bit shifted constant. We know that hi32 is
3538 non-zero, so start the mask on the first bit of the hi32
3543 unsigned long himask
, lomask
;
3547 himask
= 0xffff >> (32 - shift
);
3548 lomask
= (0xffff << shift
) & 0xffffffff;
3552 himask
= 0xffff << (shift
- 32);
3555 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
3556 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
3560 tmp
.X_op
= O_constant
;
3562 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
3563 | (lo32
.X_add_number
>> shift
));
3565 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
3566 macro_build ((char *) NULL
, counter
, &tmp
,
3567 "ori", "t,r,i", reg
, 0,
3568 (int) BFD_RELOC_LO16
);
3569 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3570 (shift
>= 32) ? "dsll32" : "dsll",
3572 (shift
>= 32) ? shift
- 32 : shift
);
3577 while (shift
<= (64 - 16));
3579 /* Find the bit number of the lowest one bit, and store the
3580 shifted value in hi/lo. */
3581 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
3582 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
3586 while ((lo
& 1) == 0)
3591 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
3597 while ((hi
& 1) == 0)
3606 /* Optimize if the shifted value is a (power of 2) - 1. */
3607 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
3608 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
3610 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
3615 /* This instruction will set the register to be all
3617 tmp
.X_op
= O_constant
;
3618 tmp
.X_add_number
= (offsetT
) -1;
3619 macro_build ((char *) NULL
, counter
, &tmp
, "addiu", "t,r,j",
3620 reg
, 0, (int) BFD_RELOC_LO16
);
3624 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3625 (bit
>= 32) ? "dsll32" : "dsll",
3627 (bit
>= 32) ? bit
- 32 : bit
);
3629 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3630 (shift
>= 32) ? "dsrl32" : "dsrl",
3632 (shift
>= 32) ? shift
- 32 : shift
);
3637 /* Sign extend hi32 before calling load_register, because we can
3638 generally get better code when we load a sign extended value. */
3639 if ((hi32
.X_add_number
& 0x80000000) != 0)
3640 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
3641 load_register (counter
, reg
, &hi32
, 0);
3644 if ((lo32
.X_add_number
& 0xffff0000) == 0)
3648 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3649 "dsll32", "d,w,<", reg
, freg
, 0);
3657 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
3659 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3660 (int) BFD_RELOC_HI16
);
3661 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3662 "dsrl32", "d,w,<", reg
, reg
, 0);
3668 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "dsll",
3669 "d,w,<", reg
, freg
, 16);
3673 mid16
.X_add_number
>>= 16;
3674 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
3675 freg
, (int) BFD_RELOC_LO16
);
3676 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "dsll",
3677 "d,w,<", reg
, reg
, 16);
3680 if ((lo32
.X_add_number
& 0xffff) != 0)
3681 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, freg
,
3682 (int) BFD_RELOC_LO16
);
3685 /* Load an address into a register. */
3688 load_address (counter
, reg
, ep
, used_at
)
3696 if (ep
->X_op
!= O_constant
3697 && ep
->X_op
!= O_symbol
)
3699 as_bad (_("expression too complex"));
3700 ep
->X_op
= O_constant
;
3703 if (ep
->X_op
== O_constant
)
3705 load_register (counter
, reg
, ep
, HAVE_64BIT_ADDRESSES
);
3709 if (mips_pic
== NO_PIC
)
3711 /* If this is a reference to a GP relative symbol, we want
3712 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3714 lui $reg,<sym> (BFD_RELOC_HI16_S)
3715 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3716 If we have an addend, we always use the latter form.
3718 With 64bit address space and a usable $at we want
3719 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3720 lui $at,<sym> (BFD_RELOC_HI16_S)
3721 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3722 daddiu $at,<sym> (BFD_RELOC_LO16)
3726 If $at is already in use, we use an path which is suboptimal
3727 on superscalar processors.
3728 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3729 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3731 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
3733 daddiu $reg,<sym> (BFD_RELOC_LO16)
3735 if (HAVE_64BIT_ADDRESSES
)
3737 /* We don't do GP optimization for now because RELAX_ENCODE can't
3738 hold the data for such large chunks. */
3742 macro_build (p
, counter
, ep
, "lui", "t,u",
3743 reg
, (int) BFD_RELOC_MIPS_HIGHEST
);
3744 macro_build (p
, counter
, ep
, "lui", "t,u",
3745 AT
, (int) BFD_RELOC_HI16_S
);
3746 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3747 reg
, reg
, (int) BFD_RELOC_MIPS_HIGHER
);
3748 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3749 AT
, AT
, (int) BFD_RELOC_LO16
);
3750 macro_build (p
, counter
, (expressionS
*) NULL
, "dsll32",
3751 "d,w,<", reg
, reg
, 0);
3752 macro_build (p
, counter
, (expressionS
*) NULL
, "dadd",
3753 "d,v,t", reg
, reg
, AT
);
3758 macro_build (p
, counter
, ep
, "lui", "t,u",
3759 reg
, (int) BFD_RELOC_MIPS_HIGHEST
);
3760 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3761 reg
, reg
, (int) BFD_RELOC_MIPS_HIGHER
);
3762 macro_build (p
, counter
, (expressionS
*) NULL
, "dsll",
3763 "d,w,<", reg
, reg
, 16);
3764 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3765 reg
, reg
, (int) BFD_RELOC_HI16_S
);
3766 macro_build (p
, counter
, (expressionS
*) NULL
, "dsll",
3767 "d,w,<", reg
, reg
, 16);
3768 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3769 reg
, reg
, (int) BFD_RELOC_LO16
);
3774 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
3775 && ! nopic_need_relax (ep
->X_add_symbol
, 1))
3778 macro_build ((char *) NULL
, counter
, ep
,
3779 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu", "t,r,j",
3780 reg
, mips_gp_register
, (int) BFD_RELOC_GPREL16
);
3781 p
= frag_var (rs_machine_dependent
, 8, 0,
3782 RELAX_ENCODE (4, 8, 0, 4, 0,
3783 mips_opts
.warn_about_macros
),
3784 ep
->X_add_symbol
, 0, NULL
);
3786 macro_build_lui (p
, counter
, ep
, reg
);
3789 macro_build (p
, counter
, ep
,
3790 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3791 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3794 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3798 /* If this is a reference to an external symbol, we want
3799 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3801 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3803 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3804 If there is a constant, it must be added in after. */
3805 ex
.X_add_number
= ep
->X_add_number
;
3806 ep
->X_add_number
= 0;
3808 macro_build ((char *) NULL
, counter
, ep
,
3809 HAVE_32BIT_ADDRESSES
? "lw" : "ld", "t,o(b)",
3810 reg
, (int) BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
3811 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
3812 p
= frag_var (rs_machine_dependent
, 4, 0,
3813 RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts
.warn_about_macros
),
3814 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3815 macro_build (p
, counter
, ep
,
3816 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3817 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3818 if (ex
.X_add_number
!= 0)
3820 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3821 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3822 ex
.X_op
= O_constant
;
3823 macro_build ((char *) NULL
, counter
, &ex
,
3824 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3825 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3828 else if (mips_pic
== SVR4_PIC
)
3833 /* This is the large GOT case. If this is a reference to an
3834 external symbol, we want
3835 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3837 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3838 Otherwise, for a reference to a local symbol, we want
3839 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3841 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3842 If we have NewABI, we want
3843 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
3844 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
3845 If there is a constant, it must be added in after. */
3846 ex
.X_add_number
= ep
->X_add_number
;
3847 ep
->X_add_number
= 0;
3850 macro_build ((char *) NULL
, counter
, ep
,
3851 HAVE_32BIT_ADDRESSES
? "lw" : "ld", "t,o(b)", reg
,
3852 (int) BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
3853 macro_build (p
, counter
, ep
,
3854 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu", "t,r,j",
3855 reg
, reg
, (int) BFD_RELOC_MIPS_GOT_OFST
);
3859 if (reg_needs_delay (mips_gp_register
))
3864 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
3865 (int) BFD_RELOC_MIPS_GOT_HI16
);
3866 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3867 HAVE_32BIT_ADDRESSES
? "addu" : "daddu", "d,v,t", reg
,
3868 reg
, mips_gp_register
);
3869 macro_build ((char *) NULL
, counter
, ep
,
3870 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
3871 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT_LO16
, reg
);
3872 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
3873 RELAX_ENCODE (12, 12 + off
, off
, 8 + off
, 0,
3874 mips_opts
.warn_about_macros
),
3875 ep
->X_add_symbol
, 0, NULL
);
3878 /* We need a nop before loading from $gp. This special
3879 check is required because the lui which starts the main
3880 instruction stream does not refer to $gp, and so will not
3881 insert the nop which may be required. */
3882 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3885 macro_build (p
, counter
, ep
,
3886 HAVE_32BIT_ADDRESSES
? "lw" : "ld", "t,o(b)", reg
,
3887 (int) BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
3889 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3891 macro_build (p
, counter
, ep
,
3892 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3893 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3896 if (ex
.X_add_number
!= 0)
3898 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3899 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3900 ex
.X_op
= O_constant
;
3901 macro_build ((char *) NULL
, counter
, &ex
,
3902 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3903 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3906 else if (mips_pic
== EMBEDDED_PIC
)
3909 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3911 macro_build ((char *) NULL
, counter
, ep
,
3912 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3913 "t,r,j", reg
, mips_gp_register
, (int) BFD_RELOC_GPREL16
);
3919 /* Move the contents of register SOURCE into register DEST. */
3922 move_register (counter
, dest
, source
)
3927 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3928 HAVE_32BIT_GPRS
? "addu" : "daddu",
3929 "d,v,t", dest
, source
, 0);
3934 * This routine implements the seemingly endless macro or synthesized
3935 * instructions and addressing modes in the mips assembly language. Many
3936 * of these macros are simple and are similar to each other. These could
3937 * probably be handled by some kind of table or grammer aproach instead of
3938 * this verbose method. Others are not simple macros but are more like
3939 * optimizing code generation.
3940 * One interesting optimization is when several store macros appear
3941 * consecutivly that would load AT with the upper half of the same address.
3942 * The ensuing load upper instructions are ommited. This implies some kind
3943 * of global optimization. We currently only optimize within a single macro.
3944 * For many of the load and store macros if the address is specified as a
3945 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
3946 * first load register 'at' with zero and use it as the base register. The
3947 * mips assembler simply uses register $zero. Just one tiny optimization
3952 struct mips_cl_insn
*ip
;
3954 register int treg
, sreg
, dreg
, breg
;
3970 bfd_reloc_code_real_type r
;
3971 int hold_mips_optimize
;
3973 assert (! mips_opts
.mips16
);
3975 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
3976 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
3977 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
3978 mask
= ip
->insn_mo
->mask
;
3980 expr1
.X_op
= O_constant
;
3981 expr1
.X_op_symbol
= NULL
;
3982 expr1
.X_add_symbol
= NULL
;
3983 expr1
.X_add_number
= 1;
3995 mips_emit_delays (true);
3996 ++mips_opts
.noreorder
;
3997 mips_any_noreorder
= 1;
3999 expr1
.X_add_number
= 8;
4000 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
4002 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "",
4005 move_register (&icnt
, dreg
, sreg
);
4006 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4007 dbl
? "dsub" : "sub", "d,v,t", dreg
, 0, sreg
);
4009 --mips_opts
.noreorder
;
4030 if (imm_expr
.X_op
== O_constant
4031 && imm_expr
.X_add_number
>= -0x8000
4032 && imm_expr
.X_add_number
< 0x8000)
4034 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
4035 (int) BFD_RELOC_LO16
);
4038 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4039 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s2
, "d,v,t",
4059 if (imm_expr
.X_op
== O_constant
4060 && imm_expr
.X_add_number
>= 0
4061 && imm_expr
.X_add_number
< 0x10000)
4063 if (mask
!= M_NOR_I
)
4064 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
4065 sreg
, (int) BFD_RELOC_LO16
);
4068 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
4069 treg
, sreg
, (int) BFD_RELOC_LO16
);
4070 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nor",
4071 "d,v,t", treg
, treg
, 0);
4076 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4077 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s2
, "d,v,t",
4095 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4097 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
4101 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4102 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
4110 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4111 likely
? "bgezl" : "bgez", "s,p", sreg
);
4116 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4117 likely
? "blezl" : "blez", "s,p", treg
);
4120 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "slt", "d,v,t",
4122 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4123 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4129 /* check for > max integer */
4130 maxnum
= 0x7fffffff;
4131 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4138 if (imm_expr
.X_op
== O_constant
4139 && imm_expr
.X_add_number
>= maxnum
4140 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4143 /* result is always false */
4147 as_warn (_("Branch %s is always false (nop)"),
4149 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop",
4155 as_warn (_("Branch likely %s is always false"),
4157 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
4162 if (imm_expr
.X_op
!= O_constant
)
4163 as_bad (_("Unsupported large constant"));
4164 ++imm_expr
.X_add_number
;
4168 if (mask
== M_BGEL_I
)
4170 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4172 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4173 likely
? "bgezl" : "bgez", "s,p", sreg
);
4176 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4178 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4179 likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4182 maxnum
= 0x7fffffff;
4183 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4190 maxnum
= - maxnum
- 1;
4191 if (imm_expr
.X_op
== O_constant
4192 && imm_expr
.X_add_number
<= maxnum
4193 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4196 /* result is always true */
4197 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
4198 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
4201 set_at (&icnt
, sreg
, 0);
4202 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4203 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4213 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4214 likely
? "beql" : "beq", "s,t,p", 0, treg
);
4217 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
4218 "d,v,t", AT
, sreg
, treg
);
4219 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4220 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4228 && imm_expr
.X_op
== O_constant
4229 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4231 if (imm_expr
.X_op
!= O_constant
)
4232 as_bad (_("Unsupported large constant"));
4233 ++imm_expr
.X_add_number
;
4237 if (mask
== M_BGEUL_I
)
4239 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4241 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4243 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4244 likely
? "bnel" : "bne", "s,t,p", sreg
, 0);
4247 set_at (&icnt
, sreg
, 1);
4248 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4249 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4257 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4258 likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4263 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4264 likely
? "bltzl" : "bltz", "s,p", treg
);
4267 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "slt", "d,v,t",
4269 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4270 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4278 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4279 likely
? "bnel" : "bne", "s,t,p", sreg
, 0);
4284 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
4285 "d,v,t", AT
, treg
, sreg
);
4286 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4287 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4295 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4296 likely
? "blezl" : "blez", "s,p", sreg
);
4301 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4302 likely
? "bgezl" : "bgez", "s,p", treg
);
4305 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "slt", "d,v,t",
4307 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4308 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4314 maxnum
= 0x7fffffff;
4315 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4322 if (imm_expr
.X_op
== O_constant
4323 && imm_expr
.X_add_number
>= maxnum
4324 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4326 if (imm_expr
.X_op
!= O_constant
)
4327 as_bad (_("Unsupported large constant"));
4328 ++imm_expr
.X_add_number
;
4332 if (mask
== M_BLTL_I
)
4334 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4336 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4337 likely
? "bltzl" : "bltz", "s,p", sreg
);
4340 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4342 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4343 likely
? "blezl" : "blez", "s,p", sreg
);
4346 set_at (&icnt
, sreg
, 0);
4347 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4348 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4356 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4357 likely
? "beql" : "beq", "s,t,p", sreg
, 0);
4362 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
4363 "d,v,t", AT
, treg
, sreg
);
4364 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4365 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4373 && imm_expr
.X_op
== O_constant
4374 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4376 if (imm_expr
.X_op
!= O_constant
)
4377 as_bad (_("Unsupported large constant"));
4378 ++imm_expr
.X_add_number
;
4382 if (mask
== M_BLTUL_I
)
4384 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4386 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4388 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4389 likely
? "beql" : "beq",
4393 set_at (&icnt
, sreg
, 1);
4394 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4395 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4403 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4404 likely
? "bltzl" : "bltz", "s,p", sreg
);
4409 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4410 likely
? "bgtzl" : "bgtz", "s,p", treg
);
4413 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "slt", "d,v,t",
4415 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4416 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4426 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4427 likely
? "bnel" : "bne", "s,t,p", 0, treg
);
4430 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
4433 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4434 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4449 as_warn (_("Divide by zero."));
4451 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "teq",
4454 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
4459 mips_emit_delays (true);
4460 ++mips_opts
.noreorder
;
4461 mips_any_noreorder
= 1;
4464 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "teq",
4466 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4467 dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
4471 expr1
.X_add_number
= 8;
4472 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
4473 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4474 dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
4475 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
4478 expr1
.X_add_number
= -1;
4479 macro_build ((char *) NULL
, &icnt
, &expr1
,
4480 dbl
? "daddiu" : "addiu",
4481 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
4482 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
4483 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
4486 expr1
.X_add_number
= 1;
4487 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
4488 (int) BFD_RELOC_LO16
);
4489 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsll32",
4490 "d,w,<", AT
, AT
, 31);
4494 expr1
.X_add_number
= 0x80000000;
4495 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
4496 (int) BFD_RELOC_HI16
);
4500 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "teq",
4502 /* We want to close the noreorder block as soon as possible, so
4503 that later insns are available for delay slot filling. */
4504 --mips_opts
.noreorder
;
4508 expr1
.X_add_number
= 8;
4509 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
4510 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "",
4513 /* We want to close the noreorder block as soon as possible, so
4514 that later insns are available for delay slot filling. */
4515 --mips_opts
.noreorder
;
4517 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
4520 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d", dreg
);
4559 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4561 as_warn (_("Divide by zero."));
4563 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "teq",
4566 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
4570 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4572 if (strcmp (s2
, "mflo") == 0)
4573 move_register (&icnt
, dreg
, sreg
);
4575 move_register (&icnt
, dreg
, 0);
4578 if (imm_expr
.X_op
== O_constant
4579 && imm_expr
.X_add_number
== -1
4580 && s
[strlen (s
) - 1] != 'u')
4582 if (strcmp (s2
, "mflo") == 0)
4584 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4585 dbl
? "dneg" : "neg", "d,w", dreg
, sreg
);
4588 move_register (&icnt
, dreg
, 0);
4592 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4593 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "z,s,t",
4595 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s2
, "d", dreg
);
4614 mips_emit_delays (true);
4615 ++mips_opts
.noreorder
;
4616 mips_any_noreorder
= 1;
4619 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "teq",
4621 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "z,s,t",
4623 /* We want to close the noreorder block as soon as possible, so
4624 that later insns are available for delay slot filling. */
4625 --mips_opts
.noreorder
;
4629 expr1
.X_add_number
= 8;
4630 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
4631 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "z,s,t",
4634 /* We want to close the noreorder block as soon as possible, so
4635 that later insns are available for delay slot filling. */
4636 --mips_opts
.noreorder
;
4637 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
4640 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s2
, "d", dreg
);
4646 /* Load the address of a symbol into a register. If breg is not
4647 zero, we then add a base register to it. */
4649 if (dbl
&& HAVE_32BIT_GPRS
)
4650 as_warn (_("dla used to load 32-bit register"));
4652 if (! dbl
&& HAVE_64BIT_OBJECTS
)
4653 as_warn (_("la used to load 64-bit address"));
4666 /* When generating embedded PIC code, we permit expressions of
4669 la $treg,foo-bar($breg)
4670 where bar is an address in the current section. These are used
4671 when getting the addresses of functions. We don't permit
4672 X_add_number to be non-zero, because if the symbol is
4673 external the relaxing code needs to know that any addend is
4674 purely the offset to X_op_symbol. */
4675 if (mips_pic
== EMBEDDED_PIC
4676 && offset_expr
.X_op
== O_subtract
4677 && (symbol_constant_p (offset_expr
.X_op_symbol
)
4678 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == now_seg
4679 : (symbol_equated_p (offset_expr
.X_op_symbol
)
4681 (symbol_get_value_expression (offset_expr
.X_op_symbol
)
4684 && (offset_expr
.X_add_number
== 0
4685 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
))
4691 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4692 tempreg
, (int) BFD_RELOC_PCREL_HI16_S
);
4696 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4697 tempreg
, (int) BFD_RELOC_PCREL_HI16_S
);
4698 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4699 (dbl
|| HAVE_64BIT_ADDRESSES
) ? "daddu" : "addu",
4700 "d,v,t", tempreg
, tempreg
, breg
);
4702 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4703 (dbl
|| HAVE_64BIT_ADDRESSES
) ? "daddiu" : "addiu",
4704 "t,r,j", treg
, tempreg
, (int) BFD_RELOC_PCREL_LO16
);
4710 if (offset_expr
.X_op
!= O_symbol
4711 && offset_expr
.X_op
!= O_constant
)
4713 as_bad (_("expression too complex"));
4714 offset_expr
.X_op
= O_constant
;
4717 if (offset_expr
.X_op
== O_constant
)
4718 load_register (&icnt
, tempreg
, &offset_expr
,
4719 ((mips_pic
== EMBEDDED_PIC
|| mips_pic
== NO_PIC
)
4720 ? (dbl
|| HAVE_64BIT_ADDRESSES
)
4721 : HAVE_64BIT_ADDRESSES
));
4722 else if (mips_pic
== NO_PIC
)
4724 /* If this is a reference to a GP relative symbol, we want
4725 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
4727 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4728 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4729 If we have a constant, we need two instructions anyhow,
4730 so we may as well always use the latter form.
4732 With 64bit address space and a usable $at we want
4733 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4734 lui $at,<sym> (BFD_RELOC_HI16_S)
4735 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4736 daddiu $at,<sym> (BFD_RELOC_LO16)
4738 dadd $tempreg,$tempreg,$at
4740 If $at is already in use, we use an path which is suboptimal
4741 on superscalar processors.
4742 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4743 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4745 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
4747 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
4750 if (HAVE_64BIT_ADDRESSES
)
4752 /* We don't do GP optimization for now because RELAX_ENCODE can't
4753 hold the data for such large chunks. */
4757 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
4758 tempreg
, (int) BFD_RELOC_MIPS_HIGHEST
);
4759 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
4760 AT
, (int) BFD_RELOC_HI16_S
);
4761 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
4762 tempreg
, tempreg
, (int) BFD_RELOC_MIPS_HIGHER
);
4763 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
4764 AT
, AT
, (int) BFD_RELOC_LO16
);
4765 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll32",
4766 "d,w,<", tempreg
, tempreg
, 0);
4767 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dadd", "d,v,t",
4768 tempreg
, tempreg
, AT
);
4773 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
4774 tempreg
, (int) BFD_RELOC_MIPS_HIGHEST
);
4775 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
4776 tempreg
, tempreg
, (int) BFD_RELOC_MIPS_HIGHER
);
4777 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll", "d,w,<",
4778 tempreg
, tempreg
, 16);
4779 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
4780 tempreg
, tempreg
, (int) BFD_RELOC_HI16_S
);
4781 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll", "d,w,<",
4782 tempreg
, tempreg
, 16);
4783 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
4784 tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4789 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
4790 && ! nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4793 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "addiu",
4794 "t,r,j", tempreg
, mips_gp_register
,
4795 (int) BFD_RELOC_GPREL16
);
4796 p
= frag_var (rs_machine_dependent
, 8, 0,
4797 RELAX_ENCODE (4, 8, 0, 4, 0,
4798 mips_opts
.warn_about_macros
),
4799 offset_expr
.X_add_symbol
, 0, NULL
);
4801 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4804 macro_build (p
, &icnt
, &offset_expr
, "addiu",
4805 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4808 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
4810 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
4812 /* If this is a reference to an external symbol, and there
4813 is no constant, we want
4814 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4815 or if tempreg is PIC_CALL_REG
4816 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4817 For a local symbol, we want
4818 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4820 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4822 If we have a small constant, and this is a reference to
4823 an external symbol, we want
4824 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4826 addiu $tempreg,$tempreg,<constant>
4827 For a local symbol, we want the same instruction
4828 sequence, but we output a BFD_RELOC_LO16 reloc on the
4831 If we have a large constant, and this is a reference to
4832 an external symbol, we want
4833 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4834 lui $at,<hiconstant>
4835 addiu $at,$at,<loconstant>
4836 addu $tempreg,$tempreg,$at
4837 For a local symbol, we want the same instruction
4838 sequence, but we output a BFD_RELOC_LO16 reloc on the
4839 addiu instruction. */
4840 expr1
.X_add_number
= offset_expr
.X_add_number
;
4841 offset_expr
.X_add_number
= 0;
4843 if (expr1
.X_add_number
== 0 && tempreg
== PIC_CALL_REG
)
4844 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
4845 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4846 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
4847 "t,o(b)", tempreg
, lw_reloc_type
, mips_gp_register
);
4848 if (expr1
.X_add_number
== 0)
4857 /* We're going to put in an addu instruction using
4858 tempreg, so we may as well insert the nop right
4860 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4864 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
4865 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
4867 ? mips_opts
.warn_about_macros
4869 offset_expr
.X_add_symbol
, 0, NULL
);
4872 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4875 macro_build (p
, &icnt
, &expr1
,
4876 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4877 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4878 /* FIXME: If breg == 0, and the next instruction uses
4879 $tempreg, then if this variant case is used an extra
4880 nop will be generated. */
4882 else if (expr1
.X_add_number
>= -0x8000
4883 && expr1
.X_add_number
< 0x8000)
4885 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4887 macro_build ((char *) NULL
, &icnt
, &expr1
,
4888 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4889 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4890 frag_var (rs_machine_dependent
, 0, 0,
4891 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
4892 offset_expr
.X_add_symbol
, 0, NULL
);
4898 /* If we are going to add in a base register, and the
4899 target register and the base register are the same,
4900 then we are using AT as a temporary register. Since
4901 we want to load the constant into AT, we add our
4902 current AT (from the global offset table) and the
4903 register into the register now, and pretend we were
4904 not using a base register. */
4909 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4911 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4912 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4913 "d,v,t", treg
, AT
, breg
);
4919 /* Set mips_optimize around the lui instruction to avoid
4920 inserting an unnecessary nop after the lw. */
4921 hold_mips_optimize
= mips_optimize
;
4923 macro_build_lui (NULL
, &icnt
, &expr1
, AT
);
4924 mips_optimize
= hold_mips_optimize
;
4926 macro_build ((char *) NULL
, &icnt
, &expr1
,
4927 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4928 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4929 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4930 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4931 "d,v,t", tempreg
, tempreg
, AT
);
4932 frag_var (rs_machine_dependent
, 0, 0,
4933 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
4934 offset_expr
.X_add_symbol
, 0, NULL
);
4938 else if (mips_pic
== SVR4_PIC
)
4942 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
4943 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
4945 /* This is the large GOT case. If this is a reference to an
4946 external symbol, and there is no constant, we want
4947 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4948 addu $tempreg,$tempreg,$gp
4949 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4950 or if tempreg is PIC_CALL_REG
4951 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
4952 addu $tempreg,$tempreg,$gp
4953 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
4954 For a local symbol, we want
4955 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4957 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4959 If we have a small constant, and this is a reference to
4960 an external symbol, we want
4961 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4962 addu $tempreg,$tempreg,$gp
4963 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4965 addiu $tempreg,$tempreg,<constant>
4966 For a local symbol, we want
4967 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4969 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
4971 If we have a large constant, and this is a reference to
4972 an external symbol, we want
4973 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4974 addu $tempreg,$tempreg,$gp
4975 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4976 lui $at,<hiconstant>
4977 addiu $at,$at,<loconstant>
4978 addu $tempreg,$tempreg,$at
4979 For a local symbol, we want
4980 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4981 lui $at,<hiconstant>
4982 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
4983 addu $tempreg,$tempreg,$at
4985 For NewABI, we want for data addresses
4986 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
4987 If tempreg is PIC_CALL_REG pointing to a external symbol, we want
4988 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4992 int reloc_type
= (tempreg
== PIC_CALL_REG
4993 ? BFD_RELOC_MIPS_CALL16
4994 : BFD_RELOC_MIPS_GOT_DISP
);
4996 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4997 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
4998 "t,o(b)", tempreg
, reloc_type
, mips_gp_register
);
5001 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5002 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5003 "d,v,t", treg
, tempreg
, breg
);
5010 expr1
.X_add_number
= offset_expr
.X_add_number
;
5011 offset_expr
.X_add_number
= 0;
5013 if (reg_needs_delay (mips_gp_register
))
5017 if (expr1
.X_add_number
== 0 && tempreg
== PIC_CALL_REG
)
5019 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
5020 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
5022 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5023 tempreg
, lui_reloc_type
);
5024 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5025 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5026 "d,v,t", tempreg
, tempreg
, mips_gp_register
);
5027 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5028 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5029 "t,o(b)", tempreg
, lw_reloc_type
, tempreg
);
5030 if (expr1
.X_add_number
== 0)
5038 /* We're going to put in an addu instruction using
5039 tempreg, so we may as well insert the nop right
5041 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5046 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
5047 RELAX_ENCODE (12 + off
, 12 + gpdel
, gpdel
,
5050 ? mips_opts
.warn_about_macros
5052 offset_expr
.X_add_symbol
, 0, NULL
);
5054 else if (expr1
.X_add_number
>= -0x8000
5055 && expr1
.X_add_number
< 0x8000)
5057 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5059 macro_build ((char *) NULL
, &icnt
, &expr1
,
5060 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5061 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5063 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
5064 RELAX_ENCODE (20, 12 + gpdel
, gpdel
, 8 + gpdel
, 0,
5066 ? mips_opts
.warn_about_macros
5068 offset_expr
.X_add_symbol
, 0, NULL
);
5074 /* If we are going to add in a base register, and the
5075 target register and the base register are the same,
5076 then we are using AT as a temporary register. Since
5077 we want to load the constant into AT, we add our
5078 current AT (from the global offset table) and the
5079 register into the register now, and pretend we were
5080 not using a base register. */
5088 assert (tempreg
== AT
);
5089 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5091 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5092 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5093 "d,v,t", treg
, AT
, breg
);
5098 /* Set mips_optimize around the lui instruction to avoid
5099 inserting an unnecessary nop after the lw. */
5100 hold_mips_optimize
= mips_optimize
;
5102 macro_build_lui (NULL
, &icnt
, &expr1
, AT
);
5103 mips_optimize
= hold_mips_optimize
;
5105 macro_build ((char *) NULL
, &icnt
, &expr1
,
5106 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5107 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
5108 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5109 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5110 "d,v,t", dreg
, dreg
, AT
);
5112 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ adj
, 0,
5113 RELAX_ENCODE (24 + adj
, 16 + gpdel
+ adj
, gpdel
,
5116 ? mips_opts
.warn_about_macros
5118 offset_expr
.X_add_symbol
, 0, NULL
);
5125 /* This is needed because this instruction uses $gp, but
5126 the first instruction on the main stream does not. */
5127 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5130 macro_build (p
, &icnt
, &offset_expr
,
5131 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5132 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
,
5135 if (expr1
.X_add_number
>= -0x8000
5136 && expr1
.X_add_number
< 0x8000)
5138 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5140 macro_build (p
, &icnt
, &expr1
,
5141 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5142 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5143 /* FIXME: If add_number is 0, and there was no base
5144 register, the external symbol case ended with a load,
5145 so if the symbol turns out to not be external, and
5146 the next instruction uses tempreg, an unnecessary nop
5147 will be inserted. */
5153 /* We must add in the base register now, as in the
5154 external symbol case. */
5155 assert (tempreg
== AT
);
5156 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5158 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5159 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5160 "d,v,t", treg
, AT
, breg
);
5163 /* We set breg to 0 because we have arranged to add
5164 it in in both cases. */
5168 macro_build_lui (p
, &icnt
, &expr1
, AT
);
5170 macro_build (p
, &icnt
, &expr1
,
5171 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5172 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
5174 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5175 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5176 "d,v,t", tempreg
, tempreg
, AT
);
5180 else if (mips_pic
== EMBEDDED_PIC
)
5183 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
5185 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5186 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu", "t,r,j",
5187 tempreg
, mips_gp_register
, (int) BFD_RELOC_GPREL16
);
5196 if (mips_pic
== EMBEDDED_PIC
|| mips_pic
== NO_PIC
)
5197 s
= (dbl
|| HAVE_64BIT_ADDRESSES
) ? "daddu" : "addu";
5199 s
= HAVE_64BIT_ADDRESSES
? "daddu" : "addu";
5201 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
,
5202 "d,v,t", treg
, tempreg
, breg
);
5211 /* The j instruction may not be used in PIC code, since it
5212 requires an absolute address. We convert it to a b
5214 if (mips_pic
== NO_PIC
)
5215 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
5217 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
5220 /* The jal instructions must be handled as macros because when
5221 generating PIC code they expand to multi-instruction
5222 sequences. Normally they are simple instructions. */
5227 if (mips_pic
== NO_PIC
5228 || mips_pic
== EMBEDDED_PIC
)
5229 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
5231 else if (mips_pic
== SVR4_PIC
)
5233 if (sreg
!= PIC_CALL_REG
)
5234 as_warn (_("MIPS PIC call to register other than $25"));
5236 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
5240 if (mips_cprestore_offset
< 0)
5241 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5244 if (! mips_frame_reg_valid
)
5246 as_warn (_("No .frame pseudo-op used in PIC code"));
5247 /* Quiet this warning. */
5248 mips_frame_reg_valid
= 1;
5250 if (! mips_cprestore_valid
)
5252 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5253 /* Quiet this warning. */
5254 mips_cprestore_valid
= 1;
5256 expr1
.X_add_number
= mips_cprestore_offset
;
5257 macro_build ((char *) NULL
, &icnt
, &expr1
,
5258 HAVE_32BIT_ADDRESSES
? "lw" : "ld", "t,o(b)",
5259 mips_gp_register
, (int) BFD_RELOC_LO16
,
5270 if (mips_pic
== NO_PIC
)
5271 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
5272 else if (mips_pic
== SVR4_PIC
)
5276 /* If this is a reference to an external symbol, and we are
5277 using a small GOT, we want
5278 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5282 lw $gp,cprestore($sp)
5283 The cprestore value is set using the .cprestore
5284 pseudo-op. If we are using a big GOT, we want
5285 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5287 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
5291 lw $gp,cprestore($sp)
5292 If the symbol is not external, we want
5293 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5295 addiu $25,$25,<sym> (BFD_RELOC_LO16)
5298 lw $gp,cprestore($sp)
5300 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5301 jalr $ra,$25 (BFD_RELOC_MIPS_JALR)
5305 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5306 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5307 "t,o(b)", PIC_CALL_REG
,
5308 (int) BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5309 macro_build_jalr (icnt
, &offset_expr
);
5316 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5317 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5318 "t,o(b)", PIC_CALL_REG
,
5319 (int) BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
5320 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5322 p
= frag_var (rs_machine_dependent
, 4, 0,
5323 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
5324 offset_expr
.X_add_symbol
, 0, NULL
);
5330 if (reg_needs_delay (mips_gp_register
))
5334 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui",
5335 "t,u", PIC_CALL_REG
,
5336 (int) BFD_RELOC_MIPS_CALL_HI16
);
5337 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5338 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5339 "d,v,t", PIC_CALL_REG
, PIC_CALL_REG
,
5341 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5342 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5343 "t,o(b)", PIC_CALL_REG
,
5344 (int) BFD_RELOC_MIPS_CALL_LO16
, PIC_CALL_REG
);
5345 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5347 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
5348 RELAX_ENCODE (16, 12 + gpdel
, gpdel
,
5350 offset_expr
.X_add_symbol
, 0, NULL
);
5353 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5356 macro_build (p
, &icnt
, &offset_expr
,
5357 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5358 "t,o(b)", PIC_CALL_REG
,
5359 (int) BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
5361 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5364 macro_build (p
, &icnt
, &offset_expr
,
5365 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5366 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
5367 (int) BFD_RELOC_LO16
);
5368 macro_build_jalr (icnt
, &offset_expr
);
5370 if (mips_cprestore_offset
< 0)
5371 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5374 if (! mips_frame_reg_valid
)
5376 as_warn (_("No .frame pseudo-op used in PIC code"));
5377 /* Quiet this warning. */
5378 mips_frame_reg_valid
= 1;
5380 if (! mips_cprestore_valid
)
5382 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5383 /* Quiet this warning. */
5384 mips_cprestore_valid
= 1;
5386 if (mips_opts
.noreorder
)
5387 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5389 expr1
.X_add_number
= mips_cprestore_offset
;
5390 macro_build ((char *) NULL
, &icnt
, &expr1
,
5391 HAVE_32BIT_ADDRESSES
? "lw" : "ld", "t,o(b)",
5392 mips_gp_register
, (int) BFD_RELOC_LO16
,
5397 else if (mips_pic
== EMBEDDED_PIC
)
5399 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
5400 /* The linker may expand the call to a longer sequence which
5401 uses $at, so we must break rather than return. */
5426 /* Itbl support may require additional care here. */
5431 /* Itbl support may require additional care here. */
5436 /* Itbl support may require additional care here. */
5441 /* Itbl support may require additional care here. */
5453 if (mips_arch
== CPU_R4650
)
5455 as_bad (_("opcode not supported on this processor"));
5459 /* Itbl support may require additional care here. */
5464 /* Itbl support may require additional care here. */
5469 /* Itbl support may require additional care here. */
5489 if (breg
== treg
|| coproc
|| lr
)
5511 /* Itbl support may require additional care here. */
5516 /* Itbl support may require additional care here. */
5521 /* Itbl support may require additional care here. */
5526 /* Itbl support may require additional care here. */
5542 if (mips_arch
== CPU_R4650
)
5544 as_bad (_("opcode not supported on this processor"));
5549 /* Itbl support may require additional care here. */
5553 /* Itbl support may require additional care here. */
5558 /* Itbl support may require additional care here. */
5570 /* Itbl support may require additional care here. */
5571 if (mask
== M_LWC1_AB
5572 || mask
== M_SWC1_AB
5573 || mask
== M_LDC1_AB
5574 || mask
== M_SDC1_AB
5583 /* For embedded PIC, we allow loads where the offset is calculated
5584 by subtracting a symbol in the current segment from an unknown
5585 symbol, relative to a base register, e.g.:
5586 <op> $treg, <sym>-<localsym>($breg)
5587 This is used by the compiler for switch statements. */
5588 if (mips_pic
== EMBEDDED_PIC
5589 && offset_expr
.X_op
== O_subtract
5590 && (symbol_constant_p (offset_expr
.X_op_symbol
)
5591 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == now_seg
5592 : (symbol_equated_p (offset_expr
.X_op_symbol
)
5594 (symbol_get_value_expression (offset_expr
.X_op_symbol
)
5598 && (offset_expr
.X_add_number
== 0
5599 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
))
5601 /* For this case, we output the instructions:
5602 lui $tempreg,<sym> (BFD_RELOC_PCREL_HI16_S)
5603 addiu $tempreg,$tempreg,$breg
5604 <op> $treg,<sym>($tempreg) (BFD_RELOC_PCREL_LO16)
5605 If the relocation would fit entirely in 16 bits, it would be
5607 <op> $treg,<sym>($breg) (BFD_RELOC_PCREL_LO16)
5608 instead, but that seems quite difficult. */
5609 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5610 tempreg
, (int) BFD_RELOC_PCREL_HI16_S
);
5611 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5612 ((bfd_arch_bits_per_address (stdoutput
) == 32
5613 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5614 ? "addu" : "daddu"),
5615 "d,v,t", tempreg
, tempreg
, breg
);
5616 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
, treg
,
5617 (int) BFD_RELOC_PCREL_LO16
, tempreg
);
5623 if (offset_expr
.X_op
!= O_constant
5624 && offset_expr
.X_op
!= O_symbol
)
5626 as_bad (_("expression too complex"));
5627 offset_expr
.X_op
= O_constant
;
5630 /* A constant expression in PIC code can be handled just as it
5631 is in non PIC code. */
5632 if (mips_pic
== NO_PIC
5633 || offset_expr
.X_op
== O_constant
)
5637 /* If this is a reference to a GP relative symbol, and there
5638 is no base register, we want
5639 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
5640 Otherwise, if there is no base register, we want
5641 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5642 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5643 If we have a constant, we need two instructions anyhow,
5644 so we always use the latter form.
5646 If we have a base register, and this is a reference to a
5647 GP relative symbol, we want
5648 addu $tempreg,$breg,$gp
5649 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
5651 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5652 addu $tempreg,$tempreg,$breg
5653 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5654 With a constant we always use the latter case.
5656 With 64bit address space and no base register and $at usable,
5658 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5659 lui $at,<sym> (BFD_RELOC_HI16_S)
5660 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5663 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5664 If we have a base register, we want
5665 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5666 lui $at,<sym> (BFD_RELOC_HI16_S)
5667 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5671 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5673 Without $at we can't generate the optimal path for superscalar
5674 processors here since this would require two temporary registers.
5675 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5676 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5678 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5680 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5681 If we have a base register, we want
5682 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5683 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5685 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5687 daddu $tempreg,$tempreg,$breg
5688 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5690 If we have 64-bit addresses, as an optimization, for
5691 addresses which are 32-bit constants (e.g. kseg0/kseg1
5692 addresses) we fall back to the 32-bit address generation
5693 mechanism since it is more efficient. This code should
5694 probably attempt to generate 64-bit constants more
5695 efficiently in general.
5697 if (HAVE_64BIT_ADDRESSES
5698 && !(offset_expr
.X_op
== O_constant
5699 && IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
)))
5703 /* We don't do GP optimization for now because RELAX_ENCODE can't
5704 hold the data for such large chunks. */
5708 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
5709 tempreg
, (int) BFD_RELOC_MIPS_HIGHEST
);
5710 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
5711 AT
, (int) BFD_RELOC_HI16_S
);
5712 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
5713 tempreg
, tempreg
, (int) BFD_RELOC_MIPS_HIGHER
);
5715 macro_build (p
, &icnt
, (expressionS
*) NULL
, "daddu",
5716 "d,v,t", AT
, AT
, breg
);
5717 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll32",
5718 "d,w,<", tempreg
, tempreg
, 0);
5719 macro_build (p
, &icnt
, (expressionS
*) NULL
, "daddu",
5720 "d,v,t", tempreg
, tempreg
, AT
);
5721 macro_build (p
, &icnt
, &offset_expr
, s
,
5722 fmt
, treg
, (int) BFD_RELOC_LO16
, tempreg
);
5727 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
5728 tempreg
, (int) BFD_RELOC_MIPS_HIGHEST
);
5729 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
5730 tempreg
, tempreg
, (int) BFD_RELOC_MIPS_HIGHER
);
5731 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll",
5732 "d,w,<", tempreg
, tempreg
, 16);
5733 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
5734 tempreg
, tempreg
, (int) BFD_RELOC_HI16_S
);
5735 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll",
5736 "d,w,<", tempreg
, tempreg
, 16);
5738 macro_build (p
, &icnt
, (expressionS
*) NULL
, "daddu",
5739 "d,v,t", tempreg
, tempreg
, breg
);
5740 macro_build (p
, &icnt
, &offset_expr
, s
,
5741 fmt
, treg
, (int) BFD_RELOC_LO16
, tempreg
);
5749 if ((valueT
) offset_expr
.X_add_number
> MAX_GPREL_OFFSET
5750 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5755 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5756 treg
, (int) BFD_RELOC_GPREL16
,
5758 p
= frag_var (rs_machine_dependent
, 8, 0,
5759 RELAX_ENCODE (4, 8, 0, 4, 0,
5760 (mips_opts
.warn_about_macros
5762 && mips_opts
.noat
))),
5763 offset_expr
.X_add_symbol
, 0, NULL
);
5766 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
5769 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
5770 (int) BFD_RELOC_LO16
, tempreg
);
5774 if ((valueT
) offset_expr
.X_add_number
> MAX_GPREL_OFFSET
5775 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5780 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5781 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5782 "d,v,t", tempreg
, breg
, mips_gp_register
);
5783 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5784 treg
, (int) BFD_RELOC_GPREL16
, tempreg
);
5785 p
= frag_var (rs_machine_dependent
, 12, 0,
5786 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
5787 offset_expr
.X_add_symbol
, 0, NULL
);
5789 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
5792 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5793 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5794 "d,v,t", tempreg
, tempreg
, breg
);
5797 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
5798 (int) BFD_RELOC_LO16
, tempreg
);
5801 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
5805 /* If this is a reference to an external symbol, we want
5806 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5808 <op> $treg,0($tempreg)
5810 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5812 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5813 <op> $treg,0($tempreg)
5814 If there is a base register, we add it to $tempreg before
5815 the <op>. If there is a constant, we stick it in the
5816 <op> instruction. We don't handle constants larger than
5817 16 bits, because we have no way to load the upper 16 bits
5818 (actually, we could handle them for the subset of cases
5819 in which we are not using $at). */
5820 assert (offset_expr
.X_op
== O_symbol
);
5821 expr1
.X_add_number
= offset_expr
.X_add_number
;
5822 offset_expr
.X_add_number
= 0;
5823 if (expr1
.X_add_number
< -0x8000
5824 || expr1
.X_add_number
>= 0x8000)
5825 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5827 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5828 HAVE_32BIT_ADDRESSES
? "lw" : "ld", "t,o(b)", tempreg
,
5829 (int) BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
5830 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5831 p
= frag_var (rs_machine_dependent
, 4, 0,
5832 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
5833 offset_expr
.X_add_symbol
, 0, NULL
);
5834 macro_build (p
, &icnt
, &offset_expr
,
5835 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5836 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5838 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5839 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5840 "d,v,t", tempreg
, tempreg
, breg
);
5841 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
5842 (int) BFD_RELOC_LO16
, tempreg
);
5844 else if (mips_pic
== SVR4_PIC
)
5849 /* If this is a reference to an external symbol, we want
5850 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5851 addu $tempreg,$tempreg,$gp
5852 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5853 <op> $treg,0($tempreg)
5855 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5857 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5858 <op> $treg,0($tempreg)
5859 If there is a base register, we add it to $tempreg before
5860 the <op>. If there is a constant, we stick it in the
5861 <op> instruction. We don't handle constants larger than
5862 16 bits, because we have no way to load the upper 16 bits
5863 (actually, we could handle them for the subset of cases
5864 in which we are not using $at).
5867 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5868 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
5869 <op> $treg,0($tempreg)
5871 assert (offset_expr
.X_op
== O_symbol
);
5872 expr1
.X_add_number
= offset_expr
.X_add_number
;
5873 offset_expr
.X_add_number
= 0;
5874 if (expr1
.X_add_number
< -0x8000
5875 || expr1
.X_add_number
>= 0x8000)
5876 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5879 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5880 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5881 "t,o(b)", tempreg
, BFD_RELOC_MIPS_GOT_PAGE
,
5883 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5884 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5885 "t,r,j", tempreg
, tempreg
,
5886 BFD_RELOC_MIPS_GOT_OFST
);
5888 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5889 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5890 "d,v,t", tempreg
, tempreg
, breg
);
5891 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
5892 (int) BFD_RELOC_LO16
, tempreg
);
5899 if (reg_needs_delay (mips_gp_register
))
5904 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5905 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
5906 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5907 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5908 "d,v,t", tempreg
, tempreg
, mips_gp_register
);
5909 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5910 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5911 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
5913 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
5914 RELAX_ENCODE (12, 12 + gpdel
, gpdel
, 8 + gpdel
, 0, 0),
5915 offset_expr
.X_add_symbol
, 0, NULL
);
5918 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5921 macro_build (p
, &icnt
, &offset_expr
,
5922 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5923 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
,
5926 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5928 macro_build (p
, &icnt
, &offset_expr
,
5929 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5930 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5932 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5933 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5934 "d,v,t", tempreg
, tempreg
, breg
);
5935 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
5936 (int) BFD_RELOC_LO16
, tempreg
);
5938 else if (mips_pic
== EMBEDDED_PIC
)
5940 /* If there is no base register, we want
5941 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
5942 If there is a base register, we want
5943 addu $tempreg,$breg,$gp
5944 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
5946 assert (offset_expr
.X_op
== O_symbol
);
5949 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5950 treg
, (int) BFD_RELOC_GPREL16
, mips_gp_register
);
5955 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5956 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5957 "d,v,t", tempreg
, breg
, mips_gp_register
);
5958 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5959 treg
, (int) BFD_RELOC_GPREL16
, tempreg
);
5972 load_register (&icnt
, treg
, &imm_expr
, 0);
5976 load_register (&icnt
, treg
, &imm_expr
, 1);
5980 if (imm_expr
.X_op
== O_constant
)
5982 load_register (&icnt
, AT
, &imm_expr
, 0);
5983 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5984 "mtc1", "t,G", AT
, treg
);
5989 assert (offset_expr
.X_op
== O_symbol
5990 && strcmp (segment_name (S_GET_SEGMENT
5991 (offset_expr
.X_add_symbol
)),
5993 && offset_expr
.X_add_number
== 0);
5994 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5995 treg
, (int) BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
6000 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
6001 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
6002 order 32 bits of the value and the low order 32 bits are either
6003 zero or in OFFSET_EXPR. */
6004 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6006 if (HAVE_64BIT_GPRS
)
6007 load_register (&icnt
, treg
, &imm_expr
, 1);
6012 if (target_big_endian
)
6024 load_register (&icnt
, hreg
, &imm_expr
, 0);
6027 if (offset_expr
.X_op
== O_absent
)
6028 move_register (&icnt
, lreg
, 0);
6031 assert (offset_expr
.X_op
== O_constant
);
6032 load_register (&icnt
, lreg
, &offset_expr
, 0);
6039 /* We know that sym is in the .rdata section. First we get the
6040 upper 16 bits of the address. */
6041 if (mips_pic
== NO_PIC
)
6043 macro_build_lui (NULL
, &icnt
, &offset_expr
, AT
);
6045 else if (mips_pic
== SVR4_PIC
)
6047 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
6048 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
6049 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
,
6052 else if (mips_pic
== EMBEDDED_PIC
)
6054 /* For embedded PIC we pick up the entire address off $gp in
6055 a single instruction. */
6056 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
6057 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu", "t,r,j", AT
,
6058 mips_gp_register
, (int) BFD_RELOC_GPREL16
);
6059 offset_expr
.X_op
= O_constant
;
6060 offset_expr
.X_add_number
= 0;
6065 /* Now we load the register(s). */
6066 if (HAVE_64BIT_GPRS
)
6067 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
6068 treg
, (int) BFD_RELOC_LO16
, AT
);
6071 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
6072 treg
, (int) BFD_RELOC_LO16
, AT
);
6075 /* FIXME: How in the world do we deal with the possible
6077 offset_expr
.X_add_number
+= 4;
6078 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
6079 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
6083 /* To avoid confusion in tc_gen_reloc, we must ensure that this
6084 does not become a variant frag. */
6085 frag_wane (frag_now
);
6091 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
6092 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
6093 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
6094 the value and the low order 32 bits are either zero or in
6096 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6098 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_FPRS
);
6099 if (HAVE_64BIT_FPRS
)
6101 assert (HAVE_64BIT_GPRS
);
6102 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6103 "dmtc1", "t,S", AT
, treg
);
6107 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6108 "mtc1", "t,G", AT
, treg
+ 1);
6109 if (offset_expr
.X_op
== O_absent
)
6110 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6111 "mtc1", "t,G", 0, treg
);
6114 assert (offset_expr
.X_op
== O_constant
);
6115 load_register (&icnt
, AT
, &offset_expr
, 0);
6116 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6117 "mtc1", "t,G", AT
, treg
);
6123 assert (offset_expr
.X_op
== O_symbol
6124 && offset_expr
.X_add_number
== 0);
6125 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
6126 if (strcmp (s
, ".lit8") == 0)
6128 if (mips_opts
.isa
!= ISA_MIPS1
)
6130 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
6131 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
,
6135 breg
= mips_gp_register
;
6136 r
= BFD_RELOC_MIPS_LITERAL
;
6141 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
6142 if (mips_pic
== SVR4_PIC
)
6143 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
6144 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
6145 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
,
6149 /* FIXME: This won't work for a 64 bit address. */
6150 macro_build_lui (NULL
, &icnt
, &offset_expr
, AT
);
6153 if (mips_opts
.isa
!= ISA_MIPS1
)
6155 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
6156 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, AT
);
6158 /* To avoid confusion in tc_gen_reloc, we must ensure
6159 that this does not become a variant frag. */
6160 frag_wane (frag_now
);
6171 if (mips_arch
== CPU_R4650
)
6173 as_bad (_("opcode not supported on this processor"));
6176 /* Even on a big endian machine $fn comes before $fn+1. We have
6177 to adjust when loading from memory. */
6180 assert (mips_opts
.isa
== ISA_MIPS1
);
6181 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
6182 target_big_endian
? treg
+ 1 : treg
,
6184 /* FIXME: A possible overflow which I don't know how to deal
6186 offset_expr
.X_add_number
+= 4;
6187 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
6188 target_big_endian
? treg
: treg
+ 1,
6191 /* To avoid confusion in tc_gen_reloc, we must ensure that this
6192 does not become a variant frag. */
6193 frag_wane (frag_now
);
6202 * The MIPS assembler seems to check for X_add_number not
6203 * being double aligned and generating:
6206 * addiu at,at,%lo(foo+1)
6209 * But, the resulting address is the same after relocation so why
6210 * generate the extra instruction?
6212 if (mips_arch
== CPU_R4650
)
6214 as_bad (_("opcode not supported on this processor"));
6217 /* Itbl support may require additional care here. */
6219 if (mips_opts
.isa
!= ISA_MIPS1
)
6230 if (mips_arch
== CPU_R4650
)
6232 as_bad (_("opcode not supported on this processor"));
6236 if (mips_opts
.isa
!= ISA_MIPS1
)
6244 /* Itbl support may require additional care here. */
6249 if (HAVE_64BIT_GPRS
)
6260 if (HAVE_64BIT_GPRS
)
6270 /* We do _not_ bother to allow embedded PIC (symbol-local_symbol)
6271 loads for the case of doing a pair of loads to simulate an 'ld'.
6272 This is not currently done by the compiler, and assembly coders
6273 writing embedded-pic code can cope. */
6275 if (offset_expr
.X_op
!= O_symbol
6276 && offset_expr
.X_op
!= O_constant
)
6278 as_bad (_("expression too complex"));
6279 offset_expr
.X_op
= O_constant
;
6282 /* Even on a big endian machine $fn comes before $fn+1. We have
6283 to adjust when loading from memory. We set coproc if we must
6284 load $fn+1 first. */
6285 /* Itbl support may require additional care here. */
6286 if (! target_big_endian
)
6289 if (mips_pic
== NO_PIC
6290 || offset_expr
.X_op
== O_constant
)
6294 /* If this is a reference to a GP relative symbol, we want
6295 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6296 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6297 If we have a base register, we use this
6299 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6300 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6301 If this is not a GP relative symbol, we want
6302 lui $at,<sym> (BFD_RELOC_HI16_S)
6303 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6304 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6305 If there is a base register, we add it to $at after the
6306 lui instruction. If there is a constant, we always use
6308 if ((valueT
) offset_expr
.X_add_number
> MAX_GPREL_OFFSET
6309 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6321 tempreg
= mips_gp_register
;
6328 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6329 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6330 "d,v,t", AT
, breg
, mips_gp_register
);
6336 /* Itbl support may require additional care here. */
6337 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
6338 coproc
? treg
+ 1 : treg
,
6339 (int) BFD_RELOC_GPREL16
, tempreg
);
6340 offset_expr
.X_add_number
+= 4;
6342 /* Set mips_optimize to 2 to avoid inserting an
6344 hold_mips_optimize
= mips_optimize
;
6346 /* Itbl support may require additional care here. */
6347 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
6348 coproc
? treg
: treg
+ 1,
6349 (int) BFD_RELOC_GPREL16
, tempreg
);
6350 mips_optimize
= hold_mips_optimize
;
6352 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
6353 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
6354 used_at
&& mips_opts
.noat
),
6355 offset_expr
.X_add_symbol
, 0, NULL
);
6357 /* We just generated two relocs. When tc_gen_reloc
6358 handles this case, it will skip the first reloc and
6359 handle the second. The second reloc already has an
6360 extra addend of 4, which we added above. We must
6361 subtract it out, and then subtract another 4 to make
6362 the first reloc come out right. The second reloc
6363 will come out right because we are going to add 4 to
6364 offset_expr when we build its instruction below.
6366 If we have a symbol, then we don't want to include
6367 the offset, because it will wind up being included
6368 when we generate the reloc. */
6370 if (offset_expr
.X_op
== O_constant
)
6371 offset_expr
.X_add_number
-= 8;
6374 offset_expr
.X_add_number
= -4;
6375 offset_expr
.X_op
= O_constant
;
6378 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
6383 macro_build (p
, &icnt
, (expressionS
*) NULL
,
6384 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6385 "d,v,t", AT
, breg
, AT
);
6389 /* Itbl support may require additional care here. */
6390 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
6391 coproc
? treg
+ 1 : treg
,
6392 (int) BFD_RELOC_LO16
, AT
);
6395 /* FIXME: How do we handle overflow here? */
6396 offset_expr
.X_add_number
+= 4;
6397 /* Itbl support may require additional care here. */
6398 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
6399 coproc
? treg
: treg
+ 1,
6400 (int) BFD_RELOC_LO16
, AT
);
6402 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
6406 /* If this is a reference to an external symbol, we want
6407 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6412 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6414 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6415 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6416 If there is a base register we add it to $at before the
6417 lwc1 instructions. If there is a constant we include it
6418 in the lwc1 instructions. */
6420 expr1
.X_add_number
= offset_expr
.X_add_number
;
6421 offset_expr
.X_add_number
= 0;
6422 if (expr1
.X_add_number
< -0x8000
6423 || expr1
.X_add_number
>= 0x8000 - 4)
6424 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6429 frag_grow (24 + off
);
6430 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
6431 HAVE_32BIT_ADDRESSES
? "lw" : "ld", "t,o(b)", AT
,
6432 (int) BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6433 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
6435 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6436 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6437 "d,v,t", AT
, breg
, AT
);
6438 /* Itbl support may require additional care here. */
6439 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
6440 coproc
? treg
+ 1 : treg
,
6441 (int) BFD_RELOC_LO16
, AT
);
6442 expr1
.X_add_number
+= 4;
6444 /* Set mips_optimize to 2 to avoid inserting an undesired
6446 hold_mips_optimize
= mips_optimize
;
6448 /* Itbl support may require additional care here. */
6449 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
6450 coproc
? treg
: treg
+ 1,
6451 (int) BFD_RELOC_LO16
, AT
);
6452 mips_optimize
= hold_mips_optimize
;
6454 (void) frag_var (rs_machine_dependent
, 0, 0,
6455 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
6456 offset_expr
.X_add_symbol
, 0, NULL
);
6458 else if (mips_pic
== SVR4_PIC
)
6463 /* If this is a reference to an external symbol, we want
6464 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6466 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
6471 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6473 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6474 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6475 If there is a base register we add it to $at before the
6476 lwc1 instructions. If there is a constant we include it
6477 in the lwc1 instructions. */
6479 expr1
.X_add_number
= offset_expr
.X_add_number
;
6480 offset_expr
.X_add_number
= 0;
6481 if (expr1
.X_add_number
< -0x8000
6482 || expr1
.X_add_number
>= 0x8000 - 4)
6483 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6484 if (reg_needs_delay (mips_gp_register
))
6493 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
6494 AT
, (int) BFD_RELOC_MIPS_GOT_HI16
);
6495 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6496 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6497 "d,v,t", AT
, AT
, mips_gp_register
);
6498 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
6499 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
6500 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT_LO16
, AT
);
6501 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
6503 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6504 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6505 "d,v,t", AT
, breg
, AT
);
6506 /* Itbl support may require additional care here. */
6507 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
6508 coproc
? treg
+ 1 : treg
,
6509 (int) BFD_RELOC_LO16
, AT
);
6510 expr1
.X_add_number
+= 4;
6512 /* Set mips_optimize to 2 to avoid inserting an undesired
6514 hold_mips_optimize
= mips_optimize
;
6516 /* Itbl support may require additional care here. */
6517 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
6518 coproc
? treg
: treg
+ 1,
6519 (int) BFD_RELOC_LO16
, AT
);
6520 mips_optimize
= hold_mips_optimize
;
6521 expr1
.X_add_number
-= 4;
6523 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ off
, 0,
6524 RELAX_ENCODE (24 + off
, 16 + gpdel
+ off
, gpdel
,
6525 8 + gpdel
+ off
, 1, 0),
6526 offset_expr
.X_add_symbol
, 0, NULL
);
6529 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
6532 macro_build (p
, &icnt
, &offset_expr
,
6533 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
6534 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
,
6537 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
6541 macro_build (p
, &icnt
, (expressionS
*) NULL
,
6542 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6543 "d,v,t", AT
, breg
, AT
);
6546 /* Itbl support may require additional care here. */
6547 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
6548 coproc
? treg
+ 1 : treg
,
6549 (int) BFD_RELOC_LO16
, AT
);
6551 expr1
.X_add_number
+= 4;
6553 /* Set mips_optimize to 2 to avoid inserting an undesired
6555 hold_mips_optimize
= mips_optimize
;
6557 /* Itbl support may require additional care here. */
6558 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
6559 coproc
? treg
: treg
+ 1,
6560 (int) BFD_RELOC_LO16
, AT
);
6561 mips_optimize
= hold_mips_optimize
;
6563 else if (mips_pic
== EMBEDDED_PIC
)
6565 /* If there is no base register, we use
6566 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6567 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6568 If we have a base register, we use
6570 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6571 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6575 tempreg
= mips_gp_register
;
6580 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6581 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6582 "d,v,t", AT
, breg
, mips_gp_register
);
6587 /* Itbl support may require additional care here. */
6588 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
6589 coproc
? treg
+ 1 : treg
,
6590 (int) BFD_RELOC_GPREL16
, tempreg
);
6591 offset_expr
.X_add_number
+= 4;
6592 /* Itbl support may require additional care here. */
6593 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
6594 coproc
? treg
: treg
+ 1,
6595 (int) BFD_RELOC_GPREL16
, tempreg
);
6611 assert (HAVE_32BIT_ADDRESSES
);
6612 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6613 (int) BFD_RELOC_LO16
, breg
);
6614 offset_expr
.X_add_number
+= 4;
6615 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
6616 (int) BFD_RELOC_LO16
, breg
);
6619 /* New code added to support COPZ instructions.
6620 This code builds table entries out of the macros in mip_opcodes.
6621 R4000 uses interlocks to handle coproc delays.
6622 Other chips (like the R3000) require nops to be inserted for delays.
6624 FIXME: Currently, we require that the user handle delays.
6625 In order to fill delay slots for non-interlocked chips,
6626 we must have a way to specify delays based on the coprocessor.
6627 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
6628 What are the side-effects of the cop instruction?
6629 What cache support might we have and what are its effects?
6630 Both coprocessor & memory require delays. how long???
6631 What registers are read/set/modified?
6633 If an itbl is provided to interpret cop instructions,
6634 this knowledge can be encoded in the itbl spec. */
6648 /* For now we just do C (same as Cz). The parameter will be
6649 stored in insn_opcode by mips_ip. */
6650 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "C",
6655 move_register (&icnt
, dreg
, sreg
);
6658 #ifdef LOSING_COMPILER
6660 /* Try and see if this is a new itbl instruction.
6661 This code builds table entries out of the macros in mip_opcodes.
6662 FIXME: For now we just assemble the expression and pass it's
6663 value along as a 32-bit immediate.
6664 We may want to have the assembler assemble this value,
6665 so that we gain the assembler's knowledge of delay slots,
6667 Would it be more efficient to use mask (id) here? */
6668 if (itbl_have_entries
6669 && (immed_expr
= itbl_assemble (ip
->insn_mo
->name
, "")))
6671 s
= ip
->insn_mo
->name
;
6673 coproc
= ITBL_DECODE_PNUM (immed_expr
);;
6674 macro_build ((char *) NULL
, &icnt
, &immed_expr
, s
, "C");
6681 as_warn (_("Macro used $at after \".set noat\""));
6686 struct mips_cl_insn
*ip
;
6688 register int treg
, sreg
, dreg
, breg
;
6704 bfd_reloc_code_real_type r
;
6707 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
6708 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
6709 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
6710 mask
= ip
->insn_mo
->mask
;
6712 expr1
.X_op
= O_constant
;
6713 expr1
.X_op_symbol
= NULL
;
6714 expr1
.X_add_symbol
= NULL
;
6715 expr1
.X_add_number
= 1;
6719 #endif /* LOSING_COMPILER */
6724 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6725 dbl
? "dmultu" : "multu", "s,t", sreg
, treg
);
6726 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "d",
6733 /* The MIPS assembler some times generates shifts and adds. I'm
6734 not trying to be that fancy. GCC should do this for us
6736 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6737 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6738 dbl
? "dmult" : "mult", "s,t", sreg
, AT
);
6739 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "d",
6753 mips_emit_delays (true);
6754 ++mips_opts
.noreorder
;
6755 mips_any_noreorder
= 1;
6757 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6758 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6759 dbl
? "dmult" : "mult", "s,t", sreg
, imm
? AT
: treg
);
6760 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "d",
6762 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6763 dbl
? "dsra32" : "sra", "d,w,<", dreg
, dreg
, RA
);
6764 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mfhi", "d",
6767 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "tne", "s,t",
6771 expr1
.X_add_number
= 8;
6772 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
,
6774 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "",
6776 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
6779 --mips_opts
.noreorder
;
6780 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "d", dreg
);
6793 mips_emit_delays (true);
6794 ++mips_opts
.noreorder
;
6795 mips_any_noreorder
= 1;
6797 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6798 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6799 dbl
? "dmultu" : "multu",
6800 "s,t", sreg
, imm
? AT
: treg
);
6801 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mfhi", "d",
6803 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "d",
6806 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "tne", "s,t",
6810 expr1
.X_add_number
= 8;
6811 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
6812 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "",
6814 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
6817 --mips_opts
.noreorder
;
6821 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsubu",
6822 "d,v,t", AT
, 0, treg
);
6823 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsrlv",
6824 "d,t,s", AT
, sreg
, AT
);
6825 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsllv",
6826 "d,t,s", dreg
, sreg
, treg
);
6827 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
6828 "d,v,t", dreg
, dreg
, AT
);
6832 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "subu",
6833 "d,v,t", AT
, 0, treg
);
6834 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srlv",
6835 "d,t,s", AT
, sreg
, AT
);
6836 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sllv",
6837 "d,t,s", dreg
, sreg
, treg
);
6838 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
6839 "d,v,t", dreg
, dreg
, AT
);
6847 if (imm_expr
.X_op
!= O_constant
)
6848 as_bad (_("rotate count too large"));
6849 rot
= imm_expr
.X_add_number
& 0x3f;
6852 l
= (rot
< 0x20) ? "dsll" : "dsll32";
6853 r
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
6855 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, l
,
6856 "d,w,<", AT
, sreg
, rot
);
6857 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, r
,
6858 "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
6859 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
6860 "d,v,t", dreg
, dreg
, AT
);
6868 if (imm_expr
.X_op
!= O_constant
)
6869 as_bad (_("rotate count too large"));
6870 rot
= imm_expr
.X_add_number
& 0x1f;
6873 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sll",
6874 "d,w,<", AT
, sreg
, rot
);
6875 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srl",
6876 "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
6877 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
6878 "d,v,t", dreg
, dreg
, AT
);
6883 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsubu",
6884 "d,v,t", AT
, 0, treg
);
6885 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsllv",
6886 "d,t,s", AT
, sreg
, AT
);
6887 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsrlv",
6888 "d,t,s", dreg
, sreg
, treg
);
6889 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
6890 "d,v,t", dreg
, dreg
, AT
);
6894 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "subu",
6895 "d,v,t", AT
, 0, treg
);
6896 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sllv",
6897 "d,t,s", AT
, sreg
, AT
);
6898 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srlv",
6899 "d,t,s", dreg
, sreg
, treg
);
6900 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
6901 "d,v,t", dreg
, dreg
, AT
);
6909 if (imm_expr
.X_op
!= O_constant
)
6910 as_bad (_("rotate count too large"));
6911 rot
= imm_expr
.X_add_number
& 0x3f;
6914 r
= (rot
< 0x20) ? "dsrl" : "dsrl32";
6915 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
6917 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, r
,
6918 "d,w,<", AT
, sreg
, rot
);
6919 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, l
,
6920 "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
6921 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
6922 "d,v,t", dreg
, dreg
, AT
);
6930 if (imm_expr
.X_op
!= O_constant
)
6931 as_bad (_("rotate count too large"));
6932 rot
= imm_expr
.X_add_number
& 0x1f;
6935 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srl",
6936 "d,w,<", AT
, sreg
, rot
);
6937 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sll",
6938 "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
6939 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
6940 "d,v,t", dreg
, dreg
, AT
);
6945 if (mips_arch
== CPU_R4650
)
6947 as_bad (_("opcode not supported on this processor"));
6950 assert (mips_opts
.isa
== ISA_MIPS1
);
6951 /* Even on a big endian machine $fn comes before $fn+1. We have
6952 to adjust when storing to memory. */
6953 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
6954 target_big_endian
? treg
+ 1 : treg
,
6955 (int) BFD_RELOC_LO16
, breg
);
6956 offset_expr
.X_add_number
+= 4;
6957 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
6958 target_big_endian
? treg
: treg
+ 1,
6959 (int) BFD_RELOC_LO16
, breg
);
6964 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6965 treg
, (int) BFD_RELOC_LO16
);
6967 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6968 sreg
, (int) BFD_RELOC_LO16
);
6971 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "xor",
6972 "d,v,t", dreg
, sreg
, treg
);
6973 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6974 dreg
, (int) BFD_RELOC_LO16
);
6979 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6981 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6982 sreg
, (int) BFD_RELOC_LO16
);
6987 as_warn (_("Instruction %s: result is always false"),
6989 move_register (&icnt
, dreg
, 0);
6992 if (imm_expr
.X_op
== O_constant
6993 && imm_expr
.X_add_number
>= 0
6994 && imm_expr
.X_add_number
< 0x10000)
6996 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
6997 sreg
, (int) BFD_RELOC_LO16
);
7000 else if (imm_expr
.X_op
== O_constant
7001 && imm_expr
.X_add_number
> -0x8000
7002 && imm_expr
.X_add_number
< 0)
7004 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7005 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
7006 HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7007 "t,r,j", dreg
, sreg
,
7008 (int) BFD_RELOC_LO16
);
7013 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7014 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "xor",
7015 "d,v,t", dreg
, sreg
, AT
);
7018 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
7019 (int) BFD_RELOC_LO16
);
7024 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
7030 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d,v,t",
7032 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
7033 (int) BFD_RELOC_LO16
);
7036 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
7038 if (imm_expr
.X_op
== O_constant
7039 && imm_expr
.X_add_number
>= -0x8000
7040 && imm_expr
.X_add_number
< 0x8000)
7042 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
7043 mask
== M_SGE_I
? "slti" : "sltiu",
7044 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
7049 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7050 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7051 mask
== M_SGE_I
? "slt" : "sltu", "d,v,t", dreg
, sreg
,
7055 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
7056 (int) BFD_RELOC_LO16
);
7061 case M_SGT
: /* sreg > treg <==> treg < sreg */
7067 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d,v,t",
7071 case M_SGT_I
: /* sreg > I <==> I < sreg */
7077 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7078 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d,v,t",
7082 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
7088 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d,v,t",
7090 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
7091 (int) BFD_RELOC_LO16
);
7094 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
7100 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7101 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d,v,t",
7103 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
7104 (int) BFD_RELOC_LO16
);
7108 if (imm_expr
.X_op
== O_constant
7109 && imm_expr
.X_add_number
>= -0x8000
7110 && imm_expr
.X_add_number
< 0x8000)
7112 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
7113 dreg
, sreg
, (int) BFD_RELOC_LO16
);
7116 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7117 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "slt", "d,v,t",
7122 if (imm_expr
.X_op
== O_constant
7123 && imm_expr
.X_add_number
>= -0x8000
7124 && imm_expr
.X_add_number
< 0x8000)
7126 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
7127 dreg
, sreg
, (int) BFD_RELOC_LO16
);
7130 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7131 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
7132 "d,v,t", dreg
, sreg
, AT
);
7137 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
7138 "d,v,t", dreg
, 0, treg
);
7140 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
7141 "d,v,t", dreg
, 0, sreg
);
7144 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "xor",
7145 "d,v,t", dreg
, sreg
, treg
);
7146 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
7147 "d,v,t", dreg
, 0, dreg
);
7152 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7154 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
7155 "d,v,t", dreg
, 0, sreg
);
7160 as_warn (_("Instruction %s: result is always true"),
7162 macro_build ((char *) NULL
, &icnt
, &expr1
,
7163 HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7164 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
7167 if (imm_expr
.X_op
== O_constant
7168 && imm_expr
.X_add_number
>= 0
7169 && imm_expr
.X_add_number
< 0x10000)
7171 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
7172 dreg
, sreg
, (int) BFD_RELOC_LO16
);
7175 else if (imm_expr
.X_op
== O_constant
7176 && imm_expr
.X_add_number
> -0x8000
7177 && imm_expr
.X_add_number
< 0)
7179 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7180 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
7181 HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7182 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
7187 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7188 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "xor",
7189 "d,v,t", dreg
, sreg
, AT
);
7192 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
7193 "d,v,t", dreg
, 0, dreg
);
7201 if (imm_expr
.X_op
== O_constant
7202 && imm_expr
.X_add_number
> -0x8000
7203 && imm_expr
.X_add_number
<= 0x8000)
7205 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7206 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
7207 dbl
? "daddi" : "addi",
7208 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
7211 load_register (&icnt
, AT
, &imm_expr
, dbl
);
7212 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7213 dbl
? "dsub" : "sub", "d,v,t", dreg
, sreg
, AT
);
7219 if (imm_expr
.X_op
== O_constant
7220 && imm_expr
.X_add_number
> -0x8000
7221 && imm_expr
.X_add_number
<= 0x8000)
7223 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7224 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
7225 dbl
? "daddiu" : "addiu",
7226 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
7229 load_register (&icnt
, AT
, &imm_expr
, dbl
);
7230 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7231 dbl
? "dsubu" : "subu", "d,v,t", dreg
, sreg
, AT
);
7252 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7253 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "s,t", sreg
,
7259 assert (mips_opts
.isa
== ISA_MIPS1
);
7260 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
7261 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
7264 * Is the double cfc1 instruction a bug in the mips assembler;
7265 * or is there a reason for it?
7267 mips_emit_delays (true);
7268 ++mips_opts
.noreorder
;
7269 mips_any_noreorder
= 1;
7270 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "cfc1", "t,G",
7272 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "cfc1", "t,G",
7274 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
7275 expr1
.X_add_number
= 3;
7276 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
7277 (int) BFD_RELOC_LO16
);
7278 expr1
.X_add_number
= 2;
7279 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
7280 (int) BFD_RELOC_LO16
);
7281 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "ctc1", "t,G",
7283 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
7284 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7285 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
7286 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "ctc1", "t,G",
7288 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
7289 --mips_opts
.noreorder
;
7298 if (offset_expr
.X_add_number
>= 0x7fff)
7299 as_bad (_("operand overflow"));
7300 /* avoid load delay */
7301 if (! target_big_endian
)
7302 ++offset_expr
.X_add_number
;
7303 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
7304 (int) BFD_RELOC_LO16
, breg
);
7305 if (! target_big_endian
)
7306 --offset_expr
.X_add_number
;
7308 ++offset_expr
.X_add_number
;
7309 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
7310 (int) BFD_RELOC_LO16
, breg
);
7311 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sll", "d,w,<",
7313 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or", "d,v,t",
7327 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7328 as_bad (_("operand overflow"));
7329 if (! target_big_endian
)
7330 offset_expr
.X_add_number
+= off
;
7331 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
7332 (int) BFD_RELOC_LO16
, breg
);
7333 if (! target_big_endian
)
7334 offset_expr
.X_add_number
-= off
;
7336 offset_expr
.X_add_number
+= off
;
7337 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
7338 (int) BFD_RELOC_LO16
, breg
);
7352 load_address (&icnt
, AT
, &offset_expr
, &used_at
);
7354 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7355 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
7356 "d,v,t", AT
, AT
, breg
);
7357 if (! target_big_endian
)
7358 expr1
.X_add_number
= off
;
7360 expr1
.X_add_number
= 0;
7361 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
7362 (int) BFD_RELOC_LO16
, AT
);
7363 if (! target_big_endian
)
7364 expr1
.X_add_number
= 0;
7366 expr1
.X_add_number
= off
;
7367 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
7368 (int) BFD_RELOC_LO16
, AT
);
7374 load_address (&icnt
, AT
, &offset_expr
, &used_at
);
7376 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7377 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
7378 "d,v,t", AT
, AT
, breg
);
7379 if (target_big_endian
)
7380 expr1
.X_add_number
= 0;
7381 macro_build ((char *) NULL
, &icnt
, &expr1
,
7382 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
7383 (int) BFD_RELOC_LO16
, AT
);
7384 if (target_big_endian
)
7385 expr1
.X_add_number
= 1;
7387 expr1
.X_add_number
= 0;
7388 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
7389 (int) BFD_RELOC_LO16
, AT
);
7390 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sll", "d,w,<",
7392 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or", "d,v,t",
7397 if (offset_expr
.X_add_number
>= 0x7fff)
7398 as_bad (_("operand overflow"));
7399 if (target_big_endian
)
7400 ++offset_expr
.X_add_number
;
7401 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
7402 (int) BFD_RELOC_LO16
, breg
);
7403 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srl", "d,w,<",
7405 if (target_big_endian
)
7406 --offset_expr
.X_add_number
;
7408 ++offset_expr
.X_add_number
;
7409 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
7410 (int) BFD_RELOC_LO16
, breg
);
7423 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7424 as_bad (_("operand overflow"));
7425 if (! target_big_endian
)
7426 offset_expr
.X_add_number
+= off
;
7427 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
7428 (int) BFD_RELOC_LO16
, breg
);
7429 if (! target_big_endian
)
7430 offset_expr
.X_add_number
-= off
;
7432 offset_expr
.X_add_number
+= off
;
7433 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
7434 (int) BFD_RELOC_LO16
, breg
);
7448 load_address (&icnt
, AT
, &offset_expr
, &used_at
);
7450 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7451 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
7452 "d,v,t", AT
, AT
, breg
);
7453 if (! target_big_endian
)
7454 expr1
.X_add_number
= off
;
7456 expr1
.X_add_number
= 0;
7457 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
7458 (int) BFD_RELOC_LO16
, AT
);
7459 if (! target_big_endian
)
7460 expr1
.X_add_number
= 0;
7462 expr1
.X_add_number
= off
;
7463 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
7464 (int) BFD_RELOC_LO16
, AT
);
7469 load_address (&icnt
, AT
, &offset_expr
, &used_at
);
7471 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7472 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
7473 "d,v,t", AT
, AT
, breg
);
7474 if (! target_big_endian
)
7475 expr1
.X_add_number
= 0;
7476 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
7477 (int) BFD_RELOC_LO16
, AT
);
7478 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srl", "d,w,<",
7480 if (! target_big_endian
)
7481 expr1
.X_add_number
= 1;
7483 expr1
.X_add_number
= 0;
7484 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
7485 (int) BFD_RELOC_LO16
, AT
);
7486 if (! target_big_endian
)
7487 expr1
.X_add_number
= 0;
7489 expr1
.X_add_number
= 1;
7490 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
7491 (int) BFD_RELOC_LO16
, AT
);
7492 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sll", "d,w,<",
7494 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or", "d,v,t",
7499 /* FIXME: Check if this is one of the itbl macros, since they
7500 are added dynamically. */
7501 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
7505 as_warn (_("Macro used $at after \".set noat\""));
7508 /* Implement macros in mips16 mode. */
7512 struct mips_cl_insn
*ip
;
7515 int xreg
, yreg
, zreg
, tmp
;
7519 const char *s
, *s2
, *s3
;
7521 mask
= ip
->insn_mo
->mask
;
7523 xreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
7524 yreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
;
7525 zreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
7529 expr1
.X_op
= O_constant
;
7530 expr1
.X_op_symbol
= NULL
;
7531 expr1
.X_add_symbol
= NULL
;
7532 expr1
.X_add_number
= 1;
7551 mips_emit_delays (true);
7552 ++mips_opts
.noreorder
;
7553 mips_any_noreorder
= 1;
7554 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7555 dbl
? "ddiv" : "div",
7556 "0,x,y", xreg
, yreg
);
7557 expr1
.X_add_number
= 2;
7558 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
7559 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break", "6",
7562 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
7563 since that causes an overflow. We should do that as well,
7564 but I don't see how to do the comparisons without a temporary
7566 --mips_opts
.noreorder
;
7567 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "x", zreg
);
7586 mips_emit_delays (true);
7587 ++mips_opts
.noreorder
;
7588 mips_any_noreorder
= 1;
7589 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "0,x,y",
7591 expr1
.X_add_number
= 2;
7592 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
7593 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
7595 --mips_opts
.noreorder
;
7596 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s2
, "x", zreg
);
7602 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7603 dbl
? "dmultu" : "multu", "x,y", xreg
, yreg
);
7604 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "x",
7613 if (imm_expr
.X_op
!= O_constant
)
7614 as_bad (_("Unsupported large constant"));
7615 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7616 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
7617 dbl
? "daddiu" : "addiu", "y,x,4", yreg
, xreg
);
7621 if (imm_expr
.X_op
!= O_constant
)
7622 as_bad (_("Unsupported large constant"));
7623 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7624 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "addiu",
7629 if (imm_expr
.X_op
!= O_constant
)
7630 as_bad (_("Unsupported large constant"));
7631 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7632 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "daddiu",
7655 goto do_reverse_branch
;
7659 goto do_reverse_branch
;
7671 goto do_reverse_branch
;
7682 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "x,y",
7684 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
7711 goto do_addone_branch_i
;
7716 goto do_addone_branch_i
;
7731 goto do_addone_branch_i
;
7738 if (imm_expr
.X_op
!= O_constant
)
7739 as_bad (_("Unsupported large constant"));
7740 ++imm_expr
.X_add_number
;
7743 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, s3
, xreg
);
7744 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
7748 expr1
.X_add_number
= 0;
7749 macro_build ((char *) NULL
, &icnt
, &expr1
, "slti", "x,8", yreg
);
7751 move_register (&icnt
, xreg
, yreg
);
7752 expr1
.X_add_number
= 2;
7753 macro_build ((char *) NULL
, &icnt
, &expr1
, "bteqz", "p");
7754 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7755 "neg", "x,w", xreg
, xreg
);
7759 /* For consistency checking, verify that all bits are specified either
7760 by the match/mask part of the instruction definition, or by the
7763 validate_mips_insn (opc
)
7764 const struct mips_opcode
*opc
;
7766 const char *p
= opc
->args
;
7768 unsigned long used_bits
= opc
->mask
;
7770 if ((used_bits
& opc
->match
) != opc
->match
)
7772 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
7773 opc
->name
, opc
->args
);
7776 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
7783 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7784 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7786 case 'B': USE_BITS (OP_MASK_CODE20
, OP_SH_CODE20
); break;
7787 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
7788 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
7789 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7791 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7792 case 'H': USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
7794 case 'J': USE_BITS (OP_MASK_CODE19
, OP_SH_CODE19
); break;
7796 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
7797 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
7798 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
7799 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7800 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7801 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7802 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7803 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
7804 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7805 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
7806 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7808 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
7809 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
7810 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7811 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
7813 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7814 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7815 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
7816 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7817 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7818 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7819 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
7820 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7821 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7824 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
7825 case 'U': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
7826 USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7828 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
7829 c
, opc
->name
, opc
->args
);
7833 if (used_bits
!= 0xffffffff)
7835 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
7836 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
7842 /* This routine assembles an instruction into its binary format. As a
7843 side effect, it sets one of the global variables imm_reloc or
7844 offset_reloc to the type of relocation to do if one of the operands
7845 is an address expression. */
7850 struct mips_cl_insn
*ip
;
7855 struct mips_opcode
*insn
;
7858 unsigned int lastregno
= 0;
7864 /* If the instruction contains a '.', we first try to match an instruction
7865 including the '.'. Then we try again without the '.'. */
7867 for (s
= str
; *s
!= '\0' && !ISSPACE (*s
); ++s
)
7870 /* If we stopped on whitespace, then replace the whitespace with null for
7871 the call to hash_find. Save the character we replaced just in case we
7872 have to re-parse the instruction. */
7879 insn
= (struct mips_opcode
*) hash_find (op_hash
, str
);
7881 /* If we didn't find the instruction in the opcode table, try again, but
7882 this time with just the instruction up to, but not including the
7886 /* Restore the character we overwrite above (if any). */
7890 /* Scan up to the first '.' or whitespace. */
7892 *s
!= '\0' && *s
!= '.' && !ISSPACE (*s
);
7896 /* If we did not find a '.', then we can quit now. */
7899 insn_error
= "unrecognized opcode";
7903 /* Lookup the instruction in the hash table. */
7905 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
7907 insn_error
= "unrecognized opcode";
7917 assert (strcmp (insn
->name
, str
) == 0);
7919 if (OPCODE_IS_MEMBER (insn
,
7921 | (mips_opts
.ase_mips3d
? INSN_MIPS3D
: 0)),
7927 if (insn
->pinfo
!= INSN_MACRO
)
7929 if (mips_arch
== CPU_R4650
&& (insn
->pinfo
& FP_D
) != 0)
7935 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
7936 && strcmp (insn
->name
, insn
[1].name
) == 0)
7945 static char buf
[100];
7947 _("opcode not supported on this processor: %s (%s)"),
7948 mips_cpu_to_str (mips_arch
),
7949 mips_isa_to_str (mips_opts
.isa
));
7960 ip
->insn_opcode
= insn
->match
;
7962 for (args
= insn
->args
;; ++args
)
7964 s
+= strspn (s
, " \t");
7967 case '\0': /* end of args */
7980 ip
->insn_opcode
|= lastregno
<< OP_SH_RS
;
7984 ip
->insn_opcode
|= lastregno
<< OP_SH_RT
;
7988 ip
->insn_opcode
|= lastregno
<< OP_SH_FT
;
7992 ip
->insn_opcode
|= lastregno
<< OP_SH_FS
;
7998 /* Handle optional base register.
7999 Either the base register is omitted or
8000 we must have a left paren. */
8001 /* This is dependent on the next operand specifier
8002 is a base register specification. */
8003 assert (args
[1] == 'b' || args
[1] == '5'
8004 || args
[1] == '-' || args
[1] == '4');
8008 case ')': /* these must match exactly */
8013 case '<': /* must be at least one digit */
8015 * According to the manual, if the shift amount is greater
8016 * than 31 or less than 0, then the shift amount should be
8017 * mod 32. In reality the mips assembler issues an error.
8018 * We issue a warning and mask out all but the low 5 bits.
8020 my_getExpression (&imm_expr
, s
);
8021 check_absolute_expr (ip
, &imm_expr
);
8022 if ((unsigned long) imm_expr
.X_add_number
> 31)
8024 as_warn (_("Improper shift amount (%ld)"),
8025 (long) imm_expr
.X_add_number
);
8026 imm_expr
.X_add_number
&= OP_MASK_SHAMT
;
8028 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_SHAMT
;
8029 imm_expr
.X_op
= O_absent
;
8033 case '>': /* shift amount minus 32 */
8034 my_getExpression (&imm_expr
, s
);
8035 check_absolute_expr (ip
, &imm_expr
);
8036 if ((unsigned long) imm_expr
.X_add_number
< 32
8037 || (unsigned long) imm_expr
.X_add_number
> 63)
8039 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << OP_SH_SHAMT
;
8040 imm_expr
.X_op
= O_absent
;
8044 case 'k': /* cache code */
8045 case 'h': /* prefx code */
8046 my_getExpression (&imm_expr
, s
);
8047 check_absolute_expr (ip
, &imm_expr
);
8048 if ((unsigned long) imm_expr
.X_add_number
> 31)
8050 as_warn (_("Invalid value for `%s' (%lu)"),
8052 (unsigned long) imm_expr
.X_add_number
);
8053 imm_expr
.X_add_number
&= 0x1f;
8056 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
8058 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
8059 imm_expr
.X_op
= O_absent
;
8063 case 'c': /* break code */
8064 my_getExpression (&imm_expr
, s
);
8065 check_absolute_expr (ip
, &imm_expr
);
8066 if ((unsigned) imm_expr
.X_add_number
> 1023)
8068 as_warn (_("Illegal break code (%ld)"),
8069 (long) imm_expr
.X_add_number
);
8070 imm_expr
.X_add_number
&= OP_MASK_CODE
;
8072 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE
;
8073 imm_expr
.X_op
= O_absent
;
8077 case 'q': /* lower break code */
8078 my_getExpression (&imm_expr
, s
);
8079 check_absolute_expr (ip
, &imm_expr
);
8080 if ((unsigned) imm_expr
.X_add_number
> 1023)
8082 as_warn (_("Illegal lower break code (%ld)"),
8083 (long) imm_expr
.X_add_number
);
8084 imm_expr
.X_add_number
&= OP_MASK_CODE2
;
8086 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE2
;
8087 imm_expr
.X_op
= O_absent
;
8091 case 'B': /* 20-bit syscall/break code. */
8092 my_getExpression (&imm_expr
, s
);
8093 check_absolute_expr (ip
, &imm_expr
);
8094 if ((unsigned) imm_expr
.X_add_number
> OP_MASK_CODE20
)
8095 as_warn (_("Illegal 20-bit code (%ld)"),
8096 (long) imm_expr
.X_add_number
);
8097 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE20
;
8098 imm_expr
.X_op
= O_absent
;
8102 case 'C': /* Coprocessor code */
8103 my_getExpression (&imm_expr
, s
);
8104 check_absolute_expr (ip
, &imm_expr
);
8105 if ((unsigned long) imm_expr
.X_add_number
>= (1 << 25))
8107 as_warn (_("Coproccesor code > 25 bits (%ld)"),
8108 (long) imm_expr
.X_add_number
);
8109 imm_expr
.X_add_number
&= ((1 << 25) - 1);
8111 ip
->insn_opcode
|= imm_expr
.X_add_number
;
8112 imm_expr
.X_op
= O_absent
;
8116 case 'J': /* 19-bit wait code. */
8117 my_getExpression (&imm_expr
, s
);
8118 check_absolute_expr (ip
, &imm_expr
);
8119 if ((unsigned) imm_expr
.X_add_number
> OP_MASK_CODE19
)
8120 as_warn (_("Illegal 19-bit code (%ld)"),
8121 (long) imm_expr
.X_add_number
);
8122 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE19
;
8123 imm_expr
.X_op
= O_absent
;
8127 case 'P': /* Performance register */
8128 my_getExpression (&imm_expr
, s
);
8129 check_absolute_expr (ip
, &imm_expr
);
8130 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
8132 as_warn (_("Invalid performance register (%ld)"),
8133 (long) imm_expr
.X_add_number
);
8134 imm_expr
.X_add_number
&= OP_MASK_PERFREG
;
8136 ip
->insn_opcode
|= (imm_expr
.X_add_number
<< OP_SH_PERFREG
);
8137 imm_expr
.X_op
= O_absent
;
8141 case 'b': /* base register */
8142 case 'd': /* destination register */
8143 case 's': /* source register */
8144 case 't': /* target register */
8145 case 'r': /* both target and source */
8146 case 'v': /* both dest and source */
8147 case 'w': /* both dest and target */
8148 case 'E': /* coprocessor target register */
8149 case 'G': /* coprocessor destination register */
8150 case 'x': /* ignore register name */
8151 case 'z': /* must be zero register */
8152 case 'U': /* destination register (clo/clz). */
8167 while (ISDIGIT (*s
));
8169 as_bad (_("Invalid register number (%d)"), regno
);
8171 else if (*args
== 'E' || *args
== 'G')
8175 if (s
[1] == 'f' && s
[2] == 'p')
8180 else if (s
[1] == 's' && s
[2] == 'p')
8185 else if (s
[1] == 'g' && s
[2] == 'p')
8190 else if (s
[1] == 'a' && s
[2] == 't')
8195 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
8200 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
8205 else if (itbl_have_entries
)
8210 p
= s
+ 1; /* advance past '$' */
8211 n
= itbl_get_field (&p
); /* n is name */
8213 /* See if this is a register defined in an
8215 if (itbl_get_reg_val (n
, &r
))
8217 /* Get_field advances to the start of
8218 the next field, so we need to back
8219 rack to the end of the last field. */
8223 s
= strchr (s
, '\0');
8236 as_warn (_("Used $at without \".set noat\""));
8242 if (c
== 'r' || c
== 'v' || c
== 'w')
8249 /* 'z' only matches $0. */
8250 if (c
== 'z' && regno
!= 0)
8253 /* Now that we have assembled one operand, we use the args string
8254 * to figure out where it goes in the instruction. */
8261 ip
->insn_opcode
|= regno
<< OP_SH_RS
;
8265 ip
->insn_opcode
|= regno
<< OP_SH_RD
;
8268 ip
->insn_opcode
|= regno
<< OP_SH_RD
;
8269 ip
->insn_opcode
|= regno
<< OP_SH_RT
;
8274 ip
->insn_opcode
|= regno
<< OP_SH_RT
;
8277 /* This case exists because on the r3000 trunc
8278 expands into a macro which requires a gp
8279 register. On the r6000 or r4000 it is
8280 assembled into a single instruction which
8281 ignores the register. Thus the insn version
8282 is MIPS_ISA2 and uses 'x', and the macro
8283 version is MIPS_ISA1 and uses 't'. */
8286 /* This case is for the div instruction, which
8287 acts differently if the destination argument
8288 is $0. This only matches $0, and is checked
8289 outside the switch. */
8292 /* Itbl operand; not yet implemented. FIXME ?? */
8294 /* What about all other operands like 'i', which
8295 can be specified in the opcode table? */
8305 ip
->insn_opcode
|= lastregno
<< OP_SH_RS
;
8308 ip
->insn_opcode
|= lastregno
<< OP_SH_RT
;
8313 case 'D': /* floating point destination register */
8314 case 'S': /* floating point source register */
8315 case 'T': /* floating point target register */
8316 case 'R': /* floating point source register */
8320 if (s
[0] == '$' && s
[1] == 'f'
8331 while (ISDIGIT (*s
));
8334 as_bad (_("Invalid float register number (%d)"), regno
);
8336 if ((regno
& 1) != 0
8338 && ! (strcmp (str
, "mtc1") == 0
8339 || strcmp (str
, "mfc1") == 0
8340 || strcmp (str
, "lwc1") == 0
8341 || strcmp (str
, "swc1") == 0
8342 || strcmp (str
, "l.s") == 0
8343 || strcmp (str
, "s.s") == 0))
8344 as_warn (_("Float register should be even, was %d"),
8352 if (c
== 'V' || c
== 'W')
8362 ip
->insn_opcode
|= regno
<< OP_SH_FD
;
8366 ip
->insn_opcode
|= regno
<< OP_SH_FS
;
8370 ip
->insn_opcode
|= regno
<< OP_SH_FT
;
8373 ip
->insn_opcode
|= regno
<< OP_SH_FR
;
8383 ip
->insn_opcode
|= lastregno
<< OP_SH_FS
;
8386 ip
->insn_opcode
|= lastregno
<< OP_SH_FT
;
8392 my_getExpression (&imm_expr
, s
);
8393 if (imm_expr
.X_op
!= O_big
8394 && imm_expr
.X_op
!= O_constant
)
8395 insn_error
= _("absolute expression required");
8400 my_getExpression (&offset_expr
, s
);
8401 *imm_reloc
= BFD_RELOC_32
;
8414 unsigned char temp
[8];
8416 unsigned int length
;
8421 /* These only appear as the last operand in an
8422 instruction, and every instruction that accepts
8423 them in any variant accepts them in all variants.
8424 This means we don't have to worry about backing out
8425 any changes if the instruction does not match.
8427 The difference between them is the size of the
8428 floating point constant and where it goes. For 'F'
8429 and 'L' the constant is 64 bits; for 'f' and 'l' it
8430 is 32 bits. Where the constant is placed is based
8431 on how the MIPS assembler does things:
8434 f -- immediate value
8437 The .lit4 and .lit8 sections are only used if
8438 permitted by the -G argument.
8440 When generating embedded PIC code, we use the
8441 .lit8 section but not the .lit4 section (we can do
8442 .lit4 inline easily; we need to put .lit8
8443 somewhere in the data segment, and using .lit8
8444 permits the linker to eventually combine identical
8447 The code below needs to know whether the target register
8448 is 32 or 64 bits wide. It relies on the fact 'f' and
8449 'F' are used with GPR-based instructions and 'l' and
8450 'L' are used with FPR-based instructions. */
8452 f64
= *args
== 'F' || *args
== 'L';
8453 using_gprs
= *args
== 'F' || *args
== 'f';
8455 save_in
= input_line_pointer
;
8456 input_line_pointer
= s
;
8457 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
8459 s
= input_line_pointer
;
8460 input_line_pointer
= save_in
;
8461 if (err
!= NULL
&& *err
!= '\0')
8463 as_bad (_("Bad floating point constant: %s"), err
);
8464 memset (temp
, '\0', sizeof temp
);
8465 length
= f64
? 8 : 4;
8468 assert (length
== (unsigned) (f64
? 8 : 4));
8472 && (! USE_GLOBAL_POINTER_OPT
8473 || mips_pic
== EMBEDDED_PIC
8474 || g_switch_value
< 4
8475 || (temp
[0] == 0 && temp
[1] == 0)
8476 || (temp
[2] == 0 && temp
[3] == 0))))
8478 imm_expr
.X_op
= O_constant
;
8479 if (! target_big_endian
)
8480 imm_expr
.X_add_number
= bfd_getl32 (temp
);
8482 imm_expr
.X_add_number
= bfd_getb32 (temp
);
8485 && ! mips_disable_float_construction
8486 /* Constants can only be constructed in GPRs and
8487 copied to FPRs if the GPRs are at least as wide
8488 as the FPRs. Force the constant into memory if
8489 we are using 64-bit FPRs but the GPRs are only
8492 || ! (HAVE_64BIT_FPRS
&& HAVE_32BIT_GPRS
))
8493 && ((temp
[0] == 0 && temp
[1] == 0)
8494 || (temp
[2] == 0 && temp
[3] == 0))
8495 && ((temp
[4] == 0 && temp
[5] == 0)
8496 || (temp
[6] == 0 && temp
[7] == 0)))
8498 /* The value is simple enough to load with a couple of
8499 instructions. If using 32-bit registers, set
8500 imm_expr to the high order 32 bits and offset_expr to
8501 the low order 32 bits. Otherwise, set imm_expr to
8502 the entire 64 bit constant. */
8503 if (using_gprs
? HAVE_32BIT_GPRS
: HAVE_32BIT_FPRS
)
8505 imm_expr
.X_op
= O_constant
;
8506 offset_expr
.X_op
= O_constant
;
8507 if (! target_big_endian
)
8509 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
8510 offset_expr
.X_add_number
= bfd_getl32 (temp
);
8514 imm_expr
.X_add_number
= bfd_getb32 (temp
);
8515 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
8517 if (offset_expr
.X_add_number
== 0)
8518 offset_expr
.X_op
= O_absent
;
8520 else if (sizeof (imm_expr
.X_add_number
) > 4)
8522 imm_expr
.X_op
= O_constant
;
8523 if (! target_big_endian
)
8524 imm_expr
.X_add_number
= bfd_getl64 (temp
);
8526 imm_expr
.X_add_number
= bfd_getb64 (temp
);
8530 imm_expr
.X_op
= O_big
;
8531 imm_expr
.X_add_number
= 4;
8532 if (! target_big_endian
)
8534 generic_bignum
[0] = bfd_getl16 (temp
);
8535 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
8536 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
8537 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
8541 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
8542 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
8543 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
8544 generic_bignum
[3] = bfd_getb16 (temp
);
8550 const char *newname
;
8553 /* Switch to the right section. */
8555 subseg
= now_subseg
;
8558 default: /* unused default case avoids warnings. */
8560 newname
= RDATA_SECTION_NAME
;
8561 if ((USE_GLOBAL_POINTER_OPT
&& g_switch_value
>= 8)
8562 || mips_pic
== EMBEDDED_PIC
)
8566 if (mips_pic
== EMBEDDED_PIC
)
8569 newname
= RDATA_SECTION_NAME
;
8572 assert (!USE_GLOBAL_POINTER_OPT
8573 || g_switch_value
>= 4);
8577 new_seg
= subseg_new (newname
, (subsegT
) 0);
8578 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
8579 bfd_set_section_flags (stdoutput
, new_seg
,
8584 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
8585 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
8586 && strcmp (TARGET_OS
, "elf") != 0)
8587 record_alignment (new_seg
, 4);
8589 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
8591 as_bad (_("Can't use floating point insn in this section"));
8593 /* Set the argument to the current address in the
8595 offset_expr
.X_op
= O_symbol
;
8596 offset_expr
.X_add_symbol
=
8597 symbol_new ("L0\001", now_seg
,
8598 (valueT
) frag_now_fix (), frag_now
);
8599 offset_expr
.X_add_number
= 0;
8601 /* Put the floating point number into the section. */
8602 p
= frag_more ((int) length
);
8603 memcpy (p
, temp
, length
);
8605 /* Switch back to the original section. */
8606 subseg_set (seg
, subseg
);
8611 case 'i': /* 16 bit unsigned immediate */
8612 case 'j': /* 16 bit signed immediate */
8613 *imm_reloc
= BFD_RELOC_LO16
;
8614 c
= my_getSmallExpression (&imm_expr
, s
);
8619 if (imm_expr
.X_op
== O_constant
)
8620 imm_expr
.X_add_number
=
8621 (imm_expr
.X_add_number
>> 16) & 0xffff;
8623 else if (c
== S_EX_HIGHEST
)
8624 *imm_reloc
= BFD_RELOC_MIPS_HIGHEST
;
8625 else if (c
== S_EX_HIGHER
)
8626 *imm_reloc
= BFD_RELOC_MIPS_HIGHER
;
8627 else if (c
== S_EX_GP_REL
)
8629 /* This occurs in NewABI only. */
8630 c
= my_getSmallExpression (&imm_expr
, s
);
8632 as_bad (_("bad composition of relocations"));
8635 c
= my_getSmallExpression (&imm_expr
, s
);
8637 as_bad (_("bad composition of relocations"));
8640 imm_reloc
[0] = BFD_RELOC_GPREL16
;
8641 imm_reloc
[1] = BFD_RELOC_MIPS_SUB
;
8642 imm_reloc
[2] = BFD_RELOC_LO16
;
8647 else if (c
== S_EX_HI
)
8649 *imm_reloc
= BFD_RELOC_HI16_S
;
8650 imm_unmatched_hi
= true;
8653 *imm_reloc
= BFD_RELOC_HI16
;
8655 else if (imm_expr
.X_op
== O_constant
)
8656 imm_expr
.X_add_number
&= 0xffff;
8660 if ((c
== S_EX_NONE
&& imm_expr
.X_op
!= O_constant
)
8661 || ((imm_expr
.X_add_number
< 0
8662 || imm_expr
.X_add_number
>= 0x10000)
8663 && imm_expr
.X_op
== O_constant
))
8665 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
8666 !strcmp (insn
->name
, insn
[1].name
))
8668 if (imm_expr
.X_op
== O_constant
8669 || imm_expr
.X_op
== O_big
)
8670 as_bad (_("16 bit expression not in range 0..65535"));
8678 /* The upper bound should be 0x8000, but
8679 unfortunately the MIPS assembler accepts numbers
8680 from 0x8000 to 0xffff and sign extends them, and
8681 we want to be compatible. We only permit this
8682 extended range for an instruction which does not
8683 provide any further alternates, since those
8684 alternates may handle other cases. People should
8685 use the numbers they mean, rather than relying on
8686 a mysterious sign extension. */
8687 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
8688 strcmp (insn
->name
, insn
[1].name
) == 0);
8693 if ((c
== S_EX_NONE
&& imm_expr
.X_op
!= O_constant
)
8694 || ((imm_expr
.X_add_number
< -0x8000
8695 || imm_expr
.X_add_number
>= max
)
8696 && imm_expr
.X_op
== O_constant
)
8698 && imm_expr
.X_add_number
< 0
8700 && imm_expr
.X_unsigned
8701 && sizeof (imm_expr
.X_add_number
) <= 4))
8705 if (imm_expr
.X_op
== O_constant
8706 || imm_expr
.X_op
== O_big
)
8707 as_bad (_("16 bit expression not in range -32768..32767"));
8713 case 'o': /* 16 bit offset */
8714 c
= my_getSmallExpression (&offset_expr
, s
);
8716 /* If this value won't fit into a 16 bit offset, then go
8717 find a macro that will generate the 32 bit offset
8720 && (offset_expr
.X_op
!= O_constant
8721 || offset_expr
.X_add_number
>= 0x8000
8722 || offset_expr
.X_add_number
< -0x8000))
8727 if (offset_expr
.X_op
!= O_constant
)
8729 offset_expr
.X_add_number
=
8730 (offset_expr
.X_add_number
>> 16) & 0xffff;
8732 *offset_reloc
= BFD_RELOC_LO16
;
8736 case 'p': /* pc relative offset */
8737 if (mips_pic
== EMBEDDED_PIC
)
8738 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
8740 *offset_reloc
= BFD_RELOC_16_PCREL
;
8741 my_getExpression (&offset_expr
, s
);
8745 case 'u': /* upper 16 bits */
8746 c
= my_getSmallExpression (&imm_expr
, s
);
8747 *imm_reloc
= BFD_RELOC_LO16
;
8752 if (imm_expr
.X_op
== O_constant
)
8753 imm_expr
.X_add_number
=
8754 (imm_expr
.X_add_number
>> 16) & 0xffff;
8755 else if (c
== S_EX_HI
)
8757 *imm_reloc
= BFD_RELOC_HI16_S
;
8758 imm_unmatched_hi
= true;
8761 else if (c
== S_EX_HIGHEST
)
8762 *imm_reloc
= BFD_RELOC_MIPS_HIGHEST
;
8763 else if (c
== S_EX_GP_REL
)
8765 /* This occurs in NewABI only. */
8766 c
= my_getSmallExpression (&imm_expr
, s
);
8768 as_bad (_("bad composition of relocations"));
8771 c
= my_getSmallExpression (&imm_expr
, s
);
8773 as_bad (_("bad composition of relocations"));
8776 imm_reloc
[0] = BFD_RELOC_GPREL16
;
8777 imm_reloc
[1] = BFD_RELOC_MIPS_SUB
;
8778 imm_reloc
[2] = BFD_RELOC_HI16_S
;
8784 *imm_reloc
= BFD_RELOC_HI16
;
8786 else if (imm_expr
.X_op
== O_constant
)
8787 imm_expr
.X_add_number
&= 0xffff;
8789 if (imm_expr
.X_op
== O_constant
8790 && (imm_expr
.X_add_number
< 0
8791 || imm_expr
.X_add_number
>= 0x10000))
8792 as_bad (_("lui expression not in range 0..65535"));
8796 case 'a': /* 26 bit address */
8797 my_getExpression (&offset_expr
, s
);
8799 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
8802 case 'N': /* 3 bit branch condition code */
8803 case 'M': /* 3 bit compare condition code */
8804 if (strncmp (s
, "$fcc", 4) != 0)
8814 while (ISDIGIT (*s
));
8816 as_bad (_("invalid condition code register $fcc%d"), regno
);
8818 ip
->insn_opcode
|= regno
<< OP_SH_BCC
;
8820 ip
->insn_opcode
|= regno
<< OP_SH_CCC
;
8824 if (s
[0] == '0' && (s
[1] == 'x' || s
[1] == 'X'))
8835 while (ISDIGIT (*s
));
8838 c
= 8; /* Invalid sel value. */
8841 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
8842 ip
->insn_opcode
|= c
;
8846 as_bad (_("bad char = '%c'\n"), *args
);
8851 /* Args don't match. */
8852 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
8853 !strcmp (insn
->name
, insn
[1].name
))
8857 insn_error
= _("illegal operands");
8862 insn_error
= _("illegal operands");
8867 /* This routine assembles an instruction into its binary format when
8868 assembling for the mips16. As a side effect, it sets one of the
8869 global variables imm_reloc or offset_reloc to the type of
8870 relocation to do if one of the operands is an address expression.
8871 It also sets mips16_small and mips16_ext if the user explicitly
8872 requested a small or extended instruction. */
8877 struct mips_cl_insn
*ip
;
8881 struct mips_opcode
*insn
;
8884 unsigned int lastregno
= 0;
8889 mips16_small
= false;
8892 for (s
= str
; ISLOWER (*s
); ++s
)
8904 if (s
[1] == 't' && s
[2] == ' ')
8907 mips16_small
= true;
8911 else if (s
[1] == 'e' && s
[2] == ' ')
8920 insn_error
= _("unknown opcode");
8924 if (mips_opts
.noautoextend
&& ! mips16_ext
)
8925 mips16_small
= true;
8927 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
8929 insn_error
= _("unrecognized opcode");
8936 assert (strcmp (insn
->name
, str
) == 0);
8939 ip
->insn_opcode
= insn
->match
;
8940 ip
->use_extend
= false;
8941 imm_expr
.X_op
= O_absent
;
8942 imm_reloc
[0] = BFD_RELOC_UNUSED
;
8943 imm_reloc
[1] = BFD_RELOC_UNUSED
;
8944 imm_reloc
[2] = BFD_RELOC_UNUSED
;
8945 offset_expr
.X_op
= O_absent
;
8946 offset_reloc
[0] = BFD_RELOC_UNUSED
;
8947 offset_reloc
[1] = BFD_RELOC_UNUSED
;
8948 offset_reloc
[2] = BFD_RELOC_UNUSED
;
8949 for (args
= insn
->args
; 1; ++args
)
8956 /* In this switch statement we call break if we did not find
8957 a match, continue if we did find a match, or return if we
8966 /* Stuff the immediate value in now, if we can. */
8967 if (imm_expr
.X_op
== O_constant
8968 && *imm_reloc
> BFD_RELOC_UNUSED
8969 && insn
->pinfo
!= INSN_MACRO
)
8971 mips16_immed (NULL
, 0, *imm_reloc
- BFD_RELOC_UNUSED
,
8972 imm_expr
.X_add_number
, true, mips16_small
,
8973 mips16_ext
, &ip
->insn_opcode
,
8974 &ip
->use_extend
, &ip
->extend
);
8975 imm_expr
.X_op
= O_absent
;
8976 *imm_reloc
= BFD_RELOC_UNUSED
;
8990 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
8993 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
9009 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
9011 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
9038 while (ISDIGIT (*s
));
9041 as_bad (_("invalid register number (%d)"), regno
);
9047 if (s
[1] == 'f' && s
[2] == 'p')
9052 else if (s
[1] == 's' && s
[2] == 'p')
9057 else if (s
[1] == 'g' && s
[2] == 'p')
9062 else if (s
[1] == 'a' && s
[2] == 't')
9067 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
9072 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
9085 if (c
== 'v' || c
== 'w')
9087 regno
= mips16_to_32_reg_map
[lastregno
];
9101 regno
= mips32_to_16_reg_map
[regno
];
9106 regno
= ILLEGAL_REG
;
9111 regno
= ILLEGAL_REG
;
9116 regno
= ILLEGAL_REG
;
9121 if (regno
== AT
&& ! mips_opts
.noat
)
9122 as_warn (_("used $at without \".set noat\""));
9129 if (regno
== ILLEGAL_REG
)
9136 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RX
;
9140 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RY
;
9143 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RZ
;
9146 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_MOVE32Z
;
9152 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REGR32
;
9155 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
9156 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
9166 if (strncmp (s
, "$pc", 3) == 0)
9190 && strncmp (s
+ 1, "gprel(", sizeof "gprel(" - 1) == 0)
9192 /* This is %gprel(SYMBOL). We need to read SYMBOL,
9193 and generate the appropriate reloc. If the text
9194 inside %gprel is not a symbol name with an
9195 optional offset, then we generate a normal reloc
9196 and will probably fail later. */
9197 my_getExpression (&imm_expr
, s
+ sizeof "%gprel" - 1);
9198 if (imm_expr
.X_op
== O_symbol
)
9201 *imm_reloc
= BFD_RELOC_MIPS16_GPREL
;
9203 ip
->use_extend
= true;
9210 /* Just pick up a normal expression. */
9211 my_getExpression (&imm_expr
, s
);
9214 if (imm_expr
.X_op
== O_register
)
9216 /* What we thought was an expression turned out to
9219 if (s
[0] == '(' && args
[1] == '(')
9221 /* It looks like the expression was omitted
9222 before a register indirection, which means
9223 that the expression is implicitly zero. We
9224 still set up imm_expr, so that we handle
9225 explicit extensions correctly. */
9226 imm_expr
.X_op
= O_constant
;
9227 imm_expr
.X_add_number
= 0;
9228 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9235 /* We need to relax this instruction. */
9236 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9245 /* We use offset_reloc rather than imm_reloc for the PC
9246 relative operands. This lets macros with both
9247 immediate and address operands work correctly. */
9248 my_getExpression (&offset_expr
, s
);
9250 if (offset_expr
.X_op
== O_register
)
9253 /* We need to relax this instruction. */
9254 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9258 case '6': /* break code */
9259 my_getExpression (&imm_expr
, s
);
9260 check_absolute_expr (ip
, &imm_expr
);
9261 if ((unsigned long) imm_expr
.X_add_number
> 63)
9263 as_warn (_("Invalid value for `%s' (%lu)"),
9265 (unsigned long) imm_expr
.X_add_number
);
9266 imm_expr
.X_add_number
&= 0x3f;
9268 ip
->insn_opcode
|= imm_expr
.X_add_number
<< MIPS16OP_SH_IMM6
;
9269 imm_expr
.X_op
= O_absent
;
9273 case 'a': /* 26 bit address */
9274 my_getExpression (&offset_expr
, s
);
9276 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
9277 ip
->insn_opcode
<<= 16;
9280 case 'l': /* register list for entry macro */
9281 case 'L': /* register list for exit macro */
9291 int freg
, reg1
, reg2
;
9293 while (*s
== ' ' || *s
== ',')
9297 as_bad (_("can't parse register list"));
9309 while (ISDIGIT (*s
))
9331 as_bad (_("invalid register list"));
9336 while (ISDIGIT (*s
))
9343 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
9348 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
9353 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
9354 mask
|= (reg2
- 3) << 3;
9355 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
9356 mask
|= (reg2
- 15) << 1;
9357 else if (reg1
== RA
&& reg2
== RA
)
9361 as_bad (_("invalid register list"));
9365 /* The mask is filled in in the opcode table for the
9366 benefit of the disassembler. We remove it before
9367 applying the actual mask. */
9368 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
9369 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
9373 case 'e': /* extend code */
9374 my_getExpression (&imm_expr
, s
);
9375 check_absolute_expr (ip
, &imm_expr
);
9376 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
9378 as_warn (_("Invalid value for `%s' (%lu)"),
9380 (unsigned long) imm_expr
.X_add_number
);
9381 imm_expr
.X_add_number
&= 0x7ff;
9383 ip
->insn_opcode
|= imm_expr
.X_add_number
;
9384 imm_expr
.X_op
= O_absent
;
9394 /* Args don't match. */
9395 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
9396 strcmp (insn
->name
, insn
[1].name
) == 0)
9403 insn_error
= _("illegal operands");
9409 /* This structure holds information we know about a mips16 immediate
9412 struct mips16_immed_operand
9414 /* The type code used in the argument string in the opcode table. */
9416 /* The number of bits in the short form of the opcode. */
9418 /* The number of bits in the extended form of the opcode. */
9420 /* The amount by which the short form is shifted when it is used;
9421 for example, the sw instruction has a shift count of 2. */
9423 /* The amount by which the short form is shifted when it is stored
9424 into the instruction code. */
9426 /* Non-zero if the short form is unsigned. */
9428 /* Non-zero if the extended form is unsigned. */
9430 /* Non-zero if the value is PC relative. */
9434 /* The mips16 immediate operand types. */
9436 static const struct mips16_immed_operand mips16_immed_operands
[] =
9438 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
9439 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
9440 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
9441 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
9442 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
9443 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9444 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9445 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9446 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9447 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
9448 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9449 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9450 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9451 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
9452 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
9453 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
9454 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
9455 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
9456 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
9457 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
9458 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
9461 #define MIPS16_NUM_IMMED \
9462 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
9464 /* Handle a mips16 instruction with an immediate value. This or's the
9465 small immediate value into *INSN. It sets *USE_EXTEND to indicate
9466 whether an extended value is needed; if one is needed, it sets
9467 *EXTEND to the value. The argument type is TYPE. The value is VAL.
9468 If SMALL is true, an unextended opcode was explicitly requested.
9469 If EXT is true, an extended opcode was explicitly requested. If
9470 WARN is true, warn if EXT does not match reality. */
9473 mips16_immed (file
, line
, type
, val
, warn
, small
, ext
, insn
, use_extend
,
9482 unsigned long *insn
;
9483 boolean
*use_extend
;
9484 unsigned short *extend
;
9486 register const struct mips16_immed_operand
*op
;
9487 int mintiny
, maxtiny
;
9490 op
= mips16_immed_operands
;
9491 while (op
->type
!= type
)
9494 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
9499 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
9502 maxtiny
= 1 << op
->nbits
;
9507 maxtiny
= (1 << op
->nbits
) - 1;
9512 mintiny
= - (1 << (op
->nbits
- 1));
9513 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
9516 /* Branch offsets have an implicit 0 in the lowest bit. */
9517 if (type
== 'p' || type
== 'q')
9520 if ((val
& ((1 << op
->shift
) - 1)) != 0
9521 || val
< (mintiny
<< op
->shift
)
9522 || val
> (maxtiny
<< op
->shift
))
9527 if (warn
&& ext
&& ! needext
)
9528 as_warn_where (file
, line
,
9529 _("extended operand requested but not required"));
9530 if (small
&& needext
)
9531 as_bad_where (file
, line
, _("invalid unextended operand value"));
9533 if (small
|| (! ext
&& ! needext
))
9537 *use_extend
= false;
9538 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
9539 insnval
<<= op
->op_shift
;
9544 long minext
, maxext
;
9550 maxext
= (1 << op
->extbits
) - 1;
9554 minext
= - (1 << (op
->extbits
- 1));
9555 maxext
= (1 << (op
->extbits
- 1)) - 1;
9557 if (val
< minext
|| val
> maxext
)
9558 as_bad_where (file
, line
,
9559 _("operand value out of range for instruction"));
9562 if (op
->extbits
== 16)
9564 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
9567 else if (op
->extbits
== 15)
9569 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
9574 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
9578 *extend
= (unsigned short) extval
;
9583 static struct percent_op_match
9586 const enum small_ex_type type
;
9591 {"%call_hi", S_EX_CALL_HI
},
9592 {"%call_lo", S_EX_CALL_LO
},
9593 {"%call16", S_EX_CALL16
},
9594 {"%got_disp", S_EX_GOT_DISP
},
9595 {"%got_page", S_EX_GOT_PAGE
},
9596 {"%got_ofst", S_EX_GOT_OFST
},
9597 {"%got_hi", S_EX_GOT_HI
},
9598 {"%got_lo", S_EX_GOT_LO
},
9600 {"%gp_rel", S_EX_GP_REL
},
9601 {"%half", S_EX_HALF
},
9602 {"%highest", S_EX_HIGHEST
},
9603 {"%higher", S_EX_HIGHER
},
9609 /* Parse small expression input. STR gets adjusted to eat up whitespace.
9610 It detects valid "%percent_op(...)" and "($reg)" strings. Percent_op's
9611 can be nested, this is handled by blanking the innermost, parsing the
9612 rest by subsequent calls. */
9615 my_getSmallParser (str
, len
, nestlevel
)
9621 *str
+= strspn (*str
, " \t");
9622 /* Check for expression in parentheses. */
9625 char *b
= *str
+ 1 + strspn (*str
+ 1, " \t");
9628 /* Check for base register. */
9632 && (e
= b
+ strcspn (b
, ") \t"))
9633 && e
- b
> 1 && e
- b
< 4)
9636 && ((b
[1] == 'f' && b
[2] == 'p')
9637 || (b
[1] == 's' && b
[2] == 'p')
9638 || (b
[1] == 'g' && b
[2] == 'p')
9639 || (b
[1] == 'a' && b
[2] == 't')
9641 && ISDIGIT (b
[2]))))
9642 || (ISDIGIT (b
[1])))
9644 *len
= strcspn (*str
, ")") + 1;
9645 return S_EX_REGISTER
;
9649 /* Check for percent_op (in parentheses). */
9650 else if (b
[0] == '%')
9653 return my_getPercentOp (str
, len
, nestlevel
);
9656 /* Some other expression in the parentheses, which can contain
9657 parentheses itself. Attempt to find the matching one. */
9663 for (s
= *str
+ 1; *s
&& pcnt
; s
++, (*len
)++)
9672 /* Check for percent_op (outside of parentheses). */
9673 else if (*str
[0] == '%')
9674 return my_getPercentOp (str
, len
, nestlevel
);
9676 /* Any other expression. */
9681 my_getPercentOp (str
, len
, nestlevel
)
9686 char *tmp
= *str
+ 1;
9689 while (ISALPHA (*tmp
) || *tmp
== '_')
9691 *tmp
= TOLOWER (*tmp
);
9694 while (i
< (sizeof (percent_op
) / sizeof (struct percent_op_match
)))
9696 if (strncmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)))
9700 int type
= percent_op
[i
].type
;
9702 /* Only %hi and %lo are allowed for OldABI. */
9703 if (! HAVE_NEWABI
&& type
!= S_EX_HI
&& type
!= S_EX_LO
)
9706 *len
= strlen (percent_op
[i
].str
);
9715 my_getSmallExpression (ep
, str
)
9719 static char *oldstr
= NULL
;
9725 /* Don't update oldstr if the last call had nested percent_op's. We need
9726 it to parse the outer ones later. */
9733 c
= my_getSmallParser (&str
, &len
, &nestlevel
);
9734 if (c
!= S_EX_NONE
&& c
!= S_EX_REGISTER
)
9737 while (c
!= S_EX_NONE
&& c
!= S_EX_REGISTER
);
9741 /* A percent_op was encountered. Don't try to get an expression if
9742 it is already blanked out. */
9743 if (*(str
+ strspn (str
+ 1, " )")) != ')')
9747 /* Let my_getExpression() stop at the closing parenthesis. */
9748 save
= *(str
+ len
);
9749 *(str
+ len
) = '\0';
9750 my_getExpression (ep
, str
);
9751 *(str
+ len
) = save
;
9755 /* Blank out including the % sign and the proper matching
9758 char *s
= strrchr (oldstr
, '%');
9761 for (end
= strchr (s
, '(') + 1; *end
&& pcnt
; end
++)
9765 else if (*end
== ')')
9769 memset (s
, ' ', end
- s
);
9773 expr_end
= str
+ len
;
9777 else if (c
== S_EX_NONE
)
9779 my_getExpression (ep
, str
);
9781 else if (c
== S_EX_REGISTER
)
9783 ep
->X_op
= O_constant
;
9785 ep
->X_add_symbol
= NULL
;
9786 ep
->X_op_symbol
= NULL
;
9787 ep
->X_add_number
= 0;
9791 as_fatal (_("internal error"));
9795 /* All percent_op's have been handled. */
9802 my_getExpression (ep
, str
)
9809 save_in
= input_line_pointer
;
9810 input_line_pointer
= str
;
9812 expr_end
= input_line_pointer
;
9813 input_line_pointer
= save_in
;
9815 /* If we are in mips16 mode, and this is an expression based on `.',
9816 then we bump the value of the symbol by 1 since that is how other
9817 text symbols are handled. We don't bother to handle complex
9818 expressions, just `.' plus or minus a constant. */
9819 if (mips_opts
.mips16
9820 && ep
->X_op
== O_symbol
9821 && strcmp (S_GET_NAME (ep
->X_add_symbol
), FAKE_LABEL_NAME
) == 0
9822 && S_GET_SEGMENT (ep
->X_add_symbol
) == now_seg
9823 && symbol_get_frag (ep
->X_add_symbol
) == frag_now
9824 && symbol_constant_p (ep
->X_add_symbol
)
9825 && (val
= S_GET_VALUE (ep
->X_add_symbol
)) == frag_now_fix ())
9826 S_SET_VALUE (ep
->X_add_symbol
, val
+ 1);
9829 /* Turn a string in input_line_pointer into a floating point constant
9830 of type TYPE, and store the appropriate bytes in *LITP. The number
9831 of LITTLENUMS emitted is stored in *SIZEP. An error message is
9832 returned, or NULL on OK. */
9835 md_atof (type
, litP
, sizeP
)
9841 LITTLENUM_TYPE words
[4];
9857 return _("bad call to md_atof");
9860 t
= atof_ieee (input_line_pointer
, type
, words
);
9862 input_line_pointer
= t
;
9866 if (! target_big_endian
)
9868 for (i
= prec
- 1; i
>= 0; i
--)
9870 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
9876 for (i
= 0; i
< prec
; i
++)
9878 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
9887 md_number_to_chars (buf
, val
, n
)
9892 if (target_big_endian
)
9893 number_to_chars_bigendian (buf
, val
, n
);
9895 number_to_chars_littleendian (buf
, val
, n
);
9899 static int support_64bit_objects(void)
9901 const char **list
, **l
;
9903 list
= bfd_target_list ();
9904 for (l
= list
; *l
!= NULL
; l
++)
9906 /* This is traditional mips */
9907 if (strcmp (*l
, "elf64-tradbigmips") == 0
9908 || strcmp (*l
, "elf64-tradlittlemips") == 0)
9910 if (strcmp (*l
, "elf64-bigmips") == 0
9911 || strcmp (*l
, "elf64-littlemips") == 0)
9915 return (*l
!= NULL
);
9917 #endif /* OBJ_ELF */
9919 CONST
char *md_shortopts
= "nO::g::G:";
9921 struct option md_longopts
[] =
9923 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
9924 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
9925 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
9926 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
9927 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
9928 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
9929 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
9930 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
9931 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
9932 #define OPTION_MIPS5 (OPTION_MD_BASE + 5)
9933 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
9934 #define OPTION_MIPS32 (OPTION_MD_BASE + 6)
9935 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
9936 #define OPTION_MIPS64 (OPTION_MD_BASE + 7)
9937 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
9938 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 8)
9939 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
9940 #define OPTION_TRAP (OPTION_MD_BASE + 9)
9941 {"trap", no_argument
, NULL
, OPTION_TRAP
},
9942 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
9943 #define OPTION_BREAK (OPTION_MD_BASE + 10)
9944 {"break", no_argument
, NULL
, OPTION_BREAK
},
9945 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
9946 #define OPTION_EB (OPTION_MD_BASE + 11)
9947 {"EB", no_argument
, NULL
, OPTION_EB
},
9948 #define OPTION_EL (OPTION_MD_BASE + 12)
9949 {"EL", no_argument
, NULL
, OPTION_EL
},
9950 #define OPTION_MIPS16 (OPTION_MD_BASE + 13)
9951 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
9952 #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 14)
9953 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
9954 #define OPTION_M7000_HILO_FIX (OPTION_MD_BASE + 15)
9955 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
9956 #define OPTION_MNO_7000_HILO_FIX (OPTION_MD_BASE + 16)
9957 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
9958 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
9959 #define OPTION_FP32 (OPTION_MD_BASE + 17)
9960 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
9961 #define OPTION_GP32 (OPTION_MD_BASE + 18)
9962 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
9963 #define OPTION_CONSTRUCT_FLOATS (OPTION_MD_BASE + 19)
9964 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
9965 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MD_BASE + 20)
9966 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
9967 #define OPTION_MARCH (OPTION_MD_BASE + 21)
9968 {"march", required_argument
, NULL
, OPTION_MARCH
},
9969 #define OPTION_MTUNE (OPTION_MD_BASE + 22)
9970 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
9971 #define OPTION_MCPU (OPTION_MD_BASE + 23)
9972 {"mcpu", required_argument
, NULL
, OPTION_MCPU
},
9973 #define OPTION_M4650 (OPTION_MD_BASE + 24)
9974 {"m4650", no_argument
, NULL
, OPTION_M4650
},
9975 #define OPTION_NO_M4650 (OPTION_MD_BASE + 25)
9976 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
9977 #define OPTION_M4010 (OPTION_MD_BASE + 26)
9978 {"m4010", no_argument
, NULL
, OPTION_M4010
},
9979 #define OPTION_NO_M4010 (OPTION_MD_BASE + 27)
9980 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
9981 #define OPTION_M4100 (OPTION_MD_BASE + 28)
9982 {"m4100", no_argument
, NULL
, OPTION_M4100
},
9983 #define OPTION_NO_M4100 (OPTION_MD_BASE + 29)
9984 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
9985 #define OPTION_M3900 (OPTION_MD_BASE + 30)
9986 {"m3900", no_argument
, NULL
, OPTION_M3900
},
9987 #define OPTION_NO_M3900 (OPTION_MD_BASE + 31)
9988 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
9989 #define OPTION_GP64 (OPTION_MD_BASE + 32)
9990 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
9991 #define OPTION_MIPS3D (OPTION_MD_BASE + 33)
9992 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
9993 #define OPTION_NO_MIPS3D (OPTION_MD_BASE + 34)
9994 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
9996 #define OPTION_ELF_BASE (OPTION_MD_BASE + 35)
9997 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
9998 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
9999 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
10000 #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1)
10001 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
10002 #define OPTION_XGOT (OPTION_ELF_BASE + 2)
10003 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
10004 #define OPTION_MABI (OPTION_ELF_BASE + 3)
10005 {"mabi", required_argument
, NULL
, OPTION_MABI
},
10006 #define OPTION_32 (OPTION_ELF_BASE + 4)
10007 {"32", no_argument
, NULL
, OPTION_32
},
10008 #define OPTION_N32 (OPTION_ELF_BASE + 5)
10009 {"n32", no_argument
, NULL
, OPTION_N32
},
10010 #define OPTION_64 (OPTION_ELF_BASE + 6)
10011 {"64", no_argument
, NULL
, OPTION_64
},
10012 #endif /* OBJ_ELF */
10013 {NULL
, no_argument
, NULL
, 0}
10015 size_t md_longopts_size
= sizeof (md_longopts
);
10018 md_parse_option (c
, arg
)
10024 case OPTION_CONSTRUCT_FLOATS
:
10025 mips_disable_float_construction
= 0;
10028 case OPTION_NO_CONSTRUCT_FLOATS
:
10029 mips_disable_float_construction
= 1;
10041 target_big_endian
= 1;
10045 target_big_endian
= 0;
10053 if (arg
&& arg
[1] == '0')
10063 mips_debug
= atoi (arg
);
10064 /* When the MIPS assembler sees -g or -g2, it does not do
10065 optimizations which limit full symbolic debugging. We take
10066 that to be equivalent to -O0. */
10067 if (mips_debug
== 2)
10072 mips_opts
.isa
= ISA_MIPS1
;
10076 mips_opts
.isa
= ISA_MIPS2
;
10080 mips_opts
.isa
= ISA_MIPS3
;
10084 mips_opts
.isa
= ISA_MIPS4
;
10088 mips_opts
.isa
= ISA_MIPS5
;
10091 case OPTION_MIPS32
:
10092 mips_opts
.isa
= ISA_MIPS32
;
10095 case OPTION_MIPS64
:
10096 mips_opts
.isa
= ISA_MIPS64
;
10103 int cpu
= CPU_UNKNOWN
;
10105 /* Identify the processor type. */
10106 if (strcasecmp (arg
, "default") != 0)
10108 const struct mips_cpu_info
*ci
;
10110 ci
= mips_cpu_info_from_name (arg
);
10111 if (ci
== NULL
|| ci
->is_isa
)
10116 as_fatal (_("invalid architecture -mtune=%s"), arg
);
10119 as_fatal (_("invalid architecture -march=%s"), arg
);
10122 as_fatal (_("invalid architecture -mcpu=%s"), arg
);
10133 if (mips_tune
!= CPU_UNKNOWN
&& mips_tune
!= cpu
)
10134 as_warn (_("A different -mtune= was already specified, is now "
10135 "-mtune=%s"), arg
);
10139 if (mips_arch
!= CPU_UNKNOWN
&& mips_arch
!= cpu
)
10140 as_warn (_("A different -march= was already specified, is now "
10141 "-march=%s"), arg
);
10145 if (mips_cpu
!= CPU_UNKNOWN
&& mips_cpu
!= cpu
)
10146 as_warn (_("A different -mcpu= was already specified, is now "
10154 if ((mips_arch
!= CPU_UNKNOWN
&& mips_arch
!= CPU_R4650
)
10155 || (mips_tune
!= CPU_UNKNOWN
&& mips_tune
!= CPU_R4650
))
10156 as_warn (_("A different -march= or -mtune= was already specified, "
10158 mips_arch
= CPU_R4650
;
10159 mips_tune
= CPU_R4650
;
10162 case OPTION_NO_M4650
:
10166 if ((mips_arch
!= CPU_UNKNOWN
&& mips_arch
!= CPU_R4010
)
10167 || (mips_tune
!= CPU_UNKNOWN
&& mips_tune
!= CPU_R4010
))
10168 as_warn (_("A different -march= or -mtune= was already specified, "
10170 mips_arch
= CPU_R4010
;
10171 mips_tune
= CPU_R4010
;
10174 case OPTION_NO_M4010
:
10178 if ((mips_arch
!= CPU_UNKNOWN
&& mips_arch
!= CPU_VR4100
)
10179 || (mips_tune
!= CPU_UNKNOWN
&& mips_tune
!= CPU_VR4100
))
10180 as_warn (_("A different -march= or -mtune= was already specified, "
10182 mips_arch
= CPU_VR4100
;
10183 mips_tune
= CPU_VR4100
;
10186 case OPTION_NO_M4100
:
10190 if ((mips_arch
!= CPU_UNKNOWN
&& mips_arch
!= CPU_R3900
)
10191 || (mips_tune
!= CPU_UNKNOWN
&& mips_tune
!= CPU_R3900
))
10192 as_warn (_("A different -march= or -mtune= was already specified, "
10194 mips_arch
= CPU_R3900
;
10195 mips_tune
= CPU_R3900
;
10198 case OPTION_NO_M3900
:
10201 case OPTION_MIPS16
:
10202 mips_opts
.mips16
= 1;
10203 mips_no_prev_insn (false);
10206 case OPTION_NO_MIPS16
:
10207 mips_opts
.mips16
= 0;
10208 mips_no_prev_insn (false);
10211 case OPTION_MIPS3D
:
10212 mips_opts
.ase_mips3d
= 1;
10215 case OPTION_NO_MIPS3D
:
10216 mips_opts
.ase_mips3d
= 0;
10219 case OPTION_MEMBEDDED_PIC
:
10220 mips_pic
= EMBEDDED_PIC
;
10221 if (USE_GLOBAL_POINTER_OPT
&& g_switch_seen
)
10223 as_bad (_("-G may not be used with embedded PIC code"));
10226 g_switch_value
= 0x7fffffff;
10230 /* When generating ELF code, we permit -KPIC and -call_shared to
10231 select SVR4_PIC, and -non_shared to select no PIC. This is
10232 intended to be compatible with Irix 5. */
10233 case OPTION_CALL_SHARED
:
10234 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10236 as_bad (_("-call_shared is supported only for ELF format"));
10239 mips_pic
= SVR4_PIC
;
10240 if (g_switch_seen
&& g_switch_value
!= 0)
10242 as_bad (_("-G may not be used with SVR4 PIC code"));
10245 g_switch_value
= 0;
10248 case OPTION_NON_SHARED
:
10249 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10251 as_bad (_("-non_shared is supported only for ELF format"));
10257 /* The -xgot option tells the assembler to use 32 offsets when
10258 accessing the got in SVR4_PIC mode. It is for Irix
10263 #endif /* OBJ_ELF */
10266 if (! USE_GLOBAL_POINTER_OPT
)
10268 as_bad (_("-G is not supported for this configuration"));
10271 else if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
10273 as_bad (_("-G may not be used with SVR4 or embedded PIC code"));
10277 g_switch_value
= atoi (arg
);
10282 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
10285 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10287 as_bad (_("-32 is supported for ELF format only"));
10290 mips_opts
.abi
= O32_ABI
;
10294 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10296 as_bad (_("-n32 is supported for ELF format only"));
10299 mips_opts
.abi
= N32_ABI
;
10303 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10305 as_bad (_("-64 is supported for ELF format only"));
10308 mips_opts
.abi
= N64_ABI
;
10309 if (! support_64bit_objects())
10310 as_fatal (_("No compiled in support for 64 bit object file format"));
10312 #endif /* OBJ_ELF */
10315 file_mips_gp32
= 1;
10316 if (mips_opts
.abi
!= O32_ABI
)
10317 mips_opts
.abi
= NO_ABI
;
10321 file_mips_gp32
= 0;
10322 if (mips_opts
.abi
== O32_ABI
)
10323 mips_opts
.abi
= NO_ABI
;
10327 file_mips_fp32
= 1;
10328 if (mips_opts
.abi
!= O32_ABI
)
10329 mips_opts
.abi
= NO_ABI
;
10334 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10336 as_bad (_("-mabi is supported for ELF format only"));
10339 if (strcmp (arg
, "32") == 0)
10340 mips_opts
.abi
= O32_ABI
;
10341 else if (strcmp (arg
, "o64") == 0)
10342 mips_opts
.abi
= O64_ABI
;
10343 else if (strcmp (arg
, "n32") == 0)
10344 mips_opts
.abi
= N32_ABI
;
10345 else if (strcmp (arg
, "64") == 0)
10347 mips_opts
.abi
= N64_ABI
;
10348 if (! support_64bit_objects())
10349 as_fatal (_("No compiled in support for 64 bit object file "
10352 else if (strcmp (arg
, "eabi") == 0)
10353 mips_opts
.abi
= EABI_ABI
;
10356 as_fatal (_("invalid abi -mabi=%s"), arg
);
10360 #endif /* OBJ_ELF */
10362 case OPTION_M7000_HILO_FIX
:
10363 mips_7000_hilo_fix
= true;
10366 case OPTION_MNO_7000_HILO_FIX
:
10367 mips_7000_hilo_fix
= false;
10378 show (stream
, string
, col_p
, first_p
)
10386 fprintf (stream
, "%24s", "");
10391 fprintf (stream
, ", ");
10395 if (*col_p
+ strlen (string
) > 72)
10397 fprintf (stream
, "\n%24s", "");
10401 fprintf (stream
, "%s", string
);
10402 *col_p
+= strlen (string
);
10408 md_show_usage (stream
)
10413 fprintf (stream
, _("\
10415 -membedded-pic generate embedded position independent code\n\
10416 -EB generate big endian output\n\
10417 -EL generate little endian output\n\
10418 -g, -g2 do not remove unneeded NOPs or swap branches\n\
10419 -G NUM allow referencing objects up to NUM bytes\n\
10420 implicitly with the gp register [default 8]\n"));
10421 fprintf (stream
, _("\
10422 -mips1 generate MIPS ISA I instructions\n\
10423 -mips2 generate MIPS ISA II instructions\n\
10424 -mips3 generate MIPS ISA III instructions\n\
10425 -mips4 generate MIPS ISA IV instructions\n\
10426 -mips5 generate MIPS ISA V instructions\n\
10427 -mips32 generate MIPS32 ISA instructions\n\
10428 -mips64 generate MIPS64 ISA instructions\n\
10429 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
10433 show (stream
, "2000", &column
, &first
);
10434 show (stream
, "3000", &column
, &first
);
10435 show (stream
, "3900", &column
, &first
);
10436 show (stream
, "4000", &column
, &first
);
10437 show (stream
, "4010", &column
, &first
);
10438 show (stream
, "4100", &column
, &first
);
10439 show (stream
, "4111", &column
, &first
);
10440 show (stream
, "4300", &column
, &first
);
10441 show (stream
, "4400", &column
, &first
);
10442 show (stream
, "4600", &column
, &first
);
10443 show (stream
, "4650", &column
, &first
);
10444 show (stream
, "5000", &column
, &first
);
10445 show (stream
, "5200", &column
, &first
);
10446 show (stream
, "5230", &column
, &first
);
10447 show (stream
, "5231", &column
, &first
);
10448 show (stream
, "5261", &column
, &first
);
10449 show (stream
, "5721", &column
, &first
);
10450 show (stream
, "6000", &column
, &first
);
10451 show (stream
, "8000", &column
, &first
);
10452 show (stream
, "10000", &column
, &first
);
10453 show (stream
, "12000", &column
, &first
);
10454 show (stream
, "sb1", &column
, &first
);
10455 fputc ('\n', stream
);
10457 fprintf (stream
, _("\
10458 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
10459 -no-mCPU don't generate code specific to CPU.\n\
10460 For -mCPU and -no-mCPU, CPU must be one of:\n"));
10464 show (stream
, "3900", &column
, &first
);
10465 show (stream
, "4010", &column
, &first
);
10466 show (stream
, "4100", &column
, &first
);
10467 show (stream
, "4650", &column
, &first
);
10468 fputc ('\n', stream
);
10470 fprintf (stream
, _("\
10471 -mips16 generate mips16 instructions\n\
10472 -no-mips16 do not generate mips16 instructions\n"));
10473 fprintf (stream
, _("\
10474 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
10475 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
10476 -O0 remove unneeded NOPs, do not swap branches\n\
10477 -O remove unneeded NOPs and swap branches\n\
10478 -n warn about NOPs generated from macros\n\
10479 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
10480 --trap, --no-break trap exception on div by 0 and mult overflow\n\
10481 --break, --no-trap break exception on div by 0 and mult overflow\n"));
10483 fprintf (stream
, _("\
10484 -KPIC, -call_shared generate SVR4 position independent code\n\
10485 -non_shared do not generate position independent code\n\
10486 -xgot assume a 32 bit GOT\n\
10487 -mabi=ABI create ABI conformant object file for:\n"));
10491 show (stream
, "32", &column
, &first
);
10492 show (stream
, "o64", &column
, &first
);
10493 show (stream
, "n32", &column
, &first
);
10494 show (stream
, "64", &column
, &first
);
10495 show (stream
, "eabi", &column
, &first
);
10497 fputc ('\n', stream
);
10499 fprintf (stream
, _("\
10500 -32 create o32 ABI object file (default)\n\
10501 -n32 create n32 ABI object file\n\
10502 -64 create 64 ABI object file\n"));
10507 mips_init_after_args ()
10509 /* initialize opcodes */
10510 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
10511 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
10515 md_pcrel_from (fixP
)
10518 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
10519 && fixP
->fx_addsy
!= (symbolS
*) NULL
10520 && ! S_IS_DEFINED (fixP
->fx_addsy
))
10522 /* This makes a branch to an undefined symbol be a branch to the
10523 current location. */
10524 if (mips_pic
== EMBEDDED_PIC
)
10530 /* Return the address of the delay slot. */
10531 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10534 /* This is called before the symbol table is processed. In order to
10535 work with gcc when using mips-tfile, we must keep all local labels.
10536 However, in other cases, we want to discard them. If we were
10537 called with -g, but we didn't see any debugging information, it may
10538 mean that gcc is smuggling debugging information through to
10539 mips-tfile, in which case we must generate all local labels. */
10542 mips_frob_file_before_adjust ()
10544 #ifndef NO_ECOFF_DEBUGGING
10545 if (ECOFF_DEBUGGING
10547 && ! ecoff_debugging_seen
)
10548 flag_keep_locals
= 1;
10552 /* Sort any unmatched HI16_S relocs so that they immediately precede
10553 the corresponding LO reloc. This is called before md_apply_fix3 and
10554 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
10555 explicit use of the %hi modifier. */
10560 struct mips_hi_fixup
*l
;
10562 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
10564 segment_info_type
*seginfo
;
10567 assert (l
->fixp
->fx_r_type
== BFD_RELOC_HI16_S
);
10569 /* Check quickly whether the next fixup happens to be a matching
10571 if (l
->fixp
->fx_next
!= NULL
10572 && l
->fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
10573 && l
->fixp
->fx_addsy
== l
->fixp
->fx_next
->fx_addsy
10574 && l
->fixp
->fx_offset
== l
->fixp
->fx_next
->fx_offset
)
10577 /* Look through the fixups for this segment for a matching %lo.
10578 When we find one, move the %hi just in front of it. We do
10579 this in two passes. In the first pass, we try to find a
10580 unique %lo. In the second pass, we permit multiple %hi
10581 relocs for a single %lo (this is a GNU extension). */
10582 seginfo
= seg_info (l
->seg
);
10583 for (pass
= 0; pass
< 2; pass
++)
10588 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
10590 /* Check whether this is a %lo fixup which matches l->fixp. */
10591 if (f
->fx_r_type
== BFD_RELOC_LO16
10592 && f
->fx_addsy
== l
->fixp
->fx_addsy
10593 && f
->fx_offset
== l
->fixp
->fx_offset
10596 || prev
->fx_r_type
!= BFD_RELOC_HI16_S
10597 || prev
->fx_addsy
!= f
->fx_addsy
10598 || prev
->fx_offset
!= f
->fx_offset
))
10602 /* Move l->fixp before f. */
10603 for (pf
= &seginfo
->fix_root
;
10605 pf
= &(*pf
)->fx_next
)
10606 assert (*pf
!= NULL
);
10608 *pf
= l
->fixp
->fx_next
;
10610 l
->fixp
->fx_next
= f
;
10612 seginfo
->fix_root
= l
->fixp
;
10614 prev
->fx_next
= l
->fixp
;
10625 #if 0 /* GCC code motion plus incomplete dead code elimination
10626 can leave a %hi without a %lo. */
10628 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
10629 _("Unmatched %%hi reloc"));
10635 /* When generating embedded PIC code we need to use a special
10636 relocation to represent the difference of two symbols in the .text
10637 section (switch tables use a difference of this sort). See
10638 include/coff/mips.h for details. This macro checks whether this
10639 fixup requires the special reloc. */
10640 #define SWITCH_TABLE(fixp) \
10641 ((fixp)->fx_r_type == BFD_RELOC_32 \
10642 && OUTPUT_FLAVOR != bfd_target_elf_flavour \
10643 && (fixp)->fx_addsy != NULL \
10644 && (fixp)->fx_subsy != NULL \
10645 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
10646 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
10648 /* When generating embedded PIC code we must keep all PC relative
10649 relocations, in case the linker has to relax a call. We also need
10650 to keep relocations for switch table entries.
10652 We may have combined relocations without symbols in the N32/N64 ABI.
10653 We have to prevent gas from dropping them. */
10656 mips_force_relocation (fixp
)
10659 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
10660 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
10664 && S_GET_SEGMENT (fixp
->fx_addsy
) == bfd_abs_section_ptr
10665 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_SUB
10666 || fixp
->fx_r_type
== BFD_RELOC_HI16_S
10667 || fixp
->fx_r_type
== BFD_RELOC_LO16
))
10670 return (mips_pic
== EMBEDDED_PIC
10672 || SWITCH_TABLE (fixp
)
10673 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
10674 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
10679 mips_need_elf_addend_fixup (fixP
)
10682 if (S_GET_OTHER (fixP
->fx_addsy
) == STO_MIPS16
)
10684 if (mips_pic
== EMBEDDED_PIC
10685 && S_IS_WEAK (fixP
->fx_addsy
))
10687 if (mips_pic
!= EMBEDDED_PIC
10688 && (S_IS_WEAK (fixP
->fx_addsy
)
10689 || S_IS_EXTERN (fixP
->fx_addsy
))
10690 && !S_IS_COMMON (fixP
->fx_addsy
))
10692 if (symbol_used_in_reloc_p (fixP
->fx_addsy
)
10693 && (((bfd_get_section_flags (stdoutput
,
10694 S_GET_SEGMENT (fixP
->fx_addsy
))
10695 & SEC_LINK_ONCE
) != 0)
10696 || !strncmp (segment_name (S_GET_SEGMENT (fixP
->fx_addsy
)),
10698 sizeof (".gnu.linkonce") - 1)))
10704 /* Apply a fixup to the object file. */
10707 md_apply_fix3 (fixP
, valP
, seg
)
10710 segT seg ATTRIBUTE_UNUSED
;
10716 assert (fixP
->fx_size
== 4
10717 || fixP
->fx_r_type
== BFD_RELOC_16
10718 || fixP
->fx_r_type
== BFD_RELOC_32
10719 || fixP
->fx_r_type
== BFD_RELOC_MIPS_JMP
10720 || fixP
->fx_r_type
== BFD_RELOC_HI16_S
10721 || fixP
->fx_r_type
== BFD_RELOC_LO16
10722 || fixP
->fx_r_type
== BFD_RELOC_GPREL16
10723 || fixP
->fx_r_type
== BFD_RELOC_MIPS_LITERAL
10724 || fixP
->fx_r_type
== BFD_RELOC_GPREL32
10725 || fixP
->fx_r_type
== BFD_RELOC_64
10726 || fixP
->fx_r_type
== BFD_RELOC_CTOR
10727 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
10728 || fixP
->fx_r_type
== BFD_RELOC_MIPS_HIGHEST
10729 || fixP
->fx_r_type
== BFD_RELOC_MIPS_HIGHER
10730 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SCN_DISP
10731 || fixP
->fx_r_type
== BFD_RELOC_MIPS_REL16
10732 || fixP
->fx_r_type
== BFD_RELOC_MIPS_RELGOT
10733 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
10734 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
10735 || fixP
->fx_r_type
== BFD_RELOC_MIPS_JALR
);
10739 /* If we aren't adjusting this fixup to be against the section
10740 symbol, we need to adjust the value. */
10742 if (fixP
->fx_addsy
!= NULL
&& OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
10744 if (mips_need_elf_addend_fixup (fixP
))
10746 valueT symval
= S_GET_VALUE (fixP
->fx_addsy
);
10749 if (value
!= 0 && ! fixP
->fx_pcrel
)
10751 /* In this case, the bfd_install_relocation routine will
10752 incorrectly add the symbol value back in. We just want
10753 the addend to appear in the object file. */
10756 /* Make sure the addend is still non-zero. If it became zero
10757 after the last operation, set it to a spurious value and
10758 subtract the same value from the object file's contents. */
10763 /* The in-place addends for LO16 relocations are signed;
10764 leave the matching HI16 in-place addends as zero. */
10765 if (fixP
->fx_r_type
!= BFD_RELOC_HI16_S
)
10767 reloc_howto_type
*howto
;
10768 bfd_vma contents
, mask
, field
;
10770 howto
= bfd_reloc_type_lookup (stdoutput
,
10773 contents
= bfd_get_bits (fixP
->fx_frag
->fr_literal
10776 target_big_endian
);
10778 /* MASK has bits set where the relocation should go.
10779 FIELD is -value, shifted into the appropriate place
10780 for this relocation. */
10781 mask
= 1 << (howto
->bitsize
- 1);
10782 mask
= (((mask
- 1) << 1) | 1) << howto
->bitpos
;
10783 field
= (-value
>> howto
->rightshift
) << howto
->bitpos
;
10785 bfd_put_bits ((field
& mask
) | (contents
& ~mask
),
10786 fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
10788 target_big_endian
);
10794 /* This code was generated using trial and error and so is
10795 fragile and not trustworthy. If you change it, you should
10796 rerun the elf-rel, elf-rel2, and empic testcases and ensure
10797 they still pass. */
10798 if (fixP
->fx_pcrel
|| fixP
->fx_subsy
!= NULL
)
10800 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
10802 /* BFD's REL handling, for MIPS, is _very_ weird.
10803 This gives the right results, but it can't possibly
10804 be the way things are supposed to work. */
10805 if ((fixP
->fx_r_type
!= BFD_RELOC_16_PCREL
10806 && fixP
->fx_r_type
!= BFD_RELOC_16_PCREL_S2
)
10807 || S_GET_SEGMENT (fixP
->fx_addsy
) != undefined_section
)
10808 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
10813 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc. */
10815 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
)
10818 switch (fixP
->fx_r_type
)
10820 case BFD_RELOC_MIPS_JMP
:
10821 case BFD_RELOC_MIPS_SHIFT5
:
10822 case BFD_RELOC_MIPS_SHIFT6
:
10823 case BFD_RELOC_MIPS_GOT_DISP
:
10824 case BFD_RELOC_MIPS_GOT_PAGE
:
10825 case BFD_RELOC_MIPS_GOT_OFST
:
10826 case BFD_RELOC_MIPS_SUB
:
10827 case BFD_RELOC_MIPS_INSERT_A
:
10828 case BFD_RELOC_MIPS_INSERT_B
:
10829 case BFD_RELOC_MIPS_DELETE
:
10830 case BFD_RELOC_MIPS_HIGHEST
:
10831 case BFD_RELOC_MIPS_HIGHER
:
10832 case BFD_RELOC_MIPS_SCN_DISP
:
10833 case BFD_RELOC_MIPS_REL16
:
10834 case BFD_RELOC_MIPS_RELGOT
:
10835 case BFD_RELOC_MIPS_JALR
:
10836 case BFD_RELOC_HI16
:
10837 case BFD_RELOC_HI16_S
:
10838 case BFD_RELOC_GPREL16
:
10839 case BFD_RELOC_MIPS_LITERAL
:
10840 case BFD_RELOC_MIPS_CALL16
:
10841 case BFD_RELOC_MIPS_GOT16
:
10842 case BFD_RELOC_GPREL32
:
10843 case BFD_RELOC_MIPS_GOT_HI16
:
10844 case BFD_RELOC_MIPS_GOT_LO16
:
10845 case BFD_RELOC_MIPS_CALL_HI16
:
10846 case BFD_RELOC_MIPS_CALL_LO16
:
10847 case BFD_RELOC_MIPS16_GPREL
:
10848 if (fixP
->fx_pcrel
)
10849 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10850 _("Invalid PC relative reloc"));
10851 /* Nothing needed to do. The value comes from the reloc entry */
10854 case BFD_RELOC_MIPS16_JMP
:
10855 /* We currently always generate a reloc against a symbol, which
10856 means that we don't want an addend even if the symbol is
10858 fixP
->fx_addnumber
= 0;
10861 case BFD_RELOC_PCREL_HI16_S
:
10862 /* The addend for this is tricky if it is internal, so we just
10863 do everything here rather than in bfd_install_relocation. */
10864 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
10869 && (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_SECTION_SYM
) == 0)
10871 /* For an external symbol adjust by the address to make it
10872 pcrel_offset. We use the address of the RELLO reloc
10873 which follows this one. */
10874 value
+= (fixP
->fx_next
->fx_frag
->fr_address
10875 + fixP
->fx_next
->fx_where
);
10877 value
= ((value
+ 0x8000) >> 16) & 0xffff;
10878 buf
= (bfd_byte
*) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
10879 if (target_big_endian
)
10881 md_number_to_chars ((char *) buf
, value
, 2);
10884 case BFD_RELOC_PCREL_LO16
:
10885 /* The addend for this is tricky if it is internal, so we just
10886 do everything here rather than in bfd_install_relocation. */
10887 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
10892 && (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_SECTION_SYM
) == 0)
10893 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
10894 buf
= (bfd_byte
*) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
10895 if (target_big_endian
)
10897 md_number_to_chars ((char *) buf
, value
, 2);
10901 /* This is handled like BFD_RELOC_32, but we output a sign
10902 extended value if we are only 32 bits. */
10904 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
10906 if (8 <= sizeof (valueT
))
10907 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
10914 w1
= w2
= fixP
->fx_where
;
10915 if (target_big_endian
)
10919 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w1
, value
, 4);
10920 if ((value
& 0x80000000) != 0)
10924 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w2
, hiv
, 4);
10929 case BFD_RELOC_RVA
:
10931 /* If we are deleting this reloc entry, we must fill in the
10932 value now. This can happen if we have a .word which is not
10933 resolved when it appears but is later defined. We also need
10934 to fill in the value if this is an embedded PIC switch table
10937 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
10938 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
10943 /* If we are deleting this reloc entry, we must fill in the
10945 assert (fixP
->fx_size
== 2);
10947 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
10951 case BFD_RELOC_LO16
:
10952 /* When handling an embedded PIC switch statement, we can wind
10953 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
10956 if (value
+ 0x8000 > 0xffff)
10957 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10958 _("relocation overflow"));
10959 buf
= (bfd_byte
*) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
10960 if (target_big_endian
)
10962 md_number_to_chars ((char *) buf
, value
, 2);
10966 case BFD_RELOC_16_PCREL_S2
:
10967 if ((value
& 0x3) != 0)
10968 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10969 _("Branch to odd address (%lx)"), (long) value
);
10971 /* Fall through. */
10973 case BFD_RELOC_16_PCREL
:
10975 * We need to save the bits in the instruction since fixup_segment()
10976 * might be deleting the relocation entry (i.e., a branch within
10977 * the current segment).
10979 if (!fixP
->fx_done
&& value
!= 0)
10981 /* If 'value' is zero, the remaining reloc code won't actually
10982 do the store, so it must be done here. This is probably
10983 a bug somewhere. */
10985 && (fixP
->fx_r_type
!= BFD_RELOC_16_PCREL_S2
10986 || fixP
->fx_addsy
== NULL
/* ??? */
10987 || ! S_IS_DEFINED (fixP
->fx_addsy
)))
10988 value
-= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
10990 value
= (offsetT
) value
>> 2;
10992 /* update old instruction data */
10993 buf
= (bfd_byte
*) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
10994 if (target_big_endian
)
10995 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
10997 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
10999 if (value
+ 0x8000 <= 0xffff)
11000 insn
|= value
& 0xffff;
11003 /* The branch offset is too large. If this is an
11004 unconditional branch, and we are not generating PIC code,
11005 we can convert it to an absolute jump instruction. */
11006 if (mips_pic
== NO_PIC
11008 && fixP
->fx_frag
->fr_address
>= text_section
->vma
11009 && (fixP
->fx_frag
->fr_address
11010 < text_section
->vma
+ text_section
->_raw_size
)
11011 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
11012 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
11013 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
11015 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
11016 insn
= 0x0c000000; /* jal */
11018 insn
= 0x08000000; /* j */
11019 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
11021 fixP
->fx_addsy
= section_symbol (text_section
);
11022 fixP
->fx_addnumber
= (value
<< 2) + md_pcrel_from (fixP
);
11026 /* FIXME. It would be possible in principle to handle
11027 conditional branches which overflow. They could be
11028 transformed into a branch around a jump. This would
11029 require setting up variant frags for each different
11030 branch type. The native MIPS assembler attempts to
11031 handle these cases, but it appears to do it
11033 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11034 _("Branch out of range"));
11038 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
11041 case BFD_RELOC_VTABLE_INHERIT
:
11044 && !S_IS_DEFINED (fixP
->fx_addsy
)
11045 && !S_IS_WEAK (fixP
->fx_addsy
))
11046 S_SET_WEAK (fixP
->fx_addsy
);
11049 case BFD_RELOC_VTABLE_ENTRY
:
11063 const struct mips_opcode
*p
;
11064 int treg
, sreg
, dreg
, shamt
;
11069 for (i
= 0; i
< NUMOPCODES
; ++i
)
11071 p
= &mips_opcodes
[i
];
11072 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
11074 printf ("%08lx %s\t", oc
, p
->name
);
11075 treg
= (oc
>> 16) & 0x1f;
11076 sreg
= (oc
>> 21) & 0x1f;
11077 dreg
= (oc
>> 11) & 0x1f;
11078 shamt
= (oc
>> 6) & 0x1f;
11080 for (args
= p
->args
;; ++args
)
11091 printf ("%c", *args
);
11095 assert (treg
== sreg
);
11096 printf ("$%d,$%d", treg
, sreg
);
11101 printf ("$%d", dreg
);
11106 printf ("$%d", treg
);
11110 printf ("0x%x", treg
);
11115 printf ("$%d", sreg
);
11119 printf ("0x%08lx", oc
& 0x1ffffff);
11126 printf ("%d", imm
);
11131 printf ("$%d", shamt
);
11142 printf (_("%08lx UNDEFINED\n"), oc
);
11153 name
= input_line_pointer
;
11154 c
= get_symbol_end ();
11155 p
= (symbolS
*) symbol_find_or_make (name
);
11156 *input_line_pointer
= c
;
11160 /* Align the current frag to a given power of two. The MIPS assembler
11161 also automatically adjusts any preceding label. */
11164 mips_align (to
, fill
, label
)
11169 mips_emit_delays (false);
11170 frag_align (to
, fill
, 0);
11171 record_alignment (now_seg
, to
);
11174 assert (S_GET_SEGMENT (label
) == now_seg
);
11175 symbol_set_frag (label
, frag_now
);
11176 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
11180 /* Align to a given power of two. .align 0 turns off the automatic
11181 alignment used by the data creating pseudo-ops. */
11185 int x ATTRIBUTE_UNUSED
;
11188 register long temp_fill
;
11189 long max_alignment
= 15;
11193 o Note that the assembler pulls down any immediately preceeding label
11194 to the aligned address.
11195 o It's not documented but auto alignment is reinstated by
11196 a .align pseudo instruction.
11197 o Note also that after auto alignment is turned off the mips assembler
11198 issues an error on attempt to assemble an improperly aligned data item.
11203 temp
= get_absolute_expression ();
11204 if (temp
> max_alignment
)
11205 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
11208 as_warn (_("Alignment negative: 0 assumed."));
11211 if (*input_line_pointer
== ',')
11213 ++input_line_pointer
;
11214 temp_fill
= get_absolute_expression ();
11221 mips_align (temp
, (int) temp_fill
,
11222 insn_labels
!= NULL
? insn_labels
->label
: NULL
);
11229 demand_empty_rest_of_line ();
11233 mips_flush_pending_output ()
11235 mips_emit_delays (false);
11236 mips_clear_insn_labels ();
11245 /* When generating embedded PIC code, we only use the .text, .lit8,
11246 .sdata and .sbss sections. We change the .data and .rdata
11247 pseudo-ops to use .sdata. */
11248 if (mips_pic
== EMBEDDED_PIC
11249 && (sec
== 'd' || sec
== 'r'))
11253 /* The ELF backend needs to know that we are changing sections, so
11254 that .previous works correctly. We could do something like check
11255 for an obj_section_change_hook macro, but that might be confusing
11256 as it would not be appropriate to use it in the section changing
11257 functions in read.c, since obj-elf.c intercepts those. FIXME:
11258 This should be cleaner, somehow. */
11259 obj_elf_section_change_hook ();
11262 mips_emit_delays (false);
11272 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
11273 demand_empty_rest_of_line ();
11277 if (USE_GLOBAL_POINTER_OPT
)
11279 seg
= subseg_new (RDATA_SECTION_NAME
,
11280 (subsegT
) get_absolute_expression ());
11281 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11283 bfd_set_section_flags (stdoutput
, seg
,
11289 if (strcmp (TARGET_OS
, "elf") != 0)
11290 record_alignment (seg
, 4);
11292 demand_empty_rest_of_line ();
11296 as_bad (_("No read only data section in this object file format"));
11297 demand_empty_rest_of_line ();
11303 if (USE_GLOBAL_POINTER_OPT
)
11305 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
11306 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11308 bfd_set_section_flags (stdoutput
, seg
,
11309 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
11311 if (strcmp (TARGET_OS
, "elf") != 0)
11312 record_alignment (seg
, 4);
11314 demand_empty_rest_of_line ();
11319 as_bad (_("Global pointers not supported; recompile -G 0"));
11320 demand_empty_rest_of_line ();
11329 mips_enable_auto_align ()
11340 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11341 mips_emit_delays (false);
11342 if (log_size
> 0 && auto_align
)
11343 mips_align (log_size
, 0, label
);
11344 mips_clear_insn_labels ();
11345 cons (1 << log_size
);
11349 s_float_cons (type
)
11354 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11356 mips_emit_delays (false);
11361 mips_align (3, 0, label
);
11363 mips_align (2, 0, label
);
11366 mips_clear_insn_labels ();
11371 /* Handle .globl. We need to override it because on Irix 5 you are
11374 where foo is an undefined symbol, to mean that foo should be
11375 considered to be the address of a function. */
11379 int x ATTRIBUTE_UNUSED
;
11386 name
= input_line_pointer
;
11387 c
= get_symbol_end ();
11388 symbolP
= symbol_find_or_make (name
);
11389 *input_line_pointer
= c
;
11390 SKIP_WHITESPACE ();
11392 /* On Irix 5, every global symbol that is not explicitly labelled as
11393 being a function is apparently labelled as being an object. */
11396 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
11401 secname
= input_line_pointer
;
11402 c
= get_symbol_end ();
11403 sec
= bfd_get_section_by_name (stdoutput
, secname
);
11405 as_bad (_("%s: no such section"), secname
);
11406 *input_line_pointer
= c
;
11408 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
11409 flag
= BSF_FUNCTION
;
11412 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
11414 S_SET_EXTERNAL (symbolP
);
11415 demand_empty_rest_of_line ();
11420 int x ATTRIBUTE_UNUSED
;
11425 opt
= input_line_pointer
;
11426 c
= get_symbol_end ();
11430 /* FIXME: What does this mean? */
11432 else if (strncmp (opt
, "pic", 3) == 0)
11436 i
= atoi (opt
+ 3);
11440 mips_pic
= SVR4_PIC
;
11442 as_bad (_(".option pic%d not supported"), i
);
11444 if (USE_GLOBAL_POINTER_OPT
&& mips_pic
== SVR4_PIC
)
11446 if (g_switch_seen
&& g_switch_value
!= 0)
11447 as_warn (_("-G may not be used with SVR4 PIC code"));
11448 g_switch_value
= 0;
11449 bfd_set_gp_size (stdoutput
, 0);
11453 as_warn (_("Unrecognized option \"%s\""), opt
);
11455 *input_line_pointer
= c
;
11456 demand_empty_rest_of_line ();
11459 /* This structure is used to hold a stack of .set values. */
11461 struct mips_option_stack
11463 struct mips_option_stack
*next
;
11464 struct mips_set_options options
;
11467 static struct mips_option_stack
*mips_opts_stack
;
11469 /* Handle the .set pseudo-op. */
11473 int x ATTRIBUTE_UNUSED
;
11475 char *name
= input_line_pointer
, ch
;
11477 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
11478 ++input_line_pointer
;
11479 ch
= *input_line_pointer
;
11480 *input_line_pointer
= '\0';
11482 if (strcmp (name
, "reorder") == 0)
11484 if (mips_opts
.noreorder
&& prev_nop_frag
!= NULL
)
11486 /* If we still have pending nops, we can discard them. The
11487 usual nop handling will insert any that are still
11489 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
11490 * (mips_opts
.mips16
? 2 : 4));
11491 prev_nop_frag
= NULL
;
11493 mips_opts
.noreorder
= 0;
11495 else if (strcmp (name
, "noreorder") == 0)
11497 mips_emit_delays (true);
11498 mips_opts
.noreorder
= 1;
11499 mips_any_noreorder
= 1;
11501 else if (strcmp (name
, "at") == 0)
11503 mips_opts
.noat
= 0;
11505 else if (strcmp (name
, "noat") == 0)
11507 mips_opts
.noat
= 1;
11509 else if (strcmp (name
, "macro") == 0)
11511 mips_opts
.warn_about_macros
= 0;
11513 else if (strcmp (name
, "nomacro") == 0)
11515 if (mips_opts
.noreorder
== 0)
11516 as_bad (_("`noreorder' must be set before `nomacro'"));
11517 mips_opts
.warn_about_macros
= 1;
11519 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
11521 mips_opts
.nomove
= 0;
11523 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
11525 mips_opts
.nomove
= 1;
11527 else if (strcmp (name
, "bopt") == 0)
11529 mips_opts
.nobopt
= 0;
11531 else if (strcmp (name
, "nobopt") == 0)
11533 mips_opts
.nobopt
= 1;
11535 else if (strcmp (name
, "mips16") == 0
11536 || strcmp (name
, "MIPS-16") == 0)
11537 mips_opts
.mips16
= 1;
11538 else if (strcmp (name
, "nomips16") == 0
11539 || strcmp (name
, "noMIPS-16") == 0)
11540 mips_opts
.mips16
= 0;
11541 else if (strcmp (name
, "mips3d") == 0)
11542 mips_opts
.ase_mips3d
= 1;
11543 else if (strcmp (name
, "nomips3d") == 0)
11544 mips_opts
.ase_mips3d
= 0;
11545 else if (strncmp (name
, "mips", 4) == 0)
11549 /* Permit the user to change the ISA on the fly. Needless to
11550 say, misuse can cause serious problems. */
11551 isa
= atoi (name
+ 4);
11555 mips_opts
.gp32
= file_mips_gp32
;
11556 mips_opts
.fp32
= file_mips_fp32
;
11557 mips_opts
.abi
= file_mips_abi
;
11562 mips_opts
.gp32
= 1;
11563 mips_opts
.fp32
= 1;
11569 /* Loosen ABI register width restriction. */
11570 if (mips_opts
.abi
== O32_ABI
)
11571 mips_opts
.abi
= NO_ABI
;
11572 mips_opts
.gp32
= 0;
11573 mips_opts
.fp32
= 0;
11576 as_bad (_("unknown ISA level %s"), name
+ 4);
11582 case 0: mips_opts
.isa
= file_mips_isa
; break;
11583 case 1: mips_opts
.isa
= ISA_MIPS1
; break;
11584 case 2: mips_opts
.isa
= ISA_MIPS2
; break;
11585 case 3: mips_opts
.isa
= ISA_MIPS3
; break;
11586 case 4: mips_opts
.isa
= ISA_MIPS4
; break;
11587 case 5: mips_opts
.isa
= ISA_MIPS5
; break;
11588 case 32: mips_opts
.isa
= ISA_MIPS32
; break;
11589 case 64: mips_opts
.isa
= ISA_MIPS64
; break;
11590 default: as_bad (_("unknown ISA level %s"), name
+ 4); break;
11593 else if (strcmp (name
, "autoextend") == 0)
11594 mips_opts
.noautoextend
= 0;
11595 else if (strcmp (name
, "noautoextend") == 0)
11596 mips_opts
.noautoextend
= 1;
11597 else if (strcmp (name
, "push") == 0)
11599 struct mips_option_stack
*s
;
11601 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
11602 s
->next
= mips_opts_stack
;
11603 s
->options
= mips_opts
;
11604 mips_opts_stack
= s
;
11606 else if (strcmp (name
, "pop") == 0)
11608 struct mips_option_stack
*s
;
11610 s
= mips_opts_stack
;
11612 as_bad (_(".set pop with no .set push"));
11615 /* If we're changing the reorder mode we need to handle
11616 delay slots correctly. */
11617 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
11618 mips_emit_delays (true);
11619 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
11621 if (prev_nop_frag
!= NULL
)
11623 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
11624 * (mips_opts
.mips16
? 2 : 4));
11625 prev_nop_frag
= NULL
;
11629 mips_opts
= s
->options
;
11630 mips_opts_stack
= s
->next
;
11636 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
11638 *input_line_pointer
= ch
;
11639 demand_empty_rest_of_line ();
11642 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
11643 .option pic2. It means to generate SVR4 PIC calls. */
11646 s_abicalls (ignore
)
11647 int ignore ATTRIBUTE_UNUSED
;
11649 mips_pic
= SVR4_PIC
;
11650 if (USE_GLOBAL_POINTER_OPT
)
11652 if (g_switch_seen
&& g_switch_value
!= 0)
11653 as_warn (_("-G may not be used with SVR4 PIC code"));
11654 g_switch_value
= 0;
11656 bfd_set_gp_size (stdoutput
, 0);
11657 demand_empty_rest_of_line ();
11660 /* Handle the .cpload pseudo-op. This is used when generating SVR4
11661 PIC code. It sets the $gp register for the function based on the
11662 function address, which is in the register named in the argument.
11663 This uses a relocation against _gp_disp, which is handled specially
11664 by the linker. The result is:
11665 lui $gp,%hi(_gp_disp)
11666 addiu $gp,$gp,%lo(_gp_disp)
11667 addu $gp,$gp,.cpload argument
11668 The .cpload argument is normally $25 == $t9. */
11672 int ignore ATTRIBUTE_UNUSED
;
11677 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
11678 .cpload is ignored. */
11679 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
11685 /* .cpload should be in a .set noreorder section. */
11686 if (mips_opts
.noreorder
== 0)
11687 as_warn (_(".cpload not in noreorder section"));
11689 ex
.X_op
= O_symbol
;
11690 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
11691 ex
.X_op_symbol
= NULL
;
11692 ex
.X_add_number
= 0;
11694 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
11695 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
11697 macro_build_lui (NULL
, &icnt
, &ex
, mips_gp_register
);
11698 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j",
11699 mips_gp_register
, mips_gp_register
, (int) BFD_RELOC_LO16
);
11701 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
11702 mips_gp_register
, mips_gp_register
, tc_get_register (0));
11704 demand_empty_rest_of_line ();
11707 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
11708 .cpsetup $reg1, offset|$reg2, label
11710 If offset is given, this results in:
11711 sd $gp, offset($sp)
11712 lui $gp, %hi(%neg(%gp_rel(label)))
11713 daddiu $gp, $gp, %lo(%neg(%gp_rel(label)))
11714 addu $gp, $gp, $reg1
11716 If $reg2 is given, this results in:
11717 daddu $reg2, $gp, $0
11718 lui $gp, %hi(%neg(%gp_rel(label)))
11719 daddiu $gp, $gp, %lo(%neg(%gp_rel(label)))
11720 addu $gp, $gp, $reg1
11724 int ignore ATTRIBUTE_UNUSED
;
11726 expressionS ex_off
;
11727 expressionS ex_sym
;
11732 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
11733 We also need NewABI support. */
11734 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
11740 reg1
= tc_get_register (0);
11741 SKIP_WHITESPACE ();
11742 if (*input_line_pointer
!= ',')
11744 as_bad (_("missing argument separator ',' for .cpsetup"));
11748 input_line_pointer
++;
11749 SKIP_WHITESPACE ();
11750 if (*input_line_pointer
== '$')
11751 mips_cpreturn_register
= tc_get_register (0);
11753 mips_cpreturn_offset
= get_absolute_expression ();
11754 SKIP_WHITESPACE ();
11755 if (*input_line_pointer
!= ',')
11757 as_bad (_("missing argument separator ',' for .cpsetup"));
11761 ++input_line_pointer
;
11762 SKIP_WHITESPACE ();
11763 sym
= input_line_pointer
;
11764 while (ISALNUM (*input_line_pointer
))
11765 ++input_line_pointer
;
11766 *input_line_pointer
= 0;
11768 ex_sym
.X_op
= O_symbol
;
11769 ex_sym
.X_add_symbol
= symbol_find_or_make (sym
);
11770 ex_sym
.X_op_symbol
= NULL
;
11771 ex_sym
.X_add_number
= 0;
11773 if (mips_cpreturn_register
== -1)
11775 ex_off
.X_op
= O_constant
;
11776 ex_off
.X_add_symbol
= NULL
;
11777 ex_off
.X_op_symbol
= NULL
;
11778 ex_off
.X_add_number
= mips_cpreturn_offset
;
11780 macro_build ((char *) NULL
, &icnt
, &ex_off
, "sd", "t,o(b)",
11781 mips_gp_register
, (int) BFD_RELOC_LO16
, SP
);
11784 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "daddu",
11785 "d,v,t", mips_cpreturn_register
, mips_gp_register
, 0);
11787 macro_build ((char *) NULL
, &icnt
, &ex_sym
, "lui", "t,u", mips_gp_register
,
11788 (int) BFD_RELOC_GPREL16
);
11789 fix_new (frag_now
, prev_insn_where
, 0, NULL
, 0, 0, BFD_RELOC_MIPS_SUB
);
11790 fix_new (frag_now
, prev_insn_where
, 0, NULL
, 0, 0, BFD_RELOC_HI16_S
);
11791 macro_build ((char *) NULL
, &icnt
, &ex_sym
, "addiu", "t,r,j",
11792 mips_gp_register
, mips_gp_register
, (int) BFD_RELOC_GPREL16
);
11793 fix_new (frag_now
, prev_insn_where
, 0, NULL
, 0, 0, BFD_RELOC_MIPS_SUB
);
11794 fix_new (frag_now
, prev_insn_where
, 0, NULL
, 0, 0, BFD_RELOC_LO16
);
11795 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
11796 HAVE_64BIT_ADDRESSES
? "daddu" : "addu", "d,v,t",
11797 mips_gp_register
, mips_gp_register
, reg1
);
11799 demand_empty_rest_of_line ();
11804 int ignore ATTRIBUTE_UNUSED
;
11806 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
11807 .cplocal is ignored. */
11808 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
11814 mips_gp_register
= tc_get_register (0);
11817 /* Handle the .cprestore pseudo-op. This stores $gp into a given
11818 offset from $sp. The offset is remembered, and after making a PIC
11819 call $gp is restored from that location. */
11822 s_cprestore (ignore
)
11823 int ignore ATTRIBUTE_UNUSED
;
11828 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
11829 .cprestore is ignored. */
11830 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
11836 mips_cprestore_offset
= get_absolute_expression ();
11837 mips_cprestore_valid
= 1;
11839 ex
.X_op
= O_constant
;
11840 ex
.X_add_symbol
= NULL
;
11841 ex
.X_op_symbol
= NULL
;
11842 ex
.X_add_number
= mips_cprestore_offset
;
11844 macro_build ((char *) NULL
, &icnt
, &ex
, HAVE_32BIT_ADDRESSES
? "sw" : "sd",
11845 "t,o(b)", mips_gp_register
, (int) BFD_RELOC_LO16
, SP
);
11847 demand_empty_rest_of_line ();
11850 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
11851 was given in the preceeding .gpsetup, it results in:
11852 ld $gp, offset($sp)
11854 If a register $reg2 was given there, it results in:
11855 daddiu $gp, $gp, $reg2
11858 s_cpreturn (ignore
)
11859 int ignore ATTRIBUTE_UNUSED
;
11864 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
11865 We also need NewABI support. */
11866 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
11872 if (mips_cpreturn_register
== -1)
11874 ex
.X_op
= O_constant
;
11875 ex
.X_add_symbol
= NULL
;
11876 ex
.X_op_symbol
= NULL
;
11877 ex
.X_add_number
= mips_cpreturn_offset
;
11879 macro_build ((char *) NULL
, &icnt
, &ex
, "ld", "t,o(b)",
11880 mips_gp_register
, (int) BFD_RELOC_LO16
, SP
);
11883 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "daddu",
11884 "d,v,t", mips_gp_register
, mips_cpreturn_register
, 0);
11886 demand_empty_rest_of_line ();
11889 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
11890 code. It sets the offset to use in gp_rel relocations. */
11894 int ignore ATTRIBUTE_UNUSED
;
11896 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
11897 We also need NewABI support. */
11898 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
11904 mips_gprel_offset
= get_absolute_expression ();
11906 demand_empty_rest_of_line ();
11909 /* Handle the .gpword pseudo-op. This is used when generating PIC
11910 code. It generates a 32 bit GP relative reloc. */
11914 int ignore ATTRIBUTE_UNUSED
;
11920 /* When not generating PIC code, this is treated as .word. */
11921 if (mips_pic
!= SVR4_PIC
)
11927 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11928 mips_emit_delays (true);
11930 mips_align (2, 0, label
);
11931 mips_clear_insn_labels ();
11935 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
11937 as_bad (_("Unsupported use of .gpword"));
11938 ignore_rest_of_line ();
11942 md_number_to_chars (p
, (valueT
) 0, 4);
11943 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, false,
11944 BFD_RELOC_GPREL32
);
11946 demand_empty_rest_of_line ();
11949 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
11950 tables in SVR4 PIC code. */
11954 int ignore ATTRIBUTE_UNUSED
;
11959 /* This is ignored when not generating SVR4 PIC code or if this is NewABI
11961 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
11967 /* Add $gp to the register named as an argument. */
11968 reg
= tc_get_register (0);
11969 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
11970 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
11971 "d,v,t", reg
, reg
, mips_gp_register
);
11973 demand_empty_rest_of_line ();
11976 /* Handle the .insn pseudo-op. This marks instruction labels in
11977 mips16 mode. This permits the linker to handle them specially,
11978 such as generating jalx instructions when needed. We also make
11979 them odd for the duration of the assembly, in order to generate the
11980 right sort of code. We will make them even in the adjust_symtab
11981 routine, while leaving them marked. This is convenient for the
11982 debugger and the disassembler. The linker knows to make them odd
11987 int ignore ATTRIBUTE_UNUSED
;
11989 mips16_mark_labels ();
11991 demand_empty_rest_of_line ();
11994 /* Handle a .stabn directive. We need these in order to mark a label
11995 as being a mips16 text label correctly. Sometimes the compiler
11996 will emit a label, followed by a .stabn, and then switch sections.
11997 If the label and .stabn are in mips16 mode, then the label is
11998 really a mips16 text label. */
12005 mips16_mark_labels ();
12010 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
12014 s_mips_weakext (ignore
)
12015 int ignore ATTRIBUTE_UNUSED
;
12022 name
= input_line_pointer
;
12023 c
= get_symbol_end ();
12024 symbolP
= symbol_find_or_make (name
);
12025 S_SET_WEAK (symbolP
);
12026 *input_line_pointer
= c
;
12028 SKIP_WHITESPACE ();
12030 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
12032 if (S_IS_DEFINED (symbolP
))
12034 as_bad ("ignoring attempt to redefine symbol %s",
12035 S_GET_NAME (symbolP
));
12036 ignore_rest_of_line ();
12040 if (*input_line_pointer
== ',')
12042 ++input_line_pointer
;
12043 SKIP_WHITESPACE ();
12047 if (exp
.X_op
!= O_symbol
)
12049 as_bad ("bad .weakext directive");
12050 ignore_rest_of_line ();
12053 symbol_set_value_expression (symbolP
, &exp
);
12056 demand_empty_rest_of_line ();
12059 /* Parse a register string into a number. Called from the ECOFF code
12060 to parse .frame. The argument is non-zero if this is the frame
12061 register, so that we can record it in mips_frame_reg. */
12064 tc_get_register (frame
)
12069 SKIP_WHITESPACE ();
12070 if (*input_line_pointer
++ != '$')
12072 as_warn (_("expected `$'"));
12075 else if (ISDIGIT (*input_line_pointer
))
12077 reg
= get_absolute_expression ();
12078 if (reg
< 0 || reg
>= 32)
12080 as_warn (_("Bad register number"));
12086 if (strncmp (input_line_pointer
, "fp", 2) == 0)
12088 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
12090 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
12092 else if (strncmp (input_line_pointer
, "at", 2) == 0)
12096 as_warn (_("Unrecognized register name"));
12099 input_line_pointer
+= 2;
12103 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
12104 mips_frame_reg_valid
= 1;
12105 mips_cprestore_valid
= 0;
12111 md_section_align (seg
, addr
)
12115 int align
= bfd_get_section_alignment (stdoutput
, seg
);
12118 /* We don't need to align ELF sections to the full alignment.
12119 However, Irix 5 may prefer that we align them at least to a 16
12120 byte boundary. We don't bother to align the sections if we are
12121 targeted for an embedded system. */
12122 if (strcmp (TARGET_OS
, "elf") == 0)
12128 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
12131 /* Utility routine, called from above as well. If called while the
12132 input file is still being read, it's only an approximation. (For
12133 example, a symbol may later become defined which appeared to be
12134 undefined earlier.) */
12137 nopic_need_relax (sym
, before_relaxing
)
12139 int before_relaxing
;
12144 if (USE_GLOBAL_POINTER_OPT
&& g_switch_value
> 0)
12146 const char *symname
;
12149 /* Find out whether this symbol can be referenced off the $gp
12150 register. It can be if it is smaller than the -G size or if
12151 it is in the .sdata or .sbss section. Certain symbols can
12152 not be referenced off the $gp, although it appears as though
12154 symname
= S_GET_NAME (sym
);
12155 if (symname
!= (const char *) NULL
12156 && (strcmp (symname
, "eprol") == 0
12157 || strcmp (symname
, "etext") == 0
12158 || strcmp (symname
, "_gp") == 0
12159 || strcmp (symname
, "edata") == 0
12160 || strcmp (symname
, "_fbss") == 0
12161 || strcmp (symname
, "_fdata") == 0
12162 || strcmp (symname
, "_ftext") == 0
12163 || strcmp (symname
, "end") == 0
12164 || strcmp (symname
, "_gp_disp") == 0))
12166 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
12168 #ifndef NO_ECOFF_DEBUGGING
12169 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
12170 && (symbol_get_obj (sym
)->ecoff_extern_size
12171 <= g_switch_value
))
12173 /* We must defer this decision until after the whole
12174 file has been read, since there might be a .extern
12175 after the first use of this symbol. */
12176 || (before_relaxing
12177 #ifndef NO_ECOFF_DEBUGGING
12178 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
12180 && S_GET_VALUE (sym
) == 0)
12181 || (S_GET_VALUE (sym
) != 0
12182 && S_GET_VALUE (sym
) <= g_switch_value
)))
12186 const char *segname
;
12188 segname
= segment_name (S_GET_SEGMENT (sym
));
12189 assert (strcmp (segname
, ".lit8") != 0
12190 && strcmp (segname
, ".lit4") != 0);
12191 change
= (strcmp (segname
, ".sdata") != 0
12192 && strcmp (segname
, ".sbss") != 0
12193 && strncmp (segname
, ".sdata.", 7) != 0
12194 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
12199 /* We are not optimizing for the $gp register. */
12203 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
12204 extended opcode. SEC is the section the frag is in. */
12207 mips16_extended_frag (fragp
, sec
, stretch
)
12213 register const struct mips16_immed_operand
*op
;
12215 int mintiny
, maxtiny
;
12219 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
12221 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
12224 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
12225 op
= mips16_immed_operands
;
12226 while (op
->type
!= type
)
12229 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
12234 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
12237 maxtiny
= 1 << op
->nbits
;
12242 maxtiny
= (1 << op
->nbits
) - 1;
12247 mintiny
= - (1 << (op
->nbits
- 1));
12248 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
12251 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
12252 val
= S_GET_VALUE (fragp
->fr_symbol
);
12253 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
12259 /* We won't have the section when we are called from
12260 mips_relax_frag. However, we will always have been called
12261 from md_estimate_size_before_relax first. If this is a
12262 branch to a different section, we mark it as such. If SEC is
12263 NULL, and the frag is not marked, then it must be a branch to
12264 the same section. */
12267 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
12272 /* Must have been called from md_estimate_size_before_relax. */
12275 fragp
->fr_subtype
=
12276 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12278 /* FIXME: We should support this, and let the linker
12279 catch branches and loads that are out of range. */
12280 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
12281 _("unsupported PC relative reference to different section"));
12285 if (fragp
!= sym_frag
&& sym_frag
->fr_address
== 0)
12286 /* Assume non-extended on the first relaxation pass.
12287 The address we have calculated will be bogus if this is
12288 a forward branch to another frag, as the forward frag
12289 will have fr_address == 0. */
12293 /* In this case, we know for sure that the symbol fragment is in
12294 the same section. If the relax_marker of the symbol fragment
12295 differs from the relax_marker of this fragment, we have not
12296 yet adjusted the symbol fragment fr_address. We want to add
12297 in STRETCH in order to get a better estimate of the address.
12298 This particularly matters because of the shift bits. */
12300 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
12304 /* Adjust stretch for any alignment frag. Note that if have
12305 been expanding the earlier code, the symbol may be
12306 defined in what appears to be an earlier frag. FIXME:
12307 This doesn't handle the fr_subtype field, which specifies
12308 a maximum number of bytes to skip when doing an
12310 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
12312 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
12315 stretch
= - ((- stretch
)
12316 & ~ ((1 << (int) f
->fr_offset
) - 1));
12318 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
12327 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
12329 /* The base address rules are complicated. The base address of
12330 a branch is the following instruction. The base address of a
12331 PC relative load or add is the instruction itself, but if it
12332 is in a delay slot (in which case it can not be extended) use
12333 the address of the instruction whose delay slot it is in. */
12334 if (type
== 'p' || type
== 'q')
12338 /* If we are currently assuming that this frag should be
12339 extended, then, the current address is two bytes
12341 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12344 /* Ignore the low bit in the target, since it will be set
12345 for a text label. */
12346 if ((val
& 1) != 0)
12349 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
12351 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
12354 val
-= addr
& ~ ((1 << op
->shift
) - 1);
12356 /* Branch offsets have an implicit 0 in the lowest bit. */
12357 if (type
== 'p' || type
== 'q')
12360 /* If any of the shifted bits are set, we must use an extended
12361 opcode. If the address depends on the size of this
12362 instruction, this can lead to a loop, so we arrange to always
12363 use an extended opcode. We only check this when we are in
12364 the main relaxation loop, when SEC is NULL. */
12365 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
12367 fragp
->fr_subtype
=
12368 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12372 /* If we are about to mark a frag as extended because the value
12373 is precisely maxtiny + 1, then there is a chance of an
12374 infinite loop as in the following code:
12379 In this case when the la is extended, foo is 0x3fc bytes
12380 away, so the la can be shrunk, but then foo is 0x400 away, so
12381 the la must be extended. To avoid this loop, we mark the
12382 frag as extended if it was small, and is about to become
12383 extended with a value of maxtiny + 1. */
12384 if (val
== ((maxtiny
+ 1) << op
->shift
)
12385 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
12388 fragp
->fr_subtype
=
12389 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12393 else if (symsec
!= absolute_section
&& sec
!= NULL
)
12394 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
12396 if ((val
& ((1 << op
->shift
) - 1)) != 0
12397 || val
< (mintiny
<< op
->shift
)
12398 || val
> (maxtiny
<< op
->shift
))
12404 /* Estimate the size of a frag before relaxing. Unless this is the
12405 mips16, we are not really relaxing here, and the final size is
12406 encoded in the subtype information. For the mips16, we have to
12407 decide whether we are using an extended opcode or not. */
12410 md_estimate_size_before_relax (fragp
, segtype
)
12415 boolean linkonce
= false;
12417 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
12418 /* We don't want to modify the EXTENDED bit here; it might get us
12419 into infinite loops. We change it only in mips_relax_frag(). */
12420 return (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2);
12422 if (mips_pic
== NO_PIC
)
12424 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
12426 else if (mips_pic
== SVR4_PIC
)
12431 sym
= fragp
->fr_symbol
;
12433 /* Handle the case of a symbol equated to another symbol. */
12434 while (symbol_equated_reloc_p (sym
))
12438 /* It's possible to get a loop here in a badly written
12440 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
12446 symsec
= S_GET_SEGMENT (sym
);
12448 /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
12449 if (symsec
!= segtype
&& ! S_IS_LOCAL (sym
))
12451 if ((bfd_get_section_flags (stdoutput
, symsec
) & SEC_LINK_ONCE
)
12455 /* The GNU toolchain uses an extension for ELF: a section
12456 beginning with the magic string .gnu.linkonce is a linkonce
12458 if (strncmp (segment_name (symsec
), ".gnu.linkonce",
12459 sizeof ".gnu.linkonce" - 1) == 0)
12463 /* This must duplicate the test in adjust_reloc_syms. */
12464 change
= (symsec
!= &bfd_und_section
12465 && symsec
!= &bfd_abs_section
12466 && ! bfd_is_com_section (symsec
)
12469 /* A global or weak symbol is treated as external. */
12470 && (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
12471 || (! S_IS_WEAK (sym
)
12472 && (! S_IS_EXTERN (sym
) || mips_pic
== EMBEDDED_PIC
)))
12481 /* Record the offset to the first reloc in the fr_opcode field.
12482 This lets md_convert_frag and tc_gen_reloc know that the code
12483 must be expanded. */
12484 fragp
->fr_opcode
= (fragp
->fr_literal
12486 - RELAX_OLD (fragp
->fr_subtype
)
12487 + RELAX_RELOC1 (fragp
->fr_subtype
));
12488 /* FIXME: This really needs as_warn_where. */
12489 if (RELAX_WARN (fragp
->fr_subtype
))
12490 as_warn (_("AT used after \".set noat\" or macro used after "
12491 "\".set nomacro\""));
12493 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
12499 /* This is called to see whether a reloc against a defined symbol
12500 should be converted into a reloc against a section. Don't adjust
12501 MIPS16 jump relocations, so we don't have to worry about the format
12502 of the offset in the .o file. Don't adjust relocations against
12503 mips16 symbols, so that the linker can find them if it needs to set
12507 mips_fix_adjustable (fixp
)
12511 /* Prevent all adjustments to global symbols. */
12512 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
12513 && mips_pic
!= EMBEDDED_PIC
12514 && (S_IS_EXTERN (fixp
->fx_addsy
) || S_IS_WEAK (fixp
->fx_addsy
)))
12517 if (fixp
->fx_r_type
== BFD_RELOC_MIPS16_JMP
)
12519 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
12520 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
12522 if (fixp
->fx_addsy
== NULL
)
12525 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
12526 && S_GET_OTHER (fixp
->fx_addsy
) == STO_MIPS16
12527 && fixp
->fx_subsy
== NULL
)
12533 /* Translate internal representation of relocation info to BFD target
12537 tc_gen_reloc (section
, fixp
)
12538 asection
*section ATTRIBUTE_UNUSED
;
12541 static arelent
*retval
[4];
12543 bfd_reloc_code_real_type code
;
12545 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
12548 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
12549 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
12550 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
12552 if (mips_pic
== EMBEDDED_PIC
12553 && SWITCH_TABLE (fixp
))
12555 /* For a switch table entry we use a special reloc. The addend
12556 is actually the difference between the reloc address and the
12558 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
12559 if (OUTPUT_FLAVOR
!= bfd_target_ecoff_flavour
)
12560 as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc"));
12561 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
12563 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
12565 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
12566 reloc
->addend
= fixp
->fx_addnumber
;
12569 /* We use a special addend for an internal RELLO reloc. */
12570 if (symbol_section_p (fixp
->fx_addsy
))
12571 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
12573 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
12576 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
12578 assert (fixp
->fx_next
!= NULL
12579 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
12581 /* The reloc is relative to the RELLO; adjust the addend
12583 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
12584 reloc
->addend
= fixp
->fx_next
->fx_addnumber
;
12587 /* We use a special addend for an internal RELHI reloc. */
12588 if (symbol_section_p (fixp
->fx_addsy
))
12589 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
12590 + fixp
->fx_next
->fx_where
12591 - S_GET_VALUE (fixp
->fx_subsy
));
12593 reloc
->addend
= (fixp
->fx_addnumber
12594 + fixp
->fx_next
->fx_frag
->fr_address
12595 + fixp
->fx_next
->fx_where
);
12598 else if (fixp
->fx_pcrel
== 0 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
12599 reloc
->addend
= fixp
->fx_addnumber
;
12602 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
)
12603 /* A gruesome hack which is a result of the gruesome gas reloc
12605 reloc
->addend
= reloc
->address
;
12607 reloc
->addend
= -reloc
->address
;
12610 /* If this is a variant frag, we may need to adjust the existing
12611 reloc and generate a new one. */
12612 if (fixp
->fx_frag
->fr_opcode
!= NULL
12613 && (fixp
->fx_r_type
== BFD_RELOC_GPREL16
12614 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
12615 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
12616 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
12617 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_LO16
12618 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
12619 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_LO16
)
12624 assert (! RELAX_MIPS16_P (fixp
->fx_frag
->fr_subtype
));
12626 /* If this is not the last reloc in this frag, then we have two
12627 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
12628 CALL_HI16/CALL_LO16, both of which are being replaced. Let
12629 the second one handle all of them. */
12630 if (fixp
->fx_next
!= NULL
12631 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
12633 assert ((fixp
->fx_r_type
== BFD_RELOC_GPREL16
12634 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_GPREL16
)
12635 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
12636 && (fixp
->fx_next
->fx_r_type
12637 == BFD_RELOC_MIPS_GOT_LO16
))
12638 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
12639 && (fixp
->fx_next
->fx_r_type
12640 == BFD_RELOC_MIPS_CALL_LO16
)));
12645 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
12646 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
12647 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
12649 reloc2
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
12650 *reloc2
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
12651 reloc2
->address
= (reloc
->address
12652 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
12653 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
12654 reloc2
->addend
= fixp
->fx_addnumber
;
12655 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
12656 assert (reloc2
->howto
!= NULL
);
12658 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
12662 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
12665 reloc3
->address
+= 4;
12668 if (mips_pic
== NO_PIC
)
12670 assert (fixp
->fx_r_type
== BFD_RELOC_GPREL16
);
12671 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
12673 else if (mips_pic
== SVR4_PIC
)
12675 switch (fixp
->fx_r_type
)
12679 case BFD_RELOC_MIPS_GOT16
:
12681 case BFD_RELOC_MIPS_CALL16
:
12682 case BFD_RELOC_MIPS_GOT_LO16
:
12683 case BFD_RELOC_MIPS_CALL_LO16
:
12684 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
12692 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
12693 entry to be used in the relocation's section offset. */
12694 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
12696 reloc
->address
= reloc
->addend
;
12700 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
12701 fixup_segment converted a non-PC relative reloc into a PC
12702 relative reloc. In such a case, we need to convert the reloc
12704 code
= fixp
->fx_r_type
;
12705 if (fixp
->fx_pcrel
)
12710 code
= BFD_RELOC_8_PCREL
;
12713 code
= BFD_RELOC_16_PCREL
;
12716 code
= BFD_RELOC_32_PCREL
;
12719 code
= BFD_RELOC_64_PCREL
;
12721 case BFD_RELOC_8_PCREL
:
12722 case BFD_RELOC_16_PCREL
:
12723 case BFD_RELOC_32_PCREL
:
12724 case BFD_RELOC_64_PCREL
:
12725 case BFD_RELOC_16_PCREL_S2
:
12726 case BFD_RELOC_PCREL_HI16_S
:
12727 case BFD_RELOC_PCREL_LO16
:
12730 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12731 _("Cannot make %s relocation PC relative"),
12732 bfd_get_reloc_code_name (code
));
12737 /* md_apply_fix3 has a double-subtraction hack to get
12738 bfd_install_relocation to behave nicely. GPREL relocations are
12739 handled correctly without this hack, so undo it here. We can't
12740 stop md_apply_fix3 from subtracting twice in the first place since
12741 the fake addend is required for variant frags above. */
12742 if (fixp
->fx_addsy
!= NULL
&& OUTPUT_FLAVOR
== bfd_target_elf_flavour
12743 && code
== BFD_RELOC_GPREL16
12744 && reloc
->addend
!= 0
12745 && mips_need_elf_addend_fixup (fixp
))
12746 reloc
->addend
+= S_GET_VALUE (fixp
->fx_addsy
);
12749 /* To support a PC relative reloc when generating embedded PIC code
12750 for ECOFF, we use a Cygnus extension. We check for that here to
12751 make sure that we don't let such a reloc escape normally. */
12752 if ((OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
12753 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
12754 && code
== BFD_RELOC_16_PCREL_S2
12755 && mips_pic
!= EMBEDDED_PIC
)
12756 reloc
->howto
= NULL
;
12758 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
12760 if (reloc
->howto
== NULL
)
12762 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12763 _("Can not represent %s relocation in this object file format"),
12764 bfd_get_reloc_code_name (code
));
12771 /* Relax a machine dependent frag. This returns the amount by which
12772 the current size of the frag should change. */
12775 mips_relax_frag (fragp
, stretch
)
12779 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
12782 if (mips16_extended_frag (fragp
, NULL
, stretch
))
12784 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12786 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
12791 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12793 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
12800 /* Convert a machine dependent frag. */
12803 md_convert_frag (abfd
, asec
, fragp
)
12804 bfd
*abfd ATTRIBUTE_UNUSED
;
12811 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
12814 register const struct mips16_immed_operand
*op
;
12815 boolean small
, ext
;
12818 unsigned long insn
;
12819 boolean use_extend
;
12820 unsigned short extend
;
12822 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
12823 op
= mips16_immed_operands
;
12824 while (op
->type
!= type
)
12827 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12838 resolve_symbol_value (fragp
->fr_symbol
);
12839 val
= S_GET_VALUE (fragp
->fr_symbol
);
12844 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
12846 /* The rules for the base address of a PC relative reloc are
12847 complicated; see mips16_extended_frag. */
12848 if (type
== 'p' || type
== 'q')
12853 /* Ignore the low bit in the target, since it will be
12854 set for a text label. */
12855 if ((val
& 1) != 0)
12858 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
12860 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
12863 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
12866 /* Make sure the section winds up with the alignment we have
12869 record_alignment (asec
, op
->shift
);
12873 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
12874 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
12875 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
12876 _("extended instruction in delay slot"));
12878 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
12880 if (target_big_endian
)
12881 insn
= bfd_getb16 (buf
);
12883 insn
= bfd_getl16 (buf
);
12885 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
12886 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
12887 small
, ext
, &insn
, &use_extend
, &extend
);
12891 md_number_to_chars ((char *) buf
, 0xf000 | extend
, 2);
12892 fragp
->fr_fix
+= 2;
12896 md_number_to_chars ((char *) buf
, insn
, 2);
12897 fragp
->fr_fix
+= 2;
12902 if (fragp
->fr_opcode
== NULL
)
12905 old
= RELAX_OLD (fragp
->fr_subtype
);
12906 new = RELAX_NEW (fragp
->fr_subtype
);
12907 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
12910 memcpy (fixptr
- old
, fixptr
, new);
12912 fragp
->fr_fix
+= new - old
;
12918 /* This function is called after the relocs have been generated.
12919 We've been storing mips16 text labels as odd. Here we convert them
12920 back to even for the convenience of the debugger. */
12923 mips_frob_file_after_relocs ()
12926 unsigned int count
, i
;
12928 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
12931 syms
= bfd_get_outsymbols (stdoutput
);
12932 count
= bfd_get_symcount (stdoutput
);
12933 for (i
= 0; i
< count
; i
++, syms
++)
12935 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
12936 && ((*syms
)->value
& 1) != 0)
12938 (*syms
)->value
&= ~1;
12939 /* If the symbol has an odd size, it was probably computed
12940 incorrectly, so adjust that as well. */
12941 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
12942 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
12949 /* This function is called whenever a label is defined. It is used
12950 when handling branch delays; if a branch has a label, we assume we
12951 can not move it. */
12954 mips_define_label (sym
)
12957 struct insn_label_list
*l
;
12959 if (free_insn_labels
== NULL
)
12960 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
12963 l
= free_insn_labels
;
12964 free_insn_labels
= l
->next
;
12968 l
->next
= insn_labels
;
12972 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12974 /* Some special processing for a MIPS ELF file. */
12977 mips_elf_final_processing ()
12979 /* Write out the register information. */
12980 if (file_mips_abi
!= N64_ABI
)
12984 s
.ri_gprmask
= mips_gprmask
;
12985 s
.ri_cprmask
[0] = mips_cprmask
[0];
12986 s
.ri_cprmask
[1] = mips_cprmask
[1];
12987 s
.ri_cprmask
[2] = mips_cprmask
[2];
12988 s
.ri_cprmask
[3] = mips_cprmask
[3];
12989 /* The gp_value field is set by the MIPS ELF backend. */
12991 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
12992 ((Elf32_External_RegInfo
*)
12993 mips_regmask_frag
));
12997 Elf64_Internal_RegInfo s
;
12999 s
.ri_gprmask
= mips_gprmask
;
13001 s
.ri_cprmask
[0] = mips_cprmask
[0];
13002 s
.ri_cprmask
[1] = mips_cprmask
[1];
13003 s
.ri_cprmask
[2] = mips_cprmask
[2];
13004 s
.ri_cprmask
[3] = mips_cprmask
[3];
13005 /* The gp_value field is set by the MIPS ELF backend. */
13007 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
13008 ((Elf64_External_RegInfo
*)
13009 mips_regmask_frag
));
13012 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
13013 sort of BFD interface for this. */
13014 if (mips_any_noreorder
)
13015 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
13016 if (mips_pic
!= NO_PIC
)
13017 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
13019 /* Set MIPS ELF flags for ASEs. */
13020 #if 0 /* XXX FIXME */
13021 if (file_ase_mips3d
)
13022 elf_elfheader (stdoutput
)->e_flags
|= ???;
13025 /* Set the MIPS ELF ABI flags. */
13026 if (file_mips_abi
== NO_ABI
)
13028 else if (file_mips_abi
== O32_ABI
)
13029 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
13030 else if (file_mips_abi
== O64_ABI
)
13031 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
13032 else if (file_mips_abi
== EABI_ABI
)
13035 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
13037 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
13039 else if (file_mips_abi
== N32_ABI
)
13040 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
13042 /* Nothing to do for N64_ABI. */
13044 if (mips_32bitmode
)
13045 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
13048 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
13050 typedef struct proc
{
13052 unsigned long reg_mask
;
13053 unsigned long reg_offset
;
13054 unsigned long fpreg_mask
;
13055 unsigned long fpreg_offset
;
13056 unsigned long frame_offset
;
13057 unsigned long frame_reg
;
13058 unsigned long pc_reg
;
13061 static procS cur_proc
;
13062 static procS
*cur_proc_ptr
;
13063 static int numprocs
;
13065 /* Fill in an rs_align_code fragment. */
13068 mips_handle_align (fragp
)
13071 if (fragp
->fr_type
!= rs_align_code
)
13074 if (mips_opts
.mips16
)
13076 static const unsigned char be_nop
[] = { 0x65, 0x00 };
13077 static const unsigned char le_nop
[] = { 0x00, 0x65 };
13082 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
13083 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
13091 memcpy (p
, (target_big_endian
? be_nop
: le_nop
), 2);
13095 /* For mips32, a nop is a zero, which we trivially get by doing nothing. */
13106 /* check for premature end, nesting errors, etc */
13108 as_warn (_("missing .end at end of assembly"));
13117 if (*input_line_pointer
== '-')
13119 ++input_line_pointer
;
13122 if (!ISDIGIT (*input_line_pointer
))
13123 as_bad (_("expected simple number"));
13124 if (input_line_pointer
[0] == '0')
13126 if (input_line_pointer
[1] == 'x')
13128 input_line_pointer
+= 2;
13129 while (ISXDIGIT (*input_line_pointer
))
13132 val
|= hex_value (*input_line_pointer
++);
13134 return negative
? -val
: val
;
13138 ++input_line_pointer
;
13139 while (ISDIGIT (*input_line_pointer
))
13142 val
|= *input_line_pointer
++ - '0';
13144 return negative
? -val
: val
;
13147 if (!ISDIGIT (*input_line_pointer
))
13149 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
13150 *input_line_pointer
, *input_line_pointer
);
13151 as_warn (_("invalid number"));
13154 while (ISDIGIT (*input_line_pointer
))
13157 val
+= *input_line_pointer
++ - '0';
13159 return negative
? -val
: val
;
13162 /* The .file directive; just like the usual .file directive, but there
13163 is an initial number which is the ECOFF file index. */
13167 int x ATTRIBUTE_UNUSED
;
13173 /* The .end directive. */
13177 int x ATTRIBUTE_UNUSED
;
13182 /* Following functions need their own .frame and .cprestore directives. */
13183 mips_frame_reg_valid
= 0;
13184 mips_cprestore_valid
= 0;
13186 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
13189 demand_empty_rest_of_line ();
13194 #ifdef BFD_ASSEMBLER
13195 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
13200 if (now_seg
!= data_section
&& now_seg
!= bss_section
)
13207 as_warn (_(".end not in text section"));
13211 as_warn (_(".end directive without a preceding .ent directive."));
13212 demand_empty_rest_of_line ();
13218 assert (S_GET_NAME (p
));
13219 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->isym
)))
13220 as_warn (_(".end symbol does not match .ent symbol."));
13223 as_warn (_(".end directive missing or unknown symbol"));
13225 #ifdef MIPS_STABS_ELF
13227 segT saved_seg
= now_seg
;
13228 subsegT saved_subseg
= now_subseg
;
13233 dot
= frag_now_fix ();
13235 #ifdef md_flush_pending_output
13236 md_flush_pending_output ();
13240 subseg_set (pdr_seg
, 0);
13242 /* Write the symbol. */
13243 exp
.X_op
= O_symbol
;
13244 exp
.X_add_symbol
= p
;
13245 exp
.X_add_number
= 0;
13246 emit_expr (&exp
, 4);
13248 fragp
= frag_more (7 * 4);
13250 md_number_to_chars (fragp
, (valueT
) cur_proc_ptr
->reg_mask
, 4);
13251 md_number_to_chars (fragp
+ 4, (valueT
) cur_proc_ptr
->reg_offset
, 4);
13252 md_number_to_chars (fragp
+ 8, (valueT
) cur_proc_ptr
->fpreg_mask
, 4);
13253 md_number_to_chars (fragp
+ 12, (valueT
) cur_proc_ptr
->fpreg_offset
, 4);
13254 md_number_to_chars (fragp
+ 16, (valueT
) cur_proc_ptr
->frame_offset
, 4);
13255 md_number_to_chars (fragp
+ 20, (valueT
) cur_proc_ptr
->frame_reg
, 4);
13256 md_number_to_chars (fragp
+ 24, (valueT
) cur_proc_ptr
->pc_reg
, 4);
13258 subseg_set (saved_seg
, saved_subseg
);
13260 #endif /* MIPS_STABS_ELF */
13262 cur_proc_ptr
= NULL
;
13265 /* The .aent and .ent directives. */
13274 symbolP
= get_symbol ();
13275 if (*input_line_pointer
== ',')
13276 ++input_line_pointer
;
13277 SKIP_WHITESPACE ();
13278 if (ISDIGIT (*input_line_pointer
)
13279 || *input_line_pointer
== '-')
13282 #ifdef BFD_ASSEMBLER
13283 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
13288 if (now_seg
!= data_section
&& now_seg
!= bss_section
)
13295 as_warn (_(".ent or .aent not in text section."));
13297 if (!aent
&& cur_proc_ptr
)
13298 as_warn (_("missing .end"));
13302 /* This function needs its own .frame and .cprestore directives. */
13303 mips_frame_reg_valid
= 0;
13304 mips_cprestore_valid
= 0;
13306 cur_proc_ptr
= &cur_proc
;
13307 memset (cur_proc_ptr
, '\0', sizeof (procS
));
13309 cur_proc_ptr
->isym
= symbolP
;
13311 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
13316 demand_empty_rest_of_line ();
13319 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
13320 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
13321 s_mips_frame is used so that we can set the PDR information correctly.
13322 We can't use the ecoff routines because they make reference to the ecoff
13323 symbol table (in the mdebug section). */
13326 s_mips_frame (ignore
)
13327 int ignore ATTRIBUTE_UNUSED
;
13329 #ifdef MIPS_STABS_ELF
13333 if (cur_proc_ptr
== (procS
*) NULL
)
13335 as_warn (_(".frame outside of .ent"));
13336 demand_empty_rest_of_line ();
13340 cur_proc_ptr
->frame_reg
= tc_get_register (1);
13342 SKIP_WHITESPACE ();
13343 if (*input_line_pointer
++ != ','
13344 || get_absolute_expression_and_terminator (&val
) != ',')
13346 as_warn (_("Bad .frame directive"));
13347 --input_line_pointer
;
13348 demand_empty_rest_of_line ();
13352 cur_proc_ptr
->frame_offset
= val
;
13353 cur_proc_ptr
->pc_reg
= tc_get_register (0);
13355 demand_empty_rest_of_line ();
13358 #endif /* MIPS_STABS_ELF */
13361 /* The .fmask and .mask directives. If the mdebug section is present
13362 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
13363 embedded targets, s_mips_mask is used so that we can set the PDR
13364 information correctly. We can't use the ecoff routines because they
13365 make reference to the ecoff symbol table (in the mdebug section). */
13368 s_mips_mask (reg_type
)
13371 #ifdef MIPS_STABS_ELF
13374 if (cur_proc_ptr
== (procS
*) NULL
)
13376 as_warn (_(".mask/.fmask outside of .ent"));
13377 demand_empty_rest_of_line ();
13381 if (get_absolute_expression_and_terminator (&mask
) != ',')
13383 as_warn (_("Bad .mask/.fmask directive"));
13384 --input_line_pointer
;
13385 demand_empty_rest_of_line ();
13389 off
= get_absolute_expression ();
13391 if (reg_type
== 'F')
13393 cur_proc_ptr
->fpreg_mask
= mask
;
13394 cur_proc_ptr
->fpreg_offset
= off
;
13398 cur_proc_ptr
->reg_mask
= mask
;
13399 cur_proc_ptr
->reg_offset
= off
;
13402 demand_empty_rest_of_line ();
13404 s_ignore (reg_type
);
13405 #endif /* MIPS_STABS_ELF */
13408 /* The .loc directive. */
13419 assert (now_seg
== text_section
);
13421 lineno
= get_number ();
13422 addroff
= frag_now_fix ();
13424 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
13425 S_SET_TYPE (symbolP
, N_SLINE
);
13426 S_SET_OTHER (symbolP
, 0);
13427 S_SET_DESC (symbolP
, lineno
);
13428 symbolP
->sy_segment
= now_seg
;
13432 /* CPU name/ISA/number mapping table.
13434 Entries are grouped by type. The first matching CPU or ISA entry
13435 gets chosen by CPU or ISA, so it should be the 'canonical' name
13436 for that type. Entries after that within the type are sorted
13439 Case is ignored in comparison, so put the canonical entry in the
13440 appropriate case but everything else in lower case to ease eye pain. */
13441 static const struct mips_cpu_info mips_cpu_info_table
[] =
13444 { "MIPS1", 1, ISA_MIPS1
, CPU_R3000
, },
13445 { "mips", 1, ISA_MIPS1
, CPU_R3000
, },
13448 { "MIPS2", 1, ISA_MIPS2
, CPU_R6000
, },
13451 { "MIPS3", 1, ISA_MIPS3
, CPU_R4000
, },
13454 { "MIPS4", 1, ISA_MIPS4
, CPU_R8000
, },
13457 { "MIPS5", 1, ISA_MIPS5
, CPU_MIPS5
, },
13458 { "Generic-MIPS5", 0, ISA_MIPS5
, CPU_MIPS5
, },
13461 { "MIPS32", 1, ISA_MIPS32
, CPU_MIPS32
, },
13462 { "mipsisa32", 0, ISA_MIPS32
, CPU_MIPS32
, },
13463 { "Generic-MIPS32", 0, ISA_MIPS32
, CPU_MIPS32
, },
13464 { "4kc", 0, ISA_MIPS32
, CPU_MIPS32
, },
13465 { "4km", 0, ISA_MIPS32
, CPU_MIPS32
, },
13466 { "4kp", 0, ISA_MIPS32
, CPU_MIPS32
, },
13468 /* For historical reasons. */
13469 { "MIPS64", 1, ISA_MIPS3
, CPU_R4000
, },
13472 { "mipsisa64", 1, ISA_MIPS64
, CPU_MIPS64
, },
13473 { "Generic-MIPS64", 0, ISA_MIPS64
, CPU_MIPS64
, },
13474 { "5kc", 0, ISA_MIPS64
, CPU_MIPS64
, },
13475 { "20kc", 0, ISA_MIPS64
, CPU_MIPS64
, },
13478 { "R2000", 0, ISA_MIPS1
, CPU_R2000
, },
13479 { "2000", 0, ISA_MIPS1
, CPU_R2000
, },
13480 { "2k", 0, ISA_MIPS1
, CPU_R2000
, },
13481 { "r2k", 0, ISA_MIPS1
, CPU_R2000
, },
13484 { "R3000", 0, ISA_MIPS1
, CPU_R3000
, },
13485 { "3000", 0, ISA_MIPS1
, CPU_R3000
, },
13486 { "3k", 0, ISA_MIPS1
, CPU_R3000
, },
13487 { "r3k", 0, ISA_MIPS1
, CPU_R3000
, },
13490 { "R3900", 0, ISA_MIPS1
, CPU_R3900
, },
13491 { "3900", 0, ISA_MIPS1
, CPU_R3900
, },
13492 { "mipstx39", 0, ISA_MIPS1
, CPU_R3900
, },
13495 { "R4000", 0, ISA_MIPS3
, CPU_R4000
, },
13496 { "4000", 0, ISA_MIPS3
, CPU_R4000
, },
13497 { "4k", 0, ISA_MIPS3
, CPU_R4000
, }, /* beware */
13498 { "r4k", 0, ISA_MIPS3
, CPU_R4000
, },
13501 { "R4010", 0, ISA_MIPS2
, CPU_R4010
, },
13502 { "4010", 0, ISA_MIPS2
, CPU_R4010
, },
13505 { "R4400", 0, ISA_MIPS3
, CPU_R4400
, },
13506 { "4400", 0, ISA_MIPS3
, CPU_R4400
, },
13509 { "R4600", 0, ISA_MIPS3
, CPU_R4600
, },
13510 { "4600", 0, ISA_MIPS3
, CPU_R4600
, },
13511 { "mips64orion", 0, ISA_MIPS3
, CPU_R4600
, },
13512 { "orion", 0, ISA_MIPS3
, CPU_R4600
, },
13515 { "R4650", 0, ISA_MIPS3
, CPU_R4650
, },
13516 { "4650", 0, ISA_MIPS3
, CPU_R4650
, },
13519 { "R6000", 0, ISA_MIPS2
, CPU_R6000
, },
13520 { "6000", 0, ISA_MIPS2
, CPU_R6000
, },
13521 { "6k", 0, ISA_MIPS2
, CPU_R6000
, },
13522 { "r6k", 0, ISA_MIPS2
, CPU_R6000
, },
13525 { "R8000", 0, ISA_MIPS4
, CPU_R8000
, },
13526 { "8000", 0, ISA_MIPS4
, CPU_R8000
, },
13527 { "8k", 0, ISA_MIPS4
, CPU_R8000
, },
13528 { "r8k", 0, ISA_MIPS4
, CPU_R8000
, },
13531 { "R10000", 0, ISA_MIPS4
, CPU_R10000
, },
13532 { "10000", 0, ISA_MIPS4
, CPU_R10000
, },
13533 { "10k", 0, ISA_MIPS4
, CPU_R10000
, },
13534 { "r10k", 0, ISA_MIPS4
, CPU_R10000
, },
13537 { "R12000", 0, ISA_MIPS4
, CPU_R12000
, },
13538 { "12000", 0, ISA_MIPS4
, CPU_R12000
, },
13539 { "12k", 0, ISA_MIPS4
, CPU_R12000
, },
13540 { "r12k", 0, ISA_MIPS4
, CPU_R12000
, },
13543 { "VR4100", 0, ISA_MIPS3
, CPU_VR4100
, },
13544 { "4100", 0, ISA_MIPS3
, CPU_VR4100
, },
13545 { "mips64vr4100", 0, ISA_MIPS3
, CPU_VR4100
, },
13546 { "r4100", 0, ISA_MIPS3
, CPU_VR4100
, },
13549 { "VR4111", 0, ISA_MIPS3
, CPU_R4111
, },
13550 { "4111", 0, ISA_MIPS3
, CPU_R4111
, },
13551 { "mips64vr4111", 0, ISA_MIPS3
, CPU_R4111
, },
13552 { "r4111", 0, ISA_MIPS3
, CPU_R4111
, },
13555 { "VR4300", 0, ISA_MIPS3
, CPU_R4300
, },
13556 { "4300", 0, ISA_MIPS3
, CPU_R4300
, },
13557 { "mips64vr4300", 0, ISA_MIPS3
, CPU_R4300
, },
13558 { "r4300", 0, ISA_MIPS3
, CPU_R4300
, },
13561 { "VR5000", 0, ISA_MIPS4
, CPU_R5000
, },
13562 { "5000", 0, ISA_MIPS4
, CPU_R5000
, },
13563 { "5k", 0, ISA_MIPS4
, CPU_R5000
, },
13564 { "mips64vr5000", 0, ISA_MIPS4
, CPU_R5000
, },
13565 { "r5000", 0, ISA_MIPS4
, CPU_R5000
, },
13566 { "r5200", 0, ISA_MIPS4
, CPU_R5000
, },
13567 { "rm5200", 0, ISA_MIPS4
, CPU_R5000
, },
13568 { "r5230", 0, ISA_MIPS4
, CPU_R5000
, },
13569 { "rm5230", 0, ISA_MIPS4
, CPU_R5000
, },
13570 { "r5231", 0, ISA_MIPS4
, CPU_R5000
, },
13571 { "rm5231", 0, ISA_MIPS4
, CPU_R5000
, },
13572 { "r5261", 0, ISA_MIPS4
, CPU_R5000
, },
13573 { "rm5261", 0, ISA_MIPS4
, CPU_R5000
, },
13574 { "r5721", 0, ISA_MIPS4
, CPU_R5000
, },
13575 { "rm5721", 0, ISA_MIPS4
, CPU_R5000
, },
13576 { "r5k", 0, ISA_MIPS4
, CPU_R5000
, },
13577 { "r7000", 0, ISA_MIPS4
, CPU_R5000
, },
13579 /* Broadcom SB-1 CPU */
13580 { "SB-1", 0, ISA_MIPS64
, CPU_SB1
, },
13581 { "sb-1250", 0, ISA_MIPS64
, CPU_SB1
, },
13582 { "sb1", 0, ISA_MIPS64
, CPU_SB1
, },
13583 { "sb1250", 0, ISA_MIPS64
, CPU_SB1
, },
13586 { NULL
, 0, 0, 0, },
13589 static const struct mips_cpu_info
*
13590 mips_cpu_info_from_name (name
)
13595 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
13596 if (strcasecmp (name
, mips_cpu_info_table
[i
].name
) == 0)
13597 return (&mips_cpu_info_table
[i
]);
13602 static const struct mips_cpu_info
*
13603 mips_cpu_info_from_isa (isa
)
13608 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
13609 if (mips_cpu_info_table
[i
].is_isa
13610 && isa
== mips_cpu_info_table
[i
].isa
)
13611 return (&mips_cpu_info_table
[i
]);
13616 static const struct mips_cpu_info
*
13617 mips_cpu_info_from_cpu (cpu
)
13622 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
13623 if (!mips_cpu_info_table
[i
].is_isa
13624 && cpu
== mips_cpu_info_table
[i
].cpu
)
13625 return (&mips_cpu_info_table
[i
]);