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[binutils.git] / opcodes / ppc-opc.c
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1 /* ppc-opc.c -- PowerPC opcode list
2 Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2004
3 Free Software Foundation, Inc.
4 Written by Ian Lance Taylor, Cygnus Support
6 This file is part of GDB, GAS, and the GNU binutils.
8 GDB, GAS, and the GNU binutils are free software; you can redistribute
9 them and/or modify them under the terms of the GNU General Public
10 License as published by the Free Software Foundation; either version
11 2, or (at your option) any later version.
13 GDB, GAS, and the GNU binutils are distributed in the hope that they
14 will be useful, but WITHOUT ANY WARRANTY; without even the implied
15 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
16 the GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this file; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
21 02111-1307, USA. */
23 #include <stdio.h>
24 #include "sysdep.h"
25 #include "opcode/ppc.h"
26 #include "opintl.h"
28 /* This file holds the PowerPC opcode table. The opcode table
29 includes almost all of the extended instruction mnemonics. This
30 permits the disassembler to use them, and simplifies the assembler
31 logic, at the cost of increasing the table size. The table is
32 strictly constant data, so the compiler should be able to put it in
33 the .text section.
35 This file also holds the operand table. All knowledge about
36 inserting operands into instructions and vice-versa is kept in this
37 file. */
39 /* Local insertion and extraction functions. */
41 static unsigned long insert_bat (unsigned long, long, int, const char **);
42 static long extract_bat (unsigned long, int, int *);
43 static unsigned long insert_bba (unsigned long, long, int, const char **);
44 static long extract_bba (unsigned long, int, int *);
45 static unsigned long insert_bd (unsigned long, long, int, const char **);
46 static long extract_bd (unsigned long, int, int *);
47 static unsigned long insert_bdm (unsigned long, long, int, const char **);
48 static long extract_bdm (unsigned long, int, int *);
49 static unsigned long insert_bdp (unsigned long, long, int, const char **);
50 static long extract_bdp (unsigned long, int, int *);
51 static unsigned long insert_bo (unsigned long, long, int, const char **);
52 static long extract_bo (unsigned long, int, int *);
53 static unsigned long insert_boe (unsigned long, long, int, const char **);
54 static long extract_boe (unsigned long, int, int *);
55 static unsigned long insert_dq (unsigned long, long, int, const char **);
56 static long extract_dq (unsigned long, int, int *);
57 static unsigned long insert_ds (unsigned long, long, int, const char **);
58 static long extract_ds (unsigned long, int, int *);
59 static unsigned long insert_de (unsigned long, long, int, const char **);
60 static long extract_de (unsigned long, int, int *);
61 static unsigned long insert_des (unsigned long, long, int, const char **);
62 static long extract_des (unsigned long, int, int *);
63 static unsigned long insert_fxm (unsigned long, long, int, const char **);
64 static long extract_fxm (unsigned long, int, int *);
65 static unsigned long insert_li (unsigned long, long, int, const char **);
66 static long extract_li (unsigned long, int, int *);
67 static unsigned long insert_mbe (unsigned long, long, int, const char **);
68 static long extract_mbe (unsigned long, int, int *);
69 static unsigned long insert_mb6 (unsigned long, long, int, const char **);
70 static long extract_mb6 (unsigned long, int, int *);
71 static unsigned long insert_nb (unsigned long, long, int, const char **);
72 static long extract_nb (unsigned long, int, int *);
73 static unsigned long insert_nsi (unsigned long, long, int, const char **);
74 static long extract_nsi (unsigned long, int, int *);
75 static unsigned long insert_ral (unsigned long, long, int, const char **);
76 static unsigned long insert_ram (unsigned long, long, int, const char **);
77 static unsigned long insert_raq (unsigned long, long, int, const char **);
78 static unsigned long insert_ras (unsigned long, long, int, const char **);
79 static unsigned long insert_rbs (unsigned long, long, int, const char **);
80 static long extract_rbs (unsigned long, int, int *);
81 static unsigned long insert_rsq (unsigned long, long, int, const char **);
82 static unsigned long insert_rtq (unsigned long, long, int, const char **);
83 static unsigned long insert_sh6 (unsigned long, long, int, const char **);
84 static long extract_sh6 (unsigned long, int, int *);
85 static unsigned long insert_spr (unsigned long, long, int, const char **);
86 static long extract_spr (unsigned long, int, int *);
87 static unsigned long insert_tbr (unsigned long, long, int, const char **);
88 static long extract_tbr (unsigned long, int, int *);
89 static unsigned long insert_ev2 (unsigned long, long, int, const char **);
90 static long extract_ev2 (unsigned long, int, int *);
91 static unsigned long insert_ev4 (unsigned long, long, int, const char **);
92 static long extract_ev4 (unsigned long, int, int *);
93 static unsigned long insert_ev8 (unsigned long, long, int, const char **);
94 static long extract_ev8 (unsigned long, int, int *);
96 /* The operands table.
98 The fields are bits, shift, insert, extract, flags.
100 We used to put parens around the various additions, like the one
101 for BA just below. However, that caused trouble with feeble
102 compilers with a limit on depth of a parenthesized expression, like
103 (reportedly) the compiler in Microsoft Developer Studio 5. So we
104 omit the parens, since the macros are never used in a context where
105 the addition will be ambiguous. */
107 const struct powerpc_operand powerpc_operands[] =
109 /* The zero index is used to indicate the end of the list of
110 operands. */
111 #define UNUSED 0
112 { 0, 0, 0, 0, 0 },
114 /* The BA field in an XL form instruction. */
115 #define BA UNUSED + 1
116 #define BA_MASK (0x1f << 16)
117 { 5, 16, 0, 0, PPC_OPERAND_CR },
119 /* The BA field in an XL form instruction when it must be the same
120 as the BT field in the same instruction. */
121 #define BAT BA + 1
122 { 5, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
124 /* The BB field in an XL form instruction. */
125 #define BB BAT + 1
126 #define BB_MASK (0x1f << 11)
127 { 5, 11, 0, 0, PPC_OPERAND_CR },
129 /* The BB field in an XL form instruction when it must be the same
130 as the BA field in the same instruction. */
131 #define BBA BB + 1
132 { 5, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },
134 /* The BD field in a B form instruction. The lower two bits are
135 forced to zero. */
136 #define BD BBA + 1
137 { 16, 0, insert_bd, extract_bd, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
139 /* The BD field in a B form instruction when absolute addressing is
140 used. */
141 #define BDA BD + 1
142 { 16, 0, insert_bd, extract_bd, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
144 /* The BD field in a B form instruction when the - modifier is used.
145 This sets the y bit of the BO field appropriately. */
146 #define BDM BDA + 1
147 { 16, 0, insert_bdm, extract_bdm,
148 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
150 /* The BD field in a B form instruction when the - modifier is used
151 and absolute address is used. */
152 #define BDMA BDM + 1
153 { 16, 0, insert_bdm, extract_bdm,
154 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
156 /* The BD field in a B form instruction when the + modifier is used.
157 This sets the y bit of the BO field appropriately. */
158 #define BDP BDMA + 1
159 { 16, 0, insert_bdp, extract_bdp,
160 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
162 /* The BD field in a B form instruction when the + modifier is used
163 and absolute addressing is used. */
164 #define BDPA BDP + 1
165 { 16, 0, insert_bdp, extract_bdp,
166 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
168 /* The BF field in an X or XL form instruction. */
169 #define BF BDPA + 1
170 { 3, 23, 0, 0, PPC_OPERAND_CR },
172 /* An optional BF field. This is used for comparison instructions,
173 in which an omitted BF field is taken as zero. */
174 #define OBF BF + 1
175 { 3, 23, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
177 /* The BFA field in an X or XL form instruction. */
178 #define BFA OBF + 1
179 { 3, 18, 0, 0, PPC_OPERAND_CR },
181 /* The BI field in a B form or XL form instruction. */
182 #define BI BFA + 1
183 #define BI_MASK (0x1f << 16)
184 { 5, 16, 0, 0, PPC_OPERAND_CR },
186 /* The BO field in a B form instruction. Certain values are
187 illegal. */
188 #define BO BI + 1
189 #define BO_MASK (0x1f << 21)
190 { 5, 21, insert_bo, extract_bo, 0 },
192 /* The BO field in a B form instruction when the + or - modifier is
193 used. This is like the BO field, but it must be even. */
194 #define BOE BO + 1
195 { 5, 21, insert_boe, extract_boe, 0 },
197 #define BH BOE + 1
198 { 2, 11, 0, 0, PPC_OPERAND_OPTIONAL },
200 /* The BT field in an X or XL form instruction. */
201 #define BT BH + 1
202 { 5, 21, 0, 0, PPC_OPERAND_CR },
204 /* The condition register number portion of the BI field in a B form
205 or XL form instruction. This is used for the extended
206 conditional branch mnemonics, which set the lower two bits of the
207 BI field. This field is optional. */
208 #define CR BT + 1
209 { 3, 18, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
211 /* The CRB field in an X form instruction. */
212 #define CRB CR + 1
213 { 5, 6, 0, 0, 0 },
215 /* The CRFD field in an X form instruction. */
216 #define CRFD CRB + 1
217 { 3, 23, 0, 0, PPC_OPERAND_CR },
219 /* The CRFS field in an X form instruction. */
220 #define CRFS CRFD + 1
221 { 3, 0, 0, 0, PPC_OPERAND_CR },
223 /* The CT field in an X form instruction. */
224 #define CT CRFS + 1
225 { 5, 21, 0, 0, PPC_OPERAND_OPTIONAL },
227 /* The D field in a D form instruction. This is a displacement off
228 a register, and implies that the next operand is a register in
229 parentheses. */
230 #define D CT + 1
231 { 16, 0, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
233 /* The DE field in a DE form instruction. This is like D, but is 12
234 bits only. */
235 #define DE D + 1
236 { 14, 0, insert_de, extract_de, PPC_OPERAND_PARENS },
238 /* The DES field in a DES form instruction. This is like DS, but is 14
239 bits only (12 stored.) */
240 #define DES DE + 1
241 { 14, 0, insert_des, extract_des, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
243 /* The DQ field in a DQ form instruction. This is like D, but the
244 lower four bits are forced to zero. */
245 #define DQ DES + 1
246 { 16, 0, insert_dq, extract_dq,
247 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ },
249 /* The DS field in a DS form instruction. This is like D, but the
250 lower two bits are forced to zero. */
251 #define DS DQ + 1
252 { 16, 0, insert_ds, extract_ds,
253 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },
255 /* The E field in a wrteei instruction. */
256 #define E DS + 1
257 { 1, 15, 0, 0, 0 },
259 /* The FL1 field in a POWER SC form instruction. */
260 #define FL1 E + 1
261 { 4, 12, 0, 0, 0 },
263 /* The FL2 field in a POWER SC form instruction. */
264 #define FL2 FL1 + 1
265 { 3, 2, 0, 0, 0 },
267 /* The FLM field in an XFL form instruction. */
268 #define FLM FL2 + 1
269 { 8, 17, 0, 0, 0 },
271 /* The FRA field in an X or A form instruction. */
272 #define FRA FLM + 1
273 #define FRA_MASK (0x1f << 16)
274 { 5, 16, 0, 0, PPC_OPERAND_FPR },
276 /* The FRB field in an X or A form instruction. */
277 #define FRB FRA + 1
278 #define FRB_MASK (0x1f << 11)
279 { 5, 11, 0, 0, PPC_OPERAND_FPR },
281 /* The FRC field in an A form instruction. */
282 #define FRC FRB + 1
283 #define FRC_MASK (0x1f << 6)
284 { 5, 6, 0, 0, PPC_OPERAND_FPR },
286 /* The FRS field in an X form instruction or the FRT field in a D, X
287 or A form instruction. */
288 #define FRS FRC + 1
289 #define FRT FRS
290 { 5, 21, 0, 0, PPC_OPERAND_FPR },
292 /* The FXM field in an XFX instruction. */
293 #define FXM FRS + 1
294 #define FXM_MASK (0xff << 12)
295 { 8, 12, insert_fxm, extract_fxm, 0 },
297 /* Power4 version for mfcr. */
298 #define FXM4 FXM + 1
299 { 8, 12, insert_fxm, extract_fxm, PPC_OPERAND_OPTIONAL },
301 /* The L field in a D or X form instruction. */
302 #define L FXM4 + 1
303 { 1, 21, 0, 0, PPC_OPERAND_OPTIONAL },
305 /* The LEV field in a POWER SC form instruction. */
306 #define LEV L + 1
307 { 7, 5, 0, 0, 0 },
309 /* The LI field in an I form instruction. The lower two bits are
310 forced to zero. */
311 #define LI LEV + 1
312 { 26, 0, insert_li, extract_li, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
314 /* The LI field in an I form instruction when used as an absolute
315 address. */
316 #define LIA LI + 1
317 { 26, 0, insert_li, extract_li, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
319 /* The LS field in an X (sync) form instruction. */
320 #define LS LIA + 1
321 { 2, 21, 0, 0, PPC_OPERAND_OPTIONAL },
323 /* The MB field in an M form instruction. */
324 #define MB LS + 1
325 #define MB_MASK (0x1f << 6)
326 { 5, 6, 0, 0, 0 },
328 /* The ME field in an M form instruction. */
329 #define ME MB + 1
330 #define ME_MASK (0x1f << 1)
331 { 5, 1, 0, 0, 0 },
333 /* The MB and ME fields in an M form instruction expressed a single
334 operand which is a bitmask indicating which bits to select. This
335 is a two operand form using PPC_OPERAND_NEXT. See the
336 description in opcode/ppc.h for what this means. */
337 #define MBE ME + 1
338 { 5, 6, 0, 0, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
339 { 32, 0, insert_mbe, extract_mbe, 0 },
341 /* The MB or ME field in an MD or MDS form instruction. The high
342 bit is wrapped to the low end. */
343 #define MB6 MBE + 2
344 #define ME6 MB6
345 #define MB6_MASK (0x3f << 5)
346 { 6, 5, insert_mb6, extract_mb6, 0 },
348 /* The MO field in an mbar instruction. */
349 #define MO MB6 + 1
350 { 5, 21, 0, 0, PPC_OPERAND_OPTIONAL },
352 /* The NB field in an X form instruction. The value 32 is stored as
353 0. */
354 #define NB MO + 1
355 { 6, 11, insert_nb, extract_nb, 0 },
357 /* The NSI field in a D form instruction. This is the same as the
358 SI field, only negated. */
359 #define NSI NB + 1
360 { 16, 0, insert_nsi, extract_nsi,
361 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
363 /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */
364 #define RA NSI + 1
365 #define RA_MASK (0x1f << 16)
366 { 5, 16, 0, 0, PPC_OPERAND_GPR },
368 /* As above, but 0 in the RA field means zero, not r0. */
369 #define RA0 RA + 1
370 { 5, 16, 0, 0, PPC_OPERAND_GPR_0 },
372 /* The RA field in the DQ form lq instruction, which has special
373 value restrictions. */
374 #define RAQ RA0 + 1
375 { 5, 16, insert_raq, 0, PPC_OPERAND_GPR_0 },
377 /* The RA field in a D or X form instruction which is an updating
378 load, which means that the RA field may not be zero and may not
379 equal the RT field. */
380 #define RAL RAQ + 1
381 { 5, 16, insert_ral, 0, PPC_OPERAND_GPR_0 },
383 /* The RA field in an lmw instruction, which has special value
384 restrictions. */
385 #define RAM RAL + 1
386 { 5, 16, insert_ram, 0, PPC_OPERAND_GPR_0 },
388 /* The RA field in a D or X form instruction which is an updating
389 store or an updating floating point load, which means that the RA
390 field may not be zero. */
391 #define RAS RAM + 1
392 { 5, 16, insert_ras, 0, PPC_OPERAND_GPR_0 },
394 /* The RA field of the tlbwe instruction, which is optional. */
395 #define RAOPT RAS + 1
396 { 5, 16, 0, 0, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
398 /* The RB field in an X, XO, M, or MDS form instruction. */
399 #define RB RAOPT + 1
400 #define RB_MASK (0x1f << 11)
401 { 5, 11, 0, 0, PPC_OPERAND_GPR },
403 /* The RB field in an X form instruction when it must be the same as
404 the RS field in the instruction. This is used for extended
405 mnemonics like mr. */
406 #define RBS RB + 1
407 { 5, 1, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },
409 /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
410 instruction or the RT field in a D, DS, X, XFX or XO form
411 instruction. */
412 #define RS RBS + 1
413 #define RT RS
414 #define RT_MASK (0x1f << 21)
415 { 5, 21, 0, 0, PPC_OPERAND_GPR },
417 /* The RS field of the DS form stq instruction, which has special
418 value restrictions. */
419 #define RSQ RS + 1
420 { 5, 21, insert_rsq, 0, PPC_OPERAND_GPR_0 },
422 /* The RT field of the DQ form lq instruction, which has special
423 value restrictions. */
424 #define RTQ RSQ + 1
425 { 5, 21, insert_rtq, 0, PPC_OPERAND_GPR_0 },
427 /* The RS field of the tlbwe instruction, which is optional. */
428 #define RSO RTQ + 1
429 { 5, 21, 0, 0, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
431 /* The SH field in an X or M form instruction. */
432 #define SH RSO + 1
433 #define SH_MASK (0x1f << 11)
434 { 5, 11, 0, 0, 0 },
436 /* The SH field in an MD form instruction. This is split. */
437 #define SH6 SH + 1
438 #define SH6_MASK ((0x1f << 11) | (1 << 1))
439 { 6, 1, insert_sh6, extract_sh6, 0 },
441 /* The SH field of the tlbwe instruction, which is optional. */
442 #define SHO SH6 + 1
443 { 5, 11,0, 0, PPC_OPERAND_OPTIONAL },
445 /* The SI field in a D form instruction. */
446 #define SI SHO + 1
447 { 16, 0, 0, 0, PPC_OPERAND_SIGNED },
449 /* The SI field in a D form instruction when we accept a wide range
450 of positive values. */
451 #define SISIGNOPT SI + 1
452 { 16, 0, 0, 0, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
454 /* The SPR field in an XFX form instruction. This is flipped--the
455 lower 5 bits are stored in the upper 5 and vice- versa. */
456 #define SPR SISIGNOPT + 1
457 #define PMR SPR
458 #define SPR_MASK (0x3ff << 11)
459 { 10, 11, insert_spr, extract_spr, 0 },
461 /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */
462 #define SPRBAT SPR + 1
463 #define SPRBAT_MASK (0x3 << 17)
464 { 2, 17, 0, 0, 0 },
466 /* The SPRG register number in an XFX form m[ft]sprg instruction. */
467 #define SPRG SPRBAT + 1
468 #define SPRG_MASK (0x3 << 16)
469 { 2, 16, 0, 0, 0 },
471 /* The SR field in an X form instruction. */
472 #define SR SPRG + 1
473 { 4, 16, 0, 0, 0 },
475 /* The STRM field in an X AltiVec form instruction. */
476 #define STRM SR + 1
477 #define STRM_MASK (0x3 << 21)
478 { 2, 21, 0, 0, 0 },
480 /* The SV field in a POWER SC form instruction. */
481 #define SV STRM + 1
482 { 14, 2, 0, 0, 0 },
484 /* The TBR field in an XFX form instruction. This is like the SPR
485 field, but it is optional. */
486 #define TBR SV + 1
487 { 10, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL },
489 /* The TO field in a D or X form instruction. */
490 #define TO TBR + 1
491 #define TO_MASK (0x1f << 21)
492 { 5, 21, 0, 0, 0 },
494 /* The U field in an X form instruction. */
495 #define U TO + 1
496 { 4, 12, 0, 0, 0 },
498 /* The UI field in a D form instruction. */
499 #define UI U + 1
500 { 16, 0, 0, 0, 0 },
502 /* The VA field in a VA, VX or VXR form instruction. */
503 #define VA UI + 1
504 #define VA_MASK (0x1f << 16)
505 { 5, 16, 0, 0, PPC_OPERAND_VR },
507 /* The VB field in a VA, VX or VXR form instruction. */
508 #define VB VA + 1
509 #define VB_MASK (0x1f << 11)
510 { 5, 11, 0, 0, PPC_OPERAND_VR },
512 /* The VC field in a VA form instruction. */
513 #define VC VB + 1
514 #define VC_MASK (0x1f << 6)
515 { 5, 6, 0, 0, PPC_OPERAND_VR },
517 /* The VD or VS field in a VA, VX, VXR or X form instruction. */
518 #define VD VC + 1
519 #define VS VD
520 #define VD_MASK (0x1f << 21)
521 { 5, 21, 0, 0, PPC_OPERAND_VR },
523 /* The SIMM field in a VX form instruction. */
524 #define SIMM VD + 1
525 { 5, 16, 0, 0, PPC_OPERAND_SIGNED},
527 /* The UIMM field in a VX form instruction. */
528 #define UIMM SIMM + 1
529 { 5, 16, 0, 0, 0 },
531 /* The SHB field in a VA form instruction. */
532 #define SHB UIMM + 1
533 { 4, 6, 0, 0, 0 },
535 /* The other UIMM field in a EVX form instruction. */
536 #define EVUIMM SHB + 1
537 { 5, 11, 0, 0, 0 },
539 /* The other UIMM field in a half word EVX form instruction. */
540 #define EVUIMM_2 EVUIMM + 1
541 { 32, 11, insert_ev2, extract_ev2, PPC_OPERAND_PARENS },
543 /* The other UIMM field in a word EVX form instruction. */
544 #define EVUIMM_4 EVUIMM_2 + 1
545 { 32, 11, insert_ev4, extract_ev4, PPC_OPERAND_PARENS },
547 /* The other UIMM field in a double EVX form instruction. */
548 #define EVUIMM_8 EVUIMM_4 + 1
549 { 32, 11, insert_ev8, extract_ev8, PPC_OPERAND_PARENS },
551 /* The WS field. */
552 #define WS EVUIMM_8 + 1
553 #define WS_MASK (0x7 << 11)
554 { 3, 11, 0, 0, 0 },
556 /* The L field in an mtmsrd instruction */
557 #define MTMSRD_L WS + 1
558 { 1, 16, 0, 0, PPC_OPERAND_OPTIONAL },
562 /* The functions used to insert and extract complicated operands. */
564 /* The BA field in an XL form instruction when it must be the same as
565 the BT field in the same instruction. This operand is marked FAKE.
566 The insertion function just copies the BT field into the BA field,
567 and the extraction function just checks that the fields are the
568 same. */
570 static unsigned long
571 insert_bat (unsigned long insn,
572 long value ATTRIBUTE_UNUSED,
573 int dialect ATTRIBUTE_UNUSED,
574 const char **errmsg ATTRIBUTE_UNUSED)
576 return insn | (((insn >> 21) & 0x1f) << 16);
579 static long
580 extract_bat (unsigned long insn,
581 int dialect ATTRIBUTE_UNUSED,
582 int *invalid)
584 if (((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
585 *invalid = 1;
586 return 0;
589 /* The BB field in an XL form instruction when it must be the same as
590 the BA field in the same instruction. This operand is marked FAKE.
591 The insertion function just copies the BA field into the BB field,
592 and the extraction function just checks that the fields are the
593 same. */
595 static unsigned long
596 insert_bba (unsigned long insn,
597 long value ATTRIBUTE_UNUSED,
598 int dialect ATTRIBUTE_UNUSED,
599 const char **errmsg ATTRIBUTE_UNUSED)
601 return insn | (((insn >> 16) & 0x1f) << 11);
604 static long
605 extract_bba (unsigned long insn,
606 int dialect ATTRIBUTE_UNUSED,
607 int *invalid)
609 if (((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
610 *invalid = 1;
611 return 0;
614 /* The BD field in a B form instruction. The lower two bits are
615 forced to zero. */
617 static unsigned long
618 insert_bd (unsigned long insn,
619 long value,
620 int dialect ATTRIBUTE_UNUSED,
621 const char **errmsg ATTRIBUTE_UNUSED)
623 return insn | (value & 0xfffc);
626 static long
627 extract_bd (unsigned long insn,
628 int dialect ATTRIBUTE_UNUSED,
629 int *invalid ATTRIBUTE_UNUSED)
631 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
634 /* The BD field in a B form instruction when the - modifier is used.
635 This modifier means that the branch is not expected to be taken.
636 For chips built to versions of the architecture prior to version 2
637 (ie. not Power4 compatible), we set the y bit of the BO field to 1
638 if the offset is negative. When extracting, we require that the y
639 bit be 1 and that the offset be positive, since if the y bit is 0
640 we just want to print the normal form of the instruction.
641 Power4 compatible targets use two bits, "a", and "t", instead of
642 the "y" bit. "at" == 00 => no hint, "at" == 01 => unpredictable,
643 "at" == 10 => not taken, "at" == 11 => taken. The "t" bit is 00001
644 in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000
645 for branch on CTR. We only handle the taken/not-taken hint here. */
647 static unsigned long
648 insert_bdm (unsigned long insn,
649 long value,
650 int dialect,
651 const char **errmsg ATTRIBUTE_UNUSED)
653 if ((dialect & PPC_OPCODE_POWER4) == 0)
655 if ((value & 0x8000) != 0)
656 insn |= 1 << 21;
658 else
660 if ((insn & (0x14 << 21)) == (0x04 << 21))
661 insn |= 0x02 << 21;
662 else if ((insn & (0x14 << 21)) == (0x10 << 21))
663 insn |= 0x08 << 21;
665 return insn | (value & 0xfffc);
668 static long
669 extract_bdm (unsigned long insn,
670 int dialect,
671 int *invalid)
673 if ((dialect & PPC_OPCODE_POWER4) == 0)
675 if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0))
676 *invalid = 1;
678 else
680 if ((insn & (0x17 << 21)) != (0x06 << 21)
681 && (insn & (0x1d << 21)) != (0x18 << 21))
682 *invalid = 1;
685 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
688 /* The BD field in a B form instruction when the + modifier is used.
689 This is like BDM, above, except that the branch is expected to be
690 taken. */
692 static unsigned long
693 insert_bdp (unsigned long insn,
694 long value,
695 int dialect,
696 const char **errmsg ATTRIBUTE_UNUSED)
698 if ((dialect & PPC_OPCODE_POWER4) == 0)
700 if ((value & 0x8000) == 0)
701 insn |= 1 << 21;
703 else
705 if ((insn & (0x14 << 21)) == (0x04 << 21))
706 insn |= 0x03 << 21;
707 else if ((insn & (0x14 << 21)) == (0x10 << 21))
708 insn |= 0x09 << 21;
710 return insn | (value & 0xfffc);
713 static long
714 extract_bdp (unsigned long insn,
715 int dialect,
716 int *invalid)
718 if ((dialect & PPC_OPCODE_POWER4) == 0)
720 if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0))
721 *invalid = 1;
723 else
725 if ((insn & (0x17 << 21)) != (0x07 << 21)
726 && (insn & (0x1d << 21)) != (0x19 << 21))
727 *invalid = 1;
730 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
733 /* Check for legal values of a BO field. */
735 static int
736 valid_bo (long value, int dialect)
738 if ((dialect & PPC_OPCODE_POWER4) == 0)
740 /* Certain encodings have bits that are required to be zero.
741 These are (z must be zero, y may be anything):
742 001zy
743 011zy
744 1z00y
745 1z01y
746 1z1zz
748 switch (value & 0x14)
750 default:
751 case 0:
752 return 1;
753 case 0x4:
754 return (value & 0x2) == 0;
755 case 0x10:
756 return (value & 0x8) == 0;
757 case 0x14:
758 return value == 0x14;
761 else
763 /* Certain encodings have bits that are required to be zero.
764 These are (z must be zero, a & t may be anything):
765 0000z
766 0001z
767 0100z
768 0101z
769 001at
770 011at
771 1a00t
772 1a01t
773 1z1zz
775 if ((value & 0x14) == 0)
776 return (value & 0x1) == 0;
777 else if ((value & 0x14) == 0x14)
778 return value == 0x14;
779 else
780 return 1;
784 /* The BO field in a B form instruction. Warn about attempts to set
785 the field to an illegal value. */
787 static unsigned long
788 insert_bo (unsigned long insn,
789 long value,
790 int dialect,
791 const char **errmsg)
793 if (!valid_bo (value, dialect))
794 *errmsg = _("invalid conditional option");
795 return insn | ((value & 0x1f) << 21);
798 static long
799 extract_bo (unsigned long insn,
800 int dialect,
801 int *invalid)
803 long value;
805 value = (insn >> 21) & 0x1f;
806 if (!valid_bo (value, dialect))
807 *invalid = 1;
808 return value;
811 /* The BO field in a B form instruction when the + or - modifier is
812 used. This is like the BO field, but it must be even. When
813 extracting it, we force it to be even. */
815 static unsigned long
816 insert_boe (unsigned long insn,
817 long value,
818 int dialect,
819 const char **errmsg)
821 if (!valid_bo (value, dialect))
822 *errmsg = _("invalid conditional option");
823 else if ((value & 1) != 0)
824 *errmsg = _("attempt to set y bit when using + or - modifier");
826 return insn | ((value & 0x1f) << 21);
829 static long
830 extract_boe (unsigned long insn,
831 int dialect,
832 int *invalid)
834 long value;
836 value = (insn >> 21) & 0x1f;
837 if (!valid_bo (value, dialect))
838 *invalid = 1;
839 return value & 0x1e;
842 /* The DQ field in a DQ form instruction. This is like D, but the
843 lower four bits are forced to zero. */
845 static unsigned long
846 insert_dq (unsigned long insn,
847 long value,
848 int dialect ATTRIBUTE_UNUSED,
849 const char **errmsg)
851 if ((value & 0xf) != 0)
852 *errmsg = _("offset not a multiple of 16");
853 return insn | (value & 0xfff0);
856 static long
857 extract_dq (unsigned long insn,
858 int dialect ATTRIBUTE_UNUSED,
859 int *invalid ATTRIBUTE_UNUSED)
861 return ((insn & 0xfff0) ^ 0x8000) - 0x8000;
864 static unsigned long
865 insert_ev2 (unsigned long insn,
866 long value,
867 int dialect ATTRIBUTE_UNUSED,
868 const char **errmsg)
870 if ((value & 1) != 0)
871 *errmsg = _("offset not a multiple of 2");
872 if ((value > 62) != 0)
873 *errmsg = _("offset greater than 62");
874 return insn | ((value & 0x3e) << 10);
877 static long
878 extract_ev2 (unsigned long insn,
879 int dialect ATTRIBUTE_UNUSED,
880 int *invalid ATTRIBUTE_UNUSED)
882 return (insn >> 10) & 0x3e;
885 static unsigned long
886 insert_ev4 (unsigned long insn,
887 long value,
888 int dialect ATTRIBUTE_UNUSED,
889 const char **errmsg)
891 if ((value & 3) != 0)
892 *errmsg = _("offset not a multiple of 4");
893 if ((value > 124) != 0)
894 *errmsg = _("offset greater than 124");
895 return insn | ((value & 0x7c) << 9);
898 static long
899 extract_ev4 (unsigned long insn,
900 int dialect ATTRIBUTE_UNUSED,
901 int *invalid ATTRIBUTE_UNUSED)
903 return (insn >> 9) & 0x7c;
906 static unsigned long
907 insert_ev8 (unsigned long insn,
908 long value,
909 int dialect ATTRIBUTE_UNUSED,
910 const char **errmsg)
912 if ((value & 7) != 0)
913 *errmsg = _("offset not a multiple of 8");
914 if ((value > 248) != 0)
915 *errmsg = _("offset greater than 248");
916 return insn | ((value & 0xf8) << 8);
919 static long
920 extract_ev8 (unsigned long insn,
921 int dialect ATTRIBUTE_UNUSED,
922 int *invalid ATTRIBUTE_UNUSED)
924 return (insn >> 8) & 0xf8;
927 /* The DS field in a DS form instruction. This is like D, but the
928 lower two bits are forced to zero. */
930 static unsigned long
931 insert_ds (unsigned long insn,
932 long value,
933 int dialect ATTRIBUTE_UNUSED,
934 const char **errmsg)
936 if ((value & 3) != 0)
937 *errmsg = _("offset not a multiple of 4");
938 return insn | (value & 0xfffc);
941 static long
942 extract_ds (unsigned long insn,
943 int dialect ATTRIBUTE_UNUSED,
944 int *invalid ATTRIBUTE_UNUSED)
946 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
949 /* The DE field in a DE form instruction. */
951 static unsigned long
952 insert_de (unsigned long insn,
953 long value,
954 int dialect ATTRIBUTE_UNUSED,
955 const char **errmsg)
957 if (value > 2047 || value < -2048)
958 *errmsg = _("offset not between -2048 and 2047");
959 return insn | ((value << 4) & 0xfff0);
962 static long
963 extract_de (unsigned long insn,
964 int dialect ATTRIBUTE_UNUSED,
965 int *invalid ATTRIBUTE_UNUSED)
967 return (insn & 0xfff0) >> 4;
970 /* The DES field in a DES form instruction. */
972 static unsigned long
973 insert_des (unsigned long insn,
974 long value,
975 int dialect ATTRIBUTE_UNUSED,
976 const char **errmsg)
978 if (value > 8191 || value < -8192)
979 *errmsg = _("offset not between -8192 and 8191");
980 else if ((value & 3) != 0)
981 *errmsg = _("offset not a multiple of 4");
982 return insn | ((value << 2) & 0xfff0);
985 static long
986 extract_des (unsigned long insn,
987 int dialect ATTRIBUTE_UNUSED,
988 int *invalid ATTRIBUTE_UNUSED)
990 return (((insn >> 2) & 0x3ffc) ^ 0x2000) - 0x2000;
993 /* FXM mask in mfcr and mtcrf instructions. */
995 static unsigned long
996 insert_fxm (unsigned long insn,
997 long value,
998 int dialect,
999 const char **errmsg)
1001 /* If we're handling the mfocrf and mtocrf insns ensure that exactly
1002 one bit of the mask field is set. */
1003 if ((insn & (1 << 20)) != 0)
1005 if (value == 0 || (value & -value) != value)
1007 *errmsg = _("invalid mask field");
1008 value = 0;
1012 /* If the optional field on mfcr is missing that means we want to use
1013 the old form of the instruction that moves the whole cr. In that
1014 case we'll have VALUE zero. There doesn't seem to be a way to
1015 distinguish this from the case where someone writes mfcr %r3,0. */
1016 else if (value == 0)
1019 /* If only one bit of the FXM field is set, we can use the new form
1020 of the instruction, which is faster. Unlike the Power4 branch hint
1021 encoding, this is not backward compatible. Do not generate the
1022 new form unless -mpower4 has been given, or -many and the two
1023 operand form of mfcr was used. */
1024 else if ((value & -value) == value
1025 && ((dialect & PPC_OPCODE_POWER4) != 0
1026 || ((dialect & PPC_OPCODE_ANY) != 0
1027 && (insn & (0x3ff << 1)) == 19 << 1)))
1028 insn |= 1 << 20;
1030 /* Any other value on mfcr is an error. */
1031 else if ((insn & (0x3ff << 1)) == 19 << 1)
1033 *errmsg = _("ignoring invalid mfcr mask");
1034 value = 0;
1037 return insn | ((value & 0xff) << 12);
1040 static long
1041 extract_fxm (unsigned long insn,
1042 int dialect ATTRIBUTE_UNUSED,
1043 int *invalid)
1045 long mask = (insn >> 12) & 0xff;
1047 /* Is this a Power4 insn? */
1048 if ((insn & (1 << 20)) != 0)
1050 /* Exactly one bit of MASK should be set. */
1051 if (mask == 0 || (mask & -mask) != mask)
1052 *invalid = 1;
1055 /* Check that non-power4 form of mfcr has a zero MASK. */
1056 else if ((insn & (0x3ff << 1)) == 19 << 1)
1058 if (mask != 0)
1059 *invalid = 1;
1062 return mask;
1065 /* The LI field in an I form instruction. The lower two bits are
1066 forced to zero. */
1068 static unsigned long
1069 insert_li (unsigned long insn,
1070 long value,
1071 int dialect ATTRIBUTE_UNUSED,
1072 const char **errmsg)
1074 if ((value & 3) != 0)
1075 *errmsg = _("ignoring least significant bits in branch offset");
1076 return insn | (value & 0x3fffffc);
1079 static long
1080 extract_li (unsigned long insn,
1081 int dialect ATTRIBUTE_UNUSED,
1082 int *invalid ATTRIBUTE_UNUSED)
1084 return ((insn & 0x3fffffc) ^ 0x2000000) - 0x2000000;
1087 /* The MB and ME fields in an M form instruction expressed as a single
1088 operand which is itself a bitmask. The extraction function always
1089 marks it as invalid, since we never want to recognize an
1090 instruction which uses a field of this type. */
1092 static unsigned long
1093 insert_mbe (unsigned long insn,
1094 long value,
1095 int dialect ATTRIBUTE_UNUSED,
1096 const char **errmsg)
1098 unsigned long uval, mask;
1099 int mb, me, mx, count, last;
1101 uval = value;
1103 if (uval == 0)
1105 *errmsg = _("illegal bitmask");
1106 return insn;
1109 mb = 0;
1110 me = 32;
1111 if ((uval & 1) != 0)
1112 last = 1;
1113 else
1114 last = 0;
1115 count = 0;
1117 /* mb: location of last 0->1 transition */
1118 /* me: location of last 1->0 transition */
1119 /* count: # transitions */
1121 for (mx = 0, mask = 1L << 31; mx < 32; ++mx, mask >>= 1)
1123 if ((uval & mask) && !last)
1125 ++count;
1126 mb = mx;
1127 last = 1;
1129 else if (!(uval & mask) && last)
1131 ++count;
1132 me = mx;
1133 last = 0;
1136 if (me == 0)
1137 me = 32;
1139 if (count != 2 && (count != 0 || ! last))
1140 *errmsg = _("illegal bitmask");
1142 return insn | (mb << 6) | ((me - 1) << 1);
1145 static long
1146 extract_mbe (unsigned long insn,
1147 int dialect ATTRIBUTE_UNUSED,
1148 int *invalid)
1150 long ret;
1151 int mb, me;
1152 int i;
1154 *invalid = 1;
1156 mb = (insn >> 6) & 0x1f;
1157 me = (insn >> 1) & 0x1f;
1158 if (mb < me + 1)
1160 ret = 0;
1161 for (i = mb; i <= me; i++)
1162 ret |= 1L << (31 - i);
1164 else if (mb == me + 1)
1165 ret = ~0;
1166 else /* (mb > me + 1) */
1168 ret = ~0;
1169 for (i = me + 1; i < mb; i++)
1170 ret &= ~(1L << (31 - i));
1172 return ret;
1175 /* The MB or ME field in an MD or MDS form instruction. The high bit
1176 is wrapped to the low end. */
1178 static unsigned long
1179 insert_mb6 (unsigned long insn,
1180 long value,
1181 int dialect ATTRIBUTE_UNUSED,
1182 const char **errmsg ATTRIBUTE_UNUSED)
1184 return insn | ((value & 0x1f) << 6) | (value & 0x20);
1187 static long
1188 extract_mb6 (unsigned long insn,
1189 int dialect ATTRIBUTE_UNUSED,
1190 int *invalid ATTRIBUTE_UNUSED)
1192 return ((insn >> 6) & 0x1f) | (insn & 0x20);
1195 /* The NB field in an X form instruction. The value 32 is stored as
1196 0. */
1198 static unsigned long
1199 insert_nb (unsigned long insn,
1200 long value,
1201 int dialect ATTRIBUTE_UNUSED,
1202 const char **errmsg)
1204 if (value < 0 || value > 32)
1205 *errmsg = _("value out of range");
1206 if (value == 32)
1207 value = 0;
1208 return insn | ((value & 0x1f) << 11);
1211 static long
1212 extract_nb (unsigned long insn,
1213 int dialect ATTRIBUTE_UNUSED,
1214 int *invalid ATTRIBUTE_UNUSED)
1216 long ret;
1218 ret = (insn >> 11) & 0x1f;
1219 if (ret == 0)
1220 ret = 32;
1221 return ret;
1224 /* The NSI field in a D form instruction. This is the same as the SI
1225 field, only negated. The extraction function always marks it as
1226 invalid, since we never want to recognize an instruction which uses
1227 a field of this type. */
1229 static unsigned long
1230 insert_nsi (unsigned long insn,
1231 long value,
1232 int dialect ATTRIBUTE_UNUSED,
1233 const char **errmsg ATTRIBUTE_UNUSED)
1235 return insn | (-value & 0xffff);
1238 static long
1239 extract_nsi (unsigned long insn,
1240 int dialect ATTRIBUTE_UNUSED,
1241 int *invalid)
1243 *invalid = 1;
1244 return -(((insn & 0xffff) ^ 0x8000) - 0x8000);
1247 /* The RA field in a D or X form instruction which is an updating
1248 load, which means that the RA field may not be zero and may not
1249 equal the RT field. */
1251 static unsigned long
1252 insert_ral (unsigned long insn,
1253 long value,
1254 int dialect ATTRIBUTE_UNUSED,
1255 const char **errmsg)
1257 if (value == 0
1258 || (unsigned long) value == ((insn >> 21) & 0x1f))
1259 *errmsg = "invalid register operand when updating";
1260 return insn | ((value & 0x1f) << 16);
1263 /* The RA field in an lmw instruction, which has special value
1264 restrictions. */
1266 static unsigned long
1267 insert_ram (unsigned long insn,
1268 long value,
1269 int dialect ATTRIBUTE_UNUSED,
1270 const char **errmsg)
1272 if ((unsigned long) value >= ((insn >> 21) & 0x1f))
1273 *errmsg = _("index register in load range");
1274 return insn | ((value & 0x1f) << 16);
1277 /* The RA field in the DQ form lq instruction, which has special
1278 value restrictions. */
1280 static unsigned long
1281 insert_raq (unsigned long insn,
1282 long value,
1283 int dialect ATTRIBUTE_UNUSED,
1284 const char **errmsg)
1286 long rtvalue = (insn & RT_MASK) >> 21;
1288 if (value == rtvalue)
1289 *errmsg = _("source and target register operands must be different");
1290 return insn | ((value & 0x1f) << 16);
1293 /* The RA field in a D or X form instruction which is an updating
1294 store or an updating floating point load, which means that the RA
1295 field may not be zero. */
1297 static unsigned long
1298 insert_ras (unsigned long insn,
1299 long value,
1300 int dialect ATTRIBUTE_UNUSED,
1301 const char **errmsg)
1303 if (value == 0)
1304 *errmsg = _("invalid register operand when updating");
1305 return insn | ((value & 0x1f) << 16);
1308 /* The RB field in an X form instruction when it must be the same as
1309 the RS field in the instruction. This is used for extended
1310 mnemonics like mr. This operand is marked FAKE. The insertion
1311 function just copies the BT field into the BA field, and the
1312 extraction function just checks that the fields are the same. */
1314 static unsigned long
1315 insert_rbs (unsigned long insn,
1316 long value ATTRIBUTE_UNUSED,
1317 int dialect ATTRIBUTE_UNUSED,
1318 const char **errmsg ATTRIBUTE_UNUSED)
1320 return insn | (((insn >> 21) & 0x1f) << 11);
1323 static long
1324 extract_rbs (unsigned long insn,
1325 int dialect ATTRIBUTE_UNUSED,
1326 int *invalid)
1328 if (((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f))
1329 *invalid = 1;
1330 return 0;
1333 /* The RT field of the DQ form lq instruction, which has special
1334 value restrictions. */
1336 static unsigned long
1337 insert_rtq (unsigned long insn,
1338 long value,
1339 int dialect ATTRIBUTE_UNUSED,
1340 const char **errmsg)
1342 if ((value & 1) != 0)
1343 *errmsg = _("target register operand must be even");
1344 return insn | ((value & 0x1f) << 21);
1347 /* The RS field of the DS form stq instruction, which has special
1348 value restrictions. */
1350 static unsigned long
1351 insert_rsq (unsigned long insn,
1352 long value ATTRIBUTE_UNUSED,
1353 int dialect ATTRIBUTE_UNUSED,
1354 const char **errmsg)
1356 if ((value & 1) != 0)
1357 *errmsg = _("source register operand must be even");
1358 return insn | ((value & 0x1f) << 21);
1361 /* The SH field in an MD form instruction. This is split. */
1363 static unsigned long
1364 insert_sh6 (unsigned long insn,
1365 long value,
1366 int dialect ATTRIBUTE_UNUSED,
1367 const char **errmsg ATTRIBUTE_UNUSED)
1369 return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
1372 static long
1373 extract_sh6 (unsigned long insn,
1374 int dialect ATTRIBUTE_UNUSED,
1375 int *invalid ATTRIBUTE_UNUSED)
1377 return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
1380 /* The SPR field in an XFX form instruction. This is flipped--the
1381 lower 5 bits are stored in the upper 5 and vice- versa. */
1383 static unsigned long
1384 insert_spr (unsigned long insn,
1385 long value,
1386 int dialect ATTRIBUTE_UNUSED,
1387 const char **errmsg ATTRIBUTE_UNUSED)
1389 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1392 static long
1393 extract_spr (unsigned long insn,
1394 int dialect ATTRIBUTE_UNUSED,
1395 int *invalid ATTRIBUTE_UNUSED)
1397 return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1400 /* The TBR field in an XFX instruction. This is just like SPR, but it
1401 is optional. When TBR is omitted, it must be inserted as 268 (the
1402 magic number of the TB register). These functions treat 0
1403 (indicating an omitted optional operand) as 268. This means that
1404 ``mftb 4,0'' is not handled correctly. This does not matter very
1405 much, since the architecture manual does not define mftb as
1406 accepting any values other than 268 or 269. */
1408 #define TB (268)
1410 static unsigned long
1411 insert_tbr (unsigned long insn,
1412 long value,
1413 int dialect ATTRIBUTE_UNUSED,
1414 const char **errmsg ATTRIBUTE_UNUSED)
1416 if (value == 0)
1417 value = TB;
1418 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1421 static long
1422 extract_tbr (unsigned long insn,
1423 int dialect ATTRIBUTE_UNUSED,
1424 int *invalid ATTRIBUTE_UNUSED)
1426 long ret;
1428 ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1429 if (ret == TB)
1430 ret = 0;
1431 return ret;
1434 /* Macros used to form opcodes. */
1436 /* The main opcode. */
1437 #define OP(x) ((((unsigned long)(x)) & 0x3f) << 26)
1438 #define OP_MASK OP (0x3f)
1440 /* The main opcode combined with a trap code in the TO field of a D
1441 form instruction. Used for extended mnemonics for the trap
1442 instructions. */
1443 #define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21))
1444 #define OPTO_MASK (OP_MASK | TO_MASK)
1446 /* The main opcode combined with a comparison size bit in the L field
1447 of a D form or X form instruction. Used for extended mnemonics for
1448 the comparison instructions. */
1449 #define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21))
1450 #define OPL_MASK OPL (0x3f,1)
1452 /* An A form instruction. */
1453 #define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1))
1454 #define A_MASK A (0x3f, 0x1f, 1)
1456 /* An A_MASK with the FRB field fixed. */
1457 #define AFRB_MASK (A_MASK | FRB_MASK)
1459 /* An A_MASK with the FRC field fixed. */
1460 #define AFRC_MASK (A_MASK | FRC_MASK)
1462 /* An A_MASK with the FRA and FRC fields fixed. */
1463 #define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
1465 /* A B form instruction. */
1466 #define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1))
1467 #define B_MASK B (0x3f, 1, 1)
1469 /* A B form instruction setting the BO field. */
1470 #define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1471 #define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
1473 /* A BBO_MASK with the y bit of the BO field removed. This permits
1474 matching a conditional branch regardless of the setting of the y
1475 bit. Similarly for the 'at' bits used for power4 branch hints. */
1476 #define Y_MASK (((unsigned long) 1) << 21)
1477 #define AT1_MASK (((unsigned long) 3) << 21)
1478 #define AT2_MASK (((unsigned long) 9) << 21)
1479 #define BBOY_MASK (BBO_MASK &~ Y_MASK)
1480 #define BBOAT_MASK (BBO_MASK &~ AT1_MASK)
1482 /* A B form instruction setting the BO field and the condition bits of
1483 the BI field. */
1484 #define BBOCB(op, bo, cb, aa, lk) \
1485 (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16))
1486 #define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
1488 /* A BBOCB_MASK with the y bit of the BO field removed. */
1489 #define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
1490 #define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK)
1491 #define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK)
1493 /* A BBOYCB_MASK in which the BI field is fixed. */
1494 #define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
1495 #define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK)
1497 /* An Context form instruction. */
1498 #define CTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7))
1499 #define CTX_MASK CTX(0x3f, 0x7)
1501 /* An User Context form instruction. */
1502 #define UCTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
1503 #define UCTX_MASK UCTX(0x3f, 0x1f)
1505 /* The main opcode mask with the RA field clear. */
1506 #define DRA_MASK (OP_MASK | RA_MASK)
1508 /* A DS form instruction. */
1509 #define DSO(op, xop) (OP (op) | ((xop) & 0x3))
1510 #define DS_MASK DSO (0x3f, 3)
1512 /* A DE form instruction. */
1513 #define DEO(op, xop) (OP (op) | ((xop) & 0xf))
1514 #define DE_MASK DEO (0x3e, 0xf)
1516 /* An EVSEL form instruction. */
1517 #define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3)
1518 #define EVSEL_MASK EVSEL(0x3f, 0xff)
1520 /* An M form instruction. */
1521 #define M(op, rc) (OP (op) | ((rc) & 1))
1522 #define M_MASK M (0x3f, 1)
1524 /* An M form instruction with the ME field specified. */
1525 #define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1))
1527 /* An M_MASK with the MB and ME fields fixed. */
1528 #define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
1530 /* An M_MASK with the SH and ME fields fixed. */
1531 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
1533 /* An MD form instruction. */
1534 #define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1))
1535 #define MD_MASK MD (0x3f, 0x7, 1)
1537 /* An MD_MASK with the MB field fixed. */
1538 #define MDMB_MASK (MD_MASK | MB6_MASK)
1540 /* An MD_MASK with the SH field fixed. */
1541 #define MDSH_MASK (MD_MASK | SH6_MASK)
1543 /* An MDS form instruction. */
1544 #define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1))
1545 #define MDS_MASK MDS (0x3f, 0xf, 1)
1547 /* An MDS_MASK with the MB field fixed. */
1548 #define MDSMB_MASK (MDS_MASK | MB6_MASK)
1550 /* An SC form instruction. */
1551 #define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
1552 #define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
1554 /* An VX form instruction. */
1555 #define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
1557 /* The mask for an VX form instruction. */
1558 #define VX_MASK VX(0x3f, 0x7ff)
1560 /* An VA form instruction. */
1561 #define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
1563 /* The mask for an VA form instruction. */
1564 #define VXA_MASK VXA(0x3f, 0x3f)
1566 /* An VXR form instruction. */
1567 #define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
1569 /* The mask for a VXR form instruction. */
1570 #define VXR_MASK VXR(0x3f, 0x3ff, 1)
1572 /* An X form instruction. */
1573 #define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1575 /* An X form instruction with the RC bit specified. */
1576 #define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
1578 /* The mask for an X form instruction. */
1579 #define X_MASK XRC (0x3f, 0x3ff, 1)
1581 /* An X_MASK with the RA field fixed. */
1582 #define XRA_MASK (X_MASK | RA_MASK)
1584 /* An X_MASK with the RB field fixed. */
1585 #define XRB_MASK (X_MASK | RB_MASK)
1587 /* An X_MASK with the RT field fixed. */
1588 #define XRT_MASK (X_MASK | RT_MASK)
1590 /* An X_MASK with the RA and RB fields fixed. */
1591 #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
1593 /* An XRARB_MASK, but with the L bit clear. */
1594 #define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16))
1596 /* An X_MASK with the RT and RA fields fixed. */
1597 #define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
1599 /* An XRTRA_MASK, but with L bit clear. */
1600 #define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21))
1602 /* An X form instruction with the L bit specified. */
1603 #define XOPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
1605 /* The mask for an X form comparison instruction. */
1606 #define XCMP_MASK (X_MASK | (((unsigned long)1) << 22))
1608 /* The mask for an X form comparison instruction with the L field
1609 fixed. */
1610 #define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21))
1612 /* An X form trap instruction with the TO field specified. */
1613 #define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21))
1614 #define XTO_MASK (X_MASK | TO_MASK)
1616 /* An X form tlb instruction with the SH field specified. */
1617 #define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11))
1618 #define XTLB_MASK (X_MASK | SH_MASK)
1620 /* An X form sync instruction. */
1621 #define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
1623 /* An X form sync instruction with everything filled in except the LS field. */
1624 #define XSYNC_MASK (0xff9fffff)
1626 /* An X form AltiVec dss instruction. */
1627 #define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25))
1628 #define XDSS_MASK XDSS(0x3f, 0x3ff, 1)
1630 /* An XFL form instruction. */
1631 #define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
1632 #define XFL_MASK (XFL (0x3f, 0x3ff, 1) | (((unsigned long)1) << 25) | (((unsigned long)1) << 16))
1634 /* An X form isel instruction. */
1635 #define XISEL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
1636 #define XISEL_MASK XISEL(0x3f, 0x1f)
1638 /* An XL form instruction with the LK field set to 0. */
1639 #define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1641 /* An XL form instruction which uses the LK field. */
1642 #define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
1644 /* The mask for an XL form instruction. */
1645 #define XL_MASK XLLK (0x3f, 0x3ff, 1)
1647 /* An XL form instruction which explicitly sets the BO field. */
1648 #define XLO(op, bo, xop, lk) \
1649 (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1650 #define XLO_MASK (XL_MASK | BO_MASK)
1652 /* An XL form instruction which explicitly sets the y bit of the BO
1653 field. */
1654 #define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21))
1655 #define XLYLK_MASK (XL_MASK | Y_MASK)
1657 /* An XL form instruction which sets the BO field and the condition
1658 bits of the BI field. */
1659 #define XLOCB(op, bo, cb, xop, lk) \
1660 (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16))
1661 #define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
1663 /* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed. */
1664 #define XLBB_MASK (XL_MASK | BB_MASK)
1665 #define XLYBB_MASK (XLYLK_MASK | BB_MASK)
1666 #define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
1668 /* A mask for branch instructions using the BH field. */
1669 #define XLBH_MASK (XL_MASK | (0x1c << 11))
1671 /* An XL_MASK with the BO and BB fields fixed. */
1672 #define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
1674 /* An XL_MASK with the BO, BI and BB fields fixed. */
1675 #define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
1677 /* An XO form instruction. */
1678 #define XO(op, xop, oe, rc) \
1679 (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1))
1680 #define XO_MASK XO (0x3f, 0x1ff, 1, 1)
1682 /* An XO_MASK with the RB field fixed. */
1683 #define XORB_MASK (XO_MASK | RB_MASK)
1685 /* An XS form instruction. */
1686 #define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1))
1687 #define XS_MASK XS (0x3f, 0x1ff, 1)
1689 /* A mask for the FXM version of an XFX form instruction. */
1690 #define XFXFXM_MASK (X_MASK | (1 << 11) | (1 << 20))
1692 /* An XFX form instruction with the FXM field filled in. */
1693 #define XFXM(op, xop, fxm, p4) \
1694 (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12) \
1695 | ((unsigned long)(p4) << 20))
1697 /* An XFX form instruction with the SPR field filled in. */
1698 #define XSPR(op, xop, spr) \
1699 (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6))
1700 #define XSPR_MASK (X_MASK | SPR_MASK)
1702 /* An XFX form instruction with the SPR field filled in except for the
1703 SPRBAT field. */
1704 #define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
1706 /* An XFX form instruction with the SPR field filled in except for the
1707 SPRG field. */
1708 #define XSPRG_MASK (XSPR_MASK &~ SPRG_MASK)
1710 /* An X form instruction with everything filled in except the E field. */
1711 #define XE_MASK (0xffff7fff)
1713 /* An X form user context instruction. */
1714 #define XUC(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
1715 #define XUC_MASK XUC(0x3f, 0x1f)
1717 /* The BO encodings used in extended conditional branch mnemonics. */
1718 #define BODNZF (0x0)
1719 #define BODNZFP (0x1)
1720 #define BODZF (0x2)
1721 #define BODZFP (0x3)
1722 #define BODNZT (0x8)
1723 #define BODNZTP (0x9)
1724 #define BODZT (0xa)
1725 #define BODZTP (0xb)
1727 #define BOF (0x4)
1728 #define BOFP (0x5)
1729 #define BOFM4 (0x6)
1730 #define BOFP4 (0x7)
1731 #define BOT (0xc)
1732 #define BOTP (0xd)
1733 #define BOTM4 (0xe)
1734 #define BOTP4 (0xf)
1736 #define BODNZ (0x10)
1737 #define BODNZP (0x11)
1738 #define BODZ (0x12)
1739 #define BODZP (0x13)
1740 #define BODNZM4 (0x18)
1741 #define BODNZP4 (0x19)
1742 #define BODZM4 (0x1a)
1743 #define BODZP4 (0x1b)
1745 #define BOU (0x14)
1747 /* The BI condition bit encodings used in extended conditional branch
1748 mnemonics. */
1749 #define CBLT (0)
1750 #define CBGT (1)
1751 #define CBEQ (2)
1752 #define CBSO (3)
1754 /* The TO encodings used in extended trap mnemonics. */
1755 #define TOLGT (0x1)
1756 #define TOLLT (0x2)
1757 #define TOEQ (0x4)
1758 #define TOLGE (0x5)
1759 #define TOLNL (0x5)
1760 #define TOLLE (0x6)
1761 #define TOLNG (0x6)
1762 #define TOGT (0x8)
1763 #define TOGE (0xc)
1764 #define TONL (0xc)
1765 #define TOLT (0x10)
1766 #define TOLE (0x14)
1767 #define TONG (0x14)
1768 #define TONE (0x18)
1769 #define TOU (0x1f)
1771 /* Smaller names for the flags so each entry in the opcodes table will
1772 fit on a single line. */
1773 #undef PPC
1774 #define PPC PPC_OPCODE_PPC
1775 #define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON
1776 #define NOPOWER4 PPC_OPCODE_NOPOWER4 | PPCCOM
1777 #define POWER4 PPC_OPCODE_POWER4
1778 #define PPC32 PPC_OPCODE_32 | PPC_OPCODE_PPC
1779 #define PPC64 PPC_OPCODE_64 | PPC_OPCODE_PPC
1780 #define PPC403 PPC_OPCODE_403
1781 #define PPC405 PPC403
1782 #define PPC440 PPC_OPCODE_440
1783 #define PPC750 PPC
1784 #define PPC860 PPC
1785 #define PPCVEC PPC_OPCODE_ALTIVEC
1786 #define POWER PPC_OPCODE_POWER
1787 #define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2
1788 #define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2
1789 #define POWER32 PPC_OPCODE_POWER | PPC_OPCODE_32
1790 #define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON
1791 #define COM32 PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_32
1792 #define M601 PPC_OPCODE_POWER | PPC_OPCODE_601
1793 #define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON
1794 #define MFDEC1 PPC_OPCODE_POWER
1795 #define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE
1796 #define BOOKE PPC_OPCODE_BOOKE
1797 #define BOOKE64 PPC_OPCODE_BOOKE64
1798 #define CLASSIC PPC_OPCODE_CLASSIC
1799 #define PPCSPE PPC_OPCODE_SPE
1800 #define PPCISEL PPC_OPCODE_ISEL
1801 #define PPCEFS PPC_OPCODE_EFS
1802 #define PPCBRLK PPC_OPCODE_BRLOCK
1803 #define PPCPMR PPC_OPCODE_PMR
1804 #define PPCCHLK PPC_OPCODE_CACHELCK
1805 #define PPCCHLK64 PPC_OPCODE_CACHELCK | PPC_OPCODE_BOOKE64
1806 #define PPCRFMCI PPC_OPCODE_RFMCI
1808 /* The opcode table.
1810 The format of the opcode table is:
1812 NAME OPCODE MASK FLAGS { OPERANDS }
1814 NAME is the name of the instruction.
1815 OPCODE is the instruction opcode.
1816 MASK is the opcode mask; this is used to tell the disassembler
1817 which bits in the actual opcode must match OPCODE.
1818 FLAGS are flags indicated what processors support the instruction.
1819 OPERANDS is the list of operands.
1821 The disassembler reads the table in order and prints the first
1822 instruction which matches, so this table is sorted to put more
1823 specific instructions before more general instructions. It is also
1824 sorted by major opcode. */
1826 const struct powerpc_opcode powerpc_opcodes[] = {
1827 { "attn", X(0,256), X_MASK, POWER4, { 0 } },
1828 { "tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, { RA, SI } },
1829 { "tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, { RA, SI } },
1830 { "tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, { RA, SI } },
1831 { "tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC64, { RA, SI } },
1832 { "tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC64, { RA, SI } },
1833 { "tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, { RA, SI } },
1834 { "tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC64, { RA, SI } },
1835 { "tdgti", OPTO(2,TOGT), OPTO_MASK, PPC64, { RA, SI } },
1836 { "tdgei", OPTO(2,TOGE), OPTO_MASK, PPC64, { RA, SI } },
1837 { "tdnli", OPTO(2,TONL), OPTO_MASK, PPC64, { RA, SI } },
1838 { "tdlti", OPTO(2,TOLT), OPTO_MASK, PPC64, { RA, SI } },
1839 { "tdlei", OPTO(2,TOLE), OPTO_MASK, PPC64, { RA, SI } },
1840 { "tdngi", OPTO(2,TONG), OPTO_MASK, PPC64, { RA, SI } },
1841 { "tdnei", OPTO(2,TONE), OPTO_MASK, PPC64, { RA, SI } },
1842 { "tdi", OP(2), OP_MASK, PPC64, { TO, RA, SI } },
1844 { "twlgti", OPTO(3,TOLGT), OPTO_MASK, PPCCOM, { RA, SI } },
1845 { "tlgti", OPTO(3,TOLGT), OPTO_MASK, PWRCOM, { RA, SI } },
1846 { "twllti", OPTO(3,TOLLT), OPTO_MASK, PPCCOM, { RA, SI } },
1847 { "tllti", OPTO(3,TOLLT), OPTO_MASK, PWRCOM, { RA, SI } },
1848 { "tweqi", OPTO(3,TOEQ), OPTO_MASK, PPCCOM, { RA, SI } },
1849 { "teqi", OPTO(3,TOEQ), OPTO_MASK, PWRCOM, { RA, SI } },
1850 { "twlgei", OPTO(3,TOLGE), OPTO_MASK, PPCCOM, { RA, SI } },
1851 { "tlgei", OPTO(3,TOLGE), OPTO_MASK, PWRCOM, { RA, SI } },
1852 { "twlnli", OPTO(3,TOLNL), OPTO_MASK, PPCCOM, { RA, SI } },
1853 { "tlnli", OPTO(3,TOLNL), OPTO_MASK, PWRCOM, { RA, SI } },
1854 { "twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, { RA, SI } },
1855 { "tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, { RA, SI } },
1856 { "twlngi", OPTO(3,TOLNG), OPTO_MASK, PPCCOM, { RA, SI } },
1857 { "tlngi", OPTO(3,TOLNG), OPTO_MASK, PWRCOM, { RA, SI } },
1858 { "twgti", OPTO(3,TOGT), OPTO_MASK, PPCCOM, { RA, SI } },
1859 { "tgti", OPTO(3,TOGT), OPTO_MASK, PWRCOM, { RA, SI } },
1860 { "twgei", OPTO(3,TOGE), OPTO_MASK, PPCCOM, { RA, SI } },
1861 { "tgei", OPTO(3,TOGE), OPTO_MASK, PWRCOM, { RA, SI } },
1862 { "twnli", OPTO(3,TONL), OPTO_MASK, PPCCOM, { RA, SI } },
1863 { "tnli", OPTO(3,TONL), OPTO_MASK, PWRCOM, { RA, SI } },
1864 { "twlti", OPTO(3,TOLT), OPTO_MASK, PPCCOM, { RA, SI } },
1865 { "tlti", OPTO(3,TOLT), OPTO_MASK, PWRCOM, { RA, SI } },
1866 { "twlei", OPTO(3,TOLE), OPTO_MASK, PPCCOM, { RA, SI } },
1867 { "tlei", OPTO(3,TOLE), OPTO_MASK, PWRCOM, { RA, SI } },
1868 { "twngi", OPTO(3,TONG), OPTO_MASK, PPCCOM, { RA, SI } },
1869 { "tngi", OPTO(3,TONG), OPTO_MASK, PWRCOM, { RA, SI } },
1870 { "twnei", OPTO(3,TONE), OPTO_MASK, PPCCOM, { RA, SI } },
1871 { "tnei", OPTO(3,TONE), OPTO_MASK, PWRCOM, { RA, SI } },
1872 { "twi", OP(3), OP_MASK, PPCCOM, { TO, RA, SI } },
1873 { "ti", OP(3), OP_MASK, PWRCOM, { TO, RA, SI } },
1875 { "macchw", XO(4,172,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1876 { "macchw.", XO(4,172,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1877 { "macchwo", XO(4,172,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1878 { "macchwo.", XO(4,172,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1879 { "macchws", XO(4,236,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1880 { "macchws.", XO(4,236,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1881 { "macchwso", XO(4,236,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1882 { "macchwso.", XO(4,236,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1883 { "macchwsu", XO(4,204,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1884 { "macchwsu.", XO(4,204,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1885 { "macchwsuo", XO(4,204,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1886 { "macchwsuo.", XO(4,204,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1887 { "macchwu", XO(4,140,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1888 { "macchwu.", XO(4,140,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1889 { "macchwuo", XO(4,140,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1890 { "macchwuo.", XO(4,140,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1891 { "machhw", XO(4,44,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1892 { "machhw.", XO(4,44,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1893 { "machhwo", XO(4,44,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1894 { "machhwo.", XO(4,44,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1895 { "machhws", XO(4,108,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1896 { "machhws.", XO(4,108,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1897 { "machhwso", XO(4,108,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1898 { "machhwso.", XO(4,108,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1899 { "machhwsu", XO(4,76,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1900 { "machhwsu.", XO(4,76,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1901 { "machhwsuo", XO(4,76,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1902 { "machhwsuo.", XO(4,76,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1903 { "machhwu", XO(4,12,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1904 { "machhwu.", XO(4,12,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1905 { "machhwuo", XO(4,12,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1906 { "machhwuo.", XO(4,12,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1907 { "maclhw", XO(4,428,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1908 { "maclhw.", XO(4,428,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1909 { "maclhwo", XO(4,428,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1910 { "maclhwo.", XO(4,428,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1911 { "maclhws", XO(4,492,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1912 { "maclhws.", XO(4,492,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1913 { "maclhwso", XO(4,492,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1914 { "maclhwso.", XO(4,492,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1915 { "maclhwsu", XO(4,460,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1916 { "maclhwsu.", XO(4,460,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1917 { "maclhwsuo", XO(4,460,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1918 { "maclhwsuo.", XO(4,460,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1919 { "maclhwu", XO(4,396,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1920 { "maclhwu.", XO(4,396,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1921 { "maclhwuo", XO(4,396,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1922 { "maclhwuo.", XO(4,396,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1923 { "mulchw", XRC(4,168,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1924 { "mulchw.", XRC(4,168,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1925 { "mulchwu", XRC(4,136,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1926 { "mulchwu.", XRC(4,136,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1927 { "mulhhw", XRC(4,40,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1928 { "mulhhw.", XRC(4,40,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1929 { "mulhhwu", XRC(4,8,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1930 { "mulhhwu.", XRC(4,8,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1931 { "mullhw", XRC(4,424,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1932 { "mullhw.", XRC(4,424,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1933 { "mullhwu", XRC(4,392,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1934 { "mullhwu.", XRC(4,392,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1935 { "nmacchw", XO(4,174,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1936 { "nmacchw.", XO(4,174,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1937 { "nmacchwo", XO(4,174,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1938 { "nmacchwo.", XO(4,174,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1939 { "nmacchws", XO(4,238,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1940 { "nmacchws.", XO(4,238,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1941 { "nmacchwso", XO(4,238,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1942 { "nmacchwso.", XO(4,238,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1943 { "nmachhw", XO(4,46,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1944 { "nmachhw.", XO(4,46,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1945 { "nmachhwo", XO(4,46,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1946 { "nmachhwo.", XO(4,46,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1947 { "nmachhws", XO(4,110,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1948 { "nmachhws.", XO(4,110,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1949 { "nmachhwso", XO(4,110,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1950 { "nmachhwso.", XO(4,110,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1951 { "nmaclhw", XO(4,430,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1952 { "nmaclhw.", XO(4,430,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1953 { "nmaclhwo", XO(4,430,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1954 { "nmaclhwo.", XO(4,430,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1955 { "nmaclhws", XO(4,494,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1956 { "nmaclhws.", XO(4,494,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1957 { "nmaclhwso", XO(4,494,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1958 { "nmaclhwso.", XO(4,494,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1959 { "mfvscr", VX(4, 1540), VX_MASK, PPCVEC, { VD } },
1960 { "mtvscr", VX(4, 1604), VX_MASK, PPCVEC, { VB } },
1961 { "vaddcuw", VX(4, 384), VX_MASK, PPCVEC, { VD, VA, VB } },
1962 { "vaddfp", VX(4, 10), VX_MASK, PPCVEC, { VD, VA, VB } },
1963 { "vaddsbs", VX(4, 768), VX_MASK, PPCVEC, { VD, VA, VB } },
1964 { "vaddshs", VX(4, 832), VX_MASK, PPCVEC, { VD, VA, VB } },
1965 { "vaddsws", VX(4, 896), VX_MASK, PPCVEC, { VD, VA, VB } },
1966 { "vaddubm", VX(4, 0), VX_MASK, PPCVEC, { VD, VA, VB } },
1967 { "vaddubs", VX(4, 512), VX_MASK, PPCVEC, { VD, VA, VB } },
1968 { "vadduhm", VX(4, 64), VX_MASK, PPCVEC, { VD, VA, VB } },
1969 { "vadduhs", VX(4, 576), VX_MASK, PPCVEC, { VD, VA, VB } },
1970 { "vadduwm", VX(4, 128), VX_MASK, PPCVEC, { VD, VA, VB } },
1971 { "vadduws", VX(4, 640), VX_MASK, PPCVEC, { VD, VA, VB } },
1972 { "vand", VX(4, 1028), VX_MASK, PPCVEC, { VD, VA, VB } },
1973 { "vandc", VX(4, 1092), VX_MASK, PPCVEC, { VD, VA, VB } },
1974 { "vavgsb", VX(4, 1282), VX_MASK, PPCVEC, { VD, VA, VB } },
1975 { "vavgsh", VX(4, 1346), VX_MASK, PPCVEC, { VD, VA, VB } },
1976 { "vavgsw", VX(4, 1410), VX_MASK, PPCVEC, { VD, VA, VB } },
1977 { "vavgub", VX(4, 1026), VX_MASK, PPCVEC, { VD, VA, VB } },
1978 { "vavguh", VX(4, 1090), VX_MASK, PPCVEC, { VD, VA, VB } },
1979 { "vavguw", VX(4, 1154), VX_MASK, PPCVEC, { VD, VA, VB } },
1980 { "vcfsx", VX(4, 842), VX_MASK, PPCVEC, { VD, VB, UIMM } },
1981 { "vcfux", VX(4, 778), VX_MASK, PPCVEC, { VD, VB, UIMM } },
1982 { "vcmpbfp", VXR(4, 966, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1983 { "vcmpbfp.", VXR(4, 966, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1984 { "vcmpeqfp", VXR(4, 198, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1985 { "vcmpeqfp.", VXR(4, 198, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1986 { "vcmpequb", VXR(4, 6, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1987 { "vcmpequb.", VXR(4, 6, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1988 { "vcmpequh", VXR(4, 70, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1989 { "vcmpequh.", VXR(4, 70, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1990 { "vcmpequw", VXR(4, 134, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1991 { "vcmpequw.", VXR(4, 134, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1992 { "vcmpgefp", VXR(4, 454, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1993 { "vcmpgefp.", VXR(4, 454, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1994 { "vcmpgtfp", VXR(4, 710, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1995 { "vcmpgtfp.", VXR(4, 710, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1996 { "vcmpgtsb", VXR(4, 774, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1997 { "vcmpgtsb.", VXR(4, 774, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1998 { "vcmpgtsh", VXR(4, 838, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1999 { "vcmpgtsh.", VXR(4, 838, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2000 { "vcmpgtsw", VXR(4, 902, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2001 { "vcmpgtsw.", VXR(4, 902, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2002 { "vcmpgtub", VXR(4, 518, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2003 { "vcmpgtub.", VXR(4, 518, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2004 { "vcmpgtuh", VXR(4, 582, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2005 { "vcmpgtuh.", VXR(4, 582, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2006 { "vcmpgtuw", VXR(4, 646, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2007 { "vcmpgtuw.", VXR(4, 646, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2008 { "vctsxs", VX(4, 970), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2009 { "vctuxs", VX(4, 906), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2010 { "vexptefp", VX(4, 394), VX_MASK, PPCVEC, { VD, VB } },
2011 { "vlogefp", VX(4, 458), VX_MASK, PPCVEC, { VD, VB } },
2012 { "vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC, { VD, VA, VC, VB } },
2013 { "vmaxfp", VX(4, 1034), VX_MASK, PPCVEC, { VD, VA, VB } },
2014 { "vmaxsb", VX(4, 258), VX_MASK, PPCVEC, { VD, VA, VB } },
2015 { "vmaxsh", VX(4, 322), VX_MASK, PPCVEC, { VD, VA, VB } },
2016 { "vmaxsw", VX(4, 386), VX_MASK, PPCVEC, { VD, VA, VB } },
2017 { "vmaxub", VX(4, 2), VX_MASK, PPCVEC, { VD, VA, VB } },
2018 { "vmaxuh", VX(4, 66), VX_MASK, PPCVEC, { VD, VA, VB } },
2019 { "vmaxuw", VX(4, 130), VX_MASK, PPCVEC, { VD, VA, VB } },
2020 { "vmhaddshs", VXA(4, 32), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2021 { "vmhraddshs", VXA(4, 33), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2022 { "vminfp", VX(4, 1098), VX_MASK, PPCVEC, { VD, VA, VB } },
2023 { "vminsb", VX(4, 770), VX_MASK, PPCVEC, { VD, VA, VB } },
2024 { "vminsh", VX(4, 834), VX_MASK, PPCVEC, { VD, VA, VB } },
2025 { "vminsw", VX(4, 898), VX_MASK, PPCVEC, { VD, VA, VB } },
2026 { "vminub", VX(4, 514), VX_MASK, PPCVEC, { VD, VA, VB } },
2027 { "vminuh", VX(4, 578), VX_MASK, PPCVEC, { VD, VA, VB } },
2028 { "vminuw", VX(4, 642), VX_MASK, PPCVEC, { VD, VA, VB } },
2029 { "vmladduhm", VXA(4, 34), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2030 { "vmrghb", VX(4, 12), VX_MASK, PPCVEC, { VD, VA, VB } },
2031 { "vmrghh", VX(4, 76), VX_MASK, PPCVEC, { VD, VA, VB } },
2032 { "vmrghw", VX(4, 140), VX_MASK, PPCVEC, { VD, VA, VB } },
2033 { "vmrglb", VX(4, 268), VX_MASK, PPCVEC, { VD, VA, VB } },
2034 { "vmrglh", VX(4, 332), VX_MASK, PPCVEC, { VD, VA, VB } },
2035 { "vmrglw", VX(4, 396), VX_MASK, PPCVEC, { VD, VA, VB } },
2036 { "vmsummbm", VXA(4, 37), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2037 { "vmsumshm", VXA(4, 40), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2038 { "vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2039 { "vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2040 { "vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2041 { "vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2042 { "vmulesb", VX(4, 776), VX_MASK, PPCVEC, { VD, VA, VB } },
2043 { "vmulesh", VX(4, 840), VX_MASK, PPCVEC, { VD, VA, VB } },
2044 { "vmuleub", VX(4, 520), VX_MASK, PPCVEC, { VD, VA, VB } },
2045 { "vmuleuh", VX(4, 584), VX_MASK, PPCVEC, { VD, VA, VB } },
2046 { "vmulosb", VX(4, 264), VX_MASK, PPCVEC, { VD, VA, VB } },
2047 { "vmulosh", VX(4, 328), VX_MASK, PPCVEC, { VD, VA, VB } },
2048 { "vmuloub", VX(4, 8), VX_MASK, PPCVEC, { VD, VA, VB } },
2049 { "vmulouh", VX(4, 72), VX_MASK, PPCVEC, { VD, VA, VB } },
2050 { "vnmsubfp", VXA(4, 47), VXA_MASK, PPCVEC, { VD, VA, VC, VB } },
2051 { "vnor", VX(4, 1284), VX_MASK, PPCVEC, { VD, VA, VB } },
2052 { "vor", VX(4, 1156), VX_MASK, PPCVEC, { VD, VA, VB } },
2053 { "vperm", VXA(4, 43), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2054 { "vpkpx", VX(4, 782), VX_MASK, PPCVEC, { VD, VA, VB } },
2055 { "vpkshss", VX(4, 398), VX_MASK, PPCVEC, { VD, VA, VB } },
2056 { "vpkshus", VX(4, 270), VX_MASK, PPCVEC, { VD, VA, VB } },
2057 { "vpkswss", VX(4, 462), VX_MASK, PPCVEC, { VD, VA, VB } },
2058 { "vpkswus", VX(4, 334), VX_MASK, PPCVEC, { VD, VA, VB } },
2059 { "vpkuhum", VX(4, 14), VX_MASK, PPCVEC, { VD, VA, VB } },
2060 { "vpkuhus", VX(4, 142), VX_MASK, PPCVEC, { VD, VA, VB } },
2061 { "vpkuwum", VX(4, 78), VX_MASK, PPCVEC, { VD, VA, VB } },
2062 { "vpkuwus", VX(4, 206), VX_MASK, PPCVEC, { VD, VA, VB } },
2063 { "vrefp", VX(4, 266), VX_MASK, PPCVEC, { VD, VB } },
2064 { "vrfim", VX(4, 714), VX_MASK, PPCVEC, { VD, VB } },
2065 { "vrfin", VX(4, 522), VX_MASK, PPCVEC, { VD, VB } },
2066 { "vrfip", VX(4, 650), VX_MASK, PPCVEC, { VD, VB } },
2067 { "vrfiz", VX(4, 586), VX_MASK, PPCVEC, { VD, VB } },
2068 { "vrlb", VX(4, 4), VX_MASK, PPCVEC, { VD, VA, VB } },
2069 { "vrlh", VX(4, 68), VX_MASK, PPCVEC, { VD, VA, VB } },
2070 { "vrlw", VX(4, 132), VX_MASK, PPCVEC, { VD, VA, VB } },
2071 { "vrsqrtefp", VX(4, 330), VX_MASK, PPCVEC, { VD, VB } },
2072 { "vsel", VXA(4, 42), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2073 { "vsl", VX(4, 452), VX_MASK, PPCVEC, { VD, VA, VB } },
2074 { "vslb", VX(4, 260), VX_MASK, PPCVEC, { VD, VA, VB } },
2075 { "vsldoi", VXA(4, 44), VXA_MASK, PPCVEC, { VD, VA, VB, SHB } },
2076 { "vslh", VX(4, 324), VX_MASK, PPCVEC, { VD, VA, VB } },
2077 { "vslo", VX(4, 1036), VX_MASK, PPCVEC, { VD, VA, VB } },
2078 { "vslw", VX(4, 388), VX_MASK, PPCVEC, { VD, VA, VB } },
2079 { "vspltb", VX(4, 524), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2080 { "vsplth", VX(4, 588), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2081 { "vspltisb", VX(4, 780), VX_MASK, PPCVEC, { VD, SIMM } },
2082 { "vspltish", VX(4, 844), VX_MASK, PPCVEC, { VD, SIMM } },
2083 { "vspltisw", VX(4, 908), VX_MASK, PPCVEC, { VD, SIMM } },
2084 { "vspltw", VX(4, 652), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2085 { "vsr", VX(4, 708), VX_MASK, PPCVEC, { VD, VA, VB } },
2086 { "vsrab", VX(4, 772), VX_MASK, PPCVEC, { VD, VA, VB } },
2087 { "vsrah", VX(4, 836), VX_MASK, PPCVEC, { VD, VA, VB } },
2088 { "vsraw", VX(4, 900), VX_MASK, PPCVEC, { VD, VA, VB } },
2089 { "vsrb", VX(4, 516), VX_MASK, PPCVEC, { VD, VA, VB } },
2090 { "vsrh", VX(4, 580), VX_MASK, PPCVEC, { VD, VA, VB } },
2091 { "vsro", VX(4, 1100), VX_MASK, PPCVEC, { VD, VA, VB } },
2092 { "vsrw", VX(4, 644), VX_MASK, PPCVEC, { VD, VA, VB } },
2093 { "vsubcuw", VX(4, 1408), VX_MASK, PPCVEC, { VD, VA, VB } },
2094 { "vsubfp", VX(4, 74), VX_MASK, PPCVEC, { VD, VA, VB } },
2095 { "vsubsbs", VX(4, 1792), VX_MASK, PPCVEC, { VD, VA, VB } },
2096 { "vsubshs", VX(4, 1856), VX_MASK, PPCVEC, { VD, VA, VB } },
2097 { "vsubsws", VX(4, 1920), VX_MASK, PPCVEC, { VD, VA, VB } },
2098 { "vsububm", VX(4, 1024), VX_MASK, PPCVEC, { VD, VA, VB } },
2099 { "vsububs", VX(4, 1536), VX_MASK, PPCVEC, { VD, VA, VB } },
2100 { "vsubuhm", VX(4, 1088), VX_MASK, PPCVEC, { VD, VA, VB } },
2101 { "vsubuhs", VX(4, 1600), VX_MASK, PPCVEC, { VD, VA, VB } },
2102 { "vsubuwm", VX(4, 1152), VX_MASK, PPCVEC, { VD, VA, VB } },
2103 { "vsubuws", VX(4, 1664), VX_MASK, PPCVEC, { VD, VA, VB } },
2104 { "vsumsws", VX(4, 1928), VX_MASK, PPCVEC, { VD, VA, VB } },
2105 { "vsum2sws", VX(4, 1672), VX_MASK, PPCVEC, { VD, VA, VB } },
2106 { "vsum4sbs", VX(4, 1800), VX_MASK, PPCVEC, { VD, VA, VB } },
2107 { "vsum4shs", VX(4, 1608), VX_MASK, PPCVEC, { VD, VA, VB } },
2108 { "vsum4ubs", VX(4, 1544), VX_MASK, PPCVEC, { VD, VA, VB } },
2109 { "vupkhpx", VX(4, 846), VX_MASK, PPCVEC, { VD, VB } },
2110 { "vupkhsb", VX(4, 526), VX_MASK, PPCVEC, { VD, VB } },
2111 { "vupkhsh", VX(4, 590), VX_MASK, PPCVEC, { VD, VB } },
2112 { "vupklpx", VX(4, 974), VX_MASK, PPCVEC, { VD, VB } },
2113 { "vupklsb", VX(4, 654), VX_MASK, PPCVEC, { VD, VB } },
2114 { "vupklsh", VX(4, 718), VX_MASK, PPCVEC, { VD, VB } },
2115 { "vxor", VX(4, 1220), VX_MASK, PPCVEC, { VD, VA, VB } },
2117 { "evaddw", VX(4, 512), VX_MASK, PPCSPE, { RS, RA, RB } },
2118 { "evaddiw", VX(4, 514), VX_MASK, PPCSPE, { RS, RB, UIMM } },
2119 { "evsubfw", VX(4, 516), VX_MASK, PPCSPE, { RS, RA, RB } },
2120 { "evsubw", VX(4, 516), VX_MASK, PPCSPE, { RS, RB, RA } },
2121 { "evsubifw", VX(4, 518), VX_MASK, PPCSPE, { RS, UIMM, RB } },
2122 { "evsubiw", VX(4, 518), VX_MASK, PPCSPE, { RS, RB, UIMM } },
2123 { "evabs", VX(4, 520), VX_MASK, PPCSPE, { RS, RA } },
2124 { "evneg", VX(4, 521), VX_MASK, PPCSPE, { RS, RA } },
2125 { "evextsb", VX(4, 522), VX_MASK, PPCSPE, { RS, RA } },
2126 { "evextsh", VX(4, 523), VX_MASK, PPCSPE, { RS, RA } },
2127 { "evrndw", VX(4, 524), VX_MASK, PPCSPE, { RS, RA } },
2128 { "evcntlzw", VX(4, 525), VX_MASK, PPCSPE, { RS, RA } },
2129 { "evcntlsw", VX(4, 526), VX_MASK, PPCSPE, { RS, RA } },
2131 { "brinc", VX(4, 527), VX_MASK, PPCSPE, { RS, RA, RB } },
2133 { "evand", VX(4, 529), VX_MASK, PPCSPE, { RS, RA, RB } },
2134 { "evandc", VX(4, 530), VX_MASK, PPCSPE, { RS, RA, RB } },
2135 { "evmr", VX(4, 535), VX_MASK, PPCSPE, { RS, RA, BBA } },
2136 { "evor", VX(4, 535), VX_MASK, PPCSPE, { RS, RA, RB } },
2137 { "evorc", VX(4, 539), VX_MASK, PPCSPE, { RS, RA, RB } },
2138 { "evxor", VX(4, 534), VX_MASK, PPCSPE, { RS, RA, RB } },
2139 { "eveqv", VX(4, 537), VX_MASK, PPCSPE, { RS, RA, RB } },
2140 { "evnand", VX(4, 542), VX_MASK, PPCSPE, { RS, RA, RB } },
2141 { "evnot", VX(4, 536), VX_MASK, PPCSPE, { RS, RA, BBA } },
2142 { "evnor", VX(4, 536), VX_MASK, PPCSPE, { RS, RA, RB } },
2144 { "evrlw", VX(4, 552), VX_MASK, PPCSPE, { RS, RA, RB } },
2145 { "evrlwi", VX(4, 554), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2146 { "evslw", VX(4, 548), VX_MASK, PPCSPE, { RS, RA, RB } },
2147 { "evslwi", VX(4, 550), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2148 { "evsrws", VX(4, 545), VX_MASK, PPCSPE, { RS, RA, RB } },
2149 { "evsrwu", VX(4, 544), VX_MASK, PPCSPE, { RS, RA, RB } },
2150 { "evsrwis", VX(4, 547), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2151 { "evsrwiu", VX(4, 546), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2152 { "evsplati", VX(4, 553), VX_MASK, PPCSPE, { RS, SIMM } },
2153 { "evsplatfi", VX(4, 555), VX_MASK, PPCSPE, { RS, SIMM } },
2154 { "evmergehi", VX(4, 556), VX_MASK, PPCSPE, { RS, RA, RB } },
2155 { "evmergelo", VX(4, 557), VX_MASK, PPCSPE, { RS, RA, RB } },
2156 { "evmergehilo",VX(4,558), VX_MASK, PPCSPE, { RS, RA, RB } },
2157 { "evmergelohi",VX(4,559), VX_MASK, PPCSPE, { RS, RA, RB } },
2159 { "evcmpgts", VX(4, 561), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2160 { "evcmpgtu", VX(4, 560), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2161 { "evcmplts", VX(4, 563), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2162 { "evcmpltu", VX(4, 562), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2163 { "evcmpeq", VX(4, 564), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2164 { "evsel", EVSEL(4,79),EVSEL_MASK, PPCSPE, { RS, RA, RB, CRFS } },
2166 { "evldd", VX(4, 769), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2167 { "evlddx", VX(4, 768), VX_MASK, PPCSPE, { RS, RA, RB } },
2168 { "evldw", VX(4, 771), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2169 { "evldwx", VX(4, 770), VX_MASK, PPCSPE, { RS, RA, RB } },
2170 { "evldh", VX(4, 773), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2171 { "evldhx", VX(4, 772), VX_MASK, PPCSPE, { RS, RA, RB } },
2172 { "evlwhe", VX(4, 785), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2173 { "evlwhex", VX(4, 784), VX_MASK, PPCSPE, { RS, RA, RB } },
2174 { "evlwhou", VX(4, 789), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2175 { "evlwhoux", VX(4, 788), VX_MASK, PPCSPE, { RS, RA, RB } },
2176 { "evlwhos", VX(4, 791), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2177 { "evlwhosx", VX(4, 790), VX_MASK, PPCSPE, { RS, RA, RB } },
2178 { "evlwwsplat",VX(4, 793), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2179 { "evlwwsplatx",VX(4, 792), VX_MASK, PPCSPE, { RS, RA, RB } },
2180 { "evlwhsplat",VX(4, 797), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2181 { "evlwhsplatx",VX(4, 796), VX_MASK, PPCSPE, { RS, RA, RB } },
2182 { "evlhhesplat",VX(4, 777), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } },
2183 { "evlhhesplatx",VX(4, 776), VX_MASK, PPCSPE, { RS, RA, RB } },
2184 { "evlhhousplat",VX(4, 781), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } },
2185 { "evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE, { RS, RA, RB } },
2186 { "evlhhossplat",VX(4, 783), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } },
2187 { "evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE, { RS, RA, RB } },
2189 { "evstdd", VX(4, 801), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2190 { "evstddx", VX(4, 800), VX_MASK, PPCSPE, { RS, RA, RB } },
2191 { "evstdw", VX(4, 803), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2192 { "evstdwx", VX(4, 802), VX_MASK, PPCSPE, { RS, RA, RB } },
2193 { "evstdh", VX(4, 805), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2194 { "evstdhx", VX(4, 804), VX_MASK, PPCSPE, { RS, RA, RB } },
2195 { "evstwwe", VX(4, 825), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2196 { "evstwwex", VX(4, 824), VX_MASK, PPCSPE, { RS, RA, RB } },
2197 { "evstwwo", VX(4, 829), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2198 { "evstwwox", VX(4, 828), VX_MASK, PPCSPE, { RS, RA, RB } },
2199 { "evstwhe", VX(4, 817), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2200 { "evstwhex", VX(4, 816), VX_MASK, PPCSPE, { RS, RA, RB } },
2201 { "evstwho", VX(4, 821), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2202 { "evstwhox", VX(4, 820), VX_MASK, PPCSPE, { RS, RA, RB } },
2204 { "evfsabs", VX(4, 644), VX_MASK, PPCSPE, { RS, RA } },
2205 { "evfsnabs", VX(4, 645), VX_MASK, PPCSPE, { RS, RA } },
2206 { "evfsneg", VX(4, 646), VX_MASK, PPCSPE, { RS, RA } },
2207 { "evfsadd", VX(4, 640), VX_MASK, PPCSPE, { RS, RA, RB } },
2208 { "evfssub", VX(4, 641), VX_MASK, PPCSPE, { RS, RA, RB } },
2209 { "evfsmul", VX(4, 648), VX_MASK, PPCSPE, { RS, RA, RB } },
2210 { "evfsdiv", VX(4, 649), VX_MASK, PPCSPE, { RS, RA, RB } },
2211 { "evfscmpgt", VX(4, 652), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2212 { "evfscmplt", VX(4, 653), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2213 { "evfscmpeq", VX(4, 654), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2214 { "evfststgt", VX(4, 668), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2215 { "evfststlt", VX(4, 669), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2216 { "evfststeq", VX(4, 670), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2217 { "evfscfui", VX(4, 656), VX_MASK, PPCSPE, { RS, RB } },
2218 { "evfsctuiz", VX(4, 664), VX_MASK, PPCSPE, { RS, RB } },
2219 { "evfscfsi", VX(4, 657), VX_MASK, PPCSPE, { RS, RB } },
2220 { "evfscfuf", VX(4, 658), VX_MASK, PPCSPE, { RS, RB } },
2221 { "evfscfsf", VX(4, 659), VX_MASK, PPCSPE, { RS, RB } },
2222 { "evfsctui", VX(4, 660), VX_MASK, PPCSPE, { RS, RB } },
2223 { "evfsctsi", VX(4, 661), VX_MASK, PPCSPE, { RS, RB } },
2224 { "evfsctsiz", VX(4, 666), VX_MASK, PPCSPE, { RS, RB } },
2225 { "evfsctuf", VX(4, 662), VX_MASK, PPCSPE, { RS, RB } },
2226 { "evfsctsf", VX(4, 663), VX_MASK, PPCSPE, { RS, RB } },
2228 { "efsabs", VX(4, 708), VX_MASK, PPCEFS, { RS, RA } },
2229 { "efsnabs", VX(4, 709), VX_MASK, PPCEFS, { RS, RA } },
2230 { "efsneg", VX(4, 710), VX_MASK, PPCEFS, { RS, RA } },
2231 { "efsadd", VX(4, 704), VX_MASK, PPCEFS, { RS, RA, RB } },
2232 { "efssub", VX(4, 705), VX_MASK, PPCEFS, { RS, RA, RB } },
2233 { "efsmul", VX(4, 712), VX_MASK, PPCEFS, { RS, RA, RB } },
2234 { "efsdiv", VX(4, 713), VX_MASK, PPCEFS, { RS, RA, RB } },
2235 { "efscmpgt", VX(4, 716), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2236 { "efscmplt", VX(4, 717), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2237 { "efscmpeq", VX(4, 718), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2238 { "efststgt", VX(4, 732), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2239 { "efststlt", VX(4, 733), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2240 { "efststeq", VX(4, 734), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2241 { "efscfui", VX(4, 720), VX_MASK, PPCEFS, { RS, RB } },
2242 { "efsctuiz", VX(4, 728), VX_MASK, PPCEFS, { RS, RB } },
2243 { "efscfsi", VX(4, 721), VX_MASK, PPCEFS, { RS, RB } },
2244 { "efscfuf", VX(4, 722), VX_MASK, PPCEFS, { RS, RB } },
2245 { "efscfsf", VX(4, 723), VX_MASK, PPCEFS, { RS, RB } },
2246 { "efsctui", VX(4, 724), VX_MASK, PPCEFS, { RS, RB } },
2247 { "efsctsi", VX(4, 725), VX_MASK, PPCEFS, { RS, RB } },
2248 { "efsctsiz", VX(4, 730), VX_MASK, PPCEFS, { RS, RB } },
2249 { "efsctuf", VX(4, 726), VX_MASK, PPCEFS, { RS, RB } },
2250 { "efsctsf", VX(4, 727), VX_MASK, PPCEFS, { RS, RB } },
2252 { "evmhossf", VX(4, 1031), VX_MASK, PPCSPE, { RS, RA, RB } },
2253 { "evmhossfa", VX(4, 1063), VX_MASK, PPCSPE, { RS, RA, RB } },
2254 { "evmhosmf", VX(4, 1039), VX_MASK, PPCSPE, { RS, RA, RB } },
2255 { "evmhosmfa", VX(4, 1071), VX_MASK, PPCSPE, { RS, RA, RB } },
2256 { "evmhosmi", VX(4, 1037), VX_MASK, PPCSPE, { RS, RA, RB } },
2257 { "evmhosmia", VX(4, 1069), VX_MASK, PPCSPE, { RS, RA, RB } },
2258 { "evmhoumi", VX(4, 1036), VX_MASK, PPCSPE, { RS, RA, RB } },
2259 { "evmhoumia", VX(4, 1068), VX_MASK, PPCSPE, { RS, RA, RB } },
2260 { "evmhessf", VX(4, 1027), VX_MASK, PPCSPE, { RS, RA, RB } },
2261 { "evmhessfa", VX(4, 1059), VX_MASK, PPCSPE, { RS, RA, RB } },
2262 { "evmhesmf", VX(4, 1035), VX_MASK, PPCSPE, { RS, RA, RB } },
2263 { "evmhesmfa", VX(4, 1067), VX_MASK, PPCSPE, { RS, RA, RB } },
2264 { "evmhesmi", VX(4, 1033), VX_MASK, PPCSPE, { RS, RA, RB } },
2265 { "evmhesmia", VX(4, 1065), VX_MASK, PPCSPE, { RS, RA, RB } },
2266 { "evmheumi", VX(4, 1032), VX_MASK, PPCSPE, { RS, RA, RB } },
2267 { "evmheumia", VX(4, 1064), VX_MASK, PPCSPE, { RS, RA, RB } },
2269 { "evmhossfaaw",VX(4, 1287), VX_MASK, PPCSPE, { RS, RA, RB } },
2270 { "evmhossiaaw",VX(4, 1285), VX_MASK, PPCSPE, { RS, RA, RB } },
2271 { "evmhosmfaaw",VX(4, 1295), VX_MASK, PPCSPE, { RS, RA, RB } },
2272 { "evmhosmiaaw",VX(4, 1293), VX_MASK, PPCSPE, { RS, RA, RB } },
2273 { "evmhousiaaw",VX(4, 1284), VX_MASK, PPCSPE, { RS, RA, RB } },
2274 { "evmhoumiaaw",VX(4, 1292), VX_MASK, PPCSPE, { RS, RA, RB } },
2275 { "evmhessfaaw",VX(4, 1283), VX_MASK, PPCSPE, { RS, RA, RB } },
2276 { "evmhessiaaw",VX(4, 1281), VX_MASK, PPCSPE, { RS, RA, RB } },
2277 { "evmhesmfaaw",VX(4, 1291), VX_MASK, PPCSPE, { RS, RA, RB } },
2278 { "evmhesmiaaw",VX(4, 1289), VX_MASK, PPCSPE, { RS, RA, RB } },
2279 { "evmheusiaaw",VX(4, 1280), VX_MASK, PPCSPE, { RS, RA, RB } },
2280 { "evmheumiaaw",VX(4, 1288), VX_MASK, PPCSPE, { RS, RA, RB } },
2282 { "evmhossfanw",VX(4, 1415), VX_MASK, PPCSPE, { RS, RA, RB } },
2283 { "evmhossianw",VX(4, 1413), VX_MASK, PPCSPE, { RS, RA, RB } },
2284 { "evmhosmfanw",VX(4, 1423), VX_MASK, PPCSPE, { RS, RA, RB } },
2285 { "evmhosmianw",VX(4, 1421), VX_MASK, PPCSPE, { RS, RA, RB } },
2286 { "evmhousianw",VX(4, 1412), VX_MASK, PPCSPE, { RS, RA, RB } },
2287 { "evmhoumianw",VX(4, 1420), VX_MASK, PPCSPE, { RS, RA, RB } },
2288 { "evmhessfanw",VX(4, 1411), VX_MASK, PPCSPE, { RS, RA, RB } },
2289 { "evmhessianw",VX(4, 1409), VX_MASK, PPCSPE, { RS, RA, RB } },
2290 { "evmhesmfanw",VX(4, 1419), VX_MASK, PPCSPE, { RS, RA, RB } },
2291 { "evmhesmianw",VX(4, 1417), VX_MASK, PPCSPE, { RS, RA, RB } },
2292 { "evmheusianw",VX(4, 1408), VX_MASK, PPCSPE, { RS, RA, RB } },
2293 { "evmheumianw",VX(4, 1416), VX_MASK, PPCSPE, { RS, RA, RB } },
2295 { "evmhogsmfaa",VX(4, 1327), VX_MASK, PPCSPE, { RS, RA, RB } },
2296 { "evmhogsmiaa",VX(4, 1325), VX_MASK, PPCSPE, { RS, RA, RB } },
2297 { "evmhogumiaa",VX(4, 1324), VX_MASK, PPCSPE, { RS, RA, RB } },
2298 { "evmhegsmfaa",VX(4, 1323), VX_MASK, PPCSPE, { RS, RA, RB } },
2299 { "evmhegsmiaa",VX(4, 1321), VX_MASK, PPCSPE, { RS, RA, RB } },
2300 { "evmhegumiaa",VX(4, 1320), VX_MASK, PPCSPE, { RS, RA, RB } },
2302 { "evmhogsmfan",VX(4, 1455), VX_MASK, PPCSPE, { RS, RA, RB } },
2303 { "evmhogsmian",VX(4, 1453), VX_MASK, PPCSPE, { RS, RA, RB } },
2304 { "evmhogumian",VX(4, 1452), VX_MASK, PPCSPE, { RS, RA, RB } },
2305 { "evmhegsmfan",VX(4, 1451), VX_MASK, PPCSPE, { RS, RA, RB } },
2306 { "evmhegsmian",VX(4, 1449), VX_MASK, PPCSPE, { RS, RA, RB } },
2307 { "evmhegumian",VX(4, 1448), VX_MASK, PPCSPE, { RS, RA, RB } },
2309 { "evmwhssf", VX(4, 1095), VX_MASK, PPCSPE, { RS, RA, RB } },
2310 { "evmwhssfa", VX(4, 1127), VX_MASK, PPCSPE, { RS, RA, RB } },
2311 { "evmwhsmf", VX(4, 1103), VX_MASK, PPCSPE, { RS, RA, RB } },
2312 { "evmwhsmfa", VX(4, 1135), VX_MASK, PPCSPE, { RS, RA, RB } },
2313 { "evmwhsmi", VX(4, 1101), VX_MASK, PPCSPE, { RS, RA, RB } },
2314 { "evmwhsmia", VX(4, 1133), VX_MASK, PPCSPE, { RS, RA, RB } },
2315 { "evmwhumi", VX(4, 1100), VX_MASK, PPCSPE, { RS, RA, RB } },
2316 { "evmwhumia", VX(4, 1132), VX_MASK, PPCSPE, { RS, RA, RB } },
2318 { "evmwlumi", VX(4, 1096), VX_MASK, PPCSPE, { RS, RA, RB } },
2319 { "evmwlumia", VX(4, 1128), VX_MASK, PPCSPE, { RS, RA, RB } },
2321 { "evmwlssiaaw",VX(4, 1345), VX_MASK, PPCSPE, { RS, RA, RB } },
2322 { "evmwlsmiaaw",VX(4, 1353), VX_MASK, PPCSPE, { RS, RA, RB } },
2323 { "evmwlusiaaw",VX(4, 1344), VX_MASK, PPCSPE, { RS, RA, RB } },
2324 { "evmwlumiaaw",VX(4, 1352), VX_MASK, PPCSPE, { RS, RA, RB } },
2326 { "evmwlssianw",VX(4, 1473), VX_MASK, PPCSPE, { RS, RA, RB } },
2327 { "evmwlsmianw",VX(4, 1481), VX_MASK, PPCSPE, { RS, RA, RB } },
2328 { "evmwlusianw",VX(4, 1472), VX_MASK, PPCSPE, { RS, RA, RB } },
2329 { "evmwlumianw",VX(4, 1480), VX_MASK, PPCSPE, { RS, RA, RB } },
2331 { "evmwssf", VX(4, 1107), VX_MASK, PPCSPE, { RS, RA, RB } },
2332 { "evmwssfa", VX(4, 1139), VX_MASK, PPCSPE, { RS, RA, RB } },
2333 { "evmwsmf", VX(4, 1115), VX_MASK, PPCSPE, { RS, RA, RB } },
2334 { "evmwsmfa", VX(4, 1147), VX_MASK, PPCSPE, { RS, RA, RB } },
2335 { "evmwsmi", VX(4, 1113), VX_MASK, PPCSPE, { RS, RA, RB } },
2336 { "evmwsmia", VX(4, 1145), VX_MASK, PPCSPE, { RS, RA, RB } },
2337 { "evmwumi", VX(4, 1112), VX_MASK, PPCSPE, { RS, RA, RB } },
2338 { "evmwumia", VX(4, 1144), VX_MASK, PPCSPE, { RS, RA, RB } },
2340 { "evmwssfaa", VX(4, 1363), VX_MASK, PPCSPE, { RS, RA, RB } },
2341 { "evmwsmfaa", VX(4, 1371), VX_MASK, PPCSPE, { RS, RA, RB } },
2342 { "evmwsmiaa", VX(4, 1369), VX_MASK, PPCSPE, { RS, RA, RB } },
2343 { "evmwumiaa", VX(4, 1368), VX_MASK, PPCSPE, { RS, RA, RB } },
2345 { "evmwssfan", VX(4, 1491), VX_MASK, PPCSPE, { RS, RA, RB } },
2346 { "evmwsmfan", VX(4, 1499), VX_MASK, PPCSPE, { RS, RA, RB } },
2347 { "evmwsmian", VX(4, 1497), VX_MASK, PPCSPE, { RS, RA, RB } },
2348 { "evmwumian", VX(4, 1496), VX_MASK, PPCSPE, { RS, RA, RB } },
2350 { "evaddssiaaw",VX(4, 1217), VX_MASK, PPCSPE, { RS, RA } },
2351 { "evaddsmiaaw",VX(4, 1225), VX_MASK, PPCSPE, { RS, RA } },
2352 { "evaddusiaaw",VX(4, 1216), VX_MASK, PPCSPE, { RS, RA } },
2353 { "evaddumiaaw",VX(4, 1224), VX_MASK, PPCSPE, { RS, RA } },
2355 { "evsubfssiaaw",VX(4, 1219), VX_MASK, PPCSPE, { RS, RA } },
2356 { "evsubfsmiaaw",VX(4, 1227), VX_MASK, PPCSPE, { RS, RA } },
2357 { "evsubfusiaaw",VX(4, 1218), VX_MASK, PPCSPE, { RS, RA } },
2358 { "evsubfumiaaw",VX(4, 1226), VX_MASK, PPCSPE, { RS, RA } },
2360 { "evmra", VX(4, 1220), VX_MASK, PPCSPE, { RS, RA } },
2362 { "evdivws", VX(4, 1222), VX_MASK, PPCSPE, { RS, RA, RB } },
2363 { "evdivwu", VX(4, 1223), VX_MASK, PPCSPE, { RS, RA, RB } },
2365 { "mulli", OP(7), OP_MASK, PPCCOM, { RT, RA, SI } },
2366 { "muli", OP(7), OP_MASK, PWRCOM, { RT, RA, SI } },
2368 { "subfic", OP(8), OP_MASK, PPCCOM, { RT, RA, SI } },
2369 { "sfi", OP(8), OP_MASK, PWRCOM, { RT, RA, SI } },
2371 { "dozi", OP(9), OP_MASK, M601, { RT, RA, SI } },
2373 { "bce", B(9,0,0), B_MASK, BOOKE64, { BO, BI, BD } },
2374 { "bcel", B(9,0,1), B_MASK, BOOKE64, { BO, BI, BD } },
2375 { "bcea", B(9,1,0), B_MASK, BOOKE64, { BO, BI, BDA } },
2376 { "bcela", B(9,1,1), B_MASK, BOOKE64, { BO, BI, BDA } },
2378 { "cmplwi", OPL(10,0), OPL_MASK, PPCCOM, { OBF, RA, UI } },
2379 { "cmpldi", OPL(10,1), OPL_MASK, PPC64, { OBF, RA, UI } },
2380 { "cmpli", OP(10), OP_MASK, PPC, { BF, L, RA, UI } },
2381 { "cmpli", OP(10), OP_MASK, PWRCOM, { BF, RA, UI } },
2383 { "cmpwi", OPL(11,0), OPL_MASK, PPCCOM, { OBF, RA, SI } },
2384 { "cmpdi", OPL(11,1), OPL_MASK, PPC64, { OBF, RA, SI } },
2385 { "cmpi", OP(11), OP_MASK, PPC, { BF, L, RA, SI } },
2386 { "cmpi", OP(11), OP_MASK, PWRCOM, { BF, RA, SI } },
2388 { "addic", OP(12), OP_MASK, PPCCOM, { RT, RA, SI } },
2389 { "ai", OP(12), OP_MASK, PWRCOM, { RT, RA, SI } },
2390 { "subic", OP(12), OP_MASK, PPCCOM, { RT, RA, NSI } },
2392 { "addic.", OP(13), OP_MASK, PPCCOM, { RT, RA, SI } },
2393 { "ai.", OP(13), OP_MASK, PWRCOM, { RT, RA, SI } },
2394 { "subic.", OP(13), OP_MASK, PPCCOM, { RT, RA, NSI } },
2396 { "li", OP(14), DRA_MASK, PPCCOM, { RT, SI } },
2397 { "lil", OP(14), DRA_MASK, PWRCOM, { RT, SI } },
2398 { "addi", OP(14), OP_MASK, PPCCOM, { RT, RA0, SI } },
2399 { "cal", OP(14), OP_MASK, PWRCOM, { RT, D, RA0 } },
2400 { "subi", OP(14), OP_MASK, PPCCOM, { RT, RA0, NSI } },
2401 { "la", OP(14), OP_MASK, PPCCOM, { RT, D, RA0 } },
2403 { "lis", OP(15), DRA_MASK, PPCCOM, { RT, SISIGNOPT } },
2404 { "liu", OP(15), DRA_MASK, PWRCOM, { RT, SISIGNOPT } },
2405 { "addis", OP(15), OP_MASK, PPCCOM, { RT,RA0,SISIGNOPT } },
2406 { "cau", OP(15), OP_MASK, PWRCOM, { RT,RA0,SISIGNOPT } },
2407 { "subis", OP(15), OP_MASK, PPCCOM, { RT, RA0, NSI } },
2409 { "bdnz-", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDM } },
2410 { "bdnz+", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDP } },
2411 { "bdnz", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BD } },
2412 { "bdn", BBO(16,BODNZ,0,0), BBOATBI_MASK, PWRCOM, { BD } },
2413 { "bdnzl-", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BDM } },
2414 { "bdnzl+", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BDP } },
2415 { "bdnzl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BD } },
2416 { "bdnl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PWRCOM, { BD } },
2417 { "bdnza-", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDMA } },
2418 { "bdnza+", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDPA } },
2419 { "bdnza", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDA } },
2420 { "bdna", BBO(16,BODNZ,1,0), BBOATBI_MASK, PWRCOM, { BDA } },
2421 { "bdnzla-", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDMA } },
2422 { "bdnzla+", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDPA } },
2423 { "bdnzla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDA } },
2424 { "bdnla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PWRCOM, { BDA } },
2425 { "bdz-", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, { BDM } },
2426 { "bdz+", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, { BDP } },
2427 { "bdz", BBO(16,BODZ,0,0), BBOATBI_MASK, COM, { BD } },
2428 { "bdzl-", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, { BDM } },
2429 { "bdzl+", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, { BDP } },
2430 { "bdzl", BBO(16,BODZ,0,1), BBOATBI_MASK, COM, { BD } },
2431 { "bdza-", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, { BDMA } },
2432 { "bdza+", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, { BDPA } },
2433 { "bdza", BBO(16,BODZ,1,0), BBOATBI_MASK, COM, { BDA } },
2434 { "bdzla-", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDMA } },
2435 { "bdzla+", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDPA } },
2436 { "bdzla", BBO(16,BODZ,1,1), BBOATBI_MASK, COM, { BDA } },
2437 { "blt-", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2438 { "blt+", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2439 { "blt", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2440 { "bltl-", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2441 { "bltl+", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2442 { "bltl", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2443 { "blta-", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2444 { "blta+", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2445 { "blta", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2446 { "bltla-", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2447 { "bltla+", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2448 { "bltla", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2449 { "bgt-", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2450 { "bgt+", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2451 { "bgt", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2452 { "bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2453 { "bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2454 { "bgtl", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2455 { "bgta-", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2456 { "bgta+", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2457 { "bgta", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2458 { "bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2459 { "bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2460 { "bgtla", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2461 { "beq-", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2462 { "beq+", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2463 { "beq", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, COM, { CR, BD } },
2464 { "beql-", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2465 { "beql+", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2466 { "beql", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, COM, { CR, BD } },
2467 { "beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2468 { "beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2469 { "beqa", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2470 { "beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2471 { "beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2472 { "beqla", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2473 { "bso-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2474 { "bso+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2475 { "bso", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, COM, { CR, BD } },
2476 { "bsol-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2477 { "bsol+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2478 { "bsol", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, COM, { CR, BD } },
2479 { "bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2480 { "bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2481 { "bsoa", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2482 { "bsola-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2483 { "bsola+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2484 { "bsola", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2485 { "bun-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2486 { "bun+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2487 { "bun", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BD } },
2488 { "bunl-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2489 { "bunl+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2490 { "bunl", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BD } },
2491 { "buna-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2492 { "buna+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2493 { "buna", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDA } },
2494 { "bunla-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2495 { "bunla+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2496 { "bunla", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDA } },
2497 { "bge-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2498 { "bge+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2499 { "bge", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2500 { "bgel-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2501 { "bgel+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2502 { "bgel", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2503 { "bgea-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2504 { "bgea+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2505 { "bgea", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2506 { "bgela-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2507 { "bgela+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2508 { "bgela", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2509 { "bnl-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2510 { "bnl+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2511 { "bnl", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2512 { "bnll-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2513 { "bnll+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2514 { "bnll", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2515 { "bnla-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2516 { "bnla+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2517 { "bnla", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2518 { "bnlla-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2519 { "bnlla+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2520 { "bnlla", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2521 { "ble-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2522 { "ble+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2523 { "ble", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2524 { "blel-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2525 { "blel+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2526 { "blel", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2527 { "blea-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2528 { "blea+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2529 { "blea", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2530 { "blela-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2531 { "blela+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2532 { "blela", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2533 { "bng-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2534 { "bng+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2535 { "bng", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2536 { "bngl-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2537 { "bngl+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2538 { "bngl", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2539 { "bnga-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2540 { "bnga+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2541 { "bnga", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2542 { "bngla-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2543 { "bngla+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2544 { "bngla", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2545 { "bne-", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2546 { "bne+", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2547 { "bne", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, COM, { CR, BD } },
2548 { "bnel-", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2549 { "bnel+", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2550 { "bnel", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, COM, { CR, BD } },
2551 { "bnea-", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2552 { "bnea+", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2553 { "bnea", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2554 { "bnela-", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2555 { "bnela+", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2556 { "bnela", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2557 { "bns-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2558 { "bns+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2559 { "bns", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, COM, { CR, BD } },
2560 { "bnsl-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2561 { "bnsl+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2562 { "bnsl", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, COM, { CR, BD } },
2563 { "bnsa-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2564 { "bnsa+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2565 { "bnsa", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2566 { "bnsla-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2567 { "bnsla+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2568 { "bnsla", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2569 { "bnu-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2570 { "bnu+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2571 { "bnu", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BD } },
2572 { "bnul-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2573 { "bnul+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2574 { "bnul", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BD } },
2575 { "bnua-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2576 { "bnua+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2577 { "bnua", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDA } },
2578 { "bnula-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2579 { "bnula+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2580 { "bnula", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDA } },
2581 { "bdnzt-", BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
2582 { "bdnzt+", BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
2583 { "bdnzt", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
2584 { "bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
2585 { "bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
2586 { "bdnztl", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
2587 { "bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2588 { "bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2589 { "bdnzta", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
2590 { "bdnztla-",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2591 { "bdnztla+",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2592 { "bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
2593 { "bdnzf-", BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
2594 { "bdnzf+", BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
2595 { "bdnzf", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
2596 { "bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
2597 { "bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
2598 { "bdnzfl", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
2599 { "bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2600 { "bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2601 { "bdnzfa", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
2602 { "bdnzfla-",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2603 { "bdnzfla+",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2604 { "bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
2605 { "bt-", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BDM } },
2606 { "bt+", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BDP } },
2607 { "bt", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BD } },
2608 { "bbt", BBO(16,BOT,0,0), BBOAT_MASK, PWRCOM, { BI, BD } },
2609 { "btl-", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BDM } },
2610 { "btl+", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BDP } },
2611 { "btl", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BD } },
2612 { "bbtl", BBO(16,BOT,0,1), BBOAT_MASK, PWRCOM, { BI, BD } },
2613 { "bta-", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2614 { "bta+", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2615 { "bta", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDA } },
2616 { "bbta", BBO(16,BOT,1,0), BBOAT_MASK, PWRCOM, { BI, BDA } },
2617 { "btla-", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2618 { "btla+", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2619 { "btla", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDA } },
2620 { "bbtla", BBO(16,BOT,1,1), BBOAT_MASK, PWRCOM, { BI, BDA } },
2621 { "bf-", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BDM } },
2622 { "bf+", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BDP } },
2623 { "bf", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BD } },
2624 { "bbf", BBO(16,BOF,0,0), BBOAT_MASK, PWRCOM, { BI, BD } },
2625 { "bfl-", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BDM } },
2626 { "bfl+", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BDP } },
2627 { "bfl", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BD } },
2628 { "bbfl", BBO(16,BOF,0,1), BBOAT_MASK, PWRCOM, { BI, BD } },
2629 { "bfa-", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2630 { "bfa+", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2631 { "bfa", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDA } },
2632 { "bbfa", BBO(16,BOF,1,0), BBOAT_MASK, PWRCOM, { BI, BDA } },
2633 { "bfla-", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2634 { "bfla+", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2635 { "bfla", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDA } },
2636 { "bbfla", BBO(16,BOF,1,1), BBOAT_MASK, PWRCOM, { BI, BDA } },
2637 { "bdzt-", BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
2638 { "bdzt+", BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
2639 { "bdzt", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
2640 { "bdztl-", BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
2641 { "bdztl+", BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
2642 { "bdztl", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
2643 { "bdzta-", BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2644 { "bdzta+", BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2645 { "bdzta", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
2646 { "bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2647 { "bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2648 { "bdztla", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
2649 { "bdzf-", BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
2650 { "bdzf+", BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
2651 { "bdzf", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
2652 { "bdzfl-", BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
2653 { "bdzfl+", BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
2654 { "bdzfl", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
2655 { "bdzfa-", BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2656 { "bdzfa+", BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2657 { "bdzfa", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
2658 { "bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2659 { "bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2660 { "bdzfla", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
2661 { "bc-", B(16,0,0), B_MASK, PPCCOM, { BOE, BI, BDM } },
2662 { "bc+", B(16,0,0), B_MASK, PPCCOM, { BOE, BI, BDP } },
2663 { "bc", B(16,0,0), B_MASK, COM, { BO, BI, BD } },
2664 { "bcl-", B(16,0,1), B_MASK, PPCCOM, { BOE, BI, BDM } },
2665 { "bcl+", B(16,0,1), B_MASK, PPCCOM, { BOE, BI, BDP } },
2666 { "bcl", B(16,0,1), B_MASK, COM, { BO, BI, BD } },
2667 { "bca-", B(16,1,0), B_MASK, PPCCOM, { BOE, BI, BDMA } },
2668 { "bca+", B(16,1,0), B_MASK, PPCCOM, { BOE, BI, BDPA } },
2669 { "bca", B(16,1,0), B_MASK, COM, { BO, BI, BDA } },
2670 { "bcla-", B(16,1,1), B_MASK, PPCCOM, { BOE, BI, BDMA } },
2671 { "bcla+", B(16,1,1), B_MASK, PPCCOM, { BOE, BI, BDPA } },
2672 { "bcla", B(16,1,1), B_MASK, COM, { BO, BI, BDA } },
2674 { "sc", SC(17,1,0), 0xffffffff, PPC, { 0 } },
2675 { "svc", SC(17,0,0), SC_MASK, POWER, { LEV, FL1, FL2 } },
2676 { "svcl", SC(17,0,1), SC_MASK, POWER, { LEV, FL1, FL2 } },
2677 { "svca", SC(17,1,0), SC_MASK, PWRCOM, { SV } },
2678 { "svcla", SC(17,1,1), SC_MASK, POWER, { SV } },
2680 { "b", B(18,0,0), B_MASK, COM, { LI } },
2681 { "bl", B(18,0,1), B_MASK, COM, { LI } },
2682 { "ba", B(18,1,0), B_MASK, COM, { LIA } },
2683 { "bla", B(18,1,1), B_MASK, COM, { LIA } },
2685 { "mcrf", XL(19,0), XLBB_MASK|(3 << 21)|(3 << 16), COM, { BF, BFA } },
2687 { "blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
2688 { "br", XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM, { 0 } },
2689 { "blrl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
2690 { "brl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM, { 0 } },
2691 { "bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
2692 { "bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2693 { "bdnzlr-", XLO(19,BODNZM4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
2694 { "bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2695 { "bdnzlr+", XLO(19,BODNZP4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
2696 { "bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
2697 { "bdnzlrl-",XLO(19,BODNZ,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2698 { "bdnzlrl-",XLO(19,BODNZM4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
2699 { "bdnzlrl+",XLO(19,BODNZP,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2700 { "bdnzlrl+",XLO(19,BODNZP4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
2701 { "bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
2702 { "bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2703 { "bdzlr-", XLO(19,BODZM4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
2704 { "bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2705 { "bdzlr+", XLO(19,BODZP4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
2706 { "bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
2707 { "bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2708 { "bdzlrl-", XLO(19,BODZM4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
2709 { "bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2710 { "bdzlrl+", XLO(19,BODZP4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
2711 { "bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2712 { "bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2713 { "bltlr-", XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2714 { "bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2715 { "bltlr+", XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2716 { "bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2717 { "bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2718 { "bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2719 { "bltlrl-", XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2720 { "bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2721 { "bltlrl+", XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2722 { "bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2723 { "bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2724 { "bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2725 { "bgtlr-", XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2726 { "bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2727 { "bgtlr+", XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2728 { "bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2729 { "bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2730 { "bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2731 { "bgtlrl-", XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2732 { "bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2733 { "bgtlrl+", XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2734 { "bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2735 { "beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2736 { "beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2737 { "beqlr-", XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2738 { "beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2739 { "beqlr+", XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2740 { "beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2741 { "beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2742 { "beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2743 { "beqlrl-", XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2744 { "beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2745 { "beqlrl+", XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2746 { "beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2747 { "bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2748 { "bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2749 { "bsolr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2750 { "bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2751 { "bsolr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2752 { "bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2753 { "bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2754 { "bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2755 { "bsolrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2756 { "bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2757 { "bsolrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2758 { "bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2759 { "bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2760 { "bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2761 { "bunlr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2762 { "bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2763 { "bunlr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2764 { "bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2765 { "bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2766 { "bunlrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2767 { "bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2768 { "bunlrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2769 { "bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2770 { "bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2771 { "bgelr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2772 { "bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2773 { "bgelr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2774 { "bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2775 { "bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2776 { "bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2777 { "bgelrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2778 { "bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2779 { "bgelrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2780 { "bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2781 { "bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2782 { "bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2783 { "bnllr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2784 { "bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2785 { "bnllr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2786 { "bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2787 { "bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2788 { "bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2789 { "bnllrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2790 { "bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2791 { "bnllrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2792 { "bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2793 { "blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2794 { "blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2795 { "blelr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2796 { "blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2797 { "blelr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2798 { "bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2799 { "blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2800 { "blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2801 { "blelrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2802 { "blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2803 { "blelrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2804 { "blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2805 { "bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2806 { "bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2807 { "bnglr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2808 { "bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2809 { "bnglr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2810 { "bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2811 { "bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2812 { "bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2813 { "bnglrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2814 { "bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2815 { "bnglrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2816 { "bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2817 { "bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2818 { "bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2819 { "bnelr-", XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2820 { "bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2821 { "bnelr+", XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2822 { "bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2823 { "bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2824 { "bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2825 { "bnelrl-", XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2826 { "bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2827 { "bnelrl+", XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2828 { "bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2829 { "bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2830 { "bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2831 { "bnslr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2832 { "bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2833 { "bnslr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2834 { "bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2835 { "bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2836 { "bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2837 { "bnslrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2838 { "bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2839 { "bnslrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2840 { "bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2841 { "bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2842 { "bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2843 { "bnulr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2844 { "bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2845 { "bnulr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2846 { "bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2847 { "bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2848 { "bnulrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2849 { "bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2850 { "bnulrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2851 { "btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2852 { "btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2853 { "btlr-", XLO(19,BOTM4,16,0), XLBOBB_MASK, POWER4, { BI } },
2854 { "btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2855 { "btlr+", XLO(19,BOTP4,16,0), XLBOBB_MASK, POWER4, { BI } },
2856 { "bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM, { BI } },
2857 { "btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2858 { "btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2859 { "btlrl-", XLO(19,BOTM4,16,1), XLBOBB_MASK, POWER4, { BI } },
2860 { "btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2861 { "btlrl+", XLO(19,BOTP4,16,1), XLBOBB_MASK, POWER4, { BI } },
2862 { "bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM, { BI } },
2863 { "bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2864 { "bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2865 { "bflr-", XLO(19,BOFM4,16,0), XLBOBB_MASK, POWER4, { BI } },
2866 { "bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2867 { "bflr+", XLO(19,BOFP4,16,0), XLBOBB_MASK, POWER4, { BI } },
2868 { "bbfr", XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM, { BI } },
2869 { "bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2870 { "bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2871 { "bflrl-", XLO(19,BOFM4,16,1), XLBOBB_MASK, POWER4, { BI } },
2872 { "bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2873 { "bflrl+", XLO(19,BOFP4,16,1), XLBOBB_MASK, POWER4, { BI } },
2874 { "bbfrl", XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM, { BI } },
2875 { "bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2876 { "bdnztlr-",XLO(19,BODNZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2877 { "bdnztlr+",XLO(19,BODNZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2878 { "bdnztlrl",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2879 { "bdnztlrl-",XLO(19,BODNZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2880 { "bdnztlrl+",XLO(19,BODNZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2881 { "bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2882 { "bdnzflr-",XLO(19,BODNZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2883 { "bdnzflr+",XLO(19,BODNZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2884 { "bdnzflrl",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2885 { "bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2886 { "bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2887 { "bdztlr", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2888 { "bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2889 { "bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2890 { "bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2891 { "bdztlrl-",XLO(19,BODZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2892 { "bdztlrl+",XLO(19,BODZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2893 { "bdzflr", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2894 { "bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2895 { "bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2896 { "bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2897 { "bdzflrl-",XLO(19,BODZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2898 { "bdzflrl+",XLO(19,BODZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2899 { "bclr+", XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
2900 { "bclrl+", XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
2901 { "bclr-", XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
2902 { "bclrl-", XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
2903 { "bclr", XLLK(19,16,0), XLBH_MASK, PPCCOM, { BO, BI, BH } },
2904 { "bclrl", XLLK(19,16,1), XLBH_MASK, PPCCOM, { BO, BI, BH } },
2905 { "bcr", XLLK(19,16,0), XLBB_MASK, PWRCOM, { BO, BI } },
2906 { "bcrl", XLLK(19,16,1), XLBB_MASK, PWRCOM, { BO, BI } },
2907 { "bclre", XLLK(19,17,0), XLBB_MASK, BOOKE64, { BO, BI } },
2908 { "bclrel", XLLK(19,17,1), XLBB_MASK, BOOKE64, { BO, BI } },
2910 { "rfid", XL(19,18), 0xffffffff, PPC64, { 0 } },
2912 { "crnot", XL(19,33), XL_MASK, PPCCOM, { BT, BA, BBA } },
2913 { "crnor", XL(19,33), XL_MASK, COM, { BT, BA, BB } },
2914 { "rfmci", X(19,38), 0xffffffff, PPCRFMCI, { 0 } },
2916 { "rfi", XL(19,50), 0xffffffff, COM, { 0 } },
2917 { "rfci", XL(19,51), 0xffffffff, PPC403 | BOOKE, { 0 } },
2919 { "rfsvc", XL(19,82), 0xffffffff, POWER, { 0 } },
2921 { "crandc", XL(19,129), XL_MASK, COM, { BT, BA, BB } },
2923 { "isync", XL(19,150), 0xffffffff, PPCCOM, { 0 } },
2924 { "ics", XL(19,150), 0xffffffff, PWRCOM, { 0 } },
2926 { "crclr", XL(19,193), XL_MASK, PPCCOM, { BT, BAT, BBA } },
2927 { "crxor", XL(19,193), XL_MASK, COM, { BT, BA, BB } },
2929 { "crnand", XL(19,225), XL_MASK, COM, { BT, BA, BB } },
2931 { "crand", XL(19,257), XL_MASK, COM, { BT, BA, BB } },
2933 { "crset", XL(19,289), XL_MASK, PPCCOM, { BT, BAT, BBA } },
2934 { "creqv", XL(19,289), XL_MASK, COM, { BT, BA, BB } },
2936 { "crorc", XL(19,417), XL_MASK, COM, { BT, BA, BB } },
2938 { "crmove", XL(19,449), XL_MASK, PPCCOM, { BT, BA, BBA } },
2939 { "cror", XL(19,449), XL_MASK, COM, { BT, BA, BB } },
2941 { "bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, COM, { 0 } },
2942 { "bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, { 0 } },
2943 { "bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2944 { "bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2945 { "bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2946 { "bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2947 { "bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2948 { "bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2949 { "bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2950 { "bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2951 { "bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2952 { "bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2953 { "bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2954 { "bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2955 { "bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2956 { "bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2957 { "bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2958 { "bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2959 { "bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2960 { "bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2961 { "bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2962 { "bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2963 { "beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2964 { "beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2965 { "beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2966 { "beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2967 { "beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2968 { "beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2969 { "beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2970 { "beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2971 { "beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2972 { "beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2973 { "bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2974 { "bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2975 { "bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2976 { "bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2977 { "bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2978 { "bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2979 { "bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2980 { "bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2981 { "bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2982 { "bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2983 { "bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2984 { "bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2985 { "bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2986 { "bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2987 { "bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2988 { "bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2989 { "bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2990 { "bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2991 { "bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2992 { "bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2993 { "bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2994 { "bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2995 { "bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2996 { "bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2997 { "bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2998 { "bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2999 { "bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3000 { "bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3001 { "bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3002 { "bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3003 { "bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3004 { "bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3005 { "bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3006 { "bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3007 { "bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3008 { "bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3009 { "bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3010 { "bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3011 { "bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3012 { "bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3013 { "blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3014 { "blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3015 { "blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3016 { "blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3017 { "blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3018 { "blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3019 { "blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3020 { "blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3021 { "blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3022 { "blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3023 { "bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3024 { "bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3025 { "bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3026 { "bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3027 { "bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3028 { "bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3029 { "bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3030 { "bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3031 { "bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3032 { "bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3033 { "bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3034 { "bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3035 { "bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3036 { "bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3037 { "bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3038 { "bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3039 { "bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3040 { "bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3041 { "bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3042 { "bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3043 { "bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3044 { "bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3045 { "bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3046 { "bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3047 { "bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3048 { "bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3049 { "bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3050 { "bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3051 { "bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3052 { "bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3053 { "bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3054 { "bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3055 { "bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3056 { "bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3057 { "bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3058 { "bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3059 { "bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3060 { "bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3061 { "bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3062 { "bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3063 { "btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, { BI } },
3064 { "btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
3065 { "btctr-", XLO(19,BOTM4,528,0), XLBOBB_MASK, POWER4, { BI } },
3066 { "btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
3067 { "btctr+", XLO(19,BOTP4,528,0), XLBOBB_MASK, POWER4, { BI } },
3068 { "btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, { BI } },
3069 { "btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
3070 { "btctrl-", XLO(19,BOTM4,528,1), XLBOBB_MASK, POWER4, { BI } },
3071 { "btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
3072 { "btctrl+", XLO(19,BOTP4,528,1), XLBOBB_MASK, POWER4, { BI } },
3073 { "bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, { BI } },
3074 { "bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
3075 { "bfctr-", XLO(19,BOFM4,528,0), XLBOBB_MASK, POWER4, { BI } },
3076 { "bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
3077 { "bfctr+", XLO(19,BOFP4,528,0), XLBOBB_MASK, POWER4, { BI } },
3078 { "bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, { BI } },
3079 { "bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
3080 { "bfctrl-", XLO(19,BOFM4,528,1), XLBOBB_MASK, POWER4, { BI } },
3081 { "bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
3082 { "bfctrl+", XLO(19,BOFP4,528,1), XLBOBB_MASK, POWER4, { BI } },
3083 { "bcctr-", XLYLK(19,528,0,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
3084 { "bcctr+", XLYLK(19,528,1,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
3085 { "bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
3086 { "bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
3087 { "bcctr", XLLK(19,528,0), XLBH_MASK, PPCCOM, { BO, BI, BH } },
3088 { "bcctrl", XLLK(19,528,1), XLBH_MASK, PPCCOM, { BO, BI, BH } },
3089 { "bcc", XLLK(19,528,0), XLBB_MASK, PWRCOM, { BO, BI } },
3090 { "bccl", XLLK(19,528,1), XLBB_MASK, PWRCOM, { BO, BI } },
3091 { "bcctre", XLLK(19,529,0), XLYBB_MASK, BOOKE64, { BO, BI } },
3092 { "bcctrel", XLLK(19,529,1), XLYBB_MASK, BOOKE64, { BO, BI } },
3094 { "rlwimi", M(20,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3095 { "rlimi", M(20,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3097 { "rlwimi.", M(20,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3098 { "rlimi.", M(20,1), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3100 { "rotlwi", MME(21,31,0), MMBME_MASK, PPCCOM, { RA, RS, SH } },
3101 { "clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, { RA, RS, MB } },
3102 { "rlwinm", M(21,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3103 { "rlinm", M(21,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3104 { "rotlwi.", MME(21,31,1), MMBME_MASK, PPCCOM, { RA,RS,SH } },
3105 { "clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, { RA, RS, MB } },
3106 { "rlwinm.", M(21,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3107 { "rlinm.", M(21,1), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3109 { "rlmi", M(22,0), M_MASK, M601, { RA,RS,RB,MBE,ME } },
3110 { "rlmi.", M(22,1), M_MASK, M601, { RA,RS,RB,MBE,ME } },
3112 { "be", B(22,0,0), B_MASK, BOOKE64, { LI } },
3113 { "bel", B(22,0,1), B_MASK, BOOKE64, { LI } },
3114 { "bea", B(22,1,0), B_MASK, BOOKE64, { LIA } },
3115 { "bela", B(22,1,1), B_MASK, BOOKE64, { LIA } },
3117 { "rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, { RA, RS, RB } },
3118 { "rlwnm", M(23,0), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } },
3119 { "rlnm", M(23,0), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } },
3120 { "rotlw.", MME(23,31,1), MMBME_MASK, PPCCOM, { RA, RS, RB } },
3121 { "rlwnm.", M(23,1), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } },
3122 { "rlnm.", M(23,1), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } },
3124 { "nop", OP(24), 0xffffffff, PPCCOM, { 0 } },
3125 { "ori", OP(24), OP_MASK, PPCCOM, { RA, RS, UI } },
3126 { "oril", OP(24), OP_MASK, PWRCOM, { RA, RS, UI } },
3128 { "oris", OP(25), OP_MASK, PPCCOM, { RA, RS, UI } },
3129 { "oriu", OP(25), OP_MASK, PWRCOM, { RA, RS, UI } },
3131 { "xori", OP(26), OP_MASK, PPCCOM, { RA, RS, UI } },
3132 { "xoril", OP(26), OP_MASK, PWRCOM, { RA, RS, UI } },
3134 { "xoris", OP(27), OP_MASK, PPCCOM, { RA, RS, UI } },
3135 { "xoriu", OP(27), OP_MASK, PWRCOM, { RA, RS, UI } },
3137 { "andi.", OP(28), OP_MASK, PPCCOM, { RA, RS, UI } },
3138 { "andil.", OP(28), OP_MASK, PWRCOM, { RA, RS, UI } },
3140 { "andis.", OP(29), OP_MASK, PPCCOM, { RA, RS, UI } },
3141 { "andiu.", OP(29), OP_MASK, PWRCOM, { RA, RS, UI } },
3143 { "rotldi", MD(30,0,0), MDMB_MASK, PPC64, { RA, RS, SH6 } },
3144 { "clrldi", MD(30,0,0), MDSH_MASK, PPC64, { RA, RS, MB6 } },
3145 { "rldicl", MD(30,0,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3146 { "rotldi.", MD(30,0,1), MDMB_MASK, PPC64, { RA, RS, SH6 } },
3147 { "clrldi.", MD(30,0,1), MDSH_MASK, PPC64, { RA, RS, MB6 } },
3148 { "rldicl.", MD(30,0,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3150 { "rldicr", MD(30,1,0), MD_MASK, PPC64, { RA, RS, SH6, ME6 } },
3151 { "rldicr.", MD(30,1,1), MD_MASK, PPC64, { RA, RS, SH6, ME6 } },
3153 { "rldic", MD(30,2,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3154 { "rldic.", MD(30,2,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3156 { "rldimi", MD(30,3,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3157 { "rldimi.", MD(30,3,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3159 { "rotld", MDS(30,8,0), MDSMB_MASK, PPC64, { RA, RS, RB } },
3160 { "rldcl", MDS(30,8,0), MDS_MASK, PPC64, { RA, RS, RB, MB6 } },
3161 { "rotld.", MDS(30,8,1), MDSMB_MASK, PPC64, { RA, RS, RB } },
3162 { "rldcl.", MDS(30,8,1), MDS_MASK, PPC64, { RA, RS, RB, MB6 } },
3164 { "rldcr", MDS(30,9,0), MDS_MASK, PPC64, { RA, RS, RB, ME6 } },
3165 { "rldcr.", MDS(30,9,1), MDS_MASK, PPC64, { RA, RS, RB, ME6 } },
3167 { "cmpw", XOPL(31,0,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } },
3168 { "cmpd", XOPL(31,0,1), XCMPL_MASK, PPC64, { OBF, RA, RB } },
3169 { "cmp", X(31,0), XCMP_MASK, PPC, { BF, L, RA, RB } },
3170 { "cmp", X(31,0), XCMPL_MASK, PWRCOM, { BF, RA, RB } },
3172 { "twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, { RA, RB } },
3173 { "tlgt", XTO(31,4,TOLGT), XTO_MASK, PWRCOM, { RA, RB } },
3174 { "twllt", XTO(31,4,TOLLT), XTO_MASK, PPCCOM, { RA, RB } },
3175 { "tllt", XTO(31,4,TOLLT), XTO_MASK, PWRCOM, { RA, RB } },
3176 { "tweq", XTO(31,4,TOEQ), XTO_MASK, PPCCOM, { RA, RB } },
3177 { "teq", XTO(31,4,TOEQ), XTO_MASK, PWRCOM, { RA, RB } },
3178 { "twlge", XTO(31,4,TOLGE), XTO_MASK, PPCCOM, { RA, RB } },
3179 { "tlge", XTO(31,4,TOLGE), XTO_MASK, PWRCOM, { RA, RB } },
3180 { "twlnl", XTO(31,4,TOLNL), XTO_MASK, PPCCOM, { RA, RB } },
3181 { "tlnl", XTO(31,4,TOLNL), XTO_MASK, PWRCOM, { RA, RB } },
3182 { "twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, { RA, RB } },
3183 { "tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, { RA, RB } },
3184 { "twlng", XTO(31,4,TOLNG), XTO_MASK, PPCCOM, { RA, RB } },
3185 { "tlng", XTO(31,4,TOLNG), XTO_MASK, PWRCOM, { RA, RB } },
3186 { "twgt", XTO(31,4,TOGT), XTO_MASK, PPCCOM, { RA, RB } },
3187 { "tgt", XTO(31,4,TOGT), XTO_MASK, PWRCOM, { RA, RB } },
3188 { "twge", XTO(31,4,TOGE), XTO_MASK, PPCCOM, { RA, RB } },
3189 { "tge", XTO(31,4,TOGE), XTO_MASK, PWRCOM, { RA, RB } },
3190 { "twnl", XTO(31,4,TONL), XTO_MASK, PPCCOM, { RA, RB } },
3191 { "tnl", XTO(31,4,TONL), XTO_MASK, PWRCOM, { RA, RB } },
3192 { "twlt", XTO(31,4,TOLT), XTO_MASK, PPCCOM, { RA, RB } },
3193 { "tlt", XTO(31,4,TOLT), XTO_MASK, PWRCOM, { RA, RB } },
3194 { "twle", XTO(31,4,TOLE), XTO_MASK, PPCCOM, { RA, RB } },
3195 { "tle", XTO(31,4,TOLE), XTO_MASK, PWRCOM, { RA, RB } },
3196 { "twng", XTO(31,4,TONG), XTO_MASK, PPCCOM, { RA, RB } },
3197 { "tng", XTO(31,4,TONG), XTO_MASK, PWRCOM, { RA, RB } },
3198 { "twne", XTO(31,4,TONE), XTO_MASK, PPCCOM, { RA, RB } },
3199 { "tne", XTO(31,4,TONE), XTO_MASK, PWRCOM, { RA, RB } },
3200 { "trap", XTO(31,4,TOU), 0xffffffff, PPCCOM, { 0 } },
3201 { "tw", X(31,4), X_MASK, PPCCOM, { TO, RA, RB } },
3202 { "t", X(31,4), X_MASK, PWRCOM, { TO, RA, RB } },
3204 { "subfc", XO(31,8,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3205 { "sf", XO(31,8,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3206 { "subc", XO(31,8,0,0), XO_MASK, PPC, { RT, RB, RA } },
3207 { "subfc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3208 { "sf.", XO(31,8,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3209 { "subc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RB, RA } },
3210 { "subfco", XO(31,8,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3211 { "sfo", XO(31,8,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3212 { "subco", XO(31,8,1,0), XO_MASK, PPC, { RT, RB, RA } },
3213 { "subfco.", XO(31,8,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3214 { "sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3215 { "subco.", XO(31,8,1,1), XO_MASK, PPC, { RT, RB, RA } },
3217 { "mulhdu", XO(31,9,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3218 { "mulhdu.", XO(31,9,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3220 { "addc", XO(31,10,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3221 { "a", XO(31,10,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3222 { "addc.", XO(31,10,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3223 { "a.", XO(31,10,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3224 { "addco", XO(31,10,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3225 { "ao", XO(31,10,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3226 { "addco.", XO(31,10,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3227 { "ao.", XO(31,10,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3229 { "mulhwu", XO(31,11,0,0), XO_MASK, PPC, { RT, RA, RB } },
3230 { "mulhwu.", XO(31,11,0,1), XO_MASK, PPC, { RT, RA, RB } },
3232 { "isellt", X(31,15), X_MASK, PPCISEL, { RT, RA, RB } },
3233 { "iselgt", X(31,47), X_MASK, PPCISEL, { RT, RA, RB } },
3234 { "iseleq", X(31,79), X_MASK, PPCISEL, { RT, RA, RB } },
3235 { "isel", XISEL(31,15), XISEL_MASK, PPCISEL, { RT, RA, RB, CRB } },
3237 { "mfocrf", XFXM(31,19,0,1), XFXFXM_MASK, COM, { RT, FXM } },
3238 { "mfcr", X(31,19), XRARB_MASK, NOPOWER4, { RT } },
3239 { "mfcr", X(31,19), XFXFXM_MASK, POWER4, { RT, FXM4 } },
3241 { "lwarx", X(31,20), X_MASK, PPC, { RT, RA0, RB } },
3243 { "ldx", X(31,21), X_MASK, PPC64, { RT, RA0, RB } },
3245 { "icbt", X(31,22), X_MASK, BOOKE, { CT, RA, RB } },
3246 { "icbt", X(31,262), XRT_MASK, PPC403, { RA, RB } },
3248 { "lwzx", X(31,23), X_MASK, PPCCOM, { RT, RA0, RB } },
3249 { "lx", X(31,23), X_MASK, PWRCOM, { RT, RA, RB } },
3251 { "slw", XRC(31,24,0), X_MASK, PPCCOM, { RA, RS, RB } },
3252 { "sl", XRC(31,24,0), X_MASK, PWRCOM, { RA, RS, RB } },
3253 { "slw.", XRC(31,24,1), X_MASK, PPCCOM, { RA, RS, RB } },
3254 { "sl.", XRC(31,24,1), X_MASK, PWRCOM, { RA, RS, RB } },
3256 { "cntlzw", XRC(31,26,0), XRB_MASK, PPCCOM, { RA, RS } },
3257 { "cntlz", XRC(31,26,0), XRB_MASK, PWRCOM, { RA, RS } },
3258 { "cntlzw.", XRC(31,26,1), XRB_MASK, PPCCOM, { RA, RS } },
3259 { "cntlz.", XRC(31,26,1), XRB_MASK, PWRCOM, { RA, RS } },
3261 { "sld", XRC(31,27,0), X_MASK, PPC64, { RA, RS, RB } },
3262 { "sld.", XRC(31,27,1), X_MASK, PPC64, { RA, RS, RB } },
3264 { "and", XRC(31,28,0), X_MASK, COM, { RA, RS, RB } },
3265 { "and.", XRC(31,28,1), X_MASK, COM, { RA, RS, RB } },
3267 { "maskg", XRC(31,29,0), X_MASK, M601, { RA, RS, RB } },
3268 { "maskg.", XRC(31,29,1), X_MASK, M601, { RA, RS, RB } },
3270 { "icbte", X(31,30), X_MASK, BOOKE64, { CT, RA, RB } },
3272 { "lwzxe", X(31,31), X_MASK, BOOKE64, { RT, RA0, RB } },
3274 { "cmplw", XOPL(31,32,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } },
3275 { "cmpld", XOPL(31,32,1), XCMPL_MASK, PPC64, { OBF, RA, RB } },
3276 { "cmpl", X(31,32), XCMP_MASK, PPC, { BF, L, RA, RB } },
3277 { "cmpl", X(31,32), XCMPL_MASK, PWRCOM, { BF, RA, RB } },
3279 { "subf", XO(31,40,0,0), XO_MASK, PPC, { RT, RA, RB } },
3280 { "sub", XO(31,40,0,0), XO_MASK, PPC, { RT, RB, RA } },
3281 { "subf.", XO(31,40,0,1), XO_MASK, PPC, { RT, RA, RB } },
3282 { "sub.", XO(31,40,0,1), XO_MASK, PPC, { RT, RB, RA } },
3283 { "subfo", XO(31,40,1,0), XO_MASK, PPC, { RT, RA, RB } },
3284 { "subo", XO(31,40,1,0), XO_MASK, PPC, { RT, RB, RA } },
3285 { "subfo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RA, RB } },
3286 { "subo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RB, RA } },
3288 { "ldux", X(31,53), X_MASK, PPC64, { RT, RAL, RB } },
3290 { "dcbst", X(31,54), XRT_MASK, PPC, { RA, RB } },
3292 { "lwzux", X(31,55), X_MASK, PPCCOM, { RT, RAL, RB } },
3293 { "lux", X(31,55), X_MASK, PWRCOM, { RT, RA, RB } },
3295 { "dcbste", X(31,62), XRT_MASK, BOOKE64, { RA, RB } },
3297 { "lwzuxe", X(31,63), X_MASK, BOOKE64, { RT, RAL, RB } },
3299 { "cntlzd", XRC(31,58,0), XRB_MASK, PPC64, { RA, RS } },
3300 { "cntlzd.", XRC(31,58,1), XRB_MASK, PPC64, { RA, RS } },
3302 { "andc", XRC(31,60,0), X_MASK, COM, { RA, RS, RB } },
3303 { "andc.", XRC(31,60,1), X_MASK, COM, { RA, RS, RB } },
3305 { "tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, { RA, RB } },
3306 { "tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC64, { RA, RB } },
3307 { "tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC64, { RA, RB } },
3308 { "tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC64, { RA, RB } },
3309 { "tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC64, { RA, RB } },
3310 { "tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, { RA, RB } },
3311 { "tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC64, { RA, RB } },
3312 { "tdgt", XTO(31,68,TOGT), XTO_MASK, PPC64, { RA, RB } },
3313 { "tdge", XTO(31,68,TOGE), XTO_MASK, PPC64, { RA, RB } },
3314 { "tdnl", XTO(31,68,TONL), XTO_MASK, PPC64, { RA, RB } },
3315 { "tdlt", XTO(31,68,TOLT), XTO_MASK, PPC64, { RA, RB } },
3316 { "tdle", XTO(31,68,TOLE), XTO_MASK, PPC64, { RA, RB } },
3317 { "tdng", XTO(31,68,TONG), XTO_MASK, PPC64, { RA, RB } },
3318 { "tdne", XTO(31,68,TONE), XTO_MASK, PPC64, { RA, RB } },
3319 { "td", X(31,68), X_MASK, PPC64, { TO, RA, RB } },
3321 { "mulhd", XO(31,73,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3322 { "mulhd.", XO(31,73,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3324 { "mulhw", XO(31,75,0,0), XO_MASK, PPC, { RT, RA, RB } },
3325 { "mulhw.", XO(31,75,0,1), XO_MASK, PPC, { RT, RA, RB } },
3327 { "dlmzb", XRC(31,78,0), X_MASK, PPC403|PPC440, { RA, RS, RB } },
3328 { "dlmzb.", XRC(31,78,1), X_MASK, PPC403|PPC440, { RA, RS, RB } },
3330 { "mtsrd", X(31,82), XRB_MASK|(1<<20), PPC64, { SR, RS } },
3332 { "mfmsr", X(31,83), XRARB_MASK, COM, { RT } },
3334 { "ldarx", X(31,84), X_MASK, PPC64, { RT, RA0, RB } },
3336 { "dcbf", X(31,86), XRT_MASK, PPC, { RA, RB } },
3338 { "lbzx", X(31,87), X_MASK, COM, { RT, RA0, RB } },
3340 { "dcbfe", X(31,94), XRT_MASK, BOOKE64, { RA, RB } },
3342 { "lbzxe", X(31,95), X_MASK, BOOKE64, { RT, RA0, RB } },
3344 { "neg", XO(31,104,0,0), XORB_MASK, COM, { RT, RA } },
3345 { "neg.", XO(31,104,0,1), XORB_MASK, COM, { RT, RA } },
3346 { "nego", XO(31,104,1,0), XORB_MASK, COM, { RT, RA } },
3347 { "nego.", XO(31,104,1,1), XORB_MASK, COM, { RT, RA } },
3349 { "mul", XO(31,107,0,0), XO_MASK, M601, { RT, RA, RB } },
3350 { "mul.", XO(31,107,0,1), XO_MASK, M601, { RT, RA, RB } },
3351 { "mulo", XO(31,107,1,0), XO_MASK, M601, { RT, RA, RB } },
3352 { "mulo.", XO(31,107,1,1), XO_MASK, M601, { RT, RA, RB } },
3354 { "mtsrdin", X(31,114), XRA_MASK, PPC64, { RS, RB } },
3356 { "clf", X(31,118), XTO_MASK, POWER, { RA, RB } },
3358 { "lbzux", X(31,119), X_MASK, COM, { RT, RAL, RB } },
3360 { "not", XRC(31,124,0), X_MASK, COM, { RA, RS, RBS } },
3361 { "nor", XRC(31,124,0), X_MASK, COM, { RA, RS, RB } },
3362 { "not.", XRC(31,124,1), X_MASK, COM, { RA, RS, RBS } },
3363 { "nor.", XRC(31,124,1), X_MASK, COM, { RA, RS, RB } },
3365 { "lwarxe", X(31,126), X_MASK, BOOKE64, { RT, RA0, RB } },
3367 { "lbzuxe", X(31,127), X_MASK, BOOKE64, { RT, RAL, RB } },
3369 { "wrtee", X(31,131), XRARB_MASK, PPC403 | BOOKE, { RS } },
3371 { "dcbtstls",X(31,134), X_MASK, PPCCHLK, { CT, RA, RB }},
3373 { "subfe", XO(31,136,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3374 { "sfe", XO(31,136,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3375 { "subfe.", XO(31,136,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3376 { "sfe.", XO(31,136,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3377 { "subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3378 { "sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3379 { "subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3380 { "sfeo.", XO(31,136,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3382 { "adde", XO(31,138,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3383 { "ae", XO(31,138,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3384 { "adde.", XO(31,138,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3385 { "ae.", XO(31,138,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3386 { "addeo", XO(31,138,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3387 { "aeo", XO(31,138,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3388 { "addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3389 { "aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3391 { "dcbtstlse",X(31,142),X_MASK, PPCCHLK64, { CT, RA, RB }},
3393 { "mtocrf", XFXM(31,144,0,1), XFXFXM_MASK, COM, { FXM, RS } },
3394 { "mtcr", XFXM(31,144,0xff,0), XRARB_MASK, COM, { RS }},
3395 { "mtcrf", X(31,144), XFXFXM_MASK, COM, { FXM, RS } },
3397 { "mtmsr", X(31,146), XRARB_MASK, COM, { RS } },
3399 { "stdx", X(31,149), X_MASK, PPC64, { RS, RA0, RB } },
3401 { "stwcx.", XRC(31,150,1), X_MASK, PPC, { RS, RA0, RB } },
3403 { "stwx", X(31,151), X_MASK, PPCCOM, { RS, RA0, RB } },
3404 { "stx", X(31,151), X_MASK, PWRCOM, { RS, RA, RB } },
3406 { "stwcxe.", XRC(31,158,1), X_MASK, BOOKE64, { RS, RA0, RB } },
3408 { "stwxe", X(31,159), X_MASK, BOOKE64, { RS, RA0, RB } },
3410 { "slq", XRC(31,152,0), X_MASK, M601, { RA, RS, RB } },
3411 { "slq.", XRC(31,152,1), X_MASK, M601, { RA, RS, RB } },
3413 { "sle", XRC(31,153,0), X_MASK, M601, { RA, RS, RB } },
3414 { "sle.", XRC(31,153,1), X_MASK, M601, { RA, RS, RB } },
3416 { "wrteei", X(31,163), XE_MASK, PPC403 | BOOKE, { E } },
3418 { "dcbtls", X(31,166), X_MASK, PPCCHLK, { CT, RA, RB }},
3419 { "dcbtlse", X(31,174), X_MASK, PPCCHLK64, { CT, RA, RB }},
3421 { "mtmsrd", X(31,178), XRLARB_MASK, PPC64, { RS, MTMSRD_L } },
3423 { "stdux", X(31,181), X_MASK, PPC64, { RS, RAS, RB } },
3425 { "stwux", X(31,183), X_MASK, PPCCOM, { RS, RAS, RB } },
3426 { "stux", X(31,183), X_MASK, PWRCOM, { RS, RA0, RB } },
3428 { "sliq", XRC(31,184,0), X_MASK, M601, { RA, RS, SH } },
3429 { "sliq.", XRC(31,184,1), X_MASK, M601, { RA, RS, SH } },
3431 { "stwuxe", X(31,191), X_MASK, BOOKE64, { RS, RAS, RB } },
3433 { "subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3434 { "sfze", XO(31,200,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3435 { "subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3436 { "sfze.", XO(31,200,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3437 { "subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3438 { "sfzeo", XO(31,200,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3439 { "subfzeo.",XO(31,200,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3440 { "sfzeo.", XO(31,200,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3442 { "addze", XO(31,202,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3443 { "aze", XO(31,202,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3444 { "addze.", XO(31,202,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3445 { "aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3446 { "addzeo", XO(31,202,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3447 { "azeo", XO(31,202,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3448 { "addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3449 { "azeo.", XO(31,202,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3451 { "mtsr", X(31,210), XRB_MASK|(1<<20), COM32, { SR, RS } },
3453 { "stdcx.", XRC(31,214,1), X_MASK, PPC64, { RS, RA0, RB } },
3455 { "stbx", X(31,215), X_MASK, COM, { RS, RA0, RB } },
3457 { "sllq", XRC(31,216,0), X_MASK, M601, { RA, RS, RB } },
3458 { "sllq.", XRC(31,216,1), X_MASK, M601, { RA, RS, RB } },
3460 { "sleq", XRC(31,217,0), X_MASK, M601, { RA, RS, RB } },
3461 { "sleq.", XRC(31,217,1), X_MASK, M601, { RA, RS, RB } },
3463 { "stbxe", X(31,223), X_MASK, BOOKE64, { RS, RA0, RB } },
3465 { "icblc", X(31,230), X_MASK, PPCCHLK, { CT, RA, RB }},
3467 { "subfme", XO(31,232,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3468 { "sfme", XO(31,232,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3469 { "subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3470 { "sfme.", XO(31,232,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3471 { "subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3472 { "sfmeo", XO(31,232,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3473 { "subfmeo.",XO(31,232,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3474 { "sfmeo.", XO(31,232,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3476 { "mulld", XO(31,233,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3477 { "mulld.", XO(31,233,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3478 { "mulldo", XO(31,233,1,0), XO_MASK, PPC64, { RT, RA, RB } },
3479 { "mulldo.", XO(31,233,1,1), XO_MASK, PPC64, { RT, RA, RB } },
3481 { "addme", XO(31,234,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3482 { "ame", XO(31,234,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3483 { "addme.", XO(31,234,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3484 { "ame.", XO(31,234,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3485 { "addmeo", XO(31,234,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3486 { "ameo", XO(31,234,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3487 { "addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3488 { "ameo.", XO(31,234,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3490 { "mullw", XO(31,235,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3491 { "muls", XO(31,235,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3492 { "mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3493 { "muls.", XO(31,235,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3494 { "mullwo", XO(31,235,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3495 { "mulso", XO(31,235,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3496 { "mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3497 { "mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3499 { "icblce", X(31,238), X_MASK, PPCCHLK64, { CT, RA, RB }},
3500 { "mtsrin", X(31,242), XRA_MASK, PPC32, { RS, RB } },
3501 { "mtsri", X(31,242), XRA_MASK, POWER32, { RS, RB } },
3503 { "dcbtst", X(31,246), X_MASK, PPC, { CT, RA, RB } },
3505 { "stbux", X(31,247), X_MASK, COM, { RS, RAS, RB } },
3507 { "slliq", XRC(31,248,0), X_MASK, M601, { RA, RS, SH } },
3508 { "slliq.", XRC(31,248,1), X_MASK, M601, { RA, RS, SH } },
3510 { "dcbtste", X(31,253), X_MASK, BOOKE64, { CT, RA, RB } },
3512 { "stbuxe", X(31,255), X_MASK, BOOKE64, { RS, RAS, RB } },
3514 { "mfdcrx", X(31,259), X_MASK, BOOKE, { RS, RA } },
3516 { "doz", XO(31,264,0,0), XO_MASK, M601, { RT, RA, RB } },
3517 { "doz.", XO(31,264,0,1), XO_MASK, M601, { RT, RA, RB } },
3518 { "dozo", XO(31,264,1,0), XO_MASK, M601, { RT, RA, RB } },
3519 { "dozo.", XO(31,264,1,1), XO_MASK, M601, { RT, RA, RB } },
3521 { "add", XO(31,266,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3522 { "cax", XO(31,266,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3523 { "add.", XO(31,266,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3524 { "cax.", XO(31,266,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3525 { "addo", XO(31,266,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3526 { "caxo", XO(31,266,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3527 { "addo.", XO(31,266,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3528 { "caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3530 { "tlbiel", X(31,274), XRTRA_MASK, POWER4, { RB } },
3532 { "mfapidi", X(31,275), X_MASK, BOOKE, { RT, RA } },
3534 { "lscbx", XRC(31,277,0), X_MASK, M601, { RT, RA, RB } },
3535 { "lscbx.", XRC(31,277,1), X_MASK, M601, { RT, RA, RB } },
3537 { "dcbt", X(31,278), X_MASK, PPC, { CT, RA, RB } },
3539 { "lhzx", X(31,279), X_MASK, COM, { RT, RA0, RB } },
3541 { "eqv", XRC(31,284,0), X_MASK, COM, { RA, RS, RB } },
3542 { "eqv.", XRC(31,284,1), X_MASK, COM, { RA, RS, RB } },
3544 { "dcbte", X(31,286), X_MASK, BOOKE64, { CT, RA, RB } },
3546 { "lhzxe", X(31,287), X_MASK, BOOKE64, { RT, RA0, RB } },
3548 { "tlbie", X(31,306), XRTLRA_MASK, PPC, { RB, L } },
3549 { "tlbi", X(31,306), XRT_MASK, POWER, { RA0, RB } },
3551 { "eciwx", X(31,310), X_MASK, PPC, { RT, RA, RB } },
3553 { "lhzux", X(31,311), X_MASK, COM, { RT, RAL, RB } },
3555 { "xor", XRC(31,316,0), X_MASK, COM, { RA, RS, RB } },
3556 { "xor.", XRC(31,316,1), X_MASK, COM, { RA, RS, RB } },
3558 { "lhzuxe", X(31,319), X_MASK, BOOKE64, { RT, RAL, RB } },
3560 { "mfexisr", XSPR(31,323,64), XSPR_MASK, PPC403, { RT } },
3561 { "mfexier", XSPR(31,323,66), XSPR_MASK, PPC403, { RT } },
3562 { "mfbr0", XSPR(31,323,128), XSPR_MASK, PPC403, { RT } },
3563 { "mfbr1", XSPR(31,323,129), XSPR_MASK, PPC403, { RT } },
3564 { "mfbr2", XSPR(31,323,130), XSPR_MASK, PPC403, { RT } },
3565 { "mfbr3", XSPR(31,323,131), XSPR_MASK, PPC403, { RT } },
3566 { "mfbr4", XSPR(31,323,132), XSPR_MASK, PPC403, { RT } },
3567 { "mfbr5", XSPR(31,323,133), XSPR_MASK, PPC403, { RT } },
3568 { "mfbr6", XSPR(31,323,134), XSPR_MASK, PPC403, { RT } },
3569 { "mfbr7", XSPR(31,323,135), XSPR_MASK, PPC403, { RT } },
3570 { "mfbear", XSPR(31,323,144), XSPR_MASK, PPC403, { RT } },
3571 { "mfbesr", XSPR(31,323,145), XSPR_MASK, PPC403, { RT } },
3572 { "mfiocr", XSPR(31,323,160), XSPR_MASK, PPC403, { RT } },
3573 { "mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403, { RT } },
3574 { "mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403, { RT } },
3575 { "mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403, { RT } },
3576 { "mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403, { RT } },
3577 { "mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403, { RT } },
3578 { "mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403, { RT } },
3579 { "mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403, { RT } },
3580 { "mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403, { RT } },
3581 { "mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403, { RT } },
3582 { "mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403, { RT } },
3583 { "mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403, { RT } },
3584 { "mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403, { RT } },
3585 { "mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403, { RT } },
3586 { "mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403, { RT } },
3587 { "mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403, { RT } },
3588 { "mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403, { RT } },
3589 { "mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403, { RT } },
3590 { "mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403, { RT } },
3591 { "mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403, { RT } },
3592 { "mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, { RT } },
3593 { "mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, { RT } },
3594 { "mfdcr", X(31,323), X_MASK, PPC403 | BOOKE, { RT, SPR } },
3596 { "div", XO(31,331,0,0), XO_MASK, M601, { RT, RA, RB } },
3597 { "div.", XO(31,331,0,1), XO_MASK, M601, { RT, RA, RB } },
3598 { "divo", XO(31,331,1,0), XO_MASK, M601, { RT, RA, RB } },
3599 { "divo.", XO(31,331,1,1), XO_MASK, M601, { RT, RA, RB } },
3601 { "mfpmr", X(31,334), X_MASK, PPCPMR, { RT, PMR }},
3603 { "mfmq", XSPR(31,339,0), XSPR_MASK, M601, { RT } },
3604 { "mfxer", XSPR(31,339,1), XSPR_MASK, COM, { RT } },
3605 { "mfrtcu", XSPR(31,339,4), XSPR_MASK, COM, { RT } },
3606 { "mfrtcl", XSPR(31,339,5), XSPR_MASK, COM, { RT } },
3607 { "mfdec", XSPR(31,339,6), XSPR_MASK, MFDEC1, { RT } },
3608 { "mfdec", XSPR(31,339,22), XSPR_MASK, MFDEC2, { RT } },
3609 { "mflr", XSPR(31,339,8), XSPR_MASK, COM, { RT } },
3610 { "mfctr", XSPR(31,339,9), XSPR_MASK, COM, { RT } },
3611 { "mftid", XSPR(31,339,17), XSPR_MASK, POWER, { RT } },
3612 { "mfdsisr", XSPR(31,339,18), XSPR_MASK, COM, { RT } },
3613 { "mfdar", XSPR(31,339,19), XSPR_MASK, COM, { RT } },
3614 { "mfsdr0", XSPR(31,339,24), XSPR_MASK, POWER, { RT } },
3615 { "mfsdr1", XSPR(31,339,25), XSPR_MASK, COM, { RT } },
3616 { "mfsrr0", XSPR(31,339,26), XSPR_MASK, COM, { RT } },
3617 { "mfsrr1", XSPR(31,339,27), XSPR_MASK, COM, { RT } },
3618 { "mfpid", XSPR(31,339,48), XSPR_MASK, BOOKE, { RT } },
3619 { "mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, { RT } },
3620 { "mfcsrr0", XSPR(31,339,58), XSPR_MASK, BOOKE, { RT } },
3621 { "mfcsrr1", XSPR(31,339,59), XSPR_MASK, BOOKE, { RT } },
3622 { "mfdear", XSPR(31,339,61), XSPR_MASK, BOOKE, { RT } },
3623 { "mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, { RT } },
3624 { "mfesr", XSPR(31,339,62), XSPR_MASK, BOOKE, { RT } },
3625 { "mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, { RT } },
3626 { "mfivpr", XSPR(31,339,63), XSPR_MASK, BOOKE, { RT } },
3627 { "mfcmpa", XSPR(31,339,144), XSPR_MASK, PPC860, { RT } },
3628 { "mfcmpb", XSPR(31,339,145), XSPR_MASK, PPC860, { RT } },
3629 { "mfcmpc", XSPR(31,339,146), XSPR_MASK, PPC860, { RT } },
3630 { "mfcmpd", XSPR(31,339,147), XSPR_MASK, PPC860, { RT } },
3631 { "mficr", XSPR(31,339,148), XSPR_MASK, PPC860, { RT } },
3632 { "mfder", XSPR(31,339,149), XSPR_MASK, PPC860, { RT } },
3633 { "mfcounta", XSPR(31,339,150), XSPR_MASK, PPC860, { RT } },
3634 { "mfcountb", XSPR(31,339,151), XSPR_MASK, PPC860, { RT } },
3635 { "mfcmpe", XSPR(31,339,152), XSPR_MASK, PPC860, { RT } },
3636 { "mfcmpf", XSPR(31,339,153), XSPR_MASK, PPC860, { RT } },
3637 { "mfcmpg", XSPR(31,339,154), XSPR_MASK, PPC860, { RT } },
3638 { "mfcmph", XSPR(31,339,155), XSPR_MASK, PPC860, { RT } },
3639 { "mflctrl1", XSPR(31,339,156), XSPR_MASK, PPC860, { RT } },
3640 { "mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860, { RT } },
3641 { "mfictrl", XSPR(31,339,158), XSPR_MASK, PPC860, { RT } },
3642 { "mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, { RT } },
3643 { "mfvrsave", XSPR(31,339,256), XSPR_MASK, PPCVEC, { RT } },
3644 { "mfusprg0", XSPR(31,339,256), XSPR_MASK, BOOKE, { RT } },
3645 { "mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405, { RT } },
3646 { "mfsprg4", XSPR(31,339,260), XSPR_MASK, BOOKE, { RT } },
3647 { "mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405, { RT } },
3648 { "mfsprg5", XSPR(31,339,261), XSPR_MASK, BOOKE, { RT } },
3649 { "mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405, { RT } },
3650 { "mfsprg6", XSPR(31,339,262), XSPR_MASK, BOOKE, { RT } },
3651 { "mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405, { RT } },
3652 { "mfsprg7", XSPR(31,339,263), XSPR_MASK, BOOKE, { RT } },
3653 { "mftb", X(31,371), X_MASK, CLASSIC, { RT, TBR } },
3654 { "mftb", XSPR(31,339,268), XSPR_MASK, BOOKE, { RT } },
3655 { "mftbl", XSPR(31,371,268), XSPR_MASK, CLASSIC, { RT } },
3656 { "mftbl", XSPR(31,339,268), XSPR_MASK, BOOKE, { RT } },
3657 { "mftbu", XSPR(31,371,269), XSPR_MASK, CLASSIC, { RT } },
3658 { "mftbu", XSPR(31,339,269), XSPR_MASK, BOOKE, { RT } },
3659 { "mfsprg", XSPR(31,339,272), XSPRG_MASK, PPC, { RT, SPRG } },
3660 { "mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, { RT } },
3661 { "mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC, { RT } },
3662 { "mfsprg2", XSPR(31,339,274), XSPR_MASK, PPC, { RT } },
3663 { "mfsprg3", XSPR(31,339,275), XSPR_MASK, PPC, { RT } },
3664 { "mfasr", XSPR(31,339,280), XSPR_MASK, PPC64, { RT } },
3665 { "mfear", XSPR(31,339,282), XSPR_MASK, PPC, { RT } },
3666 { "mfpir", XSPR(31,339,286), XSPR_MASK, BOOKE, { RT } },
3667 { "mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, { RT } },
3668 { "mfdbsr", XSPR(31,339,304), XSPR_MASK, BOOKE, { RT } },
3669 { "mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, { RT } },
3670 { "mfdbcr0", XSPR(31,339,308), XSPR_MASK, BOOKE, { RT } },
3671 { "mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405, { RT } },
3672 { "mfdbcr1", XSPR(31,339,309), XSPR_MASK, BOOKE, { RT } },
3673 { "mfdbcr1", XSPR(31,339,957), XSPR_MASK, PPC405, { RT } },
3674 { "mfdbcr2", XSPR(31,339,310), XSPR_MASK, BOOKE, { RT } },
3675 { "mfiac1", XSPR(31,339,312), XSPR_MASK, BOOKE, { RT } },
3676 { "mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, { RT } },
3677 { "mfiac2", XSPR(31,339,313), XSPR_MASK, BOOKE, { RT } },
3678 { "mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, { RT } },
3679 { "mfiac3", XSPR(31,339,314), XSPR_MASK, BOOKE, { RT } },
3680 { "mfiac3", XSPR(31,339,948), XSPR_MASK, PPC405, { RT } },
3681 { "mfiac4", XSPR(31,339,315), XSPR_MASK, BOOKE, { RT } },
3682 { "mfiac4", XSPR(31,339,949), XSPR_MASK, PPC405, { RT } },
3683 { "mfdac1", XSPR(31,339,316), XSPR_MASK, BOOKE, { RT } },
3684 { "mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, { RT } },
3685 { "mfdac2", XSPR(31,339,317), XSPR_MASK, BOOKE, { RT } },
3686 { "mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, { RT } },
3687 { "mfdvc1", XSPR(31,339,318), XSPR_MASK, BOOKE, { RT } },
3688 { "mfdvc1", XSPR(31,339,950), XSPR_MASK, PPC405, { RT } },
3689 { "mfdvc2", XSPR(31,339,319), XSPR_MASK, BOOKE, { RT } },
3690 { "mfdvc2", XSPR(31,339,951), XSPR_MASK, PPC405, { RT } },
3691 { "mftsr", XSPR(31,339,336), XSPR_MASK, BOOKE, { RT } },
3692 { "mftsr", XSPR(31,339,984), XSPR_MASK, PPC403, { RT } },
3693 { "mftcr", XSPR(31,339,340), XSPR_MASK, BOOKE, { RT } },
3694 { "mftcr", XSPR(31,339,986), XSPR_MASK, PPC403, { RT } },
3695 { "mfivor0", XSPR(31,339,400), XSPR_MASK, BOOKE, { RT } },
3696 { "mfivor1", XSPR(31,339,401), XSPR_MASK, BOOKE, { RT } },
3697 { "mfivor2", XSPR(31,339,402), XSPR_MASK, BOOKE, { RT } },
3698 { "mfivor3", XSPR(31,339,403), XSPR_MASK, BOOKE, { RT } },
3699 { "mfivor4", XSPR(31,339,404), XSPR_MASK, BOOKE, { RT } },
3700 { "mfivor5", XSPR(31,339,405), XSPR_MASK, BOOKE, { RT } },
3701 { "mfivor6", XSPR(31,339,406), XSPR_MASK, BOOKE, { RT } },
3702 { "mfivor7", XSPR(31,339,407), XSPR_MASK, BOOKE, { RT } },
3703 { "mfivor8", XSPR(31,339,408), XSPR_MASK, BOOKE, { RT } },
3704 { "mfivor9", XSPR(31,339,409), XSPR_MASK, BOOKE, { RT } },
3705 { "mfivor10", XSPR(31,339,410), XSPR_MASK, BOOKE, { RT } },
3706 { "mfivor11", XSPR(31,339,411), XSPR_MASK, BOOKE, { RT } },
3707 { "mfivor12", XSPR(31,339,412), XSPR_MASK, BOOKE, { RT } },
3708 { "mfivor13", XSPR(31,339,413), XSPR_MASK, BOOKE, { RT } },
3709 { "mfivor14", XSPR(31,339,414), XSPR_MASK, BOOKE, { RT } },
3710 { "mfivor15", XSPR(31,339,415), XSPR_MASK, BOOKE, { RT } },
3711 { "mfspefscr", XSPR(31,339,512), XSPR_MASK, PPCSPE, { RT } },
3712 { "mfbbear", XSPR(31,339,513), XSPR_MASK, PPCBRLK, { RT } },
3713 { "mfbbtar", XSPR(31,339,514), XSPR_MASK, PPCBRLK, { RT } },
3714 { "mfivor32", XSPR(31,339,528), XSPR_MASK, PPCSPE, { RT } },
3715 { "mfivor33", XSPR(31,339,529), XSPR_MASK, PPCSPE, { RT } },
3716 { "mfivor34", XSPR(31,339,530), XSPR_MASK, PPCSPE, { RT } },
3717 { "mfivor35", XSPR(31,339,531), XSPR_MASK, PPCPMR, { RT } },
3718 { "mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3719 { "mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3720 { "mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3721 { "mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3722 { "mfic_cst", XSPR(31,339,560), XSPR_MASK, PPC860, { RT } },
3723 { "mfic_adr", XSPR(31,339,561), XSPR_MASK, PPC860, { RT } },
3724 { "mfic_dat", XSPR(31,339,562), XSPR_MASK, PPC860, { RT } },
3725 { "mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860, { RT } },
3726 { "mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860, { RT } },
3727 { "mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, { RT } },
3728 { "mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860, { RT } },
3729 { "mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, { RT } },
3730 { "mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, { RT } },
3731 { "mfmcar", XSPR(31,339,573), XSPR_MASK, PPCRFMCI, { RT } },
3732 { "mfdpdr", XSPR(31,339,630), XSPR_MASK, PPC860, { RT } },
3733 { "mfdpir", XSPR(31,339,631), XSPR_MASK, PPC860, { RT } },
3734 { "mfimmr", XSPR(31,339,638), XSPR_MASK, PPC860, { RT } },
3735 { "mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860, { RT } },
3736 { "mfmi_ap", XSPR(31,339,786), XSPR_MASK, PPC860, { RT } },
3737 { "mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860, { RT } },
3738 { "mfmi_twc", XSPR(31,339,789), XSPR_MASK, PPC860, { RT } },
3739 { "mfmi_rpn", XSPR(31,339,790), XSPR_MASK, PPC860, { RT } },
3740 { "mfmd_ctr", XSPR(31,339,792), XSPR_MASK, PPC860, { RT } },
3741 { "mfm_casid", XSPR(31,339,793), XSPR_MASK, PPC860, { RT } },
3742 { "mfmd_ap", XSPR(31,339,794), XSPR_MASK, PPC860, { RT } },
3743 { "mfmd_epn", XSPR(31,339,795), XSPR_MASK, PPC860, { RT } },
3744 { "mfmd_twb", XSPR(31,339,796), XSPR_MASK, PPC860, { RT } },
3745 { "mfmd_twc", XSPR(31,339,797), XSPR_MASK, PPC860, { RT } },
3746 { "mfmd_rpn", XSPR(31,339,798), XSPR_MASK, PPC860, { RT } },
3747 { "mfm_tw", XSPR(31,339,799), XSPR_MASK, PPC860, { RT } },
3748 { "mfmi_dbcam", XSPR(31,339,816), XSPR_MASK, PPC860, { RT } },
3749 { "mfmi_dbram0",XSPR(31,339,817), XSPR_MASK, PPC860, { RT } },
3750 { "mfmi_dbram1",XSPR(31,339,818), XSPR_MASK, PPC860, { RT } },
3751 { "mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860, { RT } },
3752 { "mfmd_dbram0",XSPR(31,339,825), XSPR_MASK, PPC860, { RT } },
3753 { "mfmd_dbram1",XSPR(31,339,826), XSPR_MASK, PPC860, { RT } },
3754 { "mfummcr0", XSPR(31,339,936), XSPR_MASK, PPC750, { RT } },
3755 { "mfupmc1", XSPR(31,339,937), XSPR_MASK, PPC750, { RT } },
3756 { "mfupmc2", XSPR(31,339,938), XSPR_MASK, PPC750, { RT } },
3757 { "mfusia", XSPR(31,339,939), XSPR_MASK, PPC750, { RT } },
3758 { "mfummcr1", XSPR(31,339,940), XSPR_MASK, PPC750, { RT } },
3759 { "mfupmc3", XSPR(31,339,941), XSPR_MASK, PPC750, { RT } },
3760 { "mfupmc4", XSPR(31,339,942), XSPR_MASK, PPC750, { RT } },
3761 { "mfzpr", XSPR(31,339,944), XSPR_MASK, PPC403, { RT } },
3762 { "mfccr0", XSPR(31,339,947), XSPR_MASK, PPC405, { RT } },
3763 { "mfmmcr0", XSPR(31,339,952), XSPR_MASK, PPC750, { RT } },
3764 { "mfpmc1", XSPR(31,339,953), XSPR_MASK, PPC750, { RT } },
3765 { "mfsgr", XSPR(31,339,953), XSPR_MASK, PPC403, { RT } },
3766 { "mfpmc2", XSPR(31,339,954), XSPR_MASK, PPC750, { RT } },
3767 { "mfdcwr", XSPR(31,339,954), XSPR_MASK, PPC403, { RT } },
3768 { "mfsia", XSPR(31,339,955), XSPR_MASK, PPC750, { RT } },
3769 { "mfsler", XSPR(31,339,955), XSPR_MASK, PPC405, { RT } },
3770 { "mfmmcr1", XSPR(31,339,956), XSPR_MASK, PPC750, { RT } },
3771 { "mfsu0r", XSPR(31,339,956), XSPR_MASK, PPC405, { RT } },
3772 { "mfpmc3", XSPR(31,339,957), XSPR_MASK, PPC750, { RT } },
3773 { "mfpmc4", XSPR(31,339,958), XSPR_MASK, PPC750, { RT } },
3774 { "mficdbdr", XSPR(31,339,979), XSPR_MASK, PPC403, { RT } },
3775 { "mfevpr", XSPR(31,339,982), XSPR_MASK, PPC403, { RT } },
3776 { "mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403, { RT } },
3777 { "mfpit", XSPR(31,339,987), XSPR_MASK, PPC403, { RT } },
3778 { "mftbhi", XSPR(31,339,988), XSPR_MASK, PPC403, { RT } },
3779 { "mftblo", XSPR(31,339,989), XSPR_MASK, PPC403, { RT } },
3780 { "mfsrr2", XSPR(31,339,990), XSPR_MASK, PPC403, { RT } },
3781 { "mfsrr3", XSPR(31,339,991), XSPR_MASK, PPC403, { RT } },
3782 { "mfl2cr", XSPR(31,339,1017), XSPR_MASK, PPC750, { RT } },
3783 { "mfdccr", XSPR(31,339,1018), XSPR_MASK, PPC403, { RT } },
3784 { "mficcr", XSPR(31,339,1019), XSPR_MASK, PPC403, { RT } },
3785 { "mfictc", XSPR(31,339,1019), XSPR_MASK, PPC750, { RT } },
3786 { "mfpbl1", XSPR(31,339,1020), XSPR_MASK, PPC403, { RT } },
3787 { "mfthrm1", XSPR(31,339,1020), XSPR_MASK, PPC750, { RT } },
3788 { "mfpbu1", XSPR(31,339,1021), XSPR_MASK, PPC403, { RT } },
3789 { "mfthrm2", XSPR(31,339,1021), XSPR_MASK, PPC750, { RT } },
3790 { "mfpbl2", XSPR(31,339,1022), XSPR_MASK, PPC403, { RT } },
3791 { "mfthrm3", XSPR(31,339,1022), XSPR_MASK, PPC750, { RT } },
3792 { "mfpbu2", XSPR(31,339,1023), XSPR_MASK, PPC403, { RT } },
3793 { "mfspr", X(31,339), X_MASK, COM, { RT, SPR } },
3795 { "lwax", X(31,341), X_MASK, PPC64, { RT, RA0, RB } },
3797 { "dst", XDSS(31,342,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3798 { "dstt", XDSS(31,342,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3800 { "lhax", X(31,343), X_MASK, COM, { RT, RA0, RB } },
3802 { "lhaxe", X(31,351), X_MASK, BOOKE64, { RT, RA0, RB } },
3804 { "dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3805 { "dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3807 { "dccci", X(31,454), XRT_MASK, PPC403|PPC440, { RA, RB } },
3809 { "abs", XO(31,360,0,0), XORB_MASK, M601, { RT, RA } },
3810 { "abs.", XO(31,360,0,1), XORB_MASK, M601, { RT, RA } },
3811 { "abso", XO(31,360,1,0), XORB_MASK, M601, { RT, RA } },
3812 { "abso.", XO(31,360,1,1), XORB_MASK, M601, { RT, RA } },
3814 { "divs", XO(31,363,0,0), XO_MASK, M601, { RT, RA, RB } },
3815 { "divs.", XO(31,363,0,1), XO_MASK, M601, { RT, RA, RB } },
3816 { "divso", XO(31,363,1,0), XO_MASK, M601, { RT, RA, RB } },
3817 { "divso.", XO(31,363,1,1), XO_MASK, M601, { RT, RA, RB } },
3819 { "tlbia", X(31,370), 0xffffffff, PPC, { 0 } },
3821 { "lwaux", X(31,373), X_MASK, PPC64, { RT, RAL, RB } },
3823 { "lhaux", X(31,375), X_MASK, COM, { RT, RAL, RB } },
3825 { "lhauxe", X(31,383), X_MASK, BOOKE64, { RT, RAL, RB } },
3827 { "mtdcrx", X(31,387), X_MASK, BOOKE, { RA, RS } },
3829 { "dcblc", X(31,390), X_MASK, PPCCHLK, { CT, RA, RB }},
3831 { "subfe64", XO(31,392,0,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3832 { "subfe64o",XO(31,392,1,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3834 { "adde64", XO(31,394,0,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3835 { "adde64o", XO(31,394,1,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3837 { "dcblce", X(31,398), X_MASK, PPCCHLK64, { CT, RA, RB }},
3839 { "slbmte", X(31,402), XRA_MASK, PPC64, { RS, RB } },
3841 { "sthx", X(31,407), X_MASK, COM, { RS, RA0, RB } },
3843 { "lfqx", X(31,791), X_MASK, POWER2, { FRT, RA, RB } },
3845 { "lfqux", X(31,823), X_MASK, POWER2, { FRT, RA, RB } },
3847 { "stfqx", X(31,919), X_MASK, POWER2, { FRS, RA, RB } },
3849 { "stfqux", X(31,951), X_MASK, POWER2, { FRS, RA, RB } },
3851 { "orc", XRC(31,412,0), X_MASK, COM, { RA, RS, RB } },
3852 { "orc.", XRC(31,412,1), X_MASK, COM, { RA, RS, RB } },
3854 { "sradi", XS(31,413,0), XS_MASK, PPC64, { RA, RS, SH6 } },
3855 { "sradi.", XS(31,413,1), XS_MASK, PPC64, { RA, RS, SH6 } },
3857 { "sthxe", X(31,415), X_MASK, BOOKE64, { RS, RA0, RB } },
3859 { "slbie", X(31,434), XRTRA_MASK, PPC64, { RB } },
3861 { "ecowx", X(31,438), X_MASK, PPC, { RT, RA, RB } },
3863 { "sthux", X(31,439), X_MASK, COM, { RS, RAS, RB } },
3865 { "sthuxe", X(31,447), X_MASK, BOOKE64, { RS, RAS, RB } },
3867 { "mr", XRC(31,444,0), X_MASK, COM, { RA, RS, RBS } },
3868 { "or", XRC(31,444,0), X_MASK, COM, { RA, RS, RB } },
3869 { "mr.", XRC(31,444,1), X_MASK, COM, { RA, RS, RBS } },
3870 { "or.", XRC(31,444,1), X_MASK, COM, { RA, RS, RB } },
3872 { "mtexisr", XSPR(31,451,64), XSPR_MASK, PPC403, { RS } },
3873 { "mtexier", XSPR(31,451,66), XSPR_MASK, PPC403, { RS } },
3874 { "mtbr0", XSPR(31,451,128), XSPR_MASK, PPC403, { RS } },
3875 { "mtbr1", XSPR(31,451,129), XSPR_MASK, PPC403, { RS } },
3876 { "mtbr2", XSPR(31,451,130), XSPR_MASK, PPC403, { RS } },
3877 { "mtbr3", XSPR(31,451,131), XSPR_MASK, PPC403, { RS } },
3878 { "mtbr4", XSPR(31,451,132), XSPR_MASK, PPC403, { RS } },
3879 { "mtbr5", XSPR(31,451,133), XSPR_MASK, PPC403, { RS } },
3880 { "mtbr6", XSPR(31,451,134), XSPR_MASK, PPC403, { RS } },
3881 { "mtbr7", XSPR(31,451,135), XSPR_MASK, PPC403, { RS } },
3882 { "mtbear", XSPR(31,451,144), XSPR_MASK, PPC403, { RS } },
3883 { "mtbesr", XSPR(31,451,145), XSPR_MASK, PPC403, { RS } },
3884 { "mtiocr", XSPR(31,451,160), XSPR_MASK, PPC403, { RS } },
3885 { "mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403, { RS } },
3886 { "mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403, { RS } },
3887 { "mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403, { RS } },
3888 { "mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403, { RS } },
3889 { "mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403, { RS } },
3890 { "mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403, { RS } },
3891 { "mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403, { RS } },
3892 { "mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403, { RS } },
3893 { "mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403, { RS } },
3894 { "mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403, { RS } },
3895 { "mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403, { RS } },
3896 { "mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403, { RS } },
3897 { "mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403, { RS } },
3898 { "mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403, { RS } },
3899 { "mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403, { RS } },
3900 { "mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403, { RS } },
3901 { "mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403, { RS } },
3902 { "mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403, { RS } },
3903 { "mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, { RS } },
3904 { "mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, { RS } },
3905 { "mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, { RS } },
3906 { "mtdcr", X(31,451), X_MASK, PPC403 | BOOKE, { SPR, RS } },
3908 { "subfze64",XO(31,456,0,0), XORB_MASK, BOOKE64, { RT, RA } },
3909 { "subfze64o",XO(31,456,1,0), XORB_MASK, BOOKE64, { RT, RA } },
3911 { "divdu", XO(31,457,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3912 { "divdu.", XO(31,457,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3913 { "divduo", XO(31,457,1,0), XO_MASK, PPC64, { RT, RA, RB } },
3914 { "divduo.", XO(31,457,1,1), XO_MASK, PPC64, { RT, RA, RB } },
3916 { "addze64", XO(31,458,0,0), XORB_MASK, BOOKE64, { RT, RA } },
3917 { "addze64o",XO(31,458,1,0), XORB_MASK, BOOKE64, { RT, RA } },
3919 { "divwu", XO(31,459,0,0), XO_MASK, PPC, { RT, RA, RB } },
3920 { "divwu.", XO(31,459,0,1), XO_MASK, PPC, { RT, RA, RB } },
3921 { "divwuo", XO(31,459,1,0), XO_MASK, PPC, { RT, RA, RB } },
3922 { "divwuo.", XO(31,459,1,1), XO_MASK, PPC, { RT, RA, RB } },
3924 { "mtmq", XSPR(31,467,0), XSPR_MASK, M601, { RS } },
3925 { "mtxer", XSPR(31,467,1), XSPR_MASK, COM, { RS } },
3926 { "mtlr", XSPR(31,467,8), XSPR_MASK, COM, { RS } },
3927 { "mtctr", XSPR(31,467,9), XSPR_MASK, COM, { RS } },
3928 { "mttid", XSPR(31,467,17), XSPR_MASK, POWER, { RS } },
3929 { "mtdsisr", XSPR(31,467,18), XSPR_MASK, COM, { RS } },
3930 { "mtdar", XSPR(31,467,19), XSPR_MASK, COM, { RS } },
3931 { "mtrtcu", XSPR(31,467,20), XSPR_MASK, COM, { RS } },
3932 { "mtrtcl", XSPR(31,467,21), XSPR_MASK, COM, { RS } },
3933 { "mtdec", XSPR(31,467,22), XSPR_MASK, COM, { RS } },
3934 { "mtsdr0", XSPR(31,467,24), XSPR_MASK, POWER, { RS } },
3935 { "mtsdr1", XSPR(31,467,25), XSPR_MASK, COM, { RS } },
3936 { "mtsrr0", XSPR(31,467,26), XSPR_MASK, COM, { RS } },
3937 { "mtsrr1", XSPR(31,467,27), XSPR_MASK, COM, { RS } },
3938 { "mtpid", XSPR(31,467,48), XSPR_MASK, BOOKE, { RS } },
3939 { "mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, { RS } },
3940 { "mtdecar", XSPR(31,467,54), XSPR_MASK, BOOKE, { RS } },
3941 { "mtcsrr0", XSPR(31,467,58), XSPR_MASK, BOOKE, { RS } },
3942 { "mtcsrr1", XSPR(31,467,59), XSPR_MASK, BOOKE, { RS } },
3943 { "mtdear", XSPR(31,467,61), XSPR_MASK, BOOKE, { RS } },
3944 { "mtdear", XSPR(31,467,981), XSPR_MASK, PPC403, { RS } },
3945 { "mtesr", XSPR(31,467,62), XSPR_MASK, BOOKE, { RS } },
3946 { "mtesr", XSPR(31,467,980), XSPR_MASK, PPC403, { RS } },
3947 { "mtivpr", XSPR(31,467,63), XSPR_MASK, BOOKE, { RS } },
3948 { "mtcmpa", XSPR(31,467,144), XSPR_MASK, PPC860, { RS } },
3949 { "mtcmpb", XSPR(31,467,145), XSPR_MASK, PPC860, { RS } },
3950 { "mtcmpc", XSPR(31,467,146), XSPR_MASK, PPC860, { RS } },
3951 { "mtcmpd", XSPR(31,467,147), XSPR_MASK, PPC860, { RS } },
3952 { "mticr", XSPR(31,467,148), XSPR_MASK, PPC860, { RS } },
3953 { "mtder", XSPR(31,467,149), XSPR_MASK, PPC860, { RS } },
3954 { "mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860, { RS } },
3955 { "mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860, { RS } },
3956 { "mtcmpe", XSPR(31,467,152), XSPR_MASK, PPC860, { RS } },
3957 { "mtcmpf", XSPR(31,467,153), XSPR_MASK, PPC860, { RS } },
3958 { "mtcmpg", XSPR(31,467,154), XSPR_MASK, PPC860, { RS } },
3959 { "mtcmph", XSPR(31,467,155), XSPR_MASK, PPC860, { RS } },
3960 { "mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860, { RS } },
3961 { "mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860, { RS } },
3962 { "mtictrl", XSPR(31,467,158), XSPR_MASK, PPC860, { RS } },
3963 { "mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, { RS } },
3964 { "mtvrsave", XSPR(31,467,256), XSPR_MASK, PPCVEC, { RS } },
3965 { "mtusprg0", XSPR(31,467,256), XSPR_MASK, BOOKE, { RS } },
3966 { "mtsprg", XSPR(31,467,272), XSPRG_MASK,PPC, { SPRG, RS } },
3967 { "mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC, { RS } },
3968 { "mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, { RS } },
3969 { "mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC, { RS } },
3970 { "mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC, { RS } },
3971 { "mtsprg4", XSPR(31,467,276), XSPR_MASK, PPC405 | BOOKE, { RS } },
3972 { "mtsprg5", XSPR(31,467,277), XSPR_MASK, PPC405 | BOOKE, { RS } },
3973 { "mtsprg6", XSPR(31,467,278), XSPR_MASK, PPC405 | BOOKE, { RS } },
3974 { "mtsprg7", XSPR(31,467,279), XSPR_MASK, PPC405 | BOOKE, { RS } },
3975 { "mtasr", XSPR(31,467,280), XSPR_MASK, PPC64, { RS } },
3976 { "mtear", XSPR(31,467,282), XSPR_MASK, PPC, { RS } },
3977 { "mttbl", XSPR(31,467,284), XSPR_MASK, PPC, { RS } },
3978 { "mttbu", XSPR(31,467,285), XSPR_MASK, PPC, { RS } },
3979 { "mtdbsr", XSPR(31,467,304), XSPR_MASK, BOOKE, { RS } },
3980 { "mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, { RS } },
3981 { "mtdbcr0", XSPR(31,467,308), XSPR_MASK, BOOKE, { RS } },
3982 { "mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405, { RS } },
3983 { "mtdbcr1", XSPR(31,467,309), XSPR_MASK, BOOKE, { RS } },
3984 { "mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405, { RS } },
3985 { "mtdbcr2", XSPR(31,467,310), XSPR_MASK, BOOKE, { RS } },
3986 { "mtiac1", XSPR(31,467,312), XSPR_MASK, BOOKE, { RS } },
3987 { "mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, { RS } },
3988 { "mtiac2", XSPR(31,467,313), XSPR_MASK, BOOKE, { RS } },
3989 { "mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, { RS } },
3990 { "mtiac3", XSPR(31,467,314), XSPR_MASK, BOOKE, { RS } },
3991 { "mtiac3", XSPR(31,467,948), XSPR_MASK, PPC405, { RS } },
3992 { "mtiac4", XSPR(31,467,315), XSPR_MASK, BOOKE, { RS } },
3993 { "mtiac4", XSPR(31,467,949), XSPR_MASK, PPC405, { RS } },
3994 { "mtdac1", XSPR(31,467,316), XSPR_MASK, BOOKE, { RS } },
3995 { "mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, { RS } },
3996 { "mtdac2", XSPR(31,467,317), XSPR_MASK, BOOKE, { RS } },
3997 { "mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, { RS } },
3998 { "mtdvc1", XSPR(31,467,318), XSPR_MASK, BOOKE, { RS } },
3999 { "mtdvc1", XSPR(31,467,950), XSPR_MASK, PPC405, { RS } },
4000 { "mtdvc2", XSPR(31,467,319), XSPR_MASK, BOOKE, { RS } },
4001 { "mtdvc2", XSPR(31,467,951), XSPR_MASK, PPC405, { RS } },
4002 { "mttsr", XSPR(31,467,336), XSPR_MASK, BOOKE, { RS } },
4003 { "mttsr", XSPR(31,467,984), XSPR_MASK, PPC403, { RS } },
4004 { "mttcr", XSPR(31,467,340), XSPR_MASK, BOOKE, { RS } },
4005 { "mttcr", XSPR(31,467,986), XSPR_MASK, PPC403, { RS } },
4006 { "mtivor0", XSPR(31,467,400), XSPR_MASK, BOOKE, { RS } },
4007 { "mtivor1", XSPR(31,467,401), XSPR_MASK, BOOKE, { RS } },
4008 { "mtivor2", XSPR(31,467,402), XSPR_MASK, BOOKE, { RS } },
4009 { "mtivor3", XSPR(31,467,403), XSPR_MASK, BOOKE, { RS } },
4010 { "mtivor4", XSPR(31,467,404), XSPR_MASK, BOOKE, { RS } },
4011 { "mtivor5", XSPR(31,467,405), XSPR_MASK, BOOKE, { RS } },
4012 { "mtivor6", XSPR(31,467,406), XSPR_MASK, BOOKE, { RS } },
4013 { "mtivor7", XSPR(31,467,407), XSPR_MASK, BOOKE, { RS } },
4014 { "mtivor8", XSPR(31,467,408), XSPR_MASK, BOOKE, { RS } },
4015 { "mtivor9", XSPR(31,467,409), XSPR_MASK, BOOKE, { RS } },
4016 { "mtivor10", XSPR(31,467,410), XSPR_MASK, BOOKE, { RS } },
4017 { "mtivor11", XSPR(31,467,411), XSPR_MASK, BOOKE, { RS } },
4018 { "mtivor12", XSPR(31,467,412), XSPR_MASK, BOOKE, { RS } },
4019 { "mtivor13", XSPR(31,467,413), XSPR_MASK, BOOKE, { RS } },
4020 { "mtivor14", XSPR(31,467,414), XSPR_MASK, BOOKE, { RS } },
4021 { "mtivor15", XSPR(31,467,415), XSPR_MASK, BOOKE, { RS } },
4022 { "mtspefscr", XSPR(31,467,512), XSPR_MASK, PPCSPE, { RS } },
4023 { "mtbbear", XSPR(31,467,513), XSPR_MASK, PPCBRLK, { RS } },
4024 { "mtbbtar", XSPR(31,467,514), XSPR_MASK, PPCBRLK, { RS } },
4025 { "mtivor32", XSPR(31,467,528), XSPR_MASK, PPCSPE, { RS } },
4026 { "mtivor33", XSPR(31,467,529), XSPR_MASK, PPCSPE, { RS } },
4027 { "mtivor34", XSPR(31,467,530), XSPR_MASK, PPCSPE, { RS } },
4028 { "mtivor35", XSPR(31,467,531), XSPR_MASK, PPCPMR, { RS } },
4029 { "mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
4030 { "mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
4031 { "mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
4032 { "mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
4033 { "mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, { RS } },
4034 { "mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, { RS } },
4035 { "mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, { RS } },
4036 { "mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, { RS } },
4037 { "mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, { RS } },
4038 { "mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, { RS } },
4039 { "mtusia", XSPR(31,467,939), XSPR_MASK, PPC750, { RS } },
4040 { "mtummcr1", XSPR(31,467,940), XSPR_MASK, PPC750, { RS } },
4041 { "mtupmc3", XSPR(31,467,941), XSPR_MASK, PPC750, { RS } },
4042 { "mtupmc4", XSPR(31,467,942), XSPR_MASK, PPC750, { RS } },
4043 { "mtzpr", XSPR(31,467,944), XSPR_MASK, PPC403, { RS } },
4044 { "mtccr0", XSPR(31,467,947), XSPR_MASK, PPC405, { RS } },
4045 { "mtmmcr0", XSPR(31,467,952), XSPR_MASK, PPC750, { RS } },
4046 { "mtsgr", XSPR(31,467,953), XSPR_MASK, PPC403, { RS } },
4047 { "mtpmc1", XSPR(31,467,953), XSPR_MASK, PPC750, { RS } },
4048 { "mtdcwr", XSPR(31,467,954), XSPR_MASK, PPC403, { RS } },
4049 { "mtpmc2", XSPR(31,467,954), XSPR_MASK, PPC750, { RS } },
4050 { "mtsler", XSPR(31,467,955), XSPR_MASK, PPC405, { RS } },
4051 { "mtsia", XSPR(31,467,955), XSPR_MASK, PPC750, { RS } },
4052 { "mtsu0r", XSPR(31,467,956), XSPR_MASK, PPC405, { RS } },
4053 { "mtmmcr1", XSPR(31,467,956), XSPR_MASK, PPC750, { RS } },
4054 { "mtpmc3", XSPR(31,467,957), XSPR_MASK, PPC750, { RS } },
4055 { "mtpmc4", XSPR(31,467,958), XSPR_MASK, PPC750, { RS } },
4056 { "mticdbdr", XSPR(31,467,979), XSPR_MASK, PPC403, { RS } },
4057 { "mtevpr", XSPR(31,467,982), XSPR_MASK, PPC403, { RS } },
4058 { "mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403, { RS } },
4059 { "mtpit", XSPR(31,467,987), XSPR_MASK, PPC403, { RS } },
4060 { "mttbhi", XSPR(31,467,988), XSPR_MASK, PPC403, { RS } },
4061 { "mttblo", XSPR(31,467,989), XSPR_MASK, PPC403, { RS } },
4062 { "mtsrr2", XSPR(31,467,990), XSPR_MASK, PPC403, { RS } },
4063 { "mtsrr3", XSPR(31,467,991), XSPR_MASK, PPC403, { RS } },
4064 { "mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, { RS } },
4065 { "mtdccr", XSPR(31,467,1018), XSPR_MASK, PPC403, { RS } },
4066 { "mticcr", XSPR(31,467,1019), XSPR_MASK, PPC403, { RS } },
4067 { "mtictc", XSPR(31,467,1019), XSPR_MASK, PPC750, { RS } },
4068 { "mtpbl1", XSPR(31,467,1020), XSPR_MASK, PPC403, { RS } },
4069 { "mtthrm1", XSPR(31,467,1020), XSPR_MASK, PPC750, { RS } },
4070 { "mtpbu1", XSPR(31,467,1021), XSPR_MASK, PPC403, { RS } },
4071 { "mtthrm2", XSPR(31,467,1021), XSPR_MASK, PPC750, { RS } },
4072 { "mtpbl2", XSPR(31,467,1022), XSPR_MASK, PPC403, { RS } },
4073 { "mtthrm3", XSPR(31,467,1022), XSPR_MASK, PPC750, { RS } },
4074 { "mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, { RS } },
4075 { "mtspr", X(31,467), X_MASK, COM, { SPR, RS } },
4077 { "dcbi", X(31,470), XRT_MASK, PPC, { RA, RB } },
4079 { "nand", XRC(31,476,0), X_MASK, COM, { RA, RS, RB } },
4080 { "nand.", XRC(31,476,1), X_MASK, COM, { RA, RS, RB } },
4082 { "dcbie", X(31,478), XRT_MASK, BOOKE64, { RA, RB } },
4084 { "dcread", X(31,486), X_MASK, PPC403|PPC440, { RT, RA, RB }},
4086 { "mtpmr", X(31,462), X_MASK, PPCPMR, { PMR, RS }},
4088 { "icbtls", X(31,486), X_MASK, PPCCHLK, { CT, RA, RB }},
4090 { "nabs", XO(31,488,0,0), XORB_MASK, M601, { RT, RA } },
4091 { "subfme64",XO(31,488,0,0), XORB_MASK, BOOKE64, { RT, RA } },
4092 { "nabs.", XO(31,488,0,1), XORB_MASK, M601, { RT, RA } },
4093 { "nabso", XO(31,488,1,0), XORB_MASK, M601, { RT, RA } },
4094 { "subfme64o",XO(31,488,1,0), XORB_MASK, BOOKE64, { RT, RA } },
4095 { "nabso.", XO(31,488,1,1), XORB_MASK, M601, { RT, RA } },
4097 { "divd", XO(31,489,0,0), XO_MASK, PPC64, { RT, RA, RB } },
4098 { "divd.", XO(31,489,0,1), XO_MASK, PPC64, { RT, RA, RB } },
4099 { "divdo", XO(31,489,1,0), XO_MASK, PPC64, { RT, RA, RB } },
4100 { "divdo.", XO(31,489,1,1), XO_MASK, PPC64, { RT, RA, RB } },
4102 { "addme64", XO(31,490,0,0), XORB_MASK, BOOKE64, { RT, RA } },
4103 { "addme64o",XO(31,490,1,0), XORB_MASK, BOOKE64, { RT, RA } },
4105 { "divw", XO(31,491,0,0), XO_MASK, PPC, { RT, RA, RB } },
4106 { "divw.", XO(31,491,0,1), XO_MASK, PPC, { RT, RA, RB } },
4107 { "divwo", XO(31,491,1,0), XO_MASK, PPC, { RT, RA, RB } },
4108 { "divwo.", XO(31,491,1,1), XO_MASK, PPC, { RT, RA, RB } },
4110 { "icbtlse", X(31,494), X_MASK, PPCCHLK64, { CT, RA, RB }},
4112 { "slbia", X(31,498), 0xffffffff, PPC64, { 0 } },
4114 { "cli", X(31,502), XRB_MASK, POWER, { RT, RA } },
4116 { "stdcxe.", XRC(31,511,1), X_MASK, BOOKE64, { RS, RA, RB } },
4118 { "mcrxr", X(31,512), XRARB_MASK|(3<<21), COM, { BF } },
4120 { "bblels", X(31,518), X_MASK, PPCBRLK, { 0 }},
4121 { "mcrxr64", X(31,544), XRARB_MASK|(3<<21), BOOKE64, { BF } },
4123 { "clcs", X(31,531), XRB_MASK, M601, { RT, RA } },
4125 { "lswx", X(31,533), X_MASK, PPCCOM, { RT, RA0, RB } },
4126 { "lsx", X(31,533), X_MASK, PWRCOM, { RT, RA, RB } },
4128 { "lwbrx", X(31,534), X_MASK, PPCCOM, { RT, RA0, RB } },
4129 { "lbrx", X(31,534), X_MASK, PWRCOM, { RT, RA, RB } },
4131 { "lfsx", X(31,535), X_MASK, COM, { FRT, RA0, RB } },
4133 { "srw", XRC(31,536,0), X_MASK, PPCCOM, { RA, RS, RB } },
4134 { "sr", XRC(31,536,0), X_MASK, PWRCOM, { RA, RS, RB } },
4135 { "srw.", XRC(31,536,1), X_MASK, PPCCOM, { RA, RS, RB } },
4136 { "sr.", XRC(31,536,1), X_MASK, PWRCOM, { RA, RS, RB } },
4138 { "rrib", XRC(31,537,0), X_MASK, M601, { RA, RS, RB } },
4139 { "rrib.", XRC(31,537,1), X_MASK, M601, { RA, RS, RB } },
4141 { "srd", XRC(31,539,0), X_MASK, PPC64, { RA, RS, RB } },
4142 { "srd.", XRC(31,539,1), X_MASK, PPC64, { RA, RS, RB } },
4144 { "maskir", XRC(31,541,0), X_MASK, M601, { RA, RS, RB } },
4145 { "maskir.", XRC(31,541,1), X_MASK, M601, { RA, RS, RB } },
4147 { "lwbrxe", X(31,542), X_MASK, BOOKE64, { RT, RA0, RB } },
4149 { "lfsxe", X(31,543), X_MASK, BOOKE64, { FRT, RA0, RB } },
4151 { "bbelr", X(31,550), X_MASK, PPCBRLK, { 0 }},
4153 { "tlbsync", X(31,566), 0xffffffff, PPC, { 0 } },
4155 { "lfsux", X(31,567), X_MASK, COM, { FRT, RAS, RB } },
4157 { "lfsuxe", X(31,575), X_MASK, BOOKE64, { FRT, RAS, RB } },
4159 { "mfsr", X(31,595), XRB_MASK|(1<<20), COM32, { RT, SR } },
4161 { "lswi", X(31,597), X_MASK, PPCCOM, { RT, RA0, NB } },
4162 { "lsi", X(31,597), X_MASK, PWRCOM, { RT, RA0, NB } },
4164 { "lwsync", XSYNC(31,598,1), 0xffffffff, PPC, { 0 } },
4165 { "ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, { 0 } },
4166 { "msync", X(31,598), 0xffffffff, BOOKE, { 0 } },
4167 { "sync", X(31,598), XSYNC_MASK, PPCCOM, { LS } },
4168 { "dcs", X(31,598), 0xffffffff, PWRCOM, { 0 } },
4170 { "lfdx", X(31,599), X_MASK, COM, { FRT, RA0, RB } },
4172 { "lfdxe", X(31,607), X_MASK, BOOKE64, { FRT, RA0, RB } },
4174 { "mfsri", X(31,627), X_MASK, PWRCOM, { RT, RA, RB } },
4176 { "dclst", X(31,630), XRB_MASK, PWRCOM, { RS, RA } },
4178 { "lfdux", X(31,631), X_MASK, COM, { FRT, RAS, RB } },
4180 { "lfduxe", X(31,639), X_MASK, BOOKE64, { FRT, RAS, RB } },
4182 { "mfsrin", X(31,659), XRA_MASK, PPC32, { RT, RB } },
4184 { "stswx", X(31,661), X_MASK, PPCCOM, { RS, RA0, RB } },
4185 { "stsx", X(31,661), X_MASK, PWRCOM, { RS, RA0, RB } },
4187 { "stwbrx", X(31,662), X_MASK, PPCCOM, { RS, RA0, RB } },
4188 { "stbrx", X(31,662), X_MASK, PWRCOM, { RS, RA0, RB } },
4190 { "stfsx", X(31,663), X_MASK, COM, { FRS, RA0, RB } },
4192 { "srq", XRC(31,664,0), X_MASK, M601, { RA, RS, RB } },
4193 { "srq.", XRC(31,664,1), X_MASK, M601, { RA, RS, RB } },
4195 { "sre", XRC(31,665,0), X_MASK, M601, { RA, RS, RB } },
4196 { "sre.", XRC(31,665,1), X_MASK, M601, { RA, RS, RB } },
4198 { "stwbrxe", X(31,670), X_MASK, BOOKE64, { RS, RA0, RB } },
4200 { "stfsxe", X(31,671), X_MASK, BOOKE64, { FRS, RA0, RB } },
4202 { "stfsux", X(31,695), X_MASK, COM, { FRS, RAS, RB } },
4204 { "sriq", XRC(31,696,0), X_MASK, M601, { RA, RS, SH } },
4205 { "sriq.", XRC(31,696,1), X_MASK, M601, { RA, RS, SH } },
4207 { "stfsuxe", X(31,703), X_MASK, BOOKE64, { FRS, RAS, RB } },
4209 { "stswi", X(31,725), X_MASK, PPCCOM, { RS, RA0, NB } },
4210 { "stsi", X(31,725), X_MASK, PWRCOM, { RS, RA0, NB } },
4212 { "stfdx", X(31,727), X_MASK, COM, { FRS, RA0, RB } },
4214 { "srlq", XRC(31,728,0), X_MASK, M601, { RA, RS, RB } },
4215 { "srlq.", XRC(31,728,1), X_MASK, M601, { RA, RS, RB } },
4217 { "sreq", XRC(31,729,0), X_MASK, M601, { RA, RS, RB } },
4218 { "sreq.", XRC(31,729,1), X_MASK, M601, { RA, RS, RB } },
4220 { "stfdxe", X(31,735), X_MASK, BOOKE64, { FRS, RA0, RB } },
4222 { "dcba", X(31,758), XRT_MASK, PPC405 | BOOKE, { RA, RB } },
4224 { "stfdux", X(31,759), X_MASK, COM, { FRS, RAS, RB } },
4226 { "srliq", XRC(31,760,0), X_MASK, M601, { RA, RS, SH } },
4227 { "srliq.", XRC(31,760,1), X_MASK, M601, { RA, RS, SH } },
4229 { "dcbae", X(31,766), XRT_MASK, BOOKE64, { RA, RB } },
4231 { "stfduxe", X(31,767), X_MASK, BOOKE64, { FRS, RAS, RB } },
4233 { "tlbivax", X(31,786), XRT_MASK, BOOKE, { RA, RB } },
4234 { "tlbivaxe",X(31,787), XRT_MASK, BOOKE64, { RA, RB } },
4236 { "lhbrx", X(31,790), X_MASK, COM, { RT, RA0, RB } },
4238 { "sraw", XRC(31,792,0), X_MASK, PPCCOM, { RA, RS, RB } },
4239 { "sra", XRC(31,792,0), X_MASK, PWRCOM, { RA, RS, RB } },
4240 { "sraw.", XRC(31,792,1), X_MASK, PPCCOM, { RA, RS, RB } },
4241 { "sra.", XRC(31,792,1), X_MASK, PWRCOM, { RA, RS, RB } },
4243 { "srad", XRC(31,794,0), X_MASK, PPC64, { RA, RS, RB } },
4244 { "srad.", XRC(31,794,1), X_MASK, PPC64, { RA, RS, RB } },
4246 { "lhbrxe", X(31,798), X_MASK, BOOKE64, { RT, RA0, RB } },
4248 { "ldxe", X(31,799), X_MASK, BOOKE64, { RT, RA0, RB } },
4249 { "lduxe", X(31,831), X_MASK, BOOKE64, { RT, RA0, RB } },
4251 { "rac", X(31,818), X_MASK, PWRCOM, { RT, RA, RB } },
4253 { "dss", XDSS(31,822,0), XDSS_MASK, PPCVEC, { STRM } },
4254 { "dssall", XDSS(31,822,1), XDSS_MASK, PPCVEC, { 0 } },
4256 { "srawi", XRC(31,824,0), X_MASK, PPCCOM, { RA, RS, SH } },
4257 { "srai", XRC(31,824,0), X_MASK, PWRCOM, { RA, RS, SH } },
4258 { "srawi.", XRC(31,824,1), X_MASK, PPCCOM, { RA, RS, SH } },
4259 { "srai.", XRC(31,824,1), X_MASK, PWRCOM, { RA, RS, SH } },
4261 { "slbmfev", X(31,851), XRA_MASK, PPC64, { RT, RB } },
4263 { "mbar", X(31,854), X_MASK, BOOKE, { MO } },
4264 { "eieio", X(31,854), 0xffffffff, PPC, { 0 } },
4266 { "tlbsx", XRC(31,914,0), X_MASK, BOOKE, { RA, RB } },
4267 { "tlbsx", XRC(31,914,0), X_MASK, PPC403, { RT, RA, RB } },
4268 { "tlbsx.", XRC(31,914,1), X_MASK, BOOKE, { RA, RB } },
4269 { "tlbsx.", XRC(31,914,1), X_MASK, PPC403, { RT, RA, RB } },
4270 { "tlbsxe", XRC(31,915,0), X_MASK, BOOKE64, { RA, RB } },
4271 { "tlbsxe.", XRC(31,915,1), X_MASK, BOOKE64, { RA, RB } },
4273 { "slbmfee", X(31,915), XRA_MASK, PPC64, { RT, RB } },
4275 { "sthbrx", X(31,918), X_MASK, COM, { RS, RA0, RB } },
4277 { "sraq", XRC(31,920,0), X_MASK, M601, { RA, RS, RB } },
4278 { "sraq.", XRC(31,920,1), X_MASK, M601, { RA, RS, RB } },
4280 { "srea", XRC(31,921,0), X_MASK, M601, { RA, RS, RB } },
4281 { "srea.", XRC(31,921,1), X_MASK, M601, { RA, RS, RB } },
4283 { "extsh", XRC(31,922,0), XRB_MASK, PPCCOM, { RA, RS } },
4284 { "exts", XRC(31,922,0), XRB_MASK, PWRCOM, { RA, RS } },
4285 { "extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, { RA, RS } },
4286 { "exts.", XRC(31,922,1), XRB_MASK, PWRCOM, { RA, RS } },
4288 { "sthbrxe", X(31,926), X_MASK, BOOKE64, { RS, RA0, RB } },
4290 { "stdxe", X(31,927), X_MASK, BOOKE64, { RS, RA0, RB } },
4292 { "tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, { RT, RA } },
4293 { "tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, { RT, RA } },
4294 { "tlbre", X(31,946), X_MASK, BOOKE, { 0 } },
4295 { "tlbre", X(31,946), X_MASK, PPC403, { RS, RA, SH } },
4297 { "sraiq", XRC(31,952,0), X_MASK, M601, { RA, RS, SH } },
4298 { "sraiq.", XRC(31,952,1), X_MASK, M601, { RA, RS, SH } },
4300 { "extsb", XRC(31,954,0), XRB_MASK, PPC, { RA, RS} },
4301 { "extsb.", XRC(31,954,1), XRB_MASK, PPC, { RA, RS} },
4303 { "stduxe", X(31,959), X_MASK, BOOKE64, { RS, RAS, RB } },
4305 { "iccci", X(31,966), XRT_MASK, PPC403|PPC440, { RA, RB } },
4307 { "tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, { RT, RA } },
4308 { "tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, { RT, RA } },
4309 { "tlbwe", X(31,978), X_MASK, PPC403|BOOKE, { RSO, RAOPT, SHO } },
4310 { "tlbld", X(31,978), XRTRA_MASK, PPC, { RB } },
4312 { "icbi", X(31,982), XRT_MASK, PPC, { RA, RB } },
4314 { "stfiwx", X(31,983), X_MASK, PPC, { FRS, RA0, RB } },
4316 { "extsw", XRC(31,986,0), XRB_MASK, PPC64 | BOOKE64,{ RA, RS } },
4317 { "extsw.", XRC(31,986,1), XRB_MASK, PPC64, { RA, RS } },
4319 { "icread", X(31,998), XRT_MASK, PPC403|PPC440, { RA, RB } },
4321 { "icbie", X(31,990), XRT_MASK, BOOKE64, { RA, RB } },
4322 { "stfiwxe", X(31,991), X_MASK, BOOKE64, { FRS, RA0, RB } },
4324 { "tlbli", X(31,1010), XRTRA_MASK, PPC, { RB } },
4326 { "dcbzl", XOPL(31,1014,1), XRT_MASK,POWER4, { RA, RB } },
4327 { "dcbz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
4328 { "dclz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
4330 { "dcbze", X(31,1022), XRT_MASK, BOOKE64, { RA, RB } },
4332 { "lvebx", X(31, 7), X_MASK, PPCVEC, { VD, RA, RB } },
4333 { "lvehx", X(31, 39), X_MASK, PPCVEC, { VD, RA, RB } },
4334 { "lvewx", X(31, 71), X_MASK, PPCVEC, { VD, RA, RB } },
4335 { "lvsl", X(31, 6), X_MASK, PPCVEC, { VD, RA, RB } },
4336 { "lvsr", X(31, 38), X_MASK, PPCVEC, { VD, RA, RB } },
4337 { "lvx", X(31, 103), X_MASK, PPCVEC, { VD, RA, RB } },
4338 { "lvxl", X(31, 359), X_MASK, PPCVEC, { VD, RA, RB } },
4339 { "stvebx", X(31, 135), X_MASK, PPCVEC, { VS, RA, RB } },
4340 { "stvehx", X(31, 167), X_MASK, PPCVEC, { VS, RA, RB } },
4341 { "stvewx", X(31, 199), X_MASK, PPCVEC, { VS, RA, RB } },
4342 { "stvx", X(31, 231), X_MASK, PPCVEC, { VS, RA, RB } },
4343 { "stvxl", X(31, 487), X_MASK, PPCVEC, { VS, RA, RB } },
4345 { "lwz", OP(32), OP_MASK, PPCCOM, { RT, D, RA0 } },
4346 { "l", OP(32), OP_MASK, PWRCOM, { RT, D, RA0 } },
4348 { "lwzu", OP(33), OP_MASK, PPCCOM, { RT, D, RAL } },
4349 { "lu", OP(33), OP_MASK, PWRCOM, { RT, D, RA0 } },
4351 { "lbz", OP(34), OP_MASK, COM, { RT, D, RA0 } },
4353 { "lbzu", OP(35), OP_MASK, COM, { RT, D, RAL } },
4355 { "stw", OP(36), OP_MASK, PPCCOM, { RS, D, RA0 } },
4356 { "st", OP(36), OP_MASK, PWRCOM, { RS, D, RA0 } },
4358 { "stwu", OP(37), OP_MASK, PPCCOM, { RS, D, RAS } },
4359 { "stu", OP(37), OP_MASK, PWRCOM, { RS, D, RA0 } },
4361 { "stb", OP(38), OP_MASK, COM, { RS, D, RA0 } },
4363 { "stbu", OP(39), OP_MASK, COM, { RS, D, RAS } },
4365 { "lhz", OP(40), OP_MASK, COM, { RT, D, RA0 } },
4367 { "lhzu", OP(41), OP_MASK, COM, { RT, D, RAL } },
4369 { "lha", OP(42), OP_MASK, COM, { RT, D, RA0 } },
4371 { "lhau", OP(43), OP_MASK, COM, { RT, D, RAL } },
4373 { "sth", OP(44), OP_MASK, COM, { RS, D, RA0 } },
4375 { "sthu", OP(45), OP_MASK, COM, { RS, D, RAS } },
4377 { "lmw", OP(46), OP_MASK, PPCCOM, { RT, D, RAM } },
4378 { "lm", OP(46), OP_MASK, PWRCOM, { RT, D, RA0 } },
4380 { "stmw", OP(47), OP_MASK, PPCCOM, { RS, D, RA0 } },
4381 { "stm", OP(47), OP_MASK, PWRCOM, { RS, D, RA0 } },
4383 { "lfs", OP(48), OP_MASK, COM, { FRT, D, RA0 } },
4385 { "lfsu", OP(49), OP_MASK, COM, { FRT, D, RAS } },
4387 { "lfd", OP(50), OP_MASK, COM, { FRT, D, RA0 } },
4389 { "lfdu", OP(51), OP_MASK, COM, { FRT, D, RAS } },
4391 { "stfs", OP(52), OP_MASK, COM, { FRS, D, RA0 } },
4393 { "stfsu", OP(53), OP_MASK, COM, { FRS, D, RAS } },
4395 { "stfd", OP(54), OP_MASK, COM, { FRS, D, RA0 } },
4397 { "stfdu", OP(55), OP_MASK, COM, { FRS, D, RAS } },
4399 { "lq", OP(56), OP_MASK, POWER4, { RTQ, DQ, RAQ } },
4401 { "lfq", OP(56), OP_MASK, POWER2, { FRT, D, RA0 } },
4403 { "lfqu", OP(57), OP_MASK, POWER2, { FRT, D, RA0 } },
4405 { "lbze", DEO(58,0), DE_MASK, BOOKE64, { RT, DE, RA0 } },
4406 { "lbzue", DEO(58,1), DE_MASK, BOOKE64, { RT, DE, RAL } },
4407 { "lhze", DEO(58,2), DE_MASK, BOOKE64, { RT, DE, RA0 } },
4408 { "lhzue", DEO(58,3), DE_MASK, BOOKE64, { RT, DE, RAL } },
4409 { "lhae", DEO(58,4), DE_MASK, BOOKE64, { RT, DE, RA0 } },
4410 { "lhaue", DEO(58,5), DE_MASK, BOOKE64, { RT, DE, RAL } },
4411 { "lwze", DEO(58,6), DE_MASK, BOOKE64, { RT, DE, RA0 } },
4412 { "lwzue", DEO(58,7), DE_MASK, BOOKE64, { RT, DE, RAL } },
4413 { "stbe", DEO(58,8), DE_MASK, BOOKE64, { RS, DE, RA0 } },
4414 { "stbue", DEO(58,9), DE_MASK, BOOKE64, { RS, DE, RAS } },
4415 { "sthe", DEO(58,10), DE_MASK, BOOKE64, { RS, DE, RA0 } },
4416 { "sthue", DEO(58,11), DE_MASK, BOOKE64, { RS, DE, RAS } },
4417 { "stwe", DEO(58,14), DE_MASK, BOOKE64, { RS, DE, RA0 } },
4418 { "stwue", DEO(58,15), DE_MASK, BOOKE64, { RS, DE, RAS } },
4420 { "ld", DSO(58,0), DS_MASK, PPC64, { RT, DS, RA0 } },
4422 { "ldu", DSO(58,1), DS_MASK, PPC64, { RT, DS, RAL } },
4424 { "lwa", DSO(58,2), DS_MASK, PPC64, { RT, DS, RA0 } },
4426 { "fdivs", A(59,18,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4427 { "fdivs.", A(59,18,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4429 { "fsubs", A(59,20,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4430 { "fsubs.", A(59,20,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4432 { "fadds", A(59,21,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4433 { "fadds.", A(59,21,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4435 { "fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
4436 { "fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
4438 { "fres", A(59,24,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
4439 { "fres.", A(59,24,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
4441 { "fmuls", A(59,25,0), AFRB_MASK, PPC, { FRT, FRA, FRC } },
4442 { "fmuls.", A(59,25,1), AFRB_MASK, PPC, { FRT, FRA, FRC } },
4444 { "fmsubs", A(59,28,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4445 { "fmsubs.", A(59,28,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4447 { "fmadds", A(59,29,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4448 { "fmadds.", A(59,29,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4450 { "fnmsubs", A(59,30,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4451 { "fnmsubs.",A(59,30,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4453 { "fnmadds", A(59,31,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4454 { "fnmadds.",A(59,31,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4456 { "stfq", OP(60), OP_MASK, POWER2, { FRS, D, RA } },
4458 { "stfqu", OP(61), OP_MASK, POWER2, { FRS, D, RA } },
4460 { "lde", DEO(62,0), DE_MASK, BOOKE64, { RT, DES, RA0 } },
4461 { "ldue", DEO(62,1), DE_MASK, BOOKE64, { RT, DES, RA0 } },
4462 { "lfse", DEO(62,4), DE_MASK, BOOKE64, { FRT, DES, RA0 } },
4463 { "lfsue", DEO(62,5), DE_MASK, BOOKE64, { FRT, DES, RAS } },
4464 { "lfde", DEO(62,6), DE_MASK, BOOKE64, { FRT, DES, RA0 } },
4465 { "lfdue", DEO(62,7), DE_MASK, BOOKE64, { FRT, DES, RAS } },
4466 { "stde", DEO(62,8), DE_MASK, BOOKE64, { RS, DES, RA0 } },
4467 { "stdue", DEO(62,9), DE_MASK, BOOKE64, { RS, DES, RAS } },
4468 { "stfse", DEO(62,12), DE_MASK, BOOKE64, { FRS, DES, RA0 } },
4469 { "stfsue", DEO(62,13), DE_MASK, BOOKE64, { FRS, DES, RAS } },
4470 { "stfde", DEO(62,14), DE_MASK, BOOKE64, { FRS, DES, RA0 } },
4471 { "stfdue", DEO(62,15), DE_MASK, BOOKE64, { FRS, DES, RAS } },
4473 { "std", DSO(62,0), DS_MASK, PPC64, { RS, DS, RA0 } },
4475 { "stdu", DSO(62,1), DS_MASK, PPC64, { RS, DS, RAS } },
4477 { "stq", DSO(62,2), DS_MASK, POWER4, { RSQ, DS, RA0 } },
4479 { "fcmpu", X(63,0), X_MASK|(3<<21), COM, { BF, FRA, FRB } },
4481 { "frsp", XRC(63,12,0), XRA_MASK, COM, { FRT, FRB } },
4482 { "frsp.", XRC(63,12,1), XRA_MASK, COM, { FRT, FRB } },
4484 { "fctiw", XRC(63,14,0), XRA_MASK, PPCCOM, { FRT, FRB } },
4485 { "fcir", XRC(63,14,0), XRA_MASK, POWER2, { FRT, FRB } },
4486 { "fctiw.", XRC(63,14,1), XRA_MASK, PPCCOM, { FRT, FRB } },
4487 { "fcir.", XRC(63,14,1), XRA_MASK, POWER2, { FRT, FRB } },
4489 { "fctiwz", XRC(63,15,0), XRA_MASK, PPCCOM, { FRT, FRB } },
4490 { "fcirz", XRC(63,15,0), XRA_MASK, POWER2, { FRT, FRB } },
4491 { "fctiwz.", XRC(63,15,1), XRA_MASK, PPCCOM, { FRT, FRB } },
4492 { "fcirz.", XRC(63,15,1), XRA_MASK, POWER2, { FRT, FRB } },
4494 { "fdiv", A(63,18,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4495 { "fd", A(63,18,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4496 { "fdiv.", A(63,18,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4497 { "fd.", A(63,18,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4499 { "fsub", A(63,20,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4500 { "fs", A(63,20,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4501 { "fsub.", A(63,20,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4502 { "fs.", A(63,20,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4504 { "fadd", A(63,21,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4505 { "fa", A(63,21,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4506 { "fadd.", A(63,21,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4507 { "fa.", A(63,21,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4509 { "fsqrt", A(63,22,0), AFRAFRC_MASK, PPCPWR2, { FRT, FRB } },
4510 { "fsqrt.", A(63,22,1), AFRAFRC_MASK, PPCPWR2, { FRT, FRB } },
4512 { "fsel", A(63,23,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4513 { "fsel.", A(63,23,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4515 { "fmul", A(63,25,0), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } },
4516 { "fm", A(63,25,0), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } },
4517 { "fmul.", A(63,25,1), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } },
4518 { "fm.", A(63,25,1), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } },
4520 { "frsqrte", A(63,26,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
4521 { "frsqrte.",A(63,26,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
4523 { "fmsub", A(63,28,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4524 { "fms", A(63,28,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4525 { "fmsub.", A(63,28,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4526 { "fms.", A(63,28,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4528 { "fmadd", A(63,29,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4529 { "fma", A(63,29,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4530 { "fmadd.", A(63,29,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4531 { "fma.", A(63,29,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4533 { "fnmsub", A(63,30,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4534 { "fnms", A(63,30,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4535 { "fnmsub.", A(63,30,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4536 { "fnms.", A(63,30,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4538 { "fnmadd", A(63,31,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4539 { "fnma", A(63,31,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4540 { "fnmadd.", A(63,31,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4541 { "fnma.", A(63,31,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4543 { "fcmpo", X(63,32), X_MASK|(3<<21), COM, { BF, FRA, FRB } },
4545 { "mtfsb1", XRC(63,38,0), XRARB_MASK, COM, { BT } },
4546 { "mtfsb1.", XRC(63,38,1), XRARB_MASK, COM, { BT } },
4548 { "fneg", XRC(63,40,0), XRA_MASK, COM, { FRT, FRB } },
4549 { "fneg.", XRC(63,40,1), XRA_MASK, COM, { FRT, FRB } },
4551 { "mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, { BF, BFA } },
4553 { "mtfsb0", XRC(63,70,0), XRARB_MASK, COM, { BT } },
4554 { "mtfsb0.", XRC(63,70,1), XRARB_MASK, COM, { BT } },
4556 { "fmr", XRC(63,72,0), XRA_MASK, COM, { FRT, FRB } },
4557 { "fmr.", XRC(63,72,1), XRA_MASK, COM, { FRT, FRB } },
4559 { "mtfsfi", XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } },
4560 { "mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } },
4562 { "fnabs", XRC(63,136,0), XRA_MASK, COM, { FRT, FRB } },
4563 { "fnabs.", XRC(63,136,1), XRA_MASK, COM, { FRT, FRB } },
4565 { "fabs", XRC(63,264,0), XRA_MASK, COM, { FRT, FRB } },
4566 { "fabs.", XRC(63,264,1), XRA_MASK, COM, { FRT, FRB } },
4568 { "mffs", XRC(63,583,0), XRARB_MASK, COM, { FRT } },
4569 { "mffs.", XRC(63,583,1), XRARB_MASK, COM, { FRT } },
4571 { "mtfsf", XFL(63,711,0), XFL_MASK, COM, { FLM, FRB } },
4572 { "mtfsf.", XFL(63,711,1), XFL_MASK, COM, { FLM, FRB } },
4574 { "fctid", XRC(63,814,0), XRA_MASK, PPC64, { FRT, FRB } },
4575 { "fctid.", XRC(63,814,1), XRA_MASK, PPC64, { FRT, FRB } },
4577 { "fctidz", XRC(63,815,0), XRA_MASK, PPC64, { FRT, FRB } },
4578 { "fctidz.", XRC(63,815,1), XRA_MASK, PPC64, { FRT, FRB } },
4580 { "fcfid", XRC(63,846,0), XRA_MASK, PPC64, { FRT, FRB } },
4581 { "fcfid.", XRC(63,846,1), XRA_MASK, PPC64, { FRT, FRB } },
4585 const int powerpc_num_opcodes =
4586 sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]);
4588 /* The macro table. This is only used by the assembler. */
4590 /* The expressions of the form (-x ! 31) & (x | 31) have the value 0
4591 when x=0; 32-x when x is between 1 and 31; are negative if x is
4592 negative; and are 32 or more otherwise. This is what you want
4593 when, for instance, you are emulating a right shift by a
4594 rotate-left-and-mask, because the underlying instructions support
4595 shifts of size 0 but not shifts of size 32. By comparison, when
4596 extracting x bits from some word you want to use just 32-x, because
4597 the underlying instructions don't support extracting 0 bits but do
4598 support extracting the whole word (32 bits in this case). */
4600 const struct powerpc_macro powerpc_macros[] = {
4601 { "extldi", 4, PPC64, "rldicr %0,%1,%3,(%2)-1" },
4602 { "extldi.", 4, PPC64, "rldicr. %0,%1,%3,(%2)-1" },
4603 { "extrdi", 4, PPC64, "rldicl %0,%1,(%2)+(%3),64-(%2)" },
4604 { "extrdi.", 4, PPC64, "rldicl. %0,%1,(%2)+(%3),64-(%2)" },
4605 { "insrdi", 4, PPC64, "rldimi %0,%1,64-((%2)+(%3)),%3" },
4606 { "insrdi.", 4, PPC64, "rldimi. %0,%1,64-((%2)+(%3)),%3" },
4607 { "rotrdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),0" },
4608 { "rotrdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0" },
4609 { "sldi", 3, PPC64, "rldicr %0,%1,%2,63-(%2)" },
4610 { "sldi.", 3, PPC64, "rldicr. %0,%1,%2,63-(%2)" },
4611 { "srdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2" },
4612 { "srdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2" },
4613 { "clrrdi", 3, PPC64, "rldicr %0,%1,0,63-(%2)" },
4614 { "clrrdi.", 3, PPC64, "rldicr. %0,%1,0,63-(%2)" },
4615 { "clrlsldi",4, PPC64, "rldic %0,%1,%3,(%2)-(%3)" },
4616 { "clrlsldi.",4, PPC64, "rldic. %0,%1,%3,(%2)-(%3)" },
4618 { "extlwi", 4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1" },
4619 { "extlwi.", 4, PPCCOM, "rlwinm. %0,%1,%3,0,(%2)-1" },
4620 { "extrwi", 4, PPCCOM, "rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31" },
4621 { "extrwi.", 4, PPCCOM, "rlwinm. %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31" },
4622 { "inslwi", 4, PPCCOM, "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1" },
4623 { "inslwi.", 4, PPCCOM, "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
4624 { "insrwi", 4, PPCCOM, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1" },
4625 { "insrwi.", 4, PPCCOM, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
4626 { "rotrwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31" },
4627 { "rotrwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31" },
4628 { "slwi", 3, PPCCOM, "rlwinm %0,%1,%2,0,31-(%2)" },
4629 { "sli", 3, PWRCOM, "rlinm %0,%1,%2,0,31-(%2)" },
4630 { "slwi.", 3, PPCCOM, "rlwinm. %0,%1,%2,0,31-(%2)" },
4631 { "sli.", 3, PWRCOM, "rlinm. %0,%1,%2,0,31-(%2)" },
4632 { "srwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4633 { "sri", 3, PWRCOM, "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4634 { "srwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4635 { "sri.", 3, PWRCOM, "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4636 { "clrrwi", 3, PPCCOM, "rlwinm %0,%1,0,0,31-(%2)" },
4637 { "clrrwi.", 3, PPCCOM, "rlwinm. %0,%1,0,0,31-(%2)" },
4638 { "clrlslwi",4, PPCCOM, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)" },
4639 { "clrlslwi.",4, PPCCOM, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)" },
4642 const int powerpc_num_macros =
4643 sizeof (powerpc_macros) / sizeof (powerpc_macros[0]);