* configure.in: Define DEFAULT_ARCH for i386.
[binutils.git] / gas / config / tc-i386.c
blobc14f60a854cf116408b3321e68f58900424ac73f
1 /* i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989, 91, 92, 93, 94, 95, 96, 97, 98, 99, 2000
3 Free Software Foundation, Inc.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
20 02111-1307, USA. */
22 /* Intel 80386 machine specific gas.
23 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
24 x86_64 support by Jan Hubicka (jh@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
28 #include <ctype.h>
30 #include "as.h"
31 #include "subsegs.h"
32 #include "dwarf2dbg.h"
33 #include "opcode/i386.h"
35 #ifndef REGISTER_WARNINGS
36 #define REGISTER_WARNINGS 1
37 #endif
39 #ifndef INFER_ADDR_PREFIX
40 #define INFER_ADDR_PREFIX 1
41 #endif
43 #ifndef SCALE1_WHEN_NO_INDEX
44 /* Specifying a scale factor besides 1 when there is no index is
45 futile. eg. `mov (%ebx,2),%al' does exactly the same as
46 `mov (%ebx),%al'. To slavishly follow what the programmer
47 specified, set SCALE1_WHEN_NO_INDEX to 0. */
48 #define SCALE1_WHEN_NO_INDEX 1
49 #endif
51 #define true 1
52 #define false 0
54 static unsigned int mode_from_disp_size PARAMS ((unsigned int));
55 static int fits_in_signed_byte PARAMS ((offsetT));
56 static int fits_in_unsigned_byte PARAMS ((offsetT));
57 static int fits_in_unsigned_word PARAMS ((offsetT));
58 static int fits_in_signed_word PARAMS ((offsetT));
59 static int fits_in_unsigned_long PARAMS ((offsetT));
60 static int fits_in_signed_long PARAMS ((offsetT));
61 static int smallest_imm_type PARAMS ((offsetT));
62 static offsetT offset_in_range PARAMS ((offsetT, int));
63 static int add_prefix PARAMS ((unsigned int));
64 static void set_code_flag PARAMS ((int));
65 static void set_16bit_gcc_code_flag PARAMS ((int));
66 static void set_intel_syntax PARAMS ((int));
67 static void set_cpu_arch PARAMS ((int));
69 #ifdef BFD_ASSEMBLER
70 static bfd_reloc_code_real_type reloc
71 PARAMS ((int, int, int, bfd_reloc_code_real_type));
72 #endif
74 #ifndef DEFAULT_ARCH
75 #define DEFAULT_ARCH "i386"
76 #endif
77 static char *default_arch = DEFAULT_ARCH;
79 /* 'md_assemble ()' gathers together information and puts it into a
80 i386_insn. */
82 union i386_op
84 expressionS *disps;
85 expressionS *imms;
86 const reg_entry *regs;
89 struct _i386_insn
91 /* TM holds the template for the insn were currently assembling. */
92 template tm;
94 /* SUFFIX holds the instruction mnemonic suffix if given.
95 (e.g. 'l' for 'movl') */
96 char suffix;
98 /* OPERANDS gives the number of given operands. */
99 unsigned int operands;
101 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
102 of given register, displacement, memory operands and immediate
103 operands. */
104 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
106 /* TYPES [i] is the type (see above #defines) which tells us how to
107 use OP[i] for the corresponding operand. */
108 unsigned int types[MAX_OPERANDS];
110 /* Displacement expression, immediate expression, or register for each
111 operand. */
112 union i386_op op[MAX_OPERANDS];
114 /* Flags for operands. */
115 unsigned int flags[MAX_OPERANDS];
116 #define Operand_PCrel 1
118 /* Relocation type for operand */
119 #ifdef BFD_ASSEMBLER
120 enum bfd_reloc_code_real disp_reloc[MAX_OPERANDS];
121 #else
122 int disp_reloc[MAX_OPERANDS];
123 #endif
125 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
126 the base index byte below. */
127 const reg_entry *base_reg;
128 const reg_entry *index_reg;
129 unsigned int log2_scale_factor;
131 /* SEG gives the seg_entries of this insn. They are zero unless
132 explicit segment overrides are given. */
133 const seg_entry *seg[2];
135 /* PREFIX holds all the given prefix opcodes (usually null).
136 PREFIXES is the number of prefix opcodes. */
137 unsigned int prefixes;
138 unsigned char prefix[MAX_PREFIXES];
140 /* RM and SIB are the modrm byte and the sib byte where the
141 addressing modes of this insn are encoded. */
143 modrm_byte rm;
144 rex_byte rex;
145 sib_byte sib;
148 typedef struct _i386_insn i386_insn;
150 /* List of chars besides those in app.c:symbol_chars that can start an
151 operand. Used to prevent the scrubber eating vital white-space. */
152 #ifdef LEX_AT
153 const char extra_symbol_chars[] = "*%-(@";
154 #else
155 const char extra_symbol_chars[] = "*%-(";
156 #endif
158 /* This array holds the chars that always start a comment. If the
159 pre-processor is disabled, these aren't very useful. */
160 #if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX) && !defined(TE_FreeBSD))
161 /* Putting '/' here makes it impossible to use the divide operator.
162 However, we need it for compatibility with SVR4 systems. */
163 const char comment_chars[] = "#/";
164 #define PREFIX_SEPARATOR '\\'
165 #else
166 const char comment_chars[] = "#";
167 #define PREFIX_SEPARATOR '/'
168 #endif
170 /* This array holds the chars that only start a comment at the beginning of
171 a line. If the line seems to have the form '# 123 filename'
172 .line and .file directives will appear in the pre-processed output.
173 Note that input_file.c hand checks for '#' at the beginning of the
174 first line of the input file. This is because the compiler outputs
175 #NO_APP at the beginning of its output.
176 Also note that comments started like this one will always work if
177 '/' isn't otherwise defined. */
178 #if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX) && !defined(TE_FreeBSD))
179 const char line_comment_chars[] = "";
180 #else
181 const char line_comment_chars[] = "/";
182 #endif
184 const char line_separator_chars[] = ";";
186 /* Chars that can be used to separate mant from exp in floating point
187 nums. */
188 const char EXP_CHARS[] = "eE";
190 /* Chars that mean this number is a floating point constant
191 As in 0f12.456
192 or 0d1.2345e12. */
193 const char FLT_CHARS[] = "fFdDxX";
195 /* Tables for lexical analysis. */
196 static char mnemonic_chars[256];
197 static char register_chars[256];
198 static char operand_chars[256];
199 static char identifier_chars[256];
200 static char digit_chars[256];
202 /* Lexical macros. */
203 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
204 #define is_operand_char(x) (operand_chars[(unsigned char) x])
205 #define is_register_char(x) (register_chars[(unsigned char) x])
206 #define is_space_char(x) ((x) == ' ')
207 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
208 #define is_digit_char(x) (digit_chars[(unsigned char) x])
210 /* All non-digit non-letter charcters that may occur in an operand. */
211 static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
213 /* md_assemble() always leaves the strings it's passed unaltered. To
214 effect this we maintain a stack of saved characters that we've smashed
215 with '\0's (indicating end of strings for various sub-fields of the
216 assembler instruction). */
217 static char save_stack[32];
218 static char *save_stack_p;
219 #define END_STRING_AND_SAVE(s) \
220 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
221 #define RESTORE_END_STRING(s) \
222 do { *(s) = *--save_stack_p; } while (0)
224 /* The instruction we're assembling. */
225 static i386_insn i;
227 /* Possible templates for current insn. */
228 static const templates *current_templates;
230 /* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
231 static expressionS disp_expressions[2], im_expressions[2];
233 /* Current operand we are working on. */
234 static int this_operand;
236 /* We support four different modes. FLAG_CODE variable is used to distinguish
237 these. */
239 enum flag_code {
240 CODE_32BIT,
241 CODE_16BIT,
242 CODE_64BIT };
244 static enum flag_code flag_code;
245 static int use_rela_relocations = 0;
247 /* The names used to print error messages. */
248 static const char *flag_code_names[] =
250 "32",
251 "16",
252 "64"
255 /* 1 for intel syntax,
256 0 if att syntax. */
257 static int intel_syntax = 0;
259 /* 1 if register prefix % not required. */
260 static int allow_naked_reg = 0;
262 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
263 leave, push, and pop instructions so that gcc has the same stack
264 frame as in 32 bit mode. */
265 static char stackop_size = '\0';
267 /* Non-zero to quieten some warnings. */
268 static int quiet_warnings = 0;
270 /* CPU name. */
271 static const char *cpu_arch_name = NULL;
273 /* CPU feature flags. */
274 static unsigned int cpu_arch_flags = CpuUnknownFlags|CpuNo64;
276 /* Interface to relax_segment.
277 There are 2 relax states for 386 jump insns: one for conditional &
278 one for unconditional jumps. This is because these two types of
279 jumps add different sizes to frags when we're figuring out what
280 sort of jump to choose to reach a given label. */
282 /* Types. */
283 #define COND_JUMP 1
284 #define UNCOND_JUMP 2
285 /* Sizes. */
286 #define CODE16 1
287 #define SMALL 0
288 #define SMALL16 (SMALL|CODE16)
289 #define BIG 2
290 #define BIG16 (BIG|CODE16)
292 #ifndef INLINE
293 #ifdef __GNUC__
294 #define INLINE __inline__
295 #else
296 #define INLINE
297 #endif
298 #endif
300 #define ENCODE_RELAX_STATE(type,size) \
301 ((relax_substateT) ((type<<2) | (size)))
302 #define SIZE_FROM_RELAX_STATE(s) \
303 ( (((s) & 0x3) == BIG ? 4 : (((s) & 0x3) == BIG16 ? 2 : 1)) )
305 /* This table is used by relax_frag to promote short jumps to long
306 ones where necessary. SMALL (short) jumps may be promoted to BIG
307 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
308 don't allow a short jump in a 32 bit code segment to be promoted to
309 a 16 bit offset jump because it's slower (requires data size
310 prefix), and doesn't work, unless the destination is in the bottom
311 64k of the code segment (The top 16 bits of eip are zeroed). */
313 const relax_typeS md_relax_table[] =
315 /* The fields are:
316 1) most positive reach of this state,
317 2) most negative reach of this state,
318 3) how many bytes this mode will add to the size of the current frag
319 4) which index into the table to try if we can't fit into this one. */
320 {1, 1, 0, 0},
321 {1, 1, 0, 0},
322 {1, 1, 0, 0},
323 {1, 1, 0, 0},
325 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
326 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
327 /* dword conditionals adds 4 bytes to frag:
328 1 extra opcode byte, 3 extra displacement bytes. */
329 {0, 0, 4, 0},
330 /* word conditionals add 2 bytes to frag:
331 1 extra opcode byte, 1 extra displacement byte. */
332 {0, 0, 2, 0},
334 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
335 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
336 /* dword jmp adds 3 bytes to frag:
337 0 extra opcode bytes, 3 extra displacement bytes. */
338 {0, 0, 3, 0},
339 /* word jmp adds 1 byte to frag:
340 0 extra opcode bytes, 1 extra displacement byte. */
341 {0, 0, 1, 0}
345 static const arch_entry cpu_arch[] = {
346 {"i8086", Cpu086 },
347 {"i186", Cpu086|Cpu186 },
348 {"i286", Cpu086|Cpu186|Cpu286 },
349 {"i386", Cpu086|Cpu186|Cpu286|Cpu386 },
350 {"i486", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486 },
351 {"i586", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuMMX },
352 {"i686", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuSSE },
353 {"pentium", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuMMX },
354 {"pentiumpro",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuSSE },
355 {"pentium4", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuSSE|CpuSSE2 },
356 {"k6", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow },
357 {"athlon", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuMMX|Cpu3dnow },
358 {"sledgehammer",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuSledgehammer|CpuMMX|Cpu3dnow|CpuSSE|CpuSSE2 },
359 {NULL, 0 }
362 void
363 i386_align_code (fragP, count)
364 fragS *fragP;
365 int count;
367 /* Various efficient no-op patterns for aligning code labels.
368 Note: Don't try to assemble the instructions in the comments.
369 0L and 0w are not legal. */
370 static const char f32_1[] =
371 {0x90}; /* nop */
372 static const char f32_2[] =
373 {0x89,0xf6}; /* movl %esi,%esi */
374 static const char f32_3[] =
375 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
376 static const char f32_4[] =
377 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
378 static const char f32_5[] =
379 {0x90, /* nop */
380 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
381 static const char f32_6[] =
382 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
383 static const char f32_7[] =
384 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
385 static const char f32_8[] =
386 {0x90, /* nop */
387 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
388 static const char f32_9[] =
389 {0x89,0xf6, /* movl %esi,%esi */
390 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
391 static const char f32_10[] =
392 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
393 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
394 static const char f32_11[] =
395 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
396 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
397 static const char f32_12[] =
398 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
399 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
400 static const char f32_13[] =
401 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
402 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
403 static const char f32_14[] =
404 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
405 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
406 static const char f32_15[] =
407 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
408 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
409 static const char f16_3[] =
410 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
411 static const char f16_4[] =
412 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
413 static const char f16_5[] =
414 {0x90, /* nop */
415 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
416 static const char f16_6[] =
417 {0x89,0xf6, /* mov %si,%si */
418 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
419 static const char f16_7[] =
420 {0x8d,0x74,0x00, /* lea 0(%si),%si */
421 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
422 static const char f16_8[] =
423 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
424 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
425 static const char *const f32_patt[] = {
426 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
427 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15
429 static const char *const f16_patt[] = {
430 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8,
431 f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15
434 /* ??? We can't use these fillers for x86_64, since they often kills the
435 upper halves. Solve later. */
436 if (flag_code == CODE_64BIT)
437 count = 1;
439 if (count > 0 && count <= 15)
441 if (flag_code == CODE_16BIT)
443 memcpy (fragP->fr_literal + fragP->fr_fix,
444 f16_patt[count - 1], count);
445 if (count > 8)
446 /* Adjust jump offset. */
447 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
449 else
450 memcpy (fragP->fr_literal + fragP->fr_fix,
451 f32_patt[count - 1], count);
452 fragP->fr_var = count;
456 static char *output_invalid PARAMS ((int c));
457 static int i386_operand PARAMS ((char *operand_string));
458 static int i386_intel_operand PARAMS ((char *operand_string, int got_a_float));
459 static const reg_entry *parse_register PARAMS ((char *reg_string,
460 char **end_op));
462 #ifndef I386COFF
463 static void s_bss PARAMS ((int));
464 #endif
466 symbolS *GOT_symbol; /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
468 static INLINE unsigned int
469 mode_from_disp_size (t)
470 unsigned int t;
472 return (t & Disp8) ? 1 : (t & (Disp16 | Disp32 | Disp32S)) ? 2 : 0;
475 static INLINE int
476 fits_in_signed_byte (num)
477 offsetT num;
479 return (num >= -128) && (num <= 127);
482 static INLINE int
483 fits_in_unsigned_byte (num)
484 offsetT num;
486 return (num & 0xff) == num;
489 static INLINE int
490 fits_in_unsigned_word (num)
491 offsetT num;
493 return (num & 0xffff) == num;
496 static INLINE int
497 fits_in_signed_word (num)
498 offsetT num;
500 return (-32768 <= num) && (num <= 32767);
502 static INLINE int
503 fits_in_signed_long (num)
504 offsetT num ATTRIBUTE_UNUSED;
506 #ifndef BFD64
507 return 1;
508 #else
509 return (!(((offsetT) -1 << 31) & num)
510 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
511 #endif
512 } /* fits_in_signed_long() */
513 static INLINE int
514 fits_in_unsigned_long (num)
515 offsetT num ATTRIBUTE_UNUSED;
517 #ifndef BFD64
518 return 1;
519 #else
520 return (num & (((offsetT) 2 << 31) - 1)) == num;
521 #endif
522 } /* fits_in_unsigned_long() */
524 static int
525 smallest_imm_type (num)
526 offsetT num;
528 if (cpu_arch_flags != (Cpu086 | Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64)
529 && !(cpu_arch_flags & (CpuUnknown)))
531 /* This code is disabled on the 486 because all the Imm1 forms
532 in the opcode table are slower on the i486. They're the
533 versions with the implicitly specified single-position
534 displacement, which has another syntax if you really want to
535 use that form. */
536 if (num == 1)
537 return Imm1 | Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64;
539 return (fits_in_signed_byte (num)
540 ? (Imm8S | Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
541 : fits_in_unsigned_byte (num)
542 ? (Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
543 : (fits_in_signed_word (num) || fits_in_unsigned_word (num))
544 ? (Imm16 | Imm32 | Imm32S | Imm64)
545 : fits_in_signed_long (num)
546 ? (Imm32 | Imm32S | Imm64)
547 : fits_in_unsigned_long (num)
548 ? (Imm32 | Imm64)
549 : Imm64);
552 static offsetT
553 offset_in_range (val, size)
554 offsetT val;
555 int size;
557 addressT mask;
559 switch (size)
561 case 1: mask = ((addressT) 1 << 8) - 1; break;
562 case 2: mask = ((addressT) 1 << 16) - 1; break;
563 case 4: mask = ((addressT) 2 << 31) - 1; break;
564 #ifdef BFD64
565 case 8: mask = ((addressT) 2 << 63) - 1; break;
566 #endif
567 default: abort ();
570 /* If BFD64, sign extend val. */
571 if (!use_rela_relocations)
572 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
573 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
575 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
577 char buf1[40], buf2[40];
579 sprint_value (buf1, val);
580 sprint_value (buf2, val & mask);
581 as_warn (_("%s shortened to %s"), buf1, buf2);
583 return val & mask;
586 /* Returns 0 if attempting to add a prefix where one from the same
587 class already exists, 1 if non rep/repne added, 2 if rep/repne
588 added. */
589 static int
590 add_prefix (prefix)
591 unsigned int prefix;
593 int ret = 1;
594 int q;
596 if (prefix >= 0x40 && prefix < 0x50 && flag_code == CODE_64BIT)
597 q = REX_PREFIX;
598 else
599 switch (prefix)
601 default:
602 abort ();
604 case CS_PREFIX_OPCODE:
605 case DS_PREFIX_OPCODE:
606 case ES_PREFIX_OPCODE:
607 case FS_PREFIX_OPCODE:
608 case GS_PREFIX_OPCODE:
609 case SS_PREFIX_OPCODE:
610 q = SEG_PREFIX;
611 break;
613 case REPNE_PREFIX_OPCODE:
614 case REPE_PREFIX_OPCODE:
615 ret = 2;
616 /* fall thru */
617 case LOCK_PREFIX_OPCODE:
618 q = LOCKREP_PREFIX;
619 break;
621 case FWAIT_OPCODE:
622 q = WAIT_PREFIX;
623 break;
625 case ADDR_PREFIX_OPCODE:
626 q = ADDR_PREFIX;
627 break;
629 case DATA_PREFIX_OPCODE:
630 q = DATA_PREFIX;
631 break;
634 if (i.prefix[q])
636 as_bad (_("same type of prefix used twice"));
637 return 0;
640 i.prefixes += 1;
641 i.prefix[q] = prefix;
642 return ret;
645 static void
646 set_code_flag (value)
647 int value;
649 flag_code = value;
650 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
651 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
652 if (value == CODE_64BIT && !(cpu_arch_flags & CpuSledgehammer))
654 as_bad (_("64bit mode not supported on this CPU."));
656 if (value == CODE_32BIT && !(cpu_arch_flags & Cpu386))
658 as_bad (_("32bit mode not supported on this CPU."));
660 stackop_size = '\0';
663 static void
664 set_16bit_gcc_code_flag (new_code_flag)
665 int new_code_flag;
667 flag_code = new_code_flag;
668 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
669 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
670 stackop_size = 'l';
673 static void
674 set_intel_syntax (syntax_flag)
675 int syntax_flag;
677 /* Find out if register prefixing is specified. */
678 int ask_naked_reg = 0;
680 SKIP_WHITESPACE ();
681 if (! is_end_of_line[(unsigned char) *input_line_pointer])
683 char *string = input_line_pointer;
684 int e = get_symbol_end ();
686 if (strcmp (string, "prefix") == 0)
687 ask_naked_reg = 1;
688 else if (strcmp (string, "noprefix") == 0)
689 ask_naked_reg = -1;
690 else
691 as_bad (_("bad argument to syntax directive."));
692 *input_line_pointer = e;
694 demand_empty_rest_of_line ();
696 intel_syntax = syntax_flag;
698 if (ask_naked_reg == 0)
700 #ifdef BFD_ASSEMBLER
701 allow_naked_reg = (intel_syntax
702 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
703 #else
704 /* Conservative default. */
705 allow_naked_reg = 0;
706 #endif
708 else
709 allow_naked_reg = (ask_naked_reg < 0);
712 static void
713 set_cpu_arch (dummy)
714 int dummy ATTRIBUTE_UNUSED;
716 SKIP_WHITESPACE ();
718 if (! is_end_of_line[(unsigned char) *input_line_pointer])
720 char *string = input_line_pointer;
721 int e = get_symbol_end ();
722 int i;
724 for (i = 0; cpu_arch[i].name; i++)
726 if (strcmp (string, cpu_arch[i].name) == 0)
728 cpu_arch_name = cpu_arch[i].name;
729 cpu_arch_flags = cpu_arch[i].flags | (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
730 break;
733 if (!cpu_arch[i].name)
734 as_bad (_("no such architecture: `%s'"), string);
736 *input_line_pointer = e;
738 else
739 as_bad (_("missing cpu architecture"));
741 demand_empty_rest_of_line ();
744 const pseudo_typeS md_pseudo_table[] =
746 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
747 {"align", s_align_bytes, 0},
748 #else
749 {"align", s_align_ptwo, 0},
750 #endif
751 {"arch", set_cpu_arch, 0},
752 #ifndef I386COFF
753 {"bss", s_bss, 0},
754 #endif
755 {"ffloat", float_cons, 'f'},
756 {"dfloat", float_cons, 'd'},
757 {"tfloat", float_cons, 'x'},
758 {"value", cons, 2},
759 {"noopt", s_ignore, 0},
760 {"optim", s_ignore, 0},
761 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
762 {"code16", set_code_flag, CODE_16BIT},
763 {"code32", set_code_flag, CODE_32BIT},
764 {"code64", set_code_flag, CODE_64BIT},
765 {"intel_syntax", set_intel_syntax, 1},
766 {"att_syntax", set_intel_syntax, 0},
767 {"file", dwarf2_directive_file, 0},
768 {"loc", dwarf2_directive_loc, 0},
769 {0, 0, 0}
772 /* For interface with expression (). */
773 extern char *input_line_pointer;
775 /* Hash table for instruction mnemonic lookup. */
776 static struct hash_control *op_hash;
778 /* Hash table for register lookup. */
779 static struct hash_control *reg_hash;
781 void
782 md_begin ()
784 const char *hash_err;
786 /* Initialize op_hash hash table. */
787 op_hash = hash_new ();
790 register const template *optab;
791 register templates *core_optab;
793 /* Setup for loop. */
794 optab = i386_optab;
795 core_optab = (templates *) xmalloc (sizeof (templates));
796 core_optab->start = optab;
798 while (1)
800 ++optab;
801 if (optab->name == NULL
802 || strcmp (optab->name, (optab - 1)->name) != 0)
804 /* different name --> ship out current template list;
805 add to hash table; & begin anew. */
806 core_optab->end = optab;
807 hash_err = hash_insert (op_hash,
808 (optab - 1)->name,
809 (PTR) core_optab);
810 if (hash_err)
812 as_fatal (_("Internal Error: Can't hash %s: %s"),
813 (optab - 1)->name,
814 hash_err);
816 if (optab->name == NULL)
817 break;
818 core_optab = (templates *) xmalloc (sizeof (templates));
819 core_optab->start = optab;
824 /* Initialize reg_hash hash table. */
825 reg_hash = hash_new ();
827 register const reg_entry *regtab;
829 for (regtab = i386_regtab;
830 regtab < i386_regtab + sizeof (i386_regtab) / sizeof (i386_regtab[0]);
831 regtab++)
833 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
834 if (hash_err)
835 as_fatal (_("Internal Error: Can't hash %s: %s"),
836 regtab->reg_name,
837 hash_err);
841 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
843 register int c;
844 register char *p;
846 for (c = 0; c < 256; c++)
848 if (isdigit (c))
850 digit_chars[c] = c;
851 mnemonic_chars[c] = c;
852 register_chars[c] = c;
853 operand_chars[c] = c;
855 else if (islower (c))
857 mnemonic_chars[c] = c;
858 register_chars[c] = c;
859 operand_chars[c] = c;
861 else if (isupper (c))
863 mnemonic_chars[c] = tolower (c);
864 register_chars[c] = mnemonic_chars[c];
865 operand_chars[c] = c;
868 if (isalpha (c) || isdigit (c))
869 identifier_chars[c] = c;
870 else if (c >= 128)
872 identifier_chars[c] = c;
873 operand_chars[c] = c;
877 #ifdef LEX_AT
878 identifier_chars['@'] = '@';
879 #endif
880 digit_chars['-'] = '-';
881 identifier_chars['_'] = '_';
882 identifier_chars['.'] = '.';
884 for (p = operand_special_chars; *p != '\0'; p++)
885 operand_chars[(unsigned char) *p] = *p;
888 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
889 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
891 record_alignment (text_section, 2);
892 record_alignment (data_section, 2);
893 record_alignment (bss_section, 2);
895 #endif
898 void
899 i386_print_statistics (file)
900 FILE *file;
902 hash_print_statistics (file, "i386 opcode", op_hash);
903 hash_print_statistics (file, "i386 register", reg_hash);
906 #ifdef DEBUG386
908 /* Debugging routines for md_assemble. */
909 static void pi PARAMS ((char *, i386_insn *));
910 static void pte PARAMS ((template *));
911 static void pt PARAMS ((unsigned int));
912 static void pe PARAMS ((expressionS *));
913 static void ps PARAMS ((symbolS *));
915 static void
916 pi (line, x)
917 char *line;
918 i386_insn *x;
920 unsigned int i;
922 fprintf (stdout, "%s: template ", line);
923 pte (&x->tm);
924 fprintf (stdout, " address: base %s index %s scale %x\n",
925 x->base_reg ? x->base_reg->reg_name : "none",
926 x->index_reg ? x->index_reg->reg_name : "none",
927 x->log2_scale_factor);
928 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
929 x->rm.mode, x->rm.reg, x->rm.regmem);
930 fprintf (stdout, " sib: base %x index %x scale %x\n",
931 x->sib.base, x->sib.index, x->sib.scale);
932 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
933 x->rex.mode64, x->rex.extX, x->rex.extY, x->rex.extZ);
934 for (i = 0; i < x->operands; i++)
936 fprintf (stdout, " #%d: ", i + 1);
937 pt (x->types[i]);
938 fprintf (stdout, "\n");
939 if (x->types[i]
940 & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM))
941 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
942 if (x->types[i] & Imm)
943 pe (x->op[i].imms);
944 if (x->types[i] & Disp)
945 pe (x->op[i].disps);
949 static void
950 pte (t)
951 template *t;
953 unsigned int i;
954 fprintf (stdout, " %d operands ", t->operands);
955 fprintf (stdout, "opcode %x ", t->base_opcode);
956 if (t->extension_opcode != None)
957 fprintf (stdout, "ext %x ", t->extension_opcode);
958 if (t->opcode_modifier & D)
959 fprintf (stdout, "D");
960 if (t->opcode_modifier & W)
961 fprintf (stdout, "W");
962 fprintf (stdout, "\n");
963 for (i = 0; i < t->operands; i++)
965 fprintf (stdout, " #%d type ", i + 1);
966 pt (t->operand_types[i]);
967 fprintf (stdout, "\n");
971 static void
972 pe (e)
973 expressionS *e;
975 fprintf (stdout, " operation %d\n", e->X_op);
976 fprintf (stdout, " add_number %ld (%lx)\n",
977 (long) e->X_add_number, (long) e->X_add_number);
978 if (e->X_add_symbol)
980 fprintf (stdout, " add_symbol ");
981 ps (e->X_add_symbol);
982 fprintf (stdout, "\n");
984 if (e->X_op_symbol)
986 fprintf (stdout, " op_symbol ");
987 ps (e->X_op_symbol);
988 fprintf (stdout, "\n");
992 static void
993 ps (s)
994 symbolS *s;
996 fprintf (stdout, "%s type %s%s",
997 S_GET_NAME (s),
998 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
999 segment_name (S_GET_SEGMENT (s)));
1002 struct type_name
1004 unsigned int mask;
1005 char *tname;
1008 type_names[] =
1010 { Reg8, "r8" },
1011 { Reg16, "r16" },
1012 { Reg32, "r32" },
1013 { Reg64, "r64" },
1014 { Imm8, "i8" },
1015 { Imm8S, "i8s" },
1016 { Imm16, "i16" },
1017 { Imm32, "i32" },
1018 { Imm32S, "i32s" },
1019 { Imm64, "i64" },
1020 { Imm1, "i1" },
1021 { BaseIndex, "BaseIndex" },
1022 { Disp8, "d8" },
1023 { Disp16, "d16" },
1024 { Disp32, "d32" },
1025 { Disp32S, "d32s" },
1026 { Disp64, "d64" },
1027 { InOutPortReg, "InOutPortReg" },
1028 { ShiftCount, "ShiftCount" },
1029 { Control, "control reg" },
1030 { Test, "test reg" },
1031 { Debug, "debug reg" },
1032 { FloatReg, "FReg" },
1033 { FloatAcc, "FAcc" },
1034 { SReg2, "SReg2" },
1035 { SReg3, "SReg3" },
1036 { Acc, "Acc" },
1037 { JumpAbsolute, "Jump Absolute" },
1038 { RegMMX, "rMMX" },
1039 { RegXMM, "rXMM" },
1040 { EsSeg, "es" },
1041 { 0, "" }
1044 static void
1045 pt (t)
1046 unsigned int t;
1048 register struct type_name *ty;
1050 for (ty = type_names; ty->mask; ty++)
1051 if (t & ty->mask)
1052 fprintf (stdout, "%s, ", ty->tname);
1053 fflush (stdout);
1056 #endif /* DEBUG386 */
1059 tc_i386_force_relocation (fixp)
1060 struct fix *fixp;
1062 #ifdef BFD_ASSEMBLER
1063 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1064 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1065 return 1;
1066 return 0;
1067 #else
1068 /* For COFF. */
1069 return fixp->fx_r_type == 7;
1070 #endif
1073 #ifdef BFD_ASSEMBLER
1075 static bfd_reloc_code_real_type
1076 reloc (size, pcrel, sign, other)
1077 int size;
1078 int pcrel;
1079 int sign;
1080 bfd_reloc_code_real_type other;
1082 if (other != NO_RELOC)
1083 return other;
1085 if (pcrel)
1087 if (!sign)
1088 as_bad(_("There are no unsigned pc-relative relocations"));
1089 switch (size)
1091 case 1: return BFD_RELOC_8_PCREL;
1092 case 2: return BFD_RELOC_16_PCREL;
1093 case 4: return BFD_RELOC_32_PCREL;
1095 as_bad (_("can not do %d byte pc-relative relocation"), size);
1097 else
1099 if (sign)
1100 switch (size)
1102 case 4: return BFD_RELOC_X86_64_32S;
1104 else
1105 switch (size)
1107 case 1: return BFD_RELOC_8;
1108 case 2: return BFD_RELOC_16;
1109 case 4: return BFD_RELOC_32;
1110 case 8: return BFD_RELOC_64;
1112 as_bad (_("can not do %s %d byte relocation"),
1113 sign ? "signed" : "unsigned", size);
1116 abort();
1117 return BFD_RELOC_NONE;
1120 /* Here we decide which fixups can be adjusted to make them relative to
1121 the beginning of the section instead of the symbol. Basically we need
1122 to make sure that the dynamic relocations are done correctly, so in
1123 some cases we force the original symbol to be used. */
1126 tc_i386_fix_adjustable (fixP)
1127 fixS *fixP;
1129 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1130 /* Prevent all adjustments to global symbols, or else dynamic
1131 linking will not work correctly. */
1132 if (S_IS_EXTERNAL (fixP->fx_addsy)
1133 || S_IS_WEAK (fixP->fx_addsy))
1134 return 0;
1135 #endif
1136 /* adjust_reloc_syms doesn't know about the GOT. */
1137 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
1138 || fixP->fx_r_type == BFD_RELOC_386_PLT32
1139 || fixP->fx_r_type == BFD_RELOC_386_GOT32
1140 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
1141 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
1142 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1143 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1144 return 0;
1145 return 1;
1147 #else
1148 #define reloc(SIZE,PCREL,SIGN,OTHER) 0
1149 #define BFD_RELOC_16 0
1150 #define BFD_RELOC_32 0
1151 #define BFD_RELOC_16_PCREL 0
1152 #define BFD_RELOC_32_PCREL 0
1153 #define BFD_RELOC_386_PLT32 0
1154 #define BFD_RELOC_386_GOT32 0
1155 #define BFD_RELOC_386_GOTOFF 0
1156 #define BFD_RELOC_X86_64_PLT32 0
1157 #define BFD_RELOC_X86_64_GOT32 0
1158 #define BFD_RELOC_X86_64_GOTPCREL 0
1159 #endif
1161 static int intel_float_operand PARAMS ((char *mnemonic));
1163 static int
1164 intel_float_operand (mnemonic)
1165 char *mnemonic;
1167 if (mnemonic[0] == 'f' && mnemonic[1] == 'i')
1168 return 2;
1170 if (mnemonic[0] == 'f')
1171 return 1;
1173 return 0;
1176 /* This is the guts of the machine-dependent assembler. LINE points to a
1177 machine dependent instruction. This function is supposed to emit
1178 the frags/bytes it assembles to. */
1180 void
1181 md_assemble (line)
1182 char *line;
1184 /* Points to template once we've found it. */
1185 const template *t;
1187 /* Count the size of the instruction generated. */
1188 int insn_size = 0;
1190 int j;
1192 char mnemonic[MAX_MNEM_SIZE];
1194 /* Initialize globals. */
1195 memset (&i, '\0', sizeof (i));
1196 for (j = 0; j < MAX_OPERANDS; j++)
1197 i.disp_reloc[j] = NO_RELOC;
1198 memset (disp_expressions, '\0', sizeof (disp_expressions));
1199 memset (im_expressions, '\0', sizeof (im_expressions));
1200 save_stack_p = save_stack;
1202 /* First parse an instruction mnemonic & call i386_operand for the operands.
1203 We assume that the scrubber has arranged it so that line[0] is the valid
1204 start of a (possibly prefixed) mnemonic. */
1206 char *l = line;
1207 char *token_start = l;
1208 char *mnem_p;
1210 /* Non-zero if we found a prefix only acceptable with string insns. */
1211 const char *expecting_string_instruction = NULL;
1213 while (1)
1215 mnem_p = mnemonic;
1216 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
1218 mnem_p++;
1219 if (mnem_p >= mnemonic + sizeof (mnemonic))
1221 as_bad (_("no such instruction: `%s'"), token_start);
1222 return;
1224 l++;
1226 if (!is_space_char (*l)
1227 && *l != END_OF_INSN
1228 && *l != PREFIX_SEPARATOR)
1230 as_bad (_("invalid character %s in mnemonic"),
1231 output_invalid (*l));
1232 return;
1234 if (token_start == l)
1236 if (*l == PREFIX_SEPARATOR)
1237 as_bad (_("expecting prefix; got nothing"));
1238 else
1239 as_bad (_("expecting mnemonic; got nothing"));
1240 return;
1243 /* Look up instruction (or prefix) via hash table. */
1244 current_templates = hash_find (op_hash, mnemonic);
1246 if (*l != END_OF_INSN
1247 && (! is_space_char (*l) || l[1] != END_OF_INSN)
1248 && current_templates
1249 && (current_templates->start->opcode_modifier & IsPrefix))
1251 /* If we are in 16-bit mode, do not allow addr16 or data16.
1252 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1253 if ((current_templates->start->opcode_modifier & (Size16 | Size32))
1254 && (((current_templates->start->opcode_modifier & Size32) != 0)
1255 ^ (flag_code == CODE_16BIT)))
1257 as_bad (_("redundant %s prefix"),
1258 current_templates->start->name);
1259 return;
1261 /* Add prefix, checking for repeated prefixes. */
1262 switch (add_prefix (current_templates->start->base_opcode))
1264 case 0:
1265 return;
1266 case 2:
1267 expecting_string_instruction = current_templates->start->name;
1268 break;
1270 /* Skip past PREFIX_SEPARATOR and reset token_start. */
1271 token_start = ++l;
1273 else
1274 break;
1277 if (!current_templates)
1279 /* See if we can get a match by trimming off a suffix. */
1280 switch (mnem_p[-1])
1282 case WORD_MNEM_SUFFIX:
1283 case BYTE_MNEM_SUFFIX:
1284 case QWORD_MNEM_SUFFIX:
1285 i.suffix = mnem_p[-1];
1286 mnem_p[-1] = '\0';
1287 current_templates = hash_find (op_hash, mnemonic);
1288 break;
1289 case SHORT_MNEM_SUFFIX:
1290 case LONG_MNEM_SUFFIX:
1291 if (!intel_syntax)
1293 i.suffix = mnem_p[-1];
1294 mnem_p[-1] = '\0';
1295 current_templates = hash_find (op_hash, mnemonic);
1297 break;
1299 /* Intel Syntax. */
1300 case 'd':
1301 if (intel_syntax)
1303 if (intel_float_operand (mnemonic))
1304 i.suffix = SHORT_MNEM_SUFFIX;
1305 else
1306 i.suffix = LONG_MNEM_SUFFIX;
1307 mnem_p[-1] = '\0';
1308 current_templates = hash_find (op_hash, mnemonic);
1310 break;
1312 if (!current_templates)
1314 as_bad (_("no such instruction: `%s'"), token_start);
1315 return;
1319 /* Check if instruction is supported on specified architecture. */
1320 if (cpu_arch_flags != 0)
1322 if ((current_templates->start->cpu_flags & ~(Cpu64 | CpuNo64))
1323 & ~(cpu_arch_flags & ~(Cpu64 | CpuNo64)))
1325 as_warn (_("`%s' is not supported on `%s'"),
1326 current_templates->start->name, cpu_arch_name);
1328 else if ((Cpu386 & ~cpu_arch_flags) && (flag_code != CODE_16BIT))
1330 as_warn (_("use .code16 to ensure correct addressing mode"));
1334 /* Check for rep/repne without a string instruction. */
1335 if (expecting_string_instruction
1336 && !(current_templates->start->opcode_modifier & IsString))
1338 as_bad (_("expecting string instruction after `%s'"),
1339 expecting_string_instruction);
1340 return;
1343 /* There may be operands to parse. */
1344 if (*l != END_OF_INSN)
1346 /* 1 if operand is pending after ','. */
1347 unsigned int expecting_operand = 0;
1349 /* Non-zero if operand parens not balanced. */
1350 unsigned int paren_not_balanced;
1354 /* Skip optional white space before operand. */
1355 if (is_space_char (*l))
1356 ++l;
1357 if (!is_operand_char (*l) && *l != END_OF_INSN)
1359 as_bad (_("invalid character %s before operand %d"),
1360 output_invalid (*l),
1361 i.operands + 1);
1362 return;
1364 token_start = l; /* after white space */
1365 paren_not_balanced = 0;
1366 while (paren_not_balanced || *l != ',')
1368 if (*l == END_OF_INSN)
1370 if (paren_not_balanced)
1372 if (!intel_syntax)
1373 as_bad (_("unbalanced parenthesis in operand %d."),
1374 i.operands + 1);
1375 else
1376 as_bad (_("unbalanced brackets in operand %d."),
1377 i.operands + 1);
1378 return;
1380 else
1381 break; /* we are done */
1383 else if (!is_operand_char (*l) && !is_space_char (*l))
1385 as_bad (_("invalid character %s in operand %d"),
1386 output_invalid (*l),
1387 i.operands + 1);
1388 return;
1390 if (!intel_syntax)
1392 if (*l == '(')
1393 ++paren_not_balanced;
1394 if (*l == ')')
1395 --paren_not_balanced;
1397 else
1399 if (*l == '[')
1400 ++paren_not_balanced;
1401 if (*l == ']')
1402 --paren_not_balanced;
1404 l++;
1406 if (l != token_start)
1407 { /* Yes, we've read in another operand. */
1408 unsigned int operand_ok;
1409 this_operand = i.operands++;
1410 if (i.operands > MAX_OPERANDS)
1412 as_bad (_("spurious operands; (%d operands/instruction max)"),
1413 MAX_OPERANDS);
1414 return;
1416 /* Now parse operand adding info to 'i' as we go along. */
1417 END_STRING_AND_SAVE (l);
1419 if (intel_syntax)
1420 operand_ok =
1421 i386_intel_operand (token_start,
1422 intel_float_operand (mnemonic));
1423 else
1424 operand_ok = i386_operand (token_start);
1426 RESTORE_END_STRING (l);
1427 if (!operand_ok)
1428 return;
1430 else
1432 if (expecting_operand)
1434 expecting_operand_after_comma:
1435 as_bad (_("expecting operand after ','; got nothing"));
1436 return;
1438 if (*l == ',')
1440 as_bad (_("expecting operand before ','; got nothing"));
1441 return;
1445 /* Now *l must be either ',' or END_OF_INSN. */
1446 if (*l == ',')
1448 if (*++l == END_OF_INSN)
1450 /* Just skip it, if it's \n complain. */
1451 goto expecting_operand_after_comma;
1453 expecting_operand = 1;
1456 while (*l != END_OF_INSN);
1460 /* Now we've parsed the mnemonic into a set of templates, and have the
1461 operands at hand.
1463 Next, we find a template that matches the given insn,
1464 making sure the overlap of the given operands types is consistent
1465 with the template operand types. */
1467 #define MATCH(overlap, given, template) \
1468 ((overlap & ~JumpAbsolute) \
1469 && ((given) & (BaseIndex|JumpAbsolute)) == ((overlap) & (BaseIndex|JumpAbsolute)))
1471 /* If given types r0 and r1 are registers they must be of the same type
1472 unless the expected operand type register overlap is null.
1473 Note that Acc in a template matches every size of reg. */
1474 #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
1475 ( ((g0) & Reg) == 0 || ((g1) & Reg) == 0 || \
1476 ((g0) & Reg) == ((g1) & Reg) || \
1477 ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
1480 register unsigned int overlap0, overlap1;
1481 unsigned int overlap2;
1482 unsigned int found_reverse_match;
1483 int suffix_check;
1485 /* All intel opcodes have reversed operands except for "bound" and
1486 "enter". We also don't reverse intersegment "jmp" and "call"
1487 instructions with 2 immediate operands so that the immediate segment
1488 precedes the offset, as it does when in AT&T mode. "enter" and the
1489 intersegment "jmp" and "call" instructions are the only ones that
1490 have two immediate operands. */
1491 if (intel_syntax && i.operands > 1
1492 && (strcmp (mnemonic, "bound") != 0)
1493 && !((i.types[0] & Imm) && (i.types[1] & Imm)))
1495 union i386_op temp_op;
1496 unsigned int temp_type;
1497 #ifdef BFD_ASSEMBLER
1498 enum bfd_reloc_code_real temp_reloc;
1499 #else
1500 int temp_reloc;
1501 #endif
1502 int xchg1 = 0;
1503 int xchg2 = 0;
1505 if (i.operands == 2)
1507 xchg1 = 0;
1508 xchg2 = 1;
1510 else if (i.operands == 3)
1512 xchg1 = 0;
1513 xchg2 = 2;
1515 temp_type = i.types[xchg2];
1516 i.types[xchg2] = i.types[xchg1];
1517 i.types[xchg1] = temp_type;
1518 temp_op = i.op[xchg2];
1519 i.op[xchg2] = i.op[xchg1];
1520 i.op[xchg1] = temp_op;
1521 temp_reloc = i.disp_reloc[xchg2];
1522 i.disp_reloc[xchg2] = i.disp_reloc[xchg1];
1523 i.disp_reloc[xchg1] = temp_reloc;
1525 if (i.mem_operands == 2)
1527 const seg_entry *temp_seg;
1528 temp_seg = i.seg[0];
1529 i.seg[0] = i.seg[1];
1530 i.seg[1] = temp_seg;
1534 if (i.imm_operands)
1536 /* Try to ensure constant immediates are represented in the smallest
1537 opcode possible. */
1538 char guess_suffix = 0;
1539 int op;
1541 if (i.suffix)
1542 guess_suffix = i.suffix;
1543 else if (i.reg_operands)
1545 /* Figure out a suffix from the last register operand specified.
1546 We can't do this properly yet, ie. excluding InOutPortReg,
1547 but the following works for instructions with immediates.
1548 In any case, we can't set i.suffix yet. */
1549 for (op = i.operands; --op >= 0;)
1550 if (i.types[op] & Reg)
1552 if (i.types[op] & Reg8)
1553 guess_suffix = BYTE_MNEM_SUFFIX;
1554 else if (i.types[op] & Reg16)
1555 guess_suffix = WORD_MNEM_SUFFIX;
1556 else if (i.types[op] & Reg32)
1557 guess_suffix = LONG_MNEM_SUFFIX;
1558 else if (i.types[op] & Reg64)
1559 guess_suffix = QWORD_MNEM_SUFFIX;
1560 break;
1563 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
1564 guess_suffix = WORD_MNEM_SUFFIX;
1566 for (op = i.operands; --op >= 0;)
1567 if (i.types[op] & Imm)
1569 switch (i.op[op].imms->X_op)
1571 case O_constant:
1572 /* If a suffix is given, this operand may be shortened. */
1573 switch (guess_suffix)
1575 case LONG_MNEM_SUFFIX:
1576 i.types[op] |= Imm32 | Imm64;
1577 break;
1578 case WORD_MNEM_SUFFIX:
1579 i.types[op] |= Imm16 | Imm32S | Imm32 | Imm64;
1580 break;
1581 case BYTE_MNEM_SUFFIX:
1582 i.types[op] |= Imm16 | Imm8 | Imm8S | Imm32S | Imm32 | Imm64;
1583 break;
1586 /* If this operand is at most 16 bits, convert it to a
1587 signed 16 bit number before trying to see whether it will
1588 fit in an even smaller size. This allows a 16-bit operand
1589 such as $0xffe0 to be recognised as within Imm8S range. */
1590 if ((i.types[op] & Imm16)
1591 && (i.op[op].imms->X_add_number & ~(offsetT)0xffff) == 0)
1593 i.op[op].imms->X_add_number =
1594 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
1596 if ((i.types[op] & Imm32)
1597 && (i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1)) == 0)
1599 i.op[op].imms->X_add_number =
1600 (i.op[op].imms->X_add_number ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
1602 i.types[op] |= smallest_imm_type (i.op[op].imms->X_add_number);
1603 /* We must avoid matching of Imm32 templates when 64bit only immediate is available. */
1604 if (guess_suffix == QWORD_MNEM_SUFFIX)
1605 i.types[op] &= ~Imm32;
1606 break;
1607 case O_absent:
1608 case O_register:
1609 abort();
1610 /* Symbols and expressions. */
1611 default:
1612 /* Convert symbolic operand to proper sizes for matching. */
1613 switch (guess_suffix)
1615 case QWORD_MNEM_SUFFIX:
1616 i.types[op] = Imm64 | Imm32S;
1617 break;
1618 case LONG_MNEM_SUFFIX:
1619 i.types[op] = Imm32 | Imm64;
1620 break;
1621 case WORD_MNEM_SUFFIX:
1622 i.types[op] = Imm16 | Imm32 | Imm64;
1623 break;
1624 break;
1625 case BYTE_MNEM_SUFFIX:
1626 i.types[op] = Imm8 | Imm8S | Imm16 | Imm32S | Imm32;
1627 break;
1628 break;
1630 break;
1635 if (i.disp_operands)
1637 /* Try to use the smallest displacement type too. */
1638 int op;
1640 for (op = i.operands; --op >= 0;)
1641 if ((i.types[op] & Disp)
1642 && i.op[op].imms->X_op == O_constant)
1644 offsetT disp = i.op[op].disps->X_add_number;
1646 if (i.types[op] & Disp16)
1648 /* We know this operand is at most 16 bits, so
1649 convert to a signed 16 bit number before trying
1650 to see whether it will fit in an even smaller
1651 size. */
1653 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
1655 else if (i.types[op] & Disp32)
1657 /* We know this operand is at most 32 bits, so convert to a
1658 signed 32 bit number before trying to see whether it will
1659 fit in an even smaller size. */
1660 disp &= (((offsetT) 2 << 31) - 1);
1661 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
1663 if (flag_code == CODE_64BIT)
1665 if (fits_in_signed_long (disp))
1666 i.types[op] |= Disp32S;
1667 if (fits_in_unsigned_long (disp))
1668 i.types[op] |= Disp32;
1670 if ((i.types[op] & (Disp32 | Disp32S | Disp16))
1671 && fits_in_signed_byte (disp))
1672 i.types[op] |= Disp8;
1676 overlap0 = 0;
1677 overlap1 = 0;
1678 overlap2 = 0;
1679 found_reverse_match = 0;
1680 suffix_check = (i.suffix == BYTE_MNEM_SUFFIX
1681 ? No_bSuf
1682 : (i.suffix == WORD_MNEM_SUFFIX
1683 ? No_wSuf
1684 : (i.suffix == SHORT_MNEM_SUFFIX
1685 ? No_sSuf
1686 : (i.suffix == LONG_MNEM_SUFFIX
1687 ? No_lSuf
1688 : (i.suffix == QWORD_MNEM_SUFFIX
1689 ? No_qSuf
1690 : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX ? No_xSuf : 0))))));
1692 for (t = current_templates->start;
1693 t < current_templates->end;
1694 t++)
1696 /* Must have right number of operands. */
1697 if (i.operands != t->operands)
1698 continue;
1700 /* Check the suffix, except for some instructions in intel mode. */
1701 if ((t->opcode_modifier & suffix_check)
1702 && !(intel_syntax
1703 && (t->opcode_modifier & IgnoreSize))
1704 && !(intel_syntax
1705 && t->base_opcode == 0xd9
1706 && (t->extension_opcode == 5 /* 0xd9,5 "fldcw" */
1707 || t->extension_opcode == 7))) /* 0xd9,7 "f{n}stcw" */
1708 continue;
1710 else if (!t->operands)
1711 /* 0 operands always matches. */
1712 break;
1714 overlap0 = i.types[0] & t->operand_types[0];
1715 switch (t->operands)
1717 case 1:
1718 if (!MATCH (overlap0, i.types[0], t->operand_types[0]))
1719 continue;
1720 break;
1721 case 2:
1722 case 3:
1723 overlap1 = i.types[1] & t->operand_types[1];
1724 if (!MATCH (overlap0, i.types[0], t->operand_types[0])
1725 || !MATCH (overlap1, i.types[1], t->operand_types[1])
1726 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
1727 t->operand_types[0],
1728 overlap1, i.types[1],
1729 t->operand_types[1]))
1731 /* Check if other direction is valid ... */
1732 if ((t->opcode_modifier & (D|FloatD)) == 0)
1733 continue;
1735 /* Try reversing direction of operands. */
1736 overlap0 = i.types[0] & t->operand_types[1];
1737 overlap1 = i.types[1] & t->operand_types[0];
1738 if (!MATCH (overlap0, i.types[0], t->operand_types[1])
1739 || !MATCH (overlap1, i.types[1], t->operand_types[0])
1740 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
1741 t->operand_types[1],
1742 overlap1, i.types[1],
1743 t->operand_types[0]))
1745 /* Does not match either direction. */
1746 continue;
1748 /* found_reverse_match holds which of D or FloatDR
1749 we've found. */
1750 found_reverse_match = t->opcode_modifier & (D|FloatDR);
1752 /* Found a forward 2 operand match here. */
1753 else if (t->operands == 3)
1755 /* Here we make use of the fact that there are no
1756 reverse match 3 operand instructions, and all 3
1757 operand instructions only need to be checked for
1758 register consistency between operands 2 and 3. */
1759 overlap2 = i.types[2] & t->operand_types[2];
1760 if (!MATCH (overlap2, i.types[2], t->operand_types[2])
1761 || !CONSISTENT_REGISTER_MATCH (overlap1, i.types[1],
1762 t->operand_types[1],
1763 overlap2, i.types[2],
1764 t->operand_types[2]))
1766 continue;
1768 /* Found either forward/reverse 2 or 3 operand match here:
1769 slip through to break. */
1771 if (t->cpu_flags & ~cpu_arch_flags)
1773 found_reverse_match = 0;
1774 continue;
1776 /* We've found a match; break out of loop. */
1777 break;
1779 if (t == current_templates->end)
1781 /* We found no match. */
1782 as_bad (_("suffix or operands invalid for `%s'"),
1783 current_templates->start->name);
1784 return;
1787 if (!quiet_warnings)
1789 if (!intel_syntax
1790 && ((i.types[0] & JumpAbsolute)
1791 != (t->operand_types[0] & JumpAbsolute)))
1793 as_warn (_("indirect %s without `*'"), t->name);
1796 if ((t->opcode_modifier & (IsPrefix|IgnoreSize))
1797 == (IsPrefix|IgnoreSize))
1799 /* Warn them that a data or address size prefix doesn't
1800 affect assembly of the next line of code. */
1801 as_warn (_("stand-alone `%s' prefix"), t->name);
1805 /* Copy the template we found. */
1806 i.tm = *t;
1807 if (found_reverse_match)
1809 /* If we found a reverse match we must alter the opcode
1810 direction bit. found_reverse_match holds bits to change
1811 (different for int & float insns). */
1813 i.tm.base_opcode ^= found_reverse_match;
1815 i.tm.operand_types[0] = t->operand_types[1];
1816 i.tm.operand_types[1] = t->operand_types[0];
1819 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1820 if (SYSV386_COMPAT
1821 && intel_syntax
1822 && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
1823 i.tm.base_opcode ^= FloatR;
1825 if (i.tm.opcode_modifier & FWait)
1826 if (! add_prefix (FWAIT_OPCODE))
1827 return;
1829 /* Check string instruction segment overrides. */
1830 if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0)
1832 int mem_op = (i.types[0] & AnyMem) ? 0 : 1;
1833 if ((i.tm.operand_types[mem_op] & EsSeg) != 0)
1835 if (i.seg[0] != NULL && i.seg[0] != &es)
1837 as_bad (_("`%s' operand %d must use `%%es' segment"),
1838 i.tm.name,
1839 mem_op + 1);
1840 return;
1842 /* There's only ever one segment override allowed per instruction.
1843 This instruction possibly has a legal segment override on the
1844 second operand, so copy the segment to where non-string
1845 instructions store it, allowing common code. */
1846 i.seg[0] = i.seg[1];
1848 else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0)
1850 if (i.seg[1] != NULL && i.seg[1] != &es)
1852 as_bad (_("`%s' operand %d must use `%%es' segment"),
1853 i.tm.name,
1854 mem_op + 2);
1855 return;
1860 if (i.reg_operands && flag_code < CODE_64BIT)
1862 int op;
1863 for (op = i.operands; --op >= 0; )
1864 if ((i.types[op] & Reg)
1865 && (i.op[op].regs->reg_flags & (RegRex64|RegRex)))
1867 as_bad (_("Extended register `%%%s' available only in 64bit mode."),
1868 i.op[op].regs->reg_name);
1869 return;
1873 /* If matched instruction specifies an explicit instruction mnemonic
1874 suffix, use it. */
1875 if (i.tm.opcode_modifier & (Size16 | Size32 | Size64))
1877 if (i.tm.opcode_modifier & Size16)
1878 i.suffix = WORD_MNEM_SUFFIX;
1879 else if (i.tm.opcode_modifier & Size64)
1880 i.suffix = QWORD_MNEM_SUFFIX;
1881 else
1882 i.suffix = LONG_MNEM_SUFFIX;
1884 else if (i.reg_operands)
1886 /* If there's no instruction mnemonic suffix we try to invent one
1887 based on register operands. */
1888 if (!i.suffix)
1890 /* We take i.suffix from the last register operand specified,
1891 Destination register type is more significant than source
1892 register type. */
1893 int op;
1894 for (op = i.operands; --op >= 0;)
1895 if ((i.types[op] & Reg)
1896 && !(i.tm.operand_types[op] & InOutPortReg))
1898 i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX :
1899 (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX :
1900 (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX :
1901 LONG_MNEM_SUFFIX);
1902 break;
1905 else if (i.suffix == BYTE_MNEM_SUFFIX)
1907 int op;
1908 for (op = i.operands; --op >= 0;)
1910 /* If this is an eight bit register, it's OK. If it's
1911 the 16 or 32 bit version of an eight bit register,
1912 we will just use the low portion, and that's OK too. */
1913 if (i.types[op] & Reg8)
1914 continue;
1916 /* movzx and movsx should not generate this warning. */
1917 if (intel_syntax
1918 && (i.tm.base_opcode == 0xfb7
1919 || i.tm.base_opcode == 0xfb6
1920 || i.tm.base_opcode == 0x63
1921 || i.tm.base_opcode == 0xfbe
1922 || i.tm.base_opcode == 0xfbf))
1923 continue;
1925 if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4
1926 #if 0
1927 /* Check that the template allows eight bit regs
1928 This kills insns such as `orb $1,%edx', which
1929 maybe should be allowed. */
1930 && (i.tm.operand_types[op] & (Reg8|InOutPortReg))
1931 #endif
1934 /* Prohibit these changes in the 64bit mode, since
1935 the lowering is more complicated. */
1936 if (flag_code == CODE_64BIT
1937 && (i.tm.operand_types[op] & InOutPortReg) == 0)
1938 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
1939 i.op[op].regs->reg_name,
1940 i.suffix);
1941 #if REGISTER_WARNINGS
1942 if (!quiet_warnings
1943 && (i.tm.operand_types[op] & InOutPortReg) == 0)
1944 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
1945 (i.op[op].regs - (i.types[op] & Reg16 ? 8 : 16))->reg_name,
1946 i.op[op].regs->reg_name,
1947 i.suffix);
1948 #endif
1949 continue;
1951 /* Any other register is bad. */
1952 if (i.types[op] & (Reg | RegMMX | RegXMM
1953 | SReg2 | SReg3
1954 | Control | Debug | Test
1955 | FloatReg | FloatAcc))
1957 as_bad (_("`%%%s' not allowed with `%s%c'"),
1958 i.op[op].regs->reg_name,
1959 i.tm.name,
1960 i.suffix);
1961 return;
1965 else if (i.suffix == LONG_MNEM_SUFFIX)
1967 int op;
1969 for (op = i.operands; --op >= 0;)
1970 /* Reject eight bit registers, except where the template
1971 requires them. (eg. movzb) */
1972 if ((i.types[op] & Reg8) != 0
1973 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
1975 as_bad (_("`%%%s' not allowed with `%s%c'"),
1976 i.op[op].regs->reg_name,
1977 i.tm.name,
1978 i.suffix);
1979 return;
1981 /* Warn if the e prefix on a general reg is missing. */
1982 else if ((!quiet_warnings || flag_code == CODE_64BIT)
1983 && (i.types[op] & Reg16) != 0
1984 && (i.tm.operand_types[op] & (Reg32|Acc)) != 0)
1986 /* Prohibit these changes in the 64bit mode, since
1987 the lowering is more complicated. */
1988 if (flag_code == CODE_64BIT)
1989 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
1990 i.op[op].regs->reg_name,
1991 i.suffix);
1992 #if REGISTER_WARNINGS
1993 else
1994 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
1995 (i.op[op].regs + 8)->reg_name,
1996 i.op[op].regs->reg_name,
1997 i.suffix);
1998 #endif
2000 /* Warn if the r prefix on a general reg is missing. */
2001 else if ((i.types[op] & Reg64) != 0
2002 && (i.tm.operand_types[op] & (Reg32|Acc)) != 0)
2004 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2005 i.op[op].regs->reg_name,
2006 i.suffix);
2009 else if (i.suffix == QWORD_MNEM_SUFFIX)
2011 int op;
2013 for (op = i.operands; --op >= 0; )
2014 /* Reject eight bit registers, except where the template
2015 requires them. (eg. movzb) */
2016 if ((i.types[op] & Reg8) != 0
2017 && (i.tm.operand_types[op] & (Reg16|Reg32|Acc)) != 0)
2019 as_bad (_("`%%%s' not allowed with `%s%c'"),
2020 i.op[op].regs->reg_name,
2021 i.tm.name,
2022 i.suffix);
2023 return;
2025 /* Warn if the e prefix on a general reg is missing. */
2026 else if (((i.types[op] & Reg16) != 0
2027 || (i.types[op] & Reg32) != 0)
2028 && (i.tm.operand_types[op] & (Reg32|Acc)) != 0)
2030 /* Prohibit these changes in the 64bit mode, since
2031 the lowering is more complicated. */
2032 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2033 i.op[op].regs->reg_name,
2034 i.suffix);
2037 else if (i.suffix == WORD_MNEM_SUFFIX)
2039 int op;
2040 for (op = i.operands; --op >= 0;)
2041 /* Reject eight bit registers, except where the template
2042 requires them. (eg. movzb) */
2043 if ((i.types[op] & Reg8) != 0
2044 && (i.tm.operand_types[op] & (Reg16|Reg32|Acc)) != 0)
2046 as_bad (_("`%%%s' not allowed with `%s%c'"),
2047 i.op[op].regs->reg_name,
2048 i.tm.name,
2049 i.suffix);
2050 return;
2052 /* Warn if the e prefix on a general reg is present. */
2053 else if ((!quiet_warnings || flag_code == CODE_64BIT)
2054 && (i.types[op] & Reg32) != 0
2055 && (i.tm.operand_types[op] & (Reg16|Acc)) != 0)
2057 /* Prohibit these changes in the 64bit mode, since
2058 the lowering is more complicated. */
2059 if (flag_code == CODE_64BIT)
2060 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2061 i.op[op].regs->reg_name,
2062 i.suffix);
2063 else
2064 #if REGISTER_WARNINGS
2065 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2066 (i.op[op].regs - 8)->reg_name,
2067 i.op[op].regs->reg_name,
2068 i.suffix);
2069 #endif
2072 else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize))
2073 /* Do nothing if the instruction is going to ignore the prefix. */
2075 else
2076 abort ();
2078 else if ((i.tm.opcode_modifier & DefaultSize) && !i.suffix)
2080 i.suffix = stackop_size;
2082 /* Make still unresolved immediate matches conform to size of immediate
2083 given in i.suffix. Note: overlap2 cannot be an immediate! */
2084 if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32 | Imm32S))
2085 && overlap0 != Imm8 && overlap0 != Imm8S
2086 && overlap0 != Imm16 && overlap0 != Imm32S
2087 && overlap0 != Imm32 && overlap0 != Imm64)
2089 if (i.suffix)
2091 overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX ? (Imm8 | Imm8S) :
2092 (i.suffix == WORD_MNEM_SUFFIX ? Imm16 :
2093 (i.suffix == QWORD_MNEM_SUFFIX ? Imm64 | Imm32S : Imm32)));
2095 else if (overlap0 == (Imm16 | Imm32S | Imm32)
2096 || overlap0 == (Imm16 | Imm32)
2097 || overlap0 == (Imm16 | Imm32S))
2099 overlap0 =
2100 ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) ? Imm16 : Imm32S;
2102 if (overlap0 != Imm8 && overlap0 != Imm8S
2103 && overlap0 != Imm16 && overlap0 != Imm32S
2104 && overlap0 != Imm32 && overlap0 != Imm64)
2106 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
2107 return;
2110 if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32))
2111 && overlap1 != Imm8 && overlap1 != Imm8S
2112 && overlap1 != Imm16 && overlap1 != Imm32S
2113 && overlap1 != Imm32 && overlap1 != Imm64)
2115 if (i.suffix)
2117 overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX ? (Imm8 | Imm8S) :
2118 (i.suffix == WORD_MNEM_SUFFIX ? Imm16 :
2119 (i.suffix == QWORD_MNEM_SUFFIX ? Imm64 | Imm32S : Imm32)));
2121 else if (overlap1 == (Imm16 | Imm32 | Imm32S)
2122 || overlap1 == (Imm16 | Imm32)
2123 || overlap1 == (Imm16 | Imm32S))
2125 overlap1 =
2126 ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) ? Imm16 : Imm32S;
2128 if (overlap1 != Imm8 && overlap1 != Imm8S
2129 && overlap1 != Imm16 && overlap1 != Imm32S
2130 && overlap1 != Imm32 && overlap1 != Imm64)
2132 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1, i.suffix);
2133 return;
2136 assert ((overlap2 & Imm) == 0);
2138 i.types[0] = overlap0;
2139 if (overlap0 & ImplicitRegister)
2140 i.reg_operands--;
2141 if (overlap0 & Imm1)
2142 i.imm_operands = 0; /* kludge for shift insns. */
2144 i.types[1] = overlap1;
2145 if (overlap1 & ImplicitRegister)
2146 i.reg_operands--;
2148 i.types[2] = overlap2;
2149 if (overlap2 & ImplicitRegister)
2150 i.reg_operands--;
2152 /* Finalize opcode. First, we change the opcode based on the operand
2153 size given by i.suffix: We need not change things for byte insns. */
2155 if (!i.suffix && (i.tm.opcode_modifier & W))
2157 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2158 return;
2161 /* For movzx and movsx, need to check the register type. */
2162 if (intel_syntax
2163 && (i.tm.base_opcode == 0xfb6 || i.tm.base_opcode == 0xfbe))
2164 if (i.suffix && i.suffix == BYTE_MNEM_SUFFIX)
2166 unsigned int prefix = DATA_PREFIX_OPCODE;
2168 if ((i.op[1].regs->reg_type & Reg16) != 0)
2169 if (!add_prefix (prefix))
2170 return;
2173 if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
2175 /* It's not a byte, select word/dword operation. */
2176 if (i.tm.opcode_modifier & W)
2178 if (i.tm.opcode_modifier & ShortForm)
2179 i.tm.base_opcode |= 8;
2180 else
2181 i.tm.base_opcode |= 1;
2183 /* Now select between word & dword operations via the operand
2184 size prefix, except for instructions that will ignore this
2185 prefix anyway. */
2186 if (i.suffix != QWORD_MNEM_SUFFIX
2187 && (i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
2188 && !(i.tm.opcode_modifier & IgnoreSize))
2190 unsigned int prefix = DATA_PREFIX_OPCODE;
2191 if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */
2192 prefix = ADDR_PREFIX_OPCODE;
2194 if (! add_prefix (prefix))
2195 return;
2198 /* Set mode64 for an operand. */
2199 if (i.suffix == QWORD_MNEM_SUFFIX
2200 && !(i.tm.opcode_modifier & NoRex64))
2202 i.rex.mode64 = 1;
2203 if (flag_code < CODE_64BIT)
2205 as_bad (_("64bit operations available only in 64bit modes."));
2206 return;
2210 /* Size floating point instruction. */
2211 if (i.suffix == LONG_MNEM_SUFFIX)
2213 if (i.tm.opcode_modifier & FloatMF)
2214 i.tm.base_opcode ^= 4;
2218 if (i.tm.opcode_modifier & ImmExt)
2220 /* These AMD 3DNow! and Intel Katmai New Instructions have an
2221 opcode suffix which is coded in the same place as an 8-bit
2222 immediate field would be. Here we fake an 8-bit immediate
2223 operand from the opcode suffix stored in tm.extension_opcode. */
2225 expressionS *exp;
2227 assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS);
2229 exp = &im_expressions[i.imm_operands++];
2230 i.op[i.operands].imms = exp;
2231 i.types[i.operands++] = Imm8;
2232 exp->X_op = O_constant;
2233 exp->X_add_number = i.tm.extension_opcode;
2234 i.tm.extension_opcode = None;
2237 /* For insns with operands there are more diddles to do to the opcode. */
2238 if (i.operands)
2240 /* Default segment register this instruction will use
2241 for memory accesses. 0 means unknown.
2242 This is only for optimizing out unnecessary segment overrides. */
2243 const seg_entry *default_seg = 0;
2245 /* The imul $imm, %reg instruction is converted into
2246 imul $imm, %reg, %reg, and the clr %reg instruction
2247 is converted into xor %reg, %reg. */
2248 if (i.tm.opcode_modifier & regKludge)
2250 unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1;
2251 /* Pretend we saw the extra register operand. */
2252 assert (i.op[first_reg_op + 1].regs == 0);
2253 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
2254 i.types[first_reg_op + 1] = i.types[first_reg_op];
2255 i.reg_operands = 2;
2258 if (i.tm.opcode_modifier & ShortForm)
2260 /* The register or float register operand is in operand 0 or 1. */
2261 unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1;
2262 /* Register goes in low 3 bits of opcode. */
2263 i.tm.base_opcode |= i.op[op].regs->reg_num;
2264 if (i.op[op].regs->reg_flags & RegRex)
2265 i.rex.extZ=1;
2266 if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
2268 /* Warn about some common errors, but press on regardless.
2269 The first case can be generated by gcc (<= 2.8.1). */
2270 if (i.operands == 2)
2272 /* Reversed arguments on faddp, fsubp, etc. */
2273 as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name,
2274 i.op[1].regs->reg_name,
2275 i.op[0].regs->reg_name);
2277 else
2279 /* Extraneous `l' suffix on fp insn. */
2280 as_warn (_("translating to `%s %%%s'"), i.tm.name,
2281 i.op[0].regs->reg_name);
2285 else if (i.tm.opcode_modifier & Modrm)
2287 /* The opcode is completed (modulo i.tm.extension_opcode which
2288 must be put into the modrm byte).
2289 Now, we make the modrm & index base bytes based on all the
2290 info we've collected. */
2292 /* i.reg_operands MUST be the number of real register operands;
2293 implicit registers do not count. */
2294 if (i.reg_operands == 2)
2296 unsigned int source, dest;
2297 source = ((i.types[0]
2298 & (Reg | RegMMX | RegXMM
2299 | SReg2 | SReg3
2300 | Control | Debug | Test))
2301 ? 0 : 1);
2302 dest = source + 1;
2304 i.rm.mode = 3;
2305 /* One of the register operands will be encoded in the
2306 i.tm.reg field, the other in the combined i.tm.mode
2307 and i.tm.regmem fields. If no form of this
2308 instruction supports a memory destination operand,
2309 then we assume the source operand may sometimes be
2310 a memory operand and so we need to store the
2311 destination in the i.rm.reg field. */
2312 if ((i.tm.operand_types[dest] & AnyMem) == 0)
2314 i.rm.reg = i.op[dest].regs->reg_num;
2315 i.rm.regmem = i.op[source].regs->reg_num;
2316 if (i.op[dest].regs->reg_flags & RegRex)
2317 i.rex.extX=1;
2318 if (i.op[source].regs->reg_flags & RegRex)
2319 i.rex.extZ=1;
2321 else
2323 i.rm.reg = i.op[source].regs->reg_num;
2324 i.rm.regmem = i.op[dest].regs->reg_num;
2325 if (i.op[dest].regs->reg_flags & RegRex)
2326 i.rex.extZ=1;
2327 if (i.op[source].regs->reg_flags & RegRex)
2328 i.rex.extX=1;
2331 else
2332 { /* If it's not 2 reg operands... */
2333 if (i.mem_operands)
2335 unsigned int fake_zero_displacement = 0;
2336 unsigned int op = ((i.types[0] & AnyMem)
2338 : (i.types[1] & AnyMem) ? 1 : 2);
2340 default_seg = &ds;
2342 if (! i.base_reg)
2344 i.rm.mode = 0;
2345 if (! i.disp_operands)
2346 fake_zero_displacement = 1;
2347 if (! i.index_reg)
2349 /* Operand is just <disp> */
2350 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
2352 i.rm.regmem = NO_BASE_REGISTER_16;
2353 i.types[op] &= ~Disp;
2354 i.types[op] |= Disp16;
2356 else if (flag_code != CODE_64BIT)
2358 i.rm.regmem = NO_BASE_REGISTER;
2359 i.types[op] &= ~Disp;
2360 i.types[op] |= Disp32;
2362 else
2364 /* 64bit mode overwrites the 32bit absolute addressing
2365 by RIP relative addressing and absolute addressing
2366 is encoded by one of the redundant SIB forms. */
2368 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
2369 i.sib.base = NO_BASE_REGISTER;
2370 i.sib.index = NO_INDEX_REGISTER;
2371 i.types[op] &= ~Disp;
2372 i.types[op] |= Disp32S;
2375 else /* ! i.base_reg && i.index_reg */
2377 i.sib.index = i.index_reg->reg_num;
2378 i.sib.base = NO_BASE_REGISTER;
2379 i.sib.scale = i.log2_scale_factor;
2380 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
2381 i.types[op] &= ~Disp;
2382 if (flag_code != CODE_64BIT)
2383 i.types[op] |= Disp32; /* Must be 32 bit */
2384 else
2385 i.types[op] |= Disp32S;
2386 if (i.index_reg->reg_flags & RegRex)
2387 i.rex.extY=1;
2390 /* RIP addressing for 64bit mode. */
2391 else if (i.base_reg->reg_type == BaseIndex)
2393 i.rm.regmem = NO_BASE_REGISTER;
2394 i.types[op] &= ~Disp;
2395 i.types[op] |= Disp32S;
2396 i.flags[op] = Operand_PCrel;
2398 else if (i.base_reg->reg_type & Reg16)
2400 switch (i.base_reg->reg_num)
2402 case 3: /* (%bx) */
2403 if (! i.index_reg)
2404 i.rm.regmem = 7;
2405 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
2406 i.rm.regmem = i.index_reg->reg_num - 6;
2407 break;
2408 case 5: /* (%bp) */
2409 default_seg = &ss;
2410 if (! i.index_reg)
2412 i.rm.regmem = 6;
2413 if ((i.types[op] & Disp) == 0)
2415 /* fake (%bp) into 0(%bp) */
2416 i.types[op] |= Disp8;
2417 fake_zero_displacement = 1;
2420 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
2421 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
2422 break;
2423 default: /* (%si) -> 4 or (%di) -> 5 */
2424 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
2426 i.rm.mode = mode_from_disp_size (i.types[op]);
2428 else /* i.base_reg and 32/64 bit mode */
2430 if (flag_code == CODE_64BIT
2431 && (i.types[op] & Disp))
2433 if (i.types[op] & Disp8)
2434 i.types[op] = Disp8 | Disp32S;
2435 else
2436 i.types[op] = Disp32S;
2438 i.rm.regmem = i.base_reg->reg_num;
2439 if (i.base_reg->reg_flags & RegRex)
2440 i.rex.extZ=1;
2441 i.sib.base = i.base_reg->reg_num;
2442 /* x86-64 ignores REX prefix bit here to avoid
2443 decoder complications. */
2444 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
2446 default_seg = &ss;
2447 if (i.disp_operands == 0)
2449 fake_zero_displacement = 1;
2450 i.types[op] |= Disp8;
2453 else if (i.base_reg->reg_num == ESP_REG_NUM)
2455 default_seg = &ss;
2457 i.sib.scale = i.log2_scale_factor;
2458 if (! i.index_reg)
2460 /* <disp>(%esp) becomes two byte modrm
2461 with no index register. We've already
2462 stored the code for esp in i.rm.regmem
2463 ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. Any
2464 base register besides %esp will not use
2465 the extra modrm byte. */
2466 i.sib.index = NO_INDEX_REGISTER;
2467 #if ! SCALE1_WHEN_NO_INDEX
2468 /* Another case where we force the second
2469 modrm byte. */
2470 if (i.log2_scale_factor)
2471 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
2472 #endif
2474 else
2476 i.sib.index = i.index_reg->reg_num;
2477 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
2478 if (i.index_reg->reg_flags & RegRex)
2479 i.rex.extY=1;
2481 i.rm.mode = mode_from_disp_size (i.types[op]);
2484 if (fake_zero_displacement)
2486 /* Fakes a zero displacement assuming that i.types[op]
2487 holds the correct displacement size. */
2488 expressionS *exp;
2490 assert (i.op[op].disps == 0);
2491 exp = &disp_expressions[i.disp_operands++];
2492 i.op[op].disps = exp;
2493 exp->X_op = O_constant;
2494 exp->X_add_number = 0;
2495 exp->X_add_symbol = (symbolS *) 0;
2496 exp->X_op_symbol = (symbolS *) 0;
2500 /* Fill in i.rm.reg or i.rm.regmem field with register
2501 operand (if any) based on i.tm.extension_opcode.
2502 Again, we must be careful to make sure that
2503 segment/control/debug/test/MMX registers are coded
2504 into the i.rm.reg field. */
2505 if (i.reg_operands)
2507 unsigned int op =
2508 ((i.types[0]
2509 & (Reg | RegMMX | RegXMM
2510 | SReg2 | SReg3
2511 | Control | Debug | Test))
2513 : ((i.types[1]
2514 & (Reg | RegMMX | RegXMM
2515 | SReg2 | SReg3
2516 | Control | Debug | Test))
2518 : 2));
2519 /* If there is an extension opcode to put here, the
2520 register number must be put into the regmem field. */
2521 if (i.tm.extension_opcode != None)
2523 i.rm.regmem = i.op[op].regs->reg_num;
2524 if (i.op[op].regs->reg_flags & RegRex)
2525 i.rex.extZ=1;
2527 else
2529 i.rm.reg = i.op[op].regs->reg_num;
2530 if (i.op[op].regs->reg_flags & RegRex)
2531 i.rex.extX=1;
2534 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2
2535 we must set it to 3 to indicate this is a register
2536 operand in the regmem field. */
2537 if (!i.mem_operands)
2538 i.rm.mode = 3;
2541 /* Fill in i.rm.reg field with extension opcode (if any). */
2542 if (i.tm.extension_opcode != None)
2543 i.rm.reg = i.tm.extension_opcode;
2546 else if (i.tm.opcode_modifier & (Seg2ShortForm | Seg3ShortForm))
2548 if (i.tm.base_opcode == POP_SEG_SHORT
2549 && i.op[0].regs->reg_num == 1)
2551 as_bad (_("you can't `pop %%cs'"));
2552 return;
2554 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
2555 if (i.op[0].regs->reg_flags & RegRex)
2556 i.rex.extZ = 1;
2558 else if ((i.tm.base_opcode & ~(D|W)) == MOV_AX_DISP32)
2560 default_seg = &ds;
2562 else if ((i.tm.opcode_modifier & IsString) != 0)
2564 /* For the string instructions that allow a segment override
2565 on one of their operands, the default segment is ds. */
2566 default_seg = &ds;
2569 /* If a segment was explicitly specified,
2570 and the specified segment is not the default,
2571 use an opcode prefix to select it.
2572 If we never figured out what the default segment is,
2573 then default_seg will be zero at this point,
2574 and the specified segment prefix will always be used. */
2575 if ((i.seg[0]) && (i.seg[0] != default_seg))
2577 if (! add_prefix (i.seg[0]->seg_prefix))
2578 return;
2581 else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
2583 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2584 as_warn (_("translating to `%sp'"), i.tm.name);
2588 /* Handle conversion of 'int $3' --> special int3 insn. */
2589 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
2591 i.tm.base_opcode = INT3_OPCODE;
2592 i.imm_operands = 0;
2595 if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword))
2596 && i.op[0].disps->X_op == O_constant)
2598 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2599 the absolute address given by the constant. Since ix86 jumps and
2600 calls are pc relative, we need to generate a reloc. */
2601 i.op[0].disps->X_add_symbol = &abs_symbol;
2602 i.op[0].disps->X_op = O_symbol;
2605 if (i.tm.opcode_modifier & Rex64)
2606 i.rex.mode64 = 1;
2608 /* For 8bit registers we would need an empty rex prefix.
2609 Also in the case instruction is already having prefix,
2610 we need to convert old registers to new ones. */
2612 if (((i.types[0] & Reg8) && (i.op[0].regs->reg_flags & RegRex64))
2613 || ((i.types[1] & Reg8) && (i.op[1].regs->reg_flags & RegRex64))
2614 || ((i.rex.mode64 || i.rex.extX || i.rex.extY || i.rex.extZ || i.rex.empty)
2615 && ((i.types[0] & Reg8) || (i.types[1] & Reg8))))
2617 int x;
2618 i.rex.empty=1;
2619 for (x = 0; x < 2; x++)
2621 /* Look for 8bit operand that does use old registers. */
2622 if (i.types[x] & Reg8
2623 && !(i.op[x].regs->reg_flags & RegRex64))
2625 /* In case it is "hi" register, give up. */
2626 if (i.op[x].regs->reg_num > 3)
2627 as_bad (_("Can't encode registers '%%%s' in the instruction requiring REX prefix.\n"),
2628 i.op[x].regs->reg_name);
2630 /* Otherwise it is equivalent to the extended register.
2631 Since the encoding don't change this is merely cosmetical
2632 cleanup for debug output. */
2634 i.op[x].regs = i.op[x].regs + 8;
2639 if (i.rex.mode64 || i.rex.extX || i.rex.extY || i.rex.extZ || i.rex.empty)
2640 add_prefix (0x40
2641 | (i.rex.mode64 ? 8 : 0)
2642 | (i.rex.extX ? 4 : 0)
2643 | (i.rex.extY ? 2 : 0)
2644 | (i.rex.extZ ? 1 : 0));
2646 /* We are ready to output the insn. */
2648 register char *p;
2650 /* Output jumps. */
2651 if (i.tm.opcode_modifier & Jump)
2653 int size;
2654 int code16;
2655 int prefix;
2657 code16 = 0;
2658 if (flag_code == CODE_16BIT)
2659 code16 = CODE16;
2661 prefix = 0;
2662 if (i.prefix[DATA_PREFIX])
2664 prefix = 1;
2665 i.prefixes -= 1;
2666 code16 ^= CODE16;
2668 if (i.prefix[REX_PREFIX])
2670 prefix++;
2671 i.prefixes --;
2674 size = 4;
2675 if (code16)
2676 size = 2;
2678 if (i.prefixes != 0 && !intel_syntax)
2679 as_warn (_("skipping prefixes on this instruction"));
2681 /* It's always a symbol; End frag & setup for relax.
2682 Make sure there is enough room in this frag for the largest
2683 instruction we may generate in md_convert_frag. This is 2
2684 bytes for the opcode and room for the prefix and largest
2685 displacement. */
2686 frag_grow (prefix + 2 + size);
2687 insn_size += prefix + 1;
2688 /* Prefix and 1 opcode byte go in fr_fix. */
2689 p = frag_more (prefix + 1);
2690 if (i.prefix[DATA_PREFIX])
2691 *p++ = DATA_PREFIX_OPCODE;
2692 if (i.prefix[REX_PREFIX])
2693 *p++ = i.prefix[REX_PREFIX];
2694 *p = i.tm.base_opcode;
2695 /* 1 possible extra opcode + displacement go in var part.
2696 Pass reloc in fr_var. */
2697 frag_var (rs_machine_dependent,
2698 1 + size,
2699 i.disp_reloc[0],
2700 ((unsigned char) *p == JUMP_PC_RELATIVE
2701 ? ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL) | code16
2702 : ENCODE_RELAX_STATE (COND_JUMP, SMALL) | code16),
2703 i.op[0].disps->X_add_symbol,
2704 i.op[0].disps->X_add_number,
2707 else if (i.tm.opcode_modifier & (JumpByte | JumpDword))
2709 int size;
2711 if (i.tm.opcode_modifier & JumpByte)
2713 /* This is a loop or jecxz type instruction. */
2714 size = 1;
2715 if (i.prefix[ADDR_PREFIX])
2717 insn_size += 1;
2718 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
2719 i.prefixes -= 1;
2722 else
2724 int code16;
2726 code16 = 0;
2727 if (flag_code == CODE_16BIT)
2728 code16 = CODE16;
2730 if (i.prefix[DATA_PREFIX])
2732 insn_size += 1;
2733 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
2734 i.prefixes -= 1;
2735 code16 ^= CODE16;
2738 size = 4;
2739 if (code16)
2740 size = 2;
2743 if (i.prefix[REX_PREFIX])
2745 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
2746 insn_size++;
2747 i.prefixes -= 1;
2750 if (i.prefixes != 0 && !intel_syntax)
2751 as_warn (_("skipping prefixes on this instruction"));
2753 if (fits_in_unsigned_byte (i.tm.base_opcode))
2755 insn_size += 1 + size;
2756 p = frag_more (1 + size);
2758 else
2760 /* Opcode can be at most two bytes. */
2761 insn_size += 2 + size;
2762 p = frag_more (2 + size);
2763 *p++ = (i.tm.base_opcode >> 8) & 0xff;
2765 *p++ = i.tm.base_opcode & 0xff;
2767 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2768 i.op[0].disps, 1, reloc (size, 1, 1, i.disp_reloc[0]));
2770 else if (i.tm.opcode_modifier & JumpInterSegment)
2772 int size;
2773 int prefix;
2774 int code16;
2776 code16 = 0;
2777 if (flag_code == CODE_16BIT)
2778 code16 = CODE16;
2780 prefix = 0;
2781 if (i.prefix[DATA_PREFIX])
2783 prefix = 1;
2784 i.prefixes -= 1;
2785 code16 ^= CODE16;
2787 if (i.prefix[REX_PREFIX])
2789 prefix++;
2790 i.prefixes -= 1;
2793 size = 4;
2794 if (code16)
2795 size = 2;
2797 if (i.prefixes != 0 && !intel_syntax)
2798 as_warn (_("skipping prefixes on this instruction"));
2800 /* 1 opcode; 2 segment; offset */
2801 insn_size += prefix + 1 + 2 + size;
2802 p = frag_more (prefix + 1 + 2 + size);
2804 if (i.prefix[DATA_PREFIX])
2805 *p++ = DATA_PREFIX_OPCODE;
2807 if (i.prefix[REX_PREFIX])
2808 *p++ = i.prefix[REX_PREFIX];
2810 *p++ = i.tm.base_opcode;
2811 if (i.op[1].imms->X_op == O_constant)
2813 offsetT n = i.op[1].imms->X_add_number;
2815 if (size == 2
2816 && !fits_in_unsigned_word (n)
2817 && !fits_in_signed_word (n))
2819 as_bad (_("16-bit jump out of range"));
2820 return;
2822 md_number_to_chars (p, n, size);
2824 else
2825 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2826 i.op[1].imms, 0, reloc (size, 0, 0, i.disp_reloc[0]));
2827 if (i.op[0].imms->X_op != O_constant)
2828 as_bad (_("can't handle non absolute segment in `%s'"),
2829 i.tm.name);
2830 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
2832 else
2834 /* Output normal instructions here. */
2835 unsigned char *q;
2837 /* All opcodes on i386 have eighter 1 or 2 bytes. We may use third
2838 byte for the SSE instructions to specify prefix they require. */
2839 if (i.tm.base_opcode & 0xff0000)
2840 add_prefix ((i.tm.base_opcode >> 16) & 0xff);
2842 /* The prefix bytes. */
2843 for (q = i.prefix;
2844 q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]);
2845 q++)
2847 if (*q)
2849 insn_size += 1;
2850 p = frag_more (1);
2851 md_number_to_chars (p, (valueT) *q, 1);
2855 /* Now the opcode; be careful about word order here! */
2856 if (fits_in_unsigned_byte (i.tm.base_opcode))
2858 insn_size += 1;
2859 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
2861 else
2863 insn_size += 2;
2864 p = frag_more (2);
2865 /* Put out high byte first: can't use md_number_to_chars! */
2866 *p++ = (i.tm.base_opcode >> 8) & 0xff;
2867 *p = i.tm.base_opcode & 0xff;
2870 /* Now the modrm byte and sib byte (if present). */
2871 if (i.tm.opcode_modifier & Modrm)
2873 insn_size += 1;
2874 p = frag_more (1);
2875 md_number_to_chars (p,
2876 (valueT) (i.rm.regmem << 0
2877 | i.rm.reg << 3
2878 | i.rm.mode << 6),
2880 /* If i.rm.regmem == ESP (4)
2881 && i.rm.mode != (Register mode)
2882 && not 16 bit
2883 ==> need second modrm byte. */
2884 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
2885 && i.rm.mode != 3
2886 && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0))
2888 insn_size += 1;
2889 p = frag_more (1);
2890 md_number_to_chars (p,
2891 (valueT) (i.sib.base << 0
2892 | i.sib.index << 3
2893 | i.sib.scale << 6),
2898 if (i.disp_operands)
2900 register unsigned int n;
2902 for (n = 0; n < i.operands; n++)
2904 if (i.types[n] & Disp)
2906 if (i.op[n].disps->X_op == O_constant)
2908 int size;
2909 offsetT val;
2911 size = 4;
2912 if (i.types[n] & (Disp8 | Disp16 | Disp64))
2914 size = 2;
2915 if (i.types[n] & Disp8)
2916 size = 1;
2917 if (i.types[n] & Disp64)
2918 size = 8;
2920 val = offset_in_range (i.op[n].disps->X_add_number,
2921 size);
2922 insn_size += size;
2923 p = frag_more (size);
2924 md_number_to_chars (p, val, size);
2926 else
2928 int size = 4;
2929 int sign = 0;
2930 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
2932 /* The PC relative address is computed relative
2933 to the instruction boundary, so in case immediate
2934 fields follows, we need to adjust the value. */
2935 if (pcrel && i.imm_operands)
2937 int imm_size = 4;
2938 register unsigned int n1;
2940 for (n1 = 0; n1 < i.operands; n1++)
2941 if (i.types[n1] & Imm)
2943 if (i.types[n1] & (Imm8 | Imm8S | Imm16 | Imm64))
2945 imm_size = 2;
2946 if (i.types[n1] & (Imm8 | Imm8S))
2947 imm_size = 1;
2948 if (i.types[n1] & Imm64)
2949 imm_size = 8;
2951 break;
2953 /* We should find the immediate. */
2954 if (n1 == i.operands)
2955 abort();
2956 i.op[n].disps->X_add_number -= imm_size;
2959 if (i.types[n] & Disp32S)
2960 sign = 1;
2962 if (i.types[n] & (Disp16 | Disp64))
2964 size = 2;
2965 if (i.types[n] & Disp64)
2966 size = 8;
2969 insn_size += size;
2970 p = frag_more (size);
2971 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2972 i.op[n].disps, pcrel,
2973 reloc (size, pcrel, sign, i.disp_reloc[n]));
2979 /* Output immediate. */
2980 if (i.imm_operands)
2982 register unsigned int n;
2984 for (n = 0; n < i.operands; n++)
2986 if (i.types[n] & Imm)
2988 if (i.op[n].imms->X_op == O_constant)
2990 int size;
2991 offsetT val;
2993 size = 4;
2994 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
2996 size = 2;
2997 if (i.types[n] & (Imm8 | Imm8S))
2998 size = 1;
2999 else if (i.types[n] & Imm64)
3000 size = 8;
3002 val = offset_in_range (i.op[n].imms->X_add_number,
3003 size);
3004 insn_size += size;
3005 p = frag_more (size);
3006 md_number_to_chars (p, val, size);
3008 else
3010 /* Not absolute_section.
3011 Need a 32-bit fixup (don't support 8bit
3012 non-absolute imms). Try to support other
3013 sizes ... */
3014 #ifdef BFD_ASSEMBLER
3015 enum bfd_reloc_code_real reloc_type;
3016 #else
3017 int reloc_type;
3018 #endif
3019 int size = 4;
3020 int sign = 0;
3022 if ((i.types[n] & (Imm32S))
3023 && i.suffix == QWORD_MNEM_SUFFIX)
3024 sign = 1;
3025 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
3027 size = 2;
3028 if (i.types[n] & (Imm8 | Imm8S))
3029 size = 1;
3030 if (i.types[n] & Imm64)
3031 size = 8;
3034 insn_size += size;
3035 p = frag_more (size);
3036 reloc_type = reloc (size, 0, sign, i.disp_reloc[0]);
3037 #ifdef BFD_ASSEMBLER
3038 if (reloc_type == BFD_RELOC_32
3039 && GOT_symbol
3040 && GOT_symbol == i.op[n].imms->X_add_symbol
3041 && (i.op[n].imms->X_op == O_symbol
3042 || (i.op[n].imms->X_op == O_add
3043 && ((symbol_get_value_expression
3044 (i.op[n].imms->X_op_symbol)->X_op)
3045 == O_subtract))))
3047 /* We don't support dynamic linking on x86-64 yet. */
3048 if (flag_code == CODE_64BIT)
3049 abort();
3050 reloc_type = BFD_RELOC_386_GOTPC;
3051 i.op[n].imms->X_add_number += 3;
3053 #endif
3054 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3055 i.op[n].imms, 0, reloc_type);
3062 dwarf2_emit_insn (insn_size);
3064 #ifdef DEBUG386
3065 if (flag_debug)
3067 pi (line, &i);
3069 #endif /* DEBUG386 */
3073 static int i386_immediate PARAMS ((char *));
3075 static int
3076 i386_immediate (imm_start)
3077 char *imm_start;
3079 char *save_input_line_pointer;
3080 segT exp_seg = 0;
3081 expressionS *exp;
3083 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
3085 as_bad (_("only 1 or 2 immediate operands are allowed"));
3086 return 0;
3089 exp = &im_expressions[i.imm_operands++];
3090 i.op[this_operand].imms = exp;
3092 if (is_space_char (*imm_start))
3093 ++imm_start;
3095 save_input_line_pointer = input_line_pointer;
3096 input_line_pointer = imm_start;
3098 #ifndef LEX_AT
3100 /* We can have operands of the form
3101 <symbol>@GOTOFF+<nnn>
3102 Take the easy way out here and copy everything
3103 into a temporary buffer... */
3104 register char *cp;
3106 cp = strchr (input_line_pointer, '@');
3107 if (cp != NULL)
3109 char *tmpbuf;
3110 int len = 0;
3111 int first;
3113 /* GOT relocations are not supported in 16 bit mode. */
3114 if (flag_code == CODE_16BIT)
3115 as_bad (_("GOT relocations not supported in 16 bit mode"));
3117 if (GOT_symbol == NULL)
3118 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
3120 if (strncmp (cp + 1, "PLT", 3) == 0)
3122 if (flag_code == CODE_64BIT)
3123 i.disp_reloc[this_operand] = BFD_RELOC_X86_64_PLT32;
3124 else
3125 i.disp_reloc[this_operand] = BFD_RELOC_386_PLT32;
3126 len = 3;
3128 else if (strncmp (cp + 1, "GOTOFF", 6) == 0)
3130 if (flag_code == CODE_64BIT)
3131 as_bad ("GOTOFF relocations are unsupported in 64bit mode.");
3132 i.disp_reloc[this_operand] = BFD_RELOC_386_GOTOFF;
3133 len = 6;
3135 else if (strncmp (cp + 1, "GOT", 3) == 0)
3137 if (flag_code == CODE_64BIT)
3138 i.disp_reloc[this_operand] = BFD_RELOC_X86_64_GOT32;
3139 else
3140 i.disp_reloc[this_operand] = BFD_RELOC_386_GOT32;
3141 len = 3;
3143 else if (strncmp (cp + 1, "GOTPCREL", 3) == 0)
3145 if (flag_code == CODE_64BIT)
3146 i.disp_reloc[this_operand] = BFD_RELOC_X86_64_GOTPCREL;
3147 else
3148 as_bad ("GOTPCREL relocations are supported only in 64bit mode.");
3149 len = 3;
3151 else
3152 as_bad (_("bad reloc specifier in expression"));
3154 /* Replace the relocation token with ' ', so that errors like
3155 foo@GOTOFF1 will be detected. */
3156 first = cp - input_line_pointer;
3157 tmpbuf = (char *) alloca (strlen (input_line_pointer));
3158 memcpy (tmpbuf, input_line_pointer, first);
3159 tmpbuf[first] = ' ';
3160 strcpy (tmpbuf + first + 1, cp + 1 + len);
3161 input_line_pointer = tmpbuf;
3164 #endif
3166 exp_seg = expression (exp);
3168 SKIP_WHITESPACE ();
3169 if (*input_line_pointer)
3170 as_bad (_("ignoring junk `%s' after expression"), input_line_pointer);
3172 input_line_pointer = save_input_line_pointer;
3174 if (exp->X_op == O_absent || exp->X_op == O_big)
3176 /* Missing or bad expr becomes absolute 0. */
3177 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
3178 imm_start);
3179 exp->X_op = O_constant;
3180 exp->X_add_number = 0;
3181 exp->X_add_symbol = (symbolS *) 0;
3182 exp->X_op_symbol = (symbolS *) 0;
3184 else if (exp->X_op == O_constant)
3186 /* Size it properly later. */
3187 i.types[this_operand] |= Imm64;
3188 /* If BFD64, sign extend val. */
3189 if (!use_rela_relocations)
3190 if ((exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
3191 exp->X_add_number = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
3193 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3194 else if (1
3195 #ifdef BFD_ASSEMBLER
3196 && OUTPUT_FLAVOR == bfd_target_aout_flavour
3197 #endif
3198 && exp_seg != text_section
3199 && exp_seg != data_section
3200 && exp_seg != bss_section
3201 && exp_seg != undefined_section
3202 #ifdef BFD_ASSEMBLER
3203 && !bfd_is_com_section (exp_seg)
3204 #endif
3207 #ifdef BFD_ASSEMBLER
3208 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3209 #else
3210 as_bad (_("unimplemented segment type %d in operand"), exp_seg);
3211 #endif
3212 return 0;
3214 #endif
3215 else
3217 /* This is an address. The size of the address will be
3218 determined later, depending on destination register,
3219 suffix, or the default for the section. */
3220 i.types[this_operand] |= Imm8 | Imm16 | Imm32 | Imm32S | Imm64;
3223 return 1;
3226 static int i386_scale PARAMS ((char *));
3228 static int
3229 i386_scale (scale)
3230 char *scale;
3232 if (!isdigit (*scale))
3233 goto bad_scale;
3235 switch (*scale)
3237 case '0':
3238 case '1':
3239 i.log2_scale_factor = 0;
3240 break;
3241 case '2':
3242 i.log2_scale_factor = 1;
3243 break;
3244 case '4':
3245 i.log2_scale_factor = 2;
3246 break;
3247 case '8':
3248 i.log2_scale_factor = 3;
3249 break;
3250 default:
3251 bad_scale:
3252 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
3253 scale);
3254 return 0;
3256 if (i.log2_scale_factor != 0 && ! i.index_reg)
3258 as_warn (_("scale factor of %d without an index register"),
3259 1 << i.log2_scale_factor);
3260 #if SCALE1_WHEN_NO_INDEX
3261 i.log2_scale_factor = 0;
3262 #endif
3264 return 1;
3267 static int i386_displacement PARAMS ((char *, char *));
3269 static int
3270 i386_displacement (disp_start, disp_end)
3271 char *disp_start;
3272 char *disp_end;
3274 register expressionS *exp;
3275 segT exp_seg = 0;
3276 char *save_input_line_pointer;
3277 int bigdisp = Disp32;
3279 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
3280 bigdisp = Disp16;
3281 if (flag_code == CODE_64BIT)
3282 bigdisp = Disp64;
3283 i.types[this_operand] |= bigdisp;
3285 exp = &disp_expressions[i.disp_operands];
3286 i.op[this_operand].disps = exp;
3287 i.disp_operands++;
3288 save_input_line_pointer = input_line_pointer;
3289 input_line_pointer = disp_start;
3290 END_STRING_AND_SAVE (disp_end);
3292 #ifndef GCC_ASM_O_HACK
3293 #define GCC_ASM_O_HACK 0
3294 #endif
3295 #if GCC_ASM_O_HACK
3296 END_STRING_AND_SAVE (disp_end + 1);
3297 if ((i.types[this_operand] & BaseIndex) != 0
3298 && displacement_string_end[-1] == '+')
3300 /* This hack is to avoid a warning when using the "o"
3301 constraint within gcc asm statements.
3302 For instance:
3304 #define _set_tssldt_desc(n,addr,limit,type) \
3305 __asm__ __volatile__ ( \
3306 "movw %w2,%0\n\t" \
3307 "movw %w1,2+%0\n\t" \
3308 "rorl $16,%1\n\t" \
3309 "movb %b1,4+%0\n\t" \
3310 "movb %4,5+%0\n\t" \
3311 "movb $0,6+%0\n\t" \
3312 "movb %h1,7+%0\n\t" \
3313 "rorl $16,%1" \
3314 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
3316 This works great except that the output assembler ends
3317 up looking a bit weird if it turns out that there is
3318 no offset. You end up producing code that looks like:
3320 #APP
3321 movw $235,(%eax)
3322 movw %dx,2+(%eax)
3323 rorl $16,%edx
3324 movb %dl,4+(%eax)
3325 movb $137,5+(%eax)
3326 movb $0,6+(%eax)
3327 movb %dh,7+(%eax)
3328 rorl $16,%edx
3329 #NO_APP
3331 So here we provide the missing zero. */
3333 *displacement_string_end = '0';
3335 #endif
3336 #ifndef LEX_AT
3338 /* We can have operands of the form
3339 <symbol>@GOTOFF+<nnn>
3340 Take the easy way out here and copy everything
3341 into a temporary buffer... */
3342 register char *cp;
3344 cp = strchr (input_line_pointer, '@');
3345 if (cp != NULL)
3347 char *tmpbuf;
3348 int len = 0;
3349 int first;
3351 /* GOT relocations are not supported in 16 bit mode. */
3352 if (flag_code == CODE_16BIT)
3353 as_bad (_("GOT relocations not supported in 16 bit mode"));
3355 if (GOT_symbol == NULL)
3356 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
3358 if (strncmp (cp + 1, "PLT", 3) == 0)
3360 if (flag_code == CODE_64BIT)
3361 i.disp_reloc[this_operand] = BFD_RELOC_X86_64_PLT32;
3362 else
3363 i.disp_reloc[this_operand] = BFD_RELOC_386_PLT32;
3364 len = 3;
3366 else if (strncmp (cp + 1, "GOTOFF", 6) == 0)
3368 if (flag_code == CODE_64BIT)
3369 as_bad ("GOTOFF relocation is not supported in 64bit mode.");
3370 i.disp_reloc[this_operand] = BFD_RELOC_386_GOTOFF;
3371 len = 6;
3373 else if (strncmp (cp + 1, "GOT", 3) == 0)
3375 if (flag_code == CODE_64BIT)
3376 i.disp_reloc[this_operand] = BFD_RELOC_X86_64_GOT32;
3377 else
3378 i.disp_reloc[this_operand] = BFD_RELOC_386_GOT32;
3379 len = 3;
3381 else if (strncmp (cp + 1, "GOTPCREL", 3) == 0)
3383 if (flag_code != CODE_64BIT)
3384 as_bad ("GOTPCREL relocation is supported only in 64bit mode.");
3385 i.disp_reloc[this_operand] = BFD_RELOC_X86_64_GOTPCREL;
3386 len = 3;
3388 else
3389 as_bad (_("bad reloc specifier in expression"));
3391 /* Replace the relocation token with ' ', so that errors like
3392 foo@GOTOFF1 will be detected. */
3393 first = cp - input_line_pointer;
3394 tmpbuf = (char *) alloca (strlen (input_line_pointer));
3395 memcpy (tmpbuf, input_line_pointer, first);
3396 tmpbuf[first] = ' ';
3397 strcpy (tmpbuf + first + 1, cp + 1 + len);
3398 input_line_pointer = tmpbuf;
3401 #endif
3403 exp_seg = expression (exp);
3405 #ifdef BFD_ASSEMBLER
3406 /* We do this to make sure that the section symbol is in
3407 the symbol table. We will ultimately change the relocation
3408 to be relative to the beginning of the section. */
3409 if (i.disp_reloc[this_operand] == BFD_RELOC_386_GOTOFF
3410 || i.disp_reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
3412 if (S_IS_LOCAL(exp->X_add_symbol)
3413 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
3414 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
3415 assert (exp->X_op == O_symbol);
3416 exp->X_op = O_subtract;
3417 exp->X_op_symbol = GOT_symbol;
3418 i.disp_reloc[this_operand] = BFD_RELOC_32;
3420 #endif
3422 SKIP_WHITESPACE ();
3423 if (*input_line_pointer)
3424 as_bad (_("ignoring junk `%s' after expression"),
3425 input_line_pointer);
3426 #if GCC_ASM_O_HACK
3427 RESTORE_END_STRING (disp_end + 1);
3428 #endif
3429 RESTORE_END_STRING (disp_end);
3430 input_line_pointer = save_input_line_pointer;
3432 if (exp->X_op == O_absent || exp->X_op == O_big)
3434 /* Missing or bad expr becomes absolute 0. */
3435 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
3436 disp_start);
3437 exp->X_op = O_constant;
3438 exp->X_add_number = 0;
3439 exp->X_add_symbol = (symbolS *) 0;
3440 exp->X_op_symbol = (symbolS *) 0;
3443 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3444 if (exp->X_op != O_constant
3445 #ifdef BFD_ASSEMBLER
3446 && OUTPUT_FLAVOR == bfd_target_aout_flavour
3447 #endif
3448 && exp_seg != text_section
3449 && exp_seg != data_section
3450 && exp_seg != bss_section
3451 && exp_seg != undefined_section)
3453 #ifdef BFD_ASSEMBLER
3454 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3455 #else
3456 as_bad (_("unimplemented segment type %d in operand"), exp_seg);
3457 #endif
3458 return 0;
3460 #endif
3461 else if (flag_code == CODE_64BIT)
3462 i.types[this_operand] |= Disp32S | Disp32;
3463 return 1;
3466 static int i386_index_check PARAMS((const char *));
3468 /* Make sure the memory operand we've been dealt is valid.
3469 Return 1 on success, 0 on a failure. */
3471 static int
3472 i386_index_check (operand_string)
3473 const char *operand_string;
3475 int ok;
3476 #if INFER_ADDR_PREFIX
3477 int fudged = 0;
3479 tryprefix:
3480 #endif
3481 ok = 1;
3482 if (flag_code == CODE_64BIT)
3484 /* 64bit checks. */
3485 if ((i.base_reg
3486 && ((i.base_reg->reg_type & Reg64) == 0)
3487 && (i.base_reg->reg_type != BaseIndex
3488 || i.index_reg))
3489 || (i.index_reg
3490 && ((i.index_reg->reg_type & (Reg64|BaseIndex))
3491 != (Reg64|BaseIndex))))
3492 ok = 0;
3494 else
3496 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
3498 /* 16bit checks. */
3499 if ((i.base_reg
3500 && ((i.base_reg->reg_type & (Reg16|BaseIndex|RegRex))
3501 != (Reg16|BaseIndex)))
3502 || (i.index_reg
3503 && (((i.index_reg->reg_type & (Reg16|BaseIndex))
3504 != (Reg16|BaseIndex))
3505 || ! (i.base_reg
3506 && i.base_reg->reg_num < 6
3507 && i.index_reg->reg_num >= 6
3508 && i.log2_scale_factor == 0))))
3509 ok = 0;
3511 else
3513 /* 32bit checks. */
3514 if ((i.base_reg
3515 && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32)
3516 || (i.index_reg
3517 && ((i.index_reg->reg_type & (Reg32|BaseIndex|RegRex))
3518 != (Reg32|BaseIndex))))
3519 ok = 0;
3522 if (!ok)
3524 #if INFER_ADDR_PREFIX
3525 if (flag_code != CODE_64BIT
3526 && i.prefix[ADDR_PREFIX] == 0 && stackop_size != '\0')
3528 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
3529 i.prefixes += 1;
3530 /* Change the size of any displacement too. At most one of
3531 Disp16 or Disp32 is set.
3532 FIXME. There doesn't seem to be any real need for separate
3533 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
3534 Removing them would probably clean up the code quite a lot. */
3535 if (i.types[this_operand] & (Disp16|Disp32))
3536 i.types[this_operand] ^= (Disp16|Disp32);
3537 fudged = 1;
3538 goto tryprefix;
3540 if (fudged)
3541 as_bad (_("`%s' is not a valid base/index expression"),
3542 operand_string);
3543 else
3544 #endif
3545 as_bad (_("`%s' is not a valid %s bit base/index expression"),
3546 operand_string,
3547 flag_code_names[flag_code]);
3548 return 0;
3550 return 1;
3553 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
3554 on error. */
3556 static int
3557 i386_operand (operand_string)
3558 char *operand_string;
3560 const reg_entry *r;
3561 char *end_op;
3562 char *op_string = operand_string;
3564 if (is_space_char (*op_string))
3565 ++op_string;
3567 /* We check for an absolute prefix (differentiating,
3568 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
3569 if (*op_string == ABSOLUTE_PREFIX)
3571 ++op_string;
3572 if (is_space_char (*op_string))
3573 ++op_string;
3574 i.types[this_operand] |= JumpAbsolute;
3577 /* Check if operand is a register. */
3578 if ((*op_string == REGISTER_PREFIX || allow_naked_reg)
3579 && (r = parse_register (op_string, &end_op)) != NULL)
3581 /* Check for a segment override by searching for ':' after a
3582 segment register. */
3583 op_string = end_op;
3584 if (is_space_char (*op_string))
3585 ++op_string;
3586 if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3)))
3588 switch (r->reg_num)
3590 case 0:
3591 i.seg[i.mem_operands] = &es;
3592 break;
3593 case 1:
3594 i.seg[i.mem_operands] = &cs;
3595 break;
3596 case 2:
3597 i.seg[i.mem_operands] = &ss;
3598 break;
3599 case 3:
3600 i.seg[i.mem_operands] = &ds;
3601 break;
3602 case 4:
3603 i.seg[i.mem_operands] = &fs;
3604 break;
3605 case 5:
3606 i.seg[i.mem_operands] = &gs;
3607 break;
3610 /* Skip the ':' and whitespace. */
3611 ++op_string;
3612 if (is_space_char (*op_string))
3613 ++op_string;
3615 if (!is_digit_char (*op_string)
3616 && !is_identifier_char (*op_string)
3617 && *op_string != '('
3618 && *op_string != ABSOLUTE_PREFIX)
3620 as_bad (_("bad memory operand `%s'"), op_string);
3621 return 0;
3623 /* Handle case of %es:*foo. */
3624 if (*op_string == ABSOLUTE_PREFIX)
3626 ++op_string;
3627 if (is_space_char (*op_string))
3628 ++op_string;
3629 i.types[this_operand] |= JumpAbsolute;
3631 goto do_memory_reference;
3633 if (*op_string)
3635 as_bad (_("junk `%s' after register"), op_string);
3636 return 0;
3638 i.types[this_operand] |= r->reg_type & ~BaseIndex;
3639 i.op[this_operand].regs = r;
3640 i.reg_operands++;
3642 else if (*op_string == REGISTER_PREFIX)
3644 as_bad (_("bad register name `%s'"), op_string);
3645 return 0;
3647 else if (*op_string == IMMEDIATE_PREFIX)
3649 ++op_string;
3650 if (i.types[this_operand] & JumpAbsolute)
3652 as_bad (_("immediate operand illegal with absolute jump"));
3653 return 0;
3655 if (!i386_immediate (op_string))
3656 return 0;
3658 else if (is_digit_char (*op_string)
3659 || is_identifier_char (*op_string)
3660 || *op_string == '(' )
3662 /* This is a memory reference of some sort. */
3663 char *base_string;
3665 /* Start and end of displacement string expression (if found). */
3666 char *displacement_string_start;
3667 char *displacement_string_end;
3669 do_memory_reference:
3670 if ((i.mem_operands == 1
3671 && (current_templates->start->opcode_modifier & IsString) == 0)
3672 || i.mem_operands == 2)
3674 as_bad (_("too many memory references for `%s'"),
3675 current_templates->start->name);
3676 return 0;
3679 /* Check for base index form. We detect the base index form by
3680 looking for an ')' at the end of the operand, searching
3681 for the '(' matching it, and finding a REGISTER_PREFIX or ','
3682 after the '('. */
3683 base_string = op_string + strlen (op_string);
3685 --base_string;
3686 if (is_space_char (*base_string))
3687 --base_string;
3689 /* If we only have a displacement, set-up for it to be parsed later. */
3690 displacement_string_start = op_string;
3691 displacement_string_end = base_string + 1;
3693 if (*base_string == ')')
3695 char *temp_string;
3696 unsigned int parens_balanced = 1;
3697 /* We've already checked that the number of left & right ()'s are
3698 equal, so this loop will not be infinite. */
3701 base_string--;
3702 if (*base_string == ')')
3703 parens_balanced++;
3704 if (*base_string == '(')
3705 parens_balanced--;
3707 while (parens_balanced);
3709 temp_string = base_string;
3711 /* Skip past '(' and whitespace. */
3712 ++base_string;
3713 if (is_space_char (*base_string))
3714 ++base_string;
3716 if (*base_string == ','
3717 || ((*base_string == REGISTER_PREFIX || allow_naked_reg)
3718 && (i.base_reg = parse_register (base_string, &end_op)) != NULL))
3720 displacement_string_end = temp_string;
3722 i.types[this_operand] |= BaseIndex;
3724 if (i.base_reg)
3726 base_string = end_op;
3727 if (is_space_char (*base_string))
3728 ++base_string;
3731 /* There may be an index reg or scale factor here. */
3732 if (*base_string == ',')
3734 ++base_string;
3735 if (is_space_char (*base_string))
3736 ++base_string;
3738 if ((*base_string == REGISTER_PREFIX || allow_naked_reg)
3739 && (i.index_reg = parse_register (base_string, &end_op)) != NULL)
3741 base_string = end_op;
3742 if (is_space_char (*base_string))
3743 ++base_string;
3744 if (*base_string == ',')
3746 ++base_string;
3747 if (is_space_char (*base_string))
3748 ++base_string;
3750 else if (*base_string != ')' )
3752 as_bad (_("expecting `,' or `)' after index register in `%s'"),
3753 operand_string);
3754 return 0;
3757 else if (*base_string == REGISTER_PREFIX)
3759 as_bad (_("bad register name `%s'"), base_string);
3760 return 0;
3763 /* Check for scale factor. */
3764 if (isdigit ((unsigned char) *base_string))
3766 if (!i386_scale (base_string))
3767 return 0;
3769 ++base_string;
3770 if (is_space_char (*base_string))
3771 ++base_string;
3772 if (*base_string != ')')
3774 as_bad (_("expecting `)' after scale factor in `%s'"),
3775 operand_string);
3776 return 0;
3779 else if (!i.index_reg)
3781 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
3782 *base_string);
3783 return 0;
3786 else if (*base_string != ')')
3788 as_bad (_("expecting `,' or `)' after base register in `%s'"),
3789 operand_string);
3790 return 0;
3793 else if (*base_string == REGISTER_PREFIX)
3795 as_bad (_("bad register name `%s'"), base_string);
3796 return 0;
3800 /* If there's an expression beginning the operand, parse it,
3801 assuming displacement_string_start and
3802 displacement_string_end are meaningful. */
3803 if (displacement_string_start != displacement_string_end)
3805 if (!i386_displacement (displacement_string_start,
3806 displacement_string_end))
3807 return 0;
3810 /* Special case for (%dx) while doing input/output op. */
3811 if (i.base_reg
3812 && i.base_reg->reg_type == (Reg16 | InOutPortReg)
3813 && i.index_reg == 0
3814 && i.log2_scale_factor == 0
3815 && i.seg[i.mem_operands] == 0
3816 && (i.types[this_operand] & Disp) == 0)
3818 i.types[this_operand] = InOutPortReg;
3819 return 1;
3822 if (i386_index_check (operand_string) == 0)
3823 return 0;
3824 i.mem_operands++;
3826 else
3828 /* It's not a memory operand; argh! */
3829 as_bad (_("invalid char %s beginning operand %d `%s'"),
3830 output_invalid (*op_string),
3831 this_operand + 1,
3832 op_string);
3833 return 0;
3835 return 1; /* Normal return. */
3838 /* md_estimate_size_before_relax()
3840 Called just before relax() for rs_machine_dependent frags. The x86
3841 assembler uses these frags to handle variable size jump
3842 instructions.
3844 Any symbol that is now undefined will not become defined.
3845 Return the correct fr_subtype in the frag.
3846 Return the initial "guess for variable size of frag" to caller.
3847 The guess is actually the growth beyond the fixed part. Whatever
3848 we do to grow the fixed or variable part contributes to our
3849 returned value. */
3852 md_estimate_size_before_relax (fragP, segment)
3853 register fragS *fragP;
3854 register segT segment;
3856 /* We've already got fragP->fr_subtype right; all we have to do is
3857 check for un-relaxable symbols. On an ELF system, we can't relax
3858 an externally visible symbol, because it may be overridden by a
3859 shared library. */
3860 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
3861 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3862 || S_IS_EXTERNAL (fragP->fr_symbol)
3863 || S_IS_WEAK (fragP->fr_symbol)
3864 #endif
3867 /* Symbol is undefined in this segment, or we need to keep a
3868 reloc so that weak symbols can be overridden. */
3869 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
3870 #ifdef BFD_ASSEMBLER
3871 enum bfd_reloc_code_real reloc_type;
3872 #else
3873 int reloc_type;
3874 #endif
3875 unsigned char *opcode;
3876 int old_fr_fix;
3878 if (fragP->fr_var != NO_RELOC)
3879 reloc_type = fragP->fr_var;
3880 else if (size == 2)
3881 reloc_type = BFD_RELOC_16_PCREL;
3882 else
3883 reloc_type = BFD_RELOC_32_PCREL;
3885 old_fr_fix = fragP->fr_fix;
3886 opcode = (unsigned char *) fragP->fr_opcode;
3888 switch (opcode[0])
3890 case JUMP_PC_RELATIVE:
3891 /* Make jmp (0xeb) a dword displacement jump. */
3892 opcode[0] = 0xe9;
3893 fragP->fr_fix += size;
3894 fix_new (fragP, old_fr_fix, size,
3895 fragP->fr_symbol,
3896 fragP->fr_offset, 1,
3897 reloc_type);
3898 break;
3900 default:
3901 /* This changes the byte-displacement jump 0x7N
3902 to the dword-displacement jump 0x0f,0x8N. */
3903 opcode[1] = opcode[0] + 0x10;
3904 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
3905 /* We've added an opcode byte. */
3906 fragP->fr_fix += 1 + size;
3907 fix_new (fragP, old_fr_fix + 1, size,
3908 fragP->fr_symbol,
3909 fragP->fr_offset, 1,
3910 reloc_type);
3911 break;
3913 frag_wane (fragP);
3914 return fragP->fr_fix - old_fr_fix;
3916 /* Guess a short jump. */
3917 return 1;
3920 /* Called after relax() is finished.
3922 In: Address of frag.
3923 fr_type == rs_machine_dependent.
3924 fr_subtype is what the address relaxed to.
3926 Out: Any fixSs and constants are set up.
3927 Caller will turn frag into a ".space 0". */
3929 #ifndef BFD_ASSEMBLER
3930 void
3931 md_convert_frag (headers, sec, fragP)
3932 object_headers *headers ATTRIBUTE_UNUSED;
3933 segT sec ATTRIBUTE_UNUSED;
3934 register fragS *fragP;
3935 #else
3936 void
3937 md_convert_frag (abfd, sec, fragP)
3938 bfd *abfd ATTRIBUTE_UNUSED;
3939 segT sec ATTRIBUTE_UNUSED;
3940 register fragS *fragP;
3941 #endif
3943 register unsigned char *opcode;
3944 unsigned char *where_to_put_displacement = NULL;
3945 offsetT target_address;
3946 offsetT opcode_address;
3947 unsigned int extension = 0;
3948 offsetT displacement_from_opcode_start;
3950 opcode = (unsigned char *) fragP->fr_opcode;
3952 /* Address we want to reach in file space. */
3953 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
3954 #ifdef BFD_ASSEMBLER
3955 /* Not needed otherwise? */
3956 target_address += symbol_get_frag (fragP->fr_symbol)->fr_address;
3957 #endif
3959 /* Address opcode resides at in file space. */
3960 opcode_address = fragP->fr_address + fragP->fr_fix;
3962 /* Displacement from opcode start to fill into instruction. */
3963 displacement_from_opcode_start = target_address - opcode_address;
3965 switch (fragP->fr_subtype)
3967 case ENCODE_RELAX_STATE (COND_JUMP, SMALL):
3968 case ENCODE_RELAX_STATE (COND_JUMP, SMALL16):
3969 case ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL):
3970 case ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL16):
3971 /* Don't have to change opcode. */
3972 extension = 1; /* 1 opcode + 1 displacement */
3973 where_to_put_displacement = &opcode[1];
3974 break;
3976 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
3977 extension = 5; /* 2 opcode + 4 displacement */
3978 opcode[1] = opcode[0] + 0x10;
3979 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
3980 where_to_put_displacement = &opcode[2];
3981 break;
3983 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
3984 extension = 4; /* 1 opcode + 4 displacement */
3985 opcode[0] = 0xe9;
3986 where_to_put_displacement = &opcode[1];
3987 break;
3989 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
3990 extension = 3; /* 2 opcode + 2 displacement */
3991 opcode[1] = opcode[0] + 0x10;
3992 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
3993 where_to_put_displacement = &opcode[2];
3994 break;
3996 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
3997 extension = 2; /* 1 opcode + 2 displacement */
3998 opcode[0] = 0xe9;
3999 where_to_put_displacement = &opcode[1];
4000 break;
4002 default:
4003 BAD_CASE (fragP->fr_subtype);
4004 break;
4006 /* Now put displacement after opcode. */
4007 md_number_to_chars ((char *) where_to_put_displacement,
4008 (valueT) (displacement_from_opcode_start - extension),
4009 SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
4010 fragP->fr_fix += extension;
4013 /* Size of byte displacement jmp. */
4014 int md_short_jump_size = 2;
4016 /* Size of dword displacement jmp. */
4017 int md_long_jump_size = 5;
4019 /* Size of relocation record. */
4020 const int md_reloc_size = 8;
4022 void
4023 md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
4024 char *ptr;
4025 addressT from_addr, to_addr;
4026 fragS *frag ATTRIBUTE_UNUSED;
4027 symbolS *to_symbol ATTRIBUTE_UNUSED;
4029 offsetT offset;
4031 offset = to_addr - (from_addr + 2);
4032 /* Opcode for byte-disp jump. */
4033 md_number_to_chars (ptr, (valueT) 0xeb, 1);
4034 md_number_to_chars (ptr + 1, (valueT) offset, 1);
4037 void
4038 md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
4039 char *ptr;
4040 addressT from_addr, to_addr;
4041 fragS *frag ATTRIBUTE_UNUSED;
4042 symbolS *to_symbol ATTRIBUTE_UNUSED;
4044 offsetT offset;
4046 offset = to_addr - (from_addr + 5);
4047 md_number_to_chars (ptr, (valueT) 0xe9, 1);
4048 md_number_to_chars (ptr + 1, (valueT) offset, 4);
4051 /* Apply a fixup (fixS) to segment data, once it has been determined
4052 by our caller that we have all the info we need to fix it up.
4054 On the 386, immediates, displacements, and data pointers are all in
4055 the same (little-endian) format, so we don't need to care about which
4056 we are handling. */
4059 md_apply_fix3 (fixP, valp, seg)
4060 /* The fix we're to put in. */
4061 fixS *fixP;
4063 /* Pointer to the value of the bits. */
4064 valueT *valp;
4066 /* Segment fix is from. */
4067 segT seg ATTRIBUTE_UNUSED;
4069 register char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
4070 valueT value = *valp;
4072 #if defined (BFD_ASSEMBLER) && !defined (TE_Mach)
4073 if (fixP->fx_pcrel)
4075 switch (fixP->fx_r_type)
4077 default:
4078 break;
4080 case BFD_RELOC_32:
4081 fixP->fx_r_type = BFD_RELOC_32_PCREL;
4082 break;
4083 case BFD_RELOC_16:
4084 fixP->fx_r_type = BFD_RELOC_16_PCREL;
4085 break;
4086 case BFD_RELOC_8:
4087 fixP->fx_r_type = BFD_RELOC_8_PCREL;
4088 break;
4092 /* This is a hack. There should be a better way to handle this.
4093 This covers for the fact that bfd_install_relocation will
4094 subtract the current location (for partial_inplace, PC relative
4095 relocations); see more below. */
4096 if ((fixP->fx_r_type == BFD_RELOC_32_PCREL
4097 || fixP->fx_r_type == BFD_RELOC_16_PCREL
4098 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
4099 && fixP->fx_addsy)
4101 #ifndef OBJ_AOUT
4102 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
4103 #ifdef TE_PE
4104 || OUTPUT_FLAVOR == bfd_target_coff_flavour
4105 #endif
4107 value += fixP->fx_where + fixP->fx_frag->fr_address;
4108 #endif
4109 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4110 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
4112 segT fseg = S_GET_SEGMENT (fixP->fx_addsy);
4114 if ((fseg == seg
4115 || (symbol_section_p (fixP->fx_addsy)
4116 && fseg != absolute_section))
4117 && ! S_IS_EXTERNAL (fixP->fx_addsy)
4118 && ! S_IS_WEAK (fixP->fx_addsy)
4119 && S_IS_DEFINED (fixP->fx_addsy)
4120 && ! S_IS_COMMON (fixP->fx_addsy))
4122 /* Yes, we add the values in twice. This is because
4123 bfd_perform_relocation subtracts them out again. I think
4124 bfd_perform_relocation is broken, but I don't dare change
4125 it. FIXME. */
4126 value += fixP->fx_where + fixP->fx_frag->fr_address;
4129 #endif
4130 #if defined (OBJ_COFF) && defined (TE_PE)
4131 /* For some reason, the PE format does not store a section
4132 address offset for a PC relative symbol. */
4133 if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
4134 value += md_pcrel_from (fixP);
4135 #endif
4138 /* Fix a few things - the dynamic linker expects certain values here,
4139 and we must not dissappoint it. */
4140 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4141 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
4142 && fixP->fx_addsy)
4143 switch (fixP->fx_r_type)
4145 case BFD_RELOC_386_PLT32:
4146 case BFD_RELOC_X86_64_PLT32:
4147 /* Make the jump instruction point to the address of the operand. At
4148 runtime we merely add the offset to the actual PLT entry. */
4149 value = -4;
4150 break;
4151 case BFD_RELOC_386_GOTPC:
4153 /* This is tough to explain. We end up with this one if we have
4154 * operands that look like "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal
4155 * here is to obtain the absolute address of the GOT, and it is strongly
4156 * preferable from a performance point of view to avoid using a runtime
4157 * relocation for this. The actual sequence of instructions often look
4158 * something like:
4160 * call .L66
4161 * .L66:
4162 * popl %ebx
4163 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
4165 * The call and pop essentially return the absolute address of
4166 * the label .L66 and store it in %ebx. The linker itself will
4167 * ultimately change the first operand of the addl so that %ebx points to
4168 * the GOT, but to keep things simple, the .o file must have this operand
4169 * set so that it generates not the absolute address of .L66, but the
4170 * absolute address of itself. This allows the linker itself simply
4171 * treat a GOTPC relocation as asking for a pcrel offset to the GOT to be
4172 * added in, and the addend of the relocation is stored in the operand
4173 * field for the instruction itself.
4175 * Our job here is to fix the operand so that it would add the correct
4176 * offset so that %ebx would point to itself. The thing that is tricky is
4177 * that .-.L66 will point to the beginning of the instruction, so we need
4178 * to further modify the operand so that it will point to itself.
4179 * There are other cases where you have something like:
4181 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
4183 * and here no correction would be required. Internally in the assembler
4184 * we treat operands of this form as not being pcrel since the '.' is
4185 * explicitly mentioned, and I wonder whether it would simplify matters
4186 * to do it this way. Who knows. In earlier versions of the PIC patches,
4187 * the pcrel_adjust field was used to store the correction, but since the
4188 * expression is not pcrel, I felt it would be confusing to do it this
4189 * way. */
4191 value -= 1;
4192 break;
4193 case BFD_RELOC_386_GOT32:
4194 case BFD_RELOC_X86_64_GOT32:
4195 value = 0; /* Fully resolved at runtime. No addend. */
4196 break;
4197 case BFD_RELOC_386_GOTOFF:
4198 case BFD_RELOC_X86_64_GOTPCREL:
4199 break;
4201 case BFD_RELOC_VTABLE_INHERIT:
4202 case BFD_RELOC_VTABLE_ENTRY:
4203 fixP->fx_done = 0;
4204 return 1;
4206 default:
4207 break;
4209 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
4210 *valp = value;
4211 #endif /* defined (BFD_ASSEMBLER) && !defined (TE_Mach) */
4213 #ifndef BFD_ASSEMBLER
4214 md_number_to_chars (p, value, fixP->fx_size);
4215 #else
4216 /* Are we finished with this relocation now? */
4217 if (fixP->fx_addsy == 0 && fixP->fx_pcrel == 0)
4218 fixP->fx_done = 1;
4219 else if (use_rela_relocations)
4221 fixP->fx_no_overflow = 1;
4222 value = 0;
4224 md_number_to_chars (p, value, fixP->fx_size);
4225 #endif
4227 return 1;
4230 #define MAX_LITTLENUMS 6
4232 /* Turn the string pointed to by litP into a floating point constant
4233 of type TYPE, and emit the appropriate bytes. The number of
4234 LITTLENUMS emitted is stored in *SIZEP. An error message is
4235 returned, or NULL on OK. */
4237 char *
4238 md_atof (type, litP, sizeP)
4239 int type;
4240 char *litP;
4241 int *sizeP;
4243 int prec;
4244 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4245 LITTLENUM_TYPE *wordP;
4246 char *t;
4248 switch (type)
4250 case 'f':
4251 case 'F':
4252 prec = 2;
4253 break;
4255 case 'd':
4256 case 'D':
4257 prec = 4;
4258 break;
4260 case 'x':
4261 case 'X':
4262 prec = 5;
4263 break;
4265 default:
4266 *sizeP = 0;
4267 return _("Bad call to md_atof ()");
4269 t = atof_ieee (input_line_pointer, type, words);
4270 if (t)
4271 input_line_pointer = t;
4273 *sizeP = prec * sizeof (LITTLENUM_TYPE);
4274 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
4275 the bigendian 386. */
4276 for (wordP = words + prec - 1; prec--;)
4278 md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE));
4279 litP += sizeof (LITTLENUM_TYPE);
4281 return 0;
4284 char output_invalid_buf[8];
4286 static char *
4287 output_invalid (c)
4288 int c;
4290 if (isprint (c))
4291 sprintf (output_invalid_buf, "'%c'", c);
4292 else
4293 sprintf (output_invalid_buf, "(0x%x)", (unsigned) c);
4294 return output_invalid_buf;
4297 /* REG_STRING starts *before* REGISTER_PREFIX. */
4299 static const reg_entry *
4300 parse_register (reg_string, end_op)
4301 char *reg_string;
4302 char **end_op;
4304 char *s = reg_string;
4305 char *p;
4306 char reg_name_given[MAX_REG_NAME_SIZE + 1];
4307 const reg_entry *r;
4309 /* Skip possible REGISTER_PREFIX and possible whitespace. */
4310 if (*s == REGISTER_PREFIX)
4311 ++s;
4313 if (is_space_char (*s))
4314 ++s;
4316 p = reg_name_given;
4317 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
4319 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
4320 return (const reg_entry *) NULL;
4321 s++;
4324 /* For naked regs, make sure that we are not dealing with an identifier.
4325 This prevents confusing an identifier like `eax_var' with register
4326 `eax'. */
4327 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
4328 return (const reg_entry *) NULL;
4330 *end_op = s;
4332 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
4334 /* Handle floating point regs, allowing spaces in the (i) part. */
4335 if (r == i386_regtab /* %st is first entry of table */)
4337 if (is_space_char (*s))
4338 ++s;
4339 if (*s == '(')
4341 ++s;
4342 if (is_space_char (*s))
4343 ++s;
4344 if (*s >= '0' && *s <= '7')
4346 r = &i386_float_regtab[*s - '0'];
4347 ++s;
4348 if (is_space_char (*s))
4349 ++s;
4350 if (*s == ')')
4352 *end_op = s + 1;
4353 return r;
4356 /* We have "%st(" then garbage. */
4357 return (const reg_entry *) NULL;
4361 return r;
4364 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4365 const char *md_shortopts = "kVQ:sq";
4366 #else
4367 const char *md_shortopts = "q";
4368 #endif
4369 struct option md_longopts[] = {
4370 #define OPTION_32 (OPTION_MD_BASE + 0)
4371 {"32", no_argument, NULL, OPTION_32},
4372 #define OPTION_64 (OPTION_MD_BASE + 1)
4373 {"64", no_argument, NULL, OPTION_64},
4374 {NULL, no_argument, NULL, 0}
4376 size_t md_longopts_size = sizeof (md_longopts);
4379 md_parse_option (c, arg)
4380 int c;
4381 char *arg ATTRIBUTE_UNUSED;
4383 switch (c)
4385 case 'q':
4386 quiet_warnings = 1;
4387 break;
4389 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4390 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
4391 should be emitted or not. FIXME: Not implemented. */
4392 case 'Q':
4393 break;
4395 /* -V: SVR4 argument to print version ID. */
4396 case 'V':
4397 print_version_id ();
4398 break;
4400 /* -k: Ignore for FreeBSD compatibility. */
4401 case 'k':
4402 break;
4404 case 's':
4405 /* -s: On i386 Solaris, this tells the native assembler to use
4406 .stab instead of .stab.excl. We always use .stab anyhow. */
4407 break;
4408 #endif
4409 #ifdef OBJ_ELF
4410 case OPTION_32:
4411 case OPTION_64:
4413 const char **list, **l;
4415 default_arch = c == OPTION_32 ? "i386" : "x86_64";
4416 list = bfd_target_list ();
4417 for (l = list; *l != NULL; l++)
4419 if (c == OPTION_32)
4421 if (strcmp (*l, "elf32-i386") == 0)
4422 break;
4424 else
4426 if (strcmp (*l, "elf64-x86-64") == 0)
4427 break;
4430 if (*l == NULL)
4431 as_fatal (_("No compiled in support for %d bit object file format"),
4432 c == OPTION_32 ? 32 : 64);
4433 free (list);
4435 break;
4436 #endif
4438 default:
4439 return 0;
4441 return 1;
4444 void
4445 md_show_usage (stream)
4446 FILE *stream;
4448 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4449 fprintf (stream, _("\
4450 -Q ignored\n\
4451 -V print assembler version number\n\
4452 -k ignored\n\
4453 -q quieten some warnings\n\
4454 -s ignored\n"));
4455 #else
4456 fprintf (stream, _("\
4457 -q quieten some warnings\n"));
4458 #endif
4461 #ifdef BFD_ASSEMBLER
4462 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
4463 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
4465 /* Pick the target format to use. */
4467 const char *
4468 i386_target_format ()
4470 if (!strcmp (default_arch, "x86_64"))
4471 set_code_flag (CODE_64BIT);
4472 else if (!strcmp (default_arch, "i386"))
4473 set_code_flag (CODE_32BIT);
4474 else
4475 as_fatal (_("Unknown architecture"));
4476 switch (OUTPUT_FLAVOR)
4478 #ifdef OBJ_MAYBE_AOUT
4479 case bfd_target_aout_flavour:
4480 return AOUT_TARGET_FORMAT;
4481 #endif
4482 #ifdef OBJ_MAYBE_COFF
4483 case bfd_target_coff_flavour:
4484 return "coff-i386";
4485 #endif
4486 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
4487 case bfd_target_elf_flavour:
4489 if (flag_code == CODE_64BIT)
4490 use_rela_relocations = 1;
4491 return flag_code == CODE_64BIT ? "elf64-x86-64" : "elf32-i386";
4493 #endif
4494 default:
4495 abort ();
4496 return NULL;
4500 #endif /* OBJ_MAYBE_ more than one */
4501 #endif /* BFD_ASSEMBLER */
4503 symbolS *
4504 md_undefined_symbol (name)
4505 char *name;
4507 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
4508 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
4509 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
4510 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
4512 if (!GOT_symbol)
4514 if (symbol_find (name))
4515 as_bad (_("GOT already in symbol table"));
4516 GOT_symbol = symbol_new (name, undefined_section,
4517 (valueT) 0, &zero_address_frag);
4519 return GOT_symbol;
4521 return 0;
4524 /* Round up a section size to the appropriate boundary. */
4526 valueT
4527 md_section_align (segment, size)
4528 segT segment ATTRIBUTE_UNUSED;
4529 valueT size;
4531 #ifdef BFD_ASSEMBLER
4532 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4533 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
4535 /* For a.out, force the section size to be aligned. If we don't do
4536 this, BFD will align it for us, but it will not write out the
4537 final bytes of the section. This may be a bug in BFD, but it is
4538 easier to fix it here since that is how the other a.out targets
4539 work. */
4540 int align;
4542 align = bfd_get_section_alignment (stdoutput, segment);
4543 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
4545 #endif
4546 #endif
4548 return size;
4551 /* On the i386, PC-relative offsets are relative to the start of the
4552 next instruction. That is, the address of the offset, plus its
4553 size, since the offset is always the last part of the insn. */
4555 long
4556 md_pcrel_from (fixP)
4557 fixS *fixP;
4559 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
4562 #ifndef I386COFF
4564 static void
4565 s_bss (ignore)
4566 int ignore ATTRIBUTE_UNUSED;
4568 register int temp;
4570 temp = get_absolute_expression ();
4571 subseg_set (bss_section, (subsegT) temp);
4572 demand_empty_rest_of_line ();
4575 #endif
4577 #ifdef BFD_ASSEMBLER
4579 void
4580 i386_validate_fix (fixp)
4581 fixS *fixp;
4583 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
4585 /* GOTOFF relocation are nonsense in 64bit mode. */
4586 if (flag_code == CODE_64BIT)
4587 abort();
4588 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
4589 fixp->fx_subsy = 0;
4593 arelent *
4594 tc_gen_reloc (section, fixp)
4595 asection *section ATTRIBUTE_UNUSED;
4596 fixS *fixp;
4598 arelent *rel;
4599 bfd_reloc_code_real_type code;
4601 switch (fixp->fx_r_type)
4603 case BFD_RELOC_X86_64_PLT32:
4604 case BFD_RELOC_X86_64_GOT32:
4605 case BFD_RELOC_X86_64_GOTPCREL:
4606 case BFD_RELOC_386_PLT32:
4607 case BFD_RELOC_386_GOT32:
4608 case BFD_RELOC_386_GOTOFF:
4609 case BFD_RELOC_386_GOTPC:
4610 case BFD_RELOC_X86_64_32S:
4611 case BFD_RELOC_RVA:
4612 case BFD_RELOC_VTABLE_ENTRY:
4613 case BFD_RELOC_VTABLE_INHERIT:
4614 code = fixp->fx_r_type;
4615 break;
4616 default:
4617 if (fixp->fx_pcrel)
4619 switch (fixp->fx_size)
4621 default:
4622 as_bad (_("can not do %d byte pc-relative relocation"),
4623 fixp->fx_size);
4624 code = BFD_RELOC_32_PCREL;
4625 break;
4626 case 1: code = BFD_RELOC_8_PCREL; break;
4627 case 2: code = BFD_RELOC_16_PCREL; break;
4628 case 4: code = BFD_RELOC_32_PCREL; break;
4631 else
4633 switch (fixp->fx_size)
4635 default:
4636 as_bad (_("can not do %d byte relocation"), fixp->fx_size);
4637 code = BFD_RELOC_32;
4638 break;
4639 case 1: code = BFD_RELOC_8; break;
4640 case 2: code = BFD_RELOC_16; break;
4641 case 4: code = BFD_RELOC_32; break;
4642 case 8: code = BFD_RELOC_64; break;
4645 break;
4648 if (code == BFD_RELOC_32
4649 && GOT_symbol
4650 && fixp->fx_addsy == GOT_symbol)
4652 /* We don't support GOTPC on 64bit targets. */
4653 if (flag_code == CODE_64BIT)
4654 abort();
4655 code = BFD_RELOC_386_GOTPC;
4658 rel = (arelent *) xmalloc (sizeof (arelent));
4659 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
4660 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
4662 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
4663 if (!use_rela_relocations)
4665 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
4666 vtable entry to be used in the relocation's section offset. */
4667 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
4668 rel->address = fixp->fx_offset;
4670 if (fixp->fx_pcrel)
4671 rel->addend = fixp->fx_addnumber;
4672 else
4673 rel->addend = 0;
4675 /* Use the rela in 64bit mode. */
4676 else
4678 rel->addend = fixp->fx_offset;
4679 #ifdef OBJ_ELF
4680 /* Ohhh, this is ugly. The problem is that if this is a local global
4681 symbol, the relocation will entirely be performed at link time, not
4682 at assembly time. bfd_perform_reloc doesn't know about this sort
4683 of thing, and as a result we need to fake it out here. */
4684 if ((S_IS_EXTERN (fixp->fx_addsy) || S_IS_WEAK (fixp->fx_addsy))
4685 && !S_IS_COMMON(fixp->fx_addsy))
4686 rel->addend -= symbol_get_bfdsym (fixp->fx_addsy)->value;
4687 #endif
4688 if (fixp->fx_pcrel)
4689 rel->addend -= fixp->fx_size;
4693 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
4694 if (rel->howto == NULL)
4696 as_bad_where (fixp->fx_file, fixp->fx_line,
4697 _("cannot represent relocation type %s"),
4698 bfd_get_reloc_code_name (code));
4699 /* Set howto to a garbage value so that we can keep going. */
4700 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
4701 assert (rel->howto != NULL);
4704 return rel;
4707 #else /* ! BFD_ASSEMBLER */
4709 #if (defined(OBJ_AOUT) | defined(OBJ_BOUT))
4710 void
4711 tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
4712 char *where;
4713 fixS *fixP;
4714 relax_addressT segment_address_in_file;
4716 /* In: length of relocation (or of address) in chars: 1, 2 or 4.
4717 Out: GNU LD relocation length code: 0, 1, or 2. */
4719 static const unsigned char nbytes_r_length[] = { 42, 0, 1, 42, 2 };
4720 long r_symbolnum;
4722 know (fixP->fx_addsy != NULL);
4724 md_number_to_chars (where,
4725 (valueT) (fixP->fx_frag->fr_address
4726 + fixP->fx_where - segment_address_in_file),
4729 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
4730 ? S_GET_TYPE (fixP->fx_addsy)
4731 : fixP->fx_addsy->sy_number);
4733 where[6] = (r_symbolnum >> 16) & 0x0ff;
4734 where[5] = (r_symbolnum >> 8) & 0x0ff;
4735 where[4] = r_symbolnum & 0x0ff;
4736 where[7] = ((((!S_IS_DEFINED (fixP->fx_addsy)) << 3) & 0x08)
4737 | ((nbytes_r_length[fixP->fx_size] << 1) & 0x06)
4738 | (((fixP->fx_pcrel << 0) & 0x01) & 0x0f));
4741 #endif /* OBJ_AOUT or OBJ_BOUT. */
4743 #if defined (I386COFF)
4745 short
4746 tc_coff_fix2rtype (fixP)
4747 fixS *fixP;
4749 if (fixP->fx_r_type == R_IMAGEBASE)
4750 return R_IMAGEBASE;
4752 return (fixP->fx_pcrel ?
4753 (fixP->fx_size == 1 ? R_PCRBYTE :
4754 fixP->fx_size == 2 ? R_PCRWORD :
4755 R_PCRLONG) :
4756 (fixP->fx_size == 1 ? R_RELBYTE :
4757 fixP->fx_size == 2 ? R_RELWORD :
4758 R_DIR32));
4762 tc_coff_sizemachdep (frag)
4763 fragS *frag;
4765 if (frag->fr_next)
4766 return (frag->fr_next->fr_address - frag->fr_address);
4767 else
4768 return 0;
4771 #endif /* I386COFF */
4773 #endif /* ! BFD_ASSEMBLER */
4775 /* Parse operands using Intel syntax. This implements a recursive descent
4776 parser based on the BNF grammar published in Appendix B of the MASM 6.1
4777 Programmer's Guide.
4779 FIXME: We do not recognize the full operand grammar defined in the MASM
4780 documentation. In particular, all the structure/union and
4781 high-level macro operands are missing.
4783 Uppercase words are terminals, lower case words are non-terminals.
4784 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
4785 bars '|' denote choices. Most grammar productions are implemented in
4786 functions called 'intel_<production>'.
4788 Initial production is 'expr'.
4790 addOp + | -
4792 alpha [a-zA-Z]
4794 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
4796 constant digits [[ radixOverride ]]
4798 dataType BYTE | WORD | DWORD | QWORD | XWORD
4800 digits decdigit
4801 | digits decdigit
4802 | digits hexdigit
4804 decdigit [0-9]
4806 e05 e05 addOp e06
4807 | e06
4809 e06 e06 mulOp e09
4810 | e09
4812 e09 OFFSET e10
4813 | e09 PTR e10
4814 | e09 : e10
4815 | e10
4817 e10 e10 [ expr ]
4818 | e11
4820 e11 ( expr )
4821 | [ expr ]
4822 | constant
4823 | dataType
4824 | id
4826 | register
4828 => expr SHORT e05
4829 | e05
4831 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
4832 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
4834 hexdigit a | b | c | d | e | f
4835 | A | B | C | D | E | F
4837 id alpha
4838 | id alpha
4839 | id decdigit
4841 mulOp * | / | MOD
4843 quote " | '
4845 register specialRegister
4846 | gpRegister
4847 | byteRegister
4849 segmentRegister CS | DS | ES | FS | GS | SS
4851 specialRegister CR0 | CR2 | CR3
4852 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
4853 | TR3 | TR4 | TR5 | TR6 | TR7
4855 We simplify the grammar in obvious places (e.g., register parsing is
4856 done by calling parse_register) and eliminate immediate left recursion
4857 to implement a recursive-descent parser.
4859 expr SHORT e05
4860 | e05
4862 e05 e06 e05'
4864 e05' addOp e06 e05'
4865 | Empty
4867 e06 e09 e06'
4869 e06' mulOp e09 e06'
4870 | Empty
4872 e09 OFFSET e10 e09'
4873 | e10 e09'
4875 e09' PTR e10 e09'
4876 | : e10 e09'
4877 | Empty
4879 e10 e11 e10'
4881 e10' [ expr ] e10'
4882 | Empty
4884 e11 ( expr )
4885 | [ expr ]
4886 | BYTE
4887 | WORD
4888 | DWORD
4889 | QWORD
4890 | XWORD
4893 | register
4894 | id
4895 | constant */
4897 /* Parsing structure for the intel syntax parser. Used to implement the
4898 semantic actions for the operand grammar. */
4899 struct intel_parser_s
4901 char *op_string; /* The string being parsed. */
4902 int got_a_float; /* Whether the operand is a float. */
4903 int op_modifier; /* Operand modifier. */
4904 int is_mem; /* 1 if operand is memory reference. */
4905 const reg_entry *reg; /* Last register reference found. */
4906 char *disp; /* Displacement string being built. */
4909 static struct intel_parser_s intel_parser;
4911 /* Token structure for parsing intel syntax. */
4912 struct intel_token
4914 int code; /* Token code. */
4915 const reg_entry *reg; /* Register entry for register tokens. */
4916 char *str; /* String representation. */
4919 static struct intel_token cur_token, prev_token;
4922 /* Token codes for the intel parser. Since T_SHORT is already used
4923 by COFF, undefine it first to prevent a warning. */
4924 #define T_NIL -1
4925 #define T_CONST 1
4926 #define T_REG 2
4927 #define T_BYTE 3
4928 #define T_WORD 4
4929 #define T_DWORD 5
4930 #define T_QWORD 6
4931 #define T_XWORD 7
4932 #undef T_SHORT
4933 #define T_SHORT 8
4934 #define T_OFFSET 9
4935 #define T_PTR 10
4936 #define T_ID 11
4938 /* Prototypes for intel parser functions. */
4939 static int intel_match_token PARAMS ((int code));
4940 static void intel_get_token PARAMS ((void));
4941 static void intel_putback_token PARAMS ((void));
4942 static int intel_expr PARAMS ((void));
4943 static int intel_e05 PARAMS ((void));
4944 static int intel_e05_1 PARAMS ((void));
4945 static int intel_e06 PARAMS ((void));
4946 static int intel_e06_1 PARAMS ((void));
4947 static int intel_e09 PARAMS ((void));
4948 static int intel_e09_1 PARAMS ((void));
4949 static int intel_e10 PARAMS ((void));
4950 static int intel_e10_1 PARAMS ((void));
4951 static int intel_e11 PARAMS ((void));
4953 static int
4954 i386_intel_operand (operand_string, got_a_float)
4955 char *operand_string;
4956 int got_a_float;
4958 int ret;
4959 char *p;
4961 /* Initialize token holders. */
4962 cur_token.code = prev_token.code = T_NIL;
4963 cur_token.reg = prev_token.reg = NULL;
4964 cur_token.str = prev_token.str = NULL;
4966 /* Initialize parser structure. */
4967 p = intel_parser.op_string = (char *)malloc (strlen (operand_string) + 1);
4968 if (p == NULL)
4969 abort ();
4970 strcpy (intel_parser.op_string, operand_string);
4971 intel_parser.got_a_float = got_a_float;
4972 intel_parser.op_modifier = -1;
4973 intel_parser.is_mem = 0;
4974 intel_parser.reg = NULL;
4975 intel_parser.disp = (char *)malloc (strlen (operand_string) + 1);
4976 if (intel_parser.disp == NULL)
4977 abort ();
4978 intel_parser.disp[0] = '\0';
4980 /* Read the first token and start the parser. */
4981 intel_get_token ();
4982 ret = intel_expr ();
4984 if (ret)
4986 /* If we found a memory reference, hand it over to i386_displacement
4987 to fill in the rest of the operand fields. */
4988 if (intel_parser.is_mem)
4990 if ((i.mem_operands == 1
4991 && (current_templates->start->opcode_modifier & IsString) == 0)
4992 || i.mem_operands == 2)
4994 as_bad (_("too many memory references for '%s'"),
4995 current_templates->start->name);
4996 ret = 0;
4998 else
5000 char *s = intel_parser.disp;
5001 i.mem_operands++;
5003 /* Add the displacement expression. */
5004 if (*s != '\0')
5005 ret = i386_displacement (s, s + strlen (s))
5006 && i386_index_check (s);
5010 /* Constant and OFFSET expressions are handled by i386_immediate. */
5011 else if (intel_parser.op_modifier == OFFSET_FLAT
5012 || intel_parser.reg == NULL)
5013 ret = i386_immediate (intel_parser.disp);
5016 free (p);
5017 free (intel_parser.disp);
5019 return ret;
5022 /* expr SHORT e05
5023 | e05 */
5024 static int
5025 intel_expr ()
5027 /* expr SHORT e05 */
5028 if (cur_token.code == T_SHORT)
5030 intel_parser.op_modifier = SHORT;
5031 intel_match_token (T_SHORT);
5033 return (intel_e05 ());
5036 /* expr e05 */
5037 else
5038 return intel_e05 ();
5041 /* e05 e06 e05'
5043 e05' addOp e06 e05'
5044 | Empty */
5045 static int
5046 intel_e05 ()
5048 return (intel_e06 () && intel_e05_1 ());
5051 static int
5052 intel_e05_1 ()
5054 /* e05' addOp e06 e05' */
5055 if (cur_token.code == '+' || cur_token.code == '-')
5057 strcat (intel_parser.disp, cur_token.str);
5058 intel_match_token (cur_token.code);
5060 return (intel_e06 () && intel_e05_1 ());
5063 /* e05' Empty */
5064 else
5065 return 1;
5068 /* e06 e09 e06'
5070 e06' mulOp e09 e06'
5071 | Empty */
5072 static int
5073 intel_e06 ()
5075 return (intel_e09 () && intel_e06_1 ());
5078 static int
5079 intel_e06_1 ()
5081 /* e06' mulOp e09 e06' */
5082 if (cur_token.code == '*' || cur_token.code == '/')
5084 strcat (intel_parser.disp, cur_token.str);
5085 intel_match_token (cur_token.code);
5087 return (intel_e09 () && intel_e06_1 ());
5090 /* e06' Empty */
5091 else
5092 return 1;
5095 /* e09 OFFSET e10 e09'
5096 | e10 e09'
5098 e09' PTR e10 e09'
5099 | : e10 e09'
5100 | Empty */
5101 static int
5102 intel_e09 ()
5104 /* e09 OFFSET e10 e09' */
5105 if (cur_token.code == T_OFFSET)
5107 intel_parser.is_mem = 0;
5108 intel_parser.op_modifier = OFFSET_FLAT;
5109 intel_match_token (T_OFFSET);
5111 return (intel_e10 () && intel_e09_1 ());
5114 /* e09 e10 e09' */
5115 else
5116 return (intel_e10 () && intel_e09_1 ());
5119 static int
5120 intel_e09_1 ()
5122 /* e09' PTR e10 e09' */
5123 if (cur_token.code == T_PTR)
5125 if (prev_token.code == T_BYTE)
5126 i.suffix = BYTE_MNEM_SUFFIX;
5128 else if (prev_token.code == T_WORD)
5130 if (intel_parser.got_a_float == 2) /* "fi..." */
5131 i.suffix = SHORT_MNEM_SUFFIX;
5132 else
5133 i.suffix = WORD_MNEM_SUFFIX;
5136 else if (prev_token.code == T_DWORD)
5138 if (intel_parser.got_a_float == 1) /* "f..." */
5139 i.suffix = SHORT_MNEM_SUFFIX;
5140 else
5141 i.suffix = LONG_MNEM_SUFFIX;
5144 else if (prev_token.code == T_QWORD)
5146 if (intel_parser.got_a_float == 1) /* "f..." */
5147 i.suffix = LONG_MNEM_SUFFIX;
5148 else
5149 i.suffix = QWORD_MNEM_SUFFIX;
5152 else if (prev_token.code == T_XWORD)
5153 i.suffix = LONG_DOUBLE_MNEM_SUFFIX;
5155 else
5157 as_bad (_("Unknown operand modifier `%s'\n"), prev_token.str);
5158 return 0;
5161 intel_match_token (T_PTR);
5163 return (intel_e10 () && intel_e09_1 ());
5166 /* e09 : e10 e09' */
5167 else if (cur_token.code == ':')
5169 /* Mark as a memory operand only if it's not already known to be an
5170 offset expression. */
5171 if (intel_parser.op_modifier != OFFSET_FLAT)
5172 intel_parser.is_mem = 1;
5174 return (intel_match_token (':') && intel_e10 () && intel_e09_1 ());
5177 /* e09' Empty */
5178 else
5179 return 1;
5182 /* e10 e11 e10'
5184 e10' [ expr ] e10'
5185 | Empty */
5186 static int
5187 intel_e10 ()
5189 return (intel_e11 () && intel_e10_1 ());
5192 static int
5193 intel_e10_1 ()
5195 /* e10' [ expr ] e10' */
5196 if (cur_token.code == '[')
5198 intel_match_token ('[');
5200 /* Mark as a memory operand only if it's not already known to be an
5201 offset expression. If it's an offset expression, we need to keep
5202 the brace in. */
5203 if (intel_parser.op_modifier != OFFSET_FLAT)
5204 intel_parser.is_mem = 1;
5205 else
5206 strcat (intel_parser.disp, "[");
5208 /* Add a '+' to the displacement string if necessary. */
5209 if (*intel_parser.disp != '\0'
5210 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
5211 strcat (intel_parser.disp, "+");
5213 if (intel_expr () && intel_match_token (']'))
5215 /* Preserve brackets when the operand is an offset expression. */
5216 if (intel_parser.op_modifier == OFFSET_FLAT)
5217 strcat (intel_parser.disp, "]");
5219 return intel_e10_1 ();
5221 else
5222 return 0;
5225 /* e10' Empty */
5226 else
5227 return 1;
5230 /* e11 ( expr )
5231 | [ expr ]
5232 | BYTE
5233 | WORD
5234 | DWORD
5235 | QWORD
5236 | XWORD
5239 | register
5240 | id
5241 | constant */
5242 static int
5243 intel_e11 ()
5245 /* e11 ( expr ) */
5246 if (cur_token.code == '(')
5248 intel_match_token ('(');
5249 strcat (intel_parser.disp, "(");
5251 if (intel_expr () && intel_match_token (')'))
5253 strcat (intel_parser.disp, ")");
5254 return 1;
5256 else
5257 return 0;
5260 /* e11 [ expr ] */
5261 else if (cur_token.code == '[')
5263 intel_match_token ('[');
5265 /* Mark as a memory operand only if it's not already known to be an
5266 offset expression. If it's an offset expression, we need to keep
5267 the brace in. */
5268 if (intel_parser.op_modifier != OFFSET_FLAT)
5269 intel_parser.is_mem = 1;
5270 else
5271 strcat (intel_parser.disp, "[");
5273 /* Operands for jump/call inside brackets denote absolute addresses. */
5274 if (current_templates->start->opcode_modifier & Jump
5275 || current_templates->start->opcode_modifier & JumpDword
5276 || current_templates->start->opcode_modifier & JumpByte
5277 || current_templates->start->opcode_modifier & JumpInterSegment)
5278 i.types[this_operand] |= JumpAbsolute;
5280 /* Add a '+' to the displacement string if necessary. */
5281 if (*intel_parser.disp != '\0'
5282 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
5283 strcat (intel_parser.disp, "+");
5285 if (intel_expr () && intel_match_token (']'))
5287 /* Preserve brackets when the operand is an offset expression. */
5288 if (intel_parser.op_modifier == OFFSET_FLAT)
5289 strcat (intel_parser.disp, "]");
5291 return 1;
5293 else
5294 return 0;
5297 /* e11 BYTE
5298 | WORD
5299 | DWORD
5300 | QWORD
5301 | XWORD */
5302 else if (cur_token.code == T_BYTE
5303 || cur_token.code == T_WORD
5304 || cur_token.code == T_DWORD
5305 || cur_token.code == T_QWORD
5306 || cur_token.code == T_XWORD)
5308 intel_match_token (cur_token.code);
5310 return 1;
5313 /* e11 $
5314 | . */
5315 else if (cur_token.code == '$' || cur_token.code == '.')
5317 strcat (intel_parser.disp, cur_token.str);
5318 intel_match_token (cur_token.code);
5320 /* Mark as a memory operand only if it's not already known to be an
5321 offset expression. */
5322 if (intel_parser.op_modifier != OFFSET_FLAT)
5323 intel_parser.is_mem = 1;
5325 return 1;
5328 /* e11 register */
5329 else if (cur_token.code == T_REG)
5331 const reg_entry *reg = intel_parser.reg = cur_token.reg;
5333 intel_match_token (T_REG);
5335 /* Check for segment change. */
5336 if (cur_token.code == ':')
5338 if (reg->reg_type & (SReg2 | SReg3))
5340 switch (reg->reg_num)
5342 case 0:
5343 i.seg[i.mem_operands] = &es;
5344 break;
5345 case 1:
5346 i.seg[i.mem_operands] = &cs;
5347 break;
5348 case 2:
5349 i.seg[i.mem_operands] = &ss;
5350 break;
5351 case 3:
5352 i.seg[i.mem_operands] = &ds;
5353 break;
5354 case 4:
5355 i.seg[i.mem_operands] = &fs;
5356 break;
5357 case 5:
5358 i.seg[i.mem_operands] = &gs;
5359 break;
5362 else
5364 as_bad (_("`%s' is not a valid segment register"), reg->reg_name);
5365 return 0;
5369 /* Not a segment register. Check for register scaling. */
5370 else if (cur_token.code == '*')
5372 if (!intel_parser.is_mem)
5374 as_bad (_("Register scaling only allowed in memory operands."));
5375 return 0;
5378 /* What follows must be a valid scale. */
5379 if (intel_match_token ('*')
5380 && strchr ("01248", *cur_token.str))
5382 i.index_reg = reg;
5383 i.types[this_operand] |= BaseIndex;
5385 /* Set the scale after setting the register (otherwise,
5386 i386_scale will complain) */
5387 i386_scale (cur_token.str);
5388 intel_match_token (T_CONST);
5390 else
5392 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
5393 cur_token.str);
5394 return 0;
5398 /* No scaling. If this is a memory operand, the register is either a
5399 base register (first occurrence) or an index register (second
5400 occurrence). */
5401 else if (intel_parser.is_mem && !(reg->reg_type & (SReg2 | SReg3)))
5403 if (i.base_reg && i.index_reg)
5405 as_bad (_("Too many register references in memory operand.\n"));
5406 return 0;
5409 if (i.base_reg == NULL)
5410 i.base_reg = reg;
5411 else
5412 i.index_reg = reg;
5414 i.types[this_operand] |= BaseIndex;
5417 /* Offset modifier. Add the register to the displacement string to be
5418 parsed as an immediate expression after we're done. */
5419 else if (intel_parser.op_modifier == OFFSET_FLAT)
5420 strcat (intel_parser.disp, reg->reg_name);
5422 /* It's neither base nor index nor offset. */
5423 else
5425 i.types[this_operand] |= reg->reg_type & ~BaseIndex;
5426 i.op[this_operand].regs = reg;
5427 i.reg_operands++;
5430 /* Since registers are not part of the displacement string (except
5431 when we're parsing offset operands), we may need to remove any
5432 preceding '+' from the displacement string. */
5433 if (*intel_parser.disp != '\0'
5434 && intel_parser.op_modifier != OFFSET_FLAT)
5436 char *s = intel_parser.disp;
5437 s += strlen (s) - 1;
5438 if (*s == '+')
5439 *s = '\0';
5442 return 1;
5445 /* e11 id */
5446 else if (cur_token.code == T_ID)
5448 /* Add the identifier to the displacement string. */
5449 strcat (intel_parser.disp, cur_token.str);
5450 intel_match_token (T_ID);
5452 /* The identifier represents a memory reference only if it's not
5453 preceded by an offset modifier. */
5454 if (intel_parser.op_modifier != OFFSET_FLAT)
5455 intel_parser.is_mem = 1;
5457 return 1;
5460 /* e11 constant */
5461 else if (cur_token.code == T_CONST
5462 || cur_token.code == '-'
5463 || cur_token.code == '+')
5465 char *save_str;
5467 /* Allow constants that start with `+' or `-'. */
5468 if (cur_token.code == '-' || cur_token.code == '+')
5470 strcat (intel_parser.disp, cur_token.str);
5471 intel_match_token (cur_token.code);
5472 if (cur_token.code != T_CONST)
5474 as_bad (_("Syntax error. Expecting a constant. Got `%s'.\n"),
5475 cur_token.str);
5476 return 0;
5480 save_str = (char *)malloc (strlen (cur_token.str) + 1);
5481 if (save_str == NULL)
5482 abort ();
5483 strcpy (save_str, cur_token.str);
5485 /* Get the next token to check for register scaling. */
5486 intel_match_token (cur_token.code);
5488 /* Check if this constant is a scaling factor for an index register. */
5489 if (cur_token.code == '*')
5491 if (intel_match_token ('*') && cur_token.code == T_REG)
5493 if (!intel_parser.is_mem)
5495 as_bad (_("Register scaling only allowed in memory operands."));
5496 return 0;
5499 /* The constant is followed by `* reg', so it must be
5500 a valid scale. */
5501 if (strchr ("01248", *save_str))
5503 i.index_reg = cur_token.reg;
5504 i.types[this_operand] |= BaseIndex;
5506 /* Set the scale after setting the register (otherwise,
5507 i386_scale will complain) */
5508 i386_scale (save_str);
5509 intel_match_token (T_REG);
5511 /* Since registers are not part of the displacement
5512 string, we may need to remove any preceding '+' from
5513 the displacement string. */
5514 if (*intel_parser.disp != '\0')
5516 char *s = intel_parser.disp;
5517 s += strlen (s) - 1;
5518 if (*s == '+')
5519 *s = '\0';
5522 free (save_str);
5524 return 1;
5526 else
5527 return 0;
5530 /* The constant was not used for register scaling. Since we have
5531 already consumed the token following `*' we now need to put it
5532 back in the stream. */
5533 else
5534 intel_putback_token ();
5537 /* Add the constant to the displacement string. */
5538 strcat (intel_parser.disp, save_str);
5539 free (save_str);
5541 return 1;
5544 as_bad (_("Unrecognized token '%s'"), cur_token.str);
5545 return 0;
5548 /* Match the given token against cur_token. If they match, read the next
5549 token from the operand string. */
5550 static int
5551 intel_match_token (code)
5552 int code;
5554 if (cur_token.code == code)
5556 intel_get_token ();
5557 return 1;
5559 else
5561 as_bad (_("Unexpected token `%s'\n"), cur_token.str);
5562 return 0;
5566 /* Read a new token from intel_parser.op_string and store it in cur_token. */
5567 static void
5568 intel_get_token ()
5570 char *end_op;
5571 const reg_entry *reg;
5572 struct intel_token new_token;
5574 new_token.code = T_NIL;
5575 new_token.reg = NULL;
5576 new_token.str = NULL;
5578 /* Free the memory allocated to the previous token and move
5579 cur_token to prev_token. */
5580 if (prev_token.str)
5581 free (prev_token.str);
5583 prev_token = cur_token;
5585 /* Skip whitespace. */
5586 while (is_space_char (*intel_parser.op_string))
5587 intel_parser.op_string++;
5589 /* Return an empty token if we find nothing else on the line. */
5590 if (*intel_parser.op_string == '\0')
5592 cur_token = new_token;
5593 return;
5596 /* The new token cannot be larger than the remainder of the operand
5597 string. */
5598 new_token.str = (char *)malloc (strlen (intel_parser.op_string) + 1);
5599 if (new_token.str == NULL)
5600 abort ();
5601 new_token.str[0] = '\0';
5603 if (strchr ("0123456789", *intel_parser.op_string))
5605 char *p = new_token.str;
5606 char *q = intel_parser.op_string;
5607 new_token.code = T_CONST;
5609 /* Allow any kind of identifier char to encompass floating point and
5610 hexadecimal numbers. */
5611 while (is_identifier_char (*q))
5612 *p++ = *q++;
5613 *p = '\0';
5615 /* Recognize special symbol names [0-9][bf]. */
5616 if (strlen (intel_parser.op_string) == 2
5617 && (intel_parser.op_string[1] == 'b'
5618 || intel_parser.op_string[1] == 'f'))
5619 new_token.code = T_ID;
5622 else if (strchr ("+-/*:[]()", *intel_parser.op_string))
5624 new_token.code = *intel_parser.op_string;
5625 new_token.str[0] = *intel_parser.op_string;
5626 new_token.str[1] = '\0';
5629 else if ((*intel_parser.op_string == REGISTER_PREFIX || allow_naked_reg)
5630 && ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL))
5632 new_token.code = T_REG;
5633 new_token.reg = reg;
5635 if (*intel_parser.op_string == REGISTER_PREFIX)
5637 new_token.str[0] = REGISTER_PREFIX;
5638 new_token.str[1] = '\0';
5641 strcat (new_token.str, reg->reg_name);
5644 else if (is_identifier_char (*intel_parser.op_string))
5646 char *p = new_token.str;
5647 char *q = intel_parser.op_string;
5649 /* A '.' or '$' followed by an identifier char is an identifier.
5650 Otherwise, it's operator '.' followed by an expression. */
5651 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
5653 new_token.code = *q;
5654 new_token.str[0] = *q;
5655 new_token.str[1] = '\0';
5657 else
5659 while (is_identifier_char (*q) || *q == '@')
5660 *p++ = *q++;
5661 *p = '\0';
5663 if (strcasecmp (new_token.str, "BYTE") == 0)
5664 new_token.code = T_BYTE;
5666 else if (strcasecmp (new_token.str, "WORD") == 0)
5667 new_token.code = T_WORD;
5669 else if (strcasecmp (new_token.str, "DWORD") == 0)
5670 new_token.code = T_DWORD;
5672 else if (strcasecmp (new_token.str, "QWORD") == 0)
5673 new_token.code = T_QWORD;
5675 else if (strcasecmp (new_token.str, "XWORD") == 0)
5676 new_token.code = T_XWORD;
5678 else if (strcasecmp (new_token.str, "PTR") == 0)
5679 new_token.code = T_PTR;
5681 else if (strcasecmp (new_token.str, "SHORT") == 0)
5682 new_token.code = T_SHORT;
5684 else if (strcasecmp (new_token.str, "OFFSET") == 0)
5686 new_token.code = T_OFFSET;
5688 /* ??? This is not mentioned in the MASM grammar but gcc
5689 makes use of it with -mintel-syntax. OFFSET may be
5690 followed by FLAT: */
5691 if (strncasecmp (q, " FLAT:", 6) == 0)
5692 strcat (new_token.str, " FLAT:");
5695 /* ??? This is not mentioned in the MASM grammar. */
5696 else if (strcasecmp (new_token.str, "FLAT") == 0)
5697 new_token.code = T_OFFSET;
5699 else
5700 new_token.code = T_ID;
5704 else
5705 as_bad (_("Unrecognized token `%s'\n"), intel_parser.op_string);
5707 intel_parser.op_string += strlen (new_token.str);
5708 cur_token = new_token;
5711 /* Put cur_token back into the token stream and make cur_token point to
5712 prev_token. */
5713 static void
5714 intel_putback_token ()
5716 intel_parser.op_string -= strlen (cur_token.str);
5717 free (cur_token.str);
5718 cur_token = prev_token;
5720 /* Forget prev_token. */
5721 prev_token.code = T_NIL;
5722 prev_token.reg = NULL;
5723 prev_token.str = NULL;