opcodes/i386-opc.h

   1 /* Declarations for Intel 80386 opcode table
   2    Copyright 2007, 2008, 2009
   3    Free Software Foundation, Inc.
   4
   5    This file is part of the GNU opcodes library.
   6
   7    This library is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3, or (at your option)
  10    any later version.
  11
  12    It is distributed in the hope that it will be useful, but WITHOUT
  13    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15    License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GAS; see the file COPYING.  If not, write to the Free
  19    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
  20    02110-1301, USA.  */
  21
  22 #include "opcode/i386.h"
  23 #ifdef HAVE_LIMITS_H
  24 #include <limits.h>
  25 #endif
  26
  27 #ifndef CHAR_BIT
  28 #define CHAR_BIT 8
  29 #endif
  30
  31 /* Position of cpu flags bitfiled.  */
  32
  33 enum
  34 {
  35   /* i186 or better required */
  36   Cpu186 = 0,
  37   /* i286 or better required */
  38   Cpu286,
  39   /* i386 or better required */
  40   Cpu386,
  41   /* i486 or better required */
  42   Cpu486,
  43   /* i585 or better required */
  44   Cpu586,
  45   /* i686 or better required */
  46   Cpu686,
  47   /* CLFLUSH Instuction support required */
  48   CpuClflush,
  49   /* SYSCALL Instuctions support required */
  50   CpuSYSCALL,
  51   /* Floating point support required */
  52   Cpu8087,
  53   /* i287 support required */
  54   Cpu287,
  55   /* i387 support required */
  56   Cpu387,
  57   /* i686 and floating point support required */
  58   Cpu687,
  59   /* SSE3 and floating point support required */
  60   CpuFISTTP,
  61   /* MMX support required */
  62   CpuMMX,
  63   /* SSE support required */
  64   CpuSSE,
  65   /* SSE2 support required */
  66   CpuSSE2,
  67   /* 3dnow! support required */
  68   Cpu3dnow,
  69   /* 3dnow! Extensions support required */
  70   Cpu3dnowA,
  71   /* SSE3 support required */
  72   CpuSSE3,
  73   /* VIA PadLock required */
  74   CpuPadLock,
  75   /* AMD Secure Virtual Machine Ext-s required */
  76   CpuSVME,
  77   /* VMX Instructions required */
  78   CpuVMX,
  79   /* SMX Instructions required */
  80   CpuSMX,
  81   /* SSSE3 support required */
  82   CpuSSSE3,
  83   /* SSE4a support required */
  84   CpuSSE4a,
  85   /* ABM New Instructions required */
  86   CpuABM,
  87   /* SSE4.1 support required */
  88   CpuSSE4_1,
  89   /* SSE4.2 support required */
  90   CpuSSE4_2,
  91   /* AVX support required */
  92   CpuAVX,
  93   /* Intel L1OM support required */
  94   CpuL1OM,
  95   /* Xsave/xrstor New Instuctions support required */
  96   CpuXsave,
  97   /* AES support required */
  98   CpuAES,
  99   /* PCLMUL support required */
 100   CpuPCLMUL,
 101   /* FMA support required */
 102   CpuFMA,
 103   /* FMA4 support required */
 104   CpuFMA4,
 105   /* XOP support required */
 106   CpuXOP,
 107   /* LWP support required */
 108   CpuLWP,
 109   /* MOVBE Instuction support required */
 110   CpuMovbe,
 111   /* EPT Instructions required */
 112   CpuEPT,
 113   /* RDTSCP Instuction support required */
 114   CpuRdtscp,
 115   /* 64bit support available, used by -march= in assembler.  */
 116   CpuLM,
 117   /* 64bit support required  */
 118   Cpu64,
 119   /* Not supported in the 64bit mode  */
 120   CpuNo64,
 121   /* The last bitfield in i386_cpu_flags.  */
 122   CpuMax = CpuNo64
 123 };
 124
 125 #define CpuNumOfUints \
 126   (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
 127 #define CpuNumOfBits \
 128   (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 129
 130 /* If you get a compiler error for zero width of the unused field,
 131    comment it out.  */
 132 #define CpuUnused       (CpuMax + 1)
 133
 134 /* We can check if an instruction is available with array instead
 135    of bitfield. */
 136 typedef union i386_cpu_flags
 137 {
 138   struct
 139     {
 140       unsigned int cpui186:1;
 141       unsigned int cpui286:1;
 142       unsigned int cpui386:1;
 143       unsigned int cpui486:1;
 144       unsigned int cpui586:1;
 145       unsigned int cpui686:1;
 146       unsigned int cpuclflush:1;
 147       unsigned int cpusyscall:1;
 148       unsigned int cpu8087:1;
 149       unsigned int cpu287:1;
 150       unsigned int cpu387:1;
 151       unsigned int cpu687:1;
 152       unsigned int cpufisttp:1;
 153       unsigned int cpummx:1;
 154       unsigned int cpusse:1;
 155       unsigned int cpusse2:1;
 156       unsigned int cpua3dnow:1;
 157       unsigned int cpua3dnowa:1;
 158       unsigned int cpusse3:1;
 159       unsigned int cpupadlock:1;
 160       unsigned int cpusvme:1;
 161       unsigned int cpuvmx:1;
 162       unsigned int cpusmx:1;
 163       unsigned int cpussse3:1;
 164       unsigned int cpusse4a:1;
 165       unsigned int cpuabm:1;
 166       unsigned int cpusse4_1:1;
 167       unsigned int cpusse4_2:1;
 168       unsigned int cpuavx:1;
 169       unsigned int cpul1om:1;
 170       unsigned int cpuxsave:1;
 171       unsigned int cpuaes:1;
 172       unsigned int cpupclmul:1;
 173       unsigned int cpufma:1;
 174       unsigned int cpufma4:1;
 175       unsigned int cpuxop:1;
 176       unsigned int cpulwp:1;
 177       unsigned int cpumovbe:1;
 178       unsigned int cpuept:1;
 179       unsigned int cpurdtscp:1;
 180       unsigned int cpulm:1;
 181       unsigned int cpu64:1;
 182       unsigned int cpuno64:1;
 183 #ifdef CpuUnused
 184       unsigned int unused:(CpuNumOfBits - CpuUnused);
 185 #endif
 186     } bitfield;
 187   unsigned int array[CpuNumOfUints];
 188 } i386_cpu_flags;
 189
 190 /* Position of opcode_modifier bits.  */
 191
 192 enum
 193 {
 194   /* has direction bit. */
 195   D = 0,
 196   /* set if operands can be words or dwords encoded the canonical way */
 197   W,
 198   /* Skip the current insn and use the next insn in i386-opc.tbl to swap
 199      operand in encoding.  */
 200   S,
 201   /* insn has a modrm byte. */
 202   Modrm,
 203   /* register is in low 3 bits of opcode */
 204   ShortForm,
 205   /* special case for jump insns.  */
 206   Jump,
 207   /* call and jump */
 208   JumpDword,
 209   /* loop and jecxz */
 210   JumpByte,
 211   /* special case for intersegment leaps/calls */
 212   JumpInterSegment,
 213   /* FP insn memory format bit, sized by 0x4 */
 214   FloatMF,
 215   /* src/dest swap for floats. */
 216   FloatR,
 217   /* has float insn direction bit. */
 218   FloatD,
 219   /* needs size prefix if in 32-bit mode */
 220   Size16,
 221   /* needs size prefix if in 16-bit mode */
 222   Size32,
 223   /* needs size prefix if in 64-bit mode */
 224   Size64,
 225   /* instruction ignores operand size prefix and in Intel mode ignores
 226      mnemonic size suffix check.  */
 227   IgnoreSize,
 228   /* default insn size depends on mode */
 229   DefaultSize,
 230   /* b suffix on instruction illegal */
 231   No_bSuf,
 232   /* w suffix on instruction illegal */
 233   No_wSuf,
 234   /* l suffix on instruction illegal */
 235   No_lSuf,
 236   /* s suffix on instruction illegal */
 237   No_sSuf,
 238   /* q suffix on instruction illegal */
 239   No_qSuf,
 240   /* long double suffix on instruction illegal */
 241   No_ldSuf,
 242   /* instruction needs FWAIT */
 243   FWait,
 244   /* quick test for string instructions */
 245   IsString,
 246   /* quick test for lockable instructions */
 247   IsLockable,
 248   /* fake an extra reg operand for clr, imul and special register
 249      processing for some instructions.  */
 250   RegKludge,
 251   /* The first operand must be xmm0 */
 252   FirstXmm0,
 253   /* An implicit xmm0 as the first operand */
 254   Implicit1stXmm0,
 255   /* Convert to DWORD */
 256   ToDword,
 257   /* Convert to QWORD */
 258   ToQword,
 259   /* Address prefix changes operand 0 */
 260   AddrPrefixOp0,
 261   /* opcode is a prefix */
 262   IsPrefix,
 263   /* instruction has extension in 8 bit imm */
 264   ImmExt,
 265   /* instruction don't need Rex64 prefix.  */
 266   NoRex64,
 267   /* instruction require Rex64 prefix.  */
 268   Rex64,
 269   /* deprecated fp insn, gets a warning */
 270   Ugh,
 271   /* insn has VEX prefix:
 272         1: 128bit VEX prefix.
 273         2: 256bit VEX prefix.
 274    */
 275 #define VEX128  1
 276 #define VEX256  2
 277   Vex,
 278   /* insn has VEX NDS. Register-only source is encoded in Vex prefix.
 279      We use VexNDS on insns with VEX DDS since the register-only source
 280      is the second source register.  */
 281   VexNDS,
 282   /* insn has VEX NDD. Register destination is encoded in Vex prefix. */
 283   VexNDD,
 284   /* insn has VEX NDD. Register destination is encoded in Vex prefix
 285      and one of the operands can access a memory location.  */
 286   VexLWP,
 287   /* How the VEX.W bit is used:
 288      0: Set by the REX.W bit.
 289      1: VEX.W0.  Should always be 0.
 290      2: VEX.W1.  Should always be 1.
 291    */
 292 #define VEXW0   1
 293 #define VEXW1   2
 294   VexW,
 295   /* VEX opcode prefix:
 296      0: VEX 0x0F opcode prefix.
 297      1: VEX 0x0F38 opcode prefix.
 298      2: VEX 0x0F3A opcode prefix
 299      3: XOP 0x08 opcode prefix.
 300      4: XOP 0x09 opcode prefix
 301      5: XOP 0x0A opcode prefix.
 302    */
 303 #define VEX0F           0
 304 #define VEX0F38         1
 305 #define VEX0F3A         2
 306 #define XOP08           3
 307 #define XOP09           4
 308 #define XOP0A           5
 309   VexOpcode,
 310   /* number of VEX source operands:
 311      0: <= 2 source operands.
 312      1: 2 XOP source operands.
 313      2: 3 source operands.
 314    */
 315 #define XOP2SOURCES     1
 316 #define VEX3SOURCES     2
 317   VexSources,
 318   /* instruction has VEX 8 bit imm */
 319   VexImmExt,
 320   /* SSE to AVX support required */
 321   SSE2AVX,
 322   /* No AVX equivalent */
 323   NoAVX,
 324   /* Compatible with old (<= 2.8.1) versions of gcc  */
 325   OldGcc,
 326   /* AT&T mnemonic.  */
 327   ATTMnemonic,
 328   /* AT&T syntax.  */
 329   ATTSyntax,
 330   /* Intel syntax.  */
 331   IntelSyntax,
 332   /* The last bitfield in i386_opcode_modifier.  */
 333   Opcode_Modifier_Max
 334 };
 335
 336 typedef struct i386_opcode_modifier
 337 {
 338   unsigned int d:1;
 339   unsigned int w:1;
 340   unsigned int s:1;
 341   unsigned int modrm:1;
 342   unsigned int shortform:1;
 343   unsigned int jump:1;
 344   unsigned int jumpdword:1;
 345   unsigned int jumpbyte:1;
 346   unsigned int jumpintersegment:1;
 347   unsigned int floatmf:1;
 348   unsigned int floatr:1;
 349   unsigned int floatd:1;
 350   unsigned int size16:1;
 351   unsigned int size32:1;
 352   unsigned int size64:1;
 353   unsigned int ignoresize:1;
 354   unsigned int defaultsize:1;
 355   unsigned int no_bsuf:1;
 356   unsigned int no_wsuf:1;
 357   unsigned int no_lsuf:1;
 358   unsigned int no_ssuf:1;
 359   unsigned int no_qsuf:1;
 360   unsigned int no_ldsuf:1;
 361   unsigned int fwait:1;
 362   unsigned int isstring:1;
 363   unsigned int islockable:1;
 364   unsigned int regkludge:1;
 365   unsigned int firstxmm0:1;
 366   unsigned int implicit1stxmm0:1;
 367   unsigned int todword:1;
 368   unsigned int toqword:1;
 369   unsigned int addrprefixop0:1;
 370   unsigned int isprefix:1;
 371   unsigned int immext:1;
 372   unsigned int norex64:1;
 373   unsigned int rex64:1;
 374   unsigned int ugh:1;
 375   unsigned int vex:2;
 376   unsigned int vexnds:1;
 377   unsigned int vexndd:1;
 378   unsigned int vexlwp:1;
 379   unsigned int vexw:2;
 380   unsigned int vexopcode:3;
 381   unsigned int vexsources:2;
 382   unsigned int veximmext:1;
 383   unsigned int sse2avx:1;
 384   unsigned int noavx:1;
 385   unsigned int oldgcc:1;
 386   unsigned int attmnemonic:1;
 387   unsigned int attsyntax:1;
 388   unsigned int intelsyntax:1;
 389 } i386_opcode_modifier;
 390
 391 /* Position of operand_type bits.  */
 392
 393 enum
 394 {
 395   /* 8bit register */
 396   Reg8 = 0,
 397   /* 16bit register */
 398   Reg16,
 399   /* 32bit register */
 400   Reg32,
 401   /* 64bit register */
 402   Reg64,
 403   /* Floating pointer stack register */
 404   FloatReg,
 405   /* MMX register */
 406   RegMMX,
 407   /* SSE register */
 408   RegXMM,
 409   /* AVX registers */
 410   RegYMM,
 411   /* Control register */
 412   Control,
 413   /* Debug register */
 414   Debug,
 415   /* Test register */
 416   Test,
 417   /* 2 bit segment register */
 418   SReg2,
 419   /* 3 bit segment register */
 420   SReg3,
 421   /* 1 bit immediate */
 422   Imm1,
 423   /* 8 bit immediate */
 424   Imm8,
 425   /* 8 bit immediate sign extended */
 426   Imm8S,
 427   /* 16 bit immediate */
 428   Imm16,
 429   /* 32 bit immediate */
 430   Imm32,
 431   /* 32 bit immediate sign extended */
 432   Imm32S,
 433   /* 64 bit immediate */
 434   Imm64,
 435   /* 8bit/16bit/32bit displacements are used in different ways,
 436      depending on the instruction.  For jumps, they specify the
 437      size of the PC relative displacement, for instructions with
 438      memory operand, they specify the size of the offset relative
 439      to the base register, and for instructions with memory offset
 440      such as `mov 1234,%al' they specify the size of the offset
 441      relative to the segment base.  */
 442   /* 8 bit displacement */
 443   Disp8,
 444   /* 16 bit displacement */
 445   Disp16,
 446   /* 32 bit displacement */
 447   Disp32,
 448   /* 32 bit signed displacement */
 449   Disp32S,
 450   /* 64 bit displacement */
 451   Disp64,
 452   /* Accumulator %al/%ax/%eax/%rax */
 453   Acc,
 454   /* Floating pointer top stack register %st(0) */
 455   FloatAcc,
 456   /* Register which can be used for base or index in memory operand.  */
 457   BaseIndex,
 458   /* Register to hold in/out port addr = dx */
 459   InOutPortReg,
 460   /* Register to hold shift count = cl */
 461   ShiftCount,
 462   /* Absolute address for jump.  */
 463   JumpAbsolute,
 464   /* String insn operand with fixed es segment */
 465   EsSeg,
 466   /* RegMem is for instructions with a modrm byte where the register
 467      destination operand should be encoded in the mod and regmem fields.
 468      Normally, it will be encoded in the reg field. We add a RegMem
 469      flag to the destination register operand to indicate that it should
 470      be encoded in the regmem field.  */
 471   RegMem,
 472   /* Memory.  */
 473   Mem,
 474   /* BYTE memory. */
 475   Byte,
 476   /* WORD memory. 2 byte */
 477   Word,
 478   /* DWORD memory. 4 byte */
 479   Dword,
 480   /* FWORD memory. 6 byte */
 481   Fword,
 482   /* QWORD memory. 8 byte */
 483   Qword,
 484   /* TBYTE memory. 10 byte */
 485   Tbyte,
 486   /* XMMWORD memory. */
 487   Xmmword,
 488   /* YMMWORD memory. */
 489   Ymmword,
 490   /* Unspecified memory size.  */
 491   Unspecified,
 492   /* Any memory size.  */
 493   Anysize,
 494
 495   /* The last bitfield in i386_operand_type.  */
 496   OTMax
 497 };
 498
 499 #define OTNumOfUints \
 500   (OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
 501 #define OTNumOfBits \
 502   (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 503
 504 /* If you get a compiler error for zero width of the unused field,
 505    comment it out.  */
 506 #define OTUnused                (OTMax + 1)
 507
 508 typedef union i386_operand_type
 509 {
 510   struct
 511     {
 512       unsigned int reg8:1;
 513       unsigned int reg16:1;
 514       unsigned int reg32:1;
 515       unsigned int reg64:1;
 516       unsigned int floatreg:1;
 517       unsigned int regmmx:1;
 518       unsigned int regxmm:1;
 519       unsigned int regymm:1;
 520       unsigned int control:1;
 521       unsigned int debug:1;
 522       unsigned int test:1;
 523       unsigned int sreg2:1;
 524       unsigned int sreg3:1;
 525       unsigned int imm1:1;
 526       unsigned int imm8:1;
 527       unsigned int imm8s:1;
 528       unsigned int imm16:1;
 529       unsigned int imm32:1;
 530       unsigned int imm32s:1;
 531       unsigned int imm64:1;
 532       unsigned int disp8:1;
 533       unsigned int disp16:1;
 534       unsigned int disp32:1;
 535       unsigned int disp32s:1;
 536       unsigned int disp64:1;
 537       unsigned int acc:1;
 538       unsigned int floatacc:1;
 539       unsigned int baseindex:1;
 540       unsigned int inoutportreg:1;
 541       unsigned int shiftcount:1;
 542       unsigned int jumpabsolute:1;
 543       unsigned int esseg:1;
 544       unsigned int regmem:1;
 545       unsigned int mem:1;
 546       unsigned int byte:1;
 547       unsigned int word:1;
 548       unsigned int dword:1;
 549       unsigned int fword:1;
 550       unsigned int qword:1;
 551       unsigned int tbyte:1;
 552       unsigned int xmmword:1;
 553       unsigned int ymmword:1;
 554       unsigned int unspecified:1;
 555       unsigned int anysize:1;
 556 #ifdef OTUnused
 557       unsigned int unused:(OTNumOfBits - OTUnused);
 558 #endif
 559     } bitfield;
 560   unsigned int array[OTNumOfUints];
 561 } i386_operand_type;
 562
 563 typedef struct insn_template
 564 {
 565   /* instruction name sans width suffix ("mov" for movl insns) */
 566   char *name;
 567
 568   /* how many operands */
 569   unsigned int operands;
 570
 571   /* base_opcode is the fundamental opcode byte without optional
 572      prefix(es).  */
 573   unsigned int base_opcode;
 574 #define Opcode_D        0x2 /* Direction bit:
 575                                set if Reg --> Regmem;
 576                                unset if Regmem --> Reg. */
 577 #define Opcode_FloatR   0x8 /* Bit to swap src/dest for float insns. */
 578 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
 579
 580   /* extension_opcode is the 3 bit extension for group <n> insns.
 581      This field is also used to store the 8-bit opcode suffix for the
 582      AMD 3DNow! instructions.
 583      If this template has no extension opcode (the usual case) use None
 584      Instructions */
 585   unsigned int extension_opcode;
 586 #define None 0xffff             /* If no extension_opcode is possible.  */
 587
 588   /* Opcode length.  */
 589   unsigned char opcode_length;
 590
 591   /* cpu feature flags */
 592   i386_cpu_flags cpu_flags;
 593
 594   /* the bits in opcode_modifier are used to generate the final opcode from
 595      the base_opcode.  These bits also are used to detect alternate forms of
 596      the same instruction */
 597   i386_opcode_modifier opcode_modifier;
 598
 599   /* operand_types[i] describes the type of operand i.  This is made
 600      by OR'ing together all of the possible type masks.  (e.g.
 601      'operand_types[i] = Reg|Imm' specifies that operand i can be
 602      either a register or an immediate operand.  */
 603   i386_operand_type operand_types[MAX_OPERANDS];
 604 }
 605 insn_template;
 606
 607 extern const insn_template i386_optab[];
 608
 609 /* these are for register name --> number & type hash lookup */
 610 typedef struct
 611 {
 612   char *reg_name;
 613   i386_operand_type reg_type;
 614   unsigned char reg_flags;
 615 #define RegRex      0x1  /* Extended register.  */
 616 #define RegRex64    0x2  /* Extended 8 bit register.  */
 617   unsigned char reg_num;
 618 #define RegRip  ((unsigned char ) ~0)
 619 #define RegEip  (RegRip - 1)
 620 /* EIZ and RIZ are fake index registers.  */
 621 #define RegEiz  (RegEip - 1)
 622 #define RegRiz  (RegEiz - 1)
 623 /* FLAT is a fake segment register (Intel mode).  */
 624 #define RegFlat     ((unsigned char) ~0)
 625   signed char dw2_regnum[2];
 626 #define Dw2Inval (-1)
 627 }
 628 reg_entry;
 629
 630 /* Entries in i386_regtab.  */
 631 #define REGNAM_AL 1
 632 #define REGNAM_AX 25
 633 #define REGNAM_EAX 41
 634
 635 extern const reg_entry i386_regtab[];
 636 extern const unsigned int i386_regtab_size;
 637
 638 typedef struct
 639 {
 640   char *seg_name;
 641   unsigned int seg_prefix;
 642 }
 643 seg_entry;
 644
 645 extern const seg_entry cs;
 646 extern const seg_entry ds;
 647 extern const seg_entry ss;
 648 extern const seg_entry es;
 649 extern const seg_entry fs;
 650 extern const seg_entry gs;