1 2010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
4 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
7 2010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
10 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
12 2010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
14 * mips.h: Update commentary after last commit.
16 2010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
18 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
19 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
20 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
22 2010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
24 * mips.h: Fix previous commit.
26 2010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
28 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
29 (INSN_LOONGSON_3A): Clear bit 31.
31 2010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
34 * arm.h (ARM_AEXT_V6M_ONLY): New define.
35 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
36 (ARM_ARCH_V6M_ONLY): New define.
38 2010-11-11 Mingming Sun <mingm.sun@gmail.com>
40 * mips.h (INSN_LOONGSON_3A): Defined.
41 (CPU_LOONGSON_3A): Defined.
42 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
44 2010-10-09 Matt Rice <ratmice@gmail.com>
46 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
47 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
49 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
51 * arm.h (ARM_EXT_VIRT): New define.
52 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
53 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
56 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
58 * arm.h (ARM_AEXT_ADIV): New define.
59 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
61 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
63 * arm.h (ARM_EXT_OS): New define.
64 (ARM_AEXT_V6SM): Likewise.
65 (ARM_ARCH_V6SM): Likewise.
67 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
69 * arm.h (ARM_EXT_MP): Add.
70 (ARM_ARCH_V7A_MP): Likewise.
72 2010-09-22 Mike Frysinger <vapier@gentoo.org>
74 * bfin.h: Declare pseudoChr structs/defines.
76 2010-09-21 Mike Frysinger <vapier@gentoo.org>
78 * bfin.h: Strip trailing whitespace.
80 2010-07-29 DJ Delorie <dj@redhat.com>
82 * rx.h (RX_Operand_Type): Add TwoReg.
83 (RX_Opcode_ID): Remove ediv and ediv2.
85 2010-07-27 DJ Delorie <dj@redhat.com>
87 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
89 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
90 Ina Pandit <ina.pandit@kpitcummins.com>
92 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
93 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
95 Remove PROCESSOR_V850EA support.
96 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
97 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
98 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
99 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
100 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
101 V850_OPERAND_PERCENT.
102 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
104 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
107 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
109 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
110 (MIPS16_INSN_BRANCH): Rename to...
111 (MIPS16_INSN_COND_BRANCH): ... this.
113 2010-07-03 Alan Modra <amodra@gmail.com>
115 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
116 Renumber other PPC_OPCODE defines.
118 2010-07-03 Alan Modra <amodra@gmail.com>
120 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
122 2010-06-29 Alan Modra <amodra@gmail.com>
124 * maxq.h: Delete file.
126 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
128 * ppc.h (PPC_OPCODE_E500): Define.
130 2010-05-26 Catherine Moore <clm@codesourcery.com>
132 * opcode/mips.h (INSN_MIPS16): Remove.
134 2010-04-21 Joseph Myers <joseph@codesourcery.com>
136 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
138 2010-04-15 Nick Clifton <nickc@redhat.com>
140 * alpha.h: Update copyright notice to use GPLv3.
146 * convex.h: Likewise.
160 * m68hc11.h: Likewise.
166 * mn10200.h: Likewise.
167 * mn10300.h: Likewise.
168 * msp430.h: Likewise.
179 * score-datadep.h: Likewise.
180 * score-inst.h: Likewise.
182 * spu-insns.h: Likewise.
186 * tic54x.h: Likewise.
191 2010-03-25 Joseph Myers <joseph@codesourcery.com>
193 * tic6x-control-registers.h, tic6x-insn-formats.h,
194 tic6x-opcode-table.h, tic6x.h: New.
196 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
198 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
200 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
202 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
204 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
206 * ia64.h (ia64_find_opcode): Remove argument name.
207 (ia64_find_next_opcode): Likewise.
208 (ia64_dis_opcode): Likewise.
209 (ia64_free_opcode): Likewise.
210 (ia64_find_dependency): Likewise.
212 2009-11-22 Doug Evans <dje@sebabeach.org>
214 * cgen.h: Include bfd_stdint.h.
215 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
217 2009-11-18 Paul Brook <paul@codesourcery.com>
219 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
221 2009-11-17 Paul Brook <paul@codesourcery.com>
222 Daniel Jacobowitz <dan@codesourcery.com>
224 * arm.h (ARM_EXT_V6_DSP): Define.
225 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
226 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
228 2009-11-04 DJ Delorie <dj@redhat.com>
230 * rx.h (rx_decode_opcode) (mvtipl): Add.
231 (mvtcp, mvfcp, opecp): Remove.
233 2009-11-02 Paul Brook <paul@codesourcery.com>
235 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
236 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
237 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
238 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
239 FPU_ARCH_NEON_VFP_V4): Define.
241 2009-10-23 Doug Evans <dje@sebabeach.org>
243 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
244 * cgen.h: Update. Improve multi-inclusion macro name.
246 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
248 * ppc.h (PPC_OPCODE_476): Define.
250 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
252 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
254 2009-09-29 DJ Delorie <dj@redhat.com>
258 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
260 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
262 2009-09-21 Ben Elliston <bje@au.ibm.com>
264 * ppc.h (PPC_OPCODE_PPCA2): New.
266 2009-09-05 Martin Thuresson <martin@mtme.org>
268 * ia64.h (struct ia64_operand): Renamed member class to op_class.
270 2009-08-29 Martin Thuresson <martin@mtme.org>
272 * tic30.h (template): Rename type template to
273 insn_template. Updated code to use new name.
274 * tic54x.h (template): Rename type template to
277 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
279 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
281 2009-06-11 Anthony Green <green@moxielogic.com>
283 * moxie.h (MOXIE_F3_PCREL): Define.
284 (moxie_form3_opc_info): Grow.
286 2009-06-06 Anthony Green <green@moxielogic.com>
288 * moxie.h (MOXIE_F1_M): Define.
290 2009-04-15 Anthony Green <green@moxielogic.com>
294 2009-04-06 DJ Delorie <dj@redhat.com>
296 * h8300.h: Add relaxation attributes to MOVA opcodes.
298 2009-03-10 Alan Modra <amodra@bigpond.net.au>
300 * ppc.h (ppc_parse_cpu): Declare.
302 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
304 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
305 and _IMM11 for mbitclr and mbitset.
306 * score-datadep.h: Update dependency information.
308 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
310 * ppc.h (PPC_OPCODE_POWER7): New.
312 2009-02-06 Doug Evans <dje@google.com>
314 * i386.h: Add comment regarding sse* insns and prefixes.
316 2009-02-03 Sandip Matte <sandip@rmicorp.com>
318 * mips.h (INSN_XLR): Define.
319 (INSN_CHIP_MASK): Update.
321 (OPCODE_IS_MEMBER): Update.
322 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
324 2009-01-28 Doug Evans <dje@google.com>
326 * opcode/i386.h: Add multiple inclusion protection.
327 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
328 (EDI_REG_NUM): New macros.
329 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
330 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
331 (REX_PREFIX_P): New macro.
333 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
335 * ppc.h (struct powerpc_opcode): New field "deprecated".
336 (PPC_OPCODE_NOPOWER4): Delete.
338 2008-11-28 Joshua Kinard <kumba@gentoo.org>
340 * mips.h: Define CPU_R14000, CPU_R16000.
341 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
343 2008-11-18 Catherine Moore <clm@codesourcery.com>
345 * arm.h (FPU_NEON_FP16): New.
346 (FPU_ARCH_NEON_FP16): New.
348 2008-11-06 Chao-ying Fu <fu@mips.com>
350 * mips.h: Doucument '1' for 5-bit sync type.
352 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
354 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
357 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
359 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
361 2008-07-30 Michael J. Eager <eager@eagercon.com>
363 * ppc.h (PPC_OPCODE_405): Define.
364 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
366 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
368 * ppc.h (ppc_cpu_t): New typedef.
369 (struct powerpc_opcode <flags>): Use it.
370 (struct powerpc_operand <insert, extract>): Likewise.
371 (struct powerpc_macro <flags>): Likewise.
373 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
375 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
376 Update comment before MIPS16 field descriptors to mention MIPS16.
377 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
379 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
380 New bit masks and shift counts for cins and exts.
382 * mips.h: Document new field descriptors +Q.
383 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
385 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
387 * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
388 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
390 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
392 * ppc.h: (PPC_OPCODE_E500MC): New.
394 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
396 * i386.h (MAX_OPERANDS): Set to 5.
397 (MAX_MNEM_SIZE): Changed to 20.
399 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
401 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
403 2008-03-09 Paul Brook <paul@codesourcery.com>
405 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
407 2008-03-04 Paul Brook <paul@codesourcery.com>
409 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
410 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
411 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
413 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
414 Nick Clifton <nickc@redhat.com>
417 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
418 with a 32-bit displacement but without the top bit of the 4th byte
421 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
423 * cr16.h (cr16_num_optab): Declared.
425 2008-02-14 Hakan Ardo <hakan@debian.org>
428 * avr.h (AVR_ISA_2xxe): Define.
430 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
432 * mips.h: Update copyright.
433 (INSN_CHIP_MASK): New macro.
434 (INSN_OCTEON): New macro.
435 (CPU_OCTEON): New macro.
436 (OPCODE_IS_MEMBER): Handle Octeon instructions.
438 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
440 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
442 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
444 * avr.h (AVR_ISA_USB162): Add new opcode set.
445 (AVR_ISA_AVR3): Likewise.
447 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
449 * mips.h (INSN_LOONGSON_2E): New.
450 (INSN_LOONGSON_2F): New.
451 (CPU_LOONGSON_2E): New.
452 (CPU_LOONGSON_2F): New.
453 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
455 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
457 * mips.h (INSN_ISA*): Redefine certain values as an
458 enumeration. Update comments.
459 (mips_isa_table): New.
460 (ISA_MIPS*): Redefine to match enumeration.
461 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
464 2007-08-08 Ben Elliston <bje@au.ibm.com>
466 * ppc.h (PPC_OPCODE_PPCPS): New.
468 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
470 * m68k.h: Document j K & E.
472 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
474 * cr16.h: New file for CR16 target.
476 2007-05-02 Alan Modra <amodra@bigpond.net.au>
478 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
480 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
482 * m68k.h (mcfisa_c): New.
483 (mcfusp, mcf_mask): Adjust.
485 2007-04-20 Alan Modra <amodra@bigpond.net.au>
487 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
488 (num_powerpc_operands): Declare.
489 (PPC_OPERAND_SIGNED et al): Redefine as hex.
490 (PPC_OPERAND_PLUS1): Define.
492 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
494 * i386.h (REX_MODE64): Renamed to ...
496 (REX_EXTX): Renamed to ...
498 (REX_EXTY): Renamed to ...
500 (REX_EXTZ): Renamed to ...
503 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
505 * i386.h: Add entries from config/tc-i386.h and move tables
506 to opcodes/i386-opc.h.
508 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
510 * i386.h (FloatDR): Removed.
511 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
513 2007-03-01 Alan Modra <amodra@bigpond.net.au>
515 * spu-insns.h: Add soma double-float insns.
517 2007-02-20 Thiemo Seufer <ths@mips.com>
518 Chao-Ying Fu <fu@mips.com>
520 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
521 (INSN_DSPR2): Add flag for DSP R2 instructions.
522 (M_BALIGN): New macro.
524 2007-02-14 Alan Modra <amodra@bigpond.net.au>
526 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
527 and Seg3ShortFrom with Shortform.
529 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
532 * i386.h (i386_optab): Put the real "test" before the pseudo
535 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
537 * m68k.h (m68010up): OR fido_a.
539 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
541 * m68k.h (fido_a): New.
543 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
545 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
546 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
549 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
551 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
553 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
555 * score-inst.h (enum score_insn_type): Add Insn_internal.
557 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
558 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
559 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
560 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
561 Alan Modra <amodra@bigpond.net.au>
563 * spu-insns.h: New file.
566 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
568 * ppc.h (PPC_OPCODE_CELL): Define.
570 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
572 * i386.h : Modify opcode to support for the change in POPCNT opcode
573 in amdfam10 architecture.
575 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
577 * i386.h: Replace CpuMNI with CpuSSSE3.
579 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
580 Joseph Myers <joseph@codesourcery.com>
581 Ian Lance Taylor <ian@wasabisystems.com>
582 Ben Elliston <bje@wasabisystems.com>
584 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
586 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
588 * score-datadep.h: New file.
589 * score-inst.h: New file.
591 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
593 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
594 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
597 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
598 Michael Meissner <michael.meissner@amd.com>
600 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
602 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
604 * i386.h (i386_optab): Add "nop" with memory reference.
606 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
608 * i386.h (i386_optab): Update comment for 64bit NOP.
610 2006-06-06 Ben Elliston <bje@au.ibm.com>
611 Anton Blanchard <anton@samba.org>
613 * ppc.h (PPC_OPCODE_POWER6): Define.
616 2006-06-05 Thiemo Seufer <ths@mips.com>
618 * mips.h: Improve description of MT flags.
620 2006-05-25 Richard Sandiford <richard@codesourcery.com>
622 * m68k.h (mcf_mask): Define.
624 2006-05-05 Thiemo Seufer <ths@mips.com>
625 David Ung <davidu@mips.com>
627 * mips.h (enum): Add macro M_CACHE_AB.
629 2006-05-04 Thiemo Seufer <ths@mips.com>
630 Nigel Stephens <nigel@mips.com>
631 David Ung <davidu@mips.com>
633 * mips.h: Add INSN_SMARTMIPS define.
635 2006-04-30 Thiemo Seufer <ths@mips.com>
636 David Ung <davidu@mips.com>
638 * mips.h: Defines udi bits and masks. Add description of
639 characters which may appear in the args field of udi
642 2006-04-26 Thiemo Seufer <ths@networkno.de>
644 * mips.h: Improve comments describing the bitfield instruction
647 2006-04-26 Julian Brown <julian@codesourcery.com>
649 * arm.h (FPU_VFP_EXT_V3): Define constant.
650 (FPU_NEON_EXT_V1): Likewise.
651 (FPU_VFP_HARD): Update.
652 (FPU_VFP_V3): Define macro.
653 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
655 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
657 * avr.h (AVR_ISA_PWMx): New.
659 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
661 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
662 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
663 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
664 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
665 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
667 2006-03-10 Paul Brook <paul@codesourcery.com>
669 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
671 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
673 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
674 first. Correct mask of bb "B" opcode.
676 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
678 * i386.h (i386_optab): Support Intel Merom New Instructions.
680 2006-02-24 Paul Brook <paul@codesourcery.com>
682 * arm.h: Add V7 feature bits.
684 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
686 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
688 2006-01-31 Paul Brook <paul@codesourcery.com>
689 Richard Earnshaw <rearnsha@arm.com>
691 * arm.h: Use ARM_CPU_FEATURE.
692 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
693 (arm_feature_set): Change to a structure.
694 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
695 ARM_FEATURE): New macros.
697 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
699 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
700 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
701 (ADD_PC_INCR_OPCODE): Don't define.
703 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
706 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
708 2005-11-14 David Ung <davidu@mips.com>
710 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
711 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
712 save/restore encoding of the args field.
714 2005-10-28 Dave Brolley <brolley@redhat.com>
716 Contribute the following changes:
717 2005-02-16 Dave Brolley <brolley@redhat.com>
719 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
720 cgen_isa_mask_* to cgen_bitset_*.
723 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
725 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
726 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
727 (CGEN_CPU_TABLE): Make isas a ponter.
729 2003-09-29 Dave Brolley <brolley@redhat.com>
731 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
732 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
733 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
735 2002-12-13 Dave Brolley <brolley@redhat.com>
737 * cgen.h (symcat.h): #include it.
738 (cgen-bitset.h): #include it.
739 (CGEN_ATTR_VALUE_TYPE): Now a union.
740 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
741 (CGEN_ATTR_ENTRY): 'value' now unsigned.
742 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
743 * cgen-bitset.h: New file.
745 2005-09-30 Catherine Moore <clm@cm00re.com>
749 2005-10-24 Jan Beulich <jbeulich@novell.com>
751 * ia64.h (enum ia64_opnd): Move memory operand out of set of
754 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
756 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
757 Add FLAG_STRICT to pa10 ftest opcode.
759 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
761 * hppa.h (pa_opcodes): Remove lha entries.
763 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
765 * hppa.h (FLAG_STRICT): Revise comment.
766 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
767 before corresponding pa11 opcodes. Add strict pa10 register-immediate
770 2005-09-30 Catherine Moore <clm@cm00re.com>
774 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
776 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
778 2005-09-06 Chao-ying Fu <fu@mips.com>
780 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
781 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
783 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
784 (INSN_ASE_MASK): Update to include INSN_MT.
785 (INSN_MT): New define for MT ASE.
787 2005-08-25 Chao-ying Fu <fu@mips.com>
789 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
790 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
791 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
792 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
793 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
794 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
796 (INSN_DSP): New define for DSP ASE.
798 2005-08-18 Alan Modra <amodra@bigpond.net.au>
802 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
804 * ppc.h (PPC_OPCODE_E300): Define.
806 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
808 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
810 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
813 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
816 2005-07-27 Jan Beulich <jbeulich@novell.com>
818 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
819 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
820 Add movq-s as 64-bit variants of movd-s.
822 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
824 * hppa.h: Fix punctuation in comment.
826 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
827 implicit space-register addressing. Set space-register bits on opcodes
828 using implicit space-register addressing. Add various missing pa20
829 long-immediate opcodes. Remove various opcodes using implicit 3-bit
830 space-register addressing. Use "fE" instead of "fe" in various
833 2005-07-18 Jan Beulich <jbeulich@novell.com>
835 * i386.h (i386_optab): Operands of aam and aad are unsigned.
837 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
839 * i386.h (i386_optab): Support Intel VMX Instructions.
841 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
843 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
845 2005-07-05 Jan Beulich <jbeulich@novell.com>
847 * i386.h (i386_optab): Add new insns.
849 2005-07-01 Nick Clifton <nickc@redhat.com>
851 * sparc.h: Add typedefs to structure declarations.
853 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
856 * i386.h (i386_optab): Update comments for 64bit addressing on
857 mov. Allow 64bit addressing for mov and movq.
859 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
861 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
862 respectively, in various floating-point load and store patterns.
864 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
866 * hppa.h (FLAG_STRICT): Correct comment.
867 (pa_opcodes): Update load and store entries to allow both PA 1.X and
868 PA 2.0 mneumonics when equivalent. Entries with cache control
869 completers now require PA 1.1. Adjust whitespace.
871 2005-05-19 Anton Blanchard <anton@samba.org>
873 * ppc.h (PPC_OPCODE_POWER5): Define.
875 2005-05-10 Nick Clifton <nickc@redhat.com>
877 * Update the address and phone number of the FSF organization in
878 the GPL notices in the following files:
879 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
880 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
881 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
882 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
883 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
884 tic54x.h, tic80.h, v850.h, vax.h
886 2005-05-09 Jan Beulich <jbeulich@novell.com>
888 * i386.h (i386_optab): Add ht and hnt.
890 2005-04-18 Mark Kettenis <kettenis@gnu.org>
892 * i386.h: Insert hyphens into selected VIA PadLock extensions.
893 Add xcrypt-ctr. Provide aliases without hyphens.
895 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
897 Moved from ../ChangeLog
899 2005-04-12 Paul Brook <paul@codesourcery.com>
900 * m88k.h: Rename psr macros to avoid conflicts.
902 2005-03-12 Zack Weinberg <zack@codesourcery.com>
903 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
904 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
907 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
908 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
909 Remove redundant instruction types.
910 (struct argument): X_op - new field.
911 (struct cst4_entry): Remove.
912 (no_op_insn): Declare.
914 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
915 * crx.h (enum argtype): Rename types, remove unused types.
917 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
918 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
919 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
920 (enum operand_type): Rearrange operands, edit comments.
921 replace us<N> with ui<N> for unsigned immediate.
922 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
923 displacements (respectively).
924 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
925 (instruction type): Add NO_TYPE_INS.
926 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
927 (operand_entry): New field - 'flags'.
928 (operand flags): New.
930 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
931 * crx.h (operand_type): Remove redundant types i3, i4,
933 Add new unsigned immediate types us3, us4, us5, us16.
935 2005-04-12 Mark Kettenis <kettenis@gnu.org>
937 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
938 adjust them accordingly.
940 2005-04-01 Jan Beulich <jbeulich@novell.com>
942 * i386.h (i386_optab): Add rdtscp.
944 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
946 * i386.h (i386_optab): Don't allow the `l' suffix for moving
947 between memory and segment register. Allow movq for moving between
948 general-purpose register and segment register.
950 2005-02-09 Jan Beulich <jbeulich@novell.com>
953 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
954 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
957 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
959 * m68k.h (m68008, m68ec030, m68882): Remove.
961 (cpu_m68k, cpu_cf): New.
962 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
963 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
965 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
967 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
968 * cgen.h (enum cgen_parse_operand_type): Add
969 CGEN_PARSE_OPERAND_SYMBOLIC.
971 2005-01-21 Fred Fish <fnf@specifixinc.com>
973 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
974 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
975 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
977 2005-01-19 Fred Fish <fnf@specifixinc.com>
979 * mips.h (struct mips_opcode): Add new pinfo2 member.
980 (INSN_ALIAS): New define for opcode table entries that are
981 specific instances of another entry, such as 'move' for an 'or'
983 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
984 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
986 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
988 * mips.h (CPU_RM9000): Define.
989 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
991 2004-11-25 Jan Beulich <jbeulich@novell.com>
993 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
994 to/from test registers are illegal in 64-bit mode. Add missing
995 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
996 (previously one had to explicitly encode a rex64 prefix). Re-enable
997 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
998 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1000 2004-11-23 Jan Beulich <jbeulich@novell.com>
1002 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1003 available only with SSE2. Change the MMX additions introduced by SSE
1004 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1005 instructions by their now designated identifier (since combining i686
1006 and 3DNow! does not really imply 3DNow!A).
1008 2004-11-19 Alan Modra <amodra@bigpond.net.au>
1010 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1011 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1013 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
1014 Vineet Sharma <vineets@noida.hcltech.com>
1016 * maxq.h: New file: Disassembly information for the maxq port.
1018 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
1020 * i386.h (i386_optab): Put back "movzb".
1022 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
1024 * cris.h (enum cris_insn_version_usage): Tweak formatting and
1025 comments. Remove member cris_ver_sim. Add members
1026 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1027 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1028 (struct cris_support_reg, struct cris_cond15): New types.
1029 (cris_conds15): Declare.
1030 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1031 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1032 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1033 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1034 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1035 SIZE_FIELD_UNSIGNED.
1037 2004-11-04 Jan Beulich <jbeulich@novell.com>
1039 * i386.h (sldx_Suf): Remove.
1040 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1041 (q_FP): Define, implying no REX64.
1042 (x_FP, sl_FP): Imply FloatMF.
1043 (i386_optab): Split reg and mem forms of moving from segment registers
1044 so that the memory forms can ignore the 16-/32-bit operand size
1045 distinction. Adjust a few others for Intel mode. Remove *FP uses from
1046 all non-floating-point instructions. Unite 32- and 64-bit forms of
1047 movsx, movzx, and movd. Adjust floating point operations for the above
1048 changes to the *FP macros. Add DefaultSize to floating point control
1049 insns operating on larger memory ranges. Remove left over comments
1050 hinting at certain insns being Intel-syntax ones where the ones
1051 actually meant are already gone.
1053 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
1055 * crx.h: Add COPS_REG_INS - Coprocessor Special register
1058 2004-09-30 Paul Brook <paul@codesourcery.com>
1060 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1061 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1063 2004-09-11 Theodore A. Roth <troth@openavr.org>
1065 * avr.h: Add support for
1066 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1068 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
1070 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1072 2004-08-24 Dmitry Diky <diwil@spec.ru>
1074 * msp430.h (msp430_opc): Add new instructions.
1075 (msp430_rcodes): Declare new instructions.
1076 (msp430_hcodes): Likewise..
1078 2004-08-13 Nick Clifton <nickc@redhat.com>
1081 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1084 2004-08-30 Michal Ludvig <mludvig@suse.cz>
1086 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1088 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
1090 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1092 2004-07-21 Jan Beulich <jbeulich@novell.com>
1094 * i386.h: Adjust instruction descriptions to better match the
1097 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
1099 * arm.h: Remove all old content. Replace with architecture defines
1100 from gas/config/tc-arm.c.
1102 2004-07-09 Andreas Schwab <schwab@suse.de>
1104 * m68k.h: Fix comment.
1106 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
1110 2004-06-24 Alan Modra <amodra@bigpond.net.au>
1112 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1114 2004-05-24 Peter Barada <peter@the-baradas.com>
1116 * m68k.h: Add 'size' to m68k_opcode.
1118 2004-05-05 Peter Barada <peter@the-baradas.com>
1120 * m68k.h: Switch from ColdFire chip name to core variant.
1122 2004-04-22 Peter Barada <peter@the-baradas.com>
1124 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
1125 descriptions for new EMAC cases.
1126 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1127 handle Motorola MAC syntax.
1128 Allow disassembly of ColdFire V4e object files.
1130 2004-03-16 Alan Modra <amodra@bigpond.net.au>
1132 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
1134 2004-03-12 Jakub Jelinek <jakub@redhat.com>
1136 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1138 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1140 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1142 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1144 * i386.h (i386_optab): Added xstore/xcrypt insns.
1146 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
1148 * h8300.h (32bit ldc/stc): Add relaxing support.
1150 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
1152 * h8300.h (BITOP): Pass MEMRELAX flag.
1154 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
1156 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1159 For older changes see ChangeLog-9103
1165 version-control: never