| blob | d361a29b699e45bcbc77e06248587d5820a85065 |
1 2006-06-22 Thiemo Seufer <ths@mips.com>
3 * config/tc-mips.c (ISA_SUPPORTS_MIPS16E): New macro.
4 (append_insn): Use it.
5 (md_apply_fix): Whitespace formatting.
6 (md_begin, append_insn, macro, macro2, mips16_immed, mips_align,
7 mips16_extended_frag): Remove register specifier.
8 (md_convert_frag): Likewise. Use TRUE ans FALSE instead of numeric
9 constants.
11 2006-06-21 Mark Shinwell <shinwell@codesourcery.com>
13 * config/tc-arm.c (s_arm_unwind_save_vfp_armv6): New. Parse
14 a directive saving VFP registers for ARMv6 or later.
15 (s_arm_unwind_save): Add parameter arch_v6 and call
16 s_arm_unwind_save_vfp or s_arm_unwind_save_vfp_armv6 as
17 appropriate.
18 (md_pseudo_table): Add entry for new "vsave" directive.
19 * doc/c-arm.texi: Correct error in example for "save"
20 directive (fstmdf -> fstmdx). Also document "vsave" directive.
22 2006-06-18 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
23 Anatoly Sokolov <aesok@post.ru>
25 * config/tc-avr.c (mcu_types): Add support for atmega165p, atmega169p
26 and atmega644p devices. Rename atmega164/atmega324 devices to
27 atmega164p/atmega324p.
28 * doc/c-avr.texi: Document new mcu and arch options.
30 2006-06-17 Nick Clifton <nickc@redhat.com>
32 * config/tc-arm.c (enum parse_operand_result): Move outside of
33 #ifdef OBJ_ELF so that non-ELF targeted ARM ports can build.
35 2006-06-16 H.J. Lu <hongjiu.lu@intel.com>
37 * config/tc-i386.h (processor_type): New.
38 (arch_entry): Add type.
40 * config/tc-i386.c (cpu_arch_tune): New.
41 (cpu_arch_tune_flags): Likewise.
42 (cpu_arch_isa_flags): Likewise.
43 (cpu_arch): Updated.
44 (set_cpu_arch): Also update cpu_arch_isa_flags.
45 (md_assemble): Update cpu_arch_isa_flags.
46 (OPTION_MARCH): New.
47 (OPTION_MTUNE): Likewise.
48 (md_longopts): Add -march= and -mtune=.
49 (md_parse_option): Support -march= and -mtune=.
50 (md_show_usage): Add -march=CPU/-mtune=CPU.
51 (i386_target_format): Also update cpu_arch_isa_flags,
52 cpu_arch_tune and cpu_arch_tune_flags.
54 * doc/as.texinfo: Add -march=CPU/-mtune=CPU.
56 * doc/c-i386.texi: Document -march=CPU/-mtune=CPU.
58 2006-06-15 Mark Shinwell <shinwell@codesourcery.com>
60 * config/tc-arm.c (enum parse_operand_result): New.
61 (struct group_reloc_table_entry): New.
62 (enum group_reloc_type): New.
63 (group_reloc_table): New array.
64 (find_group_reloc_table_entry): New function.
65 (parse_shifter_operand_group_reloc): New function.
66 (parse_address_main): New function, incorporating code
67 from the old parse_address function. To be used via...
68 (parse_address): wrapper for parse_address_main; and
69 (parse_address_group_reloc): new function, likewise.
70 (enum operand_parse_code): New codes OP_SHG, OP_ADDRGLDR,
71 OP_ADDRGLDRS, OP_ADDRGLDC.
72 (parse_operands): Support for these new operand codes.
73 New macro po_misc_or_fail_no_backtrack.
74 (encode_arm_cp_address): Preserve group relocations.
75 (insns): Modify to use the above operand codes where group
76 relocations are permitted.
77 (md_apply_fix): Handle the group relocations
78 ALU_PC_G0_NC through LDC_SB_G2.
79 (tc_gen_reloc): Likewise.
80 (arm_force_relocation): Leave group relocations for the linker.
81 (arm_fix_adjustable): Likewise.
83 2006-06-15 Julian Brown <julian@codesourcery.com>
85 * config/tc-arm.c (do_vfp_nsyn_ldr_str): Remove, fold into...
86 (do_neon_ldr_str): Always defer to VFP encoding routines, which handle
87 relocs properly.
89 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
91 * config/tc-i386.c (process_suffix): Don't add rex64 for
92 "xchg %rax,%rax".
94 2006-06-09 Thiemo Seufer <ths@mips.com>
96 * config/tc-mips.c (mips_ip): Maintain argument count.
98 2006-06-09 Alan Modra <amodra@bigpond.net.au>
100 * config/tc-iq2000.c: Include sb.h.
102 2006-06-08 Nigel Stephens <nigel@mips.com>
104 * config/tc-mips.c (mips_pseudo_table): Add "origin" and "repeat"
105 aliases for better compatibility with SGI tools.
107 2006-06-08 Alan Modra <amodra@bigpond.net.au>
109 * configure.in (BFDLIB, BFDVER_H, ALL_OBJ_DEPS): Delete.
110 * Makefile.am (GASLIBS): Expand @BFDLIB@.
111 (BFDVER_H): Delete.
112 (OBJS): Expand @ALL_OBJ_DEPS@. Depend on all fopen-*.h variants.
113 (obj-aout.o): Depend on $(DEP_@target_get_type@_aout)
114 (obj-coff.o, obj-ecoff.o, obj-elf.o): Similarly.
115 Run "make dep-am".
116 * dep-in.sed: Don't substitute bfdver.h. Do remove symcat.h.
117 * Makefile.in: Regenerate.
118 * doc/Makefile.in: Regenerate.
119 * configure: Regenerate.
121 2006-06-07 Joseph S. Myers <joseph@codesourcery.com>
123 * po/Make-in (pdf, ps): New dummy targets.
125 2006-06-07 Julian Brown <julian@codesourcery.com>
127 * config/tc-arm.c (stdarg.h): include.
128 (arm_it): Add uncond_value field. Add isvec and issingle to operand
129 array.
130 (arm_reg_type): Add REG_TYPE_VFSD (single or double VFP reg) and
131 REG_TYPE_NSDQ (single, double or quad vector reg).
132 (reg_expected_msgs): Update.
133 (BAD_FPU): Add macro for unsupported FPU instruction error.
134 (parse_neon_type): Support 'd' as an alias for .f64.
135 (parse_typed_reg_or_scalar): Support REG_TYPE_VFSD, REG_TYPE_NSDQ
136 sets of registers.
137 (parse_vfp_reg_list): Don't update first arg on error.
138 (parse_neon_mov): Support extra syntax for VFP moves.
139 (operand_parse_code): Add OP_RVSD, OP_RNSDQ, OP_VRSDLST, OP_RVSD_IO,
140 OP_RNSDQ_RNSC, OP_RVC_PSR, OP_APSR_RR, OP_oRNSDQ.
141 (parse_operands): Support isvec, issingle operands fields, new parse
142 codes above.
143 (do_vfp_nsyn_mrs, do_vfp_nsyn_msr): New functions. Support VFP mrs,
144 msr variants.
145 (do_mrs, do_msr, do_t_mrs, do_t_msr): Add support for above.
146 (NEON_ENC_TAB): Add vnmul, vnmla, vnmls, vcmp, vcmpz, vcmpe, vcmpez.
147 (NEON_ENC_SINGLE, NEON_ENC_DOUBLE): Define macros.
148 (NEON_SHAPE_DEF): New macro. Define table of possible instruction
149 shapes.
150 (neon_shape): Redefine in terms of above.
151 (neon_shape_class): New enumeration, table of shape classes.
152 (neon_shape_el): New enumeration. One element of a shape.
153 (neon_shape_el_size): Register widths of above, where appropriate.
154 (neon_shape_info): New struct. Info for shape table.
155 (neon_shape_tab): New array.
156 (neon_type_mask): Add N_F64, N_VFP. Update N_MAX_NONSPECIAL.
157 (neon_check_shape): Rewrite as...
158 (neon_select_shape): New function to classify instruction shapes,
159 driven by new table neon_shape_tab array.
160 (neon_quad): New function. Return 1 if shape should set Q flag in
161 instructions (or equivalent), 0 otherwise.
162 (type_chk_of_el_type): Support F64.
163 (el_type_of_type_chk): Likewise.
164 (neon_check_type): Add support for VFP type checking (VFP data
165 elements fill their containing registers).
166 (do_vfp_cond_or_thumb): Fill in condition field in ARM mode, or 0xE
167 in thumb mode for VFP instructions.
168 (do_vfp_nsyn_opcode): New function. Look up the opcode in argument,
169 and encode the current instruction as if it were that opcode.
170 (try_vfp_nsyn): New. If this looks like a VFP instruction with ARGS
171 arguments, call function in PFN.
172 (do_vfp_nsyn_add_sub, do_vfp_nsyn_mla_mls, do_vfp_nsyn_mul)
173 (do_vfp_nsyn_abs_neg, do_vfp_nsyn_ldm_stm, do_vfp_nsyn_ldr_str)
174 (do_vfp_nsyn_sqrt, do_vfp_nsyn_div, do_vfp_nsyn_nmul)
175 (do_vfp_nsyn_cmp, nsyn_insert_sp, do_vfp_nsyn_push)
176 (do_vfp_nsyn_pop, do_vfp_nsyn_cvt, do_vfp_nsyn_cvtz): New functions.
177 Redirect Neon-syntax VFP instructions to VFP instruction handlers.
178 (do_neon_dyadic_i_su, do_neon_dyadic_i64_su, do_neon_shl_imm)
179 (do_neon_qshl_imm, do_neon_logic, do_neon_bitfield)
180 (neon_dyadic_misc, neon_compare, do_neon_tst, do_neon_qdmulh)
181 (do_neon_fcmp_absolute, do_neon_step, do_neon_sli, do_neon_sri)
182 (do_neon_qshlu_imm, neon_move_immediate, do_neon_mvn, do_neon_ext)
183 (do_neon_rev, do_neon_dup, do_neon_rshift_round_imm, do_neon_trn)
184 (do_neon_zip_uzp, do_neon_sat_abs_neg, do_neon_pair_long)
185 (do_neon_recip_est, do_neon_cls, do_neon_clz, do_neon_cnt)
186 (do_neon_swp): Use neon_select_shape not neon_check_shape. Use
187 neon_quad.
188 (vfp_or_neon_is_neon): New function. Call if a mnemonic shared
189 between VFP and Neon turns out to belong to Neon. Perform
190 architecture check and fill in condition field if appropriate.
191 (do_neon_addsub_if_i, do_neon_mac_maybe_scalar, do_neon_abs_neg)
192 (do_neon_cvt): Add support for VFP variants of instructions.
193 (neon_cvt_flavour): Extend to cover VFP conversions.
194 (do_neon_mov): Rewrite to use neon_select_shape. Add support for VFP
195 vmov variants.
196 (do_neon_ldr_str): Handle single-precision VFP load/store.
197 (do_neon_ld_st_interleave, do_neon_ld_st_lane, do_neon_ld_dup): Use
198 NS_NULL not NS_IGNORE.
199 (opcode_tag): Add OT_csuffixF for operands which either take a
200 conditional suffix, or have 0xF in the condition field.
201 (md_assemble): Add support for OT_csuffixF.
202 (NCE): Replace macro with...
203 (NCE_tag, NCE, NCEF): New macros.
204 (nCE): Replace macro with...
205 (nCE_tag, nCE, nCEF): New macros.
206 (insns): Add support for VFP insns or VFP versions of insns msr,
207 mrs, vsqrt, vdiv, vnmul, vnmla, vnmls, vcmp, vcmpe, vpush, vpop,
208 vcvtz, vmul, vmla, vmls, vadd, vsub, vabs, vneg, vldm, vldmia,
209 vldbdb, vstm, vstmia, vstmdb, vldr, vstr, vcvt, vmov. Group shared
210 VFP/Neon insns together.
212 2006-06-07 Alan Modra <amodra@bigpond.net.au>
213 Ladislav Michl <ladis@linux-mips.org>
215 * app.c: Don't include headers already included by as.h.
216 * as.c: Likewise.
217 * atof-generic.c: Likewise.
218 * cgen.c: Likewise.
219 * dwarf2dbg.c: Likewise.
220 * expr.c: Likewise.
221 * input-file.c: Likewise.
222 * input-scrub.c: Likewise.
223 * macro.c: Likewise.
224 * output-file.c: Likewise.
225 * read.c: Likewise.
226 * sb.c: Likewise.
227 * config/bfin-lex.l: Likewise.
228 * config/obj-coff.h: Likewise.
229 * config/obj-elf.h: Likewise.
230 * config/obj-som.h: Likewise.
231 * config/tc-arc.c: Likewise.
232 * config/tc-arm.c: Likewise.
233 * config/tc-avr.c: Likewise.
234 * config/tc-bfin.c: Likewise.
235 * config/tc-cris.c: Likewise.
236 * config/tc-d10v.c: Likewise.
237 * config/tc-d30v.c: Likewise.
238 * config/tc-dlx.h: Likewise.
239 * config/tc-fr30.c: Likewise.
240 * config/tc-frv.c: Likewise.
241 * config/tc-h8300.c: Likewise.
242 * config/tc-hppa.c: Likewise.
243 * config/tc-i370.c: Likewise.
244 * config/tc-i860.c: Likewise.
245 * config/tc-i960.c: Likewise.
246 * config/tc-ip2k.c: Likewise.
247 * config/tc-iq2000.c: Likewise.
248 * config/tc-m32c.c: Likewise.
249 * config/tc-m32r.c: Likewise.
250 * config/tc-maxq.c: Likewise.
251 * config/tc-mcore.c: Likewise.
252 * config/tc-mips.c: Likewise.
253 * config/tc-mmix.c: Likewise.
254 * config/tc-mn10200.c: Likewise.
255 * config/tc-mn10300.c: Likewise.
256 * config/tc-msp430.c: Likewise.
257 * config/tc-mt.c: Likewise.
258 * config/tc-ns32k.c: Likewise.
259 * config/tc-openrisc.c: Likewise.
260 * config/tc-ppc.c: Likewise.
261 * config/tc-s390.c: Likewise.
262 * config/tc-sh.c: Likewise.
263 * config/tc-sh64.c: Likewise.
264 * config/tc-sparc.c: Likewise.
265 * config/tc-tic30.c: Likewise.
266 * config/tc-tic4x.c: Likewise.
267 * config/tc-tic54x.c: Likewise.
268 * config/tc-v850.c: Likewise.
269 * config/tc-vax.c: Likewise.
270 * config/tc-xc16x.c: Likewise.
271 * config/tc-xstormy16.c: Likewise.
272 * config/tc-xtensa.c: Likewise.
273 * config/tc-z80.c: Likewise.
274 * config/tc-z8k.c: Likewise.
275 * macro.h: Don't include sb.h or ansidecl.h.
276 * sb.h: Don't include stdio.h or ansidecl.h.
277 * cond.c: Include sb.h.
278 * itbl-lex.l: Include as.h instead of other system headers.
279 * itbl-parse.y: Likewise.
280 * itbl-ops.c: Similarly.
281 * itbl-ops.h: Don't include as.h or ansidecl.h.
282 * config/bfin-defs.h: Don't include bfd.h or as.h.
283 * config/bfin-parse.y: Include as.h instead of other system headers.
285 2006-06-06 Ben Elliston <bje@au.ibm.com>
286 Anton Blanchard <anton@samba.org>
288 * config/tc-ppc.c (parse_cpu): Handle "-mpower6".
289 (md_show_usage): Document it.
290 (ppc_setup_opcodes): Test power6 opcode flag bits.
291 * doc/c-ppc.texi (PowerPC-Opts): Document "-mpower6".
293 2006-06-06 Thiemo Seufer <ths@mips.com>
294 Chao-ying Fu <fu@mips.com>
296 * config/tc-mips.c (ISA_SUPPORTS_DSP64): New macro.
297 (CPU_HAS_MIPS3D, CPU_HAS_MDMX, CPU_HAS_DSP, CPU_HAS_MT): Delete.
298 (macro_build): Update comment.
299 (mips_ip): Allow DSP64 instructions for MIPS64R2.
300 (mips_after_parse_args): Remove uses of CPU_HAS_MIPS3D and
301 CPU_HAS_MDMX.
302 (mips_cpu_info): Fix formatting. Add MIPS_CPU_ASE_MIPS3D and
303 MIPS_CPU_ASE_MDMX flags for sb1.
305 2006-06-05 Thiemo Seufer <ths@mips.com>
307 * config/tc-mips.c (macro_build): Use INSERT_OPERAND wherew
308 appropriate.
309 (mips16_macro_build): Use MIPS16_INSERT_OPERAND where appropriate.
310 (mips_ip): Make overflowed/underflowed constant arguments in DSP
311 and MT instructions a fatal error. Use INSERT_OPERAND where
312 appropriate. Improve warnings for break and wait code overflows.
313 Use symbolic constant of OP_MASK_COPZ.
314 (mips16_ip): Use MIPS16_INSERT_OPERAND where appropriate.
316 2006-06-05 Daniel Jacobowitz <dan@codesourcery.com>
318 * po/Make-in (top_builddir): Define.
320 2006-06-02 Joseph S. Myers <joseph@codesourcery.com>
322 * doc/Makefile.am (TEXI2DVI): Define.
323 * doc/Makefile.in: Regenerate.
324 * doc/c-arc.texi: Fix typo.
326 2006-06-01 Alan Modra <amodra@bigpond.net.au>
328 * config/obj-ieee.c: Delete.
329 * config/obj-ieee.h: Delete.
330 * Makefile.am (OBJ_FORMATS): Remove ieee.
331 (OBJ_FORMAT_CFILES, OBJ_FORMAT_HFILES): Similarly.
332 (obj-ieee.o): Remove rule.
333 * Makefile.in: Regenerate.
334 * configure.in (atof): Remove tahoe.
335 (OBJ_MAYBE_IEEE): Don't define.
336 * configure: Regenerate.
337 * config.in: Regenerate.
338 * doc/Makefile.in: Regenerate.
339 * po/POTFILES.in: Regenerate.
341 2006-05-31 Daniel Jacobowitz <dan@codesourcery.com>
343 * Makefile.am: Replace INTLLIBS and INTLDEPS with LIBINTL
344 and LIBINTL_DEP everywhere.
345 (INTLLIBS): Remove.
346 (INCLUDES, DEP_INCLUDES): Use @INCINTL@.
347 * acinclude.m4: Include new gettext macros.
348 * configure.in: Use ZW_GNU_GETTEXT_SISTER_DIR and AM_PO_SUBDIRS.
349 Remove local code for po/Makefile.
350 * Makefile.in, configure, doc/Makefile.in: Regenerated.
352 2006-05-30 Nick Clifton <nickc@redhat.com>
354 * po/es.po: Updated Spanish translation.
356 2006-05-06 Denis Chertykov <denisc@overta.ru>
358 * doc/c-avr.texi: New file.
359 * doc/Makefile.am (CPU_DOCS): Add c-avr.texi
360 * doc/all.texi: Set AVR
361 * doc/as.texinfo: Include c-avr.texi
363 2006-05-28 Jie Zhang <jie.zhang@analog.com>
365 * config/bfin-parse.y (check_macfunc): Loose the condition of
366 calling check_multiply_halfregs ().
368 2006-05-25 Jie Zhang <jie.zhang@analog.com>
370 * config/bfin-parse.y (asm_1): Better check and deal with
371 vector and scalar Multiply 16-Bit Operands instructions.
373 2006-05-24 Nick Clifton <nickc@redhat.com>
375 * config/tc-hppa.c: Convert to ISO C90 format.
376 * config/tc-hppa.h: Likewise.
378 2006-05-24 Carlos O'Donell <carlos@systemhalted.org>
379 Randolph Chung <randolph@tausq.org>
381 * config/tc-hppa.c (is_tls_gdidx, is_tls_ldidx, is_tls_dtpoff,
382 is_tls_ieoff, is_tls_leoff): Define.
383 (fix_new_hppa): Handle TLS.
384 (cons_fix_new_hppa): Likewise.
385 (pa_ip): Likewise.
386 (md_apply_fix): Handle TLS relocs.
387 * config/tc-hppa.h (hppa_fix_adjustable): Handle TLS.
389 2006-05-24 Bjoern Haase <bjoern.m.haase@web.de>
391 * config/tc-avr.c: Add new cpu targets avr6, avr2560 and avr2561.
393 2006-05-23 Thiemo Seufer <ths@mips.com>
394 David Ung <davidu@mips.com>
395 Nigel Stephens <nigel@mips.com>
397 [ gas/ChangeLog ]
398 * config/tc-mips.c (ISA_SUPPORTS_SMARTMIPS): Rename.
399 (ISA_SUPPORTS_DSP_ASE, ISA_SUPPORTS_MT_ASE, ISA_HAS_64BIT_FPRS,
400 ISA_HAS_MXHC1): New macros.
401 (HAVE_32BIT_FPRS): Use ISA_HAS_64BIT_FPRS instead of
402 ISA_HAS_64BIT_REGS. Formatting fixes. Improved comments.
403 (mips_cpu_info): Change to use combined ASE/IS_ISA flag.
404 (MIPS_CPU_IS_ISA, MIPS_CPU_ASE_SMARTMIPS, MIPS_CPU_ASE_DSP,
405 MIPS_CPU_ASE_MT, MIPS_CPU_ASE_MIPS3D, MIPS_CPU_ASE_MDMX): New defines.
406 (mips_after_parse_args): Change default handling of float register
407 size to account for 32bit code with 64bit FP. Better sanity checking
408 of ISA/ASE/ABI option combinations.
409 (s_mipsset): Support switching of GPR and FPR sizes via
410 .set {g,f}p={32,64,default}. Better sanity checking for .set ASE
411 options.
412 (mips_elf_final_processing): We should record the use of 64bit FP
413 registers in 32bit code but we don't, because ELF header flags are
414 a scarce ressource.
415 (mips_cpu_info_table): Add ASE flags for CPUs with mandatory ASE
416 extensions. Add 4ksc, 4kec, 4kem, 4kep, 4ksd, m4kp, 24kec, 24kef,
417 24kex, 34kc, 34kf, 34kx, 25kf CPU definitions.
418 (mips_cpu_info_from_isa): Use MIPS_CPU_IS_ISA.
419 * doc/c-mips.texi: Document .set {g,f}p={32,64,default}. Document
420 missing -march options. Document .set arch=CPU. Move .set smartmips
421 to ASE page. Use @code for .set FOO examples.
423 2006-05-23 Jie Zhang <jie.zhang@analog.com>
425 * config/tc-bfin.c (bfin_start_line_hook): Bump line counters
426 if needed.
428 2006-05-23 Jie Zhang <jie.zhang@analog.com>
430 * config/bfin-defs.h (bfin_equals): Remove declaration.
431 * config/bfin-parse.y (asm_1): Remove "expr ASSIGN expr".
432 * config/tc-bfin.c (bfin_name_is_register): Remove.
433 (bfin_equals): Remove.
434 * config/tc-bfin.h (TC_EQUAL_IN_INSN): Redefine as 1.
435 (bfin_name_is_register): Remove declaration.
437 2006-05-19 Thiemo Seufer <ths@mips.com>
438 Nigel Stephens <nigel@mips.com>
440 * config/tc-mipc.c (ISA_HAS_ODD_SINGLE_FPR): New define.
441 (mips_oddfpreg_ok): New function.
442 (mips_ip): Use it.
444 2006-05-19 Thiemo Seufer <ths@mips.com>
445 David Ung <davidu@mips.com>
447 * config/tc-mips.h (tc_mips_regname_to_dw2regnum): Declare.
448 * config/tc-mipc.c (ABI_NEEDS_64BIT_REGS, ISA_HAS_64BIT_REGS,
449 ISA_HAS_DROR, ISA_HAS_ROR): Reformat.
450 (regname, RTYPE_MASK, RTYPE_NUM, RTYPE_FPU, RTYPE_FCC, RTYPE_VEC,
451 RTYPE_GP, RTYPE_CP0, RTYPE_PC, RTYPE_ACC, RTYPE_CCC, RNUM_MASK,
452 RWARN, GENERIC_REGISTER_NUMBERS, FPU_REGISTER_NAMES,
453 FPU_CONDITION_CODE_NAMES, COPROC_CONDITION_CODE_NAMES,
454 N32N64_SYMBOLIC_REGISTER_NAMES, O32_SYMBOLIC_REGISTER_NAMES,
455 SYMBOLIC_REGISTER_NAMES, MIPS16_SPECIAL_REGISTER_NAMES,
456 MDMX_VECTOR_REGISTER_NAMES, MIPS_DSP_ACCUMULATOR_NAMES, reg_names,
457 reg_names_o32, reg_names_n32n64): Define register classes.
458 (reg_lookup): New function, use register classes.
459 (md_begin): Reserve register names in the symbol table. Simplify
460 OBJ_ELF defines.
461 (mips_ip): Fix comment formatting. Handle symbolic COP0 registers.
462 Use reg_lookup.
463 (mips16_ip): Use reg_lookup.
464 (tc_get_register): Likewise.
465 (tc_mips_regname_to_dw2regnum): New function.
467 2006-05-19 Thiemo Seufer <ths@mips.com>
469 * config/tc-arm.c, config/tc-arm.h (tc_arm_regname_to_dw2regnum):
470 Un-constify string argument.
471 * config/tc-i386.c, config/tc-i386.h (tc_x86_regname_to_dw2regnum):
472 Likewise.
473 * config/tc-m68k.c, config/tc-m68k.h (tc_m68k_regname_to_dw2regnum):
474 Likewise.
475 * config/tc-ppc.c, config/tc-ppc.h (tc_ppc_regname_to_dw2regnum):
476 Likewise.
477 * config/tc-s390.c, config/tc-s390.h (tc_s390_regname_to_dw2regnum):
478 Likewise.
479 * config/tc-sh.c, config/tc-sh.h (sh_regname_to_dw2regnum):
480 Likewise.
481 * config/tc-sparc.c, config/tc-sparc.h (sparc_regname_to_dw2regnum):
482 Likewise.
484 2006-05-19 Nathan Sidwell <nathan@codesourcery.com>
486 * gas/config/tc-m68k.c (m68k_init_arch): Move checking of
487 cfloat/m68881 to correct architecture before using it.
489 2006-05-16 Bjoern Haase <bjoern.m.haase@web.de>
491 * config/tc-avr.h (TC_VALIDATE_FIX): Allow fixups for immediate
492 constant values.
494 2006-05-15 Paul Brook <paul@codesourcery.com>
496 * config/tc-arm.c (arm_adjust_symtab): Use
497 bfd_is_arm_special_symbol_name.
499 2006-05-15 Bob Wilson <bob.wilson@acm.org>
501 * config/tc-xtensa.c (is_direct_call_opcode, is_branch_jmp_to_next,
502 xg_assemble_vliw_tokens, xtensa_mark_narrow_branches,
503 xtensa_fix_short_loop_frags, is_local_forward_loop, relax_frag_immed):
504 Handle errors from calls to xtensa_opcode_is_* functions.
506 2006-05-14 Thiemo Seufer <ths@mips.com>
508 * config/tc-mips.c (macro_build): Test for currently active
509 mips16 option.
510 (mips16_ip): Reject invalid opcodes.
512 2006-05-11 Carlos O'Donell <carlos@codesourcery.com>
514 * doc/as.texinfo: Rename "Index" to "AS Index",
515 and "ABORT" to "ABORT (COFF)".
517 2006-05-11 Paul Brook <paul@codesourcery.com>
519 * config/tc-arm.c (parse_half): New function.
520 (operand_parse_code): Remove OP_Iffff. Add OP_HALF.
521 (parse_operands): Ditto.
522 (do_mov16): Reject invalid relocations.
523 (do_t_mov16): Ditto. Use Thumb reloc numbers.
524 (insns): Replace Iffff with HALF.
525 (md_apply_fix): Add MOVW and MOVT relocs.
526 (tc_gen_reloc): Ditto.
527 * doc/c-arm.texi: Document relocation operators
529 2006-05-11 Paul Brook <paul@codesourcery.com>
531 * config/tc-arm.c (arm_fix_adjustable): Return 0 for function symbols.
533 2006-05-11 Thiemo Seufer <ths@mips.com>
535 * config/tc-mips.c (append_insn): Don't check the range of j or
536 jal addresses.
538 2006-05-11 Pedro Alves <pedro_alves@portugalmail.pt>
540 * config/tc-arm.c (md_pcrel_from_section): Force a bias for
541 relocs against external symbols for WinCE targets.
542 (md_apply_fix): Likewise.
544 2006-05-09 David Ung <davidu@mips.com>
546 * config/tc-mips.c (append_insn): Only warn about an out-of-range
547 j or jal address.
549 2006-05-09 Nick Clifton <nickc@redhat.com>
551 * config/tc-arm.c (arm_fix_adjustable): For COFF, convert fixups
552 against symbols which are not going to be placed into the symbol
553 table.
555 2006-05-09 Ben Elliston <bje@au.ibm.com>
557 * expr.c (operand): Remove `if (0 && ..)' statement and
558 subsequently unused target_op label. Collapse `if (1 || ..)'
559 statement.
560 * app.c (do_scrub_chars): Remove unused case 0, as it is handled
561 separately above the switch.
563 2006-05-08 Nick Clifton <nickc@redhat.com>
565 PR gas/2623
566 * config/tc-msp430.c (line_separator_character): Define as |.
568 2006-05-08 Thiemo Seufer <ths@mips.com>
569 Nigel Stephens <nigel@mips.com>
570 David Ung <davidu@mips.com>
572 * config/tc-mips.c (mips_set_options): Add ase_smartmips flag.
573 (mips_opts): Likewise.
574 (file_ase_smartmips): New variable.
575 (ISA_HAS_ROR): SmartMIPS implements rotate instructions.
576 (macro_build): Handle SmartMIPS instructions.
577 (mips_ip): Likewise.
578 (md_longopts): Add argument handling for smartmips.
579 (md_parse_options, mips_after_parse_args): Likewise.
580 (s_mipsset): Add .set smartmips support.
581 (md_show_usage): Document -msmartmips/-mno-smartmips.
582 * doc/as.texinfo: Document -msmartmips/-mno-smartmips and
583 .set smartmips.
584 * doc/c-mips.texi: Likewise.
586 2006-05-08 Alan Modra <amodra@bigpond.net.au>
588 * write.c (relax_segment): Add pass count arg. Don't error on
589 negative org/space on first two passes.
590 (relax_seg_info): New struct.
591 (relax_seg, write_object_file): Adjust.
592 * write.h (relax_segment): Update prototype.
594 2006-05-05 Julian Brown <julian@codesourcery.com>
596 * config/tc-arm.c (parse_vfp_reg_list): Improve register bounds
597 checking.
598 (do_neon_mov): Enable several VMOV variants for VFP. Add suitable
599 architecture version checks.
600 (insns): Allow overlapping instructions to be used in VFP mode.
602 2006-05-05 H.J. Lu <hongjiu.lu@intel.com>
604 PR gas/2598
605 * config/obj-elf.c (obj_elf_change_section): Allow user
606 specified SHF_ALPHA_GPREL.
608 2006-05-05 Bjoern Haase <bjoern.m.haase@web.de>
610 * gas/config/tc-avr.h (TC_VALIDATE_FIX): Define. Disable fixups
611 for PMEM related expressions.
613 2006-05-05 Nick Clifton <nickc@redhat.com>
615 PR gas/2582
616 * dwarf2dbg.c (INSERT_DIR_SEPARATOR): New macro. Handles the
617 insertion of a directory separator character into a string at a
618 given offset. Uses heuristics to decide when to use a backslash
619 character rather than a forward-slash character.
620 (dwarf2_directive_loc): Use the macro.
621 (out_debug_info): Likewise.
623 2006-05-05 Thiemo Seufer <ths@mips.com>
624 David Ung <davidu@mips.com>
626 * config/tc-mips.c (macro_build): Add case 'k' to handle cache
627 instruction.
628 (macro): Add new case M_CACHE_AB.
630 2006-05-04 Kazu Hirata <kazu@codesourcery.com>
632 * config/tc-arm.c (opcode_tag): Add OT_cinfix3_deprecated.
633 (opcode_lookup): Issue a warning for opcode with
634 OT_cinfix3_deprecated. Otherwise treat OT_cinfix3_deprecated
635 identical to OT_cinfix3.
636 (TxC3w, TC3w, tC3w): New.
637 (insns): Use tC3w and TC3w for comparison instructions with
638 's' suffix.
640 2006-05-04 Alan Modra <amodra@bigpond.net.au>
642 * subsegs.h (struct frchain): Delete frch_seg.
643 (frchain_root): Delete.
644 (seg_info): Define as macro.
645 * subsegs.c (frchain_root): Delete.
646 (abs_seg_info, und_seg_info, absolute_frchain): Delete.
647 (subsegs_begin, subseg_change): Adjust for above.
648 (subseg_set_rest): Likewise. Add new frchain structs to seginfo
649 rather than to one big list.
650 (subseg_get): Don't special case abs, und sections.
651 (subseg_new, subseg_force_new): Don't set frchainP here.
652 (seg_info): Delete.
653 (subsegs_print_statistics): Adjust frag chain control list traversal.
654 * debug.c (dmp_frags): Likewise.
655 * dwarf2dbg.c (first_frag_for_seg): Don't start looking for frag
656 at frchain_root. Make use of known frchain ordering.
657 (last_frag_for_seg): Likewise.
658 (get_frag_fix): Likewise. Add seg param.
659 (process_entries, out_debug_aranges): Adjust get_frag_fix calls.
660 * write.c (chain_frchains_together_1): Adjust for struct frchain.
661 (SUB_SEGMENT_ALIGN): Likewise.
662 (subsegs_finish): Adjust frchain list traversal.
663 * config/tc-xtensa.c (xtensa_cleanup_align_frags): Likewise.
664 (xtensa_fix_target_frags, xtensa_mark_narrow_branches): Likewise.
665 (xtensa_mark_zcl_first_insns, xtensa_fix_a0_b_retw_frags): Likewise.
666 (xtensa_fix_b_j_loop_end_frags): Likewise.
667 (xtensa_fix_close_loop_end_frags): Likewise.
668 (xtensa_fix_short_loop_frags, xtensa_sanity_check): Likewise.
669 (retrieve_segment_info): Delete frch_seg initialisation.
671 2006-05-03 Alan Modra <amodra@bigpond.net.au>
673 * subsegs.c (subseg_get): Don't call obj_sec_set_private_data.
674 * config/obj-elf.h (obj_sec_set_private_data): Delete.
675 * config/tc-hppa.c (tc_gen_reloc): Don't use bfd_abs_symbol.
676 * config/tc-mn10300.c (tc_gen_reloc): Likewise.
678 2006-05-02 Joseph Myers <joseph@codesourcery.com>
680 * config/tc-arm.c (do_iwmmxt_wldstbh): Don't multiply offset by 4
681 here.
682 (md_apply_fix3): Multiply offset by 4 here for
683 BFD_RELOC_ARM_CP_OFF_IMM_S2 and BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
685 2006-05-02 H.J. Lu <hongjiu.lu@intel.com>
686 Jan Beulich <jbeulich@novell.com>
688 * config/tc-i386.c (output_invalid_buf): Change size for
689 unsigned char.
690 * config/tc-tic30.c (output_invalid_buf): Likewise.
692 * config/tc-i386.c (output_invalid): Cast none-ascii char to
693 unsigned char.
694 * config/tc-tic30.c (output_invalid): Likewise.
696 2006-05-02 Daniel Jacobowitz <dan@codesourcery.com>
698 * doc/Makefile.am (AM_MAKEINFOFLAGS): New.
699 (TEXI2POD): Use AM_MAKEINFOFLAGS.
700 (asconfig.texi): Don't set top_srcdir.
701 * doc/as.texinfo: Don't use top_srcdir.
702 * aclocal.m4, Makefile.in, doc/Makefile.in: Regenerated.
704 2006-05-02 H.J. Lu <hongjiu.lu@intel.com>
706 * config/tc-i386.c (output_invalid_buf): Change size to 16.
707 * config/tc-tic30.c (output_invalid_buf): Likewise.
709 * config/tc-i386.c (output_invalid): Use snprintf instead of
710 sprintf.
711 * config/tc-ia64.c (declare_register_set): Likewise.
712 (emit_one_bundle): Likewise.
713 (check_dependencies): Likewise.
714 * config/tc-tic30.c (output_invalid): Likewise.
716 2006-05-02 Paul Brook <paul@codesourcery.com>
718 * config/tc-arm.c (arm_optimize_expr): New function.
719 * config/tc-arm.h (md_optimize_expr): Define
720 (arm_optimize_expr): Add prototype.
721 (TC_FORCE_RELOCATION_SUB_SAME): Define.
723 2006-05-02 Ben Elliston <bje@au.ibm.com>
725 * config/obj-elf.h (ELF_TARGET_SYMBOL_FIELDS): Make single bit
726 field unsigned.
728 * sb.h (sb_list_vector): Move to sb.c.
729 * sb.c (free_list): Use type of sb_list_vector directly.
730 (sb_build): Fix off-by-one error in assertion about `size'.
732 2006-05-01 Ben Elliston <bje@au.ibm.com>
734 * listing.c (listing_listing): Remove useless loop.
735 * macro.c (macro_expand): Remove is_positional local variable.
736 * read.c (s_comm_internal): Simplify `if' condition 1 || x -> 1
737 and simplify surrounding expressions, where possible.
738 (assign_symbol): Likewise.
739 (s_weakref): Likewise.
740 * symbols.c (colon): Likewise.
742 2006-05-01 James Lemke <jwlemke@wasabisystems.com>
744 * subsegs.c (subseg_set_rest): Always set seginfp->frchainP if NULL.
746 2006-04-30 Thiemo Seufer <ths@mips.com>
747 David Ung <davidu@mips.com>
749 * config/tc-mips.c (validate_mips_insn): Handling of udi cases.
750 (mips_immed): New table that records various handling of udi
751 instruction patterns.
752 (mips_ip): Adds udi handling.
754 2006-04-28 Alan Modra <amodra@bigpond.net.au>
756 * dwarf2dbg.c (get_line_subseg): Attach new struct line_seg to end
757 of list rather than beginning.
759 2006-04-26 Julian Brown <julian@codesourcery.com>
761 * gas/config/tc-arm.c (neon_is_quarter_float): Move, and rename to...
762 (is_quarter_float): Rename from above. Simplify slightly.
763 (parse_qfloat_immediate): Parse a "quarter precision" floating-point
764 number.
765 (parse_neon_mov): Parse floating-point constants.
766 (neon_qfloat_bits): Fix encoding.
767 (neon_cmode_for_move_imm): Tweak to use floating-point encoding in
768 preference to integer encoding when using the F32 type.
770 2006-04-26 Julian Brown <julian@codesourcery.com>
772 * config/tc-arm.c (neon_el_type): Make NT_invtype be the zero (so
773 zero-initialising structures containing it will lead to invalid types).
774 (arm_it): Add vectype to each operand.
775 (NTA_HASTYPE, NTA_HASINDEX): Constants used in neon_typed_alias
776 defined field.
777 (neon_typed_alias): New structure. Extra information for typed
778 register aliases.
779 (reg_entry): Add neon type info field.
780 (arm_reg_parse): Remove RTYPE argument (revert to previous arguments).
781 Break out alternative syntax for coprocessor registers, etc. into...
782 (arm_reg_alt_syntax): New function. Alternate syntax handling broken
783 out from arm_reg_parse.
784 (parse_neon_type): Move. Return SUCCESS/FAIL.
785 (first_error): New function. Call to ensure first error which occurs is
786 reported.
787 (parse_neon_operand_type): Parse exactly one type.
788 (NEON_ALL_LANES, NEON_INTERLEAVE_LANES): Move.
789 (parse_typed_reg_or_scalar): New function. Handle core of both
790 arm_typed_reg_parse and parse_scalar.
791 (arm_typed_reg_parse): Parse a register with an optional type.
792 (NEON_SCALAR_REG, NEON_SCALAR_INDEX): Extract parts of parse_scalar
793 result.
794 (parse_scalar): Parse a Neon scalar with optional type.
795 (parse_reg_list): Use first_error.
796 (parse_vfp_reg_list): Use arm_typed_reg_parse instead of arm_reg_parse.
797 (neon_alias_types_same): New function. Return true if two (alias) types
798 are the same.
799 (parse_neon_el_struct_list): Use parse_typed_reg_or_scalar. Return type
800 of elements.
801 (insert_reg_alias): Return new reg_entry not void.
802 (insert_neon_reg_alias): New function. Insert type/index information as
803 well as register for alias.
804 (create_neon_reg_alias): New function. Parse .dn/.qn directives and
805 make typed register aliases accordingly.
806 (s_dn, s_qn): New functions. Handle incorrectly used .dn/.qn at start
807 of line.
808 (s_unreq): Delete type information if present.
809 (s_arm_unwind_save_mmxwr): Remove arg 3 from arm_reg_parse calls.
810 (s_arm_unwind_save_mmxwcg): Likewise.
811 (s_arm_unwind_movsp): Likewise.
812 (s_arm_unwind_setfp): Likewise.
813 (parse_shift): Likewise.
814 (parse_shifter_operand): Likewise.
815 (parse_address): Likewise.
816 (parse_tb): Likewise.
817 (tc_arm_regname_to_dw2regnum): Likewise.
818 (md_pseudo_table): Add dn, qn.
819 (parse_neon_mov): Handle typed operands.
820 (parse_operands): Likewise.
821 (neon_type_mask): Add N_SIZ.
822 (N_ALLMODS): New macro.
823 (neon_check_shape): Fix typo in NS_DDD_QQQ case. Use first_error.
824 (el_type_of_type_chk): Add some safeguards.
825 (modify_types_allowed): Fix logic bug.
826 (neon_check_type): Handle operands with types.
827 (neon_three_same): Remove redundant optional arg handling.
828 (do_neon_dyadic_i64_su, do_neon_shl_imm, do_neon_qshl_imm)
829 (do_neon_logic, do_neon_qdmulh, do_neon_fcmp_absolute)
830 (do_neon_step): Adjust accordingly.
831 (neon_cmode_for_logic_imm): Use first_error.
832 (do_neon_bitfield): Call neon_check_type.
833 (neon_dyadic): Rename to...
834 (neon_dyadic_misc): ...this. New name for neon_dyadic. Add bitfield
835 to allow modification of type of the destination.
836 (do_neon_dyadic_if_su, do_neon_dyadic_if_i, do_neon_dyadic_if_i_d)
837 (do_neon_addsub_if_i, do_neon_mul): Adjust accordingly.
838 (do_neon_compare): Make destination be an untyped bitfield.
839 (neon_scalar_for_mul): Use NEON_SCALAR_REG, NEON_SCALAR_INDEX.
840 (neon_mul_mac): Return early in case of errors.
841 (neon_move_immediate): Use first_error.
842 (neon_mac_reg_scalar_long): Fix type to include scalar.
843 (do_neon_dup): Likewise.
844 (do_neon_mov): Likewise (in several places).
845 (do_neon_tbl_tbx): Fix type.
846 (do_neon_ld_st_interleave, neon_alignment_bit, do_neon_ld_st_lane)
847 (do_neon_ld_dup): Exit early in case of errors and/or use
848 first_error.
849 (opcode_lookup): Update for parse_neon_type returning SUCCESS/FAIL.
850 Handle .dn/.qn directives.
851 (REGDEF): Add zero for reg_entry neon field.
853 2006-04-26 Julian Brown <julian@codesourcery.com>
855 * config/tc-arm.c (limits.h): Include.
856 (fpu_arch_vfp_v3, fpu_vfp_ext_v3, fpu_neon_ext_v1)
857 (fpu_vfp_v3_or_neon_ext): Declare constants.
858 (neon_el_type): New enumeration of types for Neon vector elements.
859 (neon_type_el): New struct. Define type and size of a vector element.
860 (NEON_MAX_TYPE_ELS): Define constant. The maximum number of types per
861 instruction.
862 (neon_type): Define struct. The type of an instruction.
863 (arm_it): Add 'vectype' for the current instruction.
864 (isscalar, immisalign, regisimm, isquad): New predicates for operands.
865 (vfp_sp_reg_pos): Rename to...
866 (vfp_reg_pos): ...this, and add VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn
867 tags.
868 (arm_reg_type): Add REG_TYPE_NQ (Neon Q register) and REG_TYPE_NDQ
869 (Neon D or Q register).
870 (reg_expected_msgs): Sync with above. Allow VFD to mean VFP or Neon D
871 register.
872 (GE_OPT_PREFIX_BIG): Define constant, for use in...
873 (my_get_expression): Allow above constant as argument to accept
874 64-bit constants with optional prefix.
875 (arm_reg_parse): Add extra argument to return the specific type of
876 register in when either a D or Q register (REG_TYPE_NDQ) is
877 requested. Can be NULL.
878 (parse_scalar): New function. Parse Neon scalar (vector reg and index).
879 (parse_reg_list): Update for new arm_reg_parse args.
880 (parse_vfp_reg_list): Allow parsing of Neon D/Q register lists.
881 (parse_neon_el_struct_list): New function. Parse element/structure
882 register lists for VLD<n>/VST<n> instructions.
883 (s_arm_unwind_save_vfp): Update for new parse_vfp_reg_list args.
884 (s_arm_unwind_save_mmxwr): Likewise.
885 (s_arm_unwind_save_mmxwcg): Likewise.
886 (s_arm_unwind_movsp): Likewise.
887 (s_arm_unwind_setfp): Likewise.
888 (parse_big_immediate): New function. Parse an immediate, which may be
889 64 bits wide. Put results in inst.operands[i].
890 (parse_shift): Update for new arm_reg_parse args.
891 (parse_address): Likewise. Add parsing of alignment specifiers.
892 (parse_neon_mov): Parse the operands of a VMOV instruction.
893 (operand_parse_code): Add OP_RND, OP_RNQ, OP_RNDQ, OP_RNSC, OP_NRDLST,
894 OP_NSTRLST, OP_NILO, OP_RNDQ_I0, OP_RR_RNSC, OP_RNDQ_RNSC, OP_RND_RNSC,
895 OP_VMOV, OP_RNDQ_IMVNb, OP_RNDQ_I63b, OP_I0, OP_I16z, OP_I32z, OP_I64,
896 OP_I64z, OP_oI32b, OP_oRND, OP_oRNQ, OP_oRNDQ.
897 (parse_operands): Handle new codes above.
898 (encode_arm_vfp_sp_reg): Rename to...
899 (encode_arm_vfp_reg): ...this. Handle D regs (0-31) too. Complain if
900 selected VFP version only supports D0-D15.
901 (do_vfp_sp_monadic, do_vfp_sp_dyadic, do_vfp_sp_compare_z)
902 (do_vfp_dp_sp_cvt, do_vfp_reg_from_sp, do_vfp_reg2_from_sp2)
903 (do_vfp_sp_from_reg, do_vfp_sp2_from_reg2, do_vfp_sp_ldst)
904 (do_vfp_dp_ldst, vfp_sp_ldstm, vfp_dp_ldstm): Update for new
905 encode_arm_vfp_reg name, and allow 32 D regs.
906 (do_vfp_dp_rd_rm, do_vfp_dp_rn_rd, do_vfp_dp_rd_rn, do_vfp_dp_rd_rn_rm)
907 (do_vfp_rm_rd_rn): New functions to encode VFP insns allowing 32 D
908 regs.
909 (do_vfp_sp_const, do_vfp_dp_const, vfp_conv, do_vfp_sp_conv_16)
910 (do_vfp_dp_conv_16, do_vfp_sp_conv_32, do_vfp_dp_conv_32): Handle
911 constant-load and conversion insns introduced with VFPv3.
912 (neon_tab_entry): New struct.
913 (NEON_ENC_TAB): Bit patterns for overloaded Neon instructions, and
914 those which are the targets of pseudo-instructions.
915 (neon_opc): Enumerate opcodes, use as indices into...
916 (neon_enc_tab): ...this. Hold data from NEON_ENC_TAB.
917 (NEON_ENC_INTEGER, NEON_ENC_ARMREG, NEON_ENC_POLY, NEON_ENC_FLOAT)
918 (NEON_ENC_SCALAR, NEON_ENC_IMMED, NEON_ENC_INTERLV, NEON_ENC_LANE)
919 (NEON_ENC_DUP): Define meaningful helper macros to look up values in
920 neon_enc_tab.
921 (neon_shape): Enumerate shapes (permitted register widths, etc.) for
922 Neon instructions.
923 (neon_type_mask): New. Compact type representation for type checking.
924 (N_SU_ALL, N_SU_32, N_SU_16_64, N_SUF_32, N_I_ALL, N_IF_32): Common
925 permitted type combinations.
926 (N_IGNORE_TYPE): New macro.
927 (neon_check_shape): New function. Check an instruction shape for
928 multiple alternatives. Return the specific shape for the current
929 instruction.
930 (neon_modify_type_size): New function. Modify a vector type and size,
931 depending on the bit mask in argument 1.
932 (neon_type_promote): New function. Convert a given "key" type (of an
933 operand) into the correct type for a different operand, based on a bit
934 mask.
935 (type_chk_of_el_type): New function. Convert a type and size into the
936 compact representation used for type checking.
937 (el_type_of_type_ckh): New function. Reverse of above (only when a
938 single bit is set in the bit mask).
939 (modify_types_allowed): New function. Alter a mask of allowed types
940 based on a bit mask of modifications.
941 (neon_check_type): New function. Check the type of the current
942 instruction against the variable argument list. The "key" type of the
943 instruction is returned.
944 (neon_dp_fixup): New function. Fill in and modify instruction bits for
945 a Neon data-processing instruction depending on whether we're in ARM
946 mode or Thumb-2 mode.
947 (neon_logbits): New function.
948 (neon_three_same, neon_two_same, do_neon_dyadic_i_su)
949 (do_neon_dyadic_i64_su, neon_imm_shift, do_neon_shl_imm)
950 (do_neon_qshl_imm, neon_cmode_for_logic_imm, neon_bits_same_in_bytes)
951 (neon_squash_bits, neon_is_quarter_float, neon_qfloat_bits)
952 (neon_cmode_for_move_imm, neon_write_immbits, neon_invert_size)
953 (do_neon_logic, do_neon_bitfield, neon_dyadic, do_neon_dyadic_if_su)
954 (do_neon_dyadic_if_su_d, do_neon_dyadic_if_i, do_neon_dyadic_if_i_d)
955 (do_neon_addsub_if_i, neon_exchange_operands, neon_compare)
956 (do_neon_cmp, do_neon_cmp_inv, do_neon_ceq, neon_scalar_for_mul)
957 (neon_mul_mac, do_neon_mac_maybe_scalar, do_neon_tst, do_neon_mul)
958 (do_neon_qdmulh, do_neon_fcmp_absolute, do_neon_fcmp_absolute_inv)
959 (do_neon_step, do_neon_abs_neg, do_neon_sli, do_neon_sri)
960 (do_neon_qshlu_imm, do_neon_qmovn, do_neon_qmovun)
961 (do_neon_rshift_sat_narrow, do_neon_rshift_sat_narrow_u, do_neon_movn)
962 (do_neon_rshift_narrow, do_neon_shll, neon_cvt_flavour, do_neon_cvt)
963 (neon_move_immediate, do_neon_mvn, neon_mixed_length)
964 (do_neon_dyadic_long, do_neon_abal, neon_mac_reg_scalar_long)
965 (do_neon_mac_maybe_scalar_long, do_neon_dyadic_wide, do_neon_vmull)
966 (do_neon_ext, do_neon_rev, do_neon_dup, do_neon_mov)
967 (do_neon_rshift_round_imm, do_neon_movl, do_neon_trn, do_neon_zip_uzp)
968 (do_neon_sat_abs_neg, do_neon_pair_long, do_neon_recip_est)
969 (do_neon_cls, do_neon_clz, do_neon_cnt, do_neon_swp, do_neon_tbl_tbx)
970 (do_neon_ldm_stm, do_neon_ldr_str, do_neon_ld_st_interleave)
971 (neon_alignment_bit, do_neon_ld_st_lane, do_neon_ld_dup)
972 (do_neon_ldx_stx): New functions. Neon bit encoding and encoding
973 helpers.
974 (parse_neon_type): New function. Parse Neon type specifier.
975 (opcode_lookup): Allow parsing of Neon type specifiers.
976 (REGNUM2, REGSETH, REGSET2): New macros.
977 (reg_names): Add new VFPv3 and Neon registers.
978 (NUF, nUF, NCE, nCE): New macros for opcode table.
979 (insns): More VFP registers allowed in fcpyd, fmdhr, fmdlr, fmrdh,
980 fmrdl, fabsd, fnegd, fsqrtd, faddd, fsubd, fmuld, fdivd, fmacd, fmscd,
981 fnmuld, fnmacd, fnmscd, fcmpd, fcmpzd, fcmped, fcmpezd, fmdrr, fmrrd.
982 Add Neon instructions vaba, vhadd, vrhadd, vhsub, vqadd, vqsub, vrshl,
983 vqrshl, vshl, vqshl{u}, vand, vbic, vorr, vorn, veor, vbsl, vbit, vbif,
984 vabd, vmax, vmin, vcge, vcgt, vclt, vcle, vceq, vpmax, vpmin, vmla,
985 vmls, vpadd, vadd, vsub, vtst, vmul, vqdmulh, vqrdmulh, vacge, vacgt,
986 vaclt, vacle, vrecps, vrsqrts, vabs, vneg, v{r}shr, v{r}sra, vsli,
987 vsri, vqshrn, vq{r}shr{u}n, v{r}shrn, vshll, vcvt, vmov, vmvn, vabal,
988 vabdl, vaddl, vsubl, vmlal, vmlsl, vaddw, vsubw, v{r}addhn, v{r}subhn,
989 vqdmlal, vqdmlsl, vqdmull, vmull, vext, vrev64, vrev32, vrev16, vdup,
990 vmovl, v{q}movn, vzip, vuzp, vqabs, vqneg, vpadal, vpaddl, vrecpe,
991 vrsqrte, vcls, vclz, vcnt, vswp, vtrn, vtbl, vtbx, vldm, vstm, vldr,
992 vstr, vld[1234], vst[1234], fconst[sd], f[us][lh]to[sd],
993 fto[us][lh][sd].
994 (tc_arm_regname_to_dw2regnum): Update for arm_reg_parse args.
995 (arm_cpu_option_table): Add Neon and VFPv3 to Cortex-A8.
996 (arm_option_cpu_value): Add vfp3 and neon.
997 (aeabi_set_public_attributes): Support VFPv3 and NEON attributes. Fix
998 VFPv1 attribute.
1000 2006-04-25 Bob Wilson <bob.wilson@acm.org>
1002 * config/xtensa-relax.c (widen_spec_list): Use new "WIDE.<opcode>"
1003 syntax instead of hardcoded opcodes with ".w18" suffixes.
1004 (wide_branch_opcode): New.
1005 (build_transition): Use it to check for wide branch opcodes with
1006 either ".w18" or ".w15" suffixes.
1008 2006-04-25 Bob Wilson <bob.wilson@acm.org>
1010 * config/tc-xtensa.c (xtensa_create_literal_symbol,
1011 xg_assemble_literal, xg_assemble_literal_space): Do not set the
1012 frag's is_literal flag.
1014 2006-04-25 Bob Wilson <bob.wilson@acm.org>
1016 * config/xtensa-relax.c (XCHAL_HAVE_WIDE_BRANCHES): Provide default.
1018 2006-04-23 Kazu Hirata <kazu@codesourcery.com>
1020 * config/obj-coff.c, config/tc-arm.c, config/tc-bfin.c,
1021 config/tc-cris.c, config/tc-crx.c, config/tc-i386.c,
1022 config/tc-ia64.c, config/tc-maxq.c, config/tc-maxq.h,
1023 config/tc-mips.c, config/tc-msp430.c, config/tc-sh.c,
1024 config/tc-tic4x.c, config/tc-xtensa.c: Fix comment typos.
1026 2005-04-20 Paul Brook <paul@codesourcery.com>
1028 * config/tc-arm.c (s_arm_arch, s_arm_cpu, s_arm_fpu): Enable for
1029 all targets.
1030 (md_pseudo_table): Enable .arch, .cpu and .fpu for all targets.
1032 2006-04-19 Alan Modra <amodra@bigpond.net.au>
1034 * Makefile.am (CPU_TYPES): Add maxq and mt. Sort.
1035 (CPU_OBJ_VALID): Change sense of COFF test to default to invalid.
1036 Make some cpus unsupported on ELF. Run "make dep-am".
1037 * Makefile.in: Regenerate.
1039 2006-04-19 Alan Modra <amodra@bigpond.net.au>
1041 * configure.in (--enable-targets): Indent help message.
1042 * configure: Regenerate.
1044 2006-04-18 H.J. Lu <hongjiu.lu@intel.com>
1046 PR gas/2533
1047 * config/tc-i386.c (i386_immediate): Check illegal immediate
1048 register operand.
1050 2006-04-18 Alan Modra <amodra@bigpond.net.au>
1052 * config/tc-i386.c: Formatting.
1053 (output_disp, output_imm): ISO C90 params.
1055 * frags.c (frag_offset_fixed_p): Constify args.
1056 * frags.h (frag_offset_fixed_p): Ditto.
1058 * config/tc-dlx.h (tc_coff_symbol_emit_hook): Delete.
1059 (COFF_MAGIC): Delete.
1061 * config/tc-xc16x.h (TC_LINKRELAX_FIXUP): Delete.
1063 2006-04-16 Daniel Jacobowitz <dan@codesourcery.com>
1065 * po/POTFILES.in: Regenerated.
1067 2006-04-16 Mark Mitchell <mark@codesourcery.com>
1069 * doc/as.texinfo: Mention that some .type syntaxes are not
1070 supported on all architectures.
1072 2006-04-14 Sterling Augustine <sterling@tensilica.com>
1074 * config/tc-xtensa.c (emit_single_op): Do not relax MOVI
1075 instructions when such transformations have been disabled.
1077 2006-04-10 Sterling Augustine <sterling@tensilica.com>
1079 * config/tc-xtensa.c (xg_assemble_vliw_tokens): Record loop target
1080 symbols in RELAX[_CHECK]_ALIGN_NEXT_OPCODE frags.
1081 (xtensa_fix_close_loop_end_frags): Use the recorded values instead of
1082 decoding the loop instructions. Remove current_offset variable.
1083 (xtensa_fix_short_loop_frags): Likewise.
1084 (min_bytes_to_other_loop_end): Remove current_offset argument.
1086 2006-04-09 Arnold Metselaar <arnold.metselaar@planet.nl>
1088 * config/tc-z80.c (z80_optimize_expr): Removed.
1089 * config/tc-z80.h (z80_optimize_expr, md_optimize_expr): Removed.
1091 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
1093 * gas/config/tc-avr.c (mcu_types): Add support for attiny261,
1094 attiny461, attiny861, attiny25, attiny45, attiny85,attiny24,
1095 attiny44, attiny84, at90pwm2, at90pwm3, atmega164, atmega324,
1096 atmega644, atmega329, atmega3290, atmega649, atmega6490,
1097 atmega406, atmega640, atmega1280, atmega1281, at90can32,
1098 at90can64, at90usb646, at90usb647, at90usb1286 and
1099 at90usb1287.
1100 Move atmega48 and atmega88 from AVR_ISA_M8 to AVR_ISA_PWMx.
1102 2006-04-07 Paul Brook <paul@codesourcery.com>
1104 * config/tc-arm.c (parse_operands): Set default error message.
1106 2006-04-07 Paul Brook <paul@codesourcery.com>
1108 * config/tc-arm.c (parse_tb): Set inst.error before returning FAIL.
1110 2006-04-07 Paul Brook <paul@codesourcery.com>
1112 * config/tc-arm.c (md_apply_fix): Set H bit on blx instruction.
1114 2006-04-07 Paul Brook <paul@codesourcery.com>
1116 * config/tc-arm.c (THUMB2_LOAD_BIT): Define.
1117 (move_or_literal_pool): Handle Thumb-2 instructions.
1118 (do_t_ldst): Call move_or_literal_pool for =N addressing modes.
1120 2006-04-07 Alan Modra <amodra@bigpond.net.au>
1122 PR 2512.
1123 * config/tc-i386.c (match_template): Move 64-bit operand tests
1124 inside loop.
1126 2006-04-06 Carlos O'Donell <carlos@codesourcery.com>
1128 * po/Make-in: Add install-html target.
1129 * Makefile.am: Add install-html and install-html-recursive targets.
1130 * Makefile.in: Regenerate.
1131 * configure.in: AC_SUBST datarootdir, docdir, htmldir.
1132 * configure: Regenerate.
1133 * doc/Makefile.am: Add install-html and install-html-am targets.
1134 * doc/Makefile.in: Regenerate.
1136 2006-04-06 Alan Modra <amodra@bigpond.net.au>
1138 * frags.c (frag_offset_fixed_p): Reinitialise offset before
1139 second scan.
1141 2006-04-05 Richard Sandiford <richard@codesourcery.com>
1142 Daniel Jacobowitz <dan@codesourcery.com>
1144 * config/tc-sparc.c (sparc_target_format): Handle TE_VXWORKS.
1145 (GOTT_BASE, GOTT_INDEX): New.
1146 (tc_gen_reloc): Don't alter relocations against GOTT_BASE and
1147 GOTT_INDEX when generating VxWorks PIC.
1148 * configure.tgt (sparc*-*-vxworks*): Remove this special case;
1149 use the generic *-*-vxworks* stanza instead.
1151 2006-04-04 Alan Modra <amodra@bigpond.net.au>
1153 PR 997
1154 * frags.c (frag_offset_fixed_p): New function.
1155 * frags.h (frag_offset_fixed_p): Declare.
1156 * expr.c (expr): Use frag_offset_fixed_p when simplifying subtraction.
1157 (resolve_expression): Likewise.
1159 2006-04-03 Sterling Augustine <sterling@tensilica.com>
1161 * config/tc-xtensa.c (init_op_placement_info_table): Check for formats
1162 of the same length but different numbers of slots.
1164 2006-03-30 Andreas Schwab <schwab@suse.de>
1166 * configure.in: Fix help string for --enable-targets option.
1167 * configure: Regenerate.
1169 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1171 * gas/config/tc-m68k.c (find_cf_chip): Merge into ...
1172 (m68k_ip): ... here. Use for all chips. Protect against buffer
1173 overrun and avoid excessive copying.
1175 * config/tc-m68k.c (m68000_control_regs, m68010_control_regs,
1176 m68020_control_regs, m68040_control_regs, m68060_control_regs,
1177 mcf_control_regs, mcf5208_control_regs, mcf5213_control_regs,
1178 mcf5329_control_regs, mcf5249_control_regs, mcf528x_control_regs,
1179 mcfv4e_control_regs, m68010_control_regs): Rename and reorder to ...
1180 (m68000_ctrl, m68010_ctrl, m68020_ctrl, m68040_ctrl, m68060_ctrl,
1181 mcf_ctrl, mcf5208_ctrl, mcf5213_ctrl, mcf5235_ctrl, mcf5249_ctrl,
1182 mcf5216_ctrl, mcf5250_ctrl, mcf5271_ctrl, mcf5272_ctrl,
1183 mcf5282_ctrl, mcfv4e_ctrl): ... these.
1184 (mcf5275_ctrl, mcf5329_ctrl, mcf5373_ctrl): New.
1185 (struct m68k_cpu): Change chip field to control_regs.
1186 (current_chip): Remove.
1187 (control_regs): New.
1188 (m68k_archs, m68k_extensions): Adjust.
1189 (m68k_cpus): Reorder to be in cpu number order. Adjust.
1190 (CPU_ALLOW_MC, CPU_ALLOW_NEGATION): Remove.
1191 (find_cf_chip): Reimplement for new organization of cpu table.
1192 (select_control_regs): Remove.
1193 (mri_chip): Adjust.
1194 (struct save_opts): Save control regs, not chip.
1195 (s_save, s_restore): Adjust.
1196 (m68k_lookup_cpu): Give deprecated warning when necessary.
1197 (m68k_init_arch): Adjust.
1198 (md_show_usage): Adjust for new cpu table organization.
1200 2006-03-25 Bernd Schmidt <bernd.schmidt@analog.com>
1202 * config/bfin-defs.h (Expr_Node_Type enum): Add Expr_Node_GOT_Reloc.
1203 * config/bfin-lex.l: Recognize GOT17M4 and FUNCDESC_GOT17M4.
1204 * config/bfin-parse.y: Include "libbfd.h", "elf/common.h" and
1205 "elf/bfin.h".
1206 (GOT17M4, FUNCDESC_GOT17M4): New tokens of type <value>.
1207 (any_gotrel): New rule.
1208 (got): Use it, and create Expr_Node_GOT_Reloc nodes.
1209 * config/tc-bfin.c: Include "libbfd.h", "elf/common.h" and
1210 "elf/bfin.h".
1211 (DEFAULT_FLAGS, bfin_flags, bfin_pic_flag): New.
1212 (bfin_pic_ptr): New function.
1213 (md_pseudo_table): Add it for ".picptr".
1214 (OPTION_FDPIC): New macro.
1215 (md_longopts): Add -mfdpic.
1216 (md_parse_option): Handle it.
1217 (md_begin): Set BFD flags.
1218 (md_apply_fix3, bfin_fix_adjustable): Handle new relocs.
1219 (bfin_gen_ldstidxi): Adjust to match the trees that the parser gives
1220 us for GOT relocs.
1221 * Makefile.am (bfin-parse.o): Update dependencies.
1222 (DEPTC_bfin_elf): Likewise.
1223 * Makefile.in: Regenerate.
1225 2006-03-25 Richard Sandiford <richard@codesourcery.com>
1227 * config/tc-m68k.c (m68k_cpus): Change cpu_cf5208 entries to use
1228 mcfemac instead of mcfmac.
1230 2006-03-23 Michael Matz <matz@suse.de>
1232 * config/tc-i386.c (type_names): Correct placement of 'static'.
1233 (reloc): Map some more relocs to their 64 bit counterpart when
1234 size is 8.
1235 (output_insn): Work around breakage if DEBUG386 is defined.
1236 (output_disp): A BFD_RELOC_64 with GOT_symbol as operand also
1237 needs to be mapped to BFD_RELOC_X86_64_GOTPC64 or
1238 BFD_RELOC_X86_64_GOTPC32. Also x86-64 handles pcrel addressing
1239 different from i386.
1240 (output_imm): Ditto.
1241 (lex_got): Recognize @PLTOFF and @GOTPLT. Make @GOT accept also
1242 Imm64.
1243 (md_convert_frag): Jumps can now be larger than 2GB away, error
1244 out in that case.
1245 (tc_gen_reloc): New relocs are passed through. BFD_RELOC_64
1246 and BFD_RELOC_64_PCREL are mapped to BFD_RELOC_X86_64_GOTPC64.
1248 2006-03-22 Richard Sandiford <richard@codesourcery.com>
1249 Daniel Jacobowitz <dan@codesourcery.com>
1250 Phil Edwards <phil@codesourcery.com>
1251 Zack Weinberg <zack@codesourcery.com>
1252 Mark Mitchell <mark@codesourcery.com>
1253 Nathan Sidwell <nathan@codesourcery.com>
1255 * config/tc-mips.c (mips_target_format): Handle vxworks targets.
1256 (md_begin): Complain about -G being used for PIC. Don't change
1257 the text, data and bss alignments on VxWorks.
1258 (reloc_needs_lo_p): Don't return true for R_MIPS_GOT16 when
1259 generating VxWorks PIC.
1260 (load_address): Extend SVR4_PIC handling to VXWORKS_PIC.
1261 (macro): Likewise, but do not treat la $25 specially for
1262 VxWorks PIC, and do not handle jal.
1263 (OPTION_MVXWORKS_PIC): New macro.
1264 (md_longopts): Add -mvxworks-pic.
1265 (md_parse_option): Don't complain about using PIC and -G together here.
1266 Handle OPTION_MVXWORKS_PIC.
1267 (md_estimate_size_before_relax): Always use the first relaxation
1268 sequence on VxWorks.
1269 * config/tc-mips.h (VXWORKS_PIC): New.
1271 2006-03-21 Paul Brook <paul@codesourcery.com>
1273 * config/tc-arm.c (md_apply_fix): Fix typo in offset mask.
1275 2006-03-21 Sterling Augustine <sterling@tensilica.com>
1277 * config/tc-xtensa.c (enforce_three_byte_loop_align): New flag.
1278 (xtensa_setup_hw_workarounds): Set this new flag for older hardware.
1279 (get_loop_align_size): New.
1280 (xtensa_end): Skip xtensa_mark_narrow_branches when not aligning.
1281 (xtensa_mark_zcl_first_insns): Prevent widening of first loop frag.
1282 (get_text_align_power): Rewrite to handle inputs in the range 2-8.
1283 (get_noop_aligned_address): Use get_loop_align_size.
1284 (get_aligned_diff): Likewise.
1286 2006-03-21 Paul Brook <paul@codesourcery.com>
1288 * config/tc-arm.c (insns): Correct opcodes for ldrbt and strbt.
1290 2006-03-20 Paul Brook <paul@codesourcery.com>
1292 * config/tc-arm.c (BAD_BRANCH, BAD_NOT_IT): Define.
1293 (do_t_branch): Encode branches inside IT blocks as unconditional.
1294 (do_t_cps): New function.
1295 (do_t_blx, do_t_bkpt, do_t_branch23, do_t_bx, do_t_bxj, do_t_cpsi,
1296 do_t_czb, do_t_it, do_t_setend, do_t_tb): Add IT constaints.
1297 (opcode_lookup): Allow conditional suffixes on all instructions in
1298 Thumb mode.
1299 (md_assemble): Advance condexec state before checking for errors.
1300 (insns): Use do_t_cps.
1302 2006-03-20 Paul Brook <paul@codesourcery.com>
1304 * config/tc-arm.c (output_relax_insn): Call dwarf2_emit_insn before
1305 outputting the insn.
1307 2006-03-18 Jan-Benedict Glaw <jbglaw@lug-owl.de>
1309 * config/tc-vax.c: Update copyright year.
1310 * config/tc-vax.h: Likewise.
1312 2006-03-18 Jan-Benedict Glaw <jbglaw@lug-owl.de>
1314 * config/tc-vax.c (md_chars_to_number): Used only locally, so
1315 make it static.
1316 * config/tc-vax.h (md_chars_to_number): Remove obsolete declaration.
1318 2006-03-17 Paul Brook <paul@codesourcery.com>
1320 * config/tc-arm.c (insns): Add ldm and stm.
1322 2006-03-17 Ben Elliston <bje@au.ibm.com>
1324 PR gas/2446
1325 * doc/as.texinfo (Ident): Document this directive more thoroughly.
1327 2006-03-16 Paul Brook <paul@codesourcery.com>
1329 * config/tc-arm.c (insns): Add "svc".
1331 2006-03-13 Bob Wilson <bob.wilson@acm.org>
1333 * config/tc-xtensa.c (xg_translate_sysreg_op): Remove has_underbar
1334 flag and avoid double underscore prefixes.
1336 2006-03-10 Paul Brook <paul@codesourcery.com>
1338 * config/tc-arm.c (md_begin): Handle EABIv5.
1339 (arm_eabis): Add EF_ARM_EABI_VER5.
1340 * doc/c-arm.texi: Document -meabi=5.
1342 2006-03-10 Ben Elliston <bje@au.ibm.com>
1344 * app.c (do_scrub_chars): Simplify string handling.
1346 2006-03-07 Richard Sandiford <richard@codesourcery.com>
1347 Daniel Jacobowitz <dan@codesourcery.com>
1348 Zack Weinberg <zack@codesourcery.com>
1349 Nathan Sidwell <nathan@codesourcery.com>
1350 Paul Brook <paul@codesourcery.com>
1351 Ricardo Anguiano <anguiano@codesourcery.com>
1352 Phil Edwards <phil@codesourcery.com>
1354 * config/tc-arm.c (md_apply_fix): Install a value of zero into a
1355 BFD_RELOC_ARM_OFFSET_IMM field if we're going to generate a RELA
1356 R_ARM_ABS12 reloc.
1357 (tc_gen_reloc): Keep the original fx_offset for RELA pc-relative
1358 relocs, but adjust by md_pcrel_from_section. Create R_ARM_ABS12
1359 relocations for BFD_RELOC_ARM_OFFSET_IMM on RELA targets.
1361 2006-03-06 Bob Wilson <bob.wilson@acm.org>
1363 * config/tc-xtensa.c (xtensa_post_relax_hook): Generate literal tables
1364 even when using the text-section-literals option.
1366 2006-03-06 Nathan Sidwell <nathan@codesourcery.com>
1368 * config/tc-m68k.c (m68k_extensions): Allow 'float' on both m68k
1369 and cf.
1370 (m68k_ip): <case 'J'> Check we have some control regs.
1371 (md_parse_option): Allow raw arch switch.
1372 (m68k_init_arch): Better detection of arch/cpu mismatch. Detect
1373 whether 68881 or cfloat was meant by -mfloat.
1374 (md_show_usage): Adjust extension display.
1375 (m68k_elf_final_processing): Adjust.
1377 2006-03-03 Bjoern Haase <bjoern.m.haase@web.de>
1379 * config/tc-avr.c (avr_mod_hash_value): New function.
1380 (md_apply_fix, exp_mod): Use BFD_RELOC_HH8_LDI and
1381 BFD_RELOC_MS8_LDI for hlo8() and hhi8()
1382 (md_begin): Set linkrelax variable to 1, use avr_mod_hash_value
1383 instead of int avr_ldi_expression: use avr_mod_hash_value instead
1384 of (int).
1385 (tc_gen_reloc): Handle substractions of symbols, if possible do
1386 fixups, abort otherwise.
1387 * config/tc-avr.h (TC_LINKRELAX_FIXUP, TC_VALIDATE_FIX,
1388 tc_fix_adjustable): Define.
1390 2006-03-02 James E Wilson <wilson@specifix.com>
1392 * config/tc-ia64.c (emit_one_bundle): For IA64_OPCODE_LAST, if we
1393 change the template, then clear md.slot[curr].end_of_insn_group.
1395 2006-02-28 Jan Beulich <jbeulich@novell.com>
1397 * macro.c (get_any_string): Don't insert quotes for <>-quoted input.
1399 2006-02-28 Jan Beulich <jbeulich@novell.com>
1401 PR/1070
1402 * macro.c (getstring): Don't treat parentheses special anymore.
1403 (get_any_string): Don't consider '(' and ')' as quoting anymore.
1404 Special-case '(', ')', '[', and ']' when dealing with non-quoting
1405 characters.
1407 2006-02-28 Mat <mat@csail.mit.edu>
1409 * dwarf2dbg.c (get_filenum): Don't inadvertently decrease files_in_use.
1411 2006-02-27 Jakub Jelinek <jakub@redhat.com>
1413 * dw2gencfi.c (struct fde_entry, struct cie_entry): Add signal_frame
1414 field.
1415 (CFI_signal_frame): Define.
1416 (cfi_pseudo_table): Add .cfi_signal_frame.
1417 (dot_cfi): Handle CFI_signal_frame.
1418 (output_cie): Handle cie->signal_frame.
1419 (select_cie_for_fde): Don't share CIE if signal_frame flag is
1420 different. Copy signal_frame from FDE to newly created CIE.
1421 * doc/as.texinfo: Document .cfi_signal_frame.
1423 2006-02-27 Carlos O'Donell <carlos@codesourcery.com>
1425 * doc/Makefile.am: Add html target.
1426 * doc/Makefile.in: Regenerate.
1427 * po/Make-in: Add html target.
1429 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1431 * config/tc-i386.c (output_insn): Support Intel Merom New
1432 Instructions.
1434 * config/tc-i386.h (CpuMNI): New.
1435 (CpuUnknownFlags): Add CpuMNI.
1437 2006-02-24 David S. Miller <davem@sunset.davemloft.net>
1439 * config/tc-sparc.c (priv_reg_table): Add entry for "gl".
1440 (hpriv_reg_table): New table for hyperprivileged registers.
1441 (sparc_ip): New cases '$' and '%' for wrhpr/rdhpr hyperprivileged
1442 register encoding.
1444 2006-02-24 DJ Delorie <dj@redhat.com>
1446 * config/tc-m32c.h (md_apply_fix): Define to m32c_apply_fix.
1447 (tc_gen_reloc): Don't define.
1448 * config/tc-m32c.c (rl_for, relaxable): New convenience macros.
1449 (OPTION_LINKRELAX): New.
1450 (md_longopts): Add it.
1451 (m32c_relax): New.
1452 (md_parse_options): Set it.
1453 (md_assemble): Emit relaxation relocs as needed.
1454 (md_convert_frag): Emit relaxation relocs as needed.
1455 (md_cgen_lookup_reloc): Add LAB_8_8 and LAB_8_16.
1456 (m32c_apply_fix): New.
1457 (tc_gen_reloc): New.
1458 (m32c_force_relocation): Force out jump relocs when relaxing.
1459 (m32c_fix_adjustable): Return false if relaxing.
1461 2006-02-24 Paul Brook <paul@codesourcery.com>
1463 * config/arm/tc-arm.c (arm_ext_v6_notm, arm_ext_div, arm_ext_v7,
1464 arm_ext_v7a, arm_ext_v7r, arm_ext_v7m): New variables.
1465 (struct asm_barrier_opt): Define.
1466 (arm_v7m_psr_hsh, arm_barrier_opt_hsh): New variables.
1467 (parse_psr): Accept V7M psr names.
1468 (parse_barrier): New function.
1469 (enum operand_parse_code): Add OP_oBARRIER.
1470 (parse_operands): Implement OP_oBARRIER.
1471 (do_barrier): New function.
1472 (do_dbg, do_pli, do_t_barrier, do_t_dbg, do_t_div): New functions.
1473 (do_t_cpsi): Add V7M restrictions.
1474 (do_t_mrs, do_t_msr): Validate V7M variants.
1475 (md_assemble): Check for NULL variants.
1476 (v7m_psrs, barrier_opt_names): New tables.
1477 (insns): Add V7 instructions. Mark V6 instructions absent from V7M.
1478 (md_begin): Initialize arm_v7m_psr_hsh and arm_barrier_opt_hsh.
1479 (arm_cpu_option_table): Add Cortex-M3, R4 and A8.
1480 (arm_arch_option_table): Add armv7, armv7a, armv7r and armv7m.
1481 (struct cpu_arch_ver_table): Define.
1482 (cpu_arch_ver): New.
1483 (aeabi_set_public_attributes): Use cpu_arch_ver. Set
1484 Tag_CPU_arch_profile.
1485 * doc/c-arm.texi: Document new cpu and arch options.
1487 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1489 * config/tc-ia64.c (operand_match): Handle IA64_OPND_IMMU5b.
1491 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1493 * config/tc-ia64.c: Update copyright years.
1495 2006-02-22 H.J. Lu <hongjiu.lu@intel.com>
1497 * config/tc-ia64.c (specify_resource): Add the rule 17 from
1498 SDM 2.2.
1500 2005-02-22 Paul Brook <paul@codesourcery.com>
1502 * config/tc-arm.c (do_pld): Remove incorrect write to
1503 inst.instruction.
1504 (encode_thumb32_addr_mode): Use correct operand.
1506 2006-02-21 Paul Brook <paul@codesourcery.com>
1508 * config/tc-arm.c (md_apply_fix): Fix off-by-one errors.
1510 2006-02-17 Shrirang Khisti <shrirangk@kpitcummins.com>
1511 Anil Paranjape <anilp1@kpitcummins.com>
1512 Shilin Shakti <shilins@kpitcummins.com>
1514 * Makefile.am: Add xc16x related entry.
1515 * Makefile.in: Regenerate.
1516 * configure.in: Added xc16x related entry.
1517 * configure: Regenerate.
1518 * config/tc-xc16x.h: New file
1519 * config/tc-xc16x.c: New file
1520 * doc/c-xc16x.texi: New file for xc16x
1521 * doc/all.texi: Entry for xc16x
1522 * doc/Makefile.texi: Added c-xc16x.texi
1523 * NEWS: Announce the support for the new target.
1525 2006-02-16 Nick Hudson <nick.hudson@dsl.pipex.com>
1527 * configure.tgt: set emulation for mips-*-netbsd*
1529 2006-02-14 Jakub Jelinek <jakub@redhat.com>
1531 * config.in: Rebuilt.
1533 2006-02-13 Bob Wilson <bob.wilson@acm.org>
1535 * config/tc-xtensa.c (xg_add_opcode_fix): Number operands starting
1536 from 1, not 0, in error messages.
1537 (md_assemble): Simplify special-case check for ENTRY instructions.
1538 (tinsn_has_invalid_symbolic_operands): Do not include opcode and
1539 operand in error message.
1541 2006-02-13 Joseph S. Myers <joseph@codesourcery.com>
1543 * configure.tgt (arm-*-linux-gnueabi*): Change to
1544 arm-*-linux-*eabi*.
1546 2006-02-10 Nick Clifton <nickc@redhat.com>
1548 * config/tc-crx.c (check_range): Ensure that the sign bit of a
1549 32-bit value is propagated into the upper bits of a 64-bit long.
1551 * config/tc-arc.c (init_opcode_tables): Fix cast.
1552 (arc_extoper, md_operand): Likewise.
1554 2006-02-09 David Heine <dlheine@tensilica.com>
1556 * config/tc-xtensa.c (xg_assembly_relax): Increment steps_taken for
1557 each relaxation step.
1559 2006-02-09 Eric Botcazou <ebotcazou@libertysurf.fr>
1561 * configure.in (CHECK_DECLS): Add vsnprintf.
1562 * configure: Regenerate.
1563 * messages.c (errno.h, stdarg.h, varargs.h, va_list): Do not
1564 include/declare here, but...
1565 * as.h: Move code detecting VARARGS idiom to the top.
1566 (errno.h, stdarg.h, varargs.h, va_list): ...here.
1567 (vsnprintf): Declare if not already declared.
1569 2006-02-08 H.J. Lu <hongjiu.lu@intel.com>
1571 * as.c (close_output_file): New.
1572 (main): Register close_output_file with xatexit before
1573 dump_statistics. Don't call output_file_close.
1575 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
1577 * config/tc-m68k.c (mcf5208_control_regs, mcf5213_control_regs,
1578 mcf5329_control_regs): New.
1579 (not_current_architecture, selected_arch, selected_cpu): New.
1580 (m68k_archs, m68k_extensions): New.
1581 (archs): Renamed to ...
1582 (m68k_cpus): ... here. Adjust.
1583 (n_arches): Remove.
1584 (md_pseudo_table): Add arch and cpu directives.
1585 (find_cf_chip, m68k_ip): Adjust table scanning.
1586 (no_68851, no_68881): Remove.
1587 (md_assemble): Lazily initialize.
1588 (select_control_regs): Adjust cpu names. Add 5208, 5213, 5329.
1589 (md_init_after_args): Move functionality to m68k_init_arch.
1590 (mri_chip): Adjust table scanning.
1591 (md_parse_option): Reimplement 'm' processing to add -march & -mcpu
1592 options with saner parsing.
1593 (m68k_lookup_cpu, m68k_set_arch, m68k_set_cpu, m68k_set_extension,
1594 m68k_init_arch): New.
1595 (s_m68k_cpu, s_m68k_arch): New.
1596 (md_show_usage): Adjust.
1597 (m68k_elf_final_processing): Set CF EF flags.
1598 * config/tc-m68k.h (m68k_init_after_args): Remove.
1599 (tc_init_after_args): Remove.
1600 * doc/c-m68k.texi (M68K-Opts): Document -march, -mcpu options.
1601 (M68k-Directives): Document .arch and .cpu directives.
1603 2006-02-05 Arnold Metselaar <arnold.metselaar@planet.nl>
1605 * config/tc-z80.c (z80_start_line_hook): allow .equ and .defl as
1606 synonyms for equ and defl.
1607 (z80_cons_fix_new): New function.
1608 (emit_byte): Disallow relative jumps to absolute locations.
1609 (emit_data): Only handle defb, prototype changed, because defb is
1610 now handled as pseudo-op rather than an instruction.
1611 (instab): Entries for defb,defw,db,dw moved from here...
1612 (md_pseudo_table): ... to here, use generic cons() for defw,dw.
1613 Add entries for def24,def32,d24,d32.
1614 (md_assemble): Improved error handling.
1615 (md_apply_fix): New case BFD_RELOC_24, set fixP->fx_no_overflow to one.
1616 * config/tc-z80.h (TC_CONS_FIX_NEW): Define.
1617 (z80_cons_fix_new): Declare.
1618 * doc/c-z80.texi (defb, db): Mention warning on overflow.
1619 (def24,d24,def32,d32): New pseudo-ops.
1621 2006-02-02 Paul Brook <paul@codesourcery.com>
1623 * config/tc-arm.c (do_shift): Remove Thumb-1 constraint.
1625 2005-02-02 Paul Brook <paul@codesourcery.com>
1627 * config/tc-arm.c (T2_OPCODE_MASK, T2_DATA_OP_SHIFT, T2_OPCODE_AND,
1628 T2_OPCODE_BIC, T2_OPCODE_ORR, T2_OPCODE_ORN, T2_OPCODE_EOR,
1629 T2_OPCODE_ADD, T2_OPCODE_ADC, T2_OPCODE_SBC, T2_OPCODE_SUB,
1630 T2_OPCODE_RSB): Define.
1631 (thumb32_negate_data_op): New function.
1632 (md_apply_fix): Use it.
1634 2006-01-31 Bob Wilson <bob.wilson@acm.org>
1636 * config/xtensa-istack.h (TInsn): Remove record_fix and sub_symbol
1637 fields.
1638 * config/tc-xtensa.h (xtensa_frag_type): Remove slot_sub_symbols field.
1639 * config/tc-xtensa.c (md_apply_fix): Check for unexpected uses of
1640 subtracted symbols.
1641 (relaxation_requirements): Add pfinish_frag argument and use it to
1642 replace setting tinsn->record_fix fields.
1643 (xg_assemble_vliw_tokens): Adjust calls to relaxation_requirements
1644 and vinsn_to_insnbuf. Remove references to record_fix and
1645 slot_sub_symbols fields.
1646 (xtensa_mark_narrow_branches): Delete unused code.
1647 (is_narrow_branch_guaranteed_in_range): Handle expr that is not just
1648 a symbol.
1649 (convert_frag_immed): Adjust vinsn_to_insnbuf call and do not set
1650 record_fix fields.
1651 (tinsn_immed_from_frag): Remove code for handling slot_sub_symbols.
1652 (vinsn_to_insnbuf): Change use of record_fixup argument, replacing use
1653 of the record_fix field. Simplify error messages for unexpected
1654 symbolic operands.
1655 (set_expr_symbol_offset_diff): Delete.
1657 2006-01-31 Paul Brook <paul@codesourcery.com>
1659 * config/tc-arm.c (arm_reg_parse): Check if reg is non-NULL.
1661 2006-01-31 Paul Brook <paul@codesourcery.com>
1662 Richard Earnshaw <rearnsha@arm.com>
1664 * config/tc-arm.c: Use arm_feature_set.
1665 (arm_ext_*, arm_arch_full, arm_arch_t2, arm_arch_none,
1666 arm_cext_iwmmxt, arm_cext_xscale, arm_cext_maverick, fpu_fpa_ext_v1,
1667 fpu_fpa_ext_v2, fpu_vfp_ext_v1xd, fpu_vfp_ext_v1, fpu_vfp_ext_v2):
1668 New variables.
1669 (insns): Use them.
1670 (md_atof, opcode_select, opcode_select, md_assemble, md_assemble,
1671 md_begin, arm_parse_extension, arm_parse_cpu, arm_parse_arch,
1672 arm_parse_fpu, arm_parse_float_abi, aeabi_set_public_attributes,
1673 s_arm_cpu, s_arm_arch, s_arm_fpu): Use macros for accessing CPU
1674 feature flags.
1675 (arm_legacy_option_table, arm_option_cpu_value_table): New types.
1676 (arm_opts): Move old cpu/arch options from here...
1677 (arm_legacy_opts): ... to here.
1678 (md_parse_option): Search arm_legacy_opts.
1679 (arm_cpus, arm_archs, arm_extensions, arm_fpus)
1680 (arm_float_abis, arm_eabis): Make const.
1682 2006-01-25 Bob Wilson <bob.wilson@acm.org>
1684 * config/tc-xtensa.c (md_apply_fix): Set value to zero for PLT relocs.
1686 2006-01-21 Jie Zhang <jie.zhang@analog.com>
1688 * config/bfin-parse.y (asm_1): Check value range for 16 bit immediate
1689 in load immediate intruction.
1691 2006-01-21 Jie Zhang <jie.zhang@analog.com>
1693 * config/bfin-parse.y (value_match): Use correct conversion
1694 specifications in template string for __FILE__ and __LINE__.
1695 (binary): Ditto.
1696 (unary): Ditto.
1698 2006-01-18 Alexandre Oliva <aoliva@redhat.com>
1700 Introduce TLS descriptors for i386 and x86_64.
1701 * config/tc-i386.c (tc_i386_fix_adjustable): Handle
1702 BFD_RELOC_386_TLS_GOTDESC, BFD_RELOC_386_TLS_DESC_CALL,
1703 BFD_RELOC_X86_64_GOTPC32_TLSDESC, BFD_RELOC_X86_64_TLSDESC_CALL.
1704 (optimize_disp): Emit fix up for BFD_RELOC_386_TLS_DESC_CALL and
1705 BFD_RELOC_X86_64_TLSDESC_CALL immediately, and clear the
1706 displacement bits.
1707 (build_modrm_byte): Set up zero modrm for TLS desc calls.
1708 (lex_got): Handle @tlsdesc and @tlscall.
1709 (md_apply_fix, tc_gen_reloc): Handle the new relocations.
1711 2006-01-11 Nick Clifton <nickc@redhat.com>
1713 Fixes for building on 64-bit hosts:
1714 * config/tc-avr.c (mod_index): New union to allow conversion
1715 between pointers and integers.
1716 (md_begin, avr_ldi_expression): Use it.
1717 * config/tc-i370.c (md_assemble): Add cast for argument to print
1718 statement.
1719 * config/tc-tic54x.c (subsym_substitute): Likewise.
1720 * config/tc-mn10200.c (md_assemble): Use a union to convert the
1721 opindex field of fr_cgen structure into a pointer so that it can
1722 be stored in a frag.
1723 * config/tc-mn10300.c (md_assemble): Likewise.
1724 * config/tc-frv.c (frv_debug_tomcat): Use %p to print pointer
1725 types.
1726 * config/tc-v850.c: Replace uses of (int) casts with correct
1727 types.
1729 2006-01-09 H.J. Lu <hongjiu.lu@intel.com>
1731 PR gas/2117
1732 * symbols.c (snapshot_symbol): Don't change a defined symbol.
1734 2006-01-03 Hans-Peter Nilsson <hp@bitrange.com>
1736 PR gas/2101
1737 * config/tc-mmix.c (mmix_handle_mmixal): Don't treat #[0-9][FB] as
1738 a local-label reference.
1740 For older changes see ChangeLog-2005
1741 \f
1742 Local Variables:
1743 mode: change-log
1744 left-margin: 8
1745 fill-column: 74
1746 version-control: never
1747 End: