opcodes/i860-dis.c

   1 /* Disassembler for the i860.
   2    Copyright 2000 Free Software Foundation, Inc.
   3
   4    Contributed by Jason Eckhardt <jle@cygnus.com>.
   5
   6 This program is free software; you can redistribute it and/or modify
   7 it under the terms of the GNU General Public License as published by
   8 the Free Software Foundation; either version 2 of the License, or
   9 (at your option) any later version.
  10
  11 This program is distributed in the hope that it will be useful,
  12 but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 GNU General Public License for more details.
  15
  16 You should have received a copy of the GNU General Public License
  17 along with this program; if not, write to the Free Software
  18 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  19
  20 #include "dis-asm.h"
  21 #include "opcode/i860.h"
  22
  23 /* Later we should probably choose the prefix based on which OS flavor.  */
  24 #define I860_REG_PREFIX "%"
  25
  26 /* Integer register names (encoded as 0..31 in the instruction).  */
  27 static const char *const grnames[] =
  28  {"r0",  "r1",  "sp",  "fp",  "r4",  "r5",  "r6",  "r7",
  29   "r8",  "r9",  "r10", "r11", "r12", "r13", "r14", "r15",
  30   "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
  31   "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"};
  32
  33 /* FP register names (encoded as 0..31 in the instruction).  */
  34 static const char *const frnames[] =
  35  {"f0",  "f1",  "f2",  "f3",  "f4",  "f5",  "f6",  "f7",
  36   "f8",  "f9",  "f10", "f11", "f12", "f13", "f14", "f15",
  37   "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
  38   "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"};
  39
  40 /* Control/status register names (encoded as 0..5 in the instruction).  */
  41 static const char *const crnames[] =
  42  {"fir", "psr", "dirbase", "db", "fsr", "epsr", "", ""};
  43
  44
  45 /* Prototypes.  */
  46 static int sign_ext             PARAMS((unsigned int, int));
  47 static void print_br_address    PARAMS((disassemble_info *, bfd_vma, long));
  48
  49
  50 /* True if opcode is xor, xorh, and, andh, or, orh, andnot, andnoth.  */
  51 #define BITWISE_OP(op)  ((op) == 0x30 || (op) == 0x31           \
  52                          || (op) == 0x34 || (op) == 0x35        \
  53                          || (op) == 0x38 || (op) == 0x39        \
  54                          || (op) == 0x3c || (op) == 0x3d        \
  55                          || (op) == 0x33 || (op) == 0x37        \
  56                          || (op) == 0x3b || (op) == 0x3f)
  57
  58
  59 /* Sign extend N-bit number.  */
  60 static int
  61 sign_ext (x, n)
  62      unsigned int x;
  63      int n;
  64 {
  65   int t;
  66   t = x >> (n - 1);
  67   t = ((-t) << n) | x;
  68   return t;
  69 }
  70
  71
  72 /* Print a PC-relative branch offset.  VAL is the sign extended value
  73    from the branch instruction.  */
  74 static void
  75 print_br_address (info, memaddr, val)
  76      disassemble_info *info;
  77      bfd_vma memaddr;
  78      long val;
  79 {
  80
  81   long adj = (long)memaddr + 4 + (val << 2);
  82
  83   (*info->fprintf_func) (info->stream, "0x%08x", adj);
  84
  85   /* Attempt to obtain a symbol for the target address.  */
  86
  87   if (info->print_address_func && adj != 0)
  88     {
  89       (*info->fprintf_func) (info->stream, "\t// ");
  90       (*info->print_address_func) (adj, info);
  91     }
  92 }
  93
  94
  95 /* Print one instruction.  */
  96 int
  97 print_insn_i860 (memaddr, info)
  98      bfd_vma memaddr;
  99      disassemble_info *info;
 100 {
 101   bfd_byte buff[4];
 102   unsigned int insn, i;
 103   int status;
 104   const struct i860_opcode *opcode = 0;
 105
 106   status = (*info->read_memory_func) (memaddr, buff, sizeof (buff), info);
 107   if (status != 0)
 108     {
 109       (*info->memory_error_func) (status, memaddr, info);
 110       return -1;
 111     }
 112
 113   /* Note that i860 instructions are always accessed as little endian
 114      data, regardless of the endian mode of the i860.  */
 115   insn = bfd_getl32 (buff);
 116
 117   status = 0;
 118   i = 0;
 119   while (i860_opcodes[i].name != NULL)
 120     {
 121       opcode = &i860_opcodes[i];
 122       if ((insn & opcode->match) == opcode->match
 123           && (insn & opcode->lose) == 0)
 124         {
 125           status = 1;
 126           break;
 127         }
 128       ++i;
 129     }
 130
 131   if (status == 0)
 132     {
 133       /* Instruction not in opcode table.  */
 134       (*info->fprintf_func) (info->stream, ".long %#08x", insn);
 135     }
 136   else
 137     {
 138       const char *s;
 139       int val;
 140
 141       /* If this a flop and its dual bit is set, prefix with 'd.'.  */
 142       if ((insn & 0xfc000000) == 0x48000000 && (insn & 0x200))
 143         (*info->fprintf_func) (info->stream, "d.%s\t", opcode->name);
 144       else
 145         (*info->fprintf_func) (info->stream, "%s\t", opcode->name);
 146
 147       for (s = opcode->args; *s; s++)
 148         {
 149           switch (*s)
 150             {
 151             /* Integer register (src1).  */
 152             case '1':
 153               (*info->fprintf_func) (info->stream, "%s%s", I860_REG_PREFIX,
 154                                      grnames[(insn >> 11) & 0x1f]);
 155               break;
 156
 157             /* Integer register (src2).  */
 158             case '2':
 159               (*info->fprintf_func) (info->stream, "%s%s", I860_REG_PREFIX,
 160                                      grnames[(insn >> 21) & 0x1f]);
 161               break;
 162
 163             /* Integer destination register.  */
 164             case 'd':
 165               (*info->fprintf_func) (info->stream, "%s%s", I860_REG_PREFIX,
 166                                      grnames[(insn >> 16) & 0x1f]);
 167               break;
 168
 169             /* Floating-point register (src1).  */
 170             case 'e':
 171               (*info->fprintf_func) (info->stream, "%s%s", I860_REG_PREFIX,
 172                                      frnames[(insn >> 11) & 0x1f]);
 173               break;
 174
 175             /* Floating-point register (src2).  */
 176             case 'f':
 177               (*info->fprintf_func) (info->stream, "%s%s", I860_REG_PREFIX,
 178                                      frnames[(insn >> 21) & 0x1f]);
 179               break;
 180
 181             /* Floating-point destination register.  */
 182             case 'g':
 183               (*info->fprintf_func) (info->stream, "%s%s", I860_REG_PREFIX,
 184                                      frnames[(insn >> 16) & 0x1f]);
 185               break;
 186
 187             /* Control register.  */
 188             case 'c':
 189               (*info->fprintf_func) (info->stream, "%s%s", I860_REG_PREFIX,
 190                                      crnames[(insn >> 21) & 0x7]);
 191               break;
 192
 193             /* 16-bit immediate (sign extend, except for bitwise ops).  */
 194             case 'i':
 195               if (BITWISE_OP ((insn & 0xfc000000) >> 26))
 196                 (*info->fprintf_func) (info->stream, "0x%04x",
 197                                        (unsigned int) (insn & 0xffff));
 198               else
 199                 (*info->fprintf_func) (info->stream, "%d",
 200                                        sign_ext ((insn & 0xffff), 16));
 201               break;
 202
 203             /* 16-bit immediate, aligned (2^0, ld.b).  */
 204             case 'I':
 205               (*info->fprintf_func) (info->stream, "%d",
 206                                      sign_ext ((insn & 0xffff), 16));
 207               break;
 208
 209             /* 16-bit immediate, aligned (2^1, ld.s).  */
 210             case 'J':
 211               (*info->fprintf_func) (info->stream, "%d",
 212                                      sign_ext ((insn & 0xfffe), 16));
 213               break;
 214
 215             /* 16-bit immediate, aligned (2^2, ld.l, {p}fld.l, fst.l).  */
 216             case 'K':
 217               (*info->fprintf_func) (info->stream, "%d",
 218                                      sign_ext ((insn & 0xfffc), 16));
 219               break;
 220
 221             /* 16-bit immediate, aligned (2^3, {p}fld.d, fst.d).  */
 222             case 'L':
 223               (*info->fprintf_func) (info->stream, "%d",
 224                                      sign_ext ((insn & 0xfff8), 16));
 225               break;
 226
 227             /* 16-bit immediate, aligned (2^4, {p}fld.q, fst.q).  */
 228             case 'M':
 229               (*info->fprintf_func) (info->stream, "%d",
 230                                      sign_ext ((insn & 0xfff0), 16));
 231               break;
 232
 233             /* 5-bit immediate (zero extend).  */
 234             case '5':
 235               (*info->fprintf_func) (info->stream, "%d",
 236                                      ((insn >> 11) & 0x1f));
 237               break;
 238
 239             /* Split 16 bit immediate (20..16:10..0).  */
 240             case 's':
 241               val = ((insn >> 5) & 0xf800) | (insn & 0x07ff);
 242               (*info->fprintf_func) (info->stream, "%d",
 243                                      sign_ext (val, 16));
 244               break;
 245
 246             /* Split 16 bit immediate, aligned. (2^0, st.b).  */
 247             case 'S':
 248               val = ((insn >> 5) & 0xf800) | (insn & 0x07ff);
 249               (*info->fprintf_func) (info->stream, "%d",
 250                                      sign_ext (val, 16));
 251               break;
 252
 253             /* Split 16 bit immediate, aligned. (2^1, st.s).  */
 254             case 'T':
 255               val = ((insn >> 5) & 0xf800) | (insn & 0x07fe);
 256               (*info->fprintf_func) (info->stream, "%d",
 257                                      sign_ext (val, 16));
 258               break;
 259
 260             /* Split 16 bit immediate, aligned. (2^2, st.l).  */
 261             case 'U':
 262               val = ((insn >> 5) & 0xf800) | (insn & 0x07fc);
 263               (*info->fprintf_func) (info->stream, "%d",
 264                                      sign_ext (val, 16));
 265               break;
 266
 267             /* 26-bit PC relative immediate (lbroff).  */
 268             case 'l':
 269               val = sign_ext ((insn & 0x03ffffff), 26);
 270               print_br_address (info, memaddr, val);
 271               break;
 272
 273             /* 16-bit PC relative immediate (sbroff).  */
 274             case 'r':
 275               val = sign_ext ((((insn >> 5) & 0xf800) | (insn & 0x07ff)), 16);
 276               print_br_address (info, memaddr, val);
 277               break;
 278
 279             default:
 280               (*info->fprintf_func) (info->stream, "%c", *s);
 281               break;
 282             }
 283         }
 284     }
 285
 286   return sizeof (insn);
 287 }
 288