2006-02-14 Paolo Bonzini <bonzini@gnu.org>
[binutils.git] / gas / config / tc-sparc.c
blobb14c377b5646843d6bca27ff65500ea21ad19586
1 /* tc-sparc.c -- Assemble for the SPARC
2 Copyright 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005
4 Free Software Foundation, Inc.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public
18 License along with GAS; see the file COPYING. If not, write
19 to the Free Software Foundation, 51 Franklin Street - Fifth Floor,
20 Boston, MA 02110-1301, USA. */
22 #include <stdio.h>
24 #include "as.h"
25 #include "safe-ctype.h"
26 #include "subsegs.h"
28 #include "opcode/sparc.h"
29 #include "dw2gencfi.h"
31 #ifdef OBJ_ELF
32 #include "elf/sparc.h"
33 #include "dwarf2dbg.h"
34 #endif
36 /* Some ancient Sun C compilers would not take such hex constants as
37 unsigned, and would end up sign-extending them to form an offsetT,
38 so use these constants instead. */
39 #define U0xffffffff ((((unsigned long) 1 << 16) << 16) - 1)
40 #define U0x80000000 ((((unsigned long) 1 << 16) << 15))
42 static struct sparc_arch *lookup_arch PARAMS ((char *));
43 static void init_default_arch PARAMS ((void));
44 static int sparc_ip PARAMS ((char *, const struct sparc_opcode **));
45 static int in_signed_range PARAMS ((bfd_signed_vma, bfd_signed_vma));
46 static int in_unsigned_range PARAMS ((bfd_vma, bfd_vma));
47 static int in_bitfield_range PARAMS ((bfd_signed_vma, bfd_signed_vma));
48 static int sparc_ffs PARAMS ((unsigned int));
49 static void synthetize_setuw PARAMS ((const struct sparc_opcode *));
50 static void synthetize_setsw PARAMS ((const struct sparc_opcode *));
51 static void synthetize_setx PARAMS ((const struct sparc_opcode *));
52 static bfd_vma BSR PARAMS ((bfd_vma, int));
53 static int cmp_reg_entry PARAMS ((const PTR, const PTR));
54 static int parse_keyword_arg PARAMS ((int (*) (const char *), char **, int *));
55 static int parse_const_expr_arg PARAMS ((char **, int *));
56 static int get_expression PARAMS ((char *str));
58 /* Default architecture. */
59 /* ??? The default value should be V8, but sparclite support was added
60 by making it the default. GCC now passes -Asparclite, so maybe sometime in
61 the future we can set this to V8. */
62 #ifndef DEFAULT_ARCH
63 #define DEFAULT_ARCH "sparclite"
64 #endif
65 static char *default_arch = DEFAULT_ARCH;
67 /* Non-zero if the initial values of `max_architecture' and `sparc_arch_size'
68 have been set. */
69 static int default_init_p;
71 /* Current architecture. We don't bump up unless necessary. */
72 static enum sparc_opcode_arch_val current_architecture = SPARC_OPCODE_ARCH_V6;
74 /* The maximum architecture level we can bump up to.
75 In a 32 bit environment, don't allow bumping up to v9 by default.
76 The native assembler works this way. The user is required to pass
77 an explicit argument before we'll create v9 object files. However, if
78 we don't see any v9 insns, a v8plus object file is not created. */
79 static enum sparc_opcode_arch_val max_architecture;
81 /* Either 32 or 64, selects file format. */
82 static int sparc_arch_size;
83 /* Initial (default) value, recorded separately in case a user option
84 changes the value before md_show_usage is called. */
85 static int default_arch_size;
87 #ifdef OBJ_ELF
88 /* The currently selected v9 memory model. Currently only used for
89 ELF. */
90 static enum { MM_TSO, MM_PSO, MM_RMO } sparc_memory_model = MM_RMO;
91 #endif
93 static int architecture_requested;
94 static int warn_on_bump;
96 /* If warn_on_bump and the needed architecture is higher than this
97 architecture, issue a warning. */
98 static enum sparc_opcode_arch_val warn_after_architecture;
100 /* Non-zero if as should generate error if an undeclared g[23] register
101 has been used in -64. */
102 static int no_undeclared_regs;
104 /* Non-zero if we should try to relax jumps and calls. */
105 static int sparc_relax;
107 /* Non-zero if we are generating PIC code. */
108 int sparc_pic_code;
110 /* Non-zero if we should give an error when misaligned data is seen. */
111 static int enforce_aligned_data;
113 extern int target_big_endian;
115 static int target_little_endian_data;
117 /* Symbols for global registers on v9. */
118 static symbolS *globals[8];
120 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
121 int sparc_cie_data_alignment;
123 /* V9 and 86x have big and little endian data, but instructions are always big
124 endian. The sparclet has bi-endian support but both data and insns have
125 the same endianness. Global `target_big_endian' is used for data.
126 The following macro is used for instructions. */
127 #ifndef INSN_BIG_ENDIAN
128 #define INSN_BIG_ENDIAN (target_big_endian \
129 || default_arch_type == sparc86x \
130 || SPARC_OPCODE_ARCH_V9_P (max_architecture))
131 #endif
133 /* Handle of the OPCODE hash table. */
134 static struct hash_control *op_hash;
136 static int mylog2 PARAMS ((int));
137 static void s_data1 PARAMS ((void));
138 static void s_seg PARAMS ((int));
139 static void s_proc PARAMS ((int));
140 static void s_reserve PARAMS ((int));
141 static void s_common PARAMS ((int));
142 static void s_empty PARAMS ((int));
143 static void s_uacons PARAMS ((int));
144 static void s_ncons PARAMS ((int));
145 #ifdef OBJ_ELF
146 static void s_register PARAMS ((int));
147 #endif
149 const pseudo_typeS md_pseudo_table[] =
151 {"align", s_align_bytes, 0}, /* Defaulting is invalid (0). */
152 {"common", s_common, 0},
153 {"empty", s_empty, 0},
154 {"global", s_globl, 0},
155 {"half", cons, 2},
156 {"nword", s_ncons, 0},
157 {"optim", s_ignore, 0},
158 {"proc", s_proc, 0},
159 {"reserve", s_reserve, 0},
160 {"seg", s_seg, 0},
161 {"skip", s_space, 0},
162 {"word", cons, 4},
163 {"xword", cons, 8},
164 {"uahalf", s_uacons, 2},
165 {"uaword", s_uacons, 4},
166 {"uaxword", s_uacons, 8},
167 #ifdef OBJ_ELF
168 /* These are specific to sparc/svr4. */
169 {"2byte", s_uacons, 2},
170 {"4byte", s_uacons, 4},
171 {"8byte", s_uacons, 8},
172 {"register", s_register, 0},
173 #endif
174 {NULL, 0, 0},
177 /* This array holds the chars that always start a comment. If the
178 pre-processor is disabled, these aren't very useful. */
179 const char comment_chars[] = "!"; /* JF removed '|' from
180 comment_chars. */
182 /* This array holds the chars that only start a comment at the beginning of
183 a line. If the line seems to have the form '# 123 filename'
184 .line and .file directives will appear in the pre-processed output. */
185 /* Note that input_file.c hand checks for '#' at the beginning of the
186 first line of the input file. This is because the compiler outputs
187 #NO_APP at the beginning of its output. */
188 /* Also note that comments started like this one will always
189 work if '/' isn't otherwise defined. */
190 const char line_comment_chars[] = "#";
192 const char line_separator_chars[] = ";";
194 /* Chars that can be used to separate mant from exp in floating point
195 nums. */
196 const char EXP_CHARS[] = "eE";
198 /* Chars that mean this number is a floating point constant.
199 As in 0f12.456
200 or 0d1.2345e12 */
201 const char FLT_CHARS[] = "rRsSfFdDxXpP";
203 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
204 changed in read.c. Ideally it shouldn't have to know about it at all,
205 but nothing is ideal around here. */
207 #define isoctal(c) ((unsigned) ((c) - '0') < 8)
209 struct sparc_it
211 char *error;
212 unsigned long opcode;
213 struct nlist *nlistp;
214 expressionS exp;
215 expressionS exp2;
216 int pcrel;
217 bfd_reloc_code_real_type reloc;
220 struct sparc_it the_insn, set_insn;
222 static void output_insn
223 PARAMS ((const struct sparc_opcode *, struct sparc_it *));
225 /* Table of arguments to -A.
226 The sparc_opcode_arch table in sparc-opc.c is insufficient and incorrect
227 for this use. That table is for opcodes only. This table is for opcodes
228 and file formats. */
230 enum sparc_arch_types {v6, v7, v8, sparclet, sparclite, sparc86x, v8plus,
231 v8plusa, v9, v9a, v9b, v9_64};
233 static struct sparc_arch {
234 char *name;
235 char *opcode_arch;
236 enum sparc_arch_types arch_type;
237 /* Default word size, as specified during configuration.
238 A value of zero means can't be used to specify default architecture. */
239 int default_arch_size;
240 /* Allowable arg to -A? */
241 int user_option_p;
242 } sparc_arch_table[] = {
243 { "v6", "v6", v6, 0, 1 },
244 { "v7", "v7", v7, 0, 1 },
245 { "v8", "v8", v8, 32, 1 },
246 { "sparclet", "sparclet", sparclet, 32, 1 },
247 { "sparclite", "sparclite", sparclite, 32, 1 },
248 { "sparc86x", "sparclite", sparc86x, 32, 1 },
249 { "v8plus", "v9", v9, 0, 1 },
250 { "v8plusa", "v9a", v9, 0, 1 },
251 { "v8plusb", "v9b", v9, 0, 1 },
252 { "v9", "v9", v9, 0, 1 },
253 { "v9a", "v9a", v9, 0, 1 },
254 { "v9b", "v9b", v9, 0, 1 },
255 /* This exists to allow configure.in/Makefile.in to pass one
256 value to specify both the default machine and default word size. */
257 { "v9-64", "v9", v9, 64, 0 },
258 { NULL, NULL, v8, 0, 0 }
261 /* Variant of default_arch */
262 static enum sparc_arch_types default_arch_type;
264 static struct sparc_arch *
265 lookup_arch (name)
266 char *name;
268 struct sparc_arch *sa;
270 for (sa = &sparc_arch_table[0]; sa->name != NULL; sa++)
271 if (strcmp (sa->name, name) == 0)
272 break;
273 if (sa->name == NULL)
274 return NULL;
275 return sa;
278 /* Initialize the default opcode arch and word size from the default
279 architecture name. */
281 static void
282 init_default_arch ()
284 struct sparc_arch *sa = lookup_arch (default_arch);
286 if (sa == NULL
287 || sa->default_arch_size == 0)
288 as_fatal (_("Invalid default architecture, broken assembler."));
290 max_architecture = sparc_opcode_lookup_arch (sa->opcode_arch);
291 if (max_architecture == SPARC_OPCODE_ARCH_BAD)
292 as_fatal (_("Bad opcode table, broken assembler."));
293 default_arch_size = sparc_arch_size = sa->default_arch_size;
294 default_init_p = 1;
295 default_arch_type = sa->arch_type;
298 /* Called by TARGET_FORMAT. */
300 const char *
301 sparc_target_format ()
303 /* We don't get a chance to initialize anything before we're called,
304 so handle that now. */
305 if (! default_init_p)
306 init_default_arch ();
308 #ifdef OBJ_AOUT
309 #ifdef TE_NetBSD
310 return "a.out-sparc-netbsd";
311 #else
312 #ifdef TE_SPARCAOUT
313 if (target_big_endian)
314 return "a.out-sunos-big";
315 else if (default_arch_type == sparc86x && target_little_endian_data)
316 return "a.out-sunos-big";
317 else
318 return "a.out-sparc-little";
319 #else
320 return "a.out-sunos-big";
321 #endif
322 #endif
323 #endif
325 #ifdef OBJ_BOUT
326 return "b.out.big";
327 #endif
329 #ifdef OBJ_COFF
330 #ifdef TE_LYNX
331 return "coff-sparc-lynx";
332 #else
333 return "coff-sparc";
334 #endif
335 #endif
337 #ifdef OBJ_ELF
338 return sparc_arch_size == 64 ? "elf64-sparc" : "elf32-sparc";
339 #endif
341 abort ();
344 /* md_parse_option
345 * Invocation line includes a switch not recognized by the base assembler.
346 * See if it's a processor-specific option. These are:
348 * -bump
349 * Warn on architecture bumps. See also -A.
351 * -Av6, -Av7, -Av8, -Asparclite, -Asparclet
352 * Standard 32 bit architectures.
353 * -Av9, -Av9a, -Av9b
354 * Sparc64 in either a 32 or 64 bit world (-32/-64 says which).
355 * This used to only mean 64 bits, but properly specifying it
356 * complicated gcc's ASM_SPECs, so now opcode selection is
357 * specified orthogonally to word size (except when specifying
358 * the default, but that is an internal implementation detail).
359 * -Av8plus, -Av8plusa, -Av8plusb
360 * Same as -Av9{,a,b}.
361 * -xarch=v8plus, -xarch=v8plusa, -xarch=v8plusb
362 * Same as -Av8plus{,a,b} -32, for compatibility with Sun's
363 * assembler.
364 * -xarch=v9, -xarch=v9a, -xarch=v9b
365 * Same as -Av9{,a,b} -64, for compatibility with Sun's
366 * assembler.
368 * Select the architecture and possibly the file format.
369 * Instructions or features not supported by the selected
370 * architecture cause fatal errors.
372 * The default is to start at v6, and bump the architecture up
373 * whenever an instruction is seen at a higher level. In 32 bit
374 * environments, v9 is not bumped up to, the user must pass
375 * -Av8plus{,a,b}.
377 * If -bump is specified, a warning is printing when bumping to
378 * higher levels.
380 * If an architecture is specified, all instructions must match
381 * that architecture. Any higher level instructions are flagged
382 * as errors. Note that in the 32 bit environment specifying
383 * -Av8plus does not automatically create a v8plus object file, a
384 * v9 insn must be seen.
386 * If both an architecture and -bump are specified, the
387 * architecture starts at the specified level, but bumps are
388 * warnings. Note that we can't set `current_architecture' to
389 * the requested level in this case: in the 32 bit environment,
390 * we still must avoid creating v8plus object files unless v9
391 * insns are seen.
393 * Note:
394 * Bumping between incompatible architectures is always an
395 * error. For example, from sparclite to v9.
398 #ifdef OBJ_ELF
399 const char *md_shortopts = "A:K:VQ:sq";
400 #else
401 #ifdef OBJ_AOUT
402 const char *md_shortopts = "A:k";
403 #else
404 const char *md_shortopts = "A:";
405 #endif
406 #endif
407 struct option md_longopts[] = {
408 #define OPTION_BUMP (OPTION_MD_BASE)
409 {"bump", no_argument, NULL, OPTION_BUMP},
410 #define OPTION_SPARC (OPTION_MD_BASE + 1)
411 {"sparc", no_argument, NULL, OPTION_SPARC},
412 #define OPTION_XARCH (OPTION_MD_BASE + 2)
413 {"xarch", required_argument, NULL, OPTION_XARCH},
414 #ifdef OBJ_ELF
415 #define OPTION_32 (OPTION_MD_BASE + 3)
416 {"32", no_argument, NULL, OPTION_32},
417 #define OPTION_64 (OPTION_MD_BASE + 4)
418 {"64", no_argument, NULL, OPTION_64},
419 #define OPTION_TSO (OPTION_MD_BASE + 5)
420 {"TSO", no_argument, NULL, OPTION_TSO},
421 #define OPTION_PSO (OPTION_MD_BASE + 6)
422 {"PSO", no_argument, NULL, OPTION_PSO},
423 #define OPTION_RMO (OPTION_MD_BASE + 7)
424 {"RMO", no_argument, NULL, OPTION_RMO},
425 #endif
426 #ifdef SPARC_BIENDIAN
427 #define OPTION_LITTLE_ENDIAN (OPTION_MD_BASE + 8)
428 {"EL", no_argument, NULL, OPTION_LITTLE_ENDIAN},
429 #define OPTION_BIG_ENDIAN (OPTION_MD_BASE + 9)
430 {"EB", no_argument, NULL, OPTION_BIG_ENDIAN},
431 #endif
432 #define OPTION_ENFORCE_ALIGNED_DATA (OPTION_MD_BASE + 10)
433 {"enforce-aligned-data", no_argument, NULL, OPTION_ENFORCE_ALIGNED_DATA},
434 #define OPTION_LITTLE_ENDIAN_DATA (OPTION_MD_BASE + 11)
435 {"little-endian-data", no_argument, NULL, OPTION_LITTLE_ENDIAN_DATA},
436 #ifdef OBJ_ELF
437 #define OPTION_NO_UNDECLARED_REGS (OPTION_MD_BASE + 12)
438 {"no-undeclared-regs", no_argument, NULL, OPTION_NO_UNDECLARED_REGS},
439 #define OPTION_UNDECLARED_REGS (OPTION_MD_BASE + 13)
440 {"undeclared-regs", no_argument, NULL, OPTION_UNDECLARED_REGS},
441 #endif
442 #define OPTION_RELAX (OPTION_MD_BASE + 14)
443 {"relax", no_argument, NULL, OPTION_RELAX},
444 #define OPTION_NO_RELAX (OPTION_MD_BASE + 15)
445 {"no-relax", no_argument, NULL, OPTION_NO_RELAX},
446 {NULL, no_argument, NULL, 0}
449 size_t md_longopts_size = sizeof (md_longopts);
452 md_parse_option (c, arg)
453 int c;
454 char *arg;
456 /* We don't get a chance to initialize anything before we're called,
457 so handle that now. */
458 if (! default_init_p)
459 init_default_arch ();
461 switch (c)
463 case OPTION_BUMP:
464 warn_on_bump = 1;
465 warn_after_architecture = SPARC_OPCODE_ARCH_V6;
466 break;
468 case OPTION_XARCH:
469 #ifdef OBJ_ELF
470 if (strncmp (arg, "v9", 2) != 0)
471 md_parse_option (OPTION_32, NULL);
472 else
473 md_parse_option (OPTION_64, NULL);
474 #endif
475 /* Fall through. */
477 case 'A':
479 struct sparc_arch *sa;
480 enum sparc_opcode_arch_val opcode_arch;
482 sa = lookup_arch (arg);
483 if (sa == NULL
484 || ! sa->user_option_p)
486 if (c == OPTION_XARCH)
487 as_bad (_("invalid architecture -xarch=%s"), arg);
488 else
489 as_bad (_("invalid architecture -A%s"), arg);
490 return 0;
493 opcode_arch = sparc_opcode_lookup_arch (sa->opcode_arch);
494 if (opcode_arch == SPARC_OPCODE_ARCH_BAD)
495 as_fatal (_("Bad opcode table, broken assembler."));
497 max_architecture = opcode_arch;
498 architecture_requested = 1;
500 break;
502 case OPTION_SPARC:
503 /* Ignore -sparc, used by SunOS make default .s.o rule. */
504 break;
506 case OPTION_ENFORCE_ALIGNED_DATA:
507 enforce_aligned_data = 1;
508 break;
510 #ifdef SPARC_BIENDIAN
511 case OPTION_LITTLE_ENDIAN:
512 target_big_endian = 0;
513 if (default_arch_type != sparclet)
514 as_fatal ("This target does not support -EL");
515 break;
516 case OPTION_LITTLE_ENDIAN_DATA:
517 target_little_endian_data = 1;
518 target_big_endian = 0;
519 if (default_arch_type != sparc86x
520 && default_arch_type != v9)
521 as_fatal ("This target does not support --little-endian-data");
522 break;
523 case OPTION_BIG_ENDIAN:
524 target_big_endian = 1;
525 break;
526 #endif
528 #ifdef OBJ_AOUT
529 case 'k':
530 sparc_pic_code = 1;
531 break;
532 #endif
534 #ifdef OBJ_ELF
535 case OPTION_32:
536 case OPTION_64:
538 const char **list, **l;
540 sparc_arch_size = c == OPTION_32 ? 32 : 64;
541 list = bfd_target_list ();
542 for (l = list; *l != NULL; l++)
544 if (sparc_arch_size == 32)
546 if (strcmp (*l, "elf32-sparc") == 0)
547 break;
549 else
551 if (strcmp (*l, "elf64-sparc") == 0)
552 break;
555 if (*l == NULL)
556 as_fatal (_("No compiled in support for %d bit object file format"),
557 sparc_arch_size);
558 free (list);
560 break;
562 case OPTION_TSO:
563 sparc_memory_model = MM_TSO;
564 break;
566 case OPTION_PSO:
567 sparc_memory_model = MM_PSO;
568 break;
570 case OPTION_RMO:
571 sparc_memory_model = MM_RMO;
572 break;
574 case 'V':
575 print_version_id ();
576 break;
578 case 'Q':
579 /* Qy - do emit .comment
580 Qn - do not emit .comment. */
581 break;
583 case 's':
584 /* Use .stab instead of .stab.excl. */
585 break;
587 case 'q':
588 /* quick -- Native assembler does fewer checks. */
589 break;
591 case 'K':
592 if (strcmp (arg, "PIC") != 0)
593 as_warn (_("Unrecognized option following -K"));
594 else
595 sparc_pic_code = 1;
596 break;
598 case OPTION_NO_UNDECLARED_REGS:
599 no_undeclared_regs = 1;
600 break;
602 case OPTION_UNDECLARED_REGS:
603 no_undeclared_regs = 0;
604 break;
605 #endif
607 case OPTION_RELAX:
608 sparc_relax = 1;
609 break;
611 case OPTION_NO_RELAX:
612 sparc_relax = 0;
613 break;
615 default:
616 return 0;
619 return 1;
622 void
623 md_show_usage (stream)
624 FILE *stream;
626 const struct sparc_arch *arch;
627 int column;
629 /* We don't get a chance to initialize anything before we're called,
630 so handle that now. */
631 if (! default_init_p)
632 init_default_arch ();
634 fprintf (stream, _("SPARC options:\n"));
635 column = 0;
636 for (arch = &sparc_arch_table[0]; arch->name; arch++)
638 if (!arch->user_option_p)
639 continue;
640 if (arch != &sparc_arch_table[0])
641 fprintf (stream, " | ");
642 if (column + strlen (arch->name) > 70)
644 column = 0;
645 fputc ('\n', stream);
647 column += 5 + 2 + strlen (arch->name);
648 fprintf (stream, "-A%s", arch->name);
650 for (arch = &sparc_arch_table[0]; arch->name; arch++)
652 if (!arch->user_option_p)
653 continue;
654 fprintf (stream, " | ");
655 if (column + strlen (arch->name) > 65)
657 column = 0;
658 fputc ('\n', stream);
660 column += 5 + 7 + strlen (arch->name);
661 fprintf (stream, "-xarch=%s", arch->name);
663 fprintf (stream, _("\n\
664 specify variant of SPARC architecture\n\
665 -bump warn when assembler switches architectures\n\
666 -sparc ignored\n\
667 --enforce-aligned-data force .long, etc., to be aligned correctly\n\
668 -relax relax jumps and branches (default)\n\
669 -no-relax avoid changing any jumps and branches\n"));
670 #ifdef OBJ_AOUT
671 fprintf (stream, _("\
672 -k generate PIC\n"));
673 #endif
674 #ifdef OBJ_ELF
675 fprintf (stream, _("\
676 -32 create 32 bit object file\n\
677 -64 create 64 bit object file\n"));
678 fprintf (stream, _("\
679 [default is %d]\n"), default_arch_size);
680 fprintf (stream, _("\
681 -TSO use Total Store Ordering\n\
682 -PSO use Partial Store Ordering\n\
683 -RMO use Relaxed Memory Ordering\n"));
684 fprintf (stream, _("\
685 [default is %s]\n"), (default_arch_size == 64) ? "RMO" : "TSO");
686 fprintf (stream, _("\
687 -KPIC generate PIC\n\
688 -V print assembler version number\n\
689 -undeclared-regs ignore application global register usage without\n\
690 appropriate .register directive (default)\n\
691 -no-undeclared-regs force error on application global register usage\n\
692 without appropriate .register directive\n\
693 -q ignored\n\
694 -Qy, -Qn ignored\n\
695 -s ignored\n"));
696 #endif
697 #ifdef SPARC_BIENDIAN
698 fprintf (stream, _("\
699 -EL generate code for a little endian machine\n\
700 -EB generate code for a big endian machine\n\
701 --little-endian-data generate code for a machine having big endian\n\
702 instructions and little endian data.\n"));
703 #endif
706 /* Native operand size opcode translation. */
707 struct
709 char *name;
710 char *name32;
711 char *name64;
712 } native_op_table[] =
714 {"ldn", "ld", "ldx"},
715 {"ldna", "lda", "ldxa"},
716 {"stn", "st", "stx"},
717 {"stna", "sta", "stxa"},
718 {"slln", "sll", "sllx"},
719 {"srln", "srl", "srlx"},
720 {"sran", "sra", "srax"},
721 {"casn", "cas", "casx"},
722 {"casna", "casa", "casxa"},
723 {"clrn", "clr", "clrx"},
724 {NULL, NULL, NULL},
727 /* sparc64 privileged registers. */
729 struct priv_reg_entry
731 char *name;
732 int regnum;
735 struct priv_reg_entry priv_reg_table[] =
737 {"tpc", 0},
738 {"tnpc", 1},
739 {"tstate", 2},
740 {"tt", 3},
741 {"tick", 4},
742 {"tba", 5},
743 {"pstate", 6},
744 {"tl", 7},
745 {"pil", 8},
746 {"cwp", 9},
747 {"cansave", 10},
748 {"canrestore", 11},
749 {"cleanwin", 12},
750 {"otherwin", 13},
751 {"wstate", 14},
752 {"fq", 15},
753 {"ver", 31},
754 {"", -1}, /* End marker. */
757 /* v9a specific asrs. */
759 struct priv_reg_entry v9a_asr_table[] =
761 {"tick_cmpr", 23},
762 {"sys_tick_cmpr", 25},
763 {"sys_tick", 24},
764 {"softint", 22},
765 {"set_softint", 20},
766 {"pic", 17},
767 {"pcr", 16},
768 {"gsr", 19},
769 {"dcr", 18},
770 {"clear_softint", 21},
771 {"", -1}, /* End marker. */
774 static int
775 cmp_reg_entry (parg, qarg)
776 const PTR parg;
777 const PTR qarg;
779 const struct priv_reg_entry *p = (const struct priv_reg_entry *) parg;
780 const struct priv_reg_entry *q = (const struct priv_reg_entry *) qarg;
782 return strcmp (q->name, p->name);
785 /* This function is called once, at assembler startup time. It should
786 set up all the tables, etc. that the MD part of the assembler will
787 need. */
789 void
790 md_begin ()
792 register const char *retval = NULL;
793 int lose = 0;
794 register unsigned int i = 0;
796 /* We don't get a chance to initialize anything before md_parse_option
797 is called, and it may not be called, so handle default initialization
798 now if not already done. */
799 if (! default_init_p)
800 init_default_arch ();
802 sparc_cie_data_alignment = sparc_arch_size == 64 ? -8 : -4;
803 op_hash = hash_new ();
805 while (i < (unsigned int) sparc_num_opcodes)
807 const char *name = sparc_opcodes[i].name;
808 retval = hash_insert (op_hash, name, (PTR) &sparc_opcodes[i]);
809 if (retval != NULL)
811 as_bad (_("Internal error: can't hash `%s': %s\n"),
812 sparc_opcodes[i].name, retval);
813 lose = 1;
817 if (sparc_opcodes[i].match & sparc_opcodes[i].lose)
819 as_bad (_("Internal error: losing opcode: `%s' \"%s\"\n"),
820 sparc_opcodes[i].name, sparc_opcodes[i].args);
821 lose = 1;
823 ++i;
825 while (i < (unsigned int) sparc_num_opcodes
826 && !strcmp (sparc_opcodes[i].name, name));
829 for (i = 0; native_op_table[i].name; i++)
831 const struct sparc_opcode *insn;
832 char *name = ((sparc_arch_size == 32)
833 ? native_op_table[i].name32
834 : native_op_table[i].name64);
835 insn = (struct sparc_opcode *) hash_find (op_hash, name);
836 if (insn == NULL)
838 as_bad (_("Internal error: can't find opcode `%s' for `%s'\n"),
839 name, native_op_table[i].name);
840 lose = 1;
842 else
844 retval = hash_insert (op_hash, native_op_table[i].name, (PTR) insn);
845 if (retval != NULL)
847 as_bad (_("Internal error: can't hash `%s': %s\n"),
848 sparc_opcodes[i].name, retval);
849 lose = 1;
854 if (lose)
855 as_fatal (_("Broken assembler. No assembly attempted."));
857 qsort (priv_reg_table, sizeof (priv_reg_table) / sizeof (priv_reg_table[0]),
858 sizeof (priv_reg_table[0]), cmp_reg_entry);
860 /* If -bump, record the architecture level at which we start issuing
861 warnings. The behaviour is different depending upon whether an
862 architecture was explicitly specified. If it wasn't, we issue warnings
863 for all upwards bumps. If it was, we don't start issuing warnings until
864 we need to bump beyond the requested architecture or when we bump between
865 conflicting architectures. */
867 if (warn_on_bump
868 && architecture_requested)
870 /* `max_architecture' records the requested architecture.
871 Issue warnings if we go above it. */
872 warn_after_architecture = max_architecture;
874 /* Find the highest architecture level that doesn't conflict with
875 the requested one. */
876 for (max_architecture = SPARC_OPCODE_ARCH_MAX;
877 max_architecture > warn_after_architecture;
878 --max_architecture)
879 if (! SPARC_OPCODE_CONFLICT_P (max_architecture,
880 warn_after_architecture))
881 break;
885 /* Called after all assembly has been done. */
887 void
888 sparc_md_end ()
890 unsigned long mach = bfd_mach_sparc;
892 if (sparc_arch_size == 64)
893 switch (current_architecture)
895 case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v9a; break;
896 case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v9b; break;
897 default: mach = bfd_mach_sparc_v9; break;
899 else
900 switch (current_architecture)
902 case SPARC_OPCODE_ARCH_SPARCLET: mach = bfd_mach_sparc_sparclet; break;
903 case SPARC_OPCODE_ARCH_V9: mach = bfd_mach_sparc_v8plus; break;
904 case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v8plusa; break;
905 case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v8plusb; break;
906 /* The sparclite is treated like a normal sparc. Perhaps it shouldn't
907 be but for now it is (since that's the way it's always been
908 treated). */
909 default: break;
911 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, mach);
914 /* Return non-zero if VAL is in the range -(MAX+1) to MAX. */
916 static INLINE int
917 in_signed_range (val, max)
918 bfd_signed_vma val, max;
920 if (max <= 0)
921 abort ();
922 /* Sign-extend the value from the architecture word size, so that
923 0xffffffff is always considered -1 on sparc32. */
924 if (sparc_arch_size == 32)
926 bfd_signed_vma sign = (bfd_signed_vma) 1 << 31;
927 val = ((val & U0xffffffff) ^ sign) - sign;
929 if (val > max)
930 return 0;
931 if (val < ~max)
932 return 0;
933 return 1;
936 /* Return non-zero if VAL is in the range 0 to MAX. */
938 static INLINE int
939 in_unsigned_range (val, max)
940 bfd_vma val, max;
942 if (val > max)
943 return 0;
944 return 1;
947 /* Return non-zero if VAL is in the range -(MAX/2+1) to MAX.
948 (e.g. -15 to +31). */
950 static INLINE int
951 in_bitfield_range (val, max)
952 bfd_signed_vma val, max;
954 if (max <= 0)
955 abort ();
956 if (val > max)
957 return 0;
958 if (val < ~(max >> 1))
959 return 0;
960 return 1;
963 static int
964 sparc_ffs (mask)
965 unsigned int mask;
967 int i;
969 if (mask == 0)
970 return -1;
972 for (i = 0; (mask & 1) == 0; ++i)
973 mask >>= 1;
974 return i;
977 /* Implement big shift right. */
978 static bfd_vma
979 BSR (val, amount)
980 bfd_vma val;
981 int amount;
983 if (sizeof (bfd_vma) <= 4 && amount >= 32)
984 as_fatal (_("Support for 64-bit arithmetic not compiled in."));
985 return val >> amount;
988 /* For communication between sparc_ip and get_expression. */
989 static char *expr_end;
991 /* Values for `special_case'.
992 Instructions that require wierd handling because they're longer than
993 4 bytes. */
994 #define SPECIAL_CASE_NONE 0
995 #define SPECIAL_CASE_SET 1
996 #define SPECIAL_CASE_SETSW 2
997 #define SPECIAL_CASE_SETX 3
998 /* FIXME: sparc-opc.c doesn't have necessary "S" trigger to enable this. */
999 #define SPECIAL_CASE_FDIV 4
1001 /* Bit masks of various insns. */
1002 #define NOP_INSN 0x01000000
1003 #define OR_INSN 0x80100000
1004 #define XOR_INSN 0x80180000
1005 #define FMOVS_INSN 0x81A00020
1006 #define SETHI_INSN 0x01000000
1007 #define SLLX_INSN 0x81281000
1008 #define SRA_INSN 0x81380000
1010 /* The last instruction to be assembled. */
1011 static const struct sparc_opcode *last_insn;
1012 /* The assembled opcode of `last_insn'. */
1013 static unsigned long last_opcode;
1015 /* Handle the set and setuw synthetic instructions. */
1017 static void
1018 synthetize_setuw (insn)
1019 const struct sparc_opcode *insn;
1021 int need_hi22_p = 0;
1022 int rd = (the_insn.opcode & RD (~0)) >> 25;
1024 if (the_insn.exp.X_op == O_constant)
1026 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1028 if (sizeof (offsetT) > 4
1029 && (the_insn.exp.X_add_number < 0
1030 || the_insn.exp.X_add_number > (offsetT) U0xffffffff))
1031 as_warn (_("set: number not in 0..4294967295 range"));
1033 else
1035 if (sizeof (offsetT) > 4
1036 && (the_insn.exp.X_add_number < -(offsetT) U0x80000000
1037 || the_insn.exp.X_add_number > (offsetT) U0xffffffff))
1038 as_warn (_("set: number not in -2147483648..4294967295 range"));
1039 the_insn.exp.X_add_number = (int) the_insn.exp.X_add_number;
1043 /* See if operand is absolute and small; skip sethi if so. */
1044 if (the_insn.exp.X_op != O_constant
1045 || the_insn.exp.X_add_number >= (1 << 12)
1046 || the_insn.exp.X_add_number < -(1 << 12))
1048 the_insn.opcode = (SETHI_INSN | RD (rd)
1049 | ((the_insn.exp.X_add_number >> 10)
1050 & (the_insn.exp.X_op == O_constant
1051 ? 0x3fffff : 0)));
1052 the_insn.reloc = (the_insn.exp.X_op != O_constant
1053 ? BFD_RELOC_HI22 : BFD_RELOC_NONE);
1054 output_insn (insn, &the_insn);
1055 need_hi22_p = 1;
1058 /* See if operand has no low-order bits; skip OR if so. */
1059 if (the_insn.exp.X_op != O_constant
1060 || (need_hi22_p && (the_insn.exp.X_add_number & 0x3FF) != 0)
1061 || ! need_hi22_p)
1063 the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (rd) : 0)
1064 | RD (rd) | IMMED
1065 | (the_insn.exp.X_add_number
1066 & (the_insn.exp.X_op != O_constant
1067 ? 0 : need_hi22_p ? 0x3ff : 0x1fff)));
1068 the_insn.reloc = (the_insn.exp.X_op != O_constant
1069 ? BFD_RELOC_LO10 : BFD_RELOC_NONE);
1070 output_insn (insn, &the_insn);
1074 /* Handle the setsw synthetic instruction. */
1076 static void
1077 synthetize_setsw (insn)
1078 const struct sparc_opcode *insn;
1080 int low32, rd, opc;
1082 rd = (the_insn.opcode & RD (~0)) >> 25;
1084 if (the_insn.exp.X_op != O_constant)
1086 synthetize_setuw (insn);
1088 /* Need to sign extend it. */
1089 the_insn.opcode = (SRA_INSN | RS1 (rd) | RD (rd));
1090 the_insn.reloc = BFD_RELOC_NONE;
1091 output_insn (insn, &the_insn);
1092 return;
1095 if (sizeof (offsetT) > 4
1096 && (the_insn.exp.X_add_number < -(offsetT) U0x80000000
1097 || the_insn.exp.X_add_number > (offsetT) U0xffffffff))
1098 as_warn (_("setsw: number not in -2147483648..4294967295 range"));
1100 low32 = the_insn.exp.X_add_number;
1102 if (low32 >= 0)
1104 synthetize_setuw (insn);
1105 return;
1108 opc = OR_INSN;
1110 the_insn.reloc = BFD_RELOC_NONE;
1111 /* See if operand is absolute and small; skip sethi if so. */
1112 if (low32 < -(1 << 12))
1114 the_insn.opcode = (SETHI_INSN | RD (rd)
1115 | (((~the_insn.exp.X_add_number) >> 10) & 0x3fffff));
1116 output_insn (insn, &the_insn);
1117 low32 = 0x1c00 | (low32 & 0x3ff);
1118 opc = RS1 (rd) | XOR_INSN;
1121 the_insn.opcode = (opc | RD (rd) | IMMED
1122 | (low32 & 0x1fff));
1123 output_insn (insn, &the_insn);
1126 /* Handle the setsw synthetic instruction. */
1128 static void
1129 synthetize_setx (insn)
1130 const struct sparc_opcode *insn;
1132 int upper32, lower32;
1133 int tmpreg = (the_insn.opcode & RS1 (~0)) >> 14;
1134 int dstreg = (the_insn.opcode & RD (~0)) >> 25;
1135 int upper_dstreg;
1136 int need_hh22_p = 0, need_hm10_p = 0, need_hi22_p = 0, need_lo10_p = 0;
1137 int need_xor10_p = 0;
1139 #define SIGNEXT32(x) ((((x) & U0xffffffff) ^ U0x80000000) - U0x80000000)
1140 lower32 = SIGNEXT32 (the_insn.exp.X_add_number);
1141 upper32 = SIGNEXT32 (BSR (the_insn.exp.X_add_number, 32));
1142 #undef SIGNEXT32
1144 upper_dstreg = tmpreg;
1145 /* The tmp reg should not be the dst reg. */
1146 if (tmpreg == dstreg)
1147 as_warn (_("setx: temporary register same as destination register"));
1149 /* ??? Obviously there are other optimizations we can do
1150 (e.g. sethi+shift for 0x1f0000000) and perhaps we shouldn't be
1151 doing some of these. Later. If you do change things, try to
1152 change all of this to be table driven as well. */
1153 /* What to output depends on the number if it's constant.
1154 Compute that first, then output what we've decided upon. */
1155 if (the_insn.exp.X_op != O_constant)
1157 if (sparc_arch_size == 32)
1159 /* When arch size is 32, we want setx to be equivalent
1160 to setuw for anything but constants. */
1161 the_insn.exp.X_add_number &= 0xffffffff;
1162 synthetize_setuw (insn);
1163 return;
1165 need_hh22_p = need_hm10_p = need_hi22_p = need_lo10_p = 1;
1166 lower32 = 0;
1167 upper32 = 0;
1169 else
1171 /* Reset X_add_number, we've extracted it as upper32/lower32.
1172 Otherwise fixup_segment will complain about not being able to
1173 write an 8 byte number in a 4 byte field. */
1174 the_insn.exp.X_add_number = 0;
1176 /* Only need hh22 if `or' insn can't handle constant. */
1177 if (upper32 < -(1 << 12) || upper32 >= (1 << 12))
1178 need_hh22_p = 1;
1180 /* Does bottom part (after sethi) have bits? */
1181 if ((need_hh22_p && (upper32 & 0x3ff) != 0)
1182 /* No hh22, but does upper32 still have bits we can't set
1183 from lower32? */
1184 || (! need_hh22_p && upper32 != 0 && upper32 != -1))
1185 need_hm10_p = 1;
1187 /* If the lower half is all zero, we build the upper half directly
1188 into the dst reg. */
1189 if (lower32 != 0
1190 /* Need lower half if number is zero or 0xffffffff00000000. */
1191 || (! need_hh22_p && ! need_hm10_p))
1193 /* No need for sethi if `or' insn can handle constant. */
1194 if (lower32 < -(1 << 12) || lower32 >= (1 << 12)
1195 /* Note that we can't use a negative constant in the `or'
1196 insn unless the upper 32 bits are all ones. */
1197 || (lower32 < 0 && upper32 != -1)
1198 || (lower32 >= 0 && upper32 == -1))
1199 need_hi22_p = 1;
1201 if (need_hi22_p && upper32 == -1)
1202 need_xor10_p = 1;
1204 /* Does bottom part (after sethi) have bits? */
1205 else if ((need_hi22_p && (lower32 & 0x3ff) != 0)
1206 /* No sethi. */
1207 || (! need_hi22_p && (lower32 & 0x1fff) != 0)
1208 /* Need `or' if we didn't set anything else. */
1209 || (! need_hi22_p && ! need_hh22_p && ! need_hm10_p))
1210 need_lo10_p = 1;
1212 else
1213 /* Output directly to dst reg if lower 32 bits are all zero. */
1214 upper_dstreg = dstreg;
1217 if (!upper_dstreg && dstreg)
1218 as_warn (_("setx: illegal temporary register g0"));
1220 if (need_hh22_p)
1222 the_insn.opcode = (SETHI_INSN | RD (upper_dstreg)
1223 | ((upper32 >> 10) & 0x3fffff));
1224 the_insn.reloc = (the_insn.exp.X_op != O_constant
1225 ? BFD_RELOC_SPARC_HH22 : BFD_RELOC_NONE);
1226 output_insn (insn, &the_insn);
1229 if (need_hi22_p)
1231 the_insn.opcode = (SETHI_INSN | RD (dstreg)
1232 | (((need_xor10_p ? ~lower32 : lower32)
1233 >> 10) & 0x3fffff));
1234 the_insn.reloc = (the_insn.exp.X_op != O_constant
1235 ? BFD_RELOC_SPARC_LM22 : BFD_RELOC_NONE);
1236 output_insn (insn, &the_insn);
1239 if (need_hm10_p)
1241 the_insn.opcode = (OR_INSN
1242 | (need_hh22_p ? RS1 (upper_dstreg) : 0)
1243 | RD (upper_dstreg)
1244 | IMMED
1245 | (upper32 & (need_hh22_p ? 0x3ff : 0x1fff)));
1246 the_insn.reloc = (the_insn.exp.X_op != O_constant
1247 ? BFD_RELOC_SPARC_HM10 : BFD_RELOC_NONE);
1248 output_insn (insn, &the_insn);
1251 if (need_lo10_p)
1253 /* FIXME: One nice optimization to do here is to OR the low part
1254 with the highpart if hi22 isn't needed and the low part is
1255 positive. */
1256 the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (dstreg) : 0)
1257 | RD (dstreg)
1258 | IMMED
1259 | (lower32 & (need_hi22_p ? 0x3ff : 0x1fff)));
1260 the_insn.reloc = (the_insn.exp.X_op != O_constant
1261 ? BFD_RELOC_LO10 : BFD_RELOC_NONE);
1262 output_insn (insn, &the_insn);
1265 /* If we needed to build the upper part, shift it into place. */
1266 if (need_hh22_p || need_hm10_p)
1268 the_insn.opcode = (SLLX_INSN | RS1 (upper_dstreg) | RD (upper_dstreg)
1269 | IMMED | 32);
1270 the_insn.reloc = BFD_RELOC_NONE;
1271 output_insn (insn, &the_insn);
1274 /* To get -1 in upper32, we do sethi %hi(~x), r; xor r, -0x400 | x, r. */
1275 if (need_xor10_p)
1277 the_insn.opcode = (XOR_INSN | RS1 (dstreg) | RD (dstreg) | IMMED
1278 | 0x1c00 | (lower32 & 0x3ff));
1279 the_insn.reloc = BFD_RELOC_NONE;
1280 output_insn (insn, &the_insn);
1283 /* If we needed to build both upper and lower parts, OR them together. */
1284 else if ((need_hh22_p || need_hm10_p) && (need_hi22_p || need_lo10_p))
1286 the_insn.opcode = (OR_INSN | RS1 (dstreg) | RS2 (upper_dstreg)
1287 | RD (dstreg));
1288 the_insn.reloc = BFD_RELOC_NONE;
1289 output_insn (insn, &the_insn);
1293 /* Main entry point to assemble one instruction. */
1295 void
1296 md_assemble (str)
1297 char *str;
1299 const struct sparc_opcode *insn;
1300 int special_case;
1302 know (str);
1303 special_case = sparc_ip (str, &insn);
1304 if (insn == NULL)
1305 return;
1307 /* We warn about attempts to put a floating point branch in a delay slot,
1308 unless the delay slot has been annulled. */
1309 if (last_insn != NULL
1310 && (insn->flags & F_FBR) != 0
1311 && (last_insn->flags & F_DELAYED) != 0
1312 /* ??? This test isn't completely accurate. We assume anything with
1313 F_{UNBR,CONDBR,FBR} set is annullable. */
1314 && ((last_insn->flags & (F_UNBR | F_CONDBR | F_FBR)) == 0
1315 || (last_opcode & ANNUL) == 0))
1316 as_warn (_("FP branch in delay slot"));
1318 /* SPARC before v9 requires a nop instruction between a floating
1319 point instruction and a floating point branch. We insert one
1320 automatically, with a warning. */
1321 if (max_architecture < SPARC_OPCODE_ARCH_V9
1322 && last_insn != NULL
1323 && (insn->flags & F_FBR) != 0
1324 && (last_insn->flags & F_FLOAT) != 0)
1326 struct sparc_it nop_insn;
1328 nop_insn.opcode = NOP_INSN;
1329 nop_insn.reloc = BFD_RELOC_NONE;
1330 output_insn (insn, &nop_insn);
1331 as_warn (_("FP branch preceded by FP instruction; NOP inserted"));
1334 switch (special_case)
1336 case SPECIAL_CASE_NONE:
1337 /* Normal insn. */
1338 output_insn (insn, &the_insn);
1339 break;
1341 case SPECIAL_CASE_SETSW:
1342 synthetize_setsw (insn);
1343 break;
1345 case SPECIAL_CASE_SET:
1346 synthetize_setuw (insn);
1347 break;
1349 case SPECIAL_CASE_SETX:
1350 synthetize_setx (insn);
1351 break;
1353 case SPECIAL_CASE_FDIV:
1355 int rd = (the_insn.opcode >> 25) & 0x1f;
1357 output_insn (insn, &the_insn);
1359 /* According to information leaked from Sun, the "fdiv" instructions
1360 on early SPARC machines would produce incorrect results sometimes.
1361 The workaround is to add an fmovs of the destination register to
1362 itself just after the instruction. This was true on machines
1363 with Weitek 1165 float chips, such as the Sun-4/260 and /280. */
1364 assert (the_insn.reloc == BFD_RELOC_NONE);
1365 the_insn.opcode = FMOVS_INSN | rd | RD (rd);
1366 output_insn (insn, &the_insn);
1367 return;
1370 default:
1371 as_fatal (_("failed special case insn sanity check"));
1375 /* Subroutine of md_assemble to do the actual parsing. */
1377 static int
1378 sparc_ip (str, pinsn)
1379 char *str;
1380 const struct sparc_opcode **pinsn;
1382 char *error_message = "";
1383 char *s;
1384 const char *args;
1385 char c;
1386 const struct sparc_opcode *insn;
1387 char *argsStart;
1388 unsigned long opcode;
1389 unsigned int mask = 0;
1390 int match = 0;
1391 int comma = 0;
1392 int v9_arg_p;
1393 int special_case = SPECIAL_CASE_NONE;
1395 s = str;
1396 if (ISLOWER (*s))
1399 ++s;
1400 while (ISLOWER (*s) || ISDIGIT (*s));
1403 switch (*s)
1405 case '\0':
1406 break;
1408 case ',':
1409 comma = 1;
1410 /* Fall through. */
1412 case ' ':
1413 *s++ = '\0';
1414 break;
1416 default:
1417 as_bad (_("Unknown opcode: `%s'"), str);
1418 *pinsn = NULL;
1419 return special_case;
1421 insn = (struct sparc_opcode *) hash_find (op_hash, str);
1422 *pinsn = insn;
1423 if (insn == NULL)
1425 as_bad (_("Unknown opcode: `%s'"), str);
1426 return special_case;
1428 if (comma)
1430 *--s = ',';
1433 argsStart = s;
1434 for (;;)
1436 opcode = insn->match;
1437 memset (&the_insn, '\0', sizeof (the_insn));
1438 the_insn.reloc = BFD_RELOC_NONE;
1439 v9_arg_p = 0;
1441 /* Build the opcode, checking as we go to make sure that the
1442 operands match. */
1443 for (args = insn->args;; ++args)
1445 switch (*args)
1447 case 'K':
1449 int kmask = 0;
1451 /* Parse a series of masks. */
1452 if (*s == '#')
1454 while (*s == '#')
1456 int mask;
1458 if (! parse_keyword_arg (sparc_encode_membar, &s,
1459 &mask))
1461 error_message = _(": invalid membar mask name");
1462 goto error;
1464 kmask |= mask;
1465 while (*s == ' ')
1466 ++s;
1467 if (*s == '|' || *s == '+')
1468 ++s;
1469 while (*s == ' ')
1470 ++s;
1473 else
1475 if (! parse_const_expr_arg (&s, &kmask))
1477 error_message = _(": invalid membar mask expression");
1478 goto error;
1480 if (kmask < 0 || kmask > 127)
1482 error_message = _(": invalid membar mask number");
1483 goto error;
1487 opcode |= MEMBAR (kmask);
1488 continue;
1491 case '3':
1493 int smask = 0;
1495 if (! parse_const_expr_arg (&s, &smask))
1497 error_message = _(": invalid siam mode expression");
1498 goto error;
1500 if (smask < 0 || smask > 7)
1502 error_message = _(": invalid siam mode number");
1503 goto error;
1505 opcode |= smask;
1506 continue;
1509 case '*':
1511 int fcn = 0;
1513 /* Parse a prefetch function. */
1514 if (*s == '#')
1516 if (! parse_keyword_arg (sparc_encode_prefetch, &s, &fcn))
1518 error_message = _(": invalid prefetch function name");
1519 goto error;
1522 else
1524 if (! parse_const_expr_arg (&s, &fcn))
1526 error_message = _(": invalid prefetch function expression");
1527 goto error;
1529 if (fcn < 0 || fcn > 31)
1531 error_message = _(": invalid prefetch function number");
1532 goto error;
1535 opcode |= RD (fcn);
1536 continue;
1539 case '!':
1540 case '?':
1541 /* Parse a sparc64 privileged register. */
1542 if (*s == '%')
1544 struct priv_reg_entry *p = priv_reg_table;
1545 unsigned int len = 9999999; /* Init to make gcc happy. */
1547 s += 1;
1548 while (p->name[0] > s[0])
1549 p++;
1550 while (p->name[0] == s[0])
1552 len = strlen (p->name);
1553 if (strncmp (p->name, s, len) == 0)
1554 break;
1555 p++;
1557 if (p->name[0] != s[0])
1559 error_message = _(": unrecognizable privileged register");
1560 goto error;
1562 if (*args == '?')
1563 opcode |= (p->regnum << 14);
1564 else
1565 opcode |= (p->regnum << 25);
1566 s += len;
1567 continue;
1569 else
1571 error_message = _(": unrecognizable privileged register");
1572 goto error;
1575 case '_':
1576 case '/':
1577 /* Parse a v9a/v9b ancillary state register. */
1578 if (*s == '%')
1580 struct priv_reg_entry *p = v9a_asr_table;
1581 unsigned int len = 9999999; /* Init to make gcc happy. */
1583 s += 1;
1584 while (p->name[0] > s[0])
1585 p++;
1586 while (p->name[0] == s[0])
1588 len = strlen (p->name);
1589 if (strncmp (p->name, s, len) == 0)
1590 break;
1591 p++;
1593 if (p->name[0] != s[0])
1595 error_message = _(": unrecognizable v9a or v9b ancillary state register");
1596 goto error;
1598 if (*args == '/' && (p->regnum == 20 || p->regnum == 21))
1600 error_message = _(": rd on write only ancillary state register");
1601 goto error;
1603 if (p->regnum >= 24
1604 && (insn->architecture
1605 & SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A)))
1607 /* %sys_tick and %sys_tick_cmpr are v9bnotv9a */
1608 error_message = _(": unrecognizable v9a ancillary state register");
1609 goto error;
1611 if (*args == '/')
1612 opcode |= (p->regnum << 14);
1613 else
1614 opcode |= (p->regnum << 25);
1615 s += len;
1616 continue;
1618 else
1620 error_message = _(": unrecognizable v9a or v9b ancillary state register");
1621 goto error;
1624 case 'M':
1625 case 'm':
1626 if (strncmp (s, "%asr", 4) == 0)
1628 s += 4;
1630 if (ISDIGIT (*s))
1632 long num = 0;
1634 while (ISDIGIT (*s))
1636 num = num * 10 + *s - '0';
1637 ++s;
1640 if (current_architecture >= SPARC_OPCODE_ARCH_V9)
1642 if (num < 16 || 31 < num)
1644 error_message = _(": asr number must be between 16 and 31");
1645 goto error;
1648 else
1650 if (num < 0 || 31 < num)
1652 error_message = _(": asr number must be between 0 and 31");
1653 goto error;
1657 opcode |= (*args == 'M' ? RS1 (num) : RD (num));
1658 continue;
1660 else
1662 error_message = _(": expecting %asrN");
1663 goto error;
1665 } /* if %asr */
1666 break;
1668 case 'I':
1669 the_insn.reloc = BFD_RELOC_SPARC_11;
1670 goto immediate;
1672 case 'j':
1673 the_insn.reloc = BFD_RELOC_SPARC_10;
1674 goto immediate;
1676 case 'X':
1677 /* V8 systems don't understand BFD_RELOC_SPARC_5. */
1678 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1679 the_insn.reloc = BFD_RELOC_SPARC_5;
1680 else
1681 the_insn.reloc = BFD_RELOC_SPARC13;
1682 /* These fields are unsigned, but for upward compatibility,
1683 allow negative values as well. */
1684 goto immediate;
1686 case 'Y':
1687 /* V8 systems don't understand BFD_RELOC_SPARC_6. */
1688 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1689 the_insn.reloc = BFD_RELOC_SPARC_6;
1690 else
1691 the_insn.reloc = BFD_RELOC_SPARC13;
1692 /* These fields are unsigned, but for upward compatibility,
1693 allow negative values as well. */
1694 goto immediate;
1696 case 'k':
1697 the_insn.reloc = /* RELOC_WDISP2_14 */ BFD_RELOC_SPARC_WDISP16;
1698 the_insn.pcrel = 1;
1699 goto immediate;
1701 case 'G':
1702 the_insn.reloc = BFD_RELOC_SPARC_WDISP19;
1703 the_insn.pcrel = 1;
1704 goto immediate;
1706 case 'N':
1707 if (*s == 'p' && s[1] == 'n')
1709 s += 2;
1710 continue;
1712 break;
1714 case 'T':
1715 if (*s == 'p' && s[1] == 't')
1717 s += 2;
1718 continue;
1720 break;
1722 case 'z':
1723 if (*s == ' ')
1725 ++s;
1727 if (strncmp (s, "%icc", 4) == 0)
1729 s += 4;
1730 continue;
1732 break;
1734 case 'Z':
1735 if (*s == ' ')
1737 ++s;
1739 if (strncmp (s, "%xcc", 4) == 0)
1741 s += 4;
1742 continue;
1744 break;
1746 case '6':
1747 if (*s == ' ')
1749 ++s;
1751 if (strncmp (s, "%fcc0", 5) == 0)
1753 s += 5;
1754 continue;
1756 break;
1758 case '7':
1759 if (*s == ' ')
1761 ++s;
1763 if (strncmp (s, "%fcc1", 5) == 0)
1765 s += 5;
1766 continue;
1768 break;
1770 case '8':
1771 if (*s == ' ')
1773 ++s;
1775 if (strncmp (s, "%fcc2", 5) == 0)
1777 s += 5;
1778 continue;
1780 break;
1782 case '9':
1783 if (*s == ' ')
1785 ++s;
1787 if (strncmp (s, "%fcc3", 5) == 0)
1789 s += 5;
1790 continue;
1792 break;
1794 case 'P':
1795 if (strncmp (s, "%pc", 3) == 0)
1797 s += 3;
1798 continue;
1800 break;
1802 case 'W':
1803 if (strncmp (s, "%tick", 5) == 0)
1805 s += 5;
1806 continue;
1808 break;
1810 case '\0': /* End of args. */
1811 if (s[0] == ',' && s[1] == '%')
1813 static const struct tls_ops {
1814 /* The name as it appears in assembler. */
1815 char *name;
1816 /* strlen (name), precomputed for speed */
1817 int len;
1818 /* The reloc this pseudo-op translates to. */
1819 int reloc;
1820 /* 1 if call. */
1821 int call;
1822 } tls_ops[] = {
1823 { "tgd_add", 7, BFD_RELOC_SPARC_TLS_GD_ADD, 0 },
1824 { "tgd_call", 8, BFD_RELOC_SPARC_TLS_GD_CALL, 1 },
1825 { "tldm_add", 8, BFD_RELOC_SPARC_TLS_LDM_ADD, 0 },
1826 { "tldm_call", 9, BFD_RELOC_SPARC_TLS_LDM_CALL, 1 },
1827 { "tldo_add", 8, BFD_RELOC_SPARC_TLS_LDO_ADD, 0 },
1828 { "tie_ldx", 7, BFD_RELOC_SPARC_TLS_IE_LDX, 0 },
1829 { "tie_ld", 6, BFD_RELOC_SPARC_TLS_IE_LD, 0 },
1830 { "tie_add", 7, BFD_RELOC_SPARC_TLS_IE_ADD, 0 }
1832 const struct tls_ops *o;
1833 char *s1;
1834 int npar = 0;
1836 for (o = tls_ops; o->name; o++)
1837 if (strncmp (s + 2, o->name, o->len) == 0)
1838 break;
1839 if (o->name == NULL)
1840 break;
1842 if (s[o->len + 2] != '(')
1844 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name);
1845 return special_case;
1848 if (! o->call && the_insn.reloc != BFD_RELOC_NONE)
1850 as_bad (_("Illegal operands: %%%s cannot be used together with other relocs in the insn ()"),
1851 o->name);
1852 return special_case;
1855 if (o->call
1856 && (the_insn.reloc != BFD_RELOC_32_PCREL_S2
1857 || the_insn.exp.X_add_number != 0
1858 || the_insn.exp.X_add_symbol
1859 != symbol_find_or_make ("__tls_get_addr")))
1861 as_bad (_("Illegal operands: %%%s can be only used with call __tls_get_addr"),
1862 o->name);
1863 return special_case;
1866 the_insn.reloc = o->reloc;
1867 memset (&the_insn.exp, 0, sizeof (the_insn.exp));
1868 s += o->len + 3;
1870 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++)
1871 if (*s1 == '(')
1872 npar++;
1873 else if (*s1 == ')')
1875 if (!npar)
1876 break;
1877 npar--;
1880 if (*s1 != ')')
1882 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name);
1883 return special_case;
1886 *s1 = '\0';
1887 (void) get_expression (s);
1888 *s1 = ')';
1889 s = s1 + 1;
1891 if (*s == '\0')
1892 match = 1;
1893 break;
1895 case '+':
1896 if (*s == '+')
1898 ++s;
1899 continue;
1901 if (*s == '-')
1903 continue;
1905 break;
1907 case '[': /* These must match exactly. */
1908 case ']':
1909 case ',':
1910 case ' ':
1911 if (*s++ == *args)
1912 continue;
1913 break;
1915 case '#': /* Must be at least one digit. */
1916 if (ISDIGIT (*s++))
1918 while (ISDIGIT (*s))
1920 ++s;
1922 continue;
1924 break;
1926 case 'C': /* Coprocessor state register. */
1927 if (strncmp (s, "%csr", 4) == 0)
1929 s += 4;
1930 continue;
1932 break;
1934 case 'b': /* Next operand is a coprocessor register. */
1935 case 'c':
1936 case 'D':
1937 if (*s++ == '%' && *s++ == 'c' && ISDIGIT (*s))
1939 mask = *s++;
1940 if (ISDIGIT (*s))
1942 mask = 10 * (mask - '0') + (*s++ - '0');
1943 if (mask >= 32)
1945 break;
1948 else
1950 mask -= '0';
1952 switch (*args)
1955 case 'b':
1956 opcode |= mask << 14;
1957 continue;
1959 case 'c':
1960 opcode |= mask;
1961 continue;
1963 case 'D':
1964 opcode |= mask << 25;
1965 continue;
1968 break;
1970 case 'r': /* next operand must be a register */
1971 case 'O':
1972 case '1':
1973 case '2':
1974 case 'd':
1975 if (*s++ == '%')
1977 switch (c = *s++)
1980 case 'f': /* frame pointer */
1981 if (*s++ == 'p')
1983 mask = 0x1e;
1984 break;
1986 goto error;
1988 case 'g': /* global register */
1989 c = *s++;
1990 if (isoctal (c))
1992 mask = c - '0';
1993 break;
1995 goto error;
1997 case 'i': /* in register */
1998 c = *s++;
1999 if (isoctal (c))
2001 mask = c - '0' + 24;
2002 break;
2004 goto error;
2006 case 'l': /* local register */
2007 c = *s++;
2008 if (isoctal (c))
2010 mask = (c - '0' + 16);
2011 break;
2013 goto error;
2015 case 'o': /* out register */
2016 c = *s++;
2017 if (isoctal (c))
2019 mask = (c - '0' + 8);
2020 break;
2022 goto error;
2024 case 's': /* stack pointer */
2025 if (*s++ == 'p')
2027 mask = 0xe;
2028 break;
2030 goto error;
2032 case 'r': /* any register */
2033 if (!ISDIGIT ((c = *s++)))
2035 goto error;
2037 /* FALLTHROUGH */
2038 case '0':
2039 case '1':
2040 case '2':
2041 case '3':
2042 case '4':
2043 case '5':
2044 case '6':
2045 case '7':
2046 case '8':
2047 case '9':
2048 if (ISDIGIT (*s))
2050 if ((c = 10 * (c - '0') + (*s++ - '0')) >= 32)
2052 goto error;
2055 else
2057 c -= '0';
2059 mask = c;
2060 break;
2062 default:
2063 goto error;
2066 if ((mask & ~1) == 2 && sparc_arch_size == 64
2067 && no_undeclared_regs && ! globals[mask])
2068 as_bad (_("detected global register use not covered by .register pseudo-op"));
2070 /* Got the register, now figure out where
2071 it goes in the opcode. */
2072 switch (*args)
2074 case '1':
2075 opcode |= mask << 14;
2076 continue;
2078 case '2':
2079 opcode |= mask;
2080 continue;
2082 case 'd':
2083 opcode |= mask << 25;
2084 continue;
2086 case 'r':
2087 opcode |= (mask << 25) | (mask << 14);
2088 continue;
2090 case 'O':
2091 opcode |= (mask << 25) | (mask << 0);
2092 continue;
2095 break;
2097 case 'e': /* next operand is a floating point register */
2098 case 'v':
2099 case 'V':
2101 case 'f':
2102 case 'B':
2103 case 'R':
2105 case 'g':
2106 case 'H':
2107 case 'J':
2109 char format;
2111 if (*s++ == '%'
2112 && ((format = *s) == 'f')
2113 && ISDIGIT (*++s))
2115 for (mask = 0; ISDIGIT (*s); ++s)
2117 mask = 10 * mask + (*s - '0');
2118 } /* read the number */
2120 if ((*args == 'v'
2121 || *args == 'B'
2122 || *args == 'H')
2123 && (mask & 1))
2125 break;
2126 } /* register must be even numbered */
2128 if ((*args == 'V'
2129 || *args == 'R'
2130 || *args == 'J')
2131 && (mask & 3))
2133 break;
2134 } /* register must be multiple of 4 */
2136 if (mask >= 64)
2138 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
2139 error_message = _(": There are only 64 f registers; [0-63]");
2140 else
2141 error_message = _(": There are only 32 f registers; [0-31]");
2142 goto error;
2143 } /* on error */
2144 else if (mask >= 32)
2146 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
2148 if (*args == 'e' || *args == 'f' || *args == 'g')
2150 error_message
2151 = _(": There are only 32 single precision f registers; [0-31]");
2152 goto error;
2154 v9_arg_p = 1;
2155 mask -= 31; /* wrap high bit */
2157 else
2159 error_message = _(": There are only 32 f registers; [0-31]");
2160 goto error;
2164 else
2166 break;
2167 } /* if not an 'f' register. */
2169 switch (*args)
2171 case 'v':
2172 case 'V':
2173 case 'e':
2174 opcode |= RS1 (mask);
2175 continue;
2177 case 'f':
2178 case 'B':
2179 case 'R':
2180 opcode |= RS2 (mask);
2181 continue;
2183 case 'g':
2184 case 'H':
2185 case 'J':
2186 opcode |= RD (mask);
2187 continue;
2188 } /* Pack it in. */
2190 know (0);
2191 break;
2192 } /* float arg */
2194 case 'F':
2195 if (strncmp (s, "%fsr", 4) == 0)
2197 s += 4;
2198 continue;
2200 break;
2202 case '0': /* 64 bit immediate (set, setsw, setx insn) */
2203 the_insn.reloc = BFD_RELOC_NONE; /* reloc handled elsewhere */
2204 goto immediate;
2206 case 'l': /* 22 bit PC relative immediate */
2207 the_insn.reloc = BFD_RELOC_SPARC_WDISP22;
2208 the_insn.pcrel = 1;
2209 goto immediate;
2211 case 'L': /* 30 bit immediate */
2212 the_insn.reloc = BFD_RELOC_32_PCREL_S2;
2213 the_insn.pcrel = 1;
2214 goto immediate;
2216 case 'h':
2217 case 'n': /* 22 bit immediate */
2218 the_insn.reloc = BFD_RELOC_SPARC22;
2219 goto immediate;
2221 case 'i': /* 13 bit immediate */
2222 the_insn.reloc = BFD_RELOC_SPARC13;
2224 /* fallthrough */
2226 immediate:
2227 if (*s == ' ')
2228 s++;
2231 char *s1;
2232 char *op_arg = NULL;
2233 static expressionS op_exp;
2234 bfd_reloc_code_real_type old_reloc = the_insn.reloc;
2236 /* Check for %hi, etc. */
2237 if (*s == '%')
2239 static const struct ops {
2240 /* The name as it appears in assembler. */
2241 char *name;
2242 /* strlen (name), precomputed for speed */
2243 int len;
2244 /* The reloc this pseudo-op translates to. */
2245 int reloc;
2246 /* Non-zero if for v9 only. */
2247 int v9_p;
2248 /* Non-zero if can be used in pc-relative contexts. */
2249 int pcrel_p;/*FIXME:wip*/
2250 } ops[] = {
2251 /* hix/lox must appear before hi/lo so %hix won't be
2252 mistaken for %hi. */
2253 { "hix", 3, BFD_RELOC_SPARC_HIX22, 1, 0 },
2254 { "lox", 3, BFD_RELOC_SPARC_LOX10, 1, 0 },
2255 { "hi", 2, BFD_RELOC_HI22, 0, 1 },
2256 { "lo", 2, BFD_RELOC_LO10, 0, 1 },
2257 { "hh", 2, BFD_RELOC_SPARC_HH22, 1, 1 },
2258 { "hm", 2, BFD_RELOC_SPARC_HM10, 1, 1 },
2259 { "lm", 2, BFD_RELOC_SPARC_LM22, 1, 1 },
2260 { "h44", 3, BFD_RELOC_SPARC_H44, 1, 0 },
2261 { "m44", 3, BFD_RELOC_SPARC_M44, 1, 0 },
2262 { "l44", 3, BFD_RELOC_SPARC_L44, 1, 0 },
2263 { "uhi", 3, BFD_RELOC_SPARC_HH22, 1, 0 },
2264 { "ulo", 3, BFD_RELOC_SPARC_HM10, 1, 0 },
2265 { "tgd_hi22", 8, BFD_RELOC_SPARC_TLS_GD_HI22, 0, 0 },
2266 { "tgd_lo10", 8, BFD_RELOC_SPARC_TLS_GD_LO10, 0, 0 },
2267 { "tldm_hi22", 9, BFD_RELOC_SPARC_TLS_LDM_HI22, 0, 0 },
2268 { "tldm_lo10", 9, BFD_RELOC_SPARC_TLS_LDM_LO10, 0, 0 },
2269 { "tldo_hix22", 10, BFD_RELOC_SPARC_TLS_LDO_HIX22, 0,
2270 0 },
2271 { "tldo_lox10", 10, BFD_RELOC_SPARC_TLS_LDO_LOX10, 0,
2272 0 },
2273 { "tie_hi22", 8, BFD_RELOC_SPARC_TLS_IE_HI22, 0, 0 },
2274 { "tie_lo10", 8, BFD_RELOC_SPARC_TLS_IE_LO10, 0, 0 },
2275 { "tle_hix22", 9, BFD_RELOC_SPARC_TLS_LE_HIX22, 0, 0 },
2276 { "tle_lox10", 9, BFD_RELOC_SPARC_TLS_LE_LOX10, 0, 0 },
2277 { NULL, 0, 0, 0, 0 }
2279 const struct ops *o;
2281 for (o = ops; o->name; o++)
2282 if (strncmp (s + 1, o->name, o->len) == 0)
2283 break;
2284 if (o->name == NULL)
2285 break;
2287 if (s[o->len + 1] != '(')
2289 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name);
2290 return special_case;
2293 op_arg = o->name;
2294 the_insn.reloc = o->reloc;
2295 s += o->len + 2;
2296 v9_arg_p = o->v9_p;
2299 /* Note that if the get_expression() fails, we will still
2300 have created U entries in the symbol table for the
2301 'symbols' in the input string. Try not to create U
2302 symbols for registers, etc. */
2304 /* This stuff checks to see if the expression ends in
2305 +%reg. If it does, it removes the register from
2306 the expression, and re-sets 's' to point to the
2307 right place. */
2309 if (op_arg)
2311 int npar = 0;
2313 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++)
2314 if (*s1 == '(')
2315 npar++;
2316 else if (*s1 == ')')
2318 if (!npar)
2319 break;
2320 npar--;
2323 if (*s1 != ')')
2325 as_bad (_("Illegal operands: %%%s requires arguments in ()"), op_arg);
2326 return special_case;
2329 *s1 = '\0';
2330 (void) get_expression (s);
2331 *s1 = ')';
2332 s = s1 + 1;
2333 if (*s == ',' || *s == ']' || !*s)
2334 continue;
2335 if (*s != '+' && *s != '-')
2337 as_bad (_("Illegal operands: Can't do arithmetics other than + and - involving %%%s()"), op_arg);
2338 return special_case;
2340 *s1 = '0';
2341 s = s1;
2342 op_exp = the_insn.exp;
2343 memset (&the_insn.exp, 0, sizeof (the_insn.exp));
2346 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++)
2349 if (s1 != s && ISDIGIT (s1[-1]))
2351 if (s1[-2] == '%' && s1[-3] == '+')
2352 s1 -= 3;
2353 else if (strchr ("goli0123456789", s1[-2]) && s1[-3] == '%' && s1[-4] == '+')
2354 s1 -= 4;
2355 else
2356 s1 = NULL;
2357 if (s1)
2359 *s1 = '\0';
2360 if (op_arg && s1 == s + 1)
2361 the_insn.exp.X_op = O_absent;
2362 else
2363 (void) get_expression (s);
2364 *s1 = '+';
2365 if (op_arg)
2366 *s = ')';
2367 s = s1;
2370 else
2371 s1 = NULL;
2373 if (!s1)
2375 (void) get_expression (s);
2376 if (op_arg)
2377 *s = ')';
2378 s = expr_end;
2381 if (op_arg)
2383 the_insn.exp2 = the_insn.exp;
2384 the_insn.exp = op_exp;
2385 if (the_insn.exp2.X_op == O_absent)
2386 the_insn.exp2.X_op = O_illegal;
2387 else if (the_insn.exp.X_op == O_absent)
2389 the_insn.exp = the_insn.exp2;
2390 the_insn.exp2.X_op = O_illegal;
2392 else if (the_insn.exp.X_op == O_constant)
2394 valueT val = the_insn.exp.X_add_number;
2395 switch (the_insn.reloc)
2397 default:
2398 break;
2400 case BFD_RELOC_SPARC_HH22:
2401 val = BSR (val, 32);
2402 /* Fall through. */
2404 case BFD_RELOC_SPARC_LM22:
2405 case BFD_RELOC_HI22:
2406 val = (val >> 10) & 0x3fffff;
2407 break;
2409 case BFD_RELOC_SPARC_HM10:
2410 val = BSR (val, 32);
2411 /* Fall through. */
2413 case BFD_RELOC_LO10:
2414 val &= 0x3ff;
2415 break;
2417 case BFD_RELOC_SPARC_H44:
2418 val >>= 22;
2419 val &= 0x3fffff;
2420 break;
2422 case BFD_RELOC_SPARC_M44:
2423 val >>= 12;
2424 val &= 0x3ff;
2425 break;
2427 case BFD_RELOC_SPARC_L44:
2428 val &= 0xfff;
2429 break;
2431 case BFD_RELOC_SPARC_HIX22:
2432 val = ~val;
2433 val = (val >> 10) & 0x3fffff;
2434 break;
2436 case BFD_RELOC_SPARC_LOX10:
2437 val = (val & 0x3ff) | 0x1c00;
2438 break;
2440 the_insn.exp = the_insn.exp2;
2441 the_insn.exp.X_add_number += val;
2442 the_insn.exp2.X_op = O_illegal;
2443 the_insn.reloc = old_reloc;
2445 else if (the_insn.exp2.X_op != O_constant)
2447 as_bad (_("Illegal operands: Can't add non-constant expression to %%%s()"), op_arg);
2448 return special_case;
2450 else
2452 if (old_reloc != BFD_RELOC_SPARC13
2453 || the_insn.reloc != BFD_RELOC_LO10
2454 || sparc_arch_size != 64
2455 || sparc_pic_code)
2457 as_bad (_("Illegal operands: Can't do arithmetics involving %%%s() of a relocatable symbol"), op_arg);
2458 return special_case;
2460 the_insn.reloc = BFD_RELOC_SPARC_OLO10;
2464 /* Check for constants that don't require emitting a reloc. */
2465 if (the_insn.exp.X_op == O_constant
2466 && the_insn.exp.X_add_symbol == 0
2467 && the_insn.exp.X_op_symbol == 0)
2469 /* For pc-relative call instructions, we reject
2470 constants to get better code. */
2471 if (the_insn.pcrel
2472 && the_insn.reloc == BFD_RELOC_32_PCREL_S2
2473 && in_signed_range (the_insn.exp.X_add_number, 0x3fff))
2475 error_message = _(": PC-relative operand can't be a constant");
2476 goto error;
2479 if (the_insn.reloc >= BFD_RELOC_SPARC_TLS_GD_HI22
2480 && the_insn.reloc <= BFD_RELOC_SPARC_TLS_TPOFF64)
2482 error_message = _(": TLS operand can't be a constant");
2483 goto error;
2486 /* Constants that won't fit are checked in md_apply_fix
2487 and bfd_install_relocation.
2488 ??? It would be preferable to install the constants
2489 into the insn here and save having to create a fixS
2490 for each one. There already exists code to handle
2491 all the various cases (e.g. in md_apply_fix and
2492 bfd_install_relocation) so duplicating all that code
2493 here isn't right. */
2496 continue;
2498 case 'a':
2499 if (*s++ == 'a')
2501 opcode |= ANNUL;
2502 continue;
2504 break;
2506 case 'A':
2508 int asi = 0;
2510 /* Parse an asi. */
2511 if (*s == '#')
2513 if (! parse_keyword_arg (sparc_encode_asi, &s, &asi))
2515 error_message = _(": invalid ASI name");
2516 goto error;
2519 else
2521 if (! parse_const_expr_arg (&s, &asi))
2523 error_message = _(": invalid ASI expression");
2524 goto error;
2526 if (asi < 0 || asi > 255)
2528 error_message = _(": invalid ASI number");
2529 goto error;
2532 opcode |= ASI (asi);
2533 continue;
2534 } /* Alternate space. */
2536 case 'p':
2537 if (strncmp (s, "%psr", 4) == 0)
2539 s += 4;
2540 continue;
2542 break;
2544 case 'q': /* Floating point queue. */
2545 if (strncmp (s, "%fq", 3) == 0)
2547 s += 3;
2548 continue;
2550 break;
2552 case 'Q': /* Coprocessor queue. */
2553 if (strncmp (s, "%cq", 3) == 0)
2555 s += 3;
2556 continue;
2558 break;
2560 case 'S':
2561 if (strcmp (str, "set") == 0
2562 || strcmp (str, "setuw") == 0)
2564 special_case = SPECIAL_CASE_SET;
2565 continue;
2567 else if (strcmp (str, "setsw") == 0)
2569 special_case = SPECIAL_CASE_SETSW;
2570 continue;
2572 else if (strcmp (str, "setx") == 0)
2574 special_case = SPECIAL_CASE_SETX;
2575 continue;
2577 else if (strncmp (str, "fdiv", 4) == 0)
2579 special_case = SPECIAL_CASE_FDIV;
2580 continue;
2582 break;
2584 case 'o':
2585 if (strncmp (s, "%asi", 4) != 0)
2586 break;
2587 s += 4;
2588 continue;
2590 case 's':
2591 if (strncmp (s, "%fprs", 5) != 0)
2592 break;
2593 s += 5;
2594 continue;
2596 case 'E':
2597 if (strncmp (s, "%ccr", 4) != 0)
2598 break;
2599 s += 4;
2600 continue;
2602 case 't':
2603 if (strncmp (s, "%tbr", 4) != 0)
2604 break;
2605 s += 4;
2606 continue;
2608 case 'w':
2609 if (strncmp (s, "%wim", 4) != 0)
2610 break;
2611 s += 4;
2612 continue;
2614 case 'x':
2616 char *push = input_line_pointer;
2617 expressionS e;
2619 input_line_pointer = s;
2620 expression (&e);
2621 if (e.X_op == O_constant)
2623 int n = e.X_add_number;
2624 if (n != e.X_add_number || (n & ~0x1ff) != 0)
2625 as_bad (_("OPF immediate operand out of range (0-0x1ff)"));
2626 else
2627 opcode |= e.X_add_number << 5;
2629 else
2630 as_bad (_("non-immediate OPF operand, ignored"));
2631 s = input_line_pointer;
2632 input_line_pointer = push;
2633 continue;
2636 case 'y':
2637 if (strncmp (s, "%y", 2) != 0)
2638 break;
2639 s += 2;
2640 continue;
2642 case 'u':
2643 case 'U':
2645 /* Parse a sparclet cpreg. */
2646 int cpreg;
2647 if (! parse_keyword_arg (sparc_encode_sparclet_cpreg, &s, &cpreg))
2649 error_message = _(": invalid cpreg name");
2650 goto error;
2652 opcode |= (*args == 'U' ? RS1 (cpreg) : RD (cpreg));
2653 continue;
2656 default:
2657 as_fatal (_("failed sanity check."));
2658 } /* switch on arg code. */
2660 /* Break out of for() loop. */
2661 break;
2662 } /* For each arg that we expect. */
2664 error:
2665 if (match == 0)
2667 /* Args don't match. */
2668 if (&insn[1] - sparc_opcodes < sparc_num_opcodes
2669 && (insn->name == insn[1].name
2670 || !strcmp (insn->name, insn[1].name)))
2672 ++insn;
2673 s = argsStart;
2674 continue;
2676 else
2678 as_bad (_("Illegal operands%s"), error_message);
2679 return special_case;
2682 else
2684 /* We have a match. Now see if the architecture is OK. */
2685 int needed_arch_mask = insn->architecture;
2687 if (v9_arg_p)
2689 needed_arch_mask &=
2690 ~(SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9) - 1);
2691 if (! needed_arch_mask)
2692 needed_arch_mask =
2693 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9);
2696 if (needed_arch_mask
2697 & SPARC_OPCODE_SUPPORTED (current_architecture))
2698 /* OK. */
2700 /* Can we bump up the architecture? */
2701 else if (needed_arch_mask
2702 & SPARC_OPCODE_SUPPORTED (max_architecture))
2704 enum sparc_opcode_arch_val needed_architecture =
2705 sparc_ffs (SPARC_OPCODE_SUPPORTED (max_architecture)
2706 & needed_arch_mask);
2708 assert (needed_architecture <= SPARC_OPCODE_ARCH_MAX);
2709 if (warn_on_bump
2710 && needed_architecture > warn_after_architecture)
2712 as_warn (_("architecture bumped from \"%s\" to \"%s\" on \"%s\""),
2713 sparc_opcode_archs[current_architecture].name,
2714 sparc_opcode_archs[needed_architecture].name,
2715 str);
2716 warn_after_architecture = needed_architecture;
2718 current_architecture = needed_architecture;
2720 /* Conflict. */
2721 /* ??? This seems to be a bit fragile. What if the next entry in
2722 the opcode table is the one we want and it is supported?
2723 It is possible to arrange the table today so that this can't
2724 happen but what about tomorrow? */
2725 else
2727 int arch, printed_one_p = 0;
2728 char *p;
2729 char required_archs[SPARC_OPCODE_ARCH_MAX * 16];
2731 /* Create a list of the architectures that support the insn. */
2732 needed_arch_mask &= ~SPARC_OPCODE_SUPPORTED (max_architecture);
2733 p = required_archs;
2734 arch = sparc_ffs (needed_arch_mask);
2735 while ((1 << arch) <= needed_arch_mask)
2737 if ((1 << arch) & needed_arch_mask)
2739 if (printed_one_p)
2740 *p++ = '|';
2741 strcpy (p, sparc_opcode_archs[arch].name);
2742 p += strlen (p);
2743 printed_one_p = 1;
2745 ++arch;
2748 as_bad (_("Architecture mismatch on \"%s\"."), str);
2749 as_tsktsk (_(" (Requires %s; requested architecture is %s.)"),
2750 required_archs,
2751 sparc_opcode_archs[max_architecture].name);
2752 return special_case;
2754 } /* If no match. */
2756 break;
2757 } /* Forever looking for a match. */
2759 the_insn.opcode = opcode;
2760 return special_case;
2763 /* Parse an argument that can be expressed as a keyword.
2764 (eg: #StoreStore or %ccfr).
2765 The result is a boolean indicating success.
2766 If successful, INPUT_POINTER is updated. */
2768 static int
2769 parse_keyword_arg (lookup_fn, input_pointerP, valueP)
2770 int (*lookup_fn) PARAMS ((const char *));
2771 char **input_pointerP;
2772 int *valueP;
2774 int value;
2775 char c, *p, *q;
2777 p = *input_pointerP;
2778 for (q = p + (*p == '#' || *p == '%');
2779 ISALNUM (*q) || *q == '_';
2780 ++q)
2781 continue;
2782 c = *q;
2783 *q = 0;
2784 value = (*lookup_fn) (p);
2785 *q = c;
2786 if (value == -1)
2787 return 0;
2788 *valueP = value;
2789 *input_pointerP = q;
2790 return 1;
2793 /* Parse an argument that is a constant expression.
2794 The result is a boolean indicating success. */
2796 static int
2797 parse_const_expr_arg (input_pointerP, valueP)
2798 char **input_pointerP;
2799 int *valueP;
2801 char *save = input_line_pointer;
2802 expressionS exp;
2804 input_line_pointer = *input_pointerP;
2805 /* The next expression may be something other than a constant
2806 (say if we're not processing the right variant of the insn).
2807 Don't call expression unless we're sure it will succeed as it will
2808 signal an error (which we want to defer until later). */
2809 /* FIXME: It might be better to define md_operand and have it recognize
2810 things like %asi, etc. but continuing that route through to the end
2811 is a lot of work. */
2812 if (*input_line_pointer == '%')
2814 input_line_pointer = save;
2815 return 0;
2817 expression (&exp);
2818 *input_pointerP = input_line_pointer;
2819 input_line_pointer = save;
2820 if (exp.X_op != O_constant)
2821 return 0;
2822 *valueP = exp.X_add_number;
2823 return 1;
2826 /* Subroutine of sparc_ip to parse an expression. */
2828 static int
2829 get_expression (str)
2830 char *str;
2832 char *save_in;
2833 segT seg;
2835 save_in = input_line_pointer;
2836 input_line_pointer = str;
2837 seg = expression (&the_insn.exp);
2838 if (seg != absolute_section
2839 && seg != text_section
2840 && seg != data_section
2841 && seg != bss_section
2842 && seg != undefined_section)
2844 the_insn.error = _("bad segment");
2845 expr_end = input_line_pointer;
2846 input_line_pointer = save_in;
2847 return 1;
2849 expr_end = input_line_pointer;
2850 input_line_pointer = save_in;
2851 return 0;
2854 /* Subroutine of md_assemble to output one insn. */
2856 static void
2857 output_insn (insn, the_insn)
2858 const struct sparc_opcode *insn;
2859 struct sparc_it *the_insn;
2861 char *toP = frag_more (4);
2863 /* Put out the opcode. */
2864 if (INSN_BIG_ENDIAN)
2865 number_to_chars_bigendian (toP, (valueT) the_insn->opcode, 4);
2866 else
2867 number_to_chars_littleendian (toP, (valueT) the_insn->opcode, 4);
2869 /* Put out the symbol-dependent stuff. */
2870 if (the_insn->reloc != BFD_RELOC_NONE)
2872 fixS *fixP = fix_new_exp (frag_now, /* Which frag. */
2873 (toP - frag_now->fr_literal), /* Where. */
2874 4, /* Size. */
2875 &the_insn->exp,
2876 the_insn->pcrel,
2877 the_insn->reloc);
2878 /* Turn off overflow checking in fixup_segment. We'll do our
2879 own overflow checking in md_apply_fix. This is necessary because
2880 the insn size is 4 and fixup_segment will signal an overflow for
2881 large 8 byte quantities. */
2882 fixP->fx_no_overflow = 1;
2883 if (the_insn->reloc == BFD_RELOC_SPARC_OLO10)
2884 fixP->tc_fix_data = the_insn->exp2.X_add_number;
2887 last_insn = insn;
2888 last_opcode = the_insn->opcode;
2890 #ifdef OBJ_ELF
2891 dwarf2_emit_insn (4);
2892 #endif
2895 /* This is identical to the md_atof in m68k.c. I think this is right,
2896 but I'm not sure.
2898 Turn a string in input_line_pointer into a floating point constant
2899 of type TYPE, and store the appropriate bytes in *LITP. The number
2900 of LITTLENUMS emitted is stored in *SIZEP. An error message is
2901 returned, or NULL on OK. */
2903 /* Equal to MAX_PRECISION in atof-ieee.c. */
2904 #define MAX_LITTLENUMS 6
2906 char *
2907 md_atof (type, litP, sizeP)
2908 char type;
2909 char *litP;
2910 int *sizeP;
2912 int i, prec;
2913 LITTLENUM_TYPE words[MAX_LITTLENUMS];
2914 char *t;
2916 switch (type)
2918 case 'f':
2919 case 'F':
2920 case 's':
2921 case 'S':
2922 prec = 2;
2923 break;
2925 case 'd':
2926 case 'D':
2927 case 'r':
2928 case 'R':
2929 prec = 4;
2930 break;
2932 case 'x':
2933 case 'X':
2934 prec = 6;
2935 break;
2937 case 'p':
2938 case 'P':
2939 prec = 6;
2940 break;
2942 default:
2943 *sizeP = 0;
2944 return _("Bad call to MD_ATOF()");
2947 t = atof_ieee (input_line_pointer, type, words);
2948 if (t)
2949 input_line_pointer = t;
2950 *sizeP = prec * sizeof (LITTLENUM_TYPE);
2952 if (target_big_endian)
2954 for (i = 0; i < prec; i++)
2956 md_number_to_chars (litP, (valueT) words[i],
2957 sizeof (LITTLENUM_TYPE));
2958 litP += sizeof (LITTLENUM_TYPE);
2961 else
2963 for (i = prec - 1; i >= 0; i--)
2965 md_number_to_chars (litP, (valueT) words[i],
2966 sizeof (LITTLENUM_TYPE));
2967 litP += sizeof (LITTLENUM_TYPE);
2971 return 0;
2974 /* Write a value out to the object file, using the appropriate
2975 endianness. */
2977 void
2978 md_number_to_chars (buf, val, n)
2979 char *buf;
2980 valueT val;
2981 int n;
2983 if (target_big_endian)
2984 number_to_chars_bigendian (buf, val, n);
2985 else if (target_little_endian_data
2986 && ((n == 4 || n == 2) && ~now_seg->flags & SEC_ALLOC))
2987 /* Output debug words, which are not in allocated sections, as big
2988 endian. */
2989 number_to_chars_bigendian (buf, val, n);
2990 else if (target_little_endian_data || ! target_big_endian)
2991 number_to_chars_littleendian (buf, val, n);
2994 /* Apply a fixS to the frags, now that we know the value it ought to
2995 hold. */
2997 void
2998 md_apply_fix (fixP, valP, segment)
2999 fixS *fixP;
3000 valueT *valP;
3001 segT segment ATTRIBUTE_UNUSED;
3003 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
3004 offsetT val = * (offsetT *) valP;
3005 long insn;
3007 assert (fixP->fx_r_type < BFD_RELOC_UNUSED);
3009 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
3011 #ifdef OBJ_ELF
3012 /* SPARC ELF relocations don't use an addend in the data field. */
3013 if (fixP->fx_addsy != NULL)
3015 switch (fixP->fx_r_type)
3017 case BFD_RELOC_SPARC_TLS_GD_HI22:
3018 case BFD_RELOC_SPARC_TLS_GD_LO10:
3019 case BFD_RELOC_SPARC_TLS_GD_ADD:
3020 case BFD_RELOC_SPARC_TLS_GD_CALL:
3021 case BFD_RELOC_SPARC_TLS_LDM_HI22:
3022 case BFD_RELOC_SPARC_TLS_LDM_LO10:
3023 case BFD_RELOC_SPARC_TLS_LDM_ADD:
3024 case BFD_RELOC_SPARC_TLS_LDM_CALL:
3025 case BFD_RELOC_SPARC_TLS_LDO_HIX22:
3026 case BFD_RELOC_SPARC_TLS_LDO_LOX10:
3027 case BFD_RELOC_SPARC_TLS_LDO_ADD:
3028 case BFD_RELOC_SPARC_TLS_IE_HI22:
3029 case BFD_RELOC_SPARC_TLS_IE_LO10:
3030 case BFD_RELOC_SPARC_TLS_IE_LD:
3031 case BFD_RELOC_SPARC_TLS_IE_LDX:
3032 case BFD_RELOC_SPARC_TLS_IE_ADD:
3033 case BFD_RELOC_SPARC_TLS_LE_HIX22:
3034 case BFD_RELOC_SPARC_TLS_LE_LOX10:
3035 case BFD_RELOC_SPARC_TLS_DTPMOD32:
3036 case BFD_RELOC_SPARC_TLS_DTPMOD64:
3037 case BFD_RELOC_SPARC_TLS_DTPOFF32:
3038 case BFD_RELOC_SPARC_TLS_DTPOFF64:
3039 case BFD_RELOC_SPARC_TLS_TPOFF32:
3040 case BFD_RELOC_SPARC_TLS_TPOFF64:
3041 S_SET_THREAD_LOCAL (fixP->fx_addsy);
3043 default:
3044 break;
3047 return;
3049 #endif
3051 /* This is a hack. There should be a better way to
3052 handle this. Probably in terms of howto fields, once
3053 we can look at these fixups in terms of howtos. */
3054 if (fixP->fx_r_type == BFD_RELOC_32_PCREL_S2 && fixP->fx_addsy)
3055 val += fixP->fx_where + fixP->fx_frag->fr_address;
3057 #ifdef OBJ_AOUT
3058 /* FIXME: More ridiculous gas reloc hacking. If we are going to
3059 generate a reloc, then we just want to let the reloc addend set
3060 the value. We do not want to also stuff the addend into the
3061 object file. Including the addend in the object file works when
3062 doing a static link, because the linker will ignore the object
3063 file contents. However, the dynamic linker does not ignore the
3064 object file contents. */
3065 if (fixP->fx_addsy != NULL
3066 && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2)
3067 val = 0;
3069 /* When generating PIC code, we do not want an addend for a reloc
3070 against a local symbol. We adjust fx_addnumber to cancel out the
3071 value already included in val, and to also cancel out the
3072 adjustment which bfd_install_relocation will create. */
3073 if (sparc_pic_code
3074 && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2
3075 && fixP->fx_addsy != NULL
3076 && ! S_IS_COMMON (fixP->fx_addsy)
3077 && symbol_section_p (fixP->fx_addsy))
3078 fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy);
3080 /* When generating PIC code, we need to fiddle to get
3081 bfd_install_relocation to do the right thing for a PC relative
3082 reloc against a local symbol which we are going to keep. */
3083 if (sparc_pic_code
3084 && fixP->fx_r_type == BFD_RELOC_32_PCREL_S2
3085 && fixP->fx_addsy != NULL
3086 && (S_IS_EXTERNAL (fixP->fx_addsy)
3087 || S_IS_WEAK (fixP->fx_addsy))
3088 && S_IS_DEFINED (fixP->fx_addsy)
3089 && ! S_IS_COMMON (fixP->fx_addsy))
3091 val = 0;
3092 fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy);
3094 #endif
3096 /* If this is a data relocation, just output VAL. */
3098 if (fixP->fx_r_type == BFD_RELOC_16
3099 || fixP->fx_r_type == BFD_RELOC_SPARC_UA16)
3101 md_number_to_chars (buf, val, 2);
3103 else if (fixP->fx_r_type == BFD_RELOC_32
3104 || fixP->fx_r_type == BFD_RELOC_SPARC_UA32
3105 || fixP->fx_r_type == BFD_RELOC_SPARC_REV32)
3107 md_number_to_chars (buf, val, 4);
3109 else if (fixP->fx_r_type == BFD_RELOC_64
3110 || fixP->fx_r_type == BFD_RELOC_SPARC_UA64)
3112 md_number_to_chars (buf, val, 8);
3114 else if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3115 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3117 fixP->fx_done = 0;
3118 return;
3120 else
3122 /* It's a relocation against an instruction. */
3124 if (INSN_BIG_ENDIAN)
3125 insn = bfd_getb32 ((unsigned char *) buf);
3126 else
3127 insn = bfd_getl32 ((unsigned char *) buf);
3129 switch (fixP->fx_r_type)
3131 case BFD_RELOC_32_PCREL_S2:
3132 val = val >> 2;
3133 /* FIXME: This increment-by-one deserves a comment of why it's
3134 being done! */
3135 if (! sparc_pic_code
3136 || fixP->fx_addsy == NULL
3137 || symbol_section_p (fixP->fx_addsy))
3138 ++val;
3140 insn |= val & 0x3fffffff;
3142 /* See if we have a delay slot. */
3143 if (sparc_relax && fixP->fx_where + 8 <= fixP->fx_frag->fr_fix)
3145 #define G0 0
3146 #define O7 15
3147 #define XCC (2 << 20)
3148 #define COND(x) (((x)&0xf)<<25)
3149 #define CONDA COND(0x8)
3150 #define INSN_BPA (F2(0,1) | CONDA | BPRED | XCC)
3151 #define INSN_BA (F2(0,2) | CONDA)
3152 #define INSN_OR F3(2, 0x2, 0)
3153 #define INSN_NOP F2(0,4)
3155 long delay;
3157 /* If the instruction is a call with either:
3158 restore
3159 arithmetic instruction with rd == %o7
3160 where rs1 != %o7 and rs2 if it is register != %o7
3161 then we can optimize if the call destination is near
3162 by changing the call into a branch always. */
3163 if (INSN_BIG_ENDIAN)
3164 delay = bfd_getb32 ((unsigned char *) buf + 4);
3165 else
3166 delay = bfd_getl32 ((unsigned char *) buf + 4);
3167 if ((insn & OP (~0)) != OP (1) || (delay & OP (~0)) != OP (2))
3168 break;
3169 if ((delay & OP3 (~0)) != OP3 (0x3d) /* Restore. */
3170 && ((delay & OP3 (0x28)) != 0 /* Arithmetic. */
3171 || ((delay & RD (~0)) != RD (O7))))
3172 break;
3173 if ((delay & RS1 (~0)) == RS1 (O7)
3174 || ((delay & F3I (~0)) == 0
3175 && (delay & RS2 (~0)) == RS2 (O7)))
3176 break;
3177 /* Ensure the branch will fit into simm22. */
3178 if ((val & 0x3fe00000)
3179 && (val & 0x3fe00000) != 0x3fe00000)
3180 break;
3181 /* Check if the arch is v9 and branch will fit
3182 into simm19. */
3183 if (((val & 0x3c0000) == 0
3184 || (val & 0x3c0000) == 0x3c0000)
3185 && (sparc_arch_size == 64
3186 || current_architecture >= SPARC_OPCODE_ARCH_V9))
3187 /* ba,pt %xcc */
3188 insn = INSN_BPA | (val & 0x7ffff);
3189 else
3190 /* ba */
3191 insn = INSN_BA | (val & 0x3fffff);
3192 if (fixP->fx_where >= 4
3193 && ((delay & (0xffffffff ^ RS1 (~0)))
3194 == (INSN_OR | RD (O7) | RS2 (G0))))
3196 long setter;
3197 int reg;
3199 if (INSN_BIG_ENDIAN)
3200 setter = bfd_getb32 ((unsigned char *) buf - 4);
3201 else
3202 setter = bfd_getl32 ((unsigned char *) buf - 4);
3203 if ((setter & (0xffffffff ^ RD (~0)))
3204 != (INSN_OR | RS1 (O7) | RS2 (G0)))
3205 break;
3206 /* The sequence was
3207 or %o7, %g0, %rN
3208 call foo
3209 or %rN, %g0, %o7
3211 If call foo was replaced with ba, replace
3212 or %rN, %g0, %o7 with nop. */
3213 reg = (delay & RS1 (~0)) >> 14;
3214 if (reg != ((setter & RD (~0)) >> 25)
3215 || reg == G0 || reg == O7)
3216 break;
3218 if (INSN_BIG_ENDIAN)
3219 bfd_putb32 (INSN_NOP, (unsigned char *) buf + 4);
3220 else
3221 bfd_putl32 (INSN_NOP, (unsigned char *) buf + 4);
3224 break;
3226 case BFD_RELOC_SPARC_11:
3227 if (! in_signed_range (val, 0x7ff))
3228 as_bad_where (fixP->fx_file, fixP->fx_line,
3229 _("relocation overflow"));
3230 insn |= val & 0x7ff;
3231 break;
3233 case BFD_RELOC_SPARC_10:
3234 if (! in_signed_range (val, 0x3ff))
3235 as_bad_where (fixP->fx_file, fixP->fx_line,
3236 _("relocation overflow"));
3237 insn |= val & 0x3ff;
3238 break;
3240 case BFD_RELOC_SPARC_7:
3241 if (! in_bitfield_range (val, 0x7f))
3242 as_bad_where (fixP->fx_file, fixP->fx_line,
3243 _("relocation overflow"));
3244 insn |= val & 0x7f;
3245 break;
3247 case BFD_RELOC_SPARC_6:
3248 if (! in_bitfield_range (val, 0x3f))
3249 as_bad_where (fixP->fx_file, fixP->fx_line,
3250 _("relocation overflow"));
3251 insn |= val & 0x3f;
3252 break;
3254 case BFD_RELOC_SPARC_5:
3255 if (! in_bitfield_range (val, 0x1f))
3256 as_bad_where (fixP->fx_file, fixP->fx_line,
3257 _("relocation overflow"));
3258 insn |= val & 0x1f;
3259 break;
3261 case BFD_RELOC_SPARC_WDISP16:
3262 /* FIXME: simplify. */
3263 if (((val > 0) && (val & ~0x3fffc))
3264 || ((val < 0) && (~(val - 1) & ~0x3fffc)))
3265 as_bad_where (fixP->fx_file, fixP->fx_line,
3266 _("relocation overflow"));
3267 /* FIXME: The +1 deserves a comment. */
3268 val = (val >> 2) + 1;
3269 insn |= ((val & 0xc000) << 6) | (val & 0x3fff);
3270 break;
3272 case BFD_RELOC_SPARC_WDISP19:
3273 /* FIXME: simplify. */
3274 if (((val > 0) && (val & ~0x1ffffc))
3275 || ((val < 0) && (~(val - 1) & ~0x1ffffc)))
3276 as_bad_where (fixP->fx_file, fixP->fx_line,
3277 _("relocation overflow"));
3278 /* FIXME: The +1 deserves a comment. */
3279 val = (val >> 2) + 1;
3280 insn |= val & 0x7ffff;
3281 break;
3283 case BFD_RELOC_SPARC_HH22:
3284 val = BSR (val, 32);
3285 /* Fall through. */
3287 case BFD_RELOC_SPARC_LM22:
3288 case BFD_RELOC_HI22:
3289 if (!fixP->fx_addsy)
3290 insn |= (val >> 10) & 0x3fffff;
3291 else
3292 /* FIXME: Need comment explaining why we do this. */
3293 insn &= ~0xffff;
3294 break;
3296 case BFD_RELOC_SPARC22:
3297 if (val & ~0x003fffff)
3298 as_bad_where (fixP->fx_file, fixP->fx_line,
3299 _("relocation overflow"));
3300 insn |= (val & 0x3fffff);
3301 break;
3303 case BFD_RELOC_SPARC_HM10:
3304 val = BSR (val, 32);
3305 /* Fall through. */
3307 case BFD_RELOC_LO10:
3308 if (!fixP->fx_addsy)
3309 insn |= val & 0x3ff;
3310 else
3311 /* FIXME: Need comment explaining why we do this. */
3312 insn &= ~0xff;
3313 break;
3315 case BFD_RELOC_SPARC_OLO10:
3316 val &= 0x3ff;
3317 val += fixP->tc_fix_data;
3318 /* Fall through. */
3320 case BFD_RELOC_SPARC13:
3321 if (! in_signed_range (val, 0x1fff))
3322 as_bad_where (fixP->fx_file, fixP->fx_line,
3323 _("relocation overflow"));
3324 insn |= val & 0x1fff;
3325 break;
3327 case BFD_RELOC_SPARC_WDISP22:
3328 val = (val >> 2) + 1;
3329 /* Fall through. */
3330 case BFD_RELOC_SPARC_BASE22:
3331 insn |= val & 0x3fffff;
3332 break;
3334 case BFD_RELOC_SPARC_H44:
3335 if (!fixP->fx_addsy)
3337 bfd_vma tval = val;
3338 tval >>= 22;
3339 insn |= tval & 0x3fffff;
3341 break;
3343 case BFD_RELOC_SPARC_M44:
3344 if (!fixP->fx_addsy)
3345 insn |= (val >> 12) & 0x3ff;
3346 break;
3348 case BFD_RELOC_SPARC_L44:
3349 if (!fixP->fx_addsy)
3350 insn |= val & 0xfff;
3351 break;
3353 case BFD_RELOC_SPARC_HIX22:
3354 if (!fixP->fx_addsy)
3356 val ^= ~(offsetT) 0;
3357 insn |= (val >> 10) & 0x3fffff;
3359 break;
3361 case BFD_RELOC_SPARC_LOX10:
3362 if (!fixP->fx_addsy)
3363 insn |= 0x1c00 | (val & 0x3ff);
3364 break;
3366 case BFD_RELOC_NONE:
3367 default:
3368 as_bad_where (fixP->fx_file, fixP->fx_line,
3369 _("bad or unhandled relocation type: 0x%02x"),
3370 fixP->fx_r_type);
3371 break;
3374 if (INSN_BIG_ENDIAN)
3375 bfd_putb32 (insn, (unsigned char *) buf);
3376 else
3377 bfd_putl32 (insn, (unsigned char *) buf);
3380 /* Are we finished with this relocation now? */
3381 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
3382 fixP->fx_done = 1;
3385 /* Translate internal representation of relocation info to BFD target
3386 format. */
3388 arelent **
3389 tc_gen_reloc (section, fixp)
3390 asection *section ATTRIBUTE_UNUSED;
3391 fixS *fixp;
3393 static arelent *relocs[3];
3394 arelent *reloc;
3395 bfd_reloc_code_real_type code;
3397 relocs[0] = reloc = (arelent *) xmalloc (sizeof (arelent));
3398 relocs[1] = NULL;
3400 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
3401 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
3402 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
3404 switch (fixp->fx_r_type)
3406 case BFD_RELOC_16:
3407 case BFD_RELOC_32:
3408 case BFD_RELOC_HI22:
3409 case BFD_RELOC_LO10:
3410 case BFD_RELOC_32_PCREL_S2:
3411 case BFD_RELOC_SPARC13:
3412 case BFD_RELOC_SPARC22:
3413 case BFD_RELOC_SPARC_BASE13:
3414 case BFD_RELOC_SPARC_WDISP16:
3415 case BFD_RELOC_SPARC_WDISP19:
3416 case BFD_RELOC_SPARC_WDISP22:
3417 case BFD_RELOC_64:
3418 case BFD_RELOC_SPARC_5:
3419 case BFD_RELOC_SPARC_6:
3420 case BFD_RELOC_SPARC_7:
3421 case BFD_RELOC_SPARC_10:
3422 case BFD_RELOC_SPARC_11:
3423 case BFD_RELOC_SPARC_HH22:
3424 case BFD_RELOC_SPARC_HM10:
3425 case BFD_RELOC_SPARC_LM22:
3426 case BFD_RELOC_SPARC_PC_HH22:
3427 case BFD_RELOC_SPARC_PC_HM10:
3428 case BFD_RELOC_SPARC_PC_LM22:
3429 case BFD_RELOC_SPARC_H44:
3430 case BFD_RELOC_SPARC_M44:
3431 case BFD_RELOC_SPARC_L44:
3432 case BFD_RELOC_SPARC_HIX22:
3433 case BFD_RELOC_SPARC_LOX10:
3434 case BFD_RELOC_SPARC_REV32:
3435 case BFD_RELOC_SPARC_OLO10:
3436 case BFD_RELOC_SPARC_UA16:
3437 case BFD_RELOC_SPARC_UA32:
3438 case BFD_RELOC_SPARC_UA64:
3439 case BFD_RELOC_8_PCREL:
3440 case BFD_RELOC_16_PCREL:
3441 case BFD_RELOC_32_PCREL:
3442 case BFD_RELOC_64_PCREL:
3443 case BFD_RELOC_SPARC_PLT32:
3444 case BFD_RELOC_SPARC_PLT64:
3445 case BFD_RELOC_VTABLE_ENTRY:
3446 case BFD_RELOC_VTABLE_INHERIT:
3447 case BFD_RELOC_SPARC_TLS_GD_HI22:
3448 case BFD_RELOC_SPARC_TLS_GD_LO10:
3449 case BFD_RELOC_SPARC_TLS_GD_ADD:
3450 case BFD_RELOC_SPARC_TLS_GD_CALL:
3451 case BFD_RELOC_SPARC_TLS_LDM_HI22:
3452 case BFD_RELOC_SPARC_TLS_LDM_LO10:
3453 case BFD_RELOC_SPARC_TLS_LDM_ADD:
3454 case BFD_RELOC_SPARC_TLS_LDM_CALL:
3455 case BFD_RELOC_SPARC_TLS_LDO_HIX22:
3456 case BFD_RELOC_SPARC_TLS_LDO_LOX10:
3457 case BFD_RELOC_SPARC_TLS_LDO_ADD:
3458 case BFD_RELOC_SPARC_TLS_IE_HI22:
3459 case BFD_RELOC_SPARC_TLS_IE_LO10:
3460 case BFD_RELOC_SPARC_TLS_IE_LD:
3461 case BFD_RELOC_SPARC_TLS_IE_LDX:
3462 case BFD_RELOC_SPARC_TLS_IE_ADD:
3463 case BFD_RELOC_SPARC_TLS_LE_HIX22:
3464 case BFD_RELOC_SPARC_TLS_LE_LOX10:
3465 case BFD_RELOC_SPARC_TLS_DTPOFF32:
3466 case BFD_RELOC_SPARC_TLS_DTPOFF64:
3467 code = fixp->fx_r_type;
3468 break;
3469 default:
3470 abort ();
3471 return NULL;
3474 #if defined (OBJ_ELF) || defined (OBJ_AOUT)
3475 /* If we are generating PIC code, we need to generate a different
3476 set of relocs. */
3478 #ifdef OBJ_ELF
3479 #define GOT_NAME "_GLOBAL_OFFSET_TABLE_"
3480 #else
3481 #define GOT_NAME "__GLOBAL_OFFSET_TABLE_"
3482 #endif
3484 /* This code must be parallel to the OBJ_ELF tc_fix_adjustable. */
3486 if (sparc_pic_code)
3488 switch (code)
3490 case BFD_RELOC_32_PCREL_S2:
3491 if (generic_force_reloc (fixp))
3492 code = BFD_RELOC_SPARC_WPLT30;
3493 break;
3494 case BFD_RELOC_HI22:
3495 if (fixp->fx_addsy != NULL
3496 && strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0)
3497 code = BFD_RELOC_SPARC_PC22;
3498 else
3499 code = BFD_RELOC_SPARC_GOT22;
3500 break;
3501 case BFD_RELOC_LO10:
3502 if (fixp->fx_addsy != NULL
3503 && strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0)
3504 code = BFD_RELOC_SPARC_PC10;
3505 else
3506 code = BFD_RELOC_SPARC_GOT10;
3507 break;
3508 case BFD_RELOC_SPARC13:
3509 code = BFD_RELOC_SPARC_GOT13;
3510 break;
3511 default:
3512 break;
3515 #endif /* defined (OBJ_ELF) || defined (OBJ_AOUT) */
3517 if (code == BFD_RELOC_SPARC_OLO10)
3518 reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO10);
3519 else
3520 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
3521 if (reloc->howto == 0)
3523 as_bad_where (fixp->fx_file, fixp->fx_line,
3524 _("internal error: can't export reloc type %d (`%s')"),
3525 fixp->fx_r_type, bfd_get_reloc_code_name (code));
3526 xfree (reloc);
3527 relocs[0] = NULL;
3528 return relocs;
3531 /* @@ Why fx_addnumber sometimes and fx_offset other times? */
3532 #ifdef OBJ_AOUT
3534 if (reloc->howto->pc_relative == 0
3535 || code == BFD_RELOC_SPARC_PC10
3536 || code == BFD_RELOC_SPARC_PC22)
3537 reloc->addend = fixp->fx_addnumber;
3538 else if (sparc_pic_code
3539 && fixp->fx_r_type == BFD_RELOC_32_PCREL_S2
3540 && fixp->fx_addsy != NULL
3541 && (S_IS_EXTERNAL (fixp->fx_addsy)
3542 || S_IS_WEAK (fixp->fx_addsy))
3543 && S_IS_DEFINED (fixp->fx_addsy)
3544 && ! S_IS_COMMON (fixp->fx_addsy))
3545 reloc->addend = fixp->fx_addnumber;
3546 else
3547 reloc->addend = fixp->fx_offset - reloc->address;
3549 #else /* elf or coff */
3551 if (code != BFD_RELOC_32_PCREL_S2
3552 && code != BFD_RELOC_SPARC_WDISP22
3553 && code != BFD_RELOC_SPARC_WDISP16
3554 && code != BFD_RELOC_SPARC_WDISP19
3555 && code != BFD_RELOC_SPARC_WPLT30
3556 && code != BFD_RELOC_SPARC_TLS_GD_CALL
3557 && code != BFD_RELOC_SPARC_TLS_LDM_CALL)
3558 reloc->addend = fixp->fx_addnumber;
3559 else if (symbol_section_p (fixp->fx_addsy))
3560 reloc->addend = (section->vma
3561 + fixp->fx_addnumber
3562 + md_pcrel_from (fixp));
3563 else
3564 reloc->addend = fixp->fx_offset;
3565 #endif
3567 /* We expand R_SPARC_OLO10 to R_SPARC_LO10 and R_SPARC_13
3568 on the same location. */
3569 if (code == BFD_RELOC_SPARC_OLO10)
3571 relocs[1] = reloc = (arelent *) xmalloc (sizeof (arelent));
3572 relocs[2] = NULL;
3574 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
3575 *reloc->sym_ptr_ptr
3576 = symbol_get_bfdsym (section_symbol (absolute_section));
3577 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
3578 reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_SPARC13);
3579 reloc->addend = fixp->tc_fix_data;
3582 return relocs;
3585 /* We have no need to default values of symbols. */
3587 symbolS *
3588 md_undefined_symbol (name)
3589 char *name ATTRIBUTE_UNUSED;
3591 return 0;
3594 /* Round up a section size to the appropriate boundary. */
3596 valueT
3597 md_section_align (segment, size)
3598 segT segment ATTRIBUTE_UNUSED;
3599 valueT size;
3601 #ifndef OBJ_ELF
3602 /* This is not right for ELF; a.out wants it, and COFF will force
3603 the alignment anyways. */
3604 valueT align = ((valueT) 1
3605 << (valueT) bfd_get_section_alignment (stdoutput, segment));
3606 valueT newsize;
3608 /* Turn alignment value into a mask. */
3609 align--;
3610 newsize = (size + align) & ~align;
3611 return newsize;
3612 #else
3613 return size;
3614 #endif
3617 /* Exactly what point is a PC-relative offset relative TO?
3618 On the sparc, they're relative to the address of the offset, plus
3619 its size. This gets us to the following instruction.
3620 (??? Is this right? FIXME-SOON) */
3621 long
3622 md_pcrel_from (fixP)
3623 fixS *fixP;
3625 long ret;
3627 ret = fixP->fx_where + fixP->fx_frag->fr_address;
3628 if (! sparc_pic_code
3629 || fixP->fx_addsy == NULL
3630 || symbol_section_p (fixP->fx_addsy))
3631 ret += fixP->fx_size;
3632 return ret;
3635 /* Return log2 (VALUE), or -1 if VALUE is not an exact positive power
3636 of two. */
3638 static int
3639 mylog2 (value)
3640 int value;
3642 int shift;
3644 if (value <= 0)
3645 return -1;
3647 for (shift = 0; (value & 1) == 0; value >>= 1)
3648 ++shift;
3650 return (value == 1) ? shift : -1;
3653 /* Sort of like s_lcomm. */
3655 #ifndef OBJ_ELF
3656 static int max_alignment = 15;
3657 #endif
3659 static void
3660 s_reserve (ignore)
3661 int ignore ATTRIBUTE_UNUSED;
3663 char *name;
3664 char *p;
3665 char c;
3666 int align;
3667 int size;
3668 int temp;
3669 symbolS *symbolP;
3671 name = input_line_pointer;
3672 c = get_symbol_end ();
3673 p = input_line_pointer;
3674 *p = c;
3675 SKIP_WHITESPACE ();
3677 if (*input_line_pointer != ',')
3679 as_bad (_("Expected comma after name"));
3680 ignore_rest_of_line ();
3681 return;
3684 ++input_line_pointer;
3686 if ((size = get_absolute_expression ()) < 0)
3688 as_bad (_("BSS length (%d.) <0! Ignored."), size);
3689 ignore_rest_of_line ();
3690 return;
3691 } /* Bad length. */
3693 *p = 0;
3694 symbolP = symbol_find_or_make (name);
3695 *p = c;
3697 if (strncmp (input_line_pointer, ",\"bss\"", 6) != 0
3698 && strncmp (input_line_pointer, ",\".bss\"", 7) != 0)
3700 as_bad (_("bad .reserve segment -- expected BSS segment"));
3701 return;
3704 if (input_line_pointer[2] == '.')
3705 input_line_pointer += 7;
3706 else
3707 input_line_pointer += 6;
3708 SKIP_WHITESPACE ();
3710 if (*input_line_pointer == ',')
3712 ++input_line_pointer;
3714 SKIP_WHITESPACE ();
3715 if (*input_line_pointer == '\n')
3717 as_bad (_("missing alignment"));
3718 ignore_rest_of_line ();
3719 return;
3722 align = (int) get_absolute_expression ();
3724 #ifndef OBJ_ELF
3725 if (align > max_alignment)
3727 align = max_alignment;
3728 as_warn (_("alignment too large; assuming %d"), align);
3730 #endif
3732 if (align < 0)
3734 as_bad (_("negative alignment"));
3735 ignore_rest_of_line ();
3736 return;
3739 if (align != 0)
3741 temp = mylog2 (align);
3742 if (temp < 0)
3744 as_bad (_("alignment not a power of 2"));
3745 ignore_rest_of_line ();
3746 return;
3749 align = temp;
3752 record_alignment (bss_section, align);
3754 else
3755 align = 0;
3757 if (!S_IS_DEFINED (symbolP)
3758 #ifdef OBJ_AOUT
3759 && S_GET_OTHER (symbolP) == 0
3760 && S_GET_DESC (symbolP) == 0
3761 #endif
3764 if (! need_pass_2)
3766 char *pfrag;
3767 segT current_seg = now_seg;
3768 subsegT current_subseg = now_subseg;
3770 /* Switch to bss. */
3771 subseg_set (bss_section, 1);
3773 if (align)
3774 /* Do alignment. */
3775 frag_align (align, 0, 0);
3777 /* Detach from old frag. */
3778 if (S_GET_SEGMENT (symbolP) == bss_section)
3779 symbol_get_frag (symbolP)->fr_symbol = NULL;
3781 symbol_set_frag (symbolP, frag_now);
3782 pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP,
3783 (offsetT) size, (char *) 0);
3784 *pfrag = 0;
3786 S_SET_SEGMENT (symbolP, bss_section);
3788 subseg_set (current_seg, current_subseg);
3790 #ifdef OBJ_ELF
3791 S_SET_SIZE (symbolP, size);
3792 #endif
3795 else
3797 as_warn ("Ignoring attempt to re-define symbol %s",
3798 S_GET_NAME (symbolP));
3799 } /* if not redefining. */
3801 demand_empty_rest_of_line ();
3804 static void
3805 s_common (ignore)
3806 int ignore ATTRIBUTE_UNUSED;
3808 char *name;
3809 char c;
3810 char *p;
3811 offsetT temp, size;
3812 symbolS *symbolP;
3814 name = input_line_pointer;
3815 c = get_symbol_end ();
3816 /* Just after name is now '\0'. */
3817 p = input_line_pointer;
3818 *p = c;
3819 SKIP_WHITESPACE ();
3820 if (*input_line_pointer != ',')
3822 as_bad (_("Expected comma after symbol-name"));
3823 ignore_rest_of_line ();
3824 return;
3827 /* Skip ','. */
3828 input_line_pointer++;
3830 if ((temp = get_absolute_expression ()) < 0)
3832 as_bad (_(".COMMon length (%lu) out of range ignored"),
3833 (unsigned long) temp);
3834 ignore_rest_of_line ();
3835 return;
3837 size = temp;
3838 *p = 0;
3839 symbolP = symbol_find_or_make (name);
3840 *p = c;
3841 if (S_IS_DEFINED (symbolP) && ! S_IS_COMMON (symbolP))
3843 as_bad (_("Ignoring attempt to re-define symbol"));
3844 ignore_rest_of_line ();
3845 return;
3847 if (S_GET_VALUE (symbolP) != 0)
3849 if (S_GET_VALUE (symbolP) != (valueT) size)
3851 as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %ld."),
3852 S_GET_NAME (symbolP), (long) S_GET_VALUE (symbolP), (long) size);
3855 else
3857 #ifndef OBJ_ELF
3858 S_SET_VALUE (symbolP, (valueT) size);
3859 S_SET_EXTERNAL (symbolP);
3860 #endif
3862 know (symbol_get_frag (symbolP) == &zero_address_frag);
3863 if (*input_line_pointer != ',')
3865 as_bad (_("Expected comma after common length"));
3866 ignore_rest_of_line ();
3867 return;
3869 input_line_pointer++;
3870 SKIP_WHITESPACE ();
3871 if (*input_line_pointer != '"')
3873 temp = get_absolute_expression ();
3875 #ifndef OBJ_ELF
3876 if (temp > max_alignment)
3878 temp = max_alignment;
3879 as_warn (_("alignment too large; assuming %ld"), (long) temp);
3881 #endif
3883 if (temp < 0)
3885 as_bad (_("negative alignment"));
3886 ignore_rest_of_line ();
3887 return;
3890 #ifdef OBJ_ELF
3891 if (symbol_get_obj (symbolP)->local)
3893 segT old_sec;
3894 int old_subsec;
3895 char *p;
3896 int align;
3898 old_sec = now_seg;
3899 old_subsec = now_subseg;
3901 if (temp == 0)
3902 align = 0;
3903 else
3904 align = mylog2 (temp);
3906 if (align < 0)
3908 as_bad (_("alignment not a power of 2"));
3909 ignore_rest_of_line ();
3910 return;
3913 record_alignment (bss_section, align);
3914 subseg_set (bss_section, 0);
3915 if (align)
3916 frag_align (align, 0, 0);
3917 if (S_GET_SEGMENT (symbolP) == bss_section)
3918 symbol_get_frag (symbolP)->fr_symbol = 0;
3919 symbol_set_frag (symbolP, frag_now);
3920 p = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP,
3921 (offsetT) size, (char *) 0);
3922 *p = 0;
3923 S_SET_SEGMENT (symbolP, bss_section);
3924 S_CLEAR_EXTERNAL (symbolP);
3925 S_SET_SIZE (symbolP, size);
3926 subseg_set (old_sec, old_subsec);
3928 else
3929 #endif /* OBJ_ELF */
3931 allocate_common:
3932 S_SET_VALUE (symbolP, (valueT) size);
3933 #ifdef OBJ_ELF
3934 S_SET_ALIGN (symbolP, temp);
3935 S_SET_SIZE (symbolP, size);
3936 #endif
3937 S_SET_EXTERNAL (symbolP);
3938 S_SET_SEGMENT (symbolP, bfd_com_section_ptr);
3941 else
3943 input_line_pointer++;
3944 /* @@ Some use the dot, some don't. Can we get some consistency?? */
3945 if (*input_line_pointer == '.')
3946 input_line_pointer++;
3947 /* @@ Some say data, some say bss. */
3948 if (strncmp (input_line_pointer, "bss\"", 4)
3949 && strncmp (input_line_pointer, "data\"", 5))
3951 while (*--input_line_pointer != '"')
3953 input_line_pointer--;
3954 goto bad_common_segment;
3956 while (*input_line_pointer++ != '"')
3958 goto allocate_common;
3961 symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT;
3963 demand_empty_rest_of_line ();
3964 return;
3967 bad_common_segment:
3968 p = input_line_pointer;
3969 while (*p && *p != '\n')
3970 p++;
3971 c = *p;
3972 *p = '\0';
3973 as_bad (_("bad .common segment %s"), input_line_pointer + 1);
3974 *p = c;
3975 input_line_pointer = p;
3976 ignore_rest_of_line ();
3977 return;
3981 /* Handle the .empty pseudo-op. This suppresses the warnings about
3982 invalid delay slot usage. */
3984 static void
3985 s_empty (ignore)
3986 int ignore ATTRIBUTE_UNUSED;
3988 /* The easy way to implement is to just forget about the last
3989 instruction. */
3990 last_insn = NULL;
3993 static void
3994 s_seg (ignore)
3995 int ignore ATTRIBUTE_UNUSED;
3998 if (strncmp (input_line_pointer, "\"text\"", 6) == 0)
4000 input_line_pointer += 6;
4001 s_text (0);
4002 return;
4004 if (strncmp (input_line_pointer, "\"data\"", 6) == 0)
4006 input_line_pointer += 6;
4007 s_data (0);
4008 return;
4010 if (strncmp (input_line_pointer, "\"data1\"", 7) == 0)
4012 input_line_pointer += 7;
4013 s_data1 ();
4014 return;
4016 if (strncmp (input_line_pointer, "\"bss\"", 5) == 0)
4018 input_line_pointer += 5;
4019 /* We only support 2 segments -- text and data -- for now, so
4020 things in the "bss segment" will have to go into data for now.
4021 You can still allocate SEG_BSS stuff with .lcomm or .reserve. */
4022 subseg_set (data_section, 255); /* FIXME-SOMEDAY. */
4023 return;
4025 as_bad (_("Unknown segment type"));
4026 demand_empty_rest_of_line ();
4029 static void
4030 s_data1 ()
4032 subseg_set (data_section, 1);
4033 demand_empty_rest_of_line ();
4036 static void
4037 s_proc (ignore)
4038 int ignore ATTRIBUTE_UNUSED;
4040 while (!is_end_of_line[(unsigned char) *input_line_pointer])
4042 ++input_line_pointer;
4044 ++input_line_pointer;
4047 /* This static variable is set by s_uacons to tell sparc_cons_align
4048 that the expression does not need to be aligned. */
4050 static int sparc_no_align_cons = 0;
4052 /* This static variable is set by sparc_cons to emit requested types
4053 of relocations in cons_fix_new_sparc. */
4055 static const char *sparc_cons_special_reloc;
4057 /* This handles the unaligned space allocation pseudo-ops, such as
4058 .uaword. .uaword is just like .word, but the value does not need
4059 to be aligned. */
4061 static void
4062 s_uacons (bytes)
4063 int bytes;
4065 /* Tell sparc_cons_align not to align this value. */
4066 sparc_no_align_cons = 1;
4067 cons (bytes);
4068 sparc_no_align_cons = 0;
4071 /* This handles the native word allocation pseudo-op .nword.
4072 For sparc_arch_size 32 it is equivalent to .word, for
4073 sparc_arch_size 64 it is equivalent to .xword. */
4075 static void
4076 s_ncons (bytes)
4077 int bytes ATTRIBUTE_UNUSED;
4079 cons (sparc_arch_size == 32 ? 4 : 8);
4082 #ifdef OBJ_ELF
4083 /* Handle the SPARC ELF .register pseudo-op. This sets the binding of a
4084 global register.
4085 The syntax is:
4087 .register %g[2367],{#scratch|symbolname|#ignore}
4090 static void
4091 s_register (ignore)
4092 int ignore ATTRIBUTE_UNUSED;
4094 char c;
4095 int reg;
4096 int flags;
4097 const char *regname;
4099 if (input_line_pointer[0] != '%'
4100 || input_line_pointer[1] != 'g'
4101 || ((input_line_pointer[2] & ~1) != '2'
4102 && (input_line_pointer[2] & ~1) != '6')
4103 || input_line_pointer[3] != ',')
4104 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
4105 reg = input_line_pointer[2] - '0';
4106 input_line_pointer += 4;
4108 if (*input_line_pointer == '#')
4110 ++input_line_pointer;
4111 regname = input_line_pointer;
4112 c = get_symbol_end ();
4113 if (strcmp (regname, "scratch") && strcmp (regname, "ignore"))
4114 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
4115 if (regname[0] == 'i')
4116 regname = NULL;
4117 else
4118 regname = "";
4120 else
4122 regname = input_line_pointer;
4123 c = get_symbol_end ();
4125 if (sparc_arch_size == 64)
4127 if (globals[reg])
4129 if ((regname && globals[reg] != (symbolS *) 1
4130 && strcmp (S_GET_NAME (globals[reg]), regname))
4131 || ((regname != NULL) ^ (globals[reg] != (symbolS *) 1)))
4132 as_bad (_("redefinition of global register"));
4134 else
4136 if (regname == NULL)
4137 globals[reg] = (symbolS *) 1;
4138 else
4140 if (*regname)
4142 if (symbol_find (regname))
4143 as_bad (_("Register symbol %s already defined."),
4144 regname);
4146 globals[reg] = symbol_make (regname);
4147 flags = symbol_get_bfdsym (globals[reg])->flags;
4148 if (! *regname)
4149 flags = flags & ~(BSF_GLOBAL|BSF_LOCAL|BSF_WEAK);
4150 if (! (flags & (BSF_GLOBAL|BSF_LOCAL|BSF_WEAK)))
4151 flags |= BSF_GLOBAL;
4152 symbol_get_bfdsym (globals[reg])->flags = flags;
4153 S_SET_VALUE (globals[reg], (valueT) reg);
4154 S_SET_ALIGN (globals[reg], reg);
4155 S_SET_SIZE (globals[reg], 0);
4156 /* Although we actually want undefined_section here,
4157 we have to use absolute_section, because otherwise
4158 generic as code will make it a COM section.
4159 We fix this up in sparc_adjust_symtab. */
4160 S_SET_SEGMENT (globals[reg], absolute_section);
4161 S_SET_OTHER (globals[reg], 0);
4162 elf_symbol (symbol_get_bfdsym (globals[reg]))
4163 ->internal_elf_sym.st_info =
4164 ELF_ST_INFO(STB_GLOBAL, STT_REGISTER);
4165 elf_symbol (symbol_get_bfdsym (globals[reg]))
4166 ->internal_elf_sym.st_shndx = SHN_UNDEF;
4171 *input_line_pointer = c;
4173 demand_empty_rest_of_line ();
4176 /* Adjust the symbol table. We set undefined sections for STT_REGISTER
4177 symbols which need it. */
4179 void
4180 sparc_adjust_symtab ()
4182 symbolS *sym;
4184 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
4186 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym))
4187 ->internal_elf_sym.st_info) != STT_REGISTER)
4188 continue;
4190 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym))
4191 ->internal_elf_sym.st_shndx != SHN_UNDEF))
4192 continue;
4194 S_SET_SEGMENT (sym, undefined_section);
4197 #endif
4199 /* If the --enforce-aligned-data option is used, we require .word,
4200 et. al., to be aligned correctly. We do it by setting up an
4201 rs_align_code frag, and checking in HANDLE_ALIGN to make sure that
4202 no unexpected alignment was introduced.
4204 The SunOS and Solaris native assemblers enforce aligned data by
4205 default. We don't want to do that, because gcc can deliberately
4206 generate misaligned data if the packed attribute is used. Instead,
4207 we permit misaligned data by default, and permit the user to set an
4208 option to check for it. */
4210 void
4211 sparc_cons_align (nbytes)
4212 int nbytes;
4214 int nalign;
4215 char *p;
4217 /* Only do this if we are enforcing aligned data. */
4218 if (! enforce_aligned_data)
4219 return;
4221 /* Don't align if this is an unaligned pseudo-op. */
4222 if (sparc_no_align_cons)
4223 return;
4225 nalign = mylog2 (nbytes);
4226 if (nalign == 0)
4227 return;
4229 assert (nalign > 0);
4231 if (now_seg == absolute_section)
4233 if ((abs_section_offset & ((1 << nalign) - 1)) != 0)
4234 as_bad (_("misaligned data"));
4235 return;
4238 p = frag_var (rs_align_test, 1, 1, (relax_substateT) 0,
4239 (symbolS *) NULL, (offsetT) nalign, (char *) NULL);
4241 record_alignment (now_seg, nalign);
4244 /* This is called from HANDLE_ALIGN in tc-sparc.h. */
4246 void
4247 sparc_handle_align (fragp)
4248 fragS *fragp;
4250 int count, fix;
4251 char *p;
4253 count = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
4255 switch (fragp->fr_type)
4257 case rs_align_test:
4258 if (count != 0)
4259 as_bad_where (fragp->fr_file, fragp->fr_line, _("misaligned data"));
4260 break;
4262 case rs_align_code:
4263 p = fragp->fr_literal + fragp->fr_fix;
4264 fix = 0;
4266 if (count & 3)
4268 fix = count & 3;
4269 memset (p, 0, fix);
4270 p += fix;
4271 count -= fix;
4274 if (SPARC_OPCODE_ARCH_V9_P (max_architecture) && count > 8)
4276 unsigned wval = (0x30680000 | count >> 2); /* ba,a,pt %xcc, 1f */
4277 if (INSN_BIG_ENDIAN)
4278 number_to_chars_bigendian (p, wval, 4);
4279 else
4280 number_to_chars_littleendian (p, wval, 4);
4281 p += 4;
4282 count -= 4;
4283 fix += 4;
4286 if (INSN_BIG_ENDIAN)
4287 number_to_chars_bigendian (p, 0x01000000, 4);
4288 else
4289 number_to_chars_littleendian (p, 0x01000000, 4);
4291 fragp->fr_fix += fix;
4292 fragp->fr_var = 4;
4293 break;
4295 default:
4296 break;
4300 #ifdef OBJ_ELF
4301 /* Some special processing for a Sparc ELF file. */
4303 void
4304 sparc_elf_final_processing ()
4306 /* Set the Sparc ELF flag bits. FIXME: There should probably be some
4307 sort of BFD interface for this. */
4308 if (sparc_arch_size == 64)
4310 switch (sparc_memory_model)
4312 case MM_RMO:
4313 elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_RMO;
4314 break;
4315 case MM_PSO:
4316 elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_PSO;
4317 break;
4318 default:
4319 break;
4322 else if (current_architecture >= SPARC_OPCODE_ARCH_V9)
4323 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_32PLUS;
4324 if (current_architecture == SPARC_OPCODE_ARCH_V9A)
4325 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1;
4326 else if (current_architecture == SPARC_OPCODE_ARCH_V9B)
4327 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1|EF_SPARC_SUN_US3;
4330 void
4331 sparc_cons (exp, size)
4332 expressionS *exp;
4333 int size;
4335 char *save;
4337 SKIP_WHITESPACE ();
4338 sparc_cons_special_reloc = NULL;
4339 save = input_line_pointer;
4340 if (input_line_pointer[0] == '%'
4341 && input_line_pointer[1] == 'r'
4342 && input_line_pointer[2] == '_')
4344 if (strncmp (input_line_pointer + 3, "disp", 4) == 0)
4346 input_line_pointer += 7;
4347 sparc_cons_special_reloc = "disp";
4349 else if (strncmp (input_line_pointer + 3, "plt", 3) == 0)
4351 if (size != 4 && size != 8)
4352 as_bad (_("Illegal operands: %%r_plt in %d-byte data field"), size);
4353 else
4355 input_line_pointer += 6;
4356 sparc_cons_special_reloc = "plt";
4359 else if (strncmp (input_line_pointer + 3, "tls_dtpoff", 10) == 0)
4361 if (size != 4 && size != 8)
4362 as_bad (_("Illegal operands: %%r_tls_dtpoff in %d-byte data field"), size);
4363 else
4365 input_line_pointer += 13;
4366 sparc_cons_special_reloc = "tls_dtpoff";
4369 if (sparc_cons_special_reloc)
4371 int bad = 0;
4373 switch (size)
4375 case 1:
4376 if (*input_line_pointer != '8')
4377 bad = 1;
4378 input_line_pointer--;
4379 break;
4380 case 2:
4381 if (input_line_pointer[0] != '1' || input_line_pointer[1] != '6')
4382 bad = 1;
4383 break;
4384 case 4:
4385 if (input_line_pointer[0] != '3' || input_line_pointer[1] != '2')
4386 bad = 1;
4387 break;
4388 case 8:
4389 if (input_line_pointer[0] != '6' || input_line_pointer[1] != '4')
4390 bad = 1;
4391 break;
4392 default:
4393 bad = 1;
4394 break;
4397 if (bad)
4399 as_bad (_("Illegal operands: Only %%r_%s%d allowed in %d-byte data fields"),
4400 sparc_cons_special_reloc, size * 8, size);
4402 else
4404 input_line_pointer += 2;
4405 if (*input_line_pointer != '(')
4407 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4408 sparc_cons_special_reloc, size * 8);
4409 bad = 1;
4413 if (bad)
4415 input_line_pointer = save;
4416 sparc_cons_special_reloc = NULL;
4418 else
4420 int c;
4421 char *end = ++input_line_pointer;
4422 int npar = 0;
4424 while (! is_end_of_line[(c = *end)])
4426 if (c == '(')
4427 npar++;
4428 else if (c == ')')
4430 if (!npar)
4431 break;
4432 npar--;
4434 end++;
4437 if (c != ')')
4438 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4439 sparc_cons_special_reloc, size * 8);
4440 else
4442 *end = '\0';
4443 expression (exp);
4444 *end = c;
4445 if (input_line_pointer != end)
4447 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4448 sparc_cons_special_reloc, size * 8);
4450 else
4452 input_line_pointer++;
4453 SKIP_WHITESPACE ();
4454 c = *input_line_pointer;
4455 if (! is_end_of_line[c] && c != ',')
4456 as_bad (_("Illegal operands: garbage after %%r_%s%d()"),
4457 sparc_cons_special_reloc, size * 8);
4463 if (sparc_cons_special_reloc == NULL)
4464 expression (exp);
4467 #endif
4469 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
4470 reloc for a cons. We could use the definition there, except that
4471 we want to handle little endian relocs specially. */
4473 void
4474 cons_fix_new_sparc (frag, where, nbytes, exp)
4475 fragS *frag;
4476 int where;
4477 unsigned int nbytes;
4478 expressionS *exp;
4480 bfd_reloc_code_real_type r;
4482 r = (nbytes == 1 ? BFD_RELOC_8 :
4483 (nbytes == 2 ? BFD_RELOC_16 :
4484 (nbytes == 4 ? BFD_RELOC_32 : BFD_RELOC_64)));
4486 if (target_little_endian_data
4487 && nbytes == 4
4488 && now_seg->flags & SEC_ALLOC)
4489 r = BFD_RELOC_SPARC_REV32;
4491 if (sparc_cons_special_reloc)
4493 if (*sparc_cons_special_reloc == 'd')
4494 switch (nbytes)
4496 case 1: r = BFD_RELOC_8_PCREL; break;
4497 case 2: r = BFD_RELOC_16_PCREL; break;
4498 case 4: r = BFD_RELOC_32_PCREL; break;
4499 case 8: r = BFD_RELOC_64_PCREL; break;
4500 default: abort ();
4502 else if (*sparc_cons_special_reloc == 'p')
4503 switch (nbytes)
4505 case 4: r = BFD_RELOC_SPARC_PLT32; break;
4506 case 8: r = BFD_RELOC_SPARC_PLT64; break;
4508 else
4509 switch (nbytes)
4511 case 4: r = BFD_RELOC_SPARC_TLS_DTPOFF32; break;
4512 case 8: r = BFD_RELOC_SPARC_TLS_DTPOFF64; break;
4515 else if (sparc_no_align_cons)
4517 switch (nbytes)
4519 case 2: r = BFD_RELOC_SPARC_UA16; break;
4520 case 4: r = BFD_RELOC_SPARC_UA32; break;
4521 case 8: r = BFD_RELOC_SPARC_UA64; break;
4522 default: abort ();
4526 fix_new_exp (frag, where, (int) nbytes, exp, 0, r);
4527 sparc_cons_special_reloc = NULL;
4530 void
4531 sparc_cfi_frame_initial_instructions ()
4533 cfi_add_CFA_def_cfa (14, sparc_arch_size == 64 ? 0x7ff : 0);
4537 sparc_regname_to_dw2regnum (const char *regname)
4539 char *p, *q;
4541 if (!regname[0])
4542 return -1;
4544 q = "goli";
4545 p = strchr (q, regname[0]);
4546 if (p)
4548 if (regname[1] < '0' || regname[1] > '8' || regname[2])
4549 return -1;
4550 return (p - q) * 8 + regname[1] - '0';
4552 if (regname[0] == 's' && regname[1] == 'p' && !regname[2])
4553 return 14;
4554 if (regname[0] == 'f' && regname[1] == 'p' && !regname[2])
4555 return 30;
4556 if (regname[0] == 'f' || regname[0] == 'r')
4558 unsigned int regnum;
4560 regnum = strtoul (regname + 1, &q, 10);
4561 if (p == q || *q)
4562 return -1;
4563 if (regnum >= ((regname[0] == 'f'
4564 && SPARC_OPCODE_ARCH_V9_P (max_architecture))
4565 ? 64 : 32))
4566 return -1;
4567 if (regname[0] == 'f')
4569 regnum += 32;
4570 if (regnum >= 64 && (regnum & 1))
4571 return -1;
4573 return regnum;
4575 return -1;
4578 void
4579 sparc_cfi_emit_pcrel_expr (expressionS *exp, unsigned int nbytes)
4581 sparc_cons_special_reloc = "disp";
4582 sparc_no_align_cons = 1;
4583 emit_expr (exp, nbytes);
4584 sparc_no_align_cons = 0;
4585 sparc_cons_special_reloc = NULL;