1 /* tc-i860.c -- Assembler for the Intel i860 architecture.
2 Copyright 1989, 1992, 1993, 1994, 1995, 1998, 1999, 2000, 2001, 2002, 2003
3 Free Software Foundation, Inc.
5 Brought back from the dead and completely reworked
6 by Jason Eckhardt <jle@cygnus.com>.
8 This file is part of GAS, the GNU Assembler.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License along
21 with GAS; see the file COPYING. If not, write to the Free Software
22 Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
27 #include "safe-ctype.h"
29 #include "opcode/i860.h"
33 /* The opcode hash table. */
34 static struct hash_control
*op_hash
= NULL
;
36 /* These characters always start a comment. */
37 const char comment_chars
[] = "#!/";
39 /* These characters start a comment at the beginning of a line. */
40 const char line_comment_chars
[] = "#/";
42 const char line_separator_chars
[] = ";";
44 /* Characters that can be used to separate the mantissa from the exponent
45 in floating point numbers. */
46 const char EXP_CHARS
[] = "eE";
48 /* Characters that indicate this number is a floating point constant.
49 As in 0f12.456 or 0d1.2345e12. */
50 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
52 /* Register prefix (depends on syntax). */
53 static char reg_prefix
;
61 enum expand_type expand
;
65 bfd_reloc_code_real_type reloc
;
71 /* The current fixup count. */
74 static char *expr_end
;
76 /* Indicates error if a pseudo operation was expanded after a branch. */
77 static char last_expand
;
79 /* If true, then warn if any pseudo operations were expanded. */
80 static int target_warn_expand
= 0;
82 /* If true, then XP support is enabled. */
83 static int target_xp
= 0;
85 /* If true, then Intel syntax is enabled (default to AT&T/SVR4 syntax). */
86 static int target_intel_syntax
= 0;
90 static void i860_process_insn (char *);
91 static void s_dual (int);
92 static void s_enddual (int);
93 static void s_atmp (int);
94 static void s_align_wrapper (int);
95 static int i860_get_expression (char *);
96 static bfd_reloc_code_real_type
obtain_reloc_for_imm16 (fixS
*, long *);
98 static void print_insn (struct i860_it
*);
101 const pseudo_typeS md_pseudo_table
[] =
103 {"align", s_align_wrapper
, 0},
105 {"enddual", s_enddual
, 0},
110 /* Dual-instruction mode handling. */
113 DUAL_OFF
= 0, DUAL_ON
, DUAL_DDOT
, DUAL_ONDDOT
,
115 static enum dual dual_mode
= DUAL_OFF
;
117 /* Handle ".dual" directive. */
119 s_dual (int ignore ATTRIBUTE_UNUSED
)
121 if (target_intel_syntax
)
124 as_bad (_("Directive .dual available only with -mintel-syntax option"));
127 /* Handle ".enddual" directive. */
129 s_enddual (int ignore ATTRIBUTE_UNUSED
)
131 if (target_intel_syntax
)
132 dual_mode
= DUAL_OFF
;
134 as_bad (_("Directive .enddual available only with -mintel-syntax option"));
137 /* Temporary register used when expanding assembler pseudo operations. */
138 static int atmp
= 31;
141 s_atmp (int ignore ATTRIBUTE_UNUSED
)
145 if (! target_intel_syntax
)
147 as_bad (_("Directive .atmp available only with -mintel-syntax option"));
148 demand_empty_rest_of_line ();
152 if (strncmp (input_line_pointer
, "sp", 2) == 0)
154 input_line_pointer
+= 2;
157 else if (strncmp (input_line_pointer
, "fp", 2) == 0)
159 input_line_pointer
+= 2;
162 else if (strncmp (input_line_pointer
, "r", 1) == 0)
164 input_line_pointer
+= 1;
165 temp
= get_absolute_expression ();
166 if (temp
>= 0 && temp
<= 31)
169 as_bad (_("Unknown temporary pseudo register"));
173 as_bad (_("Unknown temporary pseudo register"));
175 demand_empty_rest_of_line ();
178 /* Handle ".align" directive depending on syntax mode.
179 AT&T/SVR4 syntax uses the standard align directive. However,
180 the Intel syntax additionally allows keywords for the alignment
181 parameter: ".align type", where type is one of {.short, .long,
182 .quad, .single, .double} representing alignments of 2, 4,
183 16, 4, and 8, respectively. */
185 s_align_wrapper (int arg
)
187 char *parm
= input_line_pointer
;
189 if (target_intel_syntax
)
191 /* Replace a keyword with the equivalent integer so the
192 standard align routine can parse the directive. */
193 if (strncmp (parm
, ".short", 6) == 0)
194 strncpy (parm
, " 2", 6);
195 else if (strncmp (parm
, ".long", 5) == 0)
196 strncpy (parm
, " 4", 5);
197 else if (strncmp (parm
, ".quad", 5) == 0)
198 strncpy (parm
, " 16", 5);
199 else if (strncmp (parm
, ".single", 7) == 0)
200 strncpy (parm
, " 4", 7);
201 else if (strncmp (parm
, ".double", 7) == 0)
202 strncpy (parm
, " 8", 7);
204 while (*input_line_pointer
== ' ')
205 ++input_line_pointer
;
211 /* This function is called once, at assembler startup time. It should
212 set up all the tables and data structures that the MD part of the
213 assembler will need. */
217 const char *retval
= NULL
;
221 op_hash
= hash_new ();
223 while (i860_opcodes
[i
].name
!= NULL
)
225 const char *name
= i860_opcodes
[i
].name
;
226 retval
= hash_insert (op_hash
, name
, (PTR
)&i860_opcodes
[i
]);
229 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
230 i860_opcodes
[i
].name
, retval
);
235 if (i860_opcodes
[i
].match
& i860_opcodes
[i
].lose
)
238 _("internal error: losing opcode: `%s' \"%s\"\n"),
239 i860_opcodes
[i
].name
, i860_opcodes
[i
].args
);
244 while (i860_opcodes
[i
].name
!= NULL
245 && strcmp (i860_opcodes
[i
].name
, name
) == 0);
249 as_fatal (_("Defective assembler. No assembly attempted."));
251 /* Set the register prefix for either Intel or AT&T/SVR4 syntax. */
252 reg_prefix
= target_intel_syntax
? 0 : '%';
255 /* This is the core of the machine-dependent assembler. STR points to a
256 machine dependent instruction. This function emits the frags/bytes
259 md_assemble (char *str
)
264 struct i860_it pseudo
[3];
269 /* Assemble the instruction. */
270 i860_process_insn (str
);
272 /* Check for expandable flag to produce pseudo-instructions. This
273 is an undesirable feature that should be avoided. */
274 if (the_insn
.expand
!= 0 && the_insn
.expand
!= XP_ONLY
275 && ! (the_insn
.fi
[0].fup
& (OP_SEL_HA
| OP_SEL_H
| OP_SEL_L
| OP_SEL_GOT
276 | OP_SEL_GOTOFF
| OP_SEL_PLT
)))
278 for (i
= 0; i
< 3; i
++)
279 pseudo
[i
] = the_insn
;
282 switch (the_insn
.expand
)
290 if (the_insn
.fi
[0].exp
.X_add_symbol
== NULL
291 && the_insn
.fi
[0].exp
.X_op_symbol
== NULL
292 && (the_insn
.fi
[0].exp
.X_add_number
< (1 << 15)
293 && the_insn
.fi
[0].exp
.X_add_number
>= -(1 << 15)))
296 /* Emit "or l%const,r0,ireg_dest". */
297 pseudo
[0].opcode
= (the_insn
.opcode
& 0x001f0000) | 0xe4000000;
298 pseudo
[0].fi
[0].fup
= (OP_IMM_S16
| OP_SEL_L
);
300 /* Emit "orh h%const,ireg_dest,ireg_dest". */
301 pseudo
[1].opcode
= (the_insn
.opcode
& 0x03ffffff) | 0xec000000
302 | ((the_insn
.opcode
& 0x001f0000) << 5);
303 pseudo
[1].fi
[0].fup
= (OP_IMM_S16
| OP_SEL_H
);
309 if (the_insn
.fi
[0].exp
.X_add_symbol
== NULL
310 && the_insn
.fi
[0].exp
.X_op_symbol
== NULL
311 && (the_insn
.fi
[0].exp
.X_add_number
< (1 << 15)
312 && the_insn
.fi
[0].exp
.X_add_number
>= -(1 << 15)))
315 /* Emit "orh ha%addr_expr,ireg_src2,r31". */
316 pseudo
[0].opcode
= 0xec000000 | (the_insn
.opcode
& 0x03e00000)
318 pseudo
[0].fi
[0].fup
= (OP_IMM_S16
| OP_SEL_HA
);
320 /* Emit "l%addr_expr(r31),ireg_dest". We pick up the fixup
321 information from the original instruction. */
322 pseudo
[1].opcode
= (the_insn
.opcode
& ~0x03e00000) | (atmp
<< 21);
323 pseudo
[1].fi
[0].fup
= the_insn
.fi
[0].fup
| OP_SEL_L
;
329 if (the_insn
.fi
[0].exp
.X_add_symbol
== NULL
330 && the_insn
.fi
[0].exp
.X_op_symbol
== NULL
331 && (the_insn
.fi
[0].exp
.X_add_number
< (1 << 16)
332 && the_insn
.fi
[0].exp
.X_add_number
>= 0))
335 /* Emit "$(opcode)h h%const,ireg_src2,r31". */
336 pseudo
[0].opcode
= (the_insn
.opcode
& 0xf3e0ffff) | 0x0c000000
338 pseudo
[0].fi
[0].fup
= (OP_IMM_S16
| OP_SEL_H
);
340 /* Emit "$(opcode) l%const,r31,ireg_dest". */
341 pseudo
[1].opcode
= (the_insn
.opcode
& 0xf01f0000) | 0x04000000
343 pseudo
[1].fi
[0].fup
= (OP_IMM_S16
| OP_SEL_L
);
349 if (the_insn
.fi
[0].exp
.X_add_symbol
== NULL
350 && the_insn
.fi
[0].exp
.X_op_symbol
== NULL
351 && (the_insn
.fi
[0].exp
.X_add_number
< (1 << 16)
352 && the_insn
.fi
[0].exp
.X_add_number
>= 0))
355 /* Emit "andnot h%const,ireg_src2,r31". */
356 pseudo
[0].opcode
= (the_insn
.opcode
& 0x03e0ffff) | 0xd4000000
358 pseudo
[0].fi
[0].fup
= (OP_IMM_S16
| OP_SEL_H
);
359 pseudo
[0].fi
[0].exp
.X_add_number
=
360 -1 - the_insn
.fi
[0].exp
.X_add_number
;
362 /* Emit "andnot l%const,r31,ireg_dest". */
363 pseudo
[1].opcode
= (the_insn
.opcode
& 0x001f0000) | 0xd4000000
365 pseudo
[1].fi
[0].fup
= (OP_IMM_S16
| OP_SEL_L
);
366 pseudo
[1].fi
[0].exp
.X_add_number
=
367 -1 - the_insn
.fi
[0].exp
.X_add_number
;
373 if (the_insn
.fi
[0].exp
.X_add_symbol
== NULL
374 && the_insn
.fi
[0].exp
.X_op_symbol
== NULL
375 && (the_insn
.fi
[0].exp
.X_add_number
< (1 << 15)
376 && the_insn
.fi
[0].exp
.X_add_number
>= -(1 << 15)))
379 /* Emit "orh h%const,r0,r31". */
380 pseudo
[0].opcode
= 0xec000000 | (atmp
<< 16);
381 pseudo
[0].fi
[0].fup
= (OP_IMM_S16
| OP_SEL_H
);
383 /* Emit "or l%const,r31,r31". */
384 pseudo
[1].opcode
= 0xe4000000 | (atmp
<< 21) | (atmp
<< 16);
385 pseudo
[1].fi
[0].fup
= (OP_IMM_S16
| OP_SEL_L
);
387 /* Emit "r31,ireg_src2,ireg_dest". */
388 pseudo
[2].opcode
= (the_insn
.opcode
& ~0x0400ffff) | (atmp
<< 11);
389 pseudo
[2].fi
[0].fup
= OP_IMM_S16
;
395 as_fatal (_("failed sanity check."));
398 the_insn
= pseudo
[0];
400 /* Warn if an opcode is expanded after a delayed branch. */
401 if (num_opcodes
> 1 && last_expand
== 1)
402 as_warn (_("Expanded opcode after delayed branch: `%s'"), str
);
404 /* Warn if an opcode is expanded in dual mode. */
405 if (num_opcodes
> 1 && dual_mode
!= DUAL_OFF
)
406 as_warn (_("Expanded opcode in dual mode: `%s'"), str
);
408 /* Notify if any expansions happen. */
409 if (target_warn_expand
&& num_opcodes
> 1)
410 as_warn (_("An instruction was expanded (%s)"), str
);
418 /* Output the opcode. Note that the i860 always reads instructions
419 as little-endian data. */
420 destp
= frag_more (4);
421 number_to_chars_littleendian (destp
, the_insn
.opcode
, 4);
423 /* Check for expanded opcode after branch or in dual mode. */
424 last_expand
= the_insn
.fi
[0].pcrel
;
426 /* Output the symbol-dependent stuff. Only btne and bte will ever
427 loop more than once here, since only they (possibly) have more
429 for (tmp
= 0; tmp
< fc
; tmp
++)
431 if (the_insn
.fi
[tmp
].fup
!= OP_NONE
)
434 fix
= fix_new_exp (frag_now
,
435 destp
- frag_now
->fr_literal
,
437 &the_insn
.fi
[tmp
].exp
,
438 the_insn
.fi
[tmp
].pcrel
,
439 the_insn
.fi
[tmp
].reloc
);
441 /* Despite the odd name, this is a scratch field. We use
442 it to encode operand type information. */
443 fix
->fx_addnumber
= the_insn
.fi
[tmp
].fup
;
446 the_insn
= pseudo
[++i
];
448 while (--num_opcodes
> 0);
452 /* Assemble the instruction pointed to by STR. */
454 i860_process_insn (char *str
)
459 struct i860_opcode
*insn
;
461 unsigned long opcode
;
466 #if 1 /* For compiler warnings. */
473 for (s
= str
; ISLOWER (*s
) || *s
== '.' || *s
== '3'
474 || *s
== '2' || *s
== '1'; ++s
)
492 as_fatal (_("Unknown opcode: `%s'"), str
);
495 /* Check for dual mode ("d.") opcode prefix. */
496 if (strncmp (str
, "d.", 2) == 0)
498 if (dual_mode
== DUAL_ON
)
499 dual_mode
= DUAL_ONDDOT
;
501 dual_mode
= DUAL_DDOT
;
505 if ((insn
= (struct i860_opcode
*) hash_find (op_hash
, str
)) == NULL
)
507 if (dual_mode
== DUAL_DDOT
|| dual_mode
== DUAL_ONDDOT
)
509 as_bad (_("Unknown opcode: `%s'"), str
);
520 opcode
= insn
->match
;
521 memset (&the_insn
, '\0', sizeof (the_insn
));
523 for (t
= 0; t
< MAX_FIXUPS
; t
++)
525 the_insn
.fi
[t
].reloc
= BFD_RELOC_NONE
;
526 the_insn
.fi
[t
].pcrel
= 0;
527 the_insn
.fi
[t
].fup
= OP_NONE
;
530 /* Build the opcode, checking as we go that the operands match. */
531 for (args
= insn
->args
; ; ++args
)
545 /* These must match exactly. */
555 /* Must be at least one digit. */
565 /* Next operand must be a register. */
569 /* Check for register prefix if necessary. */
570 if (reg_prefix
&& *s
!= reg_prefix
)
597 /* Any register r0..r31. */
600 if (!ISDIGIT (c
= *s
++))
606 if ((c
= 10 * (c
- '0') + (*s
++ - '0')) >= 32)
614 /* Not this opcode. */
619 /* Obtained the register, now place it in the opcode. */
623 opcode
|= mask
<< 11;
627 opcode
|= mask
<< 21;
631 opcode
|= mask
<< 16;
637 /* Next operand is a floating point register. */
641 /* Check for register prefix if necessary. */
642 if (reg_prefix
&& *s
!= reg_prefix
)
647 if (*s
++ == 'f' && ISDIGIT (*s
))
652 mask
= 10 * (mask
- '0') + (*s
++ - '0');
665 opcode
|= mask
<< 11;
669 opcode
|= mask
<< 21;
673 opcode
|= mask
<< 16;
674 if ((opcode
& (1 << 10)) && mask
!= 0
675 && (mask
== ((opcode
>> 11) & 0x1f)))
676 as_warn (_("Pipelined instruction: fsrc1 = fdest"));
682 /* Next operand must be a control register. */
684 /* Check for register prefix if necessary. */
685 if (reg_prefix
&& *s
!= reg_prefix
)
690 if (strncmp (s
, "fir", 3) == 0)
696 if (strncmp (s
, "psr", 3) == 0)
702 if (strncmp (s
, "dirbase", 7) == 0)
708 if (strncmp (s
, "db", 2) == 0)
714 if (strncmp (s
, "fsr", 3) == 0)
720 if (strncmp (s
, "epsr", 4) == 0)
726 /* The remaining control registers are XP only. */
727 if (target_xp
&& strncmp (s
, "bear", 4) == 0)
733 if (target_xp
&& strncmp (s
, "ccr", 3) == 0)
739 if (target_xp
&& strncmp (s
, "p0", 2) == 0)
745 if (target_xp
&& strncmp (s
, "p1", 2) == 0)
751 if (target_xp
&& strncmp (s
, "p2", 2) == 0)
757 if (target_xp
&& strncmp (s
, "p3", 2) == 0)
765 /* 5-bit immediate in src1. */
767 if (! i860_get_expression (s
))
770 the_insn
.fi
[fc
].fup
|= OP_IMM_U5
;
776 /* 26-bit immediate, relative branch (lbroff). */
778 the_insn
.fi
[fc
].pcrel
= 1;
779 the_insn
.fi
[fc
].fup
|= OP_IMM_BR26
;
782 /* 16-bit split immediate, relative branch (sbroff). */
784 the_insn
.fi
[fc
].pcrel
= 1;
785 the_insn
.fi
[fc
].fup
|= OP_IMM_BR16
;
788 /* 16-bit split immediate. */
790 the_insn
.fi
[fc
].fup
|= OP_IMM_SPLIT16
;
793 /* 16-bit split immediate, byte aligned (st.b). */
795 the_insn
.fi
[fc
].fup
|= OP_IMM_SPLIT16
;
798 /* 16-bit split immediate, half-word aligned (st.s). */
800 the_insn
.fi
[fc
].fup
|= (OP_IMM_SPLIT16
| OP_ENCODE1
| OP_ALIGN2
);
803 /* 16-bit split immediate, word aligned (st.l). */
805 the_insn
.fi
[fc
].fup
|= (OP_IMM_SPLIT16
| OP_ENCODE1
| OP_ALIGN4
);
808 /* 16-bit immediate. */
810 the_insn
.fi
[fc
].fup
|= OP_IMM_S16
;
813 /* 16-bit immediate, byte aligned (ld.b). */
815 the_insn
.fi
[fc
].fup
|= OP_IMM_S16
;
818 /* 16-bit immediate, half-word aligned (ld.s). */
820 the_insn
.fi
[fc
].fup
|= (OP_IMM_S16
| OP_ENCODE1
| OP_ALIGN2
);
823 /* 16-bit immediate, word aligned (ld.l, {p}fld.l, fst.l). */
825 if (insn
->name
[0] == 'l')
826 the_insn
.fi
[fc
].fup
|= (OP_IMM_S16
| OP_ENCODE1
| OP_ALIGN4
);
828 the_insn
.fi
[fc
].fup
|= (OP_IMM_S16
| OP_ENCODE2
| OP_ALIGN4
);
831 /* 16-bit immediate, double-word aligned ({p}fld.d, fst.d). */
833 the_insn
.fi
[fc
].fup
|= (OP_IMM_S16
| OP_ENCODE3
| OP_ALIGN8
);
836 /* 16-bit immediate, quad-word aligned (fld.q, fst.q). */
838 the_insn
.fi
[fc
].fup
|= (OP_IMM_S16
| OP_ENCODE3
| OP_ALIGN16
);
842 /* Handle the immediate for either the Intel syntax or
843 SVR4 syntax. The Intel syntax is "ha%immediate"
844 whereas SVR4 syntax is "[immediate]@ha". */
846 if (target_intel_syntax
== 0)
848 /* AT&T/SVR4 syntax. */
852 /* Note that if i860_get_expression() fails, we will still
853 have created U entries in the symbol table for the
854 'symbols' in the input string. Try not to create U
855 symbols for registers, etc. */
856 if (! i860_get_expression (s
))
861 if (strncmp (s
, "@ha", 3) == 0)
863 the_insn
.fi
[fc
].fup
|= OP_SEL_HA
;
866 else if (strncmp (s
, "@h", 2) == 0)
868 the_insn
.fi
[fc
].fup
|= OP_SEL_H
;
871 else if (strncmp (s
, "@l", 2) == 0)
873 the_insn
.fi
[fc
].fup
|= OP_SEL_L
;
876 else if (strncmp (s
, "@gotoff", 7) == 0
877 || strncmp (s
, "@GOTOFF", 7) == 0)
879 as_bad (_("Assembler does not yet support PIC"));
880 the_insn
.fi
[fc
].fup
|= OP_SEL_GOTOFF
;
883 else if (strncmp (s
, "@got", 4) == 0
884 || strncmp (s
, "@GOT", 4) == 0)
886 as_bad (_("Assembler does not yet support PIC"));
887 the_insn
.fi
[fc
].fup
|= OP_SEL_GOT
;
890 else if (strncmp (s
, "@plt", 4) == 0
891 || strncmp (s
, "@PLT", 4) == 0)
893 as_bad (_("Assembler does not yet support PIC"));
894 the_insn
.fi
[fc
].fup
|= OP_SEL_PLT
;
898 the_insn
.expand
= insn
->expand
;
908 if (strncmp (s
, "ha%", 3) == 0)
910 the_insn
.fi
[fc
].fup
|= OP_SEL_HA
;
913 else if (strncmp (s
, "h%", 2) == 0)
915 the_insn
.fi
[fc
].fup
|= OP_SEL_H
;
918 else if (strncmp (s
, "l%", 2) == 0)
920 the_insn
.fi
[fc
].fup
|= OP_SEL_L
;
923 the_insn
.expand
= insn
->expand
;
925 /* Note that if i860_get_expression() fails, we will still
926 have created U entries in the symbol table for the
927 'symbols' in the input string. Try not to create U
928 symbols for registers, etc. */
929 if (! i860_get_expression (s
))
940 as_fatal (_("failed sanity check."));
947 /* Args don't match. */
948 if (insn
[1].name
!= NULL
949 && ! strcmp (insn
->name
, insn
[1].name
))
957 as_bad (_("Illegal operands for %s"), insn
->name
);
964 /* Set the dual bit on this instruction if necessary. */
965 if (dual_mode
!= DUAL_OFF
)
967 if ((opcode
& 0xfc000000) == 0x48000000 || opcode
== 0xb0000000)
969 /* The instruction is a flop or a fnop, so set its dual bit
970 (but check that it is 8-byte aligned). */
971 if (((frag_now
->fr_address
+ frag_now_fix_octets ()) & 7) == 0)
974 as_bad (_("'d.%s' must be 8-byte aligned"), insn
->name
);
976 if (dual_mode
== DUAL_DDOT
)
977 dual_mode
= DUAL_OFF
;
978 else if (dual_mode
== DUAL_ONDDOT
)
981 else if (dual_mode
== DUAL_DDOT
|| dual_mode
== DUAL_ONDDOT
)
982 as_bad (_("Prefix 'd.' invalid for instruction `%s'"), insn
->name
);
985 the_insn
.opcode
= opcode
;
987 /* Only recognize XP instructions when the user has requested it. */
988 if (insn
->expand
== XP_ONLY
&& ! target_xp
)
989 as_bad (_("Unknown opcode: `%s'"), insn
->name
);
993 i860_get_expression (char *str
)
998 save_in
= input_line_pointer
;
999 input_line_pointer
= str
;
1000 seg
= expression (&the_insn
.fi
[fc
].exp
);
1001 if (seg
!= absolute_section
1002 && seg
!= undefined_section
1003 && ! SEG_NORMAL (seg
))
1005 the_insn
.error
= _("bad segment");
1006 expr_end
= input_line_pointer
;
1007 input_line_pointer
= save_in
;
1010 expr_end
= input_line_pointer
;
1011 input_line_pointer
= save_in
;
1015 /* Turn a string in input_line_pointer into a floating point constant of
1016 type TYPE, and store the appropriate bytes in *LITP. The number of
1017 LITTLENUMS emitted is stored in *SIZEP. An error message is returned,
1020 /* Equal to MAX_PRECISION in atof-ieee.c. */
1021 #define MAX_LITTLENUMS 6
1024 md_atof (int type
, char *litP
, int *sizeP
)
1027 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1028 LITTLENUM_TYPE
*wordP
;
1059 return _("Bad call to MD_ATOF()");
1061 t
= atof_ieee (input_line_pointer
, type
, words
);
1063 input_line_pointer
= t
;
1064 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1065 for (wordP
= words
; prec
--;)
1067 md_number_to_chars (litP
, (long) (*wordP
++), sizeof (LITTLENUM_TYPE
));
1068 litP
+= sizeof (LITTLENUM_TYPE
);
1073 /* Write out in current endian mode. */
1075 md_number_to_chars (char *buf
, valueT val
, int n
)
1077 if (target_big_endian
)
1078 number_to_chars_bigendian (buf
, val
, n
);
1080 number_to_chars_littleendian (buf
, val
, n
);
1083 /* This should never be called for i860. */
1085 md_estimate_size_before_relax (register fragS
*fragP ATTRIBUTE_UNUSED
,
1086 segT segtype ATTRIBUTE_UNUSED
)
1088 as_fatal (_("i860_estimate_size_before_relax\n"));
1093 print_insn (struct i860_it
*insn
)
1096 fprintf (stderr
, "ERROR: %s\n", insn
->error
);
1098 fprintf (stderr
, "opcode = 0x%08lx\t", insn
->opcode
);
1099 fprintf (stderr
, "expand = 0x%x\t", insn
->expand
);
1100 fprintf (stderr
, "reloc = %s\t\n",
1101 bfd_get_reloc_code_name (insn
->reloc
));
1102 fprintf (stderr
, "exp = {\n");
1103 fprintf (stderr
, "\t\tX_add_symbol = %s\n",
1104 insn
->exp
.X_add_symbol
?
1105 (S_GET_NAME (insn
->exp
.X_add_symbol
) ?
1106 S_GET_NAME (insn
->exp
.X_add_symbol
) : "???") : "0");
1107 fprintf (stderr
, "\t\tX_op_symbol = %s\n",
1108 insn
->exp
.X_op_symbol
?
1109 (S_GET_NAME (insn
->exp
.X_op_symbol
) ?
1110 S_GET_NAME (insn
->exp
.X_op_symbol
) : "???") : "0");
1111 fprintf (stderr
, "\t\tX_add_number = %lx\n",
1112 insn
->exp
.X_add_number
);
1113 fprintf (stderr
, "}\n");
1115 #endif /* DEBUG_I860 */
1119 const char *md_shortopts
= "VQ:";
1121 const char *md_shortopts
= "";
1124 #define OPTION_EB (OPTION_MD_BASE + 0)
1125 #define OPTION_EL (OPTION_MD_BASE + 1)
1126 #define OPTION_WARN_EXPAND (OPTION_MD_BASE + 2)
1127 #define OPTION_XP (OPTION_MD_BASE + 3)
1128 #define OPTION_INTEL_SYNTAX (OPTION_MD_BASE + 4)
1130 struct option md_longopts
[] = {
1131 { "EB", no_argument
, NULL
, OPTION_EB
},
1132 { "EL", no_argument
, NULL
, OPTION_EL
},
1133 { "mwarn-expand", no_argument
, NULL
, OPTION_WARN_EXPAND
},
1134 { "mxp", no_argument
, NULL
, OPTION_XP
},
1135 { "mintel-syntax",no_argument
, NULL
, OPTION_INTEL_SYNTAX
},
1136 { NULL
, no_argument
, NULL
, 0 }
1138 size_t md_longopts_size
= sizeof (md_longopts
);
1141 md_parse_option (int c
, char *arg ATTRIBUTE_UNUSED
)
1146 target_big_endian
= 1;
1150 target_big_endian
= 0;
1153 case OPTION_WARN_EXPAND
:
1154 target_warn_expand
= 1;
1161 case OPTION_INTEL_SYNTAX
:
1162 target_intel_syntax
= 1;
1166 /* SVR4 argument compatibility (-V): print version ID. */
1168 print_version_id ();
1171 /* SVR4 argument compatibility (-Qy, -Qn): controls whether
1172 a .comment section should be emitted or not (ignored). */
1185 md_show_usage (FILE *stream
)
1187 fprintf (stream
, _("\
1188 -EL generate code for little endian mode (default)\n\
1189 -EB generate code for big endian mode\n\
1190 -mwarn-expand warn if pseudo operations are expanded\n\
1191 -mxp enable i860XP support (disabled by default)\n\
1192 -mintel-syntax enable Intel syntax (default to AT&T/SVR4)\n"));
1194 /* SVR4 compatibility flags. */
1195 fprintf (stream
, _("\
1196 -V print assembler version number\n\
1197 -Qy, -Qn ignored\n"));
1202 /* We have no need to default values of symbols. */
1204 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
1209 /* The i860 denotes auto-increment with '++'. */
1211 md_operand (expressionS
*exp
)
1215 for (s
= input_line_pointer
; *s
; s
++)
1217 if (s
[0] == '+' && s
[1] == '+')
1219 input_line_pointer
+= 2;
1220 exp
->X_op
= O_register
;
1226 /* Round up a section size to the appropriate boundary. */
1228 md_section_align (segT segment ATTRIBUTE_UNUSED
,
1229 valueT size ATTRIBUTE_UNUSED
)
1231 /* Byte alignment is fine. */
1235 /* On the i860, a PC-relative offset is relative to the address of the
1236 offset plus its size. */
1238 md_pcrel_from (fixS
*fixP
)
1240 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
1243 /* Determine the relocation needed for non PC-relative 16-bit immediates.
1244 Also adjust the given immediate as necessary. Finally, check that
1245 all constraints (such as alignment) are satisfied. */
1246 static bfd_reloc_code_real_type
1247 obtain_reloc_for_imm16 (fixS
*fix
, long *val
)
1249 valueT fup
= fix
->fx_addnumber
;
1250 bfd_reloc_code_real_type reloc
;
1255 /* Check alignment restrictions. */
1256 if ((fup
& OP_ALIGN2
) && (*val
& 0x1))
1257 as_bad_where (fix
->fx_file
, fix
->fx_line
,
1258 _("This immediate requires 0 MOD 2 alignment"));
1259 else if ((fup
& OP_ALIGN4
) && (*val
& 0x3))
1260 as_bad_where (fix
->fx_file
, fix
->fx_line
,
1261 _("This immediate requires 0 MOD 4 alignment"));
1262 else if ((fup
& OP_ALIGN8
) && (*val
& 0x7))
1263 as_bad_where (fix
->fx_file
, fix
->fx_line
,
1264 _("This immediate requires 0 MOD 8 alignment"));
1265 else if ((fup
& OP_ALIGN16
) && (*val
& 0xf))
1266 as_bad_where (fix
->fx_file
, fix
->fx_line
,
1267 _("This immediate requires 0 MOD 16 alignment"));
1269 if (fup
& OP_SEL_HA
)
1271 *val
= (*val
>> 16) + (*val
& 0x8000 ? 1 : 0);
1272 reloc
= BFD_RELOC_860_HIGHADJ
;
1274 else if (fup
& OP_SEL_H
)
1277 reloc
= BFD_RELOC_860_HIGH
;
1279 else if (fup
& OP_SEL_L
)
1282 if (fup
& OP_IMM_SPLIT16
)
1284 if (fup
& OP_ENCODE1
)
1287 reloc
= BFD_RELOC_860_SPLIT1
;
1289 else if (fup
& OP_ENCODE2
)
1292 reloc
= BFD_RELOC_860_SPLIT2
;
1297 reloc
= BFD_RELOC_860_SPLIT0
;
1302 if (fup
& OP_ENCODE1
)
1305 reloc
= BFD_RELOC_860_LOW1
;
1307 else if (fup
& OP_ENCODE2
)
1310 reloc
= BFD_RELOC_860_LOW2
;
1312 else if (fup
& OP_ENCODE3
)
1315 reloc
= BFD_RELOC_860_LOW3
;
1320 reloc
= BFD_RELOC_860_LOW0
;
1324 /* Preserve size encode bits. */
1325 *val
&= ~((1 << num_encode
) - 1);
1329 /* No selector. What reloc do we generate (???)? */
1330 reloc
= BFD_RELOC_32
;
1336 /* Attempt to simplify or eliminate a fixup. To indicate that a fixup
1337 has been eliminated, set fix->fx_done. If fix->fx_addsy is non-NULL,
1338 we will have to generate a reloc entry. */
1341 md_apply_fix (fixS
*fix
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
1348 buf
= fix
->fx_frag
->fr_literal
+ fix
->fx_where
;
1350 /* Recall that earlier we stored the opcode little-endian. */
1351 insn
= bfd_getl32 (buf
);
1353 /* We stored a fix-up in this oddly-named scratch field. */
1354 fup
= fix
->fx_addnumber
;
1356 /* Determine the necessary relocations as well as inserting an
1357 immediate into the instruction. */
1358 if (fup
& OP_IMM_U5
)
1361 as_bad_where (fix
->fx_file
, fix
->fx_line
,
1362 _("5-bit immediate too large"));
1364 as_bad_where (fix
->fx_file
, fix
->fx_line
,
1365 _("5-bit field must be absolute"));
1367 insn
|= (val
& 0x1f) << 11;
1368 bfd_putl32 (insn
, buf
);
1369 fix
->fx_r_type
= BFD_RELOC_NONE
;
1372 else if (fup
& OP_IMM_S16
)
1374 fix
->fx_r_type
= obtain_reloc_for_imm16 (fix
, &val
);
1376 /* Insert the immediate. */
1381 insn
|= val
& 0xffff;
1382 bfd_putl32 (insn
, buf
);
1383 fix
->fx_r_type
= BFD_RELOC_NONE
;
1387 else if (fup
& OP_IMM_U16
)
1390 else if (fup
& OP_IMM_SPLIT16
)
1392 fix
->fx_r_type
= obtain_reloc_for_imm16 (fix
, &val
);
1394 /* Insert the immediate. */
1399 insn
|= val
& 0x7ff;
1400 insn
|= (val
& 0xf800) << 5;
1401 bfd_putl32 (insn
, buf
);
1402 fix
->fx_r_type
= BFD_RELOC_NONE
;
1406 else if (fup
& OP_IMM_BR16
)
1409 as_bad_where (fix
->fx_file
, fix
->fx_line
,
1410 _("A branch offset requires 0 MOD 4 alignment"));
1414 /* Insert the immediate. */
1418 fix
->fx_r_type
= BFD_RELOC_860_PC16
;
1422 insn
|= (val
& 0x7ff);
1423 insn
|= ((val
& 0xf800) << 5);
1424 bfd_putl32 (insn
, buf
);
1425 fix
->fx_r_type
= BFD_RELOC_NONE
;
1429 else if (fup
& OP_IMM_BR26
)
1432 as_bad_where (fix
->fx_file
, fix
->fx_line
,
1433 _("A branch offset requires 0 MOD 4 alignment"));
1437 /* Insert the immediate. */
1440 fix
->fx_r_type
= BFD_RELOC_860_PC26
;
1445 insn
|= (val
& 0x3ffffff);
1446 bfd_putl32 (insn
, buf
);
1447 fix
->fx_r_type
= BFD_RELOC_NONE
;
1451 else if (fup
!= OP_NONE
)
1453 as_bad_where (fix
->fx_file
, fix
->fx_line
,
1454 _("Unrecognized fix-up (0x%08lx)"), (unsigned long) fup
);
1459 /* I believe only fix-ups such as ".long .ep.main-main+0xc8000000"
1460 reach here (???). */
1463 fix
->fx_r_type
= BFD_RELOC_32
;
1468 insn
|= (val
& 0xffffffff);
1469 bfd_putl32 (insn
, buf
);
1470 fix
->fx_r_type
= BFD_RELOC_NONE
;
1476 /* Generate a machine dependent reloc from a fixup. */
1478 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
,
1483 reloc
= xmalloc (sizeof (*reloc
));
1484 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
1485 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
1486 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
1487 reloc
->addend
= fixp
->fx_offset
;
1488 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
1492 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
1493 "Cannot represent %s relocation in object file",
1494 bfd_get_reloc_code_name (fixp
->fx_r_type
));
1499 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
1500 of an rs_align_code fragment. */
1503 i860_handle_align (fragS
*fragp
)
1505 /* Instructions are always stored little-endian on the i860. */
1506 static const unsigned char le_nop
[] = { 0x00, 0x00, 0x00, 0xA0 };
1511 if (fragp
->fr_type
!= rs_align_code
)
1514 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
1515 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
1517 /* Make sure we are on a 4-byte boundary, in case someone has been
1518 putting data into a text section. */
1521 int fix
= bytes
& 3;
1524 fragp
->fr_fix
+= fix
;
1527 memcpy (p
, le_nop
, 4);
1531 /* This is called after a user-defined label is seen. We check
1532 if the label has a double colon (valid in Intel syntax mode only),
1533 in which case it should be externalized. */
1536 i860_check_label (symbolS
*labelsym
)
1538 /* At this point, the current line pointer is sitting on the character
1539 just after the first colon on the label. */
1540 if (target_intel_syntax
&& *input_line_pointer
== ':')
1542 S_SET_EXTERNAL (labelsym
);
1543 input_line_pointer
++;