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2006-02-14 Paolo Bonzini <bonzini@gnu.org>
[binutils.git] / gas / config / tc-arm.c
blob4ff2a7d2fc5fe89039fc46018ab9d8831a625541
1 /* tc-arm.c -- Assemble for the ARM
2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
3 2004, 2005
4 Free Software Foundation, Inc.
5 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
6 Modified by David Taylor (dtaylor@armltd.co.uk)
7 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
8 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
9 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
10
11 This file is part of GAS, the GNU Assembler.
12
13 GAS is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 2, or (at your option)
16 any later version.
17
18 GAS is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
22
23 You should have received a copy of the GNU General Public License
24 along with GAS; see the file COPYING. If not, write to the Free
25 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
26 02110-1301, USA. */
27
28 #include <string.h>
29 #define NO_RELOC 0
30 #include "as.h"
31 #include "safe-ctype.h"
32
33 /* Need TARGET_CPU. */
34 #include "config.h"
35 #include "subsegs.h"
36 #include "obstack.h"
37 #include "symbols.h"
38 #include "listing.h"
39
40 #include "opcode/arm.h"
41
42 #ifdef OBJ_ELF
43 #include "elf/arm.h"
44 #include "dwarf2dbg.h"
45 #include "dw2gencfi.h"
46 #endif
47
48 /* XXX Set this to 1 after the next binutils release. */
49 #define WARN_DEPRECATED 0
50
51 #ifdef OBJ_ELF
52 /* Must be at least the size of the largest unwind opcode (currently two). */
53 #define ARM_OPCODE_CHUNK_SIZE 8
54
55 /* This structure holds the unwinding state. */
56
57 static struct
58 {
59 symbolS * proc_start;
60 symbolS * table_entry;
61 symbolS * personality_routine;
62 int personality_index;
63 /* The segment containing the function. */
64 segT saved_seg;
65 subsegT saved_subseg;
66 /* Opcodes generated from this function. */
67 unsigned char * opcodes;
68 int opcode_count;
69 int opcode_alloc;
70 /* The number of bytes pushed to the stack. */
71 offsetT frame_size;
72 /* We don't add stack adjustment opcodes immediately so that we can merge
73 multiple adjustments. We can also omit the final adjustment
74 when using a frame pointer. */
75 offsetT pending_offset;
76 /* These two fields are set by both unwind_movsp and unwind_setfp. They
77 hold the reg+offset to use when restoring sp from a frame pointer. */
78 offsetT fp_offset;
79 int fp_reg;
80 /* Nonzero if an unwind_setfp directive has been seen. */
81 unsigned fp_used:1;
82 /* Nonzero if the last opcode restores sp from fp_reg. */
83 unsigned sp_restored:1;
84 } unwind;
85
86 /* Bit N indicates that an R_ARM_NONE relocation has been output for
87 __aeabi_unwind_cpp_prN already if set. This enables dependencies to be
88 emitted only once per section, to save unnecessary bloat. */
89 static unsigned int marked_pr_dependency = 0;
90
91 #endif /* OBJ_ELF */
92
93 enum arm_float_abi
94 {
95 ARM_FLOAT_ABI_HARD,
96 ARM_FLOAT_ABI_SOFTFP,
97 ARM_FLOAT_ABI_SOFT
98 };
99
100 /* Types of processor to assemble for. */
101 #ifndef CPU_DEFAULT
102 #if defined __XSCALE__
103 #define CPU_DEFAULT ARM_ARCH_XSCALE
104 #else
105 #if defined __thumb__
106 #define CPU_DEFAULT ARM_ARCH_V5T
107 #endif
108 #endif
109 #endif
110
111 #ifndef FPU_DEFAULT
112 # ifdef TE_LINUX
113 # define FPU_DEFAULT FPU_ARCH_FPA
114 # elif defined (TE_NetBSD)
115 # ifdef OBJ_ELF
116 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
117 # else
118 /* Legacy a.out format. */
119 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
120 # endif
121 # elif defined (TE_VXWORKS)
122 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
123 # else
124 /* For backwards compatibility, default to FPA. */
125 # define FPU_DEFAULT FPU_ARCH_FPA
126 # endif
127 #endif /* ifndef FPU_DEFAULT */
128
129 #define streq(a, b) (strcmp (a, b) == 0)
130
131 static arm_feature_set cpu_variant;
132 static arm_feature_set arm_arch_used;
133 static arm_feature_set thumb_arch_used;
134
135 /* Flags stored in private area of BFD structure. */
136 static int uses_apcs_26 = FALSE;
137 static int atpcs = FALSE;
138 static int support_interwork = FALSE;
139 static int uses_apcs_float = FALSE;
140 static int pic_code = FALSE;
141
142 /* Variables that we set while parsing command-line options. Once all
143 options have been read we re-process these values to set the real
144 assembly flags. */
145 static const arm_feature_set *legacy_cpu = NULL;
146 static const arm_feature_set *legacy_fpu = NULL;
147
148 static const arm_feature_set *mcpu_cpu_opt = NULL;
149 static const arm_feature_set *mcpu_fpu_opt = NULL;
150 static const arm_feature_set *march_cpu_opt = NULL;
151 static const arm_feature_set *march_fpu_opt = NULL;
152 static const arm_feature_set *mfpu_opt = NULL;
153
154 /* Constants for known architecture features. */
155 static const arm_feature_set fpu_default = FPU_DEFAULT;
156 static const arm_feature_set fpu_arch_vfp_v1 = FPU_ARCH_VFP_V1;
157 static const arm_feature_set fpu_arch_vfp_v2 = FPU_ARCH_VFP_V2;
158 static const arm_feature_set fpu_arch_fpa = FPU_ARCH_FPA;
159 static const arm_feature_set fpu_any_hard = FPU_ANY_HARD;
160 static const arm_feature_set fpu_arch_maverick = FPU_ARCH_MAVERICK;
161 static const arm_feature_set fpu_endian_pure = FPU_ARCH_ENDIAN_PURE;
162
163 #ifdef CPU_DEFAULT
164 static const arm_feature_set cpu_default = CPU_DEFAULT;
165 #endif
166
167 static const arm_feature_set arm_ext_v1 = ARM_FEATURE (ARM_EXT_V1, 0);
168 static const arm_feature_set arm_ext_v2 = ARM_FEATURE (ARM_EXT_V1, 0);
169 static const arm_feature_set arm_ext_v2s = ARM_FEATURE (ARM_EXT_V2S, 0);
170 static const arm_feature_set arm_ext_v3 = ARM_FEATURE (ARM_EXT_V3, 0);
171 static const arm_feature_set arm_ext_v3m = ARM_FEATURE (ARM_EXT_V3M, 0);
172 static const arm_feature_set arm_ext_v4 = ARM_FEATURE (ARM_EXT_V4, 0);
173 static const arm_feature_set arm_ext_v4t = ARM_FEATURE (ARM_EXT_V4T, 0);
174 static const arm_feature_set arm_ext_v5 = ARM_FEATURE (ARM_EXT_V5, 0);
175 static const arm_feature_set arm_ext_v4t_5 =
176 ARM_FEATURE (ARM_EXT_V4T | ARM_EXT_V5, 0);
177 static const arm_feature_set arm_ext_v5t = ARM_FEATURE (ARM_EXT_V5T, 0);
178 static const arm_feature_set arm_ext_v5e = ARM_FEATURE (ARM_EXT_V5E, 0);
179 static const arm_feature_set arm_ext_v5exp = ARM_FEATURE (ARM_EXT_V5ExP, 0);
180 static const arm_feature_set arm_ext_v5j = ARM_FEATURE (ARM_EXT_V5J, 0);
181 static const arm_feature_set arm_ext_v6 = ARM_FEATURE (ARM_EXT_V6, 0);
182 static const arm_feature_set arm_ext_v6k = ARM_FEATURE (ARM_EXT_V6K, 0);
183 static const arm_feature_set arm_ext_v6z = ARM_FEATURE (ARM_EXT_V6Z, 0);
184 static const arm_feature_set arm_ext_v6t2 = ARM_FEATURE (ARM_EXT_V6T2, 0);
185
186 static const arm_feature_set arm_arch_any = ARM_ANY;
187 static const arm_feature_set arm_arch_full = ARM_FEATURE (-1, -1);
188 static const arm_feature_set arm_arch_t2 = ARM_ARCH_THUMB2;
189 static const arm_feature_set arm_arch_none = ARM_ARCH_NONE;
190
191 static const arm_feature_set arm_cext_iwmmxt =
192 ARM_FEATURE (0, ARM_CEXT_IWMMXT);
193 static const arm_feature_set arm_cext_xscale =
194 ARM_FEATURE (0, ARM_CEXT_XSCALE);
195 static const arm_feature_set arm_cext_maverick =
196 ARM_FEATURE (0, ARM_CEXT_MAVERICK);
197 static const arm_feature_set fpu_fpa_ext_v1 = ARM_FEATURE (0, FPU_FPA_EXT_V1);
198 static const arm_feature_set fpu_fpa_ext_v2 = ARM_FEATURE (0, FPU_FPA_EXT_V2);
199 static const arm_feature_set fpu_vfp_ext_v1xd =
200 ARM_FEATURE (0, FPU_VFP_EXT_V1xD);
201 static const arm_feature_set fpu_vfp_ext_v1 = ARM_FEATURE (0, FPU_VFP_EXT_V1);
202 static const arm_feature_set fpu_vfp_ext_v2 = ARM_FEATURE (0, FPU_VFP_EXT_V2);
203
204 static int mfloat_abi_opt = -1;
205 /* Record user cpu selection for object attributes. */
206 static arm_feature_set selected_cpu = ARM_ARCH_NONE;
207 /* Must be long enough to hold any of the names in arm_cpus. */
208 static char selected_cpu_name[16];
209 #ifdef OBJ_ELF
210 # ifdef EABI_DEFAULT
211 static int meabi_flags = EABI_DEFAULT;
212 # else
213 static int meabi_flags = EF_ARM_EABI_UNKNOWN;
214 # endif
215 #endif
216
217 #ifdef OBJ_ELF
218 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
219 symbolS * GOT_symbol;
220 #endif
221
222 /* 0: assemble for ARM,
223 1: assemble for Thumb,
224 2: assemble for Thumb even though target CPU does not support thumb
225 instructions. */
226 static int thumb_mode = 0;
227
228 /* If unified_syntax is true, we are processing the new unified
229 ARM/Thumb syntax. Important differences from the old ARM mode:
230
231 - Immediate operands do not require a # prefix.
232 - Conditional affixes always appear at the end of the
233 instruction. (For backward compatibility, those instructions
234 that formerly had them in the middle, continue to accept them
235 there.)
236 - The IT instruction may appear, and if it does is validated
237 against subsequent conditional affixes. It does not generate
238 machine code.
239
240 Important differences from the old Thumb mode:
241
242 - Immediate operands do not require a # prefix.
243 - Most of the V6T2 instructions are only available in unified mode.
244 - The .N and .W suffixes are recognized and honored (it is an error
245 if they cannot be honored).
246 - All instructions set the flags if and only if they have an 's' affix.
247 - Conditional affixes may be used. They are validated against
248 preceding IT instructions. Unlike ARM mode, you cannot use a
249 conditional affix except in the scope of an IT instruction. */
250
251 static bfd_boolean unified_syntax = FALSE;
252
253 struct arm_it
254 {
255 const char * error;
256 unsigned long instruction;
257 int size;
258 int size_req;
259 int cond;
260 /* Set to the opcode if the instruction needs relaxation.
261 Zero if the instruction is not relaxed. */
262 unsigned long relax;
263 struct
264 {
265 bfd_reloc_code_real_type type;
266 expressionS exp;
267 int pc_rel;
268 } reloc;
269
270 struct
271 {
272 unsigned reg;
273 signed int imm;
274 unsigned present : 1; /* Operand present. */
275 unsigned isreg : 1; /* Operand was a register. */
276 unsigned immisreg : 1; /* .imm field is a second register. */
277 unsigned hasreloc : 1; /* Operand has relocation suffix. */
278 unsigned writeback : 1; /* Operand has trailing ! */
279 unsigned preind : 1; /* Preindexed address. */
280 unsigned postind : 1; /* Postindexed address. */
281 unsigned negative : 1; /* Index register was negated. */
282 unsigned shifted : 1; /* Shift applied to operation. */
283 unsigned shift_kind : 3; /* Shift operation (enum shift_kind). */
284 } operands[6];
285 };
286
287 static struct arm_it inst;
288
289 #define NUM_FLOAT_VALS 8
290
291 const char * fp_const[] =
292 {
293 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
294 };
295
296 /* Number of littlenums required to hold an extended precision number. */
297 #define MAX_LITTLENUMS 6
298
299 LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS];
300
301 #define FAIL (-1)
302 #define SUCCESS (0)
303
304 #define SUFF_S 1
305 #define SUFF_D 2
306 #define SUFF_E 3
307 #define SUFF_P 4
308
309 #define CP_T_X 0x00008000
310 #define CP_T_Y 0x00400000
311
312 #define CONDS_BIT 0x00100000
313 #define LOAD_BIT 0x00100000
314
315 #define DOUBLE_LOAD_FLAG 0x00000001
316
317 struct asm_cond
318 {
319 const char * template;
320 unsigned long value;
321 };
322
323 #define COND_ALWAYS 0xE
324
325 struct asm_psr
326 {
327 const char *template;
328 unsigned long field;
329 };
330
331 /* The bit that distinguishes CPSR and SPSR. */
332 #define SPSR_BIT (1 << 22)
333
334 /* The individual PSR flag bits. */
335 #define PSR_c (1 << 16)
336 #define PSR_x (1 << 17)
337 #define PSR_s (1 << 18)
338 #define PSR_f (1 << 19)
339
340 struct reloc_entry
341 {
342 char *name;
343 bfd_reloc_code_real_type reloc;
344 };
345
346 enum vfp_sp_reg_pos
347 {
348 VFP_REG_Sd, VFP_REG_Sm, VFP_REG_Sn
349 };
350
351 enum vfp_ldstm_type
352 {
353 VFP_LDSTMIA, VFP_LDSTMDB, VFP_LDSTMIAX, VFP_LDSTMDBX
354 };
355
356 /* ARM register categories. This includes coprocessor numbers and various
357 architecture extensions' registers. */
358 enum arm_reg_type
359 {
360 REG_TYPE_RN,
361 REG_TYPE_CP,
362 REG_TYPE_CN,
363 REG_TYPE_FN,
364 REG_TYPE_VFS,
365 REG_TYPE_VFD,
366 REG_TYPE_VFC,
367 REG_TYPE_MVF,
368 REG_TYPE_MVD,
369 REG_TYPE_MVFX,
370 REG_TYPE_MVDX,
371 REG_TYPE_MVAX,
372 REG_TYPE_DSPSC,
373 REG_TYPE_MMXWR,
374 REG_TYPE_MMXWC,
375 REG_TYPE_MMXWCG,
376 REG_TYPE_XSCALE,
377 };
378
379 /* Structure for a hash table entry for a register. */
380 struct reg_entry
381 {
382 const char *name;
383 unsigned char number;
384 unsigned char type;
385 unsigned char builtin;
386 };
387
388 /* Diagnostics used when we don't get a register of the expected type. */
389 const char *const reg_expected_msgs[] =
390 {
391 N_("ARM register expected"),
392 N_("bad or missing co-processor number"),
393 N_("co-processor register expected"),
394 N_("FPA register expected"),
395 N_("VFP single precision register expected"),
396 N_("VFP double precision register expected"),
397 N_("VFP system register expected"),
398 N_("Maverick MVF register expected"),
399 N_("Maverick MVD register expected"),
400 N_("Maverick MVFX register expected"),
401 N_("Maverick MVDX register expected"),
402 N_("Maverick MVAX register expected"),
403 N_("Maverick DSPSC register expected"),
404 N_("iWMMXt data register expected"),
405 N_("iWMMXt control register expected"),
406 N_("iWMMXt scalar register expected"),
407 N_("XScale accumulator register expected"),
408 };
409
410 /* Some well known registers that we refer to directly elsewhere. */
411 #define REG_SP 13
412 #define REG_LR 14
413 #define REG_PC 15
414
415 /* ARM instructions take 4bytes in the object file, Thumb instructions
416 take 2: */
417 #define INSN_SIZE 4
418
419 struct asm_opcode
420 {
421 /* Basic string to match. */
422 const char *template;
423
424 /* Parameters to instruction. */
425 unsigned char operands[8];
426
427 /* Conditional tag - see opcode_lookup. */
428 unsigned int tag : 4;
429
430 /* Basic instruction code. */
431 unsigned int avalue : 28;
432
433 /* Thumb-format instruction code. */
434 unsigned int tvalue;
435
436 /* Which architecture variant provides this instruction. */
437 const arm_feature_set *avariant;
438 const arm_feature_set *tvariant;
439
440 /* Function to call to encode instruction in ARM format. */
441 void (* aencode) (void);
442
443 /* Function to call to encode instruction in Thumb format. */
444 void (* tencode) (void);
445 };
446
447 /* Defines for various bits that we will want to toggle. */
448 #define INST_IMMEDIATE 0x02000000
449 #define OFFSET_REG 0x02000000
450 #define HWOFFSET_IMM 0x00400000
451 #define SHIFT_BY_REG 0x00000010
452 #define PRE_INDEX 0x01000000
453 #define INDEX_UP 0x00800000
454 #define WRITE_BACK 0x00200000
455 #define LDM_TYPE_2_OR_3 0x00400000
456
457 #define LITERAL_MASK 0xf000f000
458 #define OPCODE_MASK 0xfe1fffff
459 #define V4_STR_BIT 0x00000020
460
461 #define DATA_OP_SHIFT 21
462
463 #define T2_OPCODE_MASK 0xfe1fffff
464 #define T2_DATA_OP_SHIFT 21
465
466 /* Codes to distinguish the arithmetic instructions. */
467 #define OPCODE_AND 0
468 #define OPCODE_EOR 1
469 #define OPCODE_SUB 2
470 #define OPCODE_RSB 3
471 #define OPCODE_ADD 4
472 #define OPCODE_ADC 5
473 #define OPCODE_SBC 6
474 #define OPCODE_RSC 7
475 #define OPCODE_TST 8
476 #define OPCODE_TEQ 9
477 #define OPCODE_CMP 10
478 #define OPCODE_CMN 11
479 #define OPCODE_ORR 12
480 #define OPCODE_MOV 13
481 #define OPCODE_BIC 14
482 #define OPCODE_MVN 15
483
484 #define T2_OPCODE_AND 0
485 #define T2_OPCODE_BIC 1
486 #define T2_OPCODE_ORR 2
487 #define T2_OPCODE_ORN 3
488 #define T2_OPCODE_EOR 4
489 #define T2_OPCODE_ADD 8
490 #define T2_OPCODE_ADC 10
491 #define T2_OPCODE_SBC 11
492 #define T2_OPCODE_SUB 13
493 #define T2_OPCODE_RSB 14
494
495 #define T_OPCODE_MUL 0x4340
496 #define T_OPCODE_TST 0x4200
497 #define T_OPCODE_CMN 0x42c0
498 #define T_OPCODE_NEG 0x4240
499 #define T_OPCODE_MVN 0x43c0
500
501 #define T_OPCODE_ADD_R3 0x1800
502 #define T_OPCODE_SUB_R3 0x1a00
503 #define T_OPCODE_ADD_HI 0x4400
504 #define T_OPCODE_ADD_ST 0xb000
505 #define T_OPCODE_SUB_ST 0xb080
506 #define T_OPCODE_ADD_SP 0xa800
507 #define T_OPCODE_ADD_PC 0xa000
508 #define T_OPCODE_ADD_I8 0x3000
509 #define T_OPCODE_SUB_I8 0x3800
510 #define T_OPCODE_ADD_I3 0x1c00
511 #define T_OPCODE_SUB_I3 0x1e00
512
513 #define T_OPCODE_ASR_R 0x4100
514 #define T_OPCODE_LSL_R 0x4080
515 #define T_OPCODE_LSR_R 0x40c0
516 #define T_OPCODE_ROR_R 0x41c0
517 #define T_OPCODE_ASR_I 0x1000
518 #define T_OPCODE_LSL_I 0x0000
519 #define T_OPCODE_LSR_I 0x0800
520
521 #define T_OPCODE_MOV_I8 0x2000
522 #define T_OPCODE_CMP_I8 0x2800
523 #define T_OPCODE_CMP_LR 0x4280
524 #define T_OPCODE_MOV_HR 0x4600
525 #define T_OPCODE_CMP_HR 0x4500
526
527 #define T_OPCODE_LDR_PC 0x4800
528 #define T_OPCODE_LDR_SP 0x9800
529 #define T_OPCODE_STR_SP 0x9000
530 #define T_OPCODE_LDR_IW 0x6800
531 #define T_OPCODE_STR_IW 0x6000
532 #define T_OPCODE_LDR_IH 0x8800
533 #define T_OPCODE_STR_IH 0x8000
534 #define T_OPCODE_LDR_IB 0x7800
535 #define T_OPCODE_STR_IB 0x7000
536 #define T_OPCODE_LDR_RW 0x5800
537 #define T_OPCODE_STR_RW 0x5000
538 #define T_OPCODE_LDR_RH 0x5a00
539 #define T_OPCODE_STR_RH 0x5200
540 #define T_OPCODE_LDR_RB 0x5c00
541 #define T_OPCODE_STR_RB 0x5400
542
543 #define T_OPCODE_PUSH 0xb400
544 #define T_OPCODE_POP 0xbc00
545
546 #define T_OPCODE_BRANCH 0xe000
547
548 #define THUMB_SIZE 2 /* Size of thumb instruction. */
549 #define THUMB_PP_PC_LR 0x0100
550 #define THUMB_LOAD_BIT 0x0800
551
552 #define BAD_ARGS _("bad arguments to instruction")
553 #define BAD_PC _("r15 not allowed here")
554 #define BAD_COND _("instruction cannot be conditional")
555 #define BAD_OVERLAP _("registers may not be the same")
556 #define BAD_HIREG _("lo register required")
557 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
558 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
559
560 static struct hash_control *arm_ops_hsh;
561 static struct hash_control *arm_cond_hsh;
562 static struct hash_control *arm_shift_hsh;
563 static struct hash_control *arm_psr_hsh;
564 static struct hash_control *arm_reg_hsh;
565 static struct hash_control *arm_reloc_hsh;
566
567 /* Stuff needed to resolve the label ambiguity
568 As:
569 ...
570 label: <insn>
571 may differ from:
572 ...
573 label:
574 <insn>
575 */
576
577 symbolS * last_label_seen;
578 static int label_is_thumb_function_name = FALSE;
579 \f
580 /* Literal pool structure. Held on a per-section
581 and per-sub-section basis. */
582
583 #define MAX_LITERAL_POOL_SIZE 1024
584 typedef struct literal_pool
585 {
586 expressionS literals [MAX_LITERAL_POOL_SIZE];
587 unsigned int next_free_entry;
588 unsigned int id;
589 symbolS * symbol;
590 segT section;
591 subsegT sub_section;
592 struct literal_pool * next;
593 } literal_pool;
594
595 /* Pointer to a linked list of literal pools. */
596 literal_pool * list_of_pools = NULL;
597
598 /* State variables for IT block handling. */
599 static bfd_boolean current_it_mask = 0;
600 static int current_cc;
601
602 \f
603 /* Pure syntax. */
604
605 /* This array holds the chars that always start a comment. If the
606 pre-processor is disabled, these aren't very useful. */
607 const char comment_chars[] = "@";
608
609 /* This array holds the chars that only start a comment at the beginning of
610 a line. If the line seems to have the form '# 123 filename'
611 .line and .file directives will appear in the pre-processed output. */
612 /* Note that input_file.c hand checks for '#' at the beginning of the
613 first line of the input file. This is because the compiler outputs
614 #NO_APP at the beginning of its output. */
615 /* Also note that comments like this one will always work. */
616 const char line_comment_chars[] = "#";
617
618 const char line_separator_chars[] = ";";
619
620 /* Chars that can be used to separate mant
621 from exp in floating point numbers. */
622 const char EXP_CHARS[] = "eE";
623
624 /* Chars that mean this number is a floating point constant. */
625 /* As in 0f12.456 */
626 /* or 0d1.2345e12 */
627
628 const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
629
630 /* Prefix characters that indicate the start of an immediate
631 value. */
632 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
633
634 /* Separator character handling. */
635
636 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
637
638 static inline int
639 skip_past_char (char ** str, char c)
640 {
641 if (**str == c)
642 {
643 (*str)++;
644 return SUCCESS;
645 }
646 else
647 return FAIL;
648 }
649 #define skip_past_comma(str) skip_past_char (str, ',')
650
651 /* Arithmetic expressions (possibly involving symbols). */
652
653 /* Return TRUE if anything in the expression is a bignum. */
654
655 static int
656 walk_no_bignums (symbolS * sp)
657 {
658 if (symbol_get_value_expression (sp)->X_op == O_big)
659 return 1;
660
661 if (symbol_get_value_expression (sp)->X_add_symbol)
662 {
663 return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol)
664 || (symbol_get_value_expression (sp)->X_op_symbol
665 && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol)));
666 }
667
668 return 0;
669 }
670
671 static int in_my_get_expression = 0;
672
673 /* Third argument to my_get_expression. */
674 #define GE_NO_PREFIX 0
675 #define GE_IMM_PREFIX 1
676 #define GE_OPT_PREFIX 2
677
678 static int
679 my_get_expression (expressionS * ep, char ** str, int prefix_mode)
680 {
681 char * save_in;
682 segT seg;
683
684 /* In unified syntax, all prefixes are optional. */
685 if (unified_syntax)
686 prefix_mode = GE_OPT_PREFIX;
687
688 switch (prefix_mode)
689 {
690 case GE_NO_PREFIX: break;
691 case GE_IMM_PREFIX:
692 if (!is_immediate_prefix (**str))
693 {
694 inst.error = _("immediate expression requires a # prefix");
695 return FAIL;
696 }
697 (*str)++;
698 break;
699 case GE_OPT_PREFIX:
700 if (is_immediate_prefix (**str))
701 (*str)++;
702 break;
703 default: abort ();
704 }
705
706 memset (ep, 0, sizeof (expressionS));
707
708 save_in = input_line_pointer;
709 input_line_pointer = *str;
710 in_my_get_expression = 1;
711 seg = expression (ep);
712 in_my_get_expression = 0;
713
714 if (ep->X_op == O_illegal)
715 {
716 /* We found a bad expression in md_operand(). */
717 *str = input_line_pointer;
718 input_line_pointer = save_in;
719 if (inst.error == NULL)
720 inst.error = _("bad expression");
721 return 1;
722 }
723
724 #ifdef OBJ_AOUT
725 if (seg != absolute_section
726 && seg != text_section
727 && seg != data_section
728 && seg != bss_section
729 && seg != undefined_section)
730 {
731 inst.error = _("bad segment");
732 *str = input_line_pointer;
733 input_line_pointer = save_in;
734 return 1;
735 }
736 #endif
737
738 /* Get rid of any bignums now, so that we don't generate an error for which
739 we can't establish a line number later on. Big numbers are never valid
740 in instructions, which is where this routine is always called. */
741 if (ep->X_op == O_big
742 || (ep->X_add_symbol
743 && (walk_no_bignums (ep->X_add_symbol)
744 || (ep->X_op_symbol
745 && walk_no_bignums (ep->X_op_symbol)))))
746 {
747 inst.error = _("invalid constant");
748 *str = input_line_pointer;
749 input_line_pointer = save_in;
750 return 1;
751 }
752
753 *str = input_line_pointer;
754 input_line_pointer = save_in;
755 return 0;
756 }
757
758 /* Turn a string in input_line_pointer into a floating point constant
759 of type TYPE, and store the appropriate bytes in *LITP. The number
760 of LITTLENUMS emitted is stored in *SIZEP. An error message is
761 returned, or NULL on OK.
762
763 Note that fp constants aren't represent in the normal way on the ARM.
764 In big endian mode, things are as expected. However, in little endian
765 mode fp constants are big-endian word-wise, and little-endian byte-wise
766 within the words. For example, (double) 1.1 in big endian mode is
767 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
768 the byte sequence 99 99 f1 3f 9a 99 99 99.
769
770 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
771
772 char *
773 md_atof (int type, char * litP, int * sizeP)
774 {
775 int prec;
776 LITTLENUM_TYPE words[MAX_LITTLENUMS];
777 char *t;
778 int i;
779
780 switch (type)
781 {
782 case 'f':
783 case 'F':
784 case 's':
785 case 'S':
786 prec = 2;
787 break;
788
789 case 'd':
790 case 'D':
791 case 'r':
792 case 'R':
793 prec = 4;
794 break;
795
796 case 'x':
797 case 'X':
798 prec = 6;
799 break;
800
801 case 'p':
802 case 'P':
803 prec = 6;
804 break;
805
806 default:
807 *sizeP = 0;
808 return _("bad call to MD_ATOF()");
809 }
810
811 t = atof_ieee (input_line_pointer, type, words);
812 if (t)
813 input_line_pointer = t;
814 *sizeP = prec * 2;
815
816 if (target_big_endian)
817 {
818 for (i = 0; i < prec; i++)
819 {
820 md_number_to_chars (litP, (valueT) words[i], 2);
821 litP += 2;
822 }
823 }
824 else
825 {
826 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
827 for (i = prec - 1; i >= 0; i--)
828 {
829 md_number_to_chars (litP, (valueT) words[i], 2);
830 litP += 2;
831 }
832 else
833 /* For a 4 byte float the order of elements in `words' is 1 0.
834 For an 8 byte float the order is 1 0 3 2. */
835 for (i = 0; i < prec; i += 2)
836 {
837 md_number_to_chars (litP, (valueT) words[i + 1], 2);
838 md_number_to_chars (litP + 2, (valueT) words[i], 2);
839 litP += 4;
840 }
841 }
842
843 return 0;
844 }
845
846 /* We handle all bad expressions here, so that we can report the faulty
847 instruction in the error message. */
848 void
849 md_operand (expressionS * expr)
850 {
851 if (in_my_get_expression)
852 expr->X_op = O_illegal;
853 }
854
855 /* Immediate values. */
856
857 /* Generic immediate-value read function for use in directives.
858 Accepts anything that 'expression' can fold to a constant.
859 *val receives the number. */
860 #ifdef OBJ_ELF
861 static int
862 immediate_for_directive (int *val)
863 {
864 expressionS exp;
865 exp.X_op = O_illegal;
866
867 if (is_immediate_prefix (*input_line_pointer))
868 {
869 input_line_pointer++;
870 expression (&exp);
871 }
872
873 if (exp.X_op != O_constant)
874 {
875 as_bad (_("expected #constant"));
876 ignore_rest_of_line ();
877 return FAIL;
878 }
879 *val = exp.X_add_number;
880 return SUCCESS;
881 }
882 #endif
883
884 /* Register parsing. */
885
886 /* Generic register parser. CCP points to what should be the
887 beginning of a register name. If it is indeed a valid register
888 name, advance CCP over it and return the reg_entry structure;
889 otherwise return NULL. Does not issue diagnostics. */
890
891 static struct reg_entry *
892 arm_reg_parse_multi (char **ccp)
893 {
894 char *start = *ccp;
895 char *p;
896 struct reg_entry *reg;
897
898 #ifdef REGISTER_PREFIX
899 if (*start != REGISTER_PREFIX)
900 return NULL;
901 start++;
902 #endif
903 #ifdef OPTIONAL_REGISTER_PREFIX
904 if (*start == OPTIONAL_REGISTER_PREFIX)
905 start++;
906 #endif
907
908 p = start;
909 if (!ISALPHA (*p) || !is_name_beginner (*p))
910 return NULL;
911
912 do
913 p++;
914 while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_');
915
916 reg = (struct reg_entry *) hash_find_n (arm_reg_hsh, start, p - start);
917
918 if (!reg)
919 return NULL;
920
921 *ccp = p;
922 return reg;
923 }
924
925 /* As above, but the register must be of type TYPE, and the return
926 value is the register number or FAIL. */
927
928 static int
929 arm_reg_parse (char **ccp, enum arm_reg_type type)
930 {
931 char *start = *ccp;
932 struct reg_entry *reg = arm_reg_parse_multi (ccp);
933
934 if (reg && reg->type == type)
935 return reg->number;
936
937 /* Alternative syntaxes are accepted for a few register classes. */
938 switch (type)
939 {
940 case REG_TYPE_MVF:
941 case REG_TYPE_MVD:
942 case REG_TYPE_MVFX:
943 case REG_TYPE_MVDX:
944 /* Generic coprocessor register names are allowed for these. */
945 if (reg && reg->type == REG_TYPE_CN)
946 return reg->number;
947 break;
948
949 case REG_TYPE_CP:
950 /* For backward compatibility, a bare number is valid here. */
951 {
952 unsigned long processor = strtoul (start, ccp, 10);
953 if (*ccp != start && processor <= 15)
954 return processor;
955 }
956
957 case REG_TYPE_MMXWC:
958 /* WC includes WCG. ??? I'm not sure this is true for all
959 instructions that take WC registers. */
960 if (reg && reg->type == REG_TYPE_MMXWCG)
961 return reg->number;
962 break;
963
964 default:
965 break;
966 }
967
968 *ccp = start;
969 return FAIL;
970 }
971
972 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
973 static long
974 parse_reg_list (char ** strp)
975 {
976 char * str = * strp;
977 long range = 0;
978 int another_range;
979
980 /* We come back here if we get ranges concatenated by '+' or '|'. */
981 do
982 {
983 another_range = 0;
984
985 if (*str == '{')
986 {
987 int in_range = 0;
988 int cur_reg = -1;
989
990 str++;
991 do
992 {
993 int reg;
994
995 if ((reg = arm_reg_parse (&str, REG_TYPE_RN)) == FAIL)
996 {
997 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
998 return FAIL;
999 }
1000
1001 if (in_range)
1002 {
1003 int i;
1004
1005 if (reg <= cur_reg)
1006 {
1007 inst.error = _("bad range in register list");
1008 return FAIL;
1009 }
1010
1011 for (i = cur_reg + 1; i < reg; i++)
1012 {
1013 if (range & (1 << i))
1014 as_tsktsk
1015 (_("Warning: duplicated register (r%d) in register list"),
1016 i);
1017 else
1018 range |= 1 << i;
1019 }
1020 in_range = 0;
1021 }
1022
1023 if (range & (1 << reg))
1024 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1025 reg);
1026 else if (reg <= cur_reg)
1027 as_tsktsk (_("Warning: register range not in ascending order"));
1028
1029 range |= 1 << reg;
1030 cur_reg = reg;
1031 }
1032 while (skip_past_comma (&str) != FAIL
1033 || (in_range = 1, *str++ == '-'));
1034 str--;
1035
1036 if (*str++ != '}')
1037 {
1038 inst.error = _("missing `}'");
1039 return FAIL;
1040 }
1041 }
1042 else
1043 {
1044 expressionS expr;
1045
1046 if (my_get_expression (&expr, &str, GE_NO_PREFIX))
1047 return FAIL;
1048
1049 if (expr.X_op == O_constant)
1050 {
1051 if (expr.X_add_number
1052 != (expr.X_add_number & 0x0000ffff))
1053 {
1054 inst.error = _("invalid register mask");
1055 return FAIL;
1056 }
1057
1058 if ((range & expr.X_add_number) != 0)
1059 {
1060 int regno = range & expr.X_add_number;
1061
1062 regno &= -regno;
1063 regno = (1 << regno) - 1;
1064 as_tsktsk
1065 (_("Warning: duplicated register (r%d) in register list"),
1066 regno);
1067 }
1068
1069 range |= expr.X_add_number;
1070 }
1071 else
1072 {
1073 if (inst.reloc.type != 0)
1074 {
1075 inst.error = _("expression too complex");
1076 return FAIL;
1077 }
1078
1079 memcpy (&inst.reloc.exp, &expr, sizeof (expressionS));
1080 inst.reloc.type = BFD_RELOC_ARM_MULTI;
1081 inst.reloc.pc_rel = 0;
1082 }
1083 }
1084
1085 if (*str == '|' || *str == '+')
1086 {
1087 str++;
1088 another_range = 1;
1089 }
1090 }
1091 while (another_range);
1092
1093 *strp = str;
1094 return range;
1095 }
1096
1097 /* Parse a VFP register list. If the string is invalid return FAIL.
1098 Otherwise return the number of registers, and set PBASE to the first
1099 register. Double precision registers are matched if DP is nonzero. */
1100
1101 static int
1102 parse_vfp_reg_list (char **str, unsigned int *pbase, int dp)
1103 {
1104 int base_reg;
1105 int new_base;
1106 int regtype;
1107 int max_regs;
1108 int count = 0;
1109 int warned = 0;
1110 unsigned long mask = 0;
1111 int i;
1112
1113 if (**str != '{')
1114 return FAIL;
1115
1116 (*str)++;
1117
1118 if (dp)
1119 {
1120 regtype = REG_TYPE_VFD;
1121 max_regs = 16;
1122 }
1123 else
1124 {
1125 regtype = REG_TYPE_VFS;
1126 max_regs = 32;
1127 }
1128
1129 base_reg = max_regs;
1130
1131 do
1132 {
1133 new_base = arm_reg_parse (str, regtype);
1134 if (new_base == FAIL)
1135 {
1136 inst.error = gettext (reg_expected_msgs[regtype]);
1137 return FAIL;
1138 }
1139
1140 if (new_base < base_reg)
1141 base_reg = new_base;
1142
1143 if (mask & (1 << new_base))
1144 {
1145 inst.error = _("invalid register list");
1146 return FAIL;
1147 }
1148
1149 if ((mask >> new_base) != 0 && ! warned)
1150 {
1151 as_tsktsk (_("register list not in ascending order"));
1152 warned = 1;
1153 }
1154
1155 mask |= 1 << new_base;
1156 count++;
1157
1158 if (**str == '-') /* We have the start of a range expression */
1159 {
1160 int high_range;
1161
1162 (*str)++;
1163
1164 if ((high_range = arm_reg_parse (str, regtype)) == FAIL)
1165 {
1166 inst.error = gettext (reg_expected_msgs[regtype]);
1167 return FAIL;
1168 }
1169
1170 if (high_range <= new_base)
1171 {
1172 inst.error = _("register range not in ascending order");
1173 return FAIL;
1174 }
1175
1176 for (new_base++; new_base <= high_range; new_base++)
1177 {
1178 if (mask & (1 << new_base))
1179 {
1180 inst.error = _("invalid register list");
1181 return FAIL;
1182 }
1183
1184 mask |= 1 << new_base;
1185 count++;
1186 }
1187 }
1188 }
1189 while (skip_past_comma (str) != FAIL);
1190
1191 (*str)++;
1192
1193 /* Sanity check -- should have raised a parse error above. */
1194 if (count == 0 || count > max_regs)
1195 abort ();
1196
1197 *pbase = base_reg;
1198
1199 /* Final test -- the registers must be consecutive. */
1200 mask >>= base_reg;
1201 for (i = 0; i < count; i++)
1202 {
1203 if ((mask & (1u << i)) == 0)
1204 {
1205 inst.error = _("non-contiguous register range");
1206 return FAIL;
1207 }
1208 }
1209
1210 return count;
1211 }
1212
1213 /* Parse an explicit relocation suffix on an expression. This is
1214 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
1215 arm_reloc_hsh contains no entries, so this function can only
1216 succeed if there is no () after the word. Returns -1 on error,
1217 BFD_RELOC_UNUSED if there wasn't any suffix. */
1218 static int
1219 parse_reloc (char **str)
1220 {
1221 struct reloc_entry *r;
1222 char *p, *q;
1223
1224 if (**str != '(')
1225 return BFD_RELOC_UNUSED;
1226
1227 p = *str + 1;
1228 q = p;
1229
1230 while (*q && *q != ')' && *q != ',')
1231 q++;
1232 if (*q != ')')
1233 return -1;
1234
1235 if ((r = hash_find_n (arm_reloc_hsh, p, q - p)) == NULL)
1236 return -1;
1237
1238 *str = q + 1;
1239 return r->reloc;
1240 }
1241
1242 /* Directives: register aliases. */
1243
1244 static void
1245 insert_reg_alias (char *str, int number, int type)
1246 {
1247 struct reg_entry *new;
1248 const char *name;
1249
1250 if ((new = hash_find (arm_reg_hsh, str)) != 0)
1251 {
1252 if (new->builtin)
1253 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str);
1254
1255 /* Only warn about a redefinition if it's not defined as the
1256 same register. */
1257 else if (new->number != number || new->type != type)
1258 as_warn (_("ignoring redefinition of register alias '%s'"), str);
1259
1260 return;
1261 }
1262
1263 name = xstrdup (str);
1264 new = xmalloc (sizeof (struct reg_entry));
1265
1266 new->name = name;
1267 new->number = number;
1268 new->type = type;
1269 new->builtin = FALSE;
1270
1271 if (hash_insert (arm_reg_hsh, name, (PTR) new))
1272 abort ();
1273 }
1274
1275 /* Look for the .req directive. This is of the form:
1276
1277 new_register_name .req existing_register_name
1278
1279 If we find one, or if it looks sufficiently like one that we want to
1280 handle any error here, return non-zero. Otherwise return zero. */
1281
1282 static int
1283 create_register_alias (char * newname, char *p)
1284 {
1285 struct reg_entry *old;
1286 char *oldname, *nbuf;
1287 size_t nlen;
1288
1289 /* The input scrubber ensures that whitespace after the mnemonic is
1290 collapsed to single spaces. */
1291 oldname = p;
1292 if (strncmp (oldname, " .req ", 6) != 0)
1293 return 0;
1294
1295 oldname += 6;
1296 if (*oldname == '\0')
1297 return 0;
1298
1299 old = hash_find (arm_reg_hsh, oldname);
1300 if (!old)
1301 {
1302 as_warn (_("unknown register '%s' -- .req ignored"), oldname);
1303 return 1;
1304 }
1305
1306 /* If TC_CASE_SENSITIVE is defined, then newname already points to
1307 the desired alias name, and p points to its end. If not, then
1308 the desired alias name is in the global original_case_string. */
1309 #ifdef TC_CASE_SENSITIVE
1310 nlen = p - newname;
1311 #else
1312 newname = original_case_string;
1313 nlen = strlen (newname);
1314 #endif
1315
1316 nbuf = alloca (nlen + 1);
1317 memcpy (nbuf, newname, nlen);
1318 nbuf[nlen] = '\0';
1319
1320 /* Create aliases under the new name as stated; an all-lowercase
1321 version of the new name; and an all-uppercase version of the new
1322 name. */
1323 insert_reg_alias (nbuf, old->number, old->type);
1324
1325 for (p = nbuf; *p; p++)
1326 *p = TOUPPER (*p);
1327
1328 if (strncmp (nbuf, newname, nlen))
1329 insert_reg_alias (nbuf, old->number, old->type);
1330
1331 for (p = nbuf; *p; p++)
1332 *p = TOLOWER (*p);
1333
1334 if (strncmp (nbuf, newname, nlen))
1335 insert_reg_alias (nbuf, old->number, old->type);
1336
1337 return 1;
1338 }
1339
1340 /* Should never be called, as .req goes between the alias and the
1341 register name, not at the beginning of the line. */
1342 static void
1343 s_req (int a ATTRIBUTE_UNUSED)
1344 {
1345 as_bad (_("invalid syntax for .req directive"));
1346 }
1347
1348 /* The .unreq directive deletes an alias which was previously defined
1349 by .req. For example:
1350
1351 my_alias .req r11
1352 .unreq my_alias */
1353
1354 static void
1355 s_unreq (int a ATTRIBUTE_UNUSED)
1356 {
1357 char * name;
1358 char saved_char;
1359
1360 name = input_line_pointer;
1361
1362 while (*input_line_pointer != 0
1363 && *input_line_pointer != ' '
1364 && *input_line_pointer != '\n')
1365 ++input_line_pointer;
1366
1367 saved_char = *input_line_pointer;
1368 *input_line_pointer = 0;
1369
1370 if (!*name)
1371 as_bad (_("invalid syntax for .unreq directive"));
1372 else
1373 {
1374 struct reg_entry *reg = hash_find (arm_reg_hsh, name);
1375
1376 if (!reg)
1377 as_bad (_("unknown register alias '%s'"), name);
1378 else if (reg->builtin)
1379 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
1380 name);
1381 else
1382 {
1383 hash_delete (arm_reg_hsh, name);
1384 free ((char *) reg->name);
1385 free (reg);
1386 }
1387 }
1388
1389 *input_line_pointer = saved_char;
1390 demand_empty_rest_of_line ();
1391 }
1392
1393 /* Directives: Instruction set selection. */
1394
1395 #ifdef OBJ_ELF
1396 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
1397 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
1398 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
1399 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
1400
1401 static enum mstate mapstate = MAP_UNDEFINED;
1402
1403 static void
1404 mapping_state (enum mstate state)
1405 {
1406 symbolS * symbolP;
1407 const char * symname;
1408 int type;
1409
1410 if (mapstate == state)
1411 /* The mapping symbol has already been emitted.
1412 There is nothing else to do. */
1413 return;
1414
1415 mapstate = state;
1416
1417 switch (state)
1418 {
1419 case MAP_DATA:
1420 symname = "$d";
1421 type = BSF_NO_FLAGS;
1422 break;
1423 case MAP_ARM:
1424 symname = "$a";
1425 type = BSF_NO_FLAGS;
1426 break;
1427 case MAP_THUMB:
1428 symname = "$t";
1429 type = BSF_NO_FLAGS;
1430 break;
1431 case MAP_UNDEFINED:
1432 return;
1433 default:
1434 abort ();
1435 }
1436
1437 seg_info (now_seg)->tc_segment_info_data.mapstate = state;
1438
1439 symbolP = symbol_new (symname, now_seg, (valueT) frag_now_fix (), frag_now);
1440 symbol_table_insert (symbolP);
1441 symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL;
1442
1443 switch (state)
1444 {
1445 case MAP_ARM:
1446 THUMB_SET_FUNC (symbolP, 0);
1447 ARM_SET_THUMB (symbolP, 0);
1448 ARM_SET_INTERWORK (symbolP, support_interwork);
1449 break;
1450
1451 case MAP_THUMB:
1452 THUMB_SET_FUNC (symbolP, 1);
1453 ARM_SET_THUMB (symbolP, 1);
1454 ARM_SET_INTERWORK (symbolP, support_interwork);
1455 break;
1456
1457 case MAP_DATA:
1458 default:
1459 return;
1460 }
1461 }
1462 #else
1463 #define mapping_state(x) /* nothing */
1464 #endif
1465
1466 /* Find the real, Thumb encoded start of a Thumb function. */
1467
1468 static symbolS *
1469 find_real_start (symbolS * symbolP)
1470 {
1471 char * real_start;
1472 const char * name = S_GET_NAME (symbolP);
1473 symbolS * new_target;
1474
1475 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
1476 #define STUB_NAME ".real_start_of"
1477
1478 if (name == NULL)
1479 abort ();
1480
1481 /* The compiler may generate BL instructions to local labels because
1482 it needs to perform a branch to a far away location. These labels
1483 do not have a corresponding ".real_start_of" label. We check
1484 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
1485 the ".real_start_of" convention for nonlocal branches. */
1486 if (S_IS_LOCAL (symbolP) || name[0] == '.')
1487 return symbolP;
1488
1489 real_start = ACONCAT ((STUB_NAME, name, NULL));
1490 new_target = symbol_find (real_start);
1491
1492 if (new_target == NULL)
1493 {
1494 as_warn ("Failed to find real start of function: %s\n", name);
1495 new_target = symbolP;
1496 }
1497
1498 return new_target;
1499 }
1500
1501 static void
1502 opcode_select (int width)
1503 {
1504 switch (width)
1505 {
1506 case 16:
1507 if (! thumb_mode)
1508 {
1509 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
1510 as_bad (_("selected processor does not support THUMB opcodes"));
1511
1512 thumb_mode = 1;
1513 /* No need to force the alignment, since we will have been
1514 coming from ARM mode, which is word-aligned. */
1515 record_alignment (now_seg, 1);
1516 }
1517 mapping_state (MAP_THUMB);
1518 break;
1519
1520 case 32:
1521 if (thumb_mode)
1522 {
1523 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
1524 as_bad (_("selected processor does not support ARM opcodes"));
1525
1526 thumb_mode = 0;
1527
1528 if (!need_pass_2)
1529 frag_align (2, 0, 0);
1530
1531 record_alignment (now_seg, 1);
1532 }
1533 mapping_state (MAP_ARM);
1534 break;
1535
1536 default:
1537 as_bad (_("invalid instruction size selected (%d)"), width);
1538 }
1539 }
1540
1541 static void
1542 s_arm (int ignore ATTRIBUTE_UNUSED)
1543 {
1544 opcode_select (32);
1545 demand_empty_rest_of_line ();
1546 }
1547
1548 static void
1549 s_thumb (int ignore ATTRIBUTE_UNUSED)
1550 {
1551 opcode_select (16);
1552 demand_empty_rest_of_line ();
1553 }
1554
1555 static void
1556 s_code (int unused ATTRIBUTE_UNUSED)
1557 {
1558 int temp;
1559
1560 temp = get_absolute_expression ();
1561 switch (temp)
1562 {
1563 case 16:
1564 case 32:
1565 opcode_select (temp);
1566 break;
1567
1568 default:
1569 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp);
1570 }
1571 }
1572
1573 static void
1574 s_force_thumb (int ignore ATTRIBUTE_UNUSED)
1575 {
1576 /* If we are not already in thumb mode go into it, EVEN if
1577 the target processor does not support thumb instructions.
1578 This is used by gcc/config/arm/lib1funcs.asm for example
1579 to compile interworking support functions even if the
1580 target processor should not support interworking. */
1581 if (! thumb_mode)
1582 {
1583 thumb_mode = 2;
1584 record_alignment (now_seg, 1);
1585 }
1586
1587 demand_empty_rest_of_line ();
1588 }
1589
1590 static void
1591 s_thumb_func (int ignore ATTRIBUTE_UNUSED)
1592 {
1593 s_thumb (0);
1594
1595 /* The following label is the name/address of the start of a Thumb function.
1596 We need to know this for the interworking support. */
1597 label_is_thumb_function_name = TRUE;
1598 }
1599
1600 /* Perform a .set directive, but also mark the alias as
1601 being a thumb function. */
1602
1603 static void
1604 s_thumb_set (int equiv)
1605 {
1606 /* XXX the following is a duplicate of the code for s_set() in read.c
1607 We cannot just call that code as we need to get at the symbol that
1608 is created. */
1609 char * name;
1610 char delim;
1611 char * end_name;
1612 symbolS * symbolP;
1613
1614 /* Especial apologies for the random logic:
1615 This just grew, and could be parsed much more simply!
1616 Dean - in haste. */
1617 name = input_line_pointer;
1618 delim = get_symbol_end ();
1619 end_name = input_line_pointer;
1620 *end_name = delim;
1621
1622 if (*input_line_pointer != ',')
1623 {
1624 *end_name = 0;
1625 as_bad (_("expected comma after name \"%s\""), name);
1626 *end_name = delim;
1627 ignore_rest_of_line ();
1628 return;
1629 }
1630
1631 input_line_pointer++;
1632 *end_name = 0;
1633
1634 if (name[0] == '.' && name[1] == '\0')
1635 {
1636 /* XXX - this should not happen to .thumb_set. */
1637 abort ();
1638 }
1639
1640 if ((symbolP = symbol_find (name)) == NULL
1641 && (symbolP = md_undefined_symbol (name)) == NULL)
1642 {
1643 #ifndef NO_LISTING
1644 /* When doing symbol listings, play games with dummy fragments living
1645 outside the normal fragment chain to record the file and line info
1646 for this symbol. */
1647 if (listing & LISTING_SYMBOLS)
1648 {
1649 extern struct list_info_struct * listing_tail;
1650 fragS * dummy_frag = xmalloc (sizeof (fragS));
1651
1652 memset (dummy_frag, 0, sizeof (fragS));
1653 dummy_frag->fr_type = rs_fill;
1654 dummy_frag->line = listing_tail;
1655 symbolP = symbol_new (name, undefined_section, 0, dummy_frag);
1656 dummy_frag->fr_symbol = symbolP;
1657 }
1658 else
1659 #endif
1660 symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag);
1661
1662 #ifdef OBJ_COFF
1663 /* "set" symbols are local unless otherwise specified. */
1664 SF_SET_LOCAL (symbolP);
1665 #endif /* OBJ_COFF */
1666 } /* Make a new symbol. */
1667
1668 symbol_table_insert (symbolP);
1669
1670 * end_name = delim;
1671
1672 if (equiv
1673 && S_IS_DEFINED (symbolP)
1674 && S_GET_SEGMENT (symbolP) != reg_section)
1675 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP));
1676
1677 pseudo_set (symbolP);
1678
1679 demand_empty_rest_of_line ();
1680
1681 /* XXX Now we come to the Thumb specific bit of code. */
1682
1683 THUMB_SET_FUNC (symbolP, 1);
1684 ARM_SET_THUMB (symbolP, 1);
1685 #if defined OBJ_ELF || defined OBJ_COFF
1686 ARM_SET_INTERWORK (symbolP, support_interwork);
1687 #endif
1688 }
1689
1690 /* Directives: Mode selection. */
1691
1692 /* .syntax [unified|divided] - choose the new unified syntax
1693 (same for Arm and Thumb encoding, modulo slight differences in what
1694 can be represented) or the old divergent syntax for each mode. */
1695 static void
1696 s_syntax (int unused ATTRIBUTE_UNUSED)
1697 {
1698 char *name, delim;
1699
1700 name = input_line_pointer;
1701 delim = get_symbol_end ();
1702
1703 if (!strcasecmp (name, "unified"))
1704 unified_syntax = TRUE;
1705 else if (!strcasecmp (name, "divided"))
1706 unified_syntax = FALSE;
1707 else
1708 {
1709 as_bad (_("unrecognized syntax mode \"%s\""), name);
1710 return;
1711 }
1712 *input_line_pointer = delim;
1713 demand_empty_rest_of_line ();
1714 }
1715
1716 /* Directives: sectioning and alignment. */
1717
1718 /* Same as s_align_ptwo but align 0 => align 2. */
1719
1720 static void
1721 s_align (int unused ATTRIBUTE_UNUSED)
1722 {
1723 int temp;
1724 long temp_fill;
1725 long max_alignment = 15;
1726
1727 temp = get_absolute_expression ();
1728 if (temp > max_alignment)
1729 as_bad (_("alignment too large: %d assumed"), temp = max_alignment);
1730 else if (temp < 0)
1731 {
1732 as_bad (_("alignment negative. 0 assumed."));
1733 temp = 0;
1734 }
1735
1736 if (*input_line_pointer == ',')
1737 {
1738 input_line_pointer++;
1739 temp_fill = get_absolute_expression ();
1740 }
1741 else
1742 temp_fill = 0;
1743
1744 if (!temp)
1745 temp = 2;
1746
1747 /* Only make a frag if we HAVE to. */
1748 if (temp && !need_pass_2)
1749 frag_align (temp, (int) temp_fill, 0);
1750 demand_empty_rest_of_line ();
1751
1752 record_alignment (now_seg, temp);
1753 }
1754
1755 static void
1756 s_bss (int ignore ATTRIBUTE_UNUSED)
1757 {
1758 /* We don't support putting frags in the BSS segment, we fake it by
1759 marking in_bss, then looking at s_skip for clues. */
1760 subseg_set (bss_section, 0);
1761 demand_empty_rest_of_line ();
1762 mapping_state (MAP_DATA);
1763 }
1764
1765 static void
1766 s_even (int ignore ATTRIBUTE_UNUSED)
1767 {
1768 /* Never make frag if expect extra pass. */
1769 if (!need_pass_2)
1770 frag_align (1, 0, 0);
1771
1772 record_alignment (now_seg, 1);
1773
1774 demand_empty_rest_of_line ();
1775 }
1776
1777 /* Directives: Literal pools. */
1778
1779 static literal_pool *
1780 find_literal_pool (void)
1781 {
1782 literal_pool * pool;
1783
1784 for (pool = list_of_pools; pool != NULL; pool = pool->next)
1785 {
1786 if (pool->section == now_seg
1787 && pool->sub_section == now_subseg)
1788 break;
1789 }
1790
1791 return pool;
1792 }
1793
1794 static literal_pool *
1795 find_or_make_literal_pool (void)
1796 {
1797 /* Next literal pool ID number. */
1798 static unsigned int latest_pool_num = 1;
1799 literal_pool * pool;
1800
1801 pool = find_literal_pool ();
1802
1803 if (pool == NULL)
1804 {
1805 /* Create a new pool. */
1806 pool = xmalloc (sizeof (* pool));
1807 if (! pool)
1808 return NULL;
1809
1810 pool->next_free_entry = 0;
1811 pool->section = now_seg;
1812 pool->sub_section = now_subseg;
1813 pool->next = list_of_pools;
1814 pool->symbol = NULL;
1815
1816 /* Add it to the list. */
1817 list_of_pools = pool;
1818 }
1819
1820 /* New pools, and emptied pools, will have a NULL symbol. */
1821 if (pool->symbol == NULL)
1822 {
1823 pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section,
1824 (valueT) 0, &zero_address_frag);
1825 pool->id = latest_pool_num ++;
1826 }
1827
1828 /* Done. */
1829 return pool;
1830 }
1831
1832 /* Add the literal in the global 'inst'
1833 structure to the relevent literal pool. */
1834
1835 static int
1836 add_to_lit_pool (void)
1837 {
1838 literal_pool * pool;
1839 unsigned int entry;
1840
1841 pool = find_or_make_literal_pool ();
1842
1843 /* Check if this literal value is already in the pool. */
1844 for (entry = 0; entry < pool->next_free_entry; entry ++)
1845 {
1846 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
1847 && (inst.reloc.exp.X_op == O_constant)
1848 && (pool->literals[entry].X_add_number
1849 == inst.reloc.exp.X_add_number)
1850 && (pool->literals[entry].X_unsigned
1851 == inst.reloc.exp.X_unsigned))
1852 break;
1853
1854 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
1855 && (inst.reloc.exp.X_op == O_symbol)
1856 && (pool->literals[entry].X_add_number
1857 == inst.reloc.exp.X_add_number)
1858 && (pool->literals[entry].X_add_symbol
1859 == inst.reloc.exp.X_add_symbol)
1860 && (pool->literals[entry].X_op_symbol
1861 == inst.reloc.exp.X_op_symbol))
1862 break;
1863 }
1864
1865 /* Do we need to create a new entry? */
1866 if (entry == pool->next_free_entry)
1867 {
1868 if (entry >= MAX_LITERAL_POOL_SIZE)
1869 {
1870 inst.error = _("literal pool overflow");
1871 return FAIL;
1872 }
1873
1874 pool->literals[entry] = inst.reloc.exp;
1875 pool->next_free_entry += 1;
1876 }
1877
1878 inst.reloc.exp.X_op = O_symbol;
1879 inst.reloc.exp.X_add_number = ((int) entry) * 4;
1880 inst.reloc.exp.X_add_symbol = pool->symbol;
1881
1882 return SUCCESS;
1883 }
1884
1885 /* Can't use symbol_new here, so have to create a symbol and then at
1886 a later date assign it a value. Thats what these functions do. */
1887
1888 static void
1889 symbol_locate (symbolS * symbolP,
1890 const char * name, /* It is copied, the caller can modify. */
1891 segT segment, /* Segment identifier (SEG_<something>). */
1892 valueT valu, /* Symbol value. */
1893 fragS * frag) /* Associated fragment. */
1894 {
1895 unsigned int name_length;
1896 char * preserved_copy_of_name;
1897
1898 name_length = strlen (name) + 1; /* +1 for \0. */
1899 obstack_grow (&notes, name, name_length);
1900 preserved_copy_of_name = obstack_finish (&notes);
1901
1902 #ifdef tc_canonicalize_symbol_name
1903 preserved_copy_of_name =
1904 tc_canonicalize_symbol_name (preserved_copy_of_name);
1905 #endif
1906
1907 S_SET_NAME (symbolP, preserved_copy_of_name);
1908
1909 S_SET_SEGMENT (symbolP, segment);
1910 S_SET_VALUE (symbolP, valu);
1911 symbol_clear_list_pointers (symbolP);
1912
1913 symbol_set_frag (symbolP, frag);
1914
1915 /* Link to end of symbol chain. */
1916 {
1917 extern int symbol_table_frozen;
1918
1919 if (symbol_table_frozen)
1920 abort ();
1921 }
1922
1923 symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP);
1924
1925 obj_symbol_new_hook (symbolP);
1926
1927 #ifdef tc_symbol_new_hook
1928 tc_symbol_new_hook (symbolP);
1929 #endif
1930
1931 #ifdef DEBUG_SYMS
1932 verify_symbol_chain (symbol_rootP, symbol_lastP);
1933 #endif /* DEBUG_SYMS */
1934 }
1935
1936
1937 static void
1938 s_ltorg (int ignored ATTRIBUTE_UNUSED)
1939 {
1940 unsigned int entry;
1941 literal_pool * pool;
1942 char sym_name[20];
1943
1944 pool = find_literal_pool ();
1945 if (pool == NULL
1946 || pool->symbol == NULL
1947 || pool->next_free_entry == 0)
1948 return;
1949
1950 mapping_state (MAP_DATA);
1951
1952 /* Align pool as you have word accesses.
1953 Only make a frag if we have to. */
1954 if (!need_pass_2)
1955 frag_align (2, 0, 0);
1956
1957 record_alignment (now_seg, 2);
1958
1959 sprintf (sym_name, "$$lit_\002%x", pool->id);
1960
1961 symbol_locate (pool->symbol, sym_name, now_seg,
1962 (valueT) frag_now_fix (), frag_now);
1963 symbol_table_insert (pool->symbol);
1964
1965 ARM_SET_THUMB (pool->symbol, thumb_mode);
1966
1967 #if defined OBJ_COFF || defined OBJ_ELF
1968 ARM_SET_INTERWORK (pool->symbol, support_interwork);
1969 #endif
1970
1971 for (entry = 0; entry < pool->next_free_entry; entry ++)
1972 /* First output the expression in the instruction to the pool. */
1973 emit_expr (&(pool->literals[entry]), 4); /* .word */
1974
1975 /* Mark the pool as empty. */
1976 pool->next_free_entry = 0;
1977 pool->symbol = NULL;
1978 }
1979
1980 #ifdef OBJ_ELF
1981 /* Forward declarations for functions below, in the MD interface
1982 section. */
1983 static void fix_new_arm (fragS *, int, short, expressionS *, int, int);
1984 static valueT create_unwind_entry (int);
1985 static void start_unwind_section (const segT, int);
1986 static void add_unwind_opcode (valueT, int);
1987 static void flush_pending_unwind (void);
1988
1989 /* Directives: Data. */
1990
1991 static void
1992 s_arm_elf_cons (int nbytes)
1993 {
1994 expressionS exp;
1995
1996 #ifdef md_flush_pending_output
1997 md_flush_pending_output ();
1998 #endif
1999
2000 if (is_it_end_of_statement ())
2001 {
2002 demand_empty_rest_of_line ();
2003 return;
2004 }
2005
2006 #ifdef md_cons_align
2007 md_cons_align (nbytes);
2008 #endif
2009
2010 mapping_state (MAP_DATA);
2011 do
2012 {
2013 int reloc;
2014 char *base = input_line_pointer;
2015
2016 expression (& exp);
2017
2018 if (exp.X_op != O_symbol)
2019 emit_expr (&exp, (unsigned int) nbytes);
2020 else
2021 {
2022 char *before_reloc = input_line_pointer;
2023 reloc = parse_reloc (&input_line_pointer);
2024 if (reloc == -1)
2025 {
2026 as_bad (_("unrecognized relocation suffix"));
2027 ignore_rest_of_line ();
2028 return;
2029 }
2030 else if (reloc == BFD_RELOC_UNUSED)
2031 emit_expr (&exp, (unsigned int) nbytes);
2032 else
2033 {
2034 reloc_howto_type *howto = bfd_reloc_type_lookup (stdoutput, reloc);
2035 int size = bfd_get_reloc_size (howto);
2036
2037 if (reloc == BFD_RELOC_ARM_PLT32)
2038 {
2039 as_bad (_("(plt) is only valid on branch targets"));
2040 reloc = BFD_RELOC_UNUSED;
2041 size = 0;
2042 }
2043
2044 if (size > nbytes)
2045 as_bad (_("%s relocations do not fit in %d bytes"),
2046 howto->name, nbytes);
2047 else
2048 {
2049 /* We've parsed an expression stopping at O_symbol.
2050 But there may be more expression left now that we
2051 have parsed the relocation marker. Parse it again.
2052 XXX Surely there is a cleaner way to do this. */
2053 char *p = input_line_pointer;
2054 int offset;
2055 char *save_buf = alloca (input_line_pointer - base);
2056 memcpy (save_buf, base, input_line_pointer - base);
2057 memmove (base + (input_line_pointer - before_reloc),
2058 base, before_reloc - base);
2059
2060 input_line_pointer = base + (input_line_pointer-before_reloc);
2061 expression (&exp);
2062 memcpy (base, save_buf, p - base);
2063
2064 offset = nbytes - size;
2065 p = frag_more ((int) nbytes);
2066 fix_new_exp (frag_now, p - frag_now->fr_literal + offset,
2067 size, &exp, 0, reloc);
2068 }
2069 }
2070 }
2071 }
2072 while (*input_line_pointer++ == ',');
2073
2074 /* Put terminator back into stream. */
2075 input_line_pointer --;
2076 demand_empty_rest_of_line ();
2077 }
2078
2079
2080 /* Parse a .rel31 directive. */
2081
2082 static void
2083 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED)
2084 {
2085 expressionS exp;
2086 char *p;
2087 valueT highbit;
2088
2089 highbit = 0;
2090 if (*input_line_pointer == '1')
2091 highbit = 0x80000000;
2092 else if (*input_line_pointer != '0')
2093 as_bad (_("expected 0 or 1"));
2094
2095 input_line_pointer++;
2096 if (*input_line_pointer != ',')
2097 as_bad (_("missing comma"));
2098 input_line_pointer++;
2099
2100 #ifdef md_flush_pending_output
2101 md_flush_pending_output ();
2102 #endif
2103
2104 #ifdef md_cons_align
2105 md_cons_align (4);
2106 #endif
2107
2108 mapping_state (MAP_DATA);
2109
2110 expression (&exp);
2111
2112 p = frag_more (4);
2113 md_number_to_chars (p, highbit, 4);
2114 fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 1,
2115 BFD_RELOC_ARM_PREL31);
2116
2117 demand_empty_rest_of_line ();
2118 }
2119
2120 /* Directives: AEABI stack-unwind tables. */
2121
2122 /* Parse an unwind_fnstart directive. Simply records the current location. */
2123
2124 static void
2125 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED)
2126 {
2127 demand_empty_rest_of_line ();
2128 /* Mark the start of the function. */
2129 unwind.proc_start = expr_build_dot ();
2130
2131 /* Reset the rest of the unwind info. */
2132 unwind.opcode_count = 0;
2133 unwind.table_entry = NULL;
2134 unwind.personality_routine = NULL;
2135 unwind.personality_index = -1;
2136 unwind.frame_size = 0;
2137 unwind.fp_offset = 0;
2138 unwind.fp_reg = 13;
2139 unwind.fp_used = 0;
2140 unwind.sp_restored = 0;
2141 }
2142
2143
2144 /* Parse a handlerdata directive. Creates the exception handling table entry
2145 for the function. */
2146
2147 static void
2148 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED)
2149 {
2150 demand_empty_rest_of_line ();
2151 if (unwind.table_entry)
2152 as_bad (_("dupicate .handlerdata directive"));
2153
2154 create_unwind_entry (1);
2155 }
2156
2157 /* Parse an unwind_fnend directive. Generates the index table entry. */
2158
2159 static void
2160 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED)
2161 {
2162 long where;
2163 char *ptr;
2164 valueT val;
2165
2166 demand_empty_rest_of_line ();
2167
2168 /* Add eh table entry. */
2169 if (unwind.table_entry == NULL)
2170 val = create_unwind_entry (0);
2171 else
2172 val = 0;
2173
2174 /* Add index table entry. This is two words. */
2175 start_unwind_section (unwind.saved_seg, 1);
2176 frag_align (2, 0, 0);
2177 record_alignment (now_seg, 2);
2178
2179 ptr = frag_more (8);
2180 where = frag_now_fix () - 8;
2181
2182 /* Self relative offset of the function start. */
2183 fix_new (frag_now, where, 4, unwind.proc_start, 0, 1,
2184 BFD_RELOC_ARM_PREL31);
2185
2186 /* Indicate dependency on EHABI-defined personality routines to the
2187 linker, if it hasn't been done already. */
2188 if (unwind.personality_index >= 0 && unwind.personality_index < 3
2189 && !(marked_pr_dependency & (1 << unwind.personality_index)))
2190 {
2191 static const char *const name[] = {
2192 "__aeabi_unwind_cpp_pr0",
2193 "__aeabi_unwind_cpp_pr1",
2194 "__aeabi_unwind_cpp_pr2"
2195 };
2196 symbolS *pr = symbol_find_or_make (name[unwind.personality_index]);
2197 fix_new (frag_now, where, 0, pr, 0, 1, BFD_RELOC_NONE);
2198 marked_pr_dependency |= 1 << unwind.personality_index;
2199 seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency
2200 = marked_pr_dependency;
2201 }
2202
2203 if (val)
2204 /* Inline exception table entry. */
2205 md_number_to_chars (ptr + 4, val, 4);
2206 else
2207 /* Self relative offset of the table entry. */
2208 fix_new (frag_now, where + 4, 4, unwind.table_entry, 0, 1,
2209 BFD_RELOC_ARM_PREL31);
2210
2211 /* Restore the original section. */
2212 subseg_set (unwind.saved_seg, unwind.saved_subseg);
2213 }
2214
2215
2216 /* Parse an unwind_cantunwind directive. */
2217
2218 static void
2219 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED)
2220 {
2221 demand_empty_rest_of_line ();
2222 if (unwind.personality_routine || unwind.personality_index != -1)
2223 as_bad (_("personality routine specified for cantunwind frame"));
2224
2225 unwind.personality_index = -2;
2226 }
2227
2228
2229 /* Parse a personalityindex directive. */
2230
2231 static void
2232 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED)
2233 {
2234 expressionS exp;
2235
2236 if (unwind.personality_routine || unwind.personality_index != -1)
2237 as_bad (_("duplicate .personalityindex directive"));
2238
2239 expression (&exp);
2240
2241 if (exp.X_op != O_constant
2242 || exp.X_add_number < 0 || exp.X_add_number > 15)
2243 {
2244 as_bad (_("bad personality routine number"));
2245 ignore_rest_of_line ();
2246 return;
2247 }
2248
2249 unwind.personality_index = exp.X_add_number;
2250
2251 demand_empty_rest_of_line ();
2252 }
2253
2254
2255 /* Parse a personality directive. */
2256
2257 static void
2258 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED)
2259 {
2260 char *name, *p, c;
2261
2262 if (unwind.personality_routine || unwind.personality_index != -1)
2263 as_bad (_("duplicate .personality directive"));
2264
2265 name = input_line_pointer;
2266 c = get_symbol_end ();
2267 p = input_line_pointer;
2268 unwind.personality_routine = symbol_find_or_make (name);
2269 *p = c;
2270 demand_empty_rest_of_line ();
2271 }
2272
2273
2274 /* Parse a directive saving core registers. */
2275
2276 static void
2277 s_arm_unwind_save_core (void)
2278 {
2279 valueT op;
2280 long range;
2281 int n;
2282
2283 range = parse_reg_list (&input_line_pointer);
2284 if (range == FAIL)
2285 {
2286 as_bad (_("expected register list"));
2287 ignore_rest_of_line ();
2288 return;
2289 }
2290
2291 demand_empty_rest_of_line ();
2292
2293 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
2294 into .unwind_save {..., sp...}. We aren't bothered about the value of
2295 ip because it is clobbered by calls. */
2296 if (unwind.sp_restored && unwind.fp_reg == 12
2297 && (range & 0x3000) == 0x1000)
2298 {
2299 unwind.opcode_count--;
2300 unwind.sp_restored = 0;
2301 range = (range | 0x2000) & ~0x1000;
2302 unwind.pending_offset = 0;
2303 }
2304
2305 /* Pop r4-r15. */
2306 if (range & 0xfff0)
2307 {
2308 /* See if we can use the short opcodes. These pop a block of up to 8
2309 registers starting with r4, plus maybe r14. */
2310 for (n = 0; n < 8; n++)
2311 {
2312 /* Break at the first non-saved register. */
2313 if ((range & (1 << (n + 4))) == 0)
2314 break;
2315 }
2316 /* See if there are any other bits set. */
2317 if (n == 0 || (range & (0xfff0 << n) & 0xbff0) != 0)
2318 {
2319 /* Use the long form. */
2320 op = 0x8000 | ((range >> 4) & 0xfff);
2321 add_unwind_opcode (op, 2);
2322 }
2323 else
2324 {
2325 /* Use the short form. */
2326 if (range & 0x4000)
2327 op = 0xa8; /* Pop r14. */
2328 else
2329 op = 0xa0; /* Do not pop r14. */
2330 op |= (n - 1);
2331 add_unwind_opcode (op, 1);
2332 }
2333 }
2334
2335 /* Pop r0-r3. */
2336 if (range & 0xf)
2337 {
2338 op = 0xb100 | (range & 0xf);
2339 add_unwind_opcode (op, 2);
2340 }
2341
2342 /* Record the number of bytes pushed. */
2343 for (n = 0; n < 16; n++)
2344 {
2345 if (range & (1 << n))
2346 unwind.frame_size += 4;
2347 }
2348 }
2349
2350
2351 /* Parse a directive saving FPA registers. */
2352
2353 static void
2354 s_arm_unwind_save_fpa (int reg)
2355 {
2356 expressionS exp;
2357 int num_regs;
2358 valueT op;
2359
2360 /* Get Number of registers to transfer. */
2361 if (skip_past_comma (&input_line_pointer) != FAIL)
2362 expression (&exp);
2363 else
2364 exp.X_op = O_illegal;
2365
2366 if (exp.X_op != O_constant)
2367 {
2368 as_bad (_("expected , <constant>"));
2369 ignore_rest_of_line ();
2370 return;
2371 }
2372
2373 num_regs = exp.X_add_number;
2374
2375 if (num_regs < 1 || num_regs > 4)
2376 {
2377 as_bad (_("number of registers must be in the range [1:4]"));
2378 ignore_rest_of_line ();
2379 return;
2380 }
2381
2382 demand_empty_rest_of_line ();
2383
2384 if (reg == 4)
2385 {
2386 /* Short form. */
2387 op = 0xb4 | (num_regs - 1);
2388 add_unwind_opcode (op, 1);
2389 }
2390 else
2391 {
2392 /* Long form. */
2393 op = 0xc800 | (reg << 4) | (num_regs - 1);
2394 add_unwind_opcode (op, 2);
2395 }
2396 unwind.frame_size += num_regs * 12;
2397 }
2398
2399
2400 /* Parse a directive saving VFP registers. */
2401
2402 static void
2403 s_arm_unwind_save_vfp (void)
2404 {
2405 int count;
2406 unsigned int reg;
2407 valueT op;
2408
2409 count = parse_vfp_reg_list (&input_line_pointer, &reg, 1);
2410 if (count == FAIL)
2411 {
2412 as_bad (_("expected register list"));
2413 ignore_rest_of_line ();
2414 return;
2415 }
2416
2417 demand_empty_rest_of_line ();
2418
2419 if (reg == 8)
2420 {
2421 /* Short form. */
2422 op = 0xb8 | (count - 1);
2423 add_unwind_opcode (op, 1);
2424 }
2425 else
2426 {
2427 /* Long form. */
2428 op = 0xb300 | (reg << 4) | (count - 1);
2429 add_unwind_opcode (op, 2);
2430 }
2431 unwind.frame_size += count * 8 + 4;
2432 }
2433
2434
2435 /* Parse a directive saving iWMMXt data registers. */
2436
2437 static void
2438 s_arm_unwind_save_mmxwr (void)
2439 {
2440 int reg;
2441 int hi_reg;
2442 int i;
2443 unsigned mask = 0;
2444 valueT op;
2445
2446 if (*input_line_pointer == '{')
2447 input_line_pointer++;
2448
2449 do
2450 {
2451 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
2452
2453 if (reg == FAIL)
2454 {
2455 as_bad (_(reg_expected_msgs[REG_TYPE_MMXWR]));
2456 goto error;
2457 }
2458
2459 if (mask >> reg)
2460 as_tsktsk (_("register list not in ascending order"));
2461 mask |= 1 << reg;
2462
2463 if (*input_line_pointer == '-')
2464 {
2465 input_line_pointer++;
2466 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
2467 if (hi_reg == FAIL)
2468 {
2469 as_bad (_(reg_expected_msgs[REG_TYPE_MMXWR]));
2470 goto error;
2471 }
2472 else if (reg >= hi_reg)
2473 {
2474 as_bad (_("bad register range"));
2475 goto error;
2476 }
2477 for (; reg < hi_reg; reg++)
2478 mask |= 1 << reg;
2479 }
2480 }
2481 while (skip_past_comma (&input_line_pointer) != FAIL);
2482
2483 if (*input_line_pointer == '}')
2484 input_line_pointer++;
2485
2486 demand_empty_rest_of_line ();
2487
2488 /* Generate any deferred opcodes becuuse we're going to be looking at
2489 the list. */
2490 flush_pending_unwind ();
2491
2492 for (i = 0; i < 16; i++)
2493 {
2494 if (mask & (1 << i))
2495 unwind.frame_size += 8;
2496 }
2497
2498 /* Attempt to combine with a previous opcode. We do this because gcc
2499 likes to output separate unwind directives for a single block of
2500 registers. */
2501 if (unwind.opcode_count > 0)
2502 {
2503 i = unwind.opcodes[unwind.opcode_count - 1];
2504 if ((i & 0xf8) == 0xc0)
2505 {
2506 i &= 7;
2507 /* Only merge if the blocks are contiguous. */
2508 if (i < 6)
2509 {
2510 if ((mask & 0xfe00) == (1 << 9))
2511 {
2512 mask |= ((1 << (i + 11)) - 1) & 0xfc00;
2513 unwind.opcode_count--;
2514 }
2515 }
2516 else if (i == 6 && unwind.opcode_count >= 2)
2517 {
2518 i = unwind.opcodes[unwind.opcode_count - 2];
2519 reg = i >> 4;
2520 i &= 0xf;
2521
2522 op = 0xffff << (reg - 1);
2523 if (reg > 0
2524 || ((mask & op) == (1u << (reg - 1))))
2525 {
2526 op = (1 << (reg + i + 1)) - 1;
2527 op &= ~((1 << reg) - 1);
2528 mask |= op;
2529 unwind.opcode_count -= 2;
2530 }
2531 }
2532 }
2533 }
2534
2535 hi_reg = 15;
2536 /* We want to generate opcodes in the order the registers have been
2537 saved, ie. descending order. */
2538 for (reg = 15; reg >= -1; reg--)
2539 {
2540 /* Save registers in blocks. */
2541 if (reg < 0
2542 || !(mask & (1 << reg)))
2543 {
2544 /* We found an unsaved reg. Generate opcodes to save the
2545 preceeding block. */
2546 if (reg != hi_reg)
2547 {
2548 if (reg == 9)
2549 {
2550 /* Short form. */
2551 op = 0xc0 | (hi_reg - 10);
2552 add_unwind_opcode (op, 1);
2553 }
2554 else
2555 {
2556 /* Long form. */
2557 op = 0xc600 | ((reg + 1) << 4) | ((hi_reg - reg) - 1);
2558 add_unwind_opcode (op, 2);
2559 }
2560 }
2561 hi_reg = reg - 1;
2562 }
2563 }
2564
2565 return;
2566 error:
2567 ignore_rest_of_line ();
2568 }
2569
2570 static void
2571 s_arm_unwind_save_mmxwcg (void)
2572 {
2573 int reg;
2574 int hi_reg;
2575 unsigned mask = 0;
2576 valueT op;
2577
2578 if (*input_line_pointer == '{')
2579 input_line_pointer++;
2580
2581 do
2582 {
2583 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
2584
2585 if (reg == FAIL)
2586 {
2587 as_bad (_(reg_expected_msgs[REG_TYPE_MMXWCG]));
2588 goto error;
2589 }
2590
2591 reg -= 8;
2592 if (mask >> reg)
2593 as_tsktsk (_("register list not in ascending order"));
2594 mask |= 1 << reg;
2595
2596 if (*input_line_pointer == '-')
2597 {
2598 input_line_pointer++;
2599 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
2600 if (hi_reg == FAIL)
2601 {
2602 as_bad (_(reg_expected_msgs[REG_TYPE_MMXWCG]));
2603 goto error;
2604 }
2605 else if (reg >= hi_reg)
2606 {
2607 as_bad (_("bad register range"));
2608 goto error;
2609 }
2610 for (; reg < hi_reg; reg++)
2611 mask |= 1 << reg;
2612 }
2613 }
2614 while (skip_past_comma (&input_line_pointer) != FAIL);
2615
2616 if (*input_line_pointer == '}')
2617 input_line_pointer++;
2618
2619 demand_empty_rest_of_line ();
2620
2621 /* Generate any deferred opcodes becuuse we're going to be looking at
2622 the list. */
2623 flush_pending_unwind ();
2624
2625 for (reg = 0; reg < 16; reg++)
2626 {
2627 if (mask & (1 << reg))
2628 unwind.frame_size += 4;
2629 }
2630 op = 0xc700 | mask;
2631 add_unwind_opcode (op, 2);
2632 return;
2633 error:
2634 ignore_rest_of_line ();
2635 }
2636
2637
2638 /* Parse an unwind_save directive. */
2639
2640 static void
2641 s_arm_unwind_save (int ignored ATTRIBUTE_UNUSED)
2642 {
2643 char *peek;
2644 struct reg_entry *reg;
2645 bfd_boolean had_brace = FALSE;
2646
2647 /* Figure out what sort of save we have. */
2648 peek = input_line_pointer;
2649
2650 if (*peek == '{')
2651 {
2652 had_brace = TRUE;
2653 peek++;
2654 }
2655
2656 reg = arm_reg_parse_multi (&peek);
2657
2658 if (!reg)
2659 {
2660 as_bad (_("register expected"));
2661 ignore_rest_of_line ();
2662 return;
2663 }
2664
2665 switch (reg->type)
2666 {
2667 case REG_TYPE_FN:
2668 if (had_brace)
2669 {
2670 as_bad (_("FPA .unwind_save does not take a register list"));
2671 ignore_rest_of_line ();
2672 return;
2673 }
2674 s_arm_unwind_save_fpa (reg->number);
2675 return;
2676
2677 case REG_TYPE_RN: s_arm_unwind_save_core (); return;
2678 case REG_TYPE_VFD: s_arm_unwind_save_vfp (); return;
2679 case REG_TYPE_MMXWR: s_arm_unwind_save_mmxwr (); return;
2680 case REG_TYPE_MMXWCG: s_arm_unwind_save_mmxwcg (); return;
2681
2682 default:
2683 as_bad (_(".unwind_save does not support this kind of register"));
2684 ignore_rest_of_line ();
2685 }
2686 }
2687
2688
2689 /* Parse an unwind_movsp directive. */
2690
2691 static void
2692 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED)
2693 {
2694 int reg;
2695 valueT op;
2696
2697 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
2698 if (reg == FAIL)
2699 {
2700 as_bad (_(reg_expected_msgs[REG_TYPE_RN]));
2701 ignore_rest_of_line ();
2702 return;
2703 }
2704 demand_empty_rest_of_line ();
2705
2706 if (reg == REG_SP || reg == REG_PC)
2707 {
2708 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
2709 return;
2710 }
2711
2712 if (unwind.fp_reg != REG_SP)
2713 as_bad (_("unexpected .unwind_movsp directive"));
2714
2715 /* Generate opcode to restore the value. */
2716 op = 0x90 | reg;
2717 add_unwind_opcode (op, 1);
2718
2719 /* Record the information for later. */
2720 unwind.fp_reg = reg;
2721 unwind.fp_offset = unwind.frame_size;
2722 unwind.sp_restored = 1;
2723 }
2724
2725 /* Parse an unwind_pad directive. */
2726
2727 static void
2728 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED)
2729 {
2730 int offset;
2731
2732 if (immediate_for_directive (&offset) == FAIL)
2733 return;
2734
2735 if (offset & 3)
2736 {
2737 as_bad (_("stack increment must be multiple of 4"));
2738 ignore_rest_of_line ();
2739 return;
2740 }
2741
2742 /* Don't generate any opcodes, just record the details for later. */
2743 unwind.frame_size += offset;
2744 unwind.pending_offset += offset;
2745
2746 demand_empty_rest_of_line ();
2747 }
2748
2749 /* Parse an unwind_setfp directive. */
2750
2751 static void
2752 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED)
2753 {
2754 int sp_reg;
2755 int fp_reg;
2756 int offset;
2757
2758 fp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
2759 if (skip_past_comma (&input_line_pointer) == FAIL)
2760 sp_reg = FAIL;
2761 else
2762 sp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
2763
2764 if (fp_reg == FAIL || sp_reg == FAIL)
2765 {
2766 as_bad (_("expected <reg>, <reg>"));
2767 ignore_rest_of_line ();
2768 return;
2769 }
2770
2771 /* Optional constant. */
2772 if (skip_past_comma (&input_line_pointer) != FAIL)
2773 {
2774 if (immediate_for_directive (&offset) == FAIL)
2775 return;
2776 }
2777 else
2778 offset = 0;
2779
2780 demand_empty_rest_of_line ();
2781
2782 if (sp_reg != 13 && sp_reg != unwind.fp_reg)
2783 {
2784 as_bad (_("register must be either sp or set by a previous"
2785 "unwind_movsp directive"));
2786 return;
2787 }
2788
2789 /* Don't generate any opcodes, just record the information for later. */
2790 unwind.fp_reg = fp_reg;
2791 unwind.fp_used = 1;
2792 if (sp_reg == 13)
2793 unwind.fp_offset = unwind.frame_size - offset;
2794 else
2795 unwind.fp_offset -= offset;
2796 }
2797
2798 /* Parse an unwind_raw directive. */
2799
2800 static void
2801 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED)
2802 {
2803 expressionS exp;
2804 /* This is an arbitary limit. */
2805 unsigned char op[16];
2806 int count;
2807
2808 expression (&exp);
2809 if (exp.X_op == O_constant
2810 && skip_past_comma (&input_line_pointer) != FAIL)
2811 {
2812 unwind.frame_size += exp.X_add_number;
2813 expression (&exp);
2814 }
2815 else
2816 exp.X_op = O_illegal;
2817
2818 if (exp.X_op != O_constant)
2819 {
2820 as_bad (_("expected <offset>, <opcode>"));
2821 ignore_rest_of_line ();
2822 return;
2823 }
2824
2825 count = 0;
2826
2827 /* Parse the opcode. */
2828 for (;;)
2829 {
2830 if (count >= 16)
2831 {
2832 as_bad (_("unwind opcode too long"));
2833 ignore_rest_of_line ();
2834 }
2835 if (exp.X_op != O_constant || exp.X_add_number & ~0xff)
2836 {
2837 as_bad (_("invalid unwind opcode"));
2838 ignore_rest_of_line ();
2839 return;
2840 }
2841 op[count++] = exp.X_add_number;
2842
2843 /* Parse the next byte. */
2844 if (skip_past_comma (&input_line_pointer) == FAIL)
2845 break;
2846
2847 expression (&exp);
2848 }
2849
2850 /* Add the opcode bytes in reverse order. */
2851 while (count--)
2852 add_unwind_opcode (op[count], 1);
2853
2854 demand_empty_rest_of_line ();
2855 }
2856
2857
2858 /* Parse a .eabi_attribute directive. */
2859
2860 static void
2861 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED)
2862 {
2863 expressionS exp;
2864 bfd_boolean is_string;
2865 int tag;
2866 unsigned int i = 0;
2867 char *s = NULL;
2868 char saved_char;
2869
2870 expression (& exp);
2871 if (exp.X_op != O_constant)
2872 goto bad;
2873
2874 tag = exp.X_add_number;
2875 if (tag == 4 || tag == 5 || tag == 32 || (tag > 32 && (tag & 1) != 0))
2876 is_string = 1;
2877 else
2878 is_string = 0;
2879
2880 if (skip_past_comma (&input_line_pointer) == FAIL)
2881 goto bad;
2882 if (tag == 32 || !is_string)
2883 {
2884 expression (& exp);
2885 if (exp.X_op != O_constant)
2886 {
2887 as_bad (_("expected numeric constant"));
2888 ignore_rest_of_line ();
2889 return;
2890 }
2891 i = exp.X_add_number;
2892 }
2893 if (tag == Tag_compatibility
2894 && skip_past_comma (&input_line_pointer) == FAIL)
2895 {
2896 as_bad (_("expected comma"));
2897 ignore_rest_of_line ();
2898 return;
2899 }
2900 if (is_string)
2901 {
2902 skip_whitespace(input_line_pointer);
2903 if (*input_line_pointer != '"')
2904 goto bad_string;
2905 input_line_pointer++;
2906 s = input_line_pointer;
2907 while (*input_line_pointer && *input_line_pointer != '"')
2908 input_line_pointer++;
2909 if (*input_line_pointer != '"')
2910 goto bad_string;
2911 saved_char = *input_line_pointer;
2912 *input_line_pointer = 0;
2913 }
2914 else
2915 {
2916 s = NULL;
2917 saved_char = 0;
2918 }
2919
2920 if (tag == Tag_compatibility)
2921 elf32_arm_add_eabi_attr_compat (stdoutput, i, s);
2922 else if (is_string)
2923 elf32_arm_add_eabi_attr_string (stdoutput, tag, s);
2924 else
2925 elf32_arm_add_eabi_attr_int (stdoutput, tag, i);
2926
2927 if (s)
2928 {
2929 *input_line_pointer = saved_char;
2930 input_line_pointer++;
2931 }
2932 demand_empty_rest_of_line ();
2933 return;
2934 bad_string:
2935 as_bad (_("bad string constant"));
2936 ignore_rest_of_line ();
2937 return;
2938 bad:
2939 as_bad (_("expected <tag> , <value>"));
2940 ignore_rest_of_line ();
2941 }
2942
2943 static void s_arm_arch (int);
2944 static void s_arm_cpu (int);
2945 static void s_arm_fpu (int);
2946 #endif /* OBJ_ELF */
2947
2948 /* This table describes all the machine specific pseudo-ops the assembler
2949 has to support. The fields are:
2950 pseudo-op name without dot
2951 function to call to execute this pseudo-op
2952 Integer arg to pass to the function. */
2953
2954 const pseudo_typeS md_pseudo_table[] =
2955 {
2956 /* Never called because '.req' does not start a line. */
2957 { "req", s_req, 0 },
2958 { "unreq", s_unreq, 0 },
2959 { "bss", s_bss, 0 },
2960 { "align", s_align, 0 },
2961 { "arm", s_arm, 0 },
2962 { "thumb", s_thumb, 0 },
2963 { "code", s_code, 0 },
2964 { "force_thumb", s_force_thumb, 0 },
2965 { "thumb_func", s_thumb_func, 0 },
2966 { "thumb_set", s_thumb_set, 0 },
2967 { "even", s_even, 0 },
2968 { "ltorg", s_ltorg, 0 },
2969 { "pool", s_ltorg, 0 },
2970 { "syntax", s_syntax, 0 },
2971 #ifdef OBJ_ELF
2972 { "word", s_arm_elf_cons, 4 },
2973 { "long", s_arm_elf_cons, 4 },
2974 { "rel31", s_arm_rel31, 0 },
2975 { "fnstart", s_arm_unwind_fnstart, 0 },
2976 { "fnend", s_arm_unwind_fnend, 0 },
2977 { "cantunwind", s_arm_unwind_cantunwind, 0 },
2978 { "personality", s_arm_unwind_personality, 0 },
2979 { "personalityindex", s_arm_unwind_personalityindex, 0 },
2980 { "handlerdata", s_arm_unwind_handlerdata, 0 },
2981 { "save", s_arm_unwind_save, 0 },
2982 { "movsp", s_arm_unwind_movsp, 0 },
2983 { "pad", s_arm_unwind_pad, 0 },
2984 { "setfp", s_arm_unwind_setfp, 0 },
2985 { "unwind_raw", s_arm_unwind_raw, 0 },
2986 { "cpu", s_arm_cpu, 0 },
2987 { "arch", s_arm_arch, 0 },
2988 { "fpu", s_arm_fpu, 0 },
2989 { "eabi_attribute", s_arm_eabi_attribute, 0 },
2990 #else
2991 { "word", cons, 4},
2992 #endif
2993 { "extend", float_cons, 'x' },
2994 { "ldouble", float_cons, 'x' },
2995 { "packed", float_cons, 'p' },
2996 { 0, 0, 0 }
2997 };
2998 \f
2999 /* Parser functions used exclusively in instruction operands. */
3000
3001 /* Generic immediate-value read function for use in insn parsing.
3002 STR points to the beginning of the immediate (the leading #);
3003 VAL receives the value; if the value is outside [MIN, MAX]
3004 issue an error. PREFIX_OPT is true if the immediate prefix is
3005 optional. */
3006
3007 static int
3008 parse_immediate (char **str, int *val, int min, int max,
3009 bfd_boolean prefix_opt)
3010 {
3011 expressionS exp;
3012 my_get_expression (&exp, str, prefix_opt ? GE_OPT_PREFIX : GE_IMM_PREFIX);
3013 if (exp.X_op != O_constant)
3014 {
3015 inst.error = _("constant expression required");
3016 return FAIL;
3017 }
3018
3019 if (exp.X_add_number < min || exp.X_add_number > max)
3020 {
3021 inst.error = _("immediate value out of range");
3022 return FAIL;
3023 }
3024
3025 *val = exp.X_add_number;
3026 return SUCCESS;
3027 }
3028
3029 /* Returns the pseudo-register number of an FPA immediate constant,
3030 or FAIL if there isn't a valid constant here. */
3031
3032 static int
3033 parse_fpa_immediate (char ** str)
3034 {
3035 LITTLENUM_TYPE words[MAX_LITTLENUMS];
3036 char * save_in;
3037 expressionS exp;
3038 int i;
3039 int j;
3040
3041 /* First try and match exact strings, this is to guarantee
3042 that some formats will work even for cross assembly. */
3043
3044 for (i = 0; fp_const[i]; i++)
3045 {
3046 if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0)
3047 {
3048 char *start = *str;
3049
3050 *str += strlen (fp_const[i]);
3051 if (is_end_of_line[(unsigned char) **str])
3052 return i + 8;
3053 *str = start;
3054 }
3055 }
3056
3057 /* Just because we didn't get a match doesn't mean that the constant
3058 isn't valid, just that it is in a format that we don't
3059 automatically recognize. Try parsing it with the standard
3060 expression routines. */
3061
3062 memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE));
3063
3064 /* Look for a raw floating point number. */
3065 if ((save_in = atof_ieee (*str, 'x', words)) != NULL
3066 && is_end_of_line[(unsigned char) *save_in])
3067 {
3068 for (i = 0; i < NUM_FLOAT_VALS; i++)
3069 {
3070 for (j = 0; j < MAX_LITTLENUMS; j++)
3071 {
3072 if (words[j] != fp_values[i][j])
3073 break;
3074 }
3075
3076 if (j == MAX_LITTLENUMS)
3077 {
3078 *str = save_in;
3079 return i + 8;
3080 }
3081 }
3082 }
3083
3084 /* Try and parse a more complex expression, this will probably fail
3085 unless the code uses a floating point prefix (eg "0f"). */
3086 save_in = input_line_pointer;
3087 input_line_pointer = *str;
3088 if (expression (&exp) == absolute_section
3089 && exp.X_op == O_big
3090 && exp.X_add_number < 0)
3091 {
3092 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
3093 Ditto for 15. */
3094 if (gen_to_words (words, 5, (long) 15) == 0)
3095 {
3096 for (i = 0; i < NUM_FLOAT_VALS; i++)
3097 {
3098 for (j = 0; j < MAX_LITTLENUMS; j++)
3099 {
3100 if (words[j] != fp_values[i][j])
3101 break;
3102 }
3103
3104 if (j == MAX_LITTLENUMS)
3105 {
3106 *str = input_line_pointer;
3107 input_line_pointer = save_in;
3108 return i + 8;
3109 }
3110 }
3111 }
3112 }
3113
3114 *str = input_line_pointer;
3115 input_line_pointer = save_in;
3116 inst.error = _("invalid FPA immediate expression");
3117 return FAIL;
3118 }
3119
3120 /* Shift operands. */
3121 enum shift_kind
3122 {
3123 SHIFT_LSL, SHIFT_LSR, SHIFT_ASR, SHIFT_ROR, SHIFT_RRX
3124 };
3125
3126 struct asm_shift_name
3127 {
3128 const char *name;
3129 enum shift_kind kind;
3130 };
3131
3132 /* Third argument to parse_shift. */
3133 enum parse_shift_mode
3134 {
3135 NO_SHIFT_RESTRICT, /* Any kind of shift is accepted. */
3136 SHIFT_IMMEDIATE, /* Shift operand must be an immediate. */
3137 SHIFT_LSL_OR_ASR_IMMEDIATE, /* Shift must be LSL or ASR immediate. */
3138 SHIFT_ASR_IMMEDIATE, /* Shift must be ASR immediate. */
3139 SHIFT_LSL_IMMEDIATE, /* Shift must be LSL immediate. */
3140 };
3141
3142 /* Parse a <shift> specifier on an ARM data processing instruction.
3143 This has three forms:
3144
3145 (LSL|LSR|ASL|ASR|ROR) Rs
3146 (LSL|LSR|ASL|ASR|ROR) #imm
3147 RRX
3148
3149 Note that ASL is assimilated to LSL in the instruction encoding, and
3150 RRX to ROR #0 (which cannot be written as such). */
3151
3152 static int
3153 parse_shift (char **str, int i, enum parse_shift_mode mode)
3154 {
3155 const struct asm_shift_name *shift_name;
3156 enum shift_kind shift;
3157 char *s = *str;
3158 char *p = s;
3159 int reg;
3160
3161 for (p = *str; ISALPHA (*p); p++)
3162 ;
3163
3164 if (p == *str)
3165 {
3166 inst.error = _("shift expression expected");
3167 return FAIL;
3168 }
3169
3170 shift_name = hash_find_n (arm_shift_hsh, *str, p - *str);
3171
3172 if (shift_name == NULL)
3173 {
3174 inst.error = _("shift expression expected");
3175 return FAIL;
3176 }
3177
3178 shift = shift_name->kind;
3179
3180 switch (mode)
3181 {
3182 case NO_SHIFT_RESTRICT:
3183 case SHIFT_IMMEDIATE: break;
3184
3185 case SHIFT_LSL_OR_ASR_IMMEDIATE:
3186 if (shift != SHIFT_LSL && shift != SHIFT_ASR)
3187 {
3188 inst.error = _("'LSL' or 'ASR' required");
3189 return FAIL;
3190 }
3191 break;
3192
3193 case SHIFT_LSL_IMMEDIATE:
3194 if (shift != SHIFT_LSL)
3195 {
3196 inst.error = _("'LSL' required");
3197 return FAIL;
3198 }
3199 break;
3200
3201 case SHIFT_ASR_IMMEDIATE:
3202 if (shift != SHIFT_ASR)
3203 {
3204 inst.error = _("'ASR' required");
3205 return FAIL;
3206 }
3207 break;
3208
3209 default: abort ();
3210 }
3211
3212 if (shift != SHIFT_RRX)
3213 {
3214 /* Whitespace can appear here if the next thing is a bare digit. */
3215 skip_whitespace (p);
3216
3217 if (mode == NO_SHIFT_RESTRICT
3218 && (reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
3219 {
3220 inst.operands[i].imm = reg;
3221 inst.operands[i].immisreg = 1;
3222 }
3223 else if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
3224 return FAIL;
3225 }
3226 inst.operands[i].shift_kind = shift;
3227 inst.operands[i].shifted = 1;
3228 *str = p;
3229 return SUCCESS;
3230 }
3231
3232 /* Parse a <shifter_operand> for an ARM data processing instruction:
3233
3234 #<immediate>
3235 #<immediate>, <rotate>
3236 <Rm>
3237 <Rm>, <shift>
3238
3239 where <shift> is defined by parse_shift above, and <rotate> is a
3240 multiple of 2 between 0 and 30. Validation of immediate operands
3241 is deferred to md_apply_fix. */
3242
3243 static int
3244 parse_shifter_operand (char **str, int i)
3245 {
3246 int value;
3247 expressionS expr;
3248
3249 if ((value = arm_reg_parse (str, REG_TYPE_RN)) != FAIL)
3250 {
3251 inst.operands[i].reg = value;
3252 inst.operands[i].isreg = 1;
3253
3254 /* parse_shift will override this if appropriate */
3255 inst.reloc.exp.X_op = O_constant;
3256 inst.reloc.exp.X_add_number = 0;
3257
3258 if (skip_past_comma (str) == FAIL)
3259 return SUCCESS;
3260
3261 /* Shift operation on register. */
3262 return parse_shift (str, i, NO_SHIFT_RESTRICT);
3263 }
3264
3265 if (my_get_expression (&inst.reloc.exp, str, GE_IMM_PREFIX))
3266 return FAIL;
3267
3268 if (skip_past_comma (str) == SUCCESS)
3269 {
3270 /* #x, y -- ie explicit rotation by Y. */
3271 if (my_get_expression (&expr, str, GE_NO_PREFIX))
3272 return FAIL;
3273
3274 if (expr.X_op != O_constant || inst.reloc.exp.X_op != O_constant)
3275 {
3276 inst.error = _("constant expression expected");
3277 return FAIL;
3278 }
3279
3280 value = expr.X_add_number;
3281 if (value < 0 || value > 30 || value % 2 != 0)
3282 {
3283 inst.error = _("invalid rotation");
3284 return FAIL;
3285 }
3286 if (inst.reloc.exp.X_add_number < 0 || inst.reloc.exp.X_add_number > 255)
3287 {
3288 inst.error = _("invalid constant");
3289 return FAIL;
3290 }
3291
3292 /* Convert to decoded value. md_apply_fix will put it back. */
3293 inst.reloc.exp.X_add_number
3294 = (((inst.reloc.exp.X_add_number << (32 - value))
3295 | (inst.reloc.exp.X_add_number >> value)) & 0xffffffff);
3296 }
3297
3298 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
3299 inst.reloc.pc_rel = 0;
3300 return SUCCESS;
3301 }
3302
3303 /* Parse all forms of an ARM address expression. Information is written
3304 to inst.operands[i] and/or inst.reloc.
3305
3306 Preindexed addressing (.preind=1):
3307
3308 [Rn, #offset] .reg=Rn .reloc.exp=offset
3309 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
3310 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
3311 .shift_kind=shift .reloc.exp=shift_imm
3312
3313 These three may have a trailing ! which causes .writeback to be set also.
3314
3315 Postindexed addressing (.postind=1, .writeback=1):
3316
3317 [Rn], #offset .reg=Rn .reloc.exp=offset
3318 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
3319 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
3320 .shift_kind=shift .reloc.exp=shift_imm
3321
3322 Unindexed addressing (.preind=0, .postind=0):
3323
3324 [Rn], {option} .reg=Rn .imm=option .immisreg=0
3325
3326 Other:
3327
3328 [Rn]{!} shorthand for [Rn,#0]{!}
3329 =immediate .isreg=0 .reloc.exp=immediate
3330 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
3331
3332 It is the caller's responsibility to check for addressing modes not
3333 supported by the instruction, and to set inst.reloc.type. */
3334
3335 static int
3336 parse_address (char **str, int i)
3337 {
3338 char *p = *str;
3339 int reg;
3340
3341 if (skip_past_char (&p, '[') == FAIL)
3342 {
3343 if (skip_past_char (&p, '=') == FAIL)
3344 {
3345 /* bare address - translate to PC-relative offset */
3346 inst.reloc.pc_rel = 1;
3347 inst.operands[i].reg = REG_PC;
3348 inst.operands[i].isreg = 1;
3349 inst.operands[i].preind = 1;
3350 }
3351 /* else a load-constant pseudo op, no special treatment needed here */
3352
3353 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
3354 return FAIL;
3355
3356 *str = p;
3357 return SUCCESS;
3358 }
3359
3360 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
3361 {
3362 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
3363 return FAIL;
3364 }
3365 inst.operands[i].reg = reg;
3366 inst.operands[i].isreg = 1;
3367
3368 if (skip_past_comma (&p) == SUCCESS)
3369 {
3370 inst.operands[i].preind = 1;
3371
3372 if (*p == '+') p++;
3373 else if (*p == '-') p++, inst.operands[i].negative = 1;
3374
3375 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
3376 {
3377 inst.operands[i].imm = reg;
3378 inst.operands[i].immisreg = 1;
3379
3380 if (skip_past_comma (&p) == SUCCESS)
3381 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
3382 return FAIL;
3383 }
3384 else
3385 {
3386 if (inst.operands[i].negative)
3387 {
3388 inst.operands[i].negative = 0;
3389 p--;
3390 }
3391 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
3392 return FAIL;
3393 }
3394 }
3395
3396 if (skip_past_char (&p, ']') == FAIL)
3397 {
3398 inst.error = _("']' expected");
3399 return FAIL;
3400 }
3401
3402 if (skip_past_char (&p, '!') == SUCCESS)
3403 inst.operands[i].writeback = 1;
3404
3405 else if (skip_past_comma (&p) == SUCCESS)
3406 {
3407 if (skip_past_char (&p, '{') == SUCCESS)
3408 {
3409 /* [Rn], {expr} - unindexed, with option */
3410 if (parse_immediate (&p, &inst.operands[i].imm,
3411 0, 255, TRUE) == FAIL)
3412 return FAIL;
3413
3414 if (skip_past_char (&p, '}') == FAIL)
3415 {
3416 inst.error = _("'}' expected at end of 'option' field");
3417 return FAIL;
3418 }
3419 if (inst.operands[i].preind)
3420 {
3421 inst.error = _("cannot combine index with option");
3422 return FAIL;
3423 }
3424 *str = p;
3425 return SUCCESS;
3426 }
3427 else
3428 {
3429 inst.operands[i].postind = 1;
3430 inst.operands[i].writeback = 1;
3431
3432 if (inst.operands[i].preind)
3433 {
3434 inst.error = _("cannot combine pre- and post-indexing");
3435 return FAIL;
3436 }
3437
3438 if (*p == '+') p++;
3439 else if (*p == '-') p++, inst.operands[i].negative = 1;
3440
3441 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
3442 {
3443 inst.operands[i].imm = reg;
3444 inst.operands[i].immisreg = 1;
3445
3446 if (skip_past_comma (&p) == SUCCESS)
3447 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
3448 return FAIL;
3449 }
3450 else
3451 {
3452 if (inst.operands[i].negative)
3453 {
3454 inst.operands[i].negative = 0;
3455 p--;
3456 }
3457 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
3458 return FAIL;
3459 }
3460 }
3461 }
3462
3463 /* If at this point neither .preind nor .postind is set, we have a
3464 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
3465 if (inst.operands[i].preind == 0 && inst.operands[i].postind == 0)
3466 {
3467 inst.operands[i].preind = 1;
3468 inst.reloc.exp.X_op = O_constant;
3469 inst.reloc.exp.X_add_number = 0;
3470 }
3471 *str = p;
3472 return SUCCESS;
3473 }
3474
3475 /* Miscellaneous. */
3476
3477 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
3478 or a bitmask suitable to be or-ed into the ARM msr instruction. */
3479 static int
3480 parse_psr (char **str)
3481 {
3482 char *p;
3483 unsigned long psr_field;
3484
3485 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
3486 feature for ease of use and backwards compatibility. */
3487 p = *str;
3488 if (*p == 's' || *p == 'S')
3489 psr_field = SPSR_BIT;
3490 else if (*p == 'c' || *p == 'C')
3491 psr_field = 0;
3492 else
3493 goto error;
3494
3495 p++;
3496 if (strncasecmp (p, "PSR", 3) != 0)
3497 goto error;
3498 p += 3;
3499
3500 if (*p == '_')
3501 {
3502 /* A suffix follows. */
3503 const struct asm_psr *psr;
3504 char *start;
3505
3506 p++;
3507 start = p;
3508
3509 do
3510 p++;
3511 while (ISALNUM (*p) || *p == '_');
3512
3513 psr = hash_find_n (arm_psr_hsh, start, p - start);
3514 if (!psr)
3515 goto error;
3516
3517 psr_field |= psr->field;
3518 }
3519 else
3520 {
3521 if (ISALNUM (*p))
3522 goto error; /* Garbage after "[CS]PSR". */
3523
3524 psr_field |= (PSR_c | PSR_f);
3525 }
3526 *str = p;
3527 return psr_field;
3528
3529 error:
3530 inst.error = _("flag for {c}psr instruction expected");
3531 return FAIL;
3532 }
3533
3534 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
3535 value suitable for splatting into the AIF field of the instruction. */
3536
3537 static int
3538 parse_cps_flags (char **str)
3539 {
3540 int val = 0;
3541 int saw_a_flag = 0;
3542 char *s = *str;
3543
3544 for (;;)
3545 switch (*s++)
3546 {
3547 case '\0': case ',':
3548 goto done;
3549
3550 case 'a': case 'A': saw_a_flag = 1; val |= 0x4; break;
3551 case 'i': case 'I': saw_a_flag = 1; val |= 0x2; break;
3552 case 'f': case 'F': saw_a_flag = 1; val |= 0x1; break;
3553
3554 default:
3555 inst.error = _("unrecognized CPS flag");
3556 return FAIL;
3557 }
3558
3559 done:
3560 if (saw_a_flag == 0)
3561 {
3562 inst.error = _("missing CPS flags");
3563 return FAIL;
3564 }
3565
3566 *str = s - 1;
3567 return val;
3568 }
3569
3570 /* Parse an endian specifier ("BE" or "LE", case insensitive);
3571 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
3572
3573 static int
3574 parse_endian_specifier (char **str)
3575 {
3576 int little_endian;
3577 char *s = *str;
3578
3579 if (strncasecmp (s, "BE", 2))
3580 little_endian = 0;
3581 else if (strncasecmp (s, "LE", 2))
3582 little_endian = 1;
3583 else
3584 {
3585 inst.error = _("valid endian specifiers are be or le");
3586 return FAIL;
3587 }
3588
3589 if (ISALNUM (s[2]) || s[2] == '_')
3590 {
3591 inst.error = _("valid endian specifiers are be or le");
3592 return FAIL;
3593 }
3594
3595 *str = s + 2;
3596 return little_endian;
3597 }
3598
3599 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
3600 value suitable for poking into the rotate field of an sxt or sxta
3601 instruction, or FAIL on error. */
3602
3603 static int
3604 parse_ror (char **str)
3605 {
3606 int rot;
3607 char *s = *str;
3608
3609 if (strncasecmp (s, "ROR", 3) == 0)
3610 s += 3;
3611 else
3612 {
3613 inst.error = _("missing rotation field after comma");
3614 return FAIL;
3615 }
3616
3617 if (parse_immediate (&s, &rot, 0, 24, FALSE) == FAIL)
3618 return FAIL;
3619
3620 switch (rot)
3621 {
3622 case 0: *str = s; return 0x0;
3623 case 8: *str = s; return 0x1;
3624 case 16: *str = s; return 0x2;
3625 case 24: *str = s; return 0x3;
3626
3627 default:
3628 inst.error = _("rotation can only be 0, 8, 16, or 24");
3629 return FAIL;
3630 }
3631 }
3632
3633 /* Parse a conditional code (from conds[] below). The value returned is in the
3634 range 0 .. 14, or FAIL. */
3635 static int
3636 parse_cond (char **str)
3637 {
3638 char *p, *q;
3639 const struct asm_cond *c;
3640
3641 p = q = *str;
3642 while (ISALPHA (*q))
3643 q++;
3644
3645 c = hash_find_n (arm_cond_hsh, p, q - p);
3646 if (!c)
3647 {
3648 inst.error = _("condition required");
3649 return FAIL;
3650 }
3651
3652 *str = q;
3653 return c->value;
3654 }
3655
3656 /* Parse the operands of a table branch instruction. Similar to a memory
3657 operand. */
3658 static int
3659 parse_tb (char **str)
3660 {
3661 char * p = *str;
3662 int reg;
3663
3664 if (skip_past_char (&p, '[') == FAIL)
3665 return FAIL;
3666
3667 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
3668 {
3669 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
3670 return FAIL;
3671 }
3672 inst.operands[0].reg = reg;
3673
3674 if (skip_past_comma (&p) == FAIL)
3675 return FAIL;
3676
3677 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
3678 {
3679 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
3680 return FAIL;
3681 }
3682 inst.operands[0].imm = reg;
3683
3684 if (skip_past_comma (&p) == SUCCESS)
3685 {
3686 if (parse_shift (&p, 0, SHIFT_LSL_IMMEDIATE) == FAIL)
3687 return FAIL;
3688 if (inst.reloc.exp.X_add_number != 1)
3689 {
3690 inst.error = _("invalid shift");
3691 return FAIL;
3692 }
3693 inst.operands[0].shifted = 1;
3694 }
3695
3696 if (skip_past_char (&p, ']') == FAIL)
3697 {
3698 inst.error = _("']' expected");
3699 return FAIL;
3700 }
3701 *str = p;
3702 return SUCCESS;
3703 }
3704
3705 /* Matcher codes for parse_operands. */
3706 enum operand_parse_code
3707 {
3708 OP_stop, /* end of line */
3709
3710 OP_RR, /* ARM register */
3711 OP_RRnpc, /* ARM register, not r15 */
3712 OP_RRnpcb, /* ARM register, not r15, in square brackets */
3713 OP_RRw, /* ARM register, not r15, optional trailing ! */
3714 OP_RCP, /* Coprocessor number */
3715 OP_RCN, /* Coprocessor register */
3716 OP_RF, /* FPA register */
3717 OP_RVS, /* VFP single precision register */
3718 OP_RVD, /* VFP double precision register */
3719 OP_RVC, /* VFP control register */
3720 OP_RMF, /* Maverick F register */
3721 OP_RMD, /* Maverick D register */
3722 OP_RMFX, /* Maverick FX register */
3723 OP_RMDX, /* Maverick DX register */
3724 OP_RMAX, /* Maverick AX register */
3725 OP_RMDS, /* Maverick DSPSC register */
3726 OP_RIWR, /* iWMMXt wR register */
3727 OP_RIWC, /* iWMMXt wC register */
3728 OP_RIWG, /* iWMMXt wCG register */
3729 OP_RXA, /* XScale accumulator register */
3730
3731 OP_REGLST, /* ARM register list */
3732 OP_VRSLST, /* VFP single-precision register list */
3733 OP_VRDLST, /* VFP double-precision register list */
3734
3735 OP_I7, /* immediate value 0 .. 7 */
3736 OP_I15, /* 0 .. 15 */
3737 OP_I16, /* 1 .. 16 */
3738 OP_I31, /* 0 .. 31 */
3739 OP_I31w, /* 0 .. 31, optional trailing ! */
3740 OP_I32, /* 1 .. 32 */
3741 OP_I63s, /* -64 .. 63 */
3742 OP_I255, /* 0 .. 255 */
3743 OP_Iffff, /* 0 .. 65535 */
3744
3745 OP_I4b, /* immediate, prefix optional, 1 .. 4 */
3746 OP_I7b, /* 0 .. 7 */
3747 OP_I15b, /* 0 .. 15 */
3748 OP_I31b, /* 0 .. 31 */
3749
3750 OP_SH, /* shifter operand */
3751 OP_ADDR, /* Memory address expression (any mode) */
3752 OP_EXP, /* arbitrary expression */
3753 OP_EXPi, /* same, with optional immediate prefix */
3754 OP_EXPr, /* same, with optional relocation suffix */
3755
3756 OP_CPSF, /* CPS flags */
3757 OP_ENDI, /* Endianness specifier */
3758 OP_PSR, /* CPSR/SPSR mask for msr */
3759 OP_COND, /* conditional code */
3760 OP_TB, /* Table branch. */
3761
3762 OP_RRnpc_I0, /* ARM register or literal 0 */
3763 OP_RR_EXr, /* ARM register or expression with opt. reloc suff. */
3764 OP_RR_EXi, /* ARM register or expression with imm prefix */
3765 OP_RF_IF, /* FPA register or immediate */
3766 OP_RIWR_RIWC, /* iWMMXt R or C reg */
3767
3768 /* Optional operands. */
3769 OP_oI7b, /* immediate, prefix optional, 0 .. 7 */
3770 OP_oI31b, /* 0 .. 31 */
3771 OP_oIffffb, /* 0 .. 65535 */
3772 OP_oI255c, /* curly-brace enclosed, 0 .. 255 */
3773
3774 OP_oRR, /* ARM register */
3775 OP_oRRnpc, /* ARM register, not the PC */
3776 OP_oSHll, /* LSL immediate */
3777 OP_oSHar, /* ASR immediate */
3778 OP_oSHllar, /* LSL or ASR immediate */
3779 OP_oROR, /* ROR 0/8/16/24 */
3780
3781 OP_FIRST_OPTIONAL = OP_oI7b
3782 };
3783
3784 /* Generic instruction operand parser. This does no encoding and no
3785 semantic validation; it merely squirrels values away in the inst
3786 structure. Returns SUCCESS or FAIL depending on whether the
3787 specified grammar matched. */
3788 static int
3789 parse_operands (char *str, const unsigned char *pattern)
3790 {
3791 unsigned const char *upat = pattern;
3792 char *backtrack_pos = 0;
3793 const char *backtrack_error = 0;
3794 int i, val, backtrack_index = 0;
3795
3796 #define po_char_or_fail(chr) do { \
3797 if (skip_past_char (&str, chr) == FAIL) \
3798 goto bad_args; \
3799 } while (0)
3800
3801 #define po_reg_or_fail(regtype) do { \
3802 val = arm_reg_parse (&str, regtype); \
3803 if (val == FAIL) \
3804 { \
3805 inst.error = _(reg_expected_msgs[regtype]); \
3806 goto failure; \
3807 } \
3808 inst.operands[i].reg = val; \
3809 inst.operands[i].isreg = 1; \
3810 } while (0)
3811
3812 #define po_reg_or_goto(regtype, label) do { \
3813 val = arm_reg_parse (&str, regtype); \
3814 if (val == FAIL) \
3815 goto label; \
3816 \
3817 inst.operands[i].reg = val; \
3818 inst.operands[i].isreg = 1; \
3819 } while (0)
3820
3821 #define po_imm_or_fail(min, max, popt) do { \
3822 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
3823 goto failure; \
3824 inst.operands[i].imm = val; \
3825 } while (0)
3826
3827 #define po_misc_or_fail(expr) do { \
3828 if (expr) \
3829 goto failure; \
3830 } while (0)
3831
3832 skip_whitespace (str);
3833
3834 for (i = 0; upat[i] != OP_stop; i++)
3835 {
3836 if (upat[i] >= OP_FIRST_OPTIONAL)
3837 {
3838 /* Remember where we are in case we need to backtrack. */
3839 assert (!backtrack_pos);
3840 backtrack_pos = str;
3841 backtrack_error = inst.error;
3842 backtrack_index = i;
3843 }
3844
3845 if (i > 0)
3846 po_char_or_fail (',');
3847
3848 switch (upat[i])
3849 {
3850 /* Registers */
3851 case OP_oRRnpc:
3852 case OP_RRnpc:
3853 case OP_oRR:
3854 case OP_RR: po_reg_or_fail (REG_TYPE_RN); break;
3855 case OP_RCP: po_reg_or_fail (REG_TYPE_CP); break;
3856 case OP_RCN: po_reg_or_fail (REG_TYPE_CN); break;
3857 case OP_RF: po_reg_or_fail (REG_TYPE_FN); break;
3858 case OP_RVS: po_reg_or_fail (REG_TYPE_VFS); break;
3859 case OP_RVD: po_reg_or_fail (REG_TYPE_VFD); break;
3860 case OP_RVC: po_reg_or_fail (REG_TYPE_VFC); break;
3861 case OP_RMF: po_reg_or_fail (REG_TYPE_MVF); break;
3862 case OP_RMD: po_reg_or_fail (REG_TYPE_MVD); break;
3863 case OP_RMFX: po_reg_or_fail (REG_TYPE_MVFX); break;
3864 case OP_RMDX: po_reg_or_fail (REG_TYPE_MVDX); break;
3865 case OP_RMAX: po_reg_or_fail (REG_TYPE_MVAX); break;
3866 case OP_RMDS: po_reg_or_fail (REG_TYPE_DSPSC); break;
3867 case OP_RIWR: po_reg_or_fail (REG_TYPE_MMXWR); break;
3868 case OP_RIWC: po_reg_or_fail (REG_TYPE_MMXWC); break;
3869 case OP_RIWG: po_reg_or_fail (REG_TYPE_MMXWCG); break;
3870 case OP_RXA: po_reg_or_fail (REG_TYPE_XSCALE); break;
3871
3872 case OP_RRnpcb:
3873 po_char_or_fail ('[');
3874 po_reg_or_fail (REG_TYPE_RN);
3875 po_char_or_fail (']');
3876 break;
3877
3878 case OP_RRw:
3879 po_reg_or_fail (REG_TYPE_RN);
3880 if (skip_past_char (&str, '!') == SUCCESS)
3881 inst.operands[i].writeback = 1;
3882 break;
3883
3884 /* Immediates */
3885 case OP_I7: po_imm_or_fail ( 0, 7, FALSE); break;
3886 case OP_I15: po_imm_or_fail ( 0, 15, FALSE); break;
3887 case OP_I16: po_imm_or_fail ( 1, 16, FALSE); break;
3888 case OP_I31: po_imm_or_fail ( 0, 31, FALSE); break;
3889 case OP_I32: po_imm_or_fail ( 1, 32, FALSE); break;
3890 case OP_I63s: po_imm_or_fail (-64, 63, FALSE); break;
3891 case OP_I255: po_imm_or_fail ( 0, 255, FALSE); break;
3892 case OP_Iffff: po_imm_or_fail ( 0, 0xffff, FALSE); break;
3893
3894 case OP_I4b: po_imm_or_fail ( 1, 4, TRUE); break;
3895 case OP_oI7b:
3896 case OP_I7b: po_imm_or_fail ( 0, 7, TRUE); break;
3897 case OP_I15b: po_imm_or_fail ( 0, 15, TRUE); break;
3898 case OP_oI31b:
3899 case OP_I31b: po_imm_or_fail ( 0, 31, TRUE); break;
3900 case OP_oIffffb: po_imm_or_fail ( 0, 0xffff, TRUE); break;
3901
3902 /* Immediate variants */
3903 case OP_oI255c:
3904 po_char_or_fail ('{');
3905 po_imm_or_fail (0, 255, TRUE);
3906 po_char_or_fail ('}');
3907 break;
3908
3909 case OP_I31w:
3910 /* The expression parser chokes on a trailing !, so we have
3911 to find it first and zap it. */
3912 {
3913 char *s = str;
3914 while (*s && *s != ',')
3915 s++;
3916 if (s[-1] == '!')
3917 {
3918 s[-1] = '\0';
3919 inst.operands[i].writeback = 1;
3920 }
3921 po_imm_or_fail (0, 31, TRUE);
3922 if (str == s - 1)
3923 str = s;
3924 }
3925 break;
3926
3927 /* Expressions */
3928 case OP_EXPi: EXPi:
3929 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
3930 GE_OPT_PREFIX));
3931 break;
3932
3933 case OP_EXP:
3934 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
3935 GE_NO_PREFIX));
3936 break;
3937
3938 case OP_EXPr: EXPr:
3939 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
3940 GE_NO_PREFIX));
3941 if (inst.reloc.exp.X_op == O_symbol)
3942 {
3943 val = parse_reloc (&str);
3944 if (val == -1)
3945 {
3946 inst.error = _("unrecognized relocation suffix");
3947 goto failure;
3948 }
3949 else if (val != BFD_RELOC_UNUSED)
3950 {
3951 inst.operands[i].imm = val;
3952 inst.operands[i].hasreloc = 1;
3953 }
3954 }
3955 break;
3956
3957 /* Register or expression */
3958 case OP_RR_EXr: po_reg_or_goto (REG_TYPE_RN, EXPr); break;
3959 case OP_RR_EXi: po_reg_or_goto (REG_TYPE_RN, EXPi); break;
3960
3961 /* Register or immediate */
3962 case OP_RRnpc_I0: po_reg_or_goto (REG_TYPE_RN, I0); break;
3963 I0: po_imm_or_fail (0, 0, FALSE); break;
3964
3965 case OP_RF_IF: po_reg_or_goto (REG_TYPE_FN, IF); break;
3966 IF:
3967 if (!is_immediate_prefix (*str))
3968 goto bad_args;
3969 str++;
3970 val = parse_fpa_immediate (&str);
3971 if (val == FAIL)
3972 goto failure;
3973 /* FPA immediates are encoded as registers 8-15.
3974 parse_fpa_immediate has already applied the offset. */
3975 inst.operands[i].reg = val;
3976 inst.operands[i].isreg = 1;
3977 break;
3978
3979 /* Two kinds of register */
3980 case OP_RIWR_RIWC:
3981 {
3982 struct reg_entry *rege = arm_reg_parse_multi (&str);
3983 if (rege->type != REG_TYPE_MMXWR
3984 && rege->type != REG_TYPE_MMXWC
3985 && rege->type != REG_TYPE_MMXWCG)
3986 {
3987 inst.error = _("iWMMXt data or control register expected");
3988 goto failure;
3989 }
3990 inst.operands[i].reg = rege->number;
3991 inst.operands[i].isreg = (rege->type == REG_TYPE_MMXWR);
3992 }
3993 break;
3994
3995 /* Misc */
3996 case OP_CPSF: val = parse_cps_flags (&str); break;
3997 case OP_ENDI: val = parse_endian_specifier (&str); break;
3998 case OP_oROR: val = parse_ror (&str); break;
3999 case OP_PSR: val = parse_psr (&str); break;
4000 case OP_COND: val = parse_cond (&str); break;
4001
4002 case OP_TB:
4003 po_misc_or_fail (parse_tb (&str));
4004 break;
4005
4006 /* Register lists */
4007 case OP_REGLST:
4008 val = parse_reg_list (&str);
4009 if (*str == '^')
4010 {
4011 inst.operands[1].writeback = 1;
4012 str++;
4013 }
4014 break;
4015
4016 case OP_VRSLST:
4017 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, 0);
4018 break;
4019
4020 case OP_VRDLST:
4021 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, 1);
4022 break;
4023
4024 /* Addressing modes */
4025 case OP_ADDR:
4026 po_misc_or_fail (parse_address (&str, i));
4027 break;
4028
4029 case OP_SH:
4030 po_misc_or_fail (parse_shifter_operand (&str, i));
4031 break;
4032
4033 case OP_oSHll:
4034 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_IMMEDIATE));
4035 break;
4036
4037 case OP_oSHar:
4038 po_misc_or_fail (parse_shift (&str, i, SHIFT_ASR_IMMEDIATE));
4039 break;
4040
4041 case OP_oSHllar:
4042 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_OR_ASR_IMMEDIATE));
4043 break;
4044
4045 default:
4046 as_fatal ("unhandled operand code %d", upat[i]);
4047 }
4048
4049 /* Various value-based sanity checks and shared operations. We
4050 do not signal immediate failures for the register constraints;
4051 this allows a syntax error to take precedence. */
4052 switch (upat[i])
4053 {
4054 case OP_oRRnpc:
4055 case OP_RRnpc:
4056 case OP_RRnpcb:
4057 case OP_RRw:
4058 case OP_RRnpc_I0:
4059 if (inst.operands[i].isreg && inst.operands[i].reg == REG_PC)
4060 inst.error = BAD_PC;
4061 break;
4062
4063 case OP_CPSF:
4064 case OP_ENDI:
4065 case OP_oROR:
4066 case OP_PSR:
4067 case OP_COND:
4068 case OP_REGLST:
4069 case OP_VRSLST:
4070 case OP_VRDLST:
4071 if (val == FAIL)
4072 goto failure;
4073 inst.operands[i].imm = val;
4074 break;
4075
4076 default:
4077 break;
4078 }
4079
4080 /* If we get here, this operand was successfully parsed. */
4081 inst.operands[i].present = 1;
4082 continue;
4083
4084 bad_args:
4085 inst.error = BAD_ARGS;
4086
4087 failure:
4088 if (!backtrack_pos)
4089 return FAIL;
4090
4091 /* Do not backtrack over a trailing optional argument that
4092 absorbed some text. We will only fail again, with the
4093 'garbage following instruction' error message, which is
4094 probably less helpful than the current one. */
4095 if (backtrack_index == i && backtrack_pos != str
4096 && upat[i+1] == OP_stop)
4097 return FAIL;
4098
4099 /* Try again, skipping the optional argument at backtrack_pos. */
4100 str = backtrack_pos;
4101 inst.error = backtrack_error;
4102 inst.operands[backtrack_index].present = 0;
4103 i = backtrack_index;
4104 backtrack_pos = 0;
4105 }
4106
4107 /* Check that we have parsed all the arguments. */
4108 if (*str != '\0' && !inst.error)
4109 inst.error = _("garbage following instruction");
4110
4111 return inst.error ? FAIL : SUCCESS;
4112 }
4113
4114 #undef po_char_or_fail
4115 #undef po_reg_or_fail
4116 #undef po_reg_or_goto
4117 #undef po_imm_or_fail
4118 \f
4119 /* Shorthand macro for instruction encoding functions issuing errors. */
4120 #define constraint(expr, err) do { \
4121 if (expr) \
4122 { \
4123 inst.error = err; \
4124 return; \
4125 } \
4126 } while (0)
4127
4128 /* Functions for operand encoding. ARM, then Thumb. */
4129
4130 #define rotate_left(v, n) (v << n | v >> (32 - n))
4131
4132 /* If VAL can be encoded in the immediate field of an ARM instruction,
4133 return the encoded form. Otherwise, return FAIL. */
4134
4135 static unsigned int
4136 encode_arm_immediate (unsigned int val)
4137 {
4138 unsigned int a, i;
4139
4140 for (i = 0; i < 32; i += 2)
4141 if ((a = rotate_left (val, i)) <= 0xff)
4142 return a | (i << 7); /* 12-bit pack: [shift-cnt,const]. */
4143
4144 return FAIL;
4145 }
4146
4147 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
4148 return the encoded form. Otherwise, return FAIL. */
4149 static unsigned int
4150 encode_thumb32_immediate (unsigned int val)
4151 {
4152 unsigned int a, i;
4153
4154 if (val <= 0xff)
4155 return val;
4156
4157 for (i = 1; i <= 24; i++)
4158 {
4159 a = val >> i;
4160 if ((val & ~(0xff << i)) == 0)
4161 return ((val >> i) & 0x7f) | ((32 - i) << 7);
4162 }
4163
4164 a = val & 0xff;
4165 if (val == ((a << 16) | a))
4166 return 0x100 | a;
4167 if (val == ((a << 24) | (a << 16) | (a << 8) | a))
4168 return 0x300 | a;
4169
4170 a = val & 0xff00;
4171 if (val == ((a << 16) | a))
4172 return 0x200 | (a >> 8);
4173
4174 return FAIL;
4175 }
4176 /* Encode a VFP SP register number into inst.instruction. */
4177
4178 static void
4179 encode_arm_vfp_sp_reg (int reg, enum vfp_sp_reg_pos pos)
4180 {
4181 switch (pos)
4182 {
4183 case VFP_REG_Sd:
4184 inst.instruction |= ((reg >> 1) << 12) | ((reg & 1) << 22);
4185 break;
4186
4187 case VFP_REG_Sn:
4188 inst.instruction |= ((reg >> 1) << 16) | ((reg & 1) << 7);
4189 break;
4190
4191 case VFP_REG_Sm:
4192 inst.instruction |= ((reg >> 1) << 0) | ((reg & 1) << 5);
4193 break;
4194
4195 default:
4196 abort ();
4197 }
4198 }
4199
4200 /* Encode a <shift> in an ARM-format instruction. The immediate,
4201 if any, is handled by md_apply_fix. */
4202 static void
4203 encode_arm_shift (int i)
4204 {
4205 if (inst.operands[i].shift_kind == SHIFT_RRX)
4206 inst.instruction |= SHIFT_ROR << 5;
4207 else
4208 {
4209 inst.instruction |= inst.operands[i].shift_kind << 5;
4210 if (inst.operands[i].immisreg)
4211 {
4212 inst.instruction |= SHIFT_BY_REG;
4213 inst.instruction |= inst.operands[i].imm << 8;
4214 }
4215 else
4216 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
4217 }
4218 }
4219
4220 static void
4221 encode_arm_shifter_operand (int i)
4222 {
4223 if (inst.operands[i].isreg)
4224 {
4225 inst.instruction |= inst.operands[i].reg;
4226 encode_arm_shift (i);
4227 }
4228 else
4229 inst.instruction |= INST_IMMEDIATE;
4230 }
4231
4232 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
4233 static void
4234 encode_arm_addr_mode_common (int i, bfd_boolean is_t)
4235 {
4236 assert (inst.operands[i].isreg);
4237 inst.instruction |= inst.operands[i].reg << 16;
4238
4239 if (inst.operands[i].preind)
4240 {
4241 if (is_t)
4242 {
4243 inst.error = _("instruction does not accept preindexed addressing");
4244 return;
4245 }
4246 inst.instruction |= PRE_INDEX;
4247 if (inst.operands[i].writeback)
4248 inst.instruction |= WRITE_BACK;
4249
4250 }
4251 else if (inst.operands[i].postind)
4252 {
4253 assert (inst.operands[i].writeback);
4254 if (is_t)
4255 inst.instruction |= WRITE_BACK;
4256 }
4257 else /* unindexed - only for coprocessor */
4258 {
4259 inst.error = _("instruction does not accept unindexed addressing");
4260 return;
4261 }
4262
4263 if (((inst.instruction & WRITE_BACK) || !(inst.instruction & PRE_INDEX))
4264 && (((inst.instruction & 0x000f0000) >> 16)
4265 == ((inst.instruction & 0x0000f000) >> 12)))
4266 as_warn ((inst.instruction & LOAD_BIT)
4267 ? _("destination register same as write-back base")
4268 : _("source register same as write-back base"));
4269 }
4270
4271 /* inst.operands[i] was set up by parse_address. Encode it into an
4272 ARM-format mode 2 load or store instruction. If is_t is true,
4273 reject forms that cannot be used with a T instruction (i.e. not
4274 post-indexed). */
4275 static void
4276 encode_arm_addr_mode_2 (int i, bfd_boolean is_t)
4277 {
4278 encode_arm_addr_mode_common (i, is_t);
4279
4280 if (inst.operands[i].immisreg)
4281 {
4282 inst.instruction |= INST_IMMEDIATE; /* yes, this is backwards */
4283 inst.instruction |= inst.operands[i].imm;
4284 if (!inst.operands[i].negative)
4285 inst.instruction |= INDEX_UP;
4286 if (inst.operands[i].shifted)
4287 {
4288 if (inst.operands[i].shift_kind == SHIFT_RRX)
4289 inst.instruction |= SHIFT_ROR << 5;
4290 else
4291 {
4292 inst.instruction |= inst.operands[i].shift_kind << 5;
4293 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
4294 }
4295 }
4296 }
4297 else /* immediate offset in inst.reloc */
4298 {
4299 if (inst.reloc.type == BFD_RELOC_UNUSED)
4300 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM;
4301 }
4302 }
4303
4304 /* inst.operands[i] was set up by parse_address. Encode it into an
4305 ARM-format mode 3 load or store instruction. Reject forms that
4306 cannot be used with such instructions. If is_t is true, reject
4307 forms that cannot be used with a T instruction (i.e. not
4308 post-indexed). */
4309 static void
4310 encode_arm_addr_mode_3 (int i, bfd_boolean is_t)
4311 {
4312 if (inst.operands[i].immisreg && inst.operands[i].shifted)
4313 {
4314 inst.error = _("instruction does not accept scaled register index");
4315 return;
4316 }
4317
4318 encode_arm_addr_mode_common (i, is_t);
4319
4320 if (inst.operands[i].immisreg)
4321 {
4322 inst.instruction |= inst.operands[i].imm;
4323 if (!inst.operands[i].negative)
4324 inst.instruction |= INDEX_UP;
4325 }
4326 else /* immediate offset in inst.reloc */
4327 {
4328 inst.instruction |= HWOFFSET_IMM;
4329 if (inst.reloc.type == BFD_RELOC_UNUSED)
4330 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
4331 }
4332 }
4333
4334 /* inst.operands[i] was set up by parse_address. Encode it into an
4335 ARM-format instruction. Reject all forms which cannot be encoded
4336 into a coprocessor load/store instruction. If wb_ok is false,
4337 reject use of writeback; if unind_ok is false, reject use of
4338 unindexed addressing. If reloc_override is not 0, use it instead
4339 of BFD_ARM_CP_OFF_IMM. */
4340
4341 static int
4342 encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override)
4343 {
4344 inst.instruction |= inst.operands[i].reg << 16;
4345
4346 assert (!(inst.operands[i].preind && inst.operands[i].postind));
4347
4348 if (!inst.operands[i].preind && !inst.operands[i].postind) /* unindexed */
4349 {
4350 assert (!inst.operands[i].writeback);
4351 if (!unind_ok)
4352 {
4353 inst.error = _("instruction does not support unindexed addressing");
4354 return FAIL;
4355 }
4356 inst.instruction |= inst.operands[i].imm;
4357 inst.instruction |= INDEX_UP;
4358 return SUCCESS;
4359 }
4360
4361 if (inst.operands[i].preind)
4362 inst.instruction |= PRE_INDEX;
4363
4364 if (inst.operands[i].writeback)
4365 {
4366 if (inst.operands[i].reg == REG_PC)
4367 {
4368 inst.error = _("pc may not be used with write-back");
4369 return FAIL;
4370 }
4371 if (!wb_ok)
4372 {
4373 inst.error = _("instruction does not support writeback");
4374 return FAIL;
4375 }
4376 inst.instruction |= WRITE_BACK;
4377 }
4378
4379 if (reloc_override)
4380 inst.reloc.type = reloc_override;
4381 else if (thumb_mode)
4382 inst.reloc.type = BFD_RELOC_ARM_T32_CP_OFF_IMM;
4383 else
4384 inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM;
4385 return SUCCESS;
4386 }
4387
4388 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
4389 Determine whether it can be performed with a move instruction; if
4390 it can, convert inst.instruction to that move instruction and
4391 return 1; if it can't, convert inst.instruction to a literal-pool
4392 load and return 0. If this is not a valid thing to do in the
4393 current context, set inst.error and return 1.
4394
4395 inst.operands[i] describes the destination register. */
4396
4397 static int
4398 move_or_literal_pool (int i, bfd_boolean thumb_p, bfd_boolean mode_3)
4399 {
4400 if ((inst.instruction & (thumb_p ? THUMB_LOAD_BIT : LOAD_BIT)) == 0)
4401 {
4402 inst.error = _("invalid pseudo operation");
4403 return 1;
4404 }
4405 if (inst.reloc.exp.X_op != O_constant && inst.reloc.exp.X_op != O_symbol)
4406 {
4407 inst.error = _("constant expression expected");
4408 return 1;
4409 }
4410 if (inst.reloc.exp.X_op == O_constant)
4411 {
4412 if (thumb_p)
4413 {
4414 if ((inst.reloc.exp.X_add_number & ~0xFF) == 0)
4415 {
4416 /* This can be done with a mov(1) instruction. */
4417 inst.instruction = T_OPCODE_MOV_I8 | (inst.operands[i].reg << 8);
4418 inst.instruction |= inst.reloc.exp.X_add_number;
4419 return 1;
4420 }
4421 }
4422 else
4423 {
4424 int value = encode_arm_immediate (inst.reloc.exp.X_add_number);
4425 if (value != FAIL)
4426 {
4427 /* This can be done with a mov instruction. */
4428 inst.instruction &= LITERAL_MASK;
4429 inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT);
4430 inst.instruction |= value & 0xfff;
4431 return 1;
4432 }
4433
4434 value = encode_arm_immediate (~inst.reloc.exp.X_add_number);
4435 if (value != FAIL)
4436 {
4437 /* This can be done with a mvn instruction. */
4438 inst.instruction &= LITERAL_MASK;
4439 inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT);
4440 inst.instruction |= value & 0xfff;
4441 return 1;
4442 }
4443 }
4444 }
4445
4446 if (add_to_lit_pool () == FAIL)
4447 {
4448 inst.error = _("literal pool insertion failed");
4449 return 1;
4450 }
4451 inst.operands[1].reg = REG_PC;
4452 inst.operands[1].isreg = 1;
4453 inst.operands[1].preind = 1;
4454 inst.reloc.pc_rel = 1;
4455 inst.reloc.type = (thumb_p
4456 ? BFD_RELOC_ARM_THUMB_OFFSET
4457 : (mode_3
4458 ? BFD_RELOC_ARM_HWLITERAL
4459 : BFD_RELOC_ARM_LITERAL));
4460 return 0;
4461 }
4462
4463 /* Functions for instruction encoding, sorted by subarchitecture.
4464 First some generics; their names are taken from the conventional
4465 bit positions for register arguments in ARM format instructions. */
4466
4467 static void
4468 do_noargs (void)
4469 {
4470 }
4471
4472 static void
4473 do_rd (void)
4474 {
4475 inst.instruction |= inst.operands[0].reg << 12;
4476 }
4477
4478 static void
4479 do_rd_rm (void)
4480 {
4481 inst.instruction |= inst.operands[0].reg << 12;
4482 inst.instruction |= inst.operands[1].reg;
4483 }
4484
4485 static void
4486 do_rd_rn (void)
4487 {
4488 inst.instruction |= inst.operands[0].reg << 12;
4489 inst.instruction |= inst.operands[1].reg << 16;
4490 }
4491
4492 static void
4493 do_rn_rd (void)
4494 {
4495 inst.instruction |= inst.operands[0].reg << 16;
4496 inst.instruction |= inst.operands[1].reg << 12;
4497 }
4498
4499 static void
4500 do_rd_rm_rn (void)
4501 {
4502 unsigned Rn = inst.operands[2].reg;
4503 /* Enforce resutrictions on SWP instruction. */
4504 if ((inst.instruction & 0x0fbfffff) == 0x01000090)
4505 constraint (Rn == inst.operands[0].reg || Rn == inst.operands[1].reg,
4506 _("Rn must not overlap other operands"));
4507 inst.instruction |= inst.operands[0].reg << 12;
4508 inst.instruction |= inst.operands[1].reg;
4509 inst.instruction |= Rn << 16;
4510 }
4511
4512 static void
4513 do_rd_rn_rm (void)
4514 {
4515 inst.instruction |= inst.operands[0].reg << 12;
4516 inst.instruction |= inst.operands[1].reg << 16;
4517 inst.instruction |= inst.operands[2].reg;
4518 }
4519
4520 static void
4521 do_rm_rd_rn (void)
4522 {
4523 inst.instruction |= inst.operands[0].reg;
4524 inst.instruction |= inst.operands[1].reg << 12;
4525 inst.instruction |= inst.operands[2].reg << 16;
4526 }
4527
4528 static void
4529 do_imm0 (void)
4530 {
4531 inst.instruction |= inst.operands[0].imm;
4532 }
4533
4534 static void
4535 do_rd_cpaddr (void)
4536 {
4537 inst.instruction |= inst.operands[0].reg << 12;
4538 encode_arm_cp_address (1, TRUE, TRUE, 0);
4539 }
4540
4541 /* ARM instructions, in alphabetical order by function name (except
4542 that wrapper functions appear immediately after the function they
4543 wrap). */
4544
4545 /* This is a pseudo-op of the form "adr rd, label" to be converted
4546 into a relative address of the form "add rd, pc, #label-.-8". */
4547
4548 static void
4549 do_adr (void)
4550 {
4551 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
4552
4553 /* Frag hacking will turn this into a sub instruction if the offset turns
4554 out to be negative. */
4555 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
4556 inst.reloc.pc_rel = 1;
4557 inst.reloc.exp.X_add_number -= 8;
4558 }
4559
4560 /* This is a pseudo-op of the form "adrl rd, label" to be converted
4561 into a relative address of the form:
4562 add rd, pc, #low(label-.-8)"
4563 add rd, rd, #high(label-.-8)" */
4564
4565 static void
4566 do_adrl (void)
4567 {
4568 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
4569
4570 /* Frag hacking will turn this into a sub instruction if the offset turns
4571 out to be negative. */
4572 inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE;
4573 inst.reloc.pc_rel = 1;
4574 inst.size = INSN_SIZE * 2;
4575 inst.reloc.exp.X_add_number -= 8;
4576 }
4577
4578 static void
4579 do_arit (void)
4580 {
4581 if (!inst.operands[1].present)
4582 inst.operands[1].reg = inst.operands[0].reg;
4583 inst.instruction |= inst.operands[0].reg << 12;
4584 inst.instruction |= inst.operands[1].reg << 16;
4585 encode_arm_shifter_operand (2);
4586 }
4587
4588 static void
4589 do_bfc (void)
4590 {
4591 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
4592 constraint (msb > 32, _("bit-field extends past end of register"));
4593 /* The instruction encoding stores the LSB and MSB,
4594 not the LSB and width. */
4595 inst.instruction |= inst.operands[0].reg << 12;
4596 inst.instruction |= inst.operands[1].imm << 7;
4597 inst.instruction |= (msb - 1) << 16;
4598 }
4599
4600 static void
4601 do_bfi (void)
4602 {
4603 unsigned int msb;
4604
4605 /* #0 in second position is alternative syntax for bfc, which is
4606 the same instruction but with REG_PC in the Rm field. */
4607 if (!inst.operands[1].isreg)
4608 inst.operands[1].reg = REG_PC;
4609
4610 msb = inst.operands[2].imm + inst.operands[3].imm;
4611 constraint (msb > 32, _("bit-field extends past end of register"));
4612 /* The instruction encoding stores the LSB and MSB,
4613 not the LSB and width. */
4614 inst.instruction |= inst.operands[0].reg << 12;
4615 inst.instruction |= inst.operands[1].reg;
4616 inst.instruction |= inst.operands[2].imm << 7;
4617 inst.instruction |= (msb - 1) << 16;
4618 }
4619
4620 static void
4621 do_bfx (void)
4622 {
4623 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
4624 _("bit-field extends past end of register"));
4625 inst.instruction |= inst.operands[0].reg << 12;
4626 inst.instruction |= inst.operands[1].reg;
4627 inst.instruction |= inst.operands[2].imm << 7;
4628 inst.instruction |= (inst.operands[3].imm - 1) << 16;
4629 }
4630
4631 /* ARM V5 breakpoint instruction (argument parse)
4632 BKPT <16 bit unsigned immediate>
4633 Instruction is not conditional.
4634 The bit pattern given in insns[] has the COND_ALWAYS condition,
4635 and it is an error if the caller tried to override that. */
4636
4637 static void
4638 do_bkpt (void)
4639 {
4640 /* Top 12 of 16 bits to bits 19:8. */
4641 inst.instruction |= (inst.operands[0].imm & 0xfff0) << 4;
4642
4643 /* Bottom 4 of 16 bits to bits 3:0. */
4644 inst.instruction |= inst.operands[0].imm & 0xf;
4645 }
4646
4647 static void
4648 encode_branch (int default_reloc)
4649 {
4650 if (inst.operands[0].hasreloc)
4651 {
4652 constraint (inst.operands[0].imm != BFD_RELOC_ARM_PLT32,
4653 _("the only suffix valid here is '(plt)'"));
4654 inst.reloc.type = BFD_RELOC_ARM_PLT32;
4655 }
4656 else
4657 {
4658 inst.reloc.type = default_reloc;
4659 }
4660 inst.reloc.pc_rel = 1;
4661 }
4662
4663 static void
4664 do_branch (void)
4665 {
4666 #ifdef OBJ_ELF
4667 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
4668 encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
4669 else
4670 #endif
4671 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
4672 }
4673
4674 static void
4675 do_bl (void)
4676 {
4677 #ifdef OBJ_ELF
4678 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
4679 {
4680 if (inst.cond == COND_ALWAYS)
4681 encode_branch (BFD_RELOC_ARM_PCREL_CALL);
4682 else
4683 encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
4684 }
4685 else
4686 #endif
4687 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
4688 }
4689
4690 /* ARM V5 branch-link-exchange instruction (argument parse)
4691 BLX <target_addr> ie BLX(1)
4692 BLX{<condition>} <Rm> ie BLX(2)
4693 Unfortunately, there are two different opcodes for this mnemonic.
4694 So, the insns[].value is not used, and the code here zaps values
4695 into inst.instruction.
4696 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
4697
4698 static void
4699 do_blx (void)
4700 {
4701 if (inst.operands[0].isreg)
4702 {
4703 /* Arg is a register; the opcode provided by insns[] is correct.
4704 It is not illegal to do "blx pc", just useless. */
4705 if (inst.operands[0].reg == REG_PC)
4706 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
4707
4708 inst.instruction |= inst.operands[0].reg;
4709 }
4710 else
4711 {
4712 /* Arg is an address; this instruction cannot be executed
4713 conditionally, and the opcode must be adjusted. */
4714 constraint (inst.cond != COND_ALWAYS, BAD_COND);
4715 inst.instruction = 0xfa000000;
4716 #ifdef OBJ_ELF
4717 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
4718 encode_branch (BFD_RELOC_ARM_PCREL_CALL);
4719 else
4720 #endif
4721 encode_branch (BFD_RELOC_ARM_PCREL_BLX);
4722 }
4723 }
4724
4725 static void
4726 do_bx (void)
4727 {
4728 if (inst.operands[0].reg == REG_PC)
4729 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
4730
4731 inst.instruction |= inst.operands[0].reg;
4732 }
4733
4734
4735 /* ARM v5TEJ. Jump to Jazelle code. */
4736
4737 static void
4738 do_bxj (void)
4739 {
4740 if (inst.operands[0].reg == REG_PC)
4741 as_tsktsk (_("use of r15 in bxj is not really useful"));
4742
4743 inst.instruction |= inst.operands[0].reg;
4744 }
4745
4746 /* Co-processor data operation:
4747 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
4748 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
4749 static void
4750 do_cdp (void)
4751 {
4752 inst.instruction |= inst.operands[0].reg << 8;
4753 inst.instruction |= inst.operands[1].imm << 20;
4754 inst.instruction |= inst.operands[2].reg << 12;
4755 inst.instruction |= inst.operands[3].reg << 16;
4756 inst.instruction |= inst.operands[4].reg;
4757 inst.instruction |= inst.operands[5].imm << 5;
4758 }
4759
4760 static void
4761 do_cmp (void)
4762 {
4763 inst.instruction |= inst.operands[0].reg << 16;
4764 encode_arm_shifter_operand (1);
4765 }
4766
4767 /* Transfer between coprocessor and ARM registers.
4768 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
4769 MRC2
4770 MCR{cond}
4771 MCR2
4772
4773 No special properties. */
4774
4775 static void
4776 do_co_reg (void)
4777 {
4778 inst.instruction |= inst.operands[0].reg << 8;
4779 inst.instruction |= inst.operands[1].imm << 21;
4780 inst.instruction |= inst.operands[2].reg << 12;
4781 inst.instruction |= inst.operands[3].reg << 16;
4782 inst.instruction |= inst.operands[4].reg;
4783 inst.instruction |= inst.operands[5].imm << 5;
4784 }
4785
4786 /* Transfer between coprocessor register and pair of ARM registers.
4787 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
4788 MCRR2
4789 MRRC{cond}
4790 MRRC2
4791
4792 Two XScale instructions are special cases of these:
4793
4794 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
4795 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
4796
4797 Result unpredicatable if Rd or Rn is R15. */
4798
4799 static void
4800 do_co_reg2c (void)
4801 {
4802 inst.instruction |= inst.operands[0].reg << 8;
4803 inst.instruction |= inst.operands[1].imm << 4;
4804 inst.instruction |= inst.operands[2].reg << 12;
4805 inst.instruction |= inst.operands[3].reg << 16;
4806 inst.instruction |= inst.operands[4].reg;
4807 }
4808
4809 static void
4810 do_cpsi (void)
4811 {
4812 inst.instruction |= inst.operands[0].imm << 6;
4813 inst.instruction |= inst.operands[1].imm;
4814 }
4815
4816 static void
4817 do_it (void)
4818 {
4819 /* There is no IT instruction in ARM mode. We
4820 process it but do not generate code for it. */
4821 inst.size = 0;
4822 }
4823
4824 static void
4825 do_ldmstm (void)
4826 {
4827 int base_reg = inst.operands[0].reg;
4828 int range = inst.operands[1].imm;
4829
4830 inst.instruction |= base_reg << 16;
4831 inst.instruction |= range;
4832
4833 if (inst.operands[1].writeback)
4834 inst.instruction |= LDM_TYPE_2_OR_3;
4835
4836 if (inst.operands[0].writeback)
4837 {
4838 inst.instruction |= WRITE_BACK;
4839 /* Check for unpredictable uses of writeback. */
4840 if (inst.instruction & LOAD_BIT)
4841 {
4842 /* Not allowed in LDM type 2. */
4843 if ((inst.instruction & LDM_TYPE_2_OR_3)
4844 && ((range & (1 << REG_PC)) == 0))
4845 as_warn (_("writeback of base register is UNPREDICTABLE"));
4846 /* Only allowed if base reg not in list for other types. */
4847 else if (range & (1 << base_reg))
4848 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
4849 }
4850 else /* STM. */
4851 {
4852 /* Not allowed for type 2. */
4853 if (inst.instruction & LDM_TYPE_2_OR_3)
4854 as_warn (_("writeback of base register is UNPREDICTABLE"));
4855 /* Only allowed if base reg not in list, or first in list. */
4856 else if ((range & (1 << base_reg))
4857 && (range & ((1 << base_reg) - 1)))
4858 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
4859 }
4860 }
4861 }
4862
4863 /* ARMv5TE load-consecutive (argument parse)
4864 Mode is like LDRH.
4865
4866 LDRccD R, mode
4867 STRccD R, mode. */
4868
4869 static void
4870 do_ldrd (void)
4871 {
4872 constraint (inst.operands[0].reg % 2 != 0,
4873 _("first destination register must be even"));
4874 constraint (inst.operands[1].present
4875 && inst.operands[1].reg != inst.operands[0].reg + 1,
4876 _("can only load two consecutive registers"));
4877 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
4878 constraint (!inst.operands[2].isreg, _("'[' expected"));
4879
4880 if (!inst.operands[1].present)
4881 inst.operands[1].reg = inst.operands[0].reg + 1;
4882
4883 if (inst.instruction & LOAD_BIT)
4884 {
4885 /* encode_arm_addr_mode_3 will diagnose overlap between the base
4886 register and the first register written; we have to diagnose
4887 overlap between the base and the second register written here. */
4888
4889 if (inst.operands[2].reg == inst.operands[1].reg
4890 && (inst.operands[2].writeback || inst.operands[2].postind))
4891 as_warn (_("base register written back, and overlaps "
4892 "second destination register"));
4893
4894 /* For an index-register load, the index register must not overlap the
4895 destination (even if not write-back). */
4896 else if (inst.operands[2].immisreg
4897 && ((unsigned) inst.operands[2].imm == inst.operands[0].reg
4898 || (unsigned) inst.operands[2].imm == inst.operands[1].reg))
4899 as_warn (_("index register overlaps destination register"));
4900 }
4901
4902 inst.instruction |= inst.operands[0].reg << 12;
4903 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE);
4904 }
4905
4906 static void
4907 do_ldrex (void)
4908 {
4909 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
4910 || inst.operands[1].postind || inst.operands[1].writeback
4911 || inst.operands[1].immisreg || inst.operands[1].shifted
4912 || inst.operands[1].negative
4913 /* This can arise if the programmer has written
4914 strex rN, rM, foo
4915 or if they have mistakenly used a register name as the last
4916 operand, eg:
4917 strex rN, rM, rX
4918 It is very difficult to distinguish between these two cases
4919 because "rX" might actually be a label. ie the register
4920 name has been occluded by a symbol of the same name. So we
4921 just generate a general 'bad addressing mode' type error
4922 message and leave it up to the programmer to discover the
4923 true cause and fix their mistake. */
4924 || (inst.operands[1].reg == REG_PC),
4925 BAD_ADDR_MODE);
4926
4927 constraint (inst.reloc.exp.X_op != O_constant
4928 || inst.reloc.exp.X_add_number != 0,
4929 _("offset must be zero in ARM encoding"));
4930
4931 inst.instruction |= inst.operands[0].reg << 12;
4932 inst.instruction |= inst.operands[1].reg << 16;
4933 inst.reloc.type = BFD_RELOC_UNUSED;
4934 }
4935
4936 static void
4937 do_ldrexd (void)
4938 {
4939 constraint (inst.operands[0].reg % 2 != 0,
4940 _("even register required"));
4941 constraint (inst.operands[1].present
4942 && inst.operands[1].reg != inst.operands[0].reg + 1,
4943 _("can only load two consecutive registers"));
4944 /* If op 1 were present and equal to PC, this function wouldn't
4945 have been called in the first place. */
4946 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
4947
4948 inst.instruction |= inst.operands[0].reg << 12;
4949 inst.instruction |= inst.operands[2].reg << 16;
4950 }
4951
4952 static void
4953 do_ldst (void)
4954 {
4955 inst.instruction |= inst.operands[0].reg << 12;
4956 if (!inst.operands[1].isreg)
4957 if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/FALSE))
4958 return;
4959 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE);
4960 }
4961
4962 static void
4963 do_ldstt (void)
4964 {
4965 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
4966 reject [Rn,...]. */
4967 if (inst.operands[1].preind)
4968 {
4969 constraint (inst.reloc.exp.X_op != O_constant ||
4970 inst.reloc.exp.X_add_number != 0,
4971 _("this instruction requires a post-indexed address"));
4972
4973 inst.operands[1].preind = 0;
4974 inst.operands[1].postind = 1;
4975 inst.operands[1].writeback = 1;
4976 }
4977 inst.instruction |= inst.operands[0].reg << 12;
4978 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE);
4979 }
4980
4981 /* Halfword and signed-byte load/store operations. */
4982
4983 static void
4984 do_ldstv4 (void)
4985 {
4986 inst.instruction |= inst.operands[0].reg << 12;
4987 if (!inst.operands[1].isreg)
4988 if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/TRUE))
4989 return;
4990 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE);
4991 }
4992
4993 static void
4994 do_ldsttv4 (void)
4995 {
4996 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
4997 reject [Rn,...]. */
4998 if (inst.operands[1].preind)
4999 {
5000 constraint (inst.reloc.exp.X_op != O_constant ||
5001 inst.reloc.exp.X_add_number != 0,
5002 _("this instruction requires a post-indexed address"));
5003
5004 inst.operands[1].preind = 0;
5005 inst.operands[1].postind = 1;
5006 inst.operands[1].writeback = 1;
5007 }
5008 inst.instruction |= inst.operands[0].reg << 12;
5009 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE);
5010 }
5011
5012 /* Co-processor register load/store.
5013 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
5014 static void
5015 do_lstc (void)
5016 {
5017 inst.instruction |= inst.operands[0].reg << 8;
5018 inst.instruction |= inst.operands[1].reg << 12;
5019 encode_arm_cp_address (2, TRUE, TRUE, 0);
5020 }
5021
5022 static void
5023 do_mlas (void)
5024 {
5025 /* This restriction does not apply to mls (nor to mla in v6, but
5026 that's hard to detect at present). */
5027 if (inst.operands[0].reg == inst.operands[1].reg
5028 && !(inst.instruction & 0x00400000))
5029 as_tsktsk (_("rd and rm should be different in mla"));
5030
5031 inst.instruction |= inst.operands[0].reg << 16;
5032 inst.instruction |= inst.operands[1].reg;
5033 inst.instruction |= inst.operands[2].reg << 8;
5034 inst.instruction |= inst.operands[3].reg << 12;
5035
5036 }
5037
5038 static void
5039 do_mov (void)
5040 {
5041 inst.instruction |= inst.operands[0].reg << 12;
5042 encode_arm_shifter_operand (1);
5043 }
5044
5045 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
5046 static void
5047 do_mov16 (void)
5048 {
5049 inst.instruction |= inst.operands[0].reg << 12;
5050 /* The value is in two pieces: 0:11, 16:19. */
5051 inst.instruction |= (inst.operands[1].imm & 0x00000fff);
5052 inst.instruction |= (inst.operands[1].imm & 0x0000f000) << 4;
5053 }
5054
5055 static void
5056 do_mrs (void)
5057 {
5058 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
5059 constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f))
5060 != (PSR_c|PSR_f),
5061 _("'CPSR' or 'SPSR' expected"));
5062 inst.instruction |= inst.operands[0].reg << 12;
5063 inst.instruction |= (inst.operands[1].imm & SPSR_BIT);
5064 }
5065
5066 /* Two possible forms:
5067 "{C|S}PSR_<field>, Rm",
5068 "{C|S}PSR_f, #expression". */
5069
5070 static void
5071 do_msr (void)
5072 {
5073 inst.instruction |= inst.operands[0].imm;
5074 if (inst.operands[1].isreg)
5075 inst.instruction |= inst.operands[1].reg;
5076 else
5077 {
5078 inst.instruction |= INST_IMMEDIATE;
5079 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
5080 inst.reloc.pc_rel = 0;
5081 }
5082 }
5083
5084 static void
5085 do_mul (void)
5086 {
5087 if (!inst.operands[2].present)
5088 inst.operands[2].reg = inst.operands[0].reg;
5089 inst.instruction |= inst.operands[0].reg << 16;
5090 inst.instruction |= inst.operands[1].reg;
5091 inst.instruction |= inst.operands[2].reg << 8;
5092
5093 if (inst.operands[0].reg == inst.operands[1].reg)
5094 as_tsktsk (_("rd and rm should be different in mul"));
5095 }
5096
5097 /* Long Multiply Parser
5098 UMULL RdLo, RdHi, Rm, Rs
5099 SMULL RdLo, RdHi, Rm, Rs
5100 UMLAL RdLo, RdHi, Rm, Rs
5101 SMLAL RdLo, RdHi, Rm, Rs. */
5102
5103 static void
5104 do_mull (void)
5105 {
5106 inst.instruction |= inst.operands[0].reg << 12;
5107 inst.instruction |= inst.operands[1].reg << 16;
5108 inst.instruction |= inst.operands[2].reg;
5109 inst.instruction |= inst.operands[3].reg << 8;
5110
5111 /* rdhi, rdlo and rm must all be different. */
5112 if (inst.operands[0].reg == inst.operands[1].reg
5113 || inst.operands[0].reg == inst.operands[2].reg
5114 || inst.operands[1].reg == inst.operands[2].reg)
5115 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
5116 }
5117
5118 static void
5119 do_nop (void)
5120 {
5121 if (inst.operands[0].present)
5122 {
5123 /* Architectural NOP hints are CPSR sets with no bits selected. */
5124 inst.instruction &= 0xf0000000;
5125 inst.instruction |= 0x0320f000 + inst.operands[0].imm;
5126 }
5127 }
5128
5129 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
5130 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
5131 Condition defaults to COND_ALWAYS.
5132 Error if Rd, Rn or Rm are R15. */
5133
5134 static void
5135 do_pkhbt (void)
5136 {
5137 inst.instruction |= inst.operands[0].reg << 12;
5138 inst.instruction |= inst.operands[1].reg << 16;
5139 inst.instruction |= inst.operands[2].reg;
5140 if (inst.operands[3].present)
5141 encode_arm_shift (3);
5142 }
5143
5144 /* ARM V6 PKHTB (Argument Parse). */
5145
5146 static void
5147 do_pkhtb (void)
5148 {
5149 if (!inst.operands[3].present)
5150 {
5151 /* If the shift specifier is omitted, turn the instruction
5152 into pkhbt rd, rm, rn. */
5153 inst.instruction &= 0xfff00010;
5154 inst.instruction |= inst.operands[0].reg << 12;
5155 inst.instruction |= inst.operands[1].reg;
5156 inst.instruction |= inst.operands[2].reg << 16;
5157 }
5158 else
5159 {
5160 inst.instruction |= inst.operands[0].reg << 12;
5161 inst.instruction |= inst.operands[1].reg << 16;
5162 inst.instruction |= inst.operands[2].reg;
5163 encode_arm_shift (3);
5164 }
5165 }
5166
5167 /* ARMv5TE: Preload-Cache
5168
5169 PLD <addr_mode>
5170
5171 Syntactically, like LDR with B=1, W=0, L=1. */
5172
5173 static void
5174 do_pld (void)
5175 {
5176 constraint (!inst.operands[0].isreg,
5177 _("'[' expected after PLD mnemonic"));
5178 constraint (inst.operands[0].postind,
5179 _("post-indexed expression used in preload instruction"));
5180 constraint (inst.operands[0].writeback,
5181 _("writeback used in preload instruction"));
5182 constraint (!inst.operands[0].preind,
5183 _("unindexed addressing used in preload instruction"));
5184 inst.instruction |= inst.operands[0].reg;
5185 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
5186 }
5187
5188 static void
5189 do_push_pop (void)
5190 {
5191 inst.operands[1] = inst.operands[0];
5192 memset (&inst.operands[0], 0, sizeof inst.operands[0]);
5193 inst.operands[0].isreg = 1;
5194 inst.operands[0].writeback = 1;
5195 inst.operands[0].reg = REG_SP;
5196 do_ldmstm ();
5197 }
5198
5199 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
5200 word at the specified address and the following word
5201 respectively.
5202 Unconditionally executed.
5203 Error if Rn is R15. */
5204
5205 static void
5206 do_rfe (void)
5207 {
5208 inst.instruction |= inst.operands[0].reg << 16;
5209 if (inst.operands[0].writeback)
5210 inst.instruction |= WRITE_BACK;
5211 }
5212
5213 /* ARM V6 ssat (argument parse). */
5214
5215 static void
5216 do_ssat (void)
5217 {
5218 inst.instruction |= inst.operands[0].reg << 12;
5219 inst.instruction |= (inst.operands[1].imm - 1) << 16;
5220 inst.instruction |= inst.operands[2].reg;
5221
5222 if (inst.operands[3].present)
5223 encode_arm_shift (3);
5224 }
5225
5226 /* ARM V6 usat (argument parse). */
5227
5228 static void
5229 do_usat (void)
5230 {
5231 inst.instruction |= inst.operands[0].reg << 12;
5232 inst.instruction |= inst.operands[1].imm << 16;
5233 inst.instruction |= inst.operands[2].reg;
5234
5235 if (inst.operands[3].present)
5236 encode_arm_shift (3);
5237 }
5238
5239 /* ARM V6 ssat16 (argument parse). */
5240
5241 static void
5242 do_ssat16 (void)
5243 {
5244 inst.instruction |= inst.operands[0].reg << 12;
5245 inst.instruction |= ((inst.operands[1].imm - 1) << 16);
5246 inst.instruction |= inst.operands[2].reg;
5247 }
5248
5249 static void
5250 do_usat16 (void)
5251 {
5252 inst.instruction |= inst.operands[0].reg << 12;
5253 inst.instruction |= inst.operands[1].imm << 16;
5254 inst.instruction |= inst.operands[2].reg;
5255 }
5256
5257 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
5258 preserving the other bits.
5259
5260 setend <endian_specifier>, where <endian_specifier> is either
5261 BE or LE. */
5262
5263 static void
5264 do_setend (void)
5265 {
5266 if (inst.operands[0].imm)
5267 inst.instruction |= 0x200;
5268 }
5269
5270 static void
5271 do_shift (void)
5272 {
5273 unsigned int Rm = (inst.operands[1].present
5274 ? inst.operands[1].reg
5275 : inst.operands[0].reg);
5276
5277 inst.instruction |= inst.operands[0].reg << 12;
5278 inst.instruction |= Rm;
5279 if (inst.operands[2].isreg) /* Rd, {Rm,} Rs */
5280 {
5281 inst.instruction |= inst.operands[2].reg << 8;
5282 inst.instruction |= SHIFT_BY_REG;
5283 }
5284 else
5285 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
5286 }
5287
5288 static void
5289 do_smc (void)
5290 {
5291 inst.reloc.type = BFD_RELOC_ARM_SMC;
5292 inst.reloc.pc_rel = 0;
5293 }
5294
5295 static void
5296 do_swi (void)
5297 {
5298 inst.reloc.type = BFD_RELOC_ARM_SWI;
5299 inst.reloc.pc_rel = 0;
5300 }
5301
5302 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
5303 SMLAxy{cond} Rd,Rm,Rs,Rn
5304 SMLAWy{cond} Rd,Rm,Rs,Rn
5305 Error if any register is R15. */
5306
5307 static void
5308 do_smla (void)
5309 {
5310 inst.instruction |= inst.operands[0].reg << 16;
5311 inst.instruction |= inst.operands[1].reg;
5312 inst.instruction |= inst.operands[2].reg << 8;
5313 inst.instruction |= inst.operands[3].reg << 12;
5314 }
5315
5316 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
5317 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
5318 Error if any register is R15.
5319 Warning if Rdlo == Rdhi. */
5320
5321 static void
5322 do_smlal (void)
5323 {
5324 inst.instruction |= inst.operands[0].reg << 12;
5325 inst.instruction |= inst.operands[1].reg << 16;
5326 inst.instruction |= inst.operands[2].reg;
5327 inst.instruction |= inst.operands[3].reg << 8;
5328
5329 if (inst.operands[0].reg == inst.operands[1].reg)
5330 as_tsktsk (_("rdhi and rdlo must be different"));
5331 }
5332
5333 /* ARM V5E (El Segundo) signed-multiply (argument parse)
5334 SMULxy{cond} Rd,Rm,Rs
5335 Error if any register is R15. */
5336
5337 static void
5338 do_smul (void)
5339 {
5340 inst.instruction |= inst.operands[0].reg << 16;
5341 inst.instruction |= inst.operands[1].reg;
5342 inst.instruction |= inst.operands[2].reg << 8;
5343 }
5344
5345 /* ARM V6 srs (argument parse). */
5346
5347 static void
5348 do_srs (void)
5349 {
5350 inst.instruction |= inst.operands[0].imm;
5351 if (inst.operands[0].writeback)
5352 inst.instruction |= WRITE_BACK;
5353 }
5354
5355 /* ARM V6 strex (argument parse). */
5356
5357 static void
5358 do_strex (void)
5359 {
5360 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
5361 || inst.operands[2].postind || inst.operands[2].writeback
5362 || inst.operands[2].immisreg || inst.operands[2].shifted
5363 || inst.operands[2].negative
5364 /* See comment in do_ldrex(). */
5365 || (inst.operands[2].reg == REG_PC),
5366 BAD_ADDR_MODE);
5367
5368 constraint (inst.operands[0].reg == inst.operands[1].reg
5369 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
5370
5371 constraint (inst.reloc.exp.X_op != O_constant
5372 || inst.reloc.exp.X_add_number != 0,
5373 _("offset must be zero in ARM encoding"));
5374
5375 inst.instruction |= inst.operands[0].reg << 12;
5376 inst.instruction |= inst.operands[1].reg;
5377 inst.instruction |= inst.operands[2].reg << 16;
5378 inst.reloc.type = BFD_RELOC_UNUSED;
5379 }
5380
5381 static void
5382 do_strexd (void)
5383 {
5384 constraint (inst.operands[1].reg % 2 != 0,
5385 _("even register required"));
5386 constraint (inst.operands[2].present
5387 && inst.operands[2].reg != inst.operands[1].reg + 1,
5388 _("can only store two consecutive registers"));
5389 /* If op 2 were present and equal to PC, this function wouldn't
5390 have been called in the first place. */
5391 constraint (inst.operands[1].reg == REG_LR, _("r14 not allowed here"));
5392
5393 constraint (inst.operands[0].reg == inst.operands[1].reg
5394 || inst.operands[0].reg == inst.operands[1].reg + 1
5395 || inst.operands[0].reg == inst.operands[3].reg,
5396 BAD_OVERLAP);
5397
5398 inst.instruction |= inst.operands[0].reg << 12;
5399 inst.instruction |= inst.operands[1].reg;
5400 inst.instruction |= inst.operands[3].reg << 16;
5401 }
5402
5403 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
5404 extends it to 32-bits, and adds the result to a value in another
5405 register. You can specify a rotation by 0, 8, 16, or 24 bits
5406 before extracting the 16-bit value.
5407 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
5408 Condition defaults to COND_ALWAYS.
5409 Error if any register uses R15. */
5410
5411 static void
5412 do_sxtah (void)
5413 {
5414 inst.instruction |= inst.operands[0].reg << 12;
5415 inst.instruction |= inst.operands[1].reg << 16;
5416 inst.instruction |= inst.operands[2].reg;
5417 inst.instruction |= inst.operands[3].imm << 10;
5418 }
5419
5420 /* ARM V6 SXTH.
5421
5422 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
5423 Condition defaults to COND_ALWAYS.
5424 Error if any register uses R15. */
5425
5426 static void
5427 do_sxth (void)
5428 {
5429 inst.instruction |= inst.operands[0].reg << 12;
5430 inst.instruction |= inst.operands[1].reg;
5431 inst.instruction |= inst.operands[2].imm << 10;
5432 }
5433 \f
5434 /* VFP instructions. In a logical order: SP variant first, monad
5435 before dyad, arithmetic then move then load/store. */
5436
5437 static void
5438 do_vfp_sp_monadic (void)
5439 {
5440 encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sd);
5441 encode_arm_vfp_sp_reg (inst.operands[1].reg, VFP_REG_Sm);
5442 }
5443
5444 static void
5445 do_vfp_sp_dyadic (void)
5446 {
5447 encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sd);
5448 encode_arm_vfp_sp_reg (inst.operands[1].reg, VFP_REG_Sn);
5449 encode_arm_vfp_sp_reg (inst.operands[2].reg, VFP_REG_Sm);
5450 }
5451
5452 static void
5453 do_vfp_sp_compare_z (void)
5454 {
5455 encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sd);
5456 }
5457
5458 static void
5459 do_vfp_dp_sp_cvt (void)
5460 {
5461 inst.instruction |= inst.operands[0].reg << 12;
5462 encode_arm_vfp_sp_reg (inst.operands[1].reg, VFP_REG_Sm);
5463 }
5464
5465 static void
5466 do_vfp_sp_dp_cvt (void)
5467 {
5468 encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sd);
5469 inst.instruction |= inst.operands[1].reg;
5470 }
5471
5472 static void
5473 do_vfp_reg_from_sp (void)
5474 {
5475 inst.instruction |= inst.operands[0].reg << 12;
5476 encode_arm_vfp_sp_reg (inst.operands[1].reg, VFP_REG_Sn);
5477 }
5478
5479 static void
5480 do_vfp_reg2_from_sp2 (void)
5481 {
5482 constraint (inst.operands[2].imm != 2,
5483 _("only two consecutive VFP SP registers allowed here"));
5484 inst.instruction |= inst.operands[0].reg << 12;
5485 inst.instruction |= inst.operands[1].reg << 16;
5486 encode_arm_vfp_sp_reg (inst.operands[2].reg, VFP_REG_Sm);
5487 }
5488
5489 static void
5490 do_vfp_sp_from_reg (void)
5491 {
5492 encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sn);
5493 inst.instruction |= inst.operands[1].reg << 12;
5494 }
5495
5496 static void
5497 do_vfp_sp2_from_reg2 (void)
5498 {
5499 constraint (inst.operands[0].imm != 2,
5500 _("only two consecutive VFP SP registers allowed here"));
5501 encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sm);
5502 inst.instruction |= inst.operands[1].reg << 12;
5503 inst.instruction |= inst.operands[2].reg << 16;
5504 }
5505
5506 static void
5507 do_vfp_sp_ldst (void)
5508 {
5509 encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sd);
5510 encode_arm_cp_address (1, FALSE, TRUE, 0);
5511 }
5512
5513 static void
5514 do_vfp_dp_ldst (void)
5515 {
5516 inst.instruction |= inst.operands[0].reg << 12;
5517 encode_arm_cp_address (1, FALSE, TRUE, 0);
5518 }
5519
5520
5521 static void
5522 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type)
5523 {
5524 if (inst.operands[0].writeback)
5525 inst.instruction |= WRITE_BACK;
5526 else
5527 constraint (ldstm_type != VFP_LDSTMIA,
5528 _("this addressing mode requires base-register writeback"));
5529 inst.instruction |= inst.operands[0].reg << 16;
5530 encode_arm_vfp_sp_reg (inst.operands[1].reg, VFP_REG_Sd);
5531 inst.instruction |= inst.operands[1].imm;
5532 }
5533
5534 static void
5535 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type)
5536 {
5537 int count;
5538
5539 if (inst.operands[0].writeback)
5540 inst.instruction |= WRITE_BACK;
5541 else
5542 constraint (ldstm_type != VFP_LDSTMIA && ldstm_type != VFP_LDSTMIAX,
5543 _("this addressing mode requires base-register writeback"));
5544
5545 inst.instruction |= inst.operands[0].reg << 16;
5546 inst.instruction |= inst.operands[1].reg << 12;
5547
5548 count = inst.operands[1].imm << 1;
5549 if (ldstm_type == VFP_LDSTMIAX || ldstm_type == VFP_LDSTMDBX)
5550 count += 1;
5551
5552 inst.instruction |= count;
5553 }
5554
5555 static void
5556 do_vfp_sp_ldstmia (void)
5557 {
5558 vfp_sp_ldstm (VFP_LDSTMIA);
5559 }
5560
5561 static void
5562 do_vfp_sp_ldstmdb (void)
5563 {
5564 vfp_sp_ldstm (VFP_LDSTMDB);
5565 }
5566
5567 static void
5568 do_vfp_dp_ldstmia (void)
5569 {
5570 vfp_dp_ldstm (VFP_LDSTMIA);
5571 }
5572
5573 static void
5574 do_vfp_dp_ldstmdb (void)
5575 {
5576 vfp_dp_ldstm (VFP_LDSTMDB);
5577 }
5578
5579 static void
5580 do_vfp_xp_ldstmia (void)
5581 {
5582 vfp_dp_ldstm (VFP_LDSTMIAX);
5583 }
5584
5585 static void
5586 do_vfp_xp_ldstmdb (void)
5587 {
5588 vfp_dp_ldstm (VFP_LDSTMDBX);
5589 }
5590 \f
5591 /* FPA instructions. Also in a logical order. */
5592
5593 static void
5594 do_fpa_cmp (void)
5595 {
5596 inst.instruction |= inst.operands[0].reg << 16;
5597 inst.instruction |= inst.operands[1].reg;
5598 }
5599
5600 static void
5601 do_fpa_ldmstm (void)
5602 {
5603 inst.instruction |= inst.operands[0].reg << 12;
5604 switch (inst.operands[1].imm)
5605 {
5606 case 1: inst.instruction |= CP_T_X; break;
5607 case 2: inst.instruction |= CP_T_Y; break;
5608 case 3: inst.instruction |= CP_T_Y | CP_T_X; break;
5609 case 4: break;
5610 default: abort ();
5611 }
5612
5613 if (inst.instruction & (PRE_INDEX | INDEX_UP))
5614 {
5615 /* The instruction specified "ea" or "fd", so we can only accept
5616 [Rn]{!}. The instruction does not really support stacking or
5617 unstacking, so we have to emulate these by setting appropriate
5618 bits and offsets. */
5619 constraint (inst.reloc.exp.X_op != O_constant
5620 || inst.reloc.exp.X_add_number != 0,
5621 _("this instruction does not support indexing"));
5622
5623 if ((inst.instruction & PRE_INDEX) || inst.operands[2].writeback)
5624 inst.reloc.exp.X_add_number = 12 * inst.operands[1].imm;
5625
5626 if (!(inst.instruction & INDEX_UP))
5627 inst.reloc.exp.X_add_number = -inst.reloc.exp.X_add_number;
5628
5629 if (!(inst.instruction & PRE_INDEX) && inst.operands[2].writeback)
5630 {
5631 inst.operands[2].preind = 0;
5632 inst.operands[2].postind = 1;
5633 }
5634 }
5635
5636 encode_arm_cp_address (2, TRUE, TRUE, 0);
5637 }
5638 \f
5639 /* iWMMXt instructions: strictly in alphabetical order. */
5640
5641 static void
5642 do_iwmmxt_tandorc (void)
5643 {
5644 constraint (inst.operands[0].reg != REG_PC, _("only r15 allowed here"));
5645 }
5646
5647 static void
5648 do_iwmmxt_textrc (void)
5649 {
5650 inst.instruction |= inst.operands[0].reg << 12;
5651 inst.instruction |= inst.operands[1].imm;
5652 }
5653
5654 static void
5655 do_iwmmxt_textrm (void)
5656 {
5657 inst.instruction |= inst.operands[0].reg << 12;
5658 inst.instruction |= inst.operands[1].reg << 16;
5659 inst.instruction |= inst.operands[2].imm;
5660 }
5661
5662 static void
5663 do_iwmmxt_tinsr (void)
5664 {
5665 inst.instruction |= inst.operands[0].reg << 16;
5666 inst.instruction |= inst.operands[1].reg << 12;
5667 inst.instruction |= inst.operands[2].imm;
5668 }
5669
5670 static void
5671 do_iwmmxt_tmia (void)
5672 {
5673 inst.instruction |= inst.operands[0].reg << 5;
5674 inst.instruction |= inst.operands[1].reg;
5675 inst.instruction |= inst.operands[2].reg << 12;
5676 }
5677
5678 static void
5679 do_iwmmxt_waligni (void)
5680 {
5681 inst.instruction |= inst.operands[0].reg << 12;
5682 inst.instruction |= inst.operands[1].reg << 16;
5683 inst.instruction |= inst.operands[2].reg;
5684 inst.instruction |= inst.operands[3].imm << 20;
5685 }
5686
5687 static void
5688 do_iwmmxt_wmov (void)
5689 {
5690 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
5691 inst.instruction |= inst.operands[0].reg << 12;
5692 inst.instruction |= inst.operands[1].reg << 16;
5693 inst.instruction |= inst.operands[1].reg;
5694 }
5695
5696 static void
5697 do_iwmmxt_wldstbh (void)
5698 {
5699 int reloc;
5700 inst.instruction |= inst.operands[0].reg << 12;
5701 inst.reloc.exp.X_add_number *= 4;
5702 if (thumb_mode)
5703 reloc = BFD_RELOC_ARM_T32_CP_OFF_IMM_S2;
5704 else
5705 reloc = BFD_RELOC_ARM_CP_OFF_IMM_S2;
5706 encode_arm_cp_address (1, TRUE, FALSE, reloc);
5707 }
5708
5709 static void
5710 do_iwmmxt_wldstw (void)
5711 {
5712 /* RIWR_RIWC clears .isreg for a control register. */
5713 if (!inst.operands[0].isreg)
5714 {
5715 constraint (inst.cond != COND_ALWAYS, BAD_COND);
5716 inst.instruction |= 0xf0000000;
5717 }
5718
5719 inst.instruction |= inst.operands[0].reg << 12;
5720 encode_arm_cp_address (1, TRUE, TRUE, 0);
5721 }
5722
5723 static void
5724 do_iwmmxt_wldstd (void)
5725 {
5726 inst.instruction |= inst.operands[0].reg << 12;
5727 encode_arm_cp_address (1, TRUE, FALSE, 0);
5728 }
5729
5730 static void
5731 do_iwmmxt_wshufh (void)
5732 {
5733 inst.instruction |= inst.operands[0].reg << 12;
5734 inst.instruction |= inst.operands[1].reg << 16;
5735 inst.instruction |= ((inst.operands[2].imm & 0xf0) << 16);
5736 inst.instruction |= (inst.operands[2].imm & 0x0f);
5737 }
5738
5739 static void
5740 do_iwmmxt_wzero (void)
5741 {
5742 /* WZERO reg is an alias for WANDN reg, reg, reg. */
5743 inst.instruction |= inst.operands[0].reg;
5744 inst.instruction |= inst.operands[0].reg << 12;
5745 inst.instruction |= inst.operands[0].reg << 16;
5746 }
5747 \f
5748 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
5749 operations first, then control, shift, and load/store. */
5750
5751 /* Insns like "foo X,Y,Z". */
5752
5753 static void
5754 do_mav_triple (void)
5755 {
5756 inst.instruction |= inst.operands[0].reg << 16;
5757 inst.instruction |= inst.operands[1].reg;
5758 inst.instruction |= inst.operands[2].reg << 12;
5759 }
5760
5761 /* Insns like "foo W,X,Y,Z".
5762 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
5763
5764 static void
5765 do_mav_quad (void)
5766 {
5767 inst.instruction |= inst.operands[0].reg << 5;
5768 inst.instruction |= inst.operands[1].reg << 12;
5769 inst.instruction |= inst.operands[2].reg << 16;
5770 inst.instruction |= inst.operands[3].reg;
5771 }
5772
5773 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
5774 static void
5775 do_mav_dspsc (void)
5776 {
5777 inst.instruction |= inst.operands[1].reg << 12;
5778 }
5779
5780 /* Maverick shift immediate instructions.
5781 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
5782 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
5783
5784 static void
5785 do_mav_shift (void)
5786 {
5787 int imm = inst.operands[2].imm;
5788
5789 inst.instruction |= inst.operands[0].reg << 12;
5790 inst.instruction |= inst.operands[1].reg << 16;
5791
5792 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
5793 Bits 5-7 of the insn should have bits 4-6 of the immediate.
5794 Bit 4 should be 0. */
5795 imm = (imm & 0xf) | ((imm & 0x70) << 1);
5796
5797 inst.instruction |= imm;
5798 }
5799 \f
5800 /* XScale instructions. Also sorted arithmetic before move. */
5801
5802 /* Xscale multiply-accumulate (argument parse)
5803 MIAcc acc0,Rm,Rs
5804 MIAPHcc acc0,Rm,Rs
5805 MIAxycc acc0,Rm,Rs. */
5806
5807 static void
5808 do_xsc_mia (void)
5809 {
5810 inst.instruction |= inst.operands[1].reg;
5811 inst.instruction |= inst.operands[2].reg << 12;
5812 }
5813
5814 /* Xscale move-accumulator-register (argument parse)
5815
5816 MARcc acc0,RdLo,RdHi. */
5817
5818 static void
5819 do_xsc_mar (void)
5820 {
5821 inst.instruction |= inst.operands[1].reg << 12;
5822 inst.instruction |= inst.operands[2].reg << 16;
5823 }
5824
5825 /* Xscale move-register-accumulator (argument parse)
5826
5827 MRAcc RdLo,RdHi,acc0. */
5828
5829 static void
5830 do_xsc_mra (void)
5831 {
5832 constraint (inst.operands[0].reg == inst.operands[1].reg, BAD_OVERLAP);
5833 inst.instruction |= inst.operands[0].reg << 12;
5834 inst.instruction |= inst.operands[1].reg << 16;
5835 }
5836 \f
5837 /* Encoding functions relevant only to Thumb. */
5838
5839 /* inst.operands[i] is a shifted-register operand; encode
5840 it into inst.instruction in the format used by Thumb32. */
5841
5842 static void
5843 encode_thumb32_shifted_operand (int i)
5844 {
5845 unsigned int value = inst.reloc.exp.X_add_number;
5846 unsigned int shift = inst.operands[i].shift_kind;
5847
5848 constraint (inst.operands[i].immisreg,
5849 _("shift by register not allowed in thumb mode"));
5850 inst.instruction |= inst.operands[i].reg;
5851 if (shift == SHIFT_RRX)
5852 inst.instruction |= SHIFT_ROR << 4;
5853 else
5854 {
5855 constraint (inst.reloc.exp.X_op != O_constant,
5856 _("expression too complex"));
5857
5858 constraint (value > 32
5859 || (value == 32 && (shift == SHIFT_LSL
5860 || shift == SHIFT_ROR)),
5861 _("shift expression is too large"));
5862
5863 if (value == 0)
5864 shift = SHIFT_LSL;
5865 else if (value == 32)
5866 value = 0;
5867
5868 inst.instruction |= shift << 4;
5869 inst.instruction |= (value & 0x1c) << 10;
5870 inst.instruction |= (value & 0x03) << 6;
5871 }
5872 }
5873
5874
5875 /* inst.operands[i] was set up by parse_address. Encode it into a
5876 Thumb32 format load or store instruction. Reject forms that cannot
5877 be used with such instructions. If is_t is true, reject forms that
5878 cannot be used with a T instruction; if is_d is true, reject forms
5879 that cannot be used with a D instruction. */
5880
5881 static void
5882 encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d)
5883 {
5884 bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);
5885
5886 constraint (!inst.operands[i].isreg,
5887 _("Thumb does not support the ldr =N pseudo-operation"));
5888
5889 inst.instruction |= inst.operands[i].reg << 16;
5890 if (inst.operands[i].immisreg)
5891 {
5892 constraint (is_pc, _("cannot use register index with PC-relative addressing"));
5893 constraint (is_t || is_d, _("cannot use register index with this instruction"));
5894 constraint (inst.operands[i].negative,
5895 _("Thumb does not support negative register indexing"));
5896 constraint (inst.operands[i].postind,
5897 _("Thumb does not support register post-indexing"));
5898 constraint (inst.operands[i].writeback,
5899 _("Thumb does not support register indexing with writeback"));
5900 constraint (inst.operands[i].shifted && inst.operands[i].shift_kind != SHIFT_LSL,
5901 _("Thumb supports only LSL in shifted register indexing"));
5902
5903 inst.instruction |= inst.operands[1].imm;
5904 if (inst.operands[i].shifted)
5905 {
5906 constraint (inst.reloc.exp.X_op != O_constant,
5907 _("expression too complex"));
5908 constraint (inst.reloc.exp.X_add_number < 0
5909 || inst.reloc.exp.X_add_number > 3,
5910 _("shift out of range"));
5911 inst.instruction |= inst.reloc.exp.X_add_number << 4;
5912 }
5913 inst.reloc.type = BFD_RELOC_UNUSED;
5914 }
5915 else if (inst.operands[i].preind)
5916 {
5917 constraint (is_pc && inst.operands[i].writeback,
5918 _("cannot use writeback with PC-relative addressing"));
5919 constraint (is_t && inst.operands[1].writeback,
5920 _("cannot use writeback with this instruction"));
5921
5922 if (is_d)
5923 {
5924 inst.instruction |= 0x01000000;
5925 if (inst.operands[i].writeback)
5926 inst.instruction |= 0x00200000;
5927 }
5928 else
5929 {
5930 inst.instruction |= 0x00000c00;
5931 if (inst.operands[i].writeback)
5932 inst.instruction |= 0x00000100;
5933 }
5934 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
5935 }
5936 else if (inst.operands[i].postind)
5937 {
5938 assert (inst.operands[i].writeback);
5939 constraint (is_pc, _("cannot use post-indexing with PC-relative addressing"));
5940 constraint (is_t, _("cannot use post-indexing with this instruction"));
5941
5942 if (is_d)
5943 inst.instruction |= 0x00200000;
5944 else
5945 inst.instruction |= 0x00000900;
5946 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
5947 }
5948 else /* unindexed - only for coprocessor */
5949 inst.error = _("instruction does not accept unindexed addressing");
5950 }
5951
5952 /* Table of Thumb instructions which exist in both 16- and 32-bit
5953 encodings (the latter only in post-V6T2 cores). The index is the
5954 value used in the insns table below. When there is more than one
5955 possible 16-bit encoding for the instruction, this table always
5956 holds variant (1).
5957 Also contains several pseudo-instructions used during relaxation. */
5958 #define T16_32_TAB \
5959 X(adc, 4140, eb400000), \
5960 X(adcs, 4140, eb500000), \
5961 X(add, 1c00, eb000000), \
5962 X(adds, 1c00, eb100000), \
5963 X(addi, 0000, f1000000), \
5964 X(addis, 0000, f1100000), \
5965 X(add_pc,000f, f20f0000), \
5966 X(add_sp,000d, f10d0000), \
5967 X(adr, 000f, f20f0000), \
5968 X(and, 4000, ea000000), \
5969 X(ands, 4000, ea100000), \
5970 X(asr, 1000, fa40f000), \
5971 X(asrs, 1000, fa50f000), \
5972 X(b, e000, f000b000), \
5973 X(bcond, d000, f0008000), \
5974 X(bic, 4380, ea200000), \
5975 X(bics, 4380, ea300000), \
5976 X(cmn, 42c0, eb100f00), \
5977 X(cmp, 2800, ebb00f00), \
5978 X(cpsie, b660, f3af8400), \
5979 X(cpsid, b670, f3af8600), \
5980 X(cpy, 4600, ea4f0000), \
5981 X(dec_sp,80dd, f1bd0d00), \
5982 X(eor, 4040, ea800000), \
5983 X(eors, 4040, ea900000), \
5984 X(inc_sp,00dd, f10d0d00), \
5985 X(ldmia, c800, e8900000), \
5986 X(ldr, 6800, f8500000), \
5987 X(ldrb, 7800, f8100000), \
5988 X(ldrh, 8800, f8300000), \
5989 X(ldrsb, 5600, f9100000), \
5990 X(ldrsh, 5e00, f9300000), \
5991 X(ldr_pc,4800, f85f0000), \
5992 X(ldr_pc2,4800, f85f0000), \
5993 X(ldr_sp,9800, f85d0000), \
5994 X(lsl, 0000, fa00f000), \
5995 X(lsls, 0000, fa10f000), \
5996 X(lsr, 0800, fa20f000), \
5997 X(lsrs, 0800, fa30f000), \
5998 X(mov, 2000, ea4f0000), \
5999 X(movs, 2000, ea5f0000), \
6000 X(mul, 4340, fb00f000), \
6001 X(muls, 4340, ffffffff), /* no 32b muls */ \
6002 X(mvn, 43c0, ea6f0000), \
6003 X(mvns, 43c0, ea7f0000), \
6004 X(neg, 4240, f1c00000), /* rsb #0 */ \
6005 X(negs, 4240, f1d00000), /* rsbs #0 */ \
6006 X(orr, 4300, ea400000), \
6007 X(orrs, 4300, ea500000), \
6008 X(pop, bc00, e8bd0000), /* ldmia sp!,... */ \
6009 X(push, b400, e92d0000), /* stmdb sp!,... */ \
6010 X(rev, ba00, fa90f080), \
6011 X(rev16, ba40, fa90f090), \
6012 X(revsh, bac0, fa90f0b0), \
6013 X(ror, 41c0, fa60f000), \
6014 X(rors, 41c0, fa70f000), \
6015 X(sbc, 4180, eb600000), \
6016 X(sbcs, 4180, eb700000), \
6017 X(stmia, c000, e8800000), \
6018 X(str, 6000, f8400000), \
6019 X(strb, 7000, f8000000), \
6020 X(strh, 8000, f8200000), \
6021 X(str_sp,9000, f84d0000), \
6022 X(sub, 1e00, eba00000), \
6023 X(subs, 1e00, ebb00000), \
6024 X(subi, 8000, f1a00000), \
6025 X(subis, 8000, f1b00000), \
6026 X(sxtb, b240, fa4ff080), \
6027 X(sxth, b200, fa0ff080), \
6028 X(tst, 4200, ea100f00), \
6029 X(uxtb, b2c0, fa5ff080), \
6030 X(uxth, b280, fa1ff080), \
6031 X(nop, bf00, f3af8000), \
6032 X(yield, bf10, f3af8001), \
6033 X(wfe, bf20, f3af8002), \
6034 X(wfi, bf30, f3af8003), \
6035 X(sev, bf40, f3af9004), /* typo, 8004? */
6036
6037 /* To catch errors in encoding functions, the codes are all offset by
6038 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
6039 as 16-bit instructions. */
6040 #define X(a,b,c) T_MNEM_##a
6041 enum t16_32_codes { T16_32_OFFSET = 0xF7FF, T16_32_TAB };
6042 #undef X
6043
6044 #define X(a,b,c) 0x##b
6045 static const unsigned short thumb_op16[] = { T16_32_TAB };
6046 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
6047 #undef X
6048
6049 #define X(a,b,c) 0x##c
6050 static const unsigned int thumb_op32[] = { T16_32_TAB };
6051 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
6052 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
6053 #undef X
6054 #undef T16_32_TAB
6055
6056 /* Thumb instruction encoders, in alphabetical order. */
6057
6058 /* ADDW or SUBW. */
6059 static void
6060 do_t_add_sub_w (void)
6061 {
6062 int Rd, Rn;
6063
6064 Rd = inst.operands[0].reg;
6065 Rn = inst.operands[1].reg;
6066
6067 constraint (Rd == 15, _("PC not allowed as destination"));
6068 inst.instruction |= (Rn << 16) | (Rd << 8);
6069 inst.reloc.type = BFD_RELOC_ARM_T32_IMM12;
6070 }
6071
6072 /* Parse an add or subtract instruction. We get here with inst.instruction
6073 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
6074
6075 static void
6076 do_t_add_sub (void)
6077 {
6078 int Rd, Rs, Rn;
6079
6080 Rd = inst.operands[0].reg;
6081 Rs = (inst.operands[1].present
6082 ? inst.operands[1].reg /* Rd, Rs, foo */
6083 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
6084
6085 if (unified_syntax)
6086 {
6087 bfd_boolean flags;
6088 bfd_boolean narrow;
6089 int opcode;
6090
6091 flags = (inst.instruction == T_MNEM_adds
6092 || inst.instruction == T_MNEM_subs);
6093 if (flags)
6094 narrow = (current_it_mask == 0);
6095 else
6096 narrow = (current_it_mask != 0);
6097 if (!inst.operands[2].isreg)
6098 {
6099 opcode = 0;
6100 if (inst.size_req != 4)
6101 {
6102 int add;
6103
6104 add = (inst.instruction == T_MNEM_add
6105 || inst.instruction == T_MNEM_adds);
6106 /* Attempt to use a narrow opcode, with relaxation if
6107 appropriate. */
6108 if (Rd == REG_SP && Rs == REG_SP && !flags)
6109 opcode = add ? T_MNEM_inc_sp : T_MNEM_dec_sp;
6110 else if (Rd <= 7 && Rs == REG_SP && add && !flags)
6111 opcode = T_MNEM_add_sp;
6112 else if (Rd <= 7 && Rs == REG_PC && add && !flags)
6113 opcode = T_MNEM_add_pc;
6114 else if (Rd <= 7 && Rs <= 7 && narrow)
6115 {
6116 if (flags)
6117 opcode = add ? T_MNEM_addis : T_MNEM_subis;
6118 else
6119 opcode = add ? T_MNEM_addi : T_MNEM_subi;
6120 }
6121 if (opcode)
6122 {
6123 inst.instruction = THUMB_OP16(opcode);
6124 inst.instruction |= (Rd << 4) | Rs;
6125 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
6126 if (inst.size_req != 2)
6127 inst.relax = opcode;
6128 }
6129 else
6130 constraint (inst.size_req == 2, BAD_HIREG);
6131 }
6132 if (inst.size_req == 4
6133 || (inst.size_req != 2 && !opcode))
6134 {
6135 /* ??? Convert large immediates to addw/subw. */
6136 inst.instruction = THUMB_OP32 (inst.instruction);
6137 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
6138 inst.instruction |= inst.operands[0].reg << 8;
6139 inst.instruction |= inst.operands[1].reg << 16;
6140 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
6141 }
6142 }
6143 else
6144 {
6145 Rn = inst.operands[2].reg;
6146 /* See if we can do this with a 16-bit instruction. */
6147 if (!inst.operands[2].shifted && inst.size_req != 4)
6148 {
6149 if (Rd > 7 || Rs > 7 || Rn > 7)
6150 narrow = FALSE;
6151
6152 if (narrow)
6153 {
6154 inst.instruction = ((inst.instruction == T_MNEM_adds
6155 || inst.instruction == T_MNEM_add)
6156 ? T_OPCODE_ADD_R3
6157 : T_OPCODE_SUB_R3);
6158 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
6159 return;
6160 }
6161
6162 if (inst.instruction == T_MNEM_add)
6163 {
6164 if (Rd == Rs)
6165 {
6166 inst.instruction = T_OPCODE_ADD_HI;
6167 inst.instruction |= (Rd & 8) << 4;
6168 inst.instruction |= (Rd & 7);
6169 inst.instruction |= Rn << 3;
6170 return;
6171 }
6172 /* ... because addition is commutative! */
6173 else if (Rd == Rn)
6174 {
6175 inst.instruction = T_OPCODE_ADD_HI;
6176 inst.instruction |= (Rd & 8) << 4;
6177 inst.instruction |= (Rd & 7);
6178 inst.instruction |= Rs << 3;
6179 return;
6180 }
6181 }
6182 }
6183 /* If we get here, it can't be done in 16 bits. */
6184 constraint (inst.operands[2].shifted && inst.operands[2].immisreg,
6185 _("shift must be constant"));
6186 inst.instruction = THUMB_OP32 (inst.instruction);
6187 inst.instruction |= Rd << 8;
6188 inst.instruction |= Rs << 16;
6189 encode_thumb32_shifted_operand (2);
6190 }
6191 }
6192 else
6193 {
6194 constraint (inst.instruction == T_MNEM_adds
6195 || inst.instruction == T_MNEM_subs,
6196 BAD_THUMB32);
6197
6198 if (!inst.operands[2].isreg) /* Rd, Rs, #imm */
6199 {
6200 constraint ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP))
6201 || (Rs > 7 && Rs != REG_SP && Rs != REG_PC),
6202 BAD_HIREG);
6203
6204 inst.instruction = (inst.instruction == T_MNEM_add
6205 ? 0x0000 : 0x8000);
6206 inst.instruction |= (Rd << 4) | Rs;
6207 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
6208 return;
6209 }
6210
6211 Rn = inst.operands[2].reg;
6212 constraint (inst.operands[2].shifted, _("unshifted register required"));
6213
6214 /* We now have Rd, Rs, and Rn set to registers. */
6215 if (Rd > 7 || Rs > 7 || Rn > 7)
6216 {
6217 /* Can't do this for SUB. */
6218 constraint (inst.instruction == T_MNEM_sub, BAD_HIREG);
6219 inst.instruction = T_OPCODE_ADD_HI;
6220 inst.instruction |= (Rd & 8) << 4;
6221 inst.instruction |= (Rd & 7);
6222 if (Rs == Rd)
6223 inst.instruction |= Rn << 3;
6224 else if (Rn == Rd)
6225 inst.instruction |= Rs << 3;
6226 else
6227 constraint (1, _("dest must overlap one source register"));
6228 }
6229 else
6230 {
6231 inst.instruction = (inst.instruction == T_MNEM_add
6232 ? T_OPCODE_ADD_R3 : T_OPCODE_SUB_R3);
6233 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
6234 }
6235 }
6236 }
6237
6238 static void
6239 do_t_adr (void)
6240 {
6241 if (unified_syntax && inst.size_req == 0 && inst.operands[0].reg <= 7)
6242 {
6243 /* Defer to section relaxation. */
6244 inst.relax = inst.instruction;
6245 inst.instruction = THUMB_OP16 (inst.instruction);
6246 inst.instruction |= inst.operands[0].reg << 4;
6247 }
6248 else if (unified_syntax && inst.size_req != 2)
6249 {
6250 /* Generate a 32-bit opcode. */
6251 inst.instruction = THUMB_OP32 (inst.instruction);
6252 inst.instruction |= inst.operands[0].reg << 8;
6253 inst.reloc.type = BFD_RELOC_ARM_T32_ADD_PC12;
6254 inst.reloc.pc_rel = 1;
6255 }
6256 else
6257 {
6258 /* Generate a 16-bit opcode. */
6259 inst.instruction = THUMB_OP16 (inst.instruction);
6260 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
6261 inst.reloc.exp.X_add_number -= 4; /* PC relative adjust. */
6262 inst.reloc.pc_rel = 1;
6263
6264 inst.instruction |= inst.operands[0].reg << 4;
6265 }
6266 }
6267
6268 /* Arithmetic instructions for which there is just one 16-bit
6269 instruction encoding, and it allows only two low registers.
6270 For maximal compatibility with ARM syntax, we allow three register
6271 operands even when Thumb-32 instructions are not available, as long
6272 as the first two are identical. For instance, both "sbc r0,r1" and
6273 "sbc r0,r0,r1" are allowed. */
6274 static void
6275 do_t_arit3 (void)
6276 {
6277 int Rd, Rs, Rn;
6278
6279 Rd = inst.operands[0].reg;
6280 Rs = (inst.operands[1].present
6281 ? inst.operands[1].reg /* Rd, Rs, foo */
6282 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
6283 Rn = inst.operands[2].reg;
6284
6285 if (unified_syntax)
6286 {
6287 if (!inst.operands[2].isreg)
6288 {
6289 /* For an immediate, we always generate a 32-bit opcode;
6290 section relaxation will shrink it later if possible. */
6291 inst.instruction = THUMB_OP32 (inst.instruction);
6292 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
6293 inst.instruction |= Rd << 8;
6294 inst.instruction |= Rs << 16;
6295 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
6296 }
6297 else
6298 {
6299 bfd_boolean narrow;
6300
6301 /* See if we can do this with a 16-bit instruction. */
6302 if (THUMB_SETS_FLAGS (inst.instruction))
6303 narrow = current_it_mask == 0;
6304 else
6305 narrow = current_it_mask != 0;
6306
6307 if (Rd > 7 || Rn > 7 || Rs > 7)
6308 narrow = FALSE;
6309 if (inst.operands[2].shifted)
6310 narrow = FALSE;
6311 if (inst.size_req == 4)
6312 narrow = FALSE;
6313
6314 if (narrow
6315 && Rd == Rs)
6316 {
6317 inst.instruction = THUMB_OP16 (inst.instruction);
6318 inst.instruction |= Rd;
6319 inst.instruction |= Rn << 3;
6320 return;
6321 }
6322
6323 /* If we get here, it can't be done in 16 bits. */
6324 constraint (inst.operands[2].shifted
6325 && inst.operands[2].immisreg,
6326 _("shift must be constant"));
6327 inst.instruction = THUMB_OP32 (inst.instruction);
6328 inst.instruction |= Rd << 8;
6329 inst.instruction |= Rs << 16;
6330 encode_thumb32_shifted_operand (2);
6331 }
6332 }
6333 else
6334 {
6335 /* On its face this is a lie - the instruction does set the
6336 flags. However, the only supported mnemonic in this mode
6337 says it doesn't. */
6338 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
6339
6340 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
6341 _("unshifted register required"));
6342 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
6343 constraint (Rd != Rs,
6344 _("dest and source1 must be the same register"));
6345
6346 inst.instruction = THUMB_OP16 (inst.instruction);
6347 inst.instruction |= Rd;
6348 inst.instruction |= Rn << 3;
6349 }
6350 }
6351
6352 /* Similarly, but for instructions where the arithmetic operation is
6353 commutative, so we can allow either of them to be different from
6354 the destination operand in a 16-bit instruction. For instance, all
6355 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
6356 accepted. */
6357 static void
6358 do_t_arit3c (void)
6359 {
6360 int Rd, Rs, Rn;
6361
6362 Rd = inst.operands[0].reg;
6363 Rs = (inst.operands[1].present
6364 ? inst.operands[1].reg /* Rd, Rs, foo */
6365 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
6366 Rn = inst.operands[2].reg;
6367
6368 if (unified_syntax)
6369 {
6370 if (!inst.operands[2].isreg)
6371 {
6372 /* For an immediate, we always generate a 32-bit opcode;
6373 section relaxation will shrink it later if possible. */
6374 inst.instruction = THUMB_OP32 (inst.instruction);
6375 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
6376 inst.instruction |= Rd << 8;
6377 inst.instruction |= Rs << 16;
6378 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
6379 }
6380 else
6381 {
6382 bfd_boolean narrow;
6383
6384 /* See if we can do this with a 16-bit instruction. */
6385 if (THUMB_SETS_FLAGS (inst.instruction))
6386 narrow = current_it_mask == 0;
6387 else
6388 narrow = current_it_mask != 0;
6389
6390 if (Rd > 7 || Rn > 7 || Rs > 7)
6391 narrow = FALSE;
6392 if (inst.operands[2].shifted)
6393 narrow = FALSE;
6394 if (inst.size_req == 4)
6395 narrow = FALSE;
6396
6397 if (narrow)
6398 {
6399 if (Rd == Rs)
6400 {
6401 inst.instruction = THUMB_OP16 (inst.instruction);
6402 inst.instruction |= Rd;
6403 inst.instruction |= Rn << 3;
6404 return;
6405 }
6406 if (Rd == Rn)
6407 {
6408 inst.instruction = THUMB_OP16 (inst.instruction);
6409 inst.instruction |= Rd;
6410 inst.instruction |= Rs << 3;
6411 return;
6412 }
6413 }
6414
6415 /* If we get here, it can't be done in 16 bits. */
6416 constraint (inst.operands[2].shifted
6417 && inst.operands[2].immisreg,
6418 _("shift must be constant"));
6419 inst.instruction = THUMB_OP32 (inst.instruction);
6420 inst.instruction |= Rd << 8;
6421 inst.instruction |= Rs << 16;
6422 encode_thumb32_shifted_operand (2);
6423 }
6424 }
6425 else
6426 {
6427 /* On its face this is a lie - the instruction does set the
6428 flags. However, the only supported mnemonic in this mode
6429 says it doesn't. */
6430 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
6431
6432 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
6433 _("unshifted register required"));
6434 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
6435
6436 inst.instruction = THUMB_OP16 (inst.instruction);
6437 inst.instruction |= Rd;
6438
6439 if (Rd == Rs)
6440 inst.instruction |= Rn << 3;
6441 else if (Rd == Rn)
6442 inst.instruction |= Rs << 3;
6443 else
6444 constraint (1, _("dest must overlap one source register"));
6445 }
6446 }
6447
6448 static void
6449 do_t_bfc (void)
6450 {
6451 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
6452 constraint (msb > 32, _("bit-field extends past end of register"));
6453 /* The instruction encoding stores the LSB and MSB,
6454 not the LSB and width. */
6455 inst.instruction |= inst.operands[0].reg << 8;
6456 inst.instruction |= (inst.operands[1].imm & 0x1c) << 10;
6457 inst.instruction |= (inst.operands[1].imm & 0x03) << 6;
6458 inst.instruction |= msb - 1;
6459 }
6460
6461 static void
6462 do_t_bfi (void)
6463 {
6464 unsigned int msb;
6465
6466 /* #0 in second position is alternative syntax for bfc, which is
6467 the same instruction but with REG_PC in the Rm field. */
6468 if (!inst.operands[1].isreg)
6469 inst.operands[1].reg = REG_PC;
6470
6471 msb = inst.operands[2].imm + inst.operands[3].imm;
6472 constraint (msb > 32, _("bit-field extends past end of register"));
6473 /* The instruction encoding stores the LSB and MSB,
6474 not the LSB and width. */
6475 inst.instruction |= inst.operands[0].reg << 8;
6476 inst.instruction |= inst.operands[1].reg << 16;
6477 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
6478 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
6479 inst.instruction |= msb - 1;
6480 }
6481
6482 static void
6483 do_t_bfx (void)
6484 {
6485 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
6486 _("bit-field extends past end of register"));
6487 inst.instruction |= inst.operands[0].reg << 8;
6488 inst.instruction |= inst.operands[1].reg << 16;
6489 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
6490 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
6491 inst.instruction |= inst.operands[3].imm - 1;
6492 }
6493
6494 /* ARM V5 Thumb BLX (argument parse)
6495 BLX <target_addr> which is BLX(1)
6496 BLX <Rm> which is BLX(2)
6497 Unfortunately, there are two different opcodes for this mnemonic.
6498 So, the insns[].value is not used, and the code here zaps values
6499 into inst.instruction.
6500
6501 ??? How to take advantage of the additional two bits of displacement
6502 available in Thumb32 mode? Need new relocation? */
6503
6504 static void
6505 do_t_blx (void)
6506 {
6507 if (inst.operands[0].isreg)
6508 /* We have a register, so this is BLX(2). */
6509 inst.instruction |= inst.operands[0].reg << 3;
6510 else
6511 {
6512 /* No register. This must be BLX(1). */
6513 inst.instruction = 0xf000e800;
6514 #ifdef OBJ_ELF
6515 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
6516 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23;
6517 else
6518 #endif
6519 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BLX;
6520 inst.reloc.pc_rel = 1;
6521 }
6522 }
6523
6524 static void
6525 do_t_branch (void)
6526 {
6527 int opcode;
6528 if (inst.cond != COND_ALWAYS)
6529 opcode = T_MNEM_bcond;
6530 else
6531 opcode = inst.instruction;
6532
6533 if (unified_syntax && inst.size_req == 4)
6534 {
6535 inst.instruction = THUMB_OP32(opcode);
6536 if (inst.cond == COND_ALWAYS)
6537 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH25;
6538 else
6539 {
6540 assert (inst.cond != 0xF);
6541 inst.instruction |= inst.cond << 22;
6542 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH20;
6543 }
6544 }
6545 else
6546 {
6547 inst.instruction = THUMB_OP16(opcode);
6548 if (inst.cond == COND_ALWAYS)
6549 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH12;
6550 else
6551 {
6552 inst.instruction |= inst.cond << 8;
6553 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH9;
6554 }
6555 /* Allow section relaxation. */
6556 if (unified_syntax && inst.size_req != 2)
6557 inst.relax = opcode;
6558 }
6559
6560 inst.reloc.pc_rel = 1;
6561 }
6562
6563 static void
6564 do_t_bkpt (void)
6565 {
6566 if (inst.operands[0].present)
6567 {
6568 constraint (inst.operands[0].imm > 255,
6569 _("immediate value out of range"));
6570 inst.instruction |= inst.operands[0].imm;
6571 }
6572 }
6573
6574 static void
6575 do_t_branch23 (void)
6576 {
6577 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23;
6578 inst.reloc.pc_rel = 1;
6579
6580 /* If the destination of the branch is a defined symbol which does not have
6581 the THUMB_FUNC attribute, then we must be calling a function which has
6582 the (interfacearm) attribute. We look for the Thumb entry point to that
6583 function and change the branch to refer to that function instead. */
6584 if ( inst.reloc.exp.X_op == O_symbol
6585 && inst.reloc.exp.X_add_symbol != NULL
6586 && S_IS_DEFINED (inst.reloc.exp.X_add_symbol)
6587 && ! THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol))
6588 inst.reloc.exp.X_add_symbol =
6589 find_real_start (inst.reloc.exp.X_add_symbol);
6590 }
6591
6592 static void
6593 do_t_bx (void)
6594 {
6595 inst.instruction |= inst.operands[0].reg << 3;
6596 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
6597 should cause the alignment to be checked once it is known. This is
6598 because BX PC only works if the instruction is word aligned. */
6599 }
6600
6601 static void
6602 do_t_bxj (void)
6603 {
6604 if (inst.operands[0].reg == REG_PC)
6605 as_tsktsk (_("use of r15 in bxj is not really useful"));
6606
6607 inst.instruction |= inst.operands[0].reg << 16;
6608 }
6609
6610 static void
6611 do_t_clz (void)
6612 {
6613 inst.instruction |= inst.operands[0].reg << 8;
6614 inst.instruction |= inst.operands[1].reg << 16;
6615 inst.instruction |= inst.operands[1].reg;
6616 }
6617
6618 static void
6619 do_t_cpsi (void)
6620 {
6621 if (unified_syntax
6622 && (inst.operands[1].present || inst.size_req == 4))
6623 {
6624 unsigned int imod = (inst.instruction & 0x0030) >> 4;
6625 inst.instruction = 0xf3af8000;
6626 inst.instruction |= imod << 9;
6627 inst.instruction |= inst.operands[0].imm << 5;
6628 if (inst.operands[1].present)
6629 inst.instruction |= 0x100 | inst.operands[1].imm;
6630 }
6631 else
6632 {
6633 constraint (inst.operands[1].present,
6634 _("Thumb does not support the 2-argument "
6635 "form of this instruction"));
6636 inst.instruction |= inst.operands[0].imm;
6637 }
6638 }
6639
6640 /* THUMB CPY instruction (argument parse). */
6641
6642 static void
6643 do_t_cpy (void)
6644 {
6645 if (inst.size_req == 4)
6646 {
6647 inst.instruction = THUMB_OP32 (T_MNEM_mov);
6648 inst.instruction |= inst.operands[0].reg << 8;
6649 inst.instruction |= inst.operands[1].reg;
6650 }
6651 else
6652 {
6653 inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
6654 inst.instruction |= (inst.operands[0].reg & 0x7);
6655 inst.instruction |= inst.operands[1].reg << 3;
6656 }
6657 }
6658
6659 static void
6660 do_t_czb (void)
6661 {
6662 constraint (inst.operands[0].reg > 7, BAD_HIREG);
6663 inst.instruction |= inst.operands[0].reg;
6664 inst.reloc.pc_rel = 1;
6665 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH7;
6666 }
6667
6668 static void
6669 do_t_hint (void)
6670 {
6671 if (unified_syntax && inst.size_req == 4)
6672 inst.instruction = THUMB_OP32 (inst.instruction);
6673 else
6674 inst.instruction = THUMB_OP16 (inst.instruction);
6675 }
6676
6677 static void
6678 do_t_it (void)
6679 {
6680 unsigned int cond = inst.operands[0].imm;
6681
6682 current_it_mask = (inst.instruction & 0xf) | 0x10;
6683 current_cc = cond;
6684
6685 /* If the condition is a negative condition, invert the mask. */
6686 if ((cond & 0x1) == 0x0)
6687 {
6688 unsigned int mask = inst.instruction & 0x000f;
6689
6690 if ((mask & 0x7) == 0)
6691 /* no conversion needed */;
6692 else if ((mask & 0x3) == 0)
6693 mask ^= 0x8;
6694 else if ((mask & 0x1) == 0)
6695 mask ^= 0xC;
6696 else
6697 mask ^= 0xE;
6698
6699 inst.instruction &= 0xfff0;
6700 inst.instruction |= mask;
6701 }
6702
6703 inst.instruction |= cond << 4;
6704 }
6705
6706 static void
6707 do_t_ldmstm (void)
6708 {
6709 /* This really doesn't seem worth it. */
6710 constraint (inst.reloc.type != BFD_RELOC_UNUSED,
6711 _("expression too complex"));
6712 constraint (inst.operands[1].writeback,
6713 _("Thumb load/store multiple does not support {reglist}^"));
6714
6715 if (unified_syntax)
6716 {
6717 /* See if we can use a 16-bit instruction. */
6718 if (inst.instruction < 0xffff /* not ldmdb/stmdb */
6719 && inst.size_req != 4
6720 && inst.operands[0].reg <= 7
6721 && !(inst.operands[1].imm & ~0xff)
6722 && (inst.instruction == T_MNEM_stmia
6723 ? inst.operands[0].writeback
6724 : (inst.operands[0].writeback
6725 == !(inst.operands[1].imm & (1 << inst.operands[0].reg)))))
6726 {
6727 if (inst.instruction == T_MNEM_stmia
6728 && (inst.operands[1].imm & (1 << inst.operands[0].reg))
6729 && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1)))
6730 as_warn (_("value stored for r%d is UNPREDICTABLE"),
6731 inst.operands[0].reg);
6732
6733 inst.instruction = THUMB_OP16 (inst.instruction);
6734 inst.instruction |= inst.operands[0].reg << 8;
6735 inst.instruction |= inst.operands[1].imm;
6736 }
6737 else
6738 {
6739 if (inst.operands[1].imm & (1 << 13))
6740 as_warn (_("SP should not be in register list"));
6741 if (inst.instruction == T_MNEM_stmia)
6742 {
6743 if (inst.operands[1].imm & (1 << 15))
6744 as_warn (_("PC should not be in register list"));
6745 if (inst.operands[1].imm & (1 << inst.operands[0].reg))
6746 as_warn (_("value stored for r%d is UNPREDICTABLE"),
6747 inst.operands[0].reg);
6748 }
6749 else
6750 {
6751 if (inst.operands[1].imm & (1 << 14)
6752 && inst.operands[1].imm & (1 << 15))
6753 as_warn (_("LR and PC should not both be in register list"));
6754 if ((inst.operands[1].imm & (1 << inst.operands[0].reg))
6755 && inst.operands[0].writeback)
6756 as_warn (_("base register should not be in register list "
6757 "when written back"));
6758 }
6759 if (inst.instruction < 0xffff)
6760 inst.instruction = THUMB_OP32 (inst.instruction);
6761 inst.instruction |= inst.operands[0].reg << 16;
6762 inst.instruction |= inst.operands[1].imm;
6763 if (inst.operands[0].writeback)
6764 inst.instruction |= WRITE_BACK;
6765 }
6766 }
6767 else
6768 {
6769 constraint (inst.operands[0].reg > 7
6770 || (inst.operands[1].imm & ~0xff), BAD_HIREG);
6771 if (inst.instruction == T_MNEM_stmia)
6772 {
6773 if (!inst.operands[0].writeback)
6774 as_warn (_("this instruction will write back the base register"));
6775 if ((inst.operands[1].imm & (1 << inst.operands[0].reg))
6776 && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1)))
6777 as_warn (_("value stored for r%d is UNPREDICTABLE"),
6778 inst.operands[0].reg);
6779 }
6780 else
6781 {
6782 if (!inst.operands[0].writeback
6783 && !(inst.operands[1].imm & (1 << inst.operands[0].reg)))
6784 as_warn (_("this instruction will write back the base register"));
6785 else if (inst.operands[0].writeback
6786 && (inst.operands[1].imm & (1 << inst.operands[0].reg)))
6787 as_warn (_("this instruction will not write back the base register"));
6788 }
6789
6790 inst.instruction = THUMB_OP16 (inst.instruction);
6791 inst.instruction |= inst.operands[0].reg << 8;
6792 inst.instruction |= inst.operands[1].imm;
6793 }
6794 }
6795
6796 static void
6797 do_t_ldrex (void)
6798 {
6799 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
6800 || inst.operands[1].postind || inst.operands[1].writeback
6801 || inst.operands[1].immisreg || inst.operands[1].shifted
6802 || inst.operands[1].negative,
6803 BAD_ADDR_MODE);
6804
6805 inst.instruction |= inst.operands[0].reg << 12;
6806 inst.instruction |= inst.operands[1].reg << 16;
6807 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8;
6808 }
6809
6810 static void
6811 do_t_ldrexd (void)
6812 {
6813 if (!inst.operands[1].present)
6814 {
6815 constraint (inst.operands[0].reg == REG_LR,
6816 _("r14 not allowed as first register "
6817 "when second register is omitted"));
6818 inst.operands[1].reg = inst.operands[0].reg + 1;
6819 }
6820 constraint (inst.operands[0].reg == inst.operands[1].reg,
6821 BAD_OVERLAP);
6822
6823 inst.instruction |= inst.operands[0].reg << 12;
6824 inst.instruction |= inst.operands[1].reg << 8;
6825 inst.instruction |= inst.operands[2].reg << 16;
6826 }
6827
6828 static void
6829 do_t_ldst (void)
6830 {
6831 unsigned long opcode;
6832 int Rn;
6833
6834 opcode = inst.instruction;
6835 if (unified_syntax)
6836 {
6837 if (inst.operands[1].isreg
6838 && !inst.operands[1].writeback
6839 && !inst.operands[1].shifted && !inst.operands[1].postind
6840 && !inst.operands[1].negative && inst.operands[0].reg <= 7
6841 && opcode <= 0xffff
6842 && inst.size_req != 4)
6843 {
6844 /* Insn may have a 16-bit form. */
6845 Rn = inst.operands[1].reg;
6846 if (inst.operands[1].immisreg)
6847 {
6848 inst.instruction = THUMB_OP16 (opcode);
6849 /* [Rn, Ri] */
6850 if (Rn <= 7 && inst.operands[1].imm <= 7)
6851 goto op16;
6852 }
6853 else if ((Rn <= 7 && opcode != T_MNEM_ldrsh
6854 && opcode != T_MNEM_ldrsb)
6855 || ((Rn == REG_PC || Rn == REG_SP) && opcode == T_MNEM_ldr)
6856 || (Rn == REG_SP && opcode == T_MNEM_str))
6857 {
6858 /* [Rn, #const] */
6859 if (Rn > 7)
6860 {
6861 if (Rn == REG_PC)
6862 {
6863 if (inst.reloc.pc_rel)
6864 opcode = T_MNEM_ldr_pc2;
6865 else
6866 opcode = T_MNEM_ldr_pc;
6867 }
6868 else
6869 {
6870 if (opcode == T_MNEM_ldr)
6871 opcode = T_MNEM_ldr_sp;
6872 else
6873 opcode = T_MNEM_str_sp;
6874 }
6875 inst.instruction = inst.operands[0].reg << 8;
6876 }
6877 else
6878 {
6879 inst.instruction = inst.operands[0].reg;
6880 inst.instruction |= inst.operands[1].reg << 3;
6881 }
6882 inst.instruction |= THUMB_OP16 (opcode);
6883 if (inst.size_req == 2)
6884 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
6885 else
6886 inst.relax = opcode;
6887 return;
6888 }
6889 }
6890 /* Definitely a 32-bit variant. */
6891 inst.instruction = THUMB_OP32 (opcode);
6892 inst.instruction |= inst.operands[0].reg << 12;
6893 encode_thumb32_addr_mode (1, /*is_t=*/FALSE, /*is_d=*/FALSE);
6894 return;
6895 }
6896
6897 constraint (inst.operands[0].reg > 7, BAD_HIREG);
6898
6899 if (inst.instruction == T_MNEM_ldrsh || inst.instruction == T_MNEM_ldrsb)
6900 {
6901 /* Only [Rn,Rm] is acceptable. */
6902 constraint (inst.operands[1].reg > 7 || inst.operands[1].imm > 7, BAD_HIREG);
6903 constraint (!inst.operands[1].isreg || !inst.operands[1].immisreg
6904 || inst.operands[1].postind || inst.operands[1].shifted
6905 || inst.operands[1].negative,
6906 _("Thumb does not support this addressing mode"));
6907 inst.instruction = THUMB_OP16 (inst.instruction);
6908 goto op16;
6909 }
6910
6911 inst.instruction = THUMB_OP16 (inst.instruction);
6912 if (!inst.operands[1].isreg)
6913 if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE))
6914 return;
6915
6916 constraint (!inst.operands[1].preind
6917 || inst.operands[1].shifted
6918 || inst.operands[1].writeback,
6919 _("Thumb does not support this addressing mode"));
6920 if (inst.operands[1].reg == REG_PC || inst.operands[1].reg == REG_SP)
6921 {
6922 constraint (inst.instruction & 0x0600,
6923 _("byte or halfword not valid for base register"));
6924 constraint (inst.operands[1].reg == REG_PC
6925 && !(inst.instruction & THUMB_LOAD_BIT),
6926 _("r15 based store not allowed"));
6927 constraint (inst.operands[1].immisreg,
6928 _("invalid base register for register offset"));
6929
6930 if (inst.operands[1].reg == REG_PC)
6931 inst.instruction = T_OPCODE_LDR_PC;
6932 else if (inst.instruction & THUMB_LOAD_BIT)
6933 inst.instruction = T_OPCODE_LDR_SP;
6934 else
6935 inst.instruction = T_OPCODE_STR_SP;
6936
6937 inst.instruction |= inst.operands[0].reg << 8;
6938 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
6939 return;
6940 }
6941
6942 constraint (inst.operands[1].reg > 7, BAD_HIREG);
6943 if (!inst.operands[1].immisreg)
6944 {
6945 /* Immediate offset. */
6946 inst.instruction |= inst.operands[0].reg;
6947 inst.instruction |= inst.operands[1].reg << 3;
6948 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
6949 return;
6950 }
6951
6952 /* Register offset. */
6953 constraint (inst.operands[1].imm > 7, BAD_HIREG);
6954 constraint (inst.operands[1].negative,
6955 _("Thumb does not support this addressing mode"));
6956
6957 op16:
6958 switch (inst.instruction)
6959 {
6960 case T_OPCODE_STR_IW: inst.instruction = T_OPCODE_STR_RW; break;
6961 case T_OPCODE_STR_IH: inst.instruction = T_OPCODE_STR_RH; break;
6962 case T_OPCODE_STR_IB: inst.instruction = T_OPCODE_STR_RB; break;
6963 case T_OPCODE_LDR_IW: inst.instruction = T_OPCODE_LDR_RW; break;
6964 case T_OPCODE_LDR_IH: inst.instruction = T_OPCODE_LDR_RH; break;
6965 case T_OPCODE_LDR_IB: inst.instruction = T_OPCODE_LDR_RB; break;
6966 case 0x5600 /* ldrsb */:
6967 case 0x5e00 /* ldrsh */: break;
6968 default: abort ();
6969 }
6970
6971 inst.instruction |= inst.operands[0].reg;
6972 inst.instruction |= inst.operands[1].reg << 3;
6973 inst.instruction |= inst.operands[1].imm << 6;
6974 }
6975
6976 static void
6977 do_t_ldstd (void)
6978 {
6979 if (!inst.operands[1].present)
6980 {
6981 inst.operands[1].reg = inst.operands[0].reg + 1;
6982 constraint (inst.operands[0].reg == REG_LR,
6983 _("r14 not allowed here"));
6984 }
6985 inst.instruction |= inst.operands[0].reg << 12;
6986 inst.instruction |= inst.operands[1].reg << 8;
6987 encode_thumb32_addr_mode (2, /*is_t=*/FALSE, /*is_d=*/TRUE);
6988
6989 }
6990
6991 static void
6992 do_t_ldstt (void)
6993 {
6994 inst.instruction |= inst.operands[0].reg << 12;
6995 encode_thumb32_addr_mode (1, /*is_t=*/TRUE, /*is_d=*/FALSE);
6996 }
6997
6998 static void
6999 do_t_mla (void)
7000 {
7001 inst.instruction |= inst.operands[0].reg << 8;
7002 inst.instruction |= inst.operands[1].reg << 16;
7003 inst.instruction |= inst.operands[2].reg;
7004 inst.instruction |= inst.operands[3].reg << 12;
7005 }
7006
7007 static void
7008 do_t_mlal (void)
7009 {
7010 inst.instruction |= inst.operands[0].reg << 12;
7011 inst.instruction |= inst.operands[1].reg << 8;
7012 inst.instruction |= inst.operands[2].reg << 16;
7013 inst.instruction |= inst.operands[3].reg;
7014 }
7015
7016 static void
7017 do_t_mov_cmp (void)
7018 {
7019 if (unified_syntax)
7020 {
7021 int r0off = (inst.instruction == T_MNEM_mov
7022 || inst.instruction == T_MNEM_movs) ? 8 : 16;
7023 unsigned long opcode;
7024 bfd_boolean narrow;
7025 bfd_boolean low_regs;
7026
7027 low_regs = (inst.operands[0].reg <= 7 && inst.operands[1].reg <= 7);
7028 opcode = inst.instruction;
7029 if (current_it_mask)
7030 narrow = opcode != T_MNEM_movs;
7031 else
7032 narrow = opcode != T_MNEM_movs || low_regs;
7033 if (inst.size_req == 4
7034 || inst.operands[1].shifted)
7035 narrow = FALSE;
7036
7037 if (!inst.operands[1].isreg)
7038 {
7039 /* Immediate operand. */
7040 if (current_it_mask == 0 && opcode == T_MNEM_mov)
7041 narrow = 0;
7042 if (low_regs && narrow)
7043 {
7044 inst.instruction = THUMB_OP16 (opcode);
7045 inst.instruction |= inst.operands[0].reg << 8;
7046 if (inst.size_req == 2)
7047 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
7048 else
7049 inst.relax = opcode;
7050 }
7051 else
7052 {
7053 inst.instruction = THUMB_OP32 (inst.instruction);
7054 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
7055 inst.instruction |= inst.operands[0].reg << r0off;
7056 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
7057 }
7058 }
7059 else if (!narrow)
7060 {
7061 inst.instruction = THUMB_OP32 (inst.instruction);
7062 inst.instruction |= inst.operands[0].reg << r0off;
7063 encode_thumb32_shifted_operand (1);
7064 }
7065 else
7066 switch (inst.instruction)
7067 {
7068 case T_MNEM_mov:
7069 inst.instruction = T_OPCODE_MOV_HR;
7070 inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
7071 inst.instruction |= (inst.operands[0].reg & 0x7);
7072 inst.instruction |= inst.operands[1].reg << 3;
7073 break;
7074
7075 case T_MNEM_movs:
7076 /* We know we have low registers at this point.
7077 Generate ADD Rd, Rs, #0. */
7078 inst.instruction = T_OPCODE_ADD_I3;
7079 inst.instruction |= inst.operands[0].reg;
7080 inst.instruction |= inst.operands[1].reg << 3;
7081 break;
7082
7083 case T_MNEM_cmp:
7084 if (low_regs)
7085 {
7086 inst.instruction = T_OPCODE_CMP_LR;
7087 inst.instruction |= inst.operands[0].reg;
7088 inst.instruction |= inst.operands[1].reg << 3;
7089 }
7090 else
7091 {
7092 inst.instruction = T_OPCODE_CMP_HR;
7093 inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
7094 inst.instruction |= (inst.operands[0].reg & 0x7);
7095 inst.instruction |= inst.operands[1].reg << 3;
7096 }
7097 break;
7098 }
7099 return;
7100 }
7101
7102 inst.instruction = THUMB_OP16 (inst.instruction);
7103 if (inst.operands[1].isreg)
7104 {
7105 if (inst.operands[0].reg < 8 && inst.operands[1].reg < 8)
7106 {
7107 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
7108 since a MOV instruction produces unpredictable results. */
7109 if (inst.instruction == T_OPCODE_MOV_I8)
7110 inst.instruction = T_OPCODE_ADD_I3;
7111 else
7112 inst.instruction = T_OPCODE_CMP_LR;
7113
7114 inst.instruction |= inst.operands[0].reg;
7115 inst.instruction |= inst.operands[1].reg << 3;
7116 }
7117 else
7118 {
7119 if (inst.instruction == T_OPCODE_MOV_I8)
7120 inst.instruction = T_OPCODE_MOV_HR;
7121 else
7122 inst.instruction = T_OPCODE_CMP_HR;
7123 do_t_cpy ();
7124 }
7125 }
7126 else
7127 {
7128 constraint (inst.operands[0].reg > 7,
7129 _("only lo regs allowed with immediate"));
7130 inst.instruction |= inst.operands[0].reg << 8;
7131 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
7132 }
7133 }
7134
7135 static void
7136 do_t_mov16 (void)
7137 {
7138 inst.instruction |= inst.operands[0].reg << 8;
7139 inst.instruction |= (inst.operands[1].imm & 0xf000) << 4;
7140 inst.instruction |= (inst.operands[1].imm & 0x0800) << 15;
7141 inst.instruction |= (inst.operands[1].imm & 0x0700) << 4;
7142 inst.instruction |= (inst.operands[1].imm & 0x00ff);
7143 }
7144
7145 static void
7146 do_t_mvn_tst (void)
7147 {
7148 if (unified_syntax)
7149 {
7150 int r0off = (inst.instruction == T_MNEM_mvn
7151 || inst.instruction == T_MNEM_mvns) ? 8 : 16;
7152 bfd_boolean narrow;
7153
7154 if (inst.size_req == 4
7155 || inst.instruction > 0xffff
7156 || inst.operands[1].shifted
7157 || inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
7158 narrow = FALSE;
7159 else if (inst.instruction == T_MNEM_cmn)
7160 narrow = TRUE;
7161 else if (THUMB_SETS_FLAGS (inst.instruction))
7162 narrow = (current_it_mask == 0);
7163 else
7164 narrow = (current_it_mask != 0);
7165
7166 if (!inst.operands[1].isreg)
7167 {
7168 /* For an immediate, we always generate a 32-bit opcode;
7169 section relaxation will shrink it later if possible. */
7170 if (inst.instruction < 0xffff)
7171 inst.instruction = THUMB_OP32 (inst.instruction);
7172 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
7173 inst.instruction |= inst.operands[0].reg << r0off;
7174 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
7175 }
7176 else
7177 {
7178 /* See if we can do this with a 16-bit instruction. */
7179 if (narrow)
7180 {
7181 inst.instruction = THUMB_OP16 (inst.instruction);
7182 inst.instruction |= inst.operands[0].reg;
7183 inst.instruction |= inst.operands[1].reg << 3;
7184 }
7185 else
7186 {
7187 constraint (inst.operands[1].shifted
7188 && inst.operands[1].immisreg,
7189 _("shift must be constant"));
7190 if (inst.instruction < 0xffff)
7191 inst.instruction = THUMB_OP32 (inst.instruction);
7192 inst.instruction |= inst.operands[0].reg << r0off;
7193 encode_thumb32_shifted_operand (1);
7194 }
7195 }
7196 }
7197 else
7198 {
7199 constraint (inst.instruction > 0xffff
7200 || inst.instruction == T_MNEM_mvns, BAD_THUMB32);
7201 constraint (!inst.operands[1].isreg || inst.operands[1].shifted,
7202 _("unshifted register required"));
7203 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7,
7204 BAD_HIREG);
7205
7206 inst.instruction = THUMB_OP16 (inst.instruction);
7207 inst.instruction |= inst.operands[0].reg;
7208 inst.instruction |= inst.operands[1].reg << 3;
7209 }
7210 }
7211
7212 static void
7213 do_t_mrs (void)
7214 {
7215 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
7216 constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f))
7217 != (PSR_c|PSR_f),
7218 _("'CPSR' or 'SPSR' expected"));
7219 inst.instruction |= inst.operands[0].reg << 8;
7220 inst.instruction |= (inst.operands[1].imm & SPSR_BIT) >> 2;
7221 }
7222
7223 static void
7224 do_t_msr (void)
7225 {
7226 constraint (!inst.operands[1].isreg,
7227 _("Thumb encoding does not support an immediate here"));
7228 inst.instruction |= (inst.operands[0].imm & SPSR_BIT) >> 2;
7229 inst.instruction |= (inst.operands[0].imm & ~SPSR_BIT) >> 8;
7230 inst.instruction |= inst.operands[1].reg << 16;
7231 }
7232
7233 static void
7234 do_t_mul (void)
7235 {
7236 if (!inst.operands[2].present)
7237 inst.operands[2].reg = inst.operands[0].reg;
7238
7239 /* There is no 32-bit MULS and no 16-bit MUL. */
7240 if (unified_syntax && inst.instruction == T_MNEM_mul)
7241 {
7242 inst.instruction = THUMB_OP32 (inst.instruction);
7243 inst.instruction |= inst.operands[0].reg << 8;
7244 inst.instruction |= inst.operands[1].reg << 16;
7245 inst.instruction |= inst.operands[2].reg << 0;
7246 }
7247 else
7248 {
7249 constraint (!unified_syntax
7250 && inst.instruction == T_MNEM_muls, BAD_THUMB32);
7251 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7,
7252 BAD_HIREG);
7253
7254 inst.instruction = THUMB_OP16 (inst.instruction);
7255 inst.instruction |= inst.operands[0].reg;
7256
7257 if (inst.operands[0].reg == inst.operands[1].reg)
7258 inst.instruction |= inst.operands[2].reg << 3;
7259 else if (inst.operands[0].reg == inst.operands[2].reg)
7260 inst.instruction |= inst.operands[1].reg << 3;
7261 else
7262 constraint (1, _("dest must overlap one source register"));
7263 }
7264 }
7265
7266 static void
7267 do_t_mull (void)
7268 {
7269 inst.instruction |= inst.operands[0].reg << 12;
7270 inst.instruction |= inst.operands[1].reg << 8;
7271 inst.instruction |= inst.operands[2].reg << 16;
7272 inst.instruction |= inst.operands[3].reg;
7273
7274 if (inst.operands[0].reg == inst.operands[1].reg)
7275 as_tsktsk (_("rdhi and rdlo must be different"));
7276 }
7277
7278 static void
7279 do_t_nop (void)
7280 {
7281 if (unified_syntax)
7282 {
7283 if (inst.size_req == 4 || inst.operands[0].imm > 15)
7284 {
7285 inst.instruction = THUMB_OP32 (inst.instruction);
7286 inst.instruction |= inst.operands[0].imm;
7287 }
7288 else
7289 {
7290 inst.instruction = THUMB_OP16 (inst.instruction);
7291 inst.instruction |= inst.operands[0].imm << 4;
7292 }
7293 }
7294 else
7295 {
7296 constraint (inst.operands[0].present,
7297 _("Thumb does not support NOP with hints"));
7298 inst.instruction = 0x46c0;
7299 }
7300 }
7301
7302 static void
7303 do_t_neg (void)
7304 {
7305 if (unified_syntax)
7306 {
7307 bfd_boolean narrow;
7308
7309 if (THUMB_SETS_FLAGS (inst.instruction))
7310 narrow = (current_it_mask == 0);
7311 else
7312 narrow = (current_it_mask != 0);
7313 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
7314 narrow = FALSE;
7315 if (inst.size_req == 4)
7316 narrow = FALSE;
7317
7318 if (!narrow)
7319 {
7320 inst.instruction = THUMB_OP32 (inst.instruction);
7321 inst.instruction |= inst.operands[0].reg << 8;
7322 inst.instruction |= inst.operands[1].reg << 16;
7323 }
7324 else
7325 {
7326 inst.instruction = THUMB_OP16 (inst.instruction);
7327 inst.instruction |= inst.operands[0].reg;
7328 inst.instruction |= inst.operands[1].reg << 3;
7329 }
7330 }
7331 else
7332 {
7333 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7,
7334 BAD_HIREG);
7335 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
7336
7337 inst.instruction = THUMB_OP16 (inst.instruction);
7338 inst.instruction |= inst.operands[0].reg;
7339 inst.instruction |= inst.operands[1].reg << 3;
7340 }
7341 }
7342
7343 static void
7344 do_t_pkhbt (void)
7345 {
7346 inst.instruction |= inst.operands[0].reg << 8;
7347 inst.instruction |= inst.operands[1].reg << 16;
7348 inst.instruction |= inst.operands[2].reg;
7349 if (inst.operands[3].present)
7350 {
7351 unsigned int val = inst.reloc.exp.X_add_number;
7352 constraint (inst.reloc.exp.X_op != O_constant,
7353 _("expression too complex"));
7354 inst.instruction |= (val & 0x1c) << 10;
7355 inst.instruction |= (val & 0x03) << 6;
7356 }
7357 }
7358
7359 static void
7360 do_t_pkhtb (void)
7361 {
7362 if (!inst.operands[3].present)
7363 inst.instruction &= ~0x00000020;
7364 do_t_pkhbt ();
7365 }
7366
7367 static void
7368 do_t_pld (void)
7369 {
7370 encode_thumb32_addr_mode (0, /*is_t=*/FALSE, /*is_d=*/FALSE);
7371 }
7372
7373 static void
7374 do_t_push_pop (void)
7375 {
7376 unsigned mask;
7377
7378 constraint (inst.operands[0].writeback,
7379 _("push/pop do not support {reglist}^"));
7380 constraint (inst.reloc.type != BFD_RELOC_UNUSED,
7381 _("expression too complex"));
7382
7383 mask = inst.operands[0].imm;
7384 if ((mask & ~0xff) == 0)
7385 inst.instruction = THUMB_OP16 (inst.instruction);
7386 else if ((inst.instruction == T_MNEM_push
7387 && (mask & ~0xff) == 1 << REG_LR)
7388 || (inst.instruction == T_MNEM_pop
7389 && (mask & ~0xff) == 1 << REG_PC))
7390 {
7391 inst.instruction = THUMB_OP16 (inst.instruction);
7392 inst.instruction |= THUMB_PP_PC_LR;
7393 mask &= 0xff;
7394 }
7395 else if (unified_syntax)
7396 {
7397 if (mask & (1 << 13))
7398 inst.error = _("SP not allowed in register list");
7399 if (inst.instruction == T_MNEM_push)
7400 {
7401 if (mask & (1 << 15))
7402 inst.error = _("PC not allowed in register list");
7403 }
7404 else
7405 {
7406 if (mask & (1 << 14)
7407 && mask & (1 << 15))
7408 inst.error = _("LR and PC should not both be in register list");
7409 }
7410 if ((mask & (mask - 1)) == 0)
7411 {
7412 /* Single register push/pop implemented as str/ldr. */
7413 if (inst.instruction == T_MNEM_push)
7414 inst.instruction = 0xf84d0d04; /* str reg, [sp, #-4]! */
7415 else
7416 inst.instruction = 0xf85d0b04; /* ldr reg, [sp], #4 */
7417 mask = ffs(mask) - 1;
7418 mask <<= 12;
7419 }
7420 else
7421 inst.instruction = THUMB_OP32 (inst.instruction);
7422 }
7423 else
7424 {
7425 inst.error = _("invalid register list to push/pop instruction");
7426 return;
7427 }
7428
7429 inst.instruction |= mask;
7430 }
7431
7432 static void
7433 do_t_rbit (void)
7434 {
7435 inst.instruction |= inst.operands[0].reg << 8;
7436 inst.instruction |= inst.operands[1].reg << 16;
7437 }
7438
7439 static void
7440 do_t_rev (void)
7441 {
7442 if (inst.operands[0].reg <= 7 && inst.operands[1].reg <= 7
7443 && inst.size_req != 4)
7444 {
7445 inst.instruction = THUMB_OP16 (inst.instruction);
7446 inst.instruction |= inst.operands[0].reg;
7447 inst.instruction |= inst.operands[1].reg << 3;
7448 }
7449 else if (unified_syntax)
7450 {
7451 inst.instruction = THUMB_OP32 (inst.instruction);
7452 inst.instruction |= inst.operands[0].reg << 8;
7453 inst.instruction |= inst.operands[1].reg << 16;
7454 inst.instruction |= inst.operands[1].reg;
7455 }
7456 else
7457 inst.error = BAD_HIREG;
7458 }
7459
7460 static void
7461 do_t_rsb (void)
7462 {
7463 int Rd, Rs;
7464
7465 Rd = inst.operands[0].reg;
7466 Rs = (inst.operands[1].present
7467 ? inst.operands[1].reg /* Rd, Rs, foo */
7468 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
7469
7470 inst.instruction |= Rd << 8;
7471 inst.instruction |= Rs << 16;
7472 if (!inst.operands[2].isreg)
7473 {
7474 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
7475 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
7476 }
7477 else
7478 encode_thumb32_shifted_operand (2);
7479 }
7480
7481 static void
7482 do_t_setend (void)
7483 {
7484 if (inst.operands[0].imm)
7485 inst.instruction |= 0x8;
7486 }
7487
7488 static void
7489 do_t_shift (void)
7490 {
7491 if (!inst.operands[1].present)
7492 inst.operands[1].reg = inst.operands[0].reg;
7493
7494 if (unified_syntax)
7495 {
7496 bfd_boolean narrow;
7497 int shift_kind;
7498
7499 switch (inst.instruction)
7500 {
7501 case T_MNEM_asr:
7502 case T_MNEM_asrs: shift_kind = SHIFT_ASR; break;
7503 case T_MNEM_lsl:
7504 case T_MNEM_lsls: shift_kind = SHIFT_LSL; break;
7505 case T_MNEM_lsr:
7506 case T_MNEM_lsrs: shift_kind = SHIFT_LSR; break;
7507 case T_MNEM_ror:
7508 case T_MNEM_rors: shift_kind = SHIFT_ROR; break;
7509 default: abort ();
7510 }
7511
7512 if (THUMB_SETS_FLAGS (inst.instruction))
7513 narrow = (current_it_mask == 0);
7514 else
7515 narrow = (current_it_mask != 0);
7516 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
7517 narrow = FALSE;
7518 if (!inst.operands[2].isreg && shift_kind == SHIFT_ROR)
7519 narrow = FALSE;
7520 if (inst.operands[2].isreg
7521 && (inst.operands[1].reg != inst.operands[0].reg
7522 || inst.operands[2].reg > 7))
7523 narrow = FALSE;
7524 if (inst.size_req == 4)
7525 narrow = FALSE;
7526
7527 if (!narrow)
7528 {
7529 if (inst.operands[2].isreg)
7530 {
7531 inst.instruction = THUMB_OP32 (inst.instruction);
7532 inst.instruction |= inst.operands[0].reg << 8;
7533 inst.instruction |= inst.operands[1].reg << 16;
7534 inst.instruction |= inst.operands[2].reg;
7535 }
7536 else
7537 {
7538 inst.operands[1].shifted = 1;
7539 inst.operands[1].shift_kind = shift_kind;
7540 inst.instruction = THUMB_OP32 (THUMB_SETS_FLAGS (inst.instruction)
7541 ? T_MNEM_movs : T_MNEM_mov);
7542 inst.instruction |= inst.operands[0].reg << 8;
7543 encode_thumb32_shifted_operand (1);
7544 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
7545 inst.reloc.type = BFD_RELOC_UNUSED;
7546 }
7547 }
7548 else
7549 {
7550 if (inst.operands[2].isreg)
7551 {
7552 switch (shift_kind)
7553 {
7554 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_R; break;
7555 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_R; break;
7556 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_R; break;
7557 case SHIFT_ROR: inst.instruction = T_OPCODE_ROR_R; break;
7558 default: abort ();
7559 }
7560
7561 inst.instruction |= inst.operands[0].reg;
7562 inst.instruction |= inst.operands[2].reg << 3;
7563 }
7564 else
7565 {
7566 switch (shift_kind)
7567 {
7568 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
7569 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
7570 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
7571 default: abort ();
7572 }
7573 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
7574 inst.instruction |= inst.operands[0].reg;
7575 inst.instruction |= inst.operands[1].reg << 3;
7576 }
7577 }
7578 }
7579 else
7580 {
7581 constraint (inst.operands[0].reg > 7
7582 || inst.operands[1].reg > 7, BAD_HIREG);
7583 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
7584
7585 if (inst.operands[2].isreg) /* Rd, {Rs,} Rn */
7586 {
7587 constraint (inst.operands[2].reg > 7, BAD_HIREG);
7588 constraint (inst.operands[0].reg != inst.operands[1].reg,
7589 _("source1 and dest must be same register"));
7590
7591 switch (inst.instruction)
7592 {
7593 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_R; break;
7594 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_R; break;
7595 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_R; break;
7596 case T_MNEM_ror: inst.instruction = T_OPCODE_ROR_R; break;
7597 default: abort ();
7598 }
7599
7600 inst.instruction |= inst.operands[0].reg;
7601 inst.instruction |= inst.operands[2].reg << 3;
7602 }
7603 else
7604 {
7605 switch (inst.instruction)
7606 {
7607 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_I; break;
7608 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_I; break;
7609 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_I; break;
7610 case T_MNEM_ror: inst.error = _("ror #imm not supported"); return;
7611 default: abort ();
7612 }
7613 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
7614 inst.instruction |= inst.operands[0].reg;
7615 inst.instruction |= inst.operands[1].reg << 3;
7616 }
7617 }
7618 }
7619
7620 static void
7621 do_t_simd (void)
7622 {
7623 inst.instruction |= inst.operands[0].reg << 8;
7624 inst.instruction |= inst.operands[1].reg << 16;
7625 inst.instruction |= inst.operands[2].reg;
7626 }
7627
7628 static void
7629 do_t_smc (void)
7630 {
7631 unsigned int value = inst.reloc.exp.X_add_number;
7632 constraint (inst.reloc.exp.X_op != O_constant,
7633 _("expression too complex"));
7634 inst.reloc.type = BFD_RELOC_UNUSED;
7635 inst.instruction |= (value & 0xf000) >> 12;
7636 inst.instruction |= (value & 0x0ff0);
7637 inst.instruction |= (value & 0x000f) << 16;
7638 }
7639
7640 static void
7641 do_t_ssat (void)
7642 {
7643 inst.instruction |= inst.operands[0].reg << 8;
7644 inst.instruction |= inst.operands[1].imm - 1;
7645 inst.instruction |= inst.operands[2].reg << 16;
7646
7647 if (inst.operands[3].present)
7648 {
7649 constraint (inst.reloc.exp.X_op != O_constant,
7650 _("expression too complex"));
7651
7652 if (inst.reloc.exp.X_add_number != 0)
7653 {
7654 if (inst.operands[3].shift_kind == SHIFT_ASR)
7655 inst.instruction |= 0x00200000; /* sh bit */
7656 inst.instruction |= (inst.reloc.exp.X_add_number & 0x1c) << 10;
7657 inst.instruction |= (inst.reloc.exp.X_add_number & 0x03) << 6;
7658 }
7659 inst.reloc.type = BFD_RELOC_UNUSED;
7660 }
7661 }
7662
7663 static void
7664 do_t_ssat16 (void)
7665 {
7666 inst.instruction |= inst.operands[0].reg << 8;
7667 inst.instruction |= inst.operands[1].imm - 1;
7668 inst.instruction |= inst.operands[2].reg << 16;
7669 }
7670
7671 static void
7672 do_t_strex (void)
7673 {
7674 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
7675 || inst.operands[2].postind || inst.operands[2].writeback
7676 || inst.operands[2].immisreg || inst.operands[2].shifted
7677 || inst.operands[2].negative,
7678 BAD_ADDR_MODE);
7679
7680 inst.instruction |= inst.operands[0].reg << 8;
7681 inst.instruction |= inst.operands[1].reg << 12;
7682 inst.instruction |= inst.operands[2].reg << 16;
7683 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8;
7684 }
7685
7686 static void
7687 do_t_strexd (void)
7688 {
7689 if (!inst.operands[2].present)
7690 inst.operands[2].reg = inst.operands[1].reg + 1;
7691
7692 constraint (inst.operands[0].reg == inst.operands[1].reg
7693 || inst.operands[0].reg == inst.operands[2].reg
7694 || inst.operands[0].reg == inst.operands[3].reg
7695 || inst.operands[1].reg == inst.operands[2].reg,
7696 BAD_OVERLAP);
7697
7698 inst.instruction |= inst.operands[0].reg;
7699 inst.instruction |= inst.operands[1].reg << 12;
7700 inst.instruction |= inst.operands[2].reg << 8;
7701 inst.instruction |= inst.operands[3].reg << 16;
7702 }
7703
7704 static void
7705 do_t_sxtah (void)
7706 {
7707 inst.instruction |= inst.operands[0].reg << 8;
7708 inst.instruction |= inst.operands[1].reg << 16;
7709 inst.instruction |= inst.operands[2].reg;
7710 inst.instruction |= inst.operands[3].imm << 4;
7711 }
7712
7713 static void
7714 do_t_sxth (void)
7715 {
7716 if (inst.instruction <= 0xffff && inst.size_req != 4
7717 && inst.operands[0].reg <= 7 && inst.operands[1].reg <= 7
7718 && (!inst.operands[2].present || inst.operands[2].imm == 0))
7719 {
7720 inst.instruction = THUMB_OP16 (inst.instruction);
7721 inst.instruction |= inst.operands[0].reg;
7722 inst.instruction |= inst.operands[1].reg << 3;
7723 }
7724 else if (unified_syntax)
7725 {
7726 if (inst.instruction <= 0xffff)
7727 inst.instruction = THUMB_OP32 (inst.instruction);
7728 inst.instruction |= inst.operands[0].reg << 8;
7729 inst.instruction |= inst.operands[1].reg;
7730 inst.instruction |= inst.operands[2].imm << 4;
7731 }
7732 else
7733 {
7734 constraint (inst.operands[2].present && inst.operands[2].imm != 0,
7735 _("Thumb encoding does not support rotation"));
7736 constraint (1, BAD_HIREG);
7737 }
7738 }
7739
7740 static void
7741 do_t_swi (void)
7742 {
7743 inst.reloc.type = BFD_RELOC_ARM_SWI;
7744 }
7745
7746 static void
7747 do_t_tb (void)
7748 {
7749 int half;
7750
7751 half = (inst.instruction & 0x10) != 0;
7752 constraint (inst.operands[0].imm == 15,
7753 _("PC is not a valid index register"));
7754 constraint (!half && inst.operands[0].shifted,
7755 _("instruction does not allow shifted index"));
7756 constraint (half && !inst.operands[0].shifted,
7757 _("instruction requires shifted index"));
7758 inst.instruction |= (inst.operands[0].reg << 16) | inst.operands[0].imm;
7759 }
7760
7761 static void
7762 do_t_usat (void)
7763 {
7764 inst.instruction |= inst.operands[0].reg << 8;
7765 inst.instruction |= inst.operands[1].imm;
7766 inst.instruction |= inst.operands[2].reg << 16;
7767
7768 if (inst.operands[3].present)
7769 {
7770 constraint (inst.reloc.exp.X_op != O_constant,
7771 _("expression too complex"));
7772 if (inst.reloc.exp.X_add_number != 0)
7773 {
7774 if (inst.operands[3].shift_kind == SHIFT_ASR)
7775 inst.instruction |= 0x00200000; /* sh bit */
7776
7777 inst.instruction |= (inst.reloc.exp.X_add_number & 0x1c) << 10;
7778 inst.instruction |= (inst.reloc.exp.X_add_number & 0x03) << 6;
7779 }
7780 inst.reloc.type = BFD_RELOC_UNUSED;
7781 }
7782 }
7783
7784 static void
7785 do_t_usat16 (void)
7786 {
7787 inst.instruction |= inst.operands[0].reg << 8;
7788 inst.instruction |= inst.operands[1].imm;
7789 inst.instruction |= inst.operands[2].reg << 16;
7790 }
7791 \f
7792 /* Overall per-instruction processing. */
7793
7794 /* We need to be able to fix up arbitrary expressions in some statements.
7795 This is so that we can handle symbols that are an arbitrary distance from
7796 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
7797 which returns part of an address in a form which will be valid for
7798 a data instruction. We do this by pushing the expression into a symbol
7799 in the expr_section, and creating a fix for that. */
7800
7801 static void
7802 fix_new_arm (fragS * frag,
7803 int where,
7804 short int size,
7805 expressionS * exp,
7806 int pc_rel,
7807 int reloc)
7808 {
7809 fixS * new_fix;
7810
7811 switch (exp->X_op)
7812 {
7813 case O_constant:
7814 case O_symbol:
7815 case O_add:
7816 case O_subtract:
7817 new_fix = fix_new_exp (frag, where, size, exp, pc_rel, reloc);
7818 break;
7819
7820 default:
7821 new_fix = fix_new (frag, where, size, make_expr_symbol (exp), 0,
7822 pc_rel, reloc);
7823 break;
7824 }
7825
7826 /* Mark whether the fix is to a THUMB instruction, or an ARM
7827 instruction. */
7828 new_fix->tc_fix_data = thumb_mode;
7829 }
7830
7831 /* Create a frg for an instruction requiring relaxation. */
7832 static void
7833 output_relax_insn (void)
7834 {
7835 char * to;
7836 symbolS *sym;
7837 int offset;
7838
7839 switch (inst.reloc.exp.X_op)
7840 {
7841 case O_symbol:
7842 sym = inst.reloc.exp.X_add_symbol;
7843 offset = inst.reloc.exp.X_add_number;
7844 break;
7845 case O_constant:
7846 sym = NULL;
7847 offset = inst.reloc.exp.X_add_number;
7848 break;
7849 default:
7850 sym = make_expr_symbol (&inst.reloc.exp);
7851 offset = 0;
7852 break;
7853 }
7854 to = frag_var (rs_machine_dependent, INSN_SIZE, THUMB_SIZE,
7855 inst.relax, sym, offset, NULL/*offset, opcode*/);
7856 md_number_to_chars (to, inst.instruction, THUMB_SIZE);
7857
7858 #ifdef OBJ_ELF
7859 dwarf2_emit_insn (INSN_SIZE);
7860 #endif
7861 }
7862
7863 /* Write a 32-bit thumb instruction to buf. */
7864 static void
7865 put_thumb32_insn (char * buf, unsigned long insn)
7866 {
7867 md_number_to_chars (buf, insn >> 16, THUMB_SIZE);
7868 md_number_to_chars (buf + THUMB_SIZE, insn, THUMB_SIZE);
7869 }
7870
7871 static void
7872 output_inst (const char * str)
7873 {
7874 char * to = NULL;
7875
7876 if (inst.error)
7877 {
7878 as_bad ("%s -- `%s'", inst.error, str);
7879 return;
7880 }
7881 if (inst.relax) {
7882 output_relax_insn();
7883 return;
7884 }
7885 if (inst.size == 0)
7886 return;
7887
7888 to = frag_more (inst.size);
7889
7890 if (thumb_mode && (inst.size > THUMB_SIZE))
7891 {
7892 assert (inst.size == (2 * THUMB_SIZE));
7893 put_thumb32_insn (to, inst.instruction);
7894 }
7895 else if (inst.size > INSN_SIZE)
7896 {
7897 assert (inst.size == (2 * INSN_SIZE));
7898 md_number_to_chars (to, inst.instruction, INSN_SIZE);
7899 md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE);
7900 }
7901 else
7902 md_number_to_chars (to, inst.instruction, inst.size);
7903
7904 if (inst.reloc.type != BFD_RELOC_UNUSED)
7905 fix_new_arm (frag_now, to - frag_now->fr_literal,
7906 inst.size, & inst.reloc.exp, inst.reloc.pc_rel,
7907 inst.reloc.type);
7908
7909 #ifdef OBJ_ELF
7910 dwarf2_emit_insn (inst.size);
7911 #endif
7912 }
7913
7914 /* Tag values used in struct asm_opcode's tag field. */
7915 enum opcode_tag
7916 {
7917 OT_unconditional, /* Instruction cannot be conditionalized.
7918 The ARM condition field is still 0xE. */
7919 OT_unconditionalF, /* Instruction cannot be conditionalized
7920 and carries 0xF in its ARM condition field. */
7921 OT_csuffix, /* Instruction takes a conditional suffix. */
7922 OT_cinfix3, /* Instruction takes a conditional infix,
7923 beginning at character index 3. (In
7924 unified mode, it becomes a suffix.) */
7925 OT_cinfix3_legacy, /* Legacy instruction takes a conditional infix at
7926 character index 3, even in unified mode. Used for
7927 legacy instructions where suffix and infix forms
7928 may be ambiguous. */
7929 OT_csuf_or_in3, /* Instruction takes either a conditional
7930 suffix or an infix at character index 3. */
7931 OT_odd_infix_unc, /* This is the unconditional variant of an
7932 instruction that takes a conditional infix
7933 at an unusual position. In unified mode,
7934 this variant will accept a suffix. */
7935 OT_odd_infix_0 /* Values greater than or equal to OT_odd_infix_0
7936 are the conditional variants of instructions that
7937 take conditional infixes in unusual positions.
7938 The infix appears at character index
7939 (tag - OT_odd_infix_0). These are not accepted
7940 in unified mode. */
7941 };
7942
7943 /* Subroutine of md_assemble, responsible for looking up the primary
7944 opcode from the mnemonic the user wrote. STR points to the
7945 beginning of the mnemonic.
7946
7947 This is not simply a hash table lookup, because of conditional
7948 variants. Most instructions have conditional variants, which are
7949 expressed with a _conditional affix_ to the mnemonic. If we were
7950 to encode each conditional variant as a literal string in the opcode
7951 table, it would have approximately 20,000 entries.
7952
7953 Most mnemonics take this affix as a suffix, and in unified syntax,
7954 'most' is upgraded to 'all'. However, in the divided syntax, some
7955 instructions take the affix as an infix, notably the s-variants of
7956 the arithmetic instructions. Of those instructions, all but six
7957 have the infix appear after the third character of the mnemonic.
7958
7959 Accordingly, the algorithm for looking up primary opcodes given
7960 an identifier is:
7961
7962 1. Look up the identifier in the opcode table.
7963 If we find a match, go to step U.
7964
7965 2. Look up the last two characters of the identifier in the
7966 conditions table. If we find a match, look up the first N-2
7967 characters of the identifier in the opcode table. If we
7968 find a match, go to step CE.
7969
7970 3. Look up the fourth and fifth characters of the identifier in
7971 the conditions table. If we find a match, extract those
7972 characters from the identifier, and look up the remaining
7973 characters in the opcode table. If we find a match, go
7974 to step CM.
7975
7976 4. Fail.
7977
7978 U. Examine the tag field of the opcode structure, in case this is
7979 one of the six instructions with its conditional infix in an
7980 unusual place. If it is, the tag tells us where to find the
7981 infix; look it up in the conditions table and set inst.cond
7982 accordingly. Otherwise, this is an unconditional instruction.
7983 Again set inst.cond accordingly. Return the opcode structure.
7984
7985 CE. Examine the tag field to make sure this is an instruction that
7986 should receive a conditional suffix. If it is not, fail.
7987 Otherwise, set inst.cond from the suffix we already looked up,
7988 and return the opcode structure.
7989
7990 CM. Examine the tag field to make sure this is an instruction that
7991 should receive a conditional infix after the third character.
7992 If it is not, fail. Otherwise, undo the edits to the current
7993 line of input and proceed as for case CE. */
7994
7995 static const struct asm_opcode *
7996 opcode_lookup (char **str)
7997 {
7998 char *end, *base;
7999 char *affix;
8000 const struct asm_opcode *opcode;
8001 const struct asm_cond *cond;
8002 char save[2];
8003
8004 /* Scan up to the end of the mnemonic, which must end in white space,
8005 '.' (in unified mode only), or end of string. */
8006 for (base = end = *str; *end != '\0'; end++)
8007 if (*end == ' ' || (unified_syntax && *end == '.'))
8008 break;
8009
8010 if (end == base)
8011 return 0;
8012
8013 /* Handle a possible width suffix. */
8014 if (end[0] == '.')
8015 {
8016 if (end[1] == 'w' && (end[2] == ' ' || end[2] == '\0'))
8017 inst.size_req = 4;
8018 else if (end[1] == 'n' && (end[2] == ' ' || end[2] == '\0'))
8019 inst.size_req = 2;
8020 else
8021 return 0;
8022
8023 *str = end + 2;
8024 }
8025 else
8026 *str = end;
8027
8028 /* Look for unaffixed or special-case affixed mnemonic. */
8029 opcode = hash_find_n (arm_ops_hsh, base, end - base);
8030 if (opcode)
8031 {
8032 /* step U */
8033 if (opcode->tag < OT_odd_infix_0)
8034 {
8035 inst.cond = COND_ALWAYS;
8036 return opcode;
8037 }
8038
8039 if (unified_syntax)
8040 as_warn (_("conditional infixes are deprecated in unified syntax"));
8041 affix = base + (opcode->tag - OT_odd_infix_0);
8042 cond = hash_find_n (arm_cond_hsh, affix, 2);
8043 assert (cond);
8044
8045 inst.cond = cond->value;
8046 return opcode;
8047 }
8048
8049 /* Cannot have a conditional suffix on a mnemonic of less than two
8050 characters. */
8051 if (end - base < 3)
8052 return 0;
8053
8054 /* Look for suffixed mnemonic. */
8055 affix = end - 2;
8056 cond = hash_find_n (arm_cond_hsh, affix, 2);
8057 opcode = hash_find_n (arm_ops_hsh, base, affix - base);
8058 if (opcode && cond)
8059 {
8060 /* step CE */
8061 switch (opcode->tag)
8062 {
8063 case OT_cinfix3_legacy:
8064 /* Ignore conditional suffixes matched on infix only mnemonics. */
8065 break;
8066
8067 case OT_cinfix3:
8068 case OT_odd_infix_unc:
8069 if (!unified_syntax)
8070 return 0;
8071 /* else fall through */
8072
8073 case OT_csuffix:
8074 case OT_csuf_or_in3:
8075 inst.cond = cond->value;
8076 return opcode;
8077
8078 case OT_unconditional:
8079 case OT_unconditionalF:
8080 /* delayed diagnostic */
8081 inst.error = BAD_COND;
8082 inst.cond = COND_ALWAYS;
8083 return opcode;
8084
8085 default:
8086 return 0;
8087 }
8088 }
8089
8090 /* Cannot have a usual-position infix on a mnemonic of less than
8091 six characters (five would be a suffix). */
8092 if (end - base < 6)
8093 return 0;
8094
8095 /* Look for infixed mnemonic in the usual position. */
8096 affix = base + 3;
8097 cond = hash_find_n (arm_cond_hsh, affix, 2);
8098 if (!cond)
8099 return 0;
8100
8101 memcpy (save, affix, 2);
8102 memmove (affix, affix + 2, (end - affix) - 2);
8103 opcode = hash_find_n (arm_ops_hsh, base, (end - base) - 2);
8104 memmove (affix + 2, affix, (end - affix) - 2);
8105 memcpy (affix, save, 2);
8106
8107 if (opcode && (opcode->tag == OT_cinfix3 || opcode->tag == OT_csuf_or_in3
8108 || opcode->tag == OT_cinfix3_legacy))
8109 {
8110 /* step CM */
8111 if (unified_syntax && opcode->tag == OT_cinfix3)
8112 as_warn (_("conditional infixes are deprecated in unified syntax"));
8113
8114 inst.cond = cond->value;
8115 return opcode;
8116 }
8117
8118 return 0;
8119 }
8120
8121 void
8122 md_assemble (char *str)
8123 {
8124 char *p = str;
8125 const struct asm_opcode * opcode;
8126
8127 /* Align the previous label if needed. */
8128 if (last_label_seen != NULL)
8129 {
8130 symbol_set_frag (last_label_seen, frag_now);
8131 S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ());
8132 S_SET_SEGMENT (last_label_seen, now_seg);
8133 }
8134
8135 memset (&inst, '\0', sizeof (inst));
8136 inst.reloc.type = BFD_RELOC_UNUSED;
8137
8138 opcode = opcode_lookup (&p);
8139 if (!opcode)
8140 {
8141 /* It wasn't an instruction, but it might be a register alias of
8142 the form alias .req reg. */
8143 if (!create_register_alias (str, p))
8144 as_bad (_("bad instruction `%s'"), str);
8145
8146 return;
8147 }
8148
8149 if (thumb_mode)
8150 {
8151 arm_feature_set variant;
8152
8153 variant = cpu_variant;
8154 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
8155 if (!ARM_CPU_HAS_FEATURE (variant, arm_arch_t2))
8156 ARM_CLEAR_FEATURE (variant, variant, fpu_any_hard);
8157 /* Check that this instruction is supported for this CPU. */
8158 if (thumb_mode == 1
8159 && !ARM_CPU_HAS_FEATURE (variant, *opcode->tvariant))
8160 {
8161 as_bad (_("selected processor does not support `%s'"), str);
8162 return;
8163 }
8164 if (inst.cond != COND_ALWAYS && !unified_syntax
8165 && opcode->tencode != do_t_branch)
8166 {
8167 as_bad (_("Thumb does not support conditional execution"));
8168 return;
8169 }
8170
8171 /* Check conditional suffixes. */
8172 if (current_it_mask)
8173 {
8174 int cond;
8175 cond = current_cc ^ ((current_it_mask >> 4) & 1) ^ 1;
8176 if (cond != inst.cond)
8177 {
8178 as_bad (_("incorrect condition in IT block"));
8179 return;
8180 }
8181 current_it_mask <<= 1;
8182 current_it_mask &= 0x1f;
8183 }
8184 else if (inst.cond != COND_ALWAYS && opcode->tencode != do_t_branch)
8185 {
8186 as_bad (_("thumb conditional instrunction not in IT block"));
8187 return;
8188 }
8189
8190 mapping_state (MAP_THUMB);
8191 inst.instruction = opcode->tvalue;
8192
8193 if (!parse_operands (p, opcode->operands))
8194 opcode->tencode ();
8195
8196 /* Clear current_it_mask at the end of an IT block. */
8197 if (current_it_mask == 0x10)
8198 current_it_mask = 0;
8199
8200 if (!(inst.error || inst.relax))
8201 {
8202 assert (inst.instruction < 0xe800 || inst.instruction > 0xffff);
8203 inst.size = (inst.instruction > 0xffff ? 4 : 2);
8204 if (inst.size_req && inst.size_req != inst.size)
8205 {
8206 as_bad (_("cannot honor width suffix -- `%s'"), str);
8207 return;
8208 }
8209 }
8210 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
8211 *opcode->tvariant);
8212 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
8213 set those bits when Thumb-2 32-bit instuctions are seen. ie.
8214 anything other than bl/blx.
8215 This is overly pessimistic for relaxable instructions. */
8216 if ((inst.size == 4 && (inst.instruction & 0xf800e800) != 0xf000e800)
8217 || inst.relax)
8218 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
8219 arm_ext_v6t2);
8220 }
8221 else
8222 {
8223 /* Check that this instruction is supported for this CPU. */
8224 if (!ARM_CPU_HAS_FEATURE (cpu_variant, *opcode->avariant))
8225 {
8226 as_bad (_("selected processor does not support `%s'"), str);
8227 return;
8228 }
8229 if (inst.size_req)
8230 {
8231 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str);
8232 return;
8233 }
8234
8235 mapping_state (MAP_ARM);
8236 inst.instruction = opcode->avalue;
8237 if (opcode->tag == OT_unconditionalF)
8238 inst.instruction |= 0xF << 28;
8239 else
8240 inst.instruction |= inst.cond << 28;
8241 inst.size = INSN_SIZE;
8242 if (!parse_operands (p, opcode->operands))
8243 opcode->aencode ();
8244 /* Arm mode bx is marked as both v4T and v5 because it's still required
8245 on a hypothetical non-thumb v5 core. */
8246 if (ARM_CPU_HAS_FEATURE (*opcode->avariant, arm_ext_v4t)
8247 || ARM_CPU_HAS_FEATURE (*opcode->avariant, arm_ext_v5))
8248 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, arm_ext_v4t);
8249 else
8250 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
8251 *opcode->avariant);
8252 }
8253 output_inst (str);
8254 }
8255
8256 /* Various frobbings of labels and their addresses. */
8257
8258 void
8259 arm_start_line_hook (void)
8260 {
8261 last_label_seen = NULL;
8262 }
8263
8264 void
8265 arm_frob_label (symbolS * sym)
8266 {
8267 last_label_seen = sym;
8268
8269 ARM_SET_THUMB (sym, thumb_mode);
8270
8271 #if defined OBJ_COFF || defined OBJ_ELF
8272 ARM_SET_INTERWORK (sym, support_interwork);
8273 #endif
8274
8275 /* Note - do not allow local symbols (.Lxxx) to be labeled
8276 as Thumb functions. This is because these labels, whilst
8277 they exist inside Thumb code, are not the entry points for
8278 possible ARM->Thumb calls. Also, these labels can be used
8279 as part of a computed goto or switch statement. eg gcc
8280 can generate code that looks like this:
8281
8282 ldr r2, [pc, .Laaa]
8283 lsl r3, r3, #2
8284 ldr r2, [r3, r2]
8285 mov pc, r2
8286
8287 .Lbbb: .word .Lxxx
8288 .Lccc: .word .Lyyy
8289 ..etc...
8290 .Laaa: .word Lbbb
8291
8292 The first instruction loads the address of the jump table.
8293 The second instruction converts a table index into a byte offset.
8294 The third instruction gets the jump address out of the table.
8295 The fourth instruction performs the jump.
8296
8297 If the address stored at .Laaa is that of a symbol which has the
8298 Thumb_Func bit set, then the linker will arrange for this address
8299 to have the bottom bit set, which in turn would mean that the
8300 address computation performed by the third instruction would end
8301 up with the bottom bit set. Since the ARM is capable of unaligned
8302 word loads, the instruction would then load the incorrect address
8303 out of the jump table, and chaos would ensue. */
8304 if (label_is_thumb_function_name
8305 && (S_GET_NAME (sym)[0] != '.' || S_GET_NAME (sym)[1] != 'L')
8306 && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
8307 {
8308 /* When the address of a Thumb function is taken the bottom
8309 bit of that address should be set. This will allow
8310 interworking between Arm and Thumb functions to work
8311 correctly. */
8312
8313 THUMB_SET_FUNC (sym, 1);
8314
8315 label_is_thumb_function_name = FALSE;
8316 }
8317
8318 #ifdef OBJ_ELF
8319 dwarf2_emit_label (sym);
8320 #endif
8321 }
8322
8323 int
8324 arm_data_in_code (void)
8325 {
8326 if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5))
8327 {
8328 *input_line_pointer = '/';
8329 input_line_pointer += 5;
8330 *input_line_pointer = 0;
8331 return 1;
8332 }
8333
8334 return 0;
8335 }
8336
8337 char *
8338 arm_canonicalize_symbol_name (char * name)
8339 {
8340 int len;
8341
8342 if (thumb_mode && (len = strlen (name)) > 5
8343 && streq (name + len - 5, "/data"))
8344 *(name + len - 5) = 0;
8345
8346 return name;
8347 }
8348 \f
8349 /* Table of all register names defined by default. The user can
8350 define additional names with .req. Note that all register names
8351 should appear in both upper and lowercase variants. Some registers
8352 also have mixed-case names. */
8353
8354 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE }
8355 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
8356 #define REGSET(p,t) \
8357 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
8358 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
8359 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
8360 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
8361
8362 static const struct reg_entry reg_names[] =
8363 {
8364 /* ARM integer registers. */
8365 REGSET(r, RN), REGSET(R, RN),
8366
8367 /* ATPCS synonyms. */
8368 REGDEF(a1,0,RN), REGDEF(a2,1,RN), REGDEF(a3, 2,RN), REGDEF(a4, 3,RN),
8369 REGDEF(v1,4,RN), REGDEF(v2,5,RN), REGDEF(v3, 6,RN), REGDEF(v4, 7,RN),
8370 REGDEF(v5,8,RN), REGDEF(v6,9,RN), REGDEF(v7,10,RN), REGDEF(v8,11,RN),
8371
8372 REGDEF(A1,0,RN), REGDEF(A2,1,RN), REGDEF(A3, 2,RN), REGDEF(A4, 3,RN),
8373 REGDEF(V1,4,RN), REGDEF(V2,5,RN), REGDEF(V3, 6,RN), REGDEF(V4, 7,RN),
8374 REGDEF(V5,8,RN), REGDEF(V6,9,RN), REGDEF(V7,10,RN), REGDEF(V8,11,RN),
8375
8376 /* Well-known aliases. */
8377 REGDEF(wr, 7,RN), REGDEF(sb, 9,RN), REGDEF(sl,10,RN), REGDEF(fp,11,RN),
8378 REGDEF(ip,12,RN), REGDEF(sp,13,RN), REGDEF(lr,14,RN), REGDEF(pc,15,RN),
8379
8380 REGDEF(WR, 7,RN), REGDEF(SB, 9,RN), REGDEF(SL,10,RN), REGDEF(FP,11,RN),
8381 REGDEF(IP,12,RN), REGDEF(SP,13,RN), REGDEF(LR,14,RN), REGDEF(PC,15,RN),
8382
8383 /* Coprocessor numbers. */
8384 REGSET(p, CP), REGSET(P, CP),
8385
8386 /* Coprocessor register numbers. The "cr" variants are for backward
8387 compatibility. */
8388 REGSET(c, CN), REGSET(C, CN),
8389 REGSET(cr, CN), REGSET(CR, CN),
8390
8391 /* FPA registers. */
8392 REGNUM(f,0,FN), REGNUM(f,1,FN), REGNUM(f,2,FN), REGNUM(f,3,FN),
8393 REGNUM(f,4,FN), REGNUM(f,5,FN), REGNUM(f,6,FN), REGNUM(f,7, FN),
8394
8395 REGNUM(F,0,FN), REGNUM(F,1,FN), REGNUM(F,2,FN), REGNUM(F,3,FN),
8396 REGNUM(F,4,FN), REGNUM(F,5,FN), REGNUM(F,6,FN), REGNUM(F,7, FN),
8397
8398 /* VFP SP registers. */
8399 REGSET(s,VFS),
8400 REGNUM(s,16,VFS), REGNUM(s,17,VFS), REGNUM(s,18,VFS), REGNUM(s,19,VFS),
8401 REGNUM(s,20,VFS), REGNUM(s,21,VFS), REGNUM(s,22,VFS), REGNUM(s,23,VFS),
8402 REGNUM(s,24,VFS), REGNUM(s,25,VFS), REGNUM(s,26,VFS), REGNUM(s,27,VFS),
8403 REGNUM(s,28,VFS), REGNUM(s,29,VFS), REGNUM(s,30,VFS), REGNUM(s,31,VFS),
8404
8405 REGSET(S,VFS),
8406 REGNUM(S,16,VFS), REGNUM(S,17,VFS), REGNUM(S,18,VFS), REGNUM(S,19,VFS),
8407 REGNUM(S,20,VFS), REGNUM(S,21,VFS), REGNUM(S,22,VFS), REGNUM(S,23,VFS),
8408 REGNUM(S,24,VFS), REGNUM(S,25,VFS), REGNUM(S,26,VFS), REGNUM(S,27,VFS),
8409 REGNUM(S,28,VFS), REGNUM(S,29,VFS), REGNUM(S,30,VFS), REGNUM(S,31,VFS),
8410
8411 /* VFP DP Registers. */
8412 REGSET(d,VFD), REGSET(D,VFS),
8413
8414 /* VFP control registers. */
8415 REGDEF(fpsid,0,VFC), REGDEF(fpscr,1,VFC), REGDEF(fpexc,8,VFC),
8416 REGDEF(FPSID,0,VFC), REGDEF(FPSCR,1,VFC), REGDEF(FPEXC,8,VFC),
8417
8418 /* Maverick DSP coprocessor registers. */
8419 REGSET(mvf,MVF), REGSET(mvd,MVD), REGSET(mvfx,MVFX), REGSET(mvdx,MVDX),
8420 REGSET(MVF,MVF), REGSET(MVD,MVD), REGSET(MVFX,MVFX), REGSET(MVDX,MVDX),
8421
8422 REGNUM(mvax,0,MVAX), REGNUM(mvax,1,MVAX),
8423 REGNUM(mvax,2,MVAX), REGNUM(mvax,3,MVAX),
8424 REGDEF(dspsc,0,DSPSC),
8425
8426 REGNUM(MVAX,0,MVAX), REGNUM(MVAX,1,MVAX),
8427 REGNUM(MVAX,2,MVAX), REGNUM(MVAX,3,MVAX),
8428 REGDEF(DSPSC,0,DSPSC),
8429
8430 /* iWMMXt data registers - p0, c0-15. */
8431 REGSET(wr,MMXWR), REGSET(wR,MMXWR), REGSET(WR, MMXWR),
8432
8433 /* iWMMXt control registers - p1, c0-3. */
8434 REGDEF(wcid, 0,MMXWC), REGDEF(wCID, 0,MMXWC), REGDEF(WCID, 0,MMXWC),
8435 REGDEF(wcon, 1,MMXWC), REGDEF(wCon, 1,MMXWC), REGDEF(WCON, 1,MMXWC),
8436 REGDEF(wcssf, 2,MMXWC), REGDEF(wCSSF, 2,MMXWC), REGDEF(WCSSF, 2,MMXWC),
8437 REGDEF(wcasf, 3,MMXWC), REGDEF(wCASF, 3,MMXWC), REGDEF(WCASF, 3,MMXWC),
8438
8439 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
8440 REGDEF(wcgr0, 8,MMXWCG), REGDEF(wCGR0, 8,MMXWCG), REGDEF(WCGR0, 8,MMXWCG),
8441 REGDEF(wcgr1, 9,MMXWCG), REGDEF(wCGR1, 9,MMXWCG), REGDEF(WCGR1, 9,MMXWCG),
8442 REGDEF(wcgr2,10,MMXWCG), REGDEF(wCGR2,10,MMXWCG), REGDEF(WCGR2,10,MMXWCG),
8443 REGDEF(wcgr3,11,MMXWCG), REGDEF(wCGR3,11,MMXWCG), REGDEF(WCGR3,11,MMXWCG),
8444
8445 /* XScale accumulator registers. */
8446 REGNUM(acc,0,XSCALE), REGNUM(ACC,0,XSCALE),
8447 };
8448 #undef REGDEF
8449 #undef REGNUM
8450 #undef REGSET
8451
8452 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
8453 within psr_required_here. */
8454 static const struct asm_psr psrs[] =
8455 {
8456 /* Backward compatibility notation. Note that "all" is no longer
8457 truly all possible PSR bits. */
8458 {"all", PSR_c | PSR_f},
8459 {"flg", PSR_f},
8460 {"ctl", PSR_c},
8461
8462 /* Individual flags. */
8463 {"f", PSR_f},
8464 {"c", PSR_c},
8465 {"x", PSR_x},
8466 {"s", PSR_s},
8467 /* Combinations of flags. */
8468 {"fs", PSR_f | PSR_s},
8469 {"fx", PSR_f | PSR_x},
8470 {"fc", PSR_f | PSR_c},
8471 {"sf", PSR_s | PSR_f},
8472 {"sx", PSR_s | PSR_x},
8473 {"sc", PSR_s | PSR_c},
8474 {"xf", PSR_x | PSR_f},
8475 {"xs", PSR_x | PSR_s},
8476 {"xc", PSR_x | PSR_c},
8477 {"cf", PSR_c | PSR_f},
8478 {"cs", PSR_c | PSR_s},
8479 {"cx", PSR_c | PSR_x},
8480 {"fsx", PSR_f | PSR_s | PSR_x},
8481 {"fsc", PSR_f | PSR_s | PSR_c},
8482 {"fxs", PSR_f | PSR_x | PSR_s},
8483 {"fxc", PSR_f | PSR_x | PSR_c},
8484 {"fcs", PSR_f | PSR_c | PSR_s},
8485 {"fcx", PSR_f | PSR_c | PSR_x},
8486 {"sfx", PSR_s | PSR_f | PSR_x},
8487 {"sfc", PSR_s | PSR_f | PSR_c},
8488 {"sxf", PSR_s | PSR_x | PSR_f},
8489 {"sxc", PSR_s | PSR_x | PSR_c},
8490 {"scf", PSR_s | PSR_c | PSR_f},
8491 {"scx", PSR_s | PSR_c | PSR_x},
8492 {"xfs", PSR_x | PSR_f | PSR_s},
8493 {"xfc", PSR_x | PSR_f | PSR_c},
8494 {"xsf", PSR_x | PSR_s | PSR_f},
8495 {"xsc", PSR_x | PSR_s | PSR_c},
8496 {"xcf", PSR_x | PSR_c | PSR_f},
8497 {"xcs", PSR_x | PSR_c | PSR_s},
8498 {"cfs", PSR_c | PSR_f | PSR_s},
8499 {"cfx", PSR_c | PSR_f | PSR_x},
8500 {"csf", PSR_c | PSR_s | PSR_f},
8501 {"csx", PSR_c | PSR_s | PSR_x},
8502 {"cxf", PSR_c | PSR_x | PSR_f},
8503 {"cxs", PSR_c | PSR_x | PSR_s},
8504 {"fsxc", PSR_f | PSR_s | PSR_x | PSR_c},
8505 {"fscx", PSR_f | PSR_s | PSR_c | PSR_x},
8506 {"fxsc", PSR_f | PSR_x | PSR_s | PSR_c},
8507 {"fxcs", PSR_f | PSR_x | PSR_c | PSR_s},
8508 {"fcsx", PSR_f | PSR_c | PSR_s | PSR_x},
8509 {"fcxs", PSR_f | PSR_c | PSR_x | PSR_s},
8510 {"sfxc", PSR_s | PSR_f | PSR_x | PSR_c},
8511 {"sfcx", PSR_s | PSR_f | PSR_c | PSR_x},
8512 {"sxfc", PSR_s | PSR_x | PSR_f | PSR_c},
8513 {"sxcf", PSR_s | PSR_x | PSR_c | PSR_f},
8514 {"scfx", PSR_s | PSR_c | PSR_f | PSR_x},
8515 {"scxf", PSR_s | PSR_c | PSR_x | PSR_f},
8516 {"xfsc", PSR_x | PSR_f | PSR_s | PSR_c},
8517 {"xfcs", PSR_x | PSR_f | PSR_c | PSR_s},
8518 {"xsfc", PSR_x | PSR_s | PSR_f | PSR_c},
8519 {"xscf", PSR_x | PSR_s | PSR_c | PSR_f},
8520 {"xcfs", PSR_x | PSR_c | PSR_f | PSR_s},
8521 {"xcsf", PSR_x | PSR_c | PSR_s | PSR_f},
8522 {"cfsx", PSR_c | PSR_f | PSR_s | PSR_x},
8523 {"cfxs", PSR_c | PSR_f | PSR_x | PSR_s},
8524 {"csfx", PSR_c | PSR_s | PSR_f | PSR_x},
8525 {"csxf", PSR_c | PSR_s | PSR_x | PSR_f},
8526 {"cxfs", PSR_c | PSR_x | PSR_f | PSR_s},
8527 {"cxsf", PSR_c | PSR_x | PSR_s | PSR_f},
8528 };
8529
8530 /* Table of all shift-in-operand names. */
8531 static const struct asm_shift_name shift_names [] =
8532 {
8533 { "asl", SHIFT_LSL }, { "ASL", SHIFT_LSL },
8534 { "lsl", SHIFT_LSL }, { "LSL", SHIFT_LSL },
8535 { "lsr", SHIFT_LSR }, { "LSR", SHIFT_LSR },
8536 { "asr", SHIFT_ASR }, { "ASR", SHIFT_ASR },
8537 { "ror", SHIFT_ROR }, { "ROR", SHIFT_ROR },
8538 { "rrx", SHIFT_RRX }, { "RRX", SHIFT_RRX }
8539 };
8540
8541 /* Table of all explicit relocation names. */
8542 #ifdef OBJ_ELF
8543 static struct reloc_entry reloc_names[] =
8544 {
8545 { "got", BFD_RELOC_ARM_GOT32 }, { "GOT", BFD_RELOC_ARM_GOT32 },
8546 { "gotoff", BFD_RELOC_ARM_GOTOFF }, { "GOTOFF", BFD_RELOC_ARM_GOTOFF },
8547 { "plt", BFD_RELOC_ARM_PLT32 }, { "PLT", BFD_RELOC_ARM_PLT32 },
8548 { "target1", BFD_RELOC_ARM_TARGET1 }, { "TARGET1", BFD_RELOC_ARM_TARGET1 },
8549 { "target2", BFD_RELOC_ARM_TARGET2 }, { "TARGET2", BFD_RELOC_ARM_TARGET2 },
8550 { "sbrel", BFD_RELOC_ARM_SBREL32 }, { "SBREL", BFD_RELOC_ARM_SBREL32 },
8551 { "tlsgd", BFD_RELOC_ARM_TLS_GD32}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32},
8552 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32},
8553 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32},
8554 { "gottpoff",BFD_RELOC_ARM_TLS_IE32}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32},
8555 { "tpoff", BFD_RELOC_ARM_TLS_LE32}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32}
8556 };
8557 #endif
8558
8559 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
8560 static const struct asm_cond conds[] =
8561 {
8562 {"eq", 0x0},
8563 {"ne", 0x1},
8564 {"cs", 0x2}, {"hs", 0x2},
8565 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
8566 {"mi", 0x4},
8567 {"pl", 0x5},
8568 {"vs", 0x6},
8569 {"vc", 0x7},
8570 {"hi", 0x8},
8571 {"ls", 0x9},
8572 {"ge", 0xa},
8573 {"lt", 0xb},
8574 {"gt", 0xc},
8575 {"le", 0xd},
8576 {"al", 0xe}
8577 };
8578
8579 /* Table of ARM-format instructions. */
8580
8581 /* Macros for gluing together operand strings. N.B. In all cases
8582 other than OPS0, the trailing OP_stop comes from default
8583 zero-initialization of the unspecified elements of the array. */
8584 #define OPS0() { OP_stop, }
8585 #define OPS1(a) { OP_##a, }
8586 #define OPS2(a,b) { OP_##a,OP_##b, }
8587 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
8588 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
8589 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
8590 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
8591
8592 /* These macros abstract out the exact format of the mnemonic table and
8593 save some repeated characters. */
8594
8595 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
8596 #define TxCE(mnem, op, top, nops, ops, ae, te) \
8597 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
8598 THUMB_VARIANT, do_##ae, do_##te }
8599
8600 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
8601 a T_MNEM_xyz enumerator. */
8602 #define TCE(mnem, aop, top, nops, ops, ae, te) \
8603 TxCE(mnem, aop, 0x##top, nops, ops, ae, te)
8604 #define tCE(mnem, aop, top, nops, ops, ae, te) \
8605 TxCE(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
8606
8607 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
8608 infix after the third character. */
8609 #define TxC3(mnem, op, top, nops, ops, ae, te) \
8610 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
8611 THUMB_VARIANT, do_##ae, do_##te }
8612 #define TC3(mnem, aop, top, nops, ops, ae, te) \
8613 TxC3(mnem, aop, 0x##top, nops, ops, ae, te)
8614 #define tC3(mnem, aop, top, nops, ops, ae, te) \
8615 TxC3(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
8616
8617 /* Mnemonic with a conditional infix in an unusual place. Each and every variant has to
8618 appear in the condition table. */
8619 #define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \
8620 { #m1 #m2 #m3, OPS##nops ops, sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \
8621 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te }
8622
8623 #define TxCM(m1, m2, op, top, nops, ops, ae, te) \
8624 TxCM_(m1, , m2, op, top, nops, ops, ae, te), \
8625 TxCM_(m1, eq, m2, op, top, nops, ops, ae, te), \
8626 TxCM_(m1, ne, m2, op, top, nops, ops, ae, te), \
8627 TxCM_(m1, cs, m2, op, top, nops, ops, ae, te), \
8628 TxCM_(m1, hs, m2, op, top, nops, ops, ae, te), \
8629 TxCM_(m1, cc, m2, op, top, nops, ops, ae, te), \
8630 TxCM_(m1, ul, m2, op, top, nops, ops, ae, te), \
8631 TxCM_(m1, lo, m2, op, top, nops, ops, ae, te), \
8632 TxCM_(m1, mi, m2, op, top, nops, ops, ae, te), \
8633 TxCM_(m1, pl, m2, op, top, nops, ops, ae, te), \
8634 TxCM_(m1, vs, m2, op, top, nops, ops, ae, te), \
8635 TxCM_(m1, vc, m2, op, top, nops, ops, ae, te), \
8636 TxCM_(m1, hi, m2, op, top, nops, ops, ae, te), \
8637 TxCM_(m1, ls, m2, op, top, nops, ops, ae, te), \
8638 TxCM_(m1, ge, m2, op, top, nops, ops, ae, te), \
8639 TxCM_(m1, lt, m2, op, top, nops, ops, ae, te), \
8640 TxCM_(m1, gt, m2, op, top, nops, ops, ae, te), \
8641 TxCM_(m1, le, m2, op, top, nops, ops, ae, te), \
8642 TxCM_(m1, al, m2, op, top, nops, ops, ae, te)
8643
8644 #define TCM(m1,m2, aop, top, nops, ops, ae, te) \
8645 TxCM(m1,m2, aop, 0x##top, nops, ops, ae, te)
8646 #define tCM(m1,m2, aop, top, nops, ops, ae, te) \
8647 TxCM(m1,m2, aop, T_MNEM_##top, nops, ops, ae, te)
8648
8649 /* Mnemonic that cannot be conditionalized. The ARM condition-code
8650 field is still 0xE. */
8651 #define TUE(mnem, op, top, nops, ops, ae, te) \
8652 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
8653 THUMB_VARIANT, do_##ae, do_##te }
8654
8655 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
8656 condition code field. */
8657 #define TUF(mnem, op, top, nops, ops, ae, te) \
8658 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
8659 THUMB_VARIANT, do_##ae, do_##te }
8660
8661 /* ARM-only variants of all the above. */
8662 #define CE(mnem, op, nops, ops, ae) \
8663 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
8664
8665 #define C3(mnem, op, nops, ops, ae) \
8666 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
8667
8668 /* Legacy mnemonics that always have conditional infix after the third
8669 character. */
8670 #define CL(mnem, op, nops, ops, ae) \
8671 { #mnem, OPS##nops ops, OT_cinfix3_legacy, \
8672 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
8673
8674 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
8675 #define cCE(mnem, op, nops, ops, ae) \
8676 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
8677
8678 /* Legacy coprocessor instructions where conditional infix and conditional
8679 suffix are ambiguous. For consistency this includes all FPA instructions,
8680 not just the potentially ambiguous ones. */
8681 #define cCL(mnem, op, nops, ops, ae) \
8682 { #mnem, OPS##nops ops, OT_cinfix3_legacy, \
8683 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
8684
8685 /* Coprocessor, takes either a suffix or a position-3 infix
8686 (for an FPA corner case). */
8687 #define C3E(mnem, op, nops, ops, ae) \
8688 { #mnem, OPS##nops ops, OT_csuf_or_in3, \
8689 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
8690
8691 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
8692 { #m1 #m2 #m3, OPS##nops ops, \
8693 sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \
8694 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
8695
8696 #define CM(m1, m2, op, nops, ops, ae) \
8697 xCM_(m1, , m2, op, nops, ops, ae), \
8698 xCM_(m1, eq, m2, op, nops, ops, ae), \
8699 xCM_(m1, ne, m2, op, nops, ops, ae), \
8700 xCM_(m1, cs, m2, op, nops, ops, ae), \
8701 xCM_(m1, hs, m2, op, nops, ops, ae), \
8702 xCM_(m1, cc, m2, op, nops, ops, ae), \
8703 xCM_(m1, ul, m2, op, nops, ops, ae), \
8704 xCM_(m1, lo, m2, op, nops, ops, ae), \
8705 xCM_(m1, mi, m2, op, nops, ops, ae), \
8706 xCM_(m1, pl, m2, op, nops, ops, ae), \
8707 xCM_(m1, vs, m2, op, nops, ops, ae), \
8708 xCM_(m1, vc, m2, op, nops, ops, ae), \
8709 xCM_(m1, hi, m2, op, nops, ops, ae), \
8710 xCM_(m1, ls, m2, op, nops, ops, ae), \
8711 xCM_(m1, ge, m2, op, nops, ops, ae), \
8712 xCM_(m1, lt, m2, op, nops, ops, ae), \
8713 xCM_(m1, gt, m2, op, nops, ops, ae), \
8714 xCM_(m1, le, m2, op, nops, ops, ae), \
8715 xCM_(m1, al, m2, op, nops, ops, ae)
8716
8717 #define UE(mnem, op, nops, ops, ae) \
8718 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
8719
8720 #define UF(mnem, op, nops, ops, ae) \
8721 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
8722
8723 #define do_0 0
8724
8725 /* Thumb-only, unconditional. */
8726 #define UT(mnem, op, nops, ops, te) TUE(mnem, 0, op, nops, ops, 0, te)
8727
8728 static const struct asm_opcode insns[] =
8729 {
8730 #define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */
8731 #define THUMB_VARIANT &arm_ext_v4t
8732 tCE(and, 0000000, and, 3, (RR, oRR, SH), arit, t_arit3c),
8733 tC3(ands, 0100000, ands, 3, (RR, oRR, SH), arit, t_arit3c),
8734 tCE(eor, 0200000, eor, 3, (RR, oRR, SH), arit, t_arit3c),
8735 tC3(eors, 0300000, eors, 3, (RR, oRR, SH), arit, t_arit3c),
8736 tCE(sub, 0400000, sub, 3, (RR, oRR, SH), arit, t_add_sub),
8737 tC3(subs, 0500000, subs, 3, (RR, oRR, SH), arit, t_add_sub),
8738 tCE(add, 0800000, add, 3, (RR, oRR, SH), arit, t_add_sub),
8739 tC3(adds, 0900000, adds, 3, (RR, oRR, SH), arit, t_add_sub),
8740 tCE(adc, 0a00000, adc, 3, (RR, oRR, SH), arit, t_arit3c),
8741 tC3(adcs, 0b00000, adcs, 3, (RR, oRR, SH), arit, t_arit3c),
8742 tCE(sbc, 0c00000, sbc, 3, (RR, oRR, SH), arit, t_arit3),
8743 tC3(sbcs, 0d00000, sbcs, 3, (RR, oRR, SH), arit, t_arit3),
8744 tCE(orr, 1800000, orr, 3, (RR, oRR, SH), arit, t_arit3c),
8745 tC3(orrs, 1900000, orrs, 3, (RR, oRR, SH), arit, t_arit3c),
8746 tCE(bic, 1c00000, bic, 3, (RR, oRR, SH), arit, t_arit3),
8747 tC3(bics, 1d00000, bics, 3, (RR, oRR, SH), arit, t_arit3),
8748
8749 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
8750 for setting PSR flag bits. They are obsolete in V6 and do not
8751 have Thumb equivalents. */
8752 tCE(tst, 1100000, tst, 2, (RR, SH), cmp, t_mvn_tst),
8753 tC3(tsts, 1100000, tst, 2, (RR, SH), cmp, t_mvn_tst),
8754 CL(tstp, 110f000, 2, (RR, SH), cmp),
8755 tCE(cmp, 1500000, cmp, 2, (RR, SH), cmp, t_mov_cmp),
8756 tC3(cmps, 1500000, cmp, 2, (RR, SH), cmp, t_mov_cmp),
8757 CL(cmpp, 150f000, 2, (RR, SH), cmp),
8758 tCE(cmn, 1700000, cmn, 2, (RR, SH), cmp, t_mvn_tst),
8759 tC3(cmns, 1700000, cmn, 2, (RR, SH), cmp, t_mvn_tst),
8760 CL(cmnp, 170f000, 2, (RR, SH), cmp),
8761
8762 tCE(mov, 1a00000, mov, 2, (RR, SH), mov, t_mov_cmp),
8763 tC3(movs, 1b00000, movs, 2, (RR, SH), mov, t_mov_cmp),
8764 tCE(mvn, 1e00000, mvn, 2, (RR, SH), mov, t_mvn_tst),
8765 tC3(mvns, 1f00000, mvns, 2, (RR, SH), mov, t_mvn_tst),
8766
8767 tCE(ldr, 4100000, ldr, 2, (RR, ADDR), ldst, t_ldst),
8768 tC3(ldrb, 4500000, ldrb, 2, (RR, ADDR), ldst, t_ldst),
8769 tCE(str, 4000000, str, 2, (RR, ADDR), ldst, t_ldst),
8770 tC3(strb, 4400000, strb, 2, (RR, ADDR), ldst, t_ldst),
8771
8772 tC3(stmia, 8800000, stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
8773 tC3(stmea, 8800000, stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
8774 tC3(ldmia, 8900000, ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
8775 tC3(ldmfd, 8900000, ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
8776
8777 TCE(swi, f000000, df00, 1, (EXPi), swi, t_swi),
8778 tCE(b, a000000, b, 1, (EXPr), branch, t_branch),
8779 TCE(bl, b000000, f000f800, 1, (EXPr), bl, t_branch23),
8780
8781 /* Pseudo ops. */
8782 tCE(adr, 28f0000, adr, 2, (RR, EXP), adr, t_adr),
8783 C3(adrl, 28f0000, 2, (RR, EXP), adrl),
8784 tCE(nop, 1a00000, nop, 1, (oI255c), nop, t_nop),
8785
8786 /* Thumb-compatibility pseudo ops. */
8787 tCE(lsl, 1a00000, lsl, 3, (RR, oRR, SH), shift, t_shift),
8788 tC3(lsls, 1b00000, lsls, 3, (RR, oRR, SH), shift, t_shift),
8789 tCE(lsr, 1a00020, lsr, 3, (RR, oRR, SH), shift, t_shift),
8790 tC3(lsrs, 1b00020, lsrs, 3, (RR, oRR, SH), shift, t_shift),
8791 tCE(asr, 1a00040, asr, 3, (RR, oRR, SH), shift, t_shift),
8792 tC3(asrs, 1b00040, asrs, 3, (RR, oRR, SH), shift, t_shift),
8793 tCE(ror, 1a00060, ror, 3, (RR, oRR, SH), shift, t_shift),
8794 tC3(rors, 1b00060, rors, 3, (RR, oRR, SH), shift, t_shift),
8795 tCE(neg, 2600000, neg, 2, (RR, RR), rd_rn, t_neg),
8796 tC3(negs, 2700000, negs, 2, (RR, RR), rd_rn, t_neg),
8797 tCE(push, 92d0000, push, 1, (REGLST), push_pop, t_push_pop),
8798 tCE(pop, 8bd0000, pop, 1, (REGLST), push_pop, t_push_pop),
8799
8800 #undef THUMB_VARIANT
8801 #define THUMB_VARIANT &arm_ext_v6
8802 TCE(cpy, 1a00000, 4600, 2, (RR, RR), rd_rm, t_cpy),
8803
8804 /* V1 instructions with no Thumb analogue prior to V6T2. */
8805 #undef THUMB_VARIANT
8806 #define THUMB_VARIANT &arm_ext_v6t2
8807 TCE(rsb, 0600000, ebc00000, 3, (RR, oRR, SH), arit, t_rsb),
8808 TC3(rsbs, 0700000, ebd00000, 3, (RR, oRR, SH), arit, t_rsb),
8809 TCE(teq, 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
8810 TC3(teqs, 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
8811 CL(teqp, 130f000, 2, (RR, SH), cmp),
8812
8813 TC3(ldrt, 4300000, f8500e00, 2, (RR, ADDR), ldstt, t_ldstt),
8814 TC3(ldrbt, 4700000, f8300e00, 2, (RR, ADDR), ldstt, t_ldstt),
8815 TC3(strt, 4200000, f8400e00, 2, (RR, ADDR), ldstt, t_ldstt),
8816 TC3(strbt, 4600000, f8200e00, 2, (RR, ADDR), ldstt, t_ldstt),
8817
8818 TC3(stmdb, 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
8819 TC3(stmfd, 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
8820
8821 TC3(ldmdb, 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
8822 TC3(ldmea, 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
8823
8824 /* V1 instructions with no Thumb analogue at all. */
8825 CE(rsc, 0e00000, 3, (RR, oRR, SH), arit),
8826 C3(rscs, 0f00000, 3, (RR, oRR, SH), arit),
8827
8828 C3(stmib, 9800000, 2, (RRw, REGLST), ldmstm),
8829 C3(stmfa, 9800000, 2, (RRw, REGLST), ldmstm),
8830 C3(stmda, 8000000, 2, (RRw, REGLST), ldmstm),
8831 C3(stmed, 8000000, 2, (RRw, REGLST), ldmstm),
8832 C3(ldmib, 9900000, 2, (RRw, REGLST), ldmstm),
8833 C3(ldmed, 9900000, 2, (RRw, REGLST), ldmstm),
8834 C3(ldmda, 8100000, 2, (RRw, REGLST), ldmstm),
8835 C3(ldmfa, 8100000, 2, (RRw, REGLST), ldmstm),
8836
8837 #undef ARM_VARIANT
8838 #define ARM_VARIANT &arm_ext_v2 /* ARM 2 - multiplies. */
8839 #undef THUMB_VARIANT
8840 #define THUMB_VARIANT &arm_ext_v4t
8841 tCE(mul, 0000090, mul, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
8842 tC3(muls, 0100090, muls, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
8843
8844 #undef THUMB_VARIANT
8845 #define THUMB_VARIANT &arm_ext_v6t2
8846 TCE(mla, 0200090, fb000000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
8847 C3(mlas, 0300090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas),
8848
8849 /* Generic coprocessor instructions. */
8850 TCE(cdp, e000000, ee000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
8851 TCE(ldc, c100000, ec100000, 3, (RCP, RCN, ADDR), lstc, lstc),
8852 TC3(ldcl, c500000, ec500000, 3, (RCP, RCN, ADDR), lstc, lstc),
8853 TCE(stc, c000000, ec000000, 3, (RCP, RCN, ADDR), lstc, lstc),
8854 TC3(stcl, c400000, ec400000, 3, (RCP, RCN, ADDR), lstc, lstc),
8855 TCE(mcr, e000010, ee000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
8856 TCE(mrc, e100010, ee100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
8857
8858 #undef ARM_VARIANT
8859 #define ARM_VARIANT &arm_ext_v2s /* ARM 3 - swp instructions. */
8860 CE(swp, 1000090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
8861 C3(swpb, 1400090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
8862
8863 #undef ARM_VARIANT
8864 #define ARM_VARIANT &arm_ext_v3 /* ARM 6 Status register instructions. */
8865 TCE(mrs, 10f0000, f3ef8000, 2, (RR, PSR), mrs, t_mrs),
8866 TCE(msr, 120f000, f3808000, 2, (PSR, RR_EXi), msr, t_msr),
8867
8868 #undef ARM_VARIANT
8869 #define ARM_VARIANT &arm_ext_v3m /* ARM 7M long multiplies. */
8870 TCE(smull, 0c00090, fb800000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
8871 CM(smull,s, 0d00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
8872 TCE(umull, 0800090, fba00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
8873 CM(umull,s, 0900090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
8874 TCE(smlal, 0e00090, fbc00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
8875 CM(smlal,s, 0f00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
8876 TCE(umlal, 0a00090, fbe00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
8877 CM(umlal,s, 0b00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
8878
8879 #undef ARM_VARIANT
8880 #define ARM_VARIANT &arm_ext_v4 /* ARM Architecture 4. */
8881 #undef THUMB_VARIANT
8882 #define THUMB_VARIANT &arm_ext_v4t
8883 tC3(ldrh, 01000b0, ldrh, 2, (RR, ADDR), ldstv4, t_ldst),
8884 tC3(strh, 00000b0, strh, 2, (RR, ADDR), ldstv4, t_ldst),
8885 tC3(ldrsh, 01000f0, ldrsh, 2, (RR, ADDR), ldstv4, t_ldst),
8886 tC3(ldrsb, 01000d0, ldrsb, 2, (RR, ADDR), ldstv4, t_ldst),
8887 tCM(ld,sh, 01000f0, ldrsh, 2, (RR, ADDR), ldstv4, t_ldst),
8888 tCM(ld,sb, 01000d0, ldrsb, 2, (RR, ADDR), ldstv4, t_ldst),
8889
8890 #undef ARM_VARIANT
8891 #define ARM_VARIANT &arm_ext_v4t_5
8892 /* ARM Architecture 4T. */
8893 /* Note: bx (and blx) are required on V5, even if the processor does
8894 not support Thumb. */
8895 TCE(bx, 12fff10, 4700, 1, (RR), bx, t_bx),
8896
8897 #undef ARM_VARIANT
8898 #define ARM_VARIANT &arm_ext_v5 /* ARM Architecture 5T. */
8899 #undef THUMB_VARIANT
8900 #define THUMB_VARIANT &arm_ext_v5t
8901 /* Note: blx has 2 variants; the .value coded here is for
8902 BLX(2). Only this variant has conditional execution. */
8903 TCE(blx, 12fff30, 4780, 1, (RR_EXr), blx, t_blx),
8904 TUE(bkpt, 1200070, be00, 1, (oIffffb), bkpt, t_bkpt),
8905
8906 #undef THUMB_VARIANT
8907 #define THUMB_VARIANT &arm_ext_v6t2
8908 TCE(clz, 16f0f10, fab0f080, 2, (RRnpc, RRnpc), rd_rm, t_clz),
8909 TUF(ldc2, c100000, fc100000, 3, (RCP, RCN, ADDR), lstc, lstc),
8910 TUF(ldc2l, c500000, fc500000, 3, (RCP, RCN, ADDR), lstc, lstc),
8911 TUF(stc2, c000000, fc000000, 3, (RCP, RCN, ADDR), lstc, lstc),
8912 TUF(stc2l, c400000, fc400000, 3, (RCP, RCN, ADDR), lstc, lstc),
8913 TUF(cdp2, e000000, fe000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
8914 TUF(mcr2, e000010, fe000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
8915 TUF(mrc2, e100010, fe100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
8916
8917 #undef ARM_VARIANT
8918 #define ARM_VARIANT &arm_ext_v5exp /* ARM Architecture 5TExP. */
8919 TCE(smlabb, 1000080, fb100000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
8920 TCE(smlatb, 10000a0, fb100020, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
8921 TCE(smlabt, 10000c0, fb100010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
8922 TCE(smlatt, 10000e0, fb100030, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
8923
8924 TCE(smlawb, 1200080, fb300000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
8925 TCE(smlawt, 12000c0, fb300010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
8926
8927 TCE(smlalbb, 1400080, fbc00080, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
8928 TCE(smlaltb, 14000a0, fbc000a0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
8929 TCE(smlalbt, 14000c0, fbc00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
8930 TCE(smlaltt, 14000e0, fbc000b0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
8931
8932 TCE(smulbb, 1600080, fb10f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
8933 TCE(smultb, 16000a0, fb10f020, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
8934 TCE(smulbt, 16000c0, fb10f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
8935 TCE(smultt, 16000e0, fb10f030, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
8936
8937 TCE(smulwb, 12000a0, fb30f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
8938 TCE(smulwt, 12000e0, fb30f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
8939
8940 TCE(qadd, 1000050, fa80f080, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn),
8941 TCE(qdadd, 1400050, fa80f090, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn),
8942 TCE(qsub, 1200050, fa80f0a0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn),
8943 TCE(qdsub, 1600050, fa80f0b0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn),
8944
8945 #undef ARM_VARIANT
8946 #define ARM_VARIANT &arm_ext_v5e /* ARM Architecture 5TE. */
8947 TUF(pld, 450f000, f810f000, 1, (ADDR), pld, t_pld),
8948 TC3(ldrd, 00000d0, e9500000, 3, (RRnpc, oRRnpc, ADDR), ldrd, t_ldstd),
8949 TC3(strd, 00000f0, e9400000, 3, (RRnpc, oRRnpc, ADDR), ldrd, t_ldstd),
8950
8951 TCE(mcrr, c400000, ec400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
8952 TCE(mrrc, c500000, ec500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
8953
8954 #undef ARM_VARIANT
8955 #define ARM_VARIANT &arm_ext_v5j /* ARM Architecture 5TEJ. */
8956 TCE(bxj, 12fff20, f3c08f00, 1, (RR), bxj, t_bxj),
8957
8958 #undef ARM_VARIANT
8959 #define ARM_VARIANT &arm_ext_v6 /* ARM V6. */
8960 #undef THUMB_VARIANT
8961 #define THUMB_VARIANT &arm_ext_v6
8962 TUF(cpsie, 1080000, b660, 2, (CPSF, oI31b), cpsi, t_cpsi),
8963 TUF(cpsid, 10c0000, b670, 2, (CPSF, oI31b), cpsi, t_cpsi),
8964 tCE(rev, 6bf0f30, rev, 2, (RRnpc, RRnpc), rd_rm, t_rev),
8965 tCE(rev16, 6bf0fb0, rev16, 2, (RRnpc, RRnpc), rd_rm, t_rev),
8966 tCE(revsh, 6ff0fb0, revsh, 2, (RRnpc, RRnpc), rd_rm, t_rev),
8967 tCE(sxth, 6bf0070, sxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
8968 tCE(uxth, 6ff0070, uxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
8969 tCE(sxtb, 6af0070, sxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
8970 tCE(uxtb, 6ef0070, uxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
8971 TUF(setend, 1010000, b650, 1, (ENDI), setend, t_setend),
8972
8973 #undef THUMB_VARIANT
8974 #define THUMB_VARIANT &arm_ext_v6t2
8975 TUF(cps, 1020000, f3af8100, 1, (I31b), imm0, imm0),
8976 TCE(ldrex, 1900f9f, e8500f00, 2, (RRnpc, ADDR), ldrex, t_ldrex),
8977 TUF(mcrr2, c400000, fc400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
8978 TUF(mrrc2, c500000, fc500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
8979 TCE(pkhbt, 6800010, eac00000, 4, (RRnpc, RRnpc, RRnpc, oSHll), pkhbt, t_pkhbt),
8980 TCE(pkhtb, 6800050, eac00020, 4, (RRnpc, RRnpc, RRnpc, oSHar), pkhtb, t_pkhtb),
8981 TCE(qadd16, 6200f10, fa90f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8982 TCE(qadd8, 6200f90, fa80f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8983 TCE(qaddsubx, 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8984 TCE(qsub16, 6200f70, fad0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8985 TCE(qsub8, 6200ff0, fac0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8986 TCE(qsubaddx, 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8987 TCE(sadd16, 6100f10, fa90f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8988 TCE(sadd8, 6100f90, fa80f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8989 TCE(saddsubx, 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8990 TCE(shadd16, 6300f10, fa90f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8991 TCE(shadd8, 6300f90, fa80f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8992 TCE(shaddsubx, 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8993 TCE(shsub16, 6300f70, fad0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8994 TCE(shsub8, 6300ff0, fac0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8995 TCE(shsubaddx, 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8996 TCE(ssub16, 6100f70, fad0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8997 TCE(ssub8, 6100ff0, fac0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8998 TCE(ssubaddx, 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8999 TCE(uadd16, 6500f10, fa90f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9000 TCE(uadd8, 6500f90, fa80f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9001 TCE(uaddsubx, 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9002 TCE(uhadd16, 6700f10, fa90f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9003 TCE(uhadd8, 6700f90, fa80f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9004 TCE(uhaddsubx, 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9005 TCE(uhsub16, 6700f70, fad0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9006 TCE(uhsub8, 6700ff0, fac0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9007 TCE(uhsubaddx, 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9008 TCE(uqadd16, 6600f10, fa90f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9009 TCE(uqadd8, 6600f90, fa80f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9010 TCE(uqaddsubx, 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9011 TCE(uqsub16, 6600f70, fad0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9012 TCE(uqsub8, 6600ff0, fac0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9013 TCE(uqsubaddx, 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9014 TCE(usub16, 6500f70, fad0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9015 TCE(usub8, 6500ff0, fac0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9016 TCE(usubaddx, 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9017 TUF(rfeia, 8900a00, e990c000, 1, (RRw), rfe, rfe),
9018 UF(rfeib, 9900a00, 1, (RRw), rfe),
9019 UF(rfeda, 8100a00, 1, (RRw), rfe),
9020 TUF(rfedb, 9100a00, e810c000, 1, (RRw), rfe, rfe),
9021 TUF(rfefd, 8900a00, e990c000, 1, (RRw), rfe, rfe),
9022 UF(rfefa, 9900a00, 1, (RRw), rfe),
9023 UF(rfeea, 8100a00, 1, (RRw), rfe),
9024 TUF(rfeed, 9100a00, e810c000, 1, (RRw), rfe, rfe),
9025 TCE(sxtah, 6b00070, fa00f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
9026 TCE(sxtab16, 6800070, fa20f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
9027 TCE(sxtab, 6a00070, fa40f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
9028 TCE(sxtb16, 68f0070, fa2ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
9029 TCE(uxtah, 6f00070, fa10f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
9030 TCE(uxtab16, 6c00070, fa30f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
9031 TCE(uxtab, 6e00070, fa50f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
9032 TCE(uxtb16, 6cf0070, fa3ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
9033 TCE(sel, 6800fb0, faa0f080, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9034 TCE(smlad, 7000010, fb200000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
9035 TCE(smladx, 7000030, fb200010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
9036 TCE(smlald, 7400010, fbc000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
9037 TCE(smlaldx, 7400030, fbc000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
9038 TCE(smlsd, 7000050, fb400000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
9039 TCE(smlsdx, 7000070, fb400010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
9040 TCE(smlsld, 7400050, fbd000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
9041 TCE(smlsldx, 7400070, fbd000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
9042 TCE(smmla, 7500010, fb500000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
9043 TCE(smmlar, 7500030, fb500010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
9044 TCE(smmls, 75000d0, fb600000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
9045 TCE(smmlsr, 75000f0, fb600010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
9046 TCE(smmul, 750f010, fb50f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
9047 TCE(smmulr, 750f030, fb50f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
9048 TCE(smuad, 700f010, fb20f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
9049 TCE(smuadx, 700f030, fb20f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
9050 TCE(smusd, 700f050, fb40f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
9051 TCE(smusdx, 700f070, fb40f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
9052 TUF(srsia, 8cd0500, e980c000, 1, (I31w), srs, srs),
9053 UF(srsib, 9cd0500, 1, (I31w), srs),
9054 UF(srsda, 84d0500, 1, (I31w), srs),
9055 TUF(srsdb, 94d0500, e800c000, 1, (I31w), srs, srs),
9056 TCE(ssat, 6a00010, f3000000, 4, (RRnpc, I32, RRnpc, oSHllar),ssat, t_ssat),
9057 TCE(ssat16, 6a00f30, f3200000, 3, (RRnpc, I16, RRnpc), ssat16, t_ssat16),
9058 TCE(strex, 1800f90, e8400000, 3, (RRnpc, RRnpc, ADDR), strex, t_strex),
9059 TCE(umaal, 0400090, fbe00060, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal, t_mlal),
9060 TCE(usad8, 780f010, fb70f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
9061 TCE(usada8, 7800010, fb700000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
9062 TCE(usat, 6e00010, f3800000, 4, (RRnpc, I31, RRnpc, oSHllar),usat, t_usat),
9063 TCE(usat16, 6e00f30, f3a00000, 3, (RRnpc, I15, RRnpc), usat16, t_usat16),
9064
9065 #undef ARM_VARIANT
9066 #define ARM_VARIANT &arm_ext_v6k
9067 #undef THUMB_VARIANT
9068 #define THUMB_VARIANT &arm_ext_v6k
9069 tCE(yield, 320f001, yield, 0, (), noargs, t_hint),
9070 tCE(wfe, 320f002, wfe, 0, (), noargs, t_hint),
9071 tCE(wfi, 320f003, wfi, 0, (), noargs, t_hint),
9072 tCE(sev, 320f004, sev, 0, (), noargs, t_hint),
9073
9074 #undef THUMB_VARIANT
9075 #define THUMB_VARIANT &arm_ext_v6t2
9076 TCE(ldrexb, 1d00f9f, e8d00f4f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
9077 TCE(ldrexh, 1f00f9f, e8d00f5f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
9078 TCE(ldrexd, 1b00f9f, e8d0007f, 3, (RRnpc, oRRnpc, RRnpcb), ldrexd, t_ldrexd),
9079 TCE(strexb, 1c00f90, e8c00f40, 3, (RRnpc, RRnpc, ADDR), strex, rm_rd_rn),
9080 TCE(strexh, 1e00f90, e8c00f50, 3, (RRnpc, RRnpc, ADDR), strex, rm_rd_rn),
9081 TCE(strexd, 1a00f90, e8c00070, 4, (RRnpc, RRnpc, oRRnpc, RRnpcb), strexd, t_strexd),
9082 TUF(clrex, 57ff01f, f3bf8f2f, 0, (), noargs, noargs),
9083
9084 #undef ARM_VARIANT
9085 #define ARM_VARIANT &arm_ext_v6z
9086 TCE(smc, 1600070, f7f08000, 1, (EXPi), smc, t_smc),
9087
9088 #undef ARM_VARIANT
9089 #define ARM_VARIANT &arm_ext_v6t2
9090 TCE(bfc, 7c0001f, f36f0000, 3, (RRnpc, I31, I32), bfc, t_bfc),
9091 TCE(bfi, 7c00010, f3600000, 4, (RRnpc, RRnpc_I0, I31, I32), bfi, t_bfi),
9092 TCE(sbfx, 7a00050, f3400000, 4, (RR, RR, I31, I32), bfx, t_bfx),
9093 TCE(ubfx, 7e00050, f3c00000, 4, (RR, RR, I31, I32), bfx, t_bfx),
9094
9095 TCE(mls, 0600090, fb000010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
9096 TCE(movw, 3000000, f2400000, 2, (RRnpc, Iffff), mov16, t_mov16),
9097 TCE(movt, 3400000, f2c00000, 2, (RRnpc, Iffff), mov16, t_mov16),
9098 TCE(rbit, 3ff0f30, fa90f0a0, 2, (RR, RR), rd_rm, t_rbit),
9099
9100 TC3(ldrht, 03000b0, f8300e00, 2, (RR, ADDR), ldsttv4, t_ldstt),
9101 TC3(ldrsht, 03000f0, f9300e00, 2, (RR, ADDR), ldsttv4, t_ldstt),
9102 TC3(ldrsbt, 03000d0, f9100e00, 2, (RR, ADDR), ldsttv4, t_ldstt),
9103 TC3(strht, 02000b0, f8200e00, 2, (RR, ADDR), ldsttv4, t_ldstt),
9104
9105 UT(cbnz, b900, 2, (RR, EXP), t_czb),
9106 UT(cbz, b100, 2, (RR, EXP), t_czb),
9107 /* ARM does not really have an IT instruction. */
9108 TUE(it, 0, bf08, 1, (COND), it, t_it),
9109 TUE(itt, 0, bf0c, 1, (COND), it, t_it),
9110 TUE(ite, 0, bf04, 1, (COND), it, t_it),
9111 TUE(ittt, 0, bf0e, 1, (COND), it, t_it),
9112 TUE(itet, 0, bf06, 1, (COND), it, t_it),
9113 TUE(itte, 0, bf0a, 1, (COND), it, t_it),
9114 TUE(itee, 0, bf02, 1, (COND), it, t_it),
9115 TUE(itttt, 0, bf0f, 1, (COND), it, t_it),
9116 TUE(itett, 0, bf07, 1, (COND), it, t_it),
9117 TUE(ittet, 0, bf0b, 1, (COND), it, t_it),
9118 TUE(iteet, 0, bf03, 1, (COND), it, t_it),
9119 TUE(ittte, 0, bf0d, 1, (COND), it, t_it),
9120 TUE(itete, 0, bf05, 1, (COND), it, t_it),
9121 TUE(ittee, 0, bf09, 1, (COND), it, t_it),
9122 TUE(iteee, 0, bf01, 1, (COND), it, t_it),
9123
9124 /* Thumb2 only instructions. */
9125 #undef ARM_VARIANT
9126 #define ARM_VARIANT NULL
9127
9128 TCE(addw, 0, f2000000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
9129 TCE(subw, 0, f2a00000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
9130 TCE(tbb, 0, e8d0f000, 1, (TB), 0, t_tb),
9131 TCE(tbh, 0, e8d0f010, 1, (TB), 0, t_tb),
9132
9133 #undef ARM_VARIANT
9134 #define ARM_VARIANT &fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
9135 cCE(wfs, e200110, 1, (RR), rd),
9136 cCE(rfs, e300110, 1, (RR), rd),
9137 cCE(wfc, e400110, 1, (RR), rd),
9138 cCE(rfc, e500110, 1, (RR), rd),
9139
9140 cCL(ldfs, c100100, 2, (RF, ADDR), rd_cpaddr),
9141 cCL(ldfd, c108100, 2, (RF, ADDR), rd_cpaddr),
9142 cCL(ldfe, c500100, 2, (RF, ADDR), rd_cpaddr),
9143 cCL(ldfp, c508100, 2, (RF, ADDR), rd_cpaddr),
9144
9145 cCL(stfs, c000100, 2, (RF, ADDR), rd_cpaddr),
9146 cCL(stfd, c008100, 2, (RF, ADDR), rd_cpaddr),
9147 cCL(stfe, c400100, 2, (RF, ADDR), rd_cpaddr),
9148 cCL(stfp, c408100, 2, (RF, ADDR), rd_cpaddr),
9149
9150 cCL(mvfs, e008100, 2, (RF, RF_IF), rd_rm),
9151 cCL(mvfsp, e008120, 2, (RF, RF_IF), rd_rm),
9152 cCL(mvfsm, e008140, 2, (RF, RF_IF), rd_rm),
9153 cCL(mvfsz, e008160, 2, (RF, RF_IF), rd_rm),
9154 cCL(mvfd, e008180, 2, (RF, RF_IF), rd_rm),
9155 cCL(mvfdp, e0081a0, 2, (RF, RF_IF), rd_rm),
9156 cCL(mvfdm, e0081c0, 2, (RF, RF_IF), rd_rm),
9157 cCL(mvfdz, e0081e0, 2, (RF, RF_IF), rd_rm),
9158 cCL(mvfe, e088100, 2, (RF, RF_IF), rd_rm),
9159 cCL(mvfep, e088120, 2, (RF, RF_IF), rd_rm),
9160 cCL(mvfem, e088140, 2, (RF, RF_IF), rd_rm),
9161 cCL(mvfez, e088160, 2, (RF, RF_IF), rd_rm),
9162
9163 cCL(mnfs, e108100, 2, (RF, RF_IF), rd_rm),
9164 cCL(mnfsp, e108120, 2, (RF, RF_IF), rd_rm),
9165 cCL(mnfsm, e108140, 2, (RF, RF_IF), rd_rm),
9166 cCL(mnfsz, e108160, 2, (RF, RF_IF), rd_rm),
9167 cCL(mnfd, e108180, 2, (RF, RF_IF), rd_rm),
9168 cCL(mnfdp, e1081a0, 2, (RF, RF_IF), rd_rm),
9169 cCL(mnfdm, e1081c0, 2, (RF, RF_IF), rd_rm),
9170 cCL(mnfdz, e1081e0, 2, (RF, RF_IF), rd_rm),
9171 cCL(mnfe, e188100, 2, (RF, RF_IF), rd_rm),
9172 cCL(mnfep, e188120, 2, (RF, RF_IF), rd_rm),
9173 cCL(mnfem, e188140, 2, (RF, RF_IF), rd_rm),
9174 cCL(mnfez, e188160, 2, (RF, RF_IF), rd_rm),
9175
9176 cCL(abss, e208100, 2, (RF, RF_IF), rd_rm),
9177 cCL(abssp, e208120, 2, (RF, RF_IF), rd_rm),
9178 cCL(abssm, e208140, 2, (RF, RF_IF), rd_rm),
9179 cCL(abssz, e208160, 2, (RF, RF_IF), rd_rm),
9180 cCL(absd, e208180, 2, (RF, RF_IF), rd_rm),
9181 cCL(absdp, e2081a0, 2, (RF, RF_IF), rd_rm),
9182 cCL(absdm, e2081c0, 2, (RF, RF_IF), rd_rm),
9183 cCL(absdz, e2081e0, 2, (RF, RF_IF), rd_rm),
9184 cCL(abse, e288100, 2, (RF, RF_IF), rd_rm),
9185 cCL(absep, e288120, 2, (RF, RF_IF), rd_rm),
9186 cCL(absem, e288140, 2, (RF, RF_IF), rd_rm),
9187 cCL(absez, e288160, 2, (RF, RF_IF), rd_rm),
9188
9189 cCL(rnds, e308100, 2, (RF, RF_IF), rd_rm),
9190 cCL(rndsp, e308120, 2, (RF, RF_IF), rd_rm),
9191 cCL(rndsm, e308140, 2, (RF, RF_IF), rd_rm),
9192 cCL(rndsz, e308160, 2, (RF, RF_IF), rd_rm),
9193 cCL(rndd, e308180, 2, (RF, RF_IF), rd_rm),
9194 cCL(rnddp, e3081a0, 2, (RF, RF_IF), rd_rm),
9195 cCL(rnddm, e3081c0, 2, (RF, RF_IF), rd_rm),
9196 cCL(rnddz, e3081e0, 2, (RF, RF_IF), rd_rm),
9197 cCL(rnde, e388100, 2, (RF, RF_IF), rd_rm),
9198 cCL(rndep, e388120, 2, (RF, RF_IF), rd_rm),
9199 cCL(rndem, e388140, 2, (RF, RF_IF), rd_rm),
9200 cCL(rndez, e388160, 2, (RF, RF_IF), rd_rm),
9201
9202 cCL(sqts, e408100, 2, (RF, RF_IF), rd_rm),
9203 cCL(sqtsp, e408120, 2, (RF, RF_IF), rd_rm),
9204 cCL(sqtsm, e408140, 2, (RF, RF_IF), rd_rm),
9205 cCL(sqtsz, e408160, 2, (RF, RF_IF), rd_rm),
9206 cCL(sqtd, e408180, 2, (RF, RF_IF), rd_rm),
9207 cCL(sqtdp, e4081a0, 2, (RF, RF_IF), rd_rm),
9208 cCL(sqtdm, e4081c0, 2, (RF, RF_IF), rd_rm),
9209 cCL(sqtdz, e4081e0, 2, (RF, RF_IF), rd_rm),
9210 cCL(sqte, e488100, 2, (RF, RF_IF), rd_rm),
9211 cCL(sqtep, e488120, 2, (RF, RF_IF), rd_rm),
9212 cCL(sqtem, e488140, 2, (RF, RF_IF), rd_rm),
9213 cCL(sqtez, e488160, 2, (RF, RF_IF), rd_rm),
9214
9215 cCL(logs, e508100, 2, (RF, RF_IF), rd_rm),
9216 cCL(logsp, e508120, 2, (RF, RF_IF), rd_rm),
9217 cCL(logsm, e508140, 2, (RF, RF_IF), rd_rm),
9218 cCL(logsz, e508160, 2, (RF, RF_IF), rd_rm),
9219 cCL(logd, e508180, 2, (RF, RF_IF), rd_rm),
9220 cCL(logdp, e5081a0, 2, (RF, RF_IF), rd_rm),
9221 cCL(logdm, e5081c0, 2, (RF, RF_IF), rd_rm),
9222 cCL(logdz, e5081e0, 2, (RF, RF_IF), rd_rm),
9223 cCL(loge, e588100, 2, (RF, RF_IF), rd_rm),
9224 cCL(logep, e588120, 2, (RF, RF_IF), rd_rm),
9225 cCL(logem, e588140, 2, (RF, RF_IF), rd_rm),
9226 cCL(logez, e588160, 2, (RF, RF_IF), rd_rm),
9227
9228 cCL(lgns, e608100, 2, (RF, RF_IF), rd_rm),
9229 cCL(lgnsp, e608120, 2, (RF, RF_IF), rd_rm),
9230 cCL(lgnsm, e608140, 2, (RF, RF_IF), rd_rm),
9231 cCL(lgnsz, e608160, 2, (RF, RF_IF), rd_rm),
9232 cCL(lgnd, e608180, 2, (RF, RF_IF), rd_rm),
9233 cCL(lgndp, e6081a0, 2, (RF, RF_IF), rd_rm),
9234 cCL(lgndm, e6081c0, 2, (RF, RF_IF), rd_rm),
9235 cCL(lgndz, e6081e0, 2, (RF, RF_IF), rd_rm),
9236 cCL(lgne, e688100, 2, (RF, RF_IF), rd_rm),
9237 cCL(lgnep, e688120, 2, (RF, RF_IF), rd_rm),
9238 cCL(lgnem, e688140, 2, (RF, RF_IF), rd_rm),
9239 cCL(lgnez, e688160, 2, (RF, RF_IF), rd_rm),
9240
9241 cCL(exps, e708100, 2, (RF, RF_IF), rd_rm),
9242 cCL(expsp, e708120, 2, (RF, RF_IF), rd_rm),
9243 cCL(expsm, e708140, 2, (RF, RF_IF), rd_rm),
9244 cCL(expsz, e708160, 2, (RF, RF_IF), rd_rm),
9245 cCL(expd, e708180, 2, (RF, RF_IF), rd_rm),
9246 cCL(expdp, e7081a0, 2, (RF, RF_IF), rd_rm),
9247 cCL(expdm, e7081c0, 2, (RF, RF_IF), rd_rm),
9248 cCL(expdz, e7081e0, 2, (RF, RF_IF), rd_rm),
9249 cCL(expe, e788100, 2, (RF, RF_IF), rd_rm),
9250 cCL(expep, e788120, 2, (RF, RF_IF), rd_rm),
9251 cCL(expem, e788140, 2, (RF, RF_IF), rd_rm),
9252 cCL(expdz, e788160, 2, (RF, RF_IF), rd_rm),
9253
9254 cCL(sins, e808100, 2, (RF, RF_IF), rd_rm),
9255 cCL(sinsp, e808120, 2, (RF, RF_IF), rd_rm),
9256 cCL(sinsm, e808140, 2, (RF, RF_IF), rd_rm),
9257 cCL(sinsz, e808160, 2, (RF, RF_IF), rd_rm),
9258 cCL(sind, e808180, 2, (RF, RF_IF), rd_rm),
9259 cCL(sindp, e8081a0, 2, (RF, RF_IF), rd_rm),
9260 cCL(sindm, e8081c0, 2, (RF, RF_IF), rd_rm),
9261 cCL(sindz, e8081e0, 2, (RF, RF_IF), rd_rm),
9262 cCL(sine, e888100, 2, (RF, RF_IF), rd_rm),
9263 cCL(sinep, e888120, 2, (RF, RF_IF), rd_rm),
9264 cCL(sinem, e888140, 2, (RF, RF_IF), rd_rm),
9265 cCL(sinez, e888160, 2, (RF, RF_IF), rd_rm),
9266
9267 cCL(coss, e908100, 2, (RF, RF_IF), rd_rm),
9268 cCL(cossp, e908120, 2, (RF, RF_IF), rd_rm),
9269 cCL(cossm, e908140, 2, (RF, RF_IF), rd_rm),
9270 cCL(cossz, e908160, 2, (RF, RF_IF), rd_rm),
9271 cCL(cosd, e908180, 2, (RF, RF_IF), rd_rm),
9272 cCL(cosdp, e9081a0, 2, (RF, RF_IF), rd_rm),
9273 cCL(cosdm, e9081c0, 2, (RF, RF_IF), rd_rm),
9274 cCL(cosdz, e9081e0, 2, (RF, RF_IF), rd_rm),
9275 cCL(cose, e988100, 2, (RF, RF_IF), rd_rm),
9276 cCL(cosep, e988120, 2, (RF, RF_IF), rd_rm),
9277 cCL(cosem, e988140, 2, (RF, RF_IF), rd_rm),
9278 cCL(cosez, e988160, 2, (RF, RF_IF), rd_rm),
9279
9280 cCL(tans, ea08100, 2, (RF, RF_IF), rd_rm),
9281 cCL(tansp, ea08120, 2, (RF, RF_IF), rd_rm),
9282 cCL(tansm, ea08140, 2, (RF, RF_IF), rd_rm),
9283 cCL(tansz, ea08160, 2, (RF, RF_IF), rd_rm),
9284 cCL(tand, ea08180, 2, (RF, RF_IF), rd_rm),
9285 cCL(tandp, ea081a0, 2, (RF, RF_IF), rd_rm),
9286 cCL(tandm, ea081c0, 2, (RF, RF_IF), rd_rm),
9287 cCL(tandz, ea081e0, 2, (RF, RF_IF), rd_rm),
9288 cCL(tane, ea88100, 2, (RF, RF_IF), rd_rm),
9289 cCL(tanep, ea88120, 2, (RF, RF_IF), rd_rm),
9290 cCL(tanem, ea88140, 2, (RF, RF_IF), rd_rm),
9291 cCL(tanez, ea88160, 2, (RF, RF_IF), rd_rm),
9292
9293 cCL(asns, eb08100, 2, (RF, RF_IF), rd_rm),
9294 cCL(asnsp, eb08120, 2, (RF, RF_IF), rd_rm),
9295 cCL(asnsm, eb08140, 2, (RF, RF_IF), rd_rm),
9296 cCL(asnsz, eb08160, 2, (RF, RF_IF), rd_rm),
9297 cCL(asnd, eb08180, 2, (RF, RF_IF), rd_rm),
9298 cCL(asndp, eb081a0, 2, (RF, RF_IF), rd_rm),
9299 cCL(asndm, eb081c0, 2, (RF, RF_IF), rd_rm),
9300 cCL(asndz, eb081e0, 2, (RF, RF_IF), rd_rm),
9301 cCL(asne, eb88100, 2, (RF, RF_IF), rd_rm),
9302 cCL(asnep, eb88120, 2, (RF, RF_IF), rd_rm),
9303 cCL(asnem, eb88140, 2, (RF, RF_IF), rd_rm),
9304 cCL(asnez, eb88160, 2, (RF, RF_IF), rd_rm),
9305
9306 cCL(acss, ec08100, 2, (RF, RF_IF), rd_rm),
9307 cCL(acssp, ec08120, 2, (RF, RF_IF), rd_rm),
9308 cCL(acssm, ec08140, 2, (RF, RF_IF), rd_rm),
9309 cCL(acssz, ec08160, 2, (RF, RF_IF), rd_rm),
9310 cCL(acsd, ec08180, 2, (RF, RF_IF), rd_rm),
9311 cCL(acsdp, ec081a0, 2, (RF, RF_IF), rd_rm),
9312 cCL(acsdm, ec081c0, 2, (RF, RF_IF), rd_rm),
9313 cCL(acsdz, ec081e0, 2, (RF, RF_IF), rd_rm),
9314 cCL(acse, ec88100, 2, (RF, RF_IF), rd_rm),
9315 cCL(acsep, ec88120, 2, (RF, RF_IF), rd_rm),
9316 cCL(acsem, ec88140, 2, (RF, RF_IF), rd_rm),
9317 cCL(acsez, ec88160, 2, (RF, RF_IF), rd_rm),
9318
9319 cCL(atns, ed08100, 2, (RF, RF_IF), rd_rm),
9320 cCL(atnsp, ed08120, 2, (RF, RF_IF), rd_rm),
9321 cCL(atnsm, ed08140, 2, (RF, RF_IF), rd_rm),
9322 cCL(atnsz, ed08160, 2, (RF, RF_IF), rd_rm),
9323 cCL(atnd, ed08180, 2, (RF, RF_IF), rd_rm),
9324 cCL(atndp, ed081a0, 2, (RF, RF_IF), rd_rm),
9325 cCL(atndm, ed081c0, 2, (RF, RF_IF), rd_rm),
9326 cCL(atndz, ed081e0, 2, (RF, RF_IF), rd_rm),
9327 cCL(atne, ed88100, 2, (RF, RF_IF), rd_rm),
9328 cCL(atnep, ed88120, 2, (RF, RF_IF), rd_rm),
9329 cCL(atnem, ed88140, 2, (RF, RF_IF), rd_rm),
9330 cCL(atnez, ed88160, 2, (RF, RF_IF), rd_rm),
9331
9332 cCL(urds, ee08100, 2, (RF, RF_IF), rd_rm),
9333 cCL(urdsp, ee08120, 2, (RF, RF_IF), rd_rm),
9334 cCL(urdsm, ee08140, 2, (RF, RF_IF), rd_rm),
9335 cCL(urdsz, ee08160, 2, (RF, RF_IF), rd_rm),
9336 cCL(urdd, ee08180, 2, (RF, RF_IF), rd_rm),
9337 cCL(urddp, ee081a0, 2, (RF, RF_IF), rd_rm),
9338 cCL(urddm, ee081c0, 2, (RF, RF_IF), rd_rm),
9339 cCL(urddz, ee081e0, 2, (RF, RF_IF), rd_rm),
9340 cCL(urde, ee88100, 2, (RF, RF_IF), rd_rm),
9341 cCL(urdep, ee88120, 2, (RF, RF_IF), rd_rm),
9342 cCL(urdem, ee88140, 2, (RF, RF_IF), rd_rm),
9343 cCL(urdez, ee88160, 2, (RF, RF_IF), rd_rm),
9344
9345 cCL(nrms, ef08100, 2, (RF, RF_IF), rd_rm),
9346 cCL(nrmsp, ef08120, 2, (RF, RF_IF), rd_rm),
9347 cCL(nrmsm, ef08140, 2, (RF, RF_IF), rd_rm),
9348 cCL(nrmsz, ef08160, 2, (RF, RF_IF), rd_rm),
9349 cCL(nrmd, ef08180, 2, (RF, RF_IF), rd_rm),
9350 cCL(nrmdp, ef081a0, 2, (RF, RF_IF), rd_rm),
9351 cCL(nrmdm, ef081c0, 2, (RF, RF_IF), rd_rm),
9352 cCL(nrmdz, ef081e0, 2, (RF, RF_IF), rd_rm),
9353 cCL(nrme, ef88100, 2, (RF, RF_IF), rd_rm),
9354 cCL(nrmep, ef88120, 2, (RF, RF_IF), rd_rm),
9355 cCL(nrmem, ef88140, 2, (RF, RF_IF), rd_rm),
9356 cCL(nrmez, ef88160, 2, (RF, RF_IF), rd_rm),
9357
9358 cCL(adfs, e000100, 3, (RF, RF, RF_IF), rd_rn_rm),
9359 cCL(adfsp, e000120, 3, (RF, RF, RF_IF), rd_rn_rm),
9360 cCL(adfsm, e000140, 3, (RF, RF, RF_IF), rd_rn_rm),
9361 cCL(adfsz, e000160, 3, (RF, RF, RF_IF), rd_rn_rm),
9362 cCL(adfd, e000180, 3, (RF, RF, RF_IF), rd_rn_rm),
9363 cCL(adfdp, e0001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
9364 cCL(adfdm, e0001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
9365 cCL(adfdz, e0001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
9366 cCL(adfe, e080100, 3, (RF, RF, RF_IF), rd_rn_rm),
9367 cCL(adfep, e080120, 3, (RF, RF, RF_IF), rd_rn_rm),
9368 cCL(adfem, e080140, 3, (RF, RF, RF_IF), rd_rn_rm),
9369 cCL(adfez, e080160, 3, (RF, RF, RF_IF), rd_rn_rm),
9370
9371 cCL(sufs, e200100, 3, (RF, RF, RF_IF), rd_rn_rm),
9372 cCL(sufsp, e200120, 3, (RF, RF, RF_IF), rd_rn_rm),
9373 cCL(sufsm, e200140, 3, (RF, RF, RF_IF), rd_rn_rm),
9374 cCL(sufsz, e200160, 3, (RF, RF, RF_IF), rd_rn_rm),
9375 cCL(sufd, e200180, 3, (RF, RF, RF_IF), rd_rn_rm),
9376 cCL(sufdp, e2001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
9377 cCL(sufdm, e2001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
9378 cCL(sufdz, e2001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
9379 cCL(sufe, e280100, 3, (RF, RF, RF_IF), rd_rn_rm),
9380 cCL(sufep, e280120, 3, (RF, RF, RF_IF), rd_rn_rm),
9381 cCL(sufem, e280140, 3, (RF, RF, RF_IF), rd_rn_rm),
9382 cCL(sufez, e280160, 3, (RF, RF, RF_IF), rd_rn_rm),
9383
9384 cCL(rsfs, e300100, 3, (RF, RF, RF_IF), rd_rn_rm),
9385 cCL(rsfsp, e300120, 3, (RF, RF, RF_IF), rd_rn_rm),
9386 cCL(rsfsm, e300140, 3, (RF, RF, RF_IF), rd_rn_rm),
9387 cCL(rsfsz, e300160, 3, (RF, RF, RF_IF), rd_rn_rm),
9388 cCL(rsfd, e300180, 3, (RF, RF, RF_IF), rd_rn_rm),
9389 cCL(rsfdp, e3001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
9390 cCL(rsfdm, e3001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
9391 cCL(rsfdz, e3001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
9392 cCL(rsfe, e380100, 3, (RF, RF, RF_IF), rd_rn_rm),
9393 cCL(rsfep, e380120, 3, (RF, RF, RF_IF), rd_rn_rm),
9394 cCL(rsfem, e380140, 3, (RF, RF, RF_IF), rd_rn_rm),
9395 cCL(rsfez, e380160, 3, (RF, RF, RF_IF), rd_rn_rm),
9396
9397 cCL(mufs, e100100, 3, (RF, RF, RF_IF), rd_rn_rm),
9398 cCL(mufsp, e100120, 3, (RF, RF, RF_IF), rd_rn_rm),
9399 cCL(mufsm, e100140, 3, (RF, RF, RF_IF), rd_rn_rm),
9400 cCL(mufsz, e100160, 3, (RF, RF, RF_IF), rd_rn_rm),
9401 cCL(mufd, e100180, 3, (RF, RF, RF_IF), rd_rn_rm),
9402 cCL(mufdp, e1001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
9403 cCL(mufdm, e1001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
9404 cCL(mufdz, e1001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
9405 cCL(mufe, e180100, 3, (RF, RF, RF_IF), rd_rn_rm),
9406 cCL(mufep, e180120, 3, (RF, RF, RF_IF), rd_rn_rm),
9407 cCL(mufem, e180140, 3, (RF, RF, RF_IF), rd_rn_rm),
9408 cCL(mufez, e180160, 3, (RF, RF, RF_IF), rd_rn_rm),
9409
9410 cCL(dvfs, e400100, 3, (RF, RF, RF_IF), rd_rn_rm),
9411 cCL(dvfsp, e400120, 3, (RF, RF, RF_IF), rd_rn_rm),
9412 cCL(dvfsm, e400140, 3, (RF, RF, RF_IF), rd_rn_rm),
9413 cCL(dvfsz, e400160, 3, (RF, RF, RF_IF), rd_rn_rm),
9414 cCL(dvfd, e400180, 3, (RF, RF, RF_IF), rd_rn_rm),
9415 cCL(dvfdp, e4001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
9416 cCL(dvfdm, e4001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
9417 cCL(dvfdz, e4001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
9418 cCL(dvfe, e480100, 3, (RF, RF, RF_IF), rd_rn_rm),
9419 cCL(dvfep, e480120, 3, (RF, RF, RF_IF), rd_rn_rm),
9420 cCL(dvfem, e480140, 3, (RF, RF, RF_IF), rd_rn_rm),
9421 cCL(dvfez, e480160, 3, (RF, RF, RF_IF), rd_rn_rm),
9422
9423 cCL(rdfs, e500100, 3, (RF, RF, RF_IF), rd_rn_rm),
9424 cCL(rdfsp, e500120, 3, (RF, RF, RF_IF), rd_rn_rm),
9425 cCL(rdfsm, e500140, 3, (RF, RF, RF_IF), rd_rn_rm),
9426 cCL(rdfsz, e500160, 3, (RF, RF, RF_IF), rd_rn_rm),
9427 cCL(rdfd, e500180, 3, (RF, RF, RF_IF), rd_rn_rm),
9428 cCL(rdfdp, e5001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
9429 cCL(rdfdm, e5001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
9430 cCL(rdfdz, e5001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
9431 cCL(rdfe, e580100, 3, (RF, RF, RF_IF), rd_rn_rm),
9432 cCL(rdfep, e580120, 3, (RF, RF, RF_IF), rd_rn_rm),
9433 cCL(rdfem, e580140, 3, (RF, RF, RF_IF), rd_rn_rm),
9434 cCL(rdfez, e580160, 3, (RF, RF, RF_IF), rd_rn_rm),
9435
9436 cCL(pows, e600100, 3, (RF, RF, RF_IF), rd_rn_rm),
9437 cCL(powsp, e600120, 3, (RF, RF, RF_IF), rd_rn_rm),
9438 cCL(powsm, e600140, 3, (RF, RF, RF_IF), rd_rn_rm),
9439 cCL(powsz, e600160, 3, (RF, RF, RF_IF), rd_rn_rm),
9440 cCL(powd, e600180, 3, (RF, RF, RF_IF), rd_rn_rm),
9441 cCL(powdp, e6001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
9442 cCL(powdm, e6001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
9443 cCL(powdz, e6001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
9444 cCL(powe, e680100, 3, (RF, RF, RF_IF), rd_rn_rm),
9445 cCL(powep, e680120, 3, (RF, RF, RF_IF), rd_rn_rm),
9446 cCL(powem, e680140, 3, (RF, RF, RF_IF), rd_rn_rm),
9447 cCL(powez, e680160, 3, (RF, RF, RF_IF), rd_rn_rm),
9448
9449 cCL(rpws, e700100, 3, (RF, RF, RF_IF), rd_rn_rm),
9450 cCL(rpwsp, e700120, 3, (RF, RF, RF_IF), rd_rn_rm),
9451 cCL(rpwsm, e700140, 3, (RF, RF, RF_IF), rd_rn_rm),
9452 cCL(rpwsz, e700160, 3, (RF, RF, RF_IF), rd_rn_rm),
9453 cCL(rpwd, e700180, 3, (RF, RF, RF_IF), rd_rn_rm),
9454 cCL(rpwdp, e7001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
9455 cCL(rpwdm, e7001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
9456 cCL(rpwdz, e7001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
9457 cCL(rpwe, e780100, 3, (RF, RF, RF_IF), rd_rn_rm),
9458 cCL(rpwep, e780120, 3, (RF, RF, RF_IF), rd_rn_rm),
9459 cCL(rpwem, e780140, 3, (RF, RF, RF_IF), rd_rn_rm),
9460 cCL(rpwez, e780160, 3, (RF, RF, RF_IF), rd_rn_rm),
9461
9462 cCL(rmfs, e800100, 3, (RF, RF, RF_IF), rd_rn_rm),
9463 cCL(rmfsp, e800120, 3, (RF, RF, RF_IF), rd_rn_rm),
9464 cCL(rmfsm, e800140, 3, (RF, RF, RF_IF), rd_rn_rm),
9465 cCL(rmfsz, e800160, 3, (RF, RF, RF_IF), rd_rn_rm),
9466 cCL(rmfd, e800180, 3, (RF, RF, RF_IF), rd_rn_rm),
9467 cCL(rmfdp, e8001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
9468 cCL(rmfdm, e8001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
9469 cCL(rmfdz, e8001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
9470 cCL(rmfe, e880100, 3, (RF, RF, RF_IF), rd_rn_rm),
9471 cCL(rmfep, e880120, 3, (RF, RF, RF_IF), rd_rn_rm),
9472 cCL(rmfem, e880140, 3, (RF, RF, RF_IF), rd_rn_rm),
9473 cCL(rmfez, e880160, 3, (RF, RF, RF_IF), rd_rn_rm),
9474
9475 cCL(fmls, e900100, 3, (RF, RF, RF_IF), rd_rn_rm),
9476 cCL(fmlsp, e900120, 3, (RF, RF, RF_IF), rd_rn_rm),
9477 cCL(fmlsm, e900140, 3, (RF, RF, RF_IF), rd_rn_rm),
9478 cCL(fmlsz, e900160, 3, (RF, RF, RF_IF), rd_rn_rm),
9479 cCL(fmld, e900180, 3, (RF, RF, RF_IF), rd_rn_rm),
9480 cCL(fmldp, e9001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
9481 cCL(fmldm, e9001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
9482 cCL(fmldz, e9001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
9483 cCL(fmle, e980100, 3, (RF, RF, RF_IF), rd_rn_rm),
9484 cCL(fmlep, e980120, 3, (RF, RF, RF_IF), rd_rn_rm),
9485 cCL(fmlem, e980140, 3, (RF, RF, RF_IF), rd_rn_rm),
9486 cCL(fmlez, e980160, 3, (RF, RF, RF_IF), rd_rn_rm),
9487
9488 cCL(fdvs, ea00100, 3, (RF, RF, RF_IF), rd_rn_rm),
9489 cCL(fdvsp, ea00120, 3, (RF, RF, RF_IF), rd_rn_rm),
9490 cCL(fdvsm, ea00140, 3, (RF, RF, RF_IF), rd_rn_rm),
9491 cCL(fdvsz, ea00160, 3, (RF, RF, RF_IF), rd_rn_rm),
9492 cCL(fdvd, ea00180, 3, (RF, RF, RF_IF), rd_rn_rm),
9493 cCL(fdvdp, ea001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
9494 cCL(fdvdm, ea001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
9495 cCL(fdvdz, ea001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
9496 cCL(fdve, ea80100, 3, (RF, RF, RF_IF), rd_rn_rm),
9497 cCL(fdvep, ea80120, 3, (RF, RF, RF_IF), rd_rn_rm),
9498 cCL(fdvem, ea80140, 3, (RF, RF, RF_IF), rd_rn_rm),
9499 cCL(fdvez, ea80160, 3, (RF, RF, RF_IF), rd_rn_rm),
9500
9501 cCL(frds, eb00100, 3, (RF, RF, RF_IF), rd_rn_rm),
9502 cCL(frdsp, eb00120, 3, (RF, RF, RF_IF), rd_rn_rm),
9503 cCL(frdsm, eb00140, 3, (RF, RF, RF_IF), rd_rn_rm),
9504 cCL(frdsz, eb00160, 3, (RF, RF, RF_IF), rd_rn_rm),
9505 cCL(frdd, eb00180, 3, (RF, RF, RF_IF), rd_rn_rm),
9506 cCL(frddp, eb001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
9507 cCL(frddm, eb001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
9508 cCL(frddz, eb001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
9509 cCL(frde, eb80100, 3, (RF, RF, RF_IF), rd_rn_rm),
9510 cCL(frdep, eb80120, 3, (RF, RF, RF_IF), rd_rn_rm),
9511 cCL(frdem, eb80140, 3, (RF, RF, RF_IF), rd_rn_rm),
9512 cCL(frdez, eb80160, 3, (RF, RF, RF_IF), rd_rn_rm),
9513
9514 cCL(pols, ec00100, 3, (RF, RF, RF_IF), rd_rn_rm),
9515 cCL(polsp, ec00120, 3, (RF, RF, RF_IF), rd_rn_rm),
9516 cCL(polsm, ec00140, 3, (RF, RF, RF_IF), rd_rn_rm),
9517 cCL(polsz, ec00160, 3, (RF, RF, RF_IF), rd_rn_rm),
9518 cCL(pold, ec00180, 3, (RF, RF, RF_IF), rd_rn_rm),
9519 cCL(poldp, ec001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
9520 cCL(poldm, ec001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
9521 cCL(poldz, ec001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
9522 cCL(pole, ec80100, 3, (RF, RF, RF_IF), rd_rn_rm),
9523 cCL(polep, ec80120, 3, (RF, RF, RF_IF), rd_rn_rm),
9524 cCL(polem, ec80140, 3, (RF, RF, RF_IF), rd_rn_rm),
9525 cCL(polez, ec80160, 3, (RF, RF, RF_IF), rd_rn_rm),
9526
9527 cCE(cmf, e90f110, 2, (RF, RF_IF), fpa_cmp),
9528 C3E(cmfe, ed0f110, 2, (RF, RF_IF), fpa_cmp),
9529 cCE(cnf, eb0f110, 2, (RF, RF_IF), fpa_cmp),
9530 C3E(cnfe, ef0f110, 2, (RF, RF_IF), fpa_cmp),
9531
9532 cCL(flts, e000110, 2, (RF, RR), rn_rd),
9533 cCL(fltsp, e000130, 2, (RF, RR), rn_rd),
9534 cCL(fltsm, e000150, 2, (RF, RR), rn_rd),
9535 cCL(fltsz, e000170, 2, (RF, RR), rn_rd),
9536 cCL(fltd, e000190, 2, (RF, RR), rn_rd),
9537 cCL(fltdp, e0001b0, 2, (RF, RR), rn_rd),
9538 cCL(fltdm, e0001d0, 2, (RF, RR), rn_rd),
9539 cCL(fltdz, e0001f0, 2, (RF, RR), rn_rd),
9540 cCL(flte, e080110, 2, (RF, RR), rn_rd),
9541 cCL(fltep, e080130, 2, (RF, RR), rn_rd),
9542 cCL(fltem, e080150, 2, (RF, RR), rn_rd),
9543 cCL(fltez, e080170, 2, (RF, RR), rn_rd),
9544
9545 /* The implementation of the FIX instruction is broken on some
9546 assemblers, in that it accepts a precision specifier as well as a
9547 rounding specifier, despite the fact that this is meaningless.
9548 To be more compatible, we accept it as well, though of course it
9549 does not set any bits. */
9550 cCE(fix, e100110, 2, (RR, RF), rd_rm),
9551 cCL(fixp, e100130, 2, (RR, RF), rd_rm),
9552 cCL(fixm, e100150, 2, (RR, RF), rd_rm),
9553 cCL(fixz, e100170, 2, (RR, RF), rd_rm),
9554 cCL(fixsp, e100130, 2, (RR, RF), rd_rm),
9555 cCL(fixsm, e100150, 2, (RR, RF), rd_rm),
9556 cCL(fixsz, e100170, 2, (RR, RF), rd_rm),
9557 cCL(fixdp, e100130, 2, (RR, RF), rd_rm),
9558 cCL(fixdm, e100150, 2, (RR, RF), rd_rm),
9559 cCL(fixdz, e100170, 2, (RR, RF), rd_rm),
9560 cCL(fixep, e100130, 2, (RR, RF), rd_rm),
9561 cCL(fixem, e100150, 2, (RR, RF), rd_rm),
9562 cCL(fixez, e100170, 2, (RR, RF), rd_rm),
9563
9564 /* Instructions that were new with the real FPA, call them V2. */
9565 #undef ARM_VARIANT
9566 #define ARM_VARIANT &fpu_fpa_ext_v2
9567 cCE(lfm, c100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
9568 cCL(lfmfd, c900200, 3, (RF, I4b, ADDR), fpa_ldmstm),
9569 cCL(lfmea, d100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
9570 cCE(sfm, c000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
9571 cCL(sfmfd, d000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
9572 cCL(sfmea, c800200, 3, (RF, I4b, ADDR), fpa_ldmstm),
9573
9574 #undef ARM_VARIANT
9575 #define ARM_VARIANT &fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
9576 /* Moves and type conversions. */
9577 cCE(fcpys, eb00a40, 2, (RVS, RVS), vfp_sp_monadic),
9578 cCE(fmrs, e100a10, 2, (RR, RVS), vfp_reg_from_sp),
9579 cCE(fmsr, e000a10, 2, (RVS, RR), vfp_sp_from_reg),
9580 cCE(fmstat, ef1fa10, 0, (), noargs),
9581 cCE(fsitos, eb80ac0, 2, (RVS, RVS), vfp_sp_monadic),
9582 cCE(fuitos, eb80a40, 2, (RVS, RVS), vfp_sp_monadic),
9583 cCE(ftosis, ebd0a40, 2, (RVS, RVS), vfp_sp_monadic),
9584 cCE(ftosizs, ebd0ac0, 2, (RVS, RVS), vfp_sp_monadic),
9585 cCE(ftouis, ebc0a40, 2, (RVS, RVS), vfp_sp_monadic),
9586 cCE(ftouizs, ebc0ac0, 2, (RVS, RVS), vfp_sp_monadic),
9587 cCE(fmrx, ef00a10, 2, (RR, RVC), rd_rn),
9588 cCE(fmxr, ee00a10, 2, (RVC, RR), rn_rd),
9589
9590 /* Memory operations. */
9591 cCE(flds, d100a00, 2, (RVS, ADDR), vfp_sp_ldst),
9592 cCE(fsts, d000a00, 2, (RVS, ADDR), vfp_sp_ldst),
9593 cCE(fldmias, c900a00, 2, (RRw, VRSLST), vfp_sp_ldstmia),
9594 cCE(fldmfds, c900a00, 2, (RRw, VRSLST), vfp_sp_ldstmia),
9595 cCE(fldmdbs, d300a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb),
9596 cCE(fldmeas, d300a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb),
9597 cCE(fldmiax, c900b00, 2, (RRw, VRDLST), vfp_xp_ldstmia),
9598 cCE(fldmfdx, c900b00, 2, (RRw, VRDLST), vfp_xp_ldstmia),
9599 cCE(fldmdbx, d300b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb),
9600 cCE(fldmeax, d300b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb),
9601 cCE(fstmias, c800a00, 2, (RRw, VRSLST), vfp_sp_ldstmia),
9602 cCE(fstmeas, c800a00, 2, (RRw, VRSLST), vfp_sp_ldstmia),
9603 cCE(fstmdbs, d200a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb),
9604 cCE(fstmfds, d200a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb),
9605 cCE(fstmiax, c800b00, 2, (RRw, VRDLST), vfp_xp_ldstmia),
9606 cCE(fstmeax, c800b00, 2, (RRw, VRDLST), vfp_xp_ldstmia),
9607 cCE(fstmdbx, d200b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb),
9608 cCE(fstmfdx, d200b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb),
9609
9610 /* Monadic operations. */
9611 cCE(fabss, eb00ac0, 2, (RVS, RVS), vfp_sp_monadic),
9612 cCE(fnegs, eb10a40, 2, (RVS, RVS), vfp_sp_monadic),
9613 cCE(fsqrts, eb10ac0, 2, (RVS, RVS), vfp_sp_monadic),
9614
9615 /* Dyadic operations. */
9616 cCE(fadds, e300a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
9617 cCE(fsubs, e300a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
9618 cCE(fmuls, e200a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
9619 cCE(fdivs, e800a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
9620 cCE(fmacs, e000a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
9621 cCE(fmscs, e100a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
9622 cCE(fnmuls, e200a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
9623 cCE(fnmacs, e000a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
9624 cCE(fnmscs, e100a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
9625
9626 /* Comparisons. */
9627 cCE(fcmps, eb40a40, 2, (RVS, RVS), vfp_sp_monadic),
9628 cCE(fcmpzs, eb50a40, 1, (RVS), vfp_sp_compare_z),
9629 cCE(fcmpes, eb40ac0, 2, (RVS, RVS), vfp_sp_monadic),
9630 cCE(fcmpezs, eb50ac0, 1, (RVS), vfp_sp_compare_z),
9631
9632 #undef ARM_VARIANT
9633 #define ARM_VARIANT &fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
9634 /* Moves and type conversions. */
9635 cCE(fcpyd, eb00b40, 2, (RVD, RVD), rd_rm),
9636 cCE(fcvtds, eb70ac0, 2, (RVD, RVS), vfp_dp_sp_cvt),
9637 cCE(fcvtsd, eb70bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
9638 cCE(fmdhr, e200b10, 2, (RVD, RR), rn_rd),
9639 cCE(fmdlr, e000b10, 2, (RVD, RR), rn_rd),
9640 cCE(fmrdh, e300b10, 2, (RR, RVD), rd_rn),
9641 cCE(fmrdl, e100b10, 2, (RR, RVD), rd_rn),
9642 cCE(fsitod, eb80bc0, 2, (RVD, RVS), vfp_dp_sp_cvt),
9643 cCE(fuitod, eb80b40, 2, (RVD, RVS), vfp_dp_sp_cvt),
9644 cCE(ftosid, ebd0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
9645 cCE(ftosizd, ebd0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
9646 cCE(ftouid, ebc0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
9647 cCE(ftouizd, ebc0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
9648
9649 /* Memory operations. */
9650 cCE(fldd, d100b00, 2, (RVD, ADDR), vfp_dp_ldst),
9651 cCE(fstd, d000b00, 2, (RVD, ADDR), vfp_dp_ldst),
9652 cCE(fldmiad, c900b00, 2, (RRw, VRDLST), vfp_dp_ldstmia),
9653 cCE(fldmfdd, c900b00, 2, (RRw, VRDLST), vfp_dp_ldstmia),
9654 cCE(fldmdbd, d300b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb),
9655 cCE(fldmead, d300b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb),
9656 cCE(fstmiad, c800b00, 2, (RRw, VRDLST), vfp_dp_ldstmia),
9657 cCE(fstmead, c800b00, 2, (RRw, VRDLST), vfp_dp_ldstmia),
9658 cCE(fstmdbd, d200b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb),
9659 cCE(fstmfdd, d200b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb),
9660
9661 /* Monadic operations. */
9662 cCE(fabsd, eb00bc0, 2, (RVD, RVD), rd_rm),
9663 cCE(fnegd, eb10b40, 2, (RVD, RVD), rd_rm),
9664 cCE(fsqrtd, eb10bc0, 2, (RVD, RVD), rd_rm),
9665
9666 /* Dyadic operations. */
9667 cCE(faddd, e300b00, 3, (RVD, RVD, RVD), rd_rn_rm),
9668 cCE(fsubd, e300b40, 3, (RVD, RVD, RVD), rd_rn_rm),
9669 cCE(fmuld, e200b00, 3, (RVD, RVD, RVD), rd_rn_rm),
9670 cCE(fdivd, e800b00, 3, (RVD, RVD, RVD), rd_rn_rm),
9671 cCE(fmacd, e000b00, 3, (RVD, RVD, RVD), rd_rn_rm),
9672 cCE(fmscd, e100b00, 3, (RVD, RVD, RVD), rd_rn_rm),
9673 cCE(fnmuld, e200b40, 3, (RVD, RVD, RVD), rd_rn_rm),
9674 cCE(fnmacd, e000b40, 3, (RVD, RVD, RVD), rd_rn_rm),
9675 cCE(fnmscd, e100b40, 3, (RVD, RVD, RVD), rd_rn_rm),
9676
9677 /* Comparisons. */
9678 cCE(fcmpd, eb40b40, 2, (RVD, RVD), rd_rm),
9679 cCE(fcmpzd, eb50b40, 1, (RVD), rd),
9680 cCE(fcmped, eb40bc0, 2, (RVD, RVD), rd_rm),
9681 cCE(fcmpezd, eb50bc0, 1, (RVD), rd),
9682
9683 #undef ARM_VARIANT
9684 #define ARM_VARIANT &fpu_vfp_ext_v2
9685 cCE(fmsrr, c400a10, 3, (VRSLST, RR, RR), vfp_sp2_from_reg2),
9686 cCE(fmrrs, c500a10, 3, (RR, RR, VRSLST), vfp_reg2_from_sp2),
9687 cCE(fmdrr, c400b10, 3, (RVD, RR, RR), rm_rd_rn),
9688 cCE(fmrrd, c500b10, 3, (RR, RR, RVD), rd_rn_rm),
9689
9690 #undef ARM_VARIANT
9691 #define ARM_VARIANT &arm_cext_xscale /* Intel XScale extensions. */
9692 cCE(mia, e200010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
9693 cCE(miaph, e280010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
9694 cCE(miabb, e2c0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
9695 cCE(miabt, e2d0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
9696 cCE(miatb, e2e0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
9697 cCE(miatt, e2f0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
9698 cCE(mar, c400000, 3, (RXA, RRnpc, RRnpc), xsc_mar),
9699 cCE(mra, c500000, 3, (RRnpc, RRnpc, RXA), xsc_mra),
9700
9701 #undef ARM_VARIANT
9702 #define ARM_VARIANT &arm_cext_iwmmxt /* Intel Wireless MMX technology. */
9703 cCE(tandcb, e13f130, 1, (RR), iwmmxt_tandorc),
9704 cCE(tandch, e53f130, 1, (RR), iwmmxt_tandorc),
9705 cCE(tandcw, e93f130, 1, (RR), iwmmxt_tandorc),
9706 cCE(tbcstb, e400010, 2, (RIWR, RR), rn_rd),
9707 cCE(tbcsth, e400050, 2, (RIWR, RR), rn_rd),
9708 cCE(tbcstw, e400090, 2, (RIWR, RR), rn_rd),
9709 cCE(textrcb, e130170, 2, (RR, I7), iwmmxt_textrc),
9710 cCE(textrch, e530170, 2, (RR, I7), iwmmxt_textrc),
9711 cCE(textrcw, e930170, 2, (RR, I7), iwmmxt_textrc),
9712 cCE(textrmub, e100070, 3, (RR, RIWR, I7), iwmmxt_textrm),
9713 cCE(textrmuh, e500070, 3, (RR, RIWR, I7), iwmmxt_textrm),
9714 cCE(textrmuw, e900070, 3, (RR, RIWR, I7), iwmmxt_textrm),
9715 cCE(textrmsb, e100078, 3, (RR, RIWR, I7), iwmmxt_textrm),
9716 cCE(textrmsh, e500078, 3, (RR, RIWR, I7), iwmmxt_textrm),
9717 cCE(textrmsw, e900078, 3, (RR, RIWR, I7), iwmmxt_textrm),
9718 cCE(tinsrb, e600010, 3, (RIWR, RR, I7), iwmmxt_tinsr),
9719 cCE(tinsrh, e600050, 3, (RIWR, RR, I7), iwmmxt_tinsr),
9720 cCE(tinsrw, e600090, 3, (RIWR, RR, I7), iwmmxt_tinsr),
9721 cCE(tmcr, e000110, 2, (RIWC, RR), rn_rd),
9722 cCE(tmcrr, c400000, 3, (RIWR, RR, RR), rm_rd_rn),
9723 cCE(tmia, e200010, 3, (RIWR, RR, RR), iwmmxt_tmia),
9724 cCE(tmiaph, e280010, 3, (RIWR, RR, RR), iwmmxt_tmia),
9725 cCE(tmiabb, e2c0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
9726 cCE(tmiabt, e2d0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
9727 cCE(tmiatb, e2e0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
9728 cCE(tmiatt, e2f0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
9729 cCE(tmovmskb, e100030, 2, (RR, RIWR), rd_rn),
9730 cCE(tmovmskh, e500030, 2, (RR, RIWR), rd_rn),
9731 cCE(tmovmskw, e900030, 2, (RR, RIWR), rd_rn),
9732 cCE(tmrc, e100110, 2, (RR, RIWC), rd_rn),
9733 cCE(tmrrc, c500000, 3, (RR, RR, RIWR), rd_rn_rm),
9734 cCE(torcb, e13f150, 1, (RR), iwmmxt_tandorc),
9735 cCE(torch, e53f150, 1, (RR), iwmmxt_tandorc),
9736 cCE(torcw, e93f150, 1, (RR), iwmmxt_tandorc),
9737 cCE(waccb, e0001c0, 2, (RIWR, RIWR), rd_rn),
9738 cCE(wacch, e4001c0, 2, (RIWR, RIWR), rd_rn),
9739 cCE(waccw, e8001c0, 2, (RIWR, RIWR), rd_rn),
9740 cCE(waddbss, e300180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9741 cCE(waddb, e000180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9742 cCE(waddbus, e100180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9743 cCE(waddhss, e700180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9744 cCE(waddh, e400180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9745 cCE(waddhus, e500180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9746 cCE(waddwss, eb00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9747 cCE(waddw, e800180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9748 cCE(waddwus, e900180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9749 cCE(waligni, e000020, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_waligni),
9750 cCE(walignr0, e800020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9751 cCE(walignr1, e900020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9752 cCE(walignr2, ea00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9753 cCE(walignr3, eb00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9754 cCE(wand, e200000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9755 cCE(wandn, e300000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9756 cCE(wavg2b, e800000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9757 cCE(wavg2br, e900000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9758 cCE(wavg2h, ec00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9759 cCE(wavg2hr, ed00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9760 cCE(wcmpeqb, e000060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9761 cCE(wcmpeqh, e400060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9762 cCE(wcmpeqw, e800060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9763 cCE(wcmpgtub, e100060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9764 cCE(wcmpgtuh, e500060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9765 cCE(wcmpgtuw, e900060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9766 cCE(wcmpgtsb, e300060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9767 cCE(wcmpgtsh, e700060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9768 cCE(wcmpgtsw, eb00060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9769 cCE(wldrb, c100000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
9770 cCE(wldrh, c500000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
9771 cCE(wldrw, c100100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
9772 cCE(wldrd, c500100, 2, (RIWR, ADDR), iwmmxt_wldstd),
9773 cCE(wmacs, e600100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9774 cCE(wmacsz, e700100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9775 cCE(wmacu, e400100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9776 cCE(wmacuz, e500100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9777 cCE(wmadds, ea00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9778 cCE(wmaddu, e800100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9779 cCE(wmaxsb, e200160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9780 cCE(wmaxsh, e600160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9781 cCE(wmaxsw, ea00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9782 cCE(wmaxub, e000160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9783 cCE(wmaxuh, e400160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9784 cCE(wmaxuw, e800160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9785 cCE(wminsb, e300160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9786 cCE(wminsh, e700160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9787 cCE(wminsw, eb00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9788 cCE(wminub, e100160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9789 cCE(wminuh, e500160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9790 cCE(wminuw, e900160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9791 cCE(wmov, e000000, 2, (RIWR, RIWR), iwmmxt_wmov),
9792 cCE(wmulsm, e300100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9793 cCE(wmulsl, e200100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9794 cCE(wmulum, e100100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9795 cCE(wmulul, e000100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9796 cCE(wor, e000000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9797 cCE(wpackhss, e700080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9798 cCE(wpackhus, e500080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9799 cCE(wpackwss, eb00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9800 cCE(wpackwus, e900080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9801 cCE(wpackdss, ef00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9802 cCE(wpackdus, ed00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9803 cCE(wrorh, e700040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9804 cCE(wrorhg, e700148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
9805 cCE(wrorw, eb00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9806 cCE(wrorwg, eb00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
9807 cCE(wrord, ef00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9808 cCE(wrordg, ef00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
9809 cCE(wsadb, e000120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9810 cCE(wsadbz, e100120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9811 cCE(wsadh, e400120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9812 cCE(wsadhz, e500120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9813 cCE(wshufh, e0001e0, 3, (RIWR, RIWR, I255), iwmmxt_wshufh),
9814 cCE(wsllh, e500040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9815 cCE(wsllhg, e500148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
9816 cCE(wsllw, e900040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9817 cCE(wsllwg, e900148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
9818 cCE(wslld, ed00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9819 cCE(wslldg, ed00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
9820 cCE(wsrah, e400040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9821 cCE(wsrahg, e400148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
9822 cCE(wsraw, e800040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9823 cCE(wsrawg, e800148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
9824 cCE(wsrad, ec00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9825 cCE(wsradg, ec00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
9826 cCE(wsrlh, e600040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9827 cCE(wsrlhg, e600148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
9828 cCE(wsrlw, ea00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9829 cCE(wsrlwg, ea00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
9830 cCE(wsrld, ee00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9831 cCE(wsrldg, ee00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
9832 cCE(wstrb, c000000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
9833 cCE(wstrh, c400000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
9834 cCE(wstrw, c000100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
9835 cCE(wstrd, c400100, 2, (RIWR, ADDR), iwmmxt_wldstd),
9836 cCE(wsubbss, e3001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9837 cCE(wsubb, e0001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9838 cCE(wsubbus, e1001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9839 cCE(wsubhss, e7001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9840 cCE(wsubh, e4001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9841 cCE(wsubhus, e5001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9842 cCE(wsubwss, eb001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9843 cCE(wsubw, e8001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9844 cCE(wsubwus, e9001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9845 cCE(wunpckehub,e0000c0, 2, (RIWR, RIWR), rd_rn),
9846 cCE(wunpckehuh,e4000c0, 2, (RIWR, RIWR), rd_rn),
9847 cCE(wunpckehuw,e8000c0, 2, (RIWR, RIWR), rd_rn),
9848 cCE(wunpckehsb,e2000c0, 2, (RIWR, RIWR), rd_rn),
9849 cCE(wunpckehsh,e6000c0, 2, (RIWR, RIWR), rd_rn),
9850 cCE(wunpckehsw,ea000c0, 2, (RIWR, RIWR), rd_rn),
9851 cCE(wunpckihb, e1000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9852 cCE(wunpckihh, e5000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9853 cCE(wunpckihw, e9000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9854 cCE(wunpckelub,e0000e0, 2, (RIWR, RIWR), rd_rn),
9855 cCE(wunpckeluh,e4000e0, 2, (RIWR, RIWR), rd_rn),
9856 cCE(wunpckeluw,e8000e0, 2, (RIWR, RIWR), rd_rn),
9857 cCE(wunpckelsb,e2000e0, 2, (RIWR, RIWR), rd_rn),
9858 cCE(wunpckelsh,e6000e0, 2, (RIWR, RIWR), rd_rn),
9859 cCE(wunpckelsw,ea000e0, 2, (RIWR, RIWR), rd_rn),
9860 cCE(wunpckilb, e1000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9861 cCE(wunpckilh, e5000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9862 cCE(wunpckilw, e9000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9863 cCE(wxor, e100000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9864 cCE(wzero, e300000, 1, (RIWR), iwmmxt_wzero),
9865
9866 #undef ARM_VARIANT
9867 #define ARM_VARIANT &arm_cext_maverick /* Cirrus Maverick instructions. */
9868 cCE(cfldrs, c100400, 2, (RMF, ADDR), rd_cpaddr),
9869 cCE(cfldrd, c500400, 2, (RMD, ADDR), rd_cpaddr),
9870 cCE(cfldr32, c100500, 2, (RMFX, ADDR), rd_cpaddr),
9871 cCE(cfldr64, c500500, 2, (RMDX, ADDR), rd_cpaddr),
9872 cCE(cfstrs, c000400, 2, (RMF, ADDR), rd_cpaddr),
9873 cCE(cfstrd, c400400, 2, (RMD, ADDR), rd_cpaddr),
9874 cCE(cfstr32, c000500, 2, (RMFX, ADDR), rd_cpaddr),
9875 cCE(cfstr64, c400500, 2, (RMDX, ADDR), rd_cpaddr),
9876 cCE(cfmvsr, e000450, 2, (RMF, RR), rn_rd),
9877 cCE(cfmvrs, e100450, 2, (RR, RMF), rd_rn),
9878 cCE(cfmvdlr, e000410, 2, (RMD, RR), rn_rd),
9879 cCE(cfmvrdl, e100410, 2, (RR, RMD), rd_rn),
9880 cCE(cfmvdhr, e000430, 2, (RMD, RR), rn_rd),
9881 cCE(cfmvrdh, e100430, 2, (RR, RMD), rd_rn),
9882 cCE(cfmv64lr, e000510, 2, (RMDX, RR), rn_rd),
9883 cCE(cfmvr64l, e100510, 2, (RR, RMDX), rd_rn),
9884 cCE(cfmv64hr, e000530, 2, (RMDX, RR), rn_rd),
9885 cCE(cfmvr64h, e100530, 2, (RR, RMDX), rd_rn),
9886 cCE(cfmval32, e200440, 2, (RMAX, RMFX), rd_rn),
9887 cCE(cfmv32al, e100440, 2, (RMFX, RMAX), rd_rn),
9888 cCE(cfmvam32, e200460, 2, (RMAX, RMFX), rd_rn),
9889 cCE(cfmv32am, e100460, 2, (RMFX, RMAX), rd_rn),
9890 cCE(cfmvah32, e200480, 2, (RMAX, RMFX), rd_rn),
9891 cCE(cfmv32ah, e100480, 2, (RMFX, RMAX), rd_rn),
9892 cCE(cfmva32, e2004a0, 2, (RMAX, RMFX), rd_rn),
9893 cCE(cfmv32a, e1004a0, 2, (RMFX, RMAX), rd_rn),
9894 cCE(cfmva64, e2004c0, 2, (RMAX, RMDX), rd_rn),
9895 cCE(cfmv64a, e1004c0, 2, (RMDX, RMAX), rd_rn),
9896 cCE(cfmvsc32, e2004e0, 2, (RMDS, RMDX), mav_dspsc),
9897 cCE(cfmv32sc, e1004e0, 2, (RMDX, RMDS), rd),
9898 cCE(cfcpys, e000400, 2, (RMF, RMF), rd_rn),
9899 cCE(cfcpyd, e000420, 2, (RMD, RMD), rd_rn),
9900 cCE(cfcvtsd, e000460, 2, (RMD, RMF), rd_rn),
9901 cCE(cfcvtds, e000440, 2, (RMF, RMD), rd_rn),
9902 cCE(cfcvt32s, e000480, 2, (RMF, RMFX), rd_rn),
9903 cCE(cfcvt32d, e0004a0, 2, (RMD, RMFX), rd_rn),
9904 cCE(cfcvt64s, e0004c0, 2, (RMF, RMDX), rd_rn),
9905 cCE(cfcvt64d, e0004e0, 2, (RMD, RMDX), rd_rn),
9906 cCE(cfcvts32, e100580, 2, (RMFX, RMF), rd_rn),
9907 cCE(cfcvtd32, e1005a0, 2, (RMFX, RMD), rd_rn),
9908 cCE(cftruncs32,e1005c0, 2, (RMFX, RMF), rd_rn),
9909 cCE(cftruncd32,e1005e0, 2, (RMFX, RMD), rd_rn),
9910 cCE(cfrshl32, e000550, 3, (RMFX, RMFX, RR), mav_triple),
9911 cCE(cfrshl64, e000570, 3, (RMDX, RMDX, RR), mav_triple),
9912 cCE(cfsh32, e000500, 3, (RMFX, RMFX, I63s), mav_shift),
9913 cCE(cfsh64, e200500, 3, (RMDX, RMDX, I63s), mav_shift),
9914 cCE(cfcmps, e100490, 3, (RR, RMF, RMF), rd_rn_rm),
9915 cCE(cfcmpd, e1004b0, 3, (RR, RMD, RMD), rd_rn_rm),
9916 cCE(cfcmp32, e100590, 3, (RR, RMFX, RMFX), rd_rn_rm),
9917 cCE(cfcmp64, e1005b0, 3, (RR, RMDX, RMDX), rd_rn_rm),
9918 cCE(cfabss, e300400, 2, (RMF, RMF), rd_rn),
9919 cCE(cfabsd, e300420, 2, (RMD, RMD), rd_rn),
9920 cCE(cfnegs, e300440, 2, (RMF, RMF), rd_rn),
9921 cCE(cfnegd, e300460, 2, (RMD, RMD), rd_rn),
9922 cCE(cfadds, e300480, 3, (RMF, RMF, RMF), rd_rn_rm),
9923 cCE(cfaddd, e3004a0, 3, (RMD, RMD, RMD), rd_rn_rm),
9924 cCE(cfsubs, e3004c0, 3, (RMF, RMF, RMF), rd_rn_rm),
9925 cCE(cfsubd, e3004e0, 3, (RMD, RMD, RMD), rd_rn_rm),
9926 cCE(cfmuls, e100400, 3, (RMF, RMF, RMF), rd_rn_rm),
9927 cCE(cfmuld, e100420, 3, (RMD, RMD, RMD), rd_rn_rm),
9928 cCE(cfabs32, e300500, 2, (RMFX, RMFX), rd_rn),
9929 cCE(cfabs64, e300520, 2, (RMDX, RMDX), rd_rn),
9930 cCE(cfneg32, e300540, 2, (RMFX, RMFX), rd_rn),
9931 cCE(cfneg64, e300560, 2, (RMDX, RMDX), rd_rn),
9932 cCE(cfadd32, e300580, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
9933 cCE(cfadd64, e3005a0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
9934 cCE(cfsub32, e3005c0, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
9935 cCE(cfsub64, e3005e0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
9936 cCE(cfmul32, e100500, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
9937 cCE(cfmul64, e100520, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
9938 cCE(cfmac32, e100540, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
9939 cCE(cfmsc32, e100560, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
9940 cCE(cfmadd32, e000600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
9941 cCE(cfmsub32, e100600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
9942 cCE(cfmadda32, e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
9943 cCE(cfmsuba32, e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
9944 };
9945 #undef ARM_VARIANT
9946 #undef THUMB_VARIANT
9947 #undef TCE
9948 #undef TCM
9949 #undef TUE
9950 #undef TUF
9951 #undef TCC
9952 #undef cCE
9953 #undef cCL
9954 #undef C3E
9955 #undef CE
9956 #undef CM
9957 #undef UE
9958 #undef UF
9959 #undef UT
9960 #undef OPS0
9961 #undef OPS1
9962 #undef OPS2
9963 #undef OPS3
9964 #undef OPS4
9965 #undef OPS5
9966 #undef OPS6
9967 #undef do_0
9968 \f
9969 /* MD interface: bits in the object file. */
9970
9971 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
9972 for use in the a.out file, and stores them in the array pointed to by buf.
9973 This knows about the endian-ness of the target machine and does
9974 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
9975 2 (short) and 4 (long) Floating numbers are put out as a series of
9976 LITTLENUMS (shorts, here at least). */
9977
9978 void
9979 md_number_to_chars (char * buf, valueT val, int n)
9980 {
9981 if (target_big_endian)
9982 number_to_chars_bigendian (buf, val, n);
9983 else
9984 number_to_chars_littleendian (buf, val, n);
9985 }
9986
9987 static valueT
9988 md_chars_to_number (char * buf, int n)
9989 {
9990 valueT result = 0;
9991 unsigned char * where = (unsigned char *) buf;
9992
9993 if (target_big_endian)
9994 {
9995 while (n--)
9996 {
9997 result <<= 8;
9998 result |= (*where++ & 255);
9999 }
10000 }
10001 else
10002 {
10003 while (n--)
10004 {
10005 result <<= 8;
10006 result |= (where[n] & 255);
10007 }
10008 }
10009
10010 return result;
10011 }
10012
10013 /* MD interface: Sections. */
10014
10015 /* Estimate the size of a frag before relaxing. Assume everything fits in
10016 2 bytes. */
10017
10018 int
10019 md_estimate_size_before_relax (fragS * fragp,
10020 segT segtype ATTRIBUTE_UNUSED)
10021 {
10022 fragp->fr_var = 2;
10023 return 2;
10024 }
10025
10026 /* Convert a machine dependent frag. */
10027
10028 void
10029 md_convert_frag (bfd *abfd, segT asec ATTRIBUTE_UNUSED, fragS *fragp)
10030 {
10031 unsigned long insn;
10032 unsigned long old_op;
10033 char *buf;
10034 expressionS exp;
10035 fixS *fixp;
10036 int reloc_type;
10037 int pc_rel;
10038 int opcode;
10039
10040 buf = fragp->fr_literal + fragp->fr_fix;
10041
10042 old_op = bfd_get_16(abfd, buf);
10043 if (fragp->fr_symbol) {
10044 exp.X_op = O_symbol;
10045 exp.X_add_symbol = fragp->fr_symbol;
10046 } else {
10047 exp.X_op = O_constant;
10048 }
10049 exp.X_add_number = fragp->fr_offset;
10050 opcode = fragp->fr_subtype;
10051 switch (opcode)
10052 {
10053 case T_MNEM_ldr_pc:
10054 case T_MNEM_ldr_pc2:
10055 case T_MNEM_ldr_sp:
10056 case T_MNEM_str_sp:
10057 case T_MNEM_ldr:
10058 case T_MNEM_ldrb:
10059 case T_MNEM_ldrh:
10060 case T_MNEM_str:
10061 case T_MNEM_strb:
10062 case T_MNEM_strh:
10063 if (fragp->fr_var == 4)
10064 {
10065 insn = THUMB_OP32(opcode);
10066 if ((old_op >> 12) == 4 || (old_op >> 12) == 9)
10067 {
10068 insn |= (old_op & 0x700) << 4;
10069 }
10070 else
10071 {
10072 insn |= (old_op & 7) << 12;
10073 insn |= (old_op & 0x38) << 13;
10074 }
10075 insn |= 0x00000c00;
10076 put_thumb32_insn (buf, insn);
10077 reloc_type = BFD_RELOC_ARM_T32_OFFSET_IMM;
10078 }
10079 else
10080 {
10081 reloc_type = BFD_RELOC_ARM_THUMB_OFFSET;
10082 }
10083 pc_rel = (opcode == T_MNEM_ldr_pc2);
10084 break;
10085 case T_MNEM_adr:
10086 if (fragp->fr_var == 4)
10087 {
10088 insn = THUMB_OP32 (opcode);
10089 insn |= (old_op & 0xf0) << 4;
10090 put_thumb32_insn (buf, insn);
10091 reloc_type = BFD_RELOC_ARM_T32_ADD_PC12;
10092 }
10093 else
10094 {
10095 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
10096 exp.X_add_number -= 4;
10097 }
10098 pc_rel = 1;
10099 break;
10100 case T_MNEM_mov:
10101 case T_MNEM_movs:
10102 case T_MNEM_cmp:
10103 case T_MNEM_cmn:
10104 if (fragp->fr_var == 4)
10105 {
10106 int r0off = (opcode == T_MNEM_mov
10107 || opcode == T_MNEM_movs) ? 0 : 8;
10108 insn = THUMB_OP32 (opcode);
10109 insn = (insn & 0xe1ffffff) | 0x10000000;
10110 insn |= (old_op & 0x700) << r0off;
10111 put_thumb32_insn (buf, insn);
10112 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
10113 }
10114 else
10115 {
10116 reloc_type = BFD_RELOC_ARM_THUMB_IMM;
10117 }
10118 pc_rel = 0;
10119 break;
10120 case T_MNEM_b:
10121 if (fragp->fr_var == 4)
10122 {
10123 insn = THUMB_OP32(opcode);
10124 put_thumb32_insn (buf, insn);
10125 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH25;
10126 }
10127 else
10128 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH12;
10129 pc_rel = 1;
10130 break;
10131 case T_MNEM_bcond:
10132 if (fragp->fr_var == 4)
10133 {
10134 insn = THUMB_OP32(opcode);
10135 insn |= (old_op & 0xf00) << 14;
10136 put_thumb32_insn (buf, insn);
10137 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH20;
10138 }
10139 else
10140 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH9;
10141 pc_rel = 1;
10142 break;
10143 case T_MNEM_add_sp:
10144 case T_MNEM_add_pc:
10145 case T_MNEM_inc_sp:
10146 case T_MNEM_dec_sp:
10147 if (fragp->fr_var == 4)
10148 {
10149 /* ??? Choose between add and addw. */
10150 insn = THUMB_OP32 (opcode);
10151 insn |= (old_op & 0xf0) << 4;
10152 put_thumb32_insn (buf, insn);
10153 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
10154 }
10155 else
10156 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
10157 pc_rel = 0;
10158 break;
10159
10160 case T_MNEM_addi:
10161 case T_MNEM_addis:
10162 case T_MNEM_subi:
10163 case T_MNEM_subis:
10164 if (fragp->fr_var == 4)
10165 {
10166 insn = THUMB_OP32 (opcode);
10167 insn |= (old_op & 0xf0) << 4;
10168 insn |= (old_op & 0xf) << 16;
10169 put_thumb32_insn (buf, insn);
10170 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
10171 }
10172 else
10173 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
10174 pc_rel = 0;
10175 break;
10176 default:
10177 abort();
10178 }
10179 fixp = fix_new_exp (fragp, fragp->fr_fix, fragp->fr_var, &exp, pc_rel,
10180 reloc_type);
10181 fixp->fx_file = fragp->fr_file;
10182 fixp->fx_line = fragp->fr_line;
10183 fragp->fr_fix += fragp->fr_var;
10184 }
10185
10186 /* Return the size of a relaxable immediate operand instruction.
10187 SHIFT and SIZE specify the form of the allowable immediate. */
10188 static int
10189 relax_immediate (fragS *fragp, int size, int shift)
10190 {
10191 offsetT offset;
10192 offsetT mask;
10193 offsetT low;
10194
10195 /* ??? Should be able to do better than this. */
10196 if (fragp->fr_symbol)
10197 return 4;
10198
10199 low = (1 << shift) - 1;
10200 mask = (1 << (shift + size)) - (1 << shift);
10201 offset = fragp->fr_offset;
10202 /* Force misaligned offsets to 32-bit variant. */
10203 if (offset & low)
10204 return -4;
10205 if (offset & ~mask)
10206 return 4;
10207 return 2;
10208 }
10209
10210 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
10211 load. */
10212 static int
10213 relax_adr (fragS *fragp, asection *sec)
10214 {
10215 addressT addr;
10216 offsetT val;
10217
10218 /* Assume worst case for symbols not known to be in the same section. */
10219 if (!S_IS_DEFINED(fragp->fr_symbol)
10220 || sec != S_GET_SEGMENT (fragp->fr_symbol))
10221 return 4;
10222
10223 val = S_GET_VALUE(fragp->fr_symbol) + fragp->fr_offset;
10224 addr = fragp->fr_address + fragp->fr_fix;
10225 addr = (addr + 4) & ~3;
10226 /* Fix the insn as the 4-byte version if the target address is not
10227 sufficiently aligned. This is prevents an infinite loop when two
10228 instructions have contradictory range/alignment requirements. */
10229 if (val & 3)
10230 return -4;
10231 val -= addr;
10232 if (val < 0 || val > 1020)
10233 return 4;
10234 return 2;
10235 }
10236
10237 /* Return the size of a relaxable add/sub immediate instruction. */
10238 static int
10239 relax_addsub (fragS *fragp, asection *sec)
10240 {
10241 char *buf;
10242 int op;
10243
10244 buf = fragp->fr_literal + fragp->fr_fix;
10245 op = bfd_get_16(sec->owner, buf);
10246 if ((op & 0xf) == ((op >> 4) & 0xf))
10247 return relax_immediate (fragp, 8, 0);
10248 else
10249 return relax_immediate (fragp, 3, 0);
10250 }
10251
10252
10253 /* Return the size of a relaxable branch instruction. BITS is the
10254 size of the offset field in the narrow instruction. */
10255
10256 static int
10257 relax_branch (fragS *fragp, asection *sec, int bits)
10258 {
10259 addressT addr;
10260 offsetT val;
10261 offsetT limit;
10262
10263 /* Assume worst case for symbols not known to be in the same section. */
10264 if (!S_IS_DEFINED(fragp->fr_symbol)
10265 || sec != S_GET_SEGMENT (fragp->fr_symbol))
10266 return 4;
10267
10268 val = S_GET_VALUE(fragp->fr_symbol) + fragp->fr_offset;
10269 addr = fragp->fr_address + fragp->fr_fix + 4;
10270 val -= addr;
10271
10272 /* Offset is a signed value *2 */
10273 limit = 1 << bits;
10274 if (val >= limit || val < -limit)
10275 return 4;
10276 return 2;
10277 }
10278
10279
10280 /* Relax a machine dependent frag. This returns the amount by which
10281 the current size of the frag should change. */
10282
10283 int
10284 arm_relax_frag (asection *sec, fragS *fragp, long stretch ATTRIBUTE_UNUSED)
10285 {
10286 int oldsize;
10287 int newsize;
10288
10289 oldsize = fragp->fr_var;
10290 switch (fragp->fr_subtype)
10291 {
10292 case T_MNEM_ldr_pc2:
10293 newsize = relax_adr(fragp, sec);
10294 break;
10295 case T_MNEM_ldr_pc:
10296 case T_MNEM_ldr_sp:
10297 case T_MNEM_str_sp:
10298 newsize = relax_immediate(fragp, 8, 2);
10299 break;
10300 case T_MNEM_ldr:
10301 case T_MNEM_str:
10302 newsize = relax_immediate(fragp, 5, 2);
10303 break;
10304 case T_MNEM_ldrh:
10305 case T_MNEM_strh:
10306 newsize = relax_immediate(fragp, 5, 1);
10307 break;
10308 case T_MNEM_ldrb:
10309 case T_MNEM_strb:
10310 newsize = relax_immediate(fragp, 5, 0);
10311 break;
10312 case T_MNEM_adr:
10313 newsize = relax_adr(fragp, sec);
10314 break;
10315 case T_MNEM_mov:
10316 case T_MNEM_movs:
10317 case T_MNEM_cmp:
10318 case T_MNEM_cmn:
10319 newsize = relax_immediate(fragp, 8, 0);
10320 break;
10321 case T_MNEM_b:
10322 newsize = relax_branch(fragp, sec, 11);
10323 break;
10324 case T_MNEM_bcond:
10325 newsize = relax_branch(fragp, sec, 8);
10326 break;
10327 case T_MNEM_add_sp:
10328 case T_MNEM_add_pc:
10329 newsize = relax_immediate (fragp, 8, 2);
10330 break;
10331 case T_MNEM_inc_sp:
10332 case T_MNEM_dec_sp:
10333 newsize = relax_immediate (fragp, 7, 2);
10334 break;
10335 case T_MNEM_addi:
10336 case T_MNEM_addis:
10337 case T_MNEM_subi:
10338 case T_MNEM_subis:
10339 newsize = relax_addsub (fragp, sec);
10340 break;
10341 default:
10342 abort();
10343 }
10344 if (newsize < 0)
10345 {
10346 fragp->fr_var = -newsize;
10347 md_convert_frag (sec->owner, sec, fragp);
10348 frag_wane(fragp);
10349 return -(newsize + oldsize);
10350 }
10351 fragp->fr_var = newsize;
10352 return newsize - oldsize;
10353 }
10354
10355 /* Round up a section size to the appropriate boundary. */
10356
10357 valueT
10358 md_section_align (segT segment ATTRIBUTE_UNUSED,
10359 valueT size)
10360 {
10361 #ifdef OBJ_ELF
10362 return size;
10363 #else
10364 /* Round all sects to multiple of 4. */
10365 return (size + 3) & ~3;
10366 #endif
10367 }
10368
10369 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
10370 of an rs_align_code fragment. */
10371
10372 void
10373 arm_handle_align (fragS * fragP)
10374 {
10375 static char const arm_noop[4] = { 0x00, 0x00, 0xa0, 0xe1 };
10376 static char const thumb_noop[2] = { 0xc0, 0x46 };
10377 static char const arm_bigend_noop[4] = { 0xe1, 0xa0, 0x00, 0x00 };
10378 static char const thumb_bigend_noop[2] = { 0x46, 0xc0 };
10379
10380 int bytes, fix, noop_size;
10381 char * p;
10382 const char * noop;
10383
10384 if (fragP->fr_type != rs_align_code)
10385 return;
10386
10387 bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix;
10388 p = fragP->fr_literal + fragP->fr_fix;
10389 fix = 0;
10390
10391 if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE)
10392 bytes &= MAX_MEM_FOR_RS_ALIGN_CODE;
10393
10394 if (fragP->tc_frag_data)
10395 {
10396 if (target_big_endian)
10397 noop = thumb_bigend_noop;
10398 else
10399 noop = thumb_noop;
10400 noop_size = sizeof (thumb_noop);
10401 }
10402 else
10403 {
10404 if (target_big_endian)
10405 noop = arm_bigend_noop;
10406 else
10407 noop = arm_noop;
10408 noop_size = sizeof (arm_noop);
10409 }
10410
10411 if (bytes & (noop_size - 1))
10412 {
10413 fix = bytes & (noop_size - 1);
10414 memset (p, 0, fix);
10415 p += fix;
10416 bytes -= fix;
10417 }
10418
10419 while (bytes >= noop_size)
10420 {
10421 memcpy (p, noop, noop_size);
10422 p += noop_size;
10423 bytes -= noop_size;
10424 fix += noop_size;
10425 }
10426
10427 fragP->fr_fix += fix;
10428 fragP->fr_var = noop_size;
10429 }
10430
10431 /* Called from md_do_align. Used to create an alignment
10432 frag in a code section. */
10433
10434 void
10435 arm_frag_align_code (int n, int max)
10436 {
10437 char * p;
10438
10439 /* We assume that there will never be a requirement
10440 to support alignments greater than 32 bytes. */
10441 if (max > MAX_MEM_FOR_RS_ALIGN_CODE)
10442 as_fatal (_("alignments greater than 32 bytes not supported in .text sections."));
10443
10444 p = frag_var (rs_align_code,
10445 MAX_MEM_FOR_RS_ALIGN_CODE,
10446 1,
10447 (relax_substateT) max,
10448 (symbolS *) NULL,
10449 (offsetT) n,
10450 (char *) NULL);
10451 *p = 0;
10452 }
10453
10454 /* Perform target specific initialisation of a frag. */
10455
10456 void
10457 arm_init_frag (fragS * fragP)
10458 {
10459 /* Record whether this frag is in an ARM or a THUMB area. */
10460 fragP->tc_frag_data = thumb_mode;
10461 }
10462
10463 #ifdef OBJ_ELF
10464 /* When we change sections we need to issue a new mapping symbol. */
10465
10466 void
10467 arm_elf_change_section (void)
10468 {
10469 flagword flags;
10470 segment_info_type *seginfo;
10471
10472 /* Link an unlinked unwind index table section to the .text section. */
10473 if (elf_section_type (now_seg) == SHT_ARM_EXIDX
10474 && elf_linked_to_section (now_seg) == NULL)
10475 elf_linked_to_section (now_seg) = text_section;
10476
10477 if (!SEG_NORMAL (now_seg))
10478 return;
10479
10480 flags = bfd_get_section_flags (stdoutput, now_seg);
10481
10482 /* We can ignore sections that only contain debug info. */
10483 if ((flags & SEC_ALLOC) == 0)
10484 return;
10485
10486 seginfo = seg_info (now_seg);
10487 mapstate = seginfo->tc_segment_info_data.mapstate;
10488 marked_pr_dependency = seginfo->tc_segment_info_data.marked_pr_dependency;
10489 }
10490
10491 int
10492 arm_elf_section_type (const char * str, size_t len)
10493 {
10494 if (len == 5 && strncmp (str, "exidx", 5) == 0)
10495 return SHT_ARM_EXIDX;
10496
10497 return -1;
10498 }
10499 \f
10500 /* Code to deal with unwinding tables. */
10501
10502 static void add_unwind_adjustsp (offsetT);
10503
10504 /* Cenerate and deferred unwind frame offset. */
10505
10506 static void
10507 flush_pending_unwind (void)
10508 {
10509 offsetT offset;
10510
10511 offset = unwind.pending_offset;
10512 unwind.pending_offset = 0;
10513 if (offset != 0)
10514 add_unwind_adjustsp (offset);
10515 }
10516
10517 /* Add an opcode to this list for this function. Two-byte opcodes should
10518 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
10519 order. */
10520
10521 static void
10522 add_unwind_opcode (valueT op, int length)
10523 {
10524 /* Add any deferred stack adjustment. */
10525 if (unwind.pending_offset)
10526 flush_pending_unwind ();
10527
10528 unwind.sp_restored = 0;
10529
10530 if (unwind.opcode_count + length > unwind.opcode_alloc)
10531 {
10532 unwind.opcode_alloc += ARM_OPCODE_CHUNK_SIZE;
10533 if (unwind.opcodes)
10534 unwind.opcodes = xrealloc (unwind.opcodes,
10535 unwind.opcode_alloc);
10536 else
10537 unwind.opcodes = xmalloc (unwind.opcode_alloc);
10538 }
10539 while (length > 0)
10540 {
10541 length--;
10542 unwind.opcodes[unwind.opcode_count] = op & 0xff;
10543 op >>= 8;
10544 unwind.opcode_count++;
10545 }
10546 }
10547
10548 /* Add unwind opcodes to adjust the stack pointer. */
10549
10550 static void
10551 add_unwind_adjustsp (offsetT offset)
10552 {
10553 valueT op;
10554
10555 if (offset > 0x200)
10556 {
10557 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
10558 char bytes[5];
10559 int n;
10560 valueT o;
10561
10562 /* Long form: 0xb2, uleb128. */
10563 /* This might not fit in a word so add the individual bytes,
10564 remembering the list is built in reverse order. */
10565 o = (valueT) ((offset - 0x204) >> 2);
10566 if (o == 0)
10567 add_unwind_opcode (0, 1);
10568
10569 /* Calculate the uleb128 encoding of the offset. */
10570 n = 0;
10571 while (o)
10572 {
10573 bytes[n] = o & 0x7f;
10574 o >>= 7;
10575 if (o)
10576 bytes[n] |= 0x80;
10577 n++;
10578 }
10579 /* Add the insn. */
10580 for (; n; n--)
10581 add_unwind_opcode (bytes[n - 1], 1);
10582 add_unwind_opcode (0xb2, 1);
10583 }
10584 else if (offset > 0x100)
10585 {
10586 /* Two short opcodes. */
10587 add_unwind_opcode (0x3f, 1);
10588 op = (offset - 0x104) >> 2;
10589 add_unwind_opcode (op, 1);
10590 }
10591 else if (offset > 0)
10592 {
10593 /* Short opcode. */
10594 op = (offset - 4) >> 2;
10595 add_unwind_opcode (op, 1);
10596 }
10597 else if (offset < 0)
10598 {
10599 offset = -offset;
10600 while (offset > 0x100)
10601 {
10602 add_unwind_opcode (0x7f, 1);
10603 offset -= 0x100;
10604 }
10605 op = ((offset - 4) >> 2) | 0x40;
10606 add_unwind_opcode (op, 1);
10607 }
10608 }
10609
10610 /* Finish the list of unwind opcodes for this function. */
10611 static void
10612 finish_unwind_opcodes (void)
10613 {
10614 valueT op;
10615
10616 if (unwind.fp_used)
10617 {
10618 /* Adjust sp as neccessary. */
10619 unwind.pending_offset += unwind.fp_offset - unwind.frame_size;
10620 flush_pending_unwind ();
10621
10622 /* After restoring sp from the frame pointer. */
10623 op = 0x90 | unwind.fp_reg;
10624 add_unwind_opcode (op, 1);
10625 }
10626 else
10627 flush_pending_unwind ();
10628 }
10629
10630
10631 /* Start an exception table entry. If idx is nonzero this is an index table
10632 entry. */
10633
10634 static void
10635 start_unwind_section (const segT text_seg, int idx)
10636 {
10637 const char * text_name;
10638 const char * prefix;
10639 const char * prefix_once;
10640 const char * group_name;
10641 size_t prefix_len;
10642 size_t text_len;
10643 char * sec_name;
10644 size_t sec_name_len;
10645 int type;
10646 int flags;
10647 int linkonce;
10648
10649 if (idx)
10650 {
10651 prefix = ELF_STRING_ARM_unwind;
10652 prefix_once = ELF_STRING_ARM_unwind_once;
10653 type = SHT_ARM_EXIDX;
10654 }
10655 else
10656 {
10657 prefix = ELF_STRING_ARM_unwind_info;
10658 prefix_once = ELF_STRING_ARM_unwind_info_once;
10659 type = SHT_PROGBITS;
10660 }
10661
10662 text_name = segment_name (text_seg);
10663 if (streq (text_name, ".text"))
10664 text_name = "";
10665
10666 if (strncmp (text_name, ".gnu.linkonce.t.",
10667 strlen (".gnu.linkonce.t.")) == 0)
10668 {
10669 prefix = prefix_once;
10670 text_name += strlen (".gnu.linkonce.t.");
10671 }
10672
10673 prefix_len = strlen (prefix);
10674 text_len = strlen (text_name);
10675 sec_name_len = prefix_len + text_len;
10676 sec_name = xmalloc (sec_name_len + 1);
10677 memcpy (sec_name, prefix, prefix_len);
10678 memcpy (sec_name + prefix_len, text_name, text_len);
10679 sec_name[prefix_len + text_len] = '\0';
10680
10681 flags = SHF_ALLOC;
10682 linkonce = 0;
10683 group_name = 0;
10684
10685 /* Handle COMDAT group. */
10686 if (prefix != prefix_once && (text_seg->flags & SEC_LINK_ONCE) != 0)
10687 {
10688 group_name = elf_group_name (text_seg);
10689 if (group_name == NULL)
10690 {
10691 as_bad ("Group section `%s' has no group signature",
10692 segment_name (text_seg));
10693 ignore_rest_of_line ();
10694 return;
10695 }
10696 flags |= SHF_GROUP;
10697 linkonce = 1;
10698 }
10699
10700 obj_elf_change_section (sec_name, type, flags, 0, group_name, linkonce, 0);
10701
10702 /* Set the setion link for index tables. */
10703 if (idx)
10704 elf_linked_to_section (now_seg) = text_seg;
10705 }
10706
10707
10708 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
10709 personality routine data. Returns zero, or the index table value for
10710 and inline entry. */
10711
10712 static valueT
10713 create_unwind_entry (int have_data)
10714 {
10715 int size;
10716 addressT where;
10717 char *ptr;
10718 /* The current word of data. */
10719 valueT data;
10720 /* The number of bytes left in this word. */
10721 int n;
10722
10723 finish_unwind_opcodes ();
10724
10725 /* Remember the current text section. */
10726 unwind.saved_seg = now_seg;
10727 unwind.saved_subseg = now_subseg;
10728
10729 start_unwind_section (now_seg, 0);
10730
10731 if (unwind.personality_routine == NULL)
10732 {
10733 if (unwind.personality_index == -2)
10734 {
10735 if (have_data)
10736 as_bad (_("handerdata in cantunwind frame"));
10737 return 1; /* EXIDX_CANTUNWIND. */
10738 }
10739
10740 /* Use a default personality routine if none is specified. */
10741 if (unwind.personality_index == -1)
10742 {
10743 if (unwind.opcode_count > 3)
10744 unwind.personality_index = 1;
10745 else
10746 unwind.personality_index = 0;
10747 }
10748
10749 /* Space for the personality routine entry. */
10750 if (unwind.personality_index == 0)
10751 {
10752 if (unwind.opcode_count > 3)
10753 as_bad (_("too many unwind opcodes for personality routine 0"));
10754
10755 if (!have_data)
10756 {
10757 /* All the data is inline in the index table. */
10758 data = 0x80;
10759 n = 3;
10760 while (unwind.opcode_count > 0)
10761 {
10762 unwind.opcode_count--;
10763 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
10764 n--;
10765 }
10766
10767 /* Pad with "finish" opcodes. */
10768 while (n--)
10769 data = (data << 8) | 0xb0;
10770
10771 return data;
10772 }
10773 size = 0;
10774 }
10775 else
10776 /* We get two opcodes "free" in the first word. */
10777 size = unwind.opcode_count - 2;
10778 }
10779 else
10780 /* An extra byte is required for the opcode count. */
10781 size = unwind.opcode_count + 1;
10782
10783 size = (size + 3) >> 2;
10784 if (size > 0xff)
10785 as_bad (_("too many unwind opcodes"));
10786
10787 frag_align (2, 0, 0);
10788 record_alignment (now_seg, 2);
10789 unwind.table_entry = expr_build_dot ();
10790
10791 /* Allocate the table entry. */
10792 ptr = frag_more ((size << 2) + 4);
10793 where = frag_now_fix () - ((size << 2) + 4);
10794
10795 switch (unwind.personality_index)
10796 {
10797 case -1:
10798 /* ??? Should this be a PLT generating relocation? */
10799 /* Custom personality routine. */
10800 fix_new (frag_now, where, 4, unwind.personality_routine, 0, 1,
10801 BFD_RELOC_ARM_PREL31);
10802
10803 where += 4;
10804 ptr += 4;
10805
10806 /* Set the first byte to the number of additional words. */
10807 data = size - 1;
10808 n = 3;
10809 break;
10810
10811 /* ABI defined personality routines. */
10812 case 0:
10813 /* Three opcodes bytes are packed into the first word. */
10814 data = 0x80;
10815 n = 3;
10816 break;
10817
10818 case 1:
10819 case 2:
10820 /* The size and first two opcode bytes go in the first word. */
10821 data = ((0x80 + unwind.personality_index) << 8) | size;
10822 n = 2;
10823 break;
10824
10825 default:
10826 /* Should never happen. */
10827 abort ();
10828 }
10829
10830 /* Pack the opcodes into words (MSB first), reversing the list at the same
10831 time. */
10832 while (unwind.opcode_count > 0)
10833 {
10834 if (n == 0)
10835 {
10836 md_number_to_chars (ptr, data, 4);
10837 ptr += 4;
10838 n = 4;
10839 data = 0;
10840 }
10841 unwind.opcode_count--;
10842 n--;
10843 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
10844 }
10845
10846 /* Finish off the last word. */
10847 if (n < 4)
10848 {
10849 /* Pad with "finish" opcodes. */
10850 while (n--)
10851 data = (data << 8) | 0xb0;
10852
10853 md_number_to_chars (ptr, data, 4);
10854 }
10855
10856 if (!have_data)
10857 {
10858 /* Add an empty descriptor if there is no user-specified data. */
10859 ptr = frag_more (4);
10860 md_number_to_chars (ptr, 0, 4);
10861 }
10862
10863 return 0;
10864 }
10865
10866 /* Convert REGNAME to a DWARF-2 register number. */
10867
10868 int
10869 tc_arm_regname_to_dw2regnum (const char *regname)
10870 {
10871 int reg = arm_reg_parse ((char **) &regname, REG_TYPE_RN);
10872
10873 if (reg == FAIL)
10874 return -1;
10875
10876 return reg;
10877 }
10878
10879 /* Initialize the DWARF-2 unwind information for this procedure. */
10880
10881 void
10882 tc_arm_frame_initial_instructions (void)
10883 {
10884 cfi_add_CFA_def_cfa (REG_SP, 0);
10885 }
10886 #endif /* OBJ_ELF */
10887
10888
10889 /* MD interface: Symbol and relocation handling. */
10890
10891 /* Return the address within the segment that a PC-relative fixup is
10892 relative to. For ARM, PC-relative fixups applied to instructions
10893 are generally relative to the location of the fixup plus 8 bytes.
10894 Thumb branches are offset by 4, and Thumb loads relative to PC
10895 require special handling. */
10896
10897 long
10898 md_pcrel_from_section (fixS * fixP, segT seg)
10899 {
10900 offsetT base = fixP->fx_where + fixP->fx_frag->fr_address;
10901
10902 /* If this is pc-relative and we are going to emit a relocation
10903 then we just want to put out any pipeline compensation that the linker
10904 will need. Otherwise we want to use the calculated base. */
10905 if (fixP->fx_pcrel
10906 && ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg)
10907 || arm_force_relocation (fixP)))
10908 base = 0;
10909
10910 switch (fixP->fx_r_type)
10911 {
10912 /* PC relative addressing on the Thumb is slightly odd as the
10913 bottom two bits of the PC are forced to zero for the
10914 calculation. This happens *after* application of the
10915 pipeline offset. However, Thumb adrl already adjusts for
10916 this, so we need not do it again. */
10917 case BFD_RELOC_ARM_THUMB_ADD:
10918 return base & ~3;
10919
10920 case BFD_RELOC_ARM_THUMB_OFFSET:
10921 case BFD_RELOC_ARM_T32_OFFSET_IMM:
10922 case BFD_RELOC_ARM_T32_ADD_PC12:
10923 case BFD_RELOC_ARM_T32_CP_OFF_IMM:
10924 return (base + 4) & ~3;
10925
10926 /* Thumb branches are simply offset by +4. */
10927 case BFD_RELOC_THUMB_PCREL_BRANCH7:
10928 case BFD_RELOC_THUMB_PCREL_BRANCH9:
10929 case BFD_RELOC_THUMB_PCREL_BRANCH12:
10930 case BFD_RELOC_THUMB_PCREL_BRANCH20:
10931 case BFD_RELOC_THUMB_PCREL_BRANCH23:
10932 case BFD_RELOC_THUMB_PCREL_BRANCH25:
10933 case BFD_RELOC_THUMB_PCREL_BLX:
10934 return base + 4;
10935
10936 /* ARM mode branches are offset by +8. However, the Windows CE
10937 loader expects the relocation not to take this into account. */
10938 case BFD_RELOC_ARM_PCREL_BRANCH:
10939 case BFD_RELOC_ARM_PCREL_CALL:
10940 case BFD_RELOC_ARM_PCREL_JUMP:
10941 case BFD_RELOC_ARM_PCREL_BLX:
10942 case BFD_RELOC_ARM_PLT32:
10943 #ifdef TE_WINCE
10944 return base;
10945 #else
10946 return base + 8;
10947 #endif
10948
10949 /* ARM mode loads relative to PC are also offset by +8. Unlike
10950 branches, the Windows CE loader *does* expect the relocation
10951 to take this into account. */
10952 case BFD_RELOC_ARM_OFFSET_IMM:
10953 case BFD_RELOC_ARM_OFFSET_IMM8:
10954 case BFD_RELOC_ARM_HWLITERAL:
10955 case BFD_RELOC_ARM_LITERAL:
10956 case BFD_RELOC_ARM_CP_OFF_IMM:
10957 return base + 8;
10958
10959
10960 /* Other PC-relative relocations are un-offset. */
10961 default:
10962 return base;
10963 }
10964 }
10965
10966 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
10967 Otherwise we have no need to default values of symbols. */
10968
10969 symbolS *
10970 md_undefined_symbol (char * name ATTRIBUTE_UNUSED)
10971 {
10972 #ifdef OBJ_ELF
10973 if (name[0] == '_' && name[1] == 'G'
10974 && streq (name, GLOBAL_OFFSET_TABLE_NAME))
10975 {
10976 if (!GOT_symbol)
10977 {
10978 if (symbol_find (name))
10979 as_bad ("GOT already in the symbol table");
10980
10981 GOT_symbol = symbol_new (name, undefined_section,
10982 (valueT) 0, & zero_address_frag);
10983 }
10984
10985 return GOT_symbol;
10986 }
10987 #endif
10988
10989 return 0;
10990 }
10991
10992 /* Subroutine of md_apply_fix. Check to see if an immediate can be
10993 computed as two separate immediate values, added together. We
10994 already know that this value cannot be computed by just one ARM
10995 instruction. */
10996
10997 static unsigned int
10998 validate_immediate_twopart (unsigned int val,
10999 unsigned int * highpart)
11000 {
11001 unsigned int a;
11002 unsigned int i;
11003
11004 for (i = 0; i < 32; i += 2)
11005 if (((a = rotate_left (val, i)) & 0xff) != 0)
11006 {
11007 if (a & 0xff00)
11008 {
11009 if (a & ~ 0xffff)
11010 continue;
11011 * highpart = (a >> 8) | ((i + 24) << 7);
11012 }
11013 else if (a & 0xff0000)
11014 {
11015 if (a & 0xff000000)
11016 continue;
11017 * highpart = (a >> 16) | ((i + 16) << 7);
11018 }
11019 else
11020 {
11021 assert (a & 0xff000000);
11022 * highpart = (a >> 24) | ((i + 8) << 7);
11023 }
11024
11025 return (a & 0xff) | (i << 7);
11026 }
11027
11028 return FAIL;
11029 }
11030
11031 static int
11032 validate_offset_imm (unsigned int val, int hwse)
11033 {
11034 if ((hwse && val > 255) || val > 4095)
11035 return FAIL;
11036 return val;
11037 }
11038
11039 /* Subroutine of md_apply_fix. Do those data_ops which can take a
11040 negative immediate constant by altering the instruction. A bit of
11041 a hack really.
11042 MOV <-> MVN
11043 AND <-> BIC
11044 ADC <-> SBC
11045 by inverting the second operand, and
11046 ADD <-> SUB
11047 CMP <-> CMN
11048 by negating the second operand. */
11049
11050 static int
11051 negate_data_op (unsigned long * instruction,
11052 unsigned long value)
11053 {
11054 int op, new_inst;
11055 unsigned long negated, inverted;
11056
11057 negated = encode_arm_immediate (-value);
11058 inverted = encode_arm_immediate (~value);
11059
11060 op = (*instruction >> DATA_OP_SHIFT) & 0xf;
11061 switch (op)
11062 {
11063 /* First negates. */
11064 case OPCODE_SUB: /* ADD <-> SUB */
11065 new_inst = OPCODE_ADD;
11066 value = negated;
11067 break;
11068
11069 case OPCODE_ADD:
11070 new_inst = OPCODE_SUB;
11071 value = negated;
11072 break;
11073
11074 case OPCODE_CMP: /* CMP <-> CMN */
11075 new_inst = OPCODE_CMN;
11076 value = negated;
11077 break;
11078
11079 case OPCODE_CMN:
11080 new_inst = OPCODE_CMP;
11081 value = negated;
11082 break;
11083
11084 /* Now Inverted ops. */
11085 case OPCODE_MOV: /* MOV <-> MVN */
11086 new_inst = OPCODE_MVN;
11087 value = inverted;
11088 break;
11089
11090 case OPCODE_MVN:
11091 new_inst = OPCODE_MOV;
11092 value = inverted;
11093 break;
11094
11095 case OPCODE_AND: /* AND <-> BIC */
11096 new_inst = OPCODE_BIC;
11097 value = inverted;
11098 break;
11099
11100 case OPCODE_BIC:
11101 new_inst = OPCODE_AND;
11102 value = inverted;
11103 break;
11104
11105 case OPCODE_ADC: /* ADC <-> SBC */
11106 new_inst = OPCODE_SBC;
11107 value = inverted;
11108 break;
11109
11110 case OPCODE_SBC:
11111 new_inst = OPCODE_ADC;
11112 value = inverted;
11113 break;
11114
11115 /* We cannot do anything. */
11116 default:
11117 return FAIL;
11118 }
11119
11120 if (value == (unsigned) FAIL)
11121 return FAIL;
11122
11123 *instruction &= OPCODE_MASK;
11124 *instruction |= new_inst << DATA_OP_SHIFT;
11125 return value;
11126 }
11127
11128 /* Like negate_data_op, but for Thumb-2. */
11129
11130 static unsigned int
11131 thumb32_negate_data_op (offsetT *instruction, offsetT value)
11132 {
11133 int op, new_inst;
11134 int rd;
11135 offsetT negated, inverted;
11136
11137 negated = encode_thumb32_immediate (-value);
11138 inverted = encode_thumb32_immediate (~value);
11139
11140 rd = (*instruction >> 8) & 0xf;
11141 op = (*instruction >> T2_DATA_OP_SHIFT) & 0xf;
11142 switch (op)
11143 {
11144 /* ADD <-> SUB. Includes CMP <-> CMN. */
11145 case T2_OPCODE_SUB:
11146 new_inst = T2_OPCODE_ADD;
11147 value = negated;
11148 break;
11149
11150 case T2_OPCODE_ADD:
11151 new_inst = T2_OPCODE_SUB;
11152 value = negated;
11153 break;
11154
11155 /* ORR <-> ORN. Includes MOV <-> MVN. */
11156 case T2_OPCODE_ORR:
11157 new_inst = T2_OPCODE_ORN;
11158 value = inverted;
11159 break;
11160
11161 case T2_OPCODE_ORN:
11162 new_inst = T2_OPCODE_ORR;
11163 value = inverted;
11164 break;
11165
11166 /* AND <-> BIC. TST has no inverted equivalent. */
11167 case T2_OPCODE_AND:
11168 new_inst = T2_OPCODE_BIC;
11169 if (rd == 15)
11170 value = FAIL;
11171 else
11172 value = inverted;
11173 break;
11174
11175 case T2_OPCODE_BIC:
11176 new_inst = T2_OPCODE_AND;
11177 value = inverted;
11178 break;
11179
11180 /* ADC <-> SBC */
11181 case T2_OPCODE_ADC:
11182 new_inst = T2_OPCODE_SBC;
11183 value = inverted;
11184 break;
11185
11186 case T2_OPCODE_SBC:
11187 new_inst = T2_OPCODE_ADC;
11188 value = inverted;
11189 break;
11190
11191 /* We cannot do anything. */
11192 default:
11193 return FAIL;
11194 }
11195
11196 if (value == FAIL)
11197 return FAIL;
11198
11199 *instruction &= T2_OPCODE_MASK;
11200 *instruction |= new_inst << T2_DATA_OP_SHIFT;
11201 return value;
11202 }
11203
11204 /* Read a 32-bit thumb instruction from buf. */
11205 static unsigned long
11206 get_thumb32_insn (char * buf)
11207 {
11208 unsigned long insn;
11209 insn = md_chars_to_number (buf, THUMB_SIZE) << 16;
11210 insn |= md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
11211
11212 return insn;
11213 }
11214
11215 void
11216 md_apply_fix (fixS * fixP,
11217 valueT * valP,
11218 segT seg)
11219 {
11220 offsetT value = * valP;
11221 offsetT newval;
11222 unsigned int newimm;
11223 unsigned long temp;
11224 int sign;
11225 char * buf = fixP->fx_where + fixP->fx_frag->fr_literal;
11226
11227 assert (fixP->fx_r_type <= BFD_RELOC_UNUSED);
11228
11229 /* Note whether this will delete the relocation. */
11230 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
11231 fixP->fx_done = 1;
11232
11233 /* On a 64-bit host, silently truncate 'value' to 32 bits for
11234 consistency with the behavior on 32-bit hosts. Remember value
11235 for emit_reloc. */
11236 value &= 0xffffffff;
11237 value ^= 0x80000000;
11238 value -= 0x80000000;
11239
11240 *valP = value;
11241 fixP->fx_addnumber = value;
11242
11243 /* Same treatment for fixP->fx_offset. */
11244 fixP->fx_offset &= 0xffffffff;
11245 fixP->fx_offset ^= 0x80000000;
11246 fixP->fx_offset -= 0x80000000;
11247
11248 switch (fixP->fx_r_type)
11249 {
11250 case BFD_RELOC_NONE:
11251 /* This will need to go in the object file. */
11252 fixP->fx_done = 0;
11253 break;
11254
11255 case BFD_RELOC_ARM_IMMEDIATE:
11256 /* We claim that this fixup has been processed here,
11257 even if in fact we generate an error because we do
11258 not have a reloc for it, so tc_gen_reloc will reject it. */
11259 fixP->fx_done = 1;
11260
11261 if (fixP->fx_addsy
11262 && ! S_IS_DEFINED (fixP->fx_addsy))
11263 {
11264 as_bad_where (fixP->fx_file, fixP->fx_line,
11265 _("undefined symbol %s used as an immediate value"),
11266 S_GET_NAME (fixP->fx_addsy));
11267 break;
11268 }
11269
11270 newimm = encode_arm_immediate (value);
11271 temp = md_chars_to_number (buf, INSN_SIZE);
11272
11273 /* If the instruction will fail, see if we can fix things up by
11274 changing the opcode. */
11275 if (newimm == (unsigned int) FAIL
11276 && (newimm = negate_data_op (&temp, value)) == (unsigned int) FAIL)
11277 {
11278 as_bad_where (fixP->fx_file, fixP->fx_line,
11279 _("invalid constant (%lx) after fixup"),
11280 (unsigned long) value);
11281 break;
11282 }
11283
11284 newimm |= (temp & 0xfffff000);
11285 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
11286 break;
11287
11288 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
11289 {
11290 unsigned int highpart = 0;
11291 unsigned int newinsn = 0xe1a00000; /* nop. */
11292
11293 newimm = encode_arm_immediate (value);
11294 temp = md_chars_to_number (buf, INSN_SIZE);
11295
11296 /* If the instruction will fail, see if we can fix things up by
11297 changing the opcode. */
11298 if (newimm == (unsigned int) FAIL
11299 && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL)
11300 {
11301 /* No ? OK - try using two ADD instructions to generate
11302 the value. */
11303 newimm = validate_immediate_twopart (value, & highpart);
11304
11305 /* Yes - then make sure that the second instruction is
11306 also an add. */
11307 if (newimm != (unsigned int) FAIL)
11308 newinsn = temp;
11309 /* Still No ? Try using a negated value. */
11310 else if ((newimm = validate_immediate_twopart (- value, & highpart)) != (unsigned int) FAIL)
11311 temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT;
11312 /* Otherwise - give up. */
11313 else
11314 {
11315 as_bad_where (fixP->fx_file, fixP->fx_line,
11316 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
11317 (long) value);
11318 break;
11319 }
11320
11321 /* Replace the first operand in the 2nd instruction (which
11322 is the PC) with the destination register. We have
11323 already added in the PC in the first instruction and we
11324 do not want to do it again. */
11325 newinsn &= ~ 0xf0000;
11326 newinsn |= ((newinsn & 0x0f000) << 4);
11327 }
11328
11329 newimm |= (temp & 0xfffff000);
11330 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
11331
11332 highpart |= (newinsn & 0xfffff000);
11333 md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE);
11334 }
11335 break;
11336
11337 case BFD_RELOC_ARM_OFFSET_IMM:
11338 case BFD_RELOC_ARM_LITERAL:
11339 sign = value >= 0;
11340
11341 if (value < 0)
11342 value = - value;
11343
11344 if (validate_offset_imm (value, 0) == FAIL)
11345 {
11346 if (fixP->fx_r_type == BFD_RELOC_ARM_LITERAL)
11347 as_bad_where (fixP->fx_file, fixP->fx_line,
11348 _("invalid literal constant: pool needs to be closer"));
11349 else
11350 as_bad_where (fixP->fx_file, fixP->fx_line,
11351 _("bad immediate value for offset (%ld)"),
11352 (long) value);
11353 break;
11354 }
11355
11356 newval = md_chars_to_number (buf, INSN_SIZE);
11357 newval &= 0xff7ff000;
11358 newval |= value | (sign ? INDEX_UP : 0);
11359 md_number_to_chars (buf, newval, INSN_SIZE);
11360 break;
11361
11362 case BFD_RELOC_ARM_OFFSET_IMM8:
11363 case BFD_RELOC_ARM_HWLITERAL:
11364 sign = value >= 0;
11365
11366 if (value < 0)
11367 value = - value;
11368
11369 if (validate_offset_imm (value, 1) == FAIL)
11370 {
11371 if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL)
11372 as_bad_where (fixP->fx_file, fixP->fx_line,
11373 _("invalid literal constant: pool needs to be closer"));
11374 else
11375 as_bad (_("bad immediate value for half-word offset (%ld)"),
11376 (long) value);
11377 break;
11378 }
11379
11380 newval = md_chars_to_number (buf, INSN_SIZE);
11381 newval &= 0xff7ff0f0;
11382 newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0);
11383 md_number_to_chars (buf, newval, INSN_SIZE);
11384 break;
11385
11386 case BFD_RELOC_ARM_T32_OFFSET_U8:
11387 if (value < 0 || value > 1020 || value % 4 != 0)
11388 as_bad_where (fixP->fx_file, fixP->fx_line,
11389 _("bad immediate value for offset (%ld)"), (long) value);
11390 value /= 4;
11391
11392 newval = md_chars_to_number (buf+2, THUMB_SIZE);
11393 newval |= value;
11394 md_number_to_chars (buf+2, newval, THUMB_SIZE);
11395 break;
11396
11397 case BFD_RELOC_ARM_T32_OFFSET_IMM:
11398 /* This is a complicated relocation used for all varieties of Thumb32
11399 load/store instruction with immediate offset:
11400
11401 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
11402 *4, optional writeback(W)
11403 (doubleword load/store)
11404
11405 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
11406 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
11407 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
11408 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
11409 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
11410
11411 Uppercase letters indicate bits that are already encoded at
11412 this point. Lowercase letters are our problem. For the
11413 second block of instructions, the secondary opcode nybble
11414 (bits 8..11) is present, and bit 23 is zero, even if this is
11415 a PC-relative operation. */
11416 newval = md_chars_to_number (buf, THUMB_SIZE);
11417 newval <<= 16;
11418 newval |= md_chars_to_number (buf+THUMB_SIZE, THUMB_SIZE);
11419
11420 if ((newval & 0xf0000000) == 0xe0000000)
11421 {
11422 /* Doubleword load/store: 8-bit offset, scaled by 4. */
11423 if (value >= 0)
11424 newval |= (1 << 23);
11425 else
11426 value = -value;
11427 if (value % 4 != 0)
11428 {
11429 as_bad_where (fixP->fx_file, fixP->fx_line,
11430 _("offset not a multiple of 4"));
11431 break;
11432 }
11433 value /= 4;
11434 if (value >= 0xff)
11435 {
11436 as_bad_where (fixP->fx_file, fixP->fx_line,
11437 _("offset out of range"));
11438 break;
11439 }
11440 newval &= ~0xff;
11441 }
11442 else if ((newval & 0x000f0000) == 0x000f0000)
11443 {
11444 /* PC-relative, 12-bit offset. */
11445 if (value >= 0)
11446 newval |= (1 << 23);
11447 else
11448 value = -value;
11449 if (value >= 0xfff)
11450 {
11451 as_bad_where (fixP->fx_file, fixP->fx_line,
11452 _("offset out of range"));
11453 break;
11454 }
11455 newval &= ~0xfff;
11456 }
11457 else if ((newval & 0x00000100) == 0x00000100)
11458 {
11459 /* Writeback: 8-bit, +/- offset. */
11460 if (value >= 0)
11461 newval |= (1 << 9);
11462 else
11463 value = -value;
11464 if (value >= 0xff)
11465 {
11466 as_bad_where (fixP->fx_file, fixP->fx_line,
11467 _("offset out of range"));
11468 break;
11469 }
11470 newval &= ~0xff;
11471 }
11472 else if ((newval & 0x00000f00) == 0x00000e00)
11473 {
11474 /* T-instruction: positive 8-bit offset. */
11475 if (value < 0 || value >= 0xff)
11476 {
11477 as_bad_where (fixP->fx_file, fixP->fx_line,
11478 _("offset out of range"));
11479 break;
11480 }
11481 newval &= ~0xff;
11482 newval |= value;
11483 }
11484 else
11485 {
11486 /* Positive 12-bit or negative 8-bit offset. */
11487 int limit;
11488 if (value >= 0)
11489 {
11490 newval |= (1 << 23);
11491 limit = 0xfff;
11492 }
11493 else
11494 {
11495 value = -value;
11496 limit = 0xff;
11497 }
11498 if (value > limit)
11499 {
11500 as_bad_where (fixP->fx_file, fixP->fx_line,
11501 _("offset out of range"));
11502 break;
11503 }
11504 newval &= ~limit;
11505 }
11506
11507 newval |= value;
11508 md_number_to_chars (buf, (newval >> 16) & 0xffff, THUMB_SIZE);
11509 md_number_to_chars (buf + THUMB_SIZE, newval & 0xffff, THUMB_SIZE);
11510 break;
11511
11512 case BFD_RELOC_ARM_SHIFT_IMM:
11513 newval = md_chars_to_number (buf, INSN_SIZE);
11514 if (((unsigned long) value) > 32
11515 || (value == 32
11516 && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60)))
11517 {
11518 as_bad_where (fixP->fx_file, fixP->fx_line,
11519 _("shift expression is too large"));
11520 break;
11521 }
11522
11523 if (value == 0)
11524 /* Shifts of zero must be done as lsl. */
11525 newval &= ~0x60;
11526 else if (value == 32)
11527 value = 0;
11528 newval &= 0xfffff07f;
11529 newval |= (value & 0x1f) << 7;
11530 md_number_to_chars (buf, newval, INSN_SIZE);
11531 break;
11532
11533 case BFD_RELOC_ARM_T32_IMMEDIATE:
11534 case BFD_RELOC_ARM_T32_IMM12:
11535 case BFD_RELOC_ARM_T32_ADD_PC12:
11536 /* We claim that this fixup has been processed here,
11537 even if in fact we generate an error because we do
11538 not have a reloc for it, so tc_gen_reloc will reject it. */
11539 fixP->fx_done = 1;
11540
11541 if (fixP->fx_addsy
11542 && ! S_IS_DEFINED (fixP->fx_addsy))
11543 {
11544 as_bad_where (fixP->fx_file, fixP->fx_line,
11545 _("undefined symbol %s used as an immediate value"),
11546 S_GET_NAME (fixP->fx_addsy));
11547 break;
11548 }
11549
11550 newval = md_chars_to_number (buf, THUMB_SIZE);
11551 newval <<= 16;
11552 newval |= md_chars_to_number (buf+2, THUMB_SIZE);
11553
11554 /* FUTURE: Implement analogue of negate_data_op for T32. */
11555 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE)
11556 {
11557 newimm = encode_thumb32_immediate (value);
11558 if (newimm == (unsigned int) FAIL)
11559 newimm = thumb32_negate_data_op (&newval, value);
11560 }
11561 else
11562 {
11563 /* 12 bit immediate for addw/subw. */
11564 if (value < 0)
11565 {
11566 value = -value;
11567 newval ^= 0x00a00000;
11568 }
11569 if (value > 0xfff)
11570 newimm = (unsigned int) FAIL;
11571 else
11572 newimm = value;
11573 }
11574
11575 if (newimm == (unsigned int)FAIL)
11576 {
11577 as_bad_where (fixP->fx_file, fixP->fx_line,
11578 _("invalid constant (%lx) after fixup"),
11579 (unsigned long) value);
11580 break;
11581 }
11582
11583 newval |= (newimm & 0x800) << 15;
11584 newval |= (newimm & 0x700) << 4;
11585 newval |= (newimm & 0x0ff);
11586
11587 md_number_to_chars (buf, (valueT) ((newval >> 16) & 0xffff), THUMB_SIZE);
11588 md_number_to_chars (buf+2, (valueT) (newval & 0xffff), THUMB_SIZE);
11589 break;
11590
11591 case BFD_RELOC_ARM_SMC:
11592 if (((unsigned long) value) > 0xffff)
11593 as_bad_where (fixP->fx_file, fixP->fx_line,
11594 _("invalid smc expression"));
11595 newval = md_chars_to_number (buf, INSN_SIZE);
11596 newval |= (value & 0xf) | ((value & 0xfff0) << 4);
11597 md_number_to_chars (buf, newval, INSN_SIZE);
11598 break;
11599
11600 case BFD_RELOC_ARM_SWI:
11601 if (fixP->tc_fix_data != 0)
11602 {
11603 if (((unsigned long) value) > 0xff)
11604 as_bad_where (fixP->fx_file, fixP->fx_line,
11605 _("invalid swi expression"));
11606 newval = md_chars_to_number (buf, THUMB_SIZE);
11607 newval |= value;
11608 md_number_to_chars (buf, newval, THUMB_SIZE);
11609 }
11610 else
11611 {
11612 if (((unsigned long) value) > 0x00ffffff)
11613 as_bad_where (fixP->fx_file, fixP->fx_line,
11614 _("invalid swi expression"));
11615 newval = md_chars_to_number (buf, INSN_SIZE);
11616 newval |= value;
11617 md_number_to_chars (buf, newval, INSN_SIZE);
11618 }
11619 break;
11620
11621 case BFD_RELOC_ARM_MULTI:
11622 if (((unsigned long) value) > 0xffff)
11623 as_bad_where (fixP->fx_file, fixP->fx_line,
11624 _("invalid expression in load/store multiple"));
11625 newval = value | md_chars_to_number (buf, INSN_SIZE);
11626 md_number_to_chars (buf, newval, INSN_SIZE);
11627 break;
11628
11629 #ifdef OBJ_ELF
11630 case BFD_RELOC_ARM_PCREL_CALL:
11631 newval = md_chars_to_number (buf, INSN_SIZE);
11632 if ((newval & 0xf0000000) == 0xf0000000)
11633 temp = 1;
11634 else
11635 temp = 3;
11636 goto arm_branch_common;
11637
11638 case BFD_RELOC_ARM_PCREL_JUMP:
11639 case BFD_RELOC_ARM_PLT32:
11640 #endif
11641 case BFD_RELOC_ARM_PCREL_BRANCH:
11642 temp = 3;
11643 goto arm_branch_common;
11644
11645 case BFD_RELOC_ARM_PCREL_BLX:
11646 temp = 1;
11647 arm_branch_common:
11648 /* We are going to store value (shifted right by two) in the
11649 instruction, in a 24 bit, signed field. Bits 26 through 32 either
11650 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
11651 also be be clear. */
11652 if (value & temp)
11653 as_bad_where (fixP->fx_file, fixP->fx_line,
11654 _("misaligned branch destination"));
11655 if ((value & (offsetT)0xfe000000) != (offsetT)0
11656 && (value & (offsetT)0xfe000000) != (offsetT)0xfe000000)
11657 as_bad_where (fixP->fx_file, fixP->fx_line,
11658 _("branch out of range"));
11659
11660 if (fixP->fx_done || !seg->use_rela_p)
11661 {
11662 newval = md_chars_to_number (buf, INSN_SIZE);
11663 newval |= (value >> 2) & 0x00ffffff;
11664 md_number_to_chars (buf, newval, INSN_SIZE);
11665 }
11666 break;
11667
11668 case BFD_RELOC_THUMB_PCREL_BRANCH7: /* CZB */
11669 /* CZB can only branch forward. */
11670 if (value & ~0x7e)
11671 as_bad_where (fixP->fx_file, fixP->fx_line,
11672 _("branch out of range"));
11673
11674 if (fixP->fx_done || !seg->use_rela_p)
11675 {
11676 newval = md_chars_to_number (buf, THUMB_SIZE);
11677 newval |= ((value & 0x2e) << 2) | ((value & 0x40) << 3);
11678 md_number_to_chars (buf, newval, THUMB_SIZE);
11679 }
11680 break;
11681
11682 case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */
11683 if ((value & ~0xff) && ((value & ~0xff) != ~0xff))
11684 as_bad_where (fixP->fx_file, fixP->fx_line,
11685 _("branch out of range"));
11686
11687 if (fixP->fx_done || !seg->use_rela_p)
11688 {
11689 newval = md_chars_to_number (buf, THUMB_SIZE);
11690 newval |= (value & 0x1ff) >> 1;
11691 md_number_to_chars (buf, newval, THUMB_SIZE);
11692 }
11693 break;
11694
11695 case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch. */
11696 if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff))
11697 as_bad_where (fixP->fx_file, fixP->fx_line,
11698 _("branch out of range"));
11699
11700 if (fixP->fx_done || !seg->use_rela_p)
11701 {
11702 newval = md_chars_to_number (buf, THUMB_SIZE);
11703 newval |= (value & 0xfff) >> 1;
11704 md_number_to_chars (buf, newval, THUMB_SIZE);
11705 }
11706 break;
11707
11708 case BFD_RELOC_THUMB_PCREL_BRANCH20:
11709 if ((value & ~0x1fffff) && ((value & ~0x1fffff) != ~0x1fffff))
11710 as_bad_where (fixP->fx_file, fixP->fx_line,
11711 _("conditional branch out of range"));
11712
11713 if (fixP->fx_done || !seg->use_rela_p)
11714 {
11715 offsetT newval2;
11716 addressT S, J1, J2, lo, hi;
11717
11718 S = (value & 0x00100000) >> 20;
11719 J2 = (value & 0x00080000) >> 19;
11720 J1 = (value & 0x00040000) >> 18;
11721 hi = (value & 0x0003f000) >> 12;
11722 lo = (value & 0x00000ffe) >> 1;
11723
11724 newval = md_chars_to_number (buf, THUMB_SIZE);
11725 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
11726 newval |= (S << 10) | hi;
11727 newval2 |= (J1 << 13) | (J2 << 11) | lo;
11728 md_number_to_chars (buf, newval, THUMB_SIZE);
11729 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
11730 }
11731 break;
11732
11733 case BFD_RELOC_THUMB_PCREL_BLX:
11734 case BFD_RELOC_THUMB_PCREL_BRANCH23:
11735 if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff))
11736 as_bad_where (fixP->fx_file, fixP->fx_line,
11737 _("branch out of range"));
11738
11739 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
11740 /* For a BLX instruction, make sure that the relocation is rounded up
11741 to a word boundary. This follows the semantics of the instruction
11742 which specifies that bit 1 of the target address will come from bit
11743 1 of the base address. */
11744 value = (value + 1) & ~ 1;
11745
11746 if (fixP->fx_done || !seg->use_rela_p)
11747 {
11748 offsetT newval2;
11749
11750 newval = md_chars_to_number (buf, THUMB_SIZE);
11751 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
11752 newval |= (value & 0x7fffff) >> 12;
11753 newval2 |= (value & 0xfff) >> 1;
11754 md_number_to_chars (buf, newval, THUMB_SIZE);
11755 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
11756 }
11757 break;
11758
11759 case BFD_RELOC_THUMB_PCREL_BRANCH25:
11760 if ((value & ~0x1ffffff) && ((value & ~0x1ffffff) != ~0x1ffffff))
11761 as_bad_where (fixP->fx_file, fixP->fx_line,
11762 _("branch out of range"));
11763
11764 if (fixP->fx_done || !seg->use_rela_p)
11765 {
11766 offsetT newval2;
11767 addressT S, I1, I2, lo, hi;
11768
11769 S = (value & 0x01000000) >> 24;
11770 I1 = (value & 0x00800000) >> 23;
11771 I2 = (value & 0x00400000) >> 22;
11772 hi = (value & 0x003ff000) >> 12;
11773 lo = (value & 0x00000ffe) >> 1;
11774
11775 I1 = !(I1 ^ S);
11776 I2 = !(I2 ^ S);
11777
11778 newval = md_chars_to_number (buf, THUMB_SIZE);
11779 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
11780 newval |= (S << 10) | hi;
11781 newval2 |= (I1 << 13) | (I2 << 11) | lo;
11782 md_number_to_chars (buf, newval, THUMB_SIZE);
11783 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
11784 }
11785 break;
11786
11787 case BFD_RELOC_8:
11788 if (fixP->fx_done || !seg->use_rela_p)
11789 md_number_to_chars (buf, value, 1);
11790 break;
11791
11792 case BFD_RELOC_16:
11793 if (fixP->fx_done || !seg->use_rela_p)
11794 md_number_to_chars (buf, value, 2);
11795 break;
11796
11797 #ifdef OBJ_ELF
11798 case BFD_RELOC_ARM_TLS_GD32:
11799 case BFD_RELOC_ARM_TLS_LE32:
11800 case BFD_RELOC_ARM_TLS_IE32:
11801 case BFD_RELOC_ARM_TLS_LDM32:
11802 case BFD_RELOC_ARM_TLS_LDO32:
11803 S_SET_THREAD_LOCAL (fixP->fx_addsy);
11804 /* fall through */
11805
11806 case BFD_RELOC_ARM_GOT32:
11807 case BFD_RELOC_ARM_GOTOFF:
11808 case BFD_RELOC_ARM_TARGET2:
11809 if (fixP->fx_done || !seg->use_rela_p)
11810 md_number_to_chars (buf, 0, 4);
11811 break;
11812 #endif
11813
11814 case BFD_RELOC_RVA:
11815 case BFD_RELOC_32:
11816 case BFD_RELOC_ARM_TARGET1:
11817 case BFD_RELOC_ARM_ROSEGREL32:
11818 case BFD_RELOC_ARM_SBREL32:
11819 case BFD_RELOC_32_PCREL:
11820 if (fixP->fx_done || !seg->use_rela_p)
11821 md_number_to_chars (buf, value, 4);
11822 break;
11823
11824 #ifdef OBJ_ELF
11825 case BFD_RELOC_ARM_PREL31:
11826 if (fixP->fx_done || !seg->use_rela_p)
11827 {
11828 newval = md_chars_to_number (buf, 4) & 0x80000000;
11829 if ((value ^ (value >> 1)) & 0x40000000)
11830 {
11831 as_bad_where (fixP->fx_file, fixP->fx_line,
11832 _("rel31 relocation overflow"));
11833 }
11834 newval |= value & 0x7fffffff;
11835 md_number_to_chars (buf, newval, 4);
11836 }
11837 break;
11838 #endif
11839
11840 case BFD_RELOC_ARM_CP_OFF_IMM:
11841 case BFD_RELOC_ARM_T32_CP_OFF_IMM:
11842 if (value < -1023 || value > 1023 || (value & 3))
11843 as_bad_where (fixP->fx_file, fixP->fx_line,
11844 _("co-processor offset out of range"));
11845 cp_off_common:
11846 sign = value >= 0;
11847 if (value < 0)
11848 value = -value;
11849 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
11850 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
11851 newval = md_chars_to_number (buf, INSN_SIZE);
11852 else
11853 newval = get_thumb32_insn (buf);
11854 newval &= 0xff7fff00;
11855 newval |= (value >> 2) | (sign ? INDEX_UP : 0);
11856 if (value == 0)
11857 newval &= ~WRITE_BACK;
11858 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
11859 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
11860 md_number_to_chars (buf, newval, INSN_SIZE);
11861 else
11862 put_thumb32_insn (buf, newval);
11863 break;
11864
11865 case BFD_RELOC_ARM_CP_OFF_IMM_S2:
11866 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2:
11867 if (value < -255 || value > 255)
11868 as_bad_where (fixP->fx_file, fixP->fx_line,
11869 _("co-processor offset out of range"));
11870 goto cp_off_common;
11871
11872 case BFD_RELOC_ARM_THUMB_OFFSET:
11873 newval = md_chars_to_number (buf, THUMB_SIZE);
11874 /* Exactly what ranges, and where the offset is inserted depends
11875 on the type of instruction, we can establish this from the
11876 top 4 bits. */
11877 switch (newval >> 12)
11878 {
11879 case 4: /* PC load. */
11880 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
11881 forced to zero for these loads; md_pcrel_from has already
11882 compensated for this. */
11883 if (value & 3)
11884 as_bad_where (fixP->fx_file, fixP->fx_line,
11885 _("invalid offset, target not word aligned (0x%08lX)"),
11886 (((unsigned long) fixP->fx_frag->fr_address
11887 + (unsigned long) fixP->fx_where) & ~3)
11888 + (unsigned long) value);
11889
11890 if (value & ~0x3fc)
11891 as_bad_where (fixP->fx_file, fixP->fx_line,
11892 _("invalid offset, value too big (0x%08lX)"),
11893 (long) value);
11894
11895 newval |= value >> 2;
11896 break;
11897
11898 case 9: /* SP load/store. */
11899 if (value & ~0x3fc)
11900 as_bad_where (fixP->fx_file, fixP->fx_line,
11901 _("invalid offset, value too big (0x%08lX)"),
11902 (long) value);
11903 newval |= value >> 2;
11904 break;
11905
11906 case 6: /* Word load/store. */
11907 if (value & ~0x7c)
11908 as_bad_where (fixP->fx_file, fixP->fx_line,
11909 _("invalid offset, value too big (0x%08lX)"),
11910 (long) value);
11911 newval |= value << 4; /* 6 - 2. */
11912 break;
11913
11914 case 7: /* Byte load/store. */
11915 if (value & ~0x1f)
11916 as_bad_where (fixP->fx_file, fixP->fx_line,
11917 _("invalid offset, value too big (0x%08lX)"),
11918 (long) value);
11919 newval |= value << 6;
11920 break;
11921
11922 case 8: /* Halfword load/store. */
11923 if (value & ~0x3e)
11924 as_bad_where (fixP->fx_file, fixP->fx_line,
11925 _("invalid offset, value too big (0x%08lX)"),
11926 (long) value);
11927 newval |= value << 5; /* 6 - 1. */
11928 break;
11929
11930 default:
11931 as_bad_where (fixP->fx_file, fixP->fx_line,
11932 "Unable to process relocation for thumb opcode: %lx",
11933 (unsigned long) newval);
11934 break;
11935 }
11936 md_number_to_chars (buf, newval, THUMB_SIZE);
11937 break;
11938
11939 case BFD_RELOC_ARM_THUMB_ADD:
11940 /* This is a complicated relocation, since we use it for all of
11941 the following immediate relocations:
11942
11943 3bit ADD/SUB
11944 8bit ADD/SUB
11945 9bit ADD/SUB SP word-aligned
11946 10bit ADD PC/SP word-aligned
11947
11948 The type of instruction being processed is encoded in the
11949 instruction field:
11950
11951 0x8000 SUB
11952 0x00F0 Rd
11953 0x000F Rs
11954 */
11955 newval = md_chars_to_number (buf, THUMB_SIZE);
11956 {
11957 int rd = (newval >> 4) & 0xf;
11958 int rs = newval & 0xf;
11959 int subtract = !!(newval & 0x8000);
11960
11961 /* Check for HI regs, only very restricted cases allowed:
11962 Adjusting SP, and using PC or SP to get an address. */
11963 if ((rd > 7 && (rd != REG_SP || rs != REG_SP))
11964 || (rs > 7 && rs != REG_SP && rs != REG_PC))
11965 as_bad_where (fixP->fx_file, fixP->fx_line,
11966 _("invalid Hi register with immediate"));
11967
11968 /* If value is negative, choose the opposite instruction. */
11969 if (value < 0)
11970 {
11971 value = -value;
11972 subtract = !subtract;
11973 if (value < 0)
11974 as_bad_where (fixP->fx_file, fixP->fx_line,
11975 _("immediate value out of range"));
11976 }
11977
11978 if (rd == REG_SP)
11979 {
11980 if (value & ~0x1fc)
11981 as_bad_where (fixP->fx_file, fixP->fx_line,
11982 _("invalid immediate for stack address calculation"));
11983 newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST;
11984 newval |= value >> 2;
11985 }
11986 else if (rs == REG_PC || rs == REG_SP)
11987 {
11988 if (subtract || value & ~0x3fc)
11989 as_bad_where (fixP->fx_file, fixP->fx_line,
11990 _("invalid immediate for address calculation (value = 0x%08lX)"),
11991 (unsigned long) value);
11992 newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP);
11993 newval |= rd << 8;
11994 newval |= value >> 2;
11995 }
11996 else if (rs == rd)
11997 {
11998 if (value & ~0xff)
11999 as_bad_where (fixP->fx_file, fixP->fx_line,
12000 _("immediate value out of range"));
12001 newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8;
12002 newval |= (rd << 8) | value;
12003 }
12004 else
12005 {
12006 if (value & ~0x7)
12007 as_bad_where (fixP->fx_file, fixP->fx_line,
12008 _("immediate value out of range"));
12009 newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3;
12010 newval |= rd | (rs << 3) | (value << 6);
12011 }
12012 }
12013 md_number_to_chars (buf, newval, THUMB_SIZE);
12014 break;
12015
12016 case BFD_RELOC_ARM_THUMB_IMM:
12017 newval = md_chars_to_number (buf, THUMB_SIZE);
12018 if (value < 0 || value > 255)
12019 as_bad_where (fixP->fx_file, fixP->fx_line,
12020 _("invalid immediate: %ld is too large"),
12021 (long) value);
12022 newval |= value;
12023 md_number_to_chars (buf, newval, THUMB_SIZE);
12024 break;
12025
12026 case BFD_RELOC_ARM_THUMB_SHIFT:
12027 /* 5bit shift value (0..32). LSL cannot take 32. */
12028 newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf83f;
12029 temp = newval & 0xf800;
12030 if (value < 0 || value > 32 || (value == 32 && temp == T_OPCODE_LSL_I))
12031 as_bad_where (fixP->fx_file, fixP->fx_line,
12032 _("invalid shift value: %ld"), (long) value);
12033 /* Shifts of zero must be encoded as LSL. */
12034 if (value == 0)
12035 newval = (newval & 0x003f) | T_OPCODE_LSL_I;
12036 /* Shifts of 32 are encoded as zero. */
12037 else if (value == 32)
12038 value = 0;
12039 newval |= value << 6;
12040 md_number_to_chars (buf, newval, THUMB_SIZE);
12041 break;
12042
12043 case BFD_RELOC_VTABLE_INHERIT:
12044 case BFD_RELOC_VTABLE_ENTRY:
12045 fixP->fx_done = 0;
12046 return;
12047
12048 case BFD_RELOC_UNUSED:
12049 default:
12050 as_bad_where (fixP->fx_file, fixP->fx_line,
12051 _("bad relocation fixup type (%d)"), fixP->fx_r_type);
12052 }
12053 }
12054
12055 /* Translate internal representation of relocation info to BFD target
12056 format. */
12057
12058 arelent *
12059 tc_gen_reloc (asection * section ATTRIBUTE_UNUSED,
12060 fixS * fixp)
12061 {
12062 arelent * reloc;
12063 bfd_reloc_code_real_type code;
12064
12065 reloc = xmalloc (sizeof (arelent));
12066
12067 reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
12068 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
12069 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
12070
12071 if (fixp->fx_pcrel)
12072 fixp->fx_offset = reloc->address;
12073 reloc->addend = fixp->fx_offset;
12074
12075 switch (fixp->fx_r_type)
12076 {
12077 case BFD_RELOC_8:
12078 if (fixp->fx_pcrel)
12079 {
12080 code = BFD_RELOC_8_PCREL;
12081 break;
12082 }
12083
12084 case BFD_RELOC_16:
12085 if (fixp->fx_pcrel)
12086 {
12087 code = BFD_RELOC_16_PCREL;
12088 break;
12089 }
12090
12091 case BFD_RELOC_32:
12092 if (fixp->fx_pcrel)
12093 {
12094 code = BFD_RELOC_32_PCREL;
12095 break;
12096 }
12097
12098 case BFD_RELOC_NONE:
12099 case BFD_RELOC_ARM_PCREL_BRANCH:
12100 case BFD_RELOC_ARM_PCREL_BLX:
12101 case BFD_RELOC_RVA:
12102 case BFD_RELOC_THUMB_PCREL_BRANCH7:
12103 case BFD_RELOC_THUMB_PCREL_BRANCH9:
12104 case BFD_RELOC_THUMB_PCREL_BRANCH12:
12105 case BFD_RELOC_THUMB_PCREL_BRANCH20:
12106 case BFD_RELOC_THUMB_PCREL_BRANCH23:
12107 case BFD_RELOC_THUMB_PCREL_BRANCH25:
12108 case BFD_RELOC_THUMB_PCREL_BLX:
12109 case BFD_RELOC_VTABLE_ENTRY:
12110 case BFD_RELOC_VTABLE_INHERIT:
12111 code = fixp->fx_r_type;
12112 break;
12113
12114 case BFD_RELOC_ARM_LITERAL:
12115 case BFD_RELOC_ARM_HWLITERAL:
12116 /* If this is called then the a literal has
12117 been referenced across a section boundary. */
12118 as_bad_where (fixp->fx_file, fixp->fx_line,
12119 _("literal referenced across section boundary"));
12120 return NULL;
12121
12122 #ifdef OBJ_ELF
12123 case BFD_RELOC_ARM_GOT32:
12124 case BFD_RELOC_ARM_GOTOFF:
12125 case BFD_RELOC_ARM_PLT32:
12126 case BFD_RELOC_ARM_TARGET1:
12127 case BFD_RELOC_ARM_ROSEGREL32:
12128 case BFD_RELOC_ARM_SBREL32:
12129 case BFD_RELOC_ARM_PREL31:
12130 case BFD_RELOC_ARM_TARGET2:
12131 case BFD_RELOC_ARM_TLS_LE32:
12132 case BFD_RELOC_ARM_TLS_LDO32:
12133 case BFD_RELOC_ARM_PCREL_CALL:
12134 case BFD_RELOC_ARM_PCREL_JUMP:
12135 code = fixp->fx_r_type;
12136 break;
12137
12138 case BFD_RELOC_ARM_TLS_GD32:
12139 case BFD_RELOC_ARM_TLS_IE32:
12140 case BFD_RELOC_ARM_TLS_LDM32:
12141 /* BFD will include the symbol's address in the addend.
12142 But we don't want that, so subtract it out again here. */
12143 if (!S_IS_COMMON (fixp->fx_addsy))
12144 reloc->addend -= (*reloc->sym_ptr_ptr)->value;
12145 code = fixp->fx_r_type;
12146 break;
12147 #endif
12148
12149 case BFD_RELOC_ARM_IMMEDIATE:
12150 as_bad_where (fixp->fx_file, fixp->fx_line,
12151 _("internal relocation (type: IMMEDIATE) not fixed up"));
12152 return NULL;
12153
12154 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
12155 as_bad_where (fixp->fx_file, fixp->fx_line,
12156 _("ADRL used for a symbol not defined in the same file"));
12157 return NULL;
12158
12159 case BFD_RELOC_ARM_OFFSET_IMM:
12160 if (fixp->fx_addsy != NULL
12161 && !S_IS_DEFINED (fixp->fx_addsy)
12162 && S_IS_LOCAL (fixp->fx_addsy))
12163 {
12164 as_bad_where (fixp->fx_file, fixp->fx_line,
12165 _("undefined local label `%s'"),
12166 S_GET_NAME (fixp->fx_addsy));
12167 return NULL;
12168 }
12169
12170 as_bad_where (fixp->fx_file, fixp->fx_line,
12171 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
12172 return NULL;
12173
12174 default:
12175 {
12176 char * type;
12177
12178 switch (fixp->fx_r_type)
12179 {
12180 case BFD_RELOC_NONE: type = "NONE"; break;
12181 case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break;
12182 case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break;
12183 case BFD_RELOC_ARM_SMC: type = "SMC"; break;
12184 case BFD_RELOC_ARM_SWI: type = "SWI"; break;
12185 case BFD_RELOC_ARM_MULTI: type = "MULTI"; break;
12186 case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break;
12187 case BFD_RELOC_ARM_T32_CP_OFF_IMM: type = "T32_CP_OFF_IMM"; break;
12188 case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break;
12189 case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break;
12190 case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break;
12191 case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break;
12192 default: type = _("<unknown>"); break;
12193 }
12194 as_bad_where (fixp->fx_file, fixp->fx_line,
12195 _("cannot represent %s relocation in this object file format"),
12196 type);
12197 return NULL;
12198 }
12199 }
12200
12201 #ifdef OBJ_ELF
12202 if ((code == BFD_RELOC_32_PCREL || code == BFD_RELOC_32)
12203 && GOT_symbol
12204 && fixp->fx_addsy == GOT_symbol)
12205 {
12206 code = BFD_RELOC_ARM_GOTPC;
12207 reloc->addend = fixp->fx_offset = reloc->address;
12208 }
12209 #endif
12210
12211 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
12212
12213 if (reloc->howto == NULL)
12214 {
12215 as_bad_where (fixp->fx_file, fixp->fx_line,
12216 _("cannot represent %s relocation in this object file format"),
12217 bfd_get_reloc_code_name (code));
12218 return NULL;
12219 }
12220
12221 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
12222 vtable entry to be used in the relocation's section offset. */
12223 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
12224 reloc->address = fixp->fx_offset;
12225
12226 return reloc;
12227 }
12228
12229 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
12230
12231 void
12232 cons_fix_new_arm (fragS * frag,
12233 int where,
12234 int size,
12235 expressionS * exp)
12236 {
12237 bfd_reloc_code_real_type type;
12238 int pcrel = 0;
12239
12240 /* Pick a reloc.
12241 FIXME: @@ Should look at CPU word size. */
12242 switch (size)
12243 {
12244 case 1:
12245 type = BFD_RELOC_8;
12246 break;
12247 case 2:
12248 type = BFD_RELOC_16;
12249 break;
12250 case 4:
12251 default:
12252 type = BFD_RELOC_32;
12253 break;
12254 case 8:
12255 type = BFD_RELOC_64;
12256 break;
12257 }
12258
12259 fix_new_exp (frag, where, (int) size, exp, pcrel, type);
12260 }
12261
12262 #if defined OBJ_COFF || defined OBJ_ELF
12263 void
12264 arm_validate_fix (fixS * fixP)
12265 {
12266 /* If the destination of the branch is a defined symbol which does not have
12267 the THUMB_FUNC attribute, then we must be calling a function which has
12268 the (interfacearm) attribute. We look for the Thumb entry point to that
12269 function and change the branch to refer to that function instead. */
12270 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23
12271 && fixP->fx_addsy != NULL
12272 && S_IS_DEFINED (fixP->fx_addsy)
12273 && ! THUMB_IS_FUNC (fixP->fx_addsy))
12274 {
12275 fixP->fx_addsy = find_real_start (fixP->fx_addsy);
12276 }
12277 }
12278 #endif
12279
12280 int
12281 arm_force_relocation (struct fix * fixp)
12282 {
12283 #if defined (OBJ_COFF) && defined (TE_PE)
12284 if (fixp->fx_r_type == BFD_RELOC_RVA)
12285 return 1;
12286 #endif
12287
12288 /* Resolve these relocations even if the symbol is extern or weak. */
12289 if (fixp->fx_r_type == BFD_RELOC_ARM_IMMEDIATE
12290 || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM
12291 || fixp->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE
12292 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
12293 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMM12
12294 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_PC12)
12295 return 0;
12296
12297 return generic_force_reloc (fixp);
12298 }
12299
12300 #ifdef OBJ_COFF
12301 /* This is a little hack to help the gas/arm/adrl.s test. It prevents
12302 local labels from being added to the output symbol table when they
12303 are used with the ADRL pseudo op. The ADRL relocation should always
12304 be resolved before the binbary is emitted, so it is safe to say that
12305 it is adjustable. */
12306
12307 bfd_boolean
12308 arm_fix_adjustable (fixS * fixP)
12309 {
12310 if (fixP->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE)
12311 return 1;
12312 return 0;
12313 }
12314 #endif
12315
12316 #ifdef OBJ_ELF
12317 /* Relocations against Thumb function names must be left unadjusted,
12318 so that the linker can use this information to correctly set the
12319 bottom bit of their addresses. The MIPS version of this function
12320 also prevents relocations that are mips-16 specific, but I do not
12321 know why it does this.
12322
12323 FIXME:
12324 There is one other problem that ought to be addressed here, but
12325 which currently is not: Taking the address of a label (rather
12326 than a function) and then later jumping to that address. Such
12327 addresses also ought to have their bottom bit set (assuming that
12328 they reside in Thumb code), but at the moment they will not. */
12329
12330 bfd_boolean
12331 arm_fix_adjustable (fixS * fixP)
12332 {
12333 if (fixP->fx_addsy == NULL)
12334 return 1;
12335
12336 if (THUMB_IS_FUNC (fixP->fx_addsy)
12337 && fixP->fx_subsy == NULL)
12338 return 0;
12339
12340 /* We need the symbol name for the VTABLE entries. */
12341 if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
12342 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
12343 return 0;
12344
12345 /* Don't allow symbols to be discarded on GOT related relocs. */
12346 if (fixP->fx_r_type == BFD_RELOC_ARM_PLT32
12347 || fixP->fx_r_type == BFD_RELOC_ARM_GOT32
12348 || fixP->fx_r_type == BFD_RELOC_ARM_GOTOFF
12349 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32
12350 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LE32
12351 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32
12352 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32
12353 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDO32
12354 || fixP->fx_r_type == BFD_RELOC_ARM_TARGET2)
12355 return 0;
12356
12357 return 1;
12358 }
12359
12360 const char *
12361 elf32_arm_target_format (void)
12362 {
12363 #ifdef TE_SYMBIAN
12364 return (target_big_endian
12365 ? "elf32-bigarm-symbian"
12366 : "elf32-littlearm-symbian");
12367 #elif defined (TE_VXWORKS)
12368 return (target_big_endian
12369 ? "elf32-bigarm-vxworks"
12370 : "elf32-littlearm-vxworks");
12371 #else
12372 if (target_big_endian)
12373 return "elf32-bigarm";
12374 else
12375 return "elf32-littlearm";
12376 #endif
12377 }
12378
12379 void
12380 armelf_frob_symbol (symbolS * symp,
12381 int * puntp)
12382 {
12383 elf_frob_symbol (symp, puntp);
12384 }
12385 #endif
12386
12387 /* MD interface: Finalization. */
12388
12389 /* A good place to do this, although this was probably not intended
12390 for this kind of use. We need to dump the literal pool before
12391 references are made to a null symbol pointer. */
12392
12393 void
12394 arm_cleanup (void)
12395 {
12396 literal_pool * pool;
12397
12398 for (pool = list_of_pools; pool; pool = pool->next)
12399 {
12400 /* Put it at the end of the relevent section. */
12401 subseg_set (pool->section, pool->sub_section);
12402 #ifdef OBJ_ELF
12403 arm_elf_change_section ();
12404 #endif
12405 s_ltorg (0);
12406 }
12407 }
12408
12409 /* Adjust the symbol table. This marks Thumb symbols as distinct from
12410 ARM ones. */
12411
12412 void
12413 arm_adjust_symtab (void)
12414 {
12415 #ifdef OBJ_COFF
12416 symbolS * sym;
12417
12418 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
12419 {
12420 if (ARM_IS_THUMB (sym))
12421 {
12422 if (THUMB_IS_FUNC (sym))
12423 {
12424 /* Mark the symbol as a Thumb function. */
12425 if ( S_GET_STORAGE_CLASS (sym) == C_STAT
12426 || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */
12427 S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC);
12428
12429 else if (S_GET_STORAGE_CLASS (sym) == C_EXT)
12430 S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC);
12431 else
12432 as_bad (_("%s: unexpected function type: %d"),
12433 S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym));
12434 }
12435 else switch (S_GET_STORAGE_CLASS (sym))
12436 {
12437 case C_EXT:
12438 S_SET_STORAGE_CLASS (sym, C_THUMBEXT);
12439 break;
12440 case C_STAT:
12441 S_SET_STORAGE_CLASS (sym, C_THUMBSTAT);
12442 break;
12443 case C_LABEL:
12444 S_SET_STORAGE_CLASS (sym, C_THUMBLABEL);
12445 break;
12446 default:
12447 /* Do nothing. */
12448 break;
12449 }
12450 }
12451
12452 if (ARM_IS_INTERWORK (sym))
12453 coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF;
12454 }
12455 #endif
12456 #ifdef OBJ_ELF
12457 symbolS * sym;
12458 char bind;
12459
12460 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
12461 {
12462 if (ARM_IS_THUMB (sym))
12463 {
12464 elf_symbol_type * elf_sym;
12465
12466 elf_sym = elf_symbol (symbol_get_bfdsym (sym));
12467 bind = ELF_ST_BIND (elf_sym->internal_elf_sym.st_info);
12468
12469 if (! bfd_is_arm_mapping_symbol_name (elf_sym->symbol.name))
12470 {
12471 /* If it's a .thumb_func, declare it as so,
12472 otherwise tag label as .code 16. */
12473 if (THUMB_IS_FUNC (sym))
12474 elf_sym->internal_elf_sym.st_info =
12475 ELF_ST_INFO (bind, STT_ARM_TFUNC);
12476 else
12477 elf_sym->internal_elf_sym.st_info =
12478 ELF_ST_INFO (bind, STT_ARM_16BIT);
12479 }
12480 }
12481 }
12482 #endif
12483 }
12484
12485 /* MD interface: Initialization. */
12486
12487 static void
12488 set_constant_flonums (void)
12489 {
12490 int i;
12491
12492 for (i = 0; i < NUM_FLOAT_VALS; i++)
12493 if (atof_ieee ((char *) fp_const[i], 'x', fp_values[i]) == NULL)
12494 abort ();
12495 }
12496
12497 void
12498 md_begin (void)
12499 {
12500 unsigned mach;
12501 unsigned int i;
12502
12503 if ( (arm_ops_hsh = hash_new ()) == NULL
12504 || (arm_cond_hsh = hash_new ()) == NULL
12505 || (arm_shift_hsh = hash_new ()) == NULL
12506 || (arm_psr_hsh = hash_new ()) == NULL
12507 || (arm_reg_hsh = hash_new ()) == NULL
12508 || (arm_reloc_hsh = hash_new ()) == NULL)
12509 as_fatal (_("virtual memory exhausted"));
12510
12511 for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++)
12512 hash_insert (arm_ops_hsh, insns[i].template, (PTR) (insns + i));
12513 for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++)
12514 hash_insert (arm_cond_hsh, conds[i].template, (PTR) (conds + i));
12515 for (i = 0; i < sizeof (shift_names) / sizeof (struct asm_shift_name); i++)
12516 hash_insert (arm_shift_hsh, shift_names[i].name, (PTR) (shift_names + i));
12517 for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++)
12518 hash_insert (arm_psr_hsh, psrs[i].template, (PTR) (psrs + i));
12519 for (i = 0; i < sizeof (reg_names) / sizeof (struct reg_entry); i++)
12520 hash_insert (arm_reg_hsh, reg_names[i].name, (PTR) (reg_names + i));
12521 #ifdef OBJ_ELF
12522 for (i = 0; i < sizeof (reloc_names) / sizeof (struct reloc_entry); i++)
12523 hash_insert (arm_reloc_hsh, reloc_names[i].name, (PTR) (reloc_names + i));
12524 #endif
12525
12526 set_constant_flonums ();
12527
12528 /* Set the cpu variant based on the command-line options. We prefer
12529 -mcpu= over -march= if both are set (as for GCC); and we prefer
12530 -mfpu= over any other way of setting the floating point unit.
12531 Use of legacy options with new options are faulted. */
12532 if (legacy_cpu)
12533 {
12534 if (mcpu_cpu_opt || march_cpu_opt)
12535 as_bad (_("use of old and new-style options to set CPU type"));
12536
12537 mcpu_cpu_opt = legacy_cpu;
12538 }
12539 else if (!mcpu_cpu_opt)
12540 mcpu_cpu_opt = march_cpu_opt;
12541
12542 if (legacy_fpu)
12543 {
12544 if (mfpu_opt)
12545 as_bad (_("use of old and new-style options to set FPU type"));
12546
12547 mfpu_opt = legacy_fpu;
12548 }
12549 else if (!mfpu_opt)
12550 {
12551 #if !(defined (TE_LINUX) || defined (TE_NetBSD) || defined (TE_VXWORKS))
12552 /* Some environments specify a default FPU. If they don't, infer it
12553 from the processor. */
12554 if (mcpu_fpu_opt)
12555 mfpu_opt = mcpu_fpu_opt;
12556 else
12557 mfpu_opt = march_fpu_opt;
12558 #else
12559 mfpu_opt = &fpu_default;
12560 #endif
12561 }
12562
12563 if (!mfpu_opt)
12564 {
12565 if (!mcpu_cpu_opt)
12566 mfpu_opt = &fpu_default;
12567 else if (ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt, arm_ext_v5))
12568 mfpu_opt = &fpu_arch_vfp_v2;
12569 else
12570 mfpu_opt = &fpu_arch_fpa;
12571 }
12572
12573 #ifdef CPU_DEFAULT
12574 if (!mcpu_cpu_opt)
12575 {
12576 mcpu_cpu_opt = &cpu_default;
12577 selected_cpu = cpu_default;
12578 }
12579 #else
12580 if (mcpu_cpu_opt)
12581 selected_cpu = *mcpu_cpu_opt;
12582 else
12583 mcpu_cpu_opt = &arm_arch_any;
12584 #endif
12585
12586 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
12587
12588 arm_arch_used = thumb_arch_used = arm_arch_none;
12589
12590 #if defined OBJ_COFF || defined OBJ_ELF
12591 {
12592 unsigned int flags = 0;
12593
12594 #if defined OBJ_ELF
12595 flags = meabi_flags;
12596
12597 switch (meabi_flags)
12598 {
12599 case EF_ARM_EABI_UNKNOWN:
12600 #endif
12601 /* Set the flags in the private structure. */
12602 if (uses_apcs_26) flags |= F_APCS26;
12603 if (support_interwork) flags |= F_INTERWORK;
12604 if (uses_apcs_float) flags |= F_APCS_FLOAT;
12605 if (pic_code) flags |= F_PIC;
12606 if (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_any_hard))
12607 flags |= F_SOFT_FLOAT;
12608
12609 switch (mfloat_abi_opt)
12610 {
12611 case ARM_FLOAT_ABI_SOFT:
12612 case ARM_FLOAT_ABI_SOFTFP:
12613 flags |= F_SOFT_FLOAT;
12614 break;
12615
12616 case ARM_FLOAT_ABI_HARD:
12617 if (flags & F_SOFT_FLOAT)
12618 as_bad (_("hard-float conflicts with specified fpu"));
12619 break;
12620 }
12621
12622 /* Using pure-endian doubles (even if soft-float). */
12623 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
12624 flags |= F_VFP_FLOAT;
12625
12626 #if defined OBJ_ELF
12627 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_maverick))
12628 flags |= EF_ARM_MAVERICK_FLOAT;
12629 break;
12630
12631 case EF_ARM_EABI_VER4:
12632 /* No additional flags to set. */
12633 break;
12634
12635 default:
12636 abort ();
12637 }
12638 #endif
12639 bfd_set_private_flags (stdoutput, flags);
12640
12641 /* We have run out flags in the COFF header to encode the
12642 status of ATPCS support, so instead we create a dummy,
12643 empty, debug section called .arm.atpcs. */
12644 if (atpcs)
12645 {
12646 asection * sec;
12647
12648 sec = bfd_make_section (stdoutput, ".arm.atpcs");
12649
12650 if (sec != NULL)
12651 {
12652 bfd_set_section_flags
12653 (stdoutput, sec, SEC_READONLY | SEC_DEBUGGING /* | SEC_HAS_CONTENTS */);
12654 bfd_set_section_size (stdoutput, sec, 0);
12655 bfd_set_section_contents (stdoutput, sec, NULL, 0, 0);
12656 }
12657 }
12658 }
12659 #endif
12660
12661 /* Record the CPU type as well. */
12662 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt))
12663 mach = bfd_mach_arm_iWMMXt;
12664 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_xscale))
12665 mach = bfd_mach_arm_XScale;
12666 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_maverick))
12667 mach = bfd_mach_arm_ep9312;
12668 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5e))
12669 mach = bfd_mach_arm_5TE;
12670 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5))
12671 {
12672 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
12673 mach = bfd_mach_arm_5T;
12674 else
12675 mach = bfd_mach_arm_5;
12676 }
12677 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4))
12678 {
12679 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
12680 mach = bfd_mach_arm_4T;
12681 else
12682 mach = bfd_mach_arm_4;
12683 }
12684 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3m))
12685 mach = bfd_mach_arm_3M;
12686 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3))
12687 mach = bfd_mach_arm_3;
12688 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2s))
12689 mach = bfd_mach_arm_2a;
12690 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2))
12691 mach = bfd_mach_arm_2;
12692 else
12693 mach = bfd_mach_arm_unknown;
12694
12695 bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach);
12696 }
12697
12698 /* Command line processing. */
12699
12700 /* md_parse_option
12701 Invocation line includes a switch not recognized by the base assembler.
12702 See if it's a processor-specific option.
12703
12704 This routine is somewhat complicated by the need for backwards
12705 compatibility (since older releases of gcc can't be changed).
12706 The new options try to make the interface as compatible as
12707 possible with GCC.
12708
12709 New options (supported) are:
12710
12711 -mcpu=<cpu name> Assemble for selected processor
12712 -march=<architecture name> Assemble for selected architecture
12713 -mfpu=<fpu architecture> Assemble for selected FPU.
12714 -EB/-mbig-endian Big-endian
12715 -EL/-mlittle-endian Little-endian
12716 -k Generate PIC code
12717 -mthumb Start in Thumb mode
12718 -mthumb-interwork Code supports ARM/Thumb interworking
12719
12720 For now we will also provide support for:
12721
12722 -mapcs-32 32-bit Program counter
12723 -mapcs-26 26-bit Program counter
12724 -macps-float Floats passed in FP registers
12725 -mapcs-reentrant Reentrant code
12726 -matpcs
12727 (sometime these will probably be replaced with -mapcs=<list of options>
12728 and -matpcs=<list of options>)
12729
12730 The remaining options are only supported for back-wards compatibility.
12731 Cpu variants, the arm part is optional:
12732 -m[arm]1 Currently not supported.
12733 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
12734 -m[arm]3 Arm 3 processor
12735 -m[arm]6[xx], Arm 6 processors
12736 -m[arm]7[xx][t][[d]m] Arm 7 processors
12737 -m[arm]8[10] Arm 8 processors
12738 -m[arm]9[20][tdmi] Arm 9 processors
12739 -mstrongarm[110[0]] StrongARM processors
12740 -mxscale XScale processors
12741 -m[arm]v[2345[t[e]]] Arm architectures
12742 -mall All (except the ARM1)
12743 FP variants:
12744 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
12745 -mfpe-old (No float load/store multiples)
12746 -mvfpxd VFP Single precision
12747 -mvfp All VFP
12748 -mno-fpu Disable all floating point instructions
12749
12750 The following CPU names are recognized:
12751 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
12752 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
12753 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
12754 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
12755 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
12756 arm10t arm10e, arm1020t, arm1020e, arm10200e,
12757 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
12758
12759 */
12760
12761 const char * md_shortopts = "m:k";
12762
12763 #ifdef ARM_BI_ENDIAN
12764 #define OPTION_EB (OPTION_MD_BASE + 0)
12765 #define OPTION_EL (OPTION_MD_BASE + 1)
12766 #else
12767 #if TARGET_BYTES_BIG_ENDIAN
12768 #define OPTION_EB (OPTION_MD_BASE + 0)
12769 #else
12770 #define OPTION_EL (OPTION_MD_BASE + 1)
12771 #endif
12772 #endif
12773
12774 struct option md_longopts[] =
12775 {
12776 #ifdef OPTION_EB
12777 {"EB", no_argument, NULL, OPTION_EB},
12778 #endif
12779 #ifdef OPTION_EL
12780 {"EL", no_argument, NULL, OPTION_EL},
12781 #endif
12782 {NULL, no_argument, NULL, 0}
12783 };
12784
12785 size_t md_longopts_size = sizeof (md_longopts);
12786
12787 struct arm_option_table
12788 {
12789 char *option; /* Option name to match. */
12790 char *help; /* Help information. */
12791 int *var; /* Variable to change. */
12792 int value; /* What to change it to. */
12793 char *deprecated; /* If non-null, print this message. */
12794 };
12795
12796 struct arm_option_table arm_opts[] =
12797 {
12798 {"k", N_("generate PIC code"), &pic_code, 1, NULL},
12799 {"mthumb", N_("assemble Thumb code"), &thumb_mode, 1, NULL},
12800 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
12801 &support_interwork, 1, NULL},
12802 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26, 0, NULL},
12803 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26, 1, NULL},
12804 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float,
12805 1, NULL},
12806 {"mapcs-reentrant", N_("re-entrant code"), &pic_code, 1, NULL},
12807 {"matpcs", N_("code is ATPCS conformant"), &atpcs, 1, NULL},
12808 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL},
12809 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 0,
12810 NULL},
12811
12812 /* These are recognized by the assembler, but have no affect on code. */
12813 {"mapcs-frame", N_("use frame pointer"), NULL, 0, NULL},
12814 {"mapcs-stack-check", N_("use stack size checking"), NULL, 0, NULL},
12815 {NULL, NULL, NULL, 0, NULL}
12816 };
12817
12818 struct arm_legacy_option_table
12819 {
12820 char *option; /* Option name to match. */
12821 const arm_feature_set **var; /* Variable to change. */
12822 const arm_feature_set value; /* What to change it to. */
12823 char *deprecated; /* If non-null, print this message. */
12824 };
12825
12826 const struct arm_legacy_option_table arm_legacy_opts[] =
12827 {
12828 /* DON'T add any new processors to this list -- we want the whole list
12829 to go away... Add them to the processors table instead. */
12830 {"marm1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
12831 {"m1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
12832 {"marm2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
12833 {"m2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
12834 {"marm250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
12835 {"m250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
12836 {"marm3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
12837 {"m3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
12838 {"marm6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
12839 {"m6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
12840 {"marm600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
12841 {"m600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
12842 {"marm610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
12843 {"m610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
12844 {"marm620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
12845 {"m620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
12846 {"marm7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
12847 {"m7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
12848 {"marm70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
12849 {"m70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
12850 {"marm700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
12851 {"m700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
12852 {"marm700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
12853 {"m700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
12854 {"marm710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
12855 {"m710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
12856 {"marm710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
12857 {"m710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
12858 {"marm720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
12859 {"m720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
12860 {"marm7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
12861 {"m7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
12862 {"marm7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
12863 {"m7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
12864 {"marm7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
12865 {"m7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
12866 {"marm7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
12867 {"m7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
12868 {"marm7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
12869 {"m7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
12870 {"marm7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
12871 {"m7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
12872 {"marm7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
12873 {"m7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
12874 {"marm7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
12875 {"m7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
12876 {"marm7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
12877 {"m7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
12878 {"marm7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
12879 {"m7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
12880 {"marm710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
12881 {"m710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
12882 {"marm720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
12883 {"m720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
12884 {"marm740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
12885 {"m740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
12886 {"marm8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
12887 {"m8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
12888 {"marm810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
12889 {"m810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
12890 {"marm9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
12891 {"m9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
12892 {"marm9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
12893 {"m9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
12894 {"marm920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
12895 {"m920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
12896 {"marm940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
12897 {"m940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
12898 {"mstrongarm", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=strongarm")},
12899 {"mstrongarm110", &legacy_cpu, ARM_ARCH_V4,
12900 N_("use -mcpu=strongarm110")},
12901 {"mstrongarm1100", &legacy_cpu, ARM_ARCH_V4,
12902 N_("use -mcpu=strongarm1100")},
12903 {"mstrongarm1110", &legacy_cpu, ARM_ARCH_V4,
12904 N_("use -mcpu=strongarm1110")},
12905 {"mxscale", &legacy_cpu, ARM_ARCH_XSCALE, N_("use -mcpu=xscale")},
12906 {"miwmmxt", &legacy_cpu, ARM_ARCH_IWMMXT, N_("use -mcpu=iwmmxt")},
12907 {"mall", &legacy_cpu, ARM_ANY, N_("use -mcpu=all")},
12908
12909 /* Architecture variants -- don't add any more to this list either. */
12910 {"mv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
12911 {"marmv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
12912 {"mv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
12913 {"marmv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
12914 {"mv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
12915 {"marmv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
12916 {"mv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
12917 {"marmv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
12918 {"mv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
12919 {"marmv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
12920 {"mv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
12921 {"marmv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
12922 {"mv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
12923 {"marmv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
12924 {"mv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
12925 {"marmv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
12926 {"mv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
12927 {"marmv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
12928
12929 /* Floating point variants -- don't add any more to this list either. */
12930 {"mfpe-old", &legacy_fpu, FPU_ARCH_FPE, N_("use -mfpu=fpe")},
12931 {"mfpa10", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa10")},
12932 {"mfpa11", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa11")},
12933 {"mno-fpu", &legacy_fpu, ARM_ARCH_NONE,
12934 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
12935
12936 {NULL, NULL, ARM_ARCH_NONE, NULL}
12937 };
12938
12939 struct arm_cpu_option_table
12940 {
12941 char *name;
12942 const arm_feature_set value;
12943 /* For some CPUs we assume an FPU unless the user explicitly sets
12944 -mfpu=... */
12945 const arm_feature_set default_fpu;
12946 /* The canonical name of the CPU, or NULL to use NAME converted to upper
12947 case. */
12948 const char *canonical_name;
12949 };
12950
12951 /* This list should, at a minimum, contain all the cpu names
12952 recognized by GCC. */
12953 static const struct arm_cpu_option_table arm_cpus[] =
12954 {
12955 {"all", ARM_ANY, FPU_ARCH_FPA, NULL},
12956 {"arm1", ARM_ARCH_V1, FPU_ARCH_FPA, NULL},
12957 {"arm2", ARM_ARCH_V2, FPU_ARCH_FPA, NULL},
12958 {"arm250", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL},
12959 {"arm3", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL},
12960 {"arm6", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
12961 {"arm60", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
12962 {"arm600", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
12963 {"arm610", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
12964 {"arm620", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
12965 {"arm7", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
12966 {"arm7m", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL},
12967 {"arm7d", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
12968 {"arm7dm", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL},
12969 {"arm7di", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
12970 {"arm7dmi", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL},
12971 {"arm70", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
12972 {"arm700", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
12973 {"arm700i", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
12974 {"arm710", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
12975 {"arm710t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
12976 {"arm720", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
12977 {"arm720t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
12978 {"arm740t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
12979 {"arm710c", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
12980 {"arm7100", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
12981 {"arm7500", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
12982 {"arm7500fe", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
12983 {"arm7t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
12984 {"arm7tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
12985 {"arm7tdmi-s", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
12986 {"arm8", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
12987 {"arm810", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
12988 {"strongarm", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
12989 {"strongarm1", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
12990 {"strongarm110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
12991 {"strongarm1100", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
12992 {"strongarm1110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
12993 {"arm9", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
12994 {"arm920", ARM_ARCH_V4T, FPU_ARCH_FPA, "ARM920T"},
12995 {"arm920t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
12996 {"arm922t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
12997 {"arm940t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
12998 {"arm9tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
12999 /* For V5 or later processors we default to using VFP; but the user
13000 should really set the FPU type explicitly. */
13001 {"arm9e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL},
13002 {"arm9e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
13003 {"arm926ej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"},
13004 {"arm926ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"},
13005 {"arm926ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL},
13006 {"arm946e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL},
13007 {"arm946e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM946E-S"},
13008 {"arm946e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
13009 {"arm966e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL},
13010 {"arm966e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM966E-S"},
13011 {"arm966e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
13012 {"arm968e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
13013 {"arm10t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL},
13014 {"arm10tdmi", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL},
13015 {"arm10e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
13016 {"arm1020", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM1020E"},
13017 {"arm1020t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL},
13018 {"arm1020e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
13019 {"arm1022e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
13020 {"arm1026ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM1026EJ-S"},
13021 {"arm1026ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL},
13022 {"arm1136js", ARM_ARCH_V6, FPU_NONE, "ARM1136J-S"},
13023 {"arm1136j-s", ARM_ARCH_V6, FPU_NONE, NULL},
13024 {"arm1136jfs", ARM_ARCH_V6, FPU_ARCH_VFP_V2, "ARM1136JF-S"},
13025 {"arm1136jf-s", ARM_ARCH_V6, FPU_ARCH_VFP_V2, NULL},
13026 {"mpcore", ARM_ARCH_V6K, FPU_ARCH_VFP_V2, NULL},
13027 {"mpcorenovfp", ARM_ARCH_V6K, FPU_NONE, NULL},
13028 {"arm1156t2-s", ARM_ARCH_V6T2, FPU_NONE, NULL},
13029 {"arm1156t2f-s", ARM_ARCH_V6T2, FPU_ARCH_VFP_V2, NULL},
13030 {"arm1176jz-s", ARM_ARCH_V6ZK, FPU_NONE, NULL},
13031 {"arm1176jzf-s", ARM_ARCH_V6ZK, FPU_ARCH_VFP_V2, NULL},
13032 /* ??? XSCALE is really an architecture. */
13033 {"xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL},
13034 /* ??? iwmmxt is not a processor. */
13035 {"iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP_V2, NULL},
13036 {"i80200", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL},
13037 /* Maverick */
13038 {"ep9312", ARM_FEATURE(ARM_AEXT_V4T, ARM_CEXT_MAVERICK), FPU_ARCH_MAVERICK, "ARM920T"},
13039 {NULL, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL}
13040 };
13041
13042 struct arm_arch_option_table
13043 {
13044 char *name;
13045 const arm_feature_set value;
13046 const arm_feature_set default_fpu;
13047 };
13048
13049 /* This list should, at a minimum, contain all the architecture names
13050 recognized by GCC. */
13051 static const struct arm_arch_option_table arm_archs[] =
13052 {
13053 {"all", ARM_ANY, FPU_ARCH_FPA},
13054 {"armv1", ARM_ARCH_V1, FPU_ARCH_FPA},
13055 {"armv2", ARM_ARCH_V2, FPU_ARCH_FPA},
13056 {"armv2a", ARM_ARCH_V2S, FPU_ARCH_FPA},
13057 {"armv2s", ARM_ARCH_V2S, FPU_ARCH_FPA},
13058 {"armv3", ARM_ARCH_V3, FPU_ARCH_FPA},
13059 {"armv3m", ARM_ARCH_V3M, FPU_ARCH_FPA},
13060 {"armv4", ARM_ARCH_V4, FPU_ARCH_FPA},
13061 {"armv4xm", ARM_ARCH_V4xM, FPU_ARCH_FPA},
13062 {"armv4t", ARM_ARCH_V4T, FPU_ARCH_FPA},
13063 {"armv4txm", ARM_ARCH_V4TxM, FPU_ARCH_FPA},
13064 {"armv5", ARM_ARCH_V5, FPU_ARCH_VFP},
13065 {"armv5t", ARM_ARCH_V5T, FPU_ARCH_VFP},
13066 {"armv5txm", ARM_ARCH_V5TxM, FPU_ARCH_VFP},
13067 {"armv5te", ARM_ARCH_V5TE, FPU_ARCH_VFP},
13068 {"armv5texp", ARM_ARCH_V5TExP, FPU_ARCH_VFP},
13069 {"armv5tej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP},
13070 {"armv6", ARM_ARCH_V6, FPU_ARCH_VFP},
13071 {"armv6j", ARM_ARCH_V6, FPU_ARCH_VFP},
13072 {"armv6k", ARM_ARCH_V6K, FPU_ARCH_VFP},
13073 {"armv6z", ARM_ARCH_V6Z, FPU_ARCH_VFP},
13074 {"armv6zk", ARM_ARCH_V6ZK, FPU_ARCH_VFP},
13075 {"armv6t2", ARM_ARCH_V6T2, FPU_ARCH_VFP},
13076 {"armv6kt2", ARM_ARCH_V6KT2, FPU_ARCH_VFP},
13077 {"armv6zt2", ARM_ARCH_V6ZT2, FPU_ARCH_VFP},
13078 {"armv6zkt2", ARM_ARCH_V6ZKT2, FPU_ARCH_VFP},
13079 {"xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP},
13080 {"iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP},
13081 {NULL, ARM_ARCH_NONE, ARM_ARCH_NONE}
13082 };
13083
13084 /* ISA extensions in the co-processor space. */
13085 struct arm_option_cpu_value_table
13086 {
13087 char *name;
13088 const arm_feature_set value;
13089 };
13090
13091 static const struct arm_option_cpu_value_table arm_extensions[] =
13092 {
13093 {"maverick", ARM_FEATURE (0, ARM_CEXT_MAVERICK)},
13094 {"xscale", ARM_FEATURE (0, ARM_CEXT_XSCALE)},
13095 {"iwmmxt", ARM_FEATURE (0, ARM_CEXT_IWMMXT)},
13096 {NULL, ARM_ARCH_NONE}
13097 };
13098
13099 /* This list should, at a minimum, contain all the fpu names
13100 recognized by GCC. */
13101 static const struct arm_option_cpu_value_table arm_fpus[] =
13102 {
13103 {"softfpa", FPU_NONE},
13104 {"fpe", FPU_ARCH_FPE},
13105 {"fpe2", FPU_ARCH_FPE},
13106 {"fpe3", FPU_ARCH_FPA}, /* Third release supports LFM/SFM. */
13107 {"fpa", FPU_ARCH_FPA},
13108 {"fpa10", FPU_ARCH_FPA},
13109 {"fpa11", FPU_ARCH_FPA},
13110 {"arm7500fe", FPU_ARCH_FPA},
13111 {"softvfp", FPU_ARCH_VFP},
13112 {"softvfp+vfp", FPU_ARCH_VFP_V2},
13113 {"vfp", FPU_ARCH_VFP_V2},
13114 {"vfp9", FPU_ARCH_VFP_V2},
13115 {"vfp10", FPU_ARCH_VFP_V2},
13116 {"vfp10-r0", FPU_ARCH_VFP_V1},
13117 {"vfpxd", FPU_ARCH_VFP_V1xD},
13118 {"arm1020t", FPU_ARCH_VFP_V1},
13119 {"arm1020e", FPU_ARCH_VFP_V2},
13120 {"arm1136jfs", FPU_ARCH_VFP_V2},
13121 {"arm1136jf-s", FPU_ARCH_VFP_V2},
13122 {"maverick", FPU_ARCH_MAVERICK},
13123 {NULL, ARM_ARCH_NONE}
13124 };
13125
13126 struct arm_option_value_table
13127 {
13128 char *name;
13129 long value;
13130 };
13131
13132 static const struct arm_option_value_table arm_float_abis[] =
13133 {
13134 {"hard", ARM_FLOAT_ABI_HARD},
13135 {"softfp", ARM_FLOAT_ABI_SOFTFP},
13136 {"soft", ARM_FLOAT_ABI_SOFT},
13137 {NULL, 0}
13138 };
13139
13140 #ifdef OBJ_ELF
13141 /* We only know how to output GNU and ver 4 (AAELF) formats. */
13142 static const struct arm_option_value_table arm_eabis[] =
13143 {
13144 {"gnu", EF_ARM_EABI_UNKNOWN},
13145 {"4", EF_ARM_EABI_VER4},
13146 {NULL, 0}
13147 };
13148 #endif
13149
13150 struct arm_long_option_table
13151 {
13152 char * option; /* Substring to match. */
13153 char * help; /* Help information. */
13154 int (* func) (char * subopt); /* Function to decode sub-option. */
13155 char * deprecated; /* If non-null, print this message. */
13156 };
13157
13158 static int
13159 arm_parse_extension (char * str, const arm_feature_set **opt_p)
13160 {
13161 arm_feature_set *ext_set = xmalloc (sizeof (arm_feature_set));
13162
13163 /* Copy the feature set, so that we can modify it. */
13164 *ext_set = **opt_p;
13165 *opt_p = ext_set;
13166
13167 while (str != NULL && *str != 0)
13168 {
13169 const struct arm_option_cpu_value_table * opt;
13170 char * ext;
13171 int optlen;
13172
13173 if (*str != '+')
13174 {
13175 as_bad (_("invalid architectural extension"));
13176 return 0;
13177 }
13178
13179 str++;
13180 ext = strchr (str, '+');
13181
13182 if (ext != NULL)
13183 optlen = ext - str;
13184 else
13185 optlen = strlen (str);
13186
13187 if (optlen == 0)
13188 {
13189 as_bad (_("missing architectural extension"));
13190 return 0;
13191 }
13192
13193 for (opt = arm_extensions; opt->name != NULL; opt++)
13194 if (strncmp (opt->name, str, optlen) == 0)
13195 {
13196 ARM_MERGE_FEATURE_SETS (*ext_set, *ext_set, opt->value);
13197 break;
13198 }
13199
13200 if (opt->name == NULL)
13201 {
13202 as_bad (_("unknown architectural extnsion `%s'"), str);
13203 return 0;
13204 }
13205
13206 str = ext;
13207 };
13208
13209 return 1;
13210 }
13211
13212 static int
13213 arm_parse_cpu (char * str)
13214 {
13215 const struct arm_cpu_option_table * opt;
13216 char * ext = strchr (str, '+');
13217 int optlen;
13218
13219 if (ext != NULL)
13220 optlen = ext - str;
13221 else
13222 optlen = strlen (str);
13223
13224 if (optlen == 0)
13225 {
13226 as_bad (_("missing cpu name `%s'"), str);
13227 return 0;
13228 }
13229
13230 for (opt = arm_cpus; opt->name != NULL; opt++)
13231 if (strncmp (opt->name, str, optlen) == 0)
13232 {
13233 mcpu_cpu_opt = &opt->value;
13234 mcpu_fpu_opt = &opt->default_fpu;
13235 if (opt->canonical_name)
13236 strcpy(selected_cpu_name, opt->canonical_name);
13237 else
13238 {
13239 int i;
13240 for (i = 0; i < optlen; i++)
13241 selected_cpu_name[i] = TOUPPER (opt->name[i]);
13242 selected_cpu_name[i] = 0;
13243 }
13244
13245 if (ext != NULL)
13246 return arm_parse_extension (ext, &mcpu_cpu_opt);
13247
13248 return 1;
13249 }
13250
13251 as_bad (_("unknown cpu `%s'"), str);
13252 return 0;
13253 }
13254
13255 static int
13256 arm_parse_arch (char * str)
13257 {
13258 const struct arm_arch_option_table *opt;
13259 char *ext = strchr (str, '+');
13260 int optlen;
13261
13262 if (ext != NULL)
13263 optlen = ext - str;
13264 else
13265 optlen = strlen (str);
13266
13267 if (optlen == 0)
13268 {
13269 as_bad (_("missing architecture name `%s'"), str);
13270 return 0;
13271 }
13272
13273 for (opt = arm_archs; opt->name != NULL; opt++)
13274 if (streq (opt->name, str))
13275 {
13276 march_cpu_opt = &opt->value;
13277 march_fpu_opt = &opt->default_fpu;
13278 strcpy(selected_cpu_name, opt->name);
13279
13280 if (ext != NULL)
13281 return arm_parse_extension (ext, &march_cpu_opt);
13282
13283 return 1;
13284 }
13285
13286 as_bad (_("unknown architecture `%s'\n"), str);
13287 return 0;
13288 }
13289
13290 static int
13291 arm_parse_fpu (char * str)
13292 {
13293 const struct arm_option_cpu_value_table * opt;
13294
13295 for (opt = arm_fpus; opt->name != NULL; opt++)
13296 if (streq (opt->name, str))
13297 {
13298 mfpu_opt = &opt->value;
13299 return 1;
13300 }
13301
13302 as_bad (_("unknown floating point format `%s'\n"), str);
13303 return 0;
13304 }
13305
13306 static int
13307 arm_parse_float_abi (char * str)
13308 {
13309 const struct arm_option_value_table * opt;
13310
13311 for (opt = arm_float_abis; opt->name != NULL; opt++)
13312 if (streq (opt->name, str))
13313 {
13314 mfloat_abi_opt = opt->value;
13315 return 1;
13316 }
13317
13318 as_bad (_("unknown floating point abi `%s'\n"), str);
13319 return 0;
13320 }
13321
13322 #ifdef OBJ_ELF
13323 static int
13324 arm_parse_eabi (char * str)
13325 {
13326 const struct arm_option_value_table *opt;
13327
13328 for (opt = arm_eabis; opt->name != NULL; opt++)
13329 if (streq (opt->name, str))
13330 {
13331 meabi_flags = opt->value;
13332 return 1;
13333 }
13334 as_bad (_("unknown EABI `%s'\n"), str);
13335 return 0;
13336 }
13337 #endif
13338
13339 struct arm_long_option_table arm_long_opts[] =
13340 {
13341 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
13342 arm_parse_cpu, NULL},
13343 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
13344 arm_parse_arch, NULL},
13345 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
13346 arm_parse_fpu, NULL},
13347 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
13348 arm_parse_float_abi, NULL},
13349 #ifdef OBJ_ELF
13350 {"meabi=", N_("<ver>\t assemble for eabi version <ver>"),
13351 arm_parse_eabi, NULL},
13352 #endif
13353 {NULL, NULL, 0, NULL}
13354 };
13355
13356 int
13357 md_parse_option (int c, char * arg)
13358 {
13359 struct arm_option_table *opt;
13360 const struct arm_legacy_option_table *fopt;
13361 struct arm_long_option_table *lopt;
13362
13363 switch (c)
13364 {
13365 #ifdef OPTION_EB
13366 case OPTION_EB:
13367 target_big_endian = 1;
13368 break;
13369 #endif
13370
13371 #ifdef OPTION_EL
13372 case OPTION_EL:
13373 target_big_endian = 0;
13374 break;
13375 #endif
13376
13377 case 'a':
13378 /* Listing option. Just ignore these, we don't support additional
13379 ones. */
13380 return 0;
13381
13382 default:
13383 for (opt = arm_opts; opt->option != NULL; opt++)
13384 {
13385 if (c == opt->option[0]
13386 && ((arg == NULL && opt->option[1] == 0)
13387 || streq (arg, opt->option + 1)))
13388 {
13389 #if WARN_DEPRECATED
13390 /* If the option is deprecated, tell the user. */
13391 if (opt->deprecated != NULL)
13392 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
13393 arg ? arg : "", _(opt->deprecated));
13394 #endif
13395
13396 if (opt->var != NULL)
13397 *opt->var = opt->value;
13398
13399 return 1;
13400 }
13401 }
13402
13403 for (fopt = arm_legacy_opts; fopt->option != NULL; fopt++)
13404 {
13405 if (c == fopt->option[0]
13406 && ((arg == NULL && fopt->option[1] == 0)
13407 || streq (arg, fopt->option + 1)))
13408 {
13409 #if WARN_DEPRECATED
13410 /* If the option is deprecated, tell the user. */
13411 if (fopt->deprecated != NULL)
13412 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
13413 arg ? arg : "", _(fopt->deprecated));
13414 #endif
13415
13416 if (fopt->var != NULL)
13417 *fopt->var = &fopt->value;
13418
13419 return 1;
13420 }
13421 }
13422
13423 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
13424 {
13425 /* These options are expected to have an argument. */
13426 if (c == lopt->option[0]
13427 && arg != NULL
13428 && strncmp (arg, lopt->option + 1,
13429 strlen (lopt->option + 1)) == 0)
13430 {
13431 #if WARN_DEPRECATED
13432 /* If the option is deprecated, tell the user. */
13433 if (lopt->deprecated != NULL)
13434 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, arg,
13435 _(lopt->deprecated));
13436 #endif
13437
13438 /* Call the sup-option parser. */
13439 return lopt->func (arg + strlen (lopt->option) - 1);
13440 }
13441 }
13442
13443 return 0;
13444 }
13445
13446 return 1;
13447 }
13448
13449 void
13450 md_show_usage (FILE * fp)
13451 {
13452 struct arm_option_table *opt;
13453 struct arm_long_option_table *lopt;
13454
13455 fprintf (fp, _(" ARM-specific assembler options:\n"));
13456
13457 for (opt = arm_opts; opt->option != NULL; opt++)
13458 if (opt->help != NULL)
13459 fprintf (fp, " -%-23s%s\n", opt->option, _(opt->help));
13460
13461 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
13462 if (lopt->help != NULL)
13463 fprintf (fp, " -%s%s\n", lopt->option, _(lopt->help));
13464
13465 #ifdef OPTION_EB
13466 fprintf (fp, _("\
13467 -EB assemble code for a big-endian cpu\n"));
13468 #endif
13469
13470 #ifdef OPTION_EL
13471 fprintf (fp, _("\
13472 -EL assemble code for a little-endian cpu\n"));
13473 #endif
13474 }
13475
13476
13477 #ifdef OBJ_ELF
13478 /* Set the public EABI object attributes. */
13479 static void
13480 aeabi_set_public_attributes (void)
13481 {
13482 int arch;
13483 arm_feature_set flags;
13484
13485 /* Choose the architecture based on the capabilities of the requested cpu
13486 (if any) and/or the instructions actually used. */
13487 ARM_MERGE_FEATURE_SETS (flags, arm_arch_used, thumb_arch_used);
13488 ARM_MERGE_FEATURE_SETS (flags, flags, *mfpu_opt);
13489 ARM_MERGE_FEATURE_SETS (flags, flags, selected_cpu);
13490 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v6t2))
13491 arch = 8;
13492 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v6z))
13493 arch = 7;
13494 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v6k))
13495 arch = 9;
13496 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v6))
13497 arch = 6;
13498 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v5e))
13499 arch = 4;
13500 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v5)
13501 || ARM_CPU_HAS_FEATURE (flags, arm_ext_v5t))
13502 arch = 3;
13503 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v4t))
13504 arch = 2;
13505 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v4))
13506 arch = 1;
13507 else
13508 arch = 0;
13509
13510 /* Tag_CPU_name. */
13511 if (selected_cpu_name[0])
13512 {
13513 char *p;
13514
13515 p = selected_cpu_name;
13516 if (strncmp(p, "armv", 4) == 0)
13517 {
13518 int i;
13519
13520 p += 4;
13521 for (i = 0; p[i]; i++)
13522 p[i] = TOUPPER (p[i]);
13523 }
13524 elf32_arm_add_eabi_attr_string (stdoutput, 5, p);
13525 }
13526 /* Tag_CPU_arch. */
13527 elf32_arm_add_eabi_attr_int (stdoutput, 6, arch);
13528 /* Tag_ARM_ISA_use. */
13529 if (ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_full))
13530 elf32_arm_add_eabi_attr_int (stdoutput, 8, 1);
13531 /* Tag_THUMB_ISA_use. */
13532 if (ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_full))
13533 elf32_arm_add_eabi_attr_int (stdoutput, 9,
13534 ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_t2) ? 2 : 1);
13535 /* Tag_VFP_arch. */
13536 if (ARM_CPU_HAS_FEATURE (thumb_arch_used, fpu_arch_vfp_v2)
13537 || ARM_CPU_HAS_FEATURE (arm_arch_used, fpu_arch_vfp_v2))
13538 elf32_arm_add_eabi_attr_int (stdoutput, 10, 2);
13539 else if (ARM_CPU_HAS_FEATURE (thumb_arch_used, fpu_arch_vfp_v1)
13540 || ARM_CPU_HAS_FEATURE (arm_arch_used, fpu_arch_vfp_v1))
13541 elf32_arm_add_eabi_attr_int (stdoutput, 10, 1);
13542 /* Tag_WMMX_arch. */
13543 if (ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_cext_iwmmxt)
13544 || ARM_CPU_HAS_FEATURE (arm_arch_used, arm_cext_iwmmxt))
13545 elf32_arm_add_eabi_attr_int (stdoutput, 11, 1);
13546 }
13547
13548 /* Add the .ARM.attributes section. */
13549 void
13550 arm_md_end (void)
13551 {
13552 segT s;
13553 char *p;
13554 addressT addr;
13555 offsetT size;
13556
13557 if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
13558 return;
13559
13560 aeabi_set_public_attributes ();
13561 size = elf32_arm_eabi_attr_size (stdoutput);
13562 s = subseg_new (".ARM.attributes", 0);
13563 bfd_set_section_flags (stdoutput, s, SEC_READONLY | SEC_DATA);
13564 addr = frag_now_fix ();
13565 p = frag_more (size);
13566 elf32_arm_set_eabi_attr_contents (stdoutput, (bfd_byte *)p, size);
13567 }
13568
13569
13570 /* Parse a .cpu directive. */
13571
13572 static void
13573 s_arm_cpu (int ignored ATTRIBUTE_UNUSED)
13574 {
13575 const struct arm_cpu_option_table *opt;
13576 char *name;
13577 char saved_char;
13578
13579 name = input_line_pointer;
13580 while (*input_line_pointer && !ISSPACE(*input_line_pointer))
13581 input_line_pointer++;
13582 saved_char = *input_line_pointer;
13583 *input_line_pointer = 0;
13584
13585 /* Skip the first "all" entry. */
13586 for (opt = arm_cpus + 1; opt->name != NULL; opt++)
13587 if (streq (opt->name, name))
13588 {
13589 mcpu_cpu_opt = &opt->value;
13590 selected_cpu = opt->value;
13591 if (opt->canonical_name)
13592 strcpy(selected_cpu_name, opt->canonical_name);
13593 else
13594 {
13595 int i;
13596 for (i = 0; opt->name[i]; i++)
13597 selected_cpu_name[i] = TOUPPER (opt->name[i]);
13598 selected_cpu_name[i] = 0;
13599 }
13600 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
13601 *input_line_pointer = saved_char;
13602 demand_empty_rest_of_line ();
13603 return;
13604 }
13605 as_bad (_("unknown cpu `%s'"), name);
13606 *input_line_pointer = saved_char;
13607 ignore_rest_of_line ();
13608 }
13609
13610
13611 /* Parse a .arch directive. */
13612
13613 static void
13614 s_arm_arch (int ignored ATTRIBUTE_UNUSED)
13615 {
13616 const struct arm_arch_option_table *opt;
13617 char saved_char;
13618 char *name;
13619
13620 name = input_line_pointer;
13621 while (*input_line_pointer && !ISSPACE(*input_line_pointer))
13622 input_line_pointer++;
13623 saved_char = *input_line_pointer;
13624 *input_line_pointer = 0;
13625
13626 /* Skip the first "all" entry. */
13627 for (opt = arm_archs + 1; opt->name != NULL; opt++)
13628 if (streq (opt->name, name))
13629 {
13630 mcpu_cpu_opt = &opt->value;
13631 selected_cpu = opt->value;
13632 strcpy(selected_cpu_name, opt->name);
13633 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
13634 *input_line_pointer = saved_char;
13635 demand_empty_rest_of_line ();
13636 return;
13637 }
13638
13639 as_bad (_("unknown architecture `%s'\n"), name);
13640 *input_line_pointer = saved_char;
13641 ignore_rest_of_line ();
13642 }
13643
13644
13645 /* Parse a .fpu directive. */
13646
13647 static void
13648 s_arm_fpu (int ignored ATTRIBUTE_UNUSED)
13649 {
13650 const struct arm_option_cpu_value_table *opt;
13651 char saved_char;
13652 char *name;
13653
13654 name = input_line_pointer;
13655 while (*input_line_pointer && !ISSPACE(*input_line_pointer))
13656 input_line_pointer++;
13657 saved_char = *input_line_pointer;
13658 *input_line_pointer = 0;
13659
13660 for (opt = arm_fpus; opt->name != NULL; opt++)
13661 if (streq (opt->name, name))
13662 {
13663 mfpu_opt = &opt->value;
13664 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
13665 *input_line_pointer = saved_char;
13666 demand_empty_rest_of_line ();
13667 return;
13668 }
13669
13670 as_bad (_("unknown floating point format `%s'\n"), name);
13671 *input_line_pointer = saved_char;
13672 ignore_rest_of_line ();
13673 }
13674 #endif /* OBJ_ELF */
13675
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