opcodes/openrisc-desc.c

   1 /* CPU data for openrisc.
   2
   3 THIS FILE IS MACHINE GENERATED WITH CGEN.
   4
   5 Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
   6
   7 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
   8
   9 This program is free software; you can redistribute it and/or modify
  10 it under the terms of the GNU General Public License as published by
  11 the Free Software Foundation; either version 2, or (at your option)
  12 any later version.
  13
  14 This program is distributed in the hope that it will be useful,
  15 but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 GNU General Public License for more details.
  18
  19 You should have received a copy of the GNU General Public License along
  20 with this program; if not, write to the Free Software Foundation, Inc.,
  21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  22
  23 */
  24
  25 #include "sysdep.h"
  26 #include <stdio.h>
  27 #include <stdarg.h>
  28 #include "ansidecl.h"
  29 #include "bfd.h"
  30 #include "symcat.h"
  31 #include "openrisc-desc.h"
  32 #include "openrisc-opc.h"
  33 #include "opintl.h"
  34 #include "libiberty.h"
  35 #include "xregex.h"
  36
  37 /* Attributes.  */
  38
  39 static const CGEN_ATTR_ENTRY bool_attr[] =
  40 {
  41   { "#f", 0 },
  42   { "#t", 1 },
  43   { 0, 0 }
  44 };
  45
  46 static const CGEN_ATTR_ENTRY MACH_attr[] =
  47 {
  48   { "base", MACH_BASE },
  49   { "openrisc", MACH_OPENRISC },
  50   { "or1300", MACH_OR1300 },
  51   { "max", MACH_MAX },
  52   { 0, 0 }
  53 };
  54
  55 static const CGEN_ATTR_ENTRY ISA_attr[] =
  56 {
  57   { "or32", ISA_OR32 },
  58   { "max", ISA_MAX },
  59   { 0, 0 }
  60 };
  61
  62 static const CGEN_ATTR_ENTRY HAS_CACHE_attr[] =
  63 {
  64   { "DATA_CACHE", HAS_CACHE_DATA_CACHE },
  65   { "INSN_CACHE", HAS_CACHE_INSN_CACHE },
  66   { 0, 0 }
  67 };
  68
  69 const CGEN_ATTR_TABLE openrisc_cgen_ifield_attr_table[] =
  70 {
  71   { "MACH", & MACH_attr[0], & MACH_attr[0] },
  72   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
  73   { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
  74   { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
  75   { "RESERVED", &bool_attr[0], &bool_attr[0] },
  76   { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
  77   { "SIGNED", &bool_attr[0], &bool_attr[0] },
  78   { 0, 0, 0 }
  79 };
  80
  81 const CGEN_ATTR_TABLE openrisc_cgen_hardware_attr_table[] =
  82 {
  83   { "MACH", & MACH_attr[0], & MACH_attr[0] },
  84   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
  85   { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
  86   { "PC", &bool_attr[0], &bool_attr[0] },
  87   { "PROFILE", &bool_attr[0], &bool_attr[0] },
  88   { 0, 0, 0 }
  89 };
  90
  91 const CGEN_ATTR_TABLE openrisc_cgen_operand_attr_table[] =
  92 {
  93   { "MACH", & MACH_attr[0], & MACH_attr[0] },
  94   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
  95   { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
  96   { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
  97   { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
  98   { "SIGNED", &bool_attr[0], &bool_attr[0] },
  99   { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
 100   { "RELAX", &bool_attr[0], &bool_attr[0] },
 101   { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
 102   { 0, 0, 0 }
 103 };
 104
 105 const CGEN_ATTR_TABLE openrisc_cgen_insn_attr_table[] =
 106 {
 107   { "MACH", & MACH_attr[0], & MACH_attr[0] },
 108   { "ALIAS", &bool_attr[0], &bool_attr[0] },
 109   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
 110   { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
 111   { "COND-CTI", &bool_attr[0], &bool_attr[0] },
 112   { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
 113   { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
 114   { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
 115   { "RELAX", &bool_attr[0], &bool_attr[0] },
 116   { "NO-DIS", &bool_attr[0], &bool_attr[0] },
 117   { "PBB", &bool_attr[0], &bool_attr[0] },
 118   { "NOT-IN-DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
 119   { 0, 0, 0 }
 120 };
 121
 122 /* Instruction set variants.  */
 123
 124 static const CGEN_ISA openrisc_cgen_isa_table[] = {
 125   { "or32", 32, 32, 32, 32 },
 126   { 0, 0, 0, 0, 0 }
 127 };
 128
 129 /* Machine variants.  */
 130
 131 static const CGEN_MACH openrisc_cgen_mach_table[] = {
 132   { "openrisc", "openrisc", MACH_OPENRISC, 0 },
 133   { "or1300", "openrisc:1300", MACH_OR1300, 0 },
 134   { 0, 0, 0, 0 }
 135 };
 136
 137 static CGEN_KEYWORD_ENTRY openrisc_cgen_opval_h_gr_entries[] =
 138 {
 139   { "r0", 0, {0, {0}}, 0, 0 },
 140   { "r1", 1, {0, {0}}, 0, 0 },
 141   { "r2", 2, {0, {0}}, 0, 0 },
 142   { "r3", 3, {0, {0}}, 0, 0 },
 143   { "r4", 4, {0, {0}}, 0, 0 },
 144   { "r5", 5, {0, {0}}, 0, 0 },
 145   { "r6", 6, {0, {0}}, 0, 0 },
 146   { "r7", 7, {0, {0}}, 0, 0 },
 147   { "r8", 8, {0, {0}}, 0, 0 },
 148   { "r9", 9, {0, {0}}, 0, 0 },
 149   { "r10", 10, {0, {0}}, 0, 0 },
 150   { "r11", 11, {0, {0}}, 0, 0 },
 151   { "r12", 12, {0, {0}}, 0, 0 },
 152   { "r13", 13, {0, {0}}, 0, 0 },
 153   { "r14", 14, {0, {0}}, 0, 0 },
 154   { "r15", 15, {0, {0}}, 0, 0 },
 155   { "r16", 16, {0, {0}}, 0, 0 },
 156   { "r17", 17, {0, {0}}, 0, 0 },
 157   { "r18", 18, {0, {0}}, 0, 0 },
 158   { "r19", 19, {0, {0}}, 0, 0 },
 159   { "r20", 20, {0, {0}}, 0, 0 },
 160   { "r21", 21, {0, {0}}, 0, 0 },
 161   { "r22", 22, {0, {0}}, 0, 0 },
 162   { "r23", 23, {0, {0}}, 0, 0 },
 163   { "r24", 24, {0, {0}}, 0, 0 },
 164   { "r25", 25, {0, {0}}, 0, 0 },
 165   { "r26", 26, {0, {0}}, 0, 0 },
 166   { "r27", 27, {0, {0}}, 0, 0 },
 167   { "r28", 28, {0, {0}}, 0, 0 },
 168   { "r29", 29, {0, {0}}, 0, 0 },
 169   { "r30", 30, {0, {0}}, 0, 0 },
 170   { "r31", 31, {0, {0}}, 0, 0 },
 171   { "lr", 11, {0, {0}}, 0, 0 },
 172   { "sp", 1, {0, {0}}, 0, 0 },
 173   { "fp", 2, {0, {0}}, 0, 0 }
 174 };
 175
 176 CGEN_KEYWORD openrisc_cgen_opval_h_gr =
 177 {
 178   & openrisc_cgen_opval_h_gr_entries[0],
 179   35,
 180   0, 0, 0, 0, ""
 181 };
 182
 183
 184 /* The hardware table.  */
 185
 186 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
 187 #define A(a) (1 << CGEN_HW_##a)
 188 #else
 189 #define A(a) (1 << CGEN_HW_/**/a)
 190 #endif
 191
 192 const CGEN_HW_ENTRY openrisc_cgen_hw_table[] =
 193 {
 194   { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 195   { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 196   { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 197   { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 198   { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 199   { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { (1<<MACH_BASE) } } },
 200   { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & openrisc_cgen_opval_h_gr, { 0|A(PROFILE), { (1<<MACH_BASE) } } },
 201   { "h-sr", HW_H_SR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 202   { "h-hi16", HW_H_HI16, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 203   { "h-lo16", HW_H_LO16, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 204   { "h-cbit", HW_H_CBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 205   { "h-delay-insn", HW_H_DELAY_INSN, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 206   { 0, 0, CGEN_ASM_NONE, 0, {0, {0}} }
 207 };
 208
 209 #undef A
 210
 211
 212 /* The instruction field table.  */
 213
 214 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
 215 #define A(a) (1 << CGEN_IFLD_##a)
 216 #else
 217 #define A(a) (1 << CGEN_IFLD_/**/a)
 218 #endif
 219
 220 const CGEN_IFLD openrisc_cgen_ifld_table[] =
 221 {
 222   { OPENRISC_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } }  },
 223   { OPENRISC_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } }  },
 224   { OPENRISC_F_CLASS, "f-class", 0, 32, 31, 2, { 0, { (1<<MACH_BASE) } }  },
 225   { OPENRISC_F_SUB, "f-sub", 0, 32, 29, 4, { 0, { (1<<MACH_BASE) } }  },
 226   { OPENRISC_F_R1, "f-r1", 0, 32, 25, 5, { 0, { (1<<MACH_BASE) } }  },
 227   { OPENRISC_F_R2, "f-r2", 0, 32, 20, 5, { 0, { (1<<MACH_BASE) } }  },
 228   { OPENRISC_F_R3, "f-r3", 0, 32, 15, 5, { 0, { (1<<MACH_BASE) } }  },
 229   { OPENRISC_F_SIMM16, "f-simm16", 0, 32, 15, 16, { 0, { (1<<MACH_BASE) } }  },
 230   { OPENRISC_F_UIMM16, "f-uimm16", 0, 32, 15, 16, { 0, { (1<<MACH_BASE) } }  },
 231   { OPENRISC_F_UIMM5, "f-uimm5", 0, 32, 4, 5, { 0, { (1<<MACH_BASE) } }  },
 232   { OPENRISC_F_HI16, "f-hi16", 0, 32, 15, 16, { 0, { (1<<MACH_BASE) } }  },
 233   { OPENRISC_F_LO16, "f-lo16", 0, 32, 15, 16, { 0, { (1<<MACH_BASE) } }  },
 234   { OPENRISC_F_OP1, "f-op1", 0, 32, 31, 2, { 0, { (1<<MACH_BASE) } }  },
 235   { OPENRISC_F_OP2, "f-op2", 0, 32, 29, 4, { 0, { (1<<MACH_BASE) } }  },
 236   { OPENRISC_F_OP3, "f-op3", 0, 32, 25, 2, { 0, { (1<<MACH_BASE) } }  },
 237   { OPENRISC_F_OP4, "f-op4", 0, 32, 23, 3, { 0, { (1<<MACH_BASE) } }  },
 238   { OPENRISC_F_OP5, "f-op5", 0, 32, 25, 5, { 0, { (1<<MACH_BASE) } }  },
 239   { OPENRISC_F_OP6, "f-op6", 0, 32, 7, 3, { 0, { (1<<MACH_BASE) } }  },
 240   { OPENRISC_F_OP7, "f-op7", 0, 32, 3, 4, { 0, { (1<<MACH_BASE) } }  },
 241   { OPENRISC_F_I16_1, "f-i16-1", 0, 32, 10, 11, { 0, { (1<<MACH_BASE) } }  },
 242   { OPENRISC_F_I16_2, "f-i16-2", 0, 32, 25, 5, { 0, { (1<<MACH_BASE) } }  },
 243   { OPENRISC_F_DISP26, "f-disp26", 0, 32, 25, 26, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
 244   { OPENRISC_F_ABS26, "f-abs26", 0, 32, 25, 26, { 0|A(ABS_ADDR), { (1<<MACH_BASE) } }  },
 245   { OPENRISC_F_F_15_8, "f-f-15-8", 0, 32, 15, 8, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
 246   { OPENRISC_F_F_10_3, "f-f-10-3", 0, 32, 10, 3, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
 247   { OPENRISC_F_F_4_1, "f-f-4-1", 0, 32, 4, 1, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
 248   { OPENRISC_F_F_7_3, "f-f-7-3", 0, 32, 7, 3, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
 249   { OPENRISC_F_F_10_7, "f-f-10-7", 0, 32, 10, 7, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
 250   { OPENRISC_F_F_10_11, "f-f-10-11", 0, 32, 10, 11, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
 251   { 0, 0, 0, 0, 0, 0, {0, {0}} }
 252 };
 253
 254 #undef A
 255
 256
 257
 258 /* multi ifield declarations */
 259
 260 const CGEN_MAYBE_MULTI_IFLD OPENRISC_F_I16NC_MULTI_IFIELD [];
 261
 262
 263 /* multi ifield definitions */
 264
 265 const CGEN_MAYBE_MULTI_IFLD OPENRISC_F_I16NC_MULTI_IFIELD [] =
 266 {
 267     { 0, { (const PTR) &openrisc_cgen_ifld_table[19] } },
 268     { 0, { (const PTR) &openrisc_cgen_ifld_table[20] } },
 269     { 0, { (const PTR) 0 } }
 270 };
 271
 272 /* The operand table.  */
 273
 274 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
 275 #define A(a) (1 << CGEN_OPERAND_##a)
 276 #else
 277 #define A(a) (1 << CGEN_OPERAND_/**/a)
 278 #endif
 279 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
 280 #define OPERAND(op) OPENRISC_OPERAND_##op
 281 #else
 282 #define OPERAND(op) OPENRISC_OPERAND_/**/op
 283 #endif
 284
 285 const CGEN_OPERAND openrisc_cgen_operand_table[] =
 286 {
 287 /* pc: program counter */
 288   { "pc", OPENRISC_OPERAND_PC, HW_H_PC, 0, 0,
 289     { 0, { (const PTR) &openrisc_cgen_ifld_table[0] } },
 290     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
 291 /* sr: special register */
 292   { "sr", OPENRISC_OPERAND_SR, HW_H_SR, 0, 0,
 293     { 0, { (const PTR) 0 } },
 294     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
 295 /* cbit: condition bit */
 296   { "cbit", OPENRISC_OPERAND_CBIT, HW_H_CBIT, 0, 0,
 297     { 0, { (const PTR) 0 } },
 298     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
 299 /* simm-16: 16 bit signed immediate */
 300   { "simm-16", OPENRISC_OPERAND_SIMM_16, HW_H_SINT, 15, 16,
 301     { 0, { (const PTR) &openrisc_cgen_ifld_table[7] } },
 302     { 0, { (1<<MACH_BASE) } }  },
 303 /* uimm-16: 16 bit unsigned immediate */
 304   { "uimm-16", OPENRISC_OPERAND_UIMM_16, HW_H_UINT, 15, 16,
 305     { 0, { (const PTR) &openrisc_cgen_ifld_table[8] } },
 306     { 0, { (1<<MACH_BASE) } }  },
 307 /* disp-26: pc-rel 26 bit */
 308   { "disp-26", OPENRISC_OPERAND_DISP_26, HW_H_IADDR, 25, 26,
 309     { 0, { (const PTR) &openrisc_cgen_ifld_table[21] } },
 310     { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
 311 /* abs-26: abs 26 bit */
 312   { "abs-26", OPENRISC_OPERAND_ABS_26, HW_H_IADDR, 25, 26,
 313     { 0, { (const PTR) &openrisc_cgen_ifld_table[22] } },
 314     { 0|A(ABS_ADDR), { (1<<MACH_BASE) } }  },
 315 /* uimm-5: imm5 */
 316   { "uimm-5", OPENRISC_OPERAND_UIMM_5, HW_H_UINT, 4, 5,
 317     { 0, { (const PTR) &openrisc_cgen_ifld_table[9] } },
 318     { 0, { (1<<MACH_BASE) } }  },
 319 /* rD: destination register */
 320   { "rD", OPENRISC_OPERAND_RD, HW_H_GR, 25, 5,
 321     { 0, { (const PTR) &openrisc_cgen_ifld_table[4] } },
 322     { 0, { (1<<MACH_BASE) } }  },
 323 /* rA: source register A */
 324   { "rA", OPENRISC_OPERAND_RA, HW_H_GR, 20, 5,
 325     { 0, { (const PTR) &openrisc_cgen_ifld_table[5] } },
 326     { 0, { (1<<MACH_BASE) } }  },
 327 /* rB: source register B */
 328   { "rB", OPENRISC_OPERAND_RB, HW_H_GR, 15, 5,
 329     { 0, { (const PTR) &openrisc_cgen_ifld_table[6] } },
 330     { 0, { (1<<MACH_BASE) } }  },
 331 /* op-f-23: f-op23 */
 332   { "op-f-23", OPENRISC_OPERAND_OP_F_23, HW_H_UINT, 23, 3,
 333     { 0, { (const PTR) &openrisc_cgen_ifld_table[15] } },
 334     { 0, { (1<<MACH_BASE) } }  },
 335 /* op-f-3: f-op3 */
 336   { "op-f-3", OPENRISC_OPERAND_OP_F_3, HW_H_UINT, 25, 5,
 337     { 0, { (const PTR) &openrisc_cgen_ifld_table[16] } },
 338     { 0, { (1<<MACH_BASE) } }  },
 339 /* hi16: high 16 bit immediate, sign optional */
 340   { "hi16", OPENRISC_OPERAND_HI16, HW_H_HI16, 15, 16,
 341     { 0, { (const PTR) &openrisc_cgen_ifld_table[7] } },
 342     { 0|A(SIGN_OPT), { (1<<MACH_BASE) } }  },
 343 /* lo16: low 16 bit immediate, sign optional */
 344   { "lo16", OPENRISC_OPERAND_LO16, HW_H_LO16, 15, 16,
 345     { 0, { (const PTR) &openrisc_cgen_ifld_table[11] } },
 346     { 0|A(SIGN_OPT), { (1<<MACH_BASE) } }  },
 347 /* ui16nc: 16 bit immediate, sign optional */
 348   { "ui16nc", OPENRISC_OPERAND_UI16NC, HW_H_LO16, 10, 16,
 349     { 2, { (const PTR) &OPENRISC_F_I16NC_MULTI_IFIELD[0] } },
 350     { 0|A(SIGN_OPT)|A(VIRTUAL), { (1<<MACH_BASE) } }  },
 351 /* sentinel */
 352   { 0, 0, 0, 0, 0,
 353     { 0, { (const PTR) 0 } },
 354     { 0, { 0 } } }
 355 };
 356
 357 #undef A
 358
 359
 360 /* The instruction table.  */
 361
 362 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
 363 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
 364 #define A(a) (1 << CGEN_INSN_##a)
 365 #else
 366 #define A(a) (1 << CGEN_INSN_/**/a)
 367 #endif
 368
 369 static const CGEN_IBASE openrisc_cgen_insn_table[MAX_INSNS] =
 370 {
 371   /* Special null first entry.
 372      A `num' value of zero is thus invalid.
 373      Also, the special `invalid' insn resides here.  */
 374   { 0, 0, 0, 0, {0, {0}} },
 375 /* l.j ${abs-26} */
 376   {
 377     OPENRISC_INSN_L_J, "l-j", "l.j", 32,
 378     { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
 379   },
 380 /* l.jal ${abs-26} */
 381   {
 382     OPENRISC_INSN_L_JAL, "l-jal", "l.jal", 32,
 383     { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
 384   },
 385 /* l.jr $rA */
 386   {
 387     OPENRISC_INSN_L_JR, "l-jr", "l.jr", 32,
 388     { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
 389   },
 390 /* l.jalr $rA */
 391   {
 392     OPENRISC_INSN_L_JALR, "l-jalr", "l.jalr", 32,
 393     { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
 394   },
 395 /* l.bal ${disp-26} */
 396   {
 397     OPENRISC_INSN_L_BAL, "l-bal", "l.bal", 32,
 398     { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
 399   },
 400 /* l.bnf ${disp-26} */
 401   {
 402     OPENRISC_INSN_L_BNF, "l-bnf", "l.bnf", 32,
 403     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
 404   },
 405 /* l.bf ${disp-26} */
 406   {
 407     OPENRISC_INSN_L_BF, "l-bf", "l.bf", 32,
 408     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
 409   },
 410 /* l.brk ${uimm-16} */
 411   {
 412     OPENRISC_INSN_L_BRK, "l-brk", "l.brk", 32,
 413     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
 414   },
 415 /* l.rfe $rA */
 416   {
 417     OPENRISC_INSN_L_RFE, "l-rfe", "l.rfe", 32,
 418     { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
 419   },
 420 /* l.sys ${uimm-16} */
 421   {
 422     OPENRISC_INSN_L_SYS, "l-sys", "l.sys", 32,
 423     { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
 424   },
 425 /* l.nop */
 426   {
 427     OPENRISC_INSN_L_NOP, "l-nop", "l.nop", 32,
 428     { 0, { (1<<MACH_BASE) } }
 429   },
 430 /* l.movhi $rD,$hi16 */
 431   {
 432     OPENRISC_INSN_L_MOVHI, "l-movhi", "l.movhi", 32,
 433     { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } }
 434   },
 435 /* l.mfsr $rD,$rA */
 436   {
 437     OPENRISC_INSN_L_MFSR, "l-mfsr", "l.mfsr", 32,
 438     { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } }
 439   },
 440 /* l.mtsr $rA,$rB */
 441   {
 442     OPENRISC_INSN_L_MTSR, "l-mtsr", "l.mtsr", 32,
 443     { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } }
 444   },
 445 /* l.lw $rD,${simm-16}($rA) */
 446   {
 447     OPENRISC_INSN_L_LW, "l-lw", "l.lw", 32,
 448     { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } }
 449   },
 450 /* l.lbz $rD,${simm-16}($rA) */
 451   {
 452     OPENRISC_INSN_L_LBZ, "l-lbz", "l.lbz", 32,
 453     { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } }
 454   },
 455 /* l.lbs $rD,${simm-16}($rA) */
 456   {
 457     OPENRISC_INSN_L_LBS, "l-lbs", "l.lbs", 32,
 458     { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } }
 459   },
 460 /* l.lhz $rD,${simm-16}($rA) */
 461   {
 462     OPENRISC_INSN_L_LHZ, "l-lhz", "l.lhz", 32,
 463     { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } }
 464   },
 465 /* l.lhs $rD,${simm-16}($rA) */
 466   {
 467     OPENRISC_INSN_L_LHS, "l-lhs", "l.lhs", 32,
 468     { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } }
 469   },
 470 /* l.sw ${ui16nc}($rA),$rB */
 471   {
 472     OPENRISC_INSN_L_SW, "l-sw", "l.sw", 32,
 473     { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } }
 474   },
 475 /* l.sb ${ui16nc}($rA),$rB */
 476   {
 477     OPENRISC_INSN_L_SB, "l-sb", "l.sb", 32,
 478     { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } }
 479   },
 480 /* l.sh ${ui16nc}($rA),$rB */
 481   {
 482     OPENRISC_INSN_L_SH, "l-sh", "l.sh", 32,
 483     { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } }
 484   },
 485 /* l.sll $rD,$rA,$rB */
 486   {
 487     OPENRISC_INSN_L_SLL, "l-sll", "l.sll", 32,
 488     { 0, { (1<<MACH_BASE) } }
 489   },
 490 /* l.slli $rD,$rA,${uimm-5} */
 491   {
 492     OPENRISC_INSN_L_SLLI, "l-slli", "l.slli", 32,
 493     { 0, { (1<<MACH_BASE) } }
 494   },
 495 /* l.srl $rD,$rA,$rB */
 496   {
 497     OPENRISC_INSN_L_SRL, "l-srl", "l.srl", 32,
 498     { 0, { (1<<MACH_BASE) } }
 499   },
 500 /* l.srli $rD,$rA,${uimm-5} */
 501   {
 502     OPENRISC_INSN_L_SRLI, "l-srli", "l.srli", 32,
 503     { 0, { (1<<MACH_BASE) } }
 504   },
 505 /* l.sra $rD,$rA,$rB */
 506   {
 507     OPENRISC_INSN_L_SRA, "l-sra", "l.sra", 32,
 508     { 0, { (1<<MACH_BASE) } }
 509   },
 510 /* l.srai $rD,$rA,${uimm-5} */
 511   {
 512     OPENRISC_INSN_L_SRAI, "l-srai", "l.srai", 32,
 513     { 0, { (1<<MACH_BASE) } }
 514   },
 515 /* l.ror $rD,$rA,$rB */
 516   {
 517     OPENRISC_INSN_L_ROR, "l-ror", "l.ror", 32,
 518     { 0, { (1<<MACH_BASE) } }
 519   },
 520 /* l.rori $rD,$rA,${uimm-5} */
 521   {
 522     OPENRISC_INSN_L_RORI, "l-rori", "l.rori", 32,
 523     { 0, { (1<<MACH_BASE) } }
 524   },
 525 /* l.add $rD,$rA,$rB */
 526   {
 527     OPENRISC_INSN_L_ADD, "l-add", "l.add", 32,
 528     { 0, { (1<<MACH_BASE) } }
 529   },
 530 /* l.addi $rD,$rA,$lo16 */
 531   {
 532     OPENRISC_INSN_L_ADDI, "l-addi", "l.addi", 32,
 533     { 0, { (1<<MACH_BASE) } }
 534   },
 535 /* l.sub $rD,$rA,$rB */
 536   {
 537     OPENRISC_INSN_L_SUB, "l-sub", "l.sub", 32,
 538     { 0, { (1<<MACH_BASE) } }
 539   },
 540 /* l.subi $rD,$rA,$lo16 */
 541   {
 542     OPENRISC_INSN_L_SUBI, "l-subi", "l.subi", 32,
 543     { 0, { (1<<MACH_BASE) } }
 544   },
 545 /* l.and $rD,$rA,$rB */
 546   {
 547     OPENRISC_INSN_L_AND, "l-and", "l.and", 32,
 548     { 0, { (1<<MACH_BASE) } }
 549   },
 550 /* l.andi $rD,$rA,$lo16 */
 551   {
 552     OPENRISC_INSN_L_ANDI, "l-andi", "l.andi", 32,
 553     { 0, { (1<<MACH_BASE) } }
 554   },
 555 /* l.or $rD,$rA,$rB */
 556   {
 557     OPENRISC_INSN_L_OR, "l-or", "l.or", 32,
 558     { 0, { (1<<MACH_BASE) } }
 559   },
 560 /* l.ori $rD,$rA,$lo16 */
 561   {
 562     OPENRISC_INSN_L_ORI, "l-ori", "l.ori", 32,
 563     { 0, { (1<<MACH_BASE) } }
 564   },
 565 /* l.xor $rD,$rA,$rB */
 566   {
 567     OPENRISC_INSN_L_XOR, "l-xor", "l.xor", 32,
 568     { 0, { (1<<MACH_BASE) } }
 569   },
 570 /* l.xori $rD,$rA,$lo16 */
 571   {
 572     OPENRISC_INSN_L_XORI, "l-xori", "l.xori", 32,
 573     { 0, { (1<<MACH_BASE) } }
 574   },
 575 /* l.mul $rD,$rA,$rB */
 576   {
 577     OPENRISC_INSN_L_MUL, "l-mul", "l.mul", 32,
 578     { 0, { (1<<MACH_BASE) } }
 579   },
 580 /* l.muli $rD,$rA,$lo16 */
 581   {
 582     OPENRISC_INSN_L_MULI, "l-muli", "l.muli", 32,
 583     { 0, { (1<<MACH_BASE) } }
 584   },
 585 /* l.div $rD,$rA,$rB */
 586   {
 587     OPENRISC_INSN_L_DIV, "l-div", "l.div", 32,
 588     { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } }
 589   },
 590 /* l.divu $rD,$rA,$rB */
 591   {
 592     OPENRISC_INSN_L_DIVU, "l-divu", "l.divu", 32,
 593     { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } }
 594   },
 595 /* l.sfgts $rA,$rB */
 596   {
 597     OPENRISC_INSN_L_SFGTS, "l-sfgts", "l.sfgts", 32,
 598     { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } }
 599   },
 600 /* l.sfgtu $rA,$rB */
 601   {
 602     OPENRISC_INSN_L_SFGTU, "l-sfgtu", "l.sfgtu", 32,
 603     { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } }
 604   },
 605 /* l.sfges $rA,$rB */
 606   {
 607     OPENRISC_INSN_L_SFGES, "l-sfges", "l.sfges", 32,
 608     { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } }
 609   },
 610 /* l.sfgeu $rA,$rB */
 611   {
 612     OPENRISC_INSN_L_SFGEU, "l-sfgeu", "l.sfgeu", 32,
 613     { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } }
 614   },
 615 /* l.sflts $rA,$rB */
 616   {
 617     OPENRISC_INSN_L_SFLTS, "l-sflts", "l.sflts", 32,
 618     { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } }
 619   },
 620 /* l.sfltu $rA,$rB */
 621   {
 622     OPENRISC_INSN_L_SFLTU, "l-sfltu", "l.sfltu", 32,
 623     { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } }
 624   },
 625 /* l.sfles $rA,$rB */
 626   {
 627     OPENRISC_INSN_L_SFLES, "l-sfles", "l.sfles", 32,
 628     { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } }
 629   },
 630 /* l.sfleu $rA,$rB */
 631   {
 632     OPENRISC_INSN_L_SFLEU, "l-sfleu", "l.sfleu", 32,
 633     { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } }
 634   },
 635 /* l.sfgtsi $rA,${simm-16} */
 636   {
 637     OPENRISC_INSN_L_SFGTSI, "l-sfgtsi", "l.sfgtsi", 32,
 638     { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } }
 639   },
 640 /* l.sfgtui $rA,${uimm-16} */
 641   {
 642     OPENRISC_INSN_L_SFGTUI, "l-sfgtui", "l.sfgtui", 32,
 643     { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } }
 644   },
 645 /* l.sfgesi $rA,${simm-16} */
 646   {
 647     OPENRISC_INSN_L_SFGESI, "l-sfgesi", "l.sfgesi", 32,
 648     { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } }
 649   },
 650 /* l.sfgeui $rA,${uimm-16} */
 651   {
 652     OPENRISC_INSN_L_SFGEUI, "l-sfgeui", "l.sfgeui", 32,
 653     { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } }
 654   },
 655 /* l.sfltsi $rA,${simm-16} */
 656   {
 657     OPENRISC_INSN_L_SFLTSI, "l-sfltsi", "l.sfltsi", 32,
 658     { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } }
 659   },
 660 /* l.sfltui $rA,${uimm-16} */
 661   {
 662     OPENRISC_INSN_L_SFLTUI, "l-sfltui", "l.sfltui", 32,
 663     { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } }
 664   },
 665 /* l.sflesi $rA,${simm-16} */
 666   {
 667     OPENRISC_INSN_L_SFLESI, "l-sflesi", "l.sflesi", 32,
 668     { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } }
 669   },
 670 /* l.sfleui $rA,${uimm-16} */
 671   {
 672     OPENRISC_INSN_L_SFLEUI, "l-sfleui", "l.sfleui", 32,
 673     { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } }
 674   },
 675 /* l.sfeq $rA,$rB */
 676   {
 677     OPENRISC_INSN_L_SFEQ, "l-sfeq", "l.sfeq", 32,
 678     { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } }
 679   },
 680 /* l.sfeqi $rA,${simm-16} */
 681   {
 682     OPENRISC_INSN_L_SFEQI, "l-sfeqi", "l.sfeqi", 32,
 683     { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } }
 684   },
 685 /* l.sfne $rA,$rB */
 686   {
 687     OPENRISC_INSN_L_SFNE, "l-sfne", "l.sfne", 32,
 688     { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } }
 689   },
 690 /* l.sfnei $rA,${simm-16} */
 691   {
 692     OPENRISC_INSN_L_SFNEI, "l-sfnei", "l.sfnei", 32,
 693     { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } }
 694   },
 695 };
 696
 697 #undef OP
 698 #undef A
 699
 700 /* Initialize anything needed to be done once, before any cpu_open call.  */
 701 static void init_tables PARAMS ((void));
 702
 703 static void
 704 init_tables ()
 705 {
 706 }
 707
 708 static const CGEN_MACH * lookup_mach_via_bfd_name
 709   PARAMS ((const CGEN_MACH *, const char *));
 710 static void build_hw_table  PARAMS ((CGEN_CPU_TABLE *));
 711 static void build_ifield_table  PARAMS ((CGEN_CPU_TABLE *));
 712 static void build_operand_table PARAMS ((CGEN_CPU_TABLE *));
 713 static void build_insn_table    PARAMS ((CGEN_CPU_TABLE *));
 714 static void openrisc_cgen_rebuild_tables PARAMS ((CGEN_CPU_TABLE *));
 715
 716 /* Subroutine of openrisc_cgen_cpu_open to look up a mach via its bfd name.  */
 717
 718 static const CGEN_MACH *
 719 lookup_mach_via_bfd_name (table, name)
 720      const CGEN_MACH *table;
 721      const char *name;
 722 {
 723   while (table->name)
 724     {
 725       if (strcmp (name, table->bfd_name) == 0)
 726         return table;
 727       ++table;
 728     }
 729   abort ();
 730 }
 731
 732 /* Subroutine of openrisc_cgen_cpu_open to build the hardware table.  */
 733
 734 static void
 735 build_hw_table (cd)
 736      CGEN_CPU_TABLE *cd;
 737 {
 738   int i;
 739   int machs = cd->machs;
 740   const CGEN_HW_ENTRY *init = & openrisc_cgen_hw_table[0];
 741   /* MAX_HW is only an upper bound on the number of selected entries.
 742      However each entry is indexed by it's enum so there can be holes in
 743      the table.  */
 744   const CGEN_HW_ENTRY **selected =
 745     (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
 746
 747   cd->hw_table.init_entries = init;
 748   cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
 749   memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
 750   /* ??? For now we just use machs to determine which ones we want.  */
 751   for (i = 0; init[i].name != NULL; ++i)
 752     if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
 753         & machs)
 754       selected[init[i].type] = &init[i];
 755   cd->hw_table.entries = selected;
 756   cd->hw_table.num_entries = MAX_HW;
 757 }
 758
 759 /* Subroutine of openrisc_cgen_cpu_open to build the hardware table.  */
 760
 761 static void
 762 build_ifield_table (cd)
 763      CGEN_CPU_TABLE *cd;
 764 {
 765   cd->ifld_table = & openrisc_cgen_ifld_table[0];
 766 }
 767
 768 /* Subroutine of openrisc_cgen_cpu_open to build the hardware table.  */
 769
 770 static void
 771 build_operand_table (cd)
 772      CGEN_CPU_TABLE *cd;
 773 {
 774   int i;
 775   int machs = cd->machs;
 776   const CGEN_OPERAND *init = & openrisc_cgen_operand_table[0];
 777   /* MAX_OPERANDS is only an upper bound on the number of selected entries.
 778      However each entry is indexed by it's enum so there can be holes in
 779      the table.  */
 780   const CGEN_OPERAND **selected =
 781     (const CGEN_OPERAND **) xmalloc (MAX_OPERANDS * sizeof (CGEN_OPERAND *));
 782
 783   cd->operand_table.init_entries = init;
 784   cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
 785   memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
 786   /* ??? For now we just use mach to determine which ones we want.  */
 787   for (i = 0; init[i].name != NULL; ++i)
 788     if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
 789         & machs)
 790       selected[init[i].type] = &init[i];
 791   cd->operand_table.entries = selected;
 792   cd->operand_table.num_entries = MAX_OPERANDS;
 793 }
 794
 795 /* Subroutine of openrisc_cgen_cpu_open to build the hardware table.
 796    ??? This could leave out insns not supported by the specified mach/isa,
 797    but that would cause errors like "foo only supported by bar" to become
 798    "unknown insn", so for now we include all insns and require the app to
 799    do the checking later.
 800    ??? On the other hand, parsing of such insns may require their hardware or
 801    operand elements to be in the table [which they mightn't be].  */
 802
 803 static void
 804 build_insn_table (cd)
 805      CGEN_CPU_TABLE *cd;
 806 {
 807   int i;
 808   const CGEN_IBASE *ib = & openrisc_cgen_insn_table[0];
 809   CGEN_INSN *insns = (CGEN_INSN *) xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
 810
 811   memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
 812   for (i = 0; i < MAX_INSNS; ++i)
 813     insns[i].base = &ib[i];
 814   cd->insn_table.init_entries = insns;
 815   cd->insn_table.entry_size = sizeof (CGEN_IBASE);
 816   cd->insn_table.num_init_entries = MAX_INSNS;
 817 }
 818
 819 /* Subroutine of openrisc_cgen_cpu_open to rebuild the tables.  */
 820
 821 static void
 822 openrisc_cgen_rebuild_tables (cd)
 823      CGEN_CPU_TABLE *cd;
 824 {
 825   int i;
 826   unsigned int isas = cd->isas;
 827   unsigned int machs = cd->machs;
 828
 829   cd->int_insn_p = CGEN_INT_INSN_P;
 830
 831   /* Data derived from the isa spec.  */
 832 #define UNSET (CGEN_SIZE_UNKNOWN + 1)
 833   cd->default_insn_bitsize = UNSET;
 834   cd->base_insn_bitsize = UNSET;
 835   cd->min_insn_bitsize = 65535; /* some ridiculously big number */
 836   cd->max_insn_bitsize = 0;
 837   for (i = 0; i < MAX_ISAS; ++i)
 838     if (((1 << i) & isas) != 0)
 839       {
 840         const CGEN_ISA *isa = & openrisc_cgen_isa_table[i];
 841
 842         /* Default insn sizes of all selected isas must be
 843            equal or we set the result to 0, meaning "unknown".  */
 844         if (cd->default_insn_bitsize == UNSET)
 845           cd->default_insn_bitsize = isa->default_insn_bitsize;
 846         else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
 847           ; /* this is ok */
 848         else
 849           cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
 850
 851         /* Base insn sizes of all selected isas must be equal
 852            or we set the result to 0, meaning "unknown".  */
 853         if (cd->base_insn_bitsize == UNSET)
 854           cd->base_insn_bitsize = isa->base_insn_bitsize;
 855         else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
 856           ; /* this is ok */
 857         else
 858           cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
 859
 860         /* Set min,max insn sizes.  */
 861         if (isa->min_insn_bitsize < cd->min_insn_bitsize)
 862           cd->min_insn_bitsize = isa->min_insn_bitsize;
 863         if (isa->max_insn_bitsize > cd->max_insn_bitsize)
 864           cd->max_insn_bitsize = isa->max_insn_bitsize;
 865       }
 866
 867   /* Data derived from the mach spec.  */
 868   for (i = 0; i < MAX_MACHS; ++i)
 869     if (((1 << i) & machs) != 0)
 870       {
 871         const CGEN_MACH *mach = & openrisc_cgen_mach_table[i];
 872
 873         if (mach->insn_chunk_bitsize != 0)
 874         {
 875           if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
 876             {
 877               fprintf (stderr, "openrisc_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n",
 878                        cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
 879               abort ();
 880             }
 881
 882           cd->insn_chunk_bitsize = mach->insn_chunk_bitsize;
 883         }
 884       }
 885
 886   /* Determine which hw elements are used by MACH.  */
 887   build_hw_table (cd);
 888
 889   /* Build the ifield table.  */
 890   build_ifield_table (cd);
 891
 892   /* Determine which operands are used by MACH/ISA.  */
 893   build_operand_table (cd);
 894
 895   /* Build the instruction table.  */
 896   build_insn_table (cd);
 897 }
 898
 899 /* Initialize a cpu table and return a descriptor.
 900    It's much like opening a file, and must be the first function called.
 901    The arguments are a set of (type/value) pairs, terminated with
 902    CGEN_CPU_OPEN_END.
 903
 904    Currently supported values:
 905    CGEN_CPU_OPEN_ISAS:    bitmap of values in enum isa_attr
 906    CGEN_CPU_OPEN_MACHS:   bitmap of values in enum mach_attr
 907    CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
 908    CGEN_CPU_OPEN_ENDIAN:  specify endian choice
 909    CGEN_CPU_OPEN_END:     terminates arguments
 910
 911    ??? Simultaneous multiple isas might not make sense, but it's not (yet)
 912    precluded.
 913
 914    ??? We only support ISO C stdargs here, not K&R.
 915    Laziness, plus experiment to see if anything requires K&R - eventually
 916    K&R will no longer be supported - e.g. GDB is currently trying this.  */
 917
 918 CGEN_CPU_DESC
 919 openrisc_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
 920 {
 921   CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
 922   static int init_p;
 923   unsigned int isas = 0;  /* 0 = "unspecified" */
 924   unsigned int machs = 0; /* 0 = "unspecified" */
 925   enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
 926   va_list ap;
 927
 928   if (! init_p)
 929     {
 930       init_tables ();
 931       init_p = 1;
 932     }
 933
 934   memset (cd, 0, sizeof (*cd));
 935
 936   va_start (ap, arg_type);
 937   while (arg_type != CGEN_CPU_OPEN_END)
 938     {
 939       switch (arg_type)
 940         {
 941         case CGEN_CPU_OPEN_ISAS :
 942           isas = va_arg (ap, unsigned int);
 943           break;
 944         case CGEN_CPU_OPEN_MACHS :
 945           machs = va_arg (ap, unsigned int);
 946           break;
 947         case CGEN_CPU_OPEN_BFDMACH :
 948           {
 949             const char *name = va_arg (ap, const char *);
 950             const CGEN_MACH *mach =
 951               lookup_mach_via_bfd_name (openrisc_cgen_mach_table, name);
 952
 953             machs |= 1 << mach->num;
 954             break;
 955           }
 956         case CGEN_CPU_OPEN_ENDIAN :
 957           endian = va_arg (ap, enum cgen_endian);
 958           break;
 959         default :
 960           fprintf (stderr, "openrisc_cgen_cpu_open: unsupported argument `%d'\n",
 961                    arg_type);
 962           abort (); /* ??? return NULL? */
 963         }
 964       arg_type = va_arg (ap, enum cgen_cpu_open_arg);
 965     }
 966   va_end (ap);
 967
 968   /* mach unspecified means "all" */
 969   if (machs == 0)
 970     machs = (1 << MAX_MACHS) - 1;
 971   /* base mach is always selected */
 972   machs |= 1;
 973   /* isa unspecified means "all" */
 974   if (isas == 0)
 975     isas = (1 << MAX_ISAS) - 1;
 976   if (endian == CGEN_ENDIAN_UNKNOWN)
 977     {
 978       /* ??? If target has only one, could have a default.  */
 979       fprintf (stderr, "openrisc_cgen_cpu_open: no endianness specified\n");
 980       abort ();
 981     }
 982
 983   cd->isas = isas;
 984   cd->machs = machs;
 985   cd->endian = endian;
 986   /* FIXME: for the sparc case we can determine insn-endianness statically.
 987      The worry here is where both data and insn endian can be independently
 988      chosen, in which case this function will need another argument.
 989      Actually, will want to allow for more arguments in the future anyway.  */
 990   cd->insn_endian = endian;
 991
 992   /* Table (re)builder.  */
 993   cd->rebuild_tables = openrisc_cgen_rebuild_tables;
 994   openrisc_cgen_rebuild_tables (cd);
 995
 996   /* Default to not allowing signed overflow.  */
 997   cd->signed_overflow_ok_p = 0;
 998
 999   return (CGEN_CPU_DESC) cd;
1000 }
1001
1002 /* Cover fn to openrisc_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
1003    MACH_NAME is the bfd name of the mach.  */
1004
1005 CGEN_CPU_DESC
1006 openrisc_cgen_cpu_open_1 (mach_name, endian)
1007      const char *mach_name;
1008      enum cgen_endian endian;
1009 {
1010   return openrisc_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
1011                                CGEN_CPU_OPEN_ENDIAN, endian,
1012                                CGEN_CPU_OPEN_END);
1013 }
1014
1015 /* Close a cpu table.
1016    ??? This can live in a machine independent file, but there's currently
1017    no place to put this file (there's no libcgen).  libopcodes is the wrong
1018    place as some simulator ports use this but they don't use libopcodes.  */
1019
1020 void
1021 openrisc_cgen_cpu_close (cd)
1022      CGEN_CPU_DESC cd;
1023 {
1024   unsigned int i;
1025   const CGEN_INSN *insns;
1026
1027   if (cd->macro_insn_table.init_entries)
1028     {
1029       insns = cd->macro_insn_table.init_entries;
1030       for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
1031         {
1032           if (CGEN_INSN_RX ((insns)))
1033             regfree (CGEN_INSN_RX (insns));
1034         }
1035     }
1036
1037   if (cd->insn_table.init_entries)
1038     {
1039       insns = cd->insn_table.init_entries;
1040       for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
1041         {
1042           if (CGEN_INSN_RX (insns))
1043             regfree (CGEN_INSN_RX (insns));
1044         }
1045     }
1046
1047
1048
1049   if (cd->macro_insn_table.init_entries)
1050     free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
1051
1052   if (cd->insn_table.init_entries)
1053     free ((CGEN_INSN *) cd->insn_table.init_entries);
1054
1055   if (cd->hw_table.entries)
1056     free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
1057
1058   if (cd->operand_table.entries)
1059     free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
1060
1061   free (cd);
1062 }
1063